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2025-08-27 23:29:38 +02:00
AUTOM4.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001fcc 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000024 080020d8 080020d8 000030d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080020fc 080020fc 0000400c 2**0
CONTENTS, READONLY
4 .ARM 00000000 080020fc 080020fc 0000400c 2**0
CONTENTS, READONLY
5 .preinit_array 00000000 080020fc 080020fc 0000400c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080020fc 080020fc 000030fc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08002100 08002100 00003100 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08002104 00004000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000f8 2000000c 08002110 0000400c 2**2
ALLOC
10 ._user_heap_stack 00000604 20000104 08002110 00004104 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0
CONTENTS, READONLY
12 .debug_info 000075a6 00000000 00000000 00004035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000014a9 00000000 00000000 0000b5db 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000938 00000000 00000000 0000ca88 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 0000071f 00000000 00000000 0000d3c0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00016626 00000000 00000000 0000dadf 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00009ab4 00000000 00000000 00024105 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008422a 00000000 00000000 0002dbb9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000b1de3 2**0
CONTENTS, READONLY
20 .debug_frame 00002600 00000000 00000000 000b1e28 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000b4428 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 2000000c .word 0x2000000c
8000128: 00000000 .word 0x00000000
800012c: 080020c0 .word 0x080020c0
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000010 .word 0x20000010
8000148: 080020c0 .word 0x080020c0
0800014c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800014c: b580 push {r7, lr}
800014e: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000150: f000 fb74 bl 800083c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000154: f000 f80a bl 800016c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000158: f000 fa14 bl 8000584 <MX_GPIO_Init>
MX_TIM1_Init();
800015c: f000 f842 bl 80001e4 <MX_TIM1_Init>
MX_TIM2_Init();
8000160: f000 f904 bl 800036c <MX_TIM2_Init>
MX_TIM3_Init();
8000164: f000 f998 bl 8000498 <MX_TIM3_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000168: bf00 nop
800016a: e7fd b.n 8000168 <main+0x1c>
0800016c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800016c: b580 push {r7, lr}
800016e: b090 sub sp, #64 @ 0x40
8000170: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000172: f107 0318 add.w r3, r7, #24
8000176: 2228 movs r2, #40 @ 0x28
8000178: 2100 movs r1, #0
800017a: 4618 mov r0, r3
800017c: f001 ff73 bl 8002066 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000180: 1d3b adds r3, r7, #4
8000182: 2200 movs r2, #0
8000184: 601a str r2, [r3, #0]
8000186: 605a str r2, [r3, #4]
8000188: 609a str r2, [r3, #8]
800018a: 60da str r2, [r3, #12]
800018c: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800018e: 2302 movs r3, #2
8000190: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000192: 2301 movs r3, #1
8000194: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000196: 2310 movs r3, #16
8000198: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
800019a: 2300 movs r3, #0
800019c: 637b str r3, [r7, #52] @ 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800019e: f107 0318 add.w r3, r7, #24
80001a2: 4618 mov r0, r3
80001a4: f000 fe14 bl 8000dd0 <HAL_RCC_OscConfig>
80001a8: 4603 mov r3, r0
80001aa: 2b00 cmp r3, #0
80001ac: d001 beq.n 80001b2 <SystemClock_Config+0x46>
{
Error_Handler();
80001ae: f000 f9ff bl 80005b0 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80001b2: 230f movs r3, #15
80001b4: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
80001b6: 2300 movs r3, #0
80001b8: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80001ba: 2300 movs r3, #0
80001bc: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80001be: 2300 movs r3, #0
80001c0: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80001c2: 2300 movs r3, #0
80001c4: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80001c6: 1d3b adds r3, r7, #4
80001c8: 2100 movs r1, #0
80001ca: 4618 mov r0, r3
80001cc: f001 f882 bl 80012d4 <HAL_RCC_ClockConfig>
80001d0: 4603 mov r3, r0
80001d2: 2b00 cmp r3, #0
80001d4: d001 beq.n 80001da <SystemClock_Config+0x6e>
{
Error_Handler();
80001d6: f000 f9eb bl 80005b0 <Error_Handler>
}
}
80001da: bf00 nop
80001dc: 3740 adds r7, #64 @ 0x40
80001de: 46bd mov sp, r7
80001e0: bd80 pop {r7, pc}
...
080001e4 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
80001e4: b580 push {r7, lr}
80001e6: b096 sub sp, #88 @ 0x58
80001e8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80001ea: f107 0348 add.w r3, r7, #72 @ 0x48
80001ee: 2200 movs r2, #0
80001f0: 601a str r2, [r3, #0]
80001f2: 605a str r2, [r3, #4]
80001f4: 609a str r2, [r3, #8]
80001f6: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80001f8: f107 0340 add.w r3, r7, #64 @ 0x40
80001fc: 2200 movs r2, #0
80001fe: 601a str r2, [r3, #0]
8000200: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000202: f107 0324 add.w r3, r7, #36 @ 0x24
8000206: 2200 movs r2, #0
8000208: 601a str r2, [r3, #0]
800020a: 605a str r2, [r3, #4]
800020c: 609a str r2, [r3, #8]
800020e: 60da str r2, [r3, #12]
8000210: 611a str r2, [r3, #16]
8000212: 615a str r2, [r3, #20]
8000214: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8000216: 1d3b adds r3, r7, #4
8000218: 2220 movs r2, #32
800021a: 2100 movs r1, #0
800021c: 4618 mov r0, r3
800021e: f001 ff22 bl 8002066 <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000222: 4b50 ldr r3, [pc, #320] @ (8000364 <MX_TIM1_Init+0x180>)
8000224: 4a50 ldr r2, [pc, #320] @ (8000368 <MX_TIM1_Init+0x184>)
8000226: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
8000228: 4b4e ldr r3, [pc, #312] @ (8000364 <MX_TIM1_Init+0x180>)
800022a: 2200 movs r2, #0
800022c: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
800022e: 4b4d ldr r3, [pc, #308] @ (8000364 <MX_TIM1_Init+0x180>)
8000230: 2200 movs r2, #0
8000232: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
8000234: 4b4b ldr r3, [pc, #300] @ (8000364 <MX_TIM1_Init+0x180>)
8000236: f64f 72ff movw r2, #65535 @ 0xffff
800023a: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800023c: 4b49 ldr r3, [pc, #292] @ (8000364 <MX_TIM1_Init+0x180>)
800023e: 2200 movs r2, #0
8000240: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8000242: 4b48 ldr r3, [pc, #288] @ (8000364 <MX_TIM1_Init+0x180>)
8000244: 2200 movs r2, #0
8000246: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000248: 4b46 ldr r3, [pc, #280] @ (8000364 <MX_TIM1_Init+0x180>)
800024a: 2200 movs r2, #0
800024c: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
800024e: 4845 ldr r0, [pc, #276] @ (8000364 <MX_TIM1_Init+0x180>)
8000250: f001 f99c bl 800158c <HAL_TIM_Base_Init>
8000254: 4603 mov r3, r0
8000256: 2b00 cmp r3, #0
8000258: d001 beq.n 800025e <MX_TIM1_Init+0x7a>
{
Error_Handler();
800025a: f000 f9a9 bl 80005b0 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800025e: f44f 5380 mov.w r3, #4096 @ 0x1000
8000262: 64bb str r3, [r7, #72] @ 0x48
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8000264: f107 0348 add.w r3, r7, #72 @ 0x48
8000268: 4619 mov r1, r3
800026a: 483e ldr r0, [pc, #248] @ (8000364 <MX_TIM1_Init+0x180>)
800026c: f001 faf8 bl 8001860 <HAL_TIM_ConfigClockSource>
8000270: 4603 mov r3, r0
8000272: 2b00 cmp r3, #0
8000274: d001 beq.n 800027a <MX_TIM1_Init+0x96>
{
Error_Handler();
8000276: f000 f99b bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
800027a: 483a ldr r0, [pc, #232] @ (8000364 <MX_TIM1_Init+0x180>)
800027c: f001 f9d5 bl 800162a <HAL_TIM_PWM_Init>
8000280: 4603 mov r3, r0
8000282: 2b00 cmp r3, #0
8000284: d001 beq.n 800028a <MX_TIM1_Init+0xa6>
{
Error_Handler();
8000286: f000 f993 bl 80005b0 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800028a: 2300 movs r3, #0
800028c: 643b str r3, [r7, #64] @ 0x40
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800028e: 2300 movs r3, #0
8000290: 647b str r3, [r7, #68] @ 0x44
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000292: f107 0340 add.w r3, r7, #64 @ 0x40
8000296: 4619 mov r1, r3
8000298: 4832 ldr r0, [pc, #200] @ (8000364 <MX_TIM1_Init+0x180>)
800029a: f001 fe35 bl 8001f08 <HAL_TIMEx_MasterConfigSynchronization>
800029e: 4603 mov r3, r0
80002a0: 2b00 cmp r3, #0
80002a2: d001 beq.n 80002a8 <MX_TIM1_Init+0xc4>
{
Error_Handler();
80002a4: f000 f984 bl 80005b0 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80002a8: 2360 movs r3, #96 @ 0x60
80002aa: 627b str r3, [r7, #36] @ 0x24
sConfigOC.Pulse = 0;
80002ac: 2300 movs r3, #0
80002ae: 62bb str r3, [r7, #40] @ 0x28
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80002b0: 2300 movs r3, #0
80002b2: 62fb str r3, [r7, #44] @ 0x2c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80002b4: 2300 movs r3, #0
80002b6: 633b str r3, [r7, #48] @ 0x30
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80002b8: 2300 movs r3, #0
80002ba: 637b str r3, [r7, #52] @ 0x34
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80002bc: 2300 movs r3, #0
80002be: 63bb str r3, [r7, #56] @ 0x38
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80002c0: 2300 movs r3, #0
80002c2: 63fb str r3, [r7, #60] @ 0x3c
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80002c4: f107 0324 add.w r3, r7, #36 @ 0x24
80002c8: 2200 movs r2, #0
80002ca: 4619 mov r1, r3
80002cc: 4825 ldr r0, [pc, #148] @ (8000364 <MX_TIM1_Init+0x180>)
80002ce: f001 fa05 bl 80016dc <HAL_TIM_PWM_ConfigChannel>
80002d2: 4603 mov r3, r0
80002d4: 2b00 cmp r3, #0
80002d6: d001 beq.n 80002dc <MX_TIM1_Init+0xf8>
{
Error_Handler();
80002d8: f000 f96a bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80002dc: f107 0324 add.w r3, r7, #36 @ 0x24
80002e0: 2204 movs r2, #4
80002e2: 4619 mov r1, r3
80002e4: 481f ldr r0, [pc, #124] @ (8000364 <MX_TIM1_Init+0x180>)
80002e6: f001 f9f9 bl 80016dc <HAL_TIM_PWM_ConfigChannel>
80002ea: 4603 mov r3, r0
80002ec: 2b00 cmp r3, #0
80002ee: d001 beq.n 80002f4 <MX_TIM1_Init+0x110>
{
Error_Handler();
80002f0: f000 f95e bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80002f4: f107 0324 add.w r3, r7, #36 @ 0x24
80002f8: 2208 movs r2, #8
80002fa: 4619 mov r1, r3
80002fc: 4819 ldr r0, [pc, #100] @ (8000364 <MX_TIM1_Init+0x180>)
80002fe: f001 f9ed bl 80016dc <HAL_TIM_PWM_ConfigChannel>
8000302: 4603 mov r3, r0
8000304: 2b00 cmp r3, #0
8000306: d001 beq.n 800030c <MX_TIM1_Init+0x128>
{
Error_Handler();
8000308: f000 f952 bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
800030c: f107 0324 add.w r3, r7, #36 @ 0x24
8000310: 220c movs r2, #12
8000312: 4619 mov r1, r3
8000314: 4813 ldr r0, [pc, #76] @ (8000364 <MX_TIM1_Init+0x180>)
8000316: f001 f9e1 bl 80016dc <HAL_TIM_PWM_ConfigChannel>
800031a: 4603 mov r3, r0
800031c: 2b00 cmp r3, #0
800031e: d001 beq.n 8000324 <MX_TIM1_Init+0x140>
{
Error_Handler();
8000320: f000 f946 bl 80005b0 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
8000324: 2300 movs r3, #0
8000326: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8000328: 2300 movs r3, #0
800032a: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
800032c: 2300 movs r3, #0
800032e: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
8000330: 2300 movs r3, #0
8000332: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8000334: 2300 movs r3, #0
8000336: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000338: f44f 5300 mov.w r3, #8192 @ 0x2000
800033c: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
800033e: 2300 movs r3, #0
8000340: 623b str r3, [r7, #32]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
8000342: 1d3b adds r3, r7, #4
8000344: 4619 mov r1, r3
8000346: 4807 ldr r0, [pc, #28] @ (8000364 <MX_TIM1_Init+0x180>)
8000348: f001 fe3c bl 8001fc4 <HAL_TIMEx_ConfigBreakDeadTime>
800034c: 4603 mov r3, r0
800034e: 2b00 cmp r3, #0
8000350: d001 beq.n 8000356 <MX_TIM1_Init+0x172>
{
Error_Handler();
8000352: f000 f92d bl 80005b0 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
8000356: 4803 ldr r0, [pc, #12] @ (8000364 <MX_TIM1_Init+0x180>)
8000358: f000 f9a6 bl 80006a8 <HAL_TIM_MspPostInit>
}
800035c: bf00 nop
800035e: 3758 adds r7, #88 @ 0x58
8000360: 46bd mov sp, r7
8000362: bd80 pop {r7, pc}
8000364: 20000028 .word 0x20000028
8000368: 40012c00 .word 0x40012c00
0800036c <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
800036c: b580 push {r7, lr}
800036e: b08e sub sp, #56 @ 0x38
8000370: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000372: f107 0328 add.w r3, r7, #40 @ 0x28
8000376: 2200 movs r2, #0
8000378: 601a str r2, [r3, #0]
800037a: 605a str r2, [r3, #4]
800037c: 609a str r2, [r3, #8]
800037e: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000380: f107 0320 add.w r3, r7, #32
8000384: 2200 movs r2, #0
8000386: 601a str r2, [r3, #0]
8000388: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
800038a: 1d3b adds r3, r7, #4
800038c: 2200 movs r2, #0
800038e: 601a str r2, [r3, #0]
8000390: 605a str r2, [r3, #4]
8000392: 609a str r2, [r3, #8]
8000394: 60da str r2, [r3, #12]
8000396: 611a str r2, [r3, #16]
8000398: 615a str r2, [r3, #20]
800039a: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
800039c: 4b3d ldr r3, [pc, #244] @ (8000494 <MX_TIM2_Init+0x128>)
800039e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
80003a2: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80003a4: 4b3b ldr r3, [pc, #236] @ (8000494 <MX_TIM2_Init+0x128>)
80003a6: 2200 movs r2, #0
80003a8: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
80003aa: 4b3a ldr r3, [pc, #232] @ (8000494 <MX_TIM2_Init+0x128>)
80003ac: 2200 movs r2, #0
80003ae: 609a str r2, [r3, #8]
htim2.Init.Period = 65535;
80003b0: 4b38 ldr r3, [pc, #224] @ (8000494 <MX_TIM2_Init+0x128>)
80003b2: f64f 72ff movw r2, #65535 @ 0xffff
80003b6: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80003b8: 4b36 ldr r3, [pc, #216] @ (8000494 <MX_TIM2_Init+0x128>)
80003ba: 2200 movs r2, #0
80003bc: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80003be: 4b35 ldr r3, [pc, #212] @ (8000494 <MX_TIM2_Init+0x128>)
80003c0: 2200 movs r2, #0
80003c2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
80003c4: 4833 ldr r0, [pc, #204] @ (8000494 <MX_TIM2_Init+0x128>)
80003c6: f001 f8e1 bl 800158c <HAL_TIM_Base_Init>
80003ca: 4603 mov r3, r0
80003cc: 2b00 cmp r3, #0
80003ce: d001 beq.n 80003d4 <MX_TIM2_Init+0x68>
{
Error_Handler();
80003d0: f000 f8ee bl 80005b0 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80003d4: f44f 5380 mov.w r3, #4096 @ 0x1000
80003d8: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
80003da: f107 0328 add.w r3, r7, #40 @ 0x28
80003de: 4619 mov r1, r3
80003e0: 482c ldr r0, [pc, #176] @ (8000494 <MX_TIM2_Init+0x128>)
80003e2: f001 fa3d bl 8001860 <HAL_TIM_ConfigClockSource>
80003e6: 4603 mov r3, r0
80003e8: 2b00 cmp r3, #0
80003ea: d001 beq.n 80003f0 <MX_TIM2_Init+0x84>
{
Error_Handler();
80003ec: f000 f8e0 bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
80003f0: 4828 ldr r0, [pc, #160] @ (8000494 <MX_TIM2_Init+0x128>)
80003f2: f001 f91a bl 800162a <HAL_TIM_PWM_Init>
80003f6: 4603 mov r3, r0
80003f8: 2b00 cmp r3, #0
80003fa: d001 beq.n 8000400 <MX_TIM2_Init+0x94>
{
Error_Handler();
80003fc: f000 f8d8 bl 80005b0 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000400: 2300 movs r3, #0
8000402: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000404: 2300 movs r3, #0
8000406: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000408: f107 0320 add.w r3, r7, #32
800040c: 4619 mov r1, r3
800040e: 4821 ldr r0, [pc, #132] @ (8000494 <MX_TIM2_Init+0x128>)
8000410: f001 fd7a bl 8001f08 <HAL_TIMEx_MasterConfigSynchronization>
8000414: 4603 mov r3, r0
8000416: 2b00 cmp r3, #0
8000418: d001 beq.n 800041e <MX_TIM2_Init+0xb2>
{
Error_Handler();
800041a: f000 f8c9 bl 80005b0 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800041e: 2360 movs r3, #96 @ 0x60
8000420: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
8000422: 2300 movs r3, #0
8000424: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000426: 2300 movs r3, #0
8000428: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
800042a: 2300 movs r3, #0
800042c: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800042e: 1d3b adds r3, r7, #4
8000430: 2200 movs r2, #0
8000432: 4619 mov r1, r3
8000434: 4817 ldr r0, [pc, #92] @ (8000494 <MX_TIM2_Init+0x128>)
8000436: f001 f951 bl 80016dc <HAL_TIM_PWM_ConfigChannel>
800043a: 4603 mov r3, r0
800043c: 2b00 cmp r3, #0
800043e: d001 beq.n 8000444 <MX_TIM2_Init+0xd8>
{
Error_Handler();
8000440: f000 f8b6 bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000444: 1d3b adds r3, r7, #4
8000446: 2204 movs r2, #4
8000448: 4619 mov r1, r3
800044a: 4812 ldr r0, [pc, #72] @ (8000494 <MX_TIM2_Init+0x128>)
800044c: f001 f946 bl 80016dc <HAL_TIM_PWM_ConfigChannel>
8000450: 4603 mov r3, r0
8000452: 2b00 cmp r3, #0
8000454: d001 beq.n 800045a <MX_TIM2_Init+0xee>
{
Error_Handler();
8000456: f000 f8ab bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
800045a: 1d3b adds r3, r7, #4
800045c: 2208 movs r2, #8
800045e: 4619 mov r1, r3
8000460: 480c ldr r0, [pc, #48] @ (8000494 <MX_TIM2_Init+0x128>)
8000462: f001 f93b bl 80016dc <HAL_TIM_PWM_ConfigChannel>
8000466: 4603 mov r3, r0
8000468: 2b00 cmp r3, #0
800046a: d001 beq.n 8000470 <MX_TIM2_Init+0x104>
{
Error_Handler();
800046c: f000 f8a0 bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8000470: 1d3b adds r3, r7, #4
8000472: 220c movs r2, #12
8000474: 4619 mov r1, r3
8000476: 4807 ldr r0, [pc, #28] @ (8000494 <MX_TIM2_Init+0x128>)
8000478: f001 f930 bl 80016dc <HAL_TIM_PWM_ConfigChannel>
800047c: 4603 mov r3, r0
800047e: 2b00 cmp r3, #0
8000480: d001 beq.n 8000486 <MX_TIM2_Init+0x11a>
{
Error_Handler();
8000482: f000 f895 bl 80005b0 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8000486: 4803 ldr r0, [pc, #12] @ (8000494 <MX_TIM2_Init+0x128>)
8000488: f000 f90e bl 80006a8 <HAL_TIM_MspPostInit>
}
800048c: bf00 nop
800048e: 3738 adds r7, #56 @ 0x38
8000490: 46bd mov sp, r7
8000492: bd80 pop {r7, pc}
8000494: 20000070 .word 0x20000070
08000498 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
8000498: b580 push {r7, lr}
800049a: b08e sub sp, #56 @ 0x38
800049c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800049e: f107 0328 add.w r3, r7, #40 @ 0x28
80004a2: 2200 movs r2, #0
80004a4: 601a str r2, [r3, #0]
80004a6: 605a str r2, [r3, #4]
80004a8: 609a str r2, [r3, #8]
80004aa: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80004ac: f107 0320 add.w r3, r7, #32
80004b0: 2200 movs r2, #0
80004b2: 601a str r2, [r3, #0]
80004b4: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80004b6: 1d3b adds r3, r7, #4
80004b8: 2200 movs r2, #0
80004ba: 601a str r2, [r3, #0]
80004bc: 605a str r2, [r3, #4]
80004be: 609a str r2, [r3, #8]
80004c0: 60da str r2, [r3, #12]
80004c2: 611a str r2, [r3, #16]
80004c4: 615a str r2, [r3, #20]
80004c6: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80004c8: 4b2c ldr r3, [pc, #176] @ (800057c <MX_TIM3_Init+0xe4>)
80004ca: 4a2d ldr r2, [pc, #180] @ (8000580 <MX_TIM3_Init+0xe8>)
80004cc: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80004ce: 4b2b ldr r3, [pc, #172] @ (800057c <MX_TIM3_Init+0xe4>)
80004d0: 2200 movs r2, #0
80004d2: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80004d4: 4b29 ldr r3, [pc, #164] @ (800057c <MX_TIM3_Init+0xe4>)
80004d6: 2200 movs r2, #0
80004d8: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
80004da: 4b28 ldr r3, [pc, #160] @ (800057c <MX_TIM3_Init+0xe4>)
80004dc: f64f 72ff movw r2, #65535 @ 0xffff
80004e0: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80004e2: 4b26 ldr r3, [pc, #152] @ (800057c <MX_TIM3_Init+0xe4>)
80004e4: 2200 movs r2, #0
80004e6: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80004e8: 4b24 ldr r3, [pc, #144] @ (800057c <MX_TIM3_Init+0xe4>)
80004ea: 2200 movs r2, #0
80004ec: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
80004ee: 4823 ldr r0, [pc, #140] @ (800057c <MX_TIM3_Init+0xe4>)
80004f0: f001 f84c bl 800158c <HAL_TIM_Base_Init>
80004f4: 4603 mov r3, r0
80004f6: 2b00 cmp r3, #0
80004f8: d001 beq.n 80004fe <MX_TIM3_Init+0x66>
{
Error_Handler();
80004fa: f000 f859 bl 80005b0 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80004fe: f44f 5380 mov.w r3, #4096 @ 0x1000
8000502: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
8000504: f107 0328 add.w r3, r7, #40 @ 0x28
8000508: 4619 mov r1, r3
800050a: 481c ldr r0, [pc, #112] @ (800057c <MX_TIM3_Init+0xe4>)
800050c: f001 f9a8 bl 8001860 <HAL_TIM_ConfigClockSource>
8000510: 4603 mov r3, r0
8000512: 2b00 cmp r3, #0
8000514: d001 beq.n 800051a <MX_TIM3_Init+0x82>
{
Error_Handler();
8000516: f000 f84b bl 80005b0 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
800051a: 4818 ldr r0, [pc, #96] @ (800057c <MX_TIM3_Init+0xe4>)
800051c: f001 f885 bl 800162a <HAL_TIM_PWM_Init>
8000520: 4603 mov r3, r0
8000522: 2b00 cmp r3, #0
8000524: d001 beq.n 800052a <MX_TIM3_Init+0x92>
{
Error_Handler();
8000526: f000 f843 bl 80005b0 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800052a: 2300 movs r3, #0
800052c: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800052e: 2300 movs r3, #0
8000530: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000532: f107 0320 add.w r3, r7, #32
8000536: 4619 mov r1, r3
8000538: 4810 ldr r0, [pc, #64] @ (800057c <MX_TIM3_Init+0xe4>)
800053a: f001 fce5 bl 8001f08 <HAL_TIMEx_MasterConfigSynchronization>
800053e: 4603 mov r3, r0
8000540: 2b00 cmp r3, #0
8000542: d001 beq.n 8000548 <MX_TIM3_Init+0xb0>
{
Error_Handler();
8000544: f000 f834 bl 80005b0 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000548: 2360 movs r3, #96 @ 0x60
800054a: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
800054c: 2300 movs r3, #0
800054e: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000550: 2300 movs r3, #0
8000552: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000554: 2300 movs r3, #0
8000556: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000558: 1d3b adds r3, r7, #4
800055a: 2200 movs r2, #0
800055c: 4619 mov r1, r3
800055e: 4807 ldr r0, [pc, #28] @ (800057c <MX_TIM3_Init+0xe4>)
8000560: f001 f8bc bl 80016dc <HAL_TIM_PWM_ConfigChannel>
8000564: 4603 mov r3, r0
8000566: 2b00 cmp r3, #0
8000568: d001 beq.n 800056e <MX_TIM3_Init+0xd6>
{
Error_Handler();
800056a: f000 f821 bl 80005b0 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
800056e: 4803 ldr r0, [pc, #12] @ (800057c <MX_TIM3_Init+0xe4>)
8000570: f000 f89a bl 80006a8 <HAL_TIM_MspPostInit>
}
8000574: bf00 nop
8000576: 3738 adds r7, #56 @ 0x38
8000578: 46bd mov sp, r7
800057a: bd80 pop {r7, pc}
800057c: 200000b8 .word 0x200000b8
8000580: 40000400 .word 0x40000400
08000584 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000584: b480 push {r7}
8000586: b083 sub sp, #12
8000588: af00 add r7, sp, #0
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
800058a: 4b08 ldr r3, [pc, #32] @ (80005ac <MX_GPIO_Init+0x28>)
800058c: 699b ldr r3, [r3, #24]
800058e: 4a07 ldr r2, [pc, #28] @ (80005ac <MX_GPIO_Init+0x28>)
8000590: f043 0304 orr.w r3, r3, #4
8000594: 6193 str r3, [r2, #24]
8000596: 4b05 ldr r3, [pc, #20] @ (80005ac <MX_GPIO_Init+0x28>)
8000598: 699b ldr r3, [r3, #24]
800059a: f003 0304 and.w r3, r3, #4
800059e: 607b str r3, [r7, #4]
80005a0: 687b ldr r3, [r7, #4]
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80005a2: bf00 nop
80005a4: 370c adds r7, #12
80005a6: 46bd mov sp, r7
80005a8: bc80 pop {r7}
80005aa: 4770 bx lr
80005ac: 40021000 .word 0x40021000
080005b0 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80005b0: b480 push {r7}
80005b2: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80005b4: b672 cpsid i
}
80005b6: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80005b8: bf00 nop
80005ba: e7fd b.n 80005b8 <Error_Handler+0x8>
080005bc <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80005bc: b480 push {r7}
80005be: b085 sub sp, #20
80005c0: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
80005c2: 4b15 ldr r3, [pc, #84] @ (8000618 <HAL_MspInit+0x5c>)
80005c4: 699b ldr r3, [r3, #24]
80005c6: 4a14 ldr r2, [pc, #80] @ (8000618 <HAL_MspInit+0x5c>)
80005c8: f043 0301 orr.w r3, r3, #1
80005cc: 6193 str r3, [r2, #24]
80005ce: 4b12 ldr r3, [pc, #72] @ (8000618 <HAL_MspInit+0x5c>)
80005d0: 699b ldr r3, [r3, #24]
80005d2: f003 0301 and.w r3, r3, #1
80005d6: 60bb str r3, [r7, #8]
80005d8: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
80005da: 4b0f ldr r3, [pc, #60] @ (8000618 <HAL_MspInit+0x5c>)
80005dc: 69db ldr r3, [r3, #28]
80005de: 4a0e ldr r2, [pc, #56] @ (8000618 <HAL_MspInit+0x5c>)
80005e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80005e4: 61d3 str r3, [r2, #28]
80005e6: 4b0c ldr r3, [pc, #48] @ (8000618 <HAL_MspInit+0x5c>)
80005e8: 69db ldr r3, [r3, #28]
80005ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80005ee: 607b str r3, [r7, #4]
80005f0: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** DISABLE: JTAG-DP Disabled and SW-DP Disabled
*/
__HAL_AFIO_REMAP_SWJ_DISABLE();
80005f2: 4b0a ldr r3, [pc, #40] @ (800061c <HAL_MspInit+0x60>)
80005f4: 685b ldr r3, [r3, #4]
80005f6: 60fb str r3, [r7, #12]
80005f8: 68fb ldr r3, [r7, #12]
80005fa: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
80005fe: 60fb str r3, [r7, #12]
8000600: 68fb ldr r3, [r7, #12]
8000602: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8000606: 60fb str r3, [r7, #12]
8000608: 4a04 ldr r2, [pc, #16] @ (800061c <HAL_MspInit+0x60>)
800060a: 68fb ldr r3, [r7, #12]
800060c: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800060e: bf00 nop
8000610: 3714 adds r7, #20
8000612: 46bd mov sp, r7
8000614: bc80 pop {r7}
8000616: 4770 bx lr
8000618: 40021000 .word 0x40021000
800061c: 40010000 .word 0x40010000
08000620 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000620: b480 push {r7}
8000622: b087 sub sp, #28
8000624: af00 add r7, sp, #0
8000626: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000628: 687b ldr r3, [r7, #4]
800062a: 681b ldr r3, [r3, #0]
800062c: 4a1b ldr r2, [pc, #108] @ (800069c <HAL_TIM_Base_MspInit+0x7c>)
800062e: 4293 cmp r3, r2
8000630: d10c bne.n 800064c <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8000632: 4b1b ldr r3, [pc, #108] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000634: 699b ldr r3, [r3, #24]
8000636: 4a1a ldr r2, [pc, #104] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000638: f443 6300 orr.w r3, r3, #2048 @ 0x800
800063c: 6193 str r3, [r2, #24]
800063e: 4b18 ldr r3, [pc, #96] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000640: 699b ldr r3, [r3, #24]
8000642: f403 6300 and.w r3, r3, #2048 @ 0x800
8000646: 617b str r3, [r7, #20]
8000648: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
800064a: e022 b.n 8000692 <HAL_TIM_Base_MspInit+0x72>
else if(htim_base->Instance==TIM2)
800064c: 687b ldr r3, [r7, #4]
800064e: 681b ldr r3, [r3, #0]
8000650: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000654: d10c bne.n 8000670 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM2_CLK_ENABLE();
8000656: 4b12 ldr r3, [pc, #72] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000658: 69db ldr r3, [r3, #28]
800065a: 4a11 ldr r2, [pc, #68] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
800065c: f043 0301 orr.w r3, r3, #1
8000660: 61d3 str r3, [r2, #28]
8000662: 4b0f ldr r3, [pc, #60] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000664: 69db ldr r3, [r3, #28]
8000666: f003 0301 and.w r3, r3, #1
800066a: 613b str r3, [r7, #16]
800066c: 693b ldr r3, [r7, #16]
}
800066e: e010 b.n 8000692 <HAL_TIM_Base_MspInit+0x72>
else if(htim_base->Instance==TIM3)
8000670: 687b ldr r3, [r7, #4]
8000672: 681b ldr r3, [r3, #0]
8000674: 4a0b ldr r2, [pc, #44] @ (80006a4 <HAL_TIM_Base_MspInit+0x84>)
8000676: 4293 cmp r3, r2
8000678: d10b bne.n 8000692 <HAL_TIM_Base_MspInit+0x72>
__HAL_RCC_TIM3_CLK_ENABLE();
800067a: 4b09 ldr r3, [pc, #36] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
800067c: 69db ldr r3, [r3, #28]
800067e: 4a08 ldr r2, [pc, #32] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000680: f043 0302 orr.w r3, r3, #2
8000684: 61d3 str r3, [r2, #28]
8000686: 4b06 ldr r3, [pc, #24] @ (80006a0 <HAL_TIM_Base_MspInit+0x80>)
8000688: 69db ldr r3, [r3, #28]
800068a: f003 0302 and.w r3, r3, #2
800068e: 60fb str r3, [r7, #12]
8000690: 68fb ldr r3, [r7, #12]
}
8000692: bf00 nop
8000694: 371c adds r7, #28
8000696: 46bd mov sp, r7
8000698: bc80 pop {r7}
800069a: 4770 bx lr
800069c: 40012c00 .word 0x40012c00
80006a0: 40021000 .word 0x40021000
80006a4: 40000400 .word 0x40000400
080006a8 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
80006a8: b580 push {r7, lr}
80006aa: b08a sub sp, #40 @ 0x28
80006ac: af00 add r7, sp, #0
80006ae: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006b0: f107 0318 add.w r3, r7, #24
80006b4: 2200 movs r2, #0
80006b6: 601a str r2, [r3, #0]
80006b8: 605a str r2, [r3, #4]
80006ba: 609a str r2, [r3, #8]
80006bc: 60da str r2, [r3, #12]
if(htim->Instance==TIM1)
80006be: 687b ldr r3, [r7, #4]
80006c0: 681b ldr r3, [r3, #0]
80006c2: 4a2e ldr r2, [pc, #184] @ (800077c <HAL_TIM_MspPostInit+0xd4>)
80006c4: 4293 cmp r3, r2
80006c6: d119 bne.n 80006fc <HAL_TIM_MspPostInit+0x54>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
80006c8: 4b2d ldr r3, [pc, #180] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
80006ca: 699b ldr r3, [r3, #24]
80006cc: 4a2c ldr r2, [pc, #176] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
80006ce: f043 0304 orr.w r3, r3, #4
80006d2: 6193 str r3, [r2, #24]
80006d4: 4b2a ldr r3, [pc, #168] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
80006d6: 699b ldr r3, [r3, #24]
80006d8: f003 0304 and.w r3, r3, #4
80006dc: 617b str r3, [r7, #20]
80006de: 697b ldr r3, [r7, #20]
PA8 ------> TIM1_CH1
PA9 ------> TIM1_CH2
PA10 ------> TIM1_CH3
PA11 ------> TIM1_CH4
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11;
80006e0: f44f 6370 mov.w r3, #3840 @ 0xf00
80006e4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80006e6: 2302 movs r3, #2
80006e8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80006ea: 2302 movs r3, #2
80006ec: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80006ee: f107 0318 add.w r3, r7, #24
80006f2: 4619 mov r1, r3
80006f4: 4823 ldr r0, [pc, #140] @ (8000784 <HAL_TIM_MspPostInit+0xdc>)
80006f6: f000 f9e7 bl 8000ac8 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
80006fa: e03a b.n 8000772 <HAL_TIM_MspPostInit+0xca>
else if(htim->Instance==TIM2)
80006fc: 687b ldr r3, [r7, #4]
80006fe: 681b ldr r3, [r3, #0]
8000700: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000704: d118 bne.n 8000738 <HAL_TIM_MspPostInit+0x90>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000706: 4b1e ldr r3, [pc, #120] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
8000708: 699b ldr r3, [r3, #24]
800070a: 4a1d ldr r2, [pc, #116] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
800070c: f043 0304 orr.w r3, r3, #4
8000710: 6193 str r3, [r2, #24]
8000712: 4b1b ldr r3, [pc, #108] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
8000714: 699b ldr r3, [r3, #24]
8000716: f003 0304 and.w r3, r3, #4
800071a: 613b str r3, [r7, #16]
800071c: 693b ldr r3, [r7, #16]
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
800071e: 230f movs r3, #15
8000720: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000722: 2302 movs r3, #2
8000724: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000726: 2302 movs r3, #2
8000728: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800072a: f107 0318 add.w r3, r7, #24
800072e: 4619 mov r1, r3
8000730: 4814 ldr r0, [pc, #80] @ (8000784 <HAL_TIM_MspPostInit+0xdc>)
8000732: f000 f9c9 bl 8000ac8 <HAL_GPIO_Init>
}
8000736: e01c b.n 8000772 <HAL_TIM_MspPostInit+0xca>
else if(htim->Instance==TIM3)
8000738: 687b ldr r3, [r7, #4]
800073a: 681b ldr r3, [r3, #0]
800073c: 4a12 ldr r2, [pc, #72] @ (8000788 <HAL_TIM_MspPostInit+0xe0>)
800073e: 4293 cmp r3, r2
8000740: d117 bne.n 8000772 <HAL_TIM_MspPostInit+0xca>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000742: 4b0f ldr r3, [pc, #60] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
8000744: 699b ldr r3, [r3, #24]
8000746: 4a0e ldr r2, [pc, #56] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
8000748: f043 0304 orr.w r3, r3, #4
800074c: 6193 str r3, [r2, #24]
800074e: 4b0c ldr r3, [pc, #48] @ (8000780 <HAL_TIM_MspPostInit+0xd8>)
8000750: 699b ldr r3, [r3, #24]
8000752: f003 0304 and.w r3, r3, #4
8000756: 60fb str r3, [r7, #12]
8000758: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_6;
800075a: 2340 movs r3, #64 @ 0x40
800075c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800075e: 2302 movs r3, #2
8000760: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000762: 2302 movs r3, #2
8000764: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000766: f107 0318 add.w r3, r7, #24
800076a: 4619 mov r1, r3
800076c: 4805 ldr r0, [pc, #20] @ (8000784 <HAL_TIM_MspPostInit+0xdc>)
800076e: f000 f9ab bl 8000ac8 <HAL_GPIO_Init>
}
8000772: bf00 nop
8000774: 3728 adds r7, #40 @ 0x28
8000776: 46bd mov sp, r7
8000778: bd80 pop {r7, pc}
800077a: bf00 nop
800077c: 40012c00 .word 0x40012c00
8000780: 40021000 .word 0x40021000
8000784: 40010800 .word 0x40010800
8000788: 40000400 .word 0x40000400
0800078c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800078c: b480 push {r7}
800078e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000790: bf00 nop
8000792: e7fd b.n 8000790 <NMI_Handler+0x4>
08000794 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000794: b480 push {r7}
8000796: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000798: bf00 nop
800079a: e7fd b.n 8000798 <HardFault_Handler+0x4>
0800079c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
800079c: b480 push {r7}
800079e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80007a0: bf00 nop
80007a2: e7fd b.n 80007a0 <MemManage_Handler+0x4>
080007a4 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80007a4: b480 push {r7}
80007a6: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80007a8: bf00 nop
80007aa: e7fd b.n 80007a8 <BusFault_Handler+0x4>
080007ac <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80007ac: b480 push {r7}
80007ae: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80007b0: bf00 nop
80007b2: e7fd b.n 80007b0 <UsageFault_Handler+0x4>
080007b4 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80007b4: b480 push {r7}
80007b6: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80007b8: bf00 nop
80007ba: 46bd mov sp, r7
80007bc: bc80 pop {r7}
80007be: 4770 bx lr
080007c0 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80007c0: b480 push {r7}
80007c2: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80007c4: bf00 nop
80007c6: 46bd mov sp, r7
80007c8: bc80 pop {r7}
80007ca: 4770 bx lr
080007cc <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80007cc: b480 push {r7}
80007ce: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80007d0: bf00 nop
80007d2: 46bd mov sp, r7
80007d4: bc80 pop {r7}
80007d6: 4770 bx lr
080007d8 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80007d8: b580 push {r7, lr}
80007da: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80007dc: f000 f874 bl 80008c8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80007e0: bf00 nop
80007e2: bd80 pop {r7, pc}
080007e4 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80007e4: b480 push {r7}
80007e6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80007e8: bf00 nop
80007ea: 46bd mov sp, r7
80007ec: bc80 pop {r7}
80007ee: 4770 bx lr
080007f0 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80007f0: f7ff fff8 bl 80007e4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80007f4: 480b ldr r0, [pc, #44] @ (8000824 <LoopFillZerobss+0xe>)
ldr r1, =_edata
80007f6: 490c ldr r1, [pc, #48] @ (8000828 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
80007f8: 4a0c ldr r2, [pc, #48] @ (800082c <LoopFillZerobss+0x16>)
movs r3, #0
80007fa: 2300 movs r3, #0
b LoopCopyDataInit
80007fc: e002 b.n 8000804 <LoopCopyDataInit>
080007fe <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80007fe: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000800: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000802: 3304 adds r3, #4
08000804 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000804: 18c4 adds r4, r0, r3
cmp r4, r1
8000806: 428c cmp r4, r1
bcc CopyDataInit
8000808: d3f9 bcc.n 80007fe <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800080a: 4a09 ldr r2, [pc, #36] @ (8000830 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
800080c: 4c09 ldr r4, [pc, #36] @ (8000834 <LoopFillZerobss+0x1e>)
movs r3, #0
800080e: 2300 movs r3, #0
b LoopFillZerobss
8000810: e001 b.n 8000816 <LoopFillZerobss>
08000812 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000812: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000814: 3204 adds r2, #4
08000816 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000816: 42a2 cmp r2, r4
bcc FillZerobss
8000818: d3fb bcc.n 8000812 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800081a: f001 fc2d bl 8002078 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800081e: f7ff fc95 bl 800014c <main>
bx lr
8000822: 4770 bx lr
ldr r0, =_sdata
8000824: 20000000 .word 0x20000000
ldr r1, =_edata
8000828: 2000000c .word 0x2000000c
ldr r2, =_sidata
800082c: 08002104 .word 0x08002104
ldr r2, =_sbss
8000830: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000834: 20000104 .word 0x20000104
08000838 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000838: e7fe b.n 8000838 <ADC1_2_IRQHandler>
...
0800083c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800083c: b580 push {r7, lr}
800083e: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000840: 4b08 ldr r3, [pc, #32] @ (8000864 <HAL_Init+0x28>)
8000842: 681b ldr r3, [r3, #0]
8000844: 4a07 ldr r2, [pc, #28] @ (8000864 <HAL_Init+0x28>)
8000846: f043 0310 orr.w r3, r3, #16
800084a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800084c: 2003 movs r0, #3
800084e: f000 f907 bl 8000a60 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000852: 200f movs r0, #15
8000854: f000 f808 bl 8000868 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000858: f7ff feb0 bl 80005bc <HAL_MspInit>
/* Return function status */
return HAL_OK;
800085c: 2300 movs r3, #0
}
800085e: 4618 mov r0, r3
8000860: bd80 pop {r7, pc}
8000862: bf00 nop
8000864: 40022000 .word 0x40022000
08000868 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000868: b580 push {r7, lr}
800086a: b082 sub sp, #8
800086c: af00 add r7, sp, #0
800086e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000870: 4b12 ldr r3, [pc, #72] @ (80008bc <HAL_InitTick+0x54>)
8000872: 681a ldr r2, [r3, #0]
8000874: 4b12 ldr r3, [pc, #72] @ (80008c0 <HAL_InitTick+0x58>)
8000876: 781b ldrb r3, [r3, #0]
8000878: 4619 mov r1, r3
800087a: f44f 737a mov.w r3, #1000 @ 0x3e8
800087e: fbb3 f3f1 udiv r3, r3, r1
8000882: fbb2 f3f3 udiv r3, r2, r3
8000886: 4618 mov r0, r3
8000888: f000 f911 bl 8000aae <HAL_SYSTICK_Config>
800088c: 4603 mov r3, r0
800088e: 2b00 cmp r3, #0
8000890: d001 beq.n 8000896 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000892: 2301 movs r3, #1
8000894: e00e b.n 80008b4 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000896: 687b ldr r3, [r7, #4]
8000898: 2b0f cmp r3, #15
800089a: d80a bhi.n 80008b2 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800089c: 2200 movs r2, #0
800089e: 6879 ldr r1, [r7, #4]
80008a0: f04f 30ff mov.w r0, #4294967295
80008a4: f000 f8e7 bl 8000a76 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80008a8: 4a06 ldr r2, [pc, #24] @ (80008c4 <HAL_InitTick+0x5c>)
80008aa: 687b ldr r3, [r7, #4]
80008ac: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80008ae: 2300 movs r3, #0
80008b0: e000 b.n 80008b4 <HAL_InitTick+0x4c>
return HAL_ERROR;
80008b2: 2301 movs r3, #1
}
80008b4: 4618 mov r0, r3
80008b6: 3708 adds r7, #8
80008b8: 46bd mov sp, r7
80008ba: bd80 pop {r7, pc}
80008bc: 20000000 .word 0x20000000
80008c0: 20000008 .word 0x20000008
80008c4: 20000004 .word 0x20000004
080008c8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80008c8: b480 push {r7}
80008ca: af00 add r7, sp, #0
uwTick += uwTickFreq;
80008cc: 4b05 ldr r3, [pc, #20] @ (80008e4 <HAL_IncTick+0x1c>)
80008ce: 781b ldrb r3, [r3, #0]
80008d0: 461a mov r2, r3
80008d2: 4b05 ldr r3, [pc, #20] @ (80008e8 <HAL_IncTick+0x20>)
80008d4: 681b ldr r3, [r3, #0]
80008d6: 4413 add r3, r2
80008d8: 4a03 ldr r2, [pc, #12] @ (80008e8 <HAL_IncTick+0x20>)
80008da: 6013 str r3, [r2, #0]
}
80008dc: bf00 nop
80008de: 46bd mov sp, r7
80008e0: bc80 pop {r7}
80008e2: 4770 bx lr
80008e4: 20000008 .word 0x20000008
80008e8: 20000100 .word 0x20000100
080008ec <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80008ec: b480 push {r7}
80008ee: af00 add r7, sp, #0
return uwTick;
80008f0: 4b02 ldr r3, [pc, #8] @ (80008fc <HAL_GetTick+0x10>)
80008f2: 681b ldr r3, [r3, #0]
}
80008f4: 4618 mov r0, r3
80008f6: 46bd mov sp, r7
80008f8: bc80 pop {r7}
80008fa: 4770 bx lr
80008fc: 20000100 .word 0x20000100
08000900 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000900: b480 push {r7}
8000902: b085 sub sp, #20
8000904: af00 add r7, sp, #0
8000906: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000908: 687b ldr r3, [r7, #4]
800090a: f003 0307 and.w r3, r3, #7
800090e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000910: 4b0c ldr r3, [pc, #48] @ (8000944 <__NVIC_SetPriorityGrouping+0x44>)
8000912: 68db ldr r3, [r3, #12]
8000914: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000916: 68ba ldr r2, [r7, #8]
8000918: f64f 03ff movw r3, #63743 @ 0xf8ff
800091c: 4013 ands r3, r2
800091e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000920: 68fb ldr r3, [r7, #12]
8000922: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000924: 68bb ldr r3, [r7, #8]
8000926: 4313 orrs r3, r2
reg_value = (reg_value |
8000928: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
800092c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000930: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000932: 4a04 ldr r2, [pc, #16] @ (8000944 <__NVIC_SetPriorityGrouping+0x44>)
8000934: 68bb ldr r3, [r7, #8]
8000936: 60d3 str r3, [r2, #12]
}
8000938: bf00 nop
800093a: 3714 adds r7, #20
800093c: 46bd mov sp, r7
800093e: bc80 pop {r7}
8000940: 4770 bx lr
8000942: bf00 nop
8000944: e000ed00 .word 0xe000ed00
08000948 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000948: b480 push {r7}
800094a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
800094c: 4b04 ldr r3, [pc, #16] @ (8000960 <__NVIC_GetPriorityGrouping+0x18>)
800094e: 68db ldr r3, [r3, #12]
8000950: 0a1b lsrs r3, r3, #8
8000952: f003 0307 and.w r3, r3, #7
}
8000956: 4618 mov r0, r3
8000958: 46bd mov sp, r7
800095a: bc80 pop {r7}
800095c: 4770 bx lr
800095e: bf00 nop
8000960: e000ed00 .word 0xe000ed00
08000964 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000964: b480 push {r7}
8000966: b083 sub sp, #12
8000968: af00 add r7, sp, #0
800096a: 4603 mov r3, r0
800096c: 6039 str r1, [r7, #0]
800096e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000970: f997 3007 ldrsb.w r3, [r7, #7]
8000974: 2b00 cmp r3, #0
8000976: db0a blt.n 800098e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000978: 683b ldr r3, [r7, #0]
800097a: b2da uxtb r2, r3
800097c: 490c ldr r1, [pc, #48] @ (80009b0 <__NVIC_SetPriority+0x4c>)
800097e: f997 3007 ldrsb.w r3, [r7, #7]
8000982: 0112 lsls r2, r2, #4
8000984: b2d2 uxtb r2, r2
8000986: 440b add r3, r1
8000988: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
800098c: e00a b.n 80009a4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800098e: 683b ldr r3, [r7, #0]
8000990: b2da uxtb r2, r3
8000992: 4908 ldr r1, [pc, #32] @ (80009b4 <__NVIC_SetPriority+0x50>)
8000994: 79fb ldrb r3, [r7, #7]
8000996: f003 030f and.w r3, r3, #15
800099a: 3b04 subs r3, #4
800099c: 0112 lsls r2, r2, #4
800099e: b2d2 uxtb r2, r2
80009a0: 440b add r3, r1
80009a2: 761a strb r2, [r3, #24]
}
80009a4: bf00 nop
80009a6: 370c adds r7, #12
80009a8: 46bd mov sp, r7
80009aa: bc80 pop {r7}
80009ac: 4770 bx lr
80009ae: bf00 nop
80009b0: e000e100 .word 0xe000e100
80009b4: e000ed00 .word 0xe000ed00
080009b8 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80009b8: b480 push {r7}
80009ba: b089 sub sp, #36 @ 0x24
80009bc: af00 add r7, sp, #0
80009be: 60f8 str r0, [r7, #12]
80009c0: 60b9 str r1, [r7, #8]
80009c2: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80009c4: 68fb ldr r3, [r7, #12]
80009c6: f003 0307 and.w r3, r3, #7
80009ca: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80009cc: 69fb ldr r3, [r7, #28]
80009ce: f1c3 0307 rsb r3, r3, #7
80009d2: 2b04 cmp r3, #4
80009d4: bf28 it cs
80009d6: 2304 movcs r3, #4
80009d8: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80009da: 69fb ldr r3, [r7, #28]
80009dc: 3304 adds r3, #4
80009de: 2b06 cmp r3, #6
80009e0: d902 bls.n 80009e8 <NVIC_EncodePriority+0x30>
80009e2: 69fb ldr r3, [r7, #28]
80009e4: 3b03 subs r3, #3
80009e6: e000 b.n 80009ea <NVIC_EncodePriority+0x32>
80009e8: 2300 movs r3, #0
80009ea: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80009ec: f04f 32ff mov.w r2, #4294967295
80009f0: 69bb ldr r3, [r7, #24]
80009f2: fa02 f303 lsl.w r3, r2, r3
80009f6: 43da mvns r2, r3
80009f8: 68bb ldr r3, [r7, #8]
80009fa: 401a ands r2, r3
80009fc: 697b ldr r3, [r7, #20]
80009fe: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000a00: f04f 31ff mov.w r1, #4294967295
8000a04: 697b ldr r3, [r7, #20]
8000a06: fa01 f303 lsl.w r3, r1, r3
8000a0a: 43d9 mvns r1, r3
8000a0c: 687b ldr r3, [r7, #4]
8000a0e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000a10: 4313 orrs r3, r2
);
}
8000a12: 4618 mov r0, r3
8000a14: 3724 adds r7, #36 @ 0x24
8000a16: 46bd mov sp, r7
8000a18: bc80 pop {r7}
8000a1a: 4770 bx lr
08000a1c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000a1c: b580 push {r7, lr}
8000a1e: b082 sub sp, #8
8000a20: af00 add r7, sp, #0
8000a22: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000a24: 687b ldr r3, [r7, #4]
8000a26: 3b01 subs r3, #1
8000a28: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8000a2c: d301 bcc.n 8000a32 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000a2e: 2301 movs r3, #1
8000a30: e00f b.n 8000a52 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000a32: 4a0a ldr r2, [pc, #40] @ (8000a5c <SysTick_Config+0x40>)
8000a34: 687b ldr r3, [r7, #4]
8000a36: 3b01 subs r3, #1
8000a38: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000a3a: 210f movs r1, #15
8000a3c: f04f 30ff mov.w r0, #4294967295
8000a40: f7ff ff90 bl 8000964 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000a44: 4b05 ldr r3, [pc, #20] @ (8000a5c <SysTick_Config+0x40>)
8000a46: 2200 movs r2, #0
8000a48: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000a4a: 4b04 ldr r3, [pc, #16] @ (8000a5c <SysTick_Config+0x40>)
8000a4c: 2207 movs r2, #7
8000a4e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000a50: 2300 movs r3, #0
}
8000a52: 4618 mov r0, r3
8000a54: 3708 adds r7, #8
8000a56: 46bd mov sp, r7
8000a58: bd80 pop {r7, pc}
8000a5a: bf00 nop
8000a5c: e000e010 .word 0xe000e010
08000a60 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000a60: b580 push {r7, lr}
8000a62: b082 sub sp, #8
8000a64: af00 add r7, sp, #0
8000a66: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000a68: 6878 ldr r0, [r7, #4]
8000a6a: f7ff ff49 bl 8000900 <__NVIC_SetPriorityGrouping>
}
8000a6e: bf00 nop
8000a70: 3708 adds r7, #8
8000a72: 46bd mov sp, r7
8000a74: bd80 pop {r7, pc}
08000a76 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000a76: b580 push {r7, lr}
8000a78: b086 sub sp, #24
8000a7a: af00 add r7, sp, #0
8000a7c: 4603 mov r3, r0
8000a7e: 60b9 str r1, [r7, #8]
8000a80: 607a str r2, [r7, #4]
8000a82: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000a84: 2300 movs r3, #0
8000a86: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000a88: f7ff ff5e bl 8000948 <__NVIC_GetPriorityGrouping>
8000a8c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000a8e: 687a ldr r2, [r7, #4]
8000a90: 68b9 ldr r1, [r7, #8]
8000a92: 6978 ldr r0, [r7, #20]
8000a94: f7ff ff90 bl 80009b8 <NVIC_EncodePriority>
8000a98: 4602 mov r2, r0
8000a9a: f997 300f ldrsb.w r3, [r7, #15]
8000a9e: 4611 mov r1, r2
8000aa0: 4618 mov r0, r3
8000aa2: f7ff ff5f bl 8000964 <__NVIC_SetPriority>
}
8000aa6: bf00 nop
8000aa8: 3718 adds r7, #24
8000aaa: 46bd mov sp, r7
8000aac: bd80 pop {r7, pc}
08000aae <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000aae: b580 push {r7, lr}
8000ab0: b082 sub sp, #8
8000ab2: af00 add r7, sp, #0
8000ab4: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000ab6: 6878 ldr r0, [r7, #4]
8000ab8: f7ff ffb0 bl 8000a1c <SysTick_Config>
8000abc: 4603 mov r3, r0
}
8000abe: 4618 mov r0, r3
8000ac0: 3708 adds r7, #8
8000ac2: 46bd mov sp, r7
8000ac4: bd80 pop {r7, pc}
...
08000ac8 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000ac8: b480 push {r7}
8000aca: b08b sub sp, #44 @ 0x2c
8000acc: af00 add r7, sp, #0
8000ace: 6078 str r0, [r7, #4]
8000ad0: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000ad2: 2300 movs r3, #0
8000ad4: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8000ad6: 2300 movs r3, #0
8000ad8: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000ada: e169 b.n 8000db0 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8000adc: 2201 movs r2, #1
8000ade: 6a7b ldr r3, [r7, #36] @ 0x24
8000ae0: fa02 f303 lsl.w r3, r2, r3
8000ae4: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000ae6: 683b ldr r3, [r7, #0]
8000ae8: 681b ldr r3, [r3, #0]
8000aea: 69fa ldr r2, [r7, #28]
8000aec: 4013 ands r3, r2
8000aee: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8000af0: 69ba ldr r2, [r7, #24]
8000af2: 69fb ldr r3, [r7, #28]
8000af4: 429a cmp r2, r3
8000af6: f040 8158 bne.w 8000daa <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
8000afa: 683b ldr r3, [r7, #0]
8000afc: 685b ldr r3, [r3, #4]
8000afe: 4a9a ldr r2, [pc, #616] @ (8000d68 <HAL_GPIO_Init+0x2a0>)
8000b00: 4293 cmp r3, r2
8000b02: d05e beq.n 8000bc2 <HAL_GPIO_Init+0xfa>
8000b04: 4a98 ldr r2, [pc, #608] @ (8000d68 <HAL_GPIO_Init+0x2a0>)
8000b06: 4293 cmp r3, r2
8000b08: d875 bhi.n 8000bf6 <HAL_GPIO_Init+0x12e>
8000b0a: 4a98 ldr r2, [pc, #608] @ (8000d6c <HAL_GPIO_Init+0x2a4>)
8000b0c: 4293 cmp r3, r2
8000b0e: d058 beq.n 8000bc2 <HAL_GPIO_Init+0xfa>
8000b10: 4a96 ldr r2, [pc, #600] @ (8000d6c <HAL_GPIO_Init+0x2a4>)
8000b12: 4293 cmp r3, r2
8000b14: d86f bhi.n 8000bf6 <HAL_GPIO_Init+0x12e>
8000b16: 4a96 ldr r2, [pc, #600] @ (8000d70 <HAL_GPIO_Init+0x2a8>)
8000b18: 4293 cmp r3, r2
8000b1a: d052 beq.n 8000bc2 <HAL_GPIO_Init+0xfa>
8000b1c: 4a94 ldr r2, [pc, #592] @ (8000d70 <HAL_GPIO_Init+0x2a8>)
8000b1e: 4293 cmp r3, r2
8000b20: d869 bhi.n 8000bf6 <HAL_GPIO_Init+0x12e>
8000b22: 4a94 ldr r2, [pc, #592] @ (8000d74 <HAL_GPIO_Init+0x2ac>)
8000b24: 4293 cmp r3, r2
8000b26: d04c beq.n 8000bc2 <HAL_GPIO_Init+0xfa>
8000b28: 4a92 ldr r2, [pc, #584] @ (8000d74 <HAL_GPIO_Init+0x2ac>)
8000b2a: 4293 cmp r3, r2
8000b2c: d863 bhi.n 8000bf6 <HAL_GPIO_Init+0x12e>
8000b2e: 4a92 ldr r2, [pc, #584] @ (8000d78 <HAL_GPIO_Init+0x2b0>)
8000b30: 4293 cmp r3, r2
8000b32: d046 beq.n 8000bc2 <HAL_GPIO_Init+0xfa>
8000b34: 4a90 ldr r2, [pc, #576] @ (8000d78 <HAL_GPIO_Init+0x2b0>)
8000b36: 4293 cmp r3, r2
8000b38: d85d bhi.n 8000bf6 <HAL_GPIO_Init+0x12e>
8000b3a: 2b12 cmp r3, #18
8000b3c: d82a bhi.n 8000b94 <HAL_GPIO_Init+0xcc>
8000b3e: 2b12 cmp r3, #18
8000b40: d859 bhi.n 8000bf6 <HAL_GPIO_Init+0x12e>
8000b42: a201 add r2, pc, #4 @ (adr r2, 8000b48 <HAL_GPIO_Init+0x80>)
8000b44: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000b48: 08000bc3 .word 0x08000bc3
8000b4c: 08000b9d .word 0x08000b9d
8000b50: 08000baf .word 0x08000baf
8000b54: 08000bf1 .word 0x08000bf1
8000b58: 08000bf7 .word 0x08000bf7
8000b5c: 08000bf7 .word 0x08000bf7
8000b60: 08000bf7 .word 0x08000bf7
8000b64: 08000bf7 .word 0x08000bf7
8000b68: 08000bf7 .word 0x08000bf7
8000b6c: 08000bf7 .word 0x08000bf7
8000b70: 08000bf7 .word 0x08000bf7
8000b74: 08000bf7 .word 0x08000bf7
8000b78: 08000bf7 .word 0x08000bf7
8000b7c: 08000bf7 .word 0x08000bf7
8000b80: 08000bf7 .word 0x08000bf7
8000b84: 08000bf7 .word 0x08000bf7
8000b88: 08000bf7 .word 0x08000bf7
8000b8c: 08000ba5 .word 0x08000ba5
8000b90: 08000bb9 .word 0x08000bb9
8000b94: 4a79 ldr r2, [pc, #484] @ (8000d7c <HAL_GPIO_Init+0x2b4>)
8000b96: 4293 cmp r3, r2
8000b98: d013 beq.n 8000bc2 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8000b9a: e02c b.n 8000bf6 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8000b9c: 683b ldr r3, [r7, #0]
8000b9e: 68db ldr r3, [r3, #12]
8000ba0: 623b str r3, [r7, #32]
break;
8000ba2: e029 b.n 8000bf8 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8000ba4: 683b ldr r3, [r7, #0]
8000ba6: 68db ldr r3, [r3, #12]
8000ba8: 3304 adds r3, #4
8000baa: 623b str r3, [r7, #32]
break;
8000bac: e024 b.n 8000bf8 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8000bae: 683b ldr r3, [r7, #0]
8000bb0: 68db ldr r3, [r3, #12]
8000bb2: 3308 adds r3, #8
8000bb4: 623b str r3, [r7, #32]
break;
8000bb6: e01f b.n 8000bf8 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8000bb8: 683b ldr r3, [r7, #0]
8000bba: 68db ldr r3, [r3, #12]
8000bbc: 330c adds r3, #12
8000bbe: 623b str r3, [r7, #32]
break;
8000bc0: e01a b.n 8000bf8 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8000bc2: 683b ldr r3, [r7, #0]
8000bc4: 689b ldr r3, [r3, #8]
8000bc6: 2b00 cmp r3, #0
8000bc8: d102 bne.n 8000bd0 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8000bca: 2304 movs r3, #4
8000bcc: 623b str r3, [r7, #32]
break;
8000bce: e013 b.n 8000bf8 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8000bd0: 683b ldr r3, [r7, #0]
8000bd2: 689b ldr r3, [r3, #8]
8000bd4: 2b01 cmp r3, #1
8000bd6: d105 bne.n 8000be4 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000bd8: 2308 movs r3, #8
8000bda: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8000bdc: 687b ldr r3, [r7, #4]
8000bde: 69fa ldr r2, [r7, #28]
8000be0: 611a str r2, [r3, #16]
break;
8000be2: e009 b.n 8000bf8 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000be4: 2308 movs r3, #8
8000be6: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8000be8: 687b ldr r3, [r7, #4]
8000bea: 69fa ldr r2, [r7, #28]
8000bec: 615a str r2, [r3, #20]
break;
8000bee: e003 b.n 8000bf8 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8000bf0: 2300 movs r3, #0
8000bf2: 623b str r3, [r7, #32]
break;
8000bf4: e000 b.n 8000bf8 <HAL_GPIO_Init+0x130>
break;
8000bf6: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8000bf8: 69bb ldr r3, [r7, #24]
8000bfa: 2bff cmp r3, #255 @ 0xff
8000bfc: d801 bhi.n 8000c02 <HAL_GPIO_Init+0x13a>
8000bfe: 687b ldr r3, [r7, #4]
8000c00: e001 b.n 8000c06 <HAL_GPIO_Init+0x13e>
8000c02: 687b ldr r3, [r7, #4]
8000c04: 3304 adds r3, #4
8000c06: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8000c08: 69bb ldr r3, [r7, #24]
8000c0a: 2bff cmp r3, #255 @ 0xff
8000c0c: d802 bhi.n 8000c14 <HAL_GPIO_Init+0x14c>
8000c0e: 6a7b ldr r3, [r7, #36] @ 0x24
8000c10: 009b lsls r3, r3, #2
8000c12: e002 b.n 8000c1a <HAL_GPIO_Init+0x152>
8000c14: 6a7b ldr r3, [r7, #36] @ 0x24
8000c16: 3b08 subs r3, #8
8000c18: 009b lsls r3, r3, #2
8000c1a: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8000c1c: 697b ldr r3, [r7, #20]
8000c1e: 681a ldr r2, [r3, #0]
8000c20: 210f movs r1, #15
8000c22: 693b ldr r3, [r7, #16]
8000c24: fa01 f303 lsl.w r3, r1, r3
8000c28: 43db mvns r3, r3
8000c2a: 401a ands r2, r3
8000c2c: 6a39 ldr r1, [r7, #32]
8000c2e: 693b ldr r3, [r7, #16]
8000c30: fa01 f303 lsl.w r3, r1, r3
8000c34: 431a orrs r2, r3
8000c36: 697b ldr r3, [r7, #20]
8000c38: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8000c3a: 683b ldr r3, [r7, #0]
8000c3c: 685b ldr r3, [r3, #4]
8000c3e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000c42: 2b00 cmp r3, #0
8000c44: f000 80b1 beq.w 8000daa <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8000c48: 4b4d ldr r3, [pc, #308] @ (8000d80 <HAL_GPIO_Init+0x2b8>)
8000c4a: 699b ldr r3, [r3, #24]
8000c4c: 4a4c ldr r2, [pc, #304] @ (8000d80 <HAL_GPIO_Init+0x2b8>)
8000c4e: f043 0301 orr.w r3, r3, #1
8000c52: 6193 str r3, [r2, #24]
8000c54: 4b4a ldr r3, [pc, #296] @ (8000d80 <HAL_GPIO_Init+0x2b8>)
8000c56: 699b ldr r3, [r3, #24]
8000c58: f003 0301 and.w r3, r3, #1
8000c5c: 60bb str r3, [r7, #8]
8000c5e: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8000c60: 4a48 ldr r2, [pc, #288] @ (8000d84 <HAL_GPIO_Init+0x2bc>)
8000c62: 6a7b ldr r3, [r7, #36] @ 0x24
8000c64: 089b lsrs r3, r3, #2
8000c66: 3302 adds r3, #2
8000c68: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000c6c: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8000c6e: 6a7b ldr r3, [r7, #36] @ 0x24
8000c70: f003 0303 and.w r3, r3, #3
8000c74: 009b lsls r3, r3, #2
8000c76: 220f movs r2, #15
8000c78: fa02 f303 lsl.w r3, r2, r3
8000c7c: 43db mvns r3, r3
8000c7e: 68fa ldr r2, [r7, #12]
8000c80: 4013 ands r3, r2
8000c82: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8000c84: 687b ldr r3, [r7, #4]
8000c86: 4a40 ldr r2, [pc, #256] @ (8000d88 <HAL_GPIO_Init+0x2c0>)
8000c88: 4293 cmp r3, r2
8000c8a: d013 beq.n 8000cb4 <HAL_GPIO_Init+0x1ec>
8000c8c: 687b ldr r3, [r7, #4]
8000c8e: 4a3f ldr r2, [pc, #252] @ (8000d8c <HAL_GPIO_Init+0x2c4>)
8000c90: 4293 cmp r3, r2
8000c92: d00d beq.n 8000cb0 <HAL_GPIO_Init+0x1e8>
8000c94: 687b ldr r3, [r7, #4]
8000c96: 4a3e ldr r2, [pc, #248] @ (8000d90 <HAL_GPIO_Init+0x2c8>)
8000c98: 4293 cmp r3, r2
8000c9a: d007 beq.n 8000cac <HAL_GPIO_Init+0x1e4>
8000c9c: 687b ldr r3, [r7, #4]
8000c9e: 4a3d ldr r2, [pc, #244] @ (8000d94 <HAL_GPIO_Init+0x2cc>)
8000ca0: 4293 cmp r3, r2
8000ca2: d101 bne.n 8000ca8 <HAL_GPIO_Init+0x1e0>
8000ca4: 2303 movs r3, #3
8000ca6: e006 b.n 8000cb6 <HAL_GPIO_Init+0x1ee>
8000ca8: 2304 movs r3, #4
8000caa: e004 b.n 8000cb6 <HAL_GPIO_Init+0x1ee>
8000cac: 2302 movs r3, #2
8000cae: e002 b.n 8000cb6 <HAL_GPIO_Init+0x1ee>
8000cb0: 2301 movs r3, #1
8000cb2: e000 b.n 8000cb6 <HAL_GPIO_Init+0x1ee>
8000cb4: 2300 movs r3, #0
8000cb6: 6a7a ldr r2, [r7, #36] @ 0x24
8000cb8: f002 0203 and.w r2, r2, #3
8000cbc: 0092 lsls r2, r2, #2
8000cbe: 4093 lsls r3, r2
8000cc0: 68fa ldr r2, [r7, #12]
8000cc2: 4313 orrs r3, r2
8000cc4: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8000cc6: 492f ldr r1, [pc, #188] @ (8000d84 <HAL_GPIO_Init+0x2bc>)
8000cc8: 6a7b ldr r3, [r7, #36] @ 0x24
8000cca: 089b lsrs r3, r3, #2
8000ccc: 3302 adds r3, #2
8000cce: 68fa ldr r2, [r7, #12]
8000cd0: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000cd4: 683b ldr r3, [r7, #0]
8000cd6: 685b ldr r3, [r3, #4]
8000cd8: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8000cdc: 2b00 cmp r3, #0
8000cde: d006 beq.n 8000cee <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8000ce0: 4b2d ldr r3, [pc, #180] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000ce2: 689a ldr r2, [r3, #8]
8000ce4: 492c ldr r1, [pc, #176] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000ce6: 69bb ldr r3, [r7, #24]
8000ce8: 4313 orrs r3, r2
8000cea: 608b str r3, [r1, #8]
8000cec: e006 b.n 8000cfc <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8000cee: 4b2a ldr r3, [pc, #168] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000cf0: 689a ldr r2, [r3, #8]
8000cf2: 69bb ldr r3, [r7, #24]
8000cf4: 43db mvns r3, r3
8000cf6: 4928 ldr r1, [pc, #160] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000cf8: 4013 ands r3, r2
8000cfa: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000cfc: 683b ldr r3, [r7, #0]
8000cfe: 685b ldr r3, [r3, #4]
8000d00: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8000d04: 2b00 cmp r3, #0
8000d06: d006 beq.n 8000d16 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
8000d08: 4b23 ldr r3, [pc, #140] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d0a: 68da ldr r2, [r3, #12]
8000d0c: 4922 ldr r1, [pc, #136] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d0e: 69bb ldr r3, [r7, #24]
8000d10: 4313 orrs r3, r2
8000d12: 60cb str r3, [r1, #12]
8000d14: e006 b.n 8000d24 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8000d16: 4b20 ldr r3, [pc, #128] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d18: 68da ldr r2, [r3, #12]
8000d1a: 69bb ldr r3, [r7, #24]
8000d1c: 43db mvns r3, r3
8000d1e: 491e ldr r1, [pc, #120] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d20: 4013 ands r3, r2
8000d22: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000d24: 683b ldr r3, [r7, #0]
8000d26: 685b ldr r3, [r3, #4]
8000d28: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000d2c: 2b00 cmp r3, #0
8000d2e: d006 beq.n 8000d3e <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
8000d30: 4b19 ldr r3, [pc, #100] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d32: 685a ldr r2, [r3, #4]
8000d34: 4918 ldr r1, [pc, #96] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d36: 69bb ldr r3, [r7, #24]
8000d38: 4313 orrs r3, r2
8000d3a: 604b str r3, [r1, #4]
8000d3c: e006 b.n 8000d4c <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8000d3e: 4b16 ldr r3, [pc, #88] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d40: 685a ldr r2, [r3, #4]
8000d42: 69bb ldr r3, [r7, #24]
8000d44: 43db mvns r3, r3
8000d46: 4914 ldr r1, [pc, #80] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d48: 4013 ands r3, r2
8000d4a: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000d4c: 683b ldr r3, [r7, #0]
8000d4e: 685b ldr r3, [r3, #4]
8000d50: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000d54: 2b00 cmp r3, #0
8000d56: d021 beq.n 8000d9c <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
8000d58: 4b0f ldr r3, [pc, #60] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d5a: 681a ldr r2, [r3, #0]
8000d5c: 490e ldr r1, [pc, #56] @ (8000d98 <HAL_GPIO_Init+0x2d0>)
8000d5e: 69bb ldr r3, [r7, #24]
8000d60: 4313 orrs r3, r2
8000d62: 600b str r3, [r1, #0]
8000d64: e021 b.n 8000daa <HAL_GPIO_Init+0x2e2>
8000d66: bf00 nop
8000d68: 10320000 .word 0x10320000
8000d6c: 10310000 .word 0x10310000
8000d70: 10220000 .word 0x10220000
8000d74: 10210000 .word 0x10210000
8000d78: 10120000 .word 0x10120000
8000d7c: 10110000 .word 0x10110000
8000d80: 40021000 .word 0x40021000
8000d84: 40010000 .word 0x40010000
8000d88: 40010800 .word 0x40010800
8000d8c: 40010c00 .word 0x40010c00
8000d90: 40011000 .word 0x40011000
8000d94: 40011400 .word 0x40011400
8000d98: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8000d9c: 4b0b ldr r3, [pc, #44] @ (8000dcc <HAL_GPIO_Init+0x304>)
8000d9e: 681a ldr r2, [r3, #0]
8000da0: 69bb ldr r3, [r7, #24]
8000da2: 43db mvns r3, r3
8000da4: 4909 ldr r1, [pc, #36] @ (8000dcc <HAL_GPIO_Init+0x304>)
8000da6: 4013 ands r3, r2
8000da8: 600b str r3, [r1, #0]
}
}
}
position++;
8000daa: 6a7b ldr r3, [r7, #36] @ 0x24
8000dac: 3301 adds r3, #1
8000dae: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000db0: 683b ldr r3, [r7, #0]
8000db2: 681a ldr r2, [r3, #0]
8000db4: 6a7b ldr r3, [r7, #36] @ 0x24
8000db6: fa22 f303 lsr.w r3, r2, r3
8000dba: 2b00 cmp r3, #0
8000dbc: f47f ae8e bne.w 8000adc <HAL_GPIO_Init+0x14>
}
}
8000dc0: bf00 nop
8000dc2: bf00 nop
8000dc4: 372c adds r7, #44 @ 0x2c
8000dc6: 46bd mov sp, r7
8000dc8: bc80 pop {r7}
8000dca: 4770 bx lr
8000dcc: 40010400 .word 0x40010400
08000dd0 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000dd0: b580 push {r7, lr}
8000dd2: b086 sub sp, #24
8000dd4: af00 add r7, sp, #0
8000dd6: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000dd8: 687b ldr r3, [r7, #4]
8000dda: 2b00 cmp r3, #0
8000ddc: d101 bne.n 8000de2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000dde: 2301 movs r3, #1
8000de0: e272 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000de2: 687b ldr r3, [r7, #4]
8000de4: 681b ldr r3, [r3, #0]
8000de6: f003 0301 and.w r3, r3, #1
8000dea: 2b00 cmp r3, #0
8000dec: f000 8087 beq.w 8000efe <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000df0: 4b92 ldr r3, [pc, #584] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000df2: 685b ldr r3, [r3, #4]
8000df4: f003 030c and.w r3, r3, #12
8000df8: 2b04 cmp r3, #4
8000dfa: d00c beq.n 8000e16 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000dfc: 4b8f ldr r3, [pc, #572] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000dfe: 685b ldr r3, [r3, #4]
8000e00: f003 030c and.w r3, r3, #12
8000e04: 2b08 cmp r3, #8
8000e06: d112 bne.n 8000e2e <HAL_RCC_OscConfig+0x5e>
8000e08: 4b8c ldr r3, [pc, #560] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e0a: 685b ldr r3, [r3, #4]
8000e0c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000e10: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000e14: d10b bne.n 8000e2e <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000e16: 4b89 ldr r3, [pc, #548] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e18: 681b ldr r3, [r3, #0]
8000e1a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000e1e: 2b00 cmp r3, #0
8000e20: d06c beq.n 8000efc <HAL_RCC_OscConfig+0x12c>
8000e22: 687b ldr r3, [r7, #4]
8000e24: 685b ldr r3, [r3, #4]
8000e26: 2b00 cmp r3, #0
8000e28: d168 bne.n 8000efc <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000e2a: 2301 movs r3, #1
8000e2c: e24c b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000e2e: 687b ldr r3, [r7, #4]
8000e30: 685b ldr r3, [r3, #4]
8000e32: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000e36: d106 bne.n 8000e46 <HAL_RCC_OscConfig+0x76>
8000e38: 4b80 ldr r3, [pc, #512] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e3a: 681b ldr r3, [r3, #0]
8000e3c: 4a7f ldr r2, [pc, #508] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e3e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000e42: 6013 str r3, [r2, #0]
8000e44: e02e b.n 8000ea4 <HAL_RCC_OscConfig+0xd4>
8000e46: 687b ldr r3, [r7, #4]
8000e48: 685b ldr r3, [r3, #4]
8000e4a: 2b00 cmp r3, #0
8000e4c: d10c bne.n 8000e68 <HAL_RCC_OscConfig+0x98>
8000e4e: 4b7b ldr r3, [pc, #492] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e50: 681b ldr r3, [r3, #0]
8000e52: 4a7a ldr r2, [pc, #488] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e54: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000e58: 6013 str r3, [r2, #0]
8000e5a: 4b78 ldr r3, [pc, #480] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e5c: 681b ldr r3, [r3, #0]
8000e5e: 4a77 ldr r2, [pc, #476] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e60: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000e64: 6013 str r3, [r2, #0]
8000e66: e01d b.n 8000ea4 <HAL_RCC_OscConfig+0xd4>
8000e68: 687b ldr r3, [r7, #4]
8000e6a: 685b ldr r3, [r3, #4]
8000e6c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8000e70: d10c bne.n 8000e8c <HAL_RCC_OscConfig+0xbc>
8000e72: 4b72 ldr r3, [pc, #456] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e74: 681b ldr r3, [r3, #0]
8000e76: 4a71 ldr r2, [pc, #452] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e78: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000e7c: 6013 str r3, [r2, #0]
8000e7e: 4b6f ldr r3, [pc, #444] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e80: 681b ldr r3, [r3, #0]
8000e82: 4a6e ldr r2, [pc, #440] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e84: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000e88: 6013 str r3, [r2, #0]
8000e8a: e00b b.n 8000ea4 <HAL_RCC_OscConfig+0xd4>
8000e8c: 4b6b ldr r3, [pc, #428] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e8e: 681b ldr r3, [r3, #0]
8000e90: 4a6a ldr r2, [pc, #424] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e92: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000e96: 6013 str r3, [r2, #0]
8000e98: 4b68 ldr r3, [pc, #416] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e9a: 681b ldr r3, [r3, #0]
8000e9c: 4a67 ldr r2, [pc, #412] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000e9e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000ea2: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000ea4: 687b ldr r3, [r7, #4]
8000ea6: 685b ldr r3, [r3, #4]
8000ea8: 2b00 cmp r3, #0
8000eaa: d013 beq.n 8000ed4 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000eac: f7ff fd1e bl 80008ec <HAL_GetTick>
8000eb0: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000eb2: e008 b.n 8000ec6 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000eb4: f7ff fd1a bl 80008ec <HAL_GetTick>
8000eb8: 4602 mov r2, r0
8000eba: 693b ldr r3, [r7, #16]
8000ebc: 1ad3 subs r3, r2, r3
8000ebe: 2b64 cmp r3, #100 @ 0x64
8000ec0: d901 bls.n 8000ec6 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000ec2: 2303 movs r3, #3
8000ec4: e200 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000ec6: 4b5d ldr r3, [pc, #372] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000ec8: 681b ldr r3, [r3, #0]
8000eca: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000ece: 2b00 cmp r3, #0
8000ed0: d0f0 beq.n 8000eb4 <HAL_RCC_OscConfig+0xe4>
8000ed2: e014 b.n 8000efe <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ed4: f7ff fd0a bl 80008ec <HAL_GetTick>
8000ed8: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000eda: e008 b.n 8000eee <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000edc: f7ff fd06 bl 80008ec <HAL_GetTick>
8000ee0: 4602 mov r2, r0
8000ee2: 693b ldr r3, [r7, #16]
8000ee4: 1ad3 subs r3, r2, r3
8000ee6: 2b64 cmp r3, #100 @ 0x64
8000ee8: d901 bls.n 8000eee <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000eea: 2303 movs r3, #3
8000eec: e1ec b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000eee: 4b53 ldr r3, [pc, #332] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000ef0: 681b ldr r3, [r3, #0]
8000ef2: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000ef6: 2b00 cmp r3, #0
8000ef8: d1f0 bne.n 8000edc <HAL_RCC_OscConfig+0x10c>
8000efa: e000 b.n 8000efe <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000efc: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000efe: 687b ldr r3, [r7, #4]
8000f00: 681b ldr r3, [r3, #0]
8000f02: f003 0302 and.w r3, r3, #2
8000f06: 2b00 cmp r3, #0
8000f08: d063 beq.n 8000fd2 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000f0a: 4b4c ldr r3, [pc, #304] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f0c: 685b ldr r3, [r3, #4]
8000f0e: f003 030c and.w r3, r3, #12
8000f12: 2b00 cmp r3, #0
8000f14: d00b beq.n 8000f2e <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8000f16: 4b49 ldr r3, [pc, #292] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f18: 685b ldr r3, [r3, #4]
8000f1a: f003 030c and.w r3, r3, #12
8000f1e: 2b08 cmp r3, #8
8000f20: d11c bne.n 8000f5c <HAL_RCC_OscConfig+0x18c>
8000f22: 4b46 ldr r3, [pc, #280] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f24: 685b ldr r3, [r3, #4]
8000f26: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000f2a: 2b00 cmp r3, #0
8000f2c: d116 bne.n 8000f5c <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000f2e: 4b43 ldr r3, [pc, #268] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f30: 681b ldr r3, [r3, #0]
8000f32: f003 0302 and.w r3, r3, #2
8000f36: 2b00 cmp r3, #0
8000f38: d005 beq.n 8000f46 <HAL_RCC_OscConfig+0x176>
8000f3a: 687b ldr r3, [r7, #4]
8000f3c: 691b ldr r3, [r3, #16]
8000f3e: 2b01 cmp r3, #1
8000f40: d001 beq.n 8000f46 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000f42: 2301 movs r3, #1
8000f44: e1c0 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000f46: 4b3d ldr r3, [pc, #244] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f48: 681b ldr r3, [r3, #0]
8000f4a: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8000f4e: 687b ldr r3, [r7, #4]
8000f50: 695b ldr r3, [r3, #20]
8000f52: 00db lsls r3, r3, #3
8000f54: 4939 ldr r1, [pc, #228] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f56: 4313 orrs r3, r2
8000f58: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000f5a: e03a b.n 8000fd2 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000f5c: 687b ldr r3, [r7, #4]
8000f5e: 691b ldr r3, [r3, #16]
8000f60: 2b00 cmp r3, #0
8000f62: d020 beq.n 8000fa6 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000f64: 4b36 ldr r3, [pc, #216] @ (8001040 <HAL_RCC_OscConfig+0x270>)
8000f66: 2201 movs r2, #1
8000f68: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f6a: f7ff fcbf bl 80008ec <HAL_GetTick>
8000f6e: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000f70: e008 b.n 8000f84 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000f72: f7ff fcbb bl 80008ec <HAL_GetTick>
8000f76: 4602 mov r2, r0
8000f78: 693b ldr r3, [r7, #16]
8000f7a: 1ad3 subs r3, r2, r3
8000f7c: 2b02 cmp r3, #2
8000f7e: d901 bls.n 8000f84 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000f80: 2303 movs r3, #3
8000f82: e1a1 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000f84: 4b2d ldr r3, [pc, #180] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f86: 681b ldr r3, [r3, #0]
8000f88: f003 0302 and.w r3, r3, #2
8000f8c: 2b00 cmp r3, #0
8000f8e: d0f0 beq.n 8000f72 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000f90: 4b2a ldr r3, [pc, #168] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000f92: 681b ldr r3, [r3, #0]
8000f94: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8000f98: 687b ldr r3, [r7, #4]
8000f9a: 695b ldr r3, [r3, #20]
8000f9c: 00db lsls r3, r3, #3
8000f9e: 4927 ldr r1, [pc, #156] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000fa0: 4313 orrs r3, r2
8000fa2: 600b str r3, [r1, #0]
8000fa4: e015 b.n 8000fd2 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000fa6: 4b26 ldr r3, [pc, #152] @ (8001040 <HAL_RCC_OscConfig+0x270>)
8000fa8: 2200 movs r2, #0
8000faa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fac: f7ff fc9e bl 80008ec <HAL_GetTick>
8000fb0: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000fb2: e008 b.n 8000fc6 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000fb4: f7ff fc9a bl 80008ec <HAL_GetTick>
8000fb8: 4602 mov r2, r0
8000fba: 693b ldr r3, [r7, #16]
8000fbc: 1ad3 subs r3, r2, r3
8000fbe: 2b02 cmp r3, #2
8000fc0: d901 bls.n 8000fc6 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000fc2: 2303 movs r3, #3
8000fc4: e180 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000fc6: 4b1d ldr r3, [pc, #116] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8000fc8: 681b ldr r3, [r3, #0]
8000fca: f003 0302 and.w r3, r3, #2
8000fce: 2b00 cmp r3, #0
8000fd0: d1f0 bne.n 8000fb4 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000fd2: 687b ldr r3, [r7, #4]
8000fd4: 681b ldr r3, [r3, #0]
8000fd6: f003 0308 and.w r3, r3, #8
8000fda: 2b00 cmp r3, #0
8000fdc: d03a beq.n 8001054 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000fde: 687b ldr r3, [r7, #4]
8000fe0: 699b ldr r3, [r3, #24]
8000fe2: 2b00 cmp r3, #0
8000fe4: d019 beq.n 800101a <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000fe6: 4b17 ldr r3, [pc, #92] @ (8001044 <HAL_RCC_OscConfig+0x274>)
8000fe8: 2201 movs r2, #1
8000fea: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fec: f7ff fc7e bl 80008ec <HAL_GetTick>
8000ff0: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000ff2: e008 b.n 8001006 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000ff4: f7ff fc7a bl 80008ec <HAL_GetTick>
8000ff8: 4602 mov r2, r0
8000ffa: 693b ldr r3, [r7, #16]
8000ffc: 1ad3 subs r3, r2, r3
8000ffe: 2b02 cmp r3, #2
8001000: d901 bls.n 8001006 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8001002: 2303 movs r3, #3
8001004: e160 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001006: 4b0d ldr r3, [pc, #52] @ (800103c <HAL_RCC_OscConfig+0x26c>)
8001008: 6a5b ldr r3, [r3, #36] @ 0x24
800100a: f003 0302 and.w r3, r3, #2
800100e: 2b00 cmp r3, #0
8001010: d0f0 beq.n 8000ff4 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8001012: 2001 movs r0, #1
8001014: f000 fa9c bl 8001550 <RCC_Delay>
8001018: e01c b.n 8001054 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800101a: 4b0a ldr r3, [pc, #40] @ (8001044 <HAL_RCC_OscConfig+0x274>)
800101c: 2200 movs r2, #0
800101e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001020: f7ff fc64 bl 80008ec <HAL_GetTick>
8001024: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001026: e00f b.n 8001048 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001028: f7ff fc60 bl 80008ec <HAL_GetTick>
800102c: 4602 mov r2, r0
800102e: 693b ldr r3, [r7, #16]
8001030: 1ad3 subs r3, r2, r3
8001032: 2b02 cmp r3, #2
8001034: d908 bls.n 8001048 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8001036: 2303 movs r3, #3
8001038: e146 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
800103a: bf00 nop
800103c: 40021000 .word 0x40021000
8001040: 42420000 .word 0x42420000
8001044: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001048: 4b92 ldr r3, [pc, #584] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800104a: 6a5b ldr r3, [r3, #36] @ 0x24
800104c: f003 0302 and.w r3, r3, #2
8001050: 2b00 cmp r3, #0
8001052: d1e9 bne.n 8001028 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001054: 687b ldr r3, [r7, #4]
8001056: 681b ldr r3, [r3, #0]
8001058: f003 0304 and.w r3, r3, #4
800105c: 2b00 cmp r3, #0
800105e: f000 80a6 beq.w 80011ae <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8001062: 2300 movs r3, #0
8001064: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8001066: 4b8b ldr r3, [pc, #556] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001068: 69db ldr r3, [r3, #28]
800106a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800106e: 2b00 cmp r3, #0
8001070: d10d bne.n 800108e <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001072: 4b88 ldr r3, [pc, #544] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001074: 69db ldr r3, [r3, #28]
8001076: 4a87 ldr r2, [pc, #540] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001078: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800107c: 61d3 str r3, [r2, #28]
800107e: 4b85 ldr r3, [pc, #532] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001080: 69db ldr r3, [r3, #28]
8001082: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001086: 60bb str r3, [r7, #8]
8001088: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800108a: 2301 movs r3, #1
800108c: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800108e: 4b82 ldr r3, [pc, #520] @ (8001298 <HAL_RCC_OscConfig+0x4c8>)
8001090: 681b ldr r3, [r3, #0]
8001092: f403 7380 and.w r3, r3, #256 @ 0x100
8001096: 2b00 cmp r3, #0
8001098: d118 bne.n 80010cc <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800109a: 4b7f ldr r3, [pc, #508] @ (8001298 <HAL_RCC_OscConfig+0x4c8>)
800109c: 681b ldr r3, [r3, #0]
800109e: 4a7e ldr r2, [pc, #504] @ (8001298 <HAL_RCC_OscConfig+0x4c8>)
80010a0: f443 7380 orr.w r3, r3, #256 @ 0x100
80010a4: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80010a6: f7ff fc21 bl 80008ec <HAL_GetTick>
80010aa: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80010ac: e008 b.n 80010c0 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80010ae: f7ff fc1d bl 80008ec <HAL_GetTick>
80010b2: 4602 mov r2, r0
80010b4: 693b ldr r3, [r7, #16]
80010b6: 1ad3 subs r3, r2, r3
80010b8: 2b64 cmp r3, #100 @ 0x64
80010ba: d901 bls.n 80010c0 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
80010bc: 2303 movs r3, #3
80010be: e103 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80010c0: 4b75 ldr r3, [pc, #468] @ (8001298 <HAL_RCC_OscConfig+0x4c8>)
80010c2: 681b ldr r3, [r3, #0]
80010c4: f403 7380 and.w r3, r3, #256 @ 0x100
80010c8: 2b00 cmp r3, #0
80010ca: d0f0 beq.n 80010ae <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80010cc: 687b ldr r3, [r7, #4]
80010ce: 68db ldr r3, [r3, #12]
80010d0: 2b01 cmp r3, #1
80010d2: d106 bne.n 80010e2 <HAL_RCC_OscConfig+0x312>
80010d4: 4b6f ldr r3, [pc, #444] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80010d6: 6a1b ldr r3, [r3, #32]
80010d8: 4a6e ldr r2, [pc, #440] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80010da: f043 0301 orr.w r3, r3, #1
80010de: 6213 str r3, [r2, #32]
80010e0: e02d b.n 800113e <HAL_RCC_OscConfig+0x36e>
80010e2: 687b ldr r3, [r7, #4]
80010e4: 68db ldr r3, [r3, #12]
80010e6: 2b00 cmp r3, #0
80010e8: d10c bne.n 8001104 <HAL_RCC_OscConfig+0x334>
80010ea: 4b6a ldr r3, [pc, #424] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80010ec: 6a1b ldr r3, [r3, #32]
80010ee: 4a69 ldr r2, [pc, #420] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80010f0: f023 0301 bic.w r3, r3, #1
80010f4: 6213 str r3, [r2, #32]
80010f6: 4b67 ldr r3, [pc, #412] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80010f8: 6a1b ldr r3, [r3, #32]
80010fa: 4a66 ldr r2, [pc, #408] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80010fc: f023 0304 bic.w r3, r3, #4
8001100: 6213 str r3, [r2, #32]
8001102: e01c b.n 800113e <HAL_RCC_OscConfig+0x36e>
8001104: 687b ldr r3, [r7, #4]
8001106: 68db ldr r3, [r3, #12]
8001108: 2b05 cmp r3, #5
800110a: d10c bne.n 8001126 <HAL_RCC_OscConfig+0x356>
800110c: 4b61 ldr r3, [pc, #388] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800110e: 6a1b ldr r3, [r3, #32]
8001110: 4a60 ldr r2, [pc, #384] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001112: f043 0304 orr.w r3, r3, #4
8001116: 6213 str r3, [r2, #32]
8001118: 4b5e ldr r3, [pc, #376] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800111a: 6a1b ldr r3, [r3, #32]
800111c: 4a5d ldr r2, [pc, #372] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800111e: f043 0301 orr.w r3, r3, #1
8001122: 6213 str r3, [r2, #32]
8001124: e00b b.n 800113e <HAL_RCC_OscConfig+0x36e>
8001126: 4b5b ldr r3, [pc, #364] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001128: 6a1b ldr r3, [r3, #32]
800112a: 4a5a ldr r2, [pc, #360] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800112c: f023 0301 bic.w r3, r3, #1
8001130: 6213 str r3, [r2, #32]
8001132: 4b58 ldr r3, [pc, #352] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001134: 6a1b ldr r3, [r3, #32]
8001136: 4a57 ldr r2, [pc, #348] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001138: f023 0304 bic.w r3, r3, #4
800113c: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800113e: 687b ldr r3, [r7, #4]
8001140: 68db ldr r3, [r3, #12]
8001142: 2b00 cmp r3, #0
8001144: d015 beq.n 8001172 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001146: f7ff fbd1 bl 80008ec <HAL_GetTick>
800114a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800114c: e00a b.n 8001164 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800114e: f7ff fbcd bl 80008ec <HAL_GetTick>
8001152: 4602 mov r2, r0
8001154: 693b ldr r3, [r7, #16]
8001156: 1ad3 subs r3, r2, r3
8001158: f241 3288 movw r2, #5000 @ 0x1388
800115c: 4293 cmp r3, r2
800115e: d901 bls.n 8001164 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8001160: 2303 movs r3, #3
8001162: e0b1 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001164: 4b4b ldr r3, [pc, #300] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001166: 6a1b ldr r3, [r3, #32]
8001168: f003 0302 and.w r3, r3, #2
800116c: 2b00 cmp r3, #0
800116e: d0ee beq.n 800114e <HAL_RCC_OscConfig+0x37e>
8001170: e014 b.n 800119c <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001172: f7ff fbbb bl 80008ec <HAL_GetTick>
8001176: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001178: e00a b.n 8001190 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800117a: f7ff fbb7 bl 80008ec <HAL_GetTick>
800117e: 4602 mov r2, r0
8001180: 693b ldr r3, [r7, #16]
8001182: 1ad3 subs r3, r2, r3
8001184: f241 3288 movw r2, #5000 @ 0x1388
8001188: 4293 cmp r3, r2
800118a: d901 bls.n 8001190 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
800118c: 2303 movs r3, #3
800118e: e09b b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001190: 4b40 ldr r3, [pc, #256] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001192: 6a1b ldr r3, [r3, #32]
8001194: f003 0302 and.w r3, r3, #2
8001198: 2b00 cmp r3, #0
800119a: d1ee bne.n 800117a <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
800119c: 7dfb ldrb r3, [r7, #23]
800119e: 2b01 cmp r3, #1
80011a0: d105 bne.n 80011ae <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
80011a2: 4b3c ldr r3, [pc, #240] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80011a4: 69db ldr r3, [r3, #28]
80011a6: 4a3b ldr r2, [pc, #236] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80011a8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80011ac: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80011ae: 687b ldr r3, [r7, #4]
80011b0: 69db ldr r3, [r3, #28]
80011b2: 2b00 cmp r3, #0
80011b4: f000 8087 beq.w 80012c6 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80011b8: 4b36 ldr r3, [pc, #216] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80011ba: 685b ldr r3, [r3, #4]
80011bc: f003 030c and.w r3, r3, #12
80011c0: 2b08 cmp r3, #8
80011c2: d061 beq.n 8001288 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80011c4: 687b ldr r3, [r7, #4]
80011c6: 69db ldr r3, [r3, #28]
80011c8: 2b02 cmp r3, #2
80011ca: d146 bne.n 800125a <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80011cc: 4b33 ldr r3, [pc, #204] @ (800129c <HAL_RCC_OscConfig+0x4cc>)
80011ce: 2200 movs r2, #0
80011d0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011d2: f7ff fb8b bl 80008ec <HAL_GetTick>
80011d6: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80011d8: e008 b.n 80011ec <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80011da: f7ff fb87 bl 80008ec <HAL_GetTick>
80011de: 4602 mov r2, r0
80011e0: 693b ldr r3, [r7, #16]
80011e2: 1ad3 subs r3, r2, r3
80011e4: 2b02 cmp r3, #2
80011e6: d901 bls.n 80011ec <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
80011e8: 2303 movs r3, #3
80011ea: e06d b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80011ec: 4b29 ldr r3, [pc, #164] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
80011ee: 681b ldr r3, [r3, #0]
80011f0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80011f4: 2b00 cmp r3, #0
80011f6: d1f0 bne.n 80011da <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
80011f8: 687b ldr r3, [r7, #4]
80011fa: 6a1b ldr r3, [r3, #32]
80011fc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001200: d108 bne.n 8001214 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8001202: 4b24 ldr r3, [pc, #144] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001204: 685b ldr r3, [r3, #4]
8001206: f423 3200 bic.w r2, r3, #131072 @ 0x20000
800120a: 687b ldr r3, [r7, #4]
800120c: 689b ldr r3, [r3, #8]
800120e: 4921 ldr r1, [pc, #132] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001210: 4313 orrs r3, r2
8001212: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001214: 4b1f ldr r3, [pc, #124] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001216: 685b ldr r3, [r3, #4]
8001218: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
800121c: 687b ldr r3, [r7, #4]
800121e: 6a19 ldr r1, [r3, #32]
8001220: 687b ldr r3, [r7, #4]
8001222: 6a5b ldr r3, [r3, #36] @ 0x24
8001224: 430b orrs r3, r1
8001226: 491b ldr r1, [pc, #108] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
8001228: 4313 orrs r3, r2
800122a: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800122c: 4b1b ldr r3, [pc, #108] @ (800129c <HAL_RCC_OscConfig+0x4cc>)
800122e: 2201 movs r2, #1
8001230: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001232: f7ff fb5b bl 80008ec <HAL_GetTick>
8001236: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001238: e008 b.n 800124c <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800123a: f7ff fb57 bl 80008ec <HAL_GetTick>
800123e: 4602 mov r2, r0
8001240: 693b ldr r3, [r7, #16]
8001242: 1ad3 subs r3, r2, r3
8001244: 2b02 cmp r3, #2
8001246: d901 bls.n 800124c <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8001248: 2303 movs r3, #3
800124a: e03d b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800124c: 4b11 ldr r3, [pc, #68] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800124e: 681b ldr r3, [r3, #0]
8001250: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001254: 2b00 cmp r3, #0
8001256: d0f0 beq.n 800123a <HAL_RCC_OscConfig+0x46a>
8001258: e035 b.n 80012c6 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800125a: 4b10 ldr r3, [pc, #64] @ (800129c <HAL_RCC_OscConfig+0x4cc>)
800125c: 2200 movs r2, #0
800125e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001260: f7ff fb44 bl 80008ec <HAL_GetTick>
8001264: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001266: e008 b.n 800127a <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001268: f7ff fb40 bl 80008ec <HAL_GetTick>
800126c: 4602 mov r2, r0
800126e: 693b ldr r3, [r7, #16]
8001270: 1ad3 subs r3, r2, r3
8001272: 2b02 cmp r3, #2
8001274: d901 bls.n 800127a <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8001276: 2303 movs r3, #3
8001278: e026 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800127a: 4b06 ldr r3, [pc, #24] @ (8001294 <HAL_RCC_OscConfig+0x4c4>)
800127c: 681b ldr r3, [r3, #0]
800127e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001282: 2b00 cmp r3, #0
8001284: d1f0 bne.n 8001268 <HAL_RCC_OscConfig+0x498>
8001286: e01e b.n 80012c6 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001288: 687b ldr r3, [r7, #4]
800128a: 69db ldr r3, [r3, #28]
800128c: 2b01 cmp r3, #1
800128e: d107 bne.n 80012a0 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8001290: 2301 movs r3, #1
8001292: e019 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
8001294: 40021000 .word 0x40021000
8001298: 40007000 .word 0x40007000
800129c: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80012a0: 4b0b ldr r3, [pc, #44] @ (80012d0 <HAL_RCC_OscConfig+0x500>)
80012a2: 685b ldr r3, [r3, #4]
80012a4: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80012a6: 68fb ldr r3, [r7, #12]
80012a8: f403 3280 and.w r2, r3, #65536 @ 0x10000
80012ac: 687b ldr r3, [r7, #4]
80012ae: 6a1b ldr r3, [r3, #32]
80012b0: 429a cmp r2, r3
80012b2: d106 bne.n 80012c2 <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
80012b4: 68fb ldr r3, [r7, #12]
80012b6: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
80012ba: 687b ldr r3, [r7, #4]
80012bc: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80012be: 429a cmp r2, r3
80012c0: d001 beq.n 80012c6 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80012c2: 2301 movs r3, #1
80012c4: e000 b.n 80012c8 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80012c6: 2300 movs r3, #0
}
80012c8: 4618 mov r0, r3
80012ca: 3718 adds r7, #24
80012cc: 46bd mov sp, r7
80012ce: bd80 pop {r7, pc}
80012d0: 40021000 .word 0x40021000
080012d4 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80012d4: b580 push {r7, lr}
80012d6: b084 sub sp, #16
80012d8: af00 add r7, sp, #0
80012da: 6078 str r0, [r7, #4]
80012dc: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80012de: 687b ldr r3, [r7, #4]
80012e0: 2b00 cmp r3, #0
80012e2: d101 bne.n 80012e8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80012e4: 2301 movs r3, #1
80012e6: e0d0 b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80012e8: 4b6a ldr r3, [pc, #424] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
80012ea: 681b ldr r3, [r3, #0]
80012ec: f003 0307 and.w r3, r3, #7
80012f0: 683a ldr r2, [r7, #0]
80012f2: 429a cmp r2, r3
80012f4: d910 bls.n 8001318 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80012f6: 4b67 ldr r3, [pc, #412] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
80012f8: 681b ldr r3, [r3, #0]
80012fa: f023 0207 bic.w r2, r3, #7
80012fe: 4965 ldr r1, [pc, #404] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
8001300: 683b ldr r3, [r7, #0]
8001302: 4313 orrs r3, r2
8001304: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8001306: 4b63 ldr r3, [pc, #396] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
8001308: 681b ldr r3, [r3, #0]
800130a: f003 0307 and.w r3, r3, #7
800130e: 683a ldr r2, [r7, #0]
8001310: 429a cmp r2, r3
8001312: d001 beq.n 8001318 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8001314: 2301 movs r3, #1
8001316: e0b8 b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001318: 687b ldr r3, [r7, #4]
800131a: 681b ldr r3, [r3, #0]
800131c: f003 0302 and.w r3, r3, #2
8001320: 2b00 cmp r3, #0
8001322: d020 beq.n 8001366 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001324: 687b ldr r3, [r7, #4]
8001326: 681b ldr r3, [r3, #0]
8001328: f003 0304 and.w r3, r3, #4
800132c: 2b00 cmp r3, #0
800132e: d005 beq.n 800133c <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001330: 4b59 ldr r3, [pc, #356] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001332: 685b ldr r3, [r3, #4]
8001334: 4a58 ldr r2, [pc, #352] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001336: f443 63e0 orr.w r3, r3, #1792 @ 0x700
800133a: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800133c: 687b ldr r3, [r7, #4]
800133e: 681b ldr r3, [r3, #0]
8001340: f003 0308 and.w r3, r3, #8
8001344: 2b00 cmp r3, #0
8001346: d005 beq.n 8001354 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001348: 4b53 ldr r3, [pc, #332] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
800134a: 685b ldr r3, [r3, #4]
800134c: 4a52 ldr r2, [pc, #328] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
800134e: f443 5360 orr.w r3, r3, #14336 @ 0x3800
8001352: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001354: 4b50 ldr r3, [pc, #320] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001356: 685b ldr r3, [r3, #4]
8001358: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800135c: 687b ldr r3, [r7, #4]
800135e: 689b ldr r3, [r3, #8]
8001360: 494d ldr r1, [pc, #308] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001362: 4313 orrs r3, r2
8001364: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001366: 687b ldr r3, [r7, #4]
8001368: 681b ldr r3, [r3, #0]
800136a: f003 0301 and.w r3, r3, #1
800136e: 2b00 cmp r3, #0
8001370: d040 beq.n 80013f4 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001372: 687b ldr r3, [r7, #4]
8001374: 685b ldr r3, [r3, #4]
8001376: 2b01 cmp r3, #1
8001378: d107 bne.n 800138a <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800137a: 4b47 ldr r3, [pc, #284] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
800137c: 681b ldr r3, [r3, #0]
800137e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001382: 2b00 cmp r3, #0
8001384: d115 bne.n 80013b2 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001386: 2301 movs r3, #1
8001388: e07f b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800138a: 687b ldr r3, [r7, #4]
800138c: 685b ldr r3, [r3, #4]
800138e: 2b02 cmp r3, #2
8001390: d107 bne.n 80013a2 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001392: 4b41 ldr r3, [pc, #260] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001394: 681b ldr r3, [r3, #0]
8001396: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800139a: 2b00 cmp r3, #0
800139c: d109 bne.n 80013b2 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800139e: 2301 movs r3, #1
80013a0: e073 b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80013a2: 4b3d ldr r3, [pc, #244] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
80013a4: 681b ldr r3, [r3, #0]
80013a6: f003 0302 and.w r3, r3, #2
80013aa: 2b00 cmp r3, #0
80013ac: d101 bne.n 80013b2 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80013ae: 2301 movs r3, #1
80013b0: e06b b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80013b2: 4b39 ldr r3, [pc, #228] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
80013b4: 685b ldr r3, [r3, #4]
80013b6: f023 0203 bic.w r2, r3, #3
80013ba: 687b ldr r3, [r7, #4]
80013bc: 685b ldr r3, [r3, #4]
80013be: 4936 ldr r1, [pc, #216] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
80013c0: 4313 orrs r3, r2
80013c2: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013c4: f7ff fa92 bl 80008ec <HAL_GetTick>
80013c8: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80013ca: e00a b.n 80013e2 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80013cc: f7ff fa8e bl 80008ec <HAL_GetTick>
80013d0: 4602 mov r2, r0
80013d2: 68fb ldr r3, [r7, #12]
80013d4: 1ad3 subs r3, r2, r3
80013d6: f241 3288 movw r2, #5000 @ 0x1388
80013da: 4293 cmp r3, r2
80013dc: d901 bls.n 80013e2 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80013de: 2303 movs r3, #3
80013e0: e053 b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80013e2: 4b2d ldr r3, [pc, #180] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
80013e4: 685b ldr r3, [r3, #4]
80013e6: f003 020c and.w r2, r3, #12
80013ea: 687b ldr r3, [r7, #4]
80013ec: 685b ldr r3, [r3, #4]
80013ee: 009b lsls r3, r3, #2
80013f0: 429a cmp r2, r3
80013f2: d1eb bne.n 80013cc <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80013f4: 4b27 ldr r3, [pc, #156] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
80013f6: 681b ldr r3, [r3, #0]
80013f8: f003 0307 and.w r3, r3, #7
80013fc: 683a ldr r2, [r7, #0]
80013fe: 429a cmp r2, r3
8001400: d210 bcs.n 8001424 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001402: 4b24 ldr r3, [pc, #144] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
8001404: 681b ldr r3, [r3, #0]
8001406: f023 0207 bic.w r2, r3, #7
800140a: 4922 ldr r1, [pc, #136] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
800140c: 683b ldr r3, [r7, #0]
800140e: 4313 orrs r3, r2
8001410: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8001412: 4b20 ldr r3, [pc, #128] @ (8001494 <HAL_RCC_ClockConfig+0x1c0>)
8001414: 681b ldr r3, [r3, #0]
8001416: f003 0307 and.w r3, r3, #7
800141a: 683a ldr r2, [r7, #0]
800141c: 429a cmp r2, r3
800141e: d001 beq.n 8001424 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8001420: 2301 movs r3, #1
8001422: e032 b.n 800148a <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001424: 687b ldr r3, [r7, #4]
8001426: 681b ldr r3, [r3, #0]
8001428: f003 0304 and.w r3, r3, #4
800142c: 2b00 cmp r3, #0
800142e: d008 beq.n 8001442 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001430: 4b19 ldr r3, [pc, #100] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001432: 685b ldr r3, [r3, #4]
8001434: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8001438: 687b ldr r3, [r7, #4]
800143a: 68db ldr r3, [r3, #12]
800143c: 4916 ldr r1, [pc, #88] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
800143e: 4313 orrs r3, r2
8001440: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001442: 687b ldr r3, [r7, #4]
8001444: 681b ldr r3, [r3, #0]
8001446: f003 0308 and.w r3, r3, #8
800144a: 2b00 cmp r3, #0
800144c: d009 beq.n 8001462 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
800144e: 4b12 ldr r3, [pc, #72] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
8001450: 685b ldr r3, [r3, #4]
8001452: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8001456: 687b ldr r3, [r7, #4]
8001458: 691b ldr r3, [r3, #16]
800145a: 00db lsls r3, r3, #3
800145c: 490e ldr r1, [pc, #56] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
800145e: 4313 orrs r3, r2
8001460: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8001462: f000 f821 bl 80014a8 <HAL_RCC_GetSysClockFreq>
8001466: 4602 mov r2, r0
8001468: 4b0b ldr r3, [pc, #44] @ (8001498 <HAL_RCC_ClockConfig+0x1c4>)
800146a: 685b ldr r3, [r3, #4]
800146c: 091b lsrs r3, r3, #4
800146e: f003 030f and.w r3, r3, #15
8001472: 490a ldr r1, [pc, #40] @ (800149c <HAL_RCC_ClockConfig+0x1c8>)
8001474: 5ccb ldrb r3, [r1, r3]
8001476: fa22 f303 lsr.w r3, r2, r3
800147a: 4a09 ldr r2, [pc, #36] @ (80014a0 <HAL_RCC_ClockConfig+0x1cc>)
800147c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
800147e: 4b09 ldr r3, [pc, #36] @ (80014a4 <HAL_RCC_ClockConfig+0x1d0>)
8001480: 681b ldr r3, [r3, #0]
8001482: 4618 mov r0, r3
8001484: f7ff f9f0 bl 8000868 <HAL_InitTick>
return HAL_OK;
8001488: 2300 movs r3, #0
}
800148a: 4618 mov r0, r3
800148c: 3710 adds r7, #16
800148e: 46bd mov sp, r7
8001490: bd80 pop {r7, pc}
8001492: bf00 nop
8001494: 40022000 .word 0x40022000
8001498: 40021000 .word 0x40021000
800149c: 080020d8 .word 0x080020d8
80014a0: 20000000 .word 0x20000000
80014a4: 20000004 .word 0x20000004
080014a8 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80014a8: b480 push {r7}
80014aa: b087 sub sp, #28
80014ac: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80014ae: 2300 movs r3, #0
80014b0: 60fb str r3, [r7, #12]
80014b2: 2300 movs r3, #0
80014b4: 60bb str r3, [r7, #8]
80014b6: 2300 movs r3, #0
80014b8: 617b str r3, [r7, #20]
80014ba: 2300 movs r3, #0
80014bc: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80014be: 2300 movs r3, #0
80014c0: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80014c2: 4b1e ldr r3, [pc, #120] @ (800153c <HAL_RCC_GetSysClockFreq+0x94>)
80014c4: 685b ldr r3, [r3, #4]
80014c6: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80014c8: 68fb ldr r3, [r7, #12]
80014ca: f003 030c and.w r3, r3, #12
80014ce: 2b04 cmp r3, #4
80014d0: d002 beq.n 80014d8 <HAL_RCC_GetSysClockFreq+0x30>
80014d2: 2b08 cmp r3, #8
80014d4: d003 beq.n 80014de <HAL_RCC_GetSysClockFreq+0x36>
80014d6: e027 b.n 8001528 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80014d8: 4b19 ldr r3, [pc, #100] @ (8001540 <HAL_RCC_GetSysClockFreq+0x98>)
80014da: 613b str r3, [r7, #16]
break;
80014dc: e027 b.n 800152e <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80014de: 68fb ldr r3, [r7, #12]
80014e0: 0c9b lsrs r3, r3, #18
80014e2: f003 030f and.w r3, r3, #15
80014e6: 4a17 ldr r2, [pc, #92] @ (8001544 <HAL_RCC_GetSysClockFreq+0x9c>)
80014e8: 5cd3 ldrb r3, [r2, r3]
80014ea: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80014ec: 68fb ldr r3, [r7, #12]
80014ee: f403 3380 and.w r3, r3, #65536 @ 0x10000
80014f2: 2b00 cmp r3, #0
80014f4: d010 beq.n 8001518 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80014f6: 4b11 ldr r3, [pc, #68] @ (800153c <HAL_RCC_GetSysClockFreq+0x94>)
80014f8: 685b ldr r3, [r3, #4]
80014fa: 0c5b lsrs r3, r3, #17
80014fc: f003 0301 and.w r3, r3, #1
8001500: 4a11 ldr r2, [pc, #68] @ (8001548 <HAL_RCC_GetSysClockFreq+0xa0>)
8001502: 5cd3 ldrb r3, [r2, r3]
8001504: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8001506: 687b ldr r3, [r7, #4]
8001508: 4a0d ldr r2, [pc, #52] @ (8001540 <HAL_RCC_GetSysClockFreq+0x98>)
800150a: fb03 f202 mul.w r2, r3, r2
800150e: 68bb ldr r3, [r7, #8]
8001510: fbb2 f3f3 udiv r3, r2, r3
8001514: 617b str r3, [r7, #20]
8001516: e004 b.n 8001522 <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8001518: 687b ldr r3, [r7, #4]
800151a: 4a0c ldr r2, [pc, #48] @ (800154c <HAL_RCC_GetSysClockFreq+0xa4>)
800151c: fb02 f303 mul.w r3, r2, r3
8001520: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
8001522: 697b ldr r3, [r7, #20]
8001524: 613b str r3, [r7, #16]
break;
8001526: e002 b.n 800152e <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8001528: 4b05 ldr r3, [pc, #20] @ (8001540 <HAL_RCC_GetSysClockFreq+0x98>)
800152a: 613b str r3, [r7, #16]
break;
800152c: bf00 nop
}
}
return sysclockfreq;
800152e: 693b ldr r3, [r7, #16]
}
8001530: 4618 mov r0, r3
8001532: 371c adds r7, #28
8001534: 46bd mov sp, r7
8001536: bc80 pop {r7}
8001538: 4770 bx lr
800153a: bf00 nop
800153c: 40021000 .word 0x40021000
8001540: 007a1200 .word 0x007a1200
8001544: 080020e8 .word 0x080020e8
8001548: 080020f8 .word 0x080020f8
800154c: 003d0900 .word 0x003d0900
08001550 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8001550: b480 push {r7}
8001552: b085 sub sp, #20
8001554: af00 add r7, sp, #0
8001556: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8001558: 4b0a ldr r3, [pc, #40] @ (8001584 <RCC_Delay+0x34>)
800155a: 681b ldr r3, [r3, #0]
800155c: 4a0a ldr r2, [pc, #40] @ (8001588 <RCC_Delay+0x38>)
800155e: fba2 2303 umull r2, r3, r2, r3
8001562: 0a5b lsrs r3, r3, #9
8001564: 687a ldr r2, [r7, #4]
8001566: fb02 f303 mul.w r3, r2, r3
800156a: 60fb str r3, [r7, #12]
do
{
__NOP();
800156c: bf00 nop
}
while (Delay --);
800156e: 68fb ldr r3, [r7, #12]
8001570: 1e5a subs r2, r3, #1
8001572: 60fa str r2, [r7, #12]
8001574: 2b00 cmp r3, #0
8001576: d1f9 bne.n 800156c <RCC_Delay+0x1c>
}
8001578: bf00 nop
800157a: bf00 nop
800157c: 3714 adds r7, #20
800157e: 46bd mov sp, r7
8001580: bc80 pop {r7}
8001582: 4770 bx lr
8001584: 20000000 .word 0x20000000
8001588: 10624dd3 .word 0x10624dd3
0800158c <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
800158c: b580 push {r7, lr}
800158e: b082 sub sp, #8
8001590: af00 add r7, sp, #0
8001592: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001594: 687b ldr r3, [r7, #4]
8001596: 2b00 cmp r3, #0
8001598: d101 bne.n 800159e <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
800159a: 2301 movs r3, #1
800159c: e041 b.n 8001622 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800159e: 687b ldr r3, [r7, #4]
80015a0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80015a4: b2db uxtb r3, r3
80015a6: 2b00 cmp r3, #0
80015a8: d106 bne.n 80015b8 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80015aa: 687b ldr r3, [r7, #4]
80015ac: 2200 movs r2, #0
80015ae: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80015b2: 6878 ldr r0, [r7, #4]
80015b4: f7ff f834 bl 8000620 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80015b8: 687b ldr r3, [r7, #4]
80015ba: 2202 movs r2, #2
80015bc: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80015c0: 687b ldr r3, [r7, #4]
80015c2: 681a ldr r2, [r3, #0]
80015c4: 687b ldr r3, [r7, #4]
80015c6: 3304 adds r3, #4
80015c8: 4619 mov r1, r3
80015ca: 4610 mov r0, r2
80015cc: f000 fa10 bl 80019f0 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80015d0: 687b ldr r3, [r7, #4]
80015d2: 2201 movs r2, #1
80015d4: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80015d8: 687b ldr r3, [r7, #4]
80015da: 2201 movs r2, #1
80015dc: f883 203e strb.w r2, [r3, #62] @ 0x3e
80015e0: 687b ldr r3, [r7, #4]
80015e2: 2201 movs r2, #1
80015e4: f883 203f strb.w r2, [r3, #63] @ 0x3f
80015e8: 687b ldr r3, [r7, #4]
80015ea: 2201 movs r2, #1
80015ec: f883 2040 strb.w r2, [r3, #64] @ 0x40
80015f0: 687b ldr r3, [r7, #4]
80015f2: 2201 movs r2, #1
80015f4: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80015f8: 687b ldr r3, [r7, #4]
80015fa: 2201 movs r2, #1
80015fc: f883 2042 strb.w r2, [r3, #66] @ 0x42
8001600: 687b ldr r3, [r7, #4]
8001602: 2201 movs r2, #1
8001604: f883 2043 strb.w r2, [r3, #67] @ 0x43
8001608: 687b ldr r3, [r7, #4]
800160a: 2201 movs r2, #1
800160c: f883 2044 strb.w r2, [r3, #68] @ 0x44
8001610: 687b ldr r3, [r7, #4]
8001612: 2201 movs r2, #1
8001614: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001618: 687b ldr r3, [r7, #4]
800161a: 2201 movs r2, #1
800161c: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8001620: 2300 movs r3, #0
}
8001622: 4618 mov r0, r3
8001624: 3708 adds r7, #8
8001626: 46bd mov sp, r7
8001628: bd80 pop {r7, pc}
0800162a <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
800162a: b580 push {r7, lr}
800162c: b082 sub sp, #8
800162e: af00 add r7, sp, #0
8001630: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001632: 687b ldr r3, [r7, #4]
8001634: 2b00 cmp r3, #0
8001636: d101 bne.n 800163c <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8001638: 2301 movs r3, #1
800163a: e041 b.n 80016c0 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800163c: 687b ldr r3, [r7, #4]
800163e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8001642: b2db uxtb r3, r3
8001644: 2b00 cmp r3, #0
8001646: d106 bne.n 8001656 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001648: 687b ldr r3, [r7, #4]
800164a: 2200 movs r2, #0
800164c: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8001650: 6878 ldr r0, [r7, #4]
8001652: f000 f839 bl 80016c8 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001656: 687b ldr r3, [r7, #4]
8001658: 2202 movs r2, #2
800165a: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800165e: 687b ldr r3, [r7, #4]
8001660: 681a ldr r2, [r3, #0]
8001662: 687b ldr r3, [r7, #4]
8001664: 3304 adds r3, #4
8001666: 4619 mov r1, r3
8001668: 4610 mov r0, r2
800166a: f000 f9c1 bl 80019f0 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800166e: 687b ldr r3, [r7, #4]
8001670: 2201 movs r2, #1
8001672: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001676: 687b ldr r3, [r7, #4]
8001678: 2201 movs r2, #1
800167a: f883 203e strb.w r2, [r3, #62] @ 0x3e
800167e: 687b ldr r3, [r7, #4]
8001680: 2201 movs r2, #1
8001682: f883 203f strb.w r2, [r3, #63] @ 0x3f
8001686: 687b ldr r3, [r7, #4]
8001688: 2201 movs r2, #1
800168a: f883 2040 strb.w r2, [r3, #64] @ 0x40
800168e: 687b ldr r3, [r7, #4]
8001690: 2201 movs r2, #1
8001692: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001696: 687b ldr r3, [r7, #4]
8001698: 2201 movs r2, #1
800169a: f883 2042 strb.w r2, [r3, #66] @ 0x42
800169e: 687b ldr r3, [r7, #4]
80016a0: 2201 movs r2, #1
80016a2: f883 2043 strb.w r2, [r3, #67] @ 0x43
80016a6: 687b ldr r3, [r7, #4]
80016a8: 2201 movs r2, #1
80016aa: f883 2044 strb.w r2, [r3, #68] @ 0x44
80016ae: 687b ldr r3, [r7, #4]
80016b0: 2201 movs r2, #1
80016b2: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80016b6: 687b ldr r3, [r7, #4]
80016b8: 2201 movs r2, #1
80016ba: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
80016be: 2300 movs r3, #0
}
80016c0: 4618 mov r0, r3
80016c2: 3708 adds r7, #8
80016c4: 46bd mov sp, r7
80016c6: bd80 pop {r7, pc}
080016c8 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80016c8: b480 push {r7}
80016ca: b083 sub sp, #12
80016cc: af00 add r7, sp, #0
80016ce: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80016d0: bf00 nop
80016d2: 370c adds r7, #12
80016d4: 46bd mov sp, r7
80016d6: bc80 pop {r7}
80016d8: 4770 bx lr
...
080016dc <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80016dc: b580 push {r7, lr}
80016de: b086 sub sp, #24
80016e0: af00 add r7, sp, #0
80016e2: 60f8 str r0, [r7, #12]
80016e4: 60b9 str r1, [r7, #8]
80016e6: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80016e8: 2300 movs r3, #0
80016ea: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
80016ec: 68fb ldr r3, [r7, #12]
80016ee: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80016f2: 2b01 cmp r3, #1
80016f4: d101 bne.n 80016fa <HAL_TIM_PWM_ConfigChannel+0x1e>
80016f6: 2302 movs r3, #2
80016f8: e0ae b.n 8001858 <HAL_TIM_PWM_ConfigChannel+0x17c>
80016fa: 68fb ldr r3, [r7, #12]
80016fc: 2201 movs r2, #1
80016fe: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8001702: 687b ldr r3, [r7, #4]
8001704: 2b0c cmp r3, #12
8001706: f200 809f bhi.w 8001848 <HAL_TIM_PWM_ConfigChannel+0x16c>
800170a: a201 add r2, pc, #4 @ (adr r2, 8001710 <HAL_TIM_PWM_ConfigChannel+0x34>)
800170c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001710: 08001745 .word 0x08001745
8001714: 08001849 .word 0x08001849
8001718: 08001849 .word 0x08001849
800171c: 08001849 .word 0x08001849
8001720: 08001785 .word 0x08001785
8001724: 08001849 .word 0x08001849
8001728: 08001849 .word 0x08001849
800172c: 08001849 .word 0x08001849
8001730: 080017c7 .word 0x080017c7
8001734: 08001849 .word 0x08001849
8001738: 08001849 .word 0x08001849
800173c: 08001849 .word 0x08001849
8001740: 08001807 .word 0x08001807
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8001744: 68fb ldr r3, [r7, #12]
8001746: 681b ldr r3, [r3, #0]
8001748: 68b9 ldr r1, [r7, #8]
800174a: 4618 mov r0, r3
800174c: f000 f9be bl 8001acc <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8001750: 68fb ldr r3, [r7, #12]
8001752: 681b ldr r3, [r3, #0]
8001754: 699a ldr r2, [r3, #24]
8001756: 68fb ldr r3, [r7, #12]
8001758: 681b ldr r3, [r3, #0]
800175a: f042 0208 orr.w r2, r2, #8
800175e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8001760: 68fb ldr r3, [r7, #12]
8001762: 681b ldr r3, [r3, #0]
8001764: 699a ldr r2, [r3, #24]
8001766: 68fb ldr r3, [r7, #12]
8001768: 681b ldr r3, [r3, #0]
800176a: f022 0204 bic.w r2, r2, #4
800176e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8001770: 68fb ldr r3, [r7, #12]
8001772: 681b ldr r3, [r3, #0]
8001774: 6999 ldr r1, [r3, #24]
8001776: 68bb ldr r3, [r7, #8]
8001778: 691a ldr r2, [r3, #16]
800177a: 68fb ldr r3, [r7, #12]
800177c: 681b ldr r3, [r3, #0]
800177e: 430a orrs r2, r1
8001780: 619a str r2, [r3, #24]
break;
8001782: e064 b.n 800184e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8001784: 68fb ldr r3, [r7, #12]
8001786: 681b ldr r3, [r3, #0]
8001788: 68b9 ldr r1, [r7, #8]
800178a: 4618 mov r0, r3
800178c: f000 fa04 bl 8001b98 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8001790: 68fb ldr r3, [r7, #12]
8001792: 681b ldr r3, [r3, #0]
8001794: 699a ldr r2, [r3, #24]
8001796: 68fb ldr r3, [r7, #12]
8001798: 681b ldr r3, [r3, #0]
800179a: f442 6200 orr.w r2, r2, #2048 @ 0x800
800179e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80017a0: 68fb ldr r3, [r7, #12]
80017a2: 681b ldr r3, [r3, #0]
80017a4: 699a ldr r2, [r3, #24]
80017a6: 68fb ldr r3, [r7, #12]
80017a8: 681b ldr r3, [r3, #0]
80017aa: f422 6280 bic.w r2, r2, #1024 @ 0x400
80017ae: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80017b0: 68fb ldr r3, [r7, #12]
80017b2: 681b ldr r3, [r3, #0]
80017b4: 6999 ldr r1, [r3, #24]
80017b6: 68bb ldr r3, [r7, #8]
80017b8: 691b ldr r3, [r3, #16]
80017ba: 021a lsls r2, r3, #8
80017bc: 68fb ldr r3, [r7, #12]
80017be: 681b ldr r3, [r3, #0]
80017c0: 430a orrs r2, r1
80017c2: 619a str r2, [r3, #24]
break;
80017c4: e043 b.n 800184e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80017c6: 68fb ldr r3, [r7, #12]
80017c8: 681b ldr r3, [r3, #0]
80017ca: 68b9 ldr r1, [r7, #8]
80017cc: 4618 mov r0, r3
80017ce: f000 fa4d bl 8001c6c <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80017d2: 68fb ldr r3, [r7, #12]
80017d4: 681b ldr r3, [r3, #0]
80017d6: 69da ldr r2, [r3, #28]
80017d8: 68fb ldr r3, [r7, #12]
80017da: 681b ldr r3, [r3, #0]
80017dc: f042 0208 orr.w r2, r2, #8
80017e0: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80017e2: 68fb ldr r3, [r7, #12]
80017e4: 681b ldr r3, [r3, #0]
80017e6: 69da ldr r2, [r3, #28]
80017e8: 68fb ldr r3, [r7, #12]
80017ea: 681b ldr r3, [r3, #0]
80017ec: f022 0204 bic.w r2, r2, #4
80017f0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80017f2: 68fb ldr r3, [r7, #12]
80017f4: 681b ldr r3, [r3, #0]
80017f6: 69d9 ldr r1, [r3, #28]
80017f8: 68bb ldr r3, [r7, #8]
80017fa: 691a ldr r2, [r3, #16]
80017fc: 68fb ldr r3, [r7, #12]
80017fe: 681b ldr r3, [r3, #0]
8001800: 430a orrs r2, r1
8001802: 61da str r2, [r3, #28]
break;
8001804: e023 b.n 800184e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8001806: 68fb ldr r3, [r7, #12]
8001808: 681b ldr r3, [r3, #0]
800180a: 68b9 ldr r1, [r7, #8]
800180c: 4618 mov r0, r3
800180e: f000 fa97 bl 8001d40 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8001812: 68fb ldr r3, [r7, #12]
8001814: 681b ldr r3, [r3, #0]
8001816: 69da ldr r2, [r3, #28]
8001818: 68fb ldr r3, [r7, #12]
800181a: 681b ldr r3, [r3, #0]
800181c: f442 6200 orr.w r2, r2, #2048 @ 0x800
8001820: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8001822: 68fb ldr r3, [r7, #12]
8001824: 681b ldr r3, [r3, #0]
8001826: 69da ldr r2, [r3, #28]
8001828: 68fb ldr r3, [r7, #12]
800182a: 681b ldr r3, [r3, #0]
800182c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8001830: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8001832: 68fb ldr r3, [r7, #12]
8001834: 681b ldr r3, [r3, #0]
8001836: 69d9 ldr r1, [r3, #28]
8001838: 68bb ldr r3, [r7, #8]
800183a: 691b ldr r3, [r3, #16]
800183c: 021a lsls r2, r3, #8
800183e: 68fb ldr r3, [r7, #12]
8001840: 681b ldr r3, [r3, #0]
8001842: 430a orrs r2, r1
8001844: 61da str r2, [r3, #28]
break;
8001846: e002 b.n 800184e <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8001848: 2301 movs r3, #1
800184a: 75fb strb r3, [r7, #23]
break;
800184c: bf00 nop
}
__HAL_UNLOCK(htim);
800184e: 68fb ldr r3, [r7, #12]
8001850: 2200 movs r2, #0
8001852: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8001856: 7dfb ldrb r3, [r7, #23]
}
8001858: 4618 mov r0, r3
800185a: 3718 adds r7, #24
800185c: 46bd mov sp, r7
800185e: bd80 pop {r7, pc}
08001860 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8001860: b580 push {r7, lr}
8001862: b084 sub sp, #16
8001864: af00 add r7, sp, #0
8001866: 6078 str r0, [r7, #4]
8001868: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
800186a: 2300 movs r3, #0
800186c: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800186e: 687b ldr r3, [r7, #4]
8001870: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8001874: 2b01 cmp r3, #1
8001876: d101 bne.n 800187c <HAL_TIM_ConfigClockSource+0x1c>
8001878: 2302 movs r3, #2
800187a: e0b4 b.n 80019e6 <HAL_TIM_ConfigClockSource+0x186>
800187c: 687b ldr r3, [r7, #4]
800187e: 2201 movs r2, #1
8001880: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8001884: 687b ldr r3, [r7, #4]
8001886: 2202 movs r2, #2
8001888: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800188c: 687b ldr r3, [r7, #4]
800188e: 681b ldr r3, [r3, #0]
8001890: 689b ldr r3, [r3, #8]
8001892: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8001894: 68bb ldr r3, [r7, #8]
8001896: f023 0377 bic.w r3, r3, #119 @ 0x77
800189a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800189c: 68bb ldr r3, [r7, #8]
800189e: f423 437f bic.w r3, r3, #65280 @ 0xff00
80018a2: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80018a4: 687b ldr r3, [r7, #4]
80018a6: 681b ldr r3, [r3, #0]
80018a8: 68ba ldr r2, [r7, #8]
80018aa: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80018ac: 683b ldr r3, [r7, #0]
80018ae: 681b ldr r3, [r3, #0]
80018b0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80018b4: d03e beq.n 8001934 <HAL_TIM_ConfigClockSource+0xd4>
80018b6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80018ba: f200 8087 bhi.w 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018be: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80018c2: f000 8086 beq.w 80019d2 <HAL_TIM_ConfigClockSource+0x172>
80018c6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80018ca: d87f bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018cc: 2b70 cmp r3, #112 @ 0x70
80018ce: d01a beq.n 8001906 <HAL_TIM_ConfigClockSource+0xa6>
80018d0: 2b70 cmp r3, #112 @ 0x70
80018d2: d87b bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018d4: 2b60 cmp r3, #96 @ 0x60
80018d6: d050 beq.n 800197a <HAL_TIM_ConfigClockSource+0x11a>
80018d8: 2b60 cmp r3, #96 @ 0x60
80018da: d877 bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018dc: 2b50 cmp r3, #80 @ 0x50
80018de: d03c beq.n 800195a <HAL_TIM_ConfigClockSource+0xfa>
80018e0: 2b50 cmp r3, #80 @ 0x50
80018e2: d873 bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018e4: 2b40 cmp r3, #64 @ 0x40
80018e6: d058 beq.n 800199a <HAL_TIM_ConfigClockSource+0x13a>
80018e8: 2b40 cmp r3, #64 @ 0x40
80018ea: d86f bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018ec: 2b30 cmp r3, #48 @ 0x30
80018ee: d064 beq.n 80019ba <HAL_TIM_ConfigClockSource+0x15a>
80018f0: 2b30 cmp r3, #48 @ 0x30
80018f2: d86b bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018f4: 2b20 cmp r3, #32
80018f6: d060 beq.n 80019ba <HAL_TIM_ConfigClockSource+0x15a>
80018f8: 2b20 cmp r3, #32
80018fa: d867 bhi.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
80018fc: 2b00 cmp r3, #0
80018fe: d05c beq.n 80019ba <HAL_TIM_ConfigClockSource+0x15a>
8001900: 2b10 cmp r3, #16
8001902: d05a beq.n 80019ba <HAL_TIM_ConfigClockSource+0x15a>
8001904: e062 b.n 80019cc <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8001906: 687b ldr r3, [r7, #4]
8001908: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
800190a: 683b ldr r3, [r7, #0]
800190c: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800190e: 683b ldr r3, [r7, #0]
8001910: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8001912: 683b ldr r3, [r7, #0]
8001914: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8001916: f000 fad8 bl 8001eca <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800191a: 687b ldr r3, [r7, #4]
800191c: 681b ldr r3, [r3, #0]
800191e: 689b ldr r3, [r3, #8]
8001920: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8001922: 68bb ldr r3, [r7, #8]
8001924: f043 0377 orr.w r3, r3, #119 @ 0x77
8001928: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800192a: 687b ldr r3, [r7, #4]
800192c: 681b ldr r3, [r3, #0]
800192e: 68ba ldr r2, [r7, #8]
8001930: 609a str r2, [r3, #8]
break;
8001932: e04f b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8001934: 687b ldr r3, [r7, #4]
8001936: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8001938: 683b ldr r3, [r7, #0]
800193a: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800193c: 683b ldr r3, [r7, #0]
800193e: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8001940: 683b ldr r3, [r7, #0]
8001942: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8001944: f000 fac1 bl 8001eca <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8001948: 687b ldr r3, [r7, #4]
800194a: 681b ldr r3, [r3, #0]
800194c: 689a ldr r2, [r3, #8]
800194e: 687b ldr r3, [r7, #4]
8001950: 681b ldr r3, [r3, #0]
8001952: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8001956: 609a str r2, [r3, #8]
break;
8001958: e03c b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800195a: 687b ldr r3, [r7, #4]
800195c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800195e: 683b ldr r3, [r7, #0]
8001960: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8001962: 683b ldr r3, [r7, #0]
8001964: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8001966: 461a mov r2, r3
8001968: f000 fa38 bl 8001ddc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
800196c: 687b ldr r3, [r7, #4]
800196e: 681b ldr r3, [r3, #0]
8001970: 2150 movs r1, #80 @ 0x50
8001972: 4618 mov r0, r3
8001974: f000 fa8f bl 8001e96 <TIM_ITRx_SetConfig>
break;
8001978: e02c b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
800197a: 687b ldr r3, [r7, #4]
800197c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800197e: 683b ldr r3, [r7, #0]
8001980: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8001982: 683b ldr r3, [r7, #0]
8001984: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8001986: 461a mov r2, r3
8001988: f000 fa56 bl 8001e38 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800198c: 687b ldr r3, [r7, #4]
800198e: 681b ldr r3, [r3, #0]
8001990: 2160 movs r1, #96 @ 0x60
8001992: 4618 mov r0, r3
8001994: f000 fa7f bl 8001e96 <TIM_ITRx_SetConfig>
break;
8001998: e01c b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800199a: 687b ldr r3, [r7, #4]
800199c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800199e: 683b ldr r3, [r7, #0]
80019a0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80019a2: 683b ldr r3, [r7, #0]
80019a4: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80019a6: 461a mov r2, r3
80019a8: f000 fa18 bl 8001ddc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80019ac: 687b ldr r3, [r7, #4]
80019ae: 681b ldr r3, [r3, #0]
80019b0: 2140 movs r1, #64 @ 0x40
80019b2: 4618 mov r0, r3
80019b4: f000 fa6f bl 8001e96 <TIM_ITRx_SetConfig>
break;
80019b8: e00c b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80019ba: 687b ldr r3, [r7, #4]
80019bc: 681a ldr r2, [r3, #0]
80019be: 683b ldr r3, [r7, #0]
80019c0: 681b ldr r3, [r3, #0]
80019c2: 4619 mov r1, r3
80019c4: 4610 mov r0, r2
80019c6: f000 fa66 bl 8001e96 <TIM_ITRx_SetConfig>
break;
80019ca: e003 b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
80019cc: 2301 movs r3, #1
80019ce: 73fb strb r3, [r7, #15]
break;
80019d0: e000 b.n 80019d4 <HAL_TIM_ConfigClockSource+0x174>
break;
80019d2: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
80019d4: 687b ldr r3, [r7, #4]
80019d6: 2201 movs r2, #1
80019d8: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80019dc: 687b ldr r3, [r7, #4]
80019de: 2200 movs r2, #0
80019e0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80019e4: 7bfb ldrb r3, [r7, #15]
}
80019e6: 4618 mov r0, r3
80019e8: 3710 adds r7, #16
80019ea: 46bd mov sp, r7
80019ec: bd80 pop {r7, pc}
...
080019f0 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
80019f0: b480 push {r7}
80019f2: b085 sub sp, #20
80019f4: af00 add r7, sp, #0
80019f6: 6078 str r0, [r7, #4]
80019f8: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80019fa: 687b ldr r3, [r7, #4]
80019fc: 681b ldr r3, [r3, #0]
80019fe: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8001a00: 687b ldr r3, [r7, #4]
8001a02: 4a2f ldr r2, [pc, #188] @ (8001ac0 <TIM_Base_SetConfig+0xd0>)
8001a04: 4293 cmp r3, r2
8001a06: d00b beq.n 8001a20 <TIM_Base_SetConfig+0x30>
8001a08: 687b ldr r3, [r7, #4]
8001a0a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001a0e: d007 beq.n 8001a20 <TIM_Base_SetConfig+0x30>
8001a10: 687b ldr r3, [r7, #4]
8001a12: 4a2c ldr r2, [pc, #176] @ (8001ac4 <TIM_Base_SetConfig+0xd4>)
8001a14: 4293 cmp r3, r2
8001a16: d003 beq.n 8001a20 <TIM_Base_SetConfig+0x30>
8001a18: 687b ldr r3, [r7, #4]
8001a1a: 4a2b ldr r2, [pc, #172] @ (8001ac8 <TIM_Base_SetConfig+0xd8>)
8001a1c: 4293 cmp r3, r2
8001a1e: d108 bne.n 8001a32 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8001a20: 68fb ldr r3, [r7, #12]
8001a22: f023 0370 bic.w r3, r3, #112 @ 0x70
8001a26: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8001a28: 683b ldr r3, [r7, #0]
8001a2a: 685b ldr r3, [r3, #4]
8001a2c: 68fa ldr r2, [r7, #12]
8001a2e: 4313 orrs r3, r2
8001a30: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8001a32: 687b ldr r3, [r7, #4]
8001a34: 4a22 ldr r2, [pc, #136] @ (8001ac0 <TIM_Base_SetConfig+0xd0>)
8001a36: 4293 cmp r3, r2
8001a38: d00b beq.n 8001a52 <TIM_Base_SetConfig+0x62>
8001a3a: 687b ldr r3, [r7, #4]
8001a3c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001a40: d007 beq.n 8001a52 <TIM_Base_SetConfig+0x62>
8001a42: 687b ldr r3, [r7, #4]
8001a44: 4a1f ldr r2, [pc, #124] @ (8001ac4 <TIM_Base_SetConfig+0xd4>)
8001a46: 4293 cmp r3, r2
8001a48: d003 beq.n 8001a52 <TIM_Base_SetConfig+0x62>
8001a4a: 687b ldr r3, [r7, #4]
8001a4c: 4a1e ldr r2, [pc, #120] @ (8001ac8 <TIM_Base_SetConfig+0xd8>)
8001a4e: 4293 cmp r3, r2
8001a50: d108 bne.n 8001a64 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8001a52: 68fb ldr r3, [r7, #12]
8001a54: f423 7340 bic.w r3, r3, #768 @ 0x300
8001a58: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8001a5a: 683b ldr r3, [r7, #0]
8001a5c: 68db ldr r3, [r3, #12]
8001a5e: 68fa ldr r2, [r7, #12]
8001a60: 4313 orrs r3, r2
8001a62: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8001a64: 68fb ldr r3, [r7, #12]
8001a66: f023 0280 bic.w r2, r3, #128 @ 0x80
8001a6a: 683b ldr r3, [r7, #0]
8001a6c: 695b ldr r3, [r3, #20]
8001a6e: 4313 orrs r3, r2
8001a70: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8001a72: 687b ldr r3, [r7, #4]
8001a74: 68fa ldr r2, [r7, #12]
8001a76: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8001a78: 683b ldr r3, [r7, #0]
8001a7a: 689a ldr r2, [r3, #8]
8001a7c: 687b ldr r3, [r7, #4]
8001a7e: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8001a80: 683b ldr r3, [r7, #0]
8001a82: 681a ldr r2, [r3, #0]
8001a84: 687b ldr r3, [r7, #4]
8001a86: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 4a0d ldr r2, [pc, #52] @ (8001ac0 <TIM_Base_SetConfig+0xd0>)
8001a8c: 4293 cmp r3, r2
8001a8e: d103 bne.n 8001a98 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8001a90: 683b ldr r3, [r7, #0]
8001a92: 691a ldr r2, [r3, #16]
8001a94: 687b ldr r3, [r7, #4]
8001a96: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8001a98: 687b ldr r3, [r7, #4]
8001a9a: 2201 movs r2, #1
8001a9c: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8001a9e: 687b ldr r3, [r7, #4]
8001aa0: 691b ldr r3, [r3, #16]
8001aa2: f003 0301 and.w r3, r3, #1
8001aa6: 2b00 cmp r3, #0
8001aa8: d005 beq.n 8001ab6 <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8001aaa: 687b ldr r3, [r7, #4]
8001aac: 691b ldr r3, [r3, #16]
8001aae: f023 0201 bic.w r2, r3, #1
8001ab2: 687b ldr r3, [r7, #4]
8001ab4: 611a str r2, [r3, #16]
}
}
8001ab6: bf00 nop
8001ab8: 3714 adds r7, #20
8001aba: 46bd mov sp, r7
8001abc: bc80 pop {r7}
8001abe: 4770 bx lr
8001ac0: 40012c00 .word 0x40012c00
8001ac4: 40000400 .word 0x40000400
8001ac8: 40000800 .word 0x40000800
08001acc <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001acc: b480 push {r7}
8001ace: b087 sub sp, #28
8001ad0: af00 add r7, sp, #0
8001ad2: 6078 str r0, [r7, #4]
8001ad4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001ad6: 687b ldr r3, [r7, #4]
8001ad8: 6a1b ldr r3, [r3, #32]
8001ada: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8001adc: 687b ldr r3, [r7, #4]
8001ade: 6a1b ldr r3, [r3, #32]
8001ae0: f023 0201 bic.w r2, r3, #1
8001ae4: 687b ldr r3, [r7, #4]
8001ae6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001ae8: 687b ldr r3, [r7, #4]
8001aea: 685b ldr r3, [r3, #4]
8001aec: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001aee: 687b ldr r3, [r7, #4]
8001af0: 699b ldr r3, [r3, #24]
8001af2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8001af4: 68fb ldr r3, [r7, #12]
8001af6: f023 0370 bic.w r3, r3, #112 @ 0x70
8001afa: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8001afc: 68fb ldr r3, [r7, #12]
8001afe: f023 0303 bic.w r3, r3, #3
8001b02: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001b04: 683b ldr r3, [r7, #0]
8001b06: 681b ldr r3, [r3, #0]
8001b08: 68fa ldr r2, [r7, #12]
8001b0a: 4313 orrs r3, r2
8001b0c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8001b0e: 697b ldr r3, [r7, #20]
8001b10: f023 0302 bic.w r3, r3, #2
8001b14: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8001b16: 683b ldr r3, [r7, #0]
8001b18: 689b ldr r3, [r3, #8]
8001b1a: 697a ldr r2, [r7, #20]
8001b1c: 4313 orrs r3, r2
8001b1e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8001b20: 687b ldr r3, [r7, #4]
8001b22: 4a1c ldr r2, [pc, #112] @ (8001b94 <TIM_OC1_SetConfig+0xc8>)
8001b24: 4293 cmp r3, r2
8001b26: d10c bne.n 8001b42 <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8001b28: 697b ldr r3, [r7, #20]
8001b2a: f023 0308 bic.w r3, r3, #8
8001b2e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8001b30: 683b ldr r3, [r7, #0]
8001b32: 68db ldr r3, [r3, #12]
8001b34: 697a ldr r2, [r7, #20]
8001b36: 4313 orrs r3, r2
8001b38: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8001b3a: 697b ldr r3, [r7, #20]
8001b3c: f023 0304 bic.w r3, r3, #4
8001b40: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001b42: 687b ldr r3, [r7, #4]
8001b44: 4a13 ldr r2, [pc, #76] @ (8001b94 <TIM_OC1_SetConfig+0xc8>)
8001b46: 4293 cmp r3, r2
8001b48: d111 bne.n 8001b6e <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8001b4a: 693b ldr r3, [r7, #16]
8001b4c: f423 7380 bic.w r3, r3, #256 @ 0x100
8001b50: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8001b52: 693b ldr r3, [r7, #16]
8001b54: f423 7300 bic.w r3, r3, #512 @ 0x200
8001b58: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8001b5a: 683b ldr r3, [r7, #0]
8001b5c: 695b ldr r3, [r3, #20]
8001b5e: 693a ldr r2, [r7, #16]
8001b60: 4313 orrs r3, r2
8001b62: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8001b64: 683b ldr r3, [r7, #0]
8001b66: 699b ldr r3, [r3, #24]
8001b68: 693a ldr r2, [r7, #16]
8001b6a: 4313 orrs r3, r2
8001b6c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001b6e: 687b ldr r3, [r7, #4]
8001b70: 693a ldr r2, [r7, #16]
8001b72: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001b74: 687b ldr r3, [r7, #4]
8001b76: 68fa ldr r2, [r7, #12]
8001b78: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8001b7a: 683b ldr r3, [r7, #0]
8001b7c: 685a ldr r2, [r3, #4]
8001b7e: 687b ldr r3, [r7, #4]
8001b80: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001b82: 687b ldr r3, [r7, #4]
8001b84: 697a ldr r2, [r7, #20]
8001b86: 621a str r2, [r3, #32]
}
8001b88: bf00 nop
8001b8a: 371c adds r7, #28
8001b8c: 46bd mov sp, r7
8001b8e: bc80 pop {r7}
8001b90: 4770 bx lr
8001b92: bf00 nop
8001b94: 40012c00 .word 0x40012c00
08001b98 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001b98: b480 push {r7}
8001b9a: b087 sub sp, #28
8001b9c: af00 add r7, sp, #0
8001b9e: 6078 str r0, [r7, #4]
8001ba0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001ba2: 687b ldr r3, [r7, #4]
8001ba4: 6a1b ldr r3, [r3, #32]
8001ba6: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 6a1b ldr r3, [r3, #32]
8001bac: f023 0210 bic.w r2, r3, #16
8001bb0: 687b ldr r3, [r7, #4]
8001bb2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001bb4: 687b ldr r3, [r7, #4]
8001bb6: 685b ldr r3, [r3, #4]
8001bb8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001bba: 687b ldr r3, [r7, #4]
8001bbc: 699b ldr r3, [r3, #24]
8001bbe: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8001bc0: 68fb ldr r3, [r7, #12]
8001bc2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8001bc6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8001bc8: 68fb ldr r3, [r7, #12]
8001bca: f423 7340 bic.w r3, r3, #768 @ 0x300
8001bce: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001bd0: 683b ldr r3, [r7, #0]
8001bd2: 681b ldr r3, [r3, #0]
8001bd4: 021b lsls r3, r3, #8
8001bd6: 68fa ldr r2, [r7, #12]
8001bd8: 4313 orrs r3, r2
8001bda: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8001bdc: 697b ldr r3, [r7, #20]
8001bde: f023 0320 bic.w r3, r3, #32
8001be2: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8001be4: 683b ldr r3, [r7, #0]
8001be6: 689b ldr r3, [r3, #8]
8001be8: 011b lsls r3, r3, #4
8001bea: 697a ldr r2, [r7, #20]
8001bec: 4313 orrs r3, r2
8001bee: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8001bf0: 687b ldr r3, [r7, #4]
8001bf2: 4a1d ldr r2, [pc, #116] @ (8001c68 <TIM_OC2_SetConfig+0xd0>)
8001bf4: 4293 cmp r3, r2
8001bf6: d10d bne.n 8001c14 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8001bf8: 697b ldr r3, [r7, #20]
8001bfa: f023 0380 bic.w r3, r3, #128 @ 0x80
8001bfe: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8001c00: 683b ldr r3, [r7, #0]
8001c02: 68db ldr r3, [r3, #12]
8001c04: 011b lsls r3, r3, #4
8001c06: 697a ldr r2, [r7, #20]
8001c08: 4313 orrs r3, r2
8001c0a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8001c0c: 697b ldr r3, [r7, #20]
8001c0e: f023 0340 bic.w r3, r3, #64 @ 0x40
8001c12: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001c14: 687b ldr r3, [r7, #4]
8001c16: 4a14 ldr r2, [pc, #80] @ (8001c68 <TIM_OC2_SetConfig+0xd0>)
8001c18: 4293 cmp r3, r2
8001c1a: d113 bne.n 8001c44 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8001c1c: 693b ldr r3, [r7, #16]
8001c1e: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001c22: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8001c24: 693b ldr r3, [r7, #16]
8001c26: f423 6300 bic.w r3, r3, #2048 @ 0x800
8001c2a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8001c2c: 683b ldr r3, [r7, #0]
8001c2e: 695b ldr r3, [r3, #20]
8001c30: 009b lsls r3, r3, #2
8001c32: 693a ldr r2, [r7, #16]
8001c34: 4313 orrs r3, r2
8001c36: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8001c38: 683b ldr r3, [r7, #0]
8001c3a: 699b ldr r3, [r3, #24]
8001c3c: 009b lsls r3, r3, #2
8001c3e: 693a ldr r2, [r7, #16]
8001c40: 4313 orrs r3, r2
8001c42: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001c44: 687b ldr r3, [r7, #4]
8001c46: 693a ldr r2, [r7, #16]
8001c48: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001c4a: 687b ldr r3, [r7, #4]
8001c4c: 68fa ldr r2, [r7, #12]
8001c4e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8001c50: 683b ldr r3, [r7, #0]
8001c52: 685a ldr r2, [r3, #4]
8001c54: 687b ldr r3, [r7, #4]
8001c56: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001c58: 687b ldr r3, [r7, #4]
8001c5a: 697a ldr r2, [r7, #20]
8001c5c: 621a str r2, [r3, #32]
}
8001c5e: bf00 nop
8001c60: 371c adds r7, #28
8001c62: 46bd mov sp, r7
8001c64: bc80 pop {r7}
8001c66: 4770 bx lr
8001c68: 40012c00 .word 0x40012c00
08001c6c <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001c6c: b480 push {r7}
8001c6e: b087 sub sp, #28
8001c70: af00 add r7, sp, #0
8001c72: 6078 str r0, [r7, #4]
8001c74: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001c76: 687b ldr r3, [r7, #4]
8001c78: 6a1b ldr r3, [r3, #32]
8001c7a: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 6a1b ldr r3, [r3, #32]
8001c80: f423 7280 bic.w r2, r3, #256 @ 0x100
8001c84: 687b ldr r3, [r7, #4]
8001c86: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001c88: 687b ldr r3, [r7, #4]
8001c8a: 685b ldr r3, [r3, #4]
8001c8c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 69db ldr r3, [r3, #28]
8001c92: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8001c94: 68fb ldr r3, [r7, #12]
8001c96: f023 0370 bic.w r3, r3, #112 @ 0x70
8001c9a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8001c9c: 68fb ldr r3, [r7, #12]
8001c9e: f023 0303 bic.w r3, r3, #3
8001ca2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001ca4: 683b ldr r3, [r7, #0]
8001ca6: 681b ldr r3, [r3, #0]
8001ca8: 68fa ldr r2, [r7, #12]
8001caa: 4313 orrs r3, r2
8001cac: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8001cae: 697b ldr r3, [r7, #20]
8001cb0: f423 7300 bic.w r3, r3, #512 @ 0x200
8001cb4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8001cb6: 683b ldr r3, [r7, #0]
8001cb8: 689b ldr r3, [r3, #8]
8001cba: 021b lsls r3, r3, #8
8001cbc: 697a ldr r2, [r7, #20]
8001cbe: 4313 orrs r3, r2
8001cc0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8001cc2: 687b ldr r3, [r7, #4]
8001cc4: 4a1d ldr r2, [pc, #116] @ (8001d3c <TIM_OC3_SetConfig+0xd0>)
8001cc6: 4293 cmp r3, r2
8001cc8: d10d bne.n 8001ce6 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8001cca: 697b ldr r3, [r7, #20]
8001ccc: f423 6300 bic.w r3, r3, #2048 @ 0x800
8001cd0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8001cd2: 683b ldr r3, [r7, #0]
8001cd4: 68db ldr r3, [r3, #12]
8001cd6: 021b lsls r3, r3, #8
8001cd8: 697a ldr r2, [r7, #20]
8001cda: 4313 orrs r3, r2
8001cdc: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8001cde: 697b ldr r3, [r7, #20]
8001ce0: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001ce4: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001ce6: 687b ldr r3, [r7, #4]
8001ce8: 4a14 ldr r2, [pc, #80] @ (8001d3c <TIM_OC3_SetConfig+0xd0>)
8001cea: 4293 cmp r3, r2
8001cec: d113 bne.n 8001d16 <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8001cee: 693b ldr r3, [r7, #16]
8001cf0: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8001cf4: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8001cf6: 693b ldr r3, [r7, #16]
8001cf8: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8001cfc: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8001cfe: 683b ldr r3, [r7, #0]
8001d00: 695b ldr r3, [r3, #20]
8001d02: 011b lsls r3, r3, #4
8001d04: 693a ldr r2, [r7, #16]
8001d06: 4313 orrs r3, r2
8001d08: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8001d0a: 683b ldr r3, [r7, #0]
8001d0c: 699b ldr r3, [r3, #24]
8001d0e: 011b lsls r3, r3, #4
8001d10: 693a ldr r2, [r7, #16]
8001d12: 4313 orrs r3, r2
8001d14: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001d16: 687b ldr r3, [r7, #4]
8001d18: 693a ldr r2, [r7, #16]
8001d1a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001d1c: 687b ldr r3, [r7, #4]
8001d1e: 68fa ldr r2, [r7, #12]
8001d20: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8001d22: 683b ldr r3, [r7, #0]
8001d24: 685a ldr r2, [r3, #4]
8001d26: 687b ldr r3, [r7, #4]
8001d28: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001d2a: 687b ldr r3, [r7, #4]
8001d2c: 697a ldr r2, [r7, #20]
8001d2e: 621a str r2, [r3, #32]
}
8001d30: bf00 nop
8001d32: 371c adds r7, #28
8001d34: 46bd mov sp, r7
8001d36: bc80 pop {r7}
8001d38: 4770 bx lr
8001d3a: bf00 nop
8001d3c: 40012c00 .word 0x40012c00
08001d40 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001d40: b480 push {r7}
8001d42: b087 sub sp, #28
8001d44: af00 add r7, sp, #0
8001d46: 6078 str r0, [r7, #4]
8001d48: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 6a1b ldr r3, [r3, #32]
8001d4e: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8001d50: 687b ldr r3, [r7, #4]
8001d52: 6a1b ldr r3, [r3, #32]
8001d54: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8001d58: 687b ldr r3, [r7, #4]
8001d5a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 685b ldr r3, [r3, #4]
8001d60: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001d62: 687b ldr r3, [r7, #4]
8001d64: 69db ldr r3, [r3, #28]
8001d66: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8001d68: 68fb ldr r3, [r7, #12]
8001d6a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8001d6e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8001d70: 68fb ldr r3, [r7, #12]
8001d72: f423 7340 bic.w r3, r3, #768 @ 0x300
8001d76: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001d78: 683b ldr r3, [r7, #0]
8001d7a: 681b ldr r3, [r3, #0]
8001d7c: 021b lsls r3, r3, #8
8001d7e: 68fa ldr r2, [r7, #12]
8001d80: 4313 orrs r3, r2
8001d82: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8001d84: 693b ldr r3, [r7, #16]
8001d86: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8001d8a: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8001d8c: 683b ldr r3, [r7, #0]
8001d8e: 689b ldr r3, [r3, #8]
8001d90: 031b lsls r3, r3, #12
8001d92: 693a ldr r2, [r7, #16]
8001d94: 4313 orrs r3, r2
8001d96: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001d98: 687b ldr r3, [r7, #4]
8001d9a: 4a0f ldr r2, [pc, #60] @ (8001dd8 <TIM_OC4_SetConfig+0x98>)
8001d9c: 4293 cmp r3, r2
8001d9e: d109 bne.n 8001db4 <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8001da0: 697b ldr r3, [r7, #20]
8001da2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8001da6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8001da8: 683b ldr r3, [r7, #0]
8001daa: 695b ldr r3, [r3, #20]
8001dac: 019b lsls r3, r3, #6
8001dae: 697a ldr r2, [r7, #20]
8001db0: 4313 orrs r3, r2
8001db2: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001db4: 687b ldr r3, [r7, #4]
8001db6: 697a ldr r2, [r7, #20]
8001db8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001dba: 687b ldr r3, [r7, #4]
8001dbc: 68fa ldr r2, [r7, #12]
8001dbe: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8001dc0: 683b ldr r3, [r7, #0]
8001dc2: 685a ldr r2, [r3, #4]
8001dc4: 687b ldr r3, [r7, #4]
8001dc6: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001dc8: 687b ldr r3, [r7, #4]
8001dca: 693a ldr r2, [r7, #16]
8001dcc: 621a str r2, [r3, #32]
}
8001dce: bf00 nop
8001dd0: 371c adds r7, #28
8001dd2: 46bd mov sp, r7
8001dd4: bc80 pop {r7}
8001dd6: 4770 bx lr
8001dd8: 40012c00 .word 0x40012c00
08001ddc <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8001ddc: b480 push {r7}
8001dde: b087 sub sp, #28
8001de0: af00 add r7, sp, #0
8001de2: 60f8 str r0, [r7, #12]
8001de4: 60b9 str r1, [r7, #8]
8001de6: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8001de8: 68fb ldr r3, [r7, #12]
8001dea: 6a1b ldr r3, [r3, #32]
8001dec: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8001dee: 68fb ldr r3, [r7, #12]
8001df0: 6a1b ldr r3, [r3, #32]
8001df2: f023 0201 bic.w r2, r3, #1
8001df6: 68fb ldr r3, [r7, #12]
8001df8: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8001dfa: 68fb ldr r3, [r7, #12]
8001dfc: 699b ldr r3, [r3, #24]
8001dfe: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8001e00: 693b ldr r3, [r7, #16]
8001e02: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8001e06: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8001e08: 687b ldr r3, [r7, #4]
8001e0a: 011b lsls r3, r3, #4
8001e0c: 693a ldr r2, [r7, #16]
8001e0e: 4313 orrs r3, r2
8001e10: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8001e12: 697b ldr r3, [r7, #20]
8001e14: f023 030a bic.w r3, r3, #10
8001e18: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8001e1a: 697a ldr r2, [r7, #20]
8001e1c: 68bb ldr r3, [r7, #8]
8001e1e: 4313 orrs r3, r2
8001e20: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8001e22: 68fb ldr r3, [r7, #12]
8001e24: 693a ldr r2, [r7, #16]
8001e26: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8001e28: 68fb ldr r3, [r7, #12]
8001e2a: 697a ldr r2, [r7, #20]
8001e2c: 621a str r2, [r3, #32]
}
8001e2e: bf00 nop
8001e30: 371c adds r7, #28
8001e32: 46bd mov sp, r7
8001e34: bc80 pop {r7}
8001e36: 4770 bx lr
08001e38 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8001e38: b480 push {r7}
8001e3a: b087 sub sp, #28
8001e3c: af00 add r7, sp, #0
8001e3e: 60f8 str r0, [r7, #12]
8001e40: 60b9 str r1, [r7, #8]
8001e42: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8001e44: 68fb ldr r3, [r7, #12]
8001e46: 6a1b ldr r3, [r3, #32]
8001e48: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8001e4a: 68fb ldr r3, [r7, #12]
8001e4c: 6a1b ldr r3, [r3, #32]
8001e4e: f023 0210 bic.w r2, r3, #16
8001e52: 68fb ldr r3, [r7, #12]
8001e54: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8001e56: 68fb ldr r3, [r7, #12]
8001e58: 699b ldr r3, [r3, #24]
8001e5a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8001e5c: 693b ldr r3, [r7, #16]
8001e5e: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8001e62: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8001e64: 687b ldr r3, [r7, #4]
8001e66: 031b lsls r3, r3, #12
8001e68: 693a ldr r2, [r7, #16]
8001e6a: 4313 orrs r3, r2
8001e6c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8001e6e: 697b ldr r3, [r7, #20]
8001e70: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8001e74: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8001e76: 68bb ldr r3, [r7, #8]
8001e78: 011b lsls r3, r3, #4
8001e7a: 697a ldr r2, [r7, #20]
8001e7c: 4313 orrs r3, r2
8001e7e: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8001e80: 68fb ldr r3, [r7, #12]
8001e82: 693a ldr r2, [r7, #16]
8001e84: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8001e86: 68fb ldr r3, [r7, #12]
8001e88: 697a ldr r2, [r7, #20]
8001e8a: 621a str r2, [r3, #32]
}
8001e8c: bf00 nop
8001e8e: 371c adds r7, #28
8001e90: 46bd mov sp, r7
8001e92: bc80 pop {r7}
8001e94: 4770 bx lr
08001e96 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8001e96: b480 push {r7}
8001e98: b085 sub sp, #20
8001e9a: af00 add r7, sp, #0
8001e9c: 6078 str r0, [r7, #4]
8001e9e: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8001ea0: 687b ldr r3, [r7, #4]
8001ea2: 689b ldr r3, [r3, #8]
8001ea4: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8001ea6: 68fb ldr r3, [r7, #12]
8001ea8: f023 0370 bic.w r3, r3, #112 @ 0x70
8001eac: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8001eae: 683a ldr r2, [r7, #0]
8001eb0: 68fb ldr r3, [r7, #12]
8001eb2: 4313 orrs r3, r2
8001eb4: f043 0307 orr.w r3, r3, #7
8001eb8: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8001eba: 687b ldr r3, [r7, #4]
8001ebc: 68fa ldr r2, [r7, #12]
8001ebe: 609a str r2, [r3, #8]
}
8001ec0: bf00 nop
8001ec2: 3714 adds r7, #20
8001ec4: 46bd mov sp, r7
8001ec6: bc80 pop {r7}
8001ec8: 4770 bx lr
08001eca <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8001eca: b480 push {r7}
8001ecc: b087 sub sp, #28
8001ece: af00 add r7, sp, #0
8001ed0: 60f8 str r0, [r7, #12]
8001ed2: 60b9 str r1, [r7, #8]
8001ed4: 607a str r2, [r7, #4]
8001ed6: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8001ed8: 68fb ldr r3, [r7, #12]
8001eda: 689b ldr r3, [r3, #8]
8001edc: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8001ede: 697b ldr r3, [r7, #20]
8001ee0: f423 437f bic.w r3, r3, #65280 @ 0xff00
8001ee4: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8001ee6: 683b ldr r3, [r7, #0]
8001ee8: 021a lsls r2, r3, #8
8001eea: 687b ldr r3, [r7, #4]
8001eec: 431a orrs r2, r3
8001eee: 68bb ldr r3, [r7, #8]
8001ef0: 4313 orrs r3, r2
8001ef2: 697a ldr r2, [r7, #20]
8001ef4: 4313 orrs r3, r2
8001ef6: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8001ef8: 68fb ldr r3, [r7, #12]
8001efa: 697a ldr r2, [r7, #20]
8001efc: 609a str r2, [r3, #8]
}
8001efe: bf00 nop
8001f00: 371c adds r7, #28
8001f02: 46bd mov sp, r7
8001f04: bc80 pop {r7}
8001f06: 4770 bx lr
08001f08 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8001f08: b480 push {r7}
8001f0a: b085 sub sp, #20
8001f0c: af00 add r7, sp, #0
8001f0e: 6078 str r0, [r7, #4]
8001f10: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8001f12: 687b ldr r3, [r7, #4]
8001f14: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8001f18: 2b01 cmp r3, #1
8001f1a: d101 bne.n 8001f20 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8001f1c: 2302 movs r3, #2
8001f1e: e046 b.n 8001fae <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8001f20: 687b ldr r3, [r7, #4]
8001f22: 2201 movs r2, #1
8001f24: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 2202 movs r2, #2
8001f2c: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8001f30: 687b ldr r3, [r7, #4]
8001f32: 681b ldr r3, [r3, #0]
8001f34: 685b ldr r3, [r3, #4]
8001f36: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8001f38: 687b ldr r3, [r7, #4]
8001f3a: 681b ldr r3, [r3, #0]
8001f3c: 689b ldr r3, [r3, #8]
8001f3e: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8001f40: 68fb ldr r3, [r7, #12]
8001f42: f023 0370 bic.w r3, r3, #112 @ 0x70
8001f46: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8001f48: 683b ldr r3, [r7, #0]
8001f4a: 681b ldr r3, [r3, #0]
8001f4c: 68fa ldr r2, [r7, #12]
8001f4e: 4313 orrs r3, r2
8001f50: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8001f52: 687b ldr r3, [r7, #4]
8001f54: 681b ldr r3, [r3, #0]
8001f56: 68fa ldr r2, [r7, #12]
8001f58: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 681b ldr r3, [r3, #0]
8001f5e: 4a16 ldr r2, [pc, #88] @ (8001fb8 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8001f60: 4293 cmp r3, r2
8001f62: d00e beq.n 8001f82 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001f64: 687b ldr r3, [r7, #4]
8001f66: 681b ldr r3, [r3, #0]
8001f68: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001f6c: d009 beq.n 8001f82 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001f6e: 687b ldr r3, [r7, #4]
8001f70: 681b ldr r3, [r3, #0]
8001f72: 4a12 ldr r2, [pc, #72] @ (8001fbc <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8001f74: 4293 cmp r3, r2
8001f76: d004 beq.n 8001f82 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001f78: 687b ldr r3, [r7, #4]
8001f7a: 681b ldr r3, [r3, #0]
8001f7c: 4a10 ldr r2, [pc, #64] @ (8001fc0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8001f7e: 4293 cmp r3, r2
8001f80: d10c bne.n 8001f9c <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8001f82: 68bb ldr r3, [r7, #8]
8001f84: f023 0380 bic.w r3, r3, #128 @ 0x80
8001f88: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8001f8a: 683b ldr r3, [r7, #0]
8001f8c: 685b ldr r3, [r3, #4]
8001f8e: 68ba ldr r2, [r7, #8]
8001f90: 4313 orrs r3, r2
8001f92: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8001f94: 687b ldr r3, [r7, #4]
8001f96: 681b ldr r3, [r3, #0]
8001f98: 68ba ldr r2, [r7, #8]
8001f9a: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8001f9c: 687b ldr r3, [r7, #4]
8001f9e: 2201 movs r2, #1
8001fa0: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 2200 movs r2, #0
8001fa8: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8001fac: 2300 movs r3, #0
}
8001fae: 4618 mov r0, r3
8001fb0: 3714 adds r7, #20
8001fb2: 46bd mov sp, r7
8001fb4: bc80 pop {r7}
8001fb6: 4770 bx lr
8001fb8: 40012c00 .word 0x40012c00
8001fbc: 40000400 .word 0x40000400
8001fc0: 40000800 .word 0x40000800
08001fc4 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8001fc4: b480 push {r7}
8001fc6: b085 sub sp, #20
8001fc8: af00 add r7, sp, #0
8001fca: 6078 str r0, [r7, #4]
8001fcc: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8001fce: 2300 movs r3, #0
8001fd0: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8001fd8: 2b01 cmp r3, #1
8001fda: d101 bne.n 8001fe0 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8001fdc: 2302 movs r3, #2
8001fde: e03d b.n 800205c <HAL_TIMEx_ConfigBreakDeadTime+0x98>
8001fe0: 687b ldr r3, [r7, #4]
8001fe2: 2201 movs r2, #1
8001fe4: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8001fe8: 68fb ldr r3, [r7, #12]
8001fea: f023 02ff bic.w r2, r3, #255 @ 0xff
8001fee: 683b ldr r3, [r7, #0]
8001ff0: 68db ldr r3, [r3, #12]
8001ff2: 4313 orrs r3, r2
8001ff4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8001ff6: 68fb ldr r3, [r7, #12]
8001ff8: f423 7240 bic.w r2, r3, #768 @ 0x300
8001ffc: 683b ldr r3, [r7, #0]
8001ffe: 689b ldr r3, [r3, #8]
8002000: 4313 orrs r3, r2
8002002: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8002004: 68fb ldr r3, [r7, #12]
8002006: f423 6280 bic.w r2, r3, #1024 @ 0x400
800200a: 683b ldr r3, [r7, #0]
800200c: 685b ldr r3, [r3, #4]
800200e: 4313 orrs r3, r2
8002010: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8002012: 68fb ldr r3, [r7, #12]
8002014: f423 6200 bic.w r2, r3, #2048 @ 0x800
8002018: 683b ldr r3, [r7, #0]
800201a: 681b ldr r3, [r3, #0]
800201c: 4313 orrs r3, r2
800201e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8002020: 68fb ldr r3, [r7, #12]
8002022: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8002026: 683b ldr r3, [r7, #0]
8002028: 691b ldr r3, [r3, #16]
800202a: 4313 orrs r3, r2
800202c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
800202e: 68fb ldr r3, [r7, #12]
8002030: f423 5200 bic.w r2, r3, #8192 @ 0x2000
8002034: 683b ldr r3, [r7, #0]
8002036: 695b ldr r3, [r3, #20]
8002038: 4313 orrs r3, r2
800203a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
800203c: 68fb ldr r3, [r7, #12]
800203e: f423 4280 bic.w r2, r3, #16384 @ 0x4000
8002042: 683b ldr r3, [r7, #0]
8002044: 69db ldr r3, [r3, #28]
8002046: 4313 orrs r3, r2
8002048: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
800204a: 687b ldr r3, [r7, #4]
800204c: 681b ldr r3, [r3, #0]
800204e: 68fa ldr r2, [r7, #12]
8002050: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
8002052: 687b ldr r3, [r7, #4]
8002054: 2200 movs r2, #0
8002056: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
800205a: 2300 movs r3, #0
}
800205c: 4618 mov r0, r3
800205e: 3714 adds r7, #20
8002060: 46bd mov sp, r7
8002062: bc80 pop {r7}
8002064: 4770 bx lr
08002066 <memset>:
8002066: 4603 mov r3, r0
8002068: 4402 add r2, r0
800206a: 4293 cmp r3, r2
800206c: d100 bne.n 8002070 <memset+0xa>
800206e: 4770 bx lr
8002070: f803 1b01 strb.w r1, [r3], #1
8002074: e7f9 b.n 800206a <memset+0x4>
...
08002078 <__libc_init_array>:
8002078: b570 push {r4, r5, r6, lr}
800207a: 2600 movs r6, #0
800207c: 4d0c ldr r5, [pc, #48] @ (80020b0 <__libc_init_array+0x38>)
800207e: 4c0d ldr r4, [pc, #52] @ (80020b4 <__libc_init_array+0x3c>)
8002080: 1b64 subs r4, r4, r5
8002082: 10a4 asrs r4, r4, #2
8002084: 42a6 cmp r6, r4
8002086: d109 bne.n 800209c <__libc_init_array+0x24>
8002088: f000 f81a bl 80020c0 <_init>
800208c: 2600 movs r6, #0
800208e: 4d0a ldr r5, [pc, #40] @ (80020b8 <__libc_init_array+0x40>)
8002090: 4c0a ldr r4, [pc, #40] @ (80020bc <__libc_init_array+0x44>)
8002092: 1b64 subs r4, r4, r5
8002094: 10a4 asrs r4, r4, #2
8002096: 42a6 cmp r6, r4
8002098: d105 bne.n 80020a6 <__libc_init_array+0x2e>
800209a: bd70 pop {r4, r5, r6, pc}
800209c: f855 3b04 ldr.w r3, [r5], #4
80020a0: 4798 blx r3
80020a2: 3601 adds r6, #1
80020a4: e7ee b.n 8002084 <__libc_init_array+0xc>
80020a6: f855 3b04 ldr.w r3, [r5], #4
80020aa: 4798 blx r3
80020ac: 3601 adds r6, #1
80020ae: e7f2 b.n 8002096 <__libc_init_array+0x1e>
80020b0: 080020fc .word 0x080020fc
80020b4: 080020fc .word 0x080020fc
80020b8: 080020fc .word 0x080020fc
80020bc: 08002100 .word 0x08002100
080020c0 <_init>:
80020c0: b5f8 push {r3, r4, r5, r6, r7, lr}
80020c2: bf00 nop
80020c4: bcf8 pop {r3, r4, r5, r6, r7}
80020c6: bc08 pop {r3}
80020c8: 469e mov lr, r3
80020ca: 4770 bx lr
080020cc <_fini>:
80020cc: b5f8 push {r3, r4, r5, r6, r7, lr}
80020ce: bf00 nop
80020d0: bcf8 pop {r3, r4, r5, r6, r7}
80020d2: bc08 pop {r3}
80020d4: 469e mov lr, r3
80020d6: 4770 bx lr
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