: /** * @brief The application entry point. * @retval int */ int main(void) { 800014c: b580 push {r7, lr} 800014e: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000150: f000 fb74 bl 800083c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000154: f000 f80a bl 800016c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000158: f000 fa14 bl 8000584 MX_TIM1_Init(); 800015c: f000 f842 bl 80001e4 MX_TIM2_Init(); 8000160: f000 f904 bl 800036c MX_TIM3_Init(); 8000164: f000 f998 bl 8000498 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000168: bf00 nop 800016a: e7fd b.n 8000168 0800016c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800016c: b580 push {r7, lr} 800016e: b090 sub sp, #64 @ 0x40 8000170: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000172: f107 0318 add.w r3, r7, #24 8000176: 2228 movs r2, #40 @ 0x28 8000178: 2100 movs r1, #0 800017a: 4618 mov r0, r3 800017c: f001 ff73 bl 8002066 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000180: 1d3b adds r3, r7, #4 8000182: 2200 movs r2, #0 8000184: 601a str r2, [r3, #0] 8000186: 605a str r2, [r3, #4] 8000188: 609a str r2, [r3, #8] 800018a: 60da str r2, [r3, #12] 800018c: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800018e: 2302 movs r3, #2 8000190: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000192: 2301 movs r3, #1 8000194: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000196: 2310 movs r3, #16 8000198: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 800019a: 2300 movs r3, #0 800019c: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800019e: f107 0318 add.w r3, r7, #24 80001a2: 4618 mov r0, r3 80001a4: f000 fe14 bl 8000dd0 80001a8: 4603 mov r3, r0 80001aa: 2b00 cmp r3, #0 80001ac: d001 beq.n 80001b2 { Error_Handler(); 80001ae: f000 f9ff bl 80005b0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80001b2: 230f movs r3, #15 80001b4: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 80001b6: 2300 movs r3, #0 80001b8: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80001ba: 2300 movs r3, #0 80001bc: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80001be: 2300 movs r3, #0 80001c0: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80001c2: 2300 movs r3, #0 80001c4: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80001c6: 1d3b adds r3, r7, #4 80001c8: 2100 movs r1, #0 80001ca: 4618 mov r0, r3 80001cc: f001 f882 bl 80012d4 80001d0: 4603 mov r3, r0 80001d2: 2b00 cmp r3, #0 80001d4: d001 beq.n 80001da { Error_Handler(); 80001d6: f000 f9eb bl 80005b0 } } 80001da: bf00 nop 80001dc: 3740 adds r7, #64 @ 0x40 80001de: 46bd mov sp, r7 80001e0: bd80 pop {r7, pc} ... 080001e4 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 80001e4: b580 push {r7, lr} 80001e6: b096 sub sp, #88 @ 0x58 80001e8: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80001ea: f107 0348 add.w r3, r7, #72 @ 0x48 80001ee: 2200 movs r2, #0 80001f0: 601a str r2, [r3, #0] 80001f2: 605a str r2, [r3, #4] 80001f4: 609a str r2, [r3, #8] 80001f6: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80001f8: f107 0340 add.w r3, r7, #64 @ 0x40 80001fc: 2200 movs r2, #0 80001fe: 601a str r2, [r3, #0] 8000200: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 8000202: f107 0324 add.w r3, r7, #36 @ 0x24 8000206: 2200 movs r2, #0 8000208: 601a str r2, [r3, #0] 800020a: 605a str r2, [r3, #4] 800020c: 609a str r2, [r3, #8] 800020e: 60da str r2, [r3, #12] 8000210: 611a str r2, [r3, #16] 8000212: 615a str r2, [r3, #20] 8000214: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000216: 1d3b adds r3, r7, #4 8000218: 2220 movs r2, #32 800021a: 2100 movs r1, #0 800021c: 4618 mov r0, r3 800021e: f001 ff22 bl 8002066 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000222: 4b50 ldr r3, [pc, #320] @ (8000364 ) 8000224: 4a50 ldr r2, [pc, #320] @ (8000368 ) 8000226: 601a str r2, [r3, #0] htim1.Init.Prescaler = 0; 8000228: 4b4e ldr r3, [pc, #312] @ (8000364 ) 800022a: 2200 movs r2, #0 800022c: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 800022e: 4b4d ldr r3, [pc, #308] @ (8000364 ) 8000230: 2200 movs r2, #0 8000232: 609a str r2, [r3, #8] htim1.Init.Period = 65535; 8000234: 4b4b ldr r3, [pc, #300] @ (8000364 ) 8000236: f64f 72ff movw r2, #65535 @ 0xffff 800023a: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800023c: 4b49 ldr r3, [pc, #292] @ (8000364 ) 800023e: 2200 movs r2, #0 8000240: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000242: 4b48 ldr r3, [pc, #288] @ (8000364 ) 8000244: 2200 movs r2, #0 8000246: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000248: 4b46 ldr r3, [pc, #280] @ (8000364 ) 800024a: 2200 movs r2, #0 800024c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 800024e: 4845 ldr r0, [pc, #276] @ (8000364 ) 8000250: f001 f99c bl 800158c 8000254: 4603 mov r3, r0 8000256: 2b00 cmp r3, #0 8000258: d001 beq.n 800025e { Error_Handler(); 800025a: f000 f9a9 bl 80005b0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800025e: f44f 5380 mov.w r3, #4096 @ 0x1000 8000262: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 8000264: f107 0348 add.w r3, r7, #72 @ 0x48 8000268: 4619 mov r1, r3 800026a: 483e ldr r0, [pc, #248] @ (8000364 ) 800026c: f001 faf8 bl 8001860 8000270: 4603 mov r3, r0 8000272: 2b00 cmp r3, #0 8000274: d001 beq.n 800027a { Error_Handler(); 8000276: f000 f99b bl 80005b0 } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 800027a: 483a ldr r0, [pc, #232] @ (8000364 ) 800027c: f001 f9d5 bl 800162a 8000280: 4603 mov r3, r0 8000282: 2b00 cmp r3, #0 8000284: d001 beq.n 800028a { Error_Handler(); 8000286: f000 f993 bl 80005b0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800028a: 2300 movs r3, #0 800028c: 643b str r3, [r7, #64] @ 0x40 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800028e: 2300 movs r3, #0 8000290: 647b str r3, [r7, #68] @ 0x44 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000292: f107 0340 add.w r3, r7, #64 @ 0x40 8000296: 4619 mov r1, r3 8000298: 4832 ldr r0, [pc, #200] @ (8000364 ) 800029a: f001 fe35 bl 8001f08 800029e: 4603 mov r3, r0 80002a0: 2b00 cmp r3, #0 80002a2: d001 beq.n 80002a8 { Error_Handler(); 80002a4: f000 f984 bl 80005b0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 80002a8: 2360 movs r3, #96 @ 0x60 80002aa: 627b str r3, [r7, #36] @ 0x24 sConfigOC.Pulse = 0; 80002ac: 2300 movs r3, #0 80002ae: 62bb str r3, [r7, #40] @ 0x28 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80002b0: 2300 movs r3, #0 80002b2: 62fb str r3, [r7, #44] @ 0x2c sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 80002b4: 2300 movs r3, #0 80002b6: 633b str r3, [r7, #48] @ 0x30 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80002b8: 2300 movs r3, #0 80002ba: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 80002bc: 2300 movs r3, #0 80002be: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 80002c0: 2300 movs r3, #0 80002c2: 63fb str r3, [r7, #60] @ 0x3c if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80002c4: f107 0324 add.w r3, r7, #36 @ 0x24 80002c8: 2200 movs r2, #0 80002ca: 4619 mov r1, r3 80002cc: 4825 ldr r0, [pc, #148] @ (8000364 ) 80002ce: f001 fa05 bl 80016dc 80002d2: 4603 mov r3, r0 80002d4: 2b00 cmp r3, #0 80002d6: d001 beq.n 80002dc { Error_Handler(); 80002d8: f000 f96a bl 80005b0 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80002dc: f107 0324 add.w r3, r7, #36 @ 0x24 80002e0: 2204 movs r2, #4 80002e2: 4619 mov r1, r3 80002e4: 481f ldr r0, [pc, #124] @ (8000364 ) 80002e6: f001 f9f9 bl 80016dc 80002ea: 4603 mov r3, r0 80002ec: 2b00 cmp r3, #0 80002ee: d001 beq.n 80002f4 { Error_Handler(); 80002f0: f000 f95e bl 80005b0 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 80002f4: f107 0324 add.w r3, r7, #36 @ 0x24 80002f8: 2208 movs r2, #8 80002fa: 4619 mov r1, r3 80002fc: 4819 ldr r0, [pc, #100] @ (8000364 ) 80002fe: f001 f9ed bl 80016dc 8000302: 4603 mov r3, r0 8000304: 2b00 cmp r3, #0 8000306: d001 beq.n 800030c { Error_Handler(); 8000308: f000 f952 bl 80005b0 } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800030c: f107 0324 add.w r3, r7, #36 @ 0x24 8000310: 220c movs r2, #12 8000312: 4619 mov r1, r3 8000314: 4813 ldr r0, [pc, #76] @ (8000364 ) 8000316: f001 f9e1 bl 80016dc 800031a: 4603 mov r3, r0 800031c: 2b00 cmp r3, #0 800031e: d001 beq.n 8000324 { Error_Handler(); 8000320: f000 f946 bl 80005b0 } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 8000324: 2300 movs r3, #0 8000326: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8000328: 2300 movs r3, #0 800032a: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 800032c: 2300 movs r3, #0 800032e: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8000330: 2300 movs r3, #0 8000332: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 8000334: 2300 movs r3, #0 8000336: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8000338: f44f 5300 mov.w r3, #8192 @ 0x2000 800033c: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 800033e: 2300 movs r3, #0 8000340: 623b str r3, [r7, #32] if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8000342: 1d3b adds r3, r7, #4 8000344: 4619 mov r1, r3 8000346: 4807 ldr r0, [pc, #28] @ (8000364 ) 8000348: f001 fe3c bl 8001fc4 800034c: 4603 mov r3, r0 800034e: 2b00 cmp r3, #0 8000350: d001 beq.n 8000356 { Error_Handler(); 8000352: f000 f92d bl 80005b0 } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8000356: 4803 ldr r0, [pc, #12] @ (8000364 ) 8000358: f000 f9a6 bl 80006a8 } 800035c: bf00 nop 800035e: 3758 adds r7, #88 @ 0x58 8000360: 46bd mov sp, r7 8000362: bd80 pop {r7, pc} 8000364: 20000028 .word 0x20000028 8000368: 40012c00 .word 0x40012c00 0800036c : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 800036c: b580 push {r7, lr} 800036e: b08e sub sp, #56 @ 0x38 8000370: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000372: f107 0328 add.w r3, r7, #40 @ 0x28 8000376: 2200 movs r2, #0 8000378: 601a str r2, [r3, #0] 800037a: 605a str r2, [r3, #4] 800037c: 609a str r2, [r3, #8] 800037e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000380: f107 0320 add.w r3, r7, #32 8000384: 2200 movs r2, #0 8000386: 601a str r2, [r3, #0] 8000388: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800038a: 1d3b adds r3, r7, #4 800038c: 2200 movs r2, #0 800038e: 601a str r2, [r3, #0] 8000390: 605a str r2, [r3, #4] 8000392: 609a str r2, [r3, #8] 8000394: 60da str r2, [r3, #12] 8000396: 611a str r2, [r3, #16] 8000398: 615a str r2, [r3, #20] 800039a: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 800039c: 4b3d ldr r3, [pc, #244] @ (8000494 ) 800039e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80003a2: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 80003a4: 4b3b ldr r3, [pc, #236] @ (8000494 ) 80003a6: 2200 movs r2, #0 80003a8: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80003aa: 4b3a ldr r3, [pc, #232] @ (8000494 ) 80003ac: 2200 movs r2, #0 80003ae: 609a str r2, [r3, #8] htim2.Init.Period = 65535; 80003b0: 4b38 ldr r3, [pc, #224] @ (8000494 ) 80003b2: f64f 72ff movw r2, #65535 @ 0xffff 80003b6: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80003b8: 4b36 ldr r3, [pc, #216] @ (8000494 ) 80003ba: 2200 movs r2, #0 80003bc: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80003be: 4b35 ldr r3, [pc, #212] @ (8000494 ) 80003c0: 2200 movs r2, #0 80003c2: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 80003c4: 4833 ldr r0, [pc, #204] @ (8000494 ) 80003c6: f001 f8e1 bl 800158c 80003ca: 4603 mov r3, r0 80003cc: 2b00 cmp r3, #0 80003ce: d001 beq.n 80003d4 { Error_Handler(); 80003d0: f000 f8ee bl 80005b0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80003d4: f44f 5380 mov.w r3, #4096 @ 0x1000 80003d8: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 80003da: f107 0328 add.w r3, r7, #40 @ 0x28 80003de: 4619 mov r1, r3 80003e0: 482c ldr r0, [pc, #176] @ (8000494 ) 80003e2: f001 fa3d bl 8001860 80003e6: 4603 mov r3, r0 80003e8: 2b00 cmp r3, #0 80003ea: d001 beq.n 80003f0 { Error_Handler(); 80003ec: f000 f8e0 bl 80005b0 } if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 80003f0: 4828 ldr r0, [pc, #160] @ (8000494 ) 80003f2: f001 f91a bl 800162a 80003f6: 4603 mov r3, r0 80003f8: 2b00 cmp r3, #0 80003fa: d001 beq.n 8000400 { Error_Handler(); 80003fc: f000 f8d8 bl 80005b0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000400: 2300 movs r3, #0 8000402: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000404: 2300 movs r3, #0 8000406: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8000408: f107 0320 add.w r3, r7, #32 800040c: 4619 mov r1, r3 800040e: 4821 ldr r0, [pc, #132] @ (8000494 ) 8000410: f001 fd7a bl 8001f08 8000414: 4603 mov r3, r0 8000416: 2b00 cmp r3, #0 8000418: d001 beq.n 800041e { Error_Handler(); 800041a: f000 f8c9 bl 80005b0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800041e: 2360 movs r3, #96 @ 0x60 8000420: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8000422: 2300 movs r3, #0 8000424: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000426: 2300 movs r3, #0 8000428: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800042a: 2300 movs r3, #0 800042c: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800042e: 1d3b adds r3, r7, #4 8000430: 2200 movs r2, #0 8000432: 4619 mov r1, r3 8000434: 4817 ldr r0, [pc, #92] @ (8000494 ) 8000436: f001 f951 bl 80016dc 800043a: 4603 mov r3, r0 800043c: 2b00 cmp r3, #0 800043e: d001 beq.n 8000444 { Error_Handler(); 8000440: f000 f8b6 bl 80005b0 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8000444: 1d3b adds r3, r7, #4 8000446: 2204 movs r2, #4 8000448: 4619 mov r1, r3 800044a: 4812 ldr r0, [pc, #72] @ (8000494 ) 800044c: f001 f946 bl 80016dc 8000450: 4603 mov r3, r0 8000452: 2b00 cmp r3, #0 8000454: d001 beq.n 800045a { Error_Handler(); 8000456: f000 f8ab bl 80005b0 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800045a: 1d3b adds r3, r7, #4 800045c: 2208 movs r2, #8 800045e: 4619 mov r1, r3 8000460: 480c ldr r0, [pc, #48] @ (8000494 ) 8000462: f001 f93b bl 80016dc 8000466: 4603 mov r3, r0 8000468: 2b00 cmp r3, #0 800046a: d001 beq.n 8000470 { Error_Handler(); 800046c: f000 f8a0 bl 80005b0 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 8000470: 1d3b adds r3, r7, #4 8000472: 220c movs r2, #12 8000474: 4619 mov r1, r3 8000476: 4807 ldr r0, [pc, #28] @ (8000494 ) 8000478: f001 f930 bl 80016dc 800047c: 4603 mov r3, r0 800047e: 2b00 cmp r3, #0 8000480: d001 beq.n 8000486 { Error_Handler(); 8000482: f000 f895 bl 80005b0 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8000486: 4803 ldr r0, [pc, #12] @ (8000494 ) 8000488: f000 f90e bl 80006a8 } 800048c: bf00 nop 800048e: 3738 adds r7, #56 @ 0x38 8000490: 46bd mov sp, r7 8000492: bd80 pop {r7, pc} 8000494: 20000070 .word 0x20000070 08000498 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 8000498: b580 push {r7, lr} 800049a: b08e sub sp, #56 @ 0x38 800049c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800049e: f107 0328 add.w r3, r7, #40 @ 0x28 80004a2: 2200 movs r2, #0 80004a4: 601a str r2, [r3, #0] 80004a6: 605a str r2, [r3, #4] 80004a8: 609a str r2, [r3, #8] 80004aa: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80004ac: f107 0320 add.w r3, r7, #32 80004b0: 2200 movs r2, #0 80004b2: 601a str r2, [r3, #0] 80004b4: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 80004b6: 1d3b adds r3, r7, #4 80004b8: 2200 movs r2, #0 80004ba: 601a str r2, [r3, #0] 80004bc: 605a str r2, [r3, #4] 80004be: 609a str r2, [r3, #8] 80004c0: 60da str r2, [r3, #12] 80004c2: 611a str r2, [r3, #16] 80004c4: 615a str r2, [r3, #20] 80004c6: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80004c8: 4b2c ldr r3, [pc, #176] @ (800057c ) 80004ca: 4a2d ldr r2, [pc, #180] @ (8000580 ) 80004cc: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 80004ce: 4b2b ldr r3, [pc, #172] @ (800057c ) 80004d0: 2200 movs r2, #0 80004d2: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80004d4: 4b29 ldr r3, [pc, #164] @ (800057c ) 80004d6: 2200 movs r2, #0 80004d8: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 80004da: 4b28 ldr r3, [pc, #160] @ (800057c ) 80004dc: f64f 72ff movw r2, #65535 @ 0xffff 80004e0: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80004e2: 4b26 ldr r3, [pc, #152] @ (800057c ) 80004e4: 2200 movs r2, #0 80004e6: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80004e8: 4b24 ldr r3, [pc, #144] @ (800057c ) 80004ea: 2200 movs r2, #0 80004ec: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 80004ee: 4823 ldr r0, [pc, #140] @ (800057c ) 80004f0: f001 f84c bl 800158c 80004f4: 4603 mov r3, r0 80004f6: 2b00 cmp r3, #0 80004f8: d001 beq.n 80004fe { Error_Handler(); 80004fa: f000 f859 bl 80005b0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80004fe: f44f 5380 mov.w r3, #4096 @ 0x1000 8000502: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8000504: f107 0328 add.w r3, r7, #40 @ 0x28 8000508: 4619 mov r1, r3 800050a: 481c ldr r0, [pc, #112] @ (800057c ) 800050c: f001 f9a8 bl 8001860 8000510: 4603 mov r3, r0 8000512: 2b00 cmp r3, #0 8000514: d001 beq.n 800051a { Error_Handler(); 8000516: f000 f84b bl 80005b0 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800051a: 4818 ldr r0, [pc, #96] @ (800057c ) 800051c: f001 f885 bl 800162a 8000520: 4603 mov r3, r0 8000522: 2b00 cmp r3, #0 8000524: d001 beq.n 800052a { Error_Handler(); 8000526: f000 f843 bl 80005b0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800052a: 2300 movs r3, #0 800052c: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800052e: 2300 movs r3, #0 8000530: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8000532: f107 0320 add.w r3, r7, #32 8000536: 4619 mov r1, r3 8000538: 4810 ldr r0, [pc, #64] @ (800057c ) 800053a: f001 fce5 bl 8001f08 800053e: 4603 mov r3, r0 8000540: 2b00 cmp r3, #0 8000542: d001 beq.n 8000548 { Error_Handler(); 8000544: f000 f834 bl 80005b0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000548: 2360 movs r3, #96 @ 0x60 800054a: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800054c: 2300 movs r3, #0 800054e: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000550: 2300 movs r3, #0 8000552: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000554: 2300 movs r3, #0 8000556: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8000558: 1d3b adds r3, r7, #4 800055a: 2200 movs r2, #0 800055c: 4619 mov r1, r3 800055e: 4807 ldr r0, [pc, #28] @ (800057c ) 8000560: f001 f8bc bl 80016dc 8000564: 4603 mov r3, r0 8000566: 2b00 cmp r3, #0 8000568: d001 beq.n 800056e { Error_Handler(); 800056a: f000 f821 bl 80005b0 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800056e: 4803 ldr r0, [pc, #12] @ (800057c ) 8000570: f000 f89a bl 80006a8 } 8000574: bf00 nop 8000576: 3738 adds r7, #56 @ 0x38 8000578: 46bd mov sp, r7 800057a: bd80 pop {r7, pc} 800057c: 200000b8 .word 0x200000b8 8000580: 40000400 .word 0x40000400 08000584 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000584: b480 push {r7} 8000586: b083 sub sp, #12 8000588: af00 add r7, sp, #0 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800058a: 4b08 ldr r3, [pc, #32] @ (80005ac ) 800058c: 699b ldr r3, [r3, #24] 800058e: 4a07 ldr r2, [pc, #28] @ (80005ac ) 8000590: f043 0304 orr.w r3, r3, #4 8000594: 6193 str r3, [r2, #24] 8000596: 4b05 ldr r3, [pc, #20] @ (80005ac ) 8000598: 699b ldr r3, [r3, #24] 800059a: f003 0304 and.w r3, r3, #4 800059e: 607b str r3, [r7, #4] 80005a0: 687b ldr r3, [r7, #4] /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80005a2: bf00 nop 80005a4: 370c adds r7, #12 80005a6: 46bd mov sp, r7 80005a8: bc80 pop {r7} 80005aa: 4770 bx lr 80005ac: 40021000 .word 0x40021000 080005b0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80005b0: b480 push {r7} 80005b2: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80005b4: b672 cpsid i } 80005b6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80005b8: bf00 nop 80005ba: e7fd b.n 80005b8 080005bc : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80005bc: b480 push {r7} 80005be: b085 sub sp, #20 80005c0: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80005c2: 4b15 ldr r3, [pc, #84] @ (8000618 ) 80005c4: 699b ldr r3, [r3, #24] 80005c6: 4a14 ldr r2, [pc, #80] @ (8000618 ) 80005c8: f043 0301 orr.w r3, r3, #1 80005cc: 6193 str r3, [r2, #24] 80005ce: 4b12 ldr r3, [pc, #72] @ (8000618 ) 80005d0: 699b ldr r3, [r3, #24] 80005d2: f003 0301 and.w r3, r3, #1 80005d6: 60bb str r3, [r7, #8] 80005d8: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80005da: 4b0f ldr r3, [pc, #60] @ (8000618 ) 80005dc: 69db ldr r3, [r3, #28] 80005de: 4a0e ldr r2, [pc, #56] @ (8000618 ) 80005e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80005e4: 61d3 str r3, [r2, #28] 80005e6: 4b0c ldr r3, [pc, #48] @ (8000618 ) 80005e8: 69db ldr r3, [r3, #28] 80005ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80005ee: 607b str r3, [r7, #4] 80005f0: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 80005f2: 4b0a ldr r3, [pc, #40] @ (800061c ) 80005f4: 685b ldr r3, [r3, #4] 80005f6: 60fb str r3, [r7, #12] 80005f8: 68fb ldr r3, [r7, #12] 80005fa: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 80005fe: 60fb str r3, [r7, #12] 8000600: 68fb ldr r3, [r7, #12] 8000602: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8000606: 60fb str r3, [r7, #12] 8000608: 4a04 ldr r2, [pc, #16] @ (800061c ) 800060a: 68fb ldr r3, [r7, #12] 800060c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800060e: bf00 nop 8000610: 3714 adds r7, #20 8000612: 46bd mov sp, r7 8000614: bc80 pop {r7} 8000616: 4770 bx lr 8000618: 40021000 .word 0x40021000 800061c: 40010000 .word 0x40010000 08000620 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8000620: b480 push {r7} 8000622: b087 sub sp, #28 8000624: af00 add r7, sp, #0 8000626: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 8000628: 687b ldr r3, [r7, #4] 800062a: 681b ldr r3, [r3, #0] 800062c: 4a1b ldr r2, [pc, #108] @ (800069c ) 800062e: 4293 cmp r3, r2 8000630: d10c bne.n 800064c { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8000632: 4b1b ldr r3, [pc, #108] @ (80006a0 ) 8000634: 699b ldr r3, [r3, #24] 8000636: 4a1a ldr r2, [pc, #104] @ (80006a0 ) 8000638: f443 6300 orr.w r3, r3, #2048 @ 0x800 800063c: 6193 str r3, [r2, #24] 800063e: 4b18 ldr r3, [pc, #96] @ (80006a0 ) 8000640: 699b ldr r3, [r3, #24] 8000642: f403 6300 and.w r3, r3, #2048 @ 0x800 8000646: 617b str r3, [r7, #20] 8000648: 697b ldr r3, [r7, #20] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800064a: e022 b.n 8000692 else if(htim_base->Instance==TIM2) 800064c: 687b ldr r3, [r7, #4] 800064e: 681b ldr r3, [r3, #0] 8000650: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8000654: d10c bne.n 8000670 __HAL_RCC_TIM2_CLK_ENABLE(); 8000656: 4b12 ldr r3, [pc, #72] @ (80006a0 ) 8000658: 69db ldr r3, [r3, #28] 800065a: 4a11 ldr r2, [pc, #68] @ (80006a0 ) 800065c: f043 0301 orr.w r3, r3, #1 8000660: 61d3 str r3, [r2, #28] 8000662: 4b0f ldr r3, [pc, #60] @ (80006a0 ) 8000664: 69db ldr r3, [r3, #28] 8000666: f003 0301 and.w r3, r3, #1 800066a: 613b str r3, [r7, #16] 800066c: 693b ldr r3, [r7, #16] } 800066e: e010 b.n 8000692 else if(htim_base->Instance==TIM3) 8000670: 687b ldr r3, [r7, #4] 8000672: 681b ldr r3, [r3, #0] 8000674: 4a0b ldr r2, [pc, #44] @ (80006a4 ) 8000676: 4293 cmp r3, r2 8000678: d10b bne.n 8000692 __HAL_RCC_TIM3_CLK_ENABLE(); 800067a: 4b09 ldr r3, [pc, #36] @ (80006a0 ) 800067c: 69db ldr r3, [r3, #28] 800067e: 4a08 ldr r2, [pc, #32] @ (80006a0 ) 8000680: f043 0302 orr.w r3, r3, #2 8000684: 61d3 str r3, [r2, #28] 8000686: 4b06 ldr r3, [pc, #24] @ (80006a0 ) 8000688: 69db ldr r3, [r3, #28] 800068a: f003 0302 and.w r3, r3, #2 800068e: 60fb str r3, [r7, #12] 8000690: 68fb ldr r3, [r7, #12] } 8000692: bf00 nop 8000694: 371c adds r7, #28 8000696: 46bd mov sp, r7 8000698: bc80 pop {r7} 800069a: 4770 bx lr 800069c: 40012c00 .word 0x40012c00 80006a0: 40021000 .word 0x40021000 80006a4: 40000400 .word 0x40000400 080006a8 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80006a8: b580 push {r7, lr} 80006aa: b08a sub sp, #40 @ 0x28 80006ac: af00 add r7, sp, #0 80006ae: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80006b0: f107 0318 add.w r3, r7, #24 80006b4: 2200 movs r2, #0 80006b6: 601a str r2, [r3, #0] 80006b8: 605a str r2, [r3, #4] 80006ba: 609a str r2, [r3, #8] 80006bc: 60da str r2, [r3, #12] if(htim->Instance==TIM1) 80006be: 687b ldr r3, [r7, #4] 80006c0: 681b ldr r3, [r3, #0] 80006c2: 4a2e ldr r2, [pc, #184] @ (800077c ) 80006c4: 4293 cmp r3, r2 80006c6: d119 bne.n 80006fc { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80006c8: 4b2d ldr r3, [pc, #180] @ (8000780 ) 80006ca: 699b ldr r3, [r3, #24] 80006cc: 4a2c ldr r2, [pc, #176] @ (8000780 ) 80006ce: f043 0304 orr.w r3, r3, #4 80006d2: 6193 str r3, [r2, #24] 80006d4: 4b2a ldr r3, [pc, #168] @ (8000780 ) 80006d6: 699b ldr r3, [r3, #24] 80006d8: f003 0304 and.w r3, r3, #4 80006dc: 617b str r3, [r7, #20] 80006de: 697b ldr r3, [r7, #20] PA8 ------> TIM1_CH1 PA9 ------> TIM1_CH2 PA10 ------> TIM1_CH3 PA11 ------> TIM1_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11; 80006e0: f44f 6370 mov.w r3, #3840 @ 0xf00 80006e4: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80006e6: 2302 movs r3, #2 80006e8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006ea: 2302 movs r3, #2 80006ec: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80006ee: f107 0318 add.w r3, r7, #24 80006f2: 4619 mov r1, r3 80006f4: 4823 ldr r0, [pc, #140] @ (8000784 ) 80006f6: f000 f9e7 bl 8000ac8 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 80006fa: e03a b.n 8000772 else if(htim->Instance==TIM2) 80006fc: 687b ldr r3, [r7, #4] 80006fe: 681b ldr r3, [r3, #0] 8000700: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8000704: d118 bne.n 8000738 __HAL_RCC_GPIOA_CLK_ENABLE(); 8000706: 4b1e ldr r3, [pc, #120] @ (8000780 ) 8000708: 699b ldr r3, [r3, #24] 800070a: 4a1d ldr r2, [pc, #116] @ (8000780 ) 800070c: f043 0304 orr.w r3, r3, #4 8000710: 6193 str r3, [r2, #24] 8000712: 4b1b ldr r3, [pc, #108] @ (8000780 ) 8000714: 699b ldr r3, [r3, #24] 8000716: f003 0304 and.w r3, r3, #4 800071a: 613b str r3, [r7, #16] 800071c: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 800071e: 230f movs r3, #15 8000720: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000722: 2302 movs r3, #2 8000724: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000726: 2302 movs r3, #2 8000728: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800072a: f107 0318 add.w r3, r7, #24 800072e: 4619 mov r1, r3 8000730: 4814 ldr r0, [pc, #80] @ (8000784 ) 8000732: f000 f9c9 bl 8000ac8 } 8000736: e01c b.n 8000772 else if(htim->Instance==TIM3) 8000738: 687b ldr r3, [r7, #4] 800073a: 681b ldr r3, [r3, #0] 800073c: 4a12 ldr r2, [pc, #72] @ (8000788 ) 800073e: 4293 cmp r3, r2 8000740: d117 bne.n 8000772 __HAL_RCC_GPIOA_CLK_ENABLE(); 8000742: 4b0f ldr r3, [pc, #60] @ (8000780 ) 8000744: 699b ldr r3, [r3, #24] 8000746: 4a0e ldr r2, [pc, #56] @ (8000780 ) 8000748: f043 0304 orr.w r3, r3, #4 800074c: 6193 str r3, [r2, #24] 800074e: 4b0c ldr r3, [pc, #48] @ (8000780 ) 8000750: 699b ldr r3, [r3, #24] 8000752: f003 0304 and.w r3, r3, #4 8000756: 60fb str r3, [r7, #12] 8000758: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6; 800075a: 2340 movs r3, #64 @ 0x40 800075c: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800075e: 2302 movs r3, #2 8000760: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000762: 2302 movs r3, #2 8000764: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000766: f107 0318 add.w r3, r7, #24 800076a: 4619 mov r1, r3 800076c: 4805 ldr r0, [pc, #20] @ (8000784 ) 800076e: f000 f9ab bl 8000ac8 } 8000772: bf00 nop 8000774: 3728 adds r7, #40 @ 0x28 8000776: 46bd mov sp, r7 8000778: bd80 pop {r7, pc} 800077a: bf00 nop 800077c: 40012c00 .word 0x40012c00 8000780: 40021000 .word 0x40021000 8000784: 40010800 .word 0x40010800 8000788: 40000400 .word 0x40000400 0800078c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800078c: b480 push {r7} 800078e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000790: bf00 nop 8000792: e7fd b.n 8000790 08000794 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000794: b480 push {r7} 8000796: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000798: bf00 nop 800079a: e7fd b.n 8000798 0800079c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800079c: b480 push {r7} 800079e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80007a0: bf00 nop 80007a2: e7fd b.n 80007a0 080007a4 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80007a4: b480 push {r7} 80007a6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80007a8: bf00 nop 80007aa: e7fd b.n 80007a8 080007ac : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80007ac: b480 push {r7} 80007ae: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80007b0: bf00 nop 80007b2: e7fd b.n 80007b0 080007b4 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80007b4: b480 push {r7} 80007b6: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80007b8: bf00 nop 80007ba: 46bd mov sp, r7 80007bc: bc80 pop {r7} 80007be: 4770 bx lr 080007c0 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80007c0: b480 push {r7} 80007c2: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80007c4: bf00 nop 80007c6: 46bd mov sp, r7 80007c8: bc80 pop {r7} 80007ca: 4770 bx lr 080007cc : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80007cc: b480 push {r7} 80007ce: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80007d0: bf00 nop 80007d2: 46bd mov sp, r7 80007d4: bc80 pop {r7} 80007d6: 4770 bx lr 080007d8 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80007d8: b580 push {r7, lr} 80007da: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80007dc: f000 f874 bl 80008c8 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80007e0: bf00 nop 80007e2: bd80 pop {r7, pc} 080007e4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80007e4: b480 push {r7} 80007e6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80007e8: bf00 nop 80007ea: 46bd mov sp, r7 80007ec: bc80 pop {r7} 80007ee: 4770 bx lr 080007f0 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 80007f0: f7ff fff8 bl 80007e4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80007f4: 480b ldr r0, [pc, #44] @ (8000824 ) ldr r1, =_edata 80007f6: 490c ldr r1, [pc, #48] @ (8000828 ) ldr r2, =_sidata 80007f8: 4a0c ldr r2, [pc, #48] @ (800082c ) movs r3, #0 80007fa: 2300 movs r3, #0 b LoopCopyDataInit 80007fc: e002 b.n 8000804 080007fe : CopyDataInit: ldr r4, [r2, r3] 80007fe: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000800: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000802: 3304 adds r3, #4 08000804 : LoopCopyDataInit: adds r4, r0, r3 8000804: 18c4 adds r4, r0, r3 cmp r4, r1 8000806: 428c cmp r4, r1 bcc CopyDataInit 8000808: d3f9 bcc.n 80007fe /* Zero fill the bss segment. */ ldr r2, =_sbss 800080a: 4a09 ldr r2, [pc, #36] @ (8000830 ) ldr r4, =_ebss 800080c: 4c09 ldr r4, [pc, #36] @ (8000834 ) movs r3, #0 800080e: 2300 movs r3, #0 b LoopFillZerobss 8000810: e001 b.n 8000816 08000812 : FillZerobss: str r3, [r2] 8000812: 6013 str r3, [r2, #0] adds r2, r2, #4 8000814: 3204 adds r2, #4 08000816 : LoopFillZerobss: cmp r2, r4 8000816: 42a2 cmp r2, r4 bcc FillZerobss 8000818: d3fb bcc.n 8000812 /* Call static constructors */ bl __libc_init_array 800081a: f001 fc2d bl 8002078 <__libc_init_array> /* Call the application's entry point.*/ bl main 800081e: f7ff fc95 bl 800014c

bx lr 8000822: 4770 bx lr ldr r0, =_sdata 8000824: 20000000 .word 0x20000000 ldr r1, =_edata 8000828: 2000000c .word 0x2000000c ldr r2, =_sidata 800082c: 08002104 .word 0x08002104 ldr r2, =_sbss 8000830: 2000000c .word 0x2000000c ldr r4, =_ebss 8000834: 20000104 .word 0x20000104 08000838 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000838: e7fe b.n 8000838 ... 0800083c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800083c: b580 push {r7, lr} 800083e: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000840: 4b08 ldr r3, [pc, #32] @ (8000864 ) 8000842: 681b ldr r3, [r3, #0] 8000844: 4a07 ldr r2, [pc, #28] @ (8000864 ) 8000846: f043 0310 orr.w r3, r3, #16 800084a: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800084c: 2003 movs r0, #3 800084e: f000 f907 bl 8000a60 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000852: 200f movs r0, #15 8000854: f000 f808 bl 8000868 /* Init the low level hardware */ HAL_MspInit(); 8000858: f7ff feb0 bl 80005bc /* Return function status */ return HAL_OK; 800085c: 2300 movs r3, #0 } 800085e: 4618 mov r0, r3 8000860: bd80 pop {r7, pc} 8000862: bf00 nop 8000864: 40022000 .word 0x40022000 08000868 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000868: b580 push {r7, lr} 800086a: b082 sub sp, #8 800086c: af00 add r7, sp, #0 800086e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000870: 4b12 ldr r3, [pc, #72] @ (80008bc ) 8000872: 681a ldr r2, [r3, #0] 8000874: 4b12 ldr r3, [pc, #72] @ (80008c0 ) 8000876: 781b ldrb r3, [r3, #0] 8000878: 4619 mov r1, r3 800087a: f44f 737a mov.w r3, #1000 @ 0x3e8 800087e: fbb3 f3f1 udiv r3, r3, r1 8000882: fbb2 f3f3 udiv r3, r2, r3 8000886: 4618 mov r0, r3 8000888: f000 f911 bl 8000aae 800088c: 4603 mov r3, r0 800088e: 2b00 cmp r3, #0 8000890: d001 beq.n 8000896 { return HAL_ERROR; 8000892: 2301 movs r3, #1 8000894: e00e b.n 80008b4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000896: 687b ldr r3, [r7, #4] 8000898: 2b0f cmp r3, #15 800089a: d80a bhi.n 80008b2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800089c: 2200 movs r2, #0 800089e: 6879 ldr r1, [r7, #4] 80008a0: f04f 30ff mov.w r0, #4294967295 80008a4: f000 f8e7 bl 8000a76 uwTickPrio = TickPriority; 80008a8: 4a06 ldr r2, [pc, #24] @ (80008c4 ) 80008aa: 687b ldr r3, [r7, #4] 80008ac: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80008ae: 2300 movs r3, #0 80008b0: e000 b.n 80008b4 return HAL_ERROR; 80008b2: 2301 movs r3, #1 } 80008b4: 4618 mov r0, r3 80008b6: 3708 adds r7, #8 80008b8: 46bd mov sp, r7 80008ba: bd80 pop {r7, pc} 80008bc: 20000000 .word 0x20000000 80008c0: 20000008 .word 0x20000008 80008c4: 20000004 .word 0x20000004 080008c8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80008c8: b480 push {r7} 80008ca: af00 add r7, sp, #0 uwTick += uwTickFreq; 80008cc: 4b05 ldr r3, [pc, #20] @ (80008e4 ) 80008ce: 781b ldrb r3, [r3, #0] 80008d0: 461a mov r2, r3 80008d2: 4b05 ldr r3, [pc, #20] @ (80008e8 ) 80008d4: 681b ldr r3, [r3, #0] 80008d6: 4413 add r3, r2 80008d8: 4a03 ldr r2, [pc, #12] @ (80008e8 ) 80008da: 6013 str r3, [r2, #0] } 80008dc: bf00 nop 80008de: 46bd mov sp, r7 80008e0: bc80 pop {r7} 80008e2: 4770 bx lr 80008e4: 20000008 .word 0x20000008 80008e8: 20000100 .word 0x20000100 080008ec : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80008ec: b480 push {r7} 80008ee: af00 add r7, sp, #0 return uwTick; 80008f0: 4b02 ldr r3, [pc, #8] @ (80008fc ) 80008f2: 681b ldr r3, [r3, #0] } 80008f4: 4618 mov r0, r3 80008f6: 46bd mov sp, r7 80008f8: bc80 pop {r7} 80008fa: 4770 bx lr 80008fc: 20000100 .word 0x20000100 08000900 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000900: b480 push {r7} 8000902: b085 sub sp, #20 8000904: af00 add r7, sp, #0 8000906: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000908: 687b ldr r3, [r7, #4] 800090a: f003 0307 and.w r3, r3, #7 800090e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000910: 4b0c ldr r3, [pc, #48] @ (8000944 <__NVIC_SetPriorityGrouping+0x44>) 8000912: 68db ldr r3, [r3, #12] 8000914: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000916: 68ba ldr r2, [r7, #8] 8000918: f64f 03ff movw r3, #63743 @ 0xf8ff 800091c: 4013 ands r3, r2 800091e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000920: 68fb ldr r3, [r7, #12] 8000922: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000924: 68bb ldr r3, [r7, #8] 8000926: 4313 orrs r3, r2 reg_value = (reg_value | 8000928: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800092c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000930: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000932: 4a04 ldr r2, [pc, #16] @ (8000944 <__NVIC_SetPriorityGrouping+0x44>) 8000934: 68bb ldr r3, [r7, #8] 8000936: 60d3 str r3, [r2, #12] } 8000938: bf00 nop 800093a: 3714 adds r7, #20 800093c: 46bd mov sp, r7 800093e: bc80 pop {r7} 8000940: 4770 bx lr 8000942: bf00 nop 8000944: e000ed00 .word 0xe000ed00 08000948 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000948: b480 push {r7} 800094a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800094c: 4b04 ldr r3, [pc, #16] @ (8000960 <__NVIC_GetPriorityGrouping+0x18>) 800094e: 68db ldr r3, [r3, #12] 8000950: 0a1b lsrs r3, r3, #8 8000952: f003 0307 and.w r3, r3, #7 } 8000956: 4618 mov r0, r3 8000958: 46bd mov sp, r7 800095a: bc80 pop {r7} 800095c: 4770 bx lr 800095e: bf00 nop 8000960: e000ed00 .word 0xe000ed00 08000964 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000964: b480 push {r7} 8000966: b083 sub sp, #12 8000968: af00 add r7, sp, #0 800096a: 4603 mov r3, r0 800096c: 6039 str r1, [r7, #0] 800096e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000970: f997 3007 ldrsb.w r3, [r7, #7] 8000974: 2b00 cmp r3, #0 8000976: db0a blt.n 800098e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000978: 683b ldr r3, [r7, #0] 800097a: b2da uxtb r2, r3 800097c: 490c ldr r1, [pc, #48] @ (80009b0 <__NVIC_SetPriority+0x4c>) 800097e: f997 3007 ldrsb.w r3, [r7, #7] 8000982: 0112 lsls r2, r2, #4 8000984: b2d2 uxtb r2, r2 8000986: 440b add r3, r1 8000988: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800098c: e00a b.n 80009a4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800098e: 683b ldr r3, [r7, #0] 8000990: b2da uxtb r2, r3 8000992: 4908 ldr r1, [pc, #32] @ (80009b4 <__NVIC_SetPriority+0x50>) 8000994: 79fb ldrb r3, [r7, #7] 8000996: f003 030f and.w r3, r3, #15 800099a: 3b04 subs r3, #4 800099c: 0112 lsls r2, r2, #4 800099e: b2d2 uxtb r2, r2 80009a0: 440b add r3, r1 80009a2: 761a strb r2, [r3, #24] } 80009a4: bf00 nop 80009a6: 370c adds r7, #12 80009a8: 46bd mov sp, r7 80009aa: bc80 pop {r7} 80009ac: 4770 bx lr 80009ae: bf00 nop 80009b0: e000e100 .word 0xe000e100 80009b4: e000ed00 .word 0xe000ed00 080009b8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80009b8: b480 push {r7} 80009ba: b089 sub sp, #36 @ 0x24 80009bc: af00 add r7, sp, #0 80009be: 60f8 str r0, [r7, #12] 80009c0: 60b9 str r1, [r7, #8] 80009c2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80009c4: 68fb ldr r3, [r7, #12] 80009c6: f003 0307 and.w r3, r3, #7 80009ca: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80009cc: 69fb ldr r3, [r7, #28] 80009ce: f1c3 0307 rsb r3, r3, #7 80009d2: 2b04 cmp r3, #4 80009d4: bf28 it cs 80009d6: 2304 movcs r3, #4 80009d8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80009da: 69fb ldr r3, [r7, #28] 80009dc: 3304 adds r3, #4 80009de: 2b06 cmp r3, #6 80009e0: d902 bls.n 80009e8 80009e2: 69fb ldr r3, [r7, #28] 80009e4: 3b03 subs r3, #3 80009e6: e000 b.n 80009ea 80009e8: 2300 movs r3, #0 80009ea: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80009ec: f04f 32ff mov.w r2, #4294967295 80009f0: 69bb ldr r3, [r7, #24] 80009f2: fa02 f303 lsl.w r3, r2, r3 80009f6: 43da mvns r2, r3 80009f8: 68bb ldr r3, [r7, #8] 80009fa: 401a ands r2, r3 80009fc: 697b ldr r3, [r7, #20] 80009fe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000a00: f04f 31ff mov.w r1, #4294967295 8000a04: 697b ldr r3, [r7, #20] 8000a06: fa01 f303 lsl.w r3, r1, r3 8000a0a: 43d9 mvns r1, r3 8000a0c: 687b ldr r3, [r7, #4] 8000a0e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000a10: 4313 orrs r3, r2 ); } 8000a12: 4618 mov r0, r3 8000a14: 3724 adds r7, #36 @ 0x24 8000a16: 46bd mov sp, r7 8000a18: bc80 pop {r7} 8000a1a: 4770 bx lr 08000a1c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000a1c: b580 push {r7, lr} 8000a1e: b082 sub sp, #8 8000a20: af00 add r7, sp, #0 8000a22: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000a24: 687b ldr r3, [r7, #4] 8000a26: 3b01 subs r3, #1 8000a28: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8000a2c: d301 bcc.n 8000a32 { return (1UL); /* Reload value impossible */ 8000a2e: 2301 movs r3, #1 8000a30: e00f b.n 8000a52 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000a32: 4a0a ldr r2, [pc, #40] @ (8000a5c ) 8000a34: 687b ldr r3, [r7, #4] 8000a36: 3b01 subs r3, #1 8000a38: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000a3a: 210f movs r1, #15 8000a3c: f04f 30ff mov.w r0, #4294967295 8000a40: f7ff ff90 bl 8000964 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000a44: 4b05 ldr r3, [pc, #20] @ (8000a5c ) 8000a46: 2200 movs r2, #0 8000a48: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000a4a: 4b04 ldr r3, [pc, #16] @ (8000a5c ) 8000a4c: 2207 movs r2, #7 8000a4e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000a50: 2300 movs r3, #0 } 8000a52: 4618 mov r0, r3 8000a54: 3708 adds r7, #8 8000a56: 46bd mov sp, r7 8000a58: bd80 pop {r7, pc} 8000a5a: bf00 nop 8000a5c: e000e010 .word 0xe000e010 08000a60 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000a60: b580 push {r7, lr} 8000a62: b082 sub sp, #8 8000a64: af00 add r7, sp, #0 8000a66: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000a68: 6878 ldr r0, [r7, #4] 8000a6a: f7ff ff49 bl 8000900 <__NVIC_SetPriorityGrouping> } 8000a6e: bf00 nop 8000a70: 3708 adds r7, #8 8000a72: 46bd mov sp, r7 8000a74: bd80 pop {r7, pc} 08000a76 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000a76: b580 push {r7, lr} 8000a78: b086 sub sp, #24 8000a7a: af00 add r7, sp, #0 8000a7c: 4603 mov r3, r0 8000a7e: 60b9 str r1, [r7, #8] 8000a80: 607a str r2, [r7, #4] 8000a82: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000a84: 2300 movs r3, #0 8000a86: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000a88: f7ff ff5e bl 8000948 <__NVIC_GetPriorityGrouping> 8000a8c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000a8e: 687a ldr r2, [r7, #4] 8000a90: 68b9 ldr r1, [r7, #8] 8000a92: 6978 ldr r0, [r7, #20] 8000a94: f7ff ff90 bl 80009b8 8000a98: 4602 mov r2, r0 8000a9a: f997 300f ldrsb.w r3, [r7, #15] 8000a9e: 4611 mov r1, r2 8000aa0: 4618 mov r0, r3 8000aa2: f7ff ff5f bl 8000964 <__NVIC_SetPriority> } 8000aa6: bf00 nop 8000aa8: 3718 adds r7, #24 8000aaa: 46bd mov sp, r7 8000aac: bd80 pop {r7, pc} 08000aae : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000aae: b580 push {r7, lr} 8000ab0: b082 sub sp, #8 8000ab2: af00 add r7, sp, #0 8000ab4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000ab6: 6878 ldr r0, [r7, #4] 8000ab8: f7ff ffb0 bl 8000a1c 8000abc: 4603 mov r3, r0 } 8000abe: 4618 mov r0, r3 8000ac0: 3708 adds r7, #8 8000ac2: 46bd mov sp, r7 8000ac4: bd80 pop {r7, pc} ... 08000ac8 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000ac8: b480 push {r7} 8000aca: b08b sub sp, #44 @ 0x2c 8000acc: af00 add r7, sp, #0 8000ace: 6078 str r0, [r7, #4] 8000ad0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000ad2: 2300 movs r3, #0 8000ad4: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8000ad6: 2300 movs r3, #0 8000ad8: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000ada: e169 b.n 8000db0 { /* Get the IO position */ ioposition = (0x01uL << position); 8000adc: 2201 movs r2, #1 8000ade: 6a7b ldr r3, [r7, #36] @ 0x24 8000ae0: fa02 f303 lsl.w r3, r2, r3 8000ae4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8000ae6: 683b ldr r3, [r7, #0] 8000ae8: 681b ldr r3, [r3, #0] 8000aea: 69fa ldr r2, [r7, #28] 8000aec: 4013 ands r3, r2 8000aee: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8000af0: 69ba ldr r2, [r7, #24] 8000af2: 69fb ldr r3, [r7, #28] 8000af4: 429a cmp r2, r3 8000af6: f040 8158 bne.w 8000daa { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8000afa: 683b ldr r3, [r7, #0] 8000afc: 685b ldr r3, [r3, #4] 8000afe: 4a9a ldr r2, [pc, #616] @ (8000d68 ) 8000b00: 4293 cmp r3, r2 8000b02: d05e beq.n 8000bc2 8000b04: 4a98 ldr r2, [pc, #608] @ (8000d68 ) 8000b06: 4293 cmp r3, r2 8000b08: d875 bhi.n 8000bf6 8000b0a: 4a98 ldr r2, [pc, #608] @ (8000d6c ) 8000b0c: 4293 cmp r3, r2 8000b0e: d058 beq.n 8000bc2 8000b10: 4a96 ldr r2, [pc, #600] @ (8000d6c ) 8000b12: 4293 cmp r3, r2 8000b14: d86f bhi.n 8000bf6 8000b16: 4a96 ldr r2, [pc, #600] @ (8000d70 ) 8000b18: 4293 cmp r3, r2 8000b1a: d052 beq.n 8000bc2 8000b1c: 4a94 ldr r2, [pc, #592] @ (8000d70 ) 8000b1e: 4293 cmp r3, r2 8000b20: d869 bhi.n 8000bf6 8000b22: 4a94 ldr r2, [pc, #592] @ (8000d74 ) 8000b24: 4293 cmp r3, r2 8000b26: d04c beq.n 8000bc2 8000b28: 4a92 ldr r2, [pc, #584] @ (8000d74 ) 8000b2a: 4293 cmp r3, r2 8000b2c: d863 bhi.n 8000bf6 8000b2e: 4a92 ldr r2, [pc, #584] @ (8000d78 ) 8000b30: 4293 cmp r3, r2 8000b32: d046 beq.n 8000bc2 8000b34: 4a90 ldr r2, [pc, #576] @ (8000d78 ) 8000b36: 4293 cmp r3, r2 8000b38: d85d bhi.n 8000bf6 8000b3a: 2b12 cmp r3, #18 8000b3c: d82a bhi.n 8000b94 8000b3e: 2b12 cmp r3, #18 8000b40: d859 bhi.n 8000bf6 8000b42: a201 add r2, pc, #4 @ (adr r2, 8000b48 ) 8000b44: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000b48: 08000bc3 .word 0x08000bc3 8000b4c: 08000b9d .word 0x08000b9d 8000b50: 08000baf .word 0x08000baf 8000b54: 08000bf1 .word 0x08000bf1 8000b58: 08000bf7 .word 0x08000bf7 8000b5c: 08000bf7 .word 0x08000bf7 8000b60: 08000bf7 .word 0x08000bf7 8000b64: 08000bf7 .word 0x08000bf7 8000b68: 08000bf7 .word 0x08000bf7 8000b6c: 08000bf7 .word 0x08000bf7 8000b70: 08000bf7 .word 0x08000bf7 8000b74: 08000bf7 .word 0x08000bf7 8000b78: 08000bf7 .word 0x08000bf7 8000b7c: 08000bf7 .word 0x08000bf7 8000b80: 08000bf7 .word 0x08000bf7 8000b84: 08000bf7 .word 0x08000bf7 8000b88: 08000bf7 .word 0x08000bf7 8000b8c: 08000ba5 .word 0x08000ba5 8000b90: 08000bb9 .word 0x08000bb9 8000b94: 4a79 ldr r2, [pc, #484] @ (8000d7c ) 8000b96: 4293 cmp r3, r2 8000b98: d013 beq.n 8000bc2 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8000b9a: e02c b.n 8000bf6 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8000b9c: 683b ldr r3, [r7, #0] 8000b9e: 68db ldr r3, [r3, #12] 8000ba0: 623b str r3, [r7, #32] break; 8000ba2: e029 b.n 8000bf8 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8000ba4: 683b ldr r3, [r7, #0] 8000ba6: 68db ldr r3, [r3, #12] 8000ba8: 3304 adds r3, #4 8000baa: 623b str r3, [r7, #32] break; 8000bac: e024 b.n 8000bf8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8000bae: 683b ldr r3, [r7, #0] 8000bb0: 68db ldr r3, [r3, #12] 8000bb2: 3308 adds r3, #8 8000bb4: 623b str r3, [r7, #32] break; 8000bb6: e01f b.n 8000bf8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8000bb8: 683b ldr r3, [r7, #0] 8000bba: 68db ldr r3, [r3, #12] 8000bbc: 330c adds r3, #12 8000bbe: 623b str r3, [r7, #32] break; 8000bc0: e01a b.n 8000bf8 if (GPIO_Init->Pull == GPIO_NOPULL) 8000bc2: 683b ldr r3, [r7, #0] 8000bc4: 689b ldr r3, [r3, #8] 8000bc6: 2b00 cmp r3, #0 8000bc8: d102 bne.n 8000bd0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8000bca: 2304 movs r3, #4 8000bcc: 623b str r3, [r7, #32] break; 8000bce: e013 b.n 8000bf8 else if (GPIO_Init->Pull == GPIO_PULLUP) 8000bd0: 683b ldr r3, [r7, #0] 8000bd2: 689b ldr r3, [r3, #8] 8000bd4: 2b01 cmp r3, #1 8000bd6: d105 bne.n 8000be4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8000bd8: 2308 movs r3, #8 8000bda: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8000bdc: 687b ldr r3, [r7, #4] 8000bde: 69fa ldr r2, [r7, #28] 8000be0: 611a str r2, [r3, #16] break; 8000be2: e009 b.n 8000bf8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8000be4: 2308 movs r3, #8 8000be6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8000be8: 687b ldr r3, [r7, #4] 8000bea: 69fa ldr r2, [r7, #28] 8000bec: 615a str r2, [r3, #20] break; 8000bee: e003 b.n 8000bf8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8000bf0: 2300 movs r3, #0 8000bf2: 623b str r3, [r7, #32] break; 8000bf4: e000 b.n 8000bf8 break; 8000bf6: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8000bf8: 69bb ldr r3, [r7, #24] 8000bfa: 2bff cmp r3, #255 @ 0xff 8000bfc: d801 bhi.n 8000c02 8000bfe: 687b ldr r3, [r7, #4] 8000c00: e001 b.n 8000c06 8000c02: 687b ldr r3, [r7, #4] 8000c04: 3304 adds r3, #4 8000c06: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8000c08: 69bb ldr r3, [r7, #24] 8000c0a: 2bff cmp r3, #255 @ 0xff 8000c0c: d802 bhi.n 8000c14 8000c0e: 6a7b ldr r3, [r7, #36] @ 0x24 8000c10: 009b lsls r3, r3, #2 8000c12: e002 b.n 8000c1a 8000c14: 6a7b ldr r3, [r7, #36] @ 0x24 8000c16: 3b08 subs r3, #8 8000c18: 009b lsls r3, r3, #2 8000c1a: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8000c1c: 697b ldr r3, [r7, #20] 8000c1e: 681a ldr r2, [r3, #0] 8000c20: 210f movs r1, #15 8000c22: 693b ldr r3, [r7, #16] 8000c24: fa01 f303 lsl.w r3, r1, r3 8000c28: 43db mvns r3, r3 8000c2a: 401a ands r2, r3 8000c2c: 6a39 ldr r1, [r7, #32] 8000c2e: 693b ldr r3, [r7, #16] 8000c30: fa01 f303 lsl.w r3, r1, r3 8000c34: 431a orrs r2, r3 8000c36: 697b ldr r3, [r7, #20] 8000c38: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000c3a: 683b ldr r3, [r7, #0] 8000c3c: 685b ldr r3, [r3, #4] 8000c3e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000c42: 2b00 cmp r3, #0 8000c44: f000 80b1 beq.w 8000daa { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000c48: 4b4d ldr r3, [pc, #308] @ (8000d80 ) 8000c4a: 699b ldr r3, [r3, #24] 8000c4c: 4a4c ldr r2, [pc, #304] @ (8000d80 ) 8000c4e: f043 0301 orr.w r3, r3, #1 8000c52: 6193 str r3, [r2, #24] 8000c54: 4b4a ldr r3, [pc, #296] @ (8000d80 ) 8000c56: 699b ldr r3, [r3, #24] 8000c58: f003 0301 and.w r3, r3, #1 8000c5c: 60bb str r3, [r7, #8] 8000c5e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8000c60: 4a48 ldr r2, [pc, #288] @ (8000d84 ) 8000c62: 6a7b ldr r3, [r7, #36] @ 0x24 8000c64: 089b lsrs r3, r3, #2 8000c66: 3302 adds r3, #2 8000c68: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000c6c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8000c6e: 6a7b ldr r3, [r7, #36] @ 0x24 8000c70: f003 0303 and.w r3, r3, #3 8000c74: 009b lsls r3, r3, #2 8000c76: 220f movs r2, #15 8000c78: fa02 f303 lsl.w r3, r2, r3 8000c7c: 43db mvns r3, r3 8000c7e: 68fa ldr r2, [r7, #12] 8000c80: 4013 ands r3, r2 8000c82: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8000c84: 687b ldr r3, [r7, #4] 8000c86: 4a40 ldr r2, [pc, #256] @ (8000d88 ) 8000c88: 4293 cmp r3, r2 8000c8a: d013 beq.n 8000cb4 8000c8c: 687b ldr r3, [r7, #4] 8000c8e: 4a3f ldr r2, [pc, #252] @ (8000d8c ) 8000c90: 4293 cmp r3, r2 8000c92: d00d beq.n 8000cb0 8000c94: 687b ldr r3, [r7, #4] 8000c96: 4a3e ldr r2, [pc, #248] @ (8000d90 ) 8000c98: 4293 cmp r3, r2 8000c9a: d007 beq.n 8000cac 8000c9c: 687b ldr r3, [r7, #4] 8000c9e: 4a3d ldr r2, [pc, #244] @ (8000d94 ) 8000ca0: 4293 cmp r3, r2 8000ca2: d101 bne.n 8000ca8 8000ca4: 2303 movs r3, #3 8000ca6: e006 b.n 8000cb6 8000ca8: 2304 movs r3, #4 8000caa: e004 b.n 8000cb6 8000cac: 2302 movs r3, #2 8000cae: e002 b.n 8000cb6 8000cb0: 2301 movs r3, #1 8000cb2: e000 b.n 8000cb6 8000cb4: 2300 movs r3, #0 8000cb6: 6a7a ldr r2, [r7, #36] @ 0x24 8000cb8: f002 0203 and.w r2, r2, #3 8000cbc: 0092 lsls r2, r2, #2 8000cbe: 4093 lsls r3, r2 8000cc0: 68fa ldr r2, [r7, #12] 8000cc2: 4313 orrs r3, r2 8000cc4: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8000cc6: 492f ldr r1, [pc, #188] @ (8000d84 ) 8000cc8: 6a7b ldr r3, [r7, #36] @ 0x24 8000cca: 089b lsrs r3, r3, #2 8000ccc: 3302 adds r3, #2 8000cce: 68fa ldr r2, [r7, #12] 8000cd0: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000cd4: 683b ldr r3, [r7, #0] 8000cd6: 685b ldr r3, [r3, #4] 8000cd8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8000cdc: 2b00 cmp r3, #0 8000cde: d006 beq.n 8000cee { SET_BIT(EXTI->RTSR, iocurrent); 8000ce0: 4b2d ldr r3, [pc, #180] @ (8000d98 ) 8000ce2: 689a ldr r2, [r3, #8] 8000ce4: 492c ldr r1, [pc, #176] @ (8000d98 ) 8000ce6: 69bb ldr r3, [r7, #24] 8000ce8: 4313 orrs r3, r2 8000cea: 608b str r3, [r1, #8] 8000cec: e006 b.n 8000cfc } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8000cee: 4b2a ldr r3, [pc, #168] @ (8000d98 ) 8000cf0: 689a ldr r2, [r3, #8] 8000cf2: 69bb ldr r3, [r7, #24] 8000cf4: 43db mvns r3, r3 8000cf6: 4928 ldr r1, [pc, #160] @ (8000d98 ) 8000cf8: 4013 ands r3, r2 8000cfa: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000cfc: 683b ldr r3, [r7, #0] 8000cfe: 685b ldr r3, [r3, #4] 8000d00: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8000d04: 2b00 cmp r3, #0 8000d06: d006 beq.n 8000d16 { SET_BIT(EXTI->FTSR, iocurrent); 8000d08: 4b23 ldr r3, [pc, #140] @ (8000d98 ) 8000d0a: 68da ldr r2, [r3, #12] 8000d0c: 4922 ldr r1, [pc, #136] @ (8000d98 ) 8000d0e: 69bb ldr r3, [r7, #24] 8000d10: 4313 orrs r3, r2 8000d12: 60cb str r3, [r1, #12] 8000d14: e006 b.n 8000d24 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8000d16: 4b20 ldr r3, [pc, #128] @ (8000d98 ) 8000d18: 68da ldr r2, [r3, #12] 8000d1a: 69bb ldr r3, [r7, #24] 8000d1c: 43db mvns r3, r3 8000d1e: 491e ldr r1, [pc, #120] @ (8000d98 ) 8000d20: 4013 ands r3, r2 8000d22: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000d24: 683b ldr r3, [r7, #0] 8000d26: 685b ldr r3, [r3, #4] 8000d28: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000d2c: 2b00 cmp r3, #0 8000d2e: d006 beq.n 8000d3e { SET_BIT(EXTI->EMR, iocurrent); 8000d30: 4b19 ldr r3, [pc, #100] @ (8000d98 ) 8000d32: 685a ldr r2, [r3, #4] 8000d34: 4918 ldr r1, [pc, #96] @ (8000d98 ) 8000d36: 69bb ldr r3, [r7, #24] 8000d38: 4313 orrs r3, r2 8000d3a: 604b str r3, [r1, #4] 8000d3c: e006 b.n 8000d4c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8000d3e: 4b16 ldr r3, [pc, #88] @ (8000d98 ) 8000d40: 685a ldr r2, [r3, #4] 8000d42: 69bb ldr r3, [r7, #24] 8000d44: 43db mvns r3, r3 8000d46: 4914 ldr r1, [pc, #80] @ (8000d98 ) 8000d48: 4013 ands r3, r2 8000d4a: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000d4c: 683b ldr r3, [r7, #0] 8000d4e: 685b ldr r3, [r3, #4] 8000d50: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000d54: 2b00 cmp r3, #0 8000d56: d021 beq.n 8000d9c { SET_BIT(EXTI->IMR, iocurrent); 8000d58: 4b0f ldr r3, [pc, #60] @ (8000d98 ) 8000d5a: 681a ldr r2, [r3, #0] 8000d5c: 490e ldr r1, [pc, #56] @ (8000d98 ) 8000d5e: 69bb ldr r3, [r7, #24] 8000d60: 4313 orrs r3, r2 8000d62: 600b str r3, [r1, #0] 8000d64: e021 b.n 8000daa 8000d66: bf00 nop 8000d68: 10320000 .word 0x10320000 8000d6c: 10310000 .word 0x10310000 8000d70: 10220000 .word 0x10220000 8000d74: 10210000 .word 0x10210000 8000d78: 10120000 .word 0x10120000 8000d7c: 10110000 .word 0x10110000 8000d80: 40021000 .word 0x40021000 8000d84: 40010000 .word 0x40010000 8000d88: 40010800 .word 0x40010800 8000d8c: 40010c00 .word 0x40010c00 8000d90: 40011000 .word 0x40011000 8000d94: 40011400 .word 0x40011400 8000d98: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8000d9c: 4b0b ldr r3, [pc, #44] @ (8000dcc ) 8000d9e: 681a ldr r2, [r3, #0] 8000da0: 69bb ldr r3, [r7, #24] 8000da2: 43db mvns r3, r3 8000da4: 4909 ldr r1, [pc, #36] @ (8000dcc ) 8000da6: 4013 ands r3, r2 8000da8: 600b str r3, [r1, #0] } } } position++; 8000daa: 6a7b ldr r3, [r7, #36] @ 0x24 8000dac: 3301 adds r3, #1 8000dae: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8000db0: 683b ldr r3, [r7, #0] 8000db2: 681a ldr r2, [r3, #0] 8000db4: 6a7b ldr r3, [r7, #36] @ 0x24 8000db6: fa22 f303 lsr.w r3, r2, r3 8000dba: 2b00 cmp r3, #0 8000dbc: f47f ae8e bne.w 8000adc } } 8000dc0: bf00 nop 8000dc2: bf00 nop 8000dc4: 372c adds r7, #44 @ 0x2c 8000dc6: 46bd mov sp, r7 8000dc8: bc80 pop {r7} 8000dca: 4770 bx lr 8000dcc: 40010400 .word 0x40010400 08000dd0 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000dd0: b580 push {r7, lr} 8000dd2: b086 sub sp, #24 8000dd4: af00 add r7, sp, #0 8000dd6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8000dd8: 687b ldr r3, [r7, #4] 8000dda: 2b00 cmp r3, #0 8000ddc: d101 bne.n 8000de2 { return HAL_ERROR; 8000dde: 2301 movs r3, #1 8000de0: e272 b.n 80012c8 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000de2: 687b ldr r3, [r7, #4] 8000de4: 681b ldr r3, [r3, #0] 8000de6: f003 0301 and.w r3, r3, #1 8000dea: 2b00 cmp r3, #0 8000dec: f000 8087 beq.w 8000efe { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000df0: 4b92 ldr r3, [pc, #584] @ (800103c ) 8000df2: 685b ldr r3, [r3, #4] 8000df4: f003 030c and.w r3, r3, #12 8000df8: 2b04 cmp r3, #4 8000dfa: d00c beq.n 8000e16 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000dfc: 4b8f ldr r3, [pc, #572] @ (800103c ) 8000dfe: 685b ldr r3, [r3, #4] 8000e00: f003 030c and.w r3, r3, #12 8000e04: 2b08 cmp r3, #8 8000e06: d112 bne.n 8000e2e 8000e08: 4b8c ldr r3, [pc, #560] @ (800103c ) 8000e0a: 685b ldr r3, [r3, #4] 8000e0c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000e10: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8000e14: d10b bne.n 8000e2e { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000e16: 4b89 ldr r3, [pc, #548] @ (800103c ) 8000e18: 681b ldr r3, [r3, #0] 8000e1a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000e1e: 2b00 cmp r3, #0 8000e20: d06c beq.n 8000efc 8000e22: 687b ldr r3, [r7, #4] 8000e24: 685b ldr r3, [r3, #4] 8000e26: 2b00 cmp r3, #0 8000e28: d168 bne.n 8000efc { return HAL_ERROR; 8000e2a: 2301 movs r3, #1 8000e2c: e24c b.n 80012c8 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000e2e: 687b ldr r3, [r7, #4] 8000e30: 685b ldr r3, [r3, #4] 8000e32: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8000e36: d106 bne.n 8000e46 8000e38: 4b80 ldr r3, [pc, #512] @ (800103c ) 8000e3a: 681b ldr r3, [r3, #0] 8000e3c: 4a7f ldr r2, [pc, #508] @ (800103c ) 8000e3e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000e42: 6013 str r3, [r2, #0] 8000e44: e02e b.n 8000ea4 8000e46: 687b ldr r3, [r7, #4] 8000e48: 685b ldr r3, [r3, #4] 8000e4a: 2b00 cmp r3, #0 8000e4c: d10c bne.n 8000e68 8000e4e: 4b7b ldr r3, [pc, #492] @ (800103c ) 8000e50: 681b ldr r3, [r3, #0] 8000e52: 4a7a ldr r2, [pc, #488] @ (800103c ) 8000e54: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8000e58: 6013 str r3, [r2, #0] 8000e5a: 4b78 ldr r3, [pc, #480] @ (800103c ) 8000e5c: 681b ldr r3, [r3, #0] 8000e5e: 4a77 ldr r2, [pc, #476] @ (800103c ) 8000e60: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8000e64: 6013 str r3, [r2, #0] 8000e66: e01d b.n 8000ea4 8000e68: 687b ldr r3, [r7, #4] 8000e6a: 685b ldr r3, [r3, #4] 8000e6c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8000e70: d10c bne.n 8000e8c 8000e72: 4b72 ldr r3, [pc, #456] @ (800103c ) 8000e74: 681b ldr r3, [r3, #0] 8000e76: 4a71 ldr r2, [pc, #452] @ (800103c ) 8000e78: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8000e7c: 6013 str r3, [r2, #0] 8000e7e: 4b6f ldr r3, [pc, #444] @ (800103c ) 8000e80: 681b ldr r3, [r3, #0] 8000e82: 4a6e ldr r2, [pc, #440] @ (800103c ) 8000e84: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000e88: 6013 str r3, [r2, #0] 8000e8a: e00b b.n 8000ea4 8000e8c: 4b6b ldr r3, [pc, #428] @ (800103c ) 8000e8e: 681b ldr r3, [r3, #0] 8000e90: 4a6a ldr r2, [pc, #424] @ (800103c ) 8000e92: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8000e96: 6013 str r3, [r2, #0] 8000e98: 4b68 ldr r3, [pc, #416] @ (800103c ) 8000e9a: 681b ldr r3, [r3, #0] 8000e9c: 4a67 ldr r2, [pc, #412] @ (800103c ) 8000e9e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8000ea2: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000ea4: 687b ldr r3, [r7, #4] 8000ea6: 685b ldr r3, [r3, #4] 8000ea8: 2b00 cmp r3, #0 8000eaa: d013 beq.n 8000ed4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000eac: f7ff fd1e bl 80008ec 8000eb0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000eb2: e008 b.n 8000ec6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000eb4: f7ff fd1a bl 80008ec 8000eb8: 4602 mov r2, r0 8000eba: 693b ldr r3, [r7, #16] 8000ebc: 1ad3 subs r3, r2, r3 8000ebe: 2b64 cmp r3, #100 @ 0x64 8000ec0: d901 bls.n 8000ec6 { return HAL_TIMEOUT; 8000ec2: 2303 movs r3, #3 8000ec4: e200 b.n 80012c8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000ec6: 4b5d ldr r3, [pc, #372] @ (800103c ) 8000ec8: 681b ldr r3, [r3, #0] 8000eca: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000ece: 2b00 cmp r3, #0 8000ed0: d0f0 beq.n 8000eb4 8000ed2: e014 b.n 8000efe } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ed4: f7ff fd0a bl 80008ec 8000ed8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000eda: e008 b.n 8000eee { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000edc: f7ff fd06 bl 80008ec 8000ee0: 4602 mov r2, r0 8000ee2: 693b ldr r3, [r7, #16] 8000ee4: 1ad3 subs r3, r2, r3 8000ee6: 2b64 cmp r3, #100 @ 0x64 8000ee8: d901 bls.n 8000eee { return HAL_TIMEOUT; 8000eea: 2303 movs r3, #3 8000eec: e1ec b.n 80012c8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000eee: 4b53 ldr r3, [pc, #332] @ (800103c ) 8000ef0: 681b ldr r3, [r3, #0] 8000ef2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000ef6: 2b00 cmp r3, #0 8000ef8: d1f0 bne.n 8000edc 8000efa: e000 b.n 8000efe if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000efc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000efe: 687b ldr r3, [r7, #4] 8000f00: 681b ldr r3, [r3, #0] 8000f02: f003 0302 and.w r3, r3, #2 8000f06: 2b00 cmp r3, #0 8000f08: d063 beq.n 8000fd2 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000f0a: 4b4c ldr r3, [pc, #304] @ (800103c ) 8000f0c: 685b ldr r3, [r3, #4] 8000f0e: f003 030c and.w r3, r3, #12 8000f12: 2b00 cmp r3, #0 8000f14: d00b beq.n 8000f2e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000f16: 4b49 ldr r3, [pc, #292] @ (800103c ) 8000f18: 685b ldr r3, [r3, #4] 8000f1a: f003 030c and.w r3, r3, #12 8000f1e: 2b08 cmp r3, #8 8000f20: d11c bne.n 8000f5c