AUTOM10.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000ed18 0800010c 0800010c 0000110c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000007ec 0800ee24 0800ee24 0000fe24 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800f610 0800f610 000111dc 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800f610 0800f610 00010610 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800f618 0800f618 000111dc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800f618 0800f618 00010618 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800f61c 0800f61c 0001061c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001dc 20000000 0800f620 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000016c4 200001e0 0800f7fc 000111e0 2**3 ALLOC 10 ._user_heap_stack 00000604 200018a4 0800f7fc 000118a4 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000111dc 2**0 CONTENTS, READONLY 12 .debug_info 0001a759 00000000 00000000 00011205 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004a0b 00000000 00000000 0002b95e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000016b0 00000000 00000000 00030370 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001168 00000000 00000000 00031a20 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001d304 00000000 00000000 00032b88 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001f1d0 00000000 00000000 0004fe8c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00095eba 00000000 00000000 0006f05c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 00104f16 2**0 CONTENTS, READONLY 20 .debug_frame 000061b8 00000000 00000000 00104f5c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000005c 00000000 00000000 0010b114 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800010c <__do_global_dtors_aux>: 800010c: b510 push {r4, lr} 800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>) 8000110: 7823 ldrb r3, [r4, #0] 8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16> 8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>) 8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12> 8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>) 800011a: f3af 8000 nop.w 800011e: 2301 movs r3, #1 8000120: 7023 strb r3, [r4, #0] 8000122: bd10 pop {r4, pc} 8000124: 200001e0 .word 0x200001e0 8000128: 00000000 .word 0x00000000 800012c: 0800ee0c .word 0x0800ee0c 08000130 : 8000130: b508 push {r3, lr} 8000132: 4b03 ldr r3, [pc, #12] @ (8000140 ) 8000134: b11b cbz r3, 800013e 8000136: 4903 ldr r1, [pc, #12] @ (8000144 ) 8000138: 4803 ldr r0, [pc, #12] @ (8000148 ) 800013a: f3af 8000 nop.w 800013e: bd08 pop {r3, pc} 8000140: 00000000 .word 0x00000000 8000144: 200001e4 .word 0x200001e4 8000148: 0800ee0c .word 0x0800ee0c 0800014c : 800014c: 4603 mov r3, r0 800014e: f813 2b01 ldrb.w r2, [r3], #1 8000152: 2a00 cmp r2, #0 8000154: d1fb bne.n 800014e 8000156: 1a18 subs r0, r3, r0 8000158: 3801 subs r0, #1 800015a: 4770 bx lr 0800015c : uint16_t ch5 ; uint16_t ch6 ; uint16_t ch7 ; uint16_t ch8 ; void manageAdc(void){ 800015c: b480 push {r7} 800015e: af00 add r7, sp, #0 if (adc_avg_ready) 8000160: 4b12 ldr r3, [pc, #72] @ (80001ac ) 8000162: 781b ldrb r3, [r3, #0] 8000164: b2db uxtb r3, r3 8000166: 2b00 cmp r3, #0 8000168: d01b beq.n 80001a2 { adc_avg_ready = 0; 800016a: 4b10 ldr r3, [pc, #64] @ (80001ac ) 800016c: 2200 movs r2, #0 800016e: 701a strb r2, [r3, #0] // Read averaged channels (example mapping) ch4 = adc_avg[0]; 8000170: 4b0f ldr r3, [pc, #60] @ (80001b0 ) 8000172: 881b ldrh r3, [r3, #0] 8000174: b29a uxth r2, r3 8000176: 4b0f ldr r3, [pc, #60] @ (80001b4 ) 8000178: 801a strh r2, [r3, #0] ch5 = adc_avg[1]; 800017a: 4b0d ldr r3, [pc, #52] @ (80001b0 ) 800017c: 885b ldrh r3, [r3, #2] 800017e: b29a uxth r2, r3 8000180: 4b0d ldr r3, [pc, #52] @ (80001b8 ) 8000182: 801a strh r2, [r3, #0] ch6 = adc_avg[2]; 8000184: 4b0a ldr r3, [pc, #40] @ (80001b0 ) 8000186: 889b ldrh r3, [r3, #4] 8000188: b29a uxth r2, r3 800018a: 4b0c ldr r3, [pc, #48] @ (80001bc ) 800018c: 801a strh r2, [r3, #0] ch7 = adc_avg[3]; 800018e: 4b08 ldr r3, [pc, #32] @ (80001b0 ) 8000190: 88db ldrh r3, [r3, #6] 8000192: b29a uxth r2, r3 8000194: 4b0a ldr r3, [pc, #40] @ (80001c0 ) 8000196: 801a strh r2, [r3, #0] ch8 = adc_avg[4]; 8000198: 4b05 ldr r3, [pc, #20] @ (80001b0 ) 800019a: 891b ldrh r3, [r3, #8] 800019c: b29a uxth r2, r3 800019e: 4b09 ldr r3, [pc, #36] @ (80001c4 ) 80001a0: 801a strh r2, [r3, #0] // Use them (convert to volts, control, etc.) // float v4 = (3.3f * ch4) / 4095.0f; } } 80001a2: bf00 nop 80001a4: 46bd mov sp, r7 80001a6: bc80 pop {r7} 80001a8: 4770 bx lr 80001aa: bf00 nop 80001ac: 20000229 .word 0x20000229 80001b0: 20000208 .word 0x20000208 80001b4: 2000022a .word 0x2000022a 80001b8: 2000022c .word 0x2000022c 80001bc: 2000022e .word 0x2000022e 80001c0: 20000230 .word 0x20000230 80001c4: 20000232 .word 0x20000232 080001c8 : void readAdc(void){ 80001c8: b480 push {r7} 80001ca: b083 sub sp, #12 80001cc: af00 add r7, sp, #0 for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++) 80001ce: 2300 movs r3, #0 80001d0: 71fb strb r3, [r7, #7] 80001d2: e010 b.n 80001f6 { adc_sum[i] += adc_dma_buf[i]; 80001d4: 79fb ldrb r3, [r7, #7] 80001d6: 4a21 ldr r2, [pc, #132] @ (800025c ) 80001d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80001dc: b299 uxth r1, r3 80001de: 79fb ldrb r3, [r7, #7] 80001e0: 4a1f ldr r2, [pc, #124] @ (8000260 ) 80001e2: f852 2023 ldr.w r2, [r2, r3, lsl #2] 80001e6: 79fb ldrb r3, [r7, #7] 80001e8: 440a add r2, r1 80001ea: 491d ldr r1, [pc, #116] @ (8000260 ) 80001ec: f841 2023 str.w r2, [r1, r3, lsl #2] for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++) 80001f0: 79fb ldrb r3, [r7, #7] 80001f2: 3301 adds r3, #1 80001f4: 71fb strb r3, [r7, #7] 80001f6: 79fb ldrb r3, [r7, #7] 80001f8: 2b04 cmp r3, #4 80001fa: d9eb bls.n 80001d4 } adc_sum_count++; 80001fc: 4b19 ldr r3, [pc, #100] @ (8000264 ) 80001fe: 781b ldrb r3, [r3, #0] 8000200: 3301 adds r3, #1 8000202: b2da uxtb r2, r3 8000204: 4b17 ldr r3, [pc, #92] @ (8000264 ) 8000206: 701a strb r2, [r3, #0] /* When we collected ADC_AVG_WINDOW samples → compute average */ if (adc_sum_count >= ADC_AVG_WINDOW) 8000208: 4b16 ldr r3, [pc, #88] @ (8000264 ) 800020a: 781b ldrb r3, [r3, #0] 800020c: 2b04 cmp r3, #4 800020e: d920 bls.n 8000252 { for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++) 8000210: 2300 movs r3, #0 8000212: 71bb strb r3, [r7, #6] 8000214: e014 b.n 8000240 { adc_avg[i] = (uint16_t)(adc_sum[i] / ADC_AVG_WINDOW); 8000216: 79bb ldrb r3, [r7, #6] 8000218: 4a11 ldr r2, [pc, #68] @ (8000260 ) 800021a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800021e: 4a12 ldr r2, [pc, #72] @ (8000268 ) 8000220: fba2 2303 umull r2, r3, r2, r3 8000224: 089a lsrs r2, r3, #2 8000226: 79bb ldrb r3, [r7, #6] 8000228: b291 uxth r1, r2 800022a: 4a10 ldr r2, [pc, #64] @ (800026c ) 800022c: f822 1013 strh.w r1, [r2, r3, lsl #1] adc_sum[i] = 0; 8000230: 79bb ldrb r3, [r7, #6] 8000232: 4a0b ldr r2, [pc, #44] @ (8000260 ) 8000234: 2100 movs r1, #0 8000236: f842 1023 str.w r1, [r2, r3, lsl #2] for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++) 800023a: 79bb ldrb r3, [r7, #6] 800023c: 3301 adds r3, #1 800023e: 71bb strb r3, [r7, #6] 8000240: 79bb ldrb r3, [r7, #6] 8000242: 2b04 cmp r3, #4 8000244: d9e7 bls.n 8000216 } adc_sum_count = 0; 8000246: 4b07 ldr r3, [pc, #28] @ (8000264 ) 8000248: 2200 movs r2, #0 800024a: 701a strb r2, [r3, #0] adc_avg_ready = 1; // tell main loop new data is ready 800024c: 4b08 ldr r3, [pc, #32] @ (8000270 ) 800024e: 2201 movs r2, #1 8000250: 701a strb r2, [r3, #0] } } 8000252: bf00 nop 8000254: 370c adds r7, #12 8000256: 46bd mov sp, r7 8000258: bc80 pop {r7} 800025a: 4770 bx lr 800025c: 200001fc .word 0x200001fc 8000260: 20000214 .word 0x20000214 8000264: 20000228 .word 0x20000228 8000268: cccccccd .word 0xcccccccd 800026c: 20000208 .word 0x20000208 8000270: 20000229 .word 0x20000229 08000274 : uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data); void loadEE(void); void loadDefault(void); /* Pseudo-array accessor EEW[idx] */ static inline uint16_t EEW_Read(uint8_t idx, uint16_t *value) { 8000274: b580 push {r7, lr} 8000276: b082 sub sp, #8 8000278: af00 add r7, sp, #0 800027a: 4603 mov r3, r0 800027c: 6039 str r1, [r7, #0] 800027e: 71fb strb r3, [r7, #7] return EE_ReadVariable(EEW_ADDR(idx), value); 8000280: 79fb ldrb r3, [r7, #7] 8000282: b29b uxth r3, r3 8000284: 3301 adds r3, #1 8000286: b29b uxth r3, r3 8000288: 6839 ldr r1, [r7, #0] 800028a: 4618 mov r0, r3 800028c: f001 f9e4 bl 8001658 8000290: 4603 mov r3, r0 } 8000292: 4618 mov r0, r3 8000294: 3708 adds r7, #8 8000296: 46bd mov sp, r7 8000298: bd80 pop {r7, pc} 0800029a : static inline uint16_t EEW_Write(uint8_t idx, uint16_t value) { 800029a: b580 push {r7, lr} 800029c: b082 sub sp, #8 800029e: af00 add r7, sp, #0 80002a0: 4603 mov r3, r0 80002a2: 460a mov r2, r1 80002a4: 71fb strb r3, [r7, #7] 80002a6: 4613 mov r3, r2 80002a8: 80bb strh r3, [r7, #4] return EE_WriteVariable(EEW_ADDR(idx), value); 80002aa: 79fb ldrb r3, [r7, #7] 80002ac: b29b uxth r3, r3 80002ae: 3301 adds r3, #1 80002b0: b29b uxth r3, r3 80002b2: 88ba ldrh r2, [r7, #4] 80002b4: 4611 mov r1, r2 80002b6: 4618 mov r0, r3 80002b8: f001 f9ea bl 8001690 80002bc: 4603 mov r3, r0 } 80002be: 4618 mov r0, r3 80002c0: 3708 adds r7, #8 80002c2: 46bd mov sp, r7 80002c4: bd80 pop {r7, pc} 080002c6 : extern uint16_t tramp; extern uint16_t tanem; extern uint16_t thanem; extern uint16_t trampman; bool toHex(char c1,char c2,char c3,char c4,uint16_t* retval){ 80002c6: b490 push {r4, r7} 80002c8: b082 sub sp, #8 80002ca: af00 add r7, sp, #0 80002cc: 4604 mov r4, r0 80002ce: 4608 mov r0, r1 80002d0: 4611 mov r1, r2 80002d2: 461a mov r2, r3 80002d4: 4623 mov r3, r4 80002d6: 71fb strb r3, [r7, #7] 80002d8: 4603 mov r3, r0 80002da: 71bb strb r3, [r7, #6] 80002dc: 460b mov r3, r1 80002de: 717b strb r3, [r7, #5] 80002e0: 4613 mov r3, r2 80002e2: 713b strb r3, [r7, #4] if((c1>='0')&&(c1<='9')){ 80002e4: 79fb ldrb r3, [r7, #7] 80002e6: 2b2f cmp r3, #47 @ 0x2f 80002e8: d906 bls.n 80002f8 80002ea: 79fb ldrb r3, [r7, #7] 80002ec: 2b39 cmp r3, #57 @ 0x39 80002ee: d803 bhi.n 80002f8 c1-='0'; 80002f0: 79fb ldrb r3, [r7, #7] 80002f2: 3b30 subs r3, #48 @ 0x30 80002f4: 71fb strb r3, [r7, #7] 80002f6: e00b b.n 8000310 }else if((c1>='a')&&(c1<='f')){ 80002f8: 79fb ldrb r3, [r7, #7] 80002fa: 2b60 cmp r3, #96 @ 0x60 80002fc: d906 bls.n 800030c 80002fe: 79fb ldrb r3, [r7, #7] 8000300: 2b66 cmp r3, #102 @ 0x66 8000302: d803 bhi.n 800030c c1=(c1-'a')+10; 8000304: 79fb ldrb r3, [r7, #7] 8000306: 3b57 subs r3, #87 @ 0x57 8000308: 71fb strb r3, [r7, #7] 800030a: e001 b.n 8000310 }else return false; 800030c: 2300 movs r3, #0 800030e: e070 b.n 80003f2 if((c2>='0')&&(c2<='9')){ 8000310: 79bb ldrb r3, [r7, #6] 8000312: 2b2f cmp r3, #47 @ 0x2f 8000314: d906 bls.n 8000324 8000316: 79bb ldrb r3, [r7, #6] 8000318: 2b39 cmp r3, #57 @ 0x39 800031a: d803 bhi.n 8000324 c2-='0'; 800031c: 79bb ldrb r3, [r7, #6] 800031e: 3b30 subs r3, #48 @ 0x30 8000320: 71bb strb r3, [r7, #6] 8000322: e00b b.n 800033c }else if((c2>='a')&&(c2<='f')){ 8000324: 79bb ldrb r3, [r7, #6] 8000326: 2b60 cmp r3, #96 @ 0x60 8000328: d906 bls.n 8000338 800032a: 79bb ldrb r3, [r7, #6] 800032c: 2b66 cmp r3, #102 @ 0x66 800032e: d803 bhi.n 8000338 c2=(c2-'a')+10; 8000330: 79bb ldrb r3, [r7, #6] 8000332: 3b57 subs r3, #87 @ 0x57 8000334: 71bb strb r3, [r7, #6] 8000336: e001 b.n 800033c }else return false; 8000338: 2300 movs r3, #0 800033a: e05a b.n 80003f2 if((c3>='0')&&(c3<='9')){ 800033c: 797b ldrb r3, [r7, #5] 800033e: 2b2f cmp r3, #47 @ 0x2f 8000340: d906 bls.n 8000350 8000342: 797b ldrb r3, [r7, #5] 8000344: 2b39 cmp r3, #57 @ 0x39 8000346: d803 bhi.n 8000350 c3-='0'; 8000348: 797b ldrb r3, [r7, #5] 800034a: 3b30 subs r3, #48 @ 0x30 800034c: 717b strb r3, [r7, #5] 800034e: e00b b.n 8000368 }else if((c3>='a')&&(c3<='f')){ 8000350: 797b ldrb r3, [r7, #5] 8000352: 2b60 cmp r3, #96 @ 0x60 8000354: d906 bls.n 8000364 8000356: 797b ldrb r3, [r7, #5] 8000358: 2b66 cmp r3, #102 @ 0x66 800035a: d803 bhi.n 8000364 c3=(c3-'a')+10; 800035c: 797b ldrb r3, [r7, #5] 800035e: 3b57 subs r3, #87 @ 0x57 8000360: 717b strb r3, [r7, #5] 8000362: e001 b.n 8000368 }else return false; 8000364: 2300 movs r3, #0 8000366: e044 b.n 80003f2 if((c4>='0')&&(c4<='9')){ 8000368: 793b ldrb r3, [r7, #4] 800036a: 2b2f cmp r3, #47 @ 0x2f 800036c: d906 bls.n 800037c 800036e: 793b ldrb r3, [r7, #4] 8000370: 2b39 cmp r3, #57 @ 0x39 8000372: d803 bhi.n 800037c c4-='0'; 8000374: 793b ldrb r3, [r7, #4] 8000376: 3b30 subs r3, #48 @ 0x30 8000378: 713b strb r3, [r7, #4] 800037a: e00b b.n 8000394 }else if((c4>='a')&&(c4<='f')){ 800037c: 793b ldrb r3, [r7, #4] 800037e: 2b60 cmp r3, #96 @ 0x60 8000380: d906 bls.n 8000390 8000382: 793b ldrb r3, [r7, #4] 8000384: 2b66 cmp r3, #102 @ 0x66 8000386: d803 bhi.n 8000390 c4=(c4-'a')+10; 8000388: 793b ldrb r3, [r7, #4] 800038a: 3b57 subs r3, #87 @ 0x57 800038c: 713b strb r3, [r7, #4] 800038e: e001 b.n 8000394 }else return false; 8000390: 2300 movs r3, #0 8000392: e02e b.n 80003f2 *retval=c1; 8000394: 79fb ldrb r3, [r7, #7] 8000396: b29a uxth r2, r3 8000398: 693b ldr r3, [r7, #16] 800039a: 801a strh r2, [r3, #0] *retval*=16; 800039c: 693b ldr r3, [r7, #16] 800039e: 881b ldrh r3, [r3, #0] 80003a0: 011b lsls r3, r3, #4 80003a2: b29a uxth r2, r3 80003a4: 693b ldr r3, [r7, #16] 80003a6: 801a strh r2, [r3, #0] *retval+=c2; 80003a8: 693b ldr r3, [r7, #16] 80003aa: 881a ldrh r2, [r3, #0] 80003ac: 79bb ldrb r3, [r7, #6] 80003ae: b29b uxth r3, r3 80003b0: 4413 add r3, r2 80003b2: b29a uxth r2, r3 80003b4: 693b ldr r3, [r7, #16] 80003b6: 801a strh r2, [r3, #0] *retval*=16; 80003b8: 693b ldr r3, [r7, #16] 80003ba: 881b ldrh r3, [r3, #0] 80003bc: 011b lsls r3, r3, #4 80003be: b29a uxth r2, r3 80003c0: 693b ldr r3, [r7, #16] 80003c2: 801a strh r2, [r3, #0] *retval+=c3; 80003c4: 693b ldr r3, [r7, #16] 80003c6: 881a ldrh r2, [r3, #0] 80003c8: 797b ldrb r3, [r7, #5] 80003ca: b29b uxth r3, r3 80003cc: 4413 add r3, r2 80003ce: b29a uxth r2, r3 80003d0: 693b ldr r3, [r7, #16] 80003d2: 801a strh r2, [r3, #0] *retval*=16; 80003d4: 693b ldr r3, [r7, #16] 80003d6: 881b ldrh r3, [r3, #0] 80003d8: 011b lsls r3, r3, #4 80003da: b29a uxth r2, r3 80003dc: 693b ldr r3, [r7, #16] 80003de: 801a strh r2, [r3, #0] *retval+=c4; 80003e0: 693b ldr r3, [r7, #16] 80003e2: 881a ldrh r2, [r3, #0] 80003e4: 793b ldrb r3, [r7, #4] 80003e6: b29b uxth r3, r3 80003e8: 4413 add r3, r2 80003ea: b29a uxth r2, r3 80003ec: 693b ldr r3, [r7, #16] 80003ee: 801a strh r2, [r3, #0] return true; 80003f0: 2301 movs r3, #1 } 80003f2: 4618 mov r0, r3 80003f4: 3708 adds r7, #8 80003f6: 46bd mov sp, r7 80003f8: bc90 pop {r4, r7} 80003fa: 4770 bx lr 080003fc : void manageCDC(void){ 80003fc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8000400: b0c1 sub sp, #260 @ 0x104 8000402: af06 add r7, sp, #24 uint16_t val; uint16_t st; uint16_t eeadd; uint8_t i; if (CDC_Available()) { 8000404: f00d fb9e bl 800db44 8000408: 4603 mov r3, r0 800040a: 2b00 cmp r3, #0 800040c: f000 86c8 beq.w 80011a0 int rx = CDC_ReadByte(); 8000410: f00d fbac bl 800db6c 8000414: f8c7 00e0 str.w r0, [r7, #224] @ 0xe0 if (rx < 0) return; 8000418: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800041c: 2b00 cmp r3, #0 800041e: f2c0 86be blt.w 800119e //uint8_t out = (uint8_t)c; //if (out >= 'a' && out <= 'z') out -= 32; // to upper rxbuf[rxidx]=rx; 8000422: 4bbd ldr r3, [pc, #756] @ (8000718 ) 8000424: 781b ldrb r3, [r3, #0] 8000426: 461a mov r2, r3 8000428: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800042c: b2d9 uxtb r1, r3 800042e: 4bbb ldr r3, [pc, #748] @ (800071c ) 8000430: 5499 strb r1, [r3, r2] while (CDC_Transmit_FS(&rxbuf[rxidx], 1) == USBD_BUSY);//echo 8000432: bf00 nop 8000434: 4bb8 ldr r3, [pc, #736] @ (8000718 ) 8000436: 781b ldrb r3, [r3, #0] 8000438: 461a mov r2, r3 800043a: 4bb8 ldr r3, [pc, #736] @ (800071c ) 800043c: 4413 add r3, r2 800043e: 2101 movs r1, #1 8000440: 4618 mov r0, r3 8000442: f00d fc55 bl 800dcf0 8000446: 4603 mov r3, r0 8000448: 2b01 cmp r3, #1 800044a: d0f3 beq.n 8000434 if((rx==0x0d)||(rx==0x0a)){ 800044c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8000450: 2b0d cmp r3, #13 8000452: d004 beq.n 800045e 8000454: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8000458: 2b0a cmp r3, #10 800045a: f040 8699 bne.w 8001190 if(rxidx){ 800045e: 4bae ldr r3, [pc, #696] @ (8000718 ) 8000460: 781b ldrb r3, [r3, #0] 8000462: 2b00 cmp r3, #0 8000464: f000 8690 beq.w 8001188 switch(rxbuf[0]){ 8000468: 4bac ldr r3, [pc, #688] @ (800071c ) 800046a: 781b ldrb r3, [r3, #0] 800046c: 3b49 subs r3, #73 @ 0x49 800046e: 2b24 cmp r3, #36 @ 0x24 8000470: f200 8678 bhi.w 8001164 8000474: a201 add r2, pc, #4 @ (adr r2, 800047c ) 8000476: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800047a: bf00 nop 800047c: 080006c7 .word 0x080006c7 8000480: 08001165 .word 0x08001165 8000484: 08001165 .word 0x08001165 8000488: 08001165 .word 0x08001165 800048c: 08001165 .word 0x08001165 8000490: 08001165 .word 0x08001165 8000494: 08001165 .word 0x08001165 8000498: 08001165 .word 0x08001165 800049c: 08001165 .word 0x08001165 80004a0: 08001165 .word 0x08001165 80004a4: 08001165 .word 0x08001165 80004a8: 08001165 .word 0x08001165 80004ac: 08001165 .word 0x08001165 80004b0: 08001165 .word 0x08001165 80004b4: 08001165 .word 0x08001165 80004b8: 08001165 .word 0x08001165 80004bc: 08001165 .word 0x08001165 80004c0: 08001165 .word 0x08001165 80004c4: 08001165 .word 0x08001165 80004c8: 08001165 .word 0x08001165 80004cc: 08001165 .word 0x08001165 80004d0: 08001165 .word 0x08001165 80004d4: 08001165 .word 0x08001165 80004d8: 08001165 .word 0x08001165 80004dc: 08001165 .word 0x08001165 80004e0: 080006eb .word 0x080006eb 80004e4: 08001165 .word 0x08001165 80004e8: 08001165 .word 0x08001165 80004ec: 080009f5 .word 0x080009f5 80004f0: 08001165 .word 0x08001165 80004f4: 08001165 .word 0x08001165 80004f8: 08001165 .word 0x08001165 80004fc: 08000511 .word 0x08000511 8000500: 08001165 .word 0x08001165 8000504: 08001165 .word 0x08001165 8000508: 08001165 .word 0x08001165 800050c: 080007ad .word 0x080007ad case 'i': sprintf((char*)s,"info\n"); 8000510: f107 0310 add.w r3, r7, #16 8000514: 4982 ldr r1, [pc, #520] @ (8000720 ) 8000516: 4618 mov r0, r3 8000518: f00d ffc8 bl 800e4ac while (CDC_Transmit_FS(s, 5) == USBD_BUSY); 800051c: bf00 nop 800051e: f107 0310 add.w r3, r7, #16 8000522: 2105 movs r1, #5 8000524: 4618 mov r0, r3 8000526: f00d fbe3 bl 800dcf0 800052a: 4603 mov r3, r0 800052c: 2b01 cmp r3, #1 800052e: d0f6 beq.n 800051e sprintf((char*)s,"\npwm %d%d%d%d%d%d%d%d",IsPwmRunning(timMot1,FWMot1),IsPwmRunning(timMot1,BWMot1),IsPwmRunning(timMot2,FWMot2),IsPwmRunning(timMot2,BWMot2),IsPwmRunning(timMot3,FWMot3),IsPwmRunning(timMot3,BWMot3),IsPwmRunning(timMot4,FWMot4),IsPwmRunning(timMot4,BWMot4)); 8000530: 2100 movs r1, #0 8000532: 487c ldr r0, [pc, #496] @ (8000724 ) 8000534: f003 ffb4 bl 80044a0 8000538: 4603 mov r3, r0 800053a: 4698 mov r8, r3 800053c: 2104 movs r1, #4 800053e: 4879 ldr r0, [pc, #484] @ (8000724 ) 8000540: f003 ffae bl 80044a0 8000544: 4603 mov r3, r0 8000546: 4699 mov r9, r3 8000548: 2108 movs r1, #8 800054a: 4876 ldr r0, [pc, #472] @ (8000724 ) 800054c: f003 ffa8 bl 80044a0 8000550: 4603 mov r3, r0 8000552: 461c mov r4, r3 8000554: 210c movs r1, #12 8000556: 4873 ldr r0, [pc, #460] @ (8000724 ) 8000558: f003 ffa2 bl 80044a0 800055c: 4603 mov r3, r0 800055e: 461d mov r5, r3 8000560: 2100 movs r1, #0 8000562: 4871 ldr r0, [pc, #452] @ (8000728 ) 8000564: f003 ff9c bl 80044a0 8000568: 4603 mov r3, r0 800056a: 461e mov r6, r3 800056c: 2104 movs r1, #4 800056e: 486e ldr r0, [pc, #440] @ (8000728 ) 8000570: f003 ff96 bl 80044a0 8000574: 4603 mov r3, r0 8000576: 607b str r3, [r7, #4] 8000578: 2108 movs r1, #8 800057a: 486b ldr r0, [pc, #428] @ (8000728 ) 800057c: f003 ff90 bl 80044a0 8000580: 4603 mov r3, r0 8000582: 603b str r3, [r7, #0] 8000584: 210c movs r1, #12 8000586: 4868 ldr r0, [pc, #416] @ (8000728 ) 8000588: f003 ff8a bl 80044a0 800058c: 4603 mov r3, r0 800058e: f107 0010 add.w r0, r7, #16 8000592: 9305 str r3, [sp, #20] 8000594: 683a ldr r2, [r7, #0] 8000596: 9204 str r2, [sp, #16] 8000598: 687b ldr r3, [r7, #4] 800059a: 9303 str r3, [sp, #12] 800059c: 9602 str r6, [sp, #8] 800059e: 9501 str r5, [sp, #4] 80005a0: 9400 str r4, [sp, #0] 80005a2: 464b mov r3, r9 80005a4: 4642 mov r2, r8 80005a6: 4961 ldr r1, [pc, #388] @ (800072c ) 80005a8: f00d ff80 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 80005ac: bf00 nop 80005ae: f107 0310 add.w r3, r7, #16 80005b2: 4618 mov r0, r3 80005b4: f7ff fdca bl 800014c 80005b8: 4603 mov r3, r0 80005ba: b29a uxth r2, r3 80005bc: f107 0310 add.w r3, r7, #16 80005c0: 4611 mov r1, r2 80005c2: 4618 mov r0, r3 80005c4: f00d fb94 bl 800dcf0 80005c8: 4603 mov r3, r0 80005ca: 2b01 cmp r3, #1 80005cc: d0ef beq.n 80005ae sprintf((char*)s,"\n0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx",(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,FWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,BWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,FWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,BWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,FWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,BWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,FWMot4),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,BWMot4)); 80005ce: 4b55 ldr r3, [pc, #340] @ (8000724 ) 80005d0: 681b ldr r3, [r3, #0] 80005d2: 6b5b ldr r3, [r3, #52] @ 0x34 80005d4: 607b str r3, [r7, #4] 80005d6: 4b53 ldr r3, [pc, #332] @ (8000724 ) 80005d8: 681b ldr r3, [r3, #0] 80005da: 6b99 ldr r1, [r3, #56] @ 0x38 80005dc: 6039 str r1, [r7, #0] 80005de: 4b51 ldr r3, [pc, #324] @ (8000724 ) 80005e0: 681b ldr r3, [r3, #0] 80005e2: 6bdb ldr r3, [r3, #60] @ 0x3c 80005e4: 4a4f ldr r2, [pc, #316] @ (8000724 ) 80005e6: 6812 ldr r2, [r2, #0] 80005e8: 6c12 ldr r2, [r2, #64] @ 0x40 80005ea: 494f ldr r1, [pc, #316] @ (8000728 ) 80005ec: 6809 ldr r1, [r1, #0] 80005ee: 6b49 ldr r1, [r1, #52] @ 0x34 80005f0: 484d ldr r0, [pc, #308] @ (8000728 ) 80005f2: 6800 ldr r0, [r0, #0] 80005f4: 6b80 ldr r0, [r0, #56] @ 0x38 80005f6: 4c4c ldr r4, [pc, #304] @ (8000728 ) 80005f8: 6824 ldr r4, [r4, #0] 80005fa: 6be4 ldr r4, [r4, #60] @ 0x3c 80005fc: 4d4a ldr r5, [pc, #296] @ (8000728 ) 80005fe: 682d ldr r5, [r5, #0] 8000600: 6c2d ldr r5, [r5, #64] @ 0x40 8000602: f107 0610 add.w r6, r7, #16 8000606: 9505 str r5, [sp, #20] 8000608: 9404 str r4, [sp, #16] 800060a: 9003 str r0, [sp, #12] 800060c: 9102 str r1, [sp, #8] 800060e: 9201 str r2, [sp, #4] 8000610: 9300 str r3, [sp, #0] 8000612: 683b ldr r3, [r7, #0] 8000614: 687a ldr r2, [r7, #4] 8000616: 4946 ldr r1, [pc, #280] @ (8000730 ) 8000618: 4630 mov r0, r6 800061a: f00d ff47 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 800061e: bf00 nop 8000620: f107 0310 add.w r3, r7, #16 8000624: 4618 mov r0, r3 8000626: f7ff fd91 bl 800014c 800062a: 4603 mov r3, r0 800062c: b29a uxth r2, r3 800062e: f107 0310 add.w r3, r7, #16 8000632: 4611 mov r1, r2 8000634: 4618 mov r0, r3 8000636: f00d fb5b bl 800dcf0 800063a: 4603 mov r3, r0 800063c: 2b01 cmp r3, #1 800063e: d0ef beq.n 8000620 sprintf((char*)s,"\nP=0x%x ch4=%05d ch5=%05d ch6=%05d ch7=%05d ch8=%05d",pulsanti,ch4,ch5,ch6,ch7,ch8); 8000640: 4b3c ldr r3, [pc, #240] @ (8000734 ) 8000642: 781b ldrb r3, [r3, #0] 8000644: 461d mov r5, r3 8000646: 4b3c ldr r3, [pc, #240] @ (8000738 ) 8000648: 881b ldrh r3, [r3, #0] 800064a: 461e mov r6, r3 800064c: 4b3b ldr r3, [pc, #236] @ (800073c ) 800064e: 881b ldrh r3, [r3, #0] 8000650: 461a mov r2, r3 8000652: 4b3b ldr r3, [pc, #236] @ (8000740 ) 8000654: 881b ldrh r3, [r3, #0] 8000656: 4619 mov r1, r3 8000658: 4b3a ldr r3, [pc, #232] @ (8000744 ) 800065a: 881b ldrh r3, [r3, #0] 800065c: 461c mov r4, r3 800065e: 4b3a ldr r3, [pc, #232] @ (8000748 ) 8000660: 881b ldrh r3, [r3, #0] 8000662: f107 0010 add.w r0, r7, #16 8000666: 9303 str r3, [sp, #12] 8000668: 9402 str r4, [sp, #8] 800066a: 9101 str r1, [sp, #4] 800066c: 9200 str r2, [sp, #0] 800066e: 4633 mov r3, r6 8000670: 462a mov r2, r5 8000672: 4936 ldr r1, [pc, #216] @ (800074c ) 8000674: f00d ff1a bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000678: bf00 nop 800067a: f107 0310 add.w r3, r7, #16 800067e: 4618 mov r0, r3 8000680: f7ff fd64 bl 800014c 8000684: 4603 mov r3, r0 8000686: b29a uxth r2, r3 8000688: f107 0310 add.w r3, r7, #16 800068c: 4611 mov r1, r2 800068e: 4618 mov r0, r3 8000690: f00d fb2e bl 800dcf0 8000694: 4603 mov r3, r0 8000696: 2b01 cmp r3, #1 8000698: d0ef beq.n 800067a sprintf((char*)s,"\nstCiclo=%05d stPulsanti=%05d",stCiclo,stPulsanti); 800069a: 4b2d ldr r3, [pc, #180] @ (8000750 ) 800069c: 781b ldrb r3, [r3, #0] 800069e: 461a mov r2, r3 80006a0: 4b2c ldr r3, [pc, #176] @ (8000754 ) 80006a2: 781b ldrb r3, [r3, #0] 80006a4: f107 0010 add.w r0, r7, #16 80006a8: 492b ldr r1, [pc, #172] @ (8000758 ) 80006aa: f00d feff bl 800e4ac while (CDC_Transmit_FS(s, 31) == USBD_BUSY); 80006ae: bf00 nop 80006b0: f107 0310 add.w r3, r7, #16 80006b4: 211f movs r1, #31 80006b6: 4618 mov r0, r3 80006b8: f00d fb1a bl 800dcf0 80006bc: 4603 mov r3, r0 80006be: 2b01 cmp r3, #1 80006c0: d0f6 beq.n 80006b0 break; 80006c2: f000 bd61 b.w 8001188 case 'I': sprintf((char*)s,"\nID000000"); 80006c6: f107 0310 add.w r3, r7, #16 80006ca: 4924 ldr r1, [pc, #144] @ (800075c ) 80006cc: 4618 mov r0, r3 80006ce: f00d feed bl 800e4ac while (CDC_Transmit_FS(s, 9) == USBD_BUSY); 80006d2: bf00 nop 80006d4: f107 0310 add.w r3, r7, #16 80006d8: 2109 movs r1, #9 80006da: 4618 mov r0, r3 80006dc: f00d fb08 bl 800dcf0 80006e0: 4603 mov r3, r0 80006e2: 2b01 cmp r3, #1 80006e4: d0f6 beq.n 80006d4 break; 80006e6: f000 bd4f b.w 8001188 case 'b': if(rxidx==2){ 80006ea: 4b0b ldr r3, [pc, #44] @ (8000718 ) 80006ec: 781b ldrb r3, [r3, #0] 80006ee: 2b02 cmp r3, #2 80006f0: d14a bne.n 8000788 if(rxbuf[1]=='0'){ 80006f2: 4b0a ldr r3, [pc, #40] @ (800071c ) 80006f4: 785b ldrb r3, [r3, #1] 80006f6: 2b30 cmp r3, #48 @ 0x30 80006f8: d104 bne.n 8000704 nobuz=false; 80006fa: 4b19 ldr r3, [pc, #100] @ (8000760 ) 80006fc: 2200 movs r2, #0 80006fe: 701a strb r2, [r3, #0] } }else{ sprintf((char*)s,"\nb0|1"); while (CDC_Transmit_FS(s, 5) == USBD_BUSY); } break; 8000700: f000 bd42 b.w 8001188 }else if(rxbuf[1]=='1'){ 8000704: 4b05 ldr r3, [pc, #20] @ (800071c ) 8000706: 785b ldrb r3, [r3, #1] 8000708: 2b31 cmp r3, #49 @ 0x31 800070a: d12b bne.n 8000764 nobuz=true; 800070c: 4b14 ldr r3, [pc, #80] @ (8000760 ) 800070e: 2201 movs r2, #1 8000710: 701a strb r2, [r3, #0] break; 8000712: f000 bd39 b.w 8001188 8000716: bf00 nop 8000718: 20000234 .word 0x20000234 800071c: 20000238 .word 0x20000238 8000720: 0800ee24 .word 0x0800ee24 8000724: 20000318 .word 0x20000318 8000728: 20000360 .word 0x20000360 800072c: 0800ee2c .word 0x0800ee2c 8000730: 0800ee44 .word 0x0800ee44 8000734: 200003f0 .word 0x200003f0 8000738: 2000022a .word 0x2000022a 800073c: 2000022c .word 0x2000022c 8000740: 2000022e .word 0x2000022e 8000744: 20000230 .word 0x20000230 8000748: 20000232 .word 0x20000232 800074c: 0800ee78 .word 0x0800ee78 8000750: 20000456 .word 0x20000456 8000754: 20000454 .word 0x20000454 8000758: 0800eeb0 .word 0x0800eeb0 800075c: 0800eed0 .word 0x0800eed0 8000760: 20000458 .word 0x20000458 sprintf((char*)s,"\nb0|1"); 8000764: f107 0310 add.w r3, r7, #16 8000768: 499b ldr r1, [pc, #620] @ (80009d8 ) 800076a: 4618 mov r0, r3 800076c: f00d fe9e bl 800e4ac while (CDC_Transmit_FS(s, 5) == USBD_BUSY); 8000770: bf00 nop 8000772: f107 0310 add.w r3, r7, #16 8000776: 2105 movs r1, #5 8000778: 4618 mov r0, r3 800077a: f00d fab9 bl 800dcf0 800077e: 4603 mov r3, r0 8000780: 2b01 cmp r3, #1 8000782: d0f6 beq.n 8000772 break; 8000784: f000 bd00 b.w 8001188 sprintf((char*)s,"\nb0|1"); 8000788: f107 0310 add.w r3, r7, #16 800078c: 4992 ldr r1, [pc, #584] @ (80009d8 ) 800078e: 4618 mov r0, r3 8000790: f00d fe8c bl 800e4ac while (CDC_Transmit_FS(s, 5) == USBD_BUSY); 8000794: bf00 nop 8000796: f107 0310 add.w r3, r7, #16 800079a: 2105 movs r1, #5 800079c: 4618 mov r0, r3 800079e: f00d faa7 bl 800dcf0 80007a2: 4603 mov r3, r0 80007a4: 2b01 cmp r3, #1 80007a6: d0f6 beq.n 8000796 break; 80007a8: f000 bcee b.w 8001188 case 'm': if(rxidx==8){ 80007ac: 4b8b ldr r3, [pc, #556] @ (80009dc ) 80007ae: 781b ldrb r3, [r3, #0] 80007b0: 2b08 cmp r3, #8 80007b2: f040 80fe bne.w 80009b2 if((rxbuf[1]>='1')&&(rxbuf[1]<='4')){ 80007b6: 4b8a ldr r3, [pc, #552] @ (80009e0 ) 80007b8: 785b ldrb r3, [r3, #1] 80007ba: 2b30 cmp r3, #48 @ 0x30 80007bc: f240 80e8 bls.w 8000990 80007c0: 4b87 ldr r3, [pc, #540] @ (80009e0 ) 80007c2: 785b ldrb r3, [r3, #1] 80007c4: 2b34 cmp r3, #52 @ 0x34 80007c6: f200 80e3 bhi.w 8000990 mot=rxbuf[1]-='0'; 80007ca: 4b85 ldr r3, [pc, #532] @ (80009e0 ) 80007cc: 785b ldrb r3, [r3, #1] 80007ce: 3b30 subs r3, #48 @ 0x30 80007d0: b2da uxtb r2, r3 80007d2: 4b83 ldr r3, [pc, #524] @ (80009e0 ) 80007d4: 705a strb r2, [r3, #1] 80007d6: 4b82 ldr r3, [pc, #520] @ (80009e0 ) 80007d8: 785b ldrb r3, [r3, #1] 80007da: f887 30df strb.w r3, [r7, #223] @ 0xdf if(rxbuf[2]=='f'){ 80007de: 4b80 ldr r3, [pc, #512] @ (80009e0 ) 80007e0: 789b ldrb r3, [r3, #2] 80007e2: 2b66 cmp r3, #102 @ 0x66 80007e4: d103 bne.n 80007ee dir=FW; 80007e6: 2300 movs r3, #0 80007e8: f887 30e7 strb.w r3, [r7, #231] @ 0xe7 80007ec: e019 b.n 8000822 }else if(rxbuf[2]=='b'){ 80007ee: 4b7c ldr r3, [pc, #496] @ (80009e0 ) 80007f0: 789b ldrb r3, [r3, #2] 80007f2: 2b62 cmp r3, #98 @ 0x62 80007f4: d103 bne.n 80007fe dir=BW; 80007f6: 2301 movs r3, #1 80007f8: f887 30e7 strb.w r3, [r7, #231] @ 0xe7 80007fc: e011 b.n 8000822 }else{ sprintf((char*)s,"\n?mnsvvvvv s=f|b");//m nmotore senso valore 80007fe: f107 0310 add.w r3, r7, #16 8000802: 4978 ldr r1, [pc, #480] @ (80009e4 ) 8000804: 4618 mov r0, r3 8000806: f00d fe51 bl 800e4ac while (CDC_Transmit_FS(s, 16) == USBD_BUSY); 800080a: bf00 nop 800080c: f107 0310 add.w r3, r7, #16 8000810: 2110 movs r1, #16 8000812: 4618 mov r0, r3 8000814: f00d fa6c bl 800dcf0 8000818: 4603 mov r3, r0 800081a: 2b01 cmp r3, #1 800081c: d0f6 beq.n 800080c break; 800081e: f000 bcb3 b.w 8001188 } if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){ 8000822: 4b6f ldr r3, [pc, #444] @ (80009e0 ) 8000824: 78db ldrb r3, [r3, #3] 8000826: 2b2f cmp r3, #47 @ 0x2f 8000828: f240 80a1 bls.w 800096e 800082c: 4b6c ldr r3, [pc, #432] @ (80009e0 ) 800082e: 78db ldrb r3, [r3, #3] 8000830: 2b39 cmp r3, #57 @ 0x39 8000832: f200 809c bhi.w 800096e 8000836: 4b6a ldr r3, [pc, #424] @ (80009e0 ) 8000838: 791b ldrb r3, [r3, #4] 800083a: 2b2f cmp r3, #47 @ 0x2f 800083c: f240 8097 bls.w 800096e 8000840: 4b67 ldr r3, [pc, #412] @ (80009e0 ) 8000842: 791b ldrb r3, [r3, #4] 8000844: 2b39 cmp r3, #57 @ 0x39 8000846: f200 8092 bhi.w 800096e 800084a: 4b65 ldr r3, [pc, #404] @ (80009e0 ) 800084c: 795b ldrb r3, [r3, #5] 800084e: 2b2f cmp r3, #47 @ 0x2f 8000850: f240 808d bls.w 800096e 8000854: 4b62 ldr r3, [pc, #392] @ (80009e0 ) 8000856: 795b ldrb r3, [r3, #5] 8000858: 2b39 cmp r3, #57 @ 0x39 800085a: f200 8088 bhi.w 800096e 800085e: 4b60 ldr r3, [pc, #384] @ (80009e0 ) 8000860: 799b ldrb r3, [r3, #6] 8000862: 2b2f cmp r3, #47 @ 0x2f 8000864: f240 8083 bls.w 800096e 8000868: 4b5d ldr r3, [pc, #372] @ (80009e0 ) 800086a: 799b ldrb r3, [r3, #6] 800086c: 2b39 cmp r3, #57 @ 0x39 800086e: d87e bhi.n 800096e 8000870: 4b5b ldr r3, [pc, #364] @ (80009e0 ) 8000872: 79db ldrb r3, [r3, #7] 8000874: 2b2f cmp r3, #47 @ 0x2f 8000876: d97a bls.n 800096e 8000878: 4b59 ldr r3, [pc, #356] @ (80009e0 ) 800087a: 79db ldrb r3, [r3, #7] 800087c: 2b39 cmp r3, #57 @ 0x39 800087e: d876 bhi.n 800096e dm=rxbuf[3]-='0'; 8000880: 4b57 ldr r3, [pc, #348] @ (80009e0 ) 8000882: 78db ldrb r3, [r3, #3] 8000884: 3b30 subs r3, #48 @ 0x30 8000886: b2da uxtb r2, r3 8000888: 4b55 ldr r3, [pc, #340] @ (80009e0 ) 800088a: 70da strb r2, [r3, #3] 800088c: 4b54 ldr r3, [pc, #336] @ (80009e0 ) 800088e: 78db ldrb r3, [r3, #3] 8000890: f887 30de strb.w r3, [r7, #222] @ 0xde m=rxbuf[4]-='0'; 8000894: 4b52 ldr r3, [pc, #328] @ (80009e0 ) 8000896: 791b ldrb r3, [r3, #4] 8000898: 3b30 subs r3, #48 @ 0x30 800089a: b2da uxtb r2, r3 800089c: 4b50 ldr r3, [pc, #320] @ (80009e0 ) 800089e: 711a strb r2, [r3, #4] 80008a0: 4b4f ldr r3, [pc, #316] @ (80009e0 ) 80008a2: 791b ldrb r3, [r3, #4] 80008a4: f887 30dd strb.w r3, [r7, #221] @ 0xdd c=rxbuf[5]-='0'; 80008a8: 4b4d ldr r3, [pc, #308] @ (80009e0 ) 80008aa: 795b ldrb r3, [r3, #5] 80008ac: 3b30 subs r3, #48 @ 0x30 80008ae: b2da uxtb r2, r3 80008b0: 4b4b ldr r3, [pc, #300] @ (80009e0 ) 80008b2: 715a strb r2, [r3, #5] 80008b4: 4b4a ldr r3, [pc, #296] @ (80009e0 ) 80008b6: 795b ldrb r3, [r3, #5] 80008b8: f887 30dc strb.w r3, [r7, #220] @ 0xdc d=rxbuf[6]-='0'; 80008bc: 4b48 ldr r3, [pc, #288] @ (80009e0 ) 80008be: 799b ldrb r3, [r3, #6] 80008c0: 3b30 subs r3, #48 @ 0x30 80008c2: b2da uxtb r2, r3 80008c4: 4b46 ldr r3, [pc, #280] @ (80009e0 ) 80008c6: 719a strb r2, [r3, #6] 80008c8: 4b45 ldr r3, [pc, #276] @ (80009e0 ) 80008ca: 799b ldrb r3, [r3, #6] 80008cc: f887 30db strb.w r3, [r7, #219] @ 0xdb u=rxbuf[7]-='0'; 80008d0: 4b43 ldr r3, [pc, #268] @ (80009e0 ) 80008d2: 79db ldrb r3, [r3, #7] 80008d4: 3b30 subs r3, #48 @ 0x30 80008d6: b2da uxtb r2, r3 80008d8: 4b41 ldr r3, [pc, #260] @ (80009e0 ) 80008da: 71da strb r2, [r3, #7] 80008dc: 4b40 ldr r3, [pc, #256] @ (80009e0 ) 80008de: 79db ldrb r3, [r3, #7] 80008e0: f887 30da strb.w r3, [r7, #218] @ 0xda val=dm; 80008e4: f897 30de ldrb.w r3, [r7, #222] @ 0xde 80008e8: b29b uxth r3, r3 80008ea: 81fb strh r3, [r7, #14] val*=10; 80008ec: 89fb ldrh r3, [r7, #14] 80008ee: 461a mov r2, r3 80008f0: 0092 lsls r2, r2, #2 80008f2: 4413 add r3, r2 80008f4: 005b lsls r3, r3, #1 80008f6: b29b uxth r3, r3 80008f8: 81fb strh r3, [r7, #14] val+=m; 80008fa: f897 30dd ldrb.w r3, [r7, #221] @ 0xdd 80008fe: b29a uxth r2, r3 8000900: 89fb ldrh r3, [r7, #14] 8000902: 4413 add r3, r2 8000904: b29b uxth r3, r3 8000906: 81fb strh r3, [r7, #14] val*=10; 8000908: 89fb ldrh r3, [r7, #14] 800090a: 461a mov r2, r3 800090c: 0092 lsls r2, r2, #2 800090e: 4413 add r3, r2 8000910: 005b lsls r3, r3, #1 8000912: b29b uxth r3, r3 8000914: 81fb strh r3, [r7, #14] val+=c; 8000916: f897 30dc ldrb.w r3, [r7, #220] @ 0xdc 800091a: b29a uxth r2, r3 800091c: 89fb ldrh r3, [r7, #14] 800091e: 4413 add r3, r2 8000920: b29b uxth r3, r3 8000922: 81fb strh r3, [r7, #14] val*=10; 8000924: 89fb ldrh r3, [r7, #14] 8000926: 461a mov r2, r3 8000928: 0092 lsls r2, r2, #2 800092a: 4413 add r3, r2 800092c: 005b lsls r3, r3, #1 800092e: b29b uxth r3, r3 8000930: 81fb strh r3, [r7, #14] val+=d; 8000932: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8000936: b29a uxth r2, r3 8000938: 89fb ldrh r3, [r7, #14] 800093a: 4413 add r3, r2 800093c: b29b uxth r3, r3 800093e: 81fb strh r3, [r7, #14] val*=10; 8000940: 89fb ldrh r3, [r7, #14] 8000942: 461a mov r2, r3 8000944: 0092 lsls r2, r2, #2 8000946: 4413 add r3, r2 8000948: 005b lsls r3, r3, #1 800094a: b29b uxth r3, r3 800094c: 81fb strh r3, [r7, #14] val+=u; 800094e: f897 30da ldrb.w r3, [r7, #218] @ 0xda 8000952: b29a uxth r2, r3 8000954: 89fb ldrh r3, [r7, #14] 8000956: 4413 add r3, r2 8000958: b29b uxth r3, r3 800095a: 81fb strh r3, [r7, #14] SetMot(mot,dir,val); 800095c: 89fa ldrh r2, [r7, #14] 800095e: f897 10e7 ldrb.w r1, [r7, #231] @ 0xe7 8000962: f897 30df ldrb.w r3, [r7, #223] @ 0xdf 8000966: 4618 mov r0, r3 8000968: f003 fe10 bl 800458c if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){ 800096c: e032 b.n 80009d4 }else{ sprintf((char*)s,"\n?mnsvvvvv 00000>=vvvvv<=99999");//m nmotore senso valore 800096e: f107 0310 add.w r3, r7, #16 8000972: 491d ldr r1, [pc, #116] @ (80009e8 ) 8000974: 4618 mov r0, r3 8000976: f00d fd99 bl 800e4ac while (CDC_Transmit_FS(s, 19) == USBD_BUSY); 800097a: bf00 nop 800097c: f107 0310 add.w r3, r7, #16 8000980: 2113 movs r1, #19 8000982: 4618 mov r0, r3 8000984: f00d f9b4 bl 800dcf0 8000988: 4603 mov r3, r0 800098a: 2b01 cmp r3, #1 800098c: d0f6 beq.n 800097c if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){ 800098e: e021 b.n 80009d4 } }else{ sprintf((char*)s,"\n?mnsvvvvv 1>=m<=4");//m nmotore senso valore 8000990: f107 0310 add.w r3, r7, #16 8000994: 4915 ldr r1, [pc, #84] @ (80009ec ) 8000996: 4618 mov r0, r3 8000998: f00d fd88 bl 800e4ac while (CDC_Transmit_FS(s, 19) == USBD_BUSY); 800099c: bf00 nop 800099e: f107 0310 add.w r3, r7, #16 80009a2: 2113 movs r1, #19 80009a4: 4618 mov r0, r3 80009a6: f00d f9a3 bl 800dcf0 80009aa: 4603 mov r3, r0 80009ac: 2b01 cmp r3, #1 80009ae: d0f6 beq.n 800099e } }else{ sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore while (CDC_Transmit_FS(s, 10) == USBD_BUSY); } break; 80009b0: e3ea b.n 8001188 sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore 80009b2: f107 0310 add.w r3, r7, #16 80009b6: 490e ldr r1, [pc, #56] @ (80009f0 ) 80009b8: 4618 mov r0, r3 80009ba: f00d fd77 bl 800e4ac while (CDC_Transmit_FS(s, 10) == USBD_BUSY); 80009be: bf00 nop 80009c0: f107 0310 add.w r3, r7, #16 80009c4: 210a movs r1, #10 80009c6: 4618 mov r0, r3 80009c8: f00d f992 bl 800dcf0 80009cc: 4603 mov r3, r0 80009ce: 2b01 cmp r3, #1 80009d0: d0f6 beq.n 80009c0 break; 80009d2: e3d9 b.n 8001188 80009d4: e3d8 b.n 8001188 80009d6: bf00 nop 80009d8: 0800eedc .word 0x0800eedc 80009dc: 20000234 .word 0x20000234 80009e0: 20000238 .word 0x20000238 80009e4: 0800eee4 .word 0x0800eee4 80009e8: 0800eef8 .word 0x0800eef8 80009ec: 0800ef18 .word 0x0800ef18 80009f0: 0800ef2c .word 0x0800ef2c case 'e': if(rxidx>1){ 80009f4: 4bbb ldr r3, [pc, #748] @ (8000ce4 ) 80009f6: 781b ldrb r3, [r3, #0] 80009f8: 2b01 cmp r3, #1 80009fa: f240 839b bls.w 8001134 if(rxbuf[1]=='r'){ 80009fe: 4bba ldr r3, [pc, #744] @ (8000ce8 ) 8000a00: 785b ldrb r3, [r3, #1] 8000a02: 2b72 cmp r3, #114 @ 0x72 8000a04: f040 8086 bne.w 8000b14 if(rxidx==4){ 8000a08: 4bb6 ldr r3, [pc, #728] @ (8000ce4 ) 8000a0a: 781b ldrb r3, [r3, #0] 8000a0c: 2b04 cmp r3, #4 8000a0e: d169 bne.n 8000ae4 if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){ 8000a10: 4bb5 ldr r3, [pc, #724] @ (8000ce8 ) 8000a12: 789a ldrb r2, [r3, #2] 8000a14: 4bb4 ldr r3, [pc, #720] @ (8000ce8 ) 8000a16: 78d9 ldrb r1, [r3, #3] 8000a18: f107 030c add.w r3, r7, #12 8000a1c: 9300 str r3, [sp, #0] 8000a1e: 460b mov r3, r1 8000a20: 2130 movs r1, #48 @ 0x30 8000a22: 2030 movs r0, #48 @ 0x30 8000a24: f7ff fc4f bl 80002c6 8000a28: 4603 mov r3, r0 8000a2a: 2b00 cmp r3, #0 8000a2c: d042 beq.n 8000ab4 st=EEW_Read(eeadd, &val); 8000a2e: 89bb ldrh r3, [r7, #12] 8000a30: b2db uxtb r3, r3 8000a32: f107 020e add.w r2, r7, #14 8000a36: 4611 mov r1, r2 8000a38: 4618 mov r0, r3 8000a3a: f7ff fc1b bl 8000274 8000a3e: 4603 mov r3, r0 8000a40: f8a7 30d8 strh.w r3, [r7, #216] @ 0xd8 if (st == EE_OK){ 8000a44: f8b7 30d8 ldrh.w r3, [r7, #216] @ 0xd8 8000a48: 2b00 cmp r3, #0 8000a4a: d119 bne.n 8000a80 sprintf((char*)s,"\nee 0x%02x=0x%04x",eeadd,val); 8000a4c: 89bb ldrh r3, [r7, #12] 8000a4e: 461a mov r2, r3 8000a50: 89fb ldrh r3, [r7, #14] 8000a52: f107 0010 add.w r0, r7, #16 8000a56: 49a5 ldr r1, [pc, #660] @ (8000cec ) 8000a58: f00d fd28 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000a5c: bf00 nop 8000a5e: f107 0310 add.w r3, r7, #16 8000a62: 4618 mov r0, r3 8000a64: f7ff fb72 bl 800014c 8000a68: 4603 mov r3, r0 8000a6a: b29a uxth r2, r3 8000a6c: f107 0310 add.w r3, r7, #16 8000a70: 4611 mov r1, r2 8000a72: 4618 mov r0, r3 8000a74: f00d f93c bl 800dcf0 8000a78: 4603 mov r3, r0 8000a7a: 2b01 cmp r3, #1 8000a7c: d0ef beq.n 8000a5e } }else{ sprintf((char*)s,"\n?eraa | ewaavvvv"); while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); } break; 8000a7e: e382 b.n 8001186 sprintf((char*)s,"\nee read error %d",st); 8000a80: f8b7 20d8 ldrh.w r2, [r7, #216] @ 0xd8 8000a84: f107 0310 add.w r3, r7, #16 8000a88: 4999 ldr r1, [pc, #612] @ (8000cf0 ) 8000a8a: 4618 mov r0, r3 8000a8c: f00d fd0e bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000a90: bf00 nop 8000a92: f107 0310 add.w r3, r7, #16 8000a96: 4618 mov r0, r3 8000a98: f7ff fb58 bl 800014c 8000a9c: 4603 mov r3, r0 8000a9e: b29a uxth r2, r3 8000aa0: f107 0310 add.w r3, r7, #16 8000aa4: 4611 mov r1, r2 8000aa6: 4618 mov r0, r3 8000aa8: f00d f922 bl 800dcf0 8000aac: 4603 mov r3, r0 8000aae: 2b01 cmp r3, #1 8000ab0: d0ef beq.n 8000a92 break; 8000ab2: e368 b.n 8001186 sprintf((char*)s,"\n?eraa hex values"); 8000ab4: f107 0310 add.w r3, r7, #16 8000ab8: 498e ldr r1, [pc, #568] @ (8000cf4 ) 8000aba: 4618 mov r0, r3 8000abc: f00d fcf6 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000ac0: bf00 nop 8000ac2: f107 0310 add.w r3, r7, #16 8000ac6: 4618 mov r0, r3 8000ac8: f7ff fb40 bl 800014c 8000acc: 4603 mov r3, r0 8000ace: b29a uxth r2, r3 8000ad0: f107 0310 add.w r3, r7, #16 8000ad4: 4611 mov r1, r2 8000ad6: 4618 mov r0, r3 8000ad8: f00d f90a bl 800dcf0 8000adc: 4603 mov r3, r0 8000ade: 2b01 cmp r3, #1 8000ae0: d0ef beq.n 8000ac2 break; 8000ae2: e350 b.n 8001186 sprintf((char*)s,"\n?eraa"); 8000ae4: f107 0310 add.w r3, r7, #16 8000ae8: 4983 ldr r1, [pc, #524] @ (8000cf8 ) 8000aea: 4618 mov r0, r3 8000aec: f00d fcde bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000af0: bf00 nop 8000af2: f107 0310 add.w r3, r7, #16 8000af6: 4618 mov r0, r3 8000af8: f7ff fb28 bl 800014c 8000afc: 4603 mov r3, r0 8000afe: b29a uxth r2, r3 8000b00: f107 0310 add.w r3, r7, #16 8000b04: 4611 mov r1, r2 8000b06: 4618 mov r0, r3 8000b08: f00d f8f2 bl 800dcf0 8000b0c: 4603 mov r3, r0 8000b0e: 2b01 cmp r3, #1 8000b10: d0ef beq.n 8000af2 break; 8000b12: e338 b.n 8001186 }else if(rxbuf[1]=='w'){ 8000b14: 4b74 ldr r3, [pc, #464] @ (8000ce8 ) 8000b16: 785b ldrb r3, [r3, #1] 8000b18: 2b77 cmp r3, #119 @ 0x77 8000b1a: d169 bne.n 8000bf0 if(rxidx==8){ 8000b1c: 4b71 ldr r3, [pc, #452] @ (8000ce4 ) 8000b1e: 781b ldrb r3, [r3, #0] 8000b20: 2b08 cmp r3, #8 8000b22: d14d bne.n 8000bc0 if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){ 8000b24: 4b70 ldr r3, [pc, #448] @ (8000ce8 ) 8000b26: 789a ldrb r2, [r3, #2] 8000b28: 4b6f ldr r3, [pc, #444] @ (8000ce8 ) 8000b2a: 78d9 ldrb r1, [r3, #3] 8000b2c: f107 030c add.w r3, r7, #12 8000b30: 9300 str r3, [sp, #0] 8000b32: 460b mov r3, r1 8000b34: 2130 movs r1, #48 @ 0x30 8000b36: 2030 movs r0, #48 @ 0x30 8000b38: f7ff fbc5 bl 80002c6 8000b3c: 4603 mov r3, r0 8000b3e: 2b00 cmp r3, #0 8000b40: d037 beq.n 8000bb2 if(toHex(rxbuf[4],rxbuf[5],rxbuf[6],rxbuf[7],&val)){ 8000b42: 4b69 ldr r3, [pc, #420] @ (8000ce8 ) 8000b44: 7918 ldrb r0, [r3, #4] 8000b46: 4b68 ldr r3, [pc, #416] @ (8000ce8 ) 8000b48: 7959 ldrb r1, [r3, #5] 8000b4a: 4b67 ldr r3, [pc, #412] @ (8000ce8 ) 8000b4c: 799a ldrb r2, [r3, #6] 8000b4e: 4b66 ldr r3, [pc, #408] @ (8000ce8 ) 8000b50: 79dc ldrb r4, [r3, #7] 8000b52: f107 030e add.w r3, r7, #14 8000b56: 9300 str r3, [sp, #0] 8000b58: 4623 mov r3, r4 8000b5a: f7ff fbb4 bl 80002c6 8000b5e: 4603 mov r3, r0 8000b60: 2b00 cmp r3, #0 8000b62: d01f beq.n 8000ba4 st=EEW_Write(eeadd, val); 8000b64: 89bb ldrh r3, [r7, #12] 8000b66: b2db uxtb r3, r3 8000b68: 89fa ldrh r2, [r7, #14] 8000b6a: 4611 mov r1, r2 8000b6c: 4618 mov r0, r3 8000b6e: f7ff fb94 bl 800029a 8000b72: 4603 mov r3, r0 8000b74: f8a7 30d8 strh.w r3, [r7, #216] @ 0xd8 if (st == EE_OK)sprintf((char*)s,"\ndone 0x%02x=0x%04x",eeadd,val); 8000b78: f8b7 30d8 ldrh.w r3, [r7, #216] @ 0xd8 8000b7c: 2b00 cmp r3, #0 8000b7e: d108 bne.n 8000b92 8000b80: 89bb ldrh r3, [r7, #12] 8000b82: 461a mov r2, r3 8000b84: 89fb ldrh r3, [r7, #14] 8000b86: f107 0010 add.w r0, r7, #16 8000b8a: 495c ldr r1, [pc, #368] @ (8000cfc ) 8000b8c: f00d fc8e bl 800e4ac 8000b90: e01c b.n 8000bcc else sprintf((char*)s,"\nee write error %d", st); 8000b92: f8b7 20d8 ldrh.w r2, [r7, #216] @ 0xd8 8000b96: f107 0310 add.w r3, r7, #16 8000b9a: 4959 ldr r1, [pc, #356] @ (8000d00 ) 8000b9c: 4618 mov r0, r3 8000b9e: f00d fc85 bl 800e4ac 8000ba2: e013 b.n 8000bcc }else sprintf((char*)s,"\n?ewaavvvv hex values"); 8000ba4: f107 0310 add.w r3, r7, #16 8000ba8: 4956 ldr r1, [pc, #344] @ (8000d04 ) 8000baa: 4618 mov r0, r3 8000bac: f00d fc7e bl 800e4ac 8000bb0: e00c b.n 8000bcc }else sprintf((char*)s,"\n?ewaa hex values"); 8000bb2: f107 0310 add.w r3, r7, #16 8000bb6: 4954 ldr r1, [pc, #336] @ (8000d08 ) 8000bb8: 4618 mov r0, r3 8000bba: f00d fc77 bl 800e4ac 8000bbe: e005 b.n 8000bcc }else sprintf((char*)s,"\n?ewaavvvv"); 8000bc0: f107 0310 add.w r3, r7, #16 8000bc4: 4951 ldr r1, [pc, #324] @ (8000d0c ) 8000bc6: 4618 mov r0, r3 8000bc8: f00d fc70 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000bcc: bf00 nop 8000bce: f107 0310 add.w r3, r7, #16 8000bd2: 4618 mov r0, r3 8000bd4: f7ff faba bl 800014c 8000bd8: 4603 mov r3, r0 8000bda: b29a uxth r2, r3 8000bdc: f107 0310 add.w r3, r7, #16 8000be0: 4611 mov r1, r2 8000be2: 4618 mov r0, r3 8000be4: f00d f884 bl 800dcf0 8000be8: 4603 mov r3, r0 8000bea: 2b01 cmp r3, #1 8000bec: d0ef beq.n 8000bce break; 8000bee: e2ca b.n 8001186 }else if(rxbuf[1]=='d'){ 8000bf0: 4b3d ldr r3, [pc, #244] @ (8000ce8 ) 8000bf2: 785b ldrb r3, [r3, #1] 8000bf4: 2b64 cmp r3, #100 @ 0x64 8000bf6: f040 80a9 bne.w 8000d4c if(rxidx==2){ 8000bfa: 4b3a ldr r3, [pc, #232] @ (8000ce4 ) 8000bfc: 781b ldrb r3, [r3, #0] 8000bfe: 2b02 cmp r3, #2 8000c00: f040 808c bne.w 8000d1c for(i=0;i<32;i++){ 8000c04: 2300 movs r3, #0 8000c06: f887 30e6 strb.w r3, [r7, #230] @ 0xe6 8000c0a: e046 b.n 8000c9a st=EEW_Read(i, &val); 8000c0c: f107 020e add.w r2, r7, #14 8000c10: f897 30e6 ldrb.w r3, [r7, #230] @ 0xe6 8000c14: 4611 mov r1, r2 8000c16: 4618 mov r0, r3 8000c18: f7ff fb2c bl 8000274 8000c1c: 4603 mov r3, r0 8000c1e: f8a7 30d8 strh.w r3, [r7, #216] @ 0xd8 if (st == EE_OK){ 8000c22: f8b7 30d8 ldrh.w r3, [r7, #216] @ 0xd8 8000c26: 2b00 cmp r3, #0 8000c28: d119 bne.n 8000c5e sprintf((char*)s,"\n0x%02x=%5d ",i,val); 8000c2a: f897 20e6 ldrb.w r2, [r7, #230] @ 0xe6 8000c2e: 89fb ldrh r3, [r7, #14] 8000c30: f107 0010 add.w r0, r7, #16 8000c34: 4936 ldr r1, [pc, #216] @ (8000d10 ) 8000c36: f00d fc39 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000c3a: bf00 nop 8000c3c: f107 0310 add.w r3, r7, #16 8000c40: 4618 mov r0, r3 8000c42: f7ff fa83 bl 800014c 8000c46: 4603 mov r3, r0 8000c48: b29a uxth r2, r3 8000c4a: f107 0310 add.w r3, r7, #16 8000c4e: 4611 mov r1, r2 8000c50: 4618 mov r0, r3 8000c52: f00d f84d bl 800dcf0 8000c56: 4603 mov r3, r0 8000c58: 2b01 cmp r3, #1 8000c5a: d0ef beq.n 8000c3c 8000c5c: e018 b.n 8000c90 sprintf((char*)s,"rderr %d ",st); 8000c5e: f8b7 20d8 ldrh.w r2, [r7, #216] @ 0xd8 8000c62: f107 0310 add.w r3, r7, #16 8000c66: 492b ldr r1, [pc, #172] @ (8000d14 ) 8000c68: 4618 mov r0, r3 8000c6a: f00d fc1f bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000c6e: bf00 nop 8000c70: f107 0310 add.w r3, r7, #16 8000c74: 4618 mov r0, r3 8000c76: f7ff fa69 bl 800014c 8000c7a: 4603 mov r3, r0 8000c7c: b29a uxth r2, r3 8000c7e: f107 0310 add.w r3, r7, #16 8000c82: 4611 mov r1, r2 8000c84: 4618 mov r0, r3 8000c86: f00d f833 bl 800dcf0 8000c8a: 4603 mov r3, r0 8000c8c: 2b01 cmp r3, #1 8000c8e: d0ef beq.n 8000c70 for(i=0;i<32;i++){ 8000c90: f897 30e6 ldrb.w r3, [r7, #230] @ 0xe6 8000c94: 3301 adds r3, #1 8000c96: f887 30e6 strb.w r3, [r7, #230] @ 0xe6 8000c9a: f897 30e6 ldrb.w r3, [r7, #230] @ 0xe6 8000c9e: 2b1f cmp r3, #31 8000ca0: d9b4 bls.n 8000c0c if((i%4)==0){ 8000ca2: f897 30e6 ldrb.w r3, [r7, #230] @ 0xe6 8000ca6: f003 0303 and.w r3, r3, #3 8000caa: b2db uxtb r3, r3 8000cac: 2b00 cmp r3, #0 8000cae: f040 826a bne.w 8001186 sprintf((char*)s,"\n"); 8000cb2: f107 0310 add.w r3, r7, #16 8000cb6: 4918 ldr r1, [pc, #96] @ (8000d18 ) 8000cb8: 4618 mov r0, r3 8000cba: f00d fbf7 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000cbe: bf00 nop 8000cc0: f107 0310 add.w r3, r7, #16 8000cc4: 4618 mov r0, r3 8000cc6: f7ff fa41 bl 800014c 8000cca: 4603 mov r3, r0 8000ccc: b29a uxth r2, r3 8000cce: f107 0310 add.w r3, r7, #16 8000cd2: 4611 mov r1, r2 8000cd4: 4618 mov r0, r3 8000cd6: f00d f80b bl 800dcf0 8000cda: 4603 mov r3, r0 8000cdc: 2b01 cmp r3, #1 8000cde: d0ef beq.n 8000cc0 break; 8000ce0: e251 b.n 8001186 8000ce2: bf00 nop 8000ce4: 20000234 .word 0x20000234 8000ce8: 20000238 .word 0x20000238 8000cec: 0800ef38 .word 0x0800ef38 8000cf0: 0800ef4c .word 0x0800ef4c 8000cf4: 0800ef60 .word 0x0800ef60 8000cf8: 0800ef74 .word 0x0800ef74 8000cfc: 0800ef7c .word 0x0800ef7c 8000d00: 0800ef90 .word 0x0800ef90 8000d04: 0800efa4 .word 0x0800efa4 8000d08: 0800efbc .word 0x0800efbc 8000d0c: 0800efd0 .word 0x0800efd0 8000d10: 0800efdc .word 0x0800efdc 8000d14: 0800efec .word 0x0800efec 8000d18: 0800eff8 .word 0x0800eff8 sprintf((char*)s,"\n?ed"); 8000d1c: f107 0310 add.w r3, r7, #16 8000d20: 491d ldr r1, [pc, #116] @ (8000d98 ) 8000d22: 4618 mov r0, r3 8000d24: f00d fbc2 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000d28: bf00 nop 8000d2a: f107 0310 add.w r3, r7, #16 8000d2e: 4618 mov r0, r3 8000d30: f7ff fa0c bl 800014c 8000d34: 4603 mov r3, r0 8000d36: b29a uxth r2, r3 8000d38: f107 0310 add.w r3, r7, #16 8000d3c: 4611 mov r1, r2 8000d3e: 4618 mov r0, r3 8000d40: f00c ffd6 bl 800dcf0 8000d44: 4603 mov r3, r0 8000d46: 2b01 cmp r3, #1 8000d48: d0ef beq.n 8000d2a break; 8000d4a: e21c b.n 8001186 }else if(rxbuf[1]=='x'){ 8000d4c: 4b13 ldr r3, [pc, #76] @ (8000d9c ) 8000d4e: 785b ldrb r3, [r3, #1] 8000d50: 2b78 cmp r3, #120 @ 0x78 8000d52: d129 bne.n 8000da8 if(rxidx==2){ 8000d54: 4b12 ldr r3, [pc, #72] @ (8000da0 ) 8000d56: 781b ldrb r3, [r3, #0] 8000d58: 2b02 cmp r3, #2 8000d5a: d104 bne.n 8000d66 loadDefault(); 8000d5c: f000 fcd2 bl 8001704 loadEE(); 8000d60: f000 fd1e bl 80017a0 break; 8000d64: e20f b.n 8001186 sprintf((char*)s,"\n?ex"); 8000d66: f107 0310 add.w r3, r7, #16 8000d6a: 490e ldr r1, [pc, #56] @ (8000da4 ) 8000d6c: 4618 mov r0, r3 8000d6e: f00d fb9d bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000d72: bf00 nop 8000d74: f107 0310 add.w r3, r7, #16 8000d78: 4618 mov r0, r3 8000d7a: f7ff f9e7 bl 800014c 8000d7e: 4603 mov r3, r0 8000d80: b29a uxth r2, r3 8000d82: f107 0310 add.w r3, r7, #16 8000d86: 4611 mov r1, r2 8000d88: 4618 mov r0, r3 8000d8a: f00c ffb1 bl 800dcf0 8000d8e: 4603 mov r3, r0 8000d90: 2b01 cmp r3, #1 8000d92: d0ef beq.n 8000d74 break; 8000d94: e1f7 b.n 8001186 8000d96: bf00 nop 8000d98: 0800effc .word 0x0800effc 8000d9c: 20000238 .word 0x20000238 8000da0: 20000234 .word 0x20000234 8000da4: 0800f004 .word 0x0800f004 }else if(rxbuf[1]=='v'){ 8000da8: 4bb4 ldr r3, [pc, #720] @ (800107c ) 8000daa: 785b ldrb r3, [r3, #1] 8000dac: 2b76 cmp r3, #118 @ 0x76 8000dae: f040 814c bne.w 800104a if(rxidx==2){ 8000db2: 4bb3 ldr r3, [pc, #716] @ (8001080 ) 8000db4: 781b ldrb r3, [r3, #0] 8000db6: 2b02 cmp r3, #2 8000db8: f040 812f bne.w 800101a sprintf((char*)s,"\nm1pwmap=%d m1pwmch=%d m2pwmap=%d m2pwmch=%d m3pwmap=%d m3pwmch=%d m4pwmap=%d m4pwmch=%d",m1pwmap,m1pwmch,m2pwmap,m2pwmch,m3pwmap,m3pwmch,m4pwmap, m4pwmch); 8000dbc: 4bb1 ldr r3, [pc, #708] @ (8001084 ) 8000dbe: 881b ldrh r3, [r3, #0] 8000dc0: 469c mov ip, r3 8000dc2: 4bb1 ldr r3, [pc, #708] @ (8001088 ) 8000dc4: 881b ldrh r3, [r3, #0] 8000dc6: 469e mov lr, r3 8000dc8: 4bb0 ldr r3, [pc, #704] @ (800108c ) 8000dca: 881b ldrh r3, [r3, #0] 8000dcc: 461a mov r2, r3 8000dce: 4bb0 ldr r3, [pc, #704] @ (8001090 ) 8000dd0: 881b ldrh r3, [r3, #0] 8000dd2: 4619 mov r1, r3 8000dd4: 4baf ldr r3, [pc, #700] @ (8001094 ) 8000dd6: 881b ldrh r3, [r3, #0] 8000dd8: 461c mov r4, r3 8000dda: 4baf ldr r3, [pc, #700] @ (8001098 ) 8000ddc: 881b ldrh r3, [r3, #0] 8000dde: 461d mov r5, r3 8000de0: 4bae ldr r3, [pc, #696] @ (800109c ) 8000de2: 881b ldrh r3, [r3, #0] 8000de4: 461e mov r6, r3 8000de6: 4bae ldr r3, [pc, #696] @ (80010a0 ) 8000de8: 881b ldrh r3, [r3, #0] 8000dea: f107 0010 add.w r0, r7, #16 8000dee: 9305 str r3, [sp, #20] 8000df0: 9604 str r6, [sp, #16] 8000df2: 9503 str r5, [sp, #12] 8000df4: 9402 str r4, [sp, #8] 8000df6: 9101 str r1, [sp, #4] 8000df8: 9200 str r2, [sp, #0] 8000dfa: 4673 mov r3, lr 8000dfc: 4662 mov r2, ip 8000dfe: 49a9 ldr r1, [pc, #676] @ (80010a4 ) 8000e00: f00d fb54 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000e04: bf00 nop 8000e06: f107 0310 add.w r3, r7, #16 8000e0a: 4618 mov r0, r3 8000e0c: f7ff f99e bl 800014c 8000e10: 4603 mov r3, r0 8000e12: b29a uxth r2, r3 8000e14: f107 0310 add.w r3, r7, #16 8000e18: 4611 mov r1, r2 8000e1a: 4618 mov r0, r3 8000e1c: f00c ff68 bl 800dcf0 8000e20: 4603 mov r3, r0 8000e22: 2b01 cmp r3, #1 8000e24: d0ef beq.n 8000e06 sprintf((char*)s,"\nm1TimeoutMan=%d m2TimeoutMan=%d m3TimeoutMan=%d m4TimeoutMan=%d ",m1TimeoutMan,m2TimeoutMan,m3TimeoutMan,m4TimeoutMan); 8000e26: 4ba0 ldr r3, [pc, #640] @ (80010a8 ) 8000e28: 881b ldrh r3, [r3, #0] 8000e2a: 4619 mov r1, r3 8000e2c: 4b9f ldr r3, [pc, #636] @ (80010ac ) 8000e2e: 881b ldrh r3, [r3, #0] 8000e30: 461c mov r4, r3 8000e32: 4b9f ldr r3, [pc, #636] @ (80010b0 ) 8000e34: 881b ldrh r3, [r3, #0] 8000e36: 461a mov r2, r3 8000e38: 4b9e ldr r3, [pc, #632] @ (80010b4 ) 8000e3a: 881b ldrh r3, [r3, #0] 8000e3c: f107 0010 add.w r0, r7, #16 8000e40: 9301 str r3, [sp, #4] 8000e42: 9200 str r2, [sp, #0] 8000e44: 4623 mov r3, r4 8000e46: 460a mov r2, r1 8000e48: 499b ldr r1, [pc, #620] @ (80010b8 ) 8000e4a: f00d fb2f bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000e4e: bf00 nop 8000e50: f107 0310 add.w r3, r7, #16 8000e54: 4618 mov r0, r3 8000e56: f7ff f979 bl 800014c 8000e5a: 4603 mov r3, r0 8000e5c: b29a uxth r2, r3 8000e5e: f107 0310 add.w r3, r7, #16 8000e62: 4611 mov r1, r2 8000e64: 4618 mov r0, r3 8000e66: f00c ff43 bl 800dcf0 8000e6a: 4603 mov r3, r0 8000e6c: 2b01 cmp r3, #1 8000e6e: d0ef beq.n 8000e50 sprintf((char*)s,"\ntramp=%d trampman=%d",tramp,trampman); 8000e70: 4b92 ldr r3, [pc, #584] @ (80010bc ) 8000e72: 881b ldrh r3, [r3, #0] 8000e74: 461a mov r2, r3 8000e76: 4b92 ldr r3, [pc, #584] @ (80010c0 ) 8000e78: 881b ldrh r3, [r3, #0] 8000e7a: f107 0010 add.w r0, r7, #16 8000e7e: 4991 ldr r1, [pc, #580] @ (80010c4 ) 8000e80: f00d fb14 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000e84: bf00 nop 8000e86: f107 0310 add.w r3, r7, #16 8000e8a: 4618 mov r0, r3 8000e8c: f7ff f95e bl 800014c 8000e90: 4603 mov r3, r0 8000e92: b29a uxth r2, r3 8000e94: f107 0310 add.w r3, r7, #16 8000e98: 4611 mov r1, r2 8000e9a: 4618 mov r0, r3 8000e9c: f00c ff28 bl 800dcf0 8000ea0: 4603 mov r3, r0 8000ea2: 2b01 cmp r3, #1 8000ea4: d0ef beq.n 8000e86 sprintf((char*)s,"\nm1pwmMan=%d m2pwmMan=%d m3pwmMan=%d m4pwmMan=%d",m1pwmMan,m2pwmMan,m3pwmMan,m4pwmMan); 8000ea6: 4b88 ldr r3, [pc, #544] @ (80010c8 ) 8000ea8: 881b ldrh r3, [r3, #0] 8000eaa: 4619 mov r1, r3 8000eac: 4b87 ldr r3, [pc, #540] @ (80010cc ) 8000eae: 881b ldrh r3, [r3, #0] 8000eb0: 461c mov r4, r3 8000eb2: 4b87 ldr r3, [pc, #540] @ (80010d0 ) 8000eb4: 881b ldrh r3, [r3, #0] 8000eb6: 461a mov r2, r3 8000eb8: 4b86 ldr r3, [pc, #536] @ (80010d4 ) 8000eba: 881b ldrh r3, [r3, #0] 8000ebc: f107 0010 add.w r0, r7, #16 8000ec0: 9301 str r3, [sp, #4] 8000ec2: 9200 str r2, [sp, #0] 8000ec4: 4623 mov r3, r4 8000ec6: 460a mov r2, r1 8000ec8: 4983 ldr r1, [pc, #524] @ (80010d8 ) 8000eca: f00d faef bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000ece: bf00 nop 8000ed0: f107 0310 add.w r3, r7, #16 8000ed4: 4618 mov r0, r3 8000ed6: f7ff f939 bl 800014c 8000eda: 4603 mov r3, r0 8000edc: b29a uxth r2, r3 8000ede: f107 0310 add.w r3, r7, #16 8000ee2: 4611 mov r1, r2 8000ee4: 4618 mov r0, r3 8000ee6: f00c ff03 bl 800dcf0 8000eea: 4603 mov r3, r0 8000eec: 2b01 cmp r3, #1 8000eee: d0ef beq.n 8000ed0 sprintf((char*)s,"\napM1start=%d apM1stop=%d chM1start=%d chM1stop=%d",apM1start,apM1stop,chM1start,chM1stop); 8000ef0: 4b7a ldr r3, [pc, #488] @ (80010dc ) 8000ef2: 881b ldrh r3, [r3, #0] 8000ef4: 4619 mov r1, r3 8000ef6: 4b7a ldr r3, [pc, #488] @ (80010e0 ) 8000ef8: 881b ldrh r3, [r3, #0] 8000efa: 461c mov r4, r3 8000efc: 4b79 ldr r3, [pc, #484] @ (80010e4 ) 8000efe: 881b ldrh r3, [r3, #0] 8000f00: 461a mov r2, r3 8000f02: 4b79 ldr r3, [pc, #484] @ (80010e8 ) 8000f04: 881b ldrh r3, [r3, #0] 8000f06: f107 0010 add.w r0, r7, #16 8000f0a: 9301 str r3, [sp, #4] 8000f0c: 9200 str r2, [sp, #0] 8000f0e: 4623 mov r3, r4 8000f10: 460a mov r2, r1 8000f12: 4976 ldr r1, [pc, #472] @ (80010ec ) 8000f14: f00d faca bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000f18: bf00 nop 8000f1a: f107 0310 add.w r3, r7, #16 8000f1e: 4618 mov r0, r3 8000f20: f7ff f914 bl 800014c 8000f24: 4603 mov r3, r0 8000f26: b29a uxth r2, r3 8000f28: f107 0310 add.w r3, r7, #16 8000f2c: 4611 mov r1, r2 8000f2e: 4618 mov r0, r3 8000f30: f00c fede bl 800dcf0 8000f34: 4603 mov r3, r0 8000f36: 2b01 cmp r3, #1 8000f38: d0ef beq.n 8000f1a sprintf((char*)s,"\napM2start=%d apM2stop=%d chM2start=%d chM2stop=%d",apM2start,apM2stop,chM2start,chM2stop); 8000f3a: 4b6d ldr r3, [pc, #436] @ (80010f0 ) 8000f3c: 881b ldrh r3, [r3, #0] 8000f3e: 4619 mov r1, r3 8000f40: 4b6c ldr r3, [pc, #432] @ (80010f4 ) 8000f42: 881b ldrh r3, [r3, #0] 8000f44: 461c mov r4, r3 8000f46: 4b6c ldr r3, [pc, #432] @ (80010f8 ) 8000f48: 881b ldrh r3, [r3, #0] 8000f4a: 461a mov r2, r3 8000f4c: 4b6b ldr r3, [pc, #428] @ (80010fc ) 8000f4e: 881b ldrh r3, [r3, #0] 8000f50: f107 0010 add.w r0, r7, #16 8000f54: 9301 str r3, [sp, #4] 8000f56: 9200 str r2, [sp, #0] 8000f58: 4623 mov r3, r4 8000f5a: 460a mov r2, r1 8000f5c: 4968 ldr r1, [pc, #416] @ (8001100 ) 8000f5e: f00d faa5 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000f62: bf00 nop 8000f64: f107 0310 add.w r3, r7, #16 8000f68: 4618 mov r0, r3 8000f6a: f7ff f8ef bl 800014c 8000f6e: 4603 mov r3, r0 8000f70: b29a uxth r2, r3 8000f72: f107 0310 add.w r3, r7, #16 8000f76: 4611 mov r1, r2 8000f78: 4618 mov r0, r3 8000f7a: f00c feb9 bl 800dcf0 8000f7e: 4603 mov r3, r0 8000f80: 2b01 cmp r3, #1 8000f82: d0ef beq.n 8000f64 sprintf((char*)s,"\napM3start=%d apM3stop=%d chM3start=%d chM3stop=%d",apM3start,apM3stop,chM3start,chM3stop); 8000f84: 4b5f ldr r3, [pc, #380] @ (8001104 ) 8000f86: 881b ldrh r3, [r3, #0] 8000f88: 4619 mov r1, r3 8000f8a: 4b5f ldr r3, [pc, #380] @ (8001108 ) 8000f8c: 881b ldrh r3, [r3, #0] 8000f8e: 461c mov r4, r3 8000f90: 4b5e ldr r3, [pc, #376] @ (800110c ) 8000f92: 881b ldrh r3, [r3, #0] 8000f94: 461a mov r2, r3 8000f96: 4b5e ldr r3, [pc, #376] @ (8001110 ) 8000f98: 881b ldrh r3, [r3, #0] 8000f9a: f107 0010 add.w r0, r7, #16 8000f9e: 9301 str r3, [sp, #4] 8000fa0: 9200 str r2, [sp, #0] 8000fa2: 4623 mov r3, r4 8000fa4: 460a mov r2, r1 8000fa6: 495b ldr r1, [pc, #364] @ (8001114 ) 8000fa8: f00d fa80 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000fac: bf00 nop 8000fae: f107 0310 add.w r3, r7, #16 8000fb2: 4618 mov r0, r3 8000fb4: f7ff f8ca bl 800014c 8000fb8: 4603 mov r3, r0 8000fba: b29a uxth r2, r3 8000fbc: f107 0310 add.w r3, r7, #16 8000fc0: 4611 mov r1, r2 8000fc2: 4618 mov r0, r3 8000fc4: f00c fe94 bl 800dcf0 8000fc8: 4603 mov r3, r0 8000fca: 2b01 cmp r3, #1 8000fcc: d0ef beq.n 8000fae sprintf((char*)s,"\napM4start=%d apM4stop=%d chM4start=%d chM4stop=%d",apM4start,apM4stop,chM4start,chM4stop); 8000fce: 4b52 ldr r3, [pc, #328] @ (8001118 ) 8000fd0: 881b ldrh r3, [r3, #0] 8000fd2: 4619 mov r1, r3 8000fd4: 4b51 ldr r3, [pc, #324] @ (800111c ) 8000fd6: 881b ldrh r3, [r3, #0] 8000fd8: 461c mov r4, r3 8000fda: 4b51 ldr r3, [pc, #324] @ (8001120 ) 8000fdc: 881b ldrh r3, [r3, #0] 8000fde: 461a mov r2, r3 8000fe0: 4b50 ldr r3, [pc, #320] @ (8001124 ) 8000fe2: 881b ldrh r3, [r3, #0] 8000fe4: f107 0010 add.w r0, r7, #16 8000fe8: 9301 str r3, [sp, #4] 8000fea: 9200 str r2, [sp, #0] 8000fec: 4623 mov r3, r4 8000fee: 460a mov r2, r1 8000ff0: 494d ldr r1, [pc, #308] @ (8001128 ) 8000ff2: f00d fa5b bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8000ff6: bf00 nop 8000ff8: f107 0310 add.w r3, r7, #16 8000ffc: 4618 mov r0, r3 8000ffe: f7ff f8a5 bl 800014c 8001002: 4603 mov r3, r0 8001004: b29a uxth r2, r3 8001006: f107 0310 add.w r3, r7, #16 800100a: 4611 mov r1, r2 800100c: 4618 mov r0, r3 800100e: f00c fe6f bl 800dcf0 8001012: 4603 mov r3, r0 8001014: 2b01 cmp r3, #1 8001016: d0ef beq.n 8000ff8 break; 8001018: e0b5 b.n 8001186 sprintf((char*)s,"\n?ev"); 800101a: f107 0310 add.w r3, r7, #16 800101e: 4943 ldr r1, [pc, #268] @ (800112c ) 8001020: 4618 mov r0, r3 8001022: f00d fa43 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8001026: bf00 nop 8001028: f107 0310 add.w r3, r7, #16 800102c: 4618 mov r0, r3 800102e: f7ff f88d bl 800014c 8001032: 4603 mov r3, r0 8001034: b29a uxth r2, r3 8001036: f107 0310 add.w r3, r7, #16 800103a: 4611 mov r1, r2 800103c: 4618 mov r0, r3 800103e: f00c fe57 bl 800dcf0 8001042: 4603 mov r3, r0 8001044: 2b01 cmp r3, #1 8001046: d0ef beq.n 8001028 break; 8001048: e09d b.n 8001186 sprintf((char*)s,"\n?er|w|d|x|v"); 800104a: f107 0310 add.w r3, r7, #16 800104e: 4938 ldr r1, [pc, #224] @ (8001130 ) 8001050: 4618 mov r0, r3 8001052: f00d fa2b bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8001056: bf00 nop 8001058: f107 0310 add.w r3, r7, #16 800105c: 4618 mov r0, r3 800105e: f7ff f875 bl 800014c 8001062: 4603 mov r3, r0 8001064: b29a uxth r2, r3 8001066: f107 0310 add.w r3, r7, #16 800106a: 4611 mov r1, r2 800106c: 4618 mov r0, r3 800106e: f00c fe3f bl 800dcf0 8001072: 4603 mov r3, r0 8001074: 2b01 cmp r3, #1 8001076: d0ef beq.n 8001058 break; 8001078: e085 b.n 8001186 800107a: bf00 nop 800107c: 20000238 .word 0x20000238 8001080: 20000234 .word 0x20000234 8001084: 20000400 .word 0x20000400 8001088: 20000402 .word 0x20000402 800108c: 20000404 .word 0x20000404 8001090: 20000406 .word 0x20000406 8001094: 20000408 .word 0x20000408 8001098: 2000040a .word 0x2000040a 800109c: 2000040c .word 0x2000040c 80010a0: 2000040e .word 0x2000040e 80010a4: 0800f00c .word 0x0800f00c 80010a8: 20000410 .word 0x20000410 80010ac: 20000412 .word 0x20000412 80010b0: 20000414 .word 0x20000414 80010b4: 20000416 .word 0x20000416 80010b8: 0800f068 .word 0x0800f068 80010bc: 20000418 .word 0x20000418 80010c0: 2000041e .word 0x2000041e 80010c4: 0800f0ac .word 0x0800f0ac 80010c8: 20000420 .word 0x20000420 80010cc: 20000422 .word 0x20000422 80010d0: 20000424 .word 0x20000424 80010d4: 20000426 .word 0x20000426 80010d8: 0800f0c4 .word 0x0800f0c4 80010dc: 20000428 .word 0x20000428 80010e0: 2000042a .word 0x2000042a 80010e4: 20000438 .word 0x20000438 80010e8: 2000043a .word 0x2000043a 80010ec: 0800f0f8 .word 0x0800f0f8 80010f0: 2000042c .word 0x2000042c 80010f4: 2000042e .word 0x2000042e 80010f8: 2000043c .word 0x2000043c 80010fc: 2000043e .word 0x2000043e 8001100: 0800f12c .word 0x0800f12c 8001104: 20000430 .word 0x20000430 8001108: 20000432 .word 0x20000432 800110c: 20000440 .word 0x20000440 8001110: 20000442 .word 0x20000442 8001114: 0800f160 .word 0x0800f160 8001118: 20000434 .word 0x20000434 800111c: 20000436 .word 0x20000436 8001120: 20000444 .word 0x20000444 8001124: 20000446 .word 0x20000446 8001128: 0800f194 .word 0x0800f194 800112c: 0800f1c8 .word 0x0800f1c8 8001130: 0800f1d0 .word 0x0800f1d0 sprintf((char*)s,"\n?eraa | ewaavvvv"); 8001134: f107 0310 add.w r3, r7, #16 8001138: 491b ldr r1, [pc, #108] @ (80011a8 ) 800113a: 4618 mov r0, r3 800113c: f00d f9b6 bl 800e4ac while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY); 8001140: bf00 nop 8001142: f107 0310 add.w r3, r7, #16 8001146: 4618 mov r0, r3 8001148: f7ff f800 bl 800014c 800114c: 4603 mov r3, r0 800114e: b29a uxth r2, r3 8001150: f107 0310 add.w r3, r7, #16 8001154: 4611 mov r1, r2 8001156: 4618 mov r0, r3 8001158: f00c fdca bl 800dcf0 800115c: 4603 mov r3, r0 800115e: 2b01 cmp r3, #1 8001160: d0ef beq.n 8001142 break; 8001162: e010 b.n 8001186 default: sprintf((char*)s,"\n?"); 8001164: f107 0310 add.w r3, r7, #16 8001168: 4910 ldr r1, [pc, #64] @ (80011ac ) 800116a: 4618 mov r0, r3 800116c: f00d f99e bl 800e4ac while (CDC_Transmit_FS(s, 2) == USBD_BUSY); 8001170: bf00 nop 8001172: f107 0310 add.w r3, r7, #16 8001176: 2102 movs r1, #2 8001178: 4618 mov r0, r3 800117a: f00c fdb9 bl 800dcf0 800117e: 4603 mov r3, r0 8001180: 2b01 cmp r3, #1 8001182: d0f6 beq.n 8001172 break; 8001184: e000 b.n 8001188 break; 8001186: bf00 nop } } rxidx=0; 8001188: 4b09 ldr r3, [pc, #36] @ (80011b0 ) 800118a: 2200 movs r2, #0 800118c: 701a strb r2, [r3, #0] 800118e: e007 b.n 80011a0 }else rxidx++; 8001190: 4b07 ldr r3, [pc, #28] @ (80011b0 ) 8001192: 781b ldrb r3, [r3, #0] 8001194: 3301 adds r3, #1 8001196: b2da uxtb r2, r3 8001198: 4b05 ldr r3, [pc, #20] @ (80011b0 ) 800119a: 701a strb r2, [r3, #0] 800119c: e000 b.n 80011a0 if (rx < 0) return; 800119e: bf00 nop // tiny spin or yield } } 80011a0: 37ec adds r7, #236 @ 0xec 80011a2: 46bd mov sp, r7 80011a4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 80011a8: 0800f1e0 .word 0x0800f1e0 80011ac: 0800f1f4 .word 0x0800f1f4 80011b0: 20000234 .word 0x20000234 080011b4 : extern UART_HandleTypeDef huart1; extern uint8_t pulsanti; extern uint16_t stPulsanti; extern omCiclo_st stCiclo; void debug(void){ 80011b4: b580 push {r7, lr} 80011b6: b09a sub sp, #104 @ 0x68 80011b8: af00 add r7, sp, #0 static uint8_t mempulsanti=0; static uint16_t memstPulsanti=0; static omCiclo_st memstCiclo=omchiuso; char s [100]; if(mempulsanti!=pulsanti){ 80011ba: 4b2f ldr r3, [pc, #188] @ (8001278 ) 80011bc: 781a ldrb r2, [r3, #0] 80011be: 4b2f ldr r3, [pc, #188] @ (800127c ) 80011c0: 781b ldrb r3, [r3, #0] 80011c2: 429a cmp r2, r3 80011c4: d017 beq.n 80011f6 mempulsanti=pulsanti; 80011c6: 4b2d ldr r3, [pc, #180] @ (800127c ) 80011c8: 781a ldrb r2, [r3, #0] 80011ca: 4b2b ldr r3, [pc, #172] @ (8001278 ) 80011cc: 701a strb r2, [r3, #0] sprintf(s,"\npulsanti=%X",pulsanti); 80011ce: 4b2b ldr r3, [pc, #172] @ (800127c ) 80011d0: 781b ldrb r3, [r3, #0] 80011d2: 461a mov r2, r3 80011d4: 1d3b adds r3, r7, #4 80011d6: 492a ldr r1, [pc, #168] @ (8001280 ) 80011d8: 4618 mov r0, r3 80011da: f00d f967 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 80011de: 1d3b adds r3, r7, #4 80011e0: 4618 mov r0, r3 80011e2: f7fe ffb3 bl 800014c 80011e6: 4603 mov r3, r0 80011e8: b29a uxth r2, r3 80011ea: 1d39 adds r1, r7, #4 80011ec: f04f 33ff mov.w r3, #4294967295 80011f0: 4824 ldr r0, [pc, #144] @ (8001284 ) 80011f2: f008 fb6b bl 80098cc } if(memstPulsanti!=stPulsanti){ 80011f6: 4b24 ldr r3, [pc, #144] @ (8001288 ) 80011f8: 881a ldrh r2, [r3, #0] 80011fa: 4b24 ldr r3, [pc, #144] @ (800128c ) 80011fc: 881b ldrh r3, [r3, #0] 80011fe: 429a cmp r2, r3 8001200: d017 beq.n 8001232 memstPulsanti=stPulsanti; 8001202: 4b22 ldr r3, [pc, #136] @ (800128c ) 8001204: 881a ldrh r2, [r3, #0] 8001206: 4b20 ldr r3, [pc, #128] @ (8001288 ) 8001208: 801a strh r2, [r3, #0] sprintf(s,"\nstpulsanti=%X",stPulsanti); 800120a: 4b20 ldr r3, [pc, #128] @ (800128c ) 800120c: 881b ldrh r3, [r3, #0] 800120e: 461a mov r2, r3 8001210: 1d3b adds r3, r7, #4 8001212: 491f ldr r1, [pc, #124] @ (8001290 ) 8001214: 4618 mov r0, r3 8001216: f00d f949 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 800121a: 1d3b adds r3, r7, #4 800121c: 4618 mov r0, r3 800121e: f7fe ff95 bl 800014c 8001222: 4603 mov r3, r0 8001224: b29a uxth r2, r3 8001226: 1d39 adds r1, r7, #4 8001228: f04f 33ff mov.w r3, #4294967295 800122c: 4815 ldr r0, [pc, #84] @ (8001284 ) 800122e: f008 fb4d bl 80098cc } if(memstCiclo!=stCiclo){ 8001232: 4b18 ldr r3, [pc, #96] @ (8001294 ) 8001234: 781a ldrb r2, [r3, #0] 8001236: 4b18 ldr r3, [pc, #96] @ (8001298 ) 8001238: 781b ldrb r3, [r3, #0] 800123a: 429a cmp r2, r3 800123c: d017 beq.n 800126e memstCiclo=stCiclo; 800123e: 4b16 ldr r3, [pc, #88] @ (8001298 ) 8001240: 781a ldrb r2, [r3, #0] 8001242: 4b14 ldr r3, [pc, #80] @ (8001294 ) 8001244: 701a strb r2, [r3, #0] sprintf(s,"\nstCiclo=%d",stCiclo); 8001246: 4b14 ldr r3, [pc, #80] @ (8001298 ) 8001248: 781b ldrb r3, [r3, #0] 800124a: 461a mov r2, r3 800124c: 1d3b adds r3, r7, #4 800124e: 4913 ldr r1, [pc, #76] @ (800129c ) 8001250: 4618 mov r0, r3 8001252: f00d f92b bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001256: 1d3b adds r3, r7, #4 8001258: 4618 mov r0, r3 800125a: f7fe ff77 bl 800014c 800125e: 4603 mov r3, r0 8001260: b29a uxth r2, r3 8001262: 1d39 adds r1, r7, #4 8001264: f04f 33ff mov.w r3, #4294967295 8001268: 4806 ldr r0, [pc, #24] @ (8001284 ) 800126a: f008 fb2f bl 80098cc } } 800126e: bf00 nop 8001270: 3768 adds r7, #104 @ 0x68 8001272: 46bd mov sp, r7 8001274: bd80 pop {r7, pc} 8001276: bf00 nop 8001278: 2000029c .word 0x2000029c 800127c: 200003f0 .word 0x200003f0 8001280: 0800f1f8 .word 0x0800f1f8 8001284: 200003a8 .word 0x200003a8 8001288: 2000029e .word 0x2000029e 800128c: 20000454 .word 0x20000454 8001290: 0800f208 .word 0x0800f208 8001294: 200002a0 .word 0x200002a0 8001298: 20000456 .word 0x20000456 800129c: 0800f218 .word 0x0800f218 080012a0 : { 80012a0: b580 push {r7, lr} 80012a2: b082 sub sp, #8 80012a4: af00 add r7, sp, #0 80012a6: 4603 mov r3, r0 80012a8: 6039 str r1, [r7, #0] 80012aa: 71fb strb r3, [r7, #7] return EE_ReadVariable(EEW_ADDR(idx), value); 80012ac: 79fb ldrb r3, [r7, #7] 80012ae: b29b uxth r3, r3 80012b0: 3301 adds r3, #1 80012b2: b29b uxth r3, r3 80012b4: 6839 ldr r1, [r7, #0] 80012b6: 4618 mov r0, r3 80012b8: f000 f9ce bl 8001658 80012bc: 4603 mov r3, r0 } 80012be: 4618 mov r0, r3 80012c0: 3708 adds r7, #8 80012c2: 46bd mov sp, r7 80012c4: bd80 pop {r7, pc} 080012c6 : { 80012c6: b580 push {r7, lr} 80012c8: b082 sub sp, #8 80012ca: af00 add r7, sp, #0 80012cc: 4603 mov r3, r0 80012ce: 460a mov r2, r1 80012d0: 71fb strb r3, [r7, #7] 80012d2: 4613 mov r3, r2 80012d4: 80bb strh r3, [r7, #4] return EE_WriteVariable(EEW_ADDR(idx), value); 80012d6: 79fb ldrb r3, [r7, #7] 80012d8: b29b uxth r3, r3 80012da: 3301 adds r3, #1 80012dc: b29b uxth r3, r3 80012de: 88ba ldrh r2, [r7, #4] 80012e0: 4611 mov r1, r2 80012e2: 4618 mov r0, r3 80012e4: f000 f9d4 bl 8001690 80012e8: 4603 mov r3, r0 } 80012ea: 4618 mov r0, r3 80012ec: 3708 adds r7, #8 80012ee: 46bd mov sp, r7 80012f0: bd80 pop {r7, pc} 080012f2 : /* ========================================================================= */ /* --- Internal helpers ---------------------------------------------------- */ static uint16_t EE_GetPageStatus(uint32_t pageBase) { 80012f2: b480 push {r7} 80012f4: b083 sub sp, #12 80012f6: af00 add r7, sp, #0 80012f8: 6078 str r0, [r7, #4] return *(__IO uint16_t *)pageBase; 80012fa: 687b ldr r3, [r7, #4] 80012fc: 881b ldrh r3, [r3, #0] 80012fe: b29b uxth r3, r3 } 8001300: 4618 mov r0, r3 8001302: 370c adds r7, #12 8001304: 46bd mov sp, r7 8001306: bc80 pop {r7} 8001308: 4770 bx lr 0800130a : static HAL_StatusTypeDef EE_FlashProgramHalfWord(uint32_t Address, uint16_t Data) { 800130a: b5b0 push {r4, r5, r7, lr} 800130c: b084 sub sp, #16 800130e: af00 add r7, sp, #0 8001310: 6078 str r0, [r7, #4] 8001312: 460b mov r3, r1 8001314: 807b strh r3, [r7, #2] HAL_StatusTypeDef status; HAL_FLASH_Unlock(); 8001316: f004 feaf bl 8006078 status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, Address, Data); 800131a: 887b ldrh r3, [r7, #2] 800131c: 2200 movs r2, #0 800131e: 461c mov r4, r3 8001320: 4615 mov r5, r2 8001322: 4622 mov r2, r4 8001324: 462b mov r3, r5 8001326: 6879 ldr r1, [r7, #4] 8001328: 2001 movs r0, #1 800132a: f004 fe35 bl 8005f98 800132e: 4603 mov r3, r0 8001330: 73fb strb r3, [r7, #15] HAL_FLASH_Lock(); 8001332: f004 fec7 bl 80060c4 return status; 8001336: 7bfb ldrb r3, [r7, #15] } 8001338: 4618 mov r0, r3 800133a: 3710 adds r7, #16 800133c: 46bd mov sp, r7 800133e: bdb0 pop {r4, r5, r7, pc} 08001340 : static HAL_StatusTypeDef EE_FlashErasePage(uint32_t PageAddress) { 8001340: b580 push {r7, lr} 8001342: b088 sub sp, #32 8001344: af00 add r7, sp, #0 8001346: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; FLASH_EraseInitTypeDef EraseInit; uint32_t PageError = 0; 8001348: 2300 movs r3, #0 800134a: 60bb str r3, [r7, #8] HAL_FLASH_Unlock(); 800134c: f004 fe94 bl 8006078 EraseInit.TypeErase = FLASH_TYPEERASE_PAGES; 8001350: 2300 movs r3, #0 8001352: 60fb str r3, [r7, #12] EraseInit.PageAddress = PageAddress; 8001354: 687b ldr r3, [r7, #4] 8001356: 617b str r3, [r7, #20] EraseInit.NbPages = 1; 8001358: 2301 movs r3, #1 800135a: 61bb str r3, [r7, #24] status = HAL_FLASHEx_Erase(&EraseInit, &PageError); 800135c: f107 0208 add.w r2, r7, #8 8001360: f107 030c add.w r3, r7, #12 8001364: 4611 mov r1, r2 8001366: 4618 mov r0, r3 8001368: f004 ff6e bl 8006248 800136c: 4603 mov r3, r0 800136e: 77fb strb r3, [r7, #31] HAL_FLASH_Lock(); 8001370: f004 fea8 bl 80060c4 return status; 8001374: 7ffb ldrb r3, [r7, #31] } 8001376: 4618 mov r0, r3 8001378: 3720 adds r7, #32 800137a: 46bd mov sp, r7 800137c: bd80 pop {r7, pc} 0800137e : /* Find first free record address in given page (returns 0 if full) */ static uint32_t EE_FindFreeAddress(uint32_t pageBase) { 800137e: b480 push {r7} 8001380: b087 sub sp, #28 8001382: af00 add r7, sp, #0 8001384: 6078 str r0, [r7, #4] uint32_t addr = pageBase + 2U; /* Skip status word */ 8001386: 687b ldr r3, [r7, #4] 8001388: 3302 adds r3, #2 800138a: 617b str r3, [r7, #20] uint32_t pageEnd = pageBase + EE_PAGE_SIZE; 800138c: 687b ldr r3, [r7, #4] 800138e: f503 6380 add.w r3, r3, #1024 @ 0x400 8001392: 613b str r3, [r7, #16] while (addr < (pageEnd - sizeof(EE_Record_t) + 1U)) 8001394: e00c b.n 80013b0 { uint16_t vaddr = *(__IO uint16_t *)addr; 8001396: 697b ldr r3, [r7, #20] 8001398: 881b ldrh r3, [r3, #0] 800139a: 81fb strh r3, [r7, #14] if (vaddr == 0xFFFFU) 800139c: 89fb ldrh r3, [r7, #14] 800139e: f64f 72ff movw r2, #65535 @ 0xffff 80013a2: 4293 cmp r3, r2 80013a4: d101 bne.n 80013aa { /* Empty slot */ return addr; 80013a6: 697b ldr r3, [r7, #20] 80013a8: e008 b.n 80013bc } addr += sizeof(EE_Record_t); 80013aa: 697b ldr r3, [r7, #20] 80013ac: 3304 adds r3, #4 80013ae: 617b str r3, [r7, #20] while (addr < (pageEnd - sizeof(EE_Record_t) + 1U)) 80013b0: 693b ldr r3, [r7, #16] 80013b2: 3b03 subs r3, #3 80013b4: 697a ldr r2, [r7, #20] 80013b6: 429a cmp r2, r3 80013b8: d3ed bcc.n 8001396 } return 0U; /* No space */ 80013ba: 2300 movs r3, #0 } 80013bc: 4618 mov r0, r3 80013be: 371c adds r7, #28 80013c0: 46bd mov sp, r7 80013c2: bc80 pop {r7} 80013c4: 4770 bx lr 080013c6 : /* Find latest value of VirtAddress in a specific page (internal, uses EE_Status) */ /* Find latest value of VirtAddress in a specific page (scan forward) */ static EE_Status EE_FindInPage(uint32_t pageBase, uint16_t VirtAddress, uint16_t *Data) { 80013c6: b480 push {r7} 80013c8: b089 sub sp, #36 @ 0x24 80013ca: af00 add r7, sp, #0 80013cc: 60f8 str r0, [r7, #12] 80013ce: 460b mov r3, r1 80013d0: 607a str r2, [r7, #4] 80013d2: 817b strh r3, [r7, #10] uint32_t addr = pageBase + 2U; // skip status halfword 80013d4: 68fb ldr r3, [r7, #12] 80013d6: 3302 adds r3, #2 80013d8: 61fb str r3, [r7, #28] uint32_t pageEnd = pageBase + EE_PAGE_SIZE; 80013da: 68fb ldr r3, [r7, #12] 80013dc: f503 6380 add.w r3, r3, #1024 @ 0x400 80013e0: 617b str r3, [r7, #20] EE_Status result = EE_NOT_FOUND; 80013e2: 2302 movs r3, #2 80013e4: 76fb strb r3, [r7, #27] uint16_t lastVal = 0; 80013e6: 2300 movs r3, #0 80013e8: 833b strh r3, [r7, #24] if (Data == NULL) 80013ea: 687b ldr r3, [r7, #4] 80013ec: 2b00 cmp r3, #0 80013ee: d118 bne.n 8001422 return EE_ERROR; 80013f0: 2301 movs r3, #1 80013f2: e024 b.n 800143e while (addr <= (pageEnd - sizeof(EE_Record_t))) { uint16_t vaddr = *(__IO uint16_t *)addr; 80013f4: 69fb ldr r3, [r7, #28] 80013f6: 881b ldrh r3, [r3, #0] 80013f8: 827b strh r3, [r7, #18] if (vaddr == 0xFFFFU) 80013fa: 8a7b ldrh r3, [r7, #18] 80013fc: f64f 72ff movw r2, #65535 @ 0xffff 8001400: 4293 cmp r3, r2 8001402: d014 beq.n 800142e { // First empty slot => no more records in this page break; } uint16_t value = *(__IO uint16_t *)(addr + 2U); 8001404: 69fb ldr r3, [r7, #28] 8001406: 3302 adds r3, #2 8001408: 881b ldrh r3, [r3, #0] 800140a: 823b strh r3, [r7, #16] if (vaddr == VirtAddress) 800140c: 8a7a ldrh r2, [r7, #18] 800140e: 897b ldrh r3, [r7, #10] 8001410: 429a cmp r2, r3 8001412: d103 bne.n 800141c { lastVal = value; // keep most recent 8001414: 8a3b ldrh r3, [r7, #16] 8001416: 833b strh r3, [r7, #24] result = EE_OK; 8001418: 2300 movs r3, #0 800141a: 76fb strb r3, [r7, #27] } addr += sizeof(EE_Record_t); // move 4 bytes forward 800141c: 69fb ldr r3, [r7, #28] 800141e: 3304 adds r3, #4 8001420: 61fb str r3, [r7, #28] while (addr <= (pageEnd - sizeof(EE_Record_t))) 8001422: 697b ldr r3, [r7, #20] 8001424: 3b04 subs r3, #4 8001426: 69fa ldr r2, [r7, #28] 8001428: 429a cmp r2, r3 800142a: d9e3 bls.n 80013f4 800142c: e000 b.n 8001430 break; 800142e: bf00 nop } if (result == EE_OK) 8001430: 7efb ldrb r3, [r7, #27] 8001432: 2b00 cmp r3, #0 8001434: d102 bne.n 800143c *Data = lastVal; 8001436: 687b ldr r3, [r7, #4] 8001438: 8b3a ldrh r2, [r7, #24] 800143a: 801a strh r2, [r3, #0] return result; 800143c: 7efb ldrb r3, [r7, #27] } 800143e: 4618 mov r0, r3 8001440: 3724 adds r7, #36 @ 0x24 8001442: 46bd mov sp, r7 8001444: bc80 pop {r7} 8001446: 4770 bx lr 08001448 : /* Format both pages: erase and set PAGE0 as VALID */ static EE_Status EE_Format(void) { 8001448: b580 push {r7, lr} 800144a: af00 add r7, sp, #0 if (EE_FlashErasePage(EE_PAGE0_BASE) != HAL_OK) 800144c: 480f ldr r0, [pc, #60] @ (800148c ) 800144e: f7ff ff77 bl 8001340 8001452: 4603 mov r3, r0 8001454: 2b00 cmp r3, #0 8001456: d001 beq.n 800145c return EE_STATUS_ERROR; 8001458: 2301 movs r3, #1 800145a: e015 b.n 8001488 if (EE_FlashErasePage(EE_PAGE1_BASE) != HAL_OK) 800145c: 480c ldr r0, [pc, #48] @ (8001490 ) 800145e: f7ff ff6f bl 8001340 8001462: 4603 mov r3, r0 8001464: 2b00 cmp r3, #0 8001466: d001 beq.n 800146c return EE_STATUS_ERROR; 8001468: 2301 movs r3, #1 800146a: e00d b.n 8001488 if (EE_FlashProgramHalfWord(EE_PAGE0_BASE, EE_PAGE_STATUS_VALID) != HAL_OK) 800146c: f64a 21aa movw r1, #43690 @ 0xaaaa 8001470: 4806 ldr r0, [pc, #24] @ (800148c ) 8001472: f7ff ff4a bl 800130a 8001476: 4603 mov r3, r0 8001478: 2b00 cmp r3, #0 800147a: d001 beq.n 8001480 return EE_STATUS_ERROR; 800147c: 2301 movs r3, #1 800147e: e003 b.n 8001488 /* PAGE1 will remain erased (status = 0xFFFF) */ EE_ActivePageBase = EE_PAGE0_BASE; 8001480: 4b04 ldr r3, [pc, #16] @ (8001494 ) 8001482: 4a02 ldr r2, [pc, #8] @ (800148c ) 8001484: 601a str r2, [r3, #0] return EE_STATUS_OK; 8001486: 2300 movs r3, #0 } 8001488: 4618 mov r0, r3 800148a: bd80 pop {r7, pc} 800148c: 0800f800 .word 0x0800f800 8001490: 0800fc00 .word 0x0800fc00 8001494: 20000000 .word 0x20000000 08001498 : /* Get the base of the other page */ static uint32_t EE_GetOtherPageBase(uint32_t pageBase) { 8001498: b480 push {r7} 800149a: b083 sub sp, #12 800149c: af00 add r7, sp, #0 800149e: 6078 str r0, [r7, #4] return (pageBase == EE_PAGE0_BASE) ? EE_PAGE1_BASE : EE_PAGE0_BASE; 80014a0: 687b ldr r3, [r7, #4] 80014a2: 4a05 ldr r2, [pc, #20] @ (80014b8 ) 80014a4: 4293 cmp r3, r2 80014a6: d101 bne.n 80014ac 80014a8: 4b04 ldr r3, [pc, #16] @ (80014bc ) 80014aa: e000 b.n 80014ae 80014ac: 4b02 ldr r3, [pc, #8] @ (80014b8 ) } 80014ae: 4618 mov r0, r3 80014b0: 370c adds r7, #12 80014b2: 46bd mov sp, r7 80014b4: bc80 pop {r7} 80014b6: 4770 bx lr 80014b8: 0800f800 .word 0x0800f800 80014bc: 0800fc00 .word 0x0800fc00 080014c0 : /* Page transfer (garbage collection + new write) */ static EE_Status EE_PageTransfer(uint16_t VirtAddress, uint16_t Data) { 80014c0: b580 push {r7, lr} 80014c2: b088 sub sp, #32 80014c4: af00 add r7, sp, #0 80014c6: 4603 mov r3, r0 80014c8: 460a mov r2, r1 80014ca: 80fb strh r3, [r7, #6] 80014cc: 4613 mov r3, r2 80014ce: 80bb strh r3, [r7, #4] uint32_t oldBase = EE_ActivePageBase; 80014d0: 4b3c ldr r3, [pc, #240] @ (80015c4 ) 80014d2: 681b ldr r3, [r3, #0] 80014d4: 617b str r3, [r7, #20] uint32_t newBase = EE_GetOtherPageBase(oldBase); 80014d6: 6978 ldr r0, [r7, #20] 80014d8: f7ff ffde bl 8001498 80014dc: 6138 str r0, [r7, #16] uint32_t addr; uint16_t value; EE_Status st; /* Erase new page */ if (EE_FlashErasePage(newBase) != HAL_OK) 80014de: 6938 ldr r0, [r7, #16] 80014e0: f7ff ff2e bl 8001340 80014e4: 4603 mov r3, r0 80014e6: 2b00 cmp r3, #0 80014e8: d001 beq.n 80014ee return EE_STATUS_ERROR; 80014ea: 2301 movs r3, #1 80014ec: e065 b.n 80015ba /* Mark new page as RECEIVE */ if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_RECEIVE) != HAL_OK) 80014ee: f245 5155 movw r1, #21845 @ 0x5555 80014f2: 6938 ldr r0, [r7, #16] 80014f4: f7ff ff09 bl 800130a 80014f8: 4603 mov r3, r0 80014fa: 2b00 cmp r3, #0 80014fc: d001 beq.n 8001502 return EE_STATUS_ERROR; 80014fe: 2301 movs r3, #1 8001500: e05b b.n 80015ba /* Start writing records just after status */ addr = newBase + 2U; 8001502: 693b ldr r3, [r7, #16] 8001504: 3302 adds r3, #2 8001506: 61fb str r3, [r7, #28] /* For each known virtual variable */ for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++) 8001508: 2300 movs r3, #0 800150a: 837b strh r3, [r7, #26] 800150c: e03c b.n 8001588 { uint16_t vaddr = EE_VirtAddrs[i]; 800150e: 8b7b ldrh r3, [r7, #26] 8001510: 4a2d ldr r2, [pc, #180] @ (80015c8 ) 8001512: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8001516: 81fb strh r3, [r7, #14] if (vaddr == VirtAddress) 8001518: 89fa ldrh r2, [r7, #14] 800151a: 88fb ldrh r3, [r7, #6] 800151c: 429a cmp r2, r3 800151e: d102 bne.n 8001526 { /* Use the new data passed into PageTransfer */ value = Data; 8001520: 88bb ldrh r3, [r7, #4] 8001522: 817b strh r3, [r7, #10] 8001524: e00b b.n 800153e } else { /* Read latest value from old active page */ st = EE_FindInPage(oldBase, vaddr, &value); 8001526: f107 020a add.w r2, r7, #10 800152a: 89fb ldrh r3, [r7, #14] 800152c: 4619 mov r1, r3 800152e: 6978 ldr r0, [r7, #20] 8001530: f7ff ff49 bl 80013c6 8001534: 4603 mov r3, r0 8001536: 737b strb r3, [r7, #13] if (st != EE_STATUS_OK) 8001538: 7b7b ldrb r3, [r7, #13] 800153a: 2b00 cmp r3, #0 800153c: d120 bne.n 8001580 continue; } } /* Write record to new page */ if (EE_FlashProgramHalfWord(addr, vaddr) != HAL_OK) 800153e: 89fb ldrh r3, [r7, #14] 8001540: 4619 mov r1, r3 8001542: 69f8 ldr r0, [r7, #28] 8001544: f7ff fee1 bl 800130a 8001548: 4603 mov r3, r0 800154a: 2b00 cmp r3, #0 800154c: d001 beq.n 8001552 return EE_STATUS_ERROR; 800154e: 2301 movs r3, #1 8001550: e033 b.n 80015ba if (EE_FlashProgramHalfWord(addr + 2U, value) != HAL_OK) 8001552: 69fb ldr r3, [r7, #28] 8001554: 3302 adds r3, #2 8001556: 897a ldrh r2, [r7, #10] 8001558: 4611 mov r1, r2 800155a: 4618 mov r0, r3 800155c: f7ff fed5 bl 800130a 8001560: 4603 mov r3, r0 8001562: 2b00 cmp r3, #0 8001564: d001 beq.n 800156a return EE_STATUS_ERROR; 8001566: 2301 movs r3, #1 8001568: e027 b.n 80015ba addr += sizeof(EE_Record_t); 800156a: 69fb ldr r3, [r7, #28] 800156c: 3304 adds r3, #4 800156e: 61fb str r3, [r7, #28] if (addr >= (newBase + EE_PAGE_SIZE)) 8001570: 693b ldr r3, [r7, #16] 8001572: f503 6380 add.w r3, r3, #1024 @ 0x400 8001576: 69fa ldr r2, [r7, #28] 8001578: 429a cmp r2, r3 800157a: d302 bcc.n 8001582 return EE_STATUS_NO_SPACE; 800157c: 2303 movs r3, #3 800157e: e01c b.n 80015ba continue; 8001580: bf00 nop for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++) 8001582: 8b7b ldrh r3, [r7, #26] 8001584: 3301 adds r3, #1 8001586: 837b strh r3, [r7, #26] 8001588: 8b7b ldrh r3, [r7, #26] 800158a: 2b3f cmp r3, #63 @ 0x3f 800158c: d9bf bls.n 800150e } /* Erase old page */ if (EE_FlashErasePage(oldBase) != HAL_OK) 800158e: 6978 ldr r0, [r7, #20] 8001590: f7ff fed6 bl 8001340 8001594: 4603 mov r3, r0 8001596: 2b00 cmp r3, #0 8001598: d001 beq.n 800159e return EE_STATUS_ERROR; 800159a: 2301 movs r3, #1 800159c: e00d b.n 80015ba /* Mark new page as VALID */ if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_VALID) != HAL_OK) 800159e: f64a 21aa movw r1, #43690 @ 0xaaaa 80015a2: 6938 ldr r0, [r7, #16] 80015a4: f7ff feb1 bl 800130a 80015a8: 4603 mov r3, r0 80015aa: 2b00 cmp r3, #0 80015ac: d001 beq.n 80015b2 return EE_STATUS_ERROR; 80015ae: 2301 movs r3, #1 80015b0: e003 b.n 80015ba /* Update active page */ EE_ActivePageBase = newBase; 80015b2: 4a04 ldr r2, [pc, #16] @ (80015c4 ) 80015b4: 693b ldr r3, [r7, #16] 80015b6: 6013 str r3, [r2, #0] return EE_STATUS_OK; 80015b8: 2300 movs r3, #0 } 80015ba: 4618 mov r0, r3 80015bc: 3720 adds r7, #32 80015be: 46bd mov sp, r7 80015c0: bd80 pop {r7, pc} 80015c2: bf00 nop 80015c4: 20000000 .word 0x20000000 80015c8: 0800f530 .word 0x0800f530 080015cc : * - Checks page statuses and chooses the active page. * - If inconsistent or blank, formats pages. * PUBLIC RETURN TYPE: uint16_t (EE_OK / EE_ERROR / ...) */ uint16_t EE_Init(void) { 80015cc: b580 push {r7, lr} 80015ce: b082 sub sp, #8 80015d0: af00 add r7, sp, #0 uint16_t status0 = EE_GetPageStatus(EE_PAGE0_BASE); 80015d2: 481e ldr r0, [pc, #120] @ (800164c ) 80015d4: f7ff fe8d bl 80012f2 80015d8: 4603 mov r3, r0 80015da: 80fb strh r3, [r7, #6] uint16_t status1 = EE_GetPageStatus(EE_PAGE1_BASE); 80015dc: 481c ldr r0, [pc, #112] @ (8001650 ) 80015de: f7ff fe88 bl 80012f2 80015e2: 4603 mov r3, r0 80015e4: 80bb strh r3, [r7, #4] if ((status0 == EE_PAGE_STATUS_ERASED) && (status1 == EE_PAGE_STATUS_ERASED)) 80015e6: 88fb ldrh r3, [r7, #6] 80015e8: f64f 72ff movw r2, #65535 @ 0xffff 80015ec: 4293 cmp r3, r2 80015ee: d108 bne.n 8001602 80015f0: 88bb ldrh r3, [r7, #4] 80015f2: f64f 72ff movw r2, #65535 @ 0xffff 80015f6: 4293 cmp r3, r2 80015f8: d103 bne.n 8001602 { /* Fresh device -> format */ return (uint16_t)EE_Format(); 80015fa: f7ff ff25 bl 8001448 80015fe: 4603 mov r3, r0 8001600: e020 b.n 8001644 } else if ((status0 == EE_PAGE_STATUS_VALID) && (status1 == EE_PAGE_STATUS_ERASED)) 8001602: 88fb ldrh r3, [r7, #6] 8001604: f64a 22aa movw r2, #43690 @ 0xaaaa 8001608: 4293 cmp r3, r2 800160a: d109 bne.n 8001620 800160c: 88bb ldrh r3, [r7, #4] 800160e: f64f 72ff movw r2, #65535 @ 0xffff 8001612: 4293 cmp r3, r2 8001614: d104 bne.n 8001620 { EE_ActivePageBase = EE_PAGE0_BASE; 8001616: 4b0f ldr r3, [pc, #60] @ (8001654 ) 8001618: 4a0c ldr r2, [pc, #48] @ (800164c ) 800161a: 601a str r2, [r3, #0] return EE_OK; 800161c: 2300 movs r3, #0 800161e: e011 b.n 8001644 } else if ((status1 == EE_PAGE_STATUS_VALID) && (status0 == EE_PAGE_STATUS_ERASED)) 8001620: 88bb ldrh r3, [r7, #4] 8001622: f64a 22aa movw r2, #43690 @ 0xaaaa 8001626: 4293 cmp r3, r2 8001628: d109 bne.n 800163e 800162a: 88fb ldrh r3, [r7, #6] 800162c: f64f 72ff movw r2, #65535 @ 0xffff 8001630: 4293 cmp r3, r2 8001632: d104 bne.n 800163e { EE_ActivePageBase = EE_PAGE1_BASE; 8001634: 4b07 ldr r3, [pc, #28] @ (8001654 ) 8001636: 4a06 ldr r2, [pc, #24] @ (8001650 ) 8001638: 601a str r2, [r3, #0] return EE_OK; 800163a: 2300 movs r3, #0 800163c: e002 b.n 8001644 } else { /* Any weird or inconsistent state -> reformat */ return (uint16_t)EE_Format(); 800163e: f7ff ff03 bl 8001448 8001642: 4603 mov r3, r0 } } 8001644: 4618 mov r0, r3 8001646: 3708 adds r7, #8 8001648: 46bd mov sp, r7 800164a: bd80 pop {r7, pc} 800164c: 0800f800 .word 0x0800f800 8001650: 0800fc00 .word 0x0800fc00 8001654: 20000000 .word 0x20000000 08001658 : /* * Read a 16-bit variable by its virtual address. * PUBLIC RETURN: EE_OK / EE_NOT_FOUND / EE_ERROR (as uint16_t) */ uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data) { 8001658: b580 push {r7, lr} 800165a: b084 sub sp, #16 800165c: af00 add r7, sp, #0 800165e: 4603 mov r3, r0 8001660: 6039 str r1, [r7, #0] 8001662: 80fb strh r3, [r7, #6] EE_Status st; if (Data == NULL) 8001664: 683b ldr r3, [r7, #0] 8001666: 2b00 cmp r3, #0 8001668: d101 bne.n 800166e return EE_ERROR; 800166a: 2301 movs r3, #1 800166c: e00a b.n 8001684 st = EE_FindInPage(EE_ActivePageBase, VirtAddress, Data); 800166e: 4b07 ldr r3, [pc, #28] @ (800168c ) 8001670: 681b ldr r3, [r3, #0] 8001672: 88f9 ldrh r1, [r7, #6] 8001674: 683a ldr r2, [r7, #0] 8001676: 4618 mov r0, r3 8001678: f7ff fea5 bl 80013c6 800167c: 4603 mov r3, r0 800167e: 73fb strb r3, [r7, #15] return (uint16_t)st; 8001680: 7bfb ldrb r3, [r7, #15] 8001682: b29b uxth r3, r3 } 8001684: 4618 mov r0, r3 8001686: 3710 adds r7, #16 8001688: 46bd mov sp, r7 800168a: bd80 pop {r7, pc} 800168c: 20000000 .word 0x20000000 08001690 : * - Writes a new record in the active page. * - If the page is full, triggers a page transfer (GC). * PUBLIC RETURN: EE_OK / EE_ERROR / EE_NO_SPACE (as uint16_t) */ uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data) { 8001690: b580 push {r7, lr} 8001692: b084 sub sp, #16 8001694: af00 add r7, sp, #0 8001696: 4603 mov r3, r0 8001698: 460a mov r2, r1 800169a: 80fb strh r3, [r7, #6] 800169c: 4613 mov r3, r2 800169e: 80bb strh r3, [r7, #4] uint32_t freeAddr; EE_Status st; /* Find free space in active page */ freeAddr = EE_FindFreeAddress(EE_ActivePageBase); 80016a0: 4b17 ldr r3, [pc, #92] @ (8001700 ) 80016a2: 681b ldr r3, [r3, #0] 80016a4: 4618 mov r0, r3 80016a6: f7ff fe6a bl 800137e 80016aa: 60f8 str r0, [r7, #12] if (freeAddr != 0U) 80016ac: 68fb ldr r3, [r7, #12] 80016ae: 2b00 cmp r3, #0 80016b0: d017 beq.n 80016e2 { /* Write new record */ if (EE_FlashProgramHalfWord(freeAddr, VirtAddress) != HAL_OK) 80016b2: 88fb ldrh r3, [r7, #6] 80016b4: 4619 mov r1, r3 80016b6: 68f8 ldr r0, [r7, #12] 80016b8: f7ff fe27 bl 800130a 80016bc: 4603 mov r3, r0 80016be: 2b00 cmp r3, #0 80016c0: d001 beq.n 80016c6 return EE_ERROR; 80016c2: 2301 movs r3, #1 80016c4: e017 b.n 80016f6 if (EE_FlashProgramHalfWord(freeAddr + 2U, Data) != HAL_OK) 80016c6: 68fb ldr r3, [r7, #12] 80016c8: 3302 adds r3, #2 80016ca: 88ba ldrh r2, [r7, #4] 80016cc: 4611 mov r1, r2 80016ce: 4618 mov r0, r3 80016d0: f7ff fe1b bl 800130a 80016d4: 4603 mov r3, r0 80016d6: 2b00 cmp r3, #0 80016d8: d001 beq.n 80016de return EE_ERROR; 80016da: 2301 movs r3, #1 80016dc: e00b b.n 80016f6 return EE_OK; 80016de: 2300 movs r3, #0 80016e0: e009 b.n 80016f6 } /* No space -> page transfer */ st = EE_PageTransfer(VirtAddress, Data); 80016e2: 88ba ldrh r2, [r7, #4] 80016e4: 88fb ldrh r3, [r7, #6] 80016e6: 4611 mov r1, r2 80016e8: 4618 mov r0, r3 80016ea: f7ff fee9 bl 80014c0 80016ee: 4603 mov r3, r0 80016f0: 72fb strb r3, [r7, #11] return (uint16_t)st; 80016f2: 7afb ldrb r3, [r7, #11] 80016f4: b29b uxth r3, r3 } 80016f6: 4618 mov r0, r3 80016f8: 3710 adds r7, #16 80016fa: 46bd mov sp, r7 80016fc: bd80 pop {r7, pc} 80016fe: bf00 nop 8001700: 20000000 .word 0x20000000 08001704 : void loadDefault(void){ 8001704: b580 push {r7, lr} 8001706: b09a sub sp, #104 @ 0x68 8001708: af00 add r7, sp, #0 uint8_t i; char s[100]; uint16_t st; for(i=0;i st=EEW_Write(i,deftab[i]); 8001712: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8001716: 4a1e ldr r2, [pc, #120] @ (8001790 ) 8001718: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 800171c: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8001720: 4611 mov r1, r2 8001722: 4618 mov r0, r3 8001724: f7ff fdcf bl 80012c6 8001728: 4603 mov r3, r0 800172a: f8a7 3064 strh.w r3, [r7, #100] @ 0x64 if (st == EE_OK)sprintf((char*)s,"\ndone %d=%d",i,deftab[i]); 800172e: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64 8001732: 2b00 cmp r3, #0 8001734: d10b bne.n 800174e 8001736: f897 2067 ldrb.w r2, [r7, #103] @ 0x67 800173a: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 800173e: 4914 ldr r1, [pc, #80] @ (8001790 ) 8001740: f831 3013 ldrh.w r3, [r1, r3, lsl #1] 8001744: 4638 mov r0, r7 8001746: 4913 ldr r1, [pc, #76] @ (8001794 ) 8001748: f00c feb0 bl 800e4ac 800174c: e006 b.n 800175c else sprintf((char*)s,"\nee write error %d", st); 800174e: f8b7 2064 ldrh.w r2, [r7, #100] @ 0x64 8001752: 463b mov r3, r7 8001754: 4910 ldr r1, [pc, #64] @ (8001798 ) 8001756: 4618 mov r0, r3 8001758: f00c fea8 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 800175c: 463b mov r3, r7 800175e: 4618 mov r0, r3 8001760: f7fe fcf4 bl 800014c 8001764: 4603 mov r3, r0 8001766: b29a uxth r2, r3 8001768: 4639 mov r1, r7 800176a: f04f 33ff mov.w r3, #4294967295 800176e: 480b ldr r0, [pc, #44] @ (800179c ) 8001770: f008 f8ac bl 80098cc for(i=0;i } } 8001786: bf00 nop 8001788: bf00 nop 800178a: 3768 adds r7, #104 @ 0x68 800178c: 46bd mov sp, r7 800178e: bd80 pop {r7, pc} 8001790: 0800f4b0 .word 0x0800f4b0 8001794: 0800f224 .word 0x0800f224 8001798: 0800f230 .word 0x0800f230 800179c: 200003a8 .word 0x200003a8 080017a0 : void loadEE(void){ 80017a0: b5f0 push {r4, r5, r6, r7, lr} 80017a2: b0b9 sub sp, #228 @ 0xe4 80017a4: af06 add r7, sp, #24 char s [200]; EEW_Read(M1PWMAP, &m1pwmap); 80017a6: 49bc ldr r1, [pc, #752] @ (8001a98 ) 80017a8: 2000 movs r0, #0 80017aa: f7ff fd79 bl 80012a0 EEW_Read(M1PWMCH, &m1pwmch); 80017ae: 49bb ldr r1, [pc, #748] @ (8001a9c ) 80017b0: 2001 movs r0, #1 80017b2: f7ff fd75 bl 80012a0 EEW_Read(M2PWMAP, &m2pwmap); 80017b6: 49ba ldr r1, [pc, #744] @ (8001aa0 ) 80017b8: 2002 movs r0, #2 80017ba: f7ff fd71 bl 80012a0 EEW_Read(M2PWMCH, &m2pwmch); 80017be: 49b9 ldr r1, [pc, #740] @ (8001aa4 ) 80017c0: 2003 movs r0, #3 80017c2: f7ff fd6d bl 80012a0 EEW_Read(M3PWMAP, &m3pwmap); 80017c6: 49b8 ldr r1, [pc, #736] @ (8001aa8 ) 80017c8: 2004 movs r0, #4 80017ca: f7ff fd69 bl 80012a0 EEW_Read(M3PWMCH, &m3pwmch); 80017ce: 49b7 ldr r1, [pc, #732] @ (8001aac ) 80017d0: 2005 movs r0, #5 80017d2: f7ff fd65 bl 80012a0 EEW_Read(M4PWMAP, &m4pwmap); 80017d6: 49b6 ldr r1, [pc, #728] @ (8001ab0 ) 80017d8: 2006 movs r0, #6 80017da: f7ff fd61 bl 80012a0 EEW_Read(M4PWMCH, &m4pwmch); 80017de: 49b5 ldr r1, [pc, #724] @ (8001ab4 ) 80017e0: 2007 movs r0, #7 80017e2: f7ff fd5d bl 80012a0 EEW_Read(M1RAMPSTART, &mrampstart[M1-1]); 80017e6: 49b4 ldr r1, [pc, #720] @ (8001ab8 ) 80017e8: 2008 movs r0, #8 80017ea: f7ff fd59 bl 80012a0 EEW_Read(M2RAMPSTART, &mrampstart[M2-1]); 80017ee: 49b3 ldr r1, [pc, #716] @ (8001abc ) 80017f0: 2009 movs r0, #9 80017f2: f7ff fd55 bl 80012a0 EEW_Read(M3RAMPSTART, &mrampstart[M3-1]); 80017f6: 49b2 ldr r1, [pc, #712] @ (8001ac0 ) 80017f8: 200a movs r0, #10 80017fa: f7ff fd51 bl 80012a0 EEW_Read(M4RAMPSTART, &mrampstart[M4-1]); 80017fe: 49b1 ldr r1, [pc, #708] @ (8001ac4 ) 8001800: 200b movs r0, #11 8001802: f7ff fd4d bl 80012a0 EEW_Read(M1TIMEOUTMAN, &m1TimeoutMan); 8001806: 49b0 ldr r1, [pc, #704] @ (8001ac8 ) 8001808: 200c movs r0, #12 800180a: f7ff fd49 bl 80012a0 EEW_Read(M2TIMEOUTMAN, &m2TimeoutMan); 800180e: 49af ldr r1, [pc, #700] @ (8001acc ) 8001810: 200d movs r0, #13 8001812: f7ff fd45 bl 80012a0 EEW_Read(M3TIMEOUTMAN, &m3TimeoutMan); 8001816: 49ae ldr r1, [pc, #696] @ (8001ad0 ) 8001818: 200e movs r0, #14 800181a: f7ff fd41 bl 80012a0 EEW_Read(M4TIMEOUTMAN, &m4TimeoutMan); 800181e: 49ad ldr r1, [pc, #692] @ (8001ad4 ) 8001820: 200f movs r0, #15 8001822: f7ff fd3d bl 80012a0 EEW_Read(THANEM, &thanem); 8001826: 49ac ldr r1, [pc, #688] @ (8001ad8 ) 8001828: 2018 movs r0, #24 800182a: f7ff fd39 bl 80012a0 EEW_Read(TANEM, &tanem); 800182e: 49ab ldr r1, [pc, #684] @ (8001adc ) 8001830: 2019 movs r0, #25 8001832: f7ff fd35 bl 80012a0 EEW_Read(M1PWMMAN, &m1pwmMan); 8001836: 49aa ldr r1, [pc, #680] @ (8001ae0 ) 8001838: 201a movs r0, #26 800183a: f7ff fd31 bl 80012a0 EEW_Read(M2PWMMAN, &m2pwmMan); 800183e: 49a9 ldr r1, [pc, #676] @ (8001ae4 ) 8001840: 201b movs r0, #27 8001842: f7ff fd2d bl 80012a0 EEW_Read(M3PWMMAN, &m3pwmMan); 8001846: 49a8 ldr r1, [pc, #672] @ (8001ae8 ) 8001848: 201c movs r0, #28 800184a: f7ff fd29 bl 80012a0 EEW_Read(M4PWMMAN, &m4pwmMan); 800184e: 49a7 ldr r1, [pc, #668] @ (8001aec ) 8001850: 201d movs r0, #29 8001852: f7ff fd25 bl 80012a0 EEW_Read(TRAMPMAN, &trampman); 8001856: 49a6 ldr r1, [pc, #664] @ (8001af0 ) 8001858: 201e movs r0, #30 800185a: f7ff fd21 bl 80012a0 EEW_Read(TRAMP, &tramp); 800185e: 49a5 ldr r1, [pc, #660] @ (8001af4 ) 8001860: 201f movs r0, #31 8001862: f7ff fd1d bl 80012a0 EEW_Read(APM1START,&apM1start); 8001866: 49a4 ldr r1, [pc, #656] @ (8001af8 ) 8001868: 2020 movs r0, #32 800186a: f7ff fd19 bl 80012a0 EEW_Read(APM1STOP ,&apM1stop); 800186e: 49a3 ldr r1, [pc, #652] @ (8001afc ) 8001870: 2021 movs r0, #33 @ 0x21 8001872: f7ff fd15 bl 80012a0 EEW_Read(APM2START,&apM2start); 8001876: 49a2 ldr r1, [pc, #648] @ (8001b00 ) 8001878: 2022 movs r0, #34 @ 0x22 800187a: f7ff fd11 bl 80012a0 EEW_Read(APM2STOP ,&apM2stop); 800187e: 49a1 ldr r1, [pc, #644] @ (8001b04 ) 8001880: 2023 movs r0, #35 @ 0x23 8001882: f7ff fd0d bl 80012a0 EEW_Read(APM3START,&apM3start); 8001886: 49a0 ldr r1, [pc, #640] @ (8001b08 ) 8001888: 2024 movs r0, #36 @ 0x24 800188a: f7ff fd09 bl 80012a0 EEW_Read(APM3STOP ,&apM3stop); 800188e: 499f ldr r1, [pc, #636] @ (8001b0c ) 8001890: 2025 movs r0, #37 @ 0x25 8001892: f7ff fd05 bl 80012a0 EEW_Read(APM4START,&apM4start); 8001896: 499e ldr r1, [pc, #632] @ (8001b10 ) 8001898: 2026 movs r0, #38 @ 0x26 800189a: f7ff fd01 bl 80012a0 EEW_Read(APM4STOP ,&apM4stop); 800189e: 499d ldr r1, [pc, #628] @ (8001b14 ) 80018a0: 2027 movs r0, #39 @ 0x27 80018a2: f7ff fcfd bl 80012a0 EEW_Read(CHM1START,&chM1start); 80018a6: 499c ldr r1, [pc, #624] @ (8001b18 ) 80018a8: 2028 movs r0, #40 @ 0x28 80018aa: f7ff fcf9 bl 80012a0 EEW_Read(CHM1STOP ,&chM1stop); 80018ae: 499b ldr r1, [pc, #620] @ (8001b1c ) 80018b0: 2029 movs r0, #41 @ 0x29 80018b2: f7ff fcf5 bl 80012a0 EEW_Read(CHM2START,&chM2start); 80018b6: 499a ldr r1, [pc, #616] @ (8001b20 ) 80018b8: 202a movs r0, #42 @ 0x2a 80018ba: f7ff fcf1 bl 80012a0 EEW_Read(CHM2STOP ,&chM2stop); 80018be: 4999 ldr r1, [pc, #612] @ (8001b24 ) 80018c0: 202b movs r0, #43 @ 0x2b 80018c2: f7ff fced bl 80012a0 EEW_Read(CHM3START,&chM3start); 80018c6: 4998 ldr r1, [pc, #608] @ (8001b28 ) 80018c8: 202c movs r0, #44 @ 0x2c 80018ca: f7ff fce9 bl 80012a0 EEW_Read(CHM3STOP ,&chM3stop); 80018ce: 4997 ldr r1, [pc, #604] @ (8001b2c ) 80018d0: 202d movs r0, #45 @ 0x2d 80018d2: f7ff fce5 bl 80012a0 EEW_Read(CHM4START,&chM4start); 80018d6: 4996 ldr r1, [pc, #600] @ (8001b30 ) 80018d8: 202e movs r0, #46 @ 0x2e 80018da: f7ff fce1 bl 80012a0 EEW_Read(CHM4STOP ,&chM4stop); 80018de: 4995 ldr r1, [pc, #596] @ (8001b34 ) 80018e0: 202f movs r0, #47 @ 0x2f 80018e2: f7ff fcdd bl 80012a0 EEW_Read(FLAGPAR ,&flagPar); 80018e6: 4994 ldr r1, [pc, #592] @ (8001b38 ) 80018e8: 203f movs r0, #63 @ 0x3f 80018ea: f7ff fcd9 bl 80012a0 sprintf((char*)s,"LoadEE\n"); 80018ee: 463b mov r3, r7 80018f0: 4992 ldr r1, [pc, #584] @ (8001b3c ) 80018f2: 4618 mov r0, r3 80018f4: f00c fdda bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 80018f8: 463b mov r3, r7 80018fa: 4618 mov r0, r3 80018fc: f7fe fc26 bl 800014c 8001900: 4603 mov r3, r0 8001902: b29a uxth r2, r3 8001904: 4639 mov r1, r7 8001906: f04f 33ff mov.w r3, #4294967295 800190a: 488d ldr r0, [pc, #564] @ (8001b40 ) 800190c: f007 ffde bl 80098cc sprintf((char*)s,"\nm1pwmap=%d m1pwmch=%d m2pwmap=%d m2pwmch=%d m3pwmap=%d m3pwmch=%d m4pwmap=%d m4pwmch=%d",m1pwmap,m1pwmch,m2pwmap,m2pwmch,m3pwmap,m3pwmch,m4pwmap, m4pwmch); 8001910: 4b61 ldr r3, [pc, #388] @ (8001a98 ) 8001912: 881b ldrh r3, [r3, #0] 8001914: 469c mov ip, r3 8001916: 4b61 ldr r3, [pc, #388] @ (8001a9c ) 8001918: 881b ldrh r3, [r3, #0] 800191a: 469e mov lr, r3 800191c: 4b60 ldr r3, [pc, #384] @ (8001aa0 ) 800191e: 881b ldrh r3, [r3, #0] 8001920: 461a mov r2, r3 8001922: 4b60 ldr r3, [pc, #384] @ (8001aa4 ) 8001924: 881b ldrh r3, [r3, #0] 8001926: 4619 mov r1, r3 8001928: 4b5f ldr r3, [pc, #380] @ (8001aa8 ) 800192a: 881b ldrh r3, [r3, #0] 800192c: 461c mov r4, r3 800192e: 4b5f ldr r3, [pc, #380] @ (8001aac ) 8001930: 881b ldrh r3, [r3, #0] 8001932: 461d mov r5, r3 8001934: 4b5e ldr r3, [pc, #376] @ (8001ab0 ) 8001936: 881b ldrh r3, [r3, #0] 8001938: 461e mov r6, r3 800193a: 4b5e ldr r3, [pc, #376] @ (8001ab4 ) 800193c: 881b ldrh r3, [r3, #0] 800193e: 4638 mov r0, r7 8001940: 9305 str r3, [sp, #20] 8001942: 9604 str r6, [sp, #16] 8001944: 9503 str r5, [sp, #12] 8001946: 9402 str r4, [sp, #8] 8001948: 9101 str r1, [sp, #4] 800194a: 9200 str r2, [sp, #0] 800194c: 4673 mov r3, lr 800194e: 4662 mov r2, ip 8001950: 497c ldr r1, [pc, #496] @ (8001b44 ) 8001952: f00c fdab bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001956: 463b mov r3, r7 8001958: 4618 mov r0, r3 800195a: f7fe fbf7 bl 800014c 800195e: 4603 mov r3, r0 8001960: b29a uxth r2, r3 8001962: 4639 mov r1, r7 8001964: f04f 33ff mov.w r3, #4294967295 8001968: 4875 ldr r0, [pc, #468] @ (8001b40 ) 800196a: f007 ffaf bl 80098cc sprintf((char*)s,"\nm1TimeoutMan=%d m2TimeoutMan=%d m3TimeoutMan=%d m4TimeoutMan=%d ",m1TimeoutMan,m2TimeoutMan,m3TimeoutMan,m4TimeoutMan); 800196e: 4b56 ldr r3, [pc, #344] @ (8001ac8 ) 8001970: 881b ldrh r3, [r3, #0] 8001972: 4619 mov r1, r3 8001974: 4b55 ldr r3, [pc, #340] @ (8001acc ) 8001976: 881b ldrh r3, [r3, #0] 8001978: 461c mov r4, r3 800197a: 4b55 ldr r3, [pc, #340] @ (8001ad0 ) 800197c: 881b ldrh r3, [r3, #0] 800197e: 461a mov r2, r3 8001980: 4b54 ldr r3, [pc, #336] @ (8001ad4 ) 8001982: 881b ldrh r3, [r3, #0] 8001984: 4638 mov r0, r7 8001986: 9301 str r3, [sp, #4] 8001988: 9200 str r2, [sp, #0] 800198a: 4623 mov r3, r4 800198c: 460a mov r2, r1 800198e: 496e ldr r1, [pc, #440] @ (8001b48 ) 8001990: f00c fd8c bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001994: 463b mov r3, r7 8001996: 4618 mov r0, r3 8001998: f7fe fbd8 bl 800014c 800199c: 4603 mov r3, r0 800199e: b29a uxth r2, r3 80019a0: 4639 mov r1, r7 80019a2: f04f 33ff mov.w r3, #4294967295 80019a6: 4866 ldr r0, [pc, #408] @ (8001b40 ) 80019a8: f007 ff90 bl 80098cc sprintf((char*)s,"\ntramp=%d trampman=%d",tramp,trampman); 80019ac: 4b51 ldr r3, [pc, #324] @ (8001af4 ) 80019ae: 881b ldrh r3, [r3, #0] 80019b0: 461a mov r2, r3 80019b2: 4b4f ldr r3, [pc, #316] @ (8001af0 ) 80019b4: 881b ldrh r3, [r3, #0] 80019b6: 4638 mov r0, r7 80019b8: 4964 ldr r1, [pc, #400] @ (8001b4c ) 80019ba: f00c fd77 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 80019be: 463b mov r3, r7 80019c0: 4618 mov r0, r3 80019c2: f7fe fbc3 bl 800014c 80019c6: 4603 mov r3, r0 80019c8: b29a uxth r2, r3 80019ca: 4639 mov r1, r7 80019cc: f04f 33ff mov.w r3, #4294967295 80019d0: 485b ldr r0, [pc, #364] @ (8001b40 ) 80019d2: f007 ff7b bl 80098cc sprintf((char*)s,"\nm1pwmMan=%d m2pwmMan=%d m3pwmMan=%d m4pwmMan=%d",m1pwmMan,m2pwmMan,m3pwmMan,m4pwmMan); 80019d6: 4b42 ldr r3, [pc, #264] @ (8001ae0 ) 80019d8: 881b ldrh r3, [r3, #0] 80019da: 4619 mov r1, r3 80019dc: 4b41 ldr r3, [pc, #260] @ (8001ae4 ) 80019de: 881b ldrh r3, [r3, #0] 80019e0: 461c mov r4, r3 80019e2: 4b41 ldr r3, [pc, #260] @ (8001ae8 ) 80019e4: 881b ldrh r3, [r3, #0] 80019e6: 461a mov r2, r3 80019e8: 4b40 ldr r3, [pc, #256] @ (8001aec ) 80019ea: 881b ldrh r3, [r3, #0] 80019ec: 4638 mov r0, r7 80019ee: 9301 str r3, [sp, #4] 80019f0: 9200 str r2, [sp, #0] 80019f2: 4623 mov r3, r4 80019f4: 460a mov r2, r1 80019f6: 4956 ldr r1, [pc, #344] @ (8001b50 ) 80019f8: f00c fd58 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 80019fc: 463b mov r3, r7 80019fe: 4618 mov r0, r3 8001a00: f7fe fba4 bl 800014c 8001a04: 4603 mov r3, r0 8001a06: b29a uxth r2, r3 8001a08: 4639 mov r1, r7 8001a0a: f04f 33ff mov.w r3, #4294967295 8001a0e: 484c ldr r0, [pc, #304] @ (8001b40 ) 8001a10: f007 ff5c bl 80098cc sprintf((char*)s,"\napM1start=%d apM1stop=%d chM1start=%d chM1stop=%d",apM1start,apM1stop,chM1start,chM1stop); 8001a14: 4b38 ldr r3, [pc, #224] @ (8001af8 ) 8001a16: 881b ldrh r3, [r3, #0] 8001a18: 4619 mov r1, r3 8001a1a: 4b38 ldr r3, [pc, #224] @ (8001afc ) 8001a1c: 881b ldrh r3, [r3, #0] 8001a1e: 461c mov r4, r3 8001a20: 4b3d ldr r3, [pc, #244] @ (8001b18 ) 8001a22: 881b ldrh r3, [r3, #0] 8001a24: 461a mov r2, r3 8001a26: 4b3d ldr r3, [pc, #244] @ (8001b1c ) 8001a28: 881b ldrh r3, [r3, #0] 8001a2a: 4638 mov r0, r7 8001a2c: 9301 str r3, [sp, #4] 8001a2e: 9200 str r2, [sp, #0] 8001a30: 4623 mov r3, r4 8001a32: 460a mov r2, r1 8001a34: 4947 ldr r1, [pc, #284] @ (8001b54 ) 8001a36: f00c fd39 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001a3a: 463b mov r3, r7 8001a3c: 4618 mov r0, r3 8001a3e: f7fe fb85 bl 800014c 8001a42: 4603 mov r3, r0 8001a44: b29a uxth r2, r3 8001a46: 4639 mov r1, r7 8001a48: f04f 33ff mov.w r3, #4294967295 8001a4c: 483c ldr r0, [pc, #240] @ (8001b40 ) 8001a4e: f007 ff3d bl 80098cc sprintf((char*)s,"\napM2start=%d apM2stop=%d chM2start=%d chM2stop=%d",apM2start,apM2stop,chM2start,chM2stop); 8001a52: 4b2b ldr r3, [pc, #172] @ (8001b00 ) 8001a54: 881b ldrh r3, [r3, #0] 8001a56: 4619 mov r1, r3 8001a58: 4b2a ldr r3, [pc, #168] @ (8001b04 ) 8001a5a: 881b ldrh r3, [r3, #0] 8001a5c: 461c mov r4, r3 8001a5e: 4b30 ldr r3, [pc, #192] @ (8001b20 ) 8001a60: 881b ldrh r3, [r3, #0] 8001a62: 461a mov r2, r3 8001a64: 4b2f ldr r3, [pc, #188] @ (8001b24 ) 8001a66: 881b ldrh r3, [r3, #0] 8001a68: 4638 mov r0, r7 8001a6a: 9301 str r3, [sp, #4] 8001a6c: 9200 str r2, [sp, #0] 8001a6e: 4623 mov r3, r4 8001a70: 460a mov r2, r1 8001a72: 4939 ldr r1, [pc, #228] @ (8001b58 ) 8001a74: f00c fd1a bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001a78: 463b mov r3, r7 8001a7a: 4618 mov r0, r3 8001a7c: f7fe fb66 bl 800014c 8001a80: 4603 mov r3, r0 8001a82: b29a uxth r2, r3 8001a84: 4639 mov r1, r7 8001a86: f04f 33ff mov.w r3, #4294967295 8001a8a: 482d ldr r0, [pc, #180] @ (8001b40 ) 8001a8c: f007 ff1e bl 80098cc sprintf((char*)s,"\napM3start=%d apM3stop=%d chM3start=%d chM3stop=%d",apM3start,apM3stop,chM3start,chM3stop); 8001a90: 4b1d ldr r3, [pc, #116] @ (8001b08 ) 8001a92: 881b ldrh r3, [r3, #0] 8001a94: 4619 mov r1, r3 8001a96: e061 b.n 8001b5c 8001a98: 20000400 .word 0x20000400 8001a9c: 20000402 .word 0x20000402 8001aa0: 20000404 .word 0x20000404 8001aa4: 20000406 .word 0x20000406 8001aa8: 20000408 .word 0x20000408 8001aac: 2000040a .word 0x2000040a 8001ab0: 2000040c .word 0x2000040c 8001ab4: 2000040e .word 0x2000040e 8001ab8: 2000044c .word 0x2000044c 8001abc: 2000044e .word 0x2000044e 8001ac0: 20000450 .word 0x20000450 8001ac4: 20000452 .word 0x20000452 8001ac8: 20000410 .word 0x20000410 8001acc: 20000412 .word 0x20000412 8001ad0: 20000414 .word 0x20000414 8001ad4: 20000416 .word 0x20000416 8001ad8: 2000041c .word 0x2000041c 8001adc: 2000041a .word 0x2000041a 8001ae0: 20000420 .word 0x20000420 8001ae4: 20000422 .word 0x20000422 8001ae8: 20000424 .word 0x20000424 8001aec: 20000426 .word 0x20000426 8001af0: 2000041e .word 0x2000041e 8001af4: 20000418 .word 0x20000418 8001af8: 20000428 .word 0x20000428 8001afc: 2000042a .word 0x2000042a 8001b00: 2000042c .word 0x2000042c 8001b04: 2000042e .word 0x2000042e 8001b08: 20000430 .word 0x20000430 8001b0c: 20000432 .word 0x20000432 8001b10: 20000434 .word 0x20000434 8001b14: 20000436 .word 0x20000436 8001b18: 20000438 .word 0x20000438 8001b1c: 2000043a .word 0x2000043a 8001b20: 2000043c .word 0x2000043c 8001b24: 2000043e .word 0x2000043e 8001b28: 20000440 .word 0x20000440 8001b2c: 20000442 .word 0x20000442 8001b30: 20000444 .word 0x20000444 8001b34: 20000446 .word 0x20000446 8001b38: 20000448 .word 0x20000448 8001b3c: 0800f244 .word 0x0800f244 8001b40: 200003a8 .word 0x200003a8 8001b44: 0800f24c .word 0x0800f24c 8001b48: 0800f2a8 .word 0x0800f2a8 8001b4c: 0800f2ec .word 0x0800f2ec 8001b50: 0800f304 .word 0x0800f304 8001b54: 0800f338 .word 0x0800f338 8001b58: 0800f36c .word 0x0800f36c 8001b5c: 4b1f ldr r3, [pc, #124] @ (8001bdc ) 8001b5e: 881b ldrh r3, [r3, #0] 8001b60: 461c mov r4, r3 8001b62: 4b1f ldr r3, [pc, #124] @ (8001be0 ) 8001b64: 881b ldrh r3, [r3, #0] 8001b66: 461a mov r2, r3 8001b68: 4b1e ldr r3, [pc, #120] @ (8001be4 ) 8001b6a: 881b ldrh r3, [r3, #0] 8001b6c: 4638 mov r0, r7 8001b6e: 9301 str r3, [sp, #4] 8001b70: 9200 str r2, [sp, #0] 8001b72: 4623 mov r3, r4 8001b74: 460a mov r2, r1 8001b76: 491c ldr r1, [pc, #112] @ (8001be8 ) 8001b78: f00c fc98 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001b7c: 463b mov r3, r7 8001b7e: 4618 mov r0, r3 8001b80: f7fe fae4 bl 800014c 8001b84: 4603 mov r3, r0 8001b86: b29a uxth r2, r3 8001b88: 4639 mov r1, r7 8001b8a: f04f 33ff mov.w r3, #4294967295 8001b8e: 4817 ldr r0, [pc, #92] @ (8001bec ) 8001b90: f007 fe9c bl 80098cc sprintf((char*)s,"\napM4start=%d apM4stop=%d chM4start=%d chM4stop=%d",apM4start,apM4stop,chM4start,chM4stop); 8001b94: 4b16 ldr r3, [pc, #88] @ (8001bf0 ) 8001b96: 881b ldrh r3, [r3, #0] 8001b98: 4619 mov r1, r3 8001b9a: 4b16 ldr r3, [pc, #88] @ (8001bf4 ) 8001b9c: 881b ldrh r3, [r3, #0] 8001b9e: 461c mov r4, r3 8001ba0: 4b15 ldr r3, [pc, #84] @ (8001bf8 ) 8001ba2: 881b ldrh r3, [r3, #0] 8001ba4: 461a mov r2, r3 8001ba6: 4b15 ldr r3, [pc, #84] @ (8001bfc ) 8001ba8: 881b ldrh r3, [r3, #0] 8001baa: 4638 mov r0, r7 8001bac: 9301 str r3, [sp, #4] 8001bae: 9200 str r2, [sp, #0] 8001bb0: 4623 mov r3, r4 8001bb2: 460a mov r2, r1 8001bb4: 4912 ldr r1, [pc, #72] @ (8001c00 ) 8001bb6: f00c fc79 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8001bba: 463b mov r3, r7 8001bbc: 4618 mov r0, r3 8001bbe: f7fe fac5 bl 800014c 8001bc2: 4603 mov r3, r0 8001bc4: b29a uxth r2, r3 8001bc6: 4639 mov r1, r7 8001bc8: f04f 33ff mov.w r3, #4294967295 8001bcc: 4807 ldr r0, [pc, #28] @ (8001bec ) 8001bce: f007 fe7d bl 80098cc } 8001bd2: bf00 nop 8001bd4: 37cc adds r7, #204 @ 0xcc 8001bd6: 46bd mov sp, r7 8001bd8: bdf0 pop {r4, r5, r6, r7, pc} 8001bda: bf00 nop 8001bdc: 20000432 .word 0x20000432 8001be0: 20000440 .word 0x20000440 8001be4: 20000442 .word 0x20000442 8001be8: 0800f3a0 .word 0x0800f3a0 8001bec: 200003a8 .word 0x200003a8 8001bf0: 20000434 .word 0x20000434 8001bf4: 20000436 .word 0x20000436 8001bf8: 20000444 .word 0x20000444 8001bfc: 20000446 .word 0x20000446 8001c00: 0800f3d4 .word 0x0800f3d4 08001c04 : /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ void HAL_SYSTICK_Callback(void) { 8001c04: b580 push {r7, lr} 8001c06: b082 sub sp, #8 8001c08: af00 add r7, sp, #0 static uint8_t c1s = 0; static uint8_t inidx = 0; static uint8_t inbuf[4]; uint8_t i; if (++c10ms >= 10) { // 10 ms 8001c0a: 4b7c ldr r3, [pc, #496] @ (8001dfc ) 8001c0c: 781b ldrb r3, [r3, #0] 8001c0e: 3301 adds r3, #1 8001c10: b2da uxtb r2, r3 8001c12: 4b7a ldr r3, [pc, #488] @ (8001dfc ) 8001c14: 701a strb r2, [r3, #0] 8001c16: 4b79 ldr r3, [pc, #484] @ (8001dfc ) 8001c18: 781b ldrb r3, [r3, #0] 8001c1a: 2b09 cmp r3, #9 8001c1c: f240 81e7 bls.w 8001fee c10ms = 0; 8001c20: 4b76 ldr r3, [pc, #472] @ (8001dfc ) 8001c22: 2200 movs r2, #0 8001c24: 701a strb r2, [r3, #0] if (rtP1) 8001c26: 4b76 ldr r3, [pc, #472] @ (8001e00 ) 8001c28: 781b ldrb r3, [r3, #0] 8001c2a: b2db uxtb r3, r3 8001c2c: 2b00 cmp r3, #0 8001c2e: d006 beq.n 8001c3e rtP1--; 8001c30: 4b73 ldr r3, [pc, #460] @ (8001e00 ) 8001c32: 781b ldrb r3, [r3, #0] 8001c34: b2db uxtb r3, r3 8001c36: 3b01 subs r3, #1 8001c38: b2da uxtb r2, r3 8001c3a: 4b71 ldr r3, [pc, #452] @ (8001e00 ) 8001c3c: 701a strb r2, [r3, #0] if (rtP2) 8001c3e: 4b71 ldr r3, [pc, #452] @ (8001e04 ) 8001c40: 781b ldrb r3, [r3, #0] 8001c42: b2db uxtb r3, r3 8001c44: 2b00 cmp r3, #0 8001c46: d006 beq.n 8001c56 rtP2--; 8001c48: 4b6e ldr r3, [pc, #440] @ (8001e04 ) 8001c4a: 781b ldrb r3, [r3, #0] 8001c4c: b2db uxtb r3, r3 8001c4e: 3b01 subs r3, #1 8001c50: b2da uxtb r2, r3 8001c52: 4b6c ldr r3, [pc, #432] @ (8001e04 ) 8001c54: 701a strb r2, [r3, #0] if (rtTLC) 8001c56: 4b6c ldr r3, [pc, #432] @ (8001e08 ) 8001c58: 781b ldrb r3, [r3, #0] 8001c5a: b2db uxtb r3, r3 8001c5c: 2b00 cmp r3, #0 8001c5e: d006 beq.n 8001c6e rtTLC--; 8001c60: 4b69 ldr r3, [pc, #420] @ (8001e08 ) 8001c62: 781b ldrb r3, [r3, #0] 8001c64: b2db uxtb r3, r3 8001c66: 3b01 subs r3, #1 8001c68: b2da uxtb r2, r3 8001c6a: 4b67 ldr r3, [pc, #412] @ (8001e08 ) 8001c6c: 701a strb r2, [r3, #0] //**** legge i tasti******************************************************************************** inidx++; 8001c6e: 4b67 ldr r3, [pc, #412] @ (8001e0c ) 8001c70: 781b ldrb r3, [r3, #0] 8001c72: 3301 adds r3, #1 8001c74: b2da uxtb r2, r3 8001c76: 4b65 ldr r3, [pc, #404] @ (8001e0c ) 8001c78: 701a strb r2, [r3, #0] inidx &= 0x03; 8001c7a: 4b64 ldr r3, [pc, #400] @ (8001e0c ) 8001c7c: 781b ldrb r3, [r3, #0] 8001c7e: f003 0303 and.w r3, r3, #3 8001c82: b2da uxtb r2, r3 8001c84: 4b61 ldr r3, [pc, #388] @ (8001e0c ) 8001c86: 701a strb r2, [r3, #0] if (HAL_GPIO_ReadPin(P1_GPIO_Port, P1_Pin) == GPIO_PIN_RESET) 8001c88: f44f 4180 mov.w r1, #16384 @ 0x4000 8001c8c: 4860 ldr r0, [pc, #384] @ (8001e10 ) 8001c8e: f004 fd07 bl 80066a0 8001c92: 4603 mov r3, r0 8001c94: 2b00 cmp r3, #0 8001c96: d10c bne.n 8001cb2 inbuf[inidx] |= INP1; 8001c98: 4b5c ldr r3, [pc, #368] @ (8001e0c ) 8001c9a: 781b ldrb r3, [r3, #0] 8001c9c: 461a mov r2, r3 8001c9e: 4b5d ldr r3, [pc, #372] @ (8001e14 ) 8001ca0: 5c9b ldrb r3, [r3, r2] 8001ca2: 4a5a ldr r2, [pc, #360] @ (8001e0c ) 8001ca4: 7812 ldrb r2, [r2, #0] 8001ca6: f043 0301 orr.w r3, r3, #1 8001caa: b2d9 uxtb r1, r3 8001cac: 4b59 ldr r3, [pc, #356] @ (8001e14 ) 8001cae: 5499 strb r1, [r3, r2] 8001cb0: e00b b.n 8001cca else inbuf[inidx] &= (~INP1); 8001cb2: 4b56 ldr r3, [pc, #344] @ (8001e0c ) 8001cb4: 781b ldrb r3, [r3, #0] 8001cb6: 461a mov r2, r3 8001cb8: 4b56 ldr r3, [pc, #344] @ (8001e14 ) 8001cba: 5c9b ldrb r3, [r3, r2] 8001cbc: 4a53 ldr r2, [pc, #332] @ (8001e0c ) 8001cbe: 7812 ldrb r2, [r2, #0] 8001cc0: f023 0301 bic.w r3, r3, #1 8001cc4: b2d9 uxtb r1, r3 8001cc6: 4b53 ldr r3, [pc, #332] @ (8001e14 ) 8001cc8: 5499 strb r1, [r3, r2] if (HAL_GPIO_ReadPin(P2_GPIO_Port, P2_Pin) == GPIO_PIN_RESET) 8001cca: f44f 4100 mov.w r1, #32768 @ 0x8000 8001cce: 4850 ldr r0, [pc, #320] @ (8001e10 ) 8001cd0: f004 fce6 bl 80066a0 8001cd4: 4603 mov r3, r0 8001cd6: 2b00 cmp r3, #0 8001cd8: d10c bne.n 8001cf4 inbuf[inidx] |= INP2; 8001cda: 4b4c ldr r3, [pc, #304] @ (8001e0c ) 8001cdc: 781b ldrb r3, [r3, #0] 8001cde: 461a mov r2, r3 8001ce0: 4b4c ldr r3, [pc, #304] @ (8001e14 ) 8001ce2: 5c9b ldrb r3, [r3, r2] 8001ce4: 4a49 ldr r2, [pc, #292] @ (8001e0c ) 8001ce6: 7812 ldrb r2, [r2, #0] 8001ce8: f043 0302 orr.w r3, r3, #2 8001cec: b2d9 uxtb r1, r3 8001cee: 4b49 ldr r3, [pc, #292] @ (8001e14 ) 8001cf0: 5499 strb r1, [r3, r2] 8001cf2: e00b b.n 8001d0c else inbuf[inidx] &= (~INP2); 8001cf4: 4b45 ldr r3, [pc, #276] @ (8001e0c ) 8001cf6: 781b ldrb r3, [r3, #0] 8001cf8: 461a mov r2, r3 8001cfa: 4b46 ldr r3, [pc, #280] @ (8001e14 ) 8001cfc: 5c9b ldrb r3, [r3, r2] 8001cfe: 4a43 ldr r2, [pc, #268] @ (8001e0c ) 8001d00: 7812 ldrb r2, [r2, #0] 8001d02: f023 0302 bic.w r3, r3, #2 8001d06: b2d9 uxtb r1, r3 8001d08: 4b42 ldr r3, [pc, #264] @ (8001e14 ) 8001d0a: 5499 strb r1, [r3, r2] if (HAL_GPIO_ReadPin(CH1_GPIO_Port, CH1_Pin) == GPIO_PIN_RESET) 8001d0c: f44f 5180 mov.w r1, #4096 @ 0x1000 8001d10: 4841 ldr r0, [pc, #260] @ (8001e18 ) 8001d12: f004 fcc5 bl 80066a0 8001d16: 4603 mov r3, r0 8001d18: 2b00 cmp r3, #0 8001d1a: d10c bne.n 8001d36 inbuf[inidx] |= INCH1; 8001d1c: 4b3b ldr r3, [pc, #236] @ (8001e0c ) 8001d1e: 781b ldrb r3, [r3, #0] 8001d20: 461a mov r2, r3 8001d22: 4b3c ldr r3, [pc, #240] @ (8001e14 ) 8001d24: 5c9b ldrb r3, [r3, r2] 8001d26: 4a39 ldr r2, [pc, #228] @ (8001e0c ) 8001d28: 7812 ldrb r2, [r2, #0] 8001d2a: f043 0304 orr.w r3, r3, #4 8001d2e: b2d9 uxtb r1, r3 8001d30: 4b38 ldr r3, [pc, #224] @ (8001e14 ) 8001d32: 5499 strb r1, [r3, r2] 8001d34: e00b b.n 8001d4e else inbuf[inidx] &= (~INCH1); 8001d36: 4b35 ldr r3, [pc, #212] @ (8001e0c ) 8001d38: 781b ldrb r3, [r3, #0] 8001d3a: 461a mov r2, r3 8001d3c: 4b35 ldr r3, [pc, #212] @ (8001e14 ) 8001d3e: 5c9b ldrb r3, [r3, r2] 8001d40: 4a32 ldr r2, [pc, #200] @ (8001e0c ) 8001d42: 7812 ldrb r2, [r2, #0] 8001d44: f023 0304 bic.w r3, r3, #4 8001d48: b2d9 uxtb r1, r3 8001d4a: 4b32 ldr r3, [pc, #200] @ (8001e14 ) 8001d4c: 5499 strb r1, [r3, r2] if (HAL_GPIO_ReadPin(CH2_GPIO_Port, CH2_Pin) == GPIO_PIN_RESET) 8001d4e: f44f 5100 mov.w r1, #8192 @ 0x2000 8001d52: 4831 ldr r0, [pc, #196] @ (8001e18 ) 8001d54: f004 fca4 bl 80066a0 8001d58: 4603 mov r3, r0 8001d5a: 2b00 cmp r3, #0 8001d5c: d10c bne.n 8001d78 inbuf[inidx] |= INCH2; 8001d5e: 4b2b ldr r3, [pc, #172] @ (8001e0c ) 8001d60: 781b ldrb r3, [r3, #0] 8001d62: 461a mov r2, r3 8001d64: 4b2b ldr r3, [pc, #172] @ (8001e14 ) 8001d66: 5c9b ldrb r3, [r3, r2] 8001d68: 4a28 ldr r2, [pc, #160] @ (8001e0c ) 8001d6a: 7812 ldrb r2, [r2, #0] 8001d6c: f043 0308 orr.w r3, r3, #8 8001d70: b2d9 uxtb r1, r3 8001d72: 4b28 ldr r3, [pc, #160] @ (8001e14 ) 8001d74: 5499 strb r1, [r3, r2] 8001d76: e00b b.n 8001d90 else inbuf[inidx] &= (~INCH2); 8001d78: 4b24 ldr r3, [pc, #144] @ (8001e0c ) 8001d7a: 781b ldrb r3, [r3, #0] 8001d7c: 461a mov r2, r3 8001d7e: 4b25 ldr r3, [pc, #148] @ (8001e14 ) 8001d80: 5c9b ldrb r3, [r3, r2] 8001d82: 4a22 ldr r2, [pc, #136] @ (8001e0c ) 8001d84: 7812 ldrb r2, [r2, #0] 8001d86: f023 0308 bic.w r3, r3, #8 8001d8a: b2d9 uxtb r1, r3 8001d8c: 4b21 ldr r3, [pc, #132] @ (8001e14 ) 8001d8e: 5499 strb r1, [r3, r2] if (HAL_GPIO_ReadPin(CH3_GPIO_Port, CH3_Pin) == GPIO_PIN_RESET) 8001d90: f44f 4180 mov.w r1, #16384 @ 0x4000 8001d94: 4820 ldr r0, [pc, #128] @ (8001e18 ) 8001d96: f004 fc83 bl 80066a0 8001d9a: 4603 mov r3, r0 8001d9c: 2b00 cmp r3, #0 8001d9e: d10c bne.n 8001dba inbuf[inidx] |= INCH3; 8001da0: 4b1a ldr r3, [pc, #104] @ (8001e0c ) 8001da2: 781b ldrb r3, [r3, #0] 8001da4: 461a mov r2, r3 8001da6: 4b1b ldr r3, [pc, #108] @ (8001e14 ) 8001da8: 5c9b ldrb r3, [r3, r2] 8001daa: 4a18 ldr r2, [pc, #96] @ (8001e0c ) 8001dac: 7812 ldrb r2, [r2, #0] 8001dae: f043 0310 orr.w r3, r3, #16 8001db2: b2d9 uxtb r1, r3 8001db4: 4b17 ldr r3, [pc, #92] @ (8001e14 ) 8001db6: 5499 strb r1, [r3, r2] 8001db8: e00b b.n 8001dd2 else inbuf[inidx] &= (~INCH3); 8001dba: 4b14 ldr r3, [pc, #80] @ (8001e0c ) 8001dbc: 781b ldrb r3, [r3, #0] 8001dbe: 461a mov r2, r3 8001dc0: 4b14 ldr r3, [pc, #80] @ (8001e14 ) 8001dc2: 5c9b ldrb r3, [r3, r2] 8001dc4: 4a11 ldr r2, [pc, #68] @ (8001e0c ) 8001dc6: 7812 ldrb r2, [r2, #0] 8001dc8: f023 0310 bic.w r3, r3, #16 8001dcc: b2d9 uxtb r1, r3 8001dce: 4b11 ldr r3, [pc, #68] @ (8001e14 ) 8001dd0: 5499 strb r1, [r3, r2] if (HAL_GPIO_ReadPin(CH4_GPIO_Port, CH4_Pin) == GPIO_PIN_RESET) 8001dd2: f44f 4100 mov.w r1, #32768 @ 0x8000 8001dd6: 4810 ldr r0, [pc, #64] @ (8001e18 ) 8001dd8: f004 fc62 bl 80066a0 8001ddc: 4603 mov r3, r0 8001dde: 2b00 cmp r3, #0 8001de0: d11c bne.n 8001e1c inbuf[inidx] |= INCH4; 8001de2: 4b0a ldr r3, [pc, #40] @ (8001e0c ) 8001de4: 781b ldrb r3, [r3, #0] 8001de6: 461a mov r2, r3 8001de8: 4b0a ldr r3, [pc, #40] @ (8001e14 ) 8001dea: 5c9b ldrb r3, [r3, r2] 8001dec: 4a07 ldr r2, [pc, #28] @ (8001e0c ) 8001dee: 7812 ldrb r2, [r2, #0] 8001df0: f043 0320 orr.w r3, r3, #32 8001df4: b2d9 uxtb r1, r3 8001df6: 4b07 ldr r3, [pc, #28] @ (8001e14 ) 8001df8: 5499 strb r1, [r3, r2] 8001dfa: e01b b.n 8001e34 8001dfc: 2000045a .word 0x2000045a 8001e00: 20000004 .word 0x20000004 8001e04: 20000005 .word 0x20000005 8001e08: 20000006 .word 0x20000006 8001e0c: 2000045b .word 0x2000045b 8001e10: 40011000 .word 0x40011000 8001e14: 2000045c .word 0x2000045c 8001e18: 40010c00 .word 0x40010c00 else inbuf[inidx] &= (~INCH4); 8001e1c: 4b76 ldr r3, [pc, #472] @ (8001ff8 ) 8001e1e: 781b ldrb r3, [r3, #0] 8001e20: 461a mov r2, r3 8001e22: 4b76 ldr r3, [pc, #472] @ (8001ffc ) 8001e24: 5c9b ldrb r3, [r3, r2] 8001e26: 4a74 ldr r2, [pc, #464] @ (8001ff8 ) 8001e28: 7812 ldrb r2, [r2, #0] 8001e2a: f023 0320 bic.w r3, r3, #32 8001e2e: b2d9 uxtb r1, r3 8001e30: 4b72 ldr r3, [pc, #456] @ (8001ffc ) 8001e32: 5499 strb r1, [r3, r2] pulsanti |= (inbuf[0] & inbuf[1] & inbuf[2] & inbuf[3]); 8001e34: 4b71 ldr r3, [pc, #452] @ (8001ffc ) 8001e36: 781a ldrb r2, [r3, #0] 8001e38: 4b70 ldr r3, [pc, #448] @ (8001ffc ) 8001e3a: 785b ldrb r3, [r3, #1] 8001e3c: 4013 ands r3, r2 8001e3e: b2da uxtb r2, r3 8001e40: 4b6e ldr r3, [pc, #440] @ (8001ffc ) 8001e42: 789b ldrb r3, [r3, #2] 8001e44: 4013 ands r3, r2 8001e46: b2da uxtb r2, r3 8001e48: 4b6c ldr r3, [pc, #432] @ (8001ffc ) 8001e4a: 78db ldrb r3, [r3, #3] 8001e4c: 4013 ands r3, r2 8001e4e: b2da uxtb r2, r3 8001e50: 4b6b ldr r3, [pc, #428] @ (8002000 ) 8001e52: 781b ldrb r3, [r3, #0] 8001e54: 4313 orrs r3, r2 8001e56: b2da uxtb r2, r3 8001e58: 4b69 ldr r3, [pc, #420] @ (8002000 ) 8001e5a: 701a strb r2, [r3, #0] pulsanti &= (inbuf[0] | inbuf[1] | inbuf[2] | inbuf[3]); 8001e5c: 4b67 ldr r3, [pc, #412] @ (8001ffc ) 8001e5e: 781a ldrb r2, [r3, #0] 8001e60: 4b66 ldr r3, [pc, #408] @ (8001ffc ) 8001e62: 785b ldrb r3, [r3, #1] 8001e64: 4313 orrs r3, r2 8001e66: b2da uxtb r2, r3 8001e68: 4b64 ldr r3, [pc, #400] @ (8001ffc ) 8001e6a: 789b ldrb r3, [r3, #2] 8001e6c: 4313 orrs r3, r2 8001e6e: b2da uxtb r2, r3 8001e70: 4b62 ldr r3, [pc, #392] @ (8001ffc ) 8001e72: 78db ldrb r3, [r3, #3] 8001e74: 4313 orrs r3, r2 8001e76: b2da uxtb r2, r3 8001e78: 4b61 ldr r3, [pc, #388] @ (8002000 ) 8001e7a: 781b ldrb r3, [r3, #0] 8001e7c: 4013 ands r3, r2 8001e7e: b2da uxtb r2, r3 8001e80: 4b5f ldr r3, [pc, #380] @ (8002000 ) 8001e82: 701a strb r2, [r3, #0] //**** legge adc *********************************************************************************** readAdc(); 8001e84: f7fe f9a0 bl 80001c8 if (++c100ms >= 10) { // 10 ms 8001e88: 4b5e ldr r3, [pc, #376] @ (8002004 ) 8001e8a: 781b ldrb r3, [r3, #0] 8001e8c: 3301 adds r3, #1 8001e8e: b2da uxtb r2, r3 8001e90: 4b5c ldr r3, [pc, #368] @ (8002004 ) 8001e92: 701a strb r2, [r3, #0] 8001e94: 4b5b ldr r3, [pc, #364] @ (8002004 ) 8001e96: 781b ldrb r3, [r3, #0] 8001e98: 2b09 cmp r3, #9 8001e9a: f240 80a8 bls.w 8001fee c100ms = 0; //flag_10ms = 1; // set a flag; do real work in main loop 8001e9e: 4b59 ldr r3, [pc, #356] @ (8002004 ) 8001ea0: 2200 movs r2, #0 8001ea2: 701a strb r2, [r3, #0] for (i = 0; i < 4; i++) { 8001ea4: 2300 movs r3, #0 8001ea6: 71fb strb r3, [r7, #7] 8001ea8: e013 b.n 8001ed2 if (rtramp[i]) 8001eaa: 79fb ldrb r3, [r7, #7] 8001eac: 4a56 ldr r2, [pc, #344] @ (8002008 ) 8001eae: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8001eb2: b29b uxth r3, r3 8001eb4: 2b00 cmp r3, #0 8001eb6: d009 beq.n 8001ecc rtramp[i]--; 8001eb8: 79fb ldrb r3, [r7, #7] 8001eba: 4a53 ldr r2, [pc, #332] @ (8002008 ) 8001ebc: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 8001ec0: b292 uxth r2, r2 8001ec2: 3a01 subs r2, #1 8001ec4: b291 uxth r1, r2 8001ec6: 4a50 ldr r2, [pc, #320] @ (8002008 ) 8001ec8: f822 1013 strh.w r1, [r2, r3, lsl #1] for (i = 0; i < 4; i++) { 8001ecc: 79fb ldrb r3, [r7, #7] 8001ece: 3301 adds r3, #1 8001ed0: 71fb strb r3, [r7, #7] 8001ed2: 79fb ldrb r3, [r7, #7] 8001ed4: 2b03 cmp r3, #3 8001ed6: d9e8 bls.n 8001eaa } if (rtCiclo < 0xffff)rtCiclo++; 8001ed8: 4b4c ldr r3, [pc, #304] @ (800200c ) 8001eda: 881b ldrh r3, [r3, #0] 8001edc: b29b uxth r3, r3 8001ede: f64f 72ff movw r2, #65535 @ 0xffff 8001ee2: 4293 cmp r3, r2 8001ee4: d006 beq.n 8001ef4 8001ee6: 4b49 ldr r3, [pc, #292] @ (800200c ) 8001ee8: 881b ldrh r3, [r3, #0] 8001eea: b29b uxth r3, r3 8001eec: 3301 adds r3, #1 8001eee: b29a uxth r2, r3 8001ef0: 4b46 ldr r3, [pc, #280] @ (800200c ) 8001ef2: 801a strh r2, [r3, #0] if (rtAnem)rtAnem--; 8001ef4: 4b46 ldr r3, [pc, #280] @ (8002010 ) 8001ef6: 881b ldrh r3, [r3, #0] 8001ef8: b29b uxth r3, r3 8001efa: 2b00 cmp r3, #0 8001efc: d006 beq.n 8001f0c 8001efe: 4b44 ldr r3, [pc, #272] @ (8002010 ) 8001f00: 881b ldrh r3, [r3, #0] 8001f02: b29b uxth r3, r3 8001f04: 3b01 subs r3, #1 8001f06: b29a uxth r2, r3 8001f08: 4b41 ldr r3, [pc, #260] @ (8002010 ) 8001f0a: 801a strh r2, [r3, #0] //**** gestione buzzer ***************************************************************************** if (stBuz == bzmoving) { 8001f0c: 4b41 ldr r3, [pc, #260] @ (8002014 ) 8001f0e: 781b ldrb r3, [r3, #0] 8001f10: b2db uxtb r3, r3 8001f12: 2b01 cmp r3, #1 8001f14: d127 bne.n 8001f66 if (nobuz) { 8001f16: 4b40 ldr r3, [pc, #256] @ (8002018 ) 8001f18: 781b ldrb r3, [r3, #0] 8001f1a: 2b00 cmp r3, #0 8001f1c: d011 beq.n 8001f42 if (c1s >= 5) 8001f1e: 4b3f ldr r3, [pc, #252] @ (800201c ) 8001f20: 781b ldrb r3, [r3, #0] 8001f22: 2b04 cmp r3, #4 8001f24: d906 bls.n 8001f34 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, 8001f26: 2200 movs r2, #0 8001f28: f44f 5100 mov.w r1, #8192 @ 0x2000 8001f2c: 483c ldr r0, [pc, #240] @ (8002020 ) 8001f2e: f004 fbce bl 80066ce 8001f32: e04f b.n 8001fd4 GPIO_PIN_RESET); else HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, 8001f34: 2201 movs r2, #1 8001f36: f44f 5100 mov.w r1, #8192 @ 0x2000 8001f3a: 4839 ldr r0, [pc, #228] @ (8002020 ) 8001f3c: f004 fbc7 bl 80066ce 8001f40: e048 b.n 8001fd4 GPIO_PIN_SET); } else { if (c1s >= 5) 8001f42: 4b36 ldr r3, [pc, #216] @ (800201c ) 8001f44: 781b ldrb r3, [r3, #0] 8001f46: 2b04 cmp r3, #4 8001f48: d906 bls.n 8001f58 HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_RESET); 8001f4a: 2200 movs r2, #0 8001f4c: f44f 7180 mov.w r1, #256 @ 0x100 8001f50: 4834 ldr r0, [pc, #208] @ (8002024 ) 8001f52: f004 fbbc bl 80066ce 8001f56: e03d b.n 8001fd4 else HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_SET); 8001f58: 2201 movs r2, #1 8001f5a: f44f 7180 mov.w r1, #256 @ 0x100 8001f5e: 4831 ldr r0, [pc, #196] @ (8002024 ) 8001f60: f004 fbb5 bl 80066ce 8001f64: e036 b.n 8001fd4 } } else if (stBuz == bzwarning) { 8001f66: 4b2b ldr r3, [pc, #172] @ (8002014 ) 8001f68: 781b ldrb r3, [r3, #0] 8001f6a: b2db uxtb r3, r3 8001f6c: 2b02 cmp r3, #2 8001f6e: d12b bne.n 8001fc8 if (nobuz) { 8001f70: 4b29 ldr r3, [pc, #164] @ (8002018 ) 8001f72: 781b ldrb r3, [r3, #0] 8001f74: 2b00 cmp r3, #0 8001f76: d013 beq.n 8001fa0 if (c1s & 1) 8001f78: 4b28 ldr r3, [pc, #160] @ (800201c ) 8001f7a: 781b ldrb r3, [r3, #0] 8001f7c: f003 0301 and.w r3, r3, #1 8001f80: 2b00 cmp r3, #0 8001f82: d006 beq.n 8001f92 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, 8001f84: 2200 movs r2, #0 8001f86: f44f 5100 mov.w r1, #8192 @ 0x2000 8001f8a: 4825 ldr r0, [pc, #148] @ (8002020 ) 8001f8c: f004 fb9f bl 80066ce 8001f90: e020 b.n 8001fd4 GPIO_PIN_RESET); else HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, 8001f92: 2201 movs r2, #1 8001f94: f44f 5100 mov.w r1, #8192 @ 0x2000 8001f98: 4821 ldr r0, [pc, #132] @ (8002020 ) 8001f9a: f004 fb98 bl 80066ce 8001f9e: e019 b.n 8001fd4 GPIO_PIN_SET); } else { if (c1s & 1) 8001fa0: 4b1e ldr r3, [pc, #120] @ (800201c ) 8001fa2: 781b ldrb r3, [r3, #0] 8001fa4: f003 0301 and.w r3, r3, #1 8001fa8: 2b00 cmp r3, #0 8001faa: d006 beq.n 8001fba HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_RESET); 8001fac: 2200 movs r2, #0 8001fae: f44f 7180 mov.w r1, #256 @ 0x100 8001fb2: 481c ldr r0, [pc, #112] @ (8002024 ) 8001fb4: f004 fb8b bl 80066ce 8001fb8: e00c b.n 8001fd4 else HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_SET); 8001fba: 2201 movs r2, #1 8001fbc: f44f 7180 mov.w r1, #256 @ 0x100 8001fc0: 4818 ldr r0, [pc, #96] @ (8002024 ) 8001fc2: f004 fb84 bl 80066ce 8001fc6: e005 b.n 8001fd4 } } else { //bzoff HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_RESET); 8001fc8: 2200 movs r2, #0 8001fca: f44f 7180 mov.w r1, #256 @ 0x100 8001fce: 4815 ldr r0, [pc, #84] @ (8002024 ) 8001fd0: f004 fb7d bl 80066ce } //************************************************************************************************** if (++c1s >= 10) { // 1 s 8001fd4: 4b11 ldr r3, [pc, #68] @ (800201c ) 8001fd6: 781b ldrb r3, [r3, #0] 8001fd8: 3301 adds r3, #1 8001fda: b2da uxtb r2, r3 8001fdc: 4b0f ldr r3, [pc, #60] @ (800201c ) 8001fde: 701a strb r2, [r3, #0] 8001fe0: 4b0e ldr r3, [pc, #56] @ (800201c ) 8001fe2: 781b ldrb r3, [r3, #0] 8001fe4: 2b09 cmp r3, #9 8001fe6: d902 bls.n 8001fee c1s = 0; 8001fe8: 4b0c ldr r3, [pc, #48] @ (800201c ) 8001fea: 2200 movs r2, #0 8001fec: 701a strb r2, [r3, #0] //HAL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin); } } } } 8001fee: bf00 nop 8001ff0: 3708 adds r7, #8 8001ff2: 46bd mov sp, r7 8001ff4: bd80 pop {r7, pc} 8001ff6: bf00 nop 8001ff8: 2000045b .word 0x2000045b 8001ffc: 2000045c .word 0x2000045c 8002000: 200003f0 .word 0x200003f0 8002004: 20000460 .word 0x20000460 8002008: 200003f4 .word 0x200003f4 800200c: 200003fc .word 0x200003fc 8002010: 200003fe .word 0x200003fe 8002014: 20000457 .word 0x20000457 8002018: 20000458 .word 0x20000458 800201c: 20000461 .word 0x20000461 8002020: 40011000 .word 0x40011000 8002024: 40010800 .word 0x40010800 08002028 : void managePulsanti(void) { 8002028: b580 push {r7, lr} 800202a: af00 add r7, sp, #0 if (pulsanti & INP1) { 800202c: 4bac ldr r3, [pc, #688] @ (80022e0 ) 800202e: 781b ldrb r3, [r3, #0] 8002030: f003 0301 and.w r3, r3, #1 8002034: 2b00 cmp r3, #0 8002036: d013 beq.n 8002060 if (rtP1 == 0) 8002038: 4baa ldr r3, [pc, #680] @ (80022e4 ) 800203a: 781b ldrb r3, [r3, #0] 800203c: b2db uxtb r3, r3 800203e: 2b00 cmp r3, #0 8002040: d107 bne.n 8002052 stPulsanti |= P1START; 8002042: 4ba9 ldr r3, [pc, #676] @ (80022e8 ) 8002044: 881b ldrh r3, [r3, #0] 8002046: f043 0301 orr.w r3, r3, #1 800204a: b29a uxth r2, r3 800204c: 4ba6 ldr r3, [pc, #664] @ (80022e8 ) 800204e: 801a strh r2, [r3, #0] 8002050: e036 b.n 80020c0 else { HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); 8002052: 2201 movs r2, #1 8002054: f44f 5100 mov.w r1, #8192 @ 0x2000 8002058: 48a4 ldr r0, [pc, #656] @ (80022ec ) 800205a: f004 fb38 bl 80066ce 800205e: e02f b.n 80020c0 } } else { if (stPulsanti & P1START) { 8002060: 4ba1 ldr r3, [pc, #644] @ (80022e8 ) 8002062: 881b ldrh r3, [r3, #0] 8002064: f003 0301 and.w r3, r3, #1 8002068: 2b00 cmp r3, #0 800206a: d014 beq.n 8002096 stPulsanti &= (~P1START); 800206c: 4b9e ldr r3, [pc, #632] @ (80022e8 ) 800206e: 881b ldrh r3, [r3, #0] 8002070: f023 0301 bic.w r3, r3, #1 8002074: b29a uxth r2, r3 8002076: 4b9c ldr r3, [pc, #624] @ (80022e8 ) 8002078: 801a strh r2, [r3, #0] stPulsanti|=P1RELEASED; 800207a: 4b9b ldr r3, [pc, #620] @ (80022e8 ) 800207c: 881b ldrh r3, [r3, #0] 800207e: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8002082: b29a uxth r2, r3 8002084: 4b98 ldr r3, [pc, #608] @ (80022e8 ) 8002086: 801a strh r2, [r3, #0] HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 8002088: 2200 movs r2, #0 800208a: f44f 5100 mov.w r1, #8192 @ 0x2000 800208e: 4897 ldr r0, [pc, #604] @ (80022ec ) 8002090: f004 fb1d bl 80066ce 8002094: e011 b.n 80020ba } else if (rtP1 <= 190) { 8002096: 4b93 ldr r3, [pc, #588] @ (80022e4 ) 8002098: 781b ldrb r3, [r3, #0] 800209a: b2db uxtb r3, r3 800209c: 2bbe cmp r3, #190 @ 0xbe 800209e: d80c bhi.n 80020ba stPulsanti |= P1STOP; 80020a0: 4b91 ldr r3, [pc, #580] @ (80022e8 ) 80020a2: 881b ldrh r3, [r3, #0] 80020a4: f043 0302 orr.w r3, r3, #2 80020a8: b29a uxth r2, r3 80020aa: 4b8f ldr r3, [pc, #572] @ (80022e8 ) 80020ac: 801a strh r2, [r3, #0] HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 80020ae: 2200 movs r2, #0 80020b0: f44f 5100 mov.w r1, #8192 @ 0x2000 80020b4: 488d ldr r0, [pc, #564] @ (80022ec ) 80020b6: f004 fb0a bl 80066ce } rtP1 = 200; 80020ba: 4b8a ldr r3, [pc, #552] @ (80022e4 ) 80020bc: 22c8 movs r2, #200 @ 0xc8 80020be: 701a strb r2, [r3, #0] } if (pulsanti & INP2) { 80020c0: 4b87 ldr r3, [pc, #540] @ (80022e0 ) 80020c2: 781b ldrb r3, [r3, #0] 80020c4: f003 0302 and.w r3, r3, #2 80020c8: 2b00 cmp r3, #0 80020ca: d00c beq.n 80020e6 if (rtP2 == 0) 80020cc: 4b88 ldr r3, [pc, #544] @ (80022f0 ) 80020ce: 781b ldrb r3, [r3, #0] 80020d0: b2db uxtb r3, r3 80020d2: 2b00 cmp r3, #0 80020d4: d124 bne.n 8002120 stPulsanti |= P2START; 80020d6: 4b84 ldr r3, [pc, #528] @ (80022e8 ) 80020d8: 881b ldrh r3, [r3, #0] 80020da: f043 0304 orr.w r3, r3, #4 80020de: b29a uxth r2, r3 80020e0: 4b81 ldr r3, [pc, #516] @ (80022e8 ) 80020e2: 801a strh r2, [r3, #0] 80020e4: e01c b.n 8002120 } else { if (stPulsanti & P2START) 80020e6: 4b80 ldr r3, [pc, #512] @ (80022e8 ) 80020e8: 881b ldrh r3, [r3, #0] 80020ea: f003 0304 and.w r3, r3, #4 80020ee: 2b00 cmp r3, #0 80020f0: d007 beq.n 8002102 stPulsanti &= (~P2START); 80020f2: 4b7d ldr r3, [pc, #500] @ (80022e8 ) 80020f4: 881b ldrh r3, [r3, #0] 80020f6: f023 0304 bic.w r3, r3, #4 80020fa: b29a uxth r2, r3 80020fc: 4b7a ldr r3, [pc, #488] @ (80022e8 ) 80020fe: 801a strh r2, [r3, #0] 8002100: e00b b.n 800211a else if (rtP2 <= 190) 8002102: 4b7b ldr r3, [pc, #492] @ (80022f0 ) 8002104: 781b ldrb r3, [r3, #0] 8002106: b2db uxtb r3, r3 8002108: 2bbe cmp r3, #190 @ 0xbe 800210a: d806 bhi.n 800211a stPulsanti |= P2STOP; 800210c: 4b76 ldr r3, [pc, #472] @ (80022e8 ) 800210e: 881b ldrh r3, [r3, #0] 8002110: f043 0308 orr.w r3, r3, #8 8002114: b29a uxth r2, r3 8002116: 4b74 ldr r3, [pc, #464] @ (80022e8 ) 8002118: 801a strh r2, [r3, #0] rtP2 = 200; 800211a: 4b75 ldr r3, [pc, #468] @ (80022f0 ) 800211c: 22c8 movs r2, #200 @ 0xc8 800211e: 701a strb r2, [r3, #0] } stPulsanti &= (P1START | P1STOP | P2START | P2STOP |P1RELEASED); 8002120: 4b71 ldr r3, [pc, #452] @ (80022e8 ) 8002122: 881a ldrh r2, [r3, #0] 8002124: f241 030f movw r3, #4111 @ 0x100f 8002128: 4013 ands r3, r2 800212a: b29a uxth r2, r3 800212c: 4b6e ldr r3, [pc, #440] @ (80022e8 ) 800212e: 801a strh r2, [r3, #0] if (stPulsanti == 0) { 8002130: 4b6d ldr r3, [pc, #436] @ (80022e8 ) 8002132: 881b ldrh r3, [r3, #0] 8002134: 2b00 cmp r3, #0 8002136: f040 80e0 bne.w 80022fa switch (pulsanti & 0x3c) { 800213a: 4b69 ldr r3, [pc, #420] @ (80022e0 ) 800213c: 781b ldrb r3, [r3, #0] 800213e: f003 033c and.w r3, r3, #60 @ 0x3c 8002142: 2b30 cmp r3, #48 @ 0x30 8002144: f200 80bb bhi.w 80022be 8002148: a201 add r2, pc, #4 @ (adr r2, 8002150 ) 800214a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800214e: bf00 nop 8002150: 08002215 .word 0x08002215 8002154: 080022bf .word 0x080022bf 8002158: 080022bf .word 0x080022bf 800215c: 080022bf .word 0x080022bf 8002160: 08002271 .word 0x08002271 8002164: 080022bf .word 0x080022bf 8002168: 080022bf .word 0x080022bf 800216c: 080022bf .word 0x080022bf 8002170: 08002223 .word 0x08002223 8002174: 080022bf .word 0x080022bf 8002178: 080022bf .word 0x080022bf 800217c: 080022bf .word 0x080022bf 8002180: 080022a5 .word 0x080022a5 8002184: 080022bf .word 0x080022bf 8002188: 080022bf .word 0x080022bf 800218c: 080022bf .word 0x080022bf 8002190: 0800223d .word 0x0800223d 8002194: 080022bf .word 0x080022bf 8002198: 080022bf .word 0x080022bf 800219c: 080022bf .word 0x080022bf 80021a0: 080022bf .word 0x080022bf 80021a4: 080022bf .word 0x080022bf 80021a8: 080022bf .word 0x080022bf 80021ac: 080022bf .word 0x080022bf 80021b0: 080022bf .word 0x080022bf 80021b4: 080022bf .word 0x080022bf 80021b8: 080022bf .word 0x080022bf 80021bc: 080022bf .word 0x080022bf 80021c0: 080022bf .word 0x080022bf 80021c4: 080022bf .word 0x080022bf 80021c8: 080022bf .word 0x080022bf 80021cc: 080022bf .word 0x080022bf 80021d0: 08002257 .word 0x08002257 80021d4: 080022bf .word 0x080022bf 80021d8: 080022bf .word 0x080022bf 80021dc: 080022bf .word 0x080022bf 80021e0: 080022bf .word 0x080022bf 80021e4: 080022bf .word 0x080022bf 80021e8: 080022bf .word 0x080022bf 80021ec: 080022bf .word 0x080022bf 80021f0: 080022bf .word 0x080022bf 80021f4: 080022bf .word 0x080022bf 80021f8: 080022bf .word 0x080022bf 80021fc: 080022bf .word 0x080022bf 8002200: 080022bf .word 0x080022bf 8002204: 080022bf .word 0x080022bf 8002208: 080022bf .word 0x080022bf 800220c: 080022bf .word 0x080022bf 8002210: 0800228b .word 0x0800228b case 0x00: rtTLC = 100; 8002214: 4b37 ldr r3, [pc, #220] @ (80022f4 ) 8002216: 2264 movs r2, #100 @ 0x64 8002218: 701a strb r2, [r3, #0] stPulsanti &= (!(M1FW | M1BW | M3FW | M3BW | M4FW | M4BW)); 800221a: 4b33 ldr r3, [pc, #204] @ (80022e8 ) 800221c: 2200 movs r2, #0 800221e: 801a strh r2, [r3, #0] break; 8002220: e06b b.n 80022fa case 0x08: //tlc1 if (rtTLC == 0) 8002222: 4b34 ldr r3, [pc, #208] @ (80022f4 ) 8002224: 781b ldrb r3, [r3, #0] 8002226: b2db uxtb r3, r3 8002228: 2b00 cmp r3, #0 800222a: d14f bne.n 80022cc stPulsanti |= M1FW; 800222c: 4b2e ldr r3, [pc, #184] @ (80022e8 ) 800222e: 881b ldrh r3, [r3, #0] 8002230: f043 0310 orr.w r3, r3, #16 8002234: b29a uxth r2, r3 8002236: 4b2c ldr r3, [pc, #176] @ (80022e8 ) 8002238: 801a strh r2, [r3, #0] break; 800223a: e047 b.n 80022cc case 0x10: //tlc2 if (rtTLC == 0) 800223c: 4b2d ldr r3, [pc, #180] @ (80022f4 ) 800223e: 781b ldrb r3, [r3, #0] 8002240: b2db uxtb r3, r3 8002242: 2b00 cmp r3, #0 8002244: d144 bne.n 80022d0 stPulsanti |= M1BW; 8002246: 4b28 ldr r3, [pc, #160] @ (80022e8 ) 8002248: 881b ldrh r3, [r3, #0] 800224a: f043 0320 orr.w r3, r3, #32 800224e: b29a uxth r2, r3 8002250: 4b25 ldr r3, [pc, #148] @ (80022e8 ) 8002252: 801a strh r2, [r3, #0] break; 8002254: e03c b.n 80022d0 case 0x20: //tlc3 if (rtTLC == 0) 8002256: 4b27 ldr r3, [pc, #156] @ (80022f4 ) 8002258: 781b ldrb r3, [r3, #0] 800225a: b2db uxtb r3, r3 800225c: 2b00 cmp r3, #0 800225e: d139 bne.n 80022d4 stPulsanti |= M3FW; 8002260: 4b21 ldr r3, [pc, #132] @ (80022e8 ) 8002262: 881b ldrh r3, [r3, #0] 8002264: f443 7380 orr.w r3, r3, #256 @ 0x100 8002268: b29a uxth r2, r3 800226a: 4b1f ldr r3, [pc, #124] @ (80022e8 ) 800226c: 801a strh r2, [r3, #0] break; 800226e: e031 b.n 80022d4 case 0x04: //tlc4 if (rtTLC == 0) 8002270: 4b20 ldr r3, [pc, #128] @ (80022f4 ) 8002272: 781b ldrb r3, [r3, #0] 8002274: b2db uxtb r3, r3 8002276: 2b00 cmp r3, #0 8002278: d12e bne.n 80022d8 stPulsanti |= M3BW; 800227a: 4b1b ldr r3, [pc, #108] @ (80022e8 ) 800227c: 881b ldrh r3, [r3, #0] 800227e: f443 7300 orr.w r3, r3, #512 @ 0x200 8002282: b29a uxth r2, r3 8002284: 4b18 ldr r3, [pc, #96] @ (80022e8 ) 8002286: 801a strh r2, [r3, #0] break; 8002288: e026 b.n 80022d8 case 0x30: //tlc5 if (rtTLC == 0) 800228a: 4b1a ldr r3, [pc, #104] @ (80022f4 ) 800228c: 781b ldrb r3, [r3, #0] 800228e: b2db uxtb r3, r3 8002290: 2b00 cmp r3, #0 8002292: d123 bne.n 80022dc stPulsanti |= M4FW; 8002294: 4b14 ldr r3, [pc, #80] @ (80022e8 ) 8002296: 881b ldrh r3, [r3, #0] 8002298: f443 6380 orr.w r3, r3, #1024 @ 0x400 800229c: b29a uxth r2, r3 800229e: 4b12 ldr r3, [pc, #72] @ (80022e8 ) 80022a0: 801a strh r2, [r3, #0] break; 80022a2: e01b b.n 80022dc case 0x0c: //tlc6 if (rtTLC == 0) 80022a4: 4b13 ldr r3, [pc, #76] @ (80022f4 ) 80022a6: 781b ldrb r3, [r3, #0] 80022a8: b2db uxtb r3, r3 80022aa: 2b00 cmp r3, #0 80022ac: d124 bne.n 80022f8 stPulsanti |= M4BW; 80022ae: 4b0e ldr r3, [pc, #56] @ (80022e8 ) 80022b0: 881b ldrh r3, [r3, #0] 80022b2: f443 6300 orr.w r3, r3, #2048 @ 0x800 80022b6: b29a uxth r2, r3 80022b8: 4b0b ldr r3, [pc, #44] @ (80022e8 ) 80022ba: 801a strh r2, [r3, #0] break; 80022bc: e01c b.n 80022f8 default: rtTLC = 100; 80022be: 4b0d ldr r3, [pc, #52] @ (80022f4 ) 80022c0: 2264 movs r2, #100 @ 0x64 80022c2: 701a strb r2, [r3, #0] stPulsanti &= (!(M1FW | M1BW | M3FW | M3BW | M4FW | M4BW)); 80022c4: 4b08 ldr r3, [pc, #32] @ (80022e8 ) 80022c6: 2200 movs r2, #0 80022c8: 801a strh r2, [r3, #0] break; 80022ca: e016 b.n 80022fa break; 80022cc: bf00 nop 80022ce: e014 b.n 80022fa break; 80022d0: bf00 nop 80022d2: e012 b.n 80022fa break; 80022d4: bf00 nop 80022d6: e010 b.n 80022fa break; 80022d8: bf00 nop 80022da: e00e b.n 80022fa break; 80022dc: bf00 nop 80022de: e00c b.n 80022fa 80022e0: 200003f0 .word 0x200003f0 80022e4: 20000004 .word 0x20000004 80022e8: 20000454 .word 0x20000454 80022ec: 40011000 .word 0x40011000 80022f0: 20000005 .word 0x20000005 80022f4: 20000006 .word 0x20000006 break; 80022f8: bf00 nop } } } 80022fa: bf00 nop 80022fc: bd80 pop {r7, pc} 80022fe: bf00 nop 08002300 : void manageCiclo(void) { 8002300: b580 push {r7, lr} 8002302: b084 sub sp, #16 8002304: af02 add r7, sp, #8 motMov_st m1, m2, m3, m4; switch (stCiclo) { 8002306: 4b9d ldr r3, [pc, #628] @ (800257c ) 8002308: 781b ldrb r3, [r3, #0] 800230a: 2b19 cmp r3, #25 800230c: f200 8694 bhi.w 8003038 8002310: a201 add r2, pc, #4 @ (adr r2, 8002318 ) 8002312: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002316: bf00 nop 8002318: 08002381 .word 0x08002381 800231c: 08002453 .word 0x08002453 8002320: 0800249d .word 0x0800249d 8002324: 080024e7 .word 0x080024e7 8002328: 08002531 .word 0x08002531 800232c: 080025b9 .word 0x080025b9 8002330: 08002603 .word 0x08002603 8002334: 0800264d .word 0x0800264d 8002338: 08002697 .word 0x08002697 800233c: 080026e1 .word 0x080026e1 8002340: 0800272b .word 0x0800272b 8002344: 08002775 .word 0x08002775 8002348: 080027bf .word 0x080027bf 800234c: 0800282d .word 0x0800282d 8002350: 08002875 .word 0x08002875 8002354: 080028bd .word 0x080028bd 8002358: 08002905 .word 0x08002905 800235c: 0800294d .word 0x0800294d 8002360: 080029b5 .word 0x080029b5 8002364: 08002a45 .word 0x08002a45 8002368: 08002ae1 .word 0x08002ae1 800236c: 08002efb .word 0x08002efb 8002370: 08002b4b .word 0x08002b4b 8002374: 08002e0b .word 0x08002e0b 8002378: 08002e9b .word 0x08002e9b 800237c: 08002f63 .word 0x08002f63 case omchiuso: stPulsanti &= (~P1RELEASED); 8002380: 4b7f ldr r3, [pc, #508] @ (8002580 ) 8002382: 881b ldrh r3, [r3, #0] 8002384: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8002388: b29a uxth r2, r3 800238a: 4b7d ldr r3, [pc, #500] @ (8002580 ) 800238c: 801a strh r2, [r3, #0] if (stPulsanti & P1START) { 800238e: 4b7c ldr r3, [pc, #496] @ (8002580 ) 8002390: 881b ldrh r3, [r3, #0] 8002392: f003 0301 and.w r3, r3, #1 8002396: 2b00 cmp r3, #0 8002398: d014 beq.n 80023c4 stBuz = bzwarning; 800239a: 4b7a ldr r3, [pc, #488] @ (8002584 ) 800239c: 2202 movs r2, #2 800239e: 701a strb r2, [r3, #0] rtCiclo = 0; 80023a0: 4b79 ldr r3, [pc, #484] @ (8002588 ) 80023a2: 2200 movs r2, #0 80023a4: 801a strh r2, [r3, #0] stCiclo = omapertura0; 80023a6: 4b75 ldr r3, [pc, #468] @ (800257c ) 80023a8: 2212 movs r2, #18 80023aa: 701a strb r2, [r3, #0] fchiuso = false; 80023ac: 4b77 ldr r3, [pc, #476] @ (800258c ) 80023ae: 2200 movs r2, #0 80023b0: 701a strb r2, [r3, #0] (void) m1ap(); 80023b2: f001 f9df bl 8003774 (void) m2ap(); 80023b6: f001 faaf bl 8003918 (void) m3ap(); 80023ba: f001 fb7f bl 8003abc (void) m4ap(); 80023be: f001 fc51 bl 8003c64 80023c2: e00b b.n 80023dc } else if (stPulsanti & P1STOP) { 80023c4: 4b6e ldr r3, [pc, #440] @ (8002580 ) 80023c6: 881b ldrh r3, [r3, #0] 80023c8: f003 0302 and.w r3, r3, #2 80023cc: 2b00 cmp r3, #0 80023ce: d005 beq.n 80023dc fchiuso = false; 80023d0: 4b6e ldr r3, [pc, #440] @ (800258c ) 80023d2: 2200 movs r2, #0 80023d4: 701a strb r2, [r3, #0] stCiclo = omstopapertura; 80023d6: 4b69 ldr r3, [pc, #420] @ (800257c ) 80023d8: 2213 movs r2, #19 80023da: 701a strb r2, [r3, #0] } #ifdef ANEMCH fchiuso = false; 80023dc: 4b6b ldr r3, [pc, #428] @ (800258c ) 80023de: 2200 movs r2, #0 80023e0: 701a strb r2, [r3, #0] #endif if ((ch8 > thanem) && (fchiuso == false)) { 80023e2: 4b6b ldr r3, [pc, #428] @ (8002590 ) 80023e4: 881a ldrh r2, [r3, #0] 80023e6: 4b6b ldr r3, [pc, #428] @ (8002594 ) 80023e8: 881b ldrh r3, [r3, #0] 80023ea: 429a cmp r2, r3 80023ec: d923 bls.n 8002436 80023ee: 4b67 ldr r3, [pc, #412] @ (800258c ) 80023f0: 781b ldrb r3, [r3, #0] 80023f2: f083 0301 eor.w r3, r3, #1 80023f6: b2db uxtb r3, r3 80023f8: 2b00 cmp r3, #0 80023fa: d01c beq.n 8002436 HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); 80023fc: 2201 movs r2, #1 80023fe: f44f 4100 mov.w r1, #32768 @ 0x8000 8002402: 4865 ldr r0, [pc, #404] @ (8002598 ) 8002404: f004 f963 bl 80066ce if (rtAnem == 0) { 8002408: 4b64 ldr r3, [pc, #400] @ (800259c ) 800240a: 881b ldrh r3, [r3, #0] 800240c: b29b uxth r3, r3 800240e: 2b00 cmp r3, #0 8002410: d11d bne.n 800244e rtCiclo=0; 8002412: 4b5d ldr r3, [pc, #372] @ (8002588 ) 8002414: 2200 movs r2, #0 8002416: 801a strh r2, [r3, #0] stBuz = bzmoving; 8002418: 4b5a ldr r3, [pc, #360] @ (8002584 ) 800241a: 2201 movs r2, #1 800241c: 701a strb r2, [r3, #0] stCiclo = omemergenza1; 800241e: 4b57 ldr r3, [pc, #348] @ (800257c ) 8002420: 2218 movs r2, #24 8002422: 701a strb r2, [r3, #0] (void) m1ch(); 8002424: f001 fcf2 bl 8003e0c (void) m2ch(); 8002428: f001 fdc2 bl 8003fb0 (void) m3ch(); 800242c: f001 fe92 bl 8004154 (void) m4ch(); 8002430: f001 ff64 bl 80042fc if (rtAnem == 0) { 8002434: e00b b.n 800244e } } else{ HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); 8002436: 2200 movs r2, #0 8002438: f44f 4100 mov.w r1, #32768 @ 0x8000 800243c: 4856 ldr r0, [pc, #344] @ (8002598 ) 800243e: f004 f946 bl 80066ce rtAnem = tanem; 8002442: 4b57 ldr r3, [pc, #348] @ (80025a0 ) 8002444: 881a ldrh r2, [r3, #0] 8002446: 4b55 ldr r3, [pc, #340] @ (800259c ) 8002448: 801a strh r2, [r3, #0] } break; 800244a: f000 bdf5 b.w 8003038 800244e: f000 bdf3 b.w 8003038 case omM1fw1: (void) ramp(M1, FW, mrampstart[M1 - 1], m1pwmMan, trampman, RAMPRUN); 8002452: 4b54 ldr r3, [pc, #336] @ (80025a4 ) 8002454: 881b ldrh r3, [r3, #0] 8002456: b2da uxtb r2, r3 8002458: 4b53 ldr r3, [pc, #332] @ (80025a8 ) 800245a: 881b ldrh r3, [r3, #0] 800245c: b2d9 uxtb r1, r3 800245e: 4b53 ldr r3, [pc, #332] @ (80025ac ) 8002460: 881b ldrh r3, [r3, #0] 8002462: b2db uxtb r3, r3 8002464: 200a movs r0, #10 8002466: 9001 str r0, [sp, #4] 8002468: 9300 str r3, [sp, #0] 800246a: 460b mov r3, r1 800246c: 2100 movs r1, #0 800246e: 2001 movs r0, #1 8002470: f002 fb7e bl 8004b70 if (rtCiclo >= m1TimeoutMan) 8002474: 4b44 ldr r3, [pc, #272] @ (8002588 ) 8002476: 881b ldrh r3, [r3, #0] 8002478: b29a uxth r2, r3 800247a: 4b4d ldr r3, [pc, #308] @ (80025b0 ) 800247c: 881b ldrh r3, [r3, #0] 800247e: 429a cmp r2, r3 8002480: d302 bcc.n 8002488 stCiclo = omStopMan; 8002482: 4b3e ldr r3, [pc, #248] @ (800257c ) 8002484: 2211 movs r2, #17 8002486: 701a strb r2, [r3, #0] if (pulsanti == 0) 8002488: 4b4a ldr r3, [pc, #296] @ (80025b4 ) 800248a: 781b ldrb r3, [r3, #0] 800248c: 2b00 cmp r3, #0 800248e: f040 85a2 bne.w 8002fd6 stCiclo = omM1fw2; 8002492: 4b3a ldr r3, [pc, #232] @ (800257c ) 8002494: 2202 movs r2, #2 8002496: 701a strb r2, [r3, #0] break; 8002498: f000 bd9d b.w 8002fd6 case omM1fw2: (void) ramp(M1, FW, mrampstart[M1 - 1], m1pwmMan, trampman, RAMPRUN); 800249c: 4b41 ldr r3, [pc, #260] @ (80025a4 ) 800249e: 881b ldrh r3, [r3, #0] 80024a0: b2da uxtb r2, r3 80024a2: 4b41 ldr r3, [pc, #260] @ (80025a8 ) 80024a4: 881b ldrh r3, [r3, #0] 80024a6: b2d9 uxtb r1, r3 80024a8: 4b40 ldr r3, [pc, #256] @ (80025ac ) 80024aa: 881b ldrh r3, [r3, #0] 80024ac: b2db uxtb r3, r3 80024ae: 200a movs r0, #10 80024b0: 9001 str r0, [sp, #4] 80024b2: 9300 str r3, [sp, #0] 80024b4: 460b mov r3, r1 80024b6: 2100 movs r1, #0 80024b8: 2001 movs r0, #1 80024ba: f002 fb59 bl 8004b70 if (rtCiclo >= m1TimeoutMan) 80024be: 4b32 ldr r3, [pc, #200] @ (8002588 ) 80024c0: 881b ldrh r3, [r3, #0] 80024c2: b29a uxth r2, r3 80024c4: 4b3a ldr r3, [pc, #232] @ (80025b0 ) 80024c6: 881b ldrh r3, [r3, #0] 80024c8: 429a cmp r2, r3 80024ca: d302 bcc.n 80024d2 stCiclo = omStopMan; 80024cc: 4b2b ldr r3, [pc, #172] @ (800257c ) 80024ce: 2211 movs r2, #17 80024d0: 701a strb r2, [r3, #0] if (pulsanti) 80024d2: 4b38 ldr r3, [pc, #224] @ (80025b4 ) 80024d4: 781b ldrb r3, [r3, #0] 80024d6: 2b00 cmp r3, #0 80024d8: f000 857f beq.w 8002fda stCiclo = omStopMan; 80024dc: 4b27 ldr r3, [pc, #156] @ (800257c ) 80024de: 2211 movs r2, #17 80024e0: 701a strb r2, [r3, #0] break; 80024e2: f000 bd7a b.w 8002fda case omM1bw1: (void) ramp(M1, BW, mrampstart[M1 - 1], m1pwmMan, trampman, RAMPRUN); 80024e6: 4b2f ldr r3, [pc, #188] @ (80025a4 ) 80024e8: 881b ldrh r3, [r3, #0] 80024ea: b2da uxtb r2, r3 80024ec: 4b2e ldr r3, [pc, #184] @ (80025a8 ) 80024ee: 881b ldrh r3, [r3, #0] 80024f0: b2d9 uxtb r1, r3 80024f2: 4b2e ldr r3, [pc, #184] @ (80025ac ) 80024f4: 881b ldrh r3, [r3, #0] 80024f6: b2db uxtb r3, r3 80024f8: 200a movs r0, #10 80024fa: 9001 str r0, [sp, #4] 80024fc: 9300 str r3, [sp, #0] 80024fe: 460b mov r3, r1 8002500: 2101 movs r1, #1 8002502: 2001 movs r0, #1 8002504: f002 fb34 bl 8004b70 if (rtCiclo >= m1TimeoutMan) 8002508: 4b1f ldr r3, [pc, #124] @ (8002588 ) 800250a: 881b ldrh r3, [r3, #0] 800250c: b29a uxth r2, r3 800250e: 4b28 ldr r3, [pc, #160] @ (80025b0 ) 8002510: 881b ldrh r3, [r3, #0] 8002512: 429a cmp r2, r3 8002514: d302 bcc.n 800251c stCiclo = omStopMan; 8002516: 4b19 ldr r3, [pc, #100] @ (800257c ) 8002518: 2211 movs r2, #17 800251a: 701a strb r2, [r3, #0] if (pulsanti == 0) 800251c: 4b25 ldr r3, [pc, #148] @ (80025b4 ) 800251e: 781b ldrb r3, [r3, #0] 8002520: 2b00 cmp r3, #0 8002522: f040 855c bne.w 8002fde stCiclo = omM1bw2; 8002526: 4b15 ldr r3, [pc, #84] @ (800257c ) 8002528: 2204 movs r2, #4 800252a: 701a strb r2, [r3, #0] break; 800252c: f000 bd57 b.w 8002fde case omM1bw2: (void) ramp(M1, BW, mrampstart[M1 - 1], m1pwmMan, trampman, RAMPRUN); 8002530: 4b1c ldr r3, [pc, #112] @ (80025a4 ) 8002532: 881b ldrh r3, [r3, #0] 8002534: b2da uxtb r2, r3 8002536: 4b1c ldr r3, [pc, #112] @ (80025a8 ) 8002538: 881b ldrh r3, [r3, #0] 800253a: b2d9 uxtb r1, r3 800253c: 4b1b ldr r3, [pc, #108] @ (80025ac ) 800253e: 881b ldrh r3, [r3, #0] 8002540: b2db uxtb r3, r3 8002542: 200a movs r0, #10 8002544: 9001 str r0, [sp, #4] 8002546: 9300 str r3, [sp, #0] 8002548: 460b mov r3, r1 800254a: 2101 movs r1, #1 800254c: 2001 movs r0, #1 800254e: f002 fb0f bl 8004b70 if (rtCiclo >= m1TimeoutMan) 8002552: 4b0d ldr r3, [pc, #52] @ (8002588 ) 8002554: 881b ldrh r3, [r3, #0] 8002556: b29a uxth r2, r3 8002558: 4b15 ldr r3, [pc, #84] @ (80025b0 ) 800255a: 881b ldrh r3, [r3, #0] 800255c: 429a cmp r2, r3 800255e: d302 bcc.n 8002566 stCiclo = omStopMan; 8002560: 4b06 ldr r3, [pc, #24] @ (800257c ) 8002562: 2211 movs r2, #17 8002564: 701a strb r2, [r3, #0] if (pulsanti) 8002566: 4b13 ldr r3, [pc, #76] @ (80025b4 ) 8002568: 781b ldrb r3, [r3, #0] 800256a: 2b00 cmp r3, #0 800256c: f000 8539 beq.w 8002fe2 stCiclo = omStopMan; 8002570: 4b02 ldr r3, [pc, #8] @ (800257c ) 8002572: 2211 movs r2, #17 8002574: 701a strb r2, [r3, #0] break; 8002576: f000 bd34 b.w 8002fe2 800257a: bf00 nop 800257c: 20000456 .word 0x20000456 8002580: 20000454 .word 0x20000454 8002584: 20000457 .word 0x20000457 8002588: 200003fc .word 0x200003fc 800258c: 20000459 .word 0x20000459 8002590: 20000232 .word 0x20000232 8002594: 2000041c .word 0x2000041c 8002598: 40010800 .word 0x40010800 800259c: 200003fe .word 0x200003fe 80025a0: 2000041a .word 0x2000041a 80025a4: 2000044c .word 0x2000044c 80025a8: 20000420 .word 0x20000420 80025ac: 2000041e .word 0x2000041e 80025b0: 20000410 .word 0x20000410 80025b4: 200003f0 .word 0x200003f0 case omM2fw1: (void) ramp(M2, FW, mrampstart[M2 - 1], m2pwmMan, trampman, RAMPRUN); 80025b8: 4b93 ldr r3, [pc, #588] @ (8002808 ) 80025ba: 885b ldrh r3, [r3, #2] 80025bc: b2da uxtb r2, r3 80025be: 4b93 ldr r3, [pc, #588] @ (800280c ) 80025c0: 881b ldrh r3, [r3, #0] 80025c2: b2d9 uxtb r1, r3 80025c4: 4b92 ldr r3, [pc, #584] @ (8002810 ) 80025c6: 881b ldrh r3, [r3, #0] 80025c8: b2db uxtb r3, r3 80025ca: 200a movs r0, #10 80025cc: 9001 str r0, [sp, #4] 80025ce: 9300 str r3, [sp, #0] 80025d0: 460b mov r3, r1 80025d2: 2100 movs r1, #0 80025d4: 2002 movs r0, #2 80025d6: f002 facb bl 8004b70 if (rtCiclo >= m2TimeoutMan) 80025da: 4b8e ldr r3, [pc, #568] @ (8002814 ) 80025dc: 881b ldrh r3, [r3, #0] 80025de: b29a uxth r2, r3 80025e0: 4b8d ldr r3, [pc, #564] @ (8002818 ) 80025e2: 881b ldrh r3, [r3, #0] 80025e4: 429a cmp r2, r3 80025e6: d302 bcc.n 80025ee stCiclo = omStopMan; 80025e8: 4b8c ldr r3, [pc, #560] @ (800281c ) 80025ea: 2211 movs r2, #17 80025ec: 701a strb r2, [r3, #0] if (pulsanti == 0) 80025ee: 4b8c ldr r3, [pc, #560] @ (8002820 ) 80025f0: 781b ldrb r3, [r3, #0] 80025f2: 2b00 cmp r3, #0 80025f4: f040 84f7 bne.w 8002fe6 stCiclo = omM2fw2; 80025f8: 4b88 ldr r3, [pc, #544] @ (800281c ) 80025fa: 2206 movs r2, #6 80025fc: 701a strb r2, [r3, #0] break; 80025fe: f000 bcf2 b.w 8002fe6 case omM2fw2: (void) ramp(M2, FW, mrampstart[M2 - 1], m2pwmMan, trampman, RAMPRUN); 8002602: 4b81 ldr r3, [pc, #516] @ (8002808 ) 8002604: 885b ldrh r3, [r3, #2] 8002606: b2da uxtb r2, r3 8002608: 4b80 ldr r3, [pc, #512] @ (800280c ) 800260a: 881b ldrh r3, [r3, #0] 800260c: b2d9 uxtb r1, r3 800260e: 4b80 ldr r3, [pc, #512] @ (8002810 ) 8002610: 881b ldrh r3, [r3, #0] 8002612: b2db uxtb r3, r3 8002614: 200a movs r0, #10 8002616: 9001 str r0, [sp, #4] 8002618: 9300 str r3, [sp, #0] 800261a: 460b mov r3, r1 800261c: 2100 movs r1, #0 800261e: 2002 movs r0, #2 8002620: f002 faa6 bl 8004b70 if (rtCiclo >= m2TimeoutMan) 8002624: 4b7b ldr r3, [pc, #492] @ (8002814 ) 8002626: 881b ldrh r3, [r3, #0] 8002628: b29a uxth r2, r3 800262a: 4b7b ldr r3, [pc, #492] @ (8002818 ) 800262c: 881b ldrh r3, [r3, #0] 800262e: 429a cmp r2, r3 8002630: d302 bcc.n 8002638 stCiclo = omStopMan; 8002632: 4b7a ldr r3, [pc, #488] @ (800281c ) 8002634: 2211 movs r2, #17 8002636: 701a strb r2, [r3, #0] if (pulsanti) 8002638: 4b79 ldr r3, [pc, #484] @ (8002820 ) 800263a: 781b ldrb r3, [r3, #0] 800263c: 2b00 cmp r3, #0 800263e: f000 84d4 beq.w 8002fea stCiclo = omStopMan; 8002642: 4b76 ldr r3, [pc, #472] @ (800281c ) 8002644: 2211 movs r2, #17 8002646: 701a strb r2, [r3, #0] break; 8002648: f000 bccf b.w 8002fea case omM2bw1: (void) ramp(M2, BW, mrampstart[M2 - 1], m2pwmMan, trampman, RAMPRUN); 800264c: 4b6e ldr r3, [pc, #440] @ (8002808 ) 800264e: 885b ldrh r3, [r3, #2] 8002650: b2da uxtb r2, r3 8002652: 4b6e ldr r3, [pc, #440] @ (800280c ) 8002654: 881b ldrh r3, [r3, #0] 8002656: b2d9 uxtb r1, r3 8002658: 4b6d ldr r3, [pc, #436] @ (8002810 ) 800265a: 881b ldrh r3, [r3, #0] 800265c: b2db uxtb r3, r3 800265e: 200a movs r0, #10 8002660: 9001 str r0, [sp, #4] 8002662: 9300 str r3, [sp, #0] 8002664: 460b mov r3, r1 8002666: 2101 movs r1, #1 8002668: 2002 movs r0, #2 800266a: f002 fa81 bl 8004b70 if (rtCiclo >= m2TimeoutMan) 800266e: 4b69 ldr r3, [pc, #420] @ (8002814 ) 8002670: 881b ldrh r3, [r3, #0] 8002672: b29a uxth r2, r3 8002674: 4b68 ldr r3, [pc, #416] @ (8002818 ) 8002676: 881b ldrh r3, [r3, #0] 8002678: 429a cmp r2, r3 800267a: d302 bcc.n 8002682 stCiclo = omStopMan; 800267c: 4b67 ldr r3, [pc, #412] @ (800281c ) 800267e: 2211 movs r2, #17 8002680: 701a strb r2, [r3, #0] if (pulsanti == 0) 8002682: 4b67 ldr r3, [pc, #412] @ (8002820 ) 8002684: 781b ldrb r3, [r3, #0] 8002686: 2b00 cmp r3, #0 8002688: f040 84b1 bne.w 8002fee stCiclo = omM2bw2; 800268c: 4b63 ldr r3, [pc, #396] @ (800281c ) 800268e: 2208 movs r2, #8 8002690: 701a strb r2, [r3, #0] break; 8002692: f000 bcac b.w 8002fee case omM2bw2: (void) ramp(M2, BW, mrampstart[M2 - 1], m2pwmMan, trampman, RAMPRUN); 8002696: 4b5c ldr r3, [pc, #368] @ (8002808 ) 8002698: 885b ldrh r3, [r3, #2] 800269a: b2da uxtb r2, r3 800269c: 4b5b ldr r3, [pc, #364] @ (800280c ) 800269e: 881b ldrh r3, [r3, #0] 80026a0: b2d9 uxtb r1, r3 80026a2: 4b5b ldr r3, [pc, #364] @ (8002810 ) 80026a4: 881b ldrh r3, [r3, #0] 80026a6: b2db uxtb r3, r3 80026a8: 200a movs r0, #10 80026aa: 9001 str r0, [sp, #4] 80026ac: 9300 str r3, [sp, #0] 80026ae: 460b mov r3, r1 80026b0: 2101 movs r1, #1 80026b2: 2002 movs r0, #2 80026b4: f002 fa5c bl 8004b70 if (rtCiclo >= m2TimeoutMan) 80026b8: 4b56 ldr r3, [pc, #344] @ (8002814 ) 80026ba: 881b ldrh r3, [r3, #0] 80026bc: b29a uxth r2, r3 80026be: 4b56 ldr r3, [pc, #344] @ (8002818 ) 80026c0: 881b ldrh r3, [r3, #0] 80026c2: 429a cmp r2, r3 80026c4: d302 bcc.n 80026cc stCiclo = omStopMan; 80026c6: 4b55 ldr r3, [pc, #340] @ (800281c ) 80026c8: 2211 movs r2, #17 80026ca: 701a strb r2, [r3, #0] if (pulsanti) 80026cc: 4b54 ldr r3, [pc, #336] @ (8002820 ) 80026ce: 781b ldrb r3, [r3, #0] 80026d0: 2b00 cmp r3, #0 80026d2: f000 848e beq.w 8002ff2 stCiclo = omStopMan; 80026d6: 4b51 ldr r3, [pc, #324] @ (800281c ) 80026d8: 2211 movs r2, #17 80026da: 701a strb r2, [r3, #0] break; 80026dc: f000 bc89 b.w 8002ff2 case omM3fw1: (void) ramp(M3, FW, mrampstart[M3 - 1], m3pwmMan, trampman, RAMPRUN); 80026e0: 4b49 ldr r3, [pc, #292] @ (8002808 ) 80026e2: 889b ldrh r3, [r3, #4] 80026e4: b2da uxtb r2, r3 80026e6: 4b4f ldr r3, [pc, #316] @ (8002824 ) 80026e8: 881b ldrh r3, [r3, #0] 80026ea: b2d9 uxtb r1, r3 80026ec: 4b48 ldr r3, [pc, #288] @ (8002810 ) 80026ee: 881b ldrh r3, [r3, #0] 80026f0: b2db uxtb r3, r3 80026f2: 200a movs r0, #10 80026f4: 9001 str r0, [sp, #4] 80026f6: 9300 str r3, [sp, #0] 80026f8: 460b mov r3, r1 80026fa: 2100 movs r1, #0 80026fc: 2003 movs r0, #3 80026fe: f002 fa37 bl 8004b70 if (rtCiclo >= m3TimeoutMan) 8002702: 4b44 ldr r3, [pc, #272] @ (8002814 ) 8002704: 881b ldrh r3, [r3, #0] 8002706: b29a uxth r2, r3 8002708: 4b47 ldr r3, [pc, #284] @ (8002828 ) 800270a: 881b ldrh r3, [r3, #0] 800270c: 429a cmp r2, r3 800270e: d302 bcc.n 8002716 stCiclo = omStopMan; 8002710: 4b42 ldr r3, [pc, #264] @ (800281c ) 8002712: 2211 movs r2, #17 8002714: 701a strb r2, [r3, #0] if (pulsanti == 0) 8002716: 4b42 ldr r3, [pc, #264] @ (8002820 ) 8002718: 781b ldrb r3, [r3, #0] 800271a: 2b00 cmp r3, #0 800271c: f040 846b bne.w 8002ff6 stCiclo = omM3fw2; 8002720: 4b3e ldr r3, [pc, #248] @ (800281c ) 8002722: 220a movs r2, #10 8002724: 701a strb r2, [r3, #0] break; 8002726: f000 bc66 b.w 8002ff6 case omM3fw2: (void) ramp(M3, FW, mrampstart[M3 - 1], m3pwmMan, trampman, RAMPRUN); 800272a: 4b37 ldr r3, [pc, #220] @ (8002808 ) 800272c: 889b ldrh r3, [r3, #4] 800272e: b2da uxtb r2, r3 8002730: 4b3c ldr r3, [pc, #240] @ (8002824 ) 8002732: 881b ldrh r3, [r3, #0] 8002734: b2d9 uxtb r1, r3 8002736: 4b36 ldr r3, [pc, #216] @ (8002810 ) 8002738: 881b ldrh r3, [r3, #0] 800273a: b2db uxtb r3, r3 800273c: 200a movs r0, #10 800273e: 9001 str r0, [sp, #4] 8002740: 9300 str r3, [sp, #0] 8002742: 460b mov r3, r1 8002744: 2100 movs r1, #0 8002746: 2003 movs r0, #3 8002748: f002 fa12 bl 8004b70 if (rtCiclo >= m3TimeoutMan) 800274c: 4b31 ldr r3, [pc, #196] @ (8002814 ) 800274e: 881b ldrh r3, [r3, #0] 8002750: b29a uxth r2, r3 8002752: 4b35 ldr r3, [pc, #212] @ (8002828 ) 8002754: 881b ldrh r3, [r3, #0] 8002756: 429a cmp r2, r3 8002758: d302 bcc.n 8002760 stCiclo = omStopMan; 800275a: 4b30 ldr r3, [pc, #192] @ (800281c ) 800275c: 2211 movs r2, #17 800275e: 701a strb r2, [r3, #0] if (pulsanti) 8002760: 4b2f ldr r3, [pc, #188] @ (8002820 ) 8002762: 781b ldrb r3, [r3, #0] 8002764: 2b00 cmp r3, #0 8002766: f000 8448 beq.w 8002ffa stCiclo = omStopMan; 800276a: 4b2c ldr r3, [pc, #176] @ (800281c ) 800276c: 2211 movs r2, #17 800276e: 701a strb r2, [r3, #0] break; 8002770: f000 bc43 b.w 8002ffa case omM3bw1: (void) ramp(M3, BW, mrampstart[M3 - 1], m3pwmMan, trampman, RAMPRUN); 8002774: 4b24 ldr r3, [pc, #144] @ (8002808 ) 8002776: 889b ldrh r3, [r3, #4] 8002778: b2da uxtb r2, r3 800277a: 4b2a ldr r3, [pc, #168] @ (8002824 ) 800277c: 881b ldrh r3, [r3, #0] 800277e: b2d9 uxtb r1, r3 8002780: 4b23 ldr r3, [pc, #140] @ (8002810 ) 8002782: 881b ldrh r3, [r3, #0] 8002784: b2db uxtb r3, r3 8002786: 200a movs r0, #10 8002788: 9001 str r0, [sp, #4] 800278a: 9300 str r3, [sp, #0] 800278c: 460b mov r3, r1 800278e: 2101 movs r1, #1 8002790: 2003 movs r0, #3 8002792: f002 f9ed bl 8004b70 if (rtCiclo >= m3TimeoutMan) 8002796: 4b1f ldr r3, [pc, #124] @ (8002814 ) 8002798: 881b ldrh r3, [r3, #0] 800279a: b29a uxth r2, r3 800279c: 4b22 ldr r3, [pc, #136] @ (8002828 ) 800279e: 881b ldrh r3, [r3, #0] 80027a0: 429a cmp r2, r3 80027a2: d302 bcc.n 80027aa stCiclo = omStopMan; 80027a4: 4b1d ldr r3, [pc, #116] @ (800281c ) 80027a6: 2211 movs r2, #17 80027a8: 701a strb r2, [r3, #0] if (pulsanti == 0) 80027aa: 4b1d ldr r3, [pc, #116] @ (8002820 ) 80027ac: 781b ldrb r3, [r3, #0] 80027ae: 2b00 cmp r3, #0 80027b0: f040 8425 bne.w 8002ffe stCiclo = omM3bw2; 80027b4: 4b19 ldr r3, [pc, #100] @ (800281c ) 80027b6: 220c movs r2, #12 80027b8: 701a strb r2, [r3, #0] break; 80027ba: f000 bc20 b.w 8002ffe case omM3bw2: (void) ramp(M3, BW, mrampstart[M3 - 1], m3pwmMan, trampman, RAMPRUN); 80027be: 4b12 ldr r3, [pc, #72] @ (8002808 ) 80027c0: 889b ldrh r3, [r3, #4] 80027c2: b2da uxtb r2, r3 80027c4: 4b17 ldr r3, [pc, #92] @ (8002824 ) 80027c6: 881b ldrh r3, [r3, #0] 80027c8: b2d9 uxtb r1, r3 80027ca: 4b11 ldr r3, [pc, #68] @ (8002810 ) 80027cc: 881b ldrh r3, [r3, #0] 80027ce: b2db uxtb r3, r3 80027d0: 200a movs r0, #10 80027d2: 9001 str r0, [sp, #4] 80027d4: 9300 str r3, [sp, #0] 80027d6: 460b mov r3, r1 80027d8: 2101 movs r1, #1 80027da: 2003 movs r0, #3 80027dc: f002 f9c8 bl 8004b70 if (rtCiclo >= m3TimeoutMan) 80027e0: 4b0c ldr r3, [pc, #48] @ (8002814 ) 80027e2: 881b ldrh r3, [r3, #0] 80027e4: b29a uxth r2, r3 80027e6: 4b10 ldr r3, [pc, #64] @ (8002828 ) 80027e8: 881b ldrh r3, [r3, #0] 80027ea: 429a cmp r2, r3 80027ec: d302 bcc.n 80027f4 stCiclo = omStopMan; 80027ee: 4b0b ldr r3, [pc, #44] @ (800281c ) 80027f0: 2211 movs r2, #17 80027f2: 701a strb r2, [r3, #0] if (pulsanti) 80027f4: 4b0a ldr r3, [pc, #40] @ (8002820 ) 80027f6: 781b ldrb r3, [r3, #0] 80027f8: 2b00 cmp r3, #0 80027fa: f000 8402 beq.w 8003002 stCiclo = omStopMan; 80027fe: 4b07 ldr r3, [pc, #28] @ (800281c ) 8002800: 2211 movs r2, #17 8002802: 701a strb r2, [r3, #0] break; 8002804: e3fd b.n 8003002 8002806: bf00 nop 8002808: 2000044c .word 0x2000044c 800280c: 20000422 .word 0x20000422 8002810: 2000041e .word 0x2000041e 8002814: 200003fc .word 0x200003fc 8002818: 20000412 .word 0x20000412 800281c: 20000456 .word 0x20000456 8002820: 200003f0 .word 0x200003f0 8002824: 20000424 .word 0x20000424 8002828: 20000414 .word 0x20000414 case omM4fw1: (void) ramp(M4, FW, mrampstart[M4 - 1], m4pwmMan, trampman, RAMPRUN); 800282c: 4ba3 ldr r3, [pc, #652] @ (8002abc ) 800282e: 88db ldrh r3, [r3, #6] 8002830: b2da uxtb r2, r3 8002832: 4ba3 ldr r3, [pc, #652] @ (8002ac0 ) 8002834: 881b ldrh r3, [r3, #0] 8002836: b2d9 uxtb r1, r3 8002838: 4ba2 ldr r3, [pc, #648] @ (8002ac4 ) 800283a: 881b ldrh r3, [r3, #0] 800283c: b2db uxtb r3, r3 800283e: 200a movs r0, #10 8002840: 9001 str r0, [sp, #4] 8002842: 9300 str r3, [sp, #0] 8002844: 460b mov r3, r1 8002846: 2100 movs r1, #0 8002848: 2004 movs r0, #4 800284a: f002 f991 bl 8004b70 if (rtCiclo >= m4TimeoutMan) 800284e: 4b9e ldr r3, [pc, #632] @ (8002ac8 ) 8002850: 881b ldrh r3, [r3, #0] 8002852: b29a uxth r2, r3 8002854: 4b9d ldr r3, [pc, #628] @ (8002acc ) 8002856: 881b ldrh r3, [r3, #0] 8002858: 429a cmp r2, r3 800285a: d302 bcc.n 8002862 stCiclo = omStopMan; 800285c: 4b9c ldr r3, [pc, #624] @ (8002ad0 ) 800285e: 2211 movs r2, #17 8002860: 701a strb r2, [r3, #0] if (pulsanti == 0) 8002862: 4b9c ldr r3, [pc, #624] @ (8002ad4 ) 8002864: 781b ldrb r3, [r3, #0] 8002866: 2b00 cmp r3, #0 8002868: f040 83cd bne.w 8003006 stCiclo = omM4fw2; 800286c: 4b98 ldr r3, [pc, #608] @ (8002ad0 ) 800286e: 220e movs r2, #14 8002870: 701a strb r2, [r3, #0] break; 8002872: e3c8 b.n 8003006 case omM4fw2: (void) ramp(M4, FW, mrampstart[M4 - 1], m4pwmMan, trampman, RAMPRUN); 8002874: 4b91 ldr r3, [pc, #580] @ (8002abc ) 8002876: 88db ldrh r3, [r3, #6] 8002878: b2da uxtb r2, r3 800287a: 4b91 ldr r3, [pc, #580] @ (8002ac0 ) 800287c: 881b ldrh r3, [r3, #0] 800287e: b2d9 uxtb r1, r3 8002880: 4b90 ldr r3, [pc, #576] @ (8002ac4 ) 8002882: 881b ldrh r3, [r3, #0] 8002884: b2db uxtb r3, r3 8002886: 200a movs r0, #10 8002888: 9001 str r0, [sp, #4] 800288a: 9300 str r3, [sp, #0] 800288c: 460b mov r3, r1 800288e: 2100 movs r1, #0 8002890: 2004 movs r0, #4 8002892: f002 f96d bl 8004b70 if (rtCiclo >= m4TimeoutMan) 8002896: 4b8c ldr r3, [pc, #560] @ (8002ac8 ) 8002898: 881b ldrh r3, [r3, #0] 800289a: b29a uxth r2, r3 800289c: 4b8b ldr r3, [pc, #556] @ (8002acc ) 800289e: 881b ldrh r3, [r3, #0] 80028a0: 429a cmp r2, r3 80028a2: d302 bcc.n 80028aa stCiclo = omStopMan; 80028a4: 4b8a ldr r3, [pc, #552] @ (8002ad0 ) 80028a6: 2211 movs r2, #17 80028a8: 701a strb r2, [r3, #0] if (pulsanti) 80028aa: 4b8a ldr r3, [pc, #552] @ (8002ad4 ) 80028ac: 781b ldrb r3, [r3, #0] 80028ae: 2b00 cmp r3, #0 80028b0: f000 83ab beq.w 800300a stCiclo = omStopMan; 80028b4: 4b86 ldr r3, [pc, #536] @ (8002ad0 ) 80028b6: 2211 movs r2, #17 80028b8: 701a strb r2, [r3, #0] break; 80028ba: e3a6 b.n 800300a case omM4bw1: (void) ramp(M4, BW, mrampstart[M4 - 1], m4pwmMan, trampman, RAMPRUN); 80028bc: 4b7f ldr r3, [pc, #508] @ (8002abc ) 80028be: 88db ldrh r3, [r3, #6] 80028c0: b2da uxtb r2, r3 80028c2: 4b7f ldr r3, [pc, #508] @ (8002ac0 ) 80028c4: 881b ldrh r3, [r3, #0] 80028c6: b2d9 uxtb r1, r3 80028c8: 4b7e ldr r3, [pc, #504] @ (8002ac4 ) 80028ca: 881b ldrh r3, [r3, #0] 80028cc: b2db uxtb r3, r3 80028ce: 200a movs r0, #10 80028d0: 9001 str r0, [sp, #4] 80028d2: 9300 str r3, [sp, #0] 80028d4: 460b mov r3, r1 80028d6: 2101 movs r1, #1 80028d8: 2004 movs r0, #4 80028da: f002 f949 bl 8004b70 if (rtCiclo >= m4TimeoutMan) 80028de: 4b7a ldr r3, [pc, #488] @ (8002ac8 ) 80028e0: 881b ldrh r3, [r3, #0] 80028e2: b29a uxth r2, r3 80028e4: 4b79 ldr r3, [pc, #484] @ (8002acc ) 80028e6: 881b ldrh r3, [r3, #0] 80028e8: 429a cmp r2, r3 80028ea: d302 bcc.n 80028f2 stCiclo = omStopMan; 80028ec: 4b78 ldr r3, [pc, #480] @ (8002ad0 ) 80028ee: 2211 movs r2, #17 80028f0: 701a strb r2, [r3, #0] if (pulsanti == 0) 80028f2: 4b78 ldr r3, [pc, #480] @ (8002ad4 ) 80028f4: 781b ldrb r3, [r3, #0] 80028f6: 2b00 cmp r3, #0 80028f8: f040 8389 bne.w 800300e stCiclo = omM4bw2; 80028fc: 4b74 ldr r3, [pc, #464] @ (8002ad0 ) 80028fe: 2210 movs r2, #16 8002900: 701a strb r2, [r3, #0] break; 8002902: e384 b.n 800300e case omM4bw2: (void) ramp(M4, BW, mrampstart[M4 - 1], m4pwmMan, trampman, RAMPRUN); 8002904: 4b6d ldr r3, [pc, #436] @ (8002abc ) 8002906: 88db ldrh r3, [r3, #6] 8002908: b2da uxtb r2, r3 800290a: 4b6d ldr r3, [pc, #436] @ (8002ac0 ) 800290c: 881b ldrh r3, [r3, #0] 800290e: b2d9 uxtb r1, r3 8002910: 4b6c ldr r3, [pc, #432] @ (8002ac4 ) 8002912: 881b ldrh r3, [r3, #0] 8002914: b2db uxtb r3, r3 8002916: 200a movs r0, #10 8002918: 9001 str r0, [sp, #4] 800291a: 9300 str r3, [sp, #0] 800291c: 460b mov r3, r1 800291e: 2101 movs r1, #1 8002920: 2004 movs r0, #4 8002922: f002 f925 bl 8004b70 if (rtCiclo >= m4TimeoutMan) 8002926: 4b68 ldr r3, [pc, #416] @ (8002ac8 ) 8002928: 881b ldrh r3, [r3, #0] 800292a: b29a uxth r2, r3 800292c: 4b67 ldr r3, [pc, #412] @ (8002acc ) 800292e: 881b ldrh r3, [r3, #0] 8002930: 429a cmp r2, r3 8002932: d302 bcc.n 800293a stCiclo = omStopMan; 8002934: 4b66 ldr r3, [pc, #408] @ (8002ad0 ) 8002936: 2211 movs r2, #17 8002938: 701a strb r2, [r3, #0] if (pulsanti) 800293a: 4b66 ldr r3, [pc, #408] @ (8002ad4 ) 800293c: 781b ldrb r3, [r3, #0] 800293e: 2b00 cmp r3, #0 8002940: f000 8367 beq.w 8003012 stCiclo = omStopMan; 8002944: 4b62 ldr r3, [pc, #392] @ (8002ad0 ) 8002946: 2211 movs r2, #17 8002948: 701a strb r2, [r3, #0] break; 800294a: e362 b.n 8003012 case omStopMan: SetMotPerc(M1, FW, 0); 800294c: 2200 movs r2, #0 800294e: 2100 movs r1, #0 8002950: 2001 movs r0, #1 8002952: f001 ff8d bl 8004870 SetMotPerc(M2, FW, 0); 8002956: 2200 movs r2, #0 8002958: 2100 movs r1, #0 800295a: 2002 movs r0, #2 800295c: f001 ff88 bl 8004870 SetMotPerc(M3, FW, 0); 8002960: 2200 movs r2, #0 8002962: 2100 movs r1, #0 8002964: 2003 movs r0, #3 8002966: f001 ff83 bl 8004870 SetMotPerc(M4, FW, 0); 800296a: 2200 movs r2, #0 800296c: 2100 movs r1, #0 800296e: 2004 movs r0, #4 8002970: f001 ff7e bl 8004870 SetMotPerc(M1, BW, 0); 8002974: 2200 movs r2, #0 8002976: 2101 movs r1, #1 8002978: 2001 movs r0, #1 800297a: f001 ff79 bl 8004870 SetMotPerc(M2, BW, 0); 800297e: 2200 movs r2, #0 8002980: 2101 movs r1, #1 8002982: 2002 movs r0, #2 8002984: f001 ff74 bl 8004870 SetMotPerc(M3, BW, 0); 8002988: 2200 movs r2, #0 800298a: 2101 movs r1, #1 800298c: 2003 movs r0, #3 800298e: f001 ff6f bl 8004870 SetMotPerc(M4, BW, 0); 8002992: 2200 movs r2, #0 8002994: 2101 movs r1, #1 8002996: 2004 movs r0, #4 8002998: f001 ff6a bl 8004870 if (pulsanti == 0) { 800299c: 4b4d ldr r3, [pc, #308] @ (8002ad4 ) 800299e: 781b ldrb r3, [r3, #0] 80029a0: 2b00 cmp r3, #0 80029a2: f040 8338 bne.w 8003016 stBuz = bzoff; 80029a6: 4b4c ldr r3, [pc, #304] @ (8002ad8 ) 80029a8: 2200 movs r2, #0 80029aa: 701a strb r2, [r3, #0] stCiclo = omaperto; 80029ac: 4b48 ldr r3, [pc, #288] @ (8002ad0 ) 80029ae: 2216 movs r2, #22 80029b0: 701a strb r2, [r3, #0] } break; 80029b2: e330 b.n 8003016 case omapertura0: if (rtCiclo >= 30) { //dopo 3 secondi 80029b4: 4b44 ldr r3, [pc, #272] @ (8002ac8 ) 80029b6: 881b ldrh r3, [r3, #0] 80029b8: b29b uxth r3, r3 80029ba: 2b1d cmp r3, #29 80029bc: d924 bls.n 8002a08 stBuz = bzmoving; 80029be: 4b46 ldr r3, [pc, #280] @ (8002ad8 ) 80029c0: 2201 movs r2, #1 80029c2: 701a strb r2, [r3, #0] m1 = m1ap(); 80029c4: f000 fed6 bl 8003774 80029c8: 4603 mov r3, r0 80029ca: 71fb strb r3, [r7, #7] m2 = m2ap(); 80029cc: f000 ffa4 bl 8003918 80029d0: 4603 mov r3, r0 80029d2: 71bb strb r3, [r7, #6] m3 = m3ap(); 80029d4: f001 f872 bl 8003abc 80029d8: 4603 mov r3, r0 80029da: 717b strb r3, [r7, #5] m4 = m4ap(); 80029dc: f001 f942 bl 8003c64 80029e0: 4603 mov r3, r0 80029e2: 713b strb r3, [r7, #4] if ((m1 == motStop) && (m2 == motStop) && (m3 == motStop) 80029e4: 79fb ldrb r3, [r7, #7] 80029e6: 2b04 cmp r3, #4 80029e8: d10e bne.n 8002a08 80029ea: 79bb ldrb r3, [r7, #6] 80029ec: 2b04 cmp r3, #4 80029ee: d10b bne.n 8002a08 80029f0: 797b ldrb r3, [r7, #5] 80029f2: 2b04 cmp r3, #4 80029f4: d108 bne.n 8002a08 && (m4 == motStop)) { 80029f6: 793b ldrb r3, [r7, #4] 80029f8: 2b04 cmp r3, #4 80029fa: d105 bne.n 8002a08 stBuz = bzoff; 80029fc: 4b36 ldr r3, [pc, #216] @ (8002ad8 ) 80029fe: 2200 movs r2, #0 8002a00: 701a strb r2, [r3, #0] stCiclo = omaperto; 8002a02: 4b33 ldr r3, [pc, #204] @ (8002ad0 ) 8002a04: 2216 movs r2, #22 8002a06: 701a strb r2, [r3, #0] } } if (stPulsanti & P1STOP) 8002a08: 4b34 ldr r3, [pc, #208] @ (8002adc ) 8002a0a: 881b ldrh r3, [r3, #0] 8002a0c: f003 0302 and.w r3, r3, #2 8002a10: 2b00 cmp r3, #0 8002a12: d002 beq.n 8002a1a stCiclo = omstopapertura; 8002a14: 4b2e ldr r3, [pc, #184] @ (8002ad0 ) 8002a16: 2213 movs r2, #19 8002a18: 701a strb r2, [r3, #0] if ((stPulsanti & P1START)&&(stPulsanti & P1RELEASED)) { 8002a1a: 4b30 ldr r3, [pc, #192] @ (8002adc ) 8002a1c: 881b ldrh r3, [r3, #0] 8002a1e: f003 0301 and.w r3, r3, #1 8002a22: 2b00 cmp r3, #0 8002a24: f000 82f9 beq.w 800301a 8002a28: 4b2c ldr r3, [pc, #176] @ (8002adc ) 8002a2a: 881b ldrh r3, [r3, #0] 8002a2c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8002a30: 2b00 cmp r3, #0 8002a32: f000 82f2 beq.w 800301a stCiclo = omstoprestartchiusura; 8002a36: 4b26 ldr r3, [pc, #152] @ (8002ad0 ) 8002a38: 2214 movs r2, #20 8002a3a: 701a strb r2, [r3, #0] rtCiclo = 0; 8002a3c: 4b22 ldr r3, [pc, #136] @ (8002ac8 ) 8002a3e: 2200 movs r2, #0 8002a40: 801a strh r2, [r3, #0] } break; 8002a42: e2ea b.n 800301a case omstopapertura: SetMotPerc(M1, FW, 0); 8002a44: 2200 movs r2, #0 8002a46: 2100 movs r1, #0 8002a48: 2001 movs r0, #1 8002a4a: f001 ff11 bl 8004870 SetMotPerc(M2, FW, 0); 8002a4e: 2200 movs r2, #0 8002a50: 2100 movs r1, #0 8002a52: 2002 movs r0, #2 8002a54: f001 ff0c bl 8004870 SetMotPerc(M3, FW, 0); 8002a58: 2200 movs r2, #0 8002a5a: 2100 movs r1, #0 8002a5c: 2003 movs r0, #3 8002a5e: f001 ff07 bl 8004870 SetMotPerc(M4, FW, 0); 8002a62: 2200 movs r2, #0 8002a64: 2100 movs r1, #0 8002a66: 2004 movs r0, #4 8002a68: f001 ff02 bl 8004870 SetMotPerc(M1, BW, 0); 8002a6c: 2200 movs r2, #0 8002a6e: 2101 movs r1, #1 8002a70: 2001 movs r0, #1 8002a72: f001 fefd bl 8004870 SetMotPerc(M2, BW, 0); 8002a76: 2200 movs r2, #0 8002a78: 2101 movs r1, #1 8002a7a: 2002 movs r0, #2 8002a7c: f001 fef8 bl 8004870 SetMotPerc(M3, BW, 0); 8002a80: 2200 movs r2, #0 8002a82: 2101 movs r1, #1 8002a84: 2003 movs r0, #3 8002a86: f001 fef3 bl 8004870 SetMotPerc(M4, BW, 0); 8002a8a: 2200 movs r2, #0 8002a8c: 2101 movs r1, #1 8002a8e: 2004 movs r0, #4 8002a90: f001 feee bl 8004870 if (pulsanti == 0) { 8002a94: 4b0f ldr r3, [pc, #60] @ (8002ad4 ) 8002a96: 781b ldrb r3, [r3, #0] 8002a98: 2b00 cmp r3, #0 8002a9a: f040 82c0 bne.w 800301e stBuz = bzoff; 8002a9e: 4b0e ldr r3, [pc, #56] @ (8002ad8 ) 8002aa0: 2200 movs r2, #0 8002aa2: 701a strb r2, [r3, #0] stCiclo = omchiuso; 8002aa4: 4b0a ldr r3, [pc, #40] @ (8002ad0 ) 8002aa6: 2200 movs r2, #0 8002aa8: 701a strb r2, [r3, #0] stPulsanti &= (~P1STOP); 8002aaa: 4b0c ldr r3, [pc, #48] @ (8002adc ) 8002aac: 881b ldrh r3, [r3, #0] 8002aae: f023 0302 bic.w r3, r3, #2 8002ab2: b29a uxth r2, r3 8002ab4: 4b09 ldr r3, [pc, #36] @ (8002adc ) 8002ab6: 801a strh r2, [r3, #0] } break; 8002ab8: e2b1 b.n 800301e 8002aba: bf00 nop 8002abc: 2000044c .word 0x2000044c 8002ac0: 20000426 .word 0x20000426 8002ac4: 2000041e .word 0x2000041e 8002ac8: 200003fc .word 0x200003fc 8002acc: 20000416 .word 0x20000416 8002ad0: 20000456 .word 0x20000456 8002ad4: 200003f0 .word 0x200003f0 8002ad8: 20000457 .word 0x20000457 8002adc: 20000454 .word 0x20000454 case omstoprestartchiusura: SetMotPerc(M1, FW, 0); 8002ae0: 2200 movs r2, #0 8002ae2: 2100 movs r1, #0 8002ae4: 2001 movs r0, #1 8002ae6: f001 fec3 bl 8004870 SetMotPerc(M2, FW, 0); 8002aea: 2200 movs r2, #0 8002aec: 2100 movs r1, #0 8002aee: 2002 movs r0, #2 8002af0: f001 febe bl 8004870 SetMotPerc(M3, FW, 0); 8002af4: 2200 movs r2, #0 8002af6: 2100 movs r1, #0 8002af8: 2003 movs r0, #3 8002afa: f001 feb9 bl 8004870 SetMotPerc(M4, FW, 0); 8002afe: 2200 movs r2, #0 8002b00: 2100 movs r1, #0 8002b02: 2004 movs r0, #4 8002b04: f001 feb4 bl 8004870 SetMotPerc(M1, BW, 0); 8002b08: 2200 movs r2, #0 8002b0a: 2101 movs r1, #1 8002b0c: 2001 movs r0, #1 8002b0e: f001 feaf bl 8004870 SetMotPerc(M2, BW, 0); 8002b12: 2200 movs r2, #0 8002b14: 2101 movs r1, #1 8002b16: 2002 movs r0, #2 8002b18: f001 feaa bl 8004870 SetMotPerc(M3, BW, 0); 8002b1c: 2200 movs r2, #0 8002b1e: 2101 movs r1, #1 8002b20: 2003 movs r0, #3 8002b22: f001 fea5 bl 8004870 SetMotPerc(M4, BW, 0); 8002b26: 2200 movs r2, #0 8002b28: 2101 movs r1, #1 8002b2a: 2004 movs r0, #4 8002b2c: f001 fea0 bl 8004870 stBuz = bzoff; 8002b30: 4b98 ldr r3, [pc, #608] @ (8002d94 ) 8002b32: 2200 movs r2, #0 8002b34: 701a strb r2, [r3, #0] if (rtCiclo >= 20) 8002b36: 4b98 ldr r3, [pc, #608] @ (8002d98 ) 8002b38: 881b ldrh r3, [r3, #0] 8002b3a: b29b uxth r3, r3 8002b3c: 2b13 cmp r3, #19 8002b3e: f240 8270 bls.w 8003022 stCiclo = omaperto; 8002b42: 4b96 ldr r3, [pc, #600] @ (8002d9c ) 8002b44: 2216 movs r2, #22 8002b46: 701a strb r2, [r3, #0] break; 8002b48: e26b b.n 8003022 case omaperto: stPulsanti &= (~P1RELEASED); 8002b4a: 4b95 ldr r3, [pc, #596] @ (8002da0 ) 8002b4c: 881b ldrh r3, [r3, #0] 8002b4e: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8002b52: b29a uxth r2, r3 8002b54: 4b92 ldr r3, [pc, #584] @ (8002da0 ) 8002b56: 801a strh r2, [r3, #0] rtCiclo = 0; 8002b58: 4b8f ldr r3, [pc, #572] @ (8002d98 ) 8002b5a: 2200 movs r2, #0 8002b5c: 801a strh r2, [r3, #0] if (stPulsanti & P1START) { 8002b5e: 4b90 ldr r3, [pc, #576] @ (8002da0 ) 8002b60: 881b ldrh r3, [r3, #0] 8002b62: f003 0301 and.w r3, r3, #1 8002b66: 2b00 cmp r3, #0 8002b68: d00d beq.n 8002b86 stBuz = bzmoving; 8002b6a: 4b8a ldr r3, [pc, #552] @ (8002d94 ) 8002b6c: 2201 movs r2, #1 8002b6e: 701a strb r2, [r3, #0] //(void)ramp(M1,BW,mrampstart[M1-1],m1pwmch,tramp,RAMPINIT); stCiclo = omchiusura1; 8002b70: 4b8a ldr r3, [pc, #552] @ (8002d9c ) 8002b72: 2217 movs r2, #23 8002b74: 701a strb r2, [r3, #0] (void) m1ch(); 8002b76: f001 f949 bl 8003e0c (void) m2ch(); 8002b7a: f001 fa19 bl 8003fb0 (void) m3ch(); 8002b7e: f001 fae9 bl 8004154 (void) m4ch(); 8002b82: f001 fbbb bl 80042fc } if (ch8 > thanem) { 8002b86: 4b87 ldr r3, [pc, #540] @ (8002da4 ) 8002b88: 881a ldrh r2, [r3, #0] 8002b8a: 4b87 ldr r3, [pc, #540] @ (8002da8 ) 8002b8c: 881b ldrh r3, [r3, #0] 8002b8e: 429a cmp r2, r3 8002b90: d919 bls.n 8002bc6 HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); 8002b92: 2201 movs r2, #1 8002b94: f44f 4100 mov.w r1, #32768 @ 0x8000 8002b98: 4884 ldr r0, [pc, #528] @ (8002dac ) 8002b9a: f003 fd98 bl 80066ce if (rtAnem == 0) { 8002b9e: 4b84 ldr r3, [pc, #528] @ (8002db0 ) 8002ba0: 881b ldrh r3, [r3, #0] 8002ba2: b29b uxth r3, r3 8002ba4: 2b00 cmp r3, #0 8002ba6: d118 bne.n 8002bda stBuz = bzmoving; 8002ba8: 4b7a ldr r3, [pc, #488] @ (8002d94 ) 8002baa: 2201 movs r2, #1 8002bac: 701a strb r2, [r3, #0] stCiclo = omemergenza1; 8002bae: 4b7b ldr r3, [pc, #492] @ (8002d9c ) 8002bb0: 2218 movs r2, #24 8002bb2: 701a strb r2, [r3, #0] (void) m1ch(); 8002bb4: f001 f92a bl 8003e0c (void) m2ch(); 8002bb8: f001 f9fa bl 8003fb0 (void) m3ch(); 8002bbc: f001 faca bl 8004154 (void) m4ch(); 8002bc0: f001 fb9c bl 80042fc 8002bc4: e009 b.n 8002bda } } else{ HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET); 8002bc6: 2200 movs r2, #0 8002bc8: f44f 4100 mov.w r1, #32768 @ 0x8000 8002bcc: 4877 ldr r0, [pc, #476] @ (8002dac ) 8002bce: f003 fd7e bl 80066ce rtAnem = tanem; 8002bd2: 4b78 ldr r3, [pc, #480] @ (8002db4 ) 8002bd4: 881a ldrh r2, [r3, #0] 8002bd6: 4b76 ldr r3, [pc, #472] @ (8002db0 ) 8002bd8: 801a strh r2, [r3, #0] } if (stPulsanti & P1STOP) 8002bda: 4b71 ldr r3, [pc, #452] @ (8002da0 ) 8002bdc: 881b ldrh r3, [r3, #0] 8002bde: f003 0302 and.w r3, r3, #2 8002be2: 2b00 cmp r3, #0 8002be4: d003 beq.n 8002bee stCiclo = omstopchiusura; 8002be6: 4b6d ldr r3, [pc, #436] @ (8002d9c ) 8002be8: 2219 movs r2, #25 8002bea: 701a strb r2, [r3, #0] stBuz = bzmoving; (void) ramp(M4, BW, mrampstart[M4 - 1], m3pwmMan, trampman, RAMPINIT); stCiclo = omM4bw1; } break; 8002bec: e21b b.n 8003026 else if (stPulsanti & M1FW) { 8002bee: 4b6c ldr r3, [pc, #432] @ (8002da0 ) 8002bf0: 881b ldrh r3, [r3, #0] 8002bf2: f003 0310 and.w r3, r3, #16 8002bf6: 2b00 cmp r3, #0 8002bf8: d017 beq.n 8002c2a stBuz = bzmoving; 8002bfa: 4b66 ldr r3, [pc, #408] @ (8002d94 ) 8002bfc: 2201 movs r2, #1 8002bfe: 701a strb r2, [r3, #0] (void) ramp(M1, FW, mrampstart[M1 - 1], m1pwmMan, trampman, 8002c00: 4b6d ldr r3, [pc, #436] @ (8002db8 ) 8002c02: 881b ldrh r3, [r3, #0] 8002c04: b2da uxtb r2, r3 8002c06: 4b6d ldr r3, [pc, #436] @ (8002dbc ) 8002c08: 881b ldrh r3, [r3, #0] 8002c0a: b2d9 uxtb r1, r3 8002c0c: 4b6c ldr r3, [pc, #432] @ (8002dc0 ) 8002c0e: 881b ldrh r3, [r3, #0] 8002c10: b2db uxtb r3, r3 8002c12: 2000 movs r0, #0 8002c14: 9001 str r0, [sp, #4] 8002c16: 9300 str r3, [sp, #0] 8002c18: 460b mov r3, r1 8002c1a: 2100 movs r1, #0 8002c1c: 2001 movs r0, #1 8002c1e: f001 ffa7 bl 8004b70 stCiclo = omM1fw1; 8002c22: 4b5e ldr r3, [pc, #376] @ (8002d9c ) 8002c24: 2201 movs r2, #1 8002c26: 701a strb r2, [r3, #0] break; 8002c28: e1fd b.n 8003026 } else if (stPulsanti & M1BW) { 8002c2a: 4b5d ldr r3, [pc, #372] @ (8002da0 ) 8002c2c: 881b ldrh r3, [r3, #0] 8002c2e: f003 0320 and.w r3, r3, #32 8002c32: 2b00 cmp r3, #0 8002c34: d017 beq.n 8002c66 stBuz = bzmoving; 8002c36: 4b57 ldr r3, [pc, #348] @ (8002d94 ) 8002c38: 2201 movs r2, #1 8002c3a: 701a strb r2, [r3, #0] (void) ramp(M1, BW, mrampstart[M1 - 1], m1pwmMan, trampman, 8002c3c: 4b5e ldr r3, [pc, #376] @ (8002db8 ) 8002c3e: 881b ldrh r3, [r3, #0] 8002c40: b2da uxtb r2, r3 8002c42: 4b5e ldr r3, [pc, #376] @ (8002dbc ) 8002c44: 881b ldrh r3, [r3, #0] 8002c46: b2d9 uxtb r1, r3 8002c48: 4b5d ldr r3, [pc, #372] @ (8002dc0 ) 8002c4a: 881b ldrh r3, [r3, #0] 8002c4c: b2db uxtb r3, r3 8002c4e: 2000 movs r0, #0 8002c50: 9001 str r0, [sp, #4] 8002c52: 9300 str r3, [sp, #0] 8002c54: 460b mov r3, r1 8002c56: 2101 movs r1, #1 8002c58: 2001 movs r0, #1 8002c5a: f001 ff89 bl 8004b70 stCiclo = omM1bw1; 8002c5e: 4b4f ldr r3, [pc, #316] @ (8002d9c ) 8002c60: 2203 movs r2, #3 8002c62: 701a strb r2, [r3, #0] break; 8002c64: e1df b.n 8003026 } else if (stPulsanti & M2FW) { 8002c66: 4b4e ldr r3, [pc, #312] @ (8002da0 ) 8002c68: 881b ldrh r3, [r3, #0] 8002c6a: f003 0340 and.w r3, r3, #64 @ 0x40 8002c6e: 2b00 cmp r3, #0 8002c70: d017 beq.n 8002ca2 stBuz = bzmoving; 8002c72: 4b48 ldr r3, [pc, #288] @ (8002d94 ) 8002c74: 2201 movs r2, #1 8002c76: 701a strb r2, [r3, #0] (void) ramp(M2, FW, mrampstart[M2 - 1], m2pwmMan, trampman, 8002c78: 4b4f ldr r3, [pc, #316] @ (8002db8 ) 8002c7a: 885b ldrh r3, [r3, #2] 8002c7c: b2da uxtb r2, r3 8002c7e: 4b51 ldr r3, [pc, #324] @ (8002dc4 ) 8002c80: 881b ldrh r3, [r3, #0] 8002c82: b2d9 uxtb r1, r3 8002c84: 4b4e ldr r3, [pc, #312] @ (8002dc0 ) 8002c86: 881b ldrh r3, [r3, #0] 8002c88: b2db uxtb r3, r3 8002c8a: 2000 movs r0, #0 8002c8c: 9001 str r0, [sp, #4] 8002c8e: 9300 str r3, [sp, #0] 8002c90: 460b mov r3, r1 8002c92: 2100 movs r1, #0 8002c94: 2002 movs r0, #2 8002c96: f001 ff6b bl 8004b70 stCiclo = omM2fw1; 8002c9a: 4b40 ldr r3, [pc, #256] @ (8002d9c ) 8002c9c: 2205 movs r2, #5 8002c9e: 701a strb r2, [r3, #0] break; 8002ca0: e1c1 b.n 8003026 } else if (stPulsanti & M2BW) { 8002ca2: 4b3f ldr r3, [pc, #252] @ (8002da0 ) 8002ca4: 881b ldrh r3, [r3, #0] 8002ca6: f003 0380 and.w r3, r3, #128 @ 0x80 8002caa: 2b00 cmp r3, #0 8002cac: d017 beq.n 8002cde stBuz = bzmoving; 8002cae: 4b39 ldr r3, [pc, #228] @ (8002d94 ) 8002cb0: 2201 movs r2, #1 8002cb2: 701a strb r2, [r3, #0] (void) ramp(M2, BW, mrampstart[M2 - 1], m2pwmMan, trampman, 8002cb4: 4b40 ldr r3, [pc, #256] @ (8002db8 ) 8002cb6: 885b ldrh r3, [r3, #2] 8002cb8: b2da uxtb r2, r3 8002cba: 4b42 ldr r3, [pc, #264] @ (8002dc4 ) 8002cbc: 881b ldrh r3, [r3, #0] 8002cbe: b2d9 uxtb r1, r3 8002cc0: 4b3f ldr r3, [pc, #252] @ (8002dc0 ) 8002cc2: 881b ldrh r3, [r3, #0] 8002cc4: b2db uxtb r3, r3 8002cc6: 2000 movs r0, #0 8002cc8: 9001 str r0, [sp, #4] 8002cca: 9300 str r3, [sp, #0] 8002ccc: 460b mov r3, r1 8002cce: 2101 movs r1, #1 8002cd0: 2002 movs r0, #2 8002cd2: f001 ff4d bl 8004b70 stCiclo = omM2bw1; 8002cd6: 4b31 ldr r3, [pc, #196] @ (8002d9c ) 8002cd8: 2207 movs r2, #7 8002cda: 701a strb r2, [r3, #0] break; 8002cdc: e1a3 b.n 8003026 } else if (stPulsanti & M3FW) { 8002cde: 4b30 ldr r3, [pc, #192] @ (8002da0 ) 8002ce0: 881b ldrh r3, [r3, #0] 8002ce2: f403 7380 and.w r3, r3, #256 @ 0x100 8002ce6: 2b00 cmp r3, #0 8002ce8: d017 beq.n 8002d1a stBuz = bzmoving; 8002cea: 4b2a ldr r3, [pc, #168] @ (8002d94 ) 8002cec: 2201 movs r2, #1 8002cee: 701a strb r2, [r3, #0] (void) ramp(M3, FW, mrampstart[M3 - 1], m3pwmMan, trampman, 8002cf0: 4b31 ldr r3, [pc, #196] @ (8002db8 ) 8002cf2: 889b ldrh r3, [r3, #4] 8002cf4: b2da uxtb r2, r3 8002cf6: 4b34 ldr r3, [pc, #208] @ (8002dc8 ) 8002cf8: 881b ldrh r3, [r3, #0] 8002cfa: b2d9 uxtb r1, r3 8002cfc: 4b30 ldr r3, [pc, #192] @ (8002dc0 ) 8002cfe: 881b ldrh r3, [r3, #0] 8002d00: b2db uxtb r3, r3 8002d02: 2000 movs r0, #0 8002d04: 9001 str r0, [sp, #4] 8002d06: 9300 str r3, [sp, #0] 8002d08: 460b mov r3, r1 8002d0a: 2100 movs r1, #0 8002d0c: 2003 movs r0, #3 8002d0e: f001 ff2f bl 8004b70 stCiclo = omM3fw1; 8002d12: 4b22 ldr r3, [pc, #136] @ (8002d9c ) 8002d14: 2209 movs r2, #9 8002d16: 701a strb r2, [r3, #0] break; 8002d18: e185 b.n 8003026 } else if (stPulsanti & M3BW) { 8002d1a: 4b21 ldr r3, [pc, #132] @ (8002da0 ) 8002d1c: 881b ldrh r3, [r3, #0] 8002d1e: f403 7300 and.w r3, r3, #512 @ 0x200 8002d22: 2b00 cmp r3, #0 8002d24: d017 beq.n 8002d56 stBuz = bzmoving; 8002d26: 4b1b ldr r3, [pc, #108] @ (8002d94 ) 8002d28: 2201 movs r2, #1 8002d2a: 701a strb r2, [r3, #0] (void) ramp(M3, BW, mrampstart[M3 - 1], m3pwmMan, trampman, 8002d2c: 4b22 ldr r3, [pc, #136] @ (8002db8 ) 8002d2e: 889b ldrh r3, [r3, #4] 8002d30: b2da uxtb r2, r3 8002d32: 4b25 ldr r3, [pc, #148] @ (8002dc8 ) 8002d34: 881b ldrh r3, [r3, #0] 8002d36: b2d9 uxtb r1, r3 8002d38: 4b21 ldr r3, [pc, #132] @ (8002dc0 ) 8002d3a: 881b ldrh r3, [r3, #0] 8002d3c: b2db uxtb r3, r3 8002d3e: 2000 movs r0, #0 8002d40: 9001 str r0, [sp, #4] 8002d42: 9300 str r3, [sp, #0] 8002d44: 460b mov r3, r1 8002d46: 2101 movs r1, #1 8002d48: 2003 movs r0, #3 8002d4a: f001 ff11 bl 8004b70 stCiclo = omM3bw1; 8002d4e: 4b13 ldr r3, [pc, #76] @ (8002d9c ) 8002d50: 220b movs r2, #11 8002d52: 701a strb r2, [r3, #0] break; 8002d54: e167 b.n 8003026 } else if (stPulsanti & M4FW) { 8002d56: 4b12 ldr r3, [pc, #72] @ (8002da0 ) 8002d58: 881b ldrh r3, [r3, #0] 8002d5a: f403 6380 and.w r3, r3, #1024 @ 0x400 8002d5e: 2b00 cmp r3, #0 8002d60: d034 beq.n 8002dcc stBuz = bzmoving; 8002d62: 4b0c ldr r3, [pc, #48] @ (8002d94 ) 8002d64: 2201 movs r2, #1 8002d66: 701a strb r2, [r3, #0] (void) ramp(M4, FW, mrampstart[M4 - 1], m3pwmMan, trampman, 8002d68: 4b13 ldr r3, [pc, #76] @ (8002db8 ) 8002d6a: 88db ldrh r3, [r3, #6] 8002d6c: b2da uxtb r2, r3 8002d6e: 4b16 ldr r3, [pc, #88] @ (8002dc8 ) 8002d70: 881b ldrh r3, [r3, #0] 8002d72: b2d9 uxtb r1, r3 8002d74: 4b12 ldr r3, [pc, #72] @ (8002dc0 ) 8002d76: 881b ldrh r3, [r3, #0] 8002d78: b2db uxtb r3, r3 8002d7a: 2000 movs r0, #0 8002d7c: 9001 str r0, [sp, #4] 8002d7e: 9300 str r3, [sp, #0] 8002d80: 460b mov r3, r1 8002d82: 2100 movs r1, #0 8002d84: 2004 movs r0, #4 8002d86: f001 fef3 bl 8004b70 stCiclo = omM4fw1; 8002d8a: 4b04 ldr r3, [pc, #16] @ (8002d9c ) 8002d8c: 220d movs r2, #13 8002d8e: 701a strb r2, [r3, #0] break; 8002d90: e149 b.n 8003026 8002d92: bf00 nop 8002d94: 20000457 .word 0x20000457 8002d98: 200003fc .word 0x200003fc 8002d9c: 20000456 .word 0x20000456 8002da0: 20000454 .word 0x20000454 8002da4: 20000232 .word 0x20000232 8002da8: 2000041c .word 0x2000041c 8002dac: 40010800 .word 0x40010800 8002db0: 200003fe .word 0x200003fe 8002db4: 2000041a .word 0x2000041a 8002db8: 2000044c .word 0x2000044c 8002dbc: 20000420 .word 0x20000420 8002dc0: 2000041e .word 0x2000041e 8002dc4: 20000422 .word 0x20000422 8002dc8: 20000424 .word 0x20000424 } else if (stPulsanti & M4BW) { 8002dcc: 4b9c ldr r3, [pc, #624] @ (8003040 ) 8002dce: 881b ldrh r3, [r3, #0] 8002dd0: f403 6300 and.w r3, r3, #2048 @ 0x800 8002dd4: 2b00 cmp r3, #0 8002dd6: f000 8126 beq.w 8003026 stBuz = bzmoving; 8002dda: 4b9a ldr r3, [pc, #616] @ (8003044 ) 8002ddc: 2201 movs r2, #1 8002dde: 701a strb r2, [r3, #0] (void) ramp(M4, BW, mrampstart[M4 - 1], m3pwmMan, trampman, 8002de0: 4b99 ldr r3, [pc, #612] @ (8003048 ) 8002de2: 88db ldrh r3, [r3, #6] 8002de4: b2da uxtb r2, r3 8002de6: 4b99 ldr r3, [pc, #612] @ (800304c ) 8002de8: 881b ldrh r3, [r3, #0] 8002dea: b2d9 uxtb r1, r3 8002dec: 4b98 ldr r3, [pc, #608] @ (8003050 ) 8002dee: 881b ldrh r3, [r3, #0] 8002df0: b2db uxtb r3, r3 8002df2: 2000 movs r0, #0 8002df4: 9001 str r0, [sp, #4] 8002df6: 9300 str r3, [sp, #0] 8002df8: 460b mov r3, r1 8002dfa: 2101 movs r1, #1 8002dfc: 2004 movs r0, #4 8002dfe: f001 feb7 bl 8004b70 stCiclo = omM4bw1; 8002e02: 4b94 ldr r3, [pc, #592] @ (8003054 ) 8002e04: 220f movs r2, #15 8002e06: 701a strb r2, [r3, #0] break; 8002e08: e10d b.n 8003026 case omchiusura1: if (rtCiclo >= 10) { //doppo 1 secondi 8002e0a: 4b93 ldr r3, [pc, #588] @ (8003058 ) 8002e0c: 881b ldrh r3, [r3, #0] 8002e0e: b29b uxth r3, r3 8002e10: 2b09 cmp r3, #9 8002e12: d924 bls.n 8002e5e m1 = m1ch(); 8002e14: f000 fffa bl 8003e0c 8002e18: 4603 mov r3, r0 8002e1a: 71fb strb r3, [r7, #7] m2 = m2ch(); 8002e1c: f001 f8c8 bl 8003fb0 8002e20: 4603 mov r3, r0 8002e22: 71bb strb r3, [r7, #6] m3 = m3ch(); 8002e24: f001 f996 bl 8004154 8002e28: 4603 mov r3, r0 8002e2a: 717b strb r3, [r7, #5] m4 = m4ch(); 8002e2c: f001 fa66 bl 80042fc 8002e30: 4603 mov r3, r0 8002e32: 713b strb r3, [r7, #4] if ((m1 == motStop) && (m2 == motStop) && (m3 == motStop) 8002e34: 79fb ldrb r3, [r7, #7] 8002e36: 2b04 cmp r3, #4 8002e38: d111 bne.n 8002e5e 8002e3a: 79bb ldrb r3, [r7, #6] 8002e3c: 2b04 cmp r3, #4 8002e3e: d10e bne.n 8002e5e 8002e40: 797b ldrb r3, [r7, #5] 8002e42: 2b04 cmp r3, #4 8002e44: d10b bne.n 8002e5e && (m4 == motStop)) { 8002e46: 793b ldrb r3, [r7, #4] 8002e48: 2b04 cmp r3, #4 8002e4a: d108 bne.n 8002e5e stBuz = bzoff; 8002e4c: 4b7d ldr r3, [pc, #500] @ (8003044 ) 8002e4e: 2200 movs r2, #0 8002e50: 701a strb r2, [r3, #0] stCiclo = omchiuso; 8002e52: 4b80 ldr r3, [pc, #512] @ (8003054 ) 8002e54: 2200 movs r2, #0 8002e56: 701a strb r2, [r3, #0] fchiuso = true; 8002e58: 4b80 ldr r3, [pc, #512] @ (800305c ) 8002e5a: 2201 movs r2, #1 8002e5c: 701a strb r2, [r3, #0] } } if (stPulsanti & P1STOP) 8002e5e: 4b78 ldr r3, [pc, #480] @ (8003040 ) 8002e60: 881b ldrh r3, [r3, #0] 8002e62: f003 0302 and.w r3, r3, #2 8002e66: 2b00 cmp r3, #0 8002e68: d002 beq.n 8002e70 stCiclo = omstopchiusura; 8002e6a: 4b7a ldr r3, [pc, #488] @ (8003054 ) 8002e6c: 2219 movs r2, #25 8002e6e: 701a strb r2, [r3, #0] if ((stPulsanti & P1START)&&(stPulsanti & P1RELEASED)) { 8002e70: 4b73 ldr r3, [pc, #460] @ (8003040 ) 8002e72: 881b ldrh r3, [r3, #0] 8002e74: f003 0301 and.w r3, r3, #1 8002e78: 2b00 cmp r3, #0 8002e7a: f000 80d6 beq.w 800302a 8002e7e: 4b70 ldr r3, [pc, #448] @ (8003040 ) 8002e80: 881b ldrh r3, [r3, #0] 8002e82: f403 5380 and.w r3, r3, #4096 @ 0x1000 8002e86: 2b00 cmp r3, #0 8002e88: f000 80cf beq.w 800302a stCiclo = omstoprestartapertura; 8002e8c: 4b71 ldr r3, [pc, #452] @ (8003054 ) 8002e8e: 2215 movs r2, #21 8002e90: 701a strb r2, [r3, #0] rtCiclo = 0; 8002e92: 4b71 ldr r3, [pc, #452] @ (8003058 ) 8002e94: 2200 movs r2, #0 8002e96: 801a strh r2, [r3, #0] } break; 8002e98: e0c7 b.n 800302a case omemergenza1: if (rtCiclo >= 10) { //doppo 1 secondi 8002e9a: 4b6f ldr r3, [pc, #444] @ (8003058 ) 8002e9c: 881b ldrh r3, [r3, #0] 8002e9e: b29b uxth r3, r3 8002ea0: 2b09 cmp r3, #9 8002ea2: f240 80c4 bls.w 800302e m1 = m1ch(); 8002ea6: f000 ffb1 bl 8003e0c 8002eaa: 4603 mov r3, r0 8002eac: 71fb strb r3, [r7, #7] m2 = m2ch(); 8002eae: f001 f87f bl 8003fb0 8002eb2: 4603 mov r3, r0 8002eb4: 71bb strb r3, [r7, #6] m3 = m3ch(); 8002eb6: f001 f94d bl 8004154 8002eba: 4603 mov r3, r0 8002ebc: 717b strb r3, [r7, #5] m4 = m4ch(); 8002ebe: f001 fa1d bl 80042fc 8002ec2: 4603 mov r3, r0 8002ec4: 713b strb r3, [r7, #4] if ((m1 == motStop) && (m2 == motStop) && (m3 == motStop) 8002ec6: 79fb ldrb r3, [r7, #7] 8002ec8: 2b04 cmp r3, #4 8002eca: f040 80b0 bne.w 800302e 8002ece: 79bb ldrb r3, [r7, #6] 8002ed0: 2b04 cmp r3, #4 8002ed2: f040 80ac bne.w 800302e 8002ed6: 797b ldrb r3, [r7, #5] 8002ed8: 2b04 cmp r3, #4 8002eda: f040 80a8 bne.w 800302e && (m4 == motStop)) { 8002ede: 793b ldrb r3, [r7, #4] 8002ee0: 2b04 cmp r3, #4 8002ee2: f040 80a4 bne.w 800302e stBuz = bzoff; 8002ee6: 4b57 ldr r3, [pc, #348] @ (8003044 ) 8002ee8: 2200 movs r2, #0 8002eea: 701a strb r2, [r3, #0] stCiclo = omchiuso; 8002eec: 4b59 ldr r3, [pc, #356] @ (8003054 ) 8002eee: 2200 movs r2, #0 8002ef0: 701a strb r2, [r3, #0] fchiuso = true; 8002ef2: 4b5a ldr r3, [pc, #360] @ (800305c ) 8002ef4: 2201 movs r2, #1 8002ef6: 701a strb r2, [r3, #0] } } break; 8002ef8: e099 b.n 800302e case omstoprestartapertura: SetMotPerc(M1, FW, 0); 8002efa: 2200 movs r2, #0 8002efc: 2100 movs r1, #0 8002efe: 2001 movs r0, #1 8002f00: f001 fcb6 bl 8004870 SetMotPerc(M2, FW, 0); 8002f04: 2200 movs r2, #0 8002f06: 2100 movs r1, #0 8002f08: 2002 movs r0, #2 8002f0a: f001 fcb1 bl 8004870 SetMotPerc(M3, FW, 0); 8002f0e: 2200 movs r2, #0 8002f10: 2100 movs r1, #0 8002f12: 2003 movs r0, #3 8002f14: f001 fcac bl 8004870 SetMotPerc(M4, FW, 0); 8002f18: 2200 movs r2, #0 8002f1a: 2100 movs r1, #0 8002f1c: 2004 movs r0, #4 8002f1e: f001 fca7 bl 8004870 SetMotPerc(M1, BW, 0); 8002f22: 2200 movs r2, #0 8002f24: 2101 movs r1, #1 8002f26: 2001 movs r0, #1 8002f28: f001 fca2 bl 8004870 SetMotPerc(M2, BW, 0); 8002f2c: 2200 movs r2, #0 8002f2e: 2101 movs r1, #1 8002f30: 2002 movs r0, #2 8002f32: f001 fc9d bl 8004870 SetMotPerc(M3, BW, 0); 8002f36: 2200 movs r2, #0 8002f38: 2101 movs r1, #1 8002f3a: 2003 movs r0, #3 8002f3c: f001 fc98 bl 8004870 SetMotPerc(M4, BW, 0); 8002f40: 2200 movs r2, #0 8002f42: 2101 movs r1, #1 8002f44: 2004 movs r0, #4 8002f46: f001 fc93 bl 8004870 stBuz = bzoff; 8002f4a: 4b3e ldr r3, [pc, #248] @ (8003044 ) 8002f4c: 2200 movs r2, #0 8002f4e: 701a strb r2, [r3, #0] if (rtCiclo >= 20) 8002f50: 4b41 ldr r3, [pc, #260] @ (8003058 ) 8002f52: 881b ldrh r3, [r3, #0] 8002f54: b29b uxth r3, r3 8002f56: 2b13 cmp r3, #19 8002f58: d96b bls.n 8003032 stCiclo = omchiuso; 8002f5a: 4b3e ldr r3, [pc, #248] @ (8003054 ) 8002f5c: 2200 movs r2, #0 8002f5e: 701a strb r2, [r3, #0] break; 8002f60: e067 b.n 8003032 case omstopchiusura: SetMotPerc(M1, FW, 0); 8002f62: 2200 movs r2, #0 8002f64: 2100 movs r1, #0 8002f66: 2001 movs r0, #1 8002f68: f001 fc82 bl 8004870 SetMotPerc(M2, FW, 0); 8002f6c: 2200 movs r2, #0 8002f6e: 2100 movs r1, #0 8002f70: 2002 movs r0, #2 8002f72: f001 fc7d bl 8004870 SetMotPerc(M3, FW, 0); 8002f76: 2200 movs r2, #0 8002f78: 2100 movs r1, #0 8002f7a: 2003 movs r0, #3 8002f7c: f001 fc78 bl 8004870 SetMotPerc(M4, FW, 0); 8002f80: 2200 movs r2, #0 8002f82: 2100 movs r1, #0 8002f84: 2004 movs r0, #4 8002f86: f001 fc73 bl 8004870 SetMotPerc(M1, BW, 0); 8002f8a: 2200 movs r2, #0 8002f8c: 2101 movs r1, #1 8002f8e: 2001 movs r0, #1 8002f90: f001 fc6e bl 8004870 SetMotPerc(M2, BW, 0); 8002f94: 2200 movs r2, #0 8002f96: 2101 movs r1, #1 8002f98: 2002 movs r0, #2 8002f9a: f001 fc69 bl 8004870 SetMotPerc(M3, BW, 0); 8002f9e: 2200 movs r2, #0 8002fa0: 2101 movs r1, #1 8002fa2: 2003 movs r0, #3 8002fa4: f001 fc64 bl 8004870 SetMotPerc(M4, BW, 0); 8002fa8: 2200 movs r2, #0 8002faa: 2101 movs r1, #1 8002fac: 2004 movs r0, #4 8002fae: f001 fc5f bl 8004870 if (pulsanti == 0) { 8002fb2: 4b2b ldr r3, [pc, #172] @ (8003060 ) 8002fb4: 781b ldrb r3, [r3, #0] 8002fb6: 2b00 cmp r3, #0 8002fb8: d13d bne.n 8003036 stBuz = bzoff; 8002fba: 4b22 ldr r3, [pc, #136] @ (8003044 ) 8002fbc: 2200 movs r2, #0 8002fbe: 701a strb r2, [r3, #0] stCiclo = omaperto; 8002fc0: 4b24 ldr r3, [pc, #144] @ (8003054 ) 8002fc2: 2216 movs r2, #22 8002fc4: 701a strb r2, [r3, #0] stPulsanti &= (~P1STOP); 8002fc6: 4b1e ldr r3, [pc, #120] @ (8003040 ) 8002fc8: 881b ldrh r3, [r3, #0] 8002fca: f023 0302 bic.w r3, r3, #2 8002fce: b29a uxth r2, r3 8002fd0: 4b1b ldr r3, [pc, #108] @ (8003040 ) 8002fd2: 801a strh r2, [r3, #0] } break; 8002fd4: e02f b.n 8003036 break; 8002fd6: bf00 nop 8002fd8: e02e b.n 8003038 break; 8002fda: bf00 nop 8002fdc: e02c b.n 8003038 break; 8002fde: bf00 nop 8002fe0: e02a b.n 8003038 break; 8002fe2: bf00 nop 8002fe4: e028 b.n 8003038 break; 8002fe6: bf00 nop 8002fe8: e026 b.n 8003038 break; 8002fea: bf00 nop 8002fec: e024 b.n 8003038 break; 8002fee: bf00 nop 8002ff0: e022 b.n 8003038 break; 8002ff2: bf00 nop 8002ff4: e020 b.n 8003038 break; 8002ff6: bf00 nop 8002ff8: e01e b.n 8003038 break; 8002ffa: bf00 nop 8002ffc: e01c b.n 8003038 break; 8002ffe: bf00 nop 8003000: e01a b.n 8003038 break; 8003002: bf00 nop 8003004: e018 b.n 8003038 break; 8003006: bf00 nop 8003008: e016 b.n 8003038 break; 800300a: bf00 nop 800300c: e014 b.n 8003038 break; 800300e: bf00 nop 8003010: e012 b.n 8003038 break; 8003012: bf00 nop 8003014: e010 b.n 8003038 break; 8003016: bf00 nop 8003018: e00e b.n 8003038 break; 800301a: bf00 nop 800301c: e00c b.n 8003038 break; 800301e: bf00 nop 8003020: e00a b.n 8003038 break; 8003022: bf00 nop 8003024: e008 b.n 8003038 break; 8003026: bf00 nop 8003028: e006 b.n 8003038 break; 800302a: bf00 nop 800302c: e004 b.n 8003038 break; 800302e: bf00 nop 8003030: e002 b.n 8003038 break; 8003032: bf00 nop 8003034: e000 b.n 8003038 break; 8003036: bf00 nop } } 8003038: bf00 nop 800303a: 3708 adds r7, #8 800303c: 46bd mov sp, r7 800303e: bd80 pop {r7, pc} 8003040: 20000454 .word 0x20000454 8003044: 20000457 .word 0x20000457 8003048: 2000044c .word 0x2000044c 800304c: 20000424 .word 0x20000424 8003050: 2000041e .word 0x2000041e 8003054: 20000456 .word 0x20000456 8003058: 200003fc .word 0x200003fc 800305c: 20000459 .word 0x20000459 8003060: 200003f0 .word 0x200003f0 08003064
: /** * @brief The application entry point. * @retval int */ int main(void) { 8003064: b580 push {r7, lr} 8003066: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8003068: f002 f866 bl 8005138 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800306c: f000 f86e bl 800314c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8003070: f000 fad0 bl 8003614 MX_DMA_Init(); 8003074: f000 fab0 bl 80035d8 MX_USB_DEVICE_Init(); 8003078: f00a fcfe bl 800da78 MX_TIM2_Init(); 800307c: f000 f93c bl 80032f8 MX_TIM4_Init(); 8003080: f000 f9de bl 8003440 MX_ADC1_Init(); 8003084: f000 f8c0 bl 8003208 MX_USART1_UART_Init(); 8003088: f000 fa7c bl 8003584 /* USER CODE BEGIN 2 */ HAL_ADC_Start_DMA(&hadc1, (uint32_t*) adc_dma_buf, ADC_NUM_CHANNELS); 800308c: 2205 movs r2, #5 800308e: 4928 ldr r1, [pc, #160] @ (8003130 ) 8003090: 4828 ldr r0, [pc, #160] @ (8003134 ) 8003092: f002 f98b bl 80053ac StopMot(timMot1, FWMot1); 8003096: 2100 movs r1, #0 8003098: 4827 ldr r0, [pc, #156] @ (8003138 ) 800309a: f001 fa16 bl 80044ca StopMot(timMot1, BWMot1); 800309e: 2104 movs r1, #4 80030a0: 4825 ldr r0, [pc, #148] @ (8003138 ) 80030a2: f001 fa12 bl 80044ca StopMot(timMot2, FWMot2); 80030a6: 2108 movs r1, #8 80030a8: 4823 ldr r0, [pc, #140] @ (8003138 ) 80030aa: f001 fa0e bl 80044ca StopMot(timMot2, BWMot2); 80030ae: 210c movs r1, #12 80030b0: 4821 ldr r0, [pc, #132] @ (8003138 ) 80030b2: f001 fa0a bl 80044ca StopMot(timMot3, FWMot3); 80030b6: 2100 movs r1, #0 80030b8: 4820 ldr r0, [pc, #128] @ (800313c ) 80030ba: f001 fa06 bl 80044ca StopMot(timMot3, BWMot3); 80030be: 2104 movs r1, #4 80030c0: 481e ldr r0, [pc, #120] @ (800313c ) 80030c2: f001 fa02 bl 80044ca StopMot(timMot4, FWMot4); 80030c6: 2108 movs r1, #8 80030c8: 481c ldr r0, [pc, #112] @ (800313c ) 80030ca: f001 f9fe bl 80044ca StopMot(timMot4, BWMot4); 80030ce: 210c movs r1, #12 80030d0: 481a ldr r0, [pc, #104] @ (800313c ) 80030d2: f001 f9fa bl 80044ca //CDC_Transmit_FS((uint8_t*)"Start\r\n", 7); //while (CDC_Transmit_FS((uint8_t*)"Start\r\n", 7) == USBD_BUSY); if (EE_Init() != EE_OK) { 80030d6: f7fe fa79 bl 80015cc 80030da: 4603 mov r3, r0 80030dc: 2b00 cmp r3, #0 80030de: d001 beq.n 80030e4 for (;;) 80030e0: bf00 nop 80030e2: e7fd b.n 80030e0 ; //errore eeprom } loadEE(); 80030e4: f7fe fb5c bl 80017a0 if (flagPar != VERSIONE) { 80030e8: 4b15 ldr r3, [pc, #84] @ (8003140 ) 80030ea: 881b ldrh r3, [r3, #0] 80030ec: 2b05 cmp r3, #5 80030ee: d00f beq.n 8003110 HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_SET); 80030f0: 2201 movs r2, #1 80030f2: f44f 7180 mov.w r1, #256 @ 0x100 80030f6: 4813 ldr r0, [pc, #76] @ (8003144 ) 80030f8: f003 fae9 bl 80066ce loadDefault(); 80030fc: f7fe fb02 bl 8001704 loadEE(); 8003100: f7fe fb4e bl 80017a0 HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_RESET); 8003104: 2200 movs r2, #0 8003106: f44f 7180 mov.w r1, #256 @ 0x100 800310a: 480e ldr r0, [pc, #56] @ (8003144 ) 800310c: f003 fadf bl 80066ce } /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ fchiuso = false; 8003110: 4b0d ldr r3, [pc, #52] @ (8003148 ) 8003112: 2200 movs r2, #0 8003114: 701a strb r2, [r3, #0] while (1) { manageCDC(); 8003116: f7fd f971 bl 80003fc manageAdc(); 800311a: f7fd f81f bl 800015c managePulsanti(); 800311e: f7fe ff83 bl 8002028 manageCiclo(); 8003122: f7ff f8ed bl 8002300 debug(); 8003126: f7fe f845 bl 80011b4 manageCDC(); 800312a: bf00 nop 800312c: e7f3 b.n 8003116 800312e: bf00 nop 8003130: 200001fc .word 0x200001fc 8003134: 200002a4 .word 0x200002a4 8003138: 20000318 .word 0x20000318 800313c: 20000360 .word 0x20000360 8003140: 20000448 .word 0x20000448 8003144: 40010800 .word 0x40010800 8003148: 20000459 .word 0x20000459 0800314c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800314c: b580 push {r7, lr} 800314e: b094 sub sp, #80 @ 0x50 8003150: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 8003152: f107 0328 add.w r3, r7, #40 @ 0x28 8003156: 2228 movs r2, #40 @ 0x28 8003158: 2100 movs r1, #0 800315a: 4618 mov r0, r3 800315c: f00b f9c8 bl 800e4f0 RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 8003160: f107 0314 add.w r3, r7, #20 8003164: 2200 movs r2, #0 8003166: 601a str r2, [r3, #0] 8003168: 605a str r2, [r3, #4] 800316a: 609a str r2, [r3, #8] 800316c: 60da str r2, [r3, #12] 800316e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; 8003170: 1d3b adds r3, r7, #4 8003172: 2200 movs r2, #0 8003174: 601a str r2, [r3, #0] 8003176: 605a str r2, [r3, #4] 8003178: 609a str r2, [r3, #8] 800317a: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800317c: 2301 movs r3, #1 800317e: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8003180: f44f 3380 mov.w r3, #65536 @ 0x10000 8003184: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8003186: 2300 movs r3, #0 8003188: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800318a: 2301 movs r3, #1 800318c: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800318e: 2302 movs r3, #2 8003190: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8003192: f44f 3380 mov.w r3, #65536 @ 0x10000 8003196: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; 8003198: f44f 1380 mov.w r3, #1048576 @ 0x100000 800319c: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 800319e: f107 0328 add.w r3, r7, #40 @ 0x28 80031a2: 4618 mov r0, r3 80031a4: f005 f80c bl 80081c0 80031a8: 4603 mov r3, r0 80031aa: 2b00 cmp r3, #0 80031ac: d001 beq.n 80031b2 Error_Handler(); 80031ae: f000 fadb bl 8003768 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 80031b2: 230f movs r3, #15 80031b4: 617b str r3, [r7, #20] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80031b6: 2302 movs r3, #2 80031b8: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80031ba: 2300 movs r3, #0 80031bc: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80031be: f44f 6380 mov.w r3, #1024 @ 0x400 80031c2: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80031c4: 2300 movs r3, #0 80031c6: 627b str r3, [r7, #36] @ 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { 80031c8: f107 0314 add.w r3, r7, #20 80031cc: 2102 movs r1, #2 80031ce: 4618 mov r0, r3 80031d0: f005 fa78 bl 80086c4 80031d4: 4603 mov r3, r0 80031d6: 2b00 cmp r3, #0 80031d8: d001 beq.n 80031de Error_Handler(); 80031da: f000 fac5 bl 8003768 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB; 80031de: 2312 movs r3, #18 80031e0: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 80031e2: f44f 4300 mov.w r3, #32768 @ 0x8000 80031e6: 60fb str r3, [r7, #12] PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; 80031e8: 2300 movs r3, #0 80031ea: 613b str r3, [r7, #16] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { 80031ec: 1d3b adds r3, r7, #4 80031ee: 4618 mov r0, r3 80031f0: f005 fbf8 bl 80089e4 80031f4: 4603 mov r3, r0 80031f6: 2b00 cmp r3, #0 80031f8: d001 beq.n 80031fe Error_Handler(); 80031fa: f000 fab5 bl 8003768 } } 80031fe: bf00 nop 8003200: 3750 adds r7, #80 @ 0x50 8003202: 46bd mov sp, r7 8003204: bd80 pop {r7, pc} ... 08003208 : /** * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8003208: b580 push {r7, lr} 800320a: b084 sub sp, #16 800320c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = { 0 }; 800320e: 1d3b adds r3, r7, #4 8003210: 2200 movs r2, #0 8003212: 601a str r2, [r3, #0] 8003214: 605a str r2, [r3, #4] 8003216: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8003218: 4b35 ldr r3, [pc, #212] @ (80032f0 ) 800321a: 4a36 ldr r2, [pc, #216] @ (80032f4 ) 800321c: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 800321e: 4b34 ldr r3, [pc, #208] @ (80032f0 ) 8003220: f44f 7280 mov.w r2, #256 @ 0x100 8003224: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 8003226: 4b32 ldr r3, [pc, #200] @ (80032f0 ) 8003228: 2201 movs r2, #1 800322a: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 800322c: 4b30 ldr r3, [pc, #192] @ (80032f0 ) 800322e: 2200 movs r2, #0 8003230: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8003232: 4b2f ldr r3, [pc, #188] @ (80032f0 ) 8003234: f44f 2260 mov.w r2, #917504 @ 0xe0000 8003238: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800323a: 4b2d ldr r3, [pc, #180] @ (80032f0 ) 800323c: 2200 movs r2, #0 800323e: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 5; 8003240: 4b2b ldr r3, [pc, #172] @ (80032f0 ) 8003242: 2205 movs r2, #5 8003244: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) { 8003246: 482a ldr r0, [pc, #168] @ (80032f0 ) 8003248: f001 ffd8 bl 80051fc 800324c: 4603 mov r3, r0 800324e: 2b00 cmp r3, #0 8003250: d001 beq.n 8003256 Error_Handler(); 8003252: f000 fa89 bl 8003768 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8003256: 2304 movs r3, #4 8003258: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 800325a: 2301 movs r3, #1 800325c: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_28CYCLES_5; 800325e: 2303 movs r3, #3 8003260: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8003262: 1d3b adds r3, r7, #4 8003264: 4619 mov r1, r3 8003266: 4822 ldr r0, [pc, #136] @ (80032f0 ) 8003268: f002 f99a bl 80055a0 800326c: 4603 mov r3, r0 800326e: 2b00 cmp r3, #0 8003270: d001 beq.n 8003276 Error_Handler(); 8003272: f000 fa79 bl 8003768 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8003276: 2305 movs r3, #5 8003278: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800327a: 2302 movs r3, #2 800327c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 800327e: 1d3b adds r3, r7, #4 8003280: 4619 mov r1, r3 8003282: 481b ldr r0, [pc, #108] @ (80032f0 ) 8003284: f002 f98c bl 80055a0 8003288: 4603 mov r3, r0 800328a: 2b00 cmp r3, #0 800328c: d001 beq.n 8003292 Error_Handler(); 800328e: f000 fa6b bl 8003768 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_6; 8003292: 2306 movs r3, #6 8003294: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8003296: 2303 movs r3, #3 8003298: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 800329a: 1d3b adds r3, r7, #4 800329c: 4619 mov r1, r3 800329e: 4814 ldr r0, [pc, #80] @ (80032f0 ) 80032a0: f002 f97e bl 80055a0 80032a4: 4603 mov r3, r0 80032a6: 2b00 cmp r3, #0 80032a8: d001 beq.n 80032ae Error_Handler(); 80032aa: f000 fa5d bl 8003768 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 80032ae: 2307 movs r3, #7 80032b0: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 80032b2: 2304 movs r3, #4 80032b4: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 80032b6: 1d3b adds r3, r7, #4 80032b8: 4619 mov r1, r3 80032ba: 480d ldr r0, [pc, #52] @ (80032f0 ) 80032bc: f002 f970 bl 80055a0 80032c0: 4603 mov r3, r0 80032c2: 2b00 cmp r3, #0 80032c4: d001 beq.n 80032ca Error_Handler(); 80032c6: f000 fa4f bl 8003768 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 80032ca: 2308 movs r3, #8 80032cc: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 80032ce: 2305 movs r3, #5 80032d0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 80032d2: 1d3b adds r3, r7, #4 80032d4: 4619 mov r1, r3 80032d6: 4806 ldr r0, [pc, #24] @ (80032f0 ) 80032d8: f002 f962 bl 80055a0 80032dc: 4603 mov r3, r0 80032de: 2b00 cmp r3, #0 80032e0: d001 beq.n 80032e6 Error_Handler(); 80032e2: f000 fa41 bl 8003768 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80032e6: bf00 nop 80032e8: 3710 adds r7, #16 80032ea: 46bd mov sp, r7 80032ec: bd80 pop {r7, pc} 80032ee: bf00 nop 80032f0: 200002a4 .word 0x200002a4 80032f4: 40012400 .word 0x40012400 080032f8 : /** * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80032f8: b580 push {r7, lr} 80032fa: b08e sub sp, #56 @ 0x38 80032fc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; 80032fe: f107 0328 add.w r3, r7, #40 @ 0x28 8003302: 2200 movs r2, #0 8003304: 601a str r2, [r3, #0] 8003306: 605a str r2, [r3, #4] 8003308: 609a str r2, [r3, #8] 800330a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = { 0 }; 800330c: f107 0320 add.w r3, r7, #32 8003310: 2200 movs r2, #0 8003312: 601a str r2, [r3, #0] 8003314: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = { 0 }; 8003316: 1d3b adds r3, r7, #4 8003318: 2200 movs r2, #0 800331a: 601a str r2, [r3, #0] 800331c: 605a str r2, [r3, #4] 800331e: 609a str r2, [r3, #8] 8003320: 60da str r2, [r3, #12] 8003322: 611a str r2, [r3, #16] 8003324: 615a str r2, [r3, #20] 8003326: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8003328: 4b44 ldr r3, [pc, #272] @ (800343c ) 800332a: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 800332e: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8003330: 4b42 ldr r3, [pc, #264] @ (800343c ) 8003332: 2200 movs r2, #0 8003334: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8003336: 4b41 ldr r3, [pc, #260] @ (800343c ) 8003338: 2200 movs r2, #0 800333a: 609a str r2, [r3, #8] htim2.Init.Period = 17999; 800333c: 4b3f ldr r3, [pc, #252] @ (800343c ) 800333e: f244 624f movw r2, #17999 @ 0x464f 8003342: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8003344: 4b3d ldr r3, [pc, #244] @ (800343c ) 8003346: 2200 movs r2, #0 8003348: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800334a: 4b3c ldr r3, [pc, #240] @ (800343c ) 800334c: 2200 movs r2, #0 800334e: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) { 8003350: 483a ldr r0, [pc, #232] @ (800343c ) 8003352: f005 fbfd bl 8008b50 8003356: 4603 mov r3, r0 8003358: 2b00 cmp r3, #0 800335a: d001 beq.n 8003360 Error_Handler(); 800335c: f000 fa04 bl 8003768 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8003360: f44f 5380 mov.w r3, #4096 @ 0x1000 8003364: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) { 8003366: f107 0328 add.w r3, r7, #40 @ 0x28 800336a: 4619 mov r1, r3 800336c: 4833 ldr r0, [pc, #204] @ (800343c ) 800336e: f005 fe5f bl 8009030 8003372: 4603 mov r3, r0 8003374: 2b00 cmp r3, #0 8003376: d001 beq.n 800337c Error_Handler(); 8003378: f000 f9f6 bl 8003768 } if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) { 800337c: 482f ldr r0, [pc, #188] @ (800343c ) 800337e: f005 fc36 bl 8008bee 8003382: 4603 mov r3, r0 8003384: 2b00 cmp r3, #0 8003386: d001 beq.n 800338c Error_Handler(); 8003388: f000 f9ee bl 8003768 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800338c: 2300 movs r3, #0 800338e: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8003390: 2300 movs r3, #0 8003392: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) 8003394: f107 0320 add.w r3, r7, #32 8003398: 4619 mov r1, r3 800339a: 4828 ldr r0, [pc, #160] @ (800343c ) 800339c: f006 f9e8 bl 8009770 80033a0: 4603 mov r3, r0 80033a2: 2b00 cmp r3, #0 80033a4: d001 beq.n 80033aa != HAL_OK) { Error_Handler(); 80033a6: f000 f9df bl 8003768 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 80033aa: 2360 movs r3, #96 @ 0x60 80033ac: 607b str r3, [r7, #4] sConfigOC.Pulse = 1000; 80033ae: f44f 737a mov.w r3, #1000 @ 0x3e8 80033b2: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80033b4: 2300 movs r3, #0 80033b6: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 80033b8: 2304 movs r3, #4 80033ba: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) 80033bc: 1d3b adds r3, r7, #4 80033be: 2200 movs r2, #0 80033c0: 4619 mov r1, r3 80033c2: 481e ldr r0, [pc, #120] @ (800343c ) 80033c4: f005 fd72 bl 8008eac 80033c8: 4603 mov r3, r0 80033ca: 2b00 cmp r3, #0 80033cc: d001 beq.n 80033d2 != HAL_OK) { Error_Handler(); 80033ce: f000 f9cb bl 8003768 } sConfigOC.Pulse = 2000; 80033d2: f44f 63fa mov.w r3, #2000 @ 0x7d0 80033d6: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) 80033d8: 1d3b adds r3, r7, #4 80033da: 2204 movs r2, #4 80033dc: 4619 mov r1, r3 80033de: 4817 ldr r0, [pc, #92] @ (800343c ) 80033e0: f005 fd64 bl 8008eac 80033e4: 4603 mov r3, r0 80033e6: 2b00 cmp r3, #0 80033e8: d001 beq.n 80033ee != HAL_OK) { Error_Handler(); 80033ea: f000 f9bd bl 8003768 } sConfigOC.Pulse = 3000; 80033ee: f640 33b8 movw r3, #3000 @ 0xbb8 80033f2: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80033f4: 2300 movs r3, #0 80033f6: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) 80033f8: 1d3b adds r3, r7, #4 80033fa: 2208 movs r2, #8 80033fc: 4619 mov r1, r3 80033fe: 480f ldr r0, [pc, #60] @ (800343c ) 8003400: f005 fd54 bl 8008eac 8003404: 4603 mov r3, r0 8003406: 2b00 cmp r3, #0 8003408: d001 beq.n 800340e != HAL_OK) { Error_Handler(); 800340a: f000 f9ad bl 8003768 } sConfigOC.Pulse = 4000; 800340e: f44f 637a mov.w r3, #4000 @ 0xfa0 8003412: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 8003414: 2304 movs r3, #4 8003416: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) 8003418: 1d3b adds r3, r7, #4 800341a: 220c movs r2, #12 800341c: 4619 mov r1, r3 800341e: 4807 ldr r0, [pc, #28] @ (800343c ) 8003420: f005 fd44 bl 8008eac 8003424: 4603 mov r3, r0 8003426: 2b00 cmp r3, #0 8003428: d001 beq.n 800342e != HAL_OK) { Error_Handler(); 800342a: f000 f99d bl 8003768 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 800342e: 4803 ldr r0, [pc, #12] @ (800343c ) 8003430: f001 fd3e bl 8004eb0 } 8003434: bf00 nop 8003436: 3738 adds r7, #56 @ 0x38 8003438: 46bd mov sp, r7 800343a: bd80 pop {r7, pc} 800343c: 20000318 .word 0x20000318 08003440 : /** * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8003440: b580 push {r7, lr} 8003442: b08e sub sp, #56 @ 0x38 8003444: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; 8003446: f107 0328 add.w r3, r7, #40 @ 0x28 800344a: 2200 movs r2, #0 800344c: 601a str r2, [r3, #0] 800344e: 605a str r2, [r3, #4] 8003450: 609a str r2, [r3, #8] 8003452: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = { 0 }; 8003454: f107 0320 add.w r3, r7, #32 8003458: 2200 movs r2, #0 800345a: 601a str r2, [r3, #0] 800345c: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = { 0 }; 800345e: 1d3b adds r3, r7, #4 8003460: 2200 movs r2, #0 8003462: 601a str r2, [r3, #0] 8003464: 605a str r2, [r3, #4] 8003466: 609a str r2, [r3, #8] 8003468: 60da str r2, [r3, #12] 800346a: 611a str r2, [r3, #16] 800346c: 615a str r2, [r3, #20] 800346e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8003470: 4b42 ldr r3, [pc, #264] @ (800357c ) 8003472: 4a43 ldr r2, [pc, #268] @ (8003580 ) 8003474: 601a str r2, [r3, #0] htim4.Init.Prescaler = 0; 8003476: 4b41 ldr r3, [pc, #260] @ (800357c ) 8003478: 2200 movs r2, #0 800347a: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800347c: 4b3f ldr r3, [pc, #252] @ (800357c ) 800347e: 2200 movs r2, #0 8003480: 609a str r2, [r3, #8] htim4.Init.Period = 17999; 8003482: 4b3e ldr r3, [pc, #248] @ (800357c ) 8003484: f244 624f movw r2, #17999 @ 0x464f 8003488: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800348a: 4b3c ldr r3, [pc, #240] @ (800357c ) 800348c: 2200 movs r2, #0 800348e: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8003490: 4b3a ldr r3, [pc, #232] @ (800357c ) 8003492: 2200 movs r2, #0 8003494: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) { 8003496: 4839 ldr r0, [pc, #228] @ (800357c ) 8003498: f005 fb5a bl 8008b50 800349c: 4603 mov r3, r0 800349e: 2b00 cmp r3, #0 80034a0: d001 beq.n 80034a6 Error_Handler(); 80034a2: f000 f961 bl 8003768 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80034a6: f44f 5380 mov.w r3, #4096 @ 0x1000 80034aa: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) { 80034ac: f107 0328 add.w r3, r7, #40 @ 0x28 80034b0: 4619 mov r1, r3 80034b2: 4832 ldr r0, [pc, #200] @ (800357c ) 80034b4: f005 fdbc bl 8009030 80034b8: 4603 mov r3, r0 80034ba: 2b00 cmp r3, #0 80034bc: d001 beq.n 80034c2 Error_Handler(); 80034be: f000 f953 bl 8003768 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { 80034c2: 482e ldr r0, [pc, #184] @ (800357c ) 80034c4: f005 fb93 bl 8008bee 80034c8: 4603 mov r3, r0 80034ca: 2b00 cmp r3, #0 80034cc: d001 beq.n 80034d2 Error_Handler(); 80034ce: f000 f94b bl 8003768 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80034d2: 2300 movs r3, #0 80034d4: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80034d6: 2300 movs r3, #0 80034d8: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) 80034da: f107 0320 add.w r3, r7, #32 80034de: 4619 mov r1, r3 80034e0: 4826 ldr r0, [pc, #152] @ (800357c ) 80034e2: f006 f945 bl 8009770 80034e6: 4603 mov r3, r0 80034e8: 2b00 cmp r3, #0 80034ea: d001 beq.n 80034f0 != HAL_OK) { Error_Handler(); 80034ec: f000 f93c bl 8003768 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 80034f0: 2360 movs r3, #96 @ 0x60 80034f2: 607b str r3, [r7, #4] sConfigOC.Pulse = 5000; 80034f4: f241 3388 movw r3, #5000 @ 0x1388 80034f8: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80034fa: 2300 movs r3, #0 80034fc: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 80034fe: 2304 movs r3, #4 8003500: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) 8003502: 1d3b adds r3, r7, #4 8003504: 2200 movs r2, #0 8003506: 4619 mov r1, r3 8003508: 481c ldr r0, [pc, #112] @ (800357c ) 800350a: f005 fccf bl 8008eac 800350e: 4603 mov r3, r0 8003510: 2b00 cmp r3, #0 8003512: d001 beq.n 8003518 != HAL_OK) { Error_Handler(); 8003514: f000 f928 bl 8003768 } sConfigOC.Pulse = 6000; 8003518: f241 7370 movw r3, #6000 @ 0x1770 800351c: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) 800351e: 1d3b adds r3, r7, #4 8003520: 2204 movs r2, #4 8003522: 4619 mov r1, r3 8003524: 4815 ldr r0, [pc, #84] @ (800357c ) 8003526: f005 fcc1 bl 8008eac 800352a: 4603 mov r3, r0 800352c: 2b00 cmp r3, #0 800352e: d001 beq.n 8003534 != HAL_OK) { Error_Handler(); 8003530: f000 f91a bl 8003768 } sConfigOC.Pulse = 7000; 8003534: f641 3358 movw r3, #7000 @ 0x1b58 8003538: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) 800353a: 1d3b adds r3, r7, #4 800353c: 2208 movs r2, #8 800353e: 4619 mov r1, r3 8003540: 480e ldr r0, [pc, #56] @ (800357c ) 8003542: f005 fcb3 bl 8008eac 8003546: 4603 mov r3, r0 8003548: 2b00 cmp r3, #0 800354a: d001 beq.n 8003550 != HAL_OK) { Error_Handler(); 800354c: f000 f90c bl 8003768 } sConfigOC.Pulse = 8000; 8003550: f44f 53fa mov.w r3, #8000 @ 0x1f40 8003554: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) 8003556: 1d3b adds r3, r7, #4 8003558: 220c movs r2, #12 800355a: 4619 mov r1, r3 800355c: 4807 ldr r0, [pc, #28] @ (800357c ) 800355e: f005 fca5 bl 8008eac 8003562: 4603 mov r3, r0 8003564: 2b00 cmp r3, #0 8003566: d001 beq.n 800356c != HAL_OK) { Error_Handler(); 8003568: f000 f8fe bl 8003768 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800356c: 4803 ldr r0, [pc, #12] @ (800357c ) 800356e: f001 fc9f bl 8004eb0 } 8003572: bf00 nop 8003574: 3738 adds r7, #56 @ 0x38 8003576: 46bd mov sp, r7 8003578: bd80 pop {r7, pc} 800357a: bf00 nop 800357c: 20000360 .word 0x20000360 8003580: 40000800 .word 0x40000800 08003584 : /** * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8003584: b580 push {r7, lr} 8003586: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8003588: 4b11 ldr r3, [pc, #68] @ (80035d0 ) 800358a: 4a12 ldr r2, [pc, #72] @ (80035d4 ) 800358c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800358e: 4b10 ldr r3, [pc, #64] @ (80035d0 ) 8003590: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8003594: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8003596: 4b0e ldr r3, [pc, #56] @ (80035d0 ) 8003598: 2200 movs r2, #0 800359a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800359c: 4b0c ldr r3, [pc, #48] @ (80035d0 ) 800359e: 2200 movs r2, #0 80035a0: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80035a2: 4b0b ldr r3, [pc, #44] @ (80035d0 ) 80035a4: 2200 movs r2, #0 80035a6: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80035a8: 4b09 ldr r3, [pc, #36] @ (80035d0 ) 80035aa: 220c movs r2, #12 80035ac: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80035ae: 4b08 ldr r3, [pc, #32] @ (80035d0 ) 80035b0: 2200 movs r2, #0 80035b2: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80035b4: 4b06 ldr r3, [pc, #24] @ (80035d0 ) 80035b6: 2200 movs r2, #0 80035b8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) { 80035ba: 4805 ldr r0, [pc, #20] @ (80035d0 ) 80035bc: f006 f936 bl 800982c 80035c0: 4603 mov r3, r0 80035c2: 2b00 cmp r3, #0 80035c4: d001 beq.n 80035ca Error_Handler(); 80035c6: f000 f8cf bl 8003768 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80035ca: bf00 nop 80035cc: bd80 pop {r7, pc} 80035ce: bf00 nop 80035d0: 200003a8 .word 0x200003a8 80035d4: 40013800 .word 0x40013800 080035d8 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80035d8: b580 push {r7, lr} 80035da: b082 sub sp, #8 80035dc: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80035de: 4b0c ldr r3, [pc, #48] @ (8003610 ) 80035e0: 695b ldr r3, [r3, #20] 80035e2: 4a0b ldr r2, [pc, #44] @ (8003610 ) 80035e4: f043 0301 orr.w r3, r3, #1 80035e8: 6153 str r3, [r2, #20] 80035ea: 4b09 ldr r3, [pc, #36] @ (8003610 ) 80035ec: 695b ldr r3, [r3, #20] 80035ee: f003 0301 and.w r3, r3, #1 80035f2: 607b str r3, [r7, #4] 80035f4: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 80035f6: 2200 movs r2, #0 80035f8: 2100 movs r1, #0 80035fa: 200b movs r0, #11 80035fc: f002 faa1 bl 8005b42 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8003600: 200b movs r0, #11 8003602: f002 faba bl 8005b7a } 8003606: bf00 nop 8003608: 3708 adds r7, #8 800360a: 46bd mov sp, r7 800360c: bd80 pop {r7, pc} 800360e: bf00 nop 8003610: 40021000 .word 0x40021000 08003614 : /** * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8003614: b580 push {r7, lr} 8003616: b088 sub sp, #32 8003618: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 800361a: f107 0310 add.w r3, r7, #16 800361e: 2200 movs r2, #0 8003620: 601a str r2, [r3, #0] 8003622: 605a str r2, [r3, #4] 8003624: 609a str r2, [r3, #8] 8003626: 60da str r2, [r3, #12] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8003628: 4b4b ldr r3, [pc, #300] @ (8003758 ) 800362a: 699b ldr r3, [r3, #24] 800362c: 4a4a ldr r2, [pc, #296] @ (8003758 ) 800362e: f043 0310 orr.w r3, r3, #16 8003632: 6193 str r3, [r2, #24] 8003634: 4b48 ldr r3, [pc, #288] @ (8003758 ) 8003636: 699b ldr r3, [r3, #24] 8003638: f003 0310 and.w r3, r3, #16 800363c: 60fb str r3, [r7, #12] 800363e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8003640: 4b45 ldr r3, [pc, #276] @ (8003758 ) 8003642: 699b ldr r3, [r3, #24] 8003644: 4a44 ldr r2, [pc, #272] @ (8003758 ) 8003646: f043 0320 orr.w r3, r3, #32 800364a: 6193 str r3, [r2, #24] 800364c: 4b42 ldr r3, [pc, #264] @ (8003758 ) 800364e: 699b ldr r3, [r3, #24] 8003650: f003 0320 and.w r3, r3, #32 8003654: 60bb str r3, [r7, #8] 8003656: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003658: 4b3f ldr r3, [pc, #252] @ (8003758 ) 800365a: 699b ldr r3, [r3, #24] 800365c: 4a3e ldr r2, [pc, #248] @ (8003758 ) 800365e: f043 0304 orr.w r3, r3, #4 8003662: 6193 str r3, [r2, #24] 8003664: 4b3c ldr r3, [pc, #240] @ (8003758 ) 8003666: 699b ldr r3, [r3, #24] 8003668: f003 0304 and.w r3, r3, #4 800366c: 607b str r3, [r7, #4] 800366e: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003670: 4b39 ldr r3, [pc, #228] @ (8003758 ) 8003672: 699b ldr r3, [r3, #24] 8003674: 4a38 ldr r2, [pc, #224] @ (8003758 ) 8003676: f043 0308 orr.w r3, r3, #8 800367a: 6193 str r3, [r2, #24] 800367c: 4b36 ldr r3, [pc, #216] @ (8003758 ) 800367e: 699b ldr r3, [r3, #24] 8003680: f003 0308 and.w r3, r3, #8 8003684: 603b str r3, [r7, #0] 8003686: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 8003688: 2200 movs r2, #0 800368a: f44f 5100 mov.w r1, #8192 @ 0x2000 800368e: 4833 ldr r0, [pc, #204] @ (800375c ) 8003690: f003 f81d bl 80066ce /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, 8003694: 2200 movs r2, #0 8003696: f640 413e movw r1, #3134 @ 0xc3e 800369a: 4831 ldr r0, [pc, #196] @ (8003760 ) 800369c: f003 f817 bl 80066ce INH1_Pin | INH2_Pin | INH3_Pin | INH4_Pin | EXP1_Pin | EXP2_Pin | EXP3_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, BUZ_Pin | LED1_Pin, GPIO_PIN_RESET); 80036a0: 2200 movs r2, #0 80036a2: f44f 4101 mov.w r1, #33024 @ 0x8100 80036a6: 482f ldr r0, [pc, #188] @ (8003764 ) 80036a8: f003 f811 bl 80066ce /*Configure GPIO pin : LED2_Pin */ GPIO_InitStruct.Pin = LED2_Pin; 80036ac: f44f 5300 mov.w r3, #8192 @ 0x2000 80036b0: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80036b2: 2301 movs r3, #1 80036b4: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80036b6: 2300 movs r3, #0 80036b8: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80036ba: 2302 movs r3, #2 80036bc: 61fb str r3, [r7, #28] HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct); 80036be: f107 0310 add.w r3, r7, #16 80036c2: 4619 mov r1, r3 80036c4: 4825 ldr r0, [pc, #148] @ (800375c ) 80036c6: f002 fe67 bl 8006398 /*Configure GPIO pins : P1_Pin P2_Pin */ GPIO_InitStruct.Pin = P1_Pin | P2_Pin; 80036ca: f44f 4340 mov.w r3, #49152 @ 0xc000 80036ce: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80036d0: 2300 movs r3, #0 80036d2: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80036d4: 2300 movs r3, #0 80036d6: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80036d8: f107 0310 add.w r3, r7, #16 80036dc: 4619 mov r1, r3 80036de: 481f ldr r0, [pc, #124] @ (800375c ) 80036e0: f002 fe5a bl 8006398 /*Configure GPIO pin : AIN1_Pin */ GPIO_InitStruct.Pin = AIN1_Pin; 80036e4: 2310 movs r3, #16 80036e6: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80036e8: 2303 movs r3, #3 80036ea: 617b str r3, [r7, #20] HAL_GPIO_Init(AIN1_GPIO_Port, &GPIO_InitStruct); 80036ec: f107 0310 add.w r3, r7, #16 80036f0: 4619 mov r1, r3 80036f2: 481c ldr r0, [pc, #112] @ (8003764 ) 80036f4: f002 fe50 bl 8006398 /*Configure GPIO pins : INH1_Pin INH2_Pin INH3_Pin INH4_Pin EXP1_Pin EXP2_Pin EXP3_Pin */ GPIO_InitStruct.Pin = INH1_Pin | INH2_Pin | INH3_Pin | INH4_Pin | EXP1_Pin 80036f8: f640 433e movw r3, #3134 @ 0xc3e 80036fc: 613b str r3, [r7, #16] | EXP2_Pin | EXP3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80036fe: 2301 movs r3, #1 8003700: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003702: 2300 movs r3, #0 8003704: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003706: 2302 movs r3, #2 8003708: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800370a: f107 0310 add.w r3, r7, #16 800370e: 4619 mov r1, r3 8003710: 4813 ldr r0, [pc, #76] @ (8003760 ) 8003712: f002 fe41 bl 8006398 /*Configure GPIO pins : CH1_Pin CH2_Pin CH3_Pin CH4_Pin */ GPIO_InitStruct.Pin = CH1_Pin | CH2_Pin | CH3_Pin | CH4_Pin; 8003716: f44f 4370 mov.w r3, #61440 @ 0xf000 800371a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800371c: 2300 movs r3, #0 800371e: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003720: 2300 movs r3, #0 8003722: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003724: f107 0310 add.w r3, r7, #16 8003728: 4619 mov r1, r3 800372a: 480d ldr r0, [pc, #52] @ (8003760 ) 800372c: f002 fe34 bl 8006398 /*Configure GPIO pins : BUZ_Pin LED1_Pin */ GPIO_InitStruct.Pin = BUZ_Pin | LED1_Pin; 8003730: f44f 4301 mov.w r3, #33024 @ 0x8100 8003734: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8003736: 2301 movs r3, #1 8003738: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800373a: 2300 movs r3, #0 800373c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800373e: 2302 movs r3, #2 8003740: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003742: f107 0310 add.w r3, r7, #16 8003746: 4619 mov r1, r3 8003748: 4806 ldr r0, [pc, #24] @ (8003764 ) 800374a: f002 fe25 bl 8006398 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 800374e: bf00 nop 8003750: 3720 adds r7, #32 8003752: 46bd mov sp, r7 8003754: bd80 pop {r7, pc} 8003756: bf00 nop 8003758: 40021000 .word 0x40021000 800375c: 40011000 .word 0x40011000 8003760: 40010c00 .word 0x40010c00 8003764: 40010800 .word 0x40010800 08003768 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8003768: b480 push {r7} 800376a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800376c: b672 cpsid i } 800376e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 8003770: bf00 nop 8003772: e7fd b.n 8003770 08003774 : extern uint16_t mrampstart[4]; extern uint16_t tramp; extern UART_HandleTypeDef huart1; motMov_st m1ap(void){ 8003774: b580 push {r7, lr} 8003776: b09c sub sp, #112 @ 0x70 8003778: af02 add r7, sp, #8 static motMov_st m1st=motWaiting; static motMov_st memm1st=motStop; char s[100]; if(memm1st!=m1st){ 800377a: 4b5d ldr r3, [pc, #372] @ (80038f0 ) 800377c: 781a ldrb r2, [r3, #0] 800377e: 4b5d ldr r3, [pc, #372] @ (80038f4 ) 8003780: 781b ldrb r3, [r3, #0] 8003782: 429a cmp r2, r3 8003784: d017 beq.n 80037b6 memm1st=m1st; 8003786: 4b5b ldr r3, [pc, #364] @ (80038f4 ) 8003788: 781a ldrb r2, [r3, #0] 800378a: 4b59 ldr r3, [pc, #356] @ (80038f0 ) 800378c: 701a strb r2, [r3, #0] sprintf(s,"\nm1ap=%d",m1st); 800378e: 4b59 ldr r3, [pc, #356] @ (80038f4 ) 8003790: 781b ldrb r3, [r3, #0] 8003792: 461a mov r2, r3 8003794: 1d3b adds r3, r7, #4 8003796: 4958 ldr r1, [pc, #352] @ (80038f8 ) 8003798: 4618 mov r0, r3 800379a: f00a fe87 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 800379e: 1d3b adds r3, r7, #4 80037a0: 4618 mov r0, r3 80037a2: f7fc fcd3 bl 800014c 80037a6: 4603 mov r3, r0 80037a8: b29a uxth r2, r3 80037aa: 1d39 adds r1, r7, #4 80037ac: f04f 33ff mov.w r3, #4294967295 80037b0: 4852 ldr r0, [pc, #328] @ (80038fc ) 80037b2: f006 f88b bl 80098cc } if(rtCiclo) 80037b8: 881b ldrh r3, [r3, #0] 80037ba: b29a uxth r2, r3 80037bc: 4b51 ldr r3, [pc, #324] @ (8003904 ) 80037be: 881b ldrh r3, [r3, #0] 80037c0: 429a cmp r2, r3 80037c2: d202 bcs.n 80037ca 80037c4: 4b4b ldr r3, [pc, #300] @ (80038f4 ) 80037c6: 2200 movs r2, #0 80037c8: 701a strb r2, [r3, #0] switch(m1st){ 80037ca: 4b4a ldr r3, [pc, #296] @ (80038f4 ) 80037cc: 781b ldrb r3, [r3, #0] 80037ce: 2b03 cmp r3, #3 80037d0: d876 bhi.n 80038c0 80037d2: a201 add r2, pc, #4 @ (adr r2, 80037d8 ) 80037d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80037d8: 080037e9 .word 0x080037e9 80037dc: 08003835 .word 0x08003835 80037e0: 08003865 .word 0x08003865 80037e4: 08003897 .word 0x08003897 case motWaiting: SetMotPerc(M1,FW,0); 80037e8: 2200 movs r2, #0 80037ea: 2100 movs r1, #0 80037ec: 2001 movs r0, #1 80037ee: f001 f83f bl 8004870 SetMotPerc(M1,BW,0); 80037f2: 2200 movs r2, #0 80037f4: 2101 movs r1, #1 80037f6: 2001 movs r0, #1 80037f8: f001 f83a bl 8004870 if(rtCiclo>=apM1start){ 80037fc: 4b40 ldr r3, [pc, #256] @ (8003900 ) 80037fe: 881b ldrh r3, [r3, #0] 8003800: b29a uxth r2, r3 8003802: 4b40 ldr r3, [pc, #256] @ (8003904 ) 8003804: 881b ldrh r3, [r3, #0] 8003806: 429a cmp r2, r3 8003808: d365 bcc.n 80038d6 (void)ramp(M1,FW,mrampstart[M1-1],m1pwmap,tramp,RAMPINIT); 800380a: 4b3f ldr r3, [pc, #252] @ (8003908 ) 800380c: 881b ldrh r3, [r3, #0] 800380e: b2da uxtb r2, r3 8003810: 4b3e ldr r3, [pc, #248] @ (800390c ) 8003812: 881b ldrh r3, [r3, #0] 8003814: b2d9 uxtb r1, r3 8003816: 4b3e ldr r3, [pc, #248] @ (8003910 ) 8003818: 881b ldrh r3, [r3, #0] 800381a: b2db uxtb r3, r3 800381c: 2000 movs r0, #0 800381e: 9001 str r0, [sp, #4] 8003820: 9300 str r3, [sp, #0] 8003822: 460b mov r3, r1 8003824: 2100 movs r1, #0 8003826: 2001 movs r0, #1 8003828: f001 f9a2 bl 8004b70 m1st=motStartRamp; 800382c: 4b31 ldr r3, [pc, #196] @ (80038f4 ) 800382e: 2201 movs r2, #1 8003830: 701a strb r2, [r3, #0] } break; 8003832: e050 b.n 80038d6 case motStartRamp: if(ramp(M1,FW,mrampstart[M1-1],m1pwmap,tramp,RAMPRUN)==DONE){ 8003834: 4b34 ldr r3, [pc, #208] @ (8003908 ) 8003836: 881b ldrh r3, [r3, #0] 8003838: b2da uxtb r2, r3 800383a: 4b34 ldr r3, [pc, #208] @ (800390c ) 800383c: 881b ldrh r3, [r3, #0] 800383e: b2d9 uxtb r1, r3 8003840: 4b33 ldr r3, [pc, #204] @ (8003910 ) 8003842: 881b ldrh r3, [r3, #0] 8003844: b2db uxtb r3, r3 8003846: 200a movs r0, #10 8003848: 9001 str r0, [sp, #4] 800384a: 9300 str r3, [sp, #0] 800384c: 460b mov r3, r1 800384e: 2100 movs r1, #0 8003850: 2001 movs r0, #1 8003852: f001 f98d bl 8004b70 8003856: 4603 mov r3, r0 8003858: 2b00 cmp r3, #0 800385a: d13e bne.n 80038da m1st=motWaitingTime; 800385c: 4b25 ldr r3, [pc, #148] @ (80038f4 ) 800385e: 2202 movs r2, #2 8003860: 701a strb r2, [r3, #0] } break; 8003862: e03a b.n 80038da case motWaitingTime: if(rtCiclo>=apM1stop){ 8003864: 4b26 ldr r3, [pc, #152] @ (8003900 ) 8003866: 881b ldrh r3, [r3, #0] 8003868: b29a uxth r2, r3 800386a: 4b2a ldr r3, [pc, #168] @ (8003914 ) 800386c: 881b ldrh r3, [r3, #0] 800386e: 429a cmp r2, r3 8003870: d335 bcc.n 80038de (void)ramp(M1,FW,m1pwmap,0,tramp,RAMPINIT); 8003872: 4b26 ldr r3, [pc, #152] @ (800390c ) 8003874: 881b ldrh r3, [r3, #0] 8003876: b2da uxtb r2, r3 8003878: 4b25 ldr r3, [pc, #148] @ (8003910 ) 800387a: 881b ldrh r3, [r3, #0] 800387c: b2db uxtb r3, r3 800387e: 2100 movs r1, #0 8003880: 9101 str r1, [sp, #4] 8003882: 9300 str r3, [sp, #0] 8003884: 2300 movs r3, #0 8003886: 2100 movs r1, #0 8003888: 2001 movs r0, #1 800388a: f001 f971 bl 8004b70 m1st=motStopRamp; 800388e: 4b19 ldr r3, [pc, #100] @ (80038f4 ) 8003890: 2203 movs r2, #3 8003892: 701a strb r2, [r3, #0] } break; 8003894: e023 b.n 80038de case motStopRamp: if(ramp(M1,FW,m1pwmap,0,tramp,RAMPRUN)==DONE){ 8003896: 4b1d ldr r3, [pc, #116] @ (800390c ) 8003898: 881b ldrh r3, [r3, #0] 800389a: b2da uxtb r2, r3 800389c: 4b1c ldr r3, [pc, #112] @ (8003910 ) 800389e: 881b ldrh r3, [r3, #0] 80038a0: b2db uxtb r3, r3 80038a2: 210a movs r1, #10 80038a4: 9101 str r1, [sp, #4] 80038a6: 9300 str r3, [sp, #0] 80038a8: 2300 movs r3, #0 80038aa: 2100 movs r1, #0 80038ac: 2001 movs r0, #1 80038ae: f001 f95f bl 8004b70 80038b2: 4603 mov r3, r0 80038b4: 2b00 cmp r3, #0 80038b6: d114 bne.n 80038e2 m1st=motStop; 80038b8: 4b0e ldr r3, [pc, #56] @ (80038f4 ) 80038ba: 2204 movs r2, #4 80038bc: 701a strb r2, [r3, #0] } break; 80038be: e010 b.n 80038e2 case motStop: default: SetMotPerc(M1,FW,0); 80038c0: 2200 movs r2, #0 80038c2: 2100 movs r1, #0 80038c4: 2001 movs r0, #1 80038c6: f000 ffd3 bl 8004870 SetMotPerc(M1,BW,0); 80038ca: 2200 movs r2, #0 80038cc: 2101 movs r1, #1 80038ce: 2001 movs r0, #1 80038d0: f000 ffce bl 8004870 break; 80038d4: e006 b.n 80038e4 break; 80038d6: bf00 nop 80038d8: e004 b.n 80038e4 break; 80038da: bf00 nop 80038dc: e002 b.n 80038e4 break; 80038de: bf00 nop 80038e0: e000 b.n 80038e4 break; 80038e2: bf00 nop } return m1st; 80038e4: 4b03 ldr r3, [pc, #12] @ (80038f4 ) 80038e6: 781b ldrb r3, [r3, #0] } 80038e8: 4618 mov r0, r3 80038ea: 3768 adds r7, #104 @ 0x68 80038ec: 46bd mov sp, r7 80038ee: bd80 pop {r7, pc} 80038f0: 20000007 .word 0x20000007 80038f4: 20000462 .word 0x20000462 80038f8: 0800f408 .word 0x0800f408 80038fc: 200003a8 .word 0x200003a8 8003900: 200003fc .word 0x200003fc 8003904: 20000428 .word 0x20000428 8003908: 2000044c .word 0x2000044c 800390c: 20000400 .word 0x20000400 8003910: 20000418 .word 0x20000418 8003914: 2000042a .word 0x2000042a 08003918 : motMov_st m2ap(void){ 8003918: b580 push {r7, lr} 800391a: b09c sub sp, #112 @ 0x70 800391c: af02 add r7, sp, #8 static motMov_st m2st; static motMov_st memm2st=motStop; char s[100]; if(memm2st!=m2st){ 800391e: 4b5d ldr r3, [pc, #372] @ (8003a94 ) 8003920: 781a ldrb r2, [r3, #0] 8003922: 4b5d ldr r3, [pc, #372] @ (8003a98 ) 8003924: 781b ldrb r3, [r3, #0] 8003926: 429a cmp r2, r3 8003928: d017 beq.n 800395a memm2st=m2st; 800392a: 4b5b ldr r3, [pc, #364] @ (8003a98 ) 800392c: 781a ldrb r2, [r3, #0] 800392e: 4b59 ldr r3, [pc, #356] @ (8003a94 ) 8003930: 701a strb r2, [r3, #0] sprintf(s,"\nm2ap=%d",m2st); 8003932: 4b59 ldr r3, [pc, #356] @ (8003a98 ) 8003934: 781b ldrb r3, [r3, #0] 8003936: 461a mov r2, r3 8003938: 1d3b adds r3, r7, #4 800393a: 4958 ldr r1, [pc, #352] @ (8003a9c ) 800393c: 4618 mov r0, r3 800393e: f00a fdb5 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8003942: 1d3b adds r3, r7, #4 8003944: 4618 mov r0, r3 8003946: f7fc fc01 bl 800014c 800394a: 4603 mov r3, r0 800394c: b29a uxth r2, r3 800394e: 1d39 adds r1, r7, #4 8003950: f04f 33ff mov.w r3, #4294967295 8003954: 4852 ldr r0, [pc, #328] @ (8003aa0 ) 8003956: f005 ffb9 bl 80098cc } if(rtCiclo) 800395c: 881b ldrh r3, [r3, #0] 800395e: b29a uxth r2, r3 8003960: 4b51 ldr r3, [pc, #324] @ (8003aa8 ) 8003962: 881b ldrh r3, [r3, #0] 8003964: 429a cmp r2, r3 8003966: d202 bcs.n 800396e 8003968: 4b4b ldr r3, [pc, #300] @ (8003a98 ) 800396a: 2200 movs r2, #0 800396c: 701a strb r2, [r3, #0] switch(m2st){ 800396e: 4b4a ldr r3, [pc, #296] @ (8003a98 ) 8003970: 781b ldrb r3, [r3, #0] 8003972: 2b03 cmp r3, #3 8003974: d876 bhi.n 8003a64 8003976: a201 add r2, pc, #4 @ (adr r2, 800397c ) 8003978: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800397c: 0800398d .word 0x0800398d 8003980: 080039d9 .word 0x080039d9 8003984: 08003a09 .word 0x08003a09 8003988: 08003a3b .word 0x08003a3b case motWaiting: SetMotPerc(M2,FW,0); 800398c: 2200 movs r2, #0 800398e: 2100 movs r1, #0 8003990: 2002 movs r0, #2 8003992: f000 ff6d bl 8004870 SetMotPerc(M2,BW,0); 8003996: 2200 movs r2, #0 8003998: 2101 movs r1, #1 800399a: 2002 movs r0, #2 800399c: f000 ff68 bl 8004870 if(rtCiclo>=apM2start){ 80039a0: 4b40 ldr r3, [pc, #256] @ (8003aa4 ) 80039a2: 881b ldrh r3, [r3, #0] 80039a4: b29a uxth r2, r3 80039a6: 4b40 ldr r3, [pc, #256] @ (8003aa8 ) 80039a8: 881b ldrh r3, [r3, #0] 80039aa: 429a cmp r2, r3 80039ac: d365 bcc.n 8003a7a (void)ramp(M2,BW,mrampstart[M2-1],m2pwmap,tramp,RAMPINIT); 80039ae: 4b3f ldr r3, [pc, #252] @ (8003aac ) 80039b0: 885b ldrh r3, [r3, #2] 80039b2: b2da uxtb r2, r3 80039b4: 4b3e ldr r3, [pc, #248] @ (8003ab0 ) 80039b6: 881b ldrh r3, [r3, #0] 80039b8: b2d9 uxtb r1, r3 80039ba: 4b3e ldr r3, [pc, #248] @ (8003ab4 ) 80039bc: 881b ldrh r3, [r3, #0] 80039be: b2db uxtb r3, r3 80039c0: 2000 movs r0, #0 80039c2: 9001 str r0, [sp, #4] 80039c4: 9300 str r3, [sp, #0] 80039c6: 460b mov r3, r1 80039c8: 2101 movs r1, #1 80039ca: 2002 movs r0, #2 80039cc: f001 f8d0 bl 8004b70 m2st=motStartRamp; 80039d0: 4b31 ldr r3, [pc, #196] @ (8003a98 ) 80039d2: 2201 movs r2, #1 80039d4: 701a strb r2, [r3, #0] } break; 80039d6: e050 b.n 8003a7a case motStartRamp: if(ramp(M2,BW,mrampstart[M2-1],m2pwmap,tramp,RAMPRUN)==DONE){ 80039d8: 4b34 ldr r3, [pc, #208] @ (8003aac ) 80039da: 885b ldrh r3, [r3, #2] 80039dc: b2da uxtb r2, r3 80039de: 4b34 ldr r3, [pc, #208] @ (8003ab0 ) 80039e0: 881b ldrh r3, [r3, #0] 80039e2: b2d9 uxtb r1, r3 80039e4: 4b33 ldr r3, [pc, #204] @ (8003ab4 ) 80039e6: 881b ldrh r3, [r3, #0] 80039e8: b2db uxtb r3, r3 80039ea: 200a movs r0, #10 80039ec: 9001 str r0, [sp, #4] 80039ee: 9300 str r3, [sp, #0] 80039f0: 460b mov r3, r1 80039f2: 2101 movs r1, #1 80039f4: 2002 movs r0, #2 80039f6: f001 f8bb bl 8004b70 80039fa: 4603 mov r3, r0 80039fc: 2b00 cmp r3, #0 80039fe: d13e bne.n 8003a7e m2st=motWaitingTime; 8003a00: 4b25 ldr r3, [pc, #148] @ (8003a98 ) 8003a02: 2202 movs r2, #2 8003a04: 701a strb r2, [r3, #0] } break; 8003a06: e03a b.n 8003a7e case motWaitingTime: if(rtCiclo>=apM2stop){ 8003a08: 4b26 ldr r3, [pc, #152] @ (8003aa4 ) 8003a0a: 881b ldrh r3, [r3, #0] 8003a0c: b29a uxth r2, r3 8003a0e: 4b2a ldr r3, [pc, #168] @ (8003ab8 ) 8003a10: 881b ldrh r3, [r3, #0] 8003a12: 429a cmp r2, r3 8003a14: d335 bcc.n 8003a82 (void)ramp(M2,BW,m2pwmap,0,tramp,RAMPINIT); 8003a16: 4b26 ldr r3, [pc, #152] @ (8003ab0 ) 8003a18: 881b ldrh r3, [r3, #0] 8003a1a: b2da uxtb r2, r3 8003a1c: 4b25 ldr r3, [pc, #148] @ (8003ab4 ) 8003a1e: 881b ldrh r3, [r3, #0] 8003a20: b2db uxtb r3, r3 8003a22: 2100 movs r1, #0 8003a24: 9101 str r1, [sp, #4] 8003a26: 9300 str r3, [sp, #0] 8003a28: 2300 movs r3, #0 8003a2a: 2101 movs r1, #1 8003a2c: 2002 movs r0, #2 8003a2e: f001 f89f bl 8004b70 m2st=motStopRamp; 8003a32: 4b19 ldr r3, [pc, #100] @ (8003a98 ) 8003a34: 2203 movs r2, #3 8003a36: 701a strb r2, [r3, #0] } break; 8003a38: e023 b.n 8003a82 case motStopRamp: if(ramp(M2,BW,m2pwmap,0,tramp,RAMPRUN)==DONE){ 8003a3a: 4b1d ldr r3, [pc, #116] @ (8003ab0 ) 8003a3c: 881b ldrh r3, [r3, #0] 8003a3e: b2da uxtb r2, r3 8003a40: 4b1c ldr r3, [pc, #112] @ (8003ab4 ) 8003a42: 881b ldrh r3, [r3, #0] 8003a44: b2db uxtb r3, r3 8003a46: 210a movs r1, #10 8003a48: 9101 str r1, [sp, #4] 8003a4a: 9300 str r3, [sp, #0] 8003a4c: 2300 movs r3, #0 8003a4e: 2101 movs r1, #1 8003a50: 2002 movs r0, #2 8003a52: f001 f88d bl 8004b70 8003a56: 4603 mov r3, r0 8003a58: 2b00 cmp r3, #0 8003a5a: d114 bne.n 8003a86 m2st=motStop; 8003a5c: 4b0e ldr r3, [pc, #56] @ (8003a98 ) 8003a5e: 2204 movs r2, #4 8003a60: 701a strb r2, [r3, #0] } break; 8003a62: e010 b.n 8003a86 case motStop: default: SetMotPerc(M2,FW,0); 8003a64: 2200 movs r2, #0 8003a66: 2100 movs r1, #0 8003a68: 2002 movs r0, #2 8003a6a: f000 ff01 bl 8004870 SetMotPerc(M2,BW,0); 8003a6e: 2200 movs r2, #0 8003a70: 2101 movs r1, #1 8003a72: 2002 movs r0, #2 8003a74: f000 fefc bl 8004870 break; 8003a78: e006 b.n 8003a88 break; 8003a7a: bf00 nop 8003a7c: e004 b.n 8003a88 break; 8003a7e: bf00 nop 8003a80: e002 b.n 8003a88 break; 8003a82: bf00 nop 8003a84: e000 b.n 8003a88 break; 8003a86: bf00 nop } return m2st; 8003a88: 4b03 ldr r3, [pc, #12] @ (8003a98 ) 8003a8a: 781b ldrb r3, [r3, #0] } 8003a8c: 4618 mov r0, r3 8003a8e: 3768 adds r7, #104 @ 0x68 8003a90: 46bd mov sp, r7 8003a92: bd80 pop {r7, pc} 8003a94: 20000008 .word 0x20000008 8003a98: 20000463 .word 0x20000463 8003a9c: 0800f414 .word 0x0800f414 8003aa0: 200003a8 .word 0x200003a8 8003aa4: 200003fc .word 0x200003fc 8003aa8: 2000042c .word 0x2000042c 8003aac: 2000044c .word 0x2000044c 8003ab0: 20000404 .word 0x20000404 8003ab4: 20000418 .word 0x20000418 8003ab8: 2000042e .word 0x2000042e 08003abc : motMov_st m3ap(void){ 8003abc: b580 push {r7, lr} 8003abe: b09c sub sp, #112 @ 0x70 8003ac0: af02 add r7, sp, #8 static motMov_st m3st; static motMov_st memm3st=motStop; char s[100]; if(memm3st!=m3st){ 8003ac2: 4b5d ldr r3, [pc, #372] @ (8003c38 ) 8003ac4: 781a ldrb r2, [r3, #0] 8003ac6: 4b5d ldr r3, [pc, #372] @ (8003c3c ) 8003ac8: 781b ldrb r3, [r3, #0] 8003aca: 429a cmp r2, r3 8003acc: d017 beq.n 8003afe memm3st=m3st; 8003ace: 4b5b ldr r3, [pc, #364] @ (8003c3c ) 8003ad0: 781a ldrb r2, [r3, #0] 8003ad2: 4b59 ldr r3, [pc, #356] @ (8003c38 ) 8003ad4: 701a strb r2, [r3, #0] sprintf(s,"\nm3ap=%d",m3st); 8003ad6: 4b59 ldr r3, [pc, #356] @ (8003c3c ) 8003ad8: 781b ldrb r3, [r3, #0] 8003ada: 461a mov r2, r3 8003adc: 1d3b adds r3, r7, #4 8003ade: 4958 ldr r1, [pc, #352] @ (8003c40 ) 8003ae0: 4618 mov r0, r3 8003ae2: f00a fce3 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8003ae6: 1d3b adds r3, r7, #4 8003ae8: 4618 mov r0, r3 8003aea: f7fc fb2f bl 800014c 8003aee: 4603 mov r3, r0 8003af0: b29a uxth r2, r3 8003af2: 1d39 adds r1, r7, #4 8003af4: f04f 33ff mov.w r3, #4294967295 8003af8: 4852 ldr r0, [pc, #328] @ (8003c44 ) 8003afa: f005 fee7 bl 80098cc } if(rtCiclo) 8003b00: 881b ldrh r3, [r3, #0] 8003b02: b29a uxth r2, r3 8003b04: 4b51 ldr r3, [pc, #324] @ (8003c4c ) 8003b06: 881b ldrh r3, [r3, #0] 8003b08: 429a cmp r2, r3 8003b0a: d202 bcs.n 8003b12 8003b0c: 4b4b ldr r3, [pc, #300] @ (8003c3c ) 8003b0e: 2200 movs r2, #0 8003b10: 701a strb r2, [r3, #0] switch(m3st){ 8003b12: 4b4a ldr r3, [pc, #296] @ (8003c3c ) 8003b14: 781b ldrb r3, [r3, #0] 8003b16: 2b03 cmp r3, #3 8003b18: d876 bhi.n 8003c08 8003b1a: a201 add r2, pc, #4 @ (adr r2, 8003b20 ) 8003b1c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003b20: 08003b31 .word 0x08003b31 8003b24: 08003b7d .word 0x08003b7d 8003b28: 08003bad .word 0x08003bad 8003b2c: 08003bdf .word 0x08003bdf case motWaiting: SetMotPerc(M3,FW,0); 8003b30: 2200 movs r2, #0 8003b32: 2100 movs r1, #0 8003b34: 2003 movs r0, #3 8003b36: f000 fe9b bl 8004870 SetMotPerc(M3,BW,0); 8003b3a: 2200 movs r2, #0 8003b3c: 2101 movs r1, #1 8003b3e: 2003 movs r0, #3 8003b40: f000 fe96 bl 8004870 if(rtCiclo>=apM3start){ 8003b44: 4b40 ldr r3, [pc, #256] @ (8003c48 ) 8003b46: 881b ldrh r3, [r3, #0] 8003b48: b29a uxth r2, r3 8003b4a: 4b40 ldr r3, [pc, #256] @ (8003c4c ) 8003b4c: 881b ldrh r3, [r3, #0] 8003b4e: 429a cmp r2, r3 8003b50: d365 bcc.n 8003c1e (void)ramp(M3,FW,mrampstart[M3-1],m2pwmap,tramp,RAMPINIT); 8003b52: 4b3f ldr r3, [pc, #252] @ (8003c50 ) 8003b54: 889b ldrh r3, [r3, #4] 8003b56: b2da uxtb r2, r3 8003b58: 4b3e ldr r3, [pc, #248] @ (8003c54 ) 8003b5a: 881b ldrh r3, [r3, #0] 8003b5c: b2d9 uxtb r1, r3 8003b5e: 4b3e ldr r3, [pc, #248] @ (8003c58 ) 8003b60: 881b ldrh r3, [r3, #0] 8003b62: b2db uxtb r3, r3 8003b64: 2000 movs r0, #0 8003b66: 9001 str r0, [sp, #4] 8003b68: 9300 str r3, [sp, #0] 8003b6a: 460b mov r3, r1 8003b6c: 2100 movs r1, #0 8003b6e: 2003 movs r0, #3 8003b70: f000 fffe bl 8004b70 m3st=motStartRamp; 8003b74: 4b31 ldr r3, [pc, #196] @ (8003c3c ) 8003b76: 2201 movs r2, #1 8003b78: 701a strb r2, [r3, #0] } break; 8003b7a: e050 b.n 8003c1e case motStartRamp: if(ramp(M3,FW,mrampstart[M3-1],m3pwmap,tramp,RAMPRUN)==DONE){ 8003b7c: 4b34 ldr r3, [pc, #208] @ (8003c50 ) 8003b7e: 889b ldrh r3, [r3, #4] 8003b80: b2da uxtb r2, r3 8003b82: 4b36 ldr r3, [pc, #216] @ (8003c5c ) 8003b84: 881b ldrh r3, [r3, #0] 8003b86: b2d9 uxtb r1, r3 8003b88: 4b33 ldr r3, [pc, #204] @ (8003c58 ) 8003b8a: 881b ldrh r3, [r3, #0] 8003b8c: b2db uxtb r3, r3 8003b8e: 200a movs r0, #10 8003b90: 9001 str r0, [sp, #4] 8003b92: 9300 str r3, [sp, #0] 8003b94: 460b mov r3, r1 8003b96: 2100 movs r1, #0 8003b98: 2003 movs r0, #3 8003b9a: f000 ffe9 bl 8004b70 8003b9e: 4603 mov r3, r0 8003ba0: 2b00 cmp r3, #0 8003ba2: d13e bne.n 8003c22 m3st=motWaitingTime; 8003ba4: 4b25 ldr r3, [pc, #148] @ (8003c3c ) 8003ba6: 2202 movs r2, #2 8003ba8: 701a strb r2, [r3, #0] } break; 8003baa: e03a b.n 8003c22 case motWaitingTime: if(rtCiclo>=apM3stop){ 8003bac: 4b26 ldr r3, [pc, #152] @ (8003c48 ) 8003bae: 881b ldrh r3, [r3, #0] 8003bb0: b29a uxth r2, r3 8003bb2: 4b2b ldr r3, [pc, #172] @ (8003c60 ) 8003bb4: 881b ldrh r3, [r3, #0] 8003bb6: 429a cmp r2, r3 8003bb8: d335 bcc.n 8003c26 (void)ramp(M3,FW,m3pwmap,0,tramp,RAMPINIT); 8003bba: 4b28 ldr r3, [pc, #160] @ (8003c5c ) 8003bbc: 881b ldrh r3, [r3, #0] 8003bbe: b2da uxtb r2, r3 8003bc0: 4b25 ldr r3, [pc, #148] @ (8003c58 ) 8003bc2: 881b ldrh r3, [r3, #0] 8003bc4: b2db uxtb r3, r3 8003bc6: 2100 movs r1, #0 8003bc8: 9101 str r1, [sp, #4] 8003bca: 9300 str r3, [sp, #0] 8003bcc: 2300 movs r3, #0 8003bce: 2100 movs r1, #0 8003bd0: 2003 movs r0, #3 8003bd2: f000 ffcd bl 8004b70 m3st=motStopRamp; 8003bd6: 4b19 ldr r3, [pc, #100] @ (8003c3c ) 8003bd8: 2203 movs r2, #3 8003bda: 701a strb r2, [r3, #0] } break; 8003bdc: e023 b.n 8003c26 case motStopRamp: if(ramp(M3,FW,m3pwmap,0,tramp,RAMPRUN)==DONE){ 8003bde: 4b1f ldr r3, [pc, #124] @ (8003c5c ) 8003be0: 881b ldrh r3, [r3, #0] 8003be2: b2da uxtb r2, r3 8003be4: 4b1c ldr r3, [pc, #112] @ (8003c58 ) 8003be6: 881b ldrh r3, [r3, #0] 8003be8: b2db uxtb r3, r3 8003bea: 210a movs r1, #10 8003bec: 9101 str r1, [sp, #4] 8003bee: 9300 str r3, [sp, #0] 8003bf0: 2300 movs r3, #0 8003bf2: 2100 movs r1, #0 8003bf4: 2003 movs r0, #3 8003bf6: f000 ffbb bl 8004b70 8003bfa: 4603 mov r3, r0 8003bfc: 2b00 cmp r3, #0 8003bfe: d114 bne.n 8003c2a m3st=motStop; 8003c00: 4b0e ldr r3, [pc, #56] @ (8003c3c ) 8003c02: 2204 movs r2, #4 8003c04: 701a strb r2, [r3, #0] } break; 8003c06: e010 b.n 8003c2a case motStop: default: SetMotPerc(M3,FW,0); 8003c08: 2200 movs r2, #0 8003c0a: 2100 movs r1, #0 8003c0c: 2003 movs r0, #3 8003c0e: f000 fe2f bl 8004870 SetMotPerc(M3,BW,0); 8003c12: 2200 movs r2, #0 8003c14: 2101 movs r1, #1 8003c16: 2003 movs r0, #3 8003c18: f000 fe2a bl 8004870 break; 8003c1c: e006 b.n 8003c2c break; 8003c1e: bf00 nop 8003c20: e004 b.n 8003c2c break; 8003c22: bf00 nop 8003c24: e002 b.n 8003c2c break; 8003c26: bf00 nop 8003c28: e000 b.n 8003c2c break; 8003c2a: bf00 nop } return m3st; 8003c2c: 4b03 ldr r3, [pc, #12] @ (8003c3c ) 8003c2e: 781b ldrb r3, [r3, #0] } 8003c30: 4618 mov r0, r3 8003c32: 3768 adds r7, #104 @ 0x68 8003c34: 46bd mov sp, r7 8003c36: bd80 pop {r7, pc} 8003c38: 20000009 .word 0x20000009 8003c3c: 20000464 .word 0x20000464 8003c40: 0800f420 .word 0x0800f420 8003c44: 200003a8 .word 0x200003a8 8003c48: 200003fc .word 0x200003fc 8003c4c: 20000430 .word 0x20000430 8003c50: 2000044c .word 0x2000044c 8003c54: 20000404 .word 0x20000404 8003c58: 20000418 .word 0x20000418 8003c5c: 20000408 .word 0x20000408 8003c60: 20000432 .word 0x20000432 08003c64 : motMov_st m4ap(void){ 8003c64: b580 push {r7, lr} 8003c66: b09c sub sp, #112 @ 0x70 8003c68: af02 add r7, sp, #8 static motMov_st m4st; static motMov_st memm4st=motStop; char s[100]; if(memm4st!=m4st){ 8003c6a: 4b5d ldr r3, [pc, #372] @ (8003de0 ) 8003c6c: 781a ldrb r2, [r3, #0] 8003c6e: 4b5d ldr r3, [pc, #372] @ (8003de4 ) 8003c70: 781b ldrb r3, [r3, #0] 8003c72: 429a cmp r2, r3 8003c74: d017 beq.n 8003ca6 memm4st=m4st; 8003c76: 4b5b ldr r3, [pc, #364] @ (8003de4 ) 8003c78: 781a ldrb r2, [r3, #0] 8003c7a: 4b59 ldr r3, [pc, #356] @ (8003de0 ) 8003c7c: 701a strb r2, [r3, #0] sprintf(s,"\nm4ap=%d",m4st); 8003c7e: 4b59 ldr r3, [pc, #356] @ (8003de4 ) 8003c80: 781b ldrb r3, [r3, #0] 8003c82: 461a mov r2, r3 8003c84: 1d3b adds r3, r7, #4 8003c86: 4958 ldr r1, [pc, #352] @ (8003de8 ) 8003c88: 4618 mov r0, r3 8003c8a: f00a fc0f bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8003c8e: 1d3b adds r3, r7, #4 8003c90: 4618 mov r0, r3 8003c92: f7fc fa5b bl 800014c 8003c96: 4603 mov r3, r0 8003c98: b29a uxth r2, r3 8003c9a: 1d39 adds r1, r7, #4 8003c9c: f04f 33ff mov.w r3, #4294967295 8003ca0: 4852 ldr r0, [pc, #328] @ (8003dec ) 8003ca2: f005 fe13 bl 80098cc } if(rtCiclo) 8003ca8: 881b ldrh r3, [r3, #0] 8003caa: b29a uxth r2, r3 8003cac: 4b51 ldr r3, [pc, #324] @ (8003df4 ) 8003cae: 881b ldrh r3, [r3, #0] 8003cb0: 429a cmp r2, r3 8003cb2: d202 bcs.n 8003cba 8003cb4: 4b4b ldr r3, [pc, #300] @ (8003de4 ) 8003cb6: 2200 movs r2, #0 8003cb8: 701a strb r2, [r3, #0] switch(m4st){ 8003cba: 4b4a ldr r3, [pc, #296] @ (8003de4 ) 8003cbc: 781b ldrb r3, [r3, #0] 8003cbe: 2b03 cmp r3, #3 8003cc0: d876 bhi.n 8003db0 8003cc2: a201 add r2, pc, #4 @ (adr r2, 8003cc8 ) 8003cc4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003cc8: 08003cd9 .word 0x08003cd9 8003ccc: 08003d25 .word 0x08003d25 8003cd0: 08003d55 .word 0x08003d55 8003cd4: 08003d87 .word 0x08003d87 case motWaiting: SetMotPerc(M4,FW,0); 8003cd8: 2200 movs r2, #0 8003cda: 2100 movs r1, #0 8003cdc: 2004 movs r0, #4 8003cde: f000 fdc7 bl 8004870 SetMotPerc(M4,BW,0); 8003ce2: 2200 movs r2, #0 8003ce4: 2101 movs r1, #1 8003ce6: 2004 movs r0, #4 8003ce8: f000 fdc2 bl 8004870 if(rtCiclo>=apM4start){ 8003cec: 4b40 ldr r3, [pc, #256] @ (8003df0 ) 8003cee: 881b ldrh r3, [r3, #0] 8003cf0: b29a uxth r2, r3 8003cf2: 4b40 ldr r3, [pc, #256] @ (8003df4 ) 8003cf4: 881b ldrh r3, [r3, #0] 8003cf6: 429a cmp r2, r3 8003cf8: d365 bcc.n 8003dc6 (void)ramp(M4,FW,mrampstart[M4-1],m2pwmap,tramp,RAMPINIT); 8003cfa: 4b3f ldr r3, [pc, #252] @ (8003df8 ) 8003cfc: 88db ldrh r3, [r3, #6] 8003cfe: b2da uxtb r2, r3 8003d00: 4b3e ldr r3, [pc, #248] @ (8003dfc ) 8003d02: 881b ldrh r3, [r3, #0] 8003d04: b2d9 uxtb r1, r3 8003d06: 4b3e ldr r3, [pc, #248] @ (8003e00 ) 8003d08: 881b ldrh r3, [r3, #0] 8003d0a: b2db uxtb r3, r3 8003d0c: 2000 movs r0, #0 8003d0e: 9001 str r0, [sp, #4] 8003d10: 9300 str r3, [sp, #0] 8003d12: 460b mov r3, r1 8003d14: 2100 movs r1, #0 8003d16: 2004 movs r0, #4 8003d18: f000 ff2a bl 8004b70 m4st=motStartRamp; 8003d1c: 4b31 ldr r3, [pc, #196] @ (8003de4 ) 8003d1e: 2201 movs r2, #1 8003d20: 701a strb r2, [r3, #0] } break; 8003d22: e050 b.n 8003dc6 case motStartRamp: if(ramp(M4,FW,mrampstart[M4-1],m4pwmap,tramp,RAMPRUN)==DONE){ 8003d24: 4b34 ldr r3, [pc, #208] @ (8003df8 ) 8003d26: 88db ldrh r3, [r3, #6] 8003d28: b2da uxtb r2, r3 8003d2a: 4b36 ldr r3, [pc, #216] @ (8003e04 ) 8003d2c: 881b ldrh r3, [r3, #0] 8003d2e: b2d9 uxtb r1, r3 8003d30: 4b33 ldr r3, [pc, #204] @ (8003e00 ) 8003d32: 881b ldrh r3, [r3, #0] 8003d34: b2db uxtb r3, r3 8003d36: 200a movs r0, #10 8003d38: 9001 str r0, [sp, #4] 8003d3a: 9300 str r3, [sp, #0] 8003d3c: 460b mov r3, r1 8003d3e: 2100 movs r1, #0 8003d40: 2004 movs r0, #4 8003d42: f000 ff15 bl 8004b70 8003d46: 4603 mov r3, r0 8003d48: 2b00 cmp r3, #0 8003d4a: d13e bne.n 8003dca m4st=motWaitingTime; 8003d4c: 4b25 ldr r3, [pc, #148] @ (8003de4 ) 8003d4e: 2202 movs r2, #2 8003d50: 701a strb r2, [r3, #0] } break; 8003d52: e03a b.n 8003dca case motWaitingTime: if(rtCiclo>=apM4stop){ 8003d54: 4b26 ldr r3, [pc, #152] @ (8003df0 ) 8003d56: 881b ldrh r3, [r3, #0] 8003d58: b29a uxth r2, r3 8003d5a: 4b2b ldr r3, [pc, #172] @ (8003e08 ) 8003d5c: 881b ldrh r3, [r3, #0] 8003d5e: 429a cmp r2, r3 8003d60: d335 bcc.n 8003dce (void)ramp(M4,FW,m4pwmap,0,tramp,RAMPINIT); 8003d62: 4b28 ldr r3, [pc, #160] @ (8003e04 ) 8003d64: 881b ldrh r3, [r3, #0] 8003d66: b2da uxtb r2, r3 8003d68: 4b25 ldr r3, [pc, #148] @ (8003e00 ) 8003d6a: 881b ldrh r3, [r3, #0] 8003d6c: b2db uxtb r3, r3 8003d6e: 2100 movs r1, #0 8003d70: 9101 str r1, [sp, #4] 8003d72: 9300 str r3, [sp, #0] 8003d74: 2300 movs r3, #0 8003d76: 2100 movs r1, #0 8003d78: 2004 movs r0, #4 8003d7a: f000 fef9 bl 8004b70 m4st=motStopRamp; 8003d7e: 4b19 ldr r3, [pc, #100] @ (8003de4 ) 8003d80: 2203 movs r2, #3 8003d82: 701a strb r2, [r3, #0] } break; 8003d84: e023 b.n 8003dce case motStopRamp: if(ramp(M4,FW,m4pwmap,0,tramp,RAMPRUN)==DONE){ 8003d86: 4b1f ldr r3, [pc, #124] @ (8003e04 ) 8003d88: 881b ldrh r3, [r3, #0] 8003d8a: b2da uxtb r2, r3 8003d8c: 4b1c ldr r3, [pc, #112] @ (8003e00 ) 8003d8e: 881b ldrh r3, [r3, #0] 8003d90: b2db uxtb r3, r3 8003d92: 210a movs r1, #10 8003d94: 9101 str r1, [sp, #4] 8003d96: 9300 str r3, [sp, #0] 8003d98: 2300 movs r3, #0 8003d9a: 2100 movs r1, #0 8003d9c: 2004 movs r0, #4 8003d9e: f000 fee7 bl 8004b70 8003da2: 4603 mov r3, r0 8003da4: 2b00 cmp r3, #0 8003da6: d114 bne.n 8003dd2 m4st=motStop; 8003da8: 4b0e ldr r3, [pc, #56] @ (8003de4 ) 8003daa: 2204 movs r2, #4 8003dac: 701a strb r2, [r3, #0] } break; 8003dae: e010 b.n 8003dd2 case motStop: default: SetMotPerc(M4,FW,0); 8003db0: 2200 movs r2, #0 8003db2: 2100 movs r1, #0 8003db4: 2004 movs r0, #4 8003db6: f000 fd5b bl 8004870 SetMotPerc(M4,BW,0); 8003dba: 2200 movs r2, #0 8003dbc: 2101 movs r1, #1 8003dbe: 2004 movs r0, #4 8003dc0: f000 fd56 bl 8004870 break; 8003dc4: e006 b.n 8003dd4 break; 8003dc6: bf00 nop 8003dc8: e004 b.n 8003dd4 break; 8003dca: bf00 nop 8003dcc: e002 b.n 8003dd4 break; 8003dce: bf00 nop 8003dd0: e000 b.n 8003dd4 break; 8003dd2: bf00 nop } return m4st; 8003dd4: 4b03 ldr r3, [pc, #12] @ (8003de4 ) 8003dd6: 781b ldrb r3, [r3, #0] } 8003dd8: 4618 mov r0, r3 8003dda: 3768 adds r7, #104 @ 0x68 8003ddc: 46bd mov sp, r7 8003dde: bd80 pop {r7, pc} 8003de0: 2000000a .word 0x2000000a 8003de4: 20000465 .word 0x20000465 8003de8: 0800f42c .word 0x0800f42c 8003dec: 200003a8 .word 0x200003a8 8003df0: 200003fc .word 0x200003fc 8003df4: 20000434 .word 0x20000434 8003df8: 2000044c .word 0x2000044c 8003dfc: 20000404 .word 0x20000404 8003e00: 20000418 .word 0x20000418 8003e04: 2000040c .word 0x2000040c 8003e08: 20000436 .word 0x20000436 08003e0c : motMov_st m1ch(void){ 8003e0c: b580 push {r7, lr} 8003e0e: b09c sub sp, #112 @ 0x70 8003e10: af02 add r7, sp, #8 static motMov_st m1st; static motMov_st memm1st=motStop; char s[100]; if(memm1st!=m1st){ 8003e12: 4b5d ldr r3, [pc, #372] @ (8003f88 ) 8003e14: 781a ldrb r2, [r3, #0] 8003e16: 4b5d ldr r3, [pc, #372] @ (8003f8c ) 8003e18: 781b ldrb r3, [r3, #0] 8003e1a: 429a cmp r2, r3 8003e1c: d017 beq.n 8003e4e memm1st=m1st; 8003e1e: 4b5b ldr r3, [pc, #364] @ (8003f8c ) 8003e20: 781a ldrb r2, [r3, #0] 8003e22: 4b59 ldr r3, [pc, #356] @ (8003f88 ) 8003e24: 701a strb r2, [r3, #0] sprintf(s,"\nm1ch=%d",m1st); 8003e26: 4b59 ldr r3, [pc, #356] @ (8003f8c ) 8003e28: 781b ldrb r3, [r3, #0] 8003e2a: 461a mov r2, r3 8003e2c: 1d3b adds r3, r7, #4 8003e2e: 4958 ldr r1, [pc, #352] @ (8003f90 ) 8003e30: 4618 mov r0, r3 8003e32: f00a fb3b bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8003e36: 1d3b adds r3, r7, #4 8003e38: 4618 mov r0, r3 8003e3a: f7fc f987 bl 800014c 8003e3e: 4603 mov r3, r0 8003e40: b29a uxth r2, r3 8003e42: 1d39 adds r1, r7, #4 8003e44: f04f 33ff mov.w r3, #4294967295 8003e48: 4852 ldr r0, [pc, #328] @ (8003f94 ) 8003e4a: f005 fd3f bl 80098cc } if(rtCiclo) 8003e50: 881b ldrh r3, [r3, #0] 8003e52: b29a uxth r2, r3 8003e54: 4b51 ldr r3, [pc, #324] @ (8003f9c ) 8003e56: 881b ldrh r3, [r3, #0] 8003e58: 429a cmp r2, r3 8003e5a: d202 bcs.n 8003e62 8003e5c: 4b4b ldr r3, [pc, #300] @ (8003f8c ) 8003e5e: 2200 movs r2, #0 8003e60: 701a strb r2, [r3, #0] switch(m1st){ 8003e62: 4b4a ldr r3, [pc, #296] @ (8003f8c ) 8003e64: 781b ldrb r3, [r3, #0] 8003e66: 2b03 cmp r3, #3 8003e68: d876 bhi.n 8003f58 8003e6a: a201 add r2, pc, #4 @ (adr r2, 8003e70 ) 8003e6c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003e70: 08003e81 .word 0x08003e81 8003e74: 08003ecd .word 0x08003ecd 8003e78: 08003efd .word 0x08003efd 8003e7c: 08003f2f .word 0x08003f2f case motWaiting: SetMotPerc(M1,FW,0); 8003e80: 2200 movs r2, #0 8003e82: 2100 movs r1, #0 8003e84: 2001 movs r0, #1 8003e86: f000 fcf3 bl 8004870 SetMotPerc(M1,BW,0); 8003e8a: 2200 movs r2, #0 8003e8c: 2101 movs r1, #1 8003e8e: 2001 movs r0, #1 8003e90: f000 fcee bl 8004870 if(rtCiclo>=chM1start){ 8003e94: 4b40 ldr r3, [pc, #256] @ (8003f98 ) 8003e96: 881b ldrh r3, [r3, #0] 8003e98: b29a uxth r2, r3 8003e9a: 4b40 ldr r3, [pc, #256] @ (8003f9c ) 8003e9c: 881b ldrh r3, [r3, #0] 8003e9e: 429a cmp r2, r3 8003ea0: d365 bcc.n 8003f6e (void)ramp(M1,BW,mrampstart[M1-1],m1pwmch,tramp,RAMPINIT); 8003ea2: 4b3f ldr r3, [pc, #252] @ (8003fa0 ) 8003ea4: 881b ldrh r3, [r3, #0] 8003ea6: b2da uxtb r2, r3 8003ea8: 4b3e ldr r3, [pc, #248] @ (8003fa4 ) 8003eaa: 881b ldrh r3, [r3, #0] 8003eac: b2d9 uxtb r1, r3 8003eae: 4b3e ldr r3, [pc, #248] @ (8003fa8 ) 8003eb0: 881b ldrh r3, [r3, #0] 8003eb2: b2db uxtb r3, r3 8003eb4: 2000 movs r0, #0 8003eb6: 9001 str r0, [sp, #4] 8003eb8: 9300 str r3, [sp, #0] 8003eba: 460b mov r3, r1 8003ebc: 2101 movs r1, #1 8003ebe: 2001 movs r0, #1 8003ec0: f000 fe56 bl 8004b70 m1st=motStartRamp; 8003ec4: 4b31 ldr r3, [pc, #196] @ (8003f8c ) 8003ec6: 2201 movs r2, #1 8003ec8: 701a strb r2, [r3, #0] } break; 8003eca: e050 b.n 8003f6e case motStartRamp: if(ramp(M1,BW,mrampstart[M1-1],m1pwmch,tramp,RAMPRUN)==DONE){ 8003ecc: 4b34 ldr r3, [pc, #208] @ (8003fa0 ) 8003ece: 881b ldrh r3, [r3, #0] 8003ed0: b2da uxtb r2, r3 8003ed2: 4b34 ldr r3, [pc, #208] @ (8003fa4 ) 8003ed4: 881b ldrh r3, [r3, #0] 8003ed6: b2d9 uxtb r1, r3 8003ed8: 4b33 ldr r3, [pc, #204] @ (8003fa8 ) 8003eda: 881b ldrh r3, [r3, #0] 8003edc: b2db uxtb r3, r3 8003ede: 200a movs r0, #10 8003ee0: 9001 str r0, [sp, #4] 8003ee2: 9300 str r3, [sp, #0] 8003ee4: 460b mov r3, r1 8003ee6: 2101 movs r1, #1 8003ee8: 2001 movs r0, #1 8003eea: f000 fe41 bl 8004b70 8003eee: 4603 mov r3, r0 8003ef0: 2b00 cmp r3, #0 8003ef2: d13e bne.n 8003f72 m1st=motWaitingTime; 8003ef4: 4b25 ldr r3, [pc, #148] @ (8003f8c ) 8003ef6: 2202 movs r2, #2 8003ef8: 701a strb r2, [r3, #0] } break; 8003efa: e03a b.n 8003f72 case motWaitingTime: if(rtCiclo>=chM1stop){ 8003efc: 4b26 ldr r3, [pc, #152] @ (8003f98 ) 8003efe: 881b ldrh r3, [r3, #0] 8003f00: b29a uxth r2, r3 8003f02: 4b2a ldr r3, [pc, #168] @ (8003fac ) 8003f04: 881b ldrh r3, [r3, #0] 8003f06: 429a cmp r2, r3 8003f08: d335 bcc.n 8003f76 (void)ramp(M1,BW,m1pwmch,0,tramp,RAMPINIT); 8003f0a: 4b26 ldr r3, [pc, #152] @ (8003fa4 ) 8003f0c: 881b ldrh r3, [r3, #0] 8003f0e: b2da uxtb r2, r3 8003f10: 4b25 ldr r3, [pc, #148] @ (8003fa8 ) 8003f12: 881b ldrh r3, [r3, #0] 8003f14: b2db uxtb r3, r3 8003f16: 2100 movs r1, #0 8003f18: 9101 str r1, [sp, #4] 8003f1a: 9300 str r3, [sp, #0] 8003f1c: 2300 movs r3, #0 8003f1e: 2101 movs r1, #1 8003f20: 2001 movs r0, #1 8003f22: f000 fe25 bl 8004b70 m1st=motStopRamp; 8003f26: 4b19 ldr r3, [pc, #100] @ (8003f8c ) 8003f28: 2203 movs r2, #3 8003f2a: 701a strb r2, [r3, #0] } break; 8003f2c: e023 b.n 8003f76 case motStopRamp: if(ramp(M1,BW,m1pwmch,0,tramp,RAMPRUN)==DONE){ 8003f2e: 4b1d ldr r3, [pc, #116] @ (8003fa4 ) 8003f30: 881b ldrh r3, [r3, #0] 8003f32: b2da uxtb r2, r3 8003f34: 4b1c ldr r3, [pc, #112] @ (8003fa8 ) 8003f36: 881b ldrh r3, [r3, #0] 8003f38: b2db uxtb r3, r3 8003f3a: 210a movs r1, #10 8003f3c: 9101 str r1, [sp, #4] 8003f3e: 9300 str r3, [sp, #0] 8003f40: 2300 movs r3, #0 8003f42: 2101 movs r1, #1 8003f44: 2001 movs r0, #1 8003f46: f000 fe13 bl 8004b70 8003f4a: 4603 mov r3, r0 8003f4c: 2b00 cmp r3, #0 8003f4e: d114 bne.n 8003f7a m1st=motStop; 8003f50: 4b0e ldr r3, [pc, #56] @ (8003f8c ) 8003f52: 2204 movs r2, #4 8003f54: 701a strb r2, [r3, #0] } break; 8003f56: e010 b.n 8003f7a case motStop: default: SetMotPerc(M1,FW,0); 8003f58: 2200 movs r2, #0 8003f5a: 2100 movs r1, #0 8003f5c: 2001 movs r0, #1 8003f5e: f000 fc87 bl 8004870 SetMotPerc(M1,BW,0); 8003f62: 2200 movs r2, #0 8003f64: 2101 movs r1, #1 8003f66: 2001 movs r0, #1 8003f68: f000 fc82 bl 8004870 break; 8003f6c: e006 b.n 8003f7c break; 8003f6e: bf00 nop 8003f70: e004 b.n 8003f7c break; 8003f72: bf00 nop 8003f74: e002 b.n 8003f7c break; 8003f76: bf00 nop 8003f78: e000 b.n 8003f7c break; 8003f7a: bf00 nop } return m1st; 8003f7c: 4b03 ldr r3, [pc, #12] @ (8003f8c ) 8003f7e: 781b ldrb r3, [r3, #0] } 8003f80: 4618 mov r0, r3 8003f82: 3768 adds r7, #104 @ 0x68 8003f84: 46bd mov sp, r7 8003f86: bd80 pop {r7, pc} 8003f88: 2000000b .word 0x2000000b 8003f8c: 20000466 .word 0x20000466 8003f90: 0800f438 .word 0x0800f438 8003f94: 200003a8 .word 0x200003a8 8003f98: 200003fc .word 0x200003fc 8003f9c: 20000438 .word 0x20000438 8003fa0: 2000044c .word 0x2000044c 8003fa4: 20000402 .word 0x20000402 8003fa8: 20000418 .word 0x20000418 8003fac: 2000043a .word 0x2000043a 08003fb0 : motMov_st m2ch(void){ 8003fb0: b580 push {r7, lr} 8003fb2: b09c sub sp, #112 @ 0x70 8003fb4: af02 add r7, sp, #8 static motMov_st m2st; static motMov_st memm2st=motStop; char s[100]; if(memm2st!=m2st){ 8003fb6: 4b5d ldr r3, [pc, #372] @ (800412c ) 8003fb8: 781a ldrb r2, [r3, #0] 8003fba: 4b5d ldr r3, [pc, #372] @ (8004130 ) 8003fbc: 781b ldrb r3, [r3, #0] 8003fbe: 429a cmp r2, r3 8003fc0: d017 beq.n 8003ff2 memm2st=m2st; 8003fc2: 4b5b ldr r3, [pc, #364] @ (8004130 ) 8003fc4: 781a ldrb r2, [r3, #0] 8003fc6: 4b59 ldr r3, [pc, #356] @ (800412c ) 8003fc8: 701a strb r2, [r3, #0] sprintf(s,"\nm2ch=%d",m2st); 8003fca: 4b59 ldr r3, [pc, #356] @ (8004130 ) 8003fcc: 781b ldrb r3, [r3, #0] 8003fce: 461a mov r2, r3 8003fd0: 1d3b adds r3, r7, #4 8003fd2: 4958 ldr r1, [pc, #352] @ (8004134 ) 8003fd4: 4618 mov r0, r3 8003fd6: f00a fa69 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8003fda: 1d3b adds r3, r7, #4 8003fdc: 4618 mov r0, r3 8003fde: f7fc f8b5 bl 800014c 8003fe2: 4603 mov r3, r0 8003fe4: b29a uxth r2, r3 8003fe6: 1d39 adds r1, r7, #4 8003fe8: f04f 33ff mov.w r3, #4294967295 8003fec: 4852 ldr r0, [pc, #328] @ (8004138 ) 8003fee: f005 fc6d bl 80098cc } if(rtCiclo) 8003ff4: 881b ldrh r3, [r3, #0] 8003ff6: b29a uxth r2, r3 8003ff8: 4b51 ldr r3, [pc, #324] @ (8004140 ) 8003ffa: 881b ldrh r3, [r3, #0] 8003ffc: 429a cmp r2, r3 8003ffe: d202 bcs.n 8004006 8004000: 4b4b ldr r3, [pc, #300] @ (8004130 ) 8004002: 2200 movs r2, #0 8004004: 701a strb r2, [r3, #0] switch(m2st){ 8004006: 4b4a ldr r3, [pc, #296] @ (8004130 ) 8004008: 781b ldrb r3, [r3, #0] 800400a: 2b03 cmp r3, #3 800400c: d876 bhi.n 80040fc 800400e: a201 add r2, pc, #4 @ (adr r2, 8004014 ) 8004010: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004014: 08004025 .word 0x08004025 8004018: 08004071 .word 0x08004071 800401c: 080040a1 .word 0x080040a1 8004020: 080040d3 .word 0x080040d3 case motWaiting: SetMotPerc(M2,FW,0); 8004024: 2200 movs r2, #0 8004026: 2100 movs r1, #0 8004028: 2002 movs r0, #2 800402a: f000 fc21 bl 8004870 SetMotPerc(M2,BW,0); 800402e: 2200 movs r2, #0 8004030: 2101 movs r1, #1 8004032: 2002 movs r0, #2 8004034: f000 fc1c bl 8004870 if(rtCiclo>=chM2start){ 8004038: 4b40 ldr r3, [pc, #256] @ (800413c ) 800403a: 881b ldrh r3, [r3, #0] 800403c: b29a uxth r2, r3 800403e: 4b40 ldr r3, [pc, #256] @ (8004140 ) 8004040: 881b ldrh r3, [r3, #0] 8004042: 429a cmp r2, r3 8004044: d365 bcc.n 8004112 (void)ramp(M2,FW,mrampstart[M2-1],m2pwmch,tramp,RAMPINIT); 8004046: 4b3f ldr r3, [pc, #252] @ (8004144 ) 8004048: 885b ldrh r3, [r3, #2] 800404a: b2da uxtb r2, r3 800404c: 4b3e ldr r3, [pc, #248] @ (8004148 ) 800404e: 881b ldrh r3, [r3, #0] 8004050: b2d9 uxtb r1, r3 8004052: 4b3e ldr r3, [pc, #248] @ (800414c ) 8004054: 881b ldrh r3, [r3, #0] 8004056: b2db uxtb r3, r3 8004058: 2000 movs r0, #0 800405a: 9001 str r0, [sp, #4] 800405c: 9300 str r3, [sp, #0] 800405e: 460b mov r3, r1 8004060: 2100 movs r1, #0 8004062: 2002 movs r0, #2 8004064: f000 fd84 bl 8004b70 m2st=motStartRamp; 8004068: 4b31 ldr r3, [pc, #196] @ (8004130 ) 800406a: 2201 movs r2, #1 800406c: 701a strb r2, [r3, #0] } break; 800406e: e050 b.n 8004112 case motStartRamp: if(ramp(M2,FW,mrampstart[M2-1],m2pwmch,tramp,RAMPRUN)==DONE){ 8004070: 4b34 ldr r3, [pc, #208] @ (8004144 ) 8004072: 885b ldrh r3, [r3, #2] 8004074: b2da uxtb r2, r3 8004076: 4b34 ldr r3, [pc, #208] @ (8004148 ) 8004078: 881b ldrh r3, [r3, #0] 800407a: b2d9 uxtb r1, r3 800407c: 4b33 ldr r3, [pc, #204] @ (800414c ) 800407e: 881b ldrh r3, [r3, #0] 8004080: b2db uxtb r3, r3 8004082: 200a movs r0, #10 8004084: 9001 str r0, [sp, #4] 8004086: 9300 str r3, [sp, #0] 8004088: 460b mov r3, r1 800408a: 2100 movs r1, #0 800408c: 2002 movs r0, #2 800408e: f000 fd6f bl 8004b70 8004092: 4603 mov r3, r0 8004094: 2b00 cmp r3, #0 8004096: d13e bne.n 8004116 m2st=motWaitingTime; 8004098: 4b25 ldr r3, [pc, #148] @ (8004130 ) 800409a: 2202 movs r2, #2 800409c: 701a strb r2, [r3, #0] } break; 800409e: e03a b.n 8004116 case motWaitingTime: if(rtCiclo>=chM2stop){ 80040a0: 4b26 ldr r3, [pc, #152] @ (800413c ) 80040a2: 881b ldrh r3, [r3, #0] 80040a4: b29a uxth r2, r3 80040a6: 4b2a ldr r3, [pc, #168] @ (8004150 ) 80040a8: 881b ldrh r3, [r3, #0] 80040aa: 429a cmp r2, r3 80040ac: d335 bcc.n 800411a (void)ramp(M2,FW,m2pwmch,0,tramp,RAMPINIT); 80040ae: 4b26 ldr r3, [pc, #152] @ (8004148 ) 80040b0: 881b ldrh r3, [r3, #0] 80040b2: b2da uxtb r2, r3 80040b4: 4b25 ldr r3, [pc, #148] @ (800414c ) 80040b6: 881b ldrh r3, [r3, #0] 80040b8: b2db uxtb r3, r3 80040ba: 2100 movs r1, #0 80040bc: 9101 str r1, [sp, #4] 80040be: 9300 str r3, [sp, #0] 80040c0: 2300 movs r3, #0 80040c2: 2100 movs r1, #0 80040c4: 2002 movs r0, #2 80040c6: f000 fd53 bl 8004b70 m2st=motStopRamp; 80040ca: 4b19 ldr r3, [pc, #100] @ (8004130 ) 80040cc: 2203 movs r2, #3 80040ce: 701a strb r2, [r3, #0] } break; 80040d0: e023 b.n 800411a case motStopRamp: if(ramp(M2,FW,m2pwmch,0,tramp,RAMPRUN)==DONE){ 80040d2: 4b1d ldr r3, [pc, #116] @ (8004148 ) 80040d4: 881b ldrh r3, [r3, #0] 80040d6: b2da uxtb r2, r3 80040d8: 4b1c ldr r3, [pc, #112] @ (800414c ) 80040da: 881b ldrh r3, [r3, #0] 80040dc: b2db uxtb r3, r3 80040de: 210a movs r1, #10 80040e0: 9101 str r1, [sp, #4] 80040e2: 9300 str r3, [sp, #0] 80040e4: 2300 movs r3, #0 80040e6: 2100 movs r1, #0 80040e8: 2002 movs r0, #2 80040ea: f000 fd41 bl 8004b70 80040ee: 4603 mov r3, r0 80040f0: 2b00 cmp r3, #0 80040f2: d114 bne.n 800411e m2st=motStop; 80040f4: 4b0e ldr r3, [pc, #56] @ (8004130 ) 80040f6: 2204 movs r2, #4 80040f8: 701a strb r2, [r3, #0] } break; 80040fa: e010 b.n 800411e case motStop: default: SetMotPerc(M2,FW,0); 80040fc: 2200 movs r2, #0 80040fe: 2100 movs r1, #0 8004100: 2002 movs r0, #2 8004102: f000 fbb5 bl 8004870 SetMotPerc(M2,BW,0); 8004106: 2200 movs r2, #0 8004108: 2101 movs r1, #1 800410a: 2002 movs r0, #2 800410c: f000 fbb0 bl 8004870 break; 8004110: e006 b.n 8004120 break; 8004112: bf00 nop 8004114: e004 b.n 8004120 break; 8004116: bf00 nop 8004118: e002 b.n 8004120 break; 800411a: bf00 nop 800411c: e000 b.n 8004120 break; 800411e: bf00 nop } return m2st; 8004120: 4b03 ldr r3, [pc, #12] @ (8004130 ) 8004122: 781b ldrb r3, [r3, #0] } 8004124: 4618 mov r0, r3 8004126: 3768 adds r7, #104 @ 0x68 8004128: 46bd mov sp, r7 800412a: bd80 pop {r7, pc} 800412c: 2000000c .word 0x2000000c 8004130: 20000467 .word 0x20000467 8004134: 0800f444 .word 0x0800f444 8004138: 200003a8 .word 0x200003a8 800413c: 200003fc .word 0x200003fc 8004140: 2000043c .word 0x2000043c 8004144: 2000044c .word 0x2000044c 8004148: 20000406 .word 0x20000406 800414c: 20000418 .word 0x20000418 8004150: 2000043e .word 0x2000043e 08004154 : motMov_st m3ch(void){ 8004154: b580 push {r7, lr} 8004156: b09c sub sp, #112 @ 0x70 8004158: af02 add r7, sp, #8 static motMov_st m3st; static motMov_st memm3st=motStop; char s[100]; if(memm3st!=m3st){ 800415a: 4b5d ldr r3, [pc, #372] @ (80042d0 ) 800415c: 781a ldrb r2, [r3, #0] 800415e: 4b5d ldr r3, [pc, #372] @ (80042d4 ) 8004160: 781b ldrb r3, [r3, #0] 8004162: 429a cmp r2, r3 8004164: d017 beq.n 8004196 memm3st=m3st; 8004166: 4b5b ldr r3, [pc, #364] @ (80042d4 ) 8004168: 781a ldrb r2, [r3, #0] 800416a: 4b59 ldr r3, [pc, #356] @ (80042d0 ) 800416c: 701a strb r2, [r3, #0] sprintf(s,"\nm3ch=%d",m3st); 800416e: 4b59 ldr r3, [pc, #356] @ (80042d4 ) 8004170: 781b ldrb r3, [r3, #0] 8004172: 461a mov r2, r3 8004174: 1d3b adds r3, r7, #4 8004176: 4958 ldr r1, [pc, #352] @ (80042d8 ) 8004178: 4618 mov r0, r3 800417a: f00a f997 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 800417e: 1d3b adds r3, r7, #4 8004180: 4618 mov r0, r3 8004182: f7fb ffe3 bl 800014c 8004186: 4603 mov r3, r0 8004188: b29a uxth r2, r3 800418a: 1d39 adds r1, r7, #4 800418c: f04f 33ff mov.w r3, #4294967295 8004190: 4852 ldr r0, [pc, #328] @ (80042dc ) 8004192: f005 fb9b bl 80098cc } if(rtCiclo) 8004198: 881b ldrh r3, [r3, #0] 800419a: b29a uxth r2, r3 800419c: 4b51 ldr r3, [pc, #324] @ (80042e4 ) 800419e: 881b ldrh r3, [r3, #0] 80041a0: 429a cmp r2, r3 80041a2: d202 bcs.n 80041aa 80041a4: 4b4b ldr r3, [pc, #300] @ (80042d4 ) 80041a6: 2200 movs r2, #0 80041a8: 701a strb r2, [r3, #0] switch(m3st){ 80041aa: 4b4a ldr r3, [pc, #296] @ (80042d4 ) 80041ac: 781b ldrb r3, [r3, #0] 80041ae: 2b03 cmp r3, #3 80041b0: d876 bhi.n 80042a0 80041b2: a201 add r2, pc, #4 @ (adr r2, 80041b8 ) 80041b4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80041b8: 080041c9 .word 0x080041c9 80041bc: 08004215 .word 0x08004215 80041c0: 08004245 .word 0x08004245 80041c4: 08004277 .word 0x08004277 case motWaiting: SetMotPerc(M3,FW,0); 80041c8: 2200 movs r2, #0 80041ca: 2100 movs r1, #0 80041cc: 2003 movs r0, #3 80041ce: f000 fb4f bl 8004870 SetMotPerc(M3,BW,0); 80041d2: 2200 movs r2, #0 80041d4: 2101 movs r1, #1 80041d6: 2003 movs r0, #3 80041d8: f000 fb4a bl 8004870 if(rtCiclo>=chM3start){ 80041dc: 4b40 ldr r3, [pc, #256] @ (80042e0 ) 80041de: 881b ldrh r3, [r3, #0] 80041e0: b29a uxth r2, r3 80041e2: 4b40 ldr r3, [pc, #256] @ (80042e4 ) 80041e4: 881b ldrh r3, [r3, #0] 80041e6: 429a cmp r2, r3 80041e8: d365 bcc.n 80042b6 (void)ramp(M3,BW,mrampstart[M3-1],m2pwmch,tramp,RAMPINIT); 80041ea: 4b3f ldr r3, [pc, #252] @ (80042e8 ) 80041ec: 889b ldrh r3, [r3, #4] 80041ee: b2da uxtb r2, r3 80041f0: 4b3e ldr r3, [pc, #248] @ (80042ec ) 80041f2: 881b ldrh r3, [r3, #0] 80041f4: b2d9 uxtb r1, r3 80041f6: 4b3e ldr r3, [pc, #248] @ (80042f0 ) 80041f8: 881b ldrh r3, [r3, #0] 80041fa: b2db uxtb r3, r3 80041fc: 2000 movs r0, #0 80041fe: 9001 str r0, [sp, #4] 8004200: 9300 str r3, [sp, #0] 8004202: 460b mov r3, r1 8004204: 2101 movs r1, #1 8004206: 2003 movs r0, #3 8004208: f000 fcb2 bl 8004b70 m3st=motStartRamp; 800420c: 4b31 ldr r3, [pc, #196] @ (80042d4 ) 800420e: 2201 movs r2, #1 8004210: 701a strb r2, [r3, #0] } break; 8004212: e050 b.n 80042b6 case motStartRamp: if(ramp(M3,BW,mrampstart[M3-1],m3pwmch,tramp,RAMPRUN)==DONE){ 8004214: 4b34 ldr r3, [pc, #208] @ (80042e8 ) 8004216: 889b ldrh r3, [r3, #4] 8004218: b2da uxtb r2, r3 800421a: 4b36 ldr r3, [pc, #216] @ (80042f4 ) 800421c: 881b ldrh r3, [r3, #0] 800421e: b2d9 uxtb r1, r3 8004220: 4b33 ldr r3, [pc, #204] @ (80042f0 ) 8004222: 881b ldrh r3, [r3, #0] 8004224: b2db uxtb r3, r3 8004226: 200a movs r0, #10 8004228: 9001 str r0, [sp, #4] 800422a: 9300 str r3, [sp, #0] 800422c: 460b mov r3, r1 800422e: 2101 movs r1, #1 8004230: 2003 movs r0, #3 8004232: f000 fc9d bl 8004b70 8004236: 4603 mov r3, r0 8004238: 2b00 cmp r3, #0 800423a: d13e bne.n 80042ba m3st=motWaitingTime; 800423c: 4b25 ldr r3, [pc, #148] @ (80042d4 ) 800423e: 2202 movs r2, #2 8004240: 701a strb r2, [r3, #0] } break; 8004242: e03a b.n 80042ba case motWaitingTime: if(rtCiclo>=chM3stop){ 8004244: 4b26 ldr r3, [pc, #152] @ (80042e0 ) 8004246: 881b ldrh r3, [r3, #0] 8004248: b29a uxth r2, r3 800424a: 4b2b ldr r3, [pc, #172] @ (80042f8 ) 800424c: 881b ldrh r3, [r3, #0] 800424e: 429a cmp r2, r3 8004250: d335 bcc.n 80042be (void)ramp(M3,BW,m3pwmch,0,tramp,RAMPINIT); 8004252: 4b28 ldr r3, [pc, #160] @ (80042f4 ) 8004254: 881b ldrh r3, [r3, #0] 8004256: b2da uxtb r2, r3 8004258: 4b25 ldr r3, [pc, #148] @ (80042f0 ) 800425a: 881b ldrh r3, [r3, #0] 800425c: b2db uxtb r3, r3 800425e: 2100 movs r1, #0 8004260: 9101 str r1, [sp, #4] 8004262: 9300 str r3, [sp, #0] 8004264: 2300 movs r3, #0 8004266: 2101 movs r1, #1 8004268: 2003 movs r0, #3 800426a: f000 fc81 bl 8004b70 m3st=motStopRamp; 800426e: 4b19 ldr r3, [pc, #100] @ (80042d4 ) 8004270: 2203 movs r2, #3 8004272: 701a strb r2, [r3, #0] } break; 8004274: e023 b.n 80042be case motStopRamp: if(ramp(M3,BW,m3pwmch,0,tramp,RAMPRUN)==DONE){ 8004276: 4b1f ldr r3, [pc, #124] @ (80042f4 ) 8004278: 881b ldrh r3, [r3, #0] 800427a: b2da uxtb r2, r3 800427c: 4b1c ldr r3, [pc, #112] @ (80042f0 ) 800427e: 881b ldrh r3, [r3, #0] 8004280: b2db uxtb r3, r3 8004282: 210a movs r1, #10 8004284: 9101 str r1, [sp, #4] 8004286: 9300 str r3, [sp, #0] 8004288: 2300 movs r3, #0 800428a: 2101 movs r1, #1 800428c: 2003 movs r0, #3 800428e: f000 fc6f bl 8004b70 8004292: 4603 mov r3, r0 8004294: 2b00 cmp r3, #0 8004296: d114 bne.n 80042c2 m3st=motStop; 8004298: 4b0e ldr r3, [pc, #56] @ (80042d4 ) 800429a: 2204 movs r2, #4 800429c: 701a strb r2, [r3, #0] } break; 800429e: e010 b.n 80042c2 case motStop: default: SetMotPerc(M3,FW,0); 80042a0: 2200 movs r2, #0 80042a2: 2100 movs r1, #0 80042a4: 2003 movs r0, #3 80042a6: f000 fae3 bl 8004870 SetMotPerc(M3,BW,0); 80042aa: 2200 movs r2, #0 80042ac: 2101 movs r1, #1 80042ae: 2003 movs r0, #3 80042b0: f000 fade bl 8004870 break; 80042b4: e006 b.n 80042c4 break; 80042b6: bf00 nop 80042b8: e004 b.n 80042c4 break; 80042ba: bf00 nop 80042bc: e002 b.n 80042c4 break; 80042be: bf00 nop 80042c0: e000 b.n 80042c4 break; 80042c2: bf00 nop } return m3st; 80042c4: 4b03 ldr r3, [pc, #12] @ (80042d4 ) 80042c6: 781b ldrb r3, [r3, #0] } 80042c8: 4618 mov r0, r3 80042ca: 3768 adds r7, #104 @ 0x68 80042cc: 46bd mov sp, r7 80042ce: bd80 pop {r7, pc} 80042d0: 2000000d .word 0x2000000d 80042d4: 20000468 .word 0x20000468 80042d8: 0800f450 .word 0x0800f450 80042dc: 200003a8 .word 0x200003a8 80042e0: 200003fc .word 0x200003fc 80042e4: 20000440 .word 0x20000440 80042e8: 2000044c .word 0x2000044c 80042ec: 20000406 .word 0x20000406 80042f0: 20000418 .word 0x20000418 80042f4: 2000040a .word 0x2000040a 80042f8: 20000442 .word 0x20000442 080042fc : motMov_st m4ch(void){ 80042fc: b580 push {r7, lr} 80042fe: b09c sub sp, #112 @ 0x70 8004300: af02 add r7, sp, #8 static motMov_st m4st; static motMov_st memm4st=motStop; char s[100]; if(memm4st!=m4st){ 8004302: 4b5d ldr r3, [pc, #372] @ (8004478 ) 8004304: 781a ldrb r2, [r3, #0] 8004306: 4b5d ldr r3, [pc, #372] @ (800447c ) 8004308: 781b ldrb r3, [r3, #0] 800430a: 429a cmp r2, r3 800430c: d017 beq.n 800433e memm4st=m4st; 800430e: 4b5b ldr r3, [pc, #364] @ (800447c ) 8004310: 781a ldrb r2, [r3, #0] 8004312: 4b59 ldr r3, [pc, #356] @ (8004478 ) 8004314: 701a strb r2, [r3, #0] sprintf(s,"\nm4ch=%d",m4st); 8004316: 4b59 ldr r3, [pc, #356] @ (800447c ) 8004318: 781b ldrb r3, [r3, #0] 800431a: 461a mov r2, r3 800431c: 1d3b adds r3, r7, #4 800431e: 4958 ldr r1, [pc, #352] @ (8004480 ) 8004320: 4618 mov r0, r3 8004322: f00a f8c3 bl 800e4ac HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); 8004326: 1d3b adds r3, r7, #4 8004328: 4618 mov r0, r3 800432a: f7fb ff0f bl 800014c 800432e: 4603 mov r3, r0 8004330: b29a uxth r2, r3 8004332: 1d39 adds r1, r7, #4 8004334: f04f 33ff mov.w r3, #4294967295 8004338: 4852 ldr r0, [pc, #328] @ (8004484 ) 800433a: f005 fac7 bl 80098cc } if(rtCiclo) 8004340: 881b ldrh r3, [r3, #0] 8004342: b29a uxth r2, r3 8004344: 4b51 ldr r3, [pc, #324] @ (800448c ) 8004346: 881b ldrh r3, [r3, #0] 8004348: 429a cmp r2, r3 800434a: d202 bcs.n 8004352 800434c: 4b4b ldr r3, [pc, #300] @ (800447c ) 800434e: 2200 movs r2, #0 8004350: 701a strb r2, [r3, #0] switch(m4st){ 8004352: 4b4a ldr r3, [pc, #296] @ (800447c ) 8004354: 781b ldrb r3, [r3, #0] 8004356: 2b03 cmp r3, #3 8004358: d876 bhi.n 8004448 800435a: a201 add r2, pc, #4 @ (adr r2, 8004360 ) 800435c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004360: 08004371 .word 0x08004371 8004364: 080043bd .word 0x080043bd 8004368: 080043ed .word 0x080043ed 800436c: 0800441f .word 0x0800441f case motWaiting: SetMotPerc(M4,FW,0); 8004370: 2200 movs r2, #0 8004372: 2100 movs r1, #0 8004374: 2004 movs r0, #4 8004376: f000 fa7b bl 8004870 SetMotPerc(M4,BW,0); 800437a: 2200 movs r2, #0 800437c: 2101 movs r1, #1 800437e: 2004 movs r0, #4 8004380: f000 fa76 bl 8004870 if(rtCiclo>=chM4start){ 8004384: 4b40 ldr r3, [pc, #256] @ (8004488 ) 8004386: 881b ldrh r3, [r3, #0] 8004388: b29a uxth r2, r3 800438a: 4b40 ldr r3, [pc, #256] @ (800448c ) 800438c: 881b ldrh r3, [r3, #0] 800438e: 429a cmp r2, r3 8004390: d365 bcc.n 800445e (void)ramp(M4,BW,mrampstart[M4-1],m4pwmch,tramp,RAMPINIT); 8004392: 4b3f ldr r3, [pc, #252] @ (8004490 ) 8004394: 88db ldrh r3, [r3, #6] 8004396: b2da uxtb r2, r3 8004398: 4b3e ldr r3, [pc, #248] @ (8004494 ) 800439a: 881b ldrh r3, [r3, #0] 800439c: b2d9 uxtb r1, r3 800439e: 4b3e ldr r3, [pc, #248] @ (8004498 ) 80043a0: 881b ldrh r3, [r3, #0] 80043a2: b2db uxtb r3, r3 80043a4: 2000 movs r0, #0 80043a6: 9001 str r0, [sp, #4] 80043a8: 9300 str r3, [sp, #0] 80043aa: 460b mov r3, r1 80043ac: 2101 movs r1, #1 80043ae: 2004 movs r0, #4 80043b0: f000 fbde bl 8004b70 m4st=motStartRamp; 80043b4: 4b31 ldr r3, [pc, #196] @ (800447c ) 80043b6: 2201 movs r2, #1 80043b8: 701a strb r2, [r3, #0] } break; 80043ba: e050 b.n 800445e case motStartRamp: if(ramp(M4,BW,mrampstart[M4-1],m4pwmch,tramp,RAMPRUN)==DONE){ 80043bc: 4b34 ldr r3, [pc, #208] @ (8004490 ) 80043be: 88db ldrh r3, [r3, #6] 80043c0: b2da uxtb r2, r3 80043c2: 4b34 ldr r3, [pc, #208] @ (8004494 ) 80043c4: 881b ldrh r3, [r3, #0] 80043c6: b2d9 uxtb r1, r3 80043c8: 4b33 ldr r3, [pc, #204] @ (8004498 ) 80043ca: 881b ldrh r3, [r3, #0] 80043cc: b2db uxtb r3, r3 80043ce: 200a movs r0, #10 80043d0: 9001 str r0, [sp, #4] 80043d2: 9300 str r3, [sp, #0] 80043d4: 460b mov r3, r1 80043d6: 2101 movs r1, #1 80043d8: 2004 movs r0, #4 80043da: f000 fbc9 bl 8004b70 80043de: 4603 mov r3, r0 80043e0: 2b00 cmp r3, #0 80043e2: d13e bne.n 8004462 m4st=motWaitingTime; 80043e4: 4b25 ldr r3, [pc, #148] @ (800447c ) 80043e6: 2202 movs r2, #2 80043e8: 701a strb r2, [r3, #0] } break; 80043ea: e03a b.n 8004462 case motWaitingTime: if(rtCiclo>=chM4stop){ 80043ec: 4b26 ldr r3, [pc, #152] @ (8004488 ) 80043ee: 881b ldrh r3, [r3, #0] 80043f0: b29a uxth r2, r3 80043f2: 4b2a ldr r3, [pc, #168] @ (800449c ) 80043f4: 881b ldrh r3, [r3, #0] 80043f6: 429a cmp r2, r3 80043f8: d335 bcc.n 8004466 (void)ramp(M4,BW,m4pwmch,0,tramp,RAMPINIT); 80043fa: 4b26 ldr r3, [pc, #152] @ (8004494 ) 80043fc: 881b ldrh r3, [r3, #0] 80043fe: b2da uxtb r2, r3 8004400: 4b25 ldr r3, [pc, #148] @ (8004498 ) 8004402: 881b ldrh r3, [r3, #0] 8004404: b2db uxtb r3, r3 8004406: 2100 movs r1, #0 8004408: 9101 str r1, [sp, #4] 800440a: 9300 str r3, [sp, #0] 800440c: 2300 movs r3, #0 800440e: 2101 movs r1, #1 8004410: 2004 movs r0, #4 8004412: f000 fbad bl 8004b70 m4st=motStopRamp; 8004416: 4b19 ldr r3, [pc, #100] @ (800447c ) 8004418: 2203 movs r2, #3 800441a: 701a strb r2, [r3, #0] } break; 800441c: e023 b.n 8004466 case motStopRamp: if(ramp(M4,BW,m4pwmch,0,tramp,RAMPRUN)==DONE){ 800441e: 4b1d ldr r3, [pc, #116] @ (8004494 ) 8004420: 881b ldrh r3, [r3, #0] 8004422: b2da uxtb r2, r3 8004424: 4b1c ldr r3, [pc, #112] @ (8004498 ) 8004426: 881b ldrh r3, [r3, #0] 8004428: b2db uxtb r3, r3 800442a: 210a movs r1, #10 800442c: 9101 str r1, [sp, #4] 800442e: 9300 str r3, [sp, #0] 8004430: 2300 movs r3, #0 8004432: 2101 movs r1, #1 8004434: 2004 movs r0, #4 8004436: f000 fb9b bl 8004b70 800443a: 4603 mov r3, r0 800443c: 2b00 cmp r3, #0 800443e: d114 bne.n 800446a m4st=motStop; 8004440: 4b0e ldr r3, [pc, #56] @ (800447c ) 8004442: 2204 movs r2, #4 8004444: 701a strb r2, [r3, #0] } break; 8004446: e010 b.n 800446a case motStop: default: SetMotPerc(M4,FW,0); 8004448: 2200 movs r2, #0 800444a: 2100 movs r1, #0 800444c: 2004 movs r0, #4 800444e: f000 fa0f bl 8004870 SetMotPerc(M4,BW,0); 8004452: 2200 movs r2, #0 8004454: 2101 movs r1, #1 8004456: 2004 movs r0, #4 8004458: f000 fa0a bl 8004870 break; 800445c: e006 b.n 800446c break; 800445e: bf00 nop 8004460: e004 b.n 800446c break; 8004462: bf00 nop 8004464: e002 b.n 800446c break; 8004466: bf00 nop 8004468: e000 b.n 800446c break; 800446a: bf00 nop } return m4st; 800446c: 4b03 ldr r3, [pc, #12] @ (800447c ) 800446e: 781b ldrb r3, [r3, #0] } 8004470: 4618 mov r0, r3 8004472: 3768 adds r7, #104 @ 0x68 8004474: 46bd mov sp, r7 8004476: bd80 pop {r7, pc} 8004478: 2000000e .word 0x2000000e 800447c: 20000469 .word 0x20000469 8004480: 0800f45c .word 0x0800f45c 8004484: 200003a8 .word 0x200003a8 8004488: 200003fc .word 0x200003fc 800448c: 20000444 .word 0x20000444 8004490: 2000044c .word 0x2000044c 8004494: 2000040e .word 0x2000040e 8004498: 20000418 .word 0x20000418 800449c: 20000446 .word 0x20000446 080044a0 : extern volatile uint16_t rtramp[4]; extern uint16_t mrampstart[4]; extern UART_HandleTypeDef huart1; bool IsPwmRunning(TIM_HandleTypeDef *htim, uint32_t Channel) { 80044a0: b580 push {r7, lr} 80044a2: b084 sub sp, #16 80044a4: af00 add r7, sp, #0 80044a6: 6078 str r0, [r7, #4] 80044a8: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef chState = HAL_TIM_GetChannelState(htim, Channel); 80044aa: 6839 ldr r1, [r7, #0] 80044ac: 6878 ldr r0, [r7, #4] 80044ae: f004 fe86 bl 80091be 80044b2: 4603 mov r3, r0 80044b4: 73fb strb r3, [r7, #15] return (chState == HAL_TIM_CHANNEL_STATE_BUSY); 80044b6: 7bfb ldrb r3, [r7, #15] 80044b8: 2b02 cmp r3, #2 80044ba: bf0c ite eq 80044bc: 2301 moveq r3, #1 80044be: 2300 movne r3, #0 80044c0: b2db uxtb r3, r3 } 80044c2: 4618 mov r0, r3 80044c4: 3710 adds r7, #16 80044c6: 46bd mov sp, r7 80044c8: bd80 pop {r7, pc} 080044ca : void StopMot(TIM_HandleTypeDef *htim,uint32_t Channel){ 80044ca: b580 push {r7, lr} 80044cc: b082 sub sp, #8 80044ce: af00 add r7, sp, #0 80044d0: 6078 str r0, [r7, #4] 80044d2: 6039 str r1, [r7, #0] HAL_TIM_PWM_Stop(htim, Channel); 80044d4: 6839 ldr r1, [r7, #0] 80044d6: 6878 ldr r0, [r7, #4] 80044d8: f004 fc84 bl 8008de4 } 80044dc: bf00 nop 80044de: 3708 adds r7, #8 80044e0: 46bd mov sp, r7 80044e2: bd80 pop {r7, pc} 080044e4 : void StartMot(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){ 80044e4: b580 push {r7, lr} 80044e6: b084 sub sp, #16 80044e8: af00 add r7, sp, #0 80044ea: 60f8 str r0, [r7, #12] 80044ec: 60b9 str r1, [r7, #8] 80044ee: 4613 mov r3, r2 80044f0: 80fb strh r3, [r7, #6] __HAL_TIM_SET_COMPARE(htim, Channel, pwmval); 80044f2: 68bb ldr r3, [r7, #8] 80044f4: 2b00 cmp r3, #0 80044f6: d104 bne.n 8004502 80044f8: 68fb ldr r3, [r7, #12] 80044fa: 681b ldr r3, [r3, #0] 80044fc: 88fa ldrh r2, [r7, #6] 80044fe: 635a str r2, [r3, #52] @ 0x34 8004500: e013 b.n 800452a 8004502: 68bb ldr r3, [r7, #8] 8004504: 2b04 cmp r3, #4 8004506: d104 bne.n 8004512 8004508: 68fb ldr r3, [r7, #12] 800450a: 681a ldr r2, [r3, #0] 800450c: 88fb ldrh r3, [r7, #6] 800450e: 6393 str r3, [r2, #56] @ 0x38 8004510: e00b b.n 800452a 8004512: 68bb ldr r3, [r7, #8] 8004514: 2b08 cmp r3, #8 8004516: d104 bne.n 8004522 8004518: 68fb ldr r3, [r7, #12] 800451a: 681a ldr r2, [r3, #0] 800451c: 88fb ldrh r3, [r7, #6] 800451e: 63d3 str r3, [r2, #60] @ 0x3c 8004520: e003 b.n 800452a 8004522: 68fb ldr r3, [r7, #12] 8004524: 681a ldr r2, [r3, #0] 8004526: 88fb ldrh r3, [r7, #6] 8004528: 6413 str r3, [r2, #64] @ 0x40 HAL_TIM_PWM_Start(htim, Channel); 800452a: 68b9 ldr r1, [r7, #8] 800452c: 68f8 ldr r0, [r7, #12] 800452e: f004 fbb7 bl 8008ca0 } 8004532: bf00 nop 8004534: 3710 adds r7, #16 8004536: 46bd mov sp, r7 8004538: bd80 pop {r7, pc} 0800453a : void SetMotPwm(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){ 800453a: b480 push {r7} 800453c: b085 sub sp, #20 800453e: af00 add r7, sp, #0 8004540: 60f8 str r0, [r7, #12] 8004542: 60b9 str r1, [r7, #8] 8004544: 4613 mov r3, r2 8004546: 80fb strh r3, [r7, #6] __HAL_TIM_SET_COMPARE(htim, Channel, pwmval); 8004548: 68bb ldr r3, [r7, #8] 800454a: 2b00 cmp r3, #0 800454c: d104 bne.n 8004558 800454e: 68fb ldr r3, [r7, #12] 8004550: 681b ldr r3, [r3, #0] 8004552: 88fa ldrh r2, [r7, #6] 8004554: 635a str r2, [r3, #52] @ 0x34 } 8004556: e013 b.n 8004580 __HAL_TIM_SET_COMPARE(htim, Channel, pwmval); 8004558: 68bb ldr r3, [r7, #8] 800455a: 2b04 cmp r3, #4 800455c: d104 bne.n 8004568 800455e: 68fb ldr r3, [r7, #12] 8004560: 681a ldr r2, [r3, #0] 8004562: 88fb ldrh r3, [r7, #6] 8004564: 6393 str r3, [r2, #56] @ 0x38 } 8004566: e00b b.n 8004580 __HAL_TIM_SET_COMPARE(htim, Channel, pwmval); 8004568: 68bb ldr r3, [r7, #8] 800456a: 2b08 cmp r3, #8 800456c: d104 bne.n 8004578 800456e: 68fb ldr r3, [r7, #12] 8004570: 681a ldr r2, [r3, #0] 8004572: 88fb ldrh r3, [r7, #6] 8004574: 63d3 str r3, [r2, #60] @ 0x3c } 8004576: e003 b.n 8004580 __HAL_TIM_SET_COMPARE(htim, Channel, pwmval); 8004578: 68fb ldr r3, [r7, #12] 800457a: 681a ldr r2, [r3, #0] 800457c: 88fb ldrh r3, [r7, #6] 800457e: 6413 str r3, [r2, #64] @ 0x40 } 8004580: bf00 nop 8004582: 3714 adds r7, #20 8004584: 46bd mov sp, r7 8004586: bc80 pop {r7} 8004588: 4770 bx lr ... 0800458c : void SetMot(uint8_t mot,uint8_t dir,uint16_t pwmval){ 800458c: b580 push {r7, lr} 800458e: b082 sub sp, #8 8004590: af00 add r7, sp, #0 8004592: 4603 mov r3, r0 8004594: 71fb strb r3, [r7, #7] 8004596: 460b mov r3, r1 8004598: 71bb strb r3, [r7, #6] 800459a: 4613 mov r3, r2 800459c: 80bb strh r3, [r7, #4] switch(mot){ 800459e: 79fb ldrb r3, [r7, #7] 80045a0: 3b01 subs r3, #1 80045a2: 2b03 cmp r3, #3 80045a4: f200 8158 bhi.w 8004858 80045a8: a201 add r2, pc, #4 @ (adr r2, 80045b0 ) 80045aa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80045ae: bf00 nop 80045b0: 080045c1 .word 0x080045c1 80045b4: 08004663 .word 0x08004663 80045b8: 08004705 .word 0x08004705 80045bc: 080047af .word 0x080047af case 1: if(dir==FW){ 80045c0: 79bb ldrb r3, [r7, #6] 80045c2: 2b00 cmp r3, #0 80045c4: d126 bne.n 8004614 if(pwmval==0){ 80045c6: 88bb ldrh r3, [r7, #4] 80045c8: 2b00 cmp r3, #0 80045ca: d109 bne.n 80045e0 StopMot(timMot1,FWMot1); 80045cc: 2100 movs r1, #0 80045ce: 48a5 ldr r0, [pc, #660] @ (8004864 ) 80045d0: f7ff ff7b bl 80044ca HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET); 80045d4: 2200 movs r2, #0 80045d6: 2102 movs r1, #2 80045d8: 48a3 ldr r0, [pc, #652] @ (8004868 ) 80045da: f002 f878 bl 80066ce HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET); StartMot(timMot1,BWMot1,pwmval); } } break; 80045de: e13c b.n 800485a }else if(IsPwmRunning(timMot1, FWMot1)){ 80045e0: 2100 movs r1, #0 80045e2: 48a0 ldr r0, [pc, #640] @ (8004864 ) 80045e4: f7ff ff5c bl 80044a0 80045e8: 4603 mov r3, r0 80045ea: 2b00 cmp r3, #0 80045ec: d006 beq.n 80045fc SetMotPwm(timMot1,FWMot1,pwmval); 80045ee: 88bb ldrh r3, [r7, #4] 80045f0: 461a mov r2, r3 80045f2: 2100 movs r1, #0 80045f4: 489b ldr r0, [pc, #620] @ (8004864 ) 80045f6: f7ff ffa0 bl 800453a break; 80045fa: e12e b.n 800485a HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET); 80045fc: 2201 movs r2, #1 80045fe: 2102 movs r1, #2 8004600: 4899 ldr r0, [pc, #612] @ (8004868 ) 8004602: f002 f864 bl 80066ce StartMot(timMot1,FWMot1,pwmval); 8004606: 88bb ldrh r3, [r7, #4] 8004608: 461a mov r2, r3 800460a: 2100 movs r1, #0 800460c: 4895 ldr r0, [pc, #596] @ (8004864 ) 800460e: f7ff ff69 bl 80044e4 break; 8004612: e122 b.n 800485a if(pwmval==0){ 8004614: 88bb ldrh r3, [r7, #4] 8004616: 2b00 cmp r3, #0 8004618: d109 bne.n 800462e StopMot(timMot1,BWMot1); 800461a: 2104 movs r1, #4 800461c: 4891 ldr r0, [pc, #580] @ (8004864 ) 800461e: f7ff ff54 bl 80044ca HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET); 8004622: 2200 movs r2, #0 8004624: 2102 movs r1, #2 8004626: 4890 ldr r0, [pc, #576] @ (8004868 ) 8004628: f002 f851 bl 80066ce break; 800462c: e115 b.n 800485a }else if(IsPwmRunning(timMot1, BWMot1)){ 800462e: 2104 movs r1, #4 8004630: 488c ldr r0, [pc, #560] @ (8004864 ) 8004632: f7ff ff35 bl 80044a0 8004636: 4603 mov r3, r0 8004638: 2b00 cmp r3, #0 800463a: d006 beq.n 800464a SetMotPwm(timMot1,BWMot1,pwmval); 800463c: 88bb ldrh r3, [r7, #4] 800463e: 461a mov r2, r3 8004640: 2104 movs r1, #4 8004642: 4888 ldr r0, [pc, #544] @ (8004864 ) 8004644: f7ff ff79 bl 800453a break; 8004648: e107 b.n 800485a HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET); 800464a: 2201 movs r2, #1 800464c: 2102 movs r1, #2 800464e: 4886 ldr r0, [pc, #536] @ (8004868 ) 8004650: f002 f83d bl 80066ce StartMot(timMot1,BWMot1,pwmval); 8004654: 88bb ldrh r3, [r7, #4] 8004656: 461a mov r2, r3 8004658: 2104 movs r1, #4 800465a: 4882 ldr r0, [pc, #520] @ (8004864 ) 800465c: f7ff ff42 bl 80044e4 break; 8004660: e0fb b.n 800485a case 2: if(dir==FW){ 8004662: 79bb ldrb r3, [r7, #6] 8004664: 2b00 cmp r3, #0 8004666: d126 bne.n 80046b6 if(pwmval==0){ 8004668: 88bb ldrh r3, [r7, #4] 800466a: 2b00 cmp r3, #0 800466c: d109 bne.n 8004682 StopMot(timMot2,FWMot2); 800466e: 2108 movs r1, #8 8004670: 487c ldr r0, [pc, #496] @ (8004864 ) 8004672: f7ff ff2a bl 80044ca HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET); 8004676: 2200 movs r2, #0 8004678: 2104 movs r1, #4 800467a: 487b ldr r0, [pc, #492] @ (8004868 ) 800467c: f002 f827 bl 80066ce }else{ HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET); StartMot(timMot2,BWMot2,pwmval); } } break; 8004680: e0eb b.n 800485a }else if(IsPwmRunning(timMot2, FWMot2)){ 8004682: 2108 movs r1, #8 8004684: 4877 ldr r0, [pc, #476] @ (8004864 ) 8004686: f7ff ff0b bl 80044a0 800468a: 4603 mov r3, r0 800468c: 2b00 cmp r3, #0 800468e: d006 beq.n 800469e SetMotPwm(timMot2,FWMot2,pwmval); 8004690: 88bb ldrh r3, [r7, #4] 8004692: 461a mov r2, r3 8004694: 2108 movs r1, #8 8004696: 4873 ldr r0, [pc, #460] @ (8004864 ) 8004698: f7ff ff4f bl 800453a break; 800469c: e0dd b.n 800485a HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET); 800469e: 2201 movs r2, #1 80046a0: 2104 movs r1, #4 80046a2: 4871 ldr r0, [pc, #452] @ (8004868 ) 80046a4: f002 f813 bl 80066ce StartMot(timMot2,FWMot2,pwmval); 80046a8: 88bb ldrh r3, [r7, #4] 80046aa: 461a mov r2, r3 80046ac: 2108 movs r1, #8 80046ae: 486d ldr r0, [pc, #436] @ (8004864 ) 80046b0: f7ff ff18 bl 80044e4 break; 80046b4: e0d1 b.n 800485a if(pwmval==0){ 80046b6: 88bb ldrh r3, [r7, #4] 80046b8: 2b00 cmp r3, #0 80046ba: d109 bne.n 80046d0 StopMot(timMot2,BWMot2); 80046bc: 210c movs r1, #12 80046be: 4869 ldr r0, [pc, #420] @ (8004864 ) 80046c0: f7ff ff03 bl 80044ca HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET); 80046c4: 2200 movs r2, #0 80046c6: 2104 movs r1, #4 80046c8: 4867 ldr r0, [pc, #412] @ (8004868 ) 80046ca: f002 f800 bl 80066ce break; 80046ce: e0c4 b.n 800485a }else if(IsPwmRunning(timMot2, BWMot2)){ 80046d0: 210c movs r1, #12 80046d2: 4864 ldr r0, [pc, #400] @ (8004864 ) 80046d4: f7ff fee4 bl 80044a0 80046d8: 4603 mov r3, r0 80046da: 2b00 cmp r3, #0 80046dc: d006 beq.n 80046ec SetMotPwm(timMot2,BWMot2,pwmval); 80046de: 88bb ldrh r3, [r7, #4] 80046e0: 461a mov r2, r3 80046e2: 210c movs r1, #12 80046e4: 485f ldr r0, [pc, #380] @ (8004864 ) 80046e6: f7ff ff28 bl 800453a break; 80046ea: e0b6 b.n 800485a HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET); 80046ec: 2201 movs r2, #1 80046ee: 2104 movs r1, #4 80046f0: 485d ldr r0, [pc, #372] @ (8004868 ) 80046f2: f001 ffec bl 80066ce StartMot(timMot2,BWMot2,pwmval); 80046f6: 88bb ldrh r3, [r7, #4] 80046f8: 461a mov r2, r3 80046fa: 210c movs r1, #12 80046fc: 4859 ldr r0, [pc, #356] @ (8004864 ) 80046fe: f7ff fef1 bl 80044e4 break; 8004702: e0aa b.n 800485a case 3: if(dir==FW){ 8004704: 79bb ldrb r3, [r7, #6] 8004706: 2b00 cmp r3, #0 8004708: d128 bne.n 800475c if(pwmval==0){ 800470a: 88bb ldrh r3, [r7, #4] 800470c: 2b00 cmp r3, #0 800470e: d10a bne.n 8004726 StopMot(timMot3,FWMot3); 8004710: 2100 movs r1, #0 8004712: 4856 ldr r0, [pc, #344] @ (800486c ) 8004714: f7ff fed9 bl 80044ca HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET); 8004718: 2200 movs r2, #0 800471a: f44f 6180 mov.w r1, #1024 @ 0x400 800471e: 4852 ldr r0, [pc, #328] @ (8004868 ) 8004720: f001 ffd5 bl 80066ce }else{ HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET); StartMot(timMot3,BWMot3,pwmval); } } break; 8004724: e099 b.n 800485a }else if(IsPwmRunning(timMot3, FWMot3)){ 8004726: 2100 movs r1, #0 8004728: 4850 ldr r0, [pc, #320] @ (800486c ) 800472a: f7ff feb9 bl 80044a0 800472e: 4603 mov r3, r0 8004730: 2b00 cmp r3, #0 8004732: d006 beq.n 8004742 SetMotPwm(timMot3,FWMot3,pwmval); 8004734: 88bb ldrh r3, [r7, #4] 8004736: 461a mov r2, r3 8004738: 2100 movs r1, #0 800473a: 484c ldr r0, [pc, #304] @ (800486c ) 800473c: f7ff fefd bl 800453a break; 8004740: e08b b.n 800485a HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET); 8004742: 2201 movs r2, #1 8004744: f44f 6180 mov.w r1, #1024 @ 0x400 8004748: 4847 ldr r0, [pc, #284] @ (8004868 ) 800474a: f001 ffc0 bl 80066ce StartMot(timMot3,FWMot3,pwmval); 800474e: 88bb ldrh r3, [r7, #4] 8004750: 461a mov r2, r3 8004752: 2100 movs r1, #0 8004754: 4845 ldr r0, [pc, #276] @ (800486c ) 8004756: f7ff fec5 bl 80044e4 break; 800475a: e07e b.n 800485a if(pwmval==0){ 800475c: 88bb ldrh r3, [r7, #4] 800475e: 2b00 cmp r3, #0 8004760: d10a bne.n 8004778 StopMot(timMot3,BWMot3); 8004762: 2104 movs r1, #4 8004764: 4841 ldr r0, [pc, #260] @ (800486c ) 8004766: f7ff feb0 bl 80044ca HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET); 800476a: 2200 movs r2, #0 800476c: f44f 6180 mov.w r1, #1024 @ 0x400 8004770: 483d ldr r0, [pc, #244] @ (8004868 ) 8004772: f001 ffac bl 80066ce break; 8004776: e070 b.n 800485a }else if(IsPwmRunning(timMot3, BWMot3)){ 8004778: 2104 movs r1, #4 800477a: 483c ldr r0, [pc, #240] @ (800486c ) 800477c: f7ff fe90 bl 80044a0 8004780: 4603 mov r3, r0 8004782: 2b00 cmp r3, #0 8004784: d006 beq.n 8004794 SetMotPwm(timMot3,BWMot3,pwmval); 8004786: 88bb ldrh r3, [r7, #4] 8004788: 461a mov r2, r3 800478a: 2104 movs r1, #4 800478c: 4837 ldr r0, [pc, #220] @ (800486c ) 800478e: f7ff fed4 bl 800453a break; 8004792: e062 b.n 800485a HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET); 8004794: 2201 movs r2, #1 8004796: f44f 6180 mov.w r1, #1024 @ 0x400 800479a: 4833 ldr r0, [pc, #204] @ (8004868 ) 800479c: f001 ff97 bl 80066ce StartMot(timMot3,BWMot3,pwmval); 80047a0: 88bb ldrh r3, [r7, #4] 80047a2: 461a mov r2, r3 80047a4: 2104 movs r1, #4 80047a6: 4831 ldr r0, [pc, #196] @ (800486c ) 80047a8: f7ff fe9c bl 80044e4 break; 80047ac: e055 b.n 800485a case 4: if(dir==FW){ 80047ae: 79bb ldrb r3, [r7, #6] 80047b0: 2b00 cmp r3, #0 80047b2: d128 bne.n 8004806 if(pwmval==0){ 80047b4: 88bb ldrh r3, [r7, #4] 80047b6: 2b00 cmp r3, #0 80047b8: d10a bne.n 80047d0 StopMot(timMot4,FWMot4); 80047ba: 2108 movs r1, #8 80047bc: 482b ldr r0, [pc, #172] @ (800486c ) 80047be: f7ff fe84 bl 80044ca HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET); 80047c2: 2200 movs r2, #0 80047c4: f44f 6100 mov.w r1, #2048 @ 0x800 80047c8: 4827 ldr r0, [pc, #156] @ (8004868 ) 80047ca: f001 ff80 bl 80066ce }else{ HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET); StartMot(timMot4,BWMot4,pwmval); } } break; 80047ce: e044 b.n 800485a }else if(IsPwmRunning(timMot4, FWMot4)){ 80047d0: 2108 movs r1, #8 80047d2: 4826 ldr r0, [pc, #152] @ (800486c ) 80047d4: f7ff fe64 bl 80044a0 80047d8: 4603 mov r3, r0 80047da: 2b00 cmp r3, #0 80047dc: d006 beq.n 80047ec SetMotPwm(timMot4,FWMot4,pwmval); 80047de: 88bb ldrh r3, [r7, #4] 80047e0: 461a mov r2, r3 80047e2: 2108 movs r1, #8 80047e4: 4821 ldr r0, [pc, #132] @ (800486c ) 80047e6: f7ff fea8 bl 800453a break; 80047ea: e036 b.n 800485a HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET); 80047ec: 2201 movs r2, #1 80047ee: f44f 6100 mov.w r1, #2048 @ 0x800 80047f2: 481d ldr r0, [pc, #116] @ (8004868 ) 80047f4: f001 ff6b bl 80066ce StartMot(timMot4,FWMot4,pwmval); 80047f8: 88bb ldrh r3, [r7, #4] 80047fa: 461a mov r2, r3 80047fc: 2108 movs r1, #8 80047fe: 481b ldr r0, [pc, #108] @ (800486c ) 8004800: f7ff fe70 bl 80044e4 break; 8004804: e029 b.n 800485a if(pwmval==0){ 8004806: 88bb ldrh r3, [r7, #4] 8004808: 2b00 cmp r3, #0 800480a: d10a bne.n 8004822 StopMot(timMot4,BWMot4); 800480c: 210c movs r1, #12 800480e: 4817 ldr r0, [pc, #92] @ (800486c ) 8004810: f7ff fe5b bl 80044ca HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET); 8004814: 2200 movs r2, #0 8004816: f44f 6100 mov.w r1, #2048 @ 0x800 800481a: 4813 ldr r0, [pc, #76] @ (8004868 ) 800481c: f001 ff57 bl 80066ce break; 8004820: e01b b.n 800485a }else if(IsPwmRunning(timMot4, BWMot4)){ 8004822: 210c movs r1, #12 8004824: 4811 ldr r0, [pc, #68] @ (800486c ) 8004826: f7ff fe3b bl 80044a0 800482a: 4603 mov r3, r0 800482c: 2b00 cmp r3, #0 800482e: d006 beq.n 800483e SetMotPwm(timMot4,BWMot4,pwmval); 8004830: 88bb ldrh r3, [r7, #4] 8004832: 461a mov r2, r3 8004834: 210c movs r1, #12 8004836: 480d ldr r0, [pc, #52] @ (800486c ) 8004838: f7ff fe7f bl 800453a break; 800483c: e00d b.n 800485a HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET); 800483e: 2201 movs r2, #1 8004840: f44f 6100 mov.w r1, #2048 @ 0x800 8004844: 4808 ldr r0, [pc, #32] @ (8004868 ) 8004846: f001 ff42 bl 80066ce StartMot(timMot4,BWMot4,pwmval); 800484a: 88bb ldrh r3, [r7, #4] 800484c: 461a mov r2, r3 800484e: 210c movs r1, #12 8004850: 4806 ldr r0, [pc, #24] @ (800486c ) 8004852: f7ff fe47 bl 80044e4 break; 8004856: e000 b.n 800485a default: break; 8004858: bf00 nop } } 800485a: bf00 nop 800485c: 3708 adds r7, #8 800485e: 46bd mov sp, r7 8004860: bd80 pop {r7, pc} 8004862: bf00 nop 8004864: 20000318 .word 0x20000318 8004868: 40010c00 .word 0x40010c00 800486c: 20000360 .word 0x20000360 08004870 : void SetMotPerc(uint8_t mot,uint8_t dir,uint8_t perc){ 8004870: b580 push {r7, lr} 8004872: b084 sub sp, #16 8004874: af00 add r7, sp, #0 8004876: 4603 mov r3, r0 8004878: 71fb strb r3, [r7, #7] 800487a: 460b mov r3, r1 800487c: 71bb strb r3, [r7, #6] 800487e: 4613 mov r3, r2 8004880: 717b strb r3, [r7, #5] uint16_t pwmval; uint32_t tempval; tempval=perc; 8004882: 797b ldrb r3, [r7, #5] 8004884: 60fb str r3, [r7, #12] tempval*=16384; 8004886: 68fb ldr r3, [r7, #12] 8004888: 039b lsls r3, r3, #14 800488a: 60fb str r3, [r7, #12] tempval/=100; 800488c: 68fb ldr r3, [r7, #12] 800488e: 4ab4 ldr r2, [pc, #720] @ (8004b60 ) 8004890: fba2 2303 umull r2, r3, r2, r3 8004894: 095b lsrs r3, r3, #5 8004896: 60fb str r3, [r7, #12] pwmval=(uint16_t)tempval; 8004898: 68fb ldr r3, [r7, #12] 800489a: 817b strh r3, [r7, #10] switch(mot){ 800489c: 79fb ldrb r3, [r7, #7] 800489e: 3b01 subs r3, #1 80048a0: 2b03 cmp r3, #3 80048a2: f200 8157 bhi.w 8004b54 80048a6: a201 add r2, pc, #4 @ (adr r2, 80048ac ) 80048a8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80048ac: 080048bd .word 0x080048bd 80048b0: 0800495f .word 0x0800495f 80048b4: 08004a01 .word 0x08004a01 80048b8: 08004aab .word 0x08004aab case 1: if(dir==FW){ 80048bc: 79bb ldrb r3, [r7, #6] 80048be: 2b00 cmp r3, #0 80048c0: d126 bne.n 8004910 if(pwmval==0){ 80048c2: 897b ldrh r3, [r7, #10] 80048c4: 2b00 cmp r3, #0 80048c6: d109 bne.n 80048dc StopMot(timMot1,FWMot1); 80048c8: 2100 movs r1, #0 80048ca: 48a6 ldr r0, [pc, #664] @ (8004b64 ) 80048cc: f7ff fdfd bl 80044ca HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET); 80048d0: 2200 movs r2, #0 80048d2: 2102 movs r1, #2 80048d4: 48a4 ldr r0, [pc, #656] @ (8004b68 ) 80048d6: f001 fefa bl 80066ce HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET); StartMot(timMot1,BWMot1,pwmval); } } break; 80048da: e13c b.n 8004b56 }else if(IsPwmRunning(timMot1, FWMot1)){ 80048dc: 2100 movs r1, #0 80048de: 48a1 ldr r0, [pc, #644] @ (8004b64 ) 80048e0: f7ff fdde bl 80044a0 80048e4: 4603 mov r3, r0 80048e6: 2b00 cmp r3, #0 80048e8: d006 beq.n 80048f8 SetMotPwm(timMot1,FWMot1,pwmval); 80048ea: 897b ldrh r3, [r7, #10] 80048ec: 461a mov r2, r3 80048ee: 2100 movs r1, #0 80048f0: 489c ldr r0, [pc, #624] @ (8004b64 ) 80048f2: f7ff fe22 bl 800453a break; 80048f6: e12e b.n 8004b56 HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET); 80048f8: 2201 movs r2, #1 80048fa: 2102 movs r1, #2 80048fc: 489a ldr r0, [pc, #616] @ (8004b68 ) 80048fe: f001 fee6 bl 80066ce StartMot(timMot1,FWMot1,pwmval); 8004902: 897b ldrh r3, [r7, #10] 8004904: 461a mov r2, r3 8004906: 2100 movs r1, #0 8004908: 4896 ldr r0, [pc, #600] @ (8004b64 ) 800490a: f7ff fdeb bl 80044e4 break; 800490e: e122 b.n 8004b56 if(pwmval==0){ 8004910: 897b ldrh r3, [r7, #10] 8004912: 2b00 cmp r3, #0 8004914: d109 bne.n 800492a StopMot(timMot1,BWMot1); 8004916: 2104 movs r1, #4 8004918: 4892 ldr r0, [pc, #584] @ (8004b64 ) 800491a: f7ff fdd6 bl 80044ca HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET); 800491e: 2200 movs r2, #0 8004920: 2102 movs r1, #2 8004922: 4891 ldr r0, [pc, #580] @ (8004b68 ) 8004924: f001 fed3 bl 80066ce break; 8004928: e115 b.n 8004b56 }else if(IsPwmRunning(timMot1, BWMot1)){ 800492a: 2104 movs r1, #4 800492c: 488d ldr r0, [pc, #564] @ (8004b64 ) 800492e: f7ff fdb7 bl 80044a0 8004932: 4603 mov r3, r0 8004934: 2b00 cmp r3, #0 8004936: d006 beq.n 8004946 SetMotPwm(timMot1,BWMot1,pwmval); 8004938: 897b ldrh r3, [r7, #10] 800493a: 461a mov r2, r3 800493c: 2104 movs r1, #4 800493e: 4889 ldr r0, [pc, #548] @ (8004b64 ) 8004940: f7ff fdfb bl 800453a break; 8004944: e107 b.n 8004b56 HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET); 8004946: 2201 movs r2, #1 8004948: 2102 movs r1, #2 800494a: 4887 ldr r0, [pc, #540] @ (8004b68 ) 800494c: f001 febf bl 80066ce StartMot(timMot1,BWMot1,pwmval); 8004950: 897b ldrh r3, [r7, #10] 8004952: 461a mov r2, r3 8004954: 2104 movs r1, #4 8004956: 4883 ldr r0, [pc, #524] @ (8004b64 ) 8004958: f7ff fdc4 bl 80044e4 break; 800495c: e0fb b.n 8004b56 case 2: if(dir==FW){ 800495e: 79bb ldrb r3, [r7, #6] 8004960: 2b00 cmp r3, #0 8004962: d126 bne.n 80049b2 if(pwmval==0){ 8004964: 897b ldrh r3, [r7, #10] 8004966: 2b00 cmp r3, #0 8004968: d109 bne.n 800497e StopMot(timMot2,FWMot2); 800496a: 2108 movs r1, #8 800496c: 487d ldr r0, [pc, #500] @ (8004b64 ) 800496e: f7ff fdac bl 80044ca HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET); 8004972: 2200 movs r2, #0 8004974: 2104 movs r1, #4 8004976: 487c ldr r0, [pc, #496] @ (8004b68 ) 8004978: f001 fea9 bl 80066ce }else{ HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET); StartMot(timMot2,BWMot2,pwmval); } } break; 800497c: e0eb b.n 8004b56 }else if(IsPwmRunning(timMot2, FWMot2)){ 800497e: 2108 movs r1, #8 8004980: 4878 ldr r0, [pc, #480] @ (8004b64 ) 8004982: f7ff fd8d bl 80044a0 8004986: 4603 mov r3, r0 8004988: 2b00 cmp r3, #0 800498a: d006 beq.n 800499a SetMotPwm(timMot2,FWMot2,pwmval); 800498c: 897b ldrh r3, [r7, #10] 800498e: 461a mov r2, r3 8004990: 2108 movs r1, #8 8004992: 4874 ldr r0, [pc, #464] @ (8004b64 ) 8004994: f7ff fdd1 bl 800453a break; 8004998: e0dd b.n 8004b56 HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET); 800499a: 2201 movs r2, #1 800499c: 2104 movs r1, #4 800499e: 4872 ldr r0, [pc, #456] @ (8004b68 ) 80049a0: f001 fe95 bl 80066ce StartMot(timMot2,FWMot2,pwmval); 80049a4: 897b ldrh r3, [r7, #10] 80049a6: 461a mov r2, r3 80049a8: 2108 movs r1, #8 80049aa: 486e ldr r0, [pc, #440] @ (8004b64 ) 80049ac: f7ff fd9a bl 80044e4 break; 80049b0: e0d1 b.n 8004b56 if(pwmval==0){ 80049b2: 897b ldrh r3, [r7, #10] 80049b4: 2b00 cmp r3, #0 80049b6: d109 bne.n 80049cc StopMot(timMot2,BWMot2); 80049b8: 210c movs r1, #12 80049ba: 486a ldr r0, [pc, #424] @ (8004b64 ) 80049bc: f7ff fd85 bl 80044ca HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET); 80049c0: 2200 movs r2, #0 80049c2: 2104 movs r1, #4 80049c4: 4868 ldr r0, [pc, #416] @ (8004b68 ) 80049c6: f001 fe82 bl 80066ce break; 80049ca: e0c4 b.n 8004b56 }else if(IsPwmRunning(timMot2, BWMot2)){ 80049cc: 210c movs r1, #12 80049ce: 4865 ldr r0, [pc, #404] @ (8004b64 ) 80049d0: f7ff fd66 bl 80044a0 80049d4: 4603 mov r3, r0 80049d6: 2b00 cmp r3, #0 80049d8: d006 beq.n 80049e8 SetMotPwm(timMot2,BWMot2,pwmval); 80049da: 897b ldrh r3, [r7, #10] 80049dc: 461a mov r2, r3 80049de: 210c movs r1, #12 80049e0: 4860 ldr r0, [pc, #384] @ (8004b64 ) 80049e2: f7ff fdaa bl 800453a break; 80049e6: e0b6 b.n 8004b56 HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET); 80049e8: 2201 movs r2, #1 80049ea: 2104 movs r1, #4 80049ec: 485e ldr r0, [pc, #376] @ (8004b68 ) 80049ee: f001 fe6e bl 80066ce StartMot(timMot2,BWMot2,pwmval); 80049f2: 897b ldrh r3, [r7, #10] 80049f4: 461a mov r2, r3 80049f6: 210c movs r1, #12 80049f8: 485a ldr r0, [pc, #360] @ (8004b64 ) 80049fa: f7ff fd73 bl 80044e4 break; 80049fe: e0aa b.n 8004b56 case 3: if(dir==FW){ 8004a00: 79bb ldrb r3, [r7, #6] 8004a02: 2b00 cmp r3, #0 8004a04: d128 bne.n 8004a58 if(pwmval==0){ 8004a06: 897b ldrh r3, [r7, #10] 8004a08: 2b00 cmp r3, #0 8004a0a: d10a bne.n 8004a22 StopMot(timMot3,FWMot3); 8004a0c: 2100 movs r1, #0 8004a0e: 4857 ldr r0, [pc, #348] @ (8004b6c ) 8004a10: f7ff fd5b bl 80044ca HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET); 8004a14: 2200 movs r2, #0 8004a16: f44f 6180 mov.w r1, #1024 @ 0x400 8004a1a: 4853 ldr r0, [pc, #332] @ (8004b68 ) 8004a1c: f001 fe57 bl 80066ce }else{ HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET); StartMot(timMot3,BWMot3,pwmval); } } break; 8004a20: e099 b.n 8004b56 }else if(IsPwmRunning(timMot3, FWMot3)){ 8004a22: 2100 movs r1, #0 8004a24: 4851 ldr r0, [pc, #324] @ (8004b6c ) 8004a26: f7ff fd3b bl 80044a0 8004a2a: 4603 mov r3, r0 8004a2c: 2b00 cmp r3, #0 8004a2e: d006 beq.n 8004a3e SetMotPwm(timMot3,FWMot3,pwmval); 8004a30: 897b ldrh r3, [r7, #10] 8004a32: 461a mov r2, r3 8004a34: 2100 movs r1, #0 8004a36: 484d ldr r0, [pc, #308] @ (8004b6c ) 8004a38: f7ff fd7f bl 800453a break; 8004a3c: e08b b.n 8004b56 HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET); 8004a3e: 2201 movs r2, #1 8004a40: f44f 6180 mov.w r1, #1024 @ 0x400 8004a44: 4848 ldr r0, [pc, #288] @ (8004b68 ) 8004a46: f001 fe42 bl 80066ce StartMot(timMot3,FWMot3,pwmval); 8004a4a: 897b ldrh r3, [r7, #10] 8004a4c: 461a mov r2, r3 8004a4e: 2100 movs r1, #0 8004a50: 4846 ldr r0, [pc, #280] @ (8004b6c ) 8004a52: f7ff fd47 bl 80044e4 break; 8004a56: e07e b.n 8004b56 if(pwmval==0){ 8004a58: 897b ldrh r3, [r7, #10] 8004a5a: 2b00 cmp r3, #0 8004a5c: d10a bne.n 8004a74 StopMot(timMot3,BWMot3); 8004a5e: 2104 movs r1, #4 8004a60: 4842 ldr r0, [pc, #264] @ (8004b6c ) 8004a62: f7ff fd32 bl 80044ca HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET); 8004a66: 2200 movs r2, #0 8004a68: f44f 6180 mov.w r1, #1024 @ 0x400 8004a6c: 483e ldr r0, [pc, #248] @ (8004b68 ) 8004a6e: f001 fe2e bl 80066ce break; 8004a72: e070 b.n 8004b56 }else if(IsPwmRunning(timMot3, BWMot3)){ 8004a74: 2104 movs r1, #4 8004a76: 483d ldr r0, [pc, #244] @ (8004b6c ) 8004a78: f7ff fd12 bl 80044a0 8004a7c: 4603 mov r3, r0 8004a7e: 2b00 cmp r3, #0 8004a80: d006 beq.n 8004a90 SetMotPwm(timMot3,BWMot3,pwmval); 8004a82: 897b ldrh r3, [r7, #10] 8004a84: 461a mov r2, r3 8004a86: 2104 movs r1, #4 8004a88: 4838 ldr r0, [pc, #224] @ (8004b6c ) 8004a8a: f7ff fd56 bl 800453a break; 8004a8e: e062 b.n 8004b56 HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET); 8004a90: 2201 movs r2, #1 8004a92: f44f 6180 mov.w r1, #1024 @ 0x400 8004a96: 4834 ldr r0, [pc, #208] @ (8004b68 ) 8004a98: f001 fe19 bl 80066ce StartMot(timMot3,BWMot3,pwmval); 8004a9c: 897b ldrh r3, [r7, #10] 8004a9e: 461a mov r2, r3 8004aa0: 2104 movs r1, #4 8004aa2: 4832 ldr r0, [pc, #200] @ (8004b6c ) 8004aa4: f7ff fd1e bl 80044e4 break; 8004aa8: e055 b.n 8004b56 case 4: if(dir==FW){ 8004aaa: 79bb ldrb r3, [r7, #6] 8004aac: 2b00 cmp r3, #0 8004aae: d128 bne.n 8004b02 if(pwmval==0){ 8004ab0: 897b ldrh r3, [r7, #10] 8004ab2: 2b00 cmp r3, #0 8004ab4: d10a bne.n 8004acc StopMot(timMot4,FWMot4); 8004ab6: 2108 movs r1, #8 8004ab8: 482c ldr r0, [pc, #176] @ (8004b6c ) 8004aba: f7ff fd06 bl 80044ca HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET); 8004abe: 2200 movs r2, #0 8004ac0: f44f 6100 mov.w r1, #2048 @ 0x800 8004ac4: 4828 ldr r0, [pc, #160] @ (8004b68 ) 8004ac6: f001 fe02 bl 80066ce }else{ HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET); StartMot(timMot4,BWMot4,pwmval); } } break; 8004aca: e044 b.n 8004b56 }else if(IsPwmRunning(timMot4, FWMot4)){ 8004acc: 2108 movs r1, #8 8004ace: 4827 ldr r0, [pc, #156] @ (8004b6c ) 8004ad0: f7ff fce6 bl 80044a0 8004ad4: 4603 mov r3, r0 8004ad6: 2b00 cmp r3, #0 8004ad8: d006 beq.n 8004ae8 SetMotPwm(timMot4,FWMot4,pwmval); 8004ada: 897b ldrh r3, [r7, #10] 8004adc: 461a mov r2, r3 8004ade: 2108 movs r1, #8 8004ae0: 4822 ldr r0, [pc, #136] @ (8004b6c ) 8004ae2: f7ff fd2a bl 800453a break; 8004ae6: e036 b.n 8004b56 HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET); 8004ae8: 2201 movs r2, #1 8004aea: f44f 6100 mov.w r1, #2048 @ 0x800 8004aee: 481e ldr r0, [pc, #120] @ (8004b68 ) 8004af0: f001 fded bl 80066ce StartMot(timMot4,FWMot4,pwmval); 8004af4: 897b ldrh r3, [r7, #10] 8004af6: 461a mov r2, r3 8004af8: 2108 movs r1, #8 8004afa: 481c ldr r0, [pc, #112] @ (8004b6c ) 8004afc: f7ff fcf2 bl 80044e4 break; 8004b00: e029 b.n 8004b56 if(pwmval==0){ 8004b02: 897b ldrh r3, [r7, #10] 8004b04: 2b00 cmp r3, #0 8004b06: d10a bne.n 8004b1e StopMot(timMot4,BWMot4); 8004b08: 210c movs r1, #12 8004b0a: 4818 ldr r0, [pc, #96] @ (8004b6c ) 8004b0c: f7ff fcdd bl 80044ca HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET); 8004b10: 2200 movs r2, #0 8004b12: f44f 6100 mov.w r1, #2048 @ 0x800 8004b16: 4814 ldr r0, [pc, #80] @ (8004b68 ) 8004b18: f001 fdd9 bl 80066ce break; 8004b1c: e01b b.n 8004b56 }else if(IsPwmRunning(timMot4, BWMot4)){ 8004b1e: 210c movs r1, #12 8004b20: 4812 ldr r0, [pc, #72] @ (8004b6c ) 8004b22: f7ff fcbd bl 80044a0 8004b26: 4603 mov r3, r0 8004b28: 2b00 cmp r3, #0 8004b2a: d006 beq.n 8004b3a SetMotPwm(timMot4,BWMot4,pwmval); 8004b2c: 897b ldrh r3, [r7, #10] 8004b2e: 461a mov r2, r3 8004b30: 210c movs r1, #12 8004b32: 480e ldr r0, [pc, #56] @ (8004b6c ) 8004b34: f7ff fd01 bl 800453a break; 8004b38: e00d b.n 8004b56 HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET); 8004b3a: 2201 movs r2, #1 8004b3c: f44f 6100 mov.w r1, #2048 @ 0x800 8004b40: 4809 ldr r0, [pc, #36] @ (8004b68 ) 8004b42: f001 fdc4 bl 80066ce StartMot(timMot4,BWMot4,pwmval); 8004b46: 897b ldrh r3, [r7, #10] 8004b48: 461a mov r2, r3 8004b4a: 210c movs r1, #12 8004b4c: 4807 ldr r0, [pc, #28] @ (8004b6c ) 8004b4e: f7ff fcc9 bl 80044e4 break; 8004b52: e000 b.n 8004b56 default: break; 8004b54: bf00 nop } } 8004b56: bf00 nop 8004b58: 3710 adds r7, #16 8004b5a: 46bd mov sp, r7 8004b5c: bd80 pop {r7, pc} 8004b5e: bf00 nop 8004b60: 51eb851f .word 0x51eb851f 8004b64: 20000318 .word 0x20000318 8004b68: 40010c00 .word 0x40010c00 8004b6c: 20000360 .word 0x20000360 08004b70 : uint8_t ramp(uint8_t mot,uint8_t dir,uint8_t percStart,uint8_t percEnd,uint8_t tr,uint8_t mode){ 8004b70: b590 push {r4, r7, lr} 8004b72: b085 sub sp, #20 8004b74: af00 add r7, sp, #0 8004b76: 4604 mov r4, r0 8004b78: 4608 mov r0, r1 8004b7a: 4611 mov r1, r2 8004b7c: 461a mov r2, r3 8004b7e: 4623 mov r3, r4 8004b80: 71fb strb r3, [r7, #7] 8004b82: 4603 mov r3, r0 8004b84: 71bb strb r3, [r7, #6] 8004b86: 460b mov r3, r1 8004b88: 717b strb r3, [r7, #5] 8004b8a: 4613 mov r3, r2 8004b8c: 713b strb r3, [r7, #4] static uint8_t memrtramp[4]; // char s[10]; uint16_t delta; switch(mode){ 8004b8e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8004b92: 2b00 cmp r3, #0 8004b94: d002 beq.n 8004b9c 8004b96: 2b0a cmp r3, #10 8004b98: d016 beq.n 8004bc8 8004b9a: e09d b.n 8004cd8 case RAMPINIT: memrtramp[mot-1]=rtramp[mot-1]=tr; 8004b9c: 79fb ldrb r3, [r7, #7] 8004b9e: 3b01 subs r3, #1 8004ba0: f897 2020 ldrb.w r2, [r7, #32] 8004ba4: b291 uxth r1, r2 8004ba6: 4a4f ldr r2, [pc, #316] @ (8004ce4 ) 8004ba8: 4608 mov r0, r1 8004baa: f822 0013 strh.w r0, [r2, r3, lsl #1] 8004bae: 79fb ldrb r3, [r7, #7] 8004bb0: 3b01 subs r3, #1 8004bb2: b2c9 uxtb r1, r1 8004bb4: 4a4c ldr r2, [pc, #304] @ (8004ce8 ) 8004bb6: 54d1 strb r1, [r2, r3] SetMotPerc(mot,dir,percStart); 8004bb8: 797a ldrb r2, [r7, #5] 8004bba: 79b9 ldrb r1, [r7, #6] 8004bbc: 79fb ldrb r3, [r7, #7] 8004bbe: 4618 mov r0, r3 8004bc0: f7ff fe56 bl 8004870 return DONE; 8004bc4: 2300 movs r3, #0 8004bc6: e088 b.n 8004cda case RAMPRUN: if(memrtramp[mot-1]!=rtramp[mot-1]){ 8004bc8: 79fb ldrb r3, [r7, #7] 8004bca: 3b01 subs r3, #1 8004bcc: 4a46 ldr r2, [pc, #280] @ (8004ce8 ) 8004bce: 5cd3 ldrb r3, [r2, r3] 8004bd0: 4619 mov r1, r3 8004bd2: 79fb ldrb r3, [r7, #7] 8004bd4: 3b01 subs r3, #1 8004bd6: 4a43 ldr r2, [pc, #268] @ (8004ce4 ) 8004bd8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8004bdc: b29b uxth r3, r3 8004bde: 4299 cmp r1, r3 8004be0: d078 beq.n 8004cd4 memrtramp[mot-1]=rtramp[mot-1]; 8004be2: 79fb ldrb r3, [r7, #7] 8004be4: 3b01 subs r3, #1 8004be6: 4a3f ldr r2, [pc, #252] @ (8004ce4 ) 8004be8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8004bec: b29a uxth r2, r3 8004bee: 79fb ldrb r3, [r7, #7] 8004bf0: 3b01 subs r3, #1 8004bf2: b2d1 uxtb r1, r2 8004bf4: 4a3c ldr r2, [pc, #240] @ (8004ce8 ) 8004bf6: 54d1 strb r1, [r2, r3] if(rtramp[mot-1]){ 8004bf8: 79fb ldrb r3, [r7, #7] 8004bfa: 3b01 subs r3, #1 8004bfc: 4a39 ldr r2, [pc, #228] @ (8004ce4 ) 8004bfe: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8004c02: b29b uxth r3, r3 8004c04: 2b00 cmp r3, #0 8004c06: d05d beq.n 8004cc4 if(percStart>percEnd){ 8004c08: 797a ldrb r2, [r7, #5] 8004c0a: 793b ldrb r3, [r7, #4] 8004c0c: 429a cmp r2, r3 8004c0e: d926 bls.n 8004c5e delta=percStart-percEnd; 8004c10: 797b ldrb r3, [r7, #5] 8004c12: b29a uxth r2, r3 8004c14: 793b ldrb r3, [r7, #4] 8004c16: b29b uxth r3, r3 8004c18: 1ad3 subs r3, r2, r3 8004c1a: 81fb strh r3, [r7, #14] delta=delta*(uint16_t)(tr-rtramp[mot-1]); 8004c1c: f897 3020 ldrb.w r3, [r7, #32] 8004c20: b29a uxth r2, r3 8004c22: 79fb ldrb r3, [r7, #7] 8004c24: 3b01 subs r3, #1 8004c26: 492f ldr r1, [pc, #188] @ (8004ce4 ) 8004c28: f831 3013 ldrh.w r3, [r1, r3, lsl #1] 8004c2c: b29b uxth r3, r3 8004c2e: 1ad3 subs r3, r2, r3 8004c30: b29b uxth r3, r3 8004c32: 89fa ldrh r2, [r7, #14] 8004c34: fb02 f303 mul.w r3, r2, r3 8004c38: 81fb strh r3, [r7, #14] delta=delta/tr; 8004c3a: 89fa ldrh r2, [r7, #14] 8004c3c: f897 3020 ldrb.w r3, [r7, #32] 8004c40: fb92 f3f3 sdiv r3, r2, r3 8004c44: 81fb strh r3, [r7, #14] SetMotPerc(mot,dir,percStart-delta); 8004c46: 89fb ldrh r3, [r7, #14] 8004c48: b2db uxtb r3, r3 8004c4a: 797a ldrb r2, [r7, #5] 8004c4c: 1ad3 subs r3, r2, r3 8004c4e: b2da uxtb r2, r3 8004c50: 79b9 ldrb r1, [r7, #6] 8004c52: 79fb ldrb r3, [r7, #7] 8004c54: 4618 mov r0, r3 8004c56: f7ff fe0b bl 8004870 return RUNNING; 8004c5a: 2301 movs r3, #1 8004c5c: e03d b.n 8004cda }else if(percStart delta=percEnd-percStart; 8004c66: 793b ldrb r3, [r7, #4] 8004c68: b29a uxth r2, r3 8004c6a: 797b ldrb r3, [r7, #5] 8004c6c: b29b uxth r3, r3 8004c6e: 1ad3 subs r3, r2, r3 8004c70: 81fb strh r3, [r7, #14] delta=delta*(uint16_t)(tr-rtramp[mot-1]); 8004c72: f897 3020 ldrb.w r3, [r7, #32] 8004c76: b29a uxth r2, r3 8004c78: 79fb ldrb r3, [r7, #7] 8004c7a: 3b01 subs r3, #1 8004c7c: 4919 ldr r1, [pc, #100] @ (8004ce4 ) 8004c7e: f831 3013 ldrh.w r3, [r1, r3, lsl #1] 8004c82: b29b uxth r3, r3 8004c84: 1ad3 subs r3, r2, r3 8004c86: b29b uxth r3, r3 8004c88: 89fa ldrh r2, [r7, #14] 8004c8a: fb02 f303 mul.w r3, r2, r3 8004c8e: 81fb strh r3, [r7, #14] delta=delta/tr; 8004c90: 89fa ldrh r2, [r7, #14] 8004c92: f897 3020 ldrb.w r3, [r7, #32] 8004c96: fb92 f3f3 sdiv r3, r2, r3 8004c9a: 81fb strh r3, [r7, #14] SetMotPerc(mot,dir,percStart+delta); 8004c9c: 89fb ldrh r3, [r7, #14] 8004c9e: b2da uxtb r2, r3 8004ca0: 797b ldrb r3, [r7, #5] 8004ca2: 4413 add r3, r2 8004ca4: b2da uxtb r2, r3 8004ca6: 79b9 ldrb r1, [r7, #6] 8004ca8: 79fb ldrb r3, [r7, #7] 8004caa: 4618 mov r0, r3 8004cac: f7ff fde0 bl 8004870 // sprintf((char*)s,"\n%d",percStart+delta); // HAL_UART_Transmit(&huart1,(uint8_t*) s, strlen(s), HAL_MAX_DELAY); return RUNNING; 8004cb0: 2301 movs r3, #1 8004cb2: e012 b.n 8004cda }else{ SetMotPerc(mot,dir,percEnd); 8004cb4: 793a ldrb r2, [r7, #4] 8004cb6: 79b9 ldrb r1, [r7, #6] 8004cb8: 79fb ldrb r3, [r7, #7] 8004cba: 4618 mov r0, r3 8004cbc: f7ff fdd8 bl 8004870 return DONE; 8004cc0: 2300 movs r3, #0 8004cc2: e00a b.n 8004cda } }else{ SetMotPerc(mot,dir,percEnd); 8004cc4: 793a ldrb r2, [r7, #4] 8004cc6: 79b9 ldrb r1, [r7, #6] 8004cc8: 79fb ldrb r3, [r7, #7] 8004cca: 4618 mov r0, r3 8004ccc: f7ff fdd0 bl 8004870 return DONE; 8004cd0: 2300 movs r3, #0 8004cd2: e002 b.n 8004cda } }else return RUNNING; 8004cd4: 2301 movs r3, #1 8004cd6: e000 b.n 8004cda break; } return DONE; 8004cd8: 2300 movs r3, #0 } 8004cda: 4618 mov r0, r3 8004cdc: 3714 adds r7, #20 8004cde: 46bd mov sp, r7 8004ce0: bd90 pop {r4, r7, pc} 8004ce2: bf00 nop 8004ce4: 200003f4 .word 0x200003f4 8004ce8: 2000046c .word 0x2000046c 08004cec : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8004cec: b480 push {r7} 8004cee: b085 sub sp, #20 8004cf0: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8004cf2: 4b15 ldr r3, [pc, #84] @ (8004d48 ) 8004cf4: 699b ldr r3, [r3, #24] 8004cf6: 4a14 ldr r2, [pc, #80] @ (8004d48 ) 8004cf8: f043 0301 orr.w r3, r3, #1 8004cfc: 6193 str r3, [r2, #24] 8004cfe: 4b12 ldr r3, [pc, #72] @ (8004d48 ) 8004d00: 699b ldr r3, [r3, #24] 8004d02: f003 0301 and.w r3, r3, #1 8004d06: 60bb str r3, [r7, #8] 8004d08: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8004d0a: 4b0f ldr r3, [pc, #60] @ (8004d48 ) 8004d0c: 69db ldr r3, [r3, #28] 8004d0e: 4a0e ldr r2, [pc, #56] @ (8004d48 ) 8004d10: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004d14: 61d3 str r3, [r2, #28] 8004d16: 4b0c ldr r3, [pc, #48] @ (8004d48 ) 8004d18: 69db ldr r3, [r3, #28] 8004d1a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004d1e: 607b str r3, [r7, #4] 8004d20: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8004d22: 4b0a ldr r3, [pc, #40] @ (8004d4c ) 8004d24: 685b ldr r3, [r3, #4] 8004d26: 60fb str r3, [r7, #12] 8004d28: 68fb ldr r3, [r7, #12] 8004d2a: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 8004d2e: 60fb str r3, [r7, #12] 8004d30: 68fb ldr r3, [r7, #12] 8004d32: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8004d36: 60fb str r3, [r7, #12] 8004d38: 4a04 ldr r2, [pc, #16] @ (8004d4c ) 8004d3a: 68fb ldr r3, [r7, #12] 8004d3c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8004d3e: bf00 nop 8004d40: 3714 adds r7, #20 8004d42: 46bd mov sp, r7 8004d44: bc80 pop {r7} 8004d46: 4770 bx lr 8004d48: 40021000 .word 0x40021000 8004d4c: 40010000 .word 0x40010000 08004d50 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8004d50: b580 push {r7, lr} 8004d52: b08a sub sp, #40 @ 0x28 8004d54: af00 add r7, sp, #0 8004d56: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004d58: f107 0318 add.w r3, r7, #24 8004d5c: 2200 movs r2, #0 8004d5e: 601a str r2, [r3, #0] 8004d60: 605a str r2, [r3, #4] 8004d62: 609a str r2, [r3, #8] 8004d64: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 8004d66: 687b ldr r3, [r7, #4] 8004d68: 681b ldr r3, [r3, #0] 8004d6a: 4a33 ldr r2, [pc, #204] @ (8004e38 ) 8004d6c: 4293 cmp r3, r2 8004d6e: d15f bne.n 8004e30 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8004d70: 4b32 ldr r3, [pc, #200] @ (8004e3c ) 8004d72: 699b ldr r3, [r3, #24] 8004d74: 4a31 ldr r2, [pc, #196] @ (8004e3c ) 8004d76: f443 7300 orr.w r3, r3, #512 @ 0x200 8004d7a: 6193 str r3, [r2, #24] 8004d7c: 4b2f ldr r3, [pc, #188] @ (8004e3c ) 8004d7e: 699b ldr r3, [r3, #24] 8004d80: f403 7300 and.w r3, r3, #512 @ 0x200 8004d84: 617b str r3, [r7, #20] 8004d86: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004d88: 4b2c ldr r3, [pc, #176] @ (8004e3c ) 8004d8a: 699b ldr r3, [r3, #24] 8004d8c: 4a2b ldr r2, [pc, #172] @ (8004e3c ) 8004d8e: f043 0304 orr.w r3, r3, #4 8004d92: 6193 str r3, [r2, #24] 8004d94: 4b29 ldr r3, [pc, #164] @ (8004e3c ) 8004d96: 699b ldr r3, [r3, #24] 8004d98: f003 0304 and.w r3, r3, #4 8004d9c: 613b str r3, [r7, #16] 8004d9e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004da0: 4b26 ldr r3, [pc, #152] @ (8004e3c ) 8004da2: 699b ldr r3, [r3, #24] 8004da4: 4a25 ldr r2, [pc, #148] @ (8004e3c ) 8004da6: f043 0308 orr.w r3, r3, #8 8004daa: 6193 str r3, [r2, #24] 8004dac: 4b23 ldr r3, [pc, #140] @ (8004e3c ) 8004dae: 699b ldr r3, [r3, #24] 8004db0: f003 0308 and.w r3, r3, #8 8004db4: 60fb str r3, [r7, #12] 8004db6: 68fb ldr r3, [r7, #12] PA5 ------> ADC1_IN5 PA6 ------> ADC1_IN6 PA7 ------> ADC1_IN7 PB0 ------> ADC1_IN8 */ GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin|AIN3_Pin|AIN4_Pin; 8004db8: 23f0 movs r3, #240 @ 0xf0 8004dba: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8004dbc: 2303 movs r3, #3 8004dbe: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004dc0: f107 0318 add.w r3, r7, #24 8004dc4: 4619 mov r1, r3 8004dc6: 481e ldr r0, [pc, #120] @ (8004e40 ) 8004dc8: f001 fae6 bl 8006398 GPIO_InitStruct.Pin = ANEM_Pin; 8004dcc: 2301 movs r3, #1 8004dce: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8004dd0: 2303 movs r3, #3 8004dd2: 61fb str r3, [r7, #28] HAL_GPIO_Init(ANEM_GPIO_Port, &GPIO_InitStruct); 8004dd4: f107 0318 add.w r3, r7, #24 8004dd8: 4619 mov r1, r3 8004dda: 481a ldr r0, [pc, #104] @ (8004e44 ) 8004ddc: f001 fadc bl 8006398 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8004de0: 4b19 ldr r3, [pc, #100] @ (8004e48 ) 8004de2: 4a1a ldr r2, [pc, #104] @ (8004e4c ) 8004de4: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8004de6: 4b18 ldr r3, [pc, #96] @ (8004e48 ) 8004de8: 2200 movs r2, #0 8004dea: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8004dec: 4b16 ldr r3, [pc, #88] @ (8004e48 ) 8004dee: 2200 movs r2, #0 8004df0: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8004df2: 4b15 ldr r3, [pc, #84] @ (8004e48 ) 8004df4: 2280 movs r2, #128 @ 0x80 8004df6: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8004df8: 4b13 ldr r3, [pc, #76] @ (8004e48 ) 8004dfa: f44f 7280 mov.w r2, #256 @ 0x100 8004dfe: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8004e00: 4b11 ldr r3, [pc, #68] @ (8004e48 ) 8004e02: f44f 6280 mov.w r2, #1024 @ 0x400 8004e06: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 8004e08: 4b0f ldr r3, [pc, #60] @ (8004e48 ) 8004e0a: 2220 movs r2, #32 8004e0c: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8004e0e: 4b0e ldr r3, [pc, #56] @ (8004e48 ) 8004e10: 2200 movs r2, #0 8004e12: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8004e14: 480c ldr r0, [pc, #48] @ (8004e48 ) 8004e16: f000 fed1 bl 8005bbc 8004e1a: 4603 mov r3, r0 8004e1c: 2b00 cmp r3, #0 8004e1e: d001 beq.n 8004e24 { Error_Handler(); 8004e20: f7fe fca2 bl 8003768 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8004e24: 687b ldr r3, [r7, #4] 8004e26: 4a08 ldr r2, [pc, #32] @ (8004e48 ) 8004e28: 621a str r2, [r3, #32] 8004e2a: 4a07 ldr r2, [pc, #28] @ (8004e48 ) 8004e2c: 687b ldr r3, [r7, #4] 8004e2e: 6253 str r3, [r2, #36] @ 0x24 /* USER CODE END ADC1_MspInit 1 */ } } 8004e30: bf00 nop 8004e32: 3728 adds r7, #40 @ 0x28 8004e34: 46bd mov sp, r7 8004e36: bd80 pop {r7, pc} 8004e38: 40012400 .word 0x40012400 8004e3c: 40021000 .word 0x40021000 8004e40: 40010800 .word 0x40010800 8004e44: 40010c00 .word 0x40010c00 8004e48: 200002d4 .word 0x200002d4 8004e4c: 40020008 .word 0x40020008 08004e50 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8004e50: b480 push {r7} 8004e52: b085 sub sp, #20 8004e54: af00 add r7, sp, #0 8004e56: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM2) 8004e58: 687b ldr r3, [r7, #4] 8004e5a: 681b ldr r3, [r3, #0] 8004e5c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8004e60: d10c bne.n 8004e7c { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8004e62: 4b11 ldr r3, [pc, #68] @ (8004ea8 ) 8004e64: 69db ldr r3, [r3, #28] 8004e66: 4a10 ldr r2, [pc, #64] @ (8004ea8 ) 8004e68: f043 0301 orr.w r3, r3, #1 8004e6c: 61d3 str r3, [r2, #28] 8004e6e: 4b0e ldr r3, [pc, #56] @ (8004ea8 ) 8004e70: 69db ldr r3, [r3, #28] 8004e72: f003 0301 and.w r3, r3, #1 8004e76: 60fb str r3, [r7, #12] 8004e78: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 8004e7a: e010 b.n 8004e9e else if(htim_base->Instance==TIM4) 8004e7c: 687b ldr r3, [r7, #4] 8004e7e: 681b ldr r3, [r3, #0] 8004e80: 4a0a ldr r2, [pc, #40] @ (8004eac ) 8004e82: 4293 cmp r3, r2 8004e84: d10b bne.n 8004e9e __HAL_RCC_TIM4_CLK_ENABLE(); 8004e86: 4b08 ldr r3, [pc, #32] @ (8004ea8 ) 8004e88: 69db ldr r3, [r3, #28] 8004e8a: 4a07 ldr r2, [pc, #28] @ (8004ea8 ) 8004e8c: f043 0304 orr.w r3, r3, #4 8004e90: 61d3 str r3, [r2, #28] 8004e92: 4b05 ldr r3, [pc, #20] @ (8004ea8 ) 8004e94: 69db ldr r3, [r3, #28] 8004e96: f003 0304 and.w r3, r3, #4 8004e9a: 60bb str r3, [r7, #8] 8004e9c: 68bb ldr r3, [r7, #8] } 8004e9e: bf00 nop 8004ea0: 3714 adds r7, #20 8004ea2: 46bd mov sp, r7 8004ea4: bc80 pop {r7} 8004ea6: 4770 bx lr 8004ea8: 40021000 .word 0x40021000 8004eac: 40000800 .word 0x40000800 08004eb0 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8004eb0: b580 push {r7, lr} 8004eb2: b088 sub sp, #32 8004eb4: af00 add r7, sp, #0 8004eb6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004eb8: f107 0310 add.w r3, r7, #16 8004ebc: 2200 movs r2, #0 8004ebe: 601a str r2, [r3, #0] 8004ec0: 605a str r2, [r3, #4] 8004ec2: 609a str r2, [r3, #8] 8004ec4: 60da str r2, [r3, #12] if(htim->Instance==TIM2) 8004ec6: 687b ldr r3, [r7, #4] 8004ec8: 681b ldr r3, [r3, #0] 8004eca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8004ece: d118 bne.n 8004f02 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8004ed0: 4b1d ldr r3, [pc, #116] @ (8004f48 ) 8004ed2: 699b ldr r3, [r3, #24] 8004ed4: 4a1c ldr r2, [pc, #112] @ (8004f48 ) 8004ed6: f043 0304 orr.w r3, r3, #4 8004eda: 6193 str r3, [r2, #24] 8004edc: 4b1a ldr r3, [pc, #104] @ (8004f48 ) 8004ede: 699b ldr r3, [r3, #24] 8004ee0: f003 0304 and.w r3, r3, #4 8004ee4: 60fb str r3, [r7, #12] 8004ee6: 68fb ldr r3, [r7, #12] PA0-WKUP ------> TIM2_CH1 PA1 ------> TIM2_CH2 PA2 ------> TIM2_CH3 PA3 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|IN3_Pin|IN4_Pin; 8004ee8: 230f movs r3, #15 8004eea: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004eec: 2302 movs r3, #2 8004eee: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004ef0: 2302 movs r3, #2 8004ef2: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004ef4: f107 0310 add.w r3, r7, #16 8004ef8: 4619 mov r1, r3 8004efa: 4814 ldr r0, [pc, #80] @ (8004f4c ) 8004efc: f001 fa4c bl 8006398 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 8004f00: e01d b.n 8004f3e else if(htim->Instance==TIM4) 8004f02: 687b ldr r3, [r7, #4] 8004f04: 681b ldr r3, [r3, #0] 8004f06: 4a12 ldr r2, [pc, #72] @ (8004f50 ) 8004f08: 4293 cmp r3, r2 8004f0a: d118 bne.n 8004f3e __HAL_RCC_GPIOB_CLK_ENABLE(); 8004f0c: 4b0e ldr r3, [pc, #56] @ (8004f48 ) 8004f0e: 699b ldr r3, [r3, #24] 8004f10: 4a0d ldr r2, [pc, #52] @ (8004f48 ) 8004f12: f043 0308 orr.w r3, r3, #8 8004f16: 6193 str r3, [r2, #24] 8004f18: 4b0b ldr r3, [pc, #44] @ (8004f48 ) 8004f1a: 699b ldr r3, [r3, #24] 8004f1c: f003 0308 and.w r3, r3, #8 8004f20: 60bb str r3, [r7, #8] 8004f22: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = IN5_Pin|IN6_Pin|IN7_Pin|IN8_Pin; 8004f24: f44f 7370 mov.w r3, #960 @ 0x3c0 8004f28: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004f2a: 2302 movs r3, #2 8004f2c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004f2e: 2302 movs r3, #2 8004f30: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004f32: f107 0310 add.w r3, r7, #16 8004f36: 4619 mov r1, r3 8004f38: 4806 ldr r0, [pc, #24] @ (8004f54 ) 8004f3a: f001 fa2d bl 8006398 } 8004f3e: bf00 nop 8004f40: 3720 adds r7, #32 8004f42: 46bd mov sp, r7 8004f44: bd80 pop {r7, pc} 8004f46: bf00 nop 8004f48: 40021000 .word 0x40021000 8004f4c: 40010800 .word 0x40010800 8004f50: 40000800 .word 0x40000800 8004f54: 40010c00 .word 0x40010c00 08004f58 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8004f58: b580 push {r7, lr} 8004f5a: b088 sub sp, #32 8004f5c: af00 add r7, sp, #0 8004f5e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004f60: f107 0310 add.w r3, r7, #16 8004f64: 2200 movs r2, #0 8004f66: 601a str r2, [r3, #0] 8004f68: 605a str r2, [r3, #4] 8004f6a: 609a str r2, [r3, #8] 8004f6c: 60da str r2, [r3, #12] if(huart->Instance==USART1) 8004f6e: 687b ldr r3, [r7, #4] 8004f70: 681b ldr r3, [r3, #0] 8004f72: 4a1c ldr r2, [pc, #112] @ (8004fe4 ) 8004f74: 4293 cmp r3, r2 8004f76: d131 bne.n 8004fdc { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8004f78: 4b1b ldr r3, [pc, #108] @ (8004fe8 ) 8004f7a: 699b ldr r3, [r3, #24] 8004f7c: 4a1a ldr r2, [pc, #104] @ (8004fe8 ) 8004f7e: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8004f82: 6193 str r3, [r2, #24] 8004f84: 4b18 ldr r3, [pc, #96] @ (8004fe8 ) 8004f86: 699b ldr r3, [r3, #24] 8004f88: f403 4380 and.w r3, r3, #16384 @ 0x4000 8004f8c: 60fb str r3, [r7, #12] 8004f8e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004f90: 4b15 ldr r3, [pc, #84] @ (8004fe8 ) 8004f92: 699b ldr r3, [r3, #24] 8004f94: 4a14 ldr r2, [pc, #80] @ (8004fe8 ) 8004f96: f043 0304 orr.w r3, r3, #4 8004f9a: 6193 str r3, [r2, #24] 8004f9c: 4b12 ldr r3, [pc, #72] @ (8004fe8 ) 8004f9e: 699b ldr r3, [r3, #24] 8004fa0: f003 0304 and.w r3, r3, #4 8004fa4: 60bb str r3, [r7, #8] 8004fa6: 68bb ldr r3, [r7, #8] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8004fa8: f44f 7300 mov.w r3, #512 @ 0x200 8004fac: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004fae: 2302 movs r3, #2 8004fb0: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8004fb2: 2303 movs r3, #3 8004fb4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004fb6: f107 0310 add.w r3, r7, #16 8004fba: 4619 mov r1, r3 8004fbc: 480b ldr r0, [pc, #44] @ (8004fec ) 8004fbe: f001 f9eb bl 8006398 GPIO_InitStruct.Pin = GPIO_PIN_10; 8004fc2: f44f 6380 mov.w r3, #1024 @ 0x400 8004fc6: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8004fc8: 2300 movs r3, #0 8004fca: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004fcc: 2300 movs r3, #0 8004fce: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004fd0: f107 0310 add.w r3, r7, #16 8004fd4: 4619 mov r1, r3 8004fd6: 4805 ldr r0, [pc, #20] @ (8004fec ) 8004fd8: f001 f9de bl 8006398 /* USER CODE END USART1_MspInit 1 */ } } 8004fdc: bf00 nop 8004fde: 3720 adds r7, #32 8004fe0: 46bd mov sp, r7 8004fe2: bd80 pop {r7, pc} 8004fe4: 40013800 .word 0x40013800 8004fe8: 40021000 .word 0x40021000 8004fec: 40010800 .word 0x40010800 08004ff0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8004ff0: b480 push {r7} 8004ff2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8004ff4: bf00 nop 8004ff6: e7fd b.n 8004ff4 08004ff8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8004ff8: b480 push {r7} 8004ffa: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004ffc: bf00 nop 8004ffe: e7fd b.n 8004ffc 08005000 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8005000: b480 push {r7} 8005002: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8005004: bf00 nop 8005006: e7fd b.n 8005004 08005008 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8005008: b480 push {r7} 800500a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800500c: bf00 nop 800500e: e7fd b.n 800500c 08005010 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8005010: b480 push {r7} 8005012: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8005014: bf00 nop 8005016: e7fd b.n 8005014 08005018 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8005018: b480 push {r7} 800501a: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800501c: bf00 nop 800501e: 46bd mov sp, r7 8005020: bc80 pop {r7} 8005022: 4770 bx lr 08005024 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8005024: b480 push {r7} 8005026: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8005028: bf00 nop 800502a: 46bd mov sp, r7 800502c: bc80 pop {r7} 800502e: 4770 bx lr 08005030 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8005030: b480 push {r7} 8005032: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8005034: bf00 nop 8005036: 46bd mov sp, r7 8005038: bc80 pop {r7} 800503a: 4770 bx lr 0800503c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800503c: b580 push {r7, lr} 800503e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8005040: f000 f8c0 bl 80051c4 /* USER CODE BEGIN SysTick_IRQn 1 */ HAL_SYSTICK_IRQHandler(); 8005044: f000 fdb3 bl 8005bae /* USER CODE END SysTick_IRQn 1 */ } 8005048: bf00 nop 800504a: bd80 pop {r7, pc} 0800504c : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800504c: b580 push {r7, lr} 800504e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8005050: 4802 ldr r0, [pc, #8] @ (800505c ) 8005052: f000 fe6d bl 8005d30 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 8005056: bf00 nop 8005058: bd80 pop {r7, pc} 800505a: bf00 nop 800505c: 200002d4 .word 0x200002d4 08005060 : /** * @brief This function handles USB low priority or CAN RX0 interrupts. */ void USB_LP_CAN1_RX0_IRQHandler(void) { 8005060: b580 push {r7, lr} 8005062: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */ /* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_FS); 8005064: 4802 ldr r0, [pc, #8] @ (8005070 ) 8005066: f001 fc66 bl 8006936 /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */ /* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */ } 800506a: bf00 nop 800506c: bd80 pop {r7, pc} 800506e: bf00 nop 8005070: 20001264 .word 0x20001264 08005074 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8005074: b580 push {r7, lr} 8005076: b086 sub sp, #24 8005078: af00 add r7, sp, #0 800507a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800507c: 4a14 ldr r2, [pc, #80] @ (80050d0 <_sbrk+0x5c>) 800507e: 4b15 ldr r3, [pc, #84] @ (80050d4 <_sbrk+0x60>) 8005080: 1ad3 subs r3, r2, r3 8005082: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8005084: 697b ldr r3, [r7, #20] 8005086: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8005088: 4b13 ldr r3, [pc, #76] @ (80050d8 <_sbrk+0x64>) 800508a: 681b ldr r3, [r3, #0] 800508c: 2b00 cmp r3, #0 800508e: d102 bne.n 8005096 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8005090: 4b11 ldr r3, [pc, #68] @ (80050d8 <_sbrk+0x64>) 8005092: 4a12 ldr r2, [pc, #72] @ (80050dc <_sbrk+0x68>) 8005094: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8005096: 4b10 ldr r3, [pc, #64] @ (80050d8 <_sbrk+0x64>) 8005098: 681a ldr r2, [r3, #0] 800509a: 687b ldr r3, [r7, #4] 800509c: 4413 add r3, r2 800509e: 693a ldr r2, [r7, #16] 80050a0: 429a cmp r2, r3 80050a2: d207 bcs.n 80050b4 <_sbrk+0x40> { errno = ENOMEM; 80050a4: f009 fa2c bl 800e500 <__errno> 80050a8: 4603 mov r3, r0 80050aa: 220c movs r2, #12 80050ac: 601a str r2, [r3, #0] return (void *)-1; 80050ae: f04f 33ff mov.w r3, #4294967295 80050b2: e009 b.n 80050c8 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80050b4: 4b08 ldr r3, [pc, #32] @ (80050d8 <_sbrk+0x64>) 80050b6: 681b ldr r3, [r3, #0] 80050b8: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80050ba: 4b07 ldr r3, [pc, #28] @ (80050d8 <_sbrk+0x64>) 80050bc: 681a ldr r2, [r3, #0] 80050be: 687b ldr r3, [r7, #4] 80050c0: 4413 add r3, r2 80050c2: 4a05 ldr r2, [pc, #20] @ (80050d8 <_sbrk+0x64>) 80050c4: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80050c6: 68fb ldr r3, [r7, #12] } 80050c8: 4618 mov r0, r3 80050ca: 3718 adds r7, #24 80050cc: 46bd mov sp, r7 80050ce: bd80 pop {r7, pc} 80050d0: 20005000 .word 0x20005000 80050d4: 00000400 .word 0x00000400 80050d8: 20000470 .word 0x20000470 80050dc: 200018a8 .word 0x200018a8 080050e0 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80050e0: b480 push {r7} 80050e2: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80050e4: bf00 nop 80050e6: 46bd mov sp, r7 80050e8: bc80 pop {r7} 80050ea: 4770 bx lr 080050ec : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 80050ec: f7ff fff8 bl 80050e0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80050f0: 480b ldr r0, [pc, #44] @ (8005120 ) ldr r1, =_edata 80050f2: 490c ldr r1, [pc, #48] @ (8005124 ) ldr r2, =_sidata 80050f4: 4a0c ldr r2, [pc, #48] @ (8005128 ) movs r3, #0 80050f6: 2300 movs r3, #0 b LoopCopyDataInit 80050f8: e002 b.n 8005100 080050fa : CopyDataInit: ldr r4, [r2, r3] 80050fa: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80050fc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80050fe: 3304 adds r3, #4 08005100 : LoopCopyDataInit: adds r4, r0, r3 8005100: 18c4 adds r4, r0, r3 cmp r4, r1 8005102: 428c cmp r4, r1 bcc CopyDataInit 8005104: d3f9 bcc.n 80050fa /* Zero fill the bss segment. */ ldr r2, =_sbss 8005106: 4a09 ldr r2, [pc, #36] @ (800512c ) ldr r4, =_ebss 8005108: 4c09 ldr r4, [pc, #36] @ (8005130 ) movs r3, #0 800510a: 2300 movs r3, #0 b LoopFillZerobss 800510c: e001 b.n 8005112 0800510e : FillZerobss: str r3, [r2] 800510e: 6013 str r3, [r2, #0] adds r2, r2, #4 8005110: 3204 adds r2, #4 08005112 : LoopFillZerobss: cmp r2, r4 8005112: 42a2 cmp r2, r4 bcc FillZerobss 8005114: d3fb bcc.n 800510e /* Call static constructors */ bl __libc_init_array 8005116: f009 f9f9 bl 800e50c <__libc_init_array> /* Call the application's entry point.*/ bl main 800511a: f7fd ffa3 bl 8003064
bx lr 800511e: 4770 bx lr ldr r0, =_sdata 8005120: 20000000 .word 0x20000000 ldr r1, =_edata 8005124: 200001dc .word 0x200001dc ldr r2, =_sidata 8005128: 0800f620 .word 0x0800f620 ldr r2, =_sbss 800512c: 200001e0 .word 0x200001e0 ldr r4, =_ebss 8005130: 200018a4 .word 0x200018a4 08005134 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005134: e7fe b.n 8005134 ... 08005138 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8005138: b580 push {r7, lr} 800513a: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800513c: 4b08 ldr r3, [pc, #32] @ (8005160 ) 800513e: 681b ldr r3, [r3, #0] 8005140: 4a07 ldr r2, [pc, #28] @ (8005160 ) 8005142: f043 0310 orr.w r3, r3, #16 8005146: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005148: 2003 movs r0, #3 800514a: f000 fcef bl 8005b2c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800514e: 200f movs r0, #15 8005150: f000 f808 bl 8005164 /* Init the low level hardware */ HAL_MspInit(); 8005154: f7ff fdca bl 8004cec /* Return function status */ return HAL_OK; 8005158: 2300 movs r3, #0 } 800515a: 4618 mov r0, r3 800515c: bd80 pop {r7, pc} 800515e: bf00 nop 8005160: 40022000 .word 0x40022000 08005164 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8005164: b580 push {r7, lr} 8005166: b082 sub sp, #8 8005168: af00 add r7, sp, #0 800516a: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800516c: 4b12 ldr r3, [pc, #72] @ (80051b8 ) 800516e: 681a ldr r2, [r3, #0] 8005170: 4b12 ldr r3, [pc, #72] @ (80051bc ) 8005172: 781b ldrb r3, [r3, #0] 8005174: 4619 mov r1, r3 8005176: f44f 737a mov.w r3, #1000 @ 0x3e8 800517a: fbb3 f3f1 udiv r3, r3, r1 800517e: fbb2 f3f3 udiv r3, r2, r3 8005182: 4618 mov r0, r3 8005184: f000 fd07 bl 8005b96 8005188: 4603 mov r3, r0 800518a: 2b00 cmp r3, #0 800518c: d001 beq.n 8005192 { return HAL_ERROR; 800518e: 2301 movs r3, #1 8005190: e00e b.n 80051b0 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8005192: 687b ldr r3, [r7, #4] 8005194: 2b0f cmp r3, #15 8005196: d80a bhi.n 80051ae { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8005198: 2200 movs r2, #0 800519a: 6879 ldr r1, [r7, #4] 800519c: f04f 30ff mov.w r0, #4294967295 80051a0: f000 fccf bl 8005b42 uwTickPrio = TickPriority; 80051a4: 4a06 ldr r2, [pc, #24] @ (80051c0 ) 80051a6: 687b ldr r3, [r7, #4] 80051a8: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80051aa: 2300 movs r3, #0 80051ac: e000 b.n 80051b0 return HAL_ERROR; 80051ae: 2301 movs r3, #1 } 80051b0: 4618 mov r0, r3 80051b2: 3708 adds r7, #8 80051b4: 46bd mov sp, r7 80051b6: bd80 pop {r7, pc} 80051b8: 20000010 .word 0x20000010 80051bc: 20000018 .word 0x20000018 80051c0: 20000014 .word 0x20000014 080051c4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80051c4: b480 push {r7} 80051c6: af00 add r7, sp, #0 uwTick += uwTickFreq; 80051c8: 4b05 ldr r3, [pc, #20] @ (80051e0 ) 80051ca: 781b ldrb r3, [r3, #0] 80051cc: 461a mov r2, r3 80051ce: 4b05 ldr r3, [pc, #20] @ (80051e4 ) 80051d0: 681b ldr r3, [r3, #0] 80051d2: 4413 add r3, r2 80051d4: 4a03 ldr r2, [pc, #12] @ (80051e4 ) 80051d6: 6013 str r3, [r2, #0] } 80051d8: bf00 nop 80051da: 46bd mov sp, r7 80051dc: bc80 pop {r7} 80051de: 4770 bx lr 80051e0: 20000018 .word 0x20000018 80051e4: 20000474 .word 0x20000474 080051e8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80051e8: b480 push {r7} 80051ea: af00 add r7, sp, #0 return uwTick; 80051ec: 4b02 ldr r3, [pc, #8] @ (80051f8 ) 80051ee: 681b ldr r3, [r3, #0] } 80051f0: 4618 mov r0, r3 80051f2: 46bd mov sp, r7 80051f4: bc80 pop {r7} 80051f6: 4770 bx lr 80051f8: 20000474 .word 0x20000474 080051fc : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80051fc: b580 push {r7, lr} 80051fe: b086 sub sp, #24 8005200: af00 add r7, sp, #0 8005202: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005204: 2300 movs r3, #0 8005206: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8005208: 2300 movs r3, #0 800520a: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800520c: 2300 movs r3, #0 800520e: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8005210: 2300 movs r3, #0 8005212: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8005214: 687b ldr r3, [r7, #4] 8005216: 2b00 cmp r3, #0 8005218: d101 bne.n 800521e { return HAL_ERROR; 800521a: 2301 movs r3, #1 800521c: e0be b.n 800539c assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800521e: 687b ldr r3, [r7, #4] 8005220: 689b ldr r3, [r3, #8] 8005222: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8005224: 687b ldr r3, [r7, #4] 8005226: 6a9b ldr r3, [r3, #40] @ 0x28 8005228: 2b00 cmp r3, #0 800522a: d109 bne.n 8005240 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800522c: 687b ldr r3, [r7, #4] 800522e: 2200 movs r2, #0 8005230: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8005232: 687b ldr r3, [r7, #4] 8005234: 2200 movs r2, #0 8005236: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800523a: 6878 ldr r0, [r7, #4] 800523c: f7ff fd88 bl 8004d50 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8005240: 6878 ldr r0, [r7, #4] 8005242: f000 faff bl 8005844 8005246: 4603 mov r3, r0 8005248: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800524a: 687b ldr r3, [r7, #4] 800524c: 6a9b ldr r3, [r3, #40] @ 0x28 800524e: f003 0310 and.w r3, r3, #16 8005252: 2b00 cmp r3, #0 8005254: f040 8099 bne.w 800538a 8005258: 7dfb ldrb r3, [r7, #23] 800525a: 2b00 cmp r3, #0 800525c: f040 8095 bne.w 800538a (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005260: 687b ldr r3, [r7, #4] 8005262: 6a9b ldr r3, [r3, #40] @ 0x28 8005264: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8005268: f023 0302 bic.w r3, r3, #2 800526c: f043 0202 orr.w r2, r3, #2 8005270: 687b ldr r3, [r7, #4] 8005272: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8005274: 687b ldr r3, [r7, #4] 8005276: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8005278: 687b ldr r3, [r7, #4] 800527a: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800527c: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800527e: 687b ldr r3, [r7, #4] 8005280: 7b1b ldrb r3, [r3, #12] 8005282: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8005284: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8005286: 68ba ldr r2, [r7, #8] 8005288: 4313 orrs r3, r2 800528a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800528c: 687b ldr r3, [r7, #4] 800528e: 689b ldr r3, [r3, #8] 8005290: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005294: d003 beq.n 800529e 8005296: 687b ldr r3, [r7, #4] 8005298: 689b ldr r3, [r3, #8] 800529a: 2b01 cmp r3, #1 800529c: d102 bne.n 80052a4 800529e: f44f 7380 mov.w r3, #256 @ 0x100 80052a2: e000 b.n 80052a6 80052a4: 2300 movs r3, #0 80052a6: 693a ldr r2, [r7, #16] 80052a8: 4313 orrs r3, r2 80052aa: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80052ac: 687b ldr r3, [r7, #4] 80052ae: 7d1b ldrb r3, [r3, #20] 80052b0: 2b01 cmp r3, #1 80052b2: d119 bne.n 80052e8 { if (hadc->Init.ContinuousConvMode == DISABLE) 80052b4: 687b ldr r3, [r7, #4] 80052b6: 7b1b ldrb r3, [r3, #12] 80052b8: 2b00 cmp r3, #0 80052ba: d109 bne.n 80052d0 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 80052bc: 687b ldr r3, [r7, #4] 80052be: 699b ldr r3, [r3, #24] 80052c0: 3b01 subs r3, #1 80052c2: 035a lsls r2, r3, #13 80052c4: 693b ldr r3, [r7, #16] 80052c6: 4313 orrs r3, r2 80052c8: f443 6300 orr.w r3, r3, #2048 @ 0x800 80052cc: 613b str r3, [r7, #16] 80052ce: e00b b.n 80052e8 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80052d0: 687b ldr r3, [r7, #4] 80052d2: 6a9b ldr r3, [r3, #40] @ 0x28 80052d4: f043 0220 orr.w r2, r3, #32 80052d8: 687b ldr r3, [r7, #4] 80052da: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80052dc: 687b ldr r3, [r7, #4] 80052de: 6adb ldr r3, [r3, #44] @ 0x2c 80052e0: f043 0201 orr.w r2, r3, #1 80052e4: 687b ldr r3, [r7, #4] 80052e6: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 80052e8: 687b ldr r3, [r7, #4] 80052ea: 681b ldr r3, [r3, #0] 80052ec: 685b ldr r3, [r3, #4] 80052ee: f423 4169 bic.w r1, r3, #59648 @ 0xe900 80052f2: 687b ldr r3, [r7, #4] 80052f4: 681b ldr r3, [r3, #0] 80052f6: 693a ldr r2, [r7, #16] 80052f8: 430a orrs r2, r1 80052fa: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 80052fc: 687b ldr r3, [r7, #4] 80052fe: 681b ldr r3, [r3, #0] 8005300: 689a ldr r2, [r3, #8] 8005302: 4b28 ldr r3, [pc, #160] @ (80053a4 ) 8005304: 4013 ands r3, r2 8005306: 687a ldr r2, [r7, #4] 8005308: 6812 ldr r2, [r2, #0] 800530a: 68b9 ldr r1, [r7, #8] 800530c: 430b orrs r3, r1 800530e: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8005310: 687b ldr r3, [r7, #4] 8005312: 689b ldr r3, [r3, #8] 8005314: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005318: d003 beq.n 8005322 800531a: 687b ldr r3, [r7, #4] 800531c: 689b ldr r3, [r3, #8] 800531e: 2b01 cmp r3, #1 8005320: d104 bne.n 800532c { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8005322: 687b ldr r3, [r7, #4] 8005324: 691b ldr r3, [r3, #16] 8005326: 3b01 subs r3, #1 8005328: 051b lsls r3, r3, #20 800532a: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800532c: 687b ldr r3, [r7, #4] 800532e: 681b ldr r3, [r3, #0] 8005330: 6adb ldr r3, [r3, #44] @ 0x2c 8005332: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 8005336: 687b ldr r3, [r7, #4] 8005338: 681b ldr r3, [r3, #0] 800533a: 68fa ldr r2, [r7, #12] 800533c: 430a orrs r2, r1 800533e: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005340: 687b ldr r3, [r7, #4] 8005342: 681b ldr r3, [r3, #0] 8005344: 689a ldr r2, [r3, #8] 8005346: 4b18 ldr r3, [pc, #96] @ (80053a8 ) 8005348: 4013 ands r3, r2 800534a: 68ba ldr r2, [r7, #8] 800534c: 429a cmp r2, r3 800534e: d10b bne.n 8005368 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8005350: 687b ldr r3, [r7, #4] 8005352: 2200 movs r2, #0 8005354: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8005356: 687b ldr r3, [r7, #4] 8005358: 6a9b ldr r3, [r3, #40] @ 0x28 800535a: f023 0303 bic.w r3, r3, #3 800535e: f043 0201 orr.w r2, r3, #1 8005362: 687b ldr r3, [r7, #4] 8005364: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005366: e018 b.n 800539a HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8005368: 687b ldr r3, [r7, #4] 800536a: 6a9b ldr r3, [r3, #40] @ 0x28 800536c: f023 0312 bic.w r3, r3, #18 8005370: f043 0210 orr.w r2, r3, #16 8005374: 687b ldr r3, [r7, #4] 8005376: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005378: 687b ldr r3, [r7, #4] 800537a: 6adb ldr r3, [r3, #44] @ 0x2c 800537c: f043 0201 orr.w r2, r3, #1 8005380: 687b ldr r3, [r7, #4] 8005382: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 8005384: 2301 movs r3, #1 8005386: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8005388: e007 b.n 800539a } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800538a: 687b ldr r3, [r7, #4] 800538c: 6a9b ldr r3, [r3, #40] @ 0x28 800538e: f043 0210 orr.w r2, r3, #16 8005392: 687b ldr r3, [r7, #4] 8005394: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 8005396: 2301 movs r3, #1 8005398: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800539a: 7dfb ldrb r3, [r7, #23] } 800539c: 4618 mov r0, r3 800539e: 3718 adds r7, #24 80053a0: 46bd mov sp, r7 80053a2: bd80 pop {r7, pc} 80053a4: ffe1f7fd .word 0xffe1f7fd 80053a8: ff1f0efe .word 0xff1f0efe 080053ac : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 80053ac: b580 push {r7, lr} 80053ae: b086 sub sp, #24 80053b0: af00 add r7, sp, #0 80053b2: 60f8 str r0, [r7, #12] 80053b4: 60b9 str r1, [r7, #8] 80053b6: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80053b8: 2300 movs r3, #0 80053ba: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 80053bc: 68fb ldr r3, [r7, #12] 80053be: 681b ldr r3, [r3, #0] 80053c0: 4a64 ldr r2, [pc, #400] @ (8005554 ) 80053c2: 4293 cmp r3, r2 80053c4: d004 beq.n 80053d0 80053c6: 68fb ldr r3, [r7, #12] 80053c8: 681b ldr r3, [r3, #0] 80053ca: 4a63 ldr r2, [pc, #396] @ (8005558 ) 80053cc: 4293 cmp r3, r2 80053ce: d106 bne.n 80053de 80053d0: 4b60 ldr r3, [pc, #384] @ (8005554 ) 80053d2: 685b ldr r3, [r3, #4] 80053d4: f403 2370 and.w r3, r3, #983040 @ 0xf0000 80053d8: 2b00 cmp r3, #0 80053da: f040 80b3 bne.w 8005544 { /* Process locked */ __HAL_LOCK(hadc); 80053de: 68fb ldr r3, [r7, #12] 80053e0: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80053e4: 2b01 cmp r3, #1 80053e6: d101 bne.n 80053ec 80053e8: 2302 movs r3, #2 80053ea: e0ae b.n 800554a 80053ec: 68fb ldr r3, [r7, #12] 80053ee: 2201 movs r2, #1 80053f0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 80053f4: 68f8 ldr r0, [r7, #12] 80053f6: f000 f9cb bl 8005790 80053fa: 4603 mov r3, r0 80053fc: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 80053fe: 7dfb ldrb r3, [r7, #23] 8005400: 2b00 cmp r3, #0 8005402: f040 809a bne.w 800553a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8005406: 68fb ldr r3, [r7, #12] 8005408: 6a9b ldr r3, [r3, #40] @ 0x28 800540a: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800540e: f023 0301 bic.w r3, r3, #1 8005412: f443 7280 orr.w r2, r3, #256 @ 0x100 8005416: 68fb ldr r3, [r7, #12] 8005418: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800541a: 68fb ldr r3, [r7, #12] 800541c: 681b ldr r3, [r3, #0] 800541e: 4a4e ldr r2, [pc, #312] @ (8005558 ) 8005420: 4293 cmp r3, r2 8005422: d105 bne.n 8005430 8005424: 4b4b ldr r3, [pc, #300] @ (8005554 ) 8005426: 685b ldr r3, [r3, #4] 8005428: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800542c: 2b00 cmp r3, #0 800542e: d115 bne.n 800545c { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8005430: 68fb ldr r3, [r7, #12] 8005432: 6a9b ldr r3, [r3, #40] @ 0x28 8005434: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8005438: 68fb ldr r3, [r7, #12] 800543a: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800543c: 68fb ldr r3, [r7, #12] 800543e: 681b ldr r3, [r3, #0] 8005440: 685b ldr r3, [r3, #4] 8005442: f403 6380 and.w r3, r3, #1024 @ 0x400 8005446: 2b00 cmp r3, #0 8005448: d026 beq.n 8005498 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800544a: 68fb ldr r3, [r7, #12] 800544c: 6a9b ldr r3, [r3, #40] @ 0x28 800544e: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8005452: f443 5280 orr.w r2, r3, #4096 @ 0x1000 8005456: 68fb ldr r3, [r7, #12] 8005458: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800545a: e01d b.n 8005498 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800545c: 68fb ldr r3, [r7, #12] 800545e: 6a9b ldr r3, [r3, #40] @ 0x28 8005460: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8005464: 68fb ldr r3, [r7, #12] 8005466: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8005468: 68fb ldr r3, [r7, #12] 800546a: 681b ldr r3, [r3, #0] 800546c: 4a39 ldr r2, [pc, #228] @ (8005554 ) 800546e: 4293 cmp r3, r2 8005470: d004 beq.n 800547c 8005472: 68fb ldr r3, [r7, #12] 8005474: 681b ldr r3, [r3, #0] 8005476: 4a38 ldr r2, [pc, #224] @ (8005558 ) 8005478: 4293 cmp r3, r2 800547a: d10d bne.n 8005498 800547c: 4b35 ldr r3, [pc, #212] @ (8005554 ) 800547e: 685b ldr r3, [r3, #4] 8005480: f403 6380 and.w r3, r3, #1024 @ 0x400 8005484: 2b00 cmp r3, #0 8005486: d007 beq.n 8005498 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8005488: 68fb ldr r3, [r7, #12] 800548a: 6a9b ldr r3, [r3, #40] @ 0x28 800548c: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8005490: f443 5280 orr.w r2, r3, #4096 @ 0x1000 8005494: 68fb ldr r3, [r7, #12] 8005496: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8005498: 68fb ldr r3, [r7, #12] 800549a: 6a9b ldr r3, [r3, #40] @ 0x28 800549c: f403 5380 and.w r3, r3, #4096 @ 0x1000 80054a0: 2b00 cmp r3, #0 80054a2: d006 beq.n 80054b2 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 80054a4: 68fb ldr r3, [r7, #12] 80054a6: 6adb ldr r3, [r3, #44] @ 0x2c 80054a8: f023 0206 bic.w r2, r3, #6 80054ac: 68fb ldr r3, [r7, #12] 80054ae: 62da str r2, [r3, #44] @ 0x2c 80054b0: e002 b.n 80054b8 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 80054b2: 68fb ldr r3, [r7, #12] 80054b4: 2200 movs r2, #0 80054b6: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 80054b8: 68fb ldr r3, [r7, #12] 80054ba: 2200 movs r2, #0 80054bc: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 80054c0: 68fb ldr r3, [r7, #12] 80054c2: 6a1b ldr r3, [r3, #32] 80054c4: 4a25 ldr r2, [pc, #148] @ (800555c ) 80054c6: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 80054c8: 68fb ldr r3, [r7, #12] 80054ca: 6a1b ldr r3, [r3, #32] 80054cc: 4a24 ldr r2, [pc, #144] @ (8005560 ) 80054ce: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 80054d0: 68fb ldr r3, [r7, #12] 80054d2: 6a1b ldr r3, [r3, #32] 80054d4: 4a23 ldr r2, [pc, #140] @ (8005564 ) 80054d6: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 80054d8: 68fb ldr r3, [r7, #12] 80054da: 681b ldr r3, [r3, #0] 80054dc: f06f 0202 mvn.w r2, #2 80054e0: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 80054e2: 68fb ldr r3, [r7, #12] 80054e4: 681b ldr r3, [r3, #0] 80054e6: 689a ldr r2, [r3, #8] 80054e8: 68fb ldr r3, [r7, #12] 80054ea: 681b ldr r3, [r3, #0] 80054ec: f442 7280 orr.w r2, r2, #256 @ 0x100 80054f0: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 80054f2: 68fb ldr r3, [r7, #12] 80054f4: 6a18 ldr r0, [r3, #32] 80054f6: 68fb ldr r3, [r7, #12] 80054f8: 681b ldr r3, [r3, #0] 80054fa: 334c adds r3, #76 @ 0x4c 80054fc: 4619 mov r1, r3 80054fe: 68ba ldr r2, [r7, #8] 8005500: 687b ldr r3, [r7, #4] 8005502: f000 fbb5 bl 8005c70 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 8005506: 68fb ldr r3, [r7, #12] 8005508: 681b ldr r3, [r3, #0] 800550a: 689b ldr r3, [r3, #8] 800550c: f403 2360 and.w r3, r3, #917504 @ 0xe0000 8005510: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 8005514: d108 bne.n 8005528 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8005516: 68fb ldr r3, [r7, #12] 8005518: 681b ldr r3, [r3, #0] 800551a: 689a ldr r2, [r3, #8] 800551c: 68fb ldr r3, [r7, #12] 800551e: 681b ldr r3, [r3, #0] 8005520: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 8005524: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 8005526: e00f b.n 8005548 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8005528: 68fb ldr r3, [r7, #12] 800552a: 681b ldr r3, [r3, #0] 800552c: 689a ldr r2, [r3, #8] 800552e: 68fb ldr r3, [r7, #12] 8005530: 681b ldr r3, [r3, #0] 8005532: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 8005536: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 8005538: e006 b.n 8005548 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800553a: 68fb ldr r3, [r7, #12] 800553c: 2200 movs r2, #0 800553e: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 8005542: e001 b.n 8005548 } } else { tmp_hal_status = HAL_ERROR; 8005544: 2301 movs r3, #1 8005546: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8005548: 7dfb ldrb r3, [r7, #23] } 800554a: 4618 mov r0, r3 800554c: 3718 adds r7, #24 800554e: 46bd mov sp, r7 8005550: bd80 pop {r7, pc} 8005552: bf00 nop 8005554: 40012400 .word 0x40012400 8005558: 40012800 .word 0x40012800 800555c: 080058c7 .word 0x080058c7 8005560: 08005943 .word 0x08005943 8005564: 0800595f .word 0x0800595f 08005568 : * @brief Conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 8005568: b480 push {r7} 800556a: b083 sub sp, #12 800556c: af00 add r7, sp, #0 800556e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } 8005570: bf00 nop 8005572: 370c adds r7, #12 8005574: 46bd mov sp, r7 8005576: bc80 pop {r7} 8005578: 4770 bx lr 0800557a : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800557a: b480 push {r7} 800557c: b083 sub sp, #12 800557e: af00 add r7, sp, #0 8005580: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8005582: bf00 nop 8005584: 370c adds r7, #12 8005586: 46bd mov sp, r7 8005588: bc80 pop {r7} 800558a: 4770 bx lr 0800558c : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800558c: b480 push {r7} 800558e: b083 sub sp, #12 8005590: af00 add r7, sp, #0 8005592: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8005594: bf00 nop 8005596: 370c adds r7, #12 8005598: 46bd mov sp, r7 800559a: bc80 pop {r7} 800559c: 4770 bx lr ... 080055a0 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 80055a0: b480 push {r7} 80055a2: b085 sub sp, #20 80055a4: af00 add r7, sp, #0 80055a6: 6078 str r0, [r7, #4] 80055a8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80055aa: 2300 movs r3, #0 80055ac: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 80055ae: 2300 movs r3, #0 80055b0: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 80055b2: 687b ldr r3, [r7, #4] 80055b4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80055b8: 2b01 cmp r3, #1 80055ba: d101 bne.n 80055c0 80055bc: 2302 movs r3, #2 80055be: e0dc b.n 800577a 80055c0: 687b ldr r3, [r7, #4] 80055c2: 2201 movs r2, #1 80055c4: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 80055c8: 683b ldr r3, [r7, #0] 80055ca: 685b ldr r3, [r3, #4] 80055cc: 2b06 cmp r3, #6 80055ce: d81c bhi.n 800560a { MODIFY_REG(hadc->Instance->SQR3 , 80055d0: 687b ldr r3, [r7, #4] 80055d2: 681b ldr r3, [r3, #0] 80055d4: 6b59 ldr r1, [r3, #52] @ 0x34 80055d6: 683b ldr r3, [r7, #0] 80055d8: 685a ldr r2, [r3, #4] 80055da: 4613 mov r3, r2 80055dc: 009b lsls r3, r3, #2 80055de: 4413 add r3, r2 80055e0: 3b05 subs r3, #5 80055e2: 221f movs r2, #31 80055e4: fa02 f303 lsl.w r3, r2, r3 80055e8: 43db mvns r3, r3 80055ea: 4019 ands r1, r3 80055ec: 683b ldr r3, [r7, #0] 80055ee: 6818 ldr r0, [r3, #0] 80055f0: 683b ldr r3, [r7, #0] 80055f2: 685a ldr r2, [r3, #4] 80055f4: 4613 mov r3, r2 80055f6: 009b lsls r3, r3, #2 80055f8: 4413 add r3, r2 80055fa: 3b05 subs r3, #5 80055fc: fa00 f203 lsl.w r2, r0, r3 8005600: 687b ldr r3, [r7, #4] 8005602: 681b ldr r3, [r3, #0] 8005604: 430a orrs r2, r1 8005606: 635a str r2, [r3, #52] @ 0x34 8005608: e03c b.n 8005684 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800560a: 683b ldr r3, [r7, #0] 800560c: 685b ldr r3, [r3, #4] 800560e: 2b0c cmp r3, #12 8005610: d81c bhi.n 800564c { MODIFY_REG(hadc->Instance->SQR2 , 8005612: 687b ldr r3, [r7, #4] 8005614: 681b ldr r3, [r3, #0] 8005616: 6b19 ldr r1, [r3, #48] @ 0x30 8005618: 683b ldr r3, [r7, #0] 800561a: 685a ldr r2, [r3, #4] 800561c: 4613 mov r3, r2 800561e: 009b lsls r3, r3, #2 8005620: 4413 add r3, r2 8005622: 3b23 subs r3, #35 @ 0x23 8005624: 221f movs r2, #31 8005626: fa02 f303 lsl.w r3, r2, r3 800562a: 43db mvns r3, r3 800562c: 4019 ands r1, r3 800562e: 683b ldr r3, [r7, #0] 8005630: 6818 ldr r0, [r3, #0] 8005632: 683b ldr r3, [r7, #0] 8005634: 685a ldr r2, [r3, #4] 8005636: 4613 mov r3, r2 8005638: 009b lsls r3, r3, #2 800563a: 4413 add r3, r2 800563c: 3b23 subs r3, #35 @ 0x23 800563e: fa00 f203 lsl.w r2, r0, r3 8005642: 687b ldr r3, [r7, #4] 8005644: 681b ldr r3, [r3, #0] 8005646: 430a orrs r2, r1 8005648: 631a str r2, [r3, #48] @ 0x30 800564a: e01b b.n 8005684 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800564c: 687b ldr r3, [r7, #4] 800564e: 681b ldr r3, [r3, #0] 8005650: 6ad9 ldr r1, [r3, #44] @ 0x2c 8005652: 683b ldr r3, [r7, #0] 8005654: 685a ldr r2, [r3, #4] 8005656: 4613 mov r3, r2 8005658: 009b lsls r3, r3, #2 800565a: 4413 add r3, r2 800565c: 3b41 subs r3, #65 @ 0x41 800565e: 221f movs r2, #31 8005660: fa02 f303 lsl.w r3, r2, r3 8005664: 43db mvns r3, r3 8005666: 4019 ands r1, r3 8005668: 683b ldr r3, [r7, #0] 800566a: 6818 ldr r0, [r3, #0] 800566c: 683b ldr r3, [r7, #0] 800566e: 685a ldr r2, [r3, #4] 8005670: 4613 mov r3, r2 8005672: 009b lsls r3, r3, #2 8005674: 4413 add r3, r2 8005676: 3b41 subs r3, #65 @ 0x41 8005678: fa00 f203 lsl.w r2, r0, r3 800567c: 687b ldr r3, [r7, #4] 800567e: 681b ldr r3, [r3, #0] 8005680: 430a orrs r2, r1 8005682: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8005684: 683b ldr r3, [r7, #0] 8005686: 681b ldr r3, [r3, #0] 8005688: 2b09 cmp r3, #9 800568a: d91c bls.n 80056c6 { MODIFY_REG(hadc->Instance->SMPR1 , 800568c: 687b ldr r3, [r7, #4] 800568e: 681b ldr r3, [r3, #0] 8005690: 68d9 ldr r1, [r3, #12] 8005692: 683b ldr r3, [r7, #0] 8005694: 681a ldr r2, [r3, #0] 8005696: 4613 mov r3, r2 8005698: 005b lsls r3, r3, #1 800569a: 4413 add r3, r2 800569c: 3b1e subs r3, #30 800569e: 2207 movs r2, #7 80056a0: fa02 f303 lsl.w r3, r2, r3 80056a4: 43db mvns r3, r3 80056a6: 4019 ands r1, r3 80056a8: 683b ldr r3, [r7, #0] 80056aa: 6898 ldr r0, [r3, #8] 80056ac: 683b ldr r3, [r7, #0] 80056ae: 681a ldr r2, [r3, #0] 80056b0: 4613 mov r3, r2 80056b2: 005b lsls r3, r3, #1 80056b4: 4413 add r3, r2 80056b6: 3b1e subs r3, #30 80056b8: fa00 f203 lsl.w r2, r0, r3 80056bc: 687b ldr r3, [r7, #4] 80056be: 681b ldr r3, [r3, #0] 80056c0: 430a orrs r2, r1 80056c2: 60da str r2, [r3, #12] 80056c4: e019 b.n 80056fa ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 80056c6: 687b ldr r3, [r7, #4] 80056c8: 681b ldr r3, [r3, #0] 80056ca: 6919 ldr r1, [r3, #16] 80056cc: 683b ldr r3, [r7, #0] 80056ce: 681a ldr r2, [r3, #0] 80056d0: 4613 mov r3, r2 80056d2: 005b lsls r3, r3, #1 80056d4: 4413 add r3, r2 80056d6: 2207 movs r2, #7 80056d8: fa02 f303 lsl.w r3, r2, r3 80056dc: 43db mvns r3, r3 80056de: 4019 ands r1, r3 80056e0: 683b ldr r3, [r7, #0] 80056e2: 6898 ldr r0, [r3, #8] 80056e4: 683b ldr r3, [r7, #0] 80056e6: 681a ldr r2, [r3, #0] 80056e8: 4613 mov r3, r2 80056ea: 005b lsls r3, r3, #1 80056ec: 4413 add r3, r2 80056ee: fa00 f203 lsl.w r2, r0, r3 80056f2: 687b ldr r3, [r7, #4] 80056f4: 681b ldr r3, [r3, #0] 80056f6: 430a orrs r2, r1 80056f8: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80056fa: 683b ldr r3, [r7, #0] 80056fc: 681b ldr r3, [r3, #0] 80056fe: 2b10 cmp r3, #16 8005700: d003 beq.n 800570a (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8005702: 683b ldr r3, [r7, #0] 8005704: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8005706: 2b11 cmp r3, #17 8005708: d132 bne.n 8005770 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800570a: 687b ldr r3, [r7, #4] 800570c: 681b ldr r3, [r3, #0] 800570e: 4a1d ldr r2, [pc, #116] @ (8005784 ) 8005710: 4293 cmp r3, r2 8005712: d125 bne.n 8005760 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8005714: 687b ldr r3, [r7, #4] 8005716: 681b ldr r3, [r3, #0] 8005718: 689b ldr r3, [r3, #8] 800571a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800571e: 2b00 cmp r3, #0 8005720: d126 bne.n 8005770 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8005722: 687b ldr r3, [r7, #4] 8005724: 681b ldr r3, [r3, #0] 8005726: 689a ldr r2, [r3, #8] 8005728: 687b ldr r3, [r7, #4] 800572a: 681b ldr r3, [r3, #0] 800572c: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8005730: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8005732: 683b ldr r3, [r7, #0] 8005734: 681b ldr r3, [r3, #0] 8005736: 2b10 cmp r3, #16 8005738: d11a bne.n 8005770 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800573a: 4b13 ldr r3, [pc, #76] @ (8005788 ) 800573c: 681b ldr r3, [r3, #0] 800573e: 4a13 ldr r2, [pc, #76] @ (800578c ) 8005740: fba2 2303 umull r2, r3, r2, r3 8005744: 0c9a lsrs r2, r3, #18 8005746: 4613 mov r3, r2 8005748: 009b lsls r3, r3, #2 800574a: 4413 add r3, r2 800574c: 005b lsls r3, r3, #1 800574e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8005750: e002 b.n 8005758 { wait_loop_index--; 8005752: 68bb ldr r3, [r7, #8] 8005754: 3b01 subs r3, #1 8005756: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8005758: 68bb ldr r3, [r7, #8] 800575a: 2b00 cmp r3, #0 800575c: d1f9 bne.n 8005752 800575e: e007 b.n 8005770 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8005760: 687b ldr r3, [r7, #4] 8005762: 6a9b ldr r3, [r3, #40] @ 0x28 8005764: f043 0220 orr.w r2, r3, #32 8005768: 687b ldr r3, [r7, #4] 800576a: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800576c: 2301 movs r3, #1 800576e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8005770: 687b ldr r3, [r7, #4] 8005772: 2200 movs r2, #0 8005774: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 8005778: 7bfb ldrb r3, [r7, #15] } 800577a: 4618 mov r0, r3 800577c: 3714 adds r7, #20 800577e: 46bd mov sp, r7 8005780: bc80 pop {r7} 8005782: 4770 bx lr 8005784: 40012400 .word 0x40012400 8005788: 20000010 .word 0x20000010 800578c: 431bde83 .word 0x431bde83 08005790 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8005790: b580 push {r7, lr} 8005792: b084 sub sp, #16 8005794: af00 add r7, sp, #0 8005796: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8005798: 2300 movs r3, #0 800579a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800579c: 2300 movs r3, #0 800579e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 80057a0: 687b ldr r3, [r7, #4] 80057a2: 681b ldr r3, [r3, #0] 80057a4: 689b ldr r3, [r3, #8] 80057a6: f003 0301 and.w r3, r3, #1 80057aa: 2b01 cmp r3, #1 80057ac: d040 beq.n 8005830 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 80057ae: 687b ldr r3, [r7, #4] 80057b0: 681b ldr r3, [r3, #0] 80057b2: 689a ldr r2, [r3, #8] 80057b4: 687b ldr r3, [r7, #4] 80057b6: 681b ldr r3, [r3, #0] 80057b8: f042 0201 orr.w r2, r2, #1 80057bc: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 80057be: 4b1f ldr r3, [pc, #124] @ (800583c ) 80057c0: 681b ldr r3, [r3, #0] 80057c2: 4a1f ldr r2, [pc, #124] @ (8005840 ) 80057c4: fba2 2303 umull r2, r3, r2, r3 80057c8: 0c9b lsrs r3, r3, #18 80057ca: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80057cc: e002 b.n 80057d4 { wait_loop_index--; 80057ce: 68bb ldr r3, [r7, #8] 80057d0: 3b01 subs r3, #1 80057d2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80057d4: 68bb ldr r3, [r7, #8] 80057d6: 2b00 cmp r3, #0 80057d8: d1f9 bne.n 80057ce } /* Get tick count */ tickstart = HAL_GetTick(); 80057da: f7ff fd05 bl 80051e8 80057de: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 80057e0: e01f b.n 8005822 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80057e2: f7ff fd01 bl 80051e8 80057e6: 4602 mov r2, r0 80057e8: 68fb ldr r3, [r7, #12] 80057ea: 1ad3 subs r3, r2, r3 80057ec: 2b02 cmp r3, #2 80057ee: d918 bls.n 8005822 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 80057f0: 687b ldr r3, [r7, #4] 80057f2: 681b ldr r3, [r3, #0] 80057f4: 689b ldr r3, [r3, #8] 80057f6: f003 0301 and.w r3, r3, #1 80057fa: 2b01 cmp r3, #1 80057fc: d011 beq.n 8005822 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80057fe: 687b ldr r3, [r7, #4] 8005800: 6a9b ldr r3, [r3, #40] @ 0x28 8005802: f043 0210 orr.w r2, r3, #16 8005806: 687b ldr r3, [r7, #4] 8005808: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800580a: 687b ldr r3, [r7, #4] 800580c: 6adb ldr r3, [r3, #44] @ 0x2c 800580e: f043 0201 orr.w r2, r3, #1 8005812: 687b ldr r3, [r7, #4] 8005814: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 8005816: 687b ldr r3, [r7, #4] 8005818: 2200 movs r2, #0 800581a: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800581e: 2301 movs r3, #1 8005820: e007 b.n 8005832 while(ADC_IS_ENABLE(hadc) == RESET) 8005822: 687b ldr r3, [r7, #4] 8005824: 681b ldr r3, [r3, #0] 8005826: 689b ldr r3, [r3, #8] 8005828: f003 0301 and.w r3, r3, #1 800582c: 2b01 cmp r3, #1 800582e: d1d8 bne.n 80057e2 } } } /* Return HAL status */ return HAL_OK; 8005830: 2300 movs r3, #0 } 8005832: 4618 mov r0, r3 8005834: 3710 adds r7, #16 8005836: 46bd mov sp, r7 8005838: bd80 pop {r7, pc} 800583a: bf00 nop 800583c: 20000010 .word 0x20000010 8005840: 431bde83 .word 0x431bde83 08005844 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8005844: b580 push {r7, lr} 8005846: b084 sub sp, #16 8005848: af00 add r7, sp, #0 800584a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800584c: 2300 movs r3, #0 800584e: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8005850: 687b ldr r3, [r7, #4] 8005852: 681b ldr r3, [r3, #0] 8005854: 689b ldr r3, [r3, #8] 8005856: f003 0301 and.w r3, r3, #1 800585a: 2b01 cmp r3, #1 800585c: d12e bne.n 80058bc { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800585e: 687b ldr r3, [r7, #4] 8005860: 681b ldr r3, [r3, #0] 8005862: 689a ldr r2, [r3, #8] 8005864: 687b ldr r3, [r7, #4] 8005866: 681b ldr r3, [r3, #0] 8005868: f022 0201 bic.w r2, r2, #1 800586c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800586e: f7ff fcbb bl 80051e8 8005872: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8005874: e01b b.n 80058ae { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8005876: f7ff fcb7 bl 80051e8 800587a: 4602 mov r2, r0 800587c: 68fb ldr r3, [r7, #12] 800587e: 1ad3 subs r3, r2, r3 8005880: 2b02 cmp r3, #2 8005882: d914 bls.n 80058ae { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8005884: 687b ldr r3, [r7, #4] 8005886: 681b ldr r3, [r3, #0] 8005888: 689b ldr r3, [r3, #8] 800588a: f003 0301 and.w r3, r3, #1 800588e: 2b01 cmp r3, #1 8005890: d10d bne.n 80058ae { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005892: 687b ldr r3, [r7, #4] 8005894: 6a9b ldr r3, [r3, #40] @ 0x28 8005896: f043 0210 orr.w r2, r3, #16 800589a: 687b ldr r3, [r7, #4] 800589c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800589e: 687b ldr r3, [r7, #4] 80058a0: 6adb ldr r3, [r3, #44] @ 0x2c 80058a2: f043 0201 orr.w r2, r3, #1 80058a6: 687b ldr r3, [r7, #4] 80058a8: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 80058aa: 2301 movs r3, #1 80058ac: e007 b.n 80058be while(ADC_IS_ENABLE(hadc) != RESET) 80058ae: 687b ldr r3, [r7, #4] 80058b0: 681b ldr r3, [r3, #0] 80058b2: 689b ldr r3, [r3, #8] 80058b4: f003 0301 and.w r3, r3, #1 80058b8: 2b01 cmp r3, #1 80058ba: d0dc beq.n 8005876 } } } /* Return HAL status */ return HAL_OK; 80058bc: 2300 movs r3, #0 } 80058be: 4618 mov r0, r3 80058c0: 3710 adds r7, #16 80058c2: 46bd mov sp, r7 80058c4: bd80 pop {r7, pc} 080058c6 : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 80058c6: b580 push {r7, lr} 80058c8: b084 sub sp, #16 80058ca: af00 add r7, sp, #0 80058cc: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80058ce: 687b ldr r3, [r7, #4] 80058d0: 6a5b ldr r3, [r3, #36] @ 0x24 80058d2: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 80058d4: 68fb ldr r3, [r7, #12] 80058d6: 6a9b ldr r3, [r3, #40] @ 0x28 80058d8: f003 0350 and.w r3, r3, #80 @ 0x50 80058dc: 2b00 cmp r3, #0 80058de: d127 bne.n 8005930 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80058e0: 68fb ldr r3, [r7, #12] 80058e2: 6a9b ldr r3, [r3, #40] @ 0x28 80058e4: f443 7200 orr.w r2, r3, #512 @ 0x200 80058e8: 68fb ldr r3, [r7, #12] 80058ea: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80058ec: 68fb ldr r3, [r7, #12] 80058ee: 681b ldr r3, [r3, #0] 80058f0: 689b ldr r3, [r3, #8] 80058f2: f403 2360 and.w r3, r3, #917504 @ 0xe0000 80058f6: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 80058fa: d115 bne.n 8005928 (hadc->Init.ContinuousConvMode == DISABLE) ) 80058fc: 68fb ldr r3, [r7, #12] 80058fe: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8005900: 2b00 cmp r3, #0 8005902: d111 bne.n 8005928 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8005904: 68fb ldr r3, [r7, #12] 8005906: 6a9b ldr r3, [r3, #40] @ 0x28 8005908: f423 7280 bic.w r2, r3, #256 @ 0x100 800590c: 68fb ldr r3, [r7, #12] 800590e: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8005910: 68fb ldr r3, [r7, #12] 8005912: 6a9b ldr r3, [r3, #40] @ 0x28 8005914: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005918: 2b00 cmp r3, #0 800591a: d105 bne.n 8005928 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800591c: 68fb ldr r3, [r7, #12] 800591e: 6a9b ldr r3, [r3, #40] @ 0x28 8005920: f043 0201 orr.w r2, r3, #1 8005924: 68fb ldr r3, [r7, #12] 8005926: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8005928: 68f8 ldr r0, [r7, #12] 800592a: f7ff fe1d bl 8005568 else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800592e: e004 b.n 800593a hadc->DMA_Handle->XferErrorCallback(hdma); 8005930: 68fb ldr r3, [r7, #12] 8005932: 6a1b ldr r3, [r3, #32] 8005934: 6b1b ldr r3, [r3, #48] @ 0x30 8005936: 6878 ldr r0, [r7, #4] 8005938: 4798 blx r3 } 800593a: bf00 nop 800593c: 3710 adds r7, #16 800593e: 46bd mov sp, r7 8005940: bd80 pop {r7, pc} 08005942 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8005942: b580 push {r7, lr} 8005944: b084 sub sp, #16 8005946: af00 add r7, sp, #0 8005948: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800594a: 687b ldr r3, [r7, #4] 800594c: 6a5b ldr r3, [r3, #36] @ 0x24 800594e: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8005950: 68f8 ldr r0, [r7, #12] 8005952: f7ff fe12 bl 800557a #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8005956: bf00 nop 8005958: 3710 adds r7, #16 800595a: 46bd mov sp, r7 800595c: bd80 pop {r7, pc} 0800595e : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800595e: b580 push {r7, lr} 8005960: b084 sub sp, #16 8005962: af00 add r7, sp, #0 8005964: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8005966: 687b ldr r3, [r7, #4] 8005968: 6a5b ldr r3, [r3, #36] @ 0x24 800596a: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800596c: 68fb ldr r3, [r7, #12] 800596e: 6a9b ldr r3, [r3, #40] @ 0x28 8005970: f043 0240 orr.w r2, r3, #64 @ 0x40 8005974: 68fb ldr r3, [r7, #12] 8005976: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8005978: 68fb ldr r3, [r7, #12] 800597a: 6adb ldr r3, [r3, #44] @ 0x2c 800597c: f043 0204 orr.w r2, r3, #4 8005980: 68fb ldr r3, [r7, #12] 8005982: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8005984: 68f8 ldr r0, [r7, #12] 8005986: f7ff fe01 bl 800558c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800598a: bf00 nop 800598c: 3710 adds r7, #16 800598e: 46bd mov sp, r7 8005990: bd80 pop {r7, pc} ... 08005994 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8005994: b480 push {r7} 8005996: b085 sub sp, #20 8005998: af00 add r7, sp, #0 800599a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800599c: 687b ldr r3, [r7, #4] 800599e: f003 0307 and.w r3, r3, #7 80059a2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80059a4: 4b0c ldr r3, [pc, #48] @ (80059d8 <__NVIC_SetPriorityGrouping+0x44>) 80059a6: 68db ldr r3, [r3, #12] 80059a8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80059aa: 68ba ldr r2, [r7, #8] 80059ac: f64f 03ff movw r3, #63743 @ 0xf8ff 80059b0: 4013 ands r3, r2 80059b2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80059b4: 68fb ldr r3, [r7, #12] 80059b6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80059b8: 68bb ldr r3, [r7, #8] 80059ba: 4313 orrs r3, r2 reg_value = (reg_value | 80059bc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80059c0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80059c4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80059c6: 4a04 ldr r2, [pc, #16] @ (80059d8 <__NVIC_SetPriorityGrouping+0x44>) 80059c8: 68bb ldr r3, [r7, #8] 80059ca: 60d3 str r3, [r2, #12] } 80059cc: bf00 nop 80059ce: 3714 adds r7, #20 80059d0: 46bd mov sp, r7 80059d2: bc80 pop {r7} 80059d4: 4770 bx lr 80059d6: bf00 nop 80059d8: e000ed00 .word 0xe000ed00 080059dc <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80059dc: b480 push {r7} 80059de: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80059e0: 4b04 ldr r3, [pc, #16] @ (80059f4 <__NVIC_GetPriorityGrouping+0x18>) 80059e2: 68db ldr r3, [r3, #12] 80059e4: 0a1b lsrs r3, r3, #8 80059e6: f003 0307 and.w r3, r3, #7 } 80059ea: 4618 mov r0, r3 80059ec: 46bd mov sp, r7 80059ee: bc80 pop {r7} 80059f0: 4770 bx lr 80059f2: bf00 nop 80059f4: e000ed00 .word 0xe000ed00 080059f8 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80059f8: b480 push {r7} 80059fa: b083 sub sp, #12 80059fc: af00 add r7, sp, #0 80059fe: 4603 mov r3, r0 8005a00: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8005a02: f997 3007 ldrsb.w r3, [r7, #7] 8005a06: 2b00 cmp r3, #0 8005a08: db0b blt.n 8005a22 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8005a0a: 79fb ldrb r3, [r7, #7] 8005a0c: f003 021f and.w r2, r3, #31 8005a10: 4906 ldr r1, [pc, #24] @ (8005a2c <__NVIC_EnableIRQ+0x34>) 8005a12: f997 3007 ldrsb.w r3, [r7, #7] 8005a16: 095b lsrs r3, r3, #5 8005a18: 2001 movs r0, #1 8005a1a: fa00 f202 lsl.w r2, r0, r2 8005a1e: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8005a22: bf00 nop 8005a24: 370c adds r7, #12 8005a26: 46bd mov sp, r7 8005a28: bc80 pop {r7} 8005a2a: 4770 bx lr 8005a2c: e000e100 .word 0xe000e100 08005a30 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8005a30: b480 push {r7} 8005a32: b083 sub sp, #12 8005a34: af00 add r7, sp, #0 8005a36: 4603 mov r3, r0 8005a38: 6039 str r1, [r7, #0] 8005a3a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8005a3c: f997 3007 ldrsb.w r3, [r7, #7] 8005a40: 2b00 cmp r3, #0 8005a42: db0a blt.n 8005a5a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8005a44: 683b ldr r3, [r7, #0] 8005a46: b2da uxtb r2, r3 8005a48: 490c ldr r1, [pc, #48] @ (8005a7c <__NVIC_SetPriority+0x4c>) 8005a4a: f997 3007 ldrsb.w r3, [r7, #7] 8005a4e: 0112 lsls r2, r2, #4 8005a50: b2d2 uxtb r2, r2 8005a52: 440b add r3, r1 8005a54: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8005a58: e00a b.n 8005a70 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8005a5a: 683b ldr r3, [r7, #0] 8005a5c: b2da uxtb r2, r3 8005a5e: 4908 ldr r1, [pc, #32] @ (8005a80 <__NVIC_SetPriority+0x50>) 8005a60: 79fb ldrb r3, [r7, #7] 8005a62: f003 030f and.w r3, r3, #15 8005a66: 3b04 subs r3, #4 8005a68: 0112 lsls r2, r2, #4 8005a6a: b2d2 uxtb r2, r2 8005a6c: 440b add r3, r1 8005a6e: 761a strb r2, [r3, #24] } 8005a70: bf00 nop 8005a72: 370c adds r7, #12 8005a74: 46bd mov sp, r7 8005a76: bc80 pop {r7} 8005a78: 4770 bx lr 8005a7a: bf00 nop 8005a7c: e000e100 .word 0xe000e100 8005a80: e000ed00 .word 0xe000ed00 08005a84 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8005a84: b480 push {r7} 8005a86: b089 sub sp, #36 @ 0x24 8005a88: af00 add r7, sp, #0 8005a8a: 60f8 str r0, [r7, #12] 8005a8c: 60b9 str r1, [r7, #8] 8005a8e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8005a90: 68fb ldr r3, [r7, #12] 8005a92: f003 0307 and.w r3, r3, #7 8005a96: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8005a98: 69fb ldr r3, [r7, #28] 8005a9a: f1c3 0307 rsb r3, r3, #7 8005a9e: 2b04 cmp r3, #4 8005aa0: bf28 it cs 8005aa2: 2304 movcs r3, #4 8005aa4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8005aa6: 69fb ldr r3, [r7, #28] 8005aa8: 3304 adds r3, #4 8005aaa: 2b06 cmp r3, #6 8005aac: d902 bls.n 8005ab4 8005aae: 69fb ldr r3, [r7, #28] 8005ab0: 3b03 subs r3, #3 8005ab2: e000 b.n 8005ab6 8005ab4: 2300 movs r3, #0 8005ab6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8005ab8: f04f 32ff mov.w r2, #4294967295 8005abc: 69bb ldr r3, [r7, #24] 8005abe: fa02 f303 lsl.w r3, r2, r3 8005ac2: 43da mvns r2, r3 8005ac4: 68bb ldr r3, [r7, #8] 8005ac6: 401a ands r2, r3 8005ac8: 697b ldr r3, [r7, #20] 8005aca: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8005acc: f04f 31ff mov.w r1, #4294967295 8005ad0: 697b ldr r3, [r7, #20] 8005ad2: fa01 f303 lsl.w r3, r1, r3 8005ad6: 43d9 mvns r1, r3 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8005adc: 4313 orrs r3, r2 ); } 8005ade: 4618 mov r0, r3 8005ae0: 3724 adds r7, #36 @ 0x24 8005ae2: 46bd mov sp, r7 8005ae4: bc80 pop {r7} 8005ae6: 4770 bx lr 08005ae8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8005ae8: b580 push {r7, lr} 8005aea: b082 sub sp, #8 8005aec: af00 add r7, sp, #0 8005aee: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8005af0: 687b ldr r3, [r7, #4] 8005af2: 3b01 subs r3, #1 8005af4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8005af8: d301 bcc.n 8005afe { return (1UL); /* Reload value impossible */ 8005afa: 2301 movs r3, #1 8005afc: e00f b.n 8005b1e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8005afe: 4a0a ldr r2, [pc, #40] @ (8005b28 ) 8005b00: 687b ldr r3, [r7, #4] 8005b02: 3b01 subs r3, #1 8005b04: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8005b06: 210f movs r1, #15 8005b08: f04f 30ff mov.w r0, #4294967295 8005b0c: f7ff ff90 bl 8005a30 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8005b10: 4b05 ldr r3, [pc, #20] @ (8005b28 ) 8005b12: 2200 movs r2, #0 8005b14: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8005b16: 4b04 ldr r3, [pc, #16] @ (8005b28 ) 8005b18: 2207 movs r2, #7 8005b1a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8005b1c: 2300 movs r3, #0 } 8005b1e: 4618 mov r0, r3 8005b20: 3708 adds r7, #8 8005b22: 46bd mov sp, r7 8005b24: bd80 pop {r7, pc} 8005b26: bf00 nop 8005b28: e000e010 .word 0xe000e010 08005b2c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8005b2c: b580 push {r7, lr} 8005b2e: b082 sub sp, #8 8005b30: af00 add r7, sp, #0 8005b32: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8005b34: 6878 ldr r0, [r7, #4] 8005b36: f7ff ff2d bl 8005994 <__NVIC_SetPriorityGrouping> } 8005b3a: bf00 nop 8005b3c: 3708 adds r7, #8 8005b3e: 46bd mov sp, r7 8005b40: bd80 pop {r7, pc} 08005b42 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8005b42: b580 push {r7, lr} 8005b44: b086 sub sp, #24 8005b46: af00 add r7, sp, #0 8005b48: 4603 mov r3, r0 8005b4a: 60b9 str r1, [r7, #8] 8005b4c: 607a str r2, [r7, #4] 8005b4e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8005b50: 2300 movs r3, #0 8005b52: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8005b54: f7ff ff42 bl 80059dc <__NVIC_GetPriorityGrouping> 8005b58: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8005b5a: 687a ldr r2, [r7, #4] 8005b5c: 68b9 ldr r1, [r7, #8] 8005b5e: 6978 ldr r0, [r7, #20] 8005b60: f7ff ff90 bl 8005a84 8005b64: 4602 mov r2, r0 8005b66: f997 300f ldrsb.w r3, [r7, #15] 8005b6a: 4611 mov r1, r2 8005b6c: 4618 mov r0, r3 8005b6e: f7ff ff5f bl 8005a30 <__NVIC_SetPriority> } 8005b72: bf00 nop 8005b74: 3718 adds r7, #24 8005b76: 46bd mov sp, r7 8005b78: bd80 pop {r7, pc} 08005b7a : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8005b7a: b580 push {r7, lr} 8005b7c: b082 sub sp, #8 8005b7e: af00 add r7, sp, #0 8005b80: 4603 mov r3, r0 8005b82: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8005b84: f997 3007 ldrsb.w r3, [r7, #7] 8005b88: 4618 mov r0, r3 8005b8a: f7ff ff35 bl 80059f8 <__NVIC_EnableIRQ> } 8005b8e: bf00 nop 8005b90: 3708 adds r7, #8 8005b92: 46bd mov sp, r7 8005b94: bd80 pop {r7, pc} 08005b96 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8005b96: b580 push {r7, lr} 8005b98: b082 sub sp, #8 8005b9a: af00 add r7, sp, #0 8005b9c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8005b9e: 6878 ldr r0, [r7, #4] 8005ba0: f7ff ffa2 bl 8005ae8 8005ba4: 4603 mov r3, r0 } 8005ba6: 4618 mov r0, r3 8005ba8: 3708 adds r7, #8 8005baa: 46bd mov sp, r7 8005bac: bd80 pop {r7, pc} 08005bae : /** * @brief This function handles SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { 8005bae: b580 push {r7, lr} 8005bb0: af00 add r7, sp, #0 HAL_SYSTICK_Callback(); 8005bb2: f7fc f827 bl 8001c04 } 8005bb6: bf00 nop 8005bb8: bd80 pop {r7, pc} ... 08005bbc : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8005bbc: b480 push {r7} 8005bbe: b085 sub sp, #20 8005bc0: af00 add r7, sp, #0 8005bc2: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8005bc4: 2300 movs r3, #0 8005bc6: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 8005bc8: 687b ldr r3, [r7, #4] 8005bca: 2b00 cmp r3, #0 8005bcc: d101 bne.n 8005bd2 { return HAL_ERROR; 8005bce: 2301 movs r3, #1 8005bd0: e043 b.n 8005c5a hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8005bd2: 687b ldr r3, [r7, #4] 8005bd4: 681b ldr r3, [r3, #0] 8005bd6: 461a mov r2, r3 8005bd8: 4b22 ldr r3, [pc, #136] @ (8005c64 ) 8005bda: 4413 add r3, r2 8005bdc: 4a22 ldr r2, [pc, #136] @ (8005c68 ) 8005bde: fba2 2303 umull r2, r3, r2, r3 8005be2: 091b lsrs r3, r3, #4 8005be4: 009a lsls r2, r3, #2 8005be6: 687b ldr r3, [r7, #4] 8005be8: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 8005bea: 687b ldr r3, [r7, #4] 8005bec: 4a1f ldr r2, [pc, #124] @ (8005c6c ) 8005bee: 63da str r2, [r3, #60] @ 0x3c #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 2202 movs r2, #2 8005bf4: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 681b ldr r3, [r3, #0] 8005bfc: 681b ldr r3, [r3, #0] 8005bfe: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8005c00: 68fb ldr r3, [r7, #12] 8005c02: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 8005c06: f023 0330 bic.w r3, r3, #48 @ 0x30 8005c0a: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8005c0c: 687b ldr r3, [r7, #4] 8005c0e: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 8005c10: 687b ldr r3, [r7, #4] 8005c12: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 8005c14: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8005c16: 687b ldr r3, [r7, #4] 8005c18: 68db ldr r3, [r3, #12] 8005c1a: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8005c1c: 687b ldr r3, [r7, #4] 8005c1e: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 8005c20: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8005c22: 687b ldr r3, [r7, #4] 8005c24: 695b ldr r3, [r3, #20] 8005c26: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8005c28: 687b ldr r3, [r7, #4] 8005c2a: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8005c2c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8005c2e: 687b ldr r3, [r7, #4] 8005c30: 69db ldr r3, [r3, #28] 8005c32: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8005c34: 68fa ldr r2, [r7, #12] 8005c36: 4313 orrs r3, r2 8005c38: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 681b ldr r3, [r3, #0] 8005c3e: 68fa ldr r2, [r7, #12] 8005c40: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8005c42: 687b ldr r3, [r7, #4] 8005c44: 2200 movs r2, #0 8005c46: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8005c48: 687b ldr r3, [r7, #4] 8005c4a: 2201 movs r2, #1 8005c4c: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8005c50: 687b ldr r3, [r7, #4] 8005c52: 2200 movs r2, #0 8005c54: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 8005c58: 2300 movs r3, #0 } 8005c5a: 4618 mov r0, r3 8005c5c: 3714 adds r7, #20 8005c5e: 46bd mov sp, r7 8005c60: bc80 pop {r7} 8005c62: 4770 bx lr 8005c64: bffdfff8 .word 0xbffdfff8 8005c68: cccccccd .word 0xcccccccd 8005c6c: 40020000 .word 0x40020000 08005c70 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8005c70: b580 push {r7, lr} 8005c72: b086 sub sp, #24 8005c74: af00 add r7, sp, #0 8005c76: 60f8 str r0, [r7, #12] 8005c78: 60b9 str r1, [r7, #8] 8005c7a: 607a str r2, [r7, #4] 8005c7c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005c7e: 2300 movs r3, #0 8005c80: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8005c82: 68fb ldr r3, [r7, #12] 8005c84: f893 3020 ldrb.w r3, [r3, #32] 8005c88: 2b01 cmp r3, #1 8005c8a: d101 bne.n 8005c90 8005c8c: 2302 movs r3, #2 8005c8e: e04b b.n 8005d28 8005c90: 68fb ldr r3, [r7, #12] 8005c92: 2201 movs r2, #1 8005c94: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 8005c98: 68fb ldr r3, [r7, #12] 8005c9a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8005c9e: b2db uxtb r3, r3 8005ca0: 2b01 cmp r3, #1 8005ca2: d13a bne.n 8005d1a { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8005ca4: 68fb ldr r3, [r7, #12] 8005ca6: 2202 movs r2, #2 8005ca8: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8005cac: 68fb ldr r3, [r7, #12] 8005cae: 2200 movs r2, #0 8005cb0: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8005cb2: 68fb ldr r3, [r7, #12] 8005cb4: 681b ldr r3, [r3, #0] 8005cb6: 681a ldr r2, [r3, #0] 8005cb8: 68fb ldr r3, [r7, #12] 8005cba: 681b ldr r3, [r3, #0] 8005cbc: f022 0201 bic.w r2, r2, #1 8005cc0: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8005cc2: 683b ldr r3, [r7, #0] 8005cc4: 687a ldr r2, [r7, #4] 8005cc6: 68b9 ldr r1, [r7, #8] 8005cc8: 68f8 ldr r0, [r7, #12] 8005cca: f000 f937 bl 8005f3c /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 8005cce: 68fb ldr r3, [r7, #12] 8005cd0: 6adb ldr r3, [r3, #44] @ 0x2c 8005cd2: 2b00 cmp r3, #0 8005cd4: d008 beq.n 8005ce8 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8005cd6: 68fb ldr r3, [r7, #12] 8005cd8: 681b ldr r3, [r3, #0] 8005cda: 681a ldr r2, [r3, #0] 8005cdc: 68fb ldr r3, [r7, #12] 8005cde: 681b ldr r3, [r3, #0] 8005ce0: f042 020e orr.w r2, r2, #14 8005ce4: 601a str r2, [r3, #0] 8005ce6: e00f b.n 8005d08 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8005ce8: 68fb ldr r3, [r7, #12] 8005cea: 681b ldr r3, [r3, #0] 8005cec: 681a ldr r2, [r3, #0] 8005cee: 68fb ldr r3, [r7, #12] 8005cf0: 681b ldr r3, [r3, #0] 8005cf2: f022 0204 bic.w r2, r2, #4 8005cf6: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8005cf8: 68fb ldr r3, [r7, #12] 8005cfa: 681b ldr r3, [r3, #0] 8005cfc: 681a ldr r2, [r3, #0] 8005cfe: 68fb ldr r3, [r7, #12] 8005d00: 681b ldr r3, [r3, #0] 8005d02: f042 020a orr.w r2, r2, #10 8005d06: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8005d08: 68fb ldr r3, [r7, #12] 8005d0a: 681b ldr r3, [r3, #0] 8005d0c: 681a ldr r2, [r3, #0] 8005d0e: 68fb ldr r3, [r7, #12] 8005d10: 681b ldr r3, [r3, #0] 8005d12: f042 0201 orr.w r2, r2, #1 8005d16: 601a str r2, [r3, #0] 8005d18: e005 b.n 8005d26 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8005d1a: 68fb ldr r3, [r7, #12] 8005d1c: 2200 movs r2, #0 8005d1e: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 8005d22: 2302 movs r3, #2 8005d24: 75fb strb r3, [r7, #23] } return status; 8005d26: 7dfb ldrb r3, [r7, #23] } 8005d28: 4618 mov r0, r3 8005d2a: 3718 adds r7, #24 8005d2c: 46bd mov sp, r7 8005d2e: bd80 pop {r7, pc} 08005d30 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8005d30: b580 push {r7, lr} 8005d32: b084 sub sp, #16 8005d34: af00 add r7, sp, #0 8005d36: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8005d38: 687b ldr r3, [r7, #4] 8005d3a: 6bdb ldr r3, [r3, #60] @ 0x3c 8005d3c: 681b ldr r3, [r3, #0] 8005d3e: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8005d40: 687b ldr r3, [r7, #4] 8005d42: 681b ldr r3, [r3, #0] 8005d44: 681b ldr r3, [r3, #0] 8005d46: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 8005d48: 687b ldr r3, [r7, #4] 8005d4a: 6c1b ldr r3, [r3, #64] @ 0x40 8005d4c: 2204 movs r2, #4 8005d4e: 409a lsls r2, r3 8005d50: 68fb ldr r3, [r7, #12] 8005d52: 4013 ands r3, r2 8005d54: 2b00 cmp r3, #0 8005d56: d04f beq.n 8005df8 8005d58: 68bb ldr r3, [r7, #8] 8005d5a: f003 0304 and.w r3, r3, #4 8005d5e: 2b00 cmp r3, #0 8005d60: d04a beq.n 8005df8 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8005d62: 687b ldr r3, [r7, #4] 8005d64: 681b ldr r3, [r3, #0] 8005d66: 681b ldr r3, [r3, #0] 8005d68: f003 0320 and.w r3, r3, #32 8005d6c: 2b00 cmp r3, #0 8005d6e: d107 bne.n 8005d80 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8005d70: 687b ldr r3, [r7, #4] 8005d72: 681b ldr r3, [r3, #0] 8005d74: 681a ldr r2, [r3, #0] 8005d76: 687b ldr r3, [r7, #4] 8005d78: 681b ldr r3, [r3, #0] 8005d7a: f022 0204 bic.w r2, r2, #4 8005d7e: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8005d80: 687b ldr r3, [r7, #4] 8005d82: 681b ldr r3, [r3, #0] 8005d84: 4a66 ldr r2, [pc, #408] @ (8005f20 ) 8005d86: 4293 cmp r3, r2 8005d88: d029 beq.n 8005dde 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 681b ldr r3, [r3, #0] 8005d8e: 4a65 ldr r2, [pc, #404] @ (8005f24 ) 8005d90: 4293 cmp r3, r2 8005d92: d022 beq.n 8005dda 8005d94: 687b ldr r3, [r7, #4] 8005d96: 681b ldr r3, [r3, #0] 8005d98: 4a63 ldr r2, [pc, #396] @ (8005f28 ) 8005d9a: 4293 cmp r3, r2 8005d9c: d01a beq.n 8005dd4 8005d9e: 687b ldr r3, [r7, #4] 8005da0: 681b ldr r3, [r3, #0] 8005da2: 4a62 ldr r2, [pc, #392] @ (8005f2c ) 8005da4: 4293 cmp r3, r2 8005da6: d012 beq.n 8005dce 8005da8: 687b ldr r3, [r7, #4] 8005daa: 681b ldr r3, [r3, #0] 8005dac: 4a60 ldr r2, [pc, #384] @ (8005f30 ) 8005dae: 4293 cmp r3, r2 8005db0: d00a beq.n 8005dc8 8005db2: 687b ldr r3, [r7, #4] 8005db4: 681b ldr r3, [r3, #0] 8005db6: 4a5f ldr r2, [pc, #380] @ (8005f34 ) 8005db8: 4293 cmp r3, r2 8005dba: d102 bne.n 8005dc2 8005dbc: f44f 0380 mov.w r3, #4194304 @ 0x400000 8005dc0: e00e b.n 8005de0 8005dc2: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8005dc6: e00b b.n 8005de0 8005dc8: f44f 2380 mov.w r3, #262144 @ 0x40000 8005dcc: e008 b.n 8005de0 8005dce: f44f 4380 mov.w r3, #16384 @ 0x4000 8005dd2: e005 b.n 8005de0 8005dd4: f44f 6380 mov.w r3, #1024 @ 0x400 8005dd8: e002 b.n 8005de0 8005dda: 2340 movs r3, #64 @ 0x40 8005ddc: e000 b.n 8005de0 8005dde: 2304 movs r3, #4 8005de0: 4a55 ldr r2, [pc, #340] @ (8005f38 ) 8005de2: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8005de4: 687b ldr r3, [r7, #4] 8005de6: 6adb ldr r3, [r3, #44] @ 0x2c 8005de8: 2b00 cmp r3, #0 8005dea: f000 8094 beq.w 8005f16 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8005dee: 687b ldr r3, [r7, #4] 8005df0: 6adb ldr r3, [r3, #44] @ 0x2c 8005df2: 6878 ldr r0, [r7, #4] 8005df4: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 8005df6: e08e b.n 8005f16 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8005df8: 687b ldr r3, [r7, #4] 8005dfa: 6c1b ldr r3, [r3, #64] @ 0x40 8005dfc: 2202 movs r2, #2 8005dfe: 409a lsls r2, r3 8005e00: 68fb ldr r3, [r7, #12] 8005e02: 4013 ands r3, r2 8005e04: 2b00 cmp r3, #0 8005e06: d056 beq.n 8005eb6 8005e08: 68bb ldr r3, [r7, #8] 8005e0a: f003 0302 and.w r3, r3, #2 8005e0e: 2b00 cmp r3, #0 8005e10: d051 beq.n 8005eb6 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8005e12: 687b ldr r3, [r7, #4] 8005e14: 681b ldr r3, [r3, #0] 8005e16: 681b ldr r3, [r3, #0] 8005e18: f003 0320 and.w r3, r3, #32 8005e1c: 2b00 cmp r3, #0 8005e1e: d10b bne.n 8005e38 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8005e20: 687b ldr r3, [r7, #4] 8005e22: 681b ldr r3, [r3, #0] 8005e24: 681a ldr r2, [r3, #0] 8005e26: 687b ldr r3, [r7, #4] 8005e28: 681b ldr r3, [r3, #0] 8005e2a: f022 020a bic.w r2, r2, #10 8005e2e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8005e30: 687b ldr r3, [r7, #4] 8005e32: 2201 movs r2, #1 8005e34: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8005e38: 687b ldr r3, [r7, #4] 8005e3a: 681b ldr r3, [r3, #0] 8005e3c: 4a38 ldr r2, [pc, #224] @ (8005f20 ) 8005e3e: 4293 cmp r3, r2 8005e40: d029 beq.n 8005e96 8005e42: 687b ldr r3, [r7, #4] 8005e44: 681b ldr r3, [r3, #0] 8005e46: 4a37 ldr r2, [pc, #220] @ (8005f24 ) 8005e48: 4293 cmp r3, r2 8005e4a: d022 beq.n 8005e92 8005e4c: 687b ldr r3, [r7, #4] 8005e4e: 681b ldr r3, [r3, #0] 8005e50: 4a35 ldr r2, [pc, #212] @ (8005f28 ) 8005e52: 4293 cmp r3, r2 8005e54: d01a beq.n 8005e8c 8005e56: 687b ldr r3, [r7, #4] 8005e58: 681b ldr r3, [r3, #0] 8005e5a: 4a34 ldr r2, [pc, #208] @ (8005f2c ) 8005e5c: 4293 cmp r3, r2 8005e5e: d012 beq.n 8005e86 8005e60: 687b ldr r3, [r7, #4] 8005e62: 681b ldr r3, [r3, #0] 8005e64: 4a32 ldr r2, [pc, #200] @ (8005f30 ) 8005e66: 4293 cmp r3, r2 8005e68: d00a beq.n 8005e80 8005e6a: 687b ldr r3, [r7, #4] 8005e6c: 681b ldr r3, [r3, #0] 8005e6e: 4a31 ldr r2, [pc, #196] @ (8005f34 ) 8005e70: 4293 cmp r3, r2 8005e72: d102 bne.n 8005e7a 8005e74: f44f 1300 mov.w r3, #2097152 @ 0x200000 8005e78: e00e b.n 8005e98 8005e7a: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8005e7e: e00b b.n 8005e98 8005e80: f44f 3300 mov.w r3, #131072 @ 0x20000 8005e84: e008 b.n 8005e98 8005e86: f44f 5300 mov.w r3, #8192 @ 0x2000 8005e8a: e005 b.n 8005e98 8005e8c: f44f 7300 mov.w r3, #512 @ 0x200 8005e90: e002 b.n 8005e98 8005e92: 2320 movs r3, #32 8005e94: e000 b.n 8005e98 8005e96: 2302 movs r3, #2 8005e98: 4a27 ldr r2, [pc, #156] @ (8005f38 ) 8005e9a: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8005e9c: 687b ldr r3, [r7, #4] 8005e9e: 2200 movs r2, #0 8005ea0: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8005ea4: 687b ldr r3, [r7, #4] 8005ea6: 6a9b ldr r3, [r3, #40] @ 0x28 8005ea8: 2b00 cmp r3, #0 8005eaa: d034 beq.n 8005f16 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8005eac: 687b ldr r3, [r7, #4] 8005eae: 6a9b ldr r3, [r3, #40] @ 0x28 8005eb0: 6878 ldr r0, [r7, #4] 8005eb2: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8005eb4: e02f b.n 8005f16 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8005eb6: 687b ldr r3, [r7, #4] 8005eb8: 6c1b ldr r3, [r3, #64] @ 0x40 8005eba: 2208 movs r2, #8 8005ebc: 409a lsls r2, r3 8005ebe: 68fb ldr r3, [r7, #12] 8005ec0: 4013 ands r3, r2 8005ec2: 2b00 cmp r3, #0 8005ec4: d028 beq.n 8005f18 8005ec6: 68bb ldr r3, [r7, #8] 8005ec8: f003 0308 and.w r3, r3, #8 8005ecc: 2b00 cmp r3, #0 8005ece: d023 beq.n 8005f18 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8005ed0: 687b ldr r3, [r7, #4] 8005ed2: 681b ldr r3, [r3, #0] 8005ed4: 681a ldr r2, [r3, #0] 8005ed6: 687b ldr r3, [r7, #4] 8005ed8: 681b ldr r3, [r3, #0] 8005eda: f022 020e bic.w r2, r2, #14 8005ede: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8005ee0: 687b ldr r3, [r7, #4] 8005ee2: 6c1a ldr r2, [r3, #64] @ 0x40 8005ee4: 687b ldr r3, [r7, #4] 8005ee6: 6bdb ldr r3, [r3, #60] @ 0x3c 8005ee8: 2101 movs r1, #1 8005eea: fa01 f202 lsl.w r2, r1, r2 8005eee: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8005ef0: 687b ldr r3, [r7, #4] 8005ef2: 2201 movs r2, #1 8005ef4: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8005ef6: 687b ldr r3, [r7, #4] 8005ef8: 2201 movs r2, #1 8005efa: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8005efe: 687b ldr r3, [r7, #4] 8005f00: 2200 movs r2, #0 8005f02: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8005f06: 687b ldr r3, [r7, #4] 8005f08: 6b1b ldr r3, [r3, #48] @ 0x30 8005f0a: 2b00 cmp r3, #0 8005f0c: d004 beq.n 8005f18 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8005f0e: 687b ldr r3, [r7, #4] 8005f10: 6b1b ldr r3, [r3, #48] @ 0x30 8005f12: 6878 ldr r0, [r7, #4] 8005f14: 4798 blx r3 } } return; 8005f16: bf00 nop 8005f18: bf00 nop } 8005f1a: 3710 adds r7, #16 8005f1c: 46bd mov sp, r7 8005f1e: bd80 pop {r7, pc} 8005f20: 40020008 .word 0x40020008 8005f24: 4002001c .word 0x4002001c 8005f28: 40020030 .word 0x40020030 8005f2c: 40020044 .word 0x40020044 8005f30: 40020058 .word 0x40020058 8005f34: 4002006c .word 0x4002006c 8005f38: 40020000 .word 0x40020000 08005f3c : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8005f3c: b480 push {r7} 8005f3e: b085 sub sp, #20 8005f40: af00 add r7, sp, #0 8005f42: 60f8 str r0, [r7, #12] 8005f44: 60b9 str r1, [r7, #8] 8005f46: 607a str r2, [r7, #4] 8005f48: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8005f4a: 68fb ldr r3, [r7, #12] 8005f4c: 6c1a ldr r2, [r3, #64] @ 0x40 8005f4e: 68fb ldr r3, [r7, #12] 8005f50: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f52: 2101 movs r1, #1 8005f54: fa01 f202 lsl.w r2, r1, r2 8005f58: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8005f5a: 68fb ldr r3, [r7, #12] 8005f5c: 681b ldr r3, [r3, #0] 8005f5e: 683a ldr r2, [r7, #0] 8005f60: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8005f62: 68fb ldr r3, [r7, #12] 8005f64: 685b ldr r3, [r3, #4] 8005f66: 2b10 cmp r3, #16 8005f68: d108 bne.n 8005f7c { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8005f6a: 68fb ldr r3, [r7, #12] 8005f6c: 681b ldr r3, [r3, #0] 8005f6e: 687a ldr r2, [r7, #4] 8005f70: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8005f72: 68fb ldr r3, [r7, #12] 8005f74: 681b ldr r3, [r3, #0] 8005f76: 68ba ldr r2, [r7, #8] 8005f78: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8005f7a: e007 b.n 8005f8c hdma->Instance->CPAR = SrcAddress; 8005f7c: 68fb ldr r3, [r7, #12] 8005f7e: 681b ldr r3, [r3, #0] 8005f80: 68ba ldr r2, [r7, #8] 8005f82: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8005f84: 68fb ldr r3, [r7, #12] 8005f86: 681b ldr r3, [r3, #0] 8005f88: 687a ldr r2, [r7, #4] 8005f8a: 60da str r2, [r3, #12] } 8005f8c: bf00 nop 8005f8e: 3714 adds r7, #20 8005f90: 46bd mov sp, r7 8005f92: bc80 pop {r7} 8005f94: 4770 bx lr ... 08005f98 : * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { 8005f98: b5f0 push {r4, r5, r6, r7, lr} 8005f9a: b087 sub sp, #28 8005f9c: af00 add r7, sp, #0 8005f9e: 60f8 str r0, [r7, #12] 8005fa0: 60b9 str r1, [r7, #8] 8005fa2: e9c7 2300 strd r2, r3, [r7] HAL_StatusTypeDef status = HAL_ERROR; 8005fa6: 2301 movs r3, #1 8005fa8: 75fb strb r3, [r7, #23] uint8_t index = 0; 8005faa: 2300 movs r3, #0 8005fac: 75bb strb r3, [r7, #22] uint8_t nbiterations = 0; 8005fae: 2300 movs r3, #0 8005fb0: 757b strb r3, [r7, #21] /* Process Locked */ __HAL_LOCK(&pFlash); 8005fb2: 4b2f ldr r3, [pc, #188] @ (8006070 ) 8005fb4: 7e1b ldrb r3, [r3, #24] 8005fb6: 2b01 cmp r3, #1 8005fb8: d101 bne.n 8005fbe 8005fba: 2302 movs r3, #2 8005fbc: e054 b.n 8006068 8005fbe: 4b2c ldr r3, [pc, #176] @ (8006070 ) 8005fc0: 2201 movs r2, #1 8005fc2: 761a strb r2, [r3, #24] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8005fc4: f24c 3050 movw r0, #50000 @ 0xc350 8005fc8: f000 f8a8 bl 800611c 8005fcc: 4603 mov r3, r0 8005fce: 75fb strb r3, [r7, #23] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ if(status == HAL_OK) 8005fd0: 7dfb ldrb r3, [r7, #23] 8005fd2: 2b00 cmp r3, #0 8005fd4: d144 bne.n 8006060 { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) 8005fd6: 68fb ldr r3, [r7, #12] 8005fd8: 2b01 cmp r3, #1 8005fda: d102 bne.n 8005fe2 { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; 8005fdc: 2301 movs r3, #1 8005fde: 757b strb r3, [r7, #21] 8005fe0: e007 b.n 8005ff2 } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) 8005fe2: 68fb ldr r3, [r7, #12] 8005fe4: 2b02 cmp r3, #2 8005fe6: d102 bne.n 8005fee { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; 8005fe8: 2302 movs r3, #2 8005fea: 757b strb r3, [r7, #21] 8005fec: e001 b.n 8005ff2 } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; 8005fee: 2304 movs r3, #4 8005ff0: 757b strb r3, [r7, #21] } for (index = 0U; index < nbiterations; index++) 8005ff2: 2300 movs r3, #0 8005ff4: 75bb strb r3, [r7, #22] 8005ff6: e02d b.n 8006054 { FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); 8005ff8: 7dbb ldrb r3, [r7, #22] 8005ffa: 005a lsls r2, r3, #1 8005ffc: 68bb ldr r3, [r7, #8] 8005ffe: eb02 0c03 add.w ip, r2, r3 8006002: 7dbb ldrb r3, [r7, #22] 8006004: 0119 lsls r1, r3, #4 8006006: e9d7 2300 ldrd r2, r3, [r7] 800600a: f1c1 0620 rsb r6, r1, #32 800600e: f1a1 0020 sub.w r0, r1, #32 8006012: fa22 f401 lsr.w r4, r2, r1 8006016: fa03 f606 lsl.w r6, r3, r6 800601a: 4334 orrs r4, r6 800601c: fa23 f000 lsr.w r0, r3, r0 8006020: 4304 orrs r4, r0 8006022: fa23 f501 lsr.w r5, r3, r1 8006026: b2a3 uxth r3, r4 8006028: 4619 mov r1, r3 800602a: 4660 mov r0, ip 800602c: f000 f85a bl 80060e4 #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8006030: f24c 3050 movw r0, #50000 @ 0xc350 8006034: f000 f872 bl 800611c 8006038: 4603 mov r3, r0 800603a: 75fb strb r3, [r7, #23] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); 800603c: 4b0d ldr r3, [pc, #52] @ (8006074 ) 800603e: 691b ldr r3, [r3, #16] 8006040: 4a0c ldr r2, [pc, #48] @ (8006074 ) 8006042: f023 0301 bic.w r3, r3, #1 8006046: 6113 str r3, [r2, #16] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* In case of error, stop programation procedure */ if (status != HAL_OK) 8006048: 7dfb ldrb r3, [r7, #23] 800604a: 2b00 cmp r3, #0 800604c: d107 bne.n 800605e for (index = 0U; index < nbiterations; index++) 800604e: 7dbb ldrb r3, [r7, #22] 8006050: 3301 adds r3, #1 8006052: 75bb strb r3, [r7, #22] 8006054: 7dba ldrb r2, [r7, #22] 8006056: 7d7b ldrb r3, [r7, #21] 8006058: 429a cmp r2, r3 800605a: d3cd bcc.n 8005ff8 800605c: e000 b.n 8006060 { break; 800605e: bf00 nop } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8006060: 4b03 ldr r3, [pc, #12] @ (8006070 ) 8006062: 2200 movs r2, #0 8006064: 761a strb r2, [r3, #24] return status; 8006066: 7dfb ldrb r3, [r7, #23] } 8006068: 4618 mov r0, r3 800606a: 371c adds r7, #28 800606c: 46bd mov sp, r7 800606e: bdf0 pop {r4, r5, r6, r7, pc} 8006070: 20000478 .word 0x20000478 8006074: 40022000 .word 0x40022000 08006078 : /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 8006078: b480 push {r7} 800607a: b083 sub sp, #12 800607c: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 800607e: 2300 movs r3, #0 8006080: 71fb strb r3, [r7, #7] if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8006082: 4b0d ldr r3, [pc, #52] @ (80060b8 ) 8006084: 691b ldr r3, [r3, #16] 8006086: f003 0380 and.w r3, r3, #128 @ 0x80 800608a: 2b00 cmp r3, #0 800608c: d00d beq.n 80060aa { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); 800608e: 4b0a ldr r3, [pc, #40] @ (80060b8 ) 8006090: 4a0a ldr r2, [pc, #40] @ (80060bc ) 8006092: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 8006094: 4b08 ldr r3, [pc, #32] @ (80060b8 ) 8006096: 4a0a ldr r2, [pc, #40] @ (80060c0 ) 8006098: 605a str r2, [r3, #4] /* Verify Flash is unlocked */ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 800609a: 4b07 ldr r3, [pc, #28] @ (80060b8 ) 800609c: 691b ldr r3, [r3, #16] 800609e: f003 0380 and.w r3, r3, #128 @ 0x80 80060a2: 2b00 cmp r3, #0 80060a4: d001 beq.n 80060aa { status = HAL_ERROR; 80060a6: 2301 movs r3, #1 80060a8: 71fb strb r3, [r7, #7] status = HAL_ERROR; } } #endif /* FLASH_BANK2_END */ return status; 80060aa: 79fb ldrb r3, [r7, #7] } 80060ac: 4618 mov r0, r3 80060ae: 370c adds r7, #12 80060b0: 46bd mov sp, r7 80060b2: bc80 pop {r7} 80060b4: 4770 bx lr 80060b6: bf00 nop 80060b8: 40022000 .word 0x40022000 80060bc: 45670123 .word 0x45670123 80060c0: cdef89ab .word 0xcdef89ab 080060c4 : /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 80060c4: b480 push {r7} 80060c6: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); 80060c8: 4b05 ldr r3, [pc, #20] @ (80060e0 ) 80060ca: 691b ldr r3, [r3, #16] 80060cc: 4a04 ldr r2, [pc, #16] @ (80060e0 ) 80060ce: f043 0380 orr.w r3, r3, #128 @ 0x80 80060d2: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ return HAL_OK; 80060d4: 2300 movs r3, #0 } 80060d6: 4618 mov r0, r3 80060d8: 46bd mov sp, r7 80060da: bc80 pop {r7} 80060dc: 4770 bx lr 80060de: bf00 nop 80060e0: 40022000 .word 0x40022000 080060e4 : * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { 80060e4: b480 push {r7} 80060e6: b083 sub sp, #12 80060e8: af00 add r7, sp, #0 80060ea: 6078 str r0, [r7, #4] 80060ec: 460b mov r3, r1 80060ee: 807b strh r3, [r7, #2] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80060f0: 4b08 ldr r3, [pc, #32] @ (8006114 ) 80060f2: 2200 movs r2, #0 80060f4: 61da str r2, [r3, #28] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); 80060f6: 4b08 ldr r3, [pc, #32] @ (8006118 ) 80060f8: 691b ldr r3, [r3, #16] 80060fa: 4a07 ldr r2, [pc, #28] @ (8006118 ) 80060fc: f043 0301 orr.w r3, r3, #1 8006100: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* Write data in the address */ *(__IO uint16_t*)Address = Data; 8006102: 687b ldr r3, [r7, #4] 8006104: 887a ldrh r2, [r7, #2] 8006106: 801a strh r2, [r3, #0] } 8006108: bf00 nop 800610a: 370c adds r7, #12 800610c: 46bd mov sp, r7 800610e: bc80 pop {r7} 8006110: 4770 bx lr 8006112: bf00 nop 8006114: 20000478 .word 0x20000478 8006118: 40022000 .word 0x40022000 0800611c : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { 800611c: b580 push {r7, lr} 800611e: b084 sub sp, #16 8006120: af00 add r7, sp, #0 8006122: 6078 str r0, [r7, #4] /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); 8006124: f7ff f860 bl 80051e8 8006128: 60f8 str r0, [r7, #12] while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 800612a: e010 b.n 800614e { if (Timeout != HAL_MAX_DELAY) 800612c: 687b ldr r3, [r7, #4] 800612e: f1b3 3fff cmp.w r3, #4294967295 8006132: d00c beq.n 800614e { if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 8006134: 687b ldr r3, [r7, #4] 8006136: 2b00 cmp r3, #0 8006138: d007 beq.n 800614a 800613a: f7ff f855 bl 80051e8 800613e: 4602 mov r2, r0 8006140: 68fb ldr r3, [r7, #12] 8006142: 1ad3 subs r3, r2, r3 8006144: 687a ldr r2, [r7, #4] 8006146: 429a cmp r2, r3 8006148: d201 bcs.n 800614e { return HAL_TIMEOUT; 800614a: 2303 movs r3, #3 800614c: e025 b.n 800619a while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 800614e: 4b15 ldr r3, [pc, #84] @ (80061a4 ) 8006150: 68db ldr r3, [r3, #12] 8006152: f003 0301 and.w r3, r3, #1 8006156: 2b00 cmp r3, #0 8006158: d1e8 bne.n 800612c } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) 800615a: 4b12 ldr r3, [pc, #72] @ (80061a4 ) 800615c: 68db ldr r3, [r3, #12] 800615e: f003 0320 and.w r3, r3, #32 8006162: 2b00 cmp r3, #0 8006164: d002 beq.n 800616c { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); 8006166: 4b0f ldr r3, [pc, #60] @ (80061a4 ) 8006168: 2220 movs r2, #32 800616a: 60da str r2, [r3, #12] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 800616c: 4b0d ldr r3, [pc, #52] @ (80061a4 ) 800616e: 68db ldr r3, [r3, #12] 8006170: f003 0310 and.w r3, r3, #16 8006174: 2b00 cmp r3, #0 8006176: d10b bne.n 8006190 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 8006178: 4b0a ldr r3, [pc, #40] @ (80061a4 ) 800617a: 69db ldr r3, [r3, #28] 800617c: f003 0301 and.w r3, r3, #1 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8006180: 2b00 cmp r3, #0 8006182: d105 bne.n 8006190 __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8006184: 4b07 ldr r3, [pc, #28] @ (80061a4 ) 8006186: 68db ldr r3, [r3, #12] 8006188: f003 0304 and.w r3, r3, #4 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 800618c: 2b00 cmp r3, #0 800618e: d003 beq.n 8006198 { /*Save the error code*/ FLASH_SetErrorCode(); 8006190: f000 f80a bl 80061a8 return HAL_ERROR; 8006194: 2301 movs r3, #1 8006196: e000 b.n 800619a } /* There is no error flag set */ return HAL_OK; 8006198: 2300 movs r3, #0 } 800619a: 4618 mov r0, r3 800619c: 3710 adds r7, #16 800619e: 46bd mov sp, r7 80061a0: bd80 pop {r7, pc} 80061a2: bf00 nop 80061a4: 40022000 .word 0x40022000 080061a8 : /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { 80061a8: b480 push {r7} 80061aa: b083 sub sp, #12 80061ac: af00 add r7, sp, #0 uint32_t flags = 0U; 80061ae: 2300 movs r3, #0 80061b0: 607b str r3, [r7, #4] #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) 80061b2: 4b23 ldr r3, [pc, #140] @ (8006240 ) 80061b4: 68db ldr r3, [r3, #12] 80061b6: f003 0310 and.w r3, r3, #16 80061ba: 2b00 cmp r3, #0 80061bc: d009 beq.n 80061d2 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; 80061be: 4b21 ldr r3, [pc, #132] @ (8006244 ) 80061c0: 69db ldr r3, [r3, #28] 80061c2: f043 0302 orr.w r3, r3, #2 80061c6: 4a1f ldr r2, [pc, #124] @ (8006244 ) 80061c8: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; 80061ca: 687b ldr r3, [r7, #4] 80061cc: f043 0310 orr.w r3, r3, #16 80061d0: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 80061d2: 4b1b ldr r3, [pc, #108] @ (8006240 ) 80061d4: 68db ldr r3, [r3, #12] 80061d6: f003 0304 and.w r3, r3, #4 80061da: 2b00 cmp r3, #0 80061dc: d009 beq.n 80061f2 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; 80061de: 4b19 ldr r3, [pc, #100] @ (8006244 ) 80061e0: 69db ldr r3, [r3, #28] 80061e2: f043 0301 orr.w r3, r3, #1 80061e6: 4a17 ldr r2, [pc, #92] @ (8006244 ) 80061e8: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; 80061ea: 687b ldr r3, [r7, #4] 80061ec: f043 0304 orr.w r3, r3, #4 80061f0: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) 80061f2: 4b13 ldr r3, [pc, #76] @ (8006240 ) 80061f4: 69db ldr r3, [r3, #28] 80061f6: f003 0301 and.w r3, r3, #1 80061fa: 2b00 cmp r3, #0 80061fc: d00b beq.n 8006216 { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; 80061fe: 4b11 ldr r3, [pc, #68] @ (8006244 ) 8006200: 69db ldr r3, [r3, #28] 8006202: f043 0304 orr.w r3, r3, #4 8006206: 4a0f ldr r2, [pc, #60] @ (8006244 ) 8006208: 61d3 str r3, [r2, #28] __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 800620a: 4b0d ldr r3, [pc, #52] @ (8006240 ) 800620c: 69db ldr r3, [r3, #28] 800620e: 4a0c ldr r2, [pc, #48] @ (8006240 ) 8006210: f023 0301 bic.w r3, r3, #1 8006214: 61d3 str r3, [r2, #28] } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); 8006216: 687b ldr r3, [r7, #4] 8006218: f240 1201 movw r2, #257 @ 0x101 800621c: 4293 cmp r3, r2 800621e: d106 bne.n 800622e 8006220: 4b07 ldr r3, [pc, #28] @ (8006240 ) 8006222: 69db ldr r3, [r3, #28] 8006224: 4a06 ldr r2, [pc, #24] @ (8006240 ) 8006226: f023 0301 bic.w r3, r3, #1 800622a: 61d3 str r3, [r2, #28] } 800622c: e002 b.n 8006234 __HAL_FLASH_CLEAR_FLAG(flags); 800622e: 4a04 ldr r2, [pc, #16] @ (8006240 ) 8006230: 687b ldr r3, [r7, #4] 8006232: 60d3 str r3, [r2, #12] } 8006234: bf00 nop 8006236: 370c adds r7, #12 8006238: 46bd mov sp, r7 800623a: bc80 pop {r7} 800623c: 4770 bx lr 800623e: bf00 nop 8006240: 40022000 .word 0x40022000 8006244: 20000478 .word 0x20000478 08006248 : * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { 8006248: b580 push {r7, lr} 800624a: b084 sub sp, #16 800624c: af00 add r7, sp, #0 800624e: 6078 str r0, [r7, #4] 8006250: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_ERROR; 8006252: 2301 movs r3, #1 8006254: 73fb strb r3, [r7, #15] uint32_t address = 0U; 8006256: 2300 movs r3, #0 8006258: 60bb str r3, [r7, #8] /* Process Locked */ __HAL_LOCK(&pFlash); 800625a: 4b2f ldr r3, [pc, #188] @ (8006318 ) 800625c: 7e1b ldrb r3, [r3, #24] 800625e: 2b01 cmp r3, #1 8006260: d101 bne.n 8006266 8006262: 2302 movs r3, #2 8006264: e053 b.n 800630e 8006266: 4b2c ldr r3, [pc, #176] @ (8006318 ) 8006268: 2201 movs r2, #1 800626a: 761a strb r2, [r3, #24] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 800626c: 687b ldr r3, [r7, #4] 800626e: 681b ldr r3, [r3, #0] 8006270: 2b02 cmp r3, #2 8006272: d116 bne.n 80062a2 else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8006274: f24c 3050 movw r0, #50000 @ 0xc350 8006278: f7ff ff50 bl 800611c 800627c: 4603 mov r3, r0 800627e: 2b00 cmp r3, #0 8006280: d141 bne.n 8006306 { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); 8006282: 2001 movs r0, #1 8006284: f000 f84c bl 8006320 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 8006288: f24c 3050 movw r0, #50000 @ 0xc350 800628c: f7ff ff46 bl 800611c 8006290: 4603 mov r3, r0 8006292: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); 8006294: 4b21 ldr r3, [pc, #132] @ (800631c ) 8006296: 691b ldr r3, [r3, #16] 8006298: 4a20 ldr r2, [pc, #128] @ (800631c ) 800629a: f023 0304 bic.w r3, r3, #4 800629e: 6113 str r3, [r2, #16] 80062a0: e031 b.n 8006306 else #endif /* FLASH_BANK2_END */ { /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 80062a2: f24c 3050 movw r0, #50000 @ 0xc350 80062a6: f7ff ff39 bl 800611c 80062aa: 4603 mov r3, r0 80062ac: 2b00 cmp r3, #0 80062ae: d12a bne.n 8006306 { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; 80062b0: 683b ldr r3, [r7, #0] 80062b2: f04f 32ff mov.w r2, #4294967295 80062b6: 601a str r2, [r3, #0] /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; 80062b8: 687b ldr r3, [r7, #4] 80062ba: 689b ldr r3, [r3, #8] 80062bc: 60bb str r3, [r7, #8] 80062be: e019 b.n 80062f4 address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); 80062c0: 68b8 ldr r0, [r7, #8] 80062c2: f000 f849 bl 8006358 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 80062c6: f24c 3050 movw r0, #50000 @ 0xc350 80062ca: f7ff ff27 bl 800611c 80062ce: 4603 mov r3, r0 80062d0: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 80062d2: 4b12 ldr r3, [pc, #72] @ (800631c ) 80062d4: 691b ldr r3, [r3, #16] 80062d6: 4a11 ldr r2, [pc, #68] @ (800631c ) 80062d8: f023 0302 bic.w r3, r3, #2 80062dc: 6113 str r3, [r2, #16] if (status != HAL_OK) 80062de: 7bfb ldrb r3, [r7, #15] 80062e0: 2b00 cmp r3, #0 80062e2: d003 beq.n 80062ec { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; 80062e4: 683b ldr r3, [r7, #0] 80062e6: 68ba ldr r2, [r7, #8] 80062e8: 601a str r2, [r3, #0] break; 80062ea: e00c b.n 8006306 address += FLASH_PAGE_SIZE) 80062ec: 68bb ldr r3, [r7, #8] 80062ee: f503 6380 add.w r3, r3, #1024 @ 0x400 80062f2: 60bb str r3, [r7, #8] address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); 80062f4: 687b ldr r3, [r7, #4] 80062f6: 68db ldr r3, [r3, #12] 80062f8: 029a lsls r2, r3, #10 80062fa: 687b ldr r3, [r7, #4] 80062fc: 689b ldr r3, [r3, #8] 80062fe: 4413 add r3, r2 8006300: 68ba ldr r2, [r7, #8] 8006302: 429a cmp r2, r3 8006304: d3dc bcc.n 80062c0 } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8006306: 4b04 ldr r3, [pc, #16] @ (8006318 ) 8006308: 2200 movs r2, #0 800630a: 761a strb r2, [r3, #24] return status; 800630c: 7bfb ldrb r3, [r7, #15] } 800630e: 4618 mov r0, r3 8006310: 3710 adds r7, #16 8006312: 46bd mov sp, r7 8006314: bd80 pop {r7, pc} 8006316: bf00 nop 8006318: 20000478 .word 0x20000478 800631c: 40022000 .word 0x40022000 08006320 : @endif * * @retval None */ static void FLASH_MassErase(uint32_t Banks) { 8006320: b480 push {r7} 8006322: b083 sub sp, #12 8006324: af00 add r7, sp, #0 8006326: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8006328: 4b09 ldr r3, [pc, #36] @ (8006350 ) 800632a: 2200 movs r2, #0 800632c: 61da str r2, [r3, #28] #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); 800632e: 4b09 ldr r3, [pc, #36] @ (8006354 ) 8006330: 691b ldr r3, [r3, #16] 8006332: 4a08 ldr r2, [pc, #32] @ (8006354 ) 8006334: f043 0304 orr.w r3, r3, #4 8006338: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR, FLASH_CR_STRT); 800633a: 4b06 ldr r3, [pc, #24] @ (8006354 ) 800633c: 691b ldr r3, [r3, #16] 800633e: 4a05 ldr r2, [pc, #20] @ (8006354 ) 8006340: f043 0340 orr.w r3, r3, #64 @ 0x40 8006344: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 8006346: bf00 nop 8006348: 370c adds r7, #12 800634a: 46bd mov sp, r7 800634c: bc80 pop {r7} 800634e: 4770 bx lr 8006350: 20000478 .word 0x20000478 8006354: 40022000 .word 0x40022000 08006358 : * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { 8006358: b480 push {r7} 800635a: b083 sub sp, #12 800635c: af00 add r7, sp, #0 800635e: 6078 str r0, [r7, #4] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8006360: 4b0b ldr r3, [pc, #44] @ (8006390 ) 8006362: 2200 movs r2, #0 8006364: 61da str r2, [r3, #28] } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); 8006366: 4b0b ldr r3, [pc, #44] @ (8006394 ) 8006368: 691b ldr r3, [r3, #16] 800636a: 4a0a ldr r2, [pc, #40] @ (8006394 ) 800636c: f043 0302 orr.w r3, r3, #2 8006370: 6113 str r3, [r2, #16] WRITE_REG(FLASH->AR, PageAddress); 8006372: 4a08 ldr r2, [pc, #32] @ (8006394 ) 8006374: 687b ldr r3, [r7, #4] 8006376: 6153 str r3, [r2, #20] SET_BIT(FLASH->CR, FLASH_CR_STRT); 8006378: 4b06 ldr r3, [pc, #24] @ (8006394 ) 800637a: 691b ldr r3, [r3, #16] 800637c: 4a05 ldr r2, [pc, #20] @ (8006394 ) 800637e: f043 0340 orr.w r3, r3, #64 @ 0x40 8006382: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 8006384: bf00 nop 8006386: 370c adds r7, #12 8006388: 46bd mov sp, r7 800638a: bc80 pop {r7} 800638c: 4770 bx lr 800638e: bf00 nop 8006390: 20000478 .word 0x20000478 8006394: 40022000 .word 0x40022000 08006398 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8006398: b480 push {r7} 800639a: b08b sub sp, #44 @ 0x2c 800639c: af00 add r7, sp, #0 800639e: 6078 str r0, [r7, #4] 80063a0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80063a2: 2300 movs r3, #0 80063a4: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80063a6: 2300 movs r3, #0 80063a8: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80063aa: e169 b.n 8006680 { /* Get the IO position */ ioposition = (0x01uL << position); 80063ac: 2201 movs r2, #1 80063ae: 6a7b ldr r3, [r7, #36] @ 0x24 80063b0: fa02 f303 lsl.w r3, r2, r3 80063b4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80063b6: 683b ldr r3, [r7, #0] 80063b8: 681b ldr r3, [r3, #0] 80063ba: 69fa ldr r2, [r7, #28] 80063bc: 4013 ands r3, r2 80063be: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80063c0: 69ba ldr r2, [r7, #24] 80063c2: 69fb ldr r3, [r7, #28] 80063c4: 429a cmp r2, r3 80063c6: f040 8158 bne.w 800667a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80063ca: 683b ldr r3, [r7, #0] 80063cc: 685b ldr r3, [r3, #4] 80063ce: 4a9a ldr r2, [pc, #616] @ (8006638 ) 80063d0: 4293 cmp r3, r2 80063d2: d05e beq.n 8006492 80063d4: 4a98 ldr r2, [pc, #608] @ (8006638 ) 80063d6: 4293 cmp r3, r2 80063d8: d875 bhi.n 80064c6 80063da: 4a98 ldr r2, [pc, #608] @ (800663c ) 80063dc: 4293 cmp r3, r2 80063de: d058 beq.n 8006492 80063e0: 4a96 ldr r2, [pc, #600] @ (800663c ) 80063e2: 4293 cmp r3, r2 80063e4: d86f bhi.n 80064c6 80063e6: 4a96 ldr r2, [pc, #600] @ (8006640 ) 80063e8: 4293 cmp r3, r2 80063ea: d052 beq.n 8006492 80063ec: 4a94 ldr r2, [pc, #592] @ (8006640 ) 80063ee: 4293 cmp r3, r2 80063f0: d869 bhi.n 80064c6 80063f2: 4a94 ldr r2, [pc, #592] @ (8006644 ) 80063f4: 4293 cmp r3, r2 80063f6: d04c beq.n 8006492 80063f8: 4a92 ldr r2, [pc, #584] @ (8006644 ) 80063fa: 4293 cmp r3, r2 80063fc: d863 bhi.n 80064c6 80063fe: 4a92 ldr r2, [pc, #584] @ (8006648 ) 8006400: 4293 cmp r3, r2 8006402: d046 beq.n 8006492 8006404: 4a90 ldr r2, [pc, #576] @ (8006648 ) 8006406: 4293 cmp r3, r2 8006408: d85d bhi.n 80064c6 800640a: 2b12 cmp r3, #18 800640c: d82a bhi.n 8006464 800640e: 2b12 cmp r3, #18 8006410: d859 bhi.n 80064c6 8006412: a201 add r2, pc, #4 @ (adr r2, 8006418 ) 8006414: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006418: 08006493 .word 0x08006493 800641c: 0800646d .word 0x0800646d 8006420: 0800647f .word 0x0800647f 8006424: 080064c1 .word 0x080064c1 8006428: 080064c7 .word 0x080064c7 800642c: 080064c7 .word 0x080064c7 8006430: 080064c7 .word 0x080064c7 8006434: 080064c7 .word 0x080064c7 8006438: 080064c7 .word 0x080064c7 800643c: 080064c7 .word 0x080064c7 8006440: 080064c7 .word 0x080064c7 8006444: 080064c7 .word 0x080064c7 8006448: 080064c7 .word 0x080064c7 800644c: 080064c7 .word 0x080064c7 8006450: 080064c7 .word 0x080064c7 8006454: 080064c7 .word 0x080064c7 8006458: 080064c7 .word 0x080064c7 800645c: 08006475 .word 0x08006475 8006460: 08006489 .word 0x08006489 8006464: 4a79 ldr r2, [pc, #484] @ (800664c ) 8006466: 4293 cmp r3, r2 8006468: d013 beq.n 8006492 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800646a: e02c b.n 80064c6 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800646c: 683b ldr r3, [r7, #0] 800646e: 68db ldr r3, [r3, #12] 8006470: 623b str r3, [r7, #32] break; 8006472: e029 b.n 80064c8 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8006474: 683b ldr r3, [r7, #0] 8006476: 68db ldr r3, [r3, #12] 8006478: 3304 adds r3, #4 800647a: 623b str r3, [r7, #32] break; 800647c: e024 b.n 80064c8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800647e: 683b ldr r3, [r7, #0] 8006480: 68db ldr r3, [r3, #12] 8006482: 3308 adds r3, #8 8006484: 623b str r3, [r7, #32] break; 8006486: e01f b.n 80064c8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8006488: 683b ldr r3, [r7, #0] 800648a: 68db ldr r3, [r3, #12] 800648c: 330c adds r3, #12 800648e: 623b str r3, [r7, #32] break; 8006490: e01a b.n 80064c8 if (GPIO_Init->Pull == GPIO_NOPULL) 8006492: 683b ldr r3, [r7, #0] 8006494: 689b ldr r3, [r3, #8] 8006496: 2b00 cmp r3, #0 8006498: d102 bne.n 80064a0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800649a: 2304 movs r3, #4 800649c: 623b str r3, [r7, #32] break; 800649e: e013 b.n 80064c8 else if (GPIO_Init->Pull == GPIO_PULLUP) 80064a0: 683b ldr r3, [r7, #0] 80064a2: 689b ldr r3, [r3, #8] 80064a4: 2b01 cmp r3, #1 80064a6: d105 bne.n 80064b4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80064a8: 2308 movs r3, #8 80064aa: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80064ac: 687b ldr r3, [r7, #4] 80064ae: 69fa ldr r2, [r7, #28] 80064b0: 611a str r2, [r3, #16] break; 80064b2: e009 b.n 80064c8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80064b4: 2308 movs r3, #8 80064b6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80064b8: 687b ldr r3, [r7, #4] 80064ba: 69fa ldr r2, [r7, #28] 80064bc: 615a str r2, [r3, #20] break; 80064be: e003 b.n 80064c8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80064c0: 2300 movs r3, #0 80064c2: 623b str r3, [r7, #32] break; 80064c4: e000 b.n 80064c8 break; 80064c6: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80064c8: 69bb ldr r3, [r7, #24] 80064ca: 2bff cmp r3, #255 @ 0xff 80064cc: d801 bhi.n 80064d2 80064ce: 687b ldr r3, [r7, #4] 80064d0: e001 b.n 80064d6 80064d2: 687b ldr r3, [r7, #4] 80064d4: 3304 adds r3, #4 80064d6: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80064d8: 69bb ldr r3, [r7, #24] 80064da: 2bff cmp r3, #255 @ 0xff 80064dc: d802 bhi.n 80064e4 80064de: 6a7b ldr r3, [r7, #36] @ 0x24 80064e0: 009b lsls r3, r3, #2 80064e2: e002 b.n 80064ea 80064e4: 6a7b ldr r3, [r7, #36] @ 0x24 80064e6: 3b08 subs r3, #8 80064e8: 009b lsls r3, r3, #2 80064ea: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80064ec: 697b ldr r3, [r7, #20] 80064ee: 681a ldr r2, [r3, #0] 80064f0: 210f movs r1, #15 80064f2: 693b ldr r3, [r7, #16] 80064f4: fa01 f303 lsl.w r3, r1, r3 80064f8: 43db mvns r3, r3 80064fa: 401a ands r2, r3 80064fc: 6a39 ldr r1, [r7, #32] 80064fe: 693b ldr r3, [r7, #16] 8006500: fa01 f303 lsl.w r3, r1, r3 8006504: 431a orrs r2, r3 8006506: 697b ldr r3, [r7, #20] 8006508: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800650a: 683b ldr r3, [r7, #0] 800650c: 685b ldr r3, [r3, #4] 800650e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8006512: 2b00 cmp r3, #0 8006514: f000 80b1 beq.w 800667a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8006518: 4b4d ldr r3, [pc, #308] @ (8006650 ) 800651a: 699b ldr r3, [r3, #24] 800651c: 4a4c ldr r2, [pc, #304] @ (8006650 ) 800651e: f043 0301 orr.w r3, r3, #1 8006522: 6193 str r3, [r2, #24] 8006524: 4b4a ldr r3, [pc, #296] @ (8006650 ) 8006526: 699b ldr r3, [r3, #24] 8006528: f003 0301 and.w r3, r3, #1 800652c: 60bb str r3, [r7, #8] 800652e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8006530: 4a48 ldr r2, [pc, #288] @ (8006654 ) 8006532: 6a7b ldr r3, [r7, #36] @ 0x24 8006534: 089b lsrs r3, r3, #2 8006536: 3302 adds r3, #2 8006538: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800653c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800653e: 6a7b ldr r3, [r7, #36] @ 0x24 8006540: f003 0303 and.w r3, r3, #3 8006544: 009b lsls r3, r3, #2 8006546: 220f movs r2, #15 8006548: fa02 f303 lsl.w r3, r2, r3 800654c: 43db mvns r3, r3 800654e: 68fa ldr r2, [r7, #12] 8006550: 4013 ands r3, r2 8006552: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8006554: 687b ldr r3, [r7, #4] 8006556: 4a40 ldr r2, [pc, #256] @ (8006658 ) 8006558: 4293 cmp r3, r2 800655a: d013 beq.n 8006584 800655c: 687b ldr r3, [r7, #4] 800655e: 4a3f ldr r2, [pc, #252] @ (800665c ) 8006560: 4293 cmp r3, r2 8006562: d00d beq.n 8006580 8006564: 687b ldr r3, [r7, #4] 8006566: 4a3e ldr r2, [pc, #248] @ (8006660 ) 8006568: 4293 cmp r3, r2 800656a: d007 beq.n 800657c 800656c: 687b ldr r3, [r7, #4] 800656e: 4a3d ldr r2, [pc, #244] @ (8006664 ) 8006570: 4293 cmp r3, r2 8006572: d101 bne.n 8006578 8006574: 2303 movs r3, #3 8006576: e006 b.n 8006586 8006578: 2304 movs r3, #4 800657a: e004 b.n 8006586 800657c: 2302 movs r3, #2 800657e: e002 b.n 8006586 8006580: 2301 movs r3, #1 8006582: e000 b.n 8006586 8006584: 2300 movs r3, #0 8006586: 6a7a ldr r2, [r7, #36] @ 0x24 8006588: f002 0203 and.w r2, r2, #3 800658c: 0092 lsls r2, r2, #2 800658e: 4093 lsls r3, r2 8006590: 68fa ldr r2, [r7, #12] 8006592: 4313 orrs r3, r2 8006594: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8006596: 492f ldr r1, [pc, #188] @ (8006654 ) 8006598: 6a7b ldr r3, [r7, #36] @ 0x24 800659a: 089b lsrs r3, r3, #2 800659c: 3302 adds r3, #2 800659e: 68fa ldr r2, [r7, #12] 80065a0: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 80065a4: 683b ldr r3, [r7, #0] 80065a6: 685b ldr r3, [r3, #4] 80065a8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80065ac: 2b00 cmp r3, #0 80065ae: d006 beq.n 80065be { SET_BIT(EXTI->RTSR, iocurrent); 80065b0: 4b2d ldr r3, [pc, #180] @ (8006668 ) 80065b2: 689a ldr r2, [r3, #8] 80065b4: 492c ldr r1, [pc, #176] @ (8006668 ) 80065b6: 69bb ldr r3, [r7, #24] 80065b8: 4313 orrs r3, r2 80065ba: 608b str r3, [r1, #8] 80065bc: e006 b.n 80065cc } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 80065be: 4b2a ldr r3, [pc, #168] @ (8006668 ) 80065c0: 689a ldr r2, [r3, #8] 80065c2: 69bb ldr r3, [r7, #24] 80065c4: 43db mvns r3, r3 80065c6: 4928 ldr r1, [pc, #160] @ (8006668 ) 80065c8: 4013 ands r3, r2 80065ca: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80065cc: 683b ldr r3, [r7, #0] 80065ce: 685b ldr r3, [r3, #4] 80065d0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80065d4: 2b00 cmp r3, #0 80065d6: d006 beq.n 80065e6 { SET_BIT(EXTI->FTSR, iocurrent); 80065d8: 4b23 ldr r3, [pc, #140] @ (8006668 ) 80065da: 68da ldr r2, [r3, #12] 80065dc: 4922 ldr r1, [pc, #136] @ (8006668 ) 80065de: 69bb ldr r3, [r7, #24] 80065e0: 4313 orrs r3, r2 80065e2: 60cb str r3, [r1, #12] 80065e4: e006 b.n 80065f4 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80065e6: 4b20 ldr r3, [pc, #128] @ (8006668 ) 80065e8: 68da ldr r2, [r3, #12] 80065ea: 69bb ldr r3, [r7, #24] 80065ec: 43db mvns r3, r3 80065ee: 491e ldr r1, [pc, #120] @ (8006668 ) 80065f0: 4013 ands r3, r2 80065f2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80065f4: 683b ldr r3, [r7, #0] 80065f6: 685b ldr r3, [r3, #4] 80065f8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80065fc: 2b00 cmp r3, #0 80065fe: d006 beq.n 800660e { SET_BIT(EXTI->EMR, iocurrent); 8006600: 4b19 ldr r3, [pc, #100] @ (8006668 ) 8006602: 685a ldr r2, [r3, #4] 8006604: 4918 ldr r1, [pc, #96] @ (8006668 ) 8006606: 69bb ldr r3, [r7, #24] 8006608: 4313 orrs r3, r2 800660a: 604b str r3, [r1, #4] 800660c: e006 b.n 800661c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800660e: 4b16 ldr r3, [pc, #88] @ (8006668 ) 8006610: 685a ldr r2, [r3, #4] 8006612: 69bb ldr r3, [r7, #24] 8006614: 43db mvns r3, r3 8006616: 4914 ldr r1, [pc, #80] @ (8006668 ) 8006618: 4013 ands r3, r2 800661a: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800661c: 683b ldr r3, [r7, #0] 800661e: 685b ldr r3, [r3, #4] 8006620: f403 3380 and.w r3, r3, #65536 @ 0x10000 8006624: 2b00 cmp r3, #0 8006626: d021 beq.n 800666c { SET_BIT(EXTI->IMR, iocurrent); 8006628: 4b0f ldr r3, [pc, #60] @ (8006668 ) 800662a: 681a ldr r2, [r3, #0] 800662c: 490e ldr r1, [pc, #56] @ (8006668 ) 800662e: 69bb ldr r3, [r7, #24] 8006630: 4313 orrs r3, r2 8006632: 600b str r3, [r1, #0] 8006634: e021 b.n 800667a 8006636: bf00 nop 8006638: 10320000 .word 0x10320000 800663c: 10310000 .word 0x10310000 8006640: 10220000 .word 0x10220000 8006644: 10210000 .word 0x10210000 8006648: 10120000 .word 0x10120000 800664c: 10110000 .word 0x10110000 8006650: 40021000 .word 0x40021000 8006654: 40010000 .word 0x40010000 8006658: 40010800 .word 0x40010800 800665c: 40010c00 .word 0x40010c00 8006660: 40011000 .word 0x40011000 8006664: 40011400 .word 0x40011400 8006668: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800666c: 4b0b ldr r3, [pc, #44] @ (800669c ) 800666e: 681a ldr r2, [r3, #0] 8006670: 69bb ldr r3, [r7, #24] 8006672: 43db mvns r3, r3 8006674: 4909 ldr r1, [pc, #36] @ (800669c ) 8006676: 4013 ands r3, r2 8006678: 600b str r3, [r1, #0] } } } position++; 800667a: 6a7b ldr r3, [r7, #36] @ 0x24 800667c: 3301 adds r3, #1 800667e: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8006680: 683b ldr r3, [r7, #0] 8006682: 681a ldr r2, [r3, #0] 8006684: 6a7b ldr r3, [r7, #36] @ 0x24 8006686: fa22 f303 lsr.w r3, r2, r3 800668a: 2b00 cmp r3, #0 800668c: f47f ae8e bne.w 80063ac } } 8006690: bf00 nop 8006692: bf00 nop 8006694: 372c adds r7, #44 @ 0x2c 8006696: 46bd mov sp, r7 8006698: bc80 pop {r7} 800669a: 4770 bx lr 800669c: 40010400 .word 0x40010400 080066a0 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80066a0: b480 push {r7} 80066a2: b085 sub sp, #20 80066a4: af00 add r7, sp, #0 80066a6: 6078 str r0, [r7, #4] 80066a8: 460b mov r3, r1 80066aa: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80066ac: 687b ldr r3, [r7, #4] 80066ae: 689a ldr r2, [r3, #8] 80066b0: 887b ldrh r3, [r7, #2] 80066b2: 4013 ands r3, r2 80066b4: 2b00 cmp r3, #0 80066b6: d002 beq.n 80066be { bitstatus = GPIO_PIN_SET; 80066b8: 2301 movs r3, #1 80066ba: 73fb strb r3, [r7, #15] 80066bc: e001 b.n 80066c2 } else { bitstatus = GPIO_PIN_RESET; 80066be: 2300 movs r3, #0 80066c0: 73fb strb r3, [r7, #15] } return bitstatus; 80066c2: 7bfb ldrb r3, [r7, #15] } 80066c4: 4618 mov r0, r3 80066c6: 3714 adds r7, #20 80066c8: 46bd mov sp, r7 80066ca: bc80 pop {r7} 80066cc: 4770 bx lr 080066ce : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80066ce: b480 push {r7} 80066d0: b083 sub sp, #12 80066d2: af00 add r7, sp, #0 80066d4: 6078 str r0, [r7, #4] 80066d6: 460b mov r3, r1 80066d8: 807b strh r3, [r7, #2] 80066da: 4613 mov r3, r2 80066dc: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80066de: 787b ldrb r3, [r7, #1] 80066e0: 2b00 cmp r3, #0 80066e2: d003 beq.n 80066ec { GPIOx->BSRR = GPIO_Pin; 80066e4: 887a ldrh r2, [r7, #2] 80066e6: 687b ldr r3, [r7, #4] 80066e8: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 80066ea: e003 b.n 80066f4 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 80066ec: 887b ldrh r3, [r7, #2] 80066ee: 041a lsls r2, r3, #16 80066f0: 687b ldr r3, [r7, #4] 80066f2: 611a str r2, [r3, #16] } 80066f4: bf00 nop 80066f6: 370c adds r7, #12 80066f8: 46bd mov sp, r7 80066fa: bc80 pop {r7} 80066fc: 4770 bx lr 080066fe : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 80066fe: b580 push {r7, lr} 8006700: b084 sub sp, #16 8006702: af00 add r7, sp, #0 8006704: 6078 str r0, [r7, #4] uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8006706: 687b ldr r3, [r7, #4] 8006708: 2b00 cmp r3, #0 800670a: d101 bne.n 8006710 { return HAL_ERROR; 800670c: 2301 movs r3, #1 800670e: e0e8 b.n 80068e2 } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); if (hpcd->State == HAL_PCD_STATE_RESET) 8006710: 687b ldr r3, [r7, #4] 8006712: f893 3291 ldrb.w r3, [r3, #657] @ 0x291 8006716: b2db uxtb r3, r3 8006718: 2b00 cmp r3, #0 800671a: d106 bne.n 800672a { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 800671c: 687b ldr r3, [r7, #4] 800671e: 2200 movs r2, #0 8006720: f883 2290 strb.w r2, [r3, #656] @ 0x290 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8006724: 6878 ldr r0, [r7, #4] 8006726: f007 fc17 bl 800df58 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 800672a: 687b ldr r3, [r7, #4] 800672c: 2203 movs r2, #3 800672e: f883 2291 strb.w r2, [r3, #657] @ 0x291 /* Disable DMA mode for FS instance */ hpcd->Init.dma_enable = 0U; 8006732: 687b ldr r3, [r7, #4] 8006734: 2200 movs r2, #0 8006736: 715a strb r2, [r3, #5] /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8006738: 687b ldr r3, [r7, #4] 800673a: 681b ldr r3, [r3, #0] 800673c: 4618 mov r0, r3 800673e: f003 fabc bl 8009cba /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8006742: 687b ldr r3, [r7, #4] 8006744: 6818 ldr r0, [r3, #0] 8006746: 687b ldr r3, [r7, #4] 8006748: 3304 adds r3, #4 800674a: cb0e ldmia r3, {r1, r2, r3} 800674c: f003 fa92 bl 8009c74 8006750: 4603 mov r3, r0 8006752: 2b00 cmp r3, #0 8006754: d005 beq.n 8006762 { hpcd->State = HAL_PCD_STATE_ERROR; 8006756: 687b ldr r3, [r7, #4] 8006758: 2202 movs r2, #2 800675a: f883 2291 strb.w r2, [r3, #657] @ 0x291 return HAL_ERROR; 800675e: 2301 movs r3, #1 8006760: e0bf b.n 80068e2 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8006762: 687b ldr r3, [r7, #4] 8006764: 681b ldr r3, [r3, #0] 8006766: 2100 movs r1, #0 8006768: 4618 mov r0, r3 800676a: f003 fac0 bl 8009cee 800676e: 4603 mov r3, r0 8006770: 2b00 cmp r3, #0 8006772: d005 beq.n 8006780 { hpcd->State = HAL_PCD_STATE_ERROR; 8006774: 687b ldr r3, [r7, #4] 8006776: 2202 movs r2, #2 8006778: f883 2291 strb.w r2, [r3, #657] @ 0x291 return HAL_ERROR; 800677c: 2301 movs r3, #1 800677e: e0b0 b.n 80068e2 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8006780: 2300 movs r3, #0 8006782: 73fb strb r3, [r7, #15] 8006784: e03e b.n 8006804 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8006786: 7bfa ldrb r2, [r7, #15] 8006788: 6879 ldr r1, [r7, #4] 800678a: 4613 mov r3, r2 800678c: 009b lsls r3, r3, #2 800678e: 4413 add r3, r2 8006790: 00db lsls r3, r3, #3 8006792: 440b add r3, r1 8006794: 3311 adds r3, #17 8006796: 2201 movs r2, #1 8006798: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 800679a: 7bfa ldrb r2, [r7, #15] 800679c: 6879 ldr r1, [r7, #4] 800679e: 4613 mov r3, r2 80067a0: 009b lsls r3, r3, #2 80067a2: 4413 add r3, r2 80067a4: 00db lsls r3, r3, #3 80067a6: 440b add r3, r1 80067a8: 3310 adds r3, #16 80067aa: 7bfa ldrb r2, [r7, #15] 80067ac: 701a strb r2, [r3, #0] #if defined (USB_OTG_FS) hpcd->IN_ep[i].tx_fifo_num = i; #endif /* defined (USB_OTG_FS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 80067ae: 7bfa ldrb r2, [r7, #15] 80067b0: 6879 ldr r1, [r7, #4] 80067b2: 4613 mov r3, r2 80067b4: 009b lsls r3, r3, #2 80067b6: 4413 add r3, r2 80067b8: 00db lsls r3, r3, #3 80067ba: 440b add r3, r1 80067bc: 3313 adds r3, #19 80067be: 2200 movs r2, #0 80067c0: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 80067c2: 7bfa ldrb r2, [r7, #15] 80067c4: 6879 ldr r1, [r7, #4] 80067c6: 4613 mov r3, r2 80067c8: 009b lsls r3, r3, #2 80067ca: 4413 add r3, r2 80067cc: 00db lsls r3, r3, #3 80067ce: 440b add r3, r1 80067d0: 3320 adds r3, #32 80067d2: 2200 movs r2, #0 80067d4: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 80067d6: 7bfa ldrb r2, [r7, #15] 80067d8: 6879 ldr r1, [r7, #4] 80067da: 4613 mov r3, r2 80067dc: 009b lsls r3, r3, #2 80067de: 4413 add r3, r2 80067e0: 00db lsls r3, r3, #3 80067e2: 440b add r3, r1 80067e4: 3324 adds r3, #36 @ 0x24 80067e6: 2200 movs r2, #0 80067e8: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 80067ea: 7bfb ldrb r3, [r7, #15] 80067ec: 6879 ldr r1, [r7, #4] 80067ee: 1c5a adds r2, r3, #1 80067f0: 4613 mov r3, r2 80067f2: 009b lsls r3, r3, #2 80067f4: 4413 add r3, r2 80067f6: 00db lsls r3, r3, #3 80067f8: 440b add r3, r1 80067fa: 2200 movs r2, #0 80067fc: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80067fe: 7bfb ldrb r3, [r7, #15] 8006800: 3301 adds r3, #1 8006802: 73fb strb r3, [r7, #15] 8006804: 687b ldr r3, [r7, #4] 8006806: 791b ldrb r3, [r3, #4] 8006808: 7bfa ldrb r2, [r7, #15] 800680a: 429a cmp r2, r3 800680c: d3bb bcc.n 8006786 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800680e: 2300 movs r3, #0 8006810: 73fb strb r3, [r7, #15] 8006812: e044 b.n 800689e { hpcd->OUT_ep[i].is_in = 0U; 8006814: 7bfa ldrb r2, [r7, #15] 8006816: 6879 ldr r1, [r7, #4] 8006818: 4613 mov r3, r2 800681a: 009b lsls r3, r3, #2 800681c: 4413 add r3, r2 800681e: 00db lsls r3, r3, #3 8006820: 440b add r3, r1 8006822: f203 1351 addw r3, r3, #337 @ 0x151 8006826: 2200 movs r2, #0 8006828: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 800682a: 7bfa ldrb r2, [r7, #15] 800682c: 6879 ldr r1, [r7, #4] 800682e: 4613 mov r3, r2 8006830: 009b lsls r3, r3, #2 8006832: 4413 add r3, r2 8006834: 00db lsls r3, r3, #3 8006836: 440b add r3, r1 8006838: f503 73a8 add.w r3, r3, #336 @ 0x150 800683c: 7bfa ldrb r2, [r7, #15] 800683e: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8006840: 7bfa ldrb r2, [r7, #15] 8006842: 6879 ldr r1, [r7, #4] 8006844: 4613 mov r3, r2 8006846: 009b lsls r3, r3, #2 8006848: 4413 add r3, r2 800684a: 00db lsls r3, r3, #3 800684c: 440b add r3, r1 800684e: f203 1353 addw r3, r3, #339 @ 0x153 8006852: 2200 movs r2, #0 8006854: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8006856: 7bfa ldrb r2, [r7, #15] 8006858: 6879 ldr r1, [r7, #4] 800685a: 4613 mov r3, r2 800685c: 009b lsls r3, r3, #2 800685e: 4413 add r3, r2 8006860: 00db lsls r3, r3, #3 8006862: 440b add r3, r1 8006864: f503 73b0 add.w r3, r3, #352 @ 0x160 8006868: 2200 movs r2, #0 800686a: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 800686c: 7bfa ldrb r2, [r7, #15] 800686e: 6879 ldr r1, [r7, #4] 8006870: 4613 mov r3, r2 8006872: 009b lsls r3, r3, #2 8006874: 4413 add r3, r2 8006876: 00db lsls r3, r3, #3 8006878: 440b add r3, r1 800687a: f503 73b2 add.w r3, r3, #356 @ 0x164 800687e: 2200 movs r2, #0 8006880: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8006882: 7bfa ldrb r2, [r7, #15] 8006884: 6879 ldr r1, [r7, #4] 8006886: 4613 mov r3, r2 8006888: 009b lsls r3, r3, #2 800688a: 4413 add r3, r2 800688c: 00db lsls r3, r3, #3 800688e: 440b add r3, r1 8006890: f503 73b4 add.w r3, r3, #360 @ 0x168 8006894: 2200 movs r2, #0 8006896: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8006898: 7bfb ldrb r3, [r7, #15] 800689a: 3301 adds r3, #1 800689c: 73fb strb r3, [r7, #15] 800689e: 687b ldr r3, [r7, #4] 80068a0: 791b ldrb r3, [r3, #4] 80068a2: 7bfa ldrb r2, [r7, #15] 80068a4: 429a cmp r2, r3 80068a6: d3b5 bcc.n 8006814 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 80068a8: 687b ldr r3, [r7, #4] 80068aa: 6818 ldr r0, [r3, #0] 80068ac: 687b ldr r3, [r7, #4] 80068ae: 3304 adds r3, #4 80068b0: cb0e ldmia r3, {r1, r2, r3} 80068b2: f003 fa28 bl 8009d06 80068b6: 4603 mov r3, r0 80068b8: 2b00 cmp r3, #0 80068ba: d005 beq.n 80068c8 { hpcd->State = HAL_PCD_STATE_ERROR; 80068bc: 687b ldr r3, [r7, #4] 80068be: 2202 movs r2, #2 80068c0: f883 2291 strb.w r2, [r3, #657] @ 0x291 return HAL_ERROR; 80068c4: 2301 movs r3, #1 80068c6: e00c b.n 80068e2 } hpcd->USB_Address = 0U; 80068c8: 687b ldr r3, [r7, #4] 80068ca: 2200 movs r2, #0 80068cc: 735a strb r2, [r3, #13] hpcd->State = HAL_PCD_STATE_READY; 80068ce: 687b ldr r3, [r7, #4] 80068d0: 2201 movs r2, #1 80068d2: f883 2291 strb.w r2, [r3, #657] @ 0x291 (void)USB_DevDisconnect(hpcd->Instance); 80068d6: 687b ldr r3, [r7, #4] 80068d8: 681b ldr r3, [r3, #0] 80068da: 4618 mov r0, r3 80068dc: f005 fca7 bl 800c22e return HAL_OK; 80068e0: 2300 movs r3, #0 } 80068e2: 4618 mov r0, r3 80068e4: 3710 adds r7, #16 80068e6: 46bd mov sp, r7 80068e8: bd80 pop {r7, pc} 080068ea : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 80068ea: b580 push {r7, lr} 80068ec: b082 sub sp, #8 80068ee: af00 add r7, sp, #0 80068f0: 6078 str r0, [r7, #4] __HAL_LOCK(hpcd); 80068f2: 687b ldr r3, [r7, #4] 80068f4: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 80068f8: 2b01 cmp r3, #1 80068fa: d101 bne.n 8006900 80068fc: 2302 movs r3, #2 80068fe: e016 b.n 800692e 8006900: 687b ldr r3, [r7, #4] 8006902: 2201 movs r2, #1 8006904: f883 2290 strb.w r2, [r3, #656] @ 0x290 __HAL_PCD_ENABLE(hpcd); 8006908: 687b ldr r3, [r7, #4] 800690a: 681b ldr r3, [r3, #0] 800690c: 4618 mov r0, r3 800690e: f003 f9be bl 8009c8e #if defined (USB) HAL_PCDEx_SetConnectionState(hpcd, 1U); 8006912: 2101 movs r1, #1 8006914: 6878 ldr r0, [r7, #4] 8006916: f007 fd92 bl 800e43e #endif /* defined (USB) */ (void)USB_DevConnect(hpcd->Instance); 800691a: 687b ldr r3, [r7, #4] 800691c: 681b ldr r3, [r3, #0] 800691e: 4618 mov r0, r3 8006920: f005 fc7b bl 800c21a __HAL_UNLOCK(hpcd); 8006924: 687b ldr r3, [r7, #4] 8006926: 2200 movs r2, #0 8006928: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 800692c: 2300 movs r3, #0 } 800692e: 4618 mov r0, r3 8006930: 3708 adds r7, #8 8006932: 46bd mov sp, r7 8006934: bd80 pop {r7, pc} 08006936 : * @brief This function handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8006936: b580 push {r7, lr} 8006938: b088 sub sp, #32 800693a: af00 add r7, sp, #0 800693c: 6078 str r0, [r7, #4] uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); 800693e: 687b ldr r3, [r7, #4] 8006940: 681b ldr r3, [r3, #0] 8006942: 4618 mov r0, r3 8006944: f005 fc7d bl 800c242 8006948: 61b8 str r0, [r7, #24] uint16_t store_ep[8]; uint8_t i; if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) 800694a: 69bb ldr r3, [r7, #24] 800694c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8006950: 2b00 cmp r3, #0 8006952: d003 beq.n 800695c { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ (void)PCD_EP_ISR_Handler(hpcd); 8006954: 6878 ldr r0, [r7, #4] 8006956: f000 fb1a bl 8006f8e return; 800695a: e119 b.n 8006b90 } if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) 800695c: 69bb ldr r3, [r7, #24] 800695e: f403 6380 and.w r3, r3, #1024 @ 0x400 8006962: 2b00 cmp r3, #0 8006964: d013 beq.n 800698e { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); 8006966: 687b ldr r3, [r7, #4] 8006968: 681b ldr r3, [r3, #0] 800696a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800696e: b29a uxth r2, r3 8006970: 687b ldr r3, [r7, #4] 8006972: 681b ldr r3, [r3, #0] 8006974: f422 6280 bic.w r2, r2, #1024 @ 0x400 8006978: b292 uxth r2, r2 800697a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 800697e: 6878 ldr r0, [r7, #4] 8006980: f007 fb65 bl 800e04e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ (void)HAL_PCD_SetAddress(hpcd, 0U); 8006984: 2100 movs r1, #0 8006986: 6878 ldr r0, [r7, #4] 8006988: f000 f905 bl 8006b96 return; 800698c: e100 b.n 8006b90 } if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) 800698e: 69bb ldr r3, [r7, #24] 8006990: f403 4380 and.w r3, r3, #16384 @ 0x4000 8006994: 2b00 cmp r3, #0 8006996: d00c beq.n 80069b2 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); 8006998: 687b ldr r3, [r7, #4] 800699a: 681b ldr r3, [r3, #0] 800699c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80069a0: b29a uxth r2, r3 80069a2: 687b ldr r3, [r7, #4] 80069a4: 681b ldr r3, [r3, #0] 80069a6: f422 4280 bic.w r2, r2, #16384 @ 0x4000 80069aa: b292 uxth r2, r2 80069ac: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 80069b0: e0ee b.n 8006b90 } if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) 80069b2: 69bb ldr r3, [r7, #24] 80069b4: f403 5300 and.w r3, r3, #8192 @ 0x2000 80069b8: 2b00 cmp r3, #0 80069ba: d00c beq.n 80069d6 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); 80069bc: 687b ldr r3, [r7, #4] 80069be: 681b ldr r3, [r3, #0] 80069c0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80069c4: b29a uxth r2, r3 80069c6: 687b ldr r3, [r7, #4] 80069c8: 681b ldr r3, [r3, #0] 80069ca: f422 5200 bic.w r2, r2, #8192 @ 0x2000 80069ce: b292 uxth r2, r2 80069d0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 80069d4: e0dc b.n 8006b90 } if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) 80069d6: 69bb ldr r3, [r7, #24] 80069d8: f403 5380 and.w r3, r3, #4096 @ 0x1000 80069dc: 2b00 cmp r3, #0 80069de: d027 beq.n 8006a30 { hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE); 80069e0: 687b ldr r3, [r7, #4] 80069e2: 681b ldr r3, [r3, #0] 80069e4: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 80069e8: b29a uxth r2, r3 80069ea: 687b ldr r3, [r7, #4] 80069ec: 681b ldr r3, [r3, #0] 80069ee: f022 0204 bic.w r2, r2, #4 80069f2: b292 uxth r2, r2 80069f4: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); 80069f8: 687b ldr r3, [r7, #4] 80069fa: 681b ldr r3, [r3, #0] 80069fc: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8006a00: b29a uxth r2, r3 8006a02: 687b ldr r3, [r7, #4] 8006a04: 681b ldr r3, [r3, #0] 8006a06: f022 0208 bic.w r2, r2, #8 8006a0a: b292 uxth r2, r2 8006a0c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 8006a10: 6878 ldr r0, [r7, #4] 8006a12: f007 fb55 bl 800e0c0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); 8006a16: 687b ldr r3, [r7, #4] 8006a18: 681b ldr r3, [r3, #0] 8006a1a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006a1e: b29a uxth r2, r3 8006a20: 687b ldr r3, [r7, #4] 8006a22: 681b ldr r3, [r3, #0] 8006a24: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8006a28: b292 uxth r2, r2 8006a2a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 8006a2e: e0af b.n 8006b90 } if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) 8006a30: 69bb ldr r3, [r7, #24] 8006a32: f403 6300 and.w r3, r3, #2048 @ 0x800 8006a36: 2b00 cmp r3, #0 8006a38: f000 8083 beq.w 8006b42 { /* WA: To Clear Wakeup flag if raised with suspend signal */ /* Store Endpoint registers */ for (i = 0U; i < 8U; i++) 8006a3c: 2300 movs r3, #0 8006a3e: 77fb strb r3, [r7, #31] 8006a40: e010 b.n 8006a64 { store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i); 8006a42: 687b ldr r3, [r7, #4] 8006a44: 681b ldr r3, [r3, #0] 8006a46: 461a mov r2, r3 8006a48: 7ffb ldrb r3, [r7, #31] 8006a4a: 009b lsls r3, r3, #2 8006a4c: 441a add r2, r3 8006a4e: 7ffb ldrb r3, [r7, #31] 8006a50: 8812 ldrh r2, [r2, #0] 8006a52: b292 uxth r2, r2 8006a54: 005b lsls r3, r3, #1 8006a56: 3320 adds r3, #32 8006a58: 443b add r3, r7 8006a5a: f823 2c18 strh.w r2, [r3, #-24] for (i = 0U; i < 8U; i++) 8006a5e: 7ffb ldrb r3, [r7, #31] 8006a60: 3301 adds r3, #1 8006a62: 77fb strb r3, [r7, #31] 8006a64: 7ffb ldrb r3, [r7, #31] 8006a66: 2b07 cmp r3, #7 8006a68: d9eb bls.n 8006a42 } /* FORCE RESET */ hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES); 8006a6a: 687b ldr r3, [r7, #4] 8006a6c: 681b ldr r3, [r3, #0] 8006a6e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8006a72: b29a uxth r2, r3 8006a74: 687b ldr r3, [r7, #4] 8006a76: 681b ldr r3, [r3, #0] 8006a78: f042 0201 orr.w r2, r2, #1 8006a7c: b292 uxth r2, r2 8006a7e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* CLEAR RESET */ hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES); 8006a82: 687b ldr r3, [r7, #4] 8006a84: 681b ldr r3, [r3, #0] 8006a86: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8006a8a: b29a uxth r2, r3 8006a8c: 687b ldr r3, [r7, #4] 8006a8e: 681b ldr r3, [r3, #0] 8006a90: f022 0201 bic.w r2, r2, #1 8006a94: b292 uxth r2, r2 8006a96: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* wait for reset flag in ISTR */ while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U) 8006a9a: bf00 nop 8006a9c: 687b ldr r3, [r7, #4] 8006a9e: 681b ldr r3, [r3, #0] 8006aa0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006aa4: b29b uxth r3, r3 8006aa6: f403 6380 and.w r3, r3, #1024 @ 0x400 8006aaa: 2b00 cmp r3, #0 8006aac: d0f6 beq.n 8006a9c { } /* Clear Reset Flag */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); 8006aae: 687b ldr r3, [r7, #4] 8006ab0: 681b ldr r3, [r3, #0] 8006ab2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006ab6: b29a uxth r2, r3 8006ab8: 687b ldr r3, [r7, #4] 8006aba: 681b ldr r3, [r3, #0] 8006abc: f422 6280 bic.w r2, r2, #1024 @ 0x400 8006ac0: b292 uxth r2, r2 8006ac2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /* Restore Registre */ for (i = 0U; i < 8U; i++) 8006ac6: 2300 movs r3, #0 8006ac8: 77fb strb r3, [r7, #31] 8006aca: e00f b.n 8006aec { PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]); 8006acc: 7ffb ldrb r3, [r7, #31] 8006ace: 687a ldr r2, [r7, #4] 8006ad0: 6812 ldr r2, [r2, #0] 8006ad2: 4611 mov r1, r2 8006ad4: 7ffa ldrb r2, [r7, #31] 8006ad6: 0092 lsls r2, r2, #2 8006ad8: 440a add r2, r1 8006ada: 005b lsls r3, r3, #1 8006adc: 3320 adds r3, #32 8006ade: 443b add r3, r7 8006ae0: f833 3c18 ldrh.w r3, [r3, #-24] 8006ae4: 8013 strh r3, [r2, #0] for (i = 0U; i < 8U; i++) 8006ae6: 7ffb ldrb r3, [r7, #31] 8006ae8: 3301 adds r3, #1 8006aea: 77fb strb r3, [r7, #31] 8006aec: 7ffb ldrb r3, [r7, #31] 8006aee: 2b07 cmp r3, #7 8006af0: d9ec bls.n 8006acc } /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; 8006af2: 687b ldr r3, [r7, #4] 8006af4: 681b ldr r3, [r3, #0] 8006af6: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8006afa: b29a uxth r2, r3 8006afc: 687b ldr r3, [r7, #4] 8006afe: 681b ldr r3, [r3, #0] 8006b00: f042 0208 orr.w r2, r2, #8 8006b04: b292 uxth r2, r2 8006b06: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); 8006b0a: 687b ldr r3, [r7, #4] 8006b0c: 681b ldr r3, [r3, #0] 8006b0e: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006b12: b29a uxth r2, r3 8006b14: 687b ldr r3, [r7, #4] 8006b16: 681b ldr r3, [r3, #0] 8006b18: f422 6200 bic.w r2, r2, #2048 @ 0x800 8006b1c: b292 uxth r2, r2 8006b1e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE; 8006b22: 687b ldr r3, [r7, #4] 8006b24: 681b ldr r3, [r3, #0] 8006b26: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8006b2a: b29a uxth r2, r3 8006b2c: 687b ldr r3, [r7, #4] 8006b2e: 681b ldr r3, [r3, #0] 8006b30: f042 0204 orr.w r2, r2, #4 8006b34: b292 uxth r2, r2 8006b36: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8006b3a: 6878 ldr r0, [r7, #4] 8006b3c: f007 faa6 bl 800e08c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; 8006b40: e026 b.n 8006b90 } if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) 8006b42: 69bb ldr r3, [r7, #24] 8006b44: f403 7300 and.w r3, r3, #512 @ 0x200 8006b48: 2b00 cmp r3, #0 8006b4a: d00f beq.n 8006b6c { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); 8006b4c: 687b ldr r3, [r7, #4] 8006b4e: 681b ldr r3, [r3, #0] 8006b50: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006b54: b29a uxth r2, r3 8006b56: 687b ldr r3, [r7, #4] 8006b58: 681b ldr r3, [r3, #0] 8006b5a: f422 7200 bic.w r2, r2, #512 @ 0x200 8006b5e: b292 uxth r2, r2 8006b60: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 8006b64: 6878 ldr r0, [r7, #4] 8006b66: f007 fa64 bl 800e032 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; 8006b6a: e011 b.n 8006b90 } if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) 8006b6c: 69bb ldr r3, [r7, #24] 8006b6e: f403 7380 and.w r3, r3, #256 @ 0x100 8006b72: 2b00 cmp r3, #0 8006b74: d00c beq.n 8006b90 { /* clear ESOF flag in ISTR */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); 8006b76: 687b ldr r3, [r7, #4] 8006b78: 681b ldr r3, [r3, #0] 8006b7a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006b7e: b29a uxth r2, r3 8006b80: 687b ldr r3, [r7, #4] 8006b82: 681b ldr r3, [r3, #0] 8006b84: f422 7280 bic.w r2, r2, #256 @ 0x100 8006b88: b292 uxth r2, r2 8006b8a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 8006b8e: bf00 nop } } 8006b90: 3720 adds r7, #32 8006b92: 46bd mov sp, r7 8006b94: bd80 pop {r7, pc} 08006b96 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8006b96: b580 push {r7, lr} 8006b98: b082 sub sp, #8 8006b9a: af00 add r7, sp, #0 8006b9c: 6078 str r0, [r7, #4] 8006b9e: 460b mov r3, r1 8006ba0: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8006ba2: 687b ldr r3, [r7, #4] 8006ba4: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8006ba8: 2b01 cmp r3, #1 8006baa: d101 bne.n 8006bb0 8006bac: 2302 movs r3, #2 8006bae: e012 b.n 8006bd6 8006bb0: 687b ldr r3, [r7, #4] 8006bb2: 2201 movs r2, #1 8006bb4: f883 2290 strb.w r2, [r3, #656] @ 0x290 hpcd->USB_Address = address; 8006bb8: 687b ldr r3, [r7, #4] 8006bba: 78fa ldrb r2, [r7, #3] 8006bbc: 735a strb r2, [r3, #13] (void)USB_SetDevAddress(hpcd->Instance, address); 8006bbe: 687b ldr r3, [r7, #4] 8006bc0: 681b ldr r3, [r3, #0] 8006bc2: 78fa ldrb r2, [r7, #3] 8006bc4: 4611 mov r1, r2 8006bc6: 4618 mov r0, r3 8006bc8: f005 fb14 bl 800c1f4 __HAL_UNLOCK(hpcd); 8006bcc: 687b ldr r3, [r7, #4] 8006bce: 2200 movs r2, #0 8006bd0: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8006bd4: 2300 movs r3, #0 } 8006bd6: 4618 mov r0, r3 8006bd8: 3708 adds r7, #8 8006bda: 46bd mov sp, r7 8006bdc: bd80 pop {r7, pc} 08006bde : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8006bde: b580 push {r7, lr} 8006be0: b084 sub sp, #16 8006be2: af00 add r7, sp, #0 8006be4: 6078 str r0, [r7, #4] 8006be6: 4608 mov r0, r1 8006be8: 4611 mov r1, r2 8006bea: 461a mov r2, r3 8006bec: 4603 mov r3, r0 8006bee: 70fb strb r3, [r7, #3] 8006bf0: 460b mov r3, r1 8006bf2: 803b strh r3, [r7, #0] 8006bf4: 4613 mov r3, r2 8006bf6: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8006bf8: 2300 movs r3, #0 8006bfa: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8006bfc: f997 3003 ldrsb.w r3, [r7, #3] 8006c00: 2b00 cmp r3, #0 8006c02: da0e bge.n 8006c22 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8006c04: 78fb ldrb r3, [r7, #3] 8006c06: f003 0207 and.w r2, r3, #7 8006c0a: 4613 mov r3, r2 8006c0c: 009b lsls r3, r3, #2 8006c0e: 4413 add r3, r2 8006c10: 00db lsls r3, r3, #3 8006c12: 3310 adds r3, #16 8006c14: 687a ldr r2, [r7, #4] 8006c16: 4413 add r3, r2 8006c18: 60fb str r3, [r7, #12] ep->is_in = 1U; 8006c1a: 68fb ldr r3, [r7, #12] 8006c1c: 2201 movs r2, #1 8006c1e: 705a strb r2, [r3, #1] 8006c20: e00e b.n 8006c40 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8006c22: 78fb ldrb r3, [r7, #3] 8006c24: f003 0207 and.w r2, r3, #7 8006c28: 4613 mov r3, r2 8006c2a: 009b lsls r3, r3, #2 8006c2c: 4413 add r3, r2 8006c2e: 00db lsls r3, r3, #3 8006c30: f503 73a8 add.w r3, r3, #336 @ 0x150 8006c34: 687a ldr r2, [r7, #4] 8006c36: 4413 add r3, r2 8006c38: 60fb str r3, [r7, #12] ep->is_in = 0U; 8006c3a: 68fb ldr r3, [r7, #12] 8006c3c: 2200 movs r2, #0 8006c3e: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8006c40: 78fb ldrb r3, [r7, #3] 8006c42: f003 0307 and.w r3, r3, #7 8006c46: b2da uxtb r2, r3 8006c48: 68fb ldr r3, [r7, #12] 8006c4a: 701a strb r2, [r3, #0] ep->maxpacket = ep_mps; 8006c4c: 883a ldrh r2, [r7, #0] 8006c4e: 68fb ldr r3, [r7, #12] 8006c50: 611a str r2, [r3, #16] ep->type = ep_type; 8006c52: 68fb ldr r3, [r7, #12] 8006c54: 78ba ldrb r2, [r7, #2] 8006c56: 70da strb r2, [r3, #3] ep->tx_fifo_num = ep->num; } #endif /* defined (USB_OTG_FS) */ /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8006c58: 78bb ldrb r3, [r7, #2] 8006c5a: 2b02 cmp r3, #2 8006c5c: d102 bne.n 8006c64 { ep->data_pid_start = 0U; 8006c5e: 68fb ldr r3, [r7, #12] 8006c60: 2200 movs r2, #0 8006c62: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); 8006c64: 687b ldr r3, [r7, #4] 8006c66: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8006c6a: 2b01 cmp r3, #1 8006c6c: d101 bne.n 8006c72 8006c6e: 2302 movs r3, #2 8006c70: e00e b.n 8006c90 8006c72: 687b ldr r3, [r7, #4] 8006c74: 2201 movs r2, #1 8006c76: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8006c7a: 687b ldr r3, [r7, #4] 8006c7c: 681b ldr r3, [r3, #0] 8006c7e: 68f9 ldr r1, [r7, #12] 8006c80: 4618 mov r0, r3 8006c82: f003 f85d bl 8009d40 __HAL_UNLOCK(hpcd); 8006c86: 687b ldr r3, [r7, #4] 8006c88: 2200 movs r2, #0 8006c8a: f883 2290 strb.w r2, [r3, #656] @ 0x290 return ret; 8006c8e: 7afb ldrb r3, [r7, #11] } 8006c90: 4618 mov r0, r3 8006c92: 3710 adds r7, #16 8006c94: 46bd mov sp, r7 8006c96: bd80 pop {r7, pc} 08006c98 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8006c98: b580 push {r7, lr} 8006c9a: b084 sub sp, #16 8006c9c: af00 add r7, sp, #0 8006c9e: 6078 str r0, [r7, #4] 8006ca0: 460b mov r3, r1 8006ca2: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8006ca4: f997 3003 ldrsb.w r3, [r7, #3] 8006ca8: 2b00 cmp r3, #0 8006caa: da0e bge.n 8006cca { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8006cac: 78fb ldrb r3, [r7, #3] 8006cae: f003 0207 and.w r2, r3, #7 8006cb2: 4613 mov r3, r2 8006cb4: 009b lsls r3, r3, #2 8006cb6: 4413 add r3, r2 8006cb8: 00db lsls r3, r3, #3 8006cba: 3310 adds r3, #16 8006cbc: 687a ldr r2, [r7, #4] 8006cbe: 4413 add r3, r2 8006cc0: 60fb str r3, [r7, #12] ep->is_in = 1U; 8006cc2: 68fb ldr r3, [r7, #12] 8006cc4: 2201 movs r2, #1 8006cc6: 705a strb r2, [r3, #1] 8006cc8: e00e b.n 8006ce8 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8006cca: 78fb ldrb r3, [r7, #3] 8006ccc: f003 0207 and.w r2, r3, #7 8006cd0: 4613 mov r3, r2 8006cd2: 009b lsls r3, r3, #2 8006cd4: 4413 add r3, r2 8006cd6: 00db lsls r3, r3, #3 8006cd8: f503 73a8 add.w r3, r3, #336 @ 0x150 8006cdc: 687a ldr r2, [r7, #4] 8006cde: 4413 add r3, r2 8006ce0: 60fb str r3, [r7, #12] ep->is_in = 0U; 8006ce2: 68fb ldr r3, [r7, #12] 8006ce4: 2200 movs r2, #0 8006ce6: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8006ce8: 78fb ldrb r3, [r7, #3] 8006cea: f003 0307 and.w r3, r3, #7 8006cee: b2da uxtb r2, r3 8006cf0: 68fb ldr r3, [r7, #12] 8006cf2: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8006cfa: 2b01 cmp r3, #1 8006cfc: d101 bne.n 8006d02 8006cfe: 2302 movs r3, #2 8006d00: e00e b.n 8006d20 8006d02: 687b ldr r3, [r7, #4] 8006d04: 2201 movs r2, #1 8006d06: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8006d0a: 687b ldr r3, [r7, #4] 8006d0c: 681b ldr r3, [r3, #0] 8006d0e: 68f9 ldr r1, [r7, #12] 8006d10: 4618 mov r0, r3 8006d12: f003 fbd5 bl 800a4c0 __HAL_UNLOCK(hpcd); 8006d16: 687b ldr r3, [r7, #4] 8006d18: 2200 movs r2, #0 8006d1a: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8006d1e: 2300 movs r3, #0 } 8006d20: 4618 mov r0, r3 8006d22: 3710 adds r7, #16 8006d24: 46bd mov sp, r7 8006d26: bd80 pop {r7, pc} 08006d28 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8006d28: b580 push {r7, lr} 8006d2a: b086 sub sp, #24 8006d2c: af00 add r7, sp, #0 8006d2e: 60f8 str r0, [r7, #12] 8006d30: 607a str r2, [r7, #4] 8006d32: 603b str r3, [r7, #0] 8006d34: 460b mov r3, r1 8006d36: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8006d38: 7afb ldrb r3, [r7, #11] 8006d3a: f003 0207 and.w r2, r3, #7 8006d3e: 4613 mov r3, r2 8006d40: 009b lsls r3, r3, #2 8006d42: 4413 add r3, r2 8006d44: 00db lsls r3, r3, #3 8006d46: f503 73a8 add.w r3, r3, #336 @ 0x150 8006d4a: 68fa ldr r2, [r7, #12] 8006d4c: 4413 add r3, r2 8006d4e: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8006d50: 697b ldr r3, [r7, #20] 8006d52: 687a ldr r2, [r7, #4] 8006d54: 615a str r2, [r3, #20] ep->xfer_len = len; 8006d56: 697b ldr r3, [r7, #20] 8006d58: 683a ldr r2, [r7, #0] 8006d5a: 619a str r2, [r3, #24] ep->xfer_count = 0U; 8006d5c: 697b ldr r3, [r7, #20] 8006d5e: 2200 movs r2, #0 8006d60: 61da str r2, [r3, #28] ep->is_in = 0U; 8006d62: 697b ldr r3, [r7, #20] 8006d64: 2200 movs r2, #0 8006d66: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8006d68: 7afb ldrb r3, [r7, #11] 8006d6a: f003 0307 and.w r3, r3, #7 8006d6e: b2da uxtb r2, r3 8006d70: 697b ldr r3, [r7, #20] 8006d72: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); 8006d74: 68fb ldr r3, [r7, #12] 8006d76: 681b ldr r3, [r3, #0] 8006d78: 6979 ldr r1, [r7, #20] 8006d7a: 4618 mov r0, r3 8006d7c: f003 fd8c bl 800a898 return HAL_OK; 8006d80: 2300 movs r3, #0 } 8006d82: 4618 mov r0, r3 8006d84: 3718 adds r7, #24 8006d86: 46bd mov sp, r7 8006d88: bd80 pop {r7, pc} 08006d8a : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { 8006d8a: b480 push {r7} 8006d8c: b083 sub sp, #12 8006d8e: af00 add r7, sp, #0 8006d90: 6078 str r0, [r7, #4] 8006d92: 460b mov r3, r1 8006d94: 70fb strb r3, [r7, #3] return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; 8006d96: 78fb ldrb r3, [r7, #3] 8006d98: f003 0207 and.w r2, r3, #7 8006d9c: 6879 ldr r1, [r7, #4] 8006d9e: 4613 mov r3, r2 8006da0: 009b lsls r3, r3, #2 8006da2: 4413 add r3, r2 8006da4: 00db lsls r3, r3, #3 8006da6: 440b add r3, r1 8006da8: f503 73b6 add.w r3, r3, #364 @ 0x16c 8006dac: 681b ldr r3, [r3, #0] } 8006dae: 4618 mov r0, r3 8006db0: 370c adds r7, #12 8006db2: 46bd mov sp, r7 8006db4: bc80 pop {r7} 8006db6: 4770 bx lr 08006db8 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8006db8: b580 push {r7, lr} 8006dba: b086 sub sp, #24 8006dbc: af00 add r7, sp, #0 8006dbe: 60f8 str r0, [r7, #12] 8006dc0: 607a str r2, [r7, #4] 8006dc2: 603b str r3, [r7, #0] 8006dc4: 460b mov r3, r1 8006dc6: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8006dc8: 7afb ldrb r3, [r7, #11] 8006dca: f003 0207 and.w r2, r3, #7 8006dce: 4613 mov r3, r2 8006dd0: 009b lsls r3, r3, #2 8006dd2: 4413 add r3, r2 8006dd4: 00db lsls r3, r3, #3 8006dd6: 3310 adds r3, #16 8006dd8: 68fa ldr r2, [r7, #12] 8006dda: 4413 add r3, r2 8006ddc: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8006dde: 697b ldr r3, [r7, #20] 8006de0: 687a ldr r2, [r7, #4] 8006de2: 615a str r2, [r3, #20] ep->xfer_len = len; 8006de4: 697b ldr r3, [r7, #20] 8006de6: 683a ldr r2, [r7, #0] 8006de8: 619a str r2, [r3, #24] #if defined (USB) ep->xfer_fill_db = 1U; 8006dea: 697b ldr r3, [r7, #20] 8006dec: 2201 movs r2, #1 8006dee: f883 2024 strb.w r2, [r3, #36] @ 0x24 ep->xfer_len_db = len; 8006df2: 697b ldr r3, [r7, #20] 8006df4: 683a ldr r2, [r7, #0] 8006df6: 621a str r2, [r3, #32] #endif /* defined (USB) */ ep->xfer_count = 0U; 8006df8: 697b ldr r3, [r7, #20] 8006dfa: 2200 movs r2, #0 8006dfc: 61da str r2, [r3, #28] ep->is_in = 1U; 8006dfe: 697b ldr r3, [r7, #20] 8006e00: 2201 movs r2, #1 8006e02: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8006e04: 7afb ldrb r3, [r7, #11] 8006e06: f003 0307 and.w r3, r3, #7 8006e0a: b2da uxtb r2, r3 8006e0c: 697b ldr r3, [r7, #20] 8006e0e: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); 8006e10: 68fb ldr r3, [r7, #12] 8006e12: 681b ldr r3, [r3, #0] 8006e14: 6979 ldr r1, [r7, #20] 8006e16: 4618 mov r0, r3 8006e18: f003 fd3e bl 800a898 return HAL_OK; 8006e1c: 2300 movs r3, #0 } 8006e1e: 4618 mov r0, r3 8006e20: 3718 adds r7, #24 8006e22: 46bd mov sp, r7 8006e24: bd80 pop {r7, pc} 08006e26 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8006e26: b580 push {r7, lr} 8006e28: b084 sub sp, #16 8006e2a: af00 add r7, sp, #0 8006e2c: 6078 str r0, [r7, #4] 8006e2e: 460b mov r3, r1 8006e30: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8006e32: 78fb ldrb r3, [r7, #3] 8006e34: f003 0307 and.w r3, r3, #7 8006e38: 687a ldr r2, [r7, #4] 8006e3a: 7912 ldrb r2, [r2, #4] 8006e3c: 4293 cmp r3, r2 8006e3e: d901 bls.n 8006e44 { return HAL_ERROR; 8006e40: 2301 movs r3, #1 8006e42: e04c b.n 8006ede } if ((0x80U & ep_addr) == 0x80U) 8006e44: f997 3003 ldrsb.w r3, [r7, #3] 8006e48: 2b00 cmp r3, #0 8006e4a: da0e bge.n 8006e6a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8006e4c: 78fb ldrb r3, [r7, #3] 8006e4e: f003 0207 and.w r2, r3, #7 8006e52: 4613 mov r3, r2 8006e54: 009b lsls r3, r3, #2 8006e56: 4413 add r3, r2 8006e58: 00db lsls r3, r3, #3 8006e5a: 3310 adds r3, #16 8006e5c: 687a ldr r2, [r7, #4] 8006e5e: 4413 add r3, r2 8006e60: 60fb str r3, [r7, #12] ep->is_in = 1U; 8006e62: 68fb ldr r3, [r7, #12] 8006e64: 2201 movs r2, #1 8006e66: 705a strb r2, [r3, #1] 8006e68: e00c b.n 8006e84 } else { ep = &hpcd->OUT_ep[ep_addr]; 8006e6a: 78fa ldrb r2, [r7, #3] 8006e6c: 4613 mov r3, r2 8006e6e: 009b lsls r3, r3, #2 8006e70: 4413 add r3, r2 8006e72: 00db lsls r3, r3, #3 8006e74: f503 73a8 add.w r3, r3, #336 @ 0x150 8006e78: 687a ldr r2, [r7, #4] 8006e7a: 4413 add r3, r2 8006e7c: 60fb str r3, [r7, #12] ep->is_in = 0U; 8006e7e: 68fb ldr r3, [r7, #12] 8006e80: 2200 movs r2, #0 8006e82: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8006e84: 68fb ldr r3, [r7, #12] 8006e86: 2201 movs r2, #1 8006e88: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8006e8a: 78fb ldrb r3, [r7, #3] 8006e8c: f003 0307 and.w r3, r3, #7 8006e90: b2da uxtb r2, r3 8006e92: 68fb ldr r3, [r7, #12] 8006e94: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8006e96: 687b ldr r3, [r7, #4] 8006e98: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8006e9c: 2b01 cmp r3, #1 8006e9e: d101 bne.n 8006ea4 8006ea0: 2302 movs r3, #2 8006ea2: e01c b.n 8006ede 8006ea4: 687b ldr r3, [r7, #4] 8006ea6: 2201 movs r2, #1 8006ea8: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_EPSetStall(hpcd->Instance, ep); 8006eac: 687b ldr r3, [r7, #4] 8006eae: 681b ldr r3, [r3, #0] 8006eb0: 68f9 ldr r1, [r7, #12] 8006eb2: 4618 mov r0, r3 8006eb4: f005 f8a1 bl 800bffa if ((ep_addr & EP_ADDR_MSK) == 0U) 8006eb8: 78fb ldrb r3, [r7, #3] 8006eba: f003 0307 and.w r3, r3, #7 8006ebe: 2b00 cmp r3, #0 8006ec0: d108 bne.n 8006ed4 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); 8006ec2: 687b ldr r3, [r7, #4] 8006ec4: 681a ldr r2, [r3, #0] 8006ec6: 687b ldr r3, [r7, #4] 8006ec8: f503 7326 add.w r3, r3, #664 @ 0x298 8006ecc: 4619 mov r1, r3 8006ece: 4610 mov r0, r2 8006ed0: f005 f9c6 bl 800c260 } __HAL_UNLOCK(hpcd); 8006ed4: 687b ldr r3, [r7, #4] 8006ed6: 2200 movs r2, #0 8006ed8: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8006edc: 2300 movs r3, #0 } 8006ede: 4618 mov r0, r3 8006ee0: 3710 adds r7, #16 8006ee2: 46bd mov sp, r7 8006ee4: bd80 pop {r7, pc} 08006ee6 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8006ee6: b580 push {r7, lr} 8006ee8: b084 sub sp, #16 8006eea: af00 add r7, sp, #0 8006eec: 6078 str r0, [r7, #4] 8006eee: 460b mov r3, r1 8006ef0: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8006ef2: 78fb ldrb r3, [r7, #3] 8006ef4: f003 030f and.w r3, r3, #15 8006ef8: 687a ldr r2, [r7, #4] 8006efa: 7912 ldrb r2, [r2, #4] 8006efc: 4293 cmp r3, r2 8006efe: d901 bls.n 8006f04 { return HAL_ERROR; 8006f00: 2301 movs r3, #1 8006f02: e040 b.n 8006f86 } if ((0x80U & ep_addr) == 0x80U) 8006f04: f997 3003 ldrsb.w r3, [r7, #3] 8006f08: 2b00 cmp r3, #0 8006f0a: da0e bge.n 8006f2a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8006f0c: 78fb ldrb r3, [r7, #3] 8006f0e: f003 0207 and.w r2, r3, #7 8006f12: 4613 mov r3, r2 8006f14: 009b lsls r3, r3, #2 8006f16: 4413 add r3, r2 8006f18: 00db lsls r3, r3, #3 8006f1a: 3310 adds r3, #16 8006f1c: 687a ldr r2, [r7, #4] 8006f1e: 4413 add r3, r2 8006f20: 60fb str r3, [r7, #12] ep->is_in = 1U; 8006f22: 68fb ldr r3, [r7, #12] 8006f24: 2201 movs r2, #1 8006f26: 705a strb r2, [r3, #1] 8006f28: e00e b.n 8006f48 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8006f2a: 78fb ldrb r3, [r7, #3] 8006f2c: f003 0207 and.w r2, r3, #7 8006f30: 4613 mov r3, r2 8006f32: 009b lsls r3, r3, #2 8006f34: 4413 add r3, r2 8006f36: 00db lsls r3, r3, #3 8006f38: f503 73a8 add.w r3, r3, #336 @ 0x150 8006f3c: 687a ldr r2, [r7, #4] 8006f3e: 4413 add r3, r2 8006f40: 60fb str r3, [r7, #12] ep->is_in = 0U; 8006f42: 68fb ldr r3, [r7, #12] 8006f44: 2200 movs r2, #0 8006f46: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8006f48: 68fb ldr r3, [r7, #12] 8006f4a: 2200 movs r2, #0 8006f4c: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8006f4e: 78fb ldrb r3, [r7, #3] 8006f50: f003 0307 and.w r3, r3, #7 8006f54: b2da uxtb r2, r3 8006f56: 68fb ldr r3, [r7, #12] 8006f58: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8006f5a: 687b ldr r3, [r7, #4] 8006f5c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8006f60: 2b01 cmp r3, #1 8006f62: d101 bne.n 8006f68 8006f64: 2302 movs r3, #2 8006f66: e00e b.n 8006f86 8006f68: 687b ldr r3, [r7, #4] 8006f6a: 2201 movs r2, #1 8006f6c: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_EPClearStall(hpcd->Instance, ep); 8006f70: 687b ldr r3, [r7, #4] 8006f72: 681b ldr r3, [r3, #0] 8006f74: 68f9 ldr r1, [r7, #12] 8006f76: 4618 mov r0, r3 8006f78: f005 f88f bl 800c09a __HAL_UNLOCK(hpcd); 8006f7c: 687b ldr r3, [r7, #4] 8006f7e: 2200 movs r2, #0 8006f80: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8006f84: 2300 movs r3, #0 } 8006f86: 4618 mov r0, r3 8006f88: 3710 adds r7, #16 8006f8a: 46bd mov sp, r7 8006f8c: bd80 pop {r7, pc} 08006f8e : * @brief This function handles PCD Endpoint interrupt request. * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { 8006f8e: b580 push {r7, lr} 8006f90: b096 sub sp, #88 @ 0x58 8006f92: af00 add r7, sp, #0 8006f94: 6078 str r0, [r7, #4] #if (USE_USB_DOUBLE_BUFFER != 1U) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) 8006f96: e3bb b.n 8007710 { wIstr = hpcd->Instance->ISTR; 8006f98: 687b ldr r3, [r7, #4] 8006f9a: 681b ldr r3, [r3, #0] 8006f9c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8006fa0: f8a7 304e strh.w r3, [r7, #78] @ 0x4e /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); 8006fa4: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8006fa8: b2db uxtb r3, r3 8006faa: f003 030f and.w r3, r3, #15 8006fae: f887 304d strb.w r3, [r7, #77] @ 0x4d if (epindex == 0U) 8006fb2: f897 304d ldrb.w r3, [r7, #77] @ 0x4d 8006fb6: 2b00 cmp r3, #0 8006fb8: f040 8175 bne.w 80072a6 { /* Decode and service control endpoint interrupt */ /* DIR bit = origin of the interrupt */ if ((wIstr & USB_ISTR_DIR) == 0U) 8006fbc: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8006fc0: f003 0310 and.w r3, r3, #16 8006fc4: 2b00 cmp r3, #0 8006fc6: d14e bne.n 8007066 { /* DIR = 0 */ /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); 8006fc8: 687b ldr r3, [r7, #4] 8006fca: 681b ldr r3, [r3, #0] 8006fcc: 881b ldrh r3, [r3, #0] 8006fce: b29b uxth r3, r3 8006fd0: f423 43e1 bic.w r3, r3, #28800 @ 0x7080 8006fd4: f023 0370 bic.w r3, r3, #112 @ 0x70 8006fd8: 81fb strh r3, [r7, #14] 8006fda: 687b ldr r3, [r7, #4] 8006fdc: 681a ldr r2, [r3, #0] 8006fde: 89fb ldrh r3, [r7, #14] 8006fe0: ea6f 4343 mvn.w r3, r3, lsl #17 8006fe4: ea6f 4353 mvn.w r3, r3, lsr #17 8006fe8: b29b uxth r3, r3 8006fea: 8013 strh r3, [r2, #0] ep = &hpcd->IN_ep[0]; 8006fec: 687b ldr r3, [r7, #4] 8006fee: 3310 adds r3, #16 8006ff0: 657b str r3, [r7, #84] @ 0x54 ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); 8006ff2: 687b ldr r3, [r7, #4] 8006ff4: 681b ldr r3, [r3, #0] 8006ff6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8006ffa: b29b uxth r3, r3 8006ffc: 461a mov r2, r3 8006ffe: 6d7b ldr r3, [r7, #84] @ 0x54 8007000: 781b ldrb r3, [r3, #0] 8007002: 00db lsls r3, r3, #3 8007004: 4413 add r3, r2 8007006: 3302 adds r3, #2 8007008: 005b lsls r3, r3, #1 800700a: 687a ldr r2, [r7, #4] 800700c: 6812 ldr r2, [r2, #0] 800700e: 4413 add r3, r2 8007010: f503 6380 add.w r3, r3, #1024 @ 0x400 8007014: 881b ldrh r3, [r3, #0] 8007016: f3c3 0209 ubfx r2, r3, #0, #10 800701a: 6d7b ldr r3, [r7, #84] @ 0x54 800701c: 61da str r2, [r3, #28] ep->xfer_buff += ep->xfer_count; 800701e: 6d7b ldr r3, [r7, #84] @ 0x54 8007020: 695a ldr r2, [r3, #20] 8007022: 6d7b ldr r3, [r7, #84] @ 0x54 8007024: 69db ldr r3, [r3, #28] 8007026: 441a add r2, r3 8007028: 6d7b ldr r3, [r7, #84] @ 0x54 800702a: 615a str r2, [r3, #20] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, 0U); #else HAL_PCD_DataInStageCallback(hpcd, 0U); 800702c: 2100 movs r1, #0 800702e: 6878 ldr r0, [r7, #4] 8007030: f006 ffe5 bl 800dffe #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) 8007034: 687b ldr r3, [r7, #4] 8007036: 7b5b ldrb r3, [r3, #13] 8007038: b2db uxtb r3, r3 800703a: 2b00 cmp r3, #0 800703c: f000 8368 beq.w 8007710 8007040: 6d7b ldr r3, [r7, #84] @ 0x54 8007042: 699b ldr r3, [r3, #24] 8007044: 2b00 cmp r3, #0 8007046: f040 8363 bne.w 8007710 { hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); 800704a: 687b ldr r3, [r7, #4] 800704c: 7b5b ldrb r3, [r3, #13] 800704e: b2db uxtb r3, r3 8007050: f063 037f orn r3, r3, #127 @ 0x7f 8007054: b2da uxtb r2, r3 8007056: 687b ldr r3, [r7, #4] 8007058: 681b ldr r3, [r3, #0] 800705a: f8a3 204c strh.w r2, [r3, #76] @ 0x4c hpcd->USB_Address = 0U; 800705e: 687b ldr r3, [r7, #4] 8007060: 2200 movs r2, #0 8007062: 735a strb r2, [r3, #13] 8007064: e354 b.n 8007710 { /* DIR = 1 */ /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; 8007066: 687b ldr r3, [r7, #4] 8007068: f503 73a8 add.w r3, r3, #336 @ 0x150 800706c: 657b str r3, [r7, #84] @ 0x54 wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); 800706e: 687b ldr r3, [r7, #4] 8007070: 681b ldr r3, [r3, #0] 8007072: 881b ldrh r3, [r3, #0] 8007074: f8a7 304a strh.w r3, [r7, #74] @ 0x4a if ((wEPVal & USB_EP_SETUP) != 0U) 8007078: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 800707c: f403 6300 and.w r3, r3, #2048 @ 0x800 8007080: 2b00 cmp r3, #0 8007082: d034 beq.n 80070ee { /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8007084: 687b ldr r3, [r7, #4] 8007086: 681b ldr r3, [r3, #0] 8007088: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800708c: b29b uxth r3, r3 800708e: 461a mov r2, r3 8007090: 6d7b ldr r3, [r7, #84] @ 0x54 8007092: 781b ldrb r3, [r3, #0] 8007094: 00db lsls r3, r3, #3 8007096: 4413 add r3, r2 8007098: 3306 adds r3, #6 800709a: 005b lsls r3, r3, #1 800709c: 687a ldr r2, [r7, #4] 800709e: 6812 ldr r2, [r2, #0] 80070a0: 4413 add r3, r2 80070a2: f503 6380 add.w r3, r3, #1024 @ 0x400 80070a6: 881b ldrh r3, [r3, #0] 80070a8: f3c3 0209 ubfx r2, r3, #0, #10 80070ac: 6d7b ldr r3, [r7, #84] @ 0x54 80070ae: 61da str r2, [r3, #28] USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, 80070b0: 687b ldr r3, [r7, #4] 80070b2: 6818 ldr r0, [r3, #0] 80070b4: 687b ldr r3, [r7, #4] 80070b6: f503 7126 add.w r1, r3, #664 @ 0x298 80070ba: 6d7b ldr r3, [r7, #84] @ 0x54 80070bc: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); 80070be: 6d7b ldr r3, [r7, #84] @ 0x54 80070c0: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, 80070c2: b29b uxth r3, r3 80070c4: f005 f91d bl 800c302 /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 80070c8: 687b ldr r3, [r7, #4] 80070ca: 681b ldr r3, [r3, #0] 80070cc: 881b ldrh r3, [r3, #0] 80070ce: b29a uxth r2, r3 80070d0: f640 738f movw r3, #3983 @ 0xf8f 80070d4: 4013 ands r3, r2 80070d6: 823b strh r3, [r7, #16] 80070d8: 687b ldr r3, [r7, #4] 80070da: 681b ldr r3, [r3, #0] 80070dc: 8a3a ldrh r2, [r7, #16] 80070de: f042 0280 orr.w r2, r2, #128 @ 0x80 80070e2: b292 uxth r2, r2 80070e4: 801a strh r2, [r3, #0] /* Process SETUP Packet*/ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 80070e6: 6878 ldr r0, [r7, #4] 80070e8: f006 ff5c bl 800dfa4 80070ec: e310 b.n 8007710 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else if ((wEPVal & USB_EP_CTR_RX) != 0U) 80070ee: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a 80070f2: 2b00 cmp r3, #0 80070f4: f280 830c bge.w 8007710 { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 80070f8: 687b ldr r3, [r7, #4] 80070fa: 681b ldr r3, [r3, #0] 80070fc: 881b ldrh r3, [r3, #0] 80070fe: b29a uxth r2, r3 8007100: f640 738f movw r3, #3983 @ 0xf8f 8007104: 4013 ands r3, r2 8007106: 83fb strh r3, [r7, #30] 8007108: 687b ldr r3, [r7, #4] 800710a: 681b ldr r3, [r3, #0] 800710c: 8bfa ldrh r2, [r7, #30] 800710e: f042 0280 orr.w r2, r2, #128 @ 0x80 8007112: b292 uxth r2, r2 8007114: 801a strh r2, [r3, #0] /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8007116: 687b ldr r3, [r7, #4] 8007118: 681b ldr r3, [r3, #0] 800711a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800711e: b29b uxth r3, r3 8007120: 461a mov r2, r3 8007122: 6d7b ldr r3, [r7, #84] @ 0x54 8007124: 781b ldrb r3, [r3, #0] 8007126: 00db lsls r3, r3, #3 8007128: 4413 add r3, r2 800712a: 3306 adds r3, #6 800712c: 005b lsls r3, r3, #1 800712e: 687a ldr r2, [r7, #4] 8007130: 6812 ldr r2, [r2, #0] 8007132: 4413 add r3, r2 8007134: f503 6380 add.w r3, r3, #1024 @ 0x400 8007138: 881b ldrh r3, [r3, #0] 800713a: f3c3 0209 ubfx r2, r3, #0, #10 800713e: 6d7b ldr r3, [r7, #84] @ 0x54 8007140: 61da str r2, [r3, #28] if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) 8007142: 6d7b ldr r3, [r7, #84] @ 0x54 8007144: 69db ldr r3, [r3, #28] 8007146: 2b00 cmp r3, #0 8007148: d019 beq.n 800717e 800714a: 6d7b ldr r3, [r7, #84] @ 0x54 800714c: 695b ldr r3, [r3, #20] 800714e: 2b00 cmp r3, #0 8007150: d015 beq.n 800717e { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 8007152: 687b ldr r3, [r7, #4] 8007154: 6818 ldr r0, [r3, #0] 8007156: 6d7b ldr r3, [r7, #84] @ 0x54 8007158: 6959 ldr r1, [r3, #20] 800715a: 6d7b ldr r3, [r7, #84] @ 0x54 800715c: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); 800715e: 6d7b ldr r3, [r7, #84] @ 0x54 8007160: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 8007162: b29b uxth r3, r3 8007164: f005 f8cd bl 800c302 ep->xfer_buff += ep->xfer_count; 8007168: 6d7b ldr r3, [r7, #84] @ 0x54 800716a: 695a ldr r2, [r3, #20] 800716c: 6d7b ldr r3, [r7, #84] @ 0x54 800716e: 69db ldr r3, [r3, #28] 8007170: 441a add r2, r3 8007172: 6d7b ldr r3, [r7, #84] @ 0x54 8007174: 615a str r2, [r3, #20] /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, 0U); #else HAL_PCD_DataOutStageCallback(hpcd, 0U); 8007176: 2100 movs r1, #0 8007178: 6878 ldr r0, [r7, #4] 800717a: f006 ff25 bl 800dfc8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); 800717e: 687b ldr r3, [r7, #4] 8007180: 681b ldr r3, [r3, #0] 8007182: 881b ldrh r3, [r3, #0] 8007184: f8a7 304a strh.w r3, [r7, #74] @ 0x4a if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) 8007188: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 800718c: f403 6300 and.w r3, r3, #2048 @ 0x800 8007190: 2b00 cmp r3, #0 8007192: f040 82bd bne.w 8007710 8007196: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 800719a: f403 5340 and.w r3, r3, #12288 @ 0x3000 800719e: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80071a2: f000 82b5 beq.w 8007710 { PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); 80071a6: 687b ldr r3, [r7, #4] 80071a8: 681b ldr r3, [r3, #0] 80071aa: 61bb str r3, [r7, #24] 80071ac: 687b ldr r3, [r7, #4] 80071ae: 681b ldr r3, [r3, #0] 80071b0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80071b4: b29b uxth r3, r3 80071b6: 461a mov r2, r3 80071b8: 69bb ldr r3, [r7, #24] 80071ba: 4413 add r3, r2 80071bc: 61bb str r3, [r7, #24] 80071be: 69bb ldr r3, [r7, #24] 80071c0: f203 430c addw r3, r3, #1036 @ 0x40c 80071c4: 617b str r3, [r7, #20] 80071c6: 697b ldr r3, [r7, #20] 80071c8: 881b ldrh r3, [r3, #0] 80071ca: b29b uxth r3, r3 80071cc: f3c3 0309 ubfx r3, r3, #0, #10 80071d0: b29a uxth r2, r3 80071d2: 697b ldr r3, [r7, #20] 80071d4: 801a strh r2, [r3, #0] 80071d6: 6d7b ldr r3, [r7, #84] @ 0x54 80071d8: 691b ldr r3, [r3, #16] 80071da: 2b3e cmp r3, #62 @ 0x3e 80071dc: d91d bls.n 800721a 80071de: 6d7b ldr r3, [r7, #84] @ 0x54 80071e0: 691b ldr r3, [r3, #16] 80071e2: 095b lsrs r3, r3, #5 80071e4: 647b str r3, [r7, #68] @ 0x44 80071e6: 6d7b ldr r3, [r7, #84] @ 0x54 80071e8: 691b ldr r3, [r3, #16] 80071ea: f003 031f and.w r3, r3, #31 80071ee: 2b00 cmp r3, #0 80071f0: d102 bne.n 80071f8 80071f2: 6c7b ldr r3, [r7, #68] @ 0x44 80071f4: 3b01 subs r3, #1 80071f6: 647b str r3, [r7, #68] @ 0x44 80071f8: 697b ldr r3, [r7, #20] 80071fa: 881b ldrh r3, [r3, #0] 80071fc: b29a uxth r2, r3 80071fe: 6c7b ldr r3, [r7, #68] @ 0x44 8007200: b29b uxth r3, r3 8007202: 029b lsls r3, r3, #10 8007204: b29b uxth r3, r3 8007206: 4313 orrs r3, r2 8007208: b29b uxth r3, r3 800720a: ea6f 4343 mvn.w r3, r3, lsl #17 800720e: ea6f 4353 mvn.w r3, r3, lsr #17 8007212: b29a uxth r2, r3 8007214: 697b ldr r3, [r7, #20] 8007216: 801a strh r2, [r3, #0] 8007218: e026 b.n 8007268 800721a: 6d7b ldr r3, [r7, #84] @ 0x54 800721c: 691b ldr r3, [r3, #16] 800721e: 2b00 cmp r3, #0 8007220: d10a bne.n 8007238 8007222: 697b ldr r3, [r7, #20] 8007224: 881b ldrh r3, [r3, #0] 8007226: b29b uxth r3, r3 8007228: ea6f 4343 mvn.w r3, r3, lsl #17 800722c: ea6f 4353 mvn.w r3, r3, lsr #17 8007230: b29a uxth r2, r3 8007232: 697b ldr r3, [r7, #20] 8007234: 801a strh r2, [r3, #0] 8007236: e017 b.n 8007268 8007238: 6d7b ldr r3, [r7, #84] @ 0x54 800723a: 691b ldr r3, [r3, #16] 800723c: 085b lsrs r3, r3, #1 800723e: 647b str r3, [r7, #68] @ 0x44 8007240: 6d7b ldr r3, [r7, #84] @ 0x54 8007242: 691b ldr r3, [r3, #16] 8007244: f003 0301 and.w r3, r3, #1 8007248: 2b00 cmp r3, #0 800724a: d002 beq.n 8007252 800724c: 6c7b ldr r3, [r7, #68] @ 0x44 800724e: 3301 adds r3, #1 8007250: 647b str r3, [r7, #68] @ 0x44 8007252: 697b ldr r3, [r7, #20] 8007254: 881b ldrh r3, [r3, #0] 8007256: b29a uxth r2, r3 8007258: 6c7b ldr r3, [r7, #68] @ 0x44 800725a: b29b uxth r3, r3 800725c: 029b lsls r3, r3, #10 800725e: b29b uxth r3, r3 8007260: 4313 orrs r3, r2 8007262: b29a uxth r2, r3 8007264: 697b ldr r3, [r7, #20] 8007266: 801a strh r2, [r3, #0] PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); 8007268: 687b ldr r3, [r7, #4] 800726a: 681b ldr r3, [r3, #0] 800726c: 881b ldrh r3, [r3, #0] 800726e: b29b uxth r3, r3 8007270: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8007274: f023 0370 bic.w r3, r3, #112 @ 0x70 8007278: 827b strh r3, [r7, #18] 800727a: 8a7b ldrh r3, [r7, #18] 800727c: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8007280: 827b strh r3, [r7, #18] 8007282: 8a7b ldrh r3, [r7, #18] 8007284: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8007288: 827b strh r3, [r7, #18] 800728a: 687b ldr r3, [r7, #4] 800728c: 681a ldr r2, [r3, #0] 800728e: 8a7b ldrh r3, [r7, #18] 8007290: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007294: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8007298: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800729c: f043 0380 orr.w r3, r3, #128 @ 0x80 80072a0: b29b uxth r3, r3 80072a2: 8013 strh r3, [r2, #0] 80072a4: e234 b.n 8007710 } else { /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); 80072a6: 687b ldr r3, [r7, #4] 80072a8: 681b ldr r3, [r3, #0] 80072aa: 461a mov r2, r3 80072ac: f897 304d ldrb.w r3, [r7, #77] @ 0x4d 80072b0: 009b lsls r3, r3, #2 80072b2: 4413 add r3, r2 80072b4: 881b ldrh r3, [r3, #0] 80072b6: f8a7 304a strh.w r3, [r7, #74] @ 0x4a if ((wEPVal & USB_EP_CTR_RX) != 0U) 80072ba: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a 80072be: 2b00 cmp r3, #0 80072c0: f280 80fc bge.w 80074bc { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); 80072c4: 687b ldr r3, [r7, #4] 80072c6: 681b ldr r3, [r3, #0] 80072c8: 461a mov r2, r3 80072ca: f897 304d ldrb.w r3, [r7, #77] @ 0x4d 80072ce: 009b lsls r3, r3, #2 80072d0: 4413 add r3, r2 80072d2: 881b ldrh r3, [r3, #0] 80072d4: b29a uxth r2, r3 80072d6: f640 738f movw r3, #3983 @ 0xf8f 80072da: 4013 ands r3, r2 80072dc: f8a7 3048 strh.w r3, [r7, #72] @ 0x48 80072e0: 687b ldr r3, [r7, #4] 80072e2: 681b ldr r3, [r3, #0] 80072e4: 461a mov r2, r3 80072e6: f897 304d ldrb.w r3, [r7, #77] @ 0x4d 80072ea: 009b lsls r3, r3, #2 80072ec: 4413 add r3, r2 80072ee: f8b7 2048 ldrh.w r2, [r7, #72] @ 0x48 80072f2: f042 0280 orr.w r2, r2, #128 @ 0x80 80072f6: b292 uxth r2, r2 80072f8: 801a strh r2, [r3, #0] ep = &hpcd->OUT_ep[epindex]; 80072fa: f897 204d ldrb.w r2, [r7, #77] @ 0x4d 80072fe: 4613 mov r3, r2 8007300: 009b lsls r3, r3, #2 8007302: 4413 add r3, r2 8007304: 00db lsls r3, r3, #3 8007306: f503 73a8 add.w r3, r3, #336 @ 0x150 800730a: 687a ldr r2, [r7, #4] 800730c: 4413 add r3, r2 800730e: 657b str r3, [r7, #84] @ 0x54 /* OUT Single Buffering */ if (ep->doublebuffer == 0U) 8007310: 6d7b ldr r3, [r7, #84] @ 0x54 8007312: 7b1b ldrb r3, [r3, #12] 8007314: 2b00 cmp r3, #0 8007316: d125 bne.n 8007364 { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8007318: 687b ldr r3, [r7, #4] 800731a: 681b ldr r3, [r3, #0] 800731c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007320: b29b uxth r3, r3 8007322: 461a mov r2, r3 8007324: 6d7b ldr r3, [r7, #84] @ 0x54 8007326: 781b ldrb r3, [r3, #0] 8007328: 00db lsls r3, r3, #3 800732a: 4413 add r3, r2 800732c: 3306 adds r3, #6 800732e: 005b lsls r3, r3, #1 8007330: 687a ldr r2, [r7, #4] 8007332: 6812 ldr r2, [r2, #0] 8007334: 4413 add r3, r2 8007336: f503 6380 add.w r3, r3, #1024 @ 0x400 800733a: 881b ldrh r3, [r3, #0] 800733c: f3c3 0309 ubfx r3, r3, #0, #10 8007340: f8a7 3050 strh.w r3, [r7, #80] @ 0x50 if (count != 0U) 8007344: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 8007348: 2b00 cmp r3, #0 800734a: f000 8092 beq.w 8007472 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); 800734e: 687b ldr r3, [r7, #4] 8007350: 6818 ldr r0, [r3, #0] 8007352: 6d7b ldr r3, [r7, #84] @ 0x54 8007354: 6959 ldr r1, [r3, #20] 8007356: 6d7b ldr r3, [r7, #84] @ 0x54 8007358: 88da ldrh r2, [r3, #6] 800735a: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 800735e: f004 ffd0 bl 800c302 8007362: e086 b.n 8007472 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* manage double buffer bulk out */ if (ep->type == EP_TYPE_BULK) 8007364: 6d7b ldr r3, [r7, #84] @ 0x54 8007366: 78db ldrb r3, [r3, #3] 8007368: 2b02 cmp r3, #2 800736a: d10a bne.n 8007382 { count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); 800736c: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 8007370: 461a mov r2, r3 8007372: 6d79 ldr r1, [r7, #84] @ 0x54 8007374: 6878 ldr r0, [r7, #4] 8007376: f000 f9d9 bl 800772c 800737a: 4603 mov r3, r0 800737c: f8a7 3050 strh.w r3, [r7, #80] @ 0x50 8007380: e077 b.n 8007472 } else /* manage double buffer iso out */ { /* free EP OUT Buffer */ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 8007382: 687b ldr r3, [r7, #4] 8007384: 681b ldr r3, [r3, #0] 8007386: 461a mov r2, r3 8007388: 6d7b ldr r3, [r7, #84] @ 0x54 800738a: 781b ldrb r3, [r3, #0] 800738c: 009b lsls r3, r3, #2 800738e: 4413 add r3, r2 8007390: 881b ldrh r3, [r3, #0] 8007392: b29b uxth r3, r3 8007394: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8007398: f023 0370 bic.w r3, r3, #112 @ 0x70 800739c: f8a7 3052 strh.w r3, [r7, #82] @ 0x52 80073a0: 687b ldr r3, [r7, #4] 80073a2: 681b ldr r3, [r3, #0] 80073a4: 461a mov r2, r3 80073a6: 6d7b ldr r3, [r7, #84] @ 0x54 80073a8: 781b ldrb r3, [r3, #0] 80073aa: 009b lsls r3, r3, #2 80073ac: 441a add r2, r3 80073ae: f8b7 3052 ldrh.w r3, [r7, #82] @ 0x52 80073b2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80073b6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80073ba: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80073be: f043 03c0 orr.w r3, r3, #192 @ 0xc0 80073c2: b29b uxth r3, r3 80073c4: 8013 strh r3, [r2, #0] if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) 80073c6: 687b ldr r3, [r7, #4] 80073c8: 681b ldr r3, [r3, #0] 80073ca: 461a mov r2, r3 80073cc: 6d7b ldr r3, [r7, #84] @ 0x54 80073ce: 781b ldrb r3, [r3, #0] 80073d0: 009b lsls r3, r3, #2 80073d2: 4413 add r3, r2 80073d4: 881b ldrh r3, [r3, #0] 80073d6: b29b uxth r3, r3 80073d8: f403 4380 and.w r3, r3, #16384 @ 0x4000 80073dc: 2b00 cmp r3, #0 80073de: d024 beq.n 800742a { /* read from endpoint BUF0Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 80073e0: 687b ldr r3, [r7, #4] 80073e2: 681b ldr r3, [r3, #0] 80073e4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80073e8: b29b uxth r3, r3 80073ea: 461a mov r2, r3 80073ec: 6d7b ldr r3, [r7, #84] @ 0x54 80073ee: 781b ldrb r3, [r3, #0] 80073f0: 00db lsls r3, r3, #3 80073f2: 4413 add r3, r2 80073f4: 3302 adds r3, #2 80073f6: 005b lsls r3, r3, #1 80073f8: 687a ldr r2, [r7, #4] 80073fa: 6812 ldr r2, [r2, #0] 80073fc: 4413 add r3, r2 80073fe: f503 6380 add.w r3, r3, #1024 @ 0x400 8007402: 881b ldrh r3, [r3, #0] 8007404: f3c3 0309 ubfx r3, r3, #0, #10 8007408: f8a7 3050 strh.w r3, [r7, #80] @ 0x50 if (count != 0U) 800740c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 8007410: 2b00 cmp r3, #0 8007412: d02e beq.n 8007472 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); 8007414: 687b ldr r3, [r7, #4] 8007416: 6818 ldr r0, [r3, #0] 8007418: 6d7b ldr r3, [r7, #84] @ 0x54 800741a: 6959 ldr r1, [r3, #20] 800741c: 6d7b ldr r3, [r7, #84] @ 0x54 800741e: 891a ldrh r2, [r3, #8] 8007420: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 8007424: f004 ff6d bl 800c302 8007428: e023 b.n 8007472 } } else { /* read from endpoint BUF1Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 800742a: 687b ldr r3, [r7, #4] 800742c: 681b ldr r3, [r3, #0] 800742e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007432: b29b uxth r3, r3 8007434: 461a mov r2, r3 8007436: 6d7b ldr r3, [r7, #84] @ 0x54 8007438: 781b ldrb r3, [r3, #0] 800743a: 00db lsls r3, r3, #3 800743c: 4413 add r3, r2 800743e: 3306 adds r3, #6 8007440: 005b lsls r3, r3, #1 8007442: 687a ldr r2, [r7, #4] 8007444: 6812 ldr r2, [r2, #0] 8007446: 4413 add r3, r2 8007448: f503 6380 add.w r3, r3, #1024 @ 0x400 800744c: 881b ldrh r3, [r3, #0] 800744e: f3c3 0309 ubfx r3, r3, #0, #10 8007452: f8a7 3050 strh.w r3, [r7, #80] @ 0x50 if (count != 0U) 8007456: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 800745a: 2b00 cmp r3, #0 800745c: d009 beq.n 8007472 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); 800745e: 687b ldr r3, [r7, #4] 8007460: 6818 ldr r0, [r3, #0] 8007462: 6d7b ldr r3, [r7, #84] @ 0x54 8007464: 6959 ldr r1, [r3, #20] 8007466: 6d7b ldr r3, [r7, #84] @ 0x54 8007468: 895a ldrh r2, [r3, #10] 800746a: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 800746e: f004 ff48 bl 800c302 } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; 8007472: 6d7b ldr r3, [r7, #84] @ 0x54 8007474: 69da ldr r2, [r3, #28] 8007476: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 800747a: 441a add r2, r3 800747c: 6d7b ldr r3, [r7, #84] @ 0x54 800747e: 61da str r2, [r3, #28] ep->xfer_buff += count; 8007480: 6d7b ldr r3, [r7, #84] @ 0x54 8007482: 695a ldr r2, [r3, #20] 8007484: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50 8007488: 441a add r2, r3 800748a: 6d7b ldr r3, [r7, #84] @ 0x54 800748c: 615a str r2, [r3, #20] if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) 800748e: 6d7b ldr r3, [r7, #84] @ 0x54 8007490: 699b ldr r3, [r3, #24] 8007492: 2b00 cmp r3, #0 8007494: d005 beq.n 80074a2 8007496: f8b7 2050 ldrh.w r2, [r7, #80] @ 0x50 800749a: 6d7b ldr r3, [r7, #84] @ 0x54 800749c: 691b ldr r3, [r3, #16] 800749e: 429a cmp r2, r3 80074a0: d206 bcs.n 80074b0 { /* RX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, ep->num); #else HAL_PCD_DataOutStageCallback(hpcd, ep->num); 80074a2: 6d7b ldr r3, [r7, #84] @ 0x54 80074a4: 781b ldrb r3, [r3, #0] 80074a6: 4619 mov r1, r3 80074a8: 6878 ldr r0, [r7, #4] 80074aa: f006 fd8d bl 800dfc8 80074ae: e005 b.n 80074bc #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { (void)USB_EPStartXfer(hpcd->Instance, ep); 80074b0: 687b ldr r3, [r7, #4] 80074b2: 681b ldr r3, [r3, #0] 80074b4: 6d79 ldr r1, [r7, #84] @ 0x54 80074b6: 4618 mov r0, r3 80074b8: f003 f9ee bl 800a898 } } if ((wEPVal & USB_EP_CTR_TX) != 0U) 80074bc: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 80074c0: f003 0380 and.w r3, r3, #128 @ 0x80 80074c4: 2b00 cmp r3, #0 80074c6: f000 8123 beq.w 8007710 { ep = &hpcd->IN_ep[epindex]; 80074ca: f897 204d ldrb.w r2, [r7, #77] @ 0x4d 80074ce: 4613 mov r3, r2 80074d0: 009b lsls r3, r3, #2 80074d2: 4413 add r3, r2 80074d4: 00db lsls r3, r3, #3 80074d6: 3310 adds r3, #16 80074d8: 687a ldr r2, [r7, #4] 80074da: 4413 add r3, r2 80074dc: 657b str r3, [r7, #84] @ 0x54 /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); 80074de: 687b ldr r3, [r7, #4] 80074e0: 681b ldr r3, [r3, #0] 80074e2: 461a mov r2, r3 80074e4: f897 304d ldrb.w r3, [r7, #77] @ 0x4d 80074e8: 009b lsls r3, r3, #2 80074ea: 4413 add r3, r2 80074ec: 881b ldrh r3, [r3, #0] 80074ee: b29b uxth r3, r3 80074f0: f423 43e1 bic.w r3, r3, #28800 @ 0x7080 80074f4: f023 0370 bic.w r3, r3, #112 @ 0x70 80074f8: f8a7 3042 strh.w r3, [r7, #66] @ 0x42 80074fc: 687b ldr r3, [r7, #4] 80074fe: 681b ldr r3, [r3, #0] 8007500: 461a mov r2, r3 8007502: f897 304d ldrb.w r3, [r7, #77] @ 0x4d 8007506: 009b lsls r3, r3, #2 8007508: 441a add r2, r3 800750a: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42 800750e: ea6f 4343 mvn.w r3, r3, lsl #17 8007512: ea6f 4353 mvn.w r3, r3, lsr #17 8007516: b29b uxth r3, r3 8007518: 8013 strh r3, [r2, #0] if (ep->type == EP_TYPE_ISOC) 800751a: 6d7b ldr r3, [r7, #84] @ 0x54 800751c: 78db ldrb r3, [r3, #3] 800751e: 2b01 cmp r3, #1 8007520: f040 80a2 bne.w 8007668 { ep->xfer_len = 0U; 8007524: 6d7b ldr r3, [r7, #84] @ 0x54 8007526: 2200 movs r2, #0 8007528: 619a str r2, [r3, #24] #if (USE_USB_DOUBLE_BUFFER == 1U) if (ep->doublebuffer != 0U) 800752a: 6d7b ldr r3, [r7, #84] @ 0x54 800752c: 7b1b ldrb r3, [r3, #12] 800752e: 2b00 cmp r3, #0 8007530: f000 8093 beq.w 800765a { if ((wEPVal & USB_EP_DTOG_TX) != 0U) 8007534: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 8007538: f003 0340 and.w r3, r3, #64 @ 0x40 800753c: 2b00 cmp r3, #0 800753e: d046 beq.n 80075ce { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 8007540: 6d7b ldr r3, [r7, #84] @ 0x54 8007542: 785b ldrb r3, [r3, #1] 8007544: 2b00 cmp r3, #0 8007546: d126 bne.n 8007596 8007548: 687b ldr r3, [r7, #4] 800754a: 681b ldr r3, [r3, #0] 800754c: 627b str r3, [r7, #36] @ 0x24 800754e: 687b ldr r3, [r7, #4] 8007550: 681b ldr r3, [r3, #0] 8007552: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007556: b29b uxth r3, r3 8007558: 461a mov r2, r3 800755a: 6a7b ldr r3, [r7, #36] @ 0x24 800755c: 4413 add r3, r2 800755e: 627b str r3, [r7, #36] @ 0x24 8007560: 6d7b ldr r3, [r7, #84] @ 0x54 8007562: 781b ldrb r3, [r3, #0] 8007564: 011a lsls r2, r3, #4 8007566: 6a7b ldr r3, [r7, #36] @ 0x24 8007568: 4413 add r3, r2 800756a: f203 4304 addw r3, r3, #1028 @ 0x404 800756e: 623b str r3, [r7, #32] 8007570: 6a3b ldr r3, [r7, #32] 8007572: 881b ldrh r3, [r3, #0] 8007574: b29b uxth r3, r3 8007576: f3c3 0309 ubfx r3, r3, #0, #10 800757a: b29a uxth r2, r3 800757c: 6a3b ldr r3, [r7, #32] 800757e: 801a strh r2, [r3, #0] 8007580: 6a3b ldr r3, [r7, #32] 8007582: 881b ldrh r3, [r3, #0] 8007584: b29b uxth r3, r3 8007586: ea6f 4343 mvn.w r3, r3, lsl #17 800758a: ea6f 4353 mvn.w r3, r3, lsr #17 800758e: b29a uxth r2, r3 8007590: 6a3b ldr r3, [r7, #32] 8007592: 801a strh r2, [r3, #0] 8007594: e061 b.n 800765a 8007596: 6d7b ldr r3, [r7, #84] @ 0x54 8007598: 785b ldrb r3, [r3, #1] 800759a: 2b01 cmp r3, #1 800759c: d15d bne.n 800765a 800759e: 687b ldr r3, [r7, #4] 80075a0: 681b ldr r3, [r3, #0] 80075a2: 62fb str r3, [r7, #44] @ 0x2c 80075a4: 687b ldr r3, [r7, #4] 80075a6: 681b ldr r3, [r3, #0] 80075a8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80075ac: b29b uxth r3, r3 80075ae: 461a mov r2, r3 80075b0: 6afb ldr r3, [r7, #44] @ 0x2c 80075b2: 4413 add r3, r2 80075b4: 62fb str r3, [r7, #44] @ 0x2c 80075b6: 6d7b ldr r3, [r7, #84] @ 0x54 80075b8: 781b ldrb r3, [r3, #0] 80075ba: 011a lsls r2, r3, #4 80075bc: 6afb ldr r3, [r7, #44] @ 0x2c 80075be: 4413 add r3, r2 80075c0: f203 4304 addw r3, r3, #1028 @ 0x404 80075c4: 62bb str r3, [r7, #40] @ 0x28 80075c6: 6abb ldr r3, [r7, #40] @ 0x28 80075c8: 2200 movs r2, #0 80075ca: 801a strh r2, [r3, #0] 80075cc: e045 b.n 800765a } else { PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 80075ce: 687b ldr r3, [r7, #4] 80075d0: 681b ldr r3, [r3, #0] 80075d2: 63fb str r3, [r7, #60] @ 0x3c 80075d4: 6d7b ldr r3, [r7, #84] @ 0x54 80075d6: 785b ldrb r3, [r3, #1] 80075d8: 2b00 cmp r3, #0 80075da: d126 bne.n 800762a 80075dc: 687b ldr r3, [r7, #4] 80075de: 681b ldr r3, [r3, #0] 80075e0: 637b str r3, [r7, #52] @ 0x34 80075e2: 687b ldr r3, [r7, #4] 80075e4: 681b ldr r3, [r3, #0] 80075e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80075ea: b29b uxth r3, r3 80075ec: 461a mov r2, r3 80075ee: 6b7b ldr r3, [r7, #52] @ 0x34 80075f0: 4413 add r3, r2 80075f2: 637b str r3, [r7, #52] @ 0x34 80075f4: 6d7b ldr r3, [r7, #84] @ 0x54 80075f6: 781b ldrb r3, [r3, #0] 80075f8: 011a lsls r2, r3, #4 80075fa: 6b7b ldr r3, [r7, #52] @ 0x34 80075fc: 4413 add r3, r2 80075fe: f203 430c addw r3, r3, #1036 @ 0x40c 8007602: 633b str r3, [r7, #48] @ 0x30 8007604: 6b3b ldr r3, [r7, #48] @ 0x30 8007606: 881b ldrh r3, [r3, #0] 8007608: b29b uxth r3, r3 800760a: f3c3 0309 ubfx r3, r3, #0, #10 800760e: b29a uxth r2, r3 8007610: 6b3b ldr r3, [r7, #48] @ 0x30 8007612: 801a strh r2, [r3, #0] 8007614: 6b3b ldr r3, [r7, #48] @ 0x30 8007616: 881b ldrh r3, [r3, #0] 8007618: b29b uxth r3, r3 800761a: ea6f 4343 mvn.w r3, r3, lsl #17 800761e: ea6f 4353 mvn.w r3, r3, lsr #17 8007622: b29a uxth r2, r3 8007624: 6b3b ldr r3, [r7, #48] @ 0x30 8007626: 801a strh r2, [r3, #0] 8007628: e017 b.n 800765a 800762a: 6d7b ldr r3, [r7, #84] @ 0x54 800762c: 785b ldrb r3, [r3, #1] 800762e: 2b01 cmp r3, #1 8007630: d113 bne.n 800765a 8007632: 687b ldr r3, [r7, #4] 8007634: 681b ldr r3, [r3, #0] 8007636: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800763a: b29b uxth r3, r3 800763c: 461a mov r2, r3 800763e: 6bfb ldr r3, [r7, #60] @ 0x3c 8007640: 4413 add r3, r2 8007642: 63fb str r3, [r7, #60] @ 0x3c 8007644: 6d7b ldr r3, [r7, #84] @ 0x54 8007646: 781b ldrb r3, [r3, #0] 8007648: 011a lsls r2, r3, #4 800764a: 6bfb ldr r3, [r7, #60] @ 0x3c 800764c: 4413 add r3, r2 800764e: f203 430c addw r3, r3, #1036 @ 0x40c 8007652: 63bb str r3, [r7, #56] @ 0x38 8007654: 6bbb ldr r3, [r7, #56] @ 0x38 8007656: 2200 movs r2, #0 8007658: 801a strh r2, [r3, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800765a: 6d7b ldr r3, [r7, #84] @ 0x54 800765c: 781b ldrb r3, [r3, #0] 800765e: 4619 mov r1, r3 8007660: 6878 ldr r0, [r7, #4] 8007662: f006 fccc bl 800dffe 8007666: e053 b.n 8007710 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) 8007668: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 800766c: f403 7380 and.w r3, r3, #256 @ 0x100 8007670: 2b00 cmp r3, #0 8007672: d146 bne.n 8007702 { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); 8007674: 687b ldr r3, [r7, #4] 8007676: 681b ldr r3, [r3, #0] 8007678: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800767c: b29b uxth r3, r3 800767e: 461a mov r2, r3 8007680: 6d7b ldr r3, [r7, #84] @ 0x54 8007682: 781b ldrb r3, [r3, #0] 8007684: 00db lsls r3, r3, #3 8007686: 4413 add r3, r2 8007688: 3302 adds r3, #2 800768a: 005b lsls r3, r3, #1 800768c: 687a ldr r2, [r7, #4] 800768e: 6812 ldr r2, [r2, #0] 8007690: 4413 add r3, r2 8007692: f503 6380 add.w r3, r3, #1024 @ 0x400 8007696: 881b ldrh r3, [r3, #0] 8007698: f3c3 0309 ubfx r3, r3, #0, #10 800769c: f8a7 3040 strh.w r3, [r7, #64] @ 0x40 if (ep->xfer_len > TxPctSize) 80076a0: 6d7b ldr r3, [r7, #84] @ 0x54 80076a2: 699a ldr r2, [r3, #24] 80076a4: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40 80076a8: 429a cmp r2, r3 80076aa: d907 bls.n 80076bc { ep->xfer_len -= TxPctSize; 80076ac: 6d7b ldr r3, [r7, #84] @ 0x54 80076ae: 699a ldr r2, [r3, #24] 80076b0: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40 80076b4: 1ad2 subs r2, r2, r3 80076b6: 6d7b ldr r3, [r7, #84] @ 0x54 80076b8: 619a str r2, [r3, #24] 80076ba: e002 b.n 80076c2 } else { ep->xfer_len = 0U; 80076bc: 6d7b ldr r3, [r7, #84] @ 0x54 80076be: 2200 movs r2, #0 80076c0: 619a str r2, [r3, #24] } /* Zero Length Packet? */ if (ep->xfer_len == 0U) 80076c2: 6d7b ldr r3, [r7, #84] @ 0x54 80076c4: 699b ldr r3, [r3, #24] 80076c6: 2b00 cmp r3, #0 80076c8: d106 bne.n 80076d8 { /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 80076ca: 6d7b ldr r3, [r7, #84] @ 0x54 80076cc: 781b ldrb r3, [r3, #0] 80076ce: 4619 mov r1, r3 80076d0: 6878 ldr r0, [r7, #4] 80076d2: f006 fc94 bl 800dffe 80076d6: e01b b.n 8007710 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Transfer is not yet Done */ ep->xfer_buff += TxPctSize; 80076d8: 6d7b ldr r3, [r7, #84] @ 0x54 80076da: 695a ldr r2, [r3, #20] 80076dc: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40 80076e0: 441a add r2, r3 80076e2: 6d7b ldr r3, [r7, #84] @ 0x54 80076e4: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 80076e6: 6d7b ldr r3, [r7, #84] @ 0x54 80076e8: 69da ldr r2, [r3, #28] 80076ea: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40 80076ee: 441a add r2, r3 80076f0: 6d7b ldr r3, [r7, #84] @ 0x54 80076f2: 61da str r2, [r3, #28] (void)USB_EPStartXfer(hpcd->Instance, ep); 80076f4: 687b ldr r3, [r7, #4] 80076f6: 681b ldr r3, [r3, #0] 80076f8: 6d79 ldr r1, [r7, #84] @ 0x54 80076fa: 4618 mov r0, r3 80076fc: f003 f8cc bl 800a898 8007700: e006 b.n 8007710 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); 8007702: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 8007706: 461a mov r2, r3 8007708: 6d79 ldr r1, [r7, #84] @ 0x54 800770a: 6878 ldr r0, [r7, #4] 800770c: f000 f91b bl 8007946 while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) 8007710: 687b ldr r3, [r7, #4] 8007712: 681b ldr r3, [r3, #0] 8007714: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8007718: b29b uxth r3, r3 800771a: b21b sxth r3, r3 800771c: 2b00 cmp r3, #0 800771e: f6ff ac3b blt.w 8006f98 } } } } return HAL_OK; 8007722: 2300 movs r3, #0 } 8007724: 4618 mov r0, r3 8007726: 3758 adds r7, #88 @ 0x58 8007728: 46bd mov sp, r7 800772a: bd80 pop {r7, pc} 0800772c : * @param wEPVal Last snapshot of EPRx register value taken in ISR * @retval HAL status */ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal) { 800772c: b580 push {r7, lr} 800772e: b088 sub sp, #32 8007730: af00 add r7, sp, #0 8007732: 60f8 str r0, [r7, #12] 8007734: 60b9 str r1, [r7, #8] 8007736: 4613 mov r3, r2 8007738: 80fb strh r3, [r7, #6] uint16_t count; /* Manage Buffer0 OUT */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 800773a: 88fb ldrh r3, [r7, #6] 800773c: f403 4380 and.w r3, r3, #16384 @ 0x4000 8007740: 2b00 cmp r3, #0 8007742: d07e beq.n 8007842 { /* Get count of received Data on buffer0 */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 8007744: 68fb ldr r3, [r7, #12] 8007746: 681b ldr r3, [r3, #0] 8007748: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800774c: b29b uxth r3, r3 800774e: 461a mov r2, r3 8007750: 68bb ldr r3, [r7, #8] 8007752: 781b ldrb r3, [r3, #0] 8007754: 00db lsls r3, r3, #3 8007756: 4413 add r3, r2 8007758: 3302 adds r3, #2 800775a: 005b lsls r3, r3, #1 800775c: 68fa ldr r2, [r7, #12] 800775e: 6812 ldr r2, [r2, #0] 8007760: 4413 add r3, r2 8007762: f503 6380 add.w r3, r3, #1024 @ 0x400 8007766: 881b ldrh r3, [r3, #0] 8007768: f3c3 0309 ubfx r3, r3, #0, #10 800776c: 837b strh r3, [r7, #26] if (ep->xfer_len >= count) 800776e: 68bb ldr r3, [r7, #8] 8007770: 699a ldr r2, [r3, #24] 8007772: 8b7b ldrh r3, [r7, #26] 8007774: 429a cmp r2, r3 8007776: d306 bcc.n 8007786 { ep->xfer_len -= count; 8007778: 68bb ldr r3, [r7, #8] 800777a: 699a ldr r2, [r3, #24] 800777c: 8b7b ldrh r3, [r7, #26] 800777e: 1ad2 subs r2, r2, r3 8007780: 68bb ldr r3, [r7, #8] 8007782: 619a str r2, [r3, #24] 8007784: e002 b.n 800778c } else { ep->xfer_len = 0U; 8007786: 68bb ldr r3, [r7, #8] 8007788: 2200 movs r2, #0 800778a: 619a str r2, [r3, #24] } if (ep->xfer_len == 0U) 800778c: 68bb ldr r3, [r7, #8] 800778e: 699b ldr r3, [r3, #24] 8007790: 2b00 cmp r3, #0 8007792: d123 bne.n 80077dc { /* set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); 8007794: 68fb ldr r3, [r7, #12] 8007796: 681b ldr r3, [r3, #0] 8007798: 461a mov r2, r3 800779a: 68bb ldr r3, [r7, #8] 800779c: 781b ldrb r3, [r3, #0] 800779e: 009b lsls r3, r3, #2 80077a0: 4413 add r3, r2 80077a2: 881b ldrh r3, [r3, #0] 80077a4: b29b uxth r3, r3 80077a6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80077aa: f023 0370 bic.w r3, r3, #112 @ 0x70 80077ae: 833b strh r3, [r7, #24] 80077b0: 8b3b ldrh r3, [r7, #24] 80077b2: f483 5300 eor.w r3, r3, #8192 @ 0x2000 80077b6: 833b strh r3, [r7, #24] 80077b8: 68fb ldr r3, [r7, #12] 80077ba: 681b ldr r3, [r3, #0] 80077bc: 461a mov r2, r3 80077be: 68bb ldr r3, [r7, #8] 80077c0: 781b ldrb r3, [r3, #0] 80077c2: 009b lsls r3, r3, #2 80077c4: 441a add r2, r3 80077c6: 8b3b ldrh r3, [r7, #24] 80077c8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80077cc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80077d0: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80077d4: f043 0380 orr.w r3, r3, #128 @ 0x80 80077d8: b29b uxth r3, r3 80077da: 8013 strh r3, [r2, #0] } /* Check if Buffer1 is in blocked state which requires to toggle */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) 80077dc: 88fb ldrh r3, [r7, #6] 80077de: f003 0340 and.w r3, r3, #64 @ 0x40 80077e2: 2b00 cmp r3, #0 80077e4: d01f beq.n 8007826 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 80077e6: 68fb ldr r3, [r7, #12] 80077e8: 681b ldr r3, [r3, #0] 80077ea: 461a mov r2, r3 80077ec: 68bb ldr r3, [r7, #8] 80077ee: 781b ldrb r3, [r3, #0] 80077f0: 009b lsls r3, r3, #2 80077f2: 4413 add r3, r2 80077f4: 881b ldrh r3, [r3, #0] 80077f6: b29b uxth r3, r3 80077f8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80077fc: f023 0370 bic.w r3, r3, #112 @ 0x70 8007800: 82fb strh r3, [r7, #22] 8007802: 68fb ldr r3, [r7, #12] 8007804: 681b ldr r3, [r3, #0] 8007806: 461a mov r2, r3 8007808: 68bb ldr r3, [r7, #8] 800780a: 781b ldrb r3, [r3, #0] 800780c: 009b lsls r3, r3, #2 800780e: 441a add r2, r3 8007810: 8afb ldrh r3, [r7, #22] 8007812: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007816: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800781a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800781e: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8007822: b29b uxth r3, r3 8007824: 8013 strh r3, [r2, #0] } if (count != 0U) 8007826: 8b7b ldrh r3, [r7, #26] 8007828: 2b00 cmp r3, #0 800782a: f000 8087 beq.w 800793c { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); 800782e: 68fb ldr r3, [r7, #12] 8007830: 6818 ldr r0, [r3, #0] 8007832: 68bb ldr r3, [r7, #8] 8007834: 6959 ldr r1, [r3, #20] 8007836: 68bb ldr r3, [r7, #8] 8007838: 891a ldrh r2, [r3, #8] 800783a: 8b7b ldrh r3, [r7, #26] 800783c: f004 fd61 bl 800c302 8007840: e07c b.n 800793c } /* Manage Buffer 1 DTOG_RX=0 */ else { /* Get count of received data */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 8007842: 68fb ldr r3, [r7, #12] 8007844: 681b ldr r3, [r3, #0] 8007846: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800784a: b29b uxth r3, r3 800784c: 461a mov r2, r3 800784e: 68bb ldr r3, [r7, #8] 8007850: 781b ldrb r3, [r3, #0] 8007852: 00db lsls r3, r3, #3 8007854: 4413 add r3, r2 8007856: 3306 adds r3, #6 8007858: 005b lsls r3, r3, #1 800785a: 68fa ldr r2, [r7, #12] 800785c: 6812 ldr r2, [r2, #0] 800785e: 4413 add r3, r2 8007860: f503 6380 add.w r3, r3, #1024 @ 0x400 8007864: 881b ldrh r3, [r3, #0] 8007866: f3c3 0309 ubfx r3, r3, #0, #10 800786a: 837b strh r3, [r7, #26] if (ep->xfer_len >= count) 800786c: 68bb ldr r3, [r7, #8] 800786e: 699a ldr r2, [r3, #24] 8007870: 8b7b ldrh r3, [r7, #26] 8007872: 429a cmp r2, r3 8007874: d306 bcc.n 8007884 { ep->xfer_len -= count; 8007876: 68bb ldr r3, [r7, #8] 8007878: 699a ldr r2, [r3, #24] 800787a: 8b7b ldrh r3, [r7, #26] 800787c: 1ad2 subs r2, r2, r3 800787e: 68bb ldr r3, [r7, #8] 8007880: 619a str r2, [r3, #24] 8007882: e002 b.n 800788a } else { ep->xfer_len = 0U; 8007884: 68bb ldr r3, [r7, #8] 8007886: 2200 movs r2, #0 8007888: 619a str r2, [r3, #24] } if (ep->xfer_len == 0U) 800788a: 68bb ldr r3, [r7, #8] 800788c: 699b ldr r3, [r3, #24] 800788e: 2b00 cmp r3, #0 8007890: d123 bne.n 80078da { /* set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); 8007892: 68fb ldr r3, [r7, #12] 8007894: 681b ldr r3, [r3, #0] 8007896: 461a mov r2, r3 8007898: 68bb ldr r3, [r7, #8] 800789a: 781b ldrb r3, [r3, #0] 800789c: 009b lsls r3, r3, #2 800789e: 4413 add r3, r2 80078a0: 881b ldrh r3, [r3, #0] 80078a2: b29b uxth r3, r3 80078a4: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80078a8: f023 0370 bic.w r3, r3, #112 @ 0x70 80078ac: 83fb strh r3, [r7, #30] 80078ae: 8bfb ldrh r3, [r7, #30] 80078b0: f483 5300 eor.w r3, r3, #8192 @ 0x2000 80078b4: 83fb strh r3, [r7, #30] 80078b6: 68fb ldr r3, [r7, #12] 80078b8: 681b ldr r3, [r3, #0] 80078ba: 461a mov r2, r3 80078bc: 68bb ldr r3, [r7, #8] 80078be: 781b ldrb r3, [r3, #0] 80078c0: 009b lsls r3, r3, #2 80078c2: 441a add r2, r3 80078c4: 8bfb ldrh r3, [r7, #30] 80078c6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80078ca: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80078ce: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80078d2: f043 0380 orr.w r3, r3, #128 @ 0x80 80078d6: b29b uxth r3, r3 80078d8: 8013 strh r3, [r2, #0] } /*Need to FreeUser Buffer*/ if ((wEPVal & USB_EP_DTOG_TX) == 0U) 80078da: 88fb ldrh r3, [r7, #6] 80078dc: f003 0340 and.w r3, r3, #64 @ 0x40 80078e0: 2b00 cmp r3, #0 80078e2: d11f bne.n 8007924 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 80078e4: 68fb ldr r3, [r7, #12] 80078e6: 681b ldr r3, [r3, #0] 80078e8: 461a mov r2, r3 80078ea: 68bb ldr r3, [r7, #8] 80078ec: 781b ldrb r3, [r3, #0] 80078ee: 009b lsls r3, r3, #2 80078f0: 4413 add r3, r2 80078f2: 881b ldrh r3, [r3, #0] 80078f4: b29b uxth r3, r3 80078f6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80078fa: f023 0370 bic.w r3, r3, #112 @ 0x70 80078fe: 83bb strh r3, [r7, #28] 8007900: 68fb ldr r3, [r7, #12] 8007902: 681b ldr r3, [r3, #0] 8007904: 461a mov r2, r3 8007906: 68bb ldr r3, [r7, #8] 8007908: 781b ldrb r3, [r3, #0] 800790a: 009b lsls r3, r3, #2 800790c: 441a add r2, r3 800790e: 8bbb ldrh r3, [r7, #28] 8007910: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007914: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8007918: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800791c: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8007920: b29b uxth r3, r3 8007922: 8013 strh r3, [r2, #0] } if (count != 0U) 8007924: 8b7b ldrh r3, [r7, #26] 8007926: 2b00 cmp r3, #0 8007928: d008 beq.n 800793c { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); 800792a: 68fb ldr r3, [r7, #12] 800792c: 6818 ldr r0, [r3, #0] 800792e: 68bb ldr r3, [r7, #8] 8007930: 6959 ldr r1, [r3, #20] 8007932: 68bb ldr r3, [r7, #8] 8007934: 895a ldrh r2, [r3, #10] 8007936: 8b7b ldrh r3, [r7, #26] 8007938: f004 fce3 bl 800c302 } } return count; 800793c: 8b7b ldrh r3, [r7, #26] } 800793e: 4618 mov r0, r3 8007940: 3720 adds r7, #32 8007942: 46bd mov sp, r7 8007944: bd80 pop {r7, pc} 08007946 : * @param wEPVal Last snapshot of EPRx register value taken in ISR * @retval HAL status */ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal) { 8007946: b580 push {r7, lr} 8007948: b0a4 sub sp, #144 @ 0x90 800794a: af00 add r7, sp, #0 800794c: 60f8 str r0, [r7, #12] 800794e: 60b9 str r1, [r7, #8] 8007950: 4613 mov r3, r2 8007952: 80fb strh r3, [r7, #6] uint32_t len; uint16_t TxPctSize; /* Data Buffer0 ACK received */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) 8007954: 88fb ldrh r3, [r7, #6] 8007956: f003 0340 and.w r3, r3, #64 @ 0x40 800795a: 2b00 cmp r3, #0 800795c: f000 81dd beq.w 8007d1a { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 8007960: 68fb ldr r3, [r7, #12] 8007962: 681b ldr r3, [r3, #0] 8007964: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007968: b29b uxth r3, r3 800796a: 461a mov r2, r3 800796c: 68bb ldr r3, [r7, #8] 800796e: 781b ldrb r3, [r3, #0] 8007970: 00db lsls r3, r3, #3 8007972: 4413 add r3, r2 8007974: 3302 adds r3, #2 8007976: 005b lsls r3, r3, #1 8007978: 68fa ldr r2, [r7, #12] 800797a: 6812 ldr r2, [r2, #0] 800797c: 4413 add r3, r2 800797e: f503 6380 add.w r3, r3, #1024 @ 0x400 8007982: 881b ldrh r3, [r3, #0] 8007984: f3c3 0309 ubfx r3, r3, #0, #10 8007988: f8a7 3086 strh.w r3, [r7, #134] @ 0x86 if (ep->xfer_len > TxPctSize) 800798c: 68bb ldr r3, [r7, #8] 800798e: 699a ldr r2, [r3, #24] 8007990: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007994: 429a cmp r2, r3 8007996: d907 bls.n 80079a8 { ep->xfer_len -= TxPctSize; 8007998: 68bb ldr r3, [r7, #8] 800799a: 699a ldr r2, [r3, #24] 800799c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 80079a0: 1ad2 subs r2, r2, r3 80079a2: 68bb ldr r3, [r7, #8] 80079a4: 619a str r2, [r3, #24] 80079a6: e002 b.n 80079ae } else { ep->xfer_len = 0U; 80079a8: 68bb ldr r3, [r7, #8] 80079aa: 2200 movs r2, #0 80079ac: 619a str r2, [r3, #24] } /* Transfer is completed */ if (ep->xfer_len == 0U) 80079ae: 68bb ldr r3, [r7, #8] 80079b0: 699b ldr r3, [r3, #24] 80079b2: 2b00 cmp r3, #0 80079b4: f040 80b9 bne.w 8007b2a { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 80079b8: 68bb ldr r3, [r7, #8] 80079ba: 785b ldrb r3, [r3, #1] 80079bc: 2b00 cmp r3, #0 80079be: d126 bne.n 8007a0e 80079c0: 68fb ldr r3, [r7, #12] 80079c2: 681b ldr r3, [r3, #0] 80079c4: 62fb str r3, [r7, #44] @ 0x2c 80079c6: 68fb ldr r3, [r7, #12] 80079c8: 681b ldr r3, [r3, #0] 80079ca: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80079ce: b29b uxth r3, r3 80079d0: 461a mov r2, r3 80079d2: 6afb ldr r3, [r7, #44] @ 0x2c 80079d4: 4413 add r3, r2 80079d6: 62fb str r3, [r7, #44] @ 0x2c 80079d8: 68bb ldr r3, [r7, #8] 80079da: 781b ldrb r3, [r3, #0] 80079dc: 011a lsls r2, r3, #4 80079de: 6afb ldr r3, [r7, #44] @ 0x2c 80079e0: 4413 add r3, r2 80079e2: f203 4304 addw r3, r3, #1028 @ 0x404 80079e6: 62bb str r3, [r7, #40] @ 0x28 80079e8: 6abb ldr r3, [r7, #40] @ 0x28 80079ea: 881b ldrh r3, [r3, #0] 80079ec: b29b uxth r3, r3 80079ee: f3c3 0309 ubfx r3, r3, #0, #10 80079f2: b29a uxth r2, r3 80079f4: 6abb ldr r3, [r7, #40] @ 0x28 80079f6: 801a strh r2, [r3, #0] 80079f8: 6abb ldr r3, [r7, #40] @ 0x28 80079fa: 881b ldrh r3, [r3, #0] 80079fc: b29b uxth r3, r3 80079fe: ea6f 4343 mvn.w r3, r3, lsl #17 8007a02: ea6f 4353 mvn.w r3, r3, lsr #17 8007a06: b29a uxth r2, r3 8007a08: 6abb ldr r3, [r7, #40] @ 0x28 8007a0a: 801a strh r2, [r3, #0] 8007a0c: e01a b.n 8007a44 8007a0e: 68bb ldr r3, [r7, #8] 8007a10: 785b ldrb r3, [r3, #1] 8007a12: 2b01 cmp r3, #1 8007a14: d116 bne.n 8007a44 8007a16: 68fb ldr r3, [r7, #12] 8007a18: 681b ldr r3, [r3, #0] 8007a1a: 637b str r3, [r7, #52] @ 0x34 8007a1c: 68fb ldr r3, [r7, #12] 8007a1e: 681b ldr r3, [r3, #0] 8007a20: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007a24: b29b uxth r3, r3 8007a26: 461a mov r2, r3 8007a28: 6b7b ldr r3, [r7, #52] @ 0x34 8007a2a: 4413 add r3, r2 8007a2c: 637b str r3, [r7, #52] @ 0x34 8007a2e: 68bb ldr r3, [r7, #8] 8007a30: 781b ldrb r3, [r3, #0] 8007a32: 011a lsls r2, r3, #4 8007a34: 6b7b ldr r3, [r7, #52] @ 0x34 8007a36: 4413 add r3, r2 8007a38: f203 4304 addw r3, r3, #1028 @ 0x404 8007a3c: 633b str r3, [r7, #48] @ 0x30 8007a3e: 6b3b ldr r3, [r7, #48] @ 0x30 8007a40: 2200 movs r2, #0 8007a42: 801a strh r2, [r3, #0] PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 8007a44: 68fb ldr r3, [r7, #12] 8007a46: 681b ldr r3, [r3, #0] 8007a48: 627b str r3, [r7, #36] @ 0x24 8007a4a: 68bb ldr r3, [r7, #8] 8007a4c: 785b ldrb r3, [r3, #1] 8007a4e: 2b00 cmp r3, #0 8007a50: d126 bne.n 8007aa0 8007a52: 68fb ldr r3, [r7, #12] 8007a54: 681b ldr r3, [r3, #0] 8007a56: 61fb str r3, [r7, #28] 8007a58: 68fb ldr r3, [r7, #12] 8007a5a: 681b ldr r3, [r3, #0] 8007a5c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007a60: b29b uxth r3, r3 8007a62: 461a mov r2, r3 8007a64: 69fb ldr r3, [r7, #28] 8007a66: 4413 add r3, r2 8007a68: 61fb str r3, [r7, #28] 8007a6a: 68bb ldr r3, [r7, #8] 8007a6c: 781b ldrb r3, [r3, #0] 8007a6e: 011a lsls r2, r3, #4 8007a70: 69fb ldr r3, [r7, #28] 8007a72: 4413 add r3, r2 8007a74: f203 430c addw r3, r3, #1036 @ 0x40c 8007a78: 61bb str r3, [r7, #24] 8007a7a: 69bb ldr r3, [r7, #24] 8007a7c: 881b ldrh r3, [r3, #0] 8007a7e: b29b uxth r3, r3 8007a80: f3c3 0309 ubfx r3, r3, #0, #10 8007a84: b29a uxth r2, r3 8007a86: 69bb ldr r3, [r7, #24] 8007a88: 801a strh r2, [r3, #0] 8007a8a: 69bb ldr r3, [r7, #24] 8007a8c: 881b ldrh r3, [r3, #0] 8007a8e: b29b uxth r3, r3 8007a90: ea6f 4343 mvn.w r3, r3, lsl #17 8007a94: ea6f 4353 mvn.w r3, r3, lsr #17 8007a98: b29a uxth r2, r3 8007a9a: 69bb ldr r3, [r7, #24] 8007a9c: 801a strh r2, [r3, #0] 8007a9e: e017 b.n 8007ad0 8007aa0: 68bb ldr r3, [r7, #8] 8007aa2: 785b ldrb r3, [r3, #1] 8007aa4: 2b01 cmp r3, #1 8007aa6: d113 bne.n 8007ad0 8007aa8: 68fb ldr r3, [r7, #12] 8007aaa: 681b ldr r3, [r3, #0] 8007aac: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007ab0: b29b uxth r3, r3 8007ab2: 461a mov r2, r3 8007ab4: 6a7b ldr r3, [r7, #36] @ 0x24 8007ab6: 4413 add r3, r2 8007ab8: 627b str r3, [r7, #36] @ 0x24 8007aba: 68bb ldr r3, [r7, #8] 8007abc: 781b ldrb r3, [r3, #0] 8007abe: 011a lsls r2, r3, #4 8007ac0: 6a7b ldr r3, [r7, #36] @ 0x24 8007ac2: 4413 add r3, r2 8007ac4: f203 430c addw r3, r3, #1036 @ 0x40c 8007ac8: 623b str r3, [r7, #32] 8007aca: 6a3b ldr r3, [r7, #32] 8007acc: 2200 movs r2, #0 8007ace: 801a strh r2, [r3, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 8007ad0: 68bb ldr r3, [r7, #8] 8007ad2: 781b ldrb r3, [r3, #0] 8007ad4: 4619 mov r1, r3 8007ad6: 68f8 ldr r0, [r7, #12] 8007ad8: f006 fa91 bl 800dffe #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 8007adc: 88fb ldrh r3, [r7, #6] 8007ade: f403 4380 and.w r3, r3, #16384 @ 0x4000 8007ae2: 2b00 cmp r3, #0 8007ae4: f000 82fc beq.w 80080e0 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 8007ae8: 68fb ldr r3, [r7, #12] 8007aea: 681b ldr r3, [r3, #0] 8007aec: 461a mov r2, r3 8007aee: 68bb ldr r3, [r7, #8] 8007af0: 781b ldrb r3, [r3, #0] 8007af2: 009b lsls r3, r3, #2 8007af4: 4413 add r3, r2 8007af6: 881b ldrh r3, [r3, #0] 8007af8: b29b uxth r3, r3 8007afa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8007afe: f023 0370 bic.w r3, r3, #112 @ 0x70 8007b02: 82fb strh r3, [r7, #22] 8007b04: 68fb ldr r3, [r7, #12] 8007b06: 681b ldr r3, [r3, #0] 8007b08: 461a mov r2, r3 8007b0a: 68bb ldr r3, [r7, #8] 8007b0c: 781b ldrb r3, [r3, #0] 8007b0e: 009b lsls r3, r3, #2 8007b10: 441a add r2, r3 8007b12: 8afb ldrh r3, [r7, #22] 8007b14: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007b18: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8007b1c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8007b20: f043 0380 orr.w r3, r3, #128 @ 0x80 8007b24: b29b uxth r3, r3 8007b26: 8013 strh r3, [r2, #0] 8007b28: e2da b.n 80080e0 } } else /* Transfer is not yet Done */ { /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 8007b2a: 88fb ldrh r3, [r7, #6] 8007b2c: f403 4380 and.w r3, r3, #16384 @ 0x4000 8007b30: 2b00 cmp r3, #0 8007b32: d021 beq.n 8007b78 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 8007b34: 68fb ldr r3, [r7, #12] 8007b36: 681b ldr r3, [r3, #0] 8007b38: 461a mov r2, r3 8007b3a: 68bb ldr r3, [r7, #8] 8007b3c: 781b ldrb r3, [r3, #0] 8007b3e: 009b lsls r3, r3, #2 8007b40: 4413 add r3, r2 8007b42: 881b ldrh r3, [r3, #0] 8007b44: b29b uxth r3, r3 8007b46: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8007b4a: f023 0370 bic.w r3, r3, #112 @ 0x70 8007b4e: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 8007b52: 68fb ldr r3, [r7, #12] 8007b54: 681b ldr r3, [r3, #0] 8007b56: 461a mov r2, r3 8007b58: 68bb ldr r3, [r7, #8] 8007b5a: 781b ldrb r3, [r3, #0] 8007b5c: 009b lsls r3, r3, #2 8007b5e: 441a add r2, r3 8007b60: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8007b64: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007b68: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8007b6c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8007b70: f043 0380 orr.w r3, r3, #128 @ 0x80 8007b74: b29b uxth r3, r3 8007b76: 8013 strh r3, [r2, #0] } /* Still there is data to Fill in the next Buffer */ if (ep->xfer_fill_db == 1U) 8007b78: 68bb ldr r3, [r7, #8] 8007b7a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8007b7e: 2b01 cmp r3, #1 8007b80: f040 82ae bne.w 80080e0 { ep->xfer_buff += TxPctSize; 8007b84: 68bb ldr r3, [r7, #8] 8007b86: 695a ldr r2, [r3, #20] 8007b88: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007b8c: 441a add r2, r3 8007b8e: 68bb ldr r3, [r7, #8] 8007b90: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 8007b92: 68bb ldr r3, [r7, #8] 8007b94: 69da ldr r2, [r3, #28] 8007b96: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007b9a: 441a add r2, r3 8007b9c: 68bb ldr r3, [r7, #8] 8007b9e: 61da str r2, [r3, #28] /* Calculate the len of the new buffer to fill */ if (ep->xfer_len_db >= ep->maxpacket) 8007ba0: 68bb ldr r3, [r7, #8] 8007ba2: 6a1a ldr r2, [r3, #32] 8007ba4: 68bb ldr r3, [r7, #8] 8007ba6: 691b ldr r3, [r3, #16] 8007ba8: 429a cmp r2, r3 8007baa: d30b bcc.n 8007bc4 { len = ep->maxpacket; 8007bac: 68bb ldr r3, [r7, #8] 8007bae: 691b ldr r3, [r3, #16] 8007bb0: f8c7 308c str.w r3, [r7, #140] @ 0x8c ep->xfer_len_db -= len; 8007bb4: 68bb ldr r3, [r7, #8] 8007bb6: 6a1a ldr r2, [r3, #32] 8007bb8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007bbc: 1ad2 subs r2, r2, r3 8007bbe: 68bb ldr r3, [r7, #8] 8007bc0: 621a str r2, [r3, #32] 8007bc2: e017 b.n 8007bf4 } else if (ep->xfer_len_db == 0U) 8007bc4: 68bb ldr r3, [r7, #8] 8007bc6: 6a1b ldr r3, [r3, #32] 8007bc8: 2b00 cmp r3, #0 8007bca: d108 bne.n 8007bde { len = TxPctSize; 8007bcc: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007bd0: f8c7 308c str.w r3, [r7, #140] @ 0x8c ep->xfer_fill_db = 0U; 8007bd4: 68bb ldr r3, [r7, #8] 8007bd6: 2200 movs r2, #0 8007bd8: f883 2024 strb.w r2, [r3, #36] @ 0x24 8007bdc: e00a b.n 8007bf4 } else { ep->xfer_fill_db = 0U; 8007bde: 68bb ldr r3, [r7, #8] 8007be0: 2200 movs r2, #0 8007be2: f883 2024 strb.w r2, [r3, #36] @ 0x24 len = ep->xfer_len_db; 8007be6: 68bb ldr r3, [r7, #8] 8007be8: 6a1b ldr r3, [r3, #32] 8007bea: f8c7 308c str.w r3, [r7, #140] @ 0x8c ep->xfer_len_db = 0U; 8007bee: 68bb ldr r3, [r7, #8] 8007bf0: 2200 movs r2, #0 8007bf2: 621a str r2, [r3, #32] } /* Write remaining Data to Buffer */ /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); 8007bf4: 68bb ldr r3, [r7, #8] 8007bf6: 785b ldrb r3, [r3, #1] 8007bf8: 2b00 cmp r3, #0 8007bfa: d165 bne.n 8007cc8 8007bfc: 68fb ldr r3, [r7, #12] 8007bfe: 681b ldr r3, [r3, #0] 8007c00: 63fb str r3, [r7, #60] @ 0x3c 8007c02: 68fb ldr r3, [r7, #12] 8007c04: 681b ldr r3, [r3, #0] 8007c06: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007c0a: b29b uxth r3, r3 8007c0c: 461a mov r2, r3 8007c0e: 6bfb ldr r3, [r7, #60] @ 0x3c 8007c10: 4413 add r3, r2 8007c12: 63fb str r3, [r7, #60] @ 0x3c 8007c14: 68bb ldr r3, [r7, #8] 8007c16: 781b ldrb r3, [r3, #0] 8007c18: 011a lsls r2, r3, #4 8007c1a: 6bfb ldr r3, [r7, #60] @ 0x3c 8007c1c: 4413 add r3, r2 8007c1e: f203 4304 addw r3, r3, #1028 @ 0x404 8007c22: 63bb str r3, [r7, #56] @ 0x38 8007c24: 6bbb ldr r3, [r7, #56] @ 0x38 8007c26: 881b ldrh r3, [r3, #0] 8007c28: b29b uxth r3, r3 8007c2a: f3c3 0309 ubfx r3, r3, #0, #10 8007c2e: b29a uxth r2, r3 8007c30: 6bbb ldr r3, [r7, #56] @ 0x38 8007c32: 801a strh r2, [r3, #0] 8007c34: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007c38: 2b3e cmp r3, #62 @ 0x3e 8007c3a: d91d bls.n 8007c78 8007c3c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007c40: 095b lsrs r3, r3, #5 8007c42: 64bb str r3, [r7, #72] @ 0x48 8007c44: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007c48: f003 031f and.w r3, r3, #31 8007c4c: 2b00 cmp r3, #0 8007c4e: d102 bne.n 8007c56 8007c50: 6cbb ldr r3, [r7, #72] @ 0x48 8007c52: 3b01 subs r3, #1 8007c54: 64bb str r3, [r7, #72] @ 0x48 8007c56: 6bbb ldr r3, [r7, #56] @ 0x38 8007c58: 881b ldrh r3, [r3, #0] 8007c5a: b29a uxth r2, r3 8007c5c: 6cbb ldr r3, [r7, #72] @ 0x48 8007c5e: b29b uxth r3, r3 8007c60: 029b lsls r3, r3, #10 8007c62: b29b uxth r3, r3 8007c64: 4313 orrs r3, r2 8007c66: b29b uxth r3, r3 8007c68: ea6f 4343 mvn.w r3, r3, lsl #17 8007c6c: ea6f 4353 mvn.w r3, r3, lsr #17 8007c70: b29a uxth r2, r3 8007c72: 6bbb ldr r3, [r7, #56] @ 0x38 8007c74: 801a strh r2, [r3, #0] 8007c76: e044 b.n 8007d02 8007c78: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007c7c: 2b00 cmp r3, #0 8007c7e: d10a bne.n 8007c96 8007c80: 6bbb ldr r3, [r7, #56] @ 0x38 8007c82: 881b ldrh r3, [r3, #0] 8007c84: b29b uxth r3, r3 8007c86: ea6f 4343 mvn.w r3, r3, lsl #17 8007c8a: ea6f 4353 mvn.w r3, r3, lsr #17 8007c8e: b29a uxth r2, r3 8007c90: 6bbb ldr r3, [r7, #56] @ 0x38 8007c92: 801a strh r2, [r3, #0] 8007c94: e035 b.n 8007d02 8007c96: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007c9a: 085b lsrs r3, r3, #1 8007c9c: 64bb str r3, [r7, #72] @ 0x48 8007c9e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007ca2: f003 0301 and.w r3, r3, #1 8007ca6: 2b00 cmp r3, #0 8007ca8: d002 beq.n 8007cb0 8007caa: 6cbb ldr r3, [r7, #72] @ 0x48 8007cac: 3301 adds r3, #1 8007cae: 64bb str r3, [r7, #72] @ 0x48 8007cb0: 6bbb ldr r3, [r7, #56] @ 0x38 8007cb2: 881b ldrh r3, [r3, #0] 8007cb4: b29a uxth r2, r3 8007cb6: 6cbb ldr r3, [r7, #72] @ 0x48 8007cb8: b29b uxth r3, r3 8007cba: 029b lsls r3, r3, #10 8007cbc: b29b uxth r3, r3 8007cbe: 4313 orrs r3, r2 8007cc0: b29a uxth r2, r3 8007cc2: 6bbb ldr r3, [r7, #56] @ 0x38 8007cc4: 801a strh r2, [r3, #0] 8007cc6: e01c b.n 8007d02 8007cc8: 68bb ldr r3, [r7, #8] 8007cca: 785b ldrb r3, [r3, #1] 8007ccc: 2b01 cmp r3, #1 8007cce: d118 bne.n 8007d02 8007cd0: 68fb ldr r3, [r7, #12] 8007cd2: 681b ldr r3, [r3, #0] 8007cd4: 647b str r3, [r7, #68] @ 0x44 8007cd6: 68fb ldr r3, [r7, #12] 8007cd8: 681b ldr r3, [r3, #0] 8007cda: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007cde: b29b uxth r3, r3 8007ce0: 461a mov r2, r3 8007ce2: 6c7b ldr r3, [r7, #68] @ 0x44 8007ce4: 4413 add r3, r2 8007ce6: 647b str r3, [r7, #68] @ 0x44 8007ce8: 68bb ldr r3, [r7, #8] 8007cea: 781b ldrb r3, [r3, #0] 8007cec: 011a lsls r2, r3, #4 8007cee: 6c7b ldr r3, [r7, #68] @ 0x44 8007cf0: 4413 add r3, r2 8007cf2: f203 4304 addw r3, r3, #1028 @ 0x404 8007cf6: 643b str r3, [r7, #64] @ 0x40 8007cf8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007cfc: b29a uxth r2, r3 8007cfe: 6c3b ldr r3, [r7, #64] @ 0x40 8007d00: 801a strh r2, [r3, #0] /* Copy user buffer to USB PMA */ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); 8007d02: 68fb ldr r3, [r7, #12] 8007d04: 6818 ldr r0, [r3, #0] 8007d06: 68bb ldr r3, [r7, #8] 8007d08: 6959 ldr r1, [r3, #20] 8007d0a: 68bb ldr r3, [r7, #8] 8007d0c: 891a ldrh r2, [r3, #8] 8007d0e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007d12: b29b uxth r3, r3 8007d14: f004 faaf bl 800c276 8007d18: e1e2 b.n 80080e0 } } else /* Data Buffer1 ACK received */ { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 8007d1a: 68fb ldr r3, [r7, #12] 8007d1c: 681b ldr r3, [r3, #0] 8007d1e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007d22: b29b uxth r3, r3 8007d24: 461a mov r2, r3 8007d26: 68bb ldr r3, [r7, #8] 8007d28: 781b ldrb r3, [r3, #0] 8007d2a: 00db lsls r3, r3, #3 8007d2c: 4413 add r3, r2 8007d2e: 3306 adds r3, #6 8007d30: 005b lsls r3, r3, #1 8007d32: 68fa ldr r2, [r7, #12] 8007d34: 6812 ldr r2, [r2, #0] 8007d36: 4413 add r3, r2 8007d38: f503 6380 add.w r3, r3, #1024 @ 0x400 8007d3c: 881b ldrh r3, [r3, #0] 8007d3e: f3c3 0309 ubfx r3, r3, #0, #10 8007d42: f8a7 3086 strh.w r3, [r7, #134] @ 0x86 if (ep->xfer_len >= TxPctSize) 8007d46: 68bb ldr r3, [r7, #8] 8007d48: 699a ldr r2, [r3, #24] 8007d4a: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007d4e: 429a cmp r2, r3 8007d50: d307 bcc.n 8007d62 { ep->xfer_len -= TxPctSize; 8007d52: 68bb ldr r3, [r7, #8] 8007d54: 699a ldr r2, [r3, #24] 8007d56: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007d5a: 1ad2 subs r2, r2, r3 8007d5c: 68bb ldr r3, [r7, #8] 8007d5e: 619a str r2, [r3, #24] 8007d60: e002 b.n 8007d68 } else { ep->xfer_len = 0U; 8007d62: 68bb ldr r3, [r7, #8] 8007d64: 2200 movs r2, #0 8007d66: 619a str r2, [r3, #24] } /* Transfer is completed */ if (ep->xfer_len == 0U) 8007d68: 68bb ldr r3, [r7, #8] 8007d6a: 699b ldr r3, [r3, #24] 8007d6c: 2b00 cmp r3, #0 8007d6e: f040 80c0 bne.w 8007ef2 { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 8007d72: 68bb ldr r3, [r7, #8] 8007d74: 785b ldrb r3, [r3, #1] 8007d76: 2b00 cmp r3, #0 8007d78: d126 bne.n 8007dc8 8007d7a: 68fb ldr r3, [r7, #12] 8007d7c: 681b ldr r3, [r3, #0] 8007d7e: 67fb str r3, [r7, #124] @ 0x7c 8007d80: 68fb ldr r3, [r7, #12] 8007d82: 681b ldr r3, [r3, #0] 8007d84: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007d88: b29b uxth r3, r3 8007d8a: 461a mov r2, r3 8007d8c: 6ffb ldr r3, [r7, #124] @ 0x7c 8007d8e: 4413 add r3, r2 8007d90: 67fb str r3, [r7, #124] @ 0x7c 8007d92: 68bb ldr r3, [r7, #8] 8007d94: 781b ldrb r3, [r3, #0] 8007d96: 011a lsls r2, r3, #4 8007d98: 6ffb ldr r3, [r7, #124] @ 0x7c 8007d9a: 4413 add r3, r2 8007d9c: f203 4304 addw r3, r3, #1028 @ 0x404 8007da0: 67bb str r3, [r7, #120] @ 0x78 8007da2: 6fbb ldr r3, [r7, #120] @ 0x78 8007da4: 881b ldrh r3, [r3, #0] 8007da6: b29b uxth r3, r3 8007da8: f3c3 0309 ubfx r3, r3, #0, #10 8007dac: b29a uxth r2, r3 8007dae: 6fbb ldr r3, [r7, #120] @ 0x78 8007db0: 801a strh r2, [r3, #0] 8007db2: 6fbb ldr r3, [r7, #120] @ 0x78 8007db4: 881b ldrh r3, [r3, #0] 8007db6: b29b uxth r3, r3 8007db8: ea6f 4343 mvn.w r3, r3, lsl #17 8007dbc: ea6f 4353 mvn.w r3, r3, lsr #17 8007dc0: b29a uxth r2, r3 8007dc2: 6fbb ldr r3, [r7, #120] @ 0x78 8007dc4: 801a strh r2, [r3, #0] 8007dc6: e01a b.n 8007dfe 8007dc8: 68bb ldr r3, [r7, #8] 8007dca: 785b ldrb r3, [r3, #1] 8007dcc: 2b01 cmp r3, #1 8007dce: d116 bne.n 8007dfe 8007dd0: 68fb ldr r3, [r7, #12] 8007dd2: 681b ldr r3, [r3, #0] 8007dd4: 667b str r3, [r7, #100] @ 0x64 8007dd6: 68fb ldr r3, [r7, #12] 8007dd8: 681b ldr r3, [r3, #0] 8007dda: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007dde: b29b uxth r3, r3 8007de0: 461a mov r2, r3 8007de2: 6e7b ldr r3, [r7, #100] @ 0x64 8007de4: 4413 add r3, r2 8007de6: 667b str r3, [r7, #100] @ 0x64 8007de8: 68bb ldr r3, [r7, #8] 8007dea: 781b ldrb r3, [r3, #0] 8007dec: 011a lsls r2, r3, #4 8007dee: 6e7b ldr r3, [r7, #100] @ 0x64 8007df0: 4413 add r3, r2 8007df2: f203 4304 addw r3, r3, #1028 @ 0x404 8007df6: 663b str r3, [r7, #96] @ 0x60 8007df8: 6e3b ldr r3, [r7, #96] @ 0x60 8007dfa: 2200 movs r2, #0 8007dfc: 801a strh r2, [r3, #0] PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 8007dfe: 68fb ldr r3, [r7, #12] 8007e00: 681b ldr r3, [r3, #0] 8007e02: 677b str r3, [r7, #116] @ 0x74 8007e04: 68bb ldr r3, [r7, #8] 8007e06: 785b ldrb r3, [r3, #1] 8007e08: 2b00 cmp r3, #0 8007e0a: d12b bne.n 8007e64 8007e0c: 68fb ldr r3, [r7, #12] 8007e0e: 681b ldr r3, [r3, #0] 8007e10: 66fb str r3, [r7, #108] @ 0x6c 8007e12: 68fb ldr r3, [r7, #12] 8007e14: 681b ldr r3, [r3, #0] 8007e16: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007e1a: b29b uxth r3, r3 8007e1c: 461a mov r2, r3 8007e1e: 6efb ldr r3, [r7, #108] @ 0x6c 8007e20: 4413 add r3, r2 8007e22: 66fb str r3, [r7, #108] @ 0x6c 8007e24: 68bb ldr r3, [r7, #8] 8007e26: 781b ldrb r3, [r3, #0] 8007e28: 011a lsls r2, r3, #4 8007e2a: 6efb ldr r3, [r7, #108] @ 0x6c 8007e2c: 4413 add r3, r2 8007e2e: f203 430c addw r3, r3, #1036 @ 0x40c 8007e32: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8007e36: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8007e3a: 881b ldrh r3, [r3, #0] 8007e3c: b29b uxth r3, r3 8007e3e: f3c3 0309 ubfx r3, r3, #0, #10 8007e42: b29a uxth r2, r3 8007e44: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8007e48: 801a strh r2, [r3, #0] 8007e4a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8007e4e: 881b ldrh r3, [r3, #0] 8007e50: b29b uxth r3, r3 8007e52: ea6f 4343 mvn.w r3, r3, lsl #17 8007e56: ea6f 4353 mvn.w r3, r3, lsr #17 8007e5a: b29a uxth r2, r3 8007e5c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8007e60: 801a strh r2, [r3, #0] 8007e62: e017 b.n 8007e94 8007e64: 68bb ldr r3, [r7, #8] 8007e66: 785b ldrb r3, [r3, #1] 8007e68: 2b01 cmp r3, #1 8007e6a: d113 bne.n 8007e94 8007e6c: 68fb ldr r3, [r7, #12] 8007e6e: 681b ldr r3, [r3, #0] 8007e70: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007e74: b29b uxth r3, r3 8007e76: 461a mov r2, r3 8007e78: 6f7b ldr r3, [r7, #116] @ 0x74 8007e7a: 4413 add r3, r2 8007e7c: 677b str r3, [r7, #116] @ 0x74 8007e7e: 68bb ldr r3, [r7, #8] 8007e80: 781b ldrb r3, [r3, #0] 8007e82: 011a lsls r2, r3, #4 8007e84: 6f7b ldr r3, [r7, #116] @ 0x74 8007e86: 4413 add r3, r2 8007e88: f203 430c addw r3, r3, #1036 @ 0x40c 8007e8c: 673b str r3, [r7, #112] @ 0x70 8007e8e: 6f3b ldr r3, [r7, #112] @ 0x70 8007e90: 2200 movs r2, #0 8007e92: 801a strh r2, [r3, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 8007e94: 68bb ldr r3, [r7, #8] 8007e96: 781b ldrb r3, [r3, #0] 8007e98: 4619 mov r1, r3 8007e9a: 68f8 ldr r0, [r7, #12] 8007e9c: f006 f8af bl 800dffe #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) 8007ea0: 88fb ldrh r3, [r7, #6] 8007ea2: f403 4380 and.w r3, r3, #16384 @ 0x4000 8007ea6: 2b00 cmp r3, #0 8007ea8: f040 811a bne.w 80080e0 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 8007eac: 68fb ldr r3, [r7, #12] 8007eae: 681b ldr r3, [r3, #0] 8007eb0: 461a mov r2, r3 8007eb2: 68bb ldr r3, [r7, #8] 8007eb4: 781b ldrb r3, [r3, #0] 8007eb6: 009b lsls r3, r3, #2 8007eb8: 4413 add r3, r2 8007eba: 881b ldrh r3, [r3, #0] 8007ebc: b29b uxth r3, r3 8007ebe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8007ec2: f023 0370 bic.w r3, r3, #112 @ 0x70 8007ec6: f8a7 3088 strh.w r3, [r7, #136] @ 0x88 8007eca: 68fb ldr r3, [r7, #12] 8007ecc: 681b ldr r3, [r3, #0] 8007ece: 461a mov r2, r3 8007ed0: 68bb ldr r3, [r7, #8] 8007ed2: 781b ldrb r3, [r3, #0] 8007ed4: 009b lsls r3, r3, #2 8007ed6: 441a add r2, r3 8007ed8: f8b7 3088 ldrh.w r3, [r7, #136] @ 0x88 8007edc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007ee0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8007ee4: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8007ee8: f043 0380 orr.w r3, r3, #128 @ 0x80 8007eec: b29b uxth r3, r3 8007eee: 8013 strh r3, [r2, #0] 8007ef0: e0f6 b.n 80080e0 } } else /* Transfer is not yet Done */ { /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) 8007ef2: 88fb ldrh r3, [r7, #6] 8007ef4: f403 4380 and.w r3, r3, #16384 @ 0x4000 8007ef8: 2b00 cmp r3, #0 8007efa: d121 bne.n 8007f40 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 8007efc: 68fb ldr r3, [r7, #12] 8007efe: 681b ldr r3, [r3, #0] 8007f00: 461a mov r2, r3 8007f02: 68bb ldr r3, [r7, #8] 8007f04: 781b ldrb r3, [r3, #0] 8007f06: 009b lsls r3, r3, #2 8007f08: 4413 add r3, r2 8007f0a: 881b ldrh r3, [r3, #0] 8007f0c: b29b uxth r3, r3 8007f0e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8007f12: f023 0370 bic.w r3, r3, #112 @ 0x70 8007f16: f8a7 304e strh.w r3, [r7, #78] @ 0x4e 8007f1a: 68fb ldr r3, [r7, #12] 8007f1c: 681b ldr r3, [r3, #0] 8007f1e: 461a mov r2, r3 8007f20: 68bb ldr r3, [r7, #8] 8007f22: 781b ldrb r3, [r3, #0] 8007f24: 009b lsls r3, r3, #2 8007f26: 441a add r2, r3 8007f28: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8007f2c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8007f30: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8007f34: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8007f38: f043 0380 orr.w r3, r3, #128 @ 0x80 8007f3c: b29b uxth r3, r3 8007f3e: 8013 strh r3, [r2, #0] } /* Still there is data to Fill in the next Buffer */ if (ep->xfer_fill_db == 1U) 8007f40: 68bb ldr r3, [r7, #8] 8007f42: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8007f46: 2b01 cmp r3, #1 8007f48: f040 80ca bne.w 80080e0 { ep->xfer_buff += TxPctSize; 8007f4c: 68bb ldr r3, [r7, #8] 8007f4e: 695a ldr r2, [r3, #20] 8007f50: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007f54: 441a add r2, r3 8007f56: 68bb ldr r3, [r7, #8] 8007f58: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 8007f5a: 68bb ldr r3, [r7, #8] 8007f5c: 69da ldr r2, [r3, #28] 8007f5e: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007f62: 441a add r2, r3 8007f64: 68bb ldr r3, [r7, #8] 8007f66: 61da str r2, [r3, #28] /* Calculate the len of the new buffer to fill */ if (ep->xfer_len_db >= ep->maxpacket) 8007f68: 68bb ldr r3, [r7, #8] 8007f6a: 6a1a ldr r2, [r3, #32] 8007f6c: 68bb ldr r3, [r7, #8] 8007f6e: 691b ldr r3, [r3, #16] 8007f70: 429a cmp r2, r3 8007f72: d30b bcc.n 8007f8c { len = ep->maxpacket; 8007f74: 68bb ldr r3, [r7, #8] 8007f76: 691b ldr r3, [r3, #16] 8007f78: f8c7 308c str.w r3, [r7, #140] @ 0x8c ep->xfer_len_db -= len; 8007f7c: 68bb ldr r3, [r7, #8] 8007f7e: 6a1a ldr r2, [r3, #32] 8007f80: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8007f84: 1ad2 subs r2, r2, r3 8007f86: 68bb ldr r3, [r7, #8] 8007f88: 621a str r2, [r3, #32] 8007f8a: e017 b.n 8007fbc } else if (ep->xfer_len_db == 0U) 8007f8c: 68bb ldr r3, [r7, #8] 8007f8e: 6a1b ldr r3, [r3, #32] 8007f90: 2b00 cmp r3, #0 8007f92: d108 bne.n 8007fa6 { len = TxPctSize; 8007f94: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 8007f98: f8c7 308c str.w r3, [r7, #140] @ 0x8c ep->xfer_fill_db = 0U; 8007f9c: 68bb ldr r3, [r7, #8] 8007f9e: 2200 movs r2, #0 8007fa0: f883 2024 strb.w r2, [r3, #36] @ 0x24 8007fa4: e00a b.n 8007fbc } else { len = ep->xfer_len_db; 8007fa6: 68bb ldr r3, [r7, #8] 8007fa8: 6a1b ldr r3, [r3, #32] 8007faa: f8c7 308c str.w r3, [r7, #140] @ 0x8c ep->xfer_len_db = 0U; 8007fae: 68bb ldr r3, [r7, #8] 8007fb0: 2200 movs r2, #0 8007fb2: 621a str r2, [r3, #32] ep->xfer_fill_db = 0; 8007fb4: 68bb ldr r3, [r7, #8] 8007fb6: 2200 movs r2, #0 8007fb8: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); 8007fbc: 68fb ldr r3, [r7, #12] 8007fbe: 681b ldr r3, [r3, #0] 8007fc0: 657b str r3, [r7, #84] @ 0x54 8007fc2: 68bb ldr r3, [r7, #8] 8007fc4: 785b ldrb r3, [r3, #1] 8007fc6: 2b00 cmp r3, #0 8007fc8: d165 bne.n 8008096 8007fca: 68fb ldr r3, [r7, #12] 8007fcc: 681b ldr r3, [r3, #0] 8007fce: 65fb str r3, [r7, #92] @ 0x5c 8007fd0: 68fb ldr r3, [r7, #12] 8007fd2: 681b ldr r3, [r3, #0] 8007fd4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8007fd8: b29b uxth r3, r3 8007fda: 461a mov r2, r3 8007fdc: 6dfb ldr r3, [r7, #92] @ 0x5c 8007fde: 4413 add r3, r2 8007fe0: 65fb str r3, [r7, #92] @ 0x5c 8007fe2: 68bb ldr r3, [r7, #8] 8007fe4: 781b ldrb r3, [r3, #0] 8007fe6: 011a lsls r2, r3, #4 8007fe8: 6dfb ldr r3, [r7, #92] @ 0x5c 8007fea: 4413 add r3, r2 8007fec: f203 430c addw r3, r3, #1036 @ 0x40c 8007ff0: 65bb str r3, [r7, #88] @ 0x58 8007ff2: 6dbb ldr r3, [r7, #88] @ 0x58 8007ff4: 881b ldrh r3, [r3, #0] 8007ff6: b29b uxth r3, r3 8007ff8: f3c3 0309 ubfx r3, r3, #0, #10 8007ffc: b29a uxth r2, r3 8007ffe: 6dbb ldr r3, [r7, #88] @ 0x58 8008000: 801a strh r2, [r3, #0] 8008002: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8008006: 2b3e cmp r3, #62 @ 0x3e 8008008: d91d bls.n 8008046 800800a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800800e: 095b lsrs r3, r3, #5 8008010: 66bb str r3, [r7, #104] @ 0x68 8008012: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8008016: f003 031f and.w r3, r3, #31 800801a: 2b00 cmp r3, #0 800801c: d102 bne.n 8008024 800801e: 6ebb ldr r3, [r7, #104] @ 0x68 8008020: 3b01 subs r3, #1 8008022: 66bb str r3, [r7, #104] @ 0x68 8008024: 6dbb ldr r3, [r7, #88] @ 0x58 8008026: 881b ldrh r3, [r3, #0] 8008028: b29a uxth r2, r3 800802a: 6ebb ldr r3, [r7, #104] @ 0x68 800802c: b29b uxth r3, r3 800802e: 029b lsls r3, r3, #10 8008030: b29b uxth r3, r3 8008032: 4313 orrs r3, r2 8008034: b29b uxth r3, r3 8008036: ea6f 4343 mvn.w r3, r3, lsl #17 800803a: ea6f 4353 mvn.w r3, r3, lsr #17 800803e: b29a uxth r2, r3 8008040: 6dbb ldr r3, [r7, #88] @ 0x58 8008042: 801a strh r2, [r3, #0] 8008044: e041 b.n 80080ca 8008046: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800804a: 2b00 cmp r3, #0 800804c: d10a bne.n 8008064 800804e: 6dbb ldr r3, [r7, #88] @ 0x58 8008050: 881b ldrh r3, [r3, #0] 8008052: b29b uxth r3, r3 8008054: ea6f 4343 mvn.w r3, r3, lsl #17 8008058: ea6f 4353 mvn.w r3, r3, lsr #17 800805c: b29a uxth r2, r3 800805e: 6dbb ldr r3, [r7, #88] @ 0x58 8008060: 801a strh r2, [r3, #0] 8008062: e032 b.n 80080ca 8008064: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8008068: 085b lsrs r3, r3, #1 800806a: 66bb str r3, [r7, #104] @ 0x68 800806c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8008070: f003 0301 and.w r3, r3, #1 8008074: 2b00 cmp r3, #0 8008076: d002 beq.n 800807e 8008078: 6ebb ldr r3, [r7, #104] @ 0x68 800807a: 3301 adds r3, #1 800807c: 66bb str r3, [r7, #104] @ 0x68 800807e: 6dbb ldr r3, [r7, #88] @ 0x58 8008080: 881b ldrh r3, [r3, #0] 8008082: b29a uxth r2, r3 8008084: 6ebb ldr r3, [r7, #104] @ 0x68 8008086: b29b uxth r3, r3 8008088: 029b lsls r3, r3, #10 800808a: b29b uxth r3, r3 800808c: 4313 orrs r3, r2 800808e: b29a uxth r2, r3 8008090: 6dbb ldr r3, [r7, #88] @ 0x58 8008092: 801a strh r2, [r3, #0] 8008094: e019 b.n 80080ca 8008096: 68bb ldr r3, [r7, #8] 8008098: 785b ldrb r3, [r3, #1] 800809a: 2b01 cmp r3, #1 800809c: d115 bne.n 80080ca 800809e: 68fb ldr r3, [r7, #12] 80080a0: 681b ldr r3, [r3, #0] 80080a2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80080a6: b29b uxth r3, r3 80080a8: 461a mov r2, r3 80080aa: 6d7b ldr r3, [r7, #84] @ 0x54 80080ac: 4413 add r3, r2 80080ae: 657b str r3, [r7, #84] @ 0x54 80080b0: 68bb ldr r3, [r7, #8] 80080b2: 781b ldrb r3, [r3, #0] 80080b4: 011a lsls r2, r3, #4 80080b6: 6d7b ldr r3, [r7, #84] @ 0x54 80080b8: 4413 add r3, r2 80080ba: f203 430c addw r3, r3, #1036 @ 0x40c 80080be: 653b str r3, [r7, #80] @ 0x50 80080c0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80080c4: b29a uxth r2, r3 80080c6: 6d3b ldr r3, [r7, #80] @ 0x50 80080c8: 801a strh r2, [r3, #0] /* Copy the user buffer to USB PMA */ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); 80080ca: 68fb ldr r3, [r7, #12] 80080cc: 6818 ldr r0, [r3, #0] 80080ce: 68bb ldr r3, [r7, #8] 80080d0: 6959 ldr r1, [r3, #20] 80080d2: 68bb ldr r3, [r7, #8] 80080d4: 895a ldrh r2, [r3, #10] 80080d6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80080da: b29b uxth r3, r3 80080dc: f004 f8cb bl 800c276 } } } /*enable endpoint IN*/ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); 80080e0: 68fb ldr r3, [r7, #12] 80080e2: 681b ldr r3, [r3, #0] 80080e4: 461a mov r2, r3 80080e6: 68bb ldr r3, [r7, #8] 80080e8: 781b ldrb r3, [r3, #0] 80080ea: 009b lsls r3, r3, #2 80080ec: 4413 add r3, r2 80080ee: 881b ldrh r3, [r3, #0] 80080f0: b29b uxth r3, r3 80080f2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80080f6: f023 0340 bic.w r3, r3, #64 @ 0x40 80080fa: 82bb strh r3, [r7, #20] 80080fc: 8abb ldrh r3, [r7, #20] 80080fe: f083 0310 eor.w r3, r3, #16 8008102: 82bb strh r3, [r7, #20] 8008104: 8abb ldrh r3, [r7, #20] 8008106: f083 0320 eor.w r3, r3, #32 800810a: 82bb strh r3, [r7, #20] 800810c: 68fb ldr r3, [r7, #12] 800810e: 681b ldr r3, [r3, #0] 8008110: 461a mov r2, r3 8008112: 68bb ldr r3, [r7, #8] 8008114: 781b ldrb r3, [r3, #0] 8008116: 009b lsls r3, r3, #2 8008118: 441a add r2, r3 800811a: 8abb ldrh r3, [r7, #20] 800811c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8008120: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8008124: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8008128: f043 0380 orr.w r3, r3, #128 @ 0x80 800812c: b29b uxth r3, r3 800812e: 8013 strh r3, [r2, #0] return HAL_OK; 8008130: 2300 movs r3, #0 } 8008132: 4618 mov r0, r3 8008134: 3790 adds r7, #144 @ 0x90 8008136: 46bd mov sp, r7 8008138: bd80 pop {r7, pc} 0800813a : * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) { 800813a: b480 push {r7} 800813c: b087 sub sp, #28 800813e: af00 add r7, sp, #0 8008140: 60f8 str r0, [r7, #12] 8008142: 607b str r3, [r7, #4] 8008144: 460b mov r3, r1 8008146: 817b strh r3, [r7, #10] 8008148: 4613 mov r3, r2 800814a: 813b strh r3, [r7, #8] PCD_EPTypeDef *ep; /* initialize ep structure*/ if ((0x80U & ep_addr) == 0x80U) 800814c: 897b ldrh r3, [r7, #10] 800814e: f003 0380 and.w r3, r3, #128 @ 0x80 8008152: b29b uxth r3, r3 8008154: 2b00 cmp r3, #0 8008156: d00b beq.n 8008170 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8008158: 897b ldrh r3, [r7, #10] 800815a: f003 0207 and.w r2, r3, #7 800815e: 4613 mov r3, r2 8008160: 009b lsls r3, r3, #2 8008162: 4413 add r3, r2 8008164: 00db lsls r3, r3, #3 8008166: 3310 adds r3, #16 8008168: 68fa ldr r2, [r7, #12] 800816a: 4413 add r3, r2 800816c: 617b str r3, [r7, #20] 800816e: e009 b.n 8008184 } else { ep = &hpcd->OUT_ep[ep_addr]; 8008170: 897a ldrh r2, [r7, #10] 8008172: 4613 mov r3, r2 8008174: 009b lsls r3, r3, #2 8008176: 4413 add r3, r2 8008178: 00db lsls r3, r3, #3 800817a: f503 73a8 add.w r3, r3, #336 @ 0x150 800817e: 68fa ldr r2, [r7, #12] 8008180: 4413 add r3, r2 8008182: 617b str r3, [r7, #20] } /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) 8008184: 893b ldrh r3, [r7, #8] 8008186: 2b00 cmp r3, #0 8008188: d107 bne.n 800819a { /* Single Buffer */ ep->doublebuffer = 0U; 800818a: 697b ldr r3, [r7, #20] 800818c: 2200 movs r2, #0 800818e: 731a strb r2, [r3, #12] /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; 8008190: 687b ldr r3, [r7, #4] 8008192: b29a uxth r2, r3 8008194: 697b ldr r3, [r7, #20] 8008196: 80da strh r2, [r3, #6] 8008198: e00b b.n 80081b2 } #if (USE_USB_DOUBLE_BUFFER == 1U) else /* USB_DBL_BUF */ { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; 800819a: 697b ldr r3, [r7, #20] 800819c: 2201 movs r2, #1 800819e: 731a strb r2, [r3, #12] /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); 80081a0: 687b ldr r3, [r7, #4] 80081a2: b29a uxth r2, r3 80081a4: 697b ldr r3, [r7, #20] 80081a6: 811a strh r2, [r3, #8] ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); 80081a8: 687b ldr r3, [r7, #4] 80081aa: 0c1b lsrs r3, r3, #16 80081ac: b29a uxth r2, r3 80081ae: 697b ldr r3, [r7, #20] 80081b0: 815a strh r2, [r3, #10] } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; 80081b2: 2300 movs r3, #0 } 80081b4: 4618 mov r0, r3 80081b6: 371c adds r7, #28 80081b8: 46bd mov sp, r7 80081ba: bc80 pop {r7} 80081bc: 4770 bx lr ... 080081c0 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80081c0: b580 push {r7, lr} 80081c2: b086 sub sp, #24 80081c4: af00 add r7, sp, #0 80081c6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80081c8: 687b ldr r3, [r7, #4] 80081ca: 2b00 cmp r3, #0 80081cc: d101 bne.n 80081d2 { return HAL_ERROR; 80081ce: 2301 movs r3, #1 80081d0: e272 b.n 80086b8 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80081d2: 687b ldr r3, [r7, #4] 80081d4: 681b ldr r3, [r3, #0] 80081d6: f003 0301 and.w r3, r3, #1 80081da: 2b00 cmp r3, #0 80081dc: f000 8087 beq.w 80082ee { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80081e0: 4b92 ldr r3, [pc, #584] @ (800842c ) 80081e2: 685b ldr r3, [r3, #4] 80081e4: f003 030c and.w r3, r3, #12 80081e8: 2b04 cmp r3, #4 80081ea: d00c beq.n 8008206 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80081ec: 4b8f ldr r3, [pc, #572] @ (800842c ) 80081ee: 685b ldr r3, [r3, #4] 80081f0: f003 030c and.w r3, r3, #12 80081f4: 2b08 cmp r3, #8 80081f6: d112 bne.n 800821e 80081f8: 4b8c ldr r3, [pc, #560] @ (800842c ) 80081fa: 685b ldr r3, [r3, #4] 80081fc: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008200: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8008204: d10b bne.n 800821e { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8008206: 4b89 ldr r3, [pc, #548] @ (800842c ) 8008208: 681b ldr r3, [r3, #0] 800820a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800820e: 2b00 cmp r3, #0 8008210: d06c beq.n 80082ec 8008212: 687b ldr r3, [r7, #4] 8008214: 685b ldr r3, [r3, #4] 8008216: 2b00 cmp r3, #0 8008218: d168 bne.n 80082ec { return HAL_ERROR; 800821a: 2301 movs r3, #1 800821c: e24c b.n 80086b8 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800821e: 687b ldr r3, [r7, #4] 8008220: 685b ldr r3, [r3, #4] 8008222: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8008226: d106 bne.n 8008236 8008228: 4b80 ldr r3, [pc, #512] @ (800842c ) 800822a: 681b ldr r3, [r3, #0] 800822c: 4a7f ldr r2, [pc, #508] @ (800842c ) 800822e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8008232: 6013 str r3, [r2, #0] 8008234: e02e b.n 8008294 8008236: 687b ldr r3, [r7, #4] 8008238: 685b ldr r3, [r3, #4] 800823a: 2b00 cmp r3, #0 800823c: d10c bne.n 8008258 800823e: 4b7b ldr r3, [pc, #492] @ (800842c ) 8008240: 681b ldr r3, [r3, #0] 8008242: 4a7a ldr r2, [pc, #488] @ (800842c ) 8008244: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8008248: 6013 str r3, [r2, #0] 800824a: 4b78 ldr r3, [pc, #480] @ (800842c ) 800824c: 681b ldr r3, [r3, #0] 800824e: 4a77 ldr r2, [pc, #476] @ (800842c ) 8008250: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8008254: 6013 str r3, [r2, #0] 8008256: e01d b.n 8008294 8008258: 687b ldr r3, [r7, #4] 800825a: 685b ldr r3, [r3, #4] 800825c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8008260: d10c bne.n 800827c 8008262: 4b72 ldr r3, [pc, #456] @ (800842c ) 8008264: 681b ldr r3, [r3, #0] 8008266: 4a71 ldr r2, [pc, #452] @ (800842c ) 8008268: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800826c: 6013 str r3, [r2, #0] 800826e: 4b6f ldr r3, [pc, #444] @ (800842c ) 8008270: 681b ldr r3, [r3, #0] 8008272: 4a6e ldr r2, [pc, #440] @ (800842c ) 8008274: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8008278: 6013 str r3, [r2, #0] 800827a: e00b b.n 8008294 800827c: 4b6b ldr r3, [pc, #428] @ (800842c ) 800827e: 681b ldr r3, [r3, #0] 8008280: 4a6a ldr r2, [pc, #424] @ (800842c ) 8008282: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8008286: 6013 str r3, [r2, #0] 8008288: 4b68 ldr r3, [pc, #416] @ (800842c ) 800828a: 681b ldr r3, [r3, #0] 800828c: 4a67 ldr r2, [pc, #412] @ (800842c ) 800828e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8008292: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8008294: 687b ldr r3, [r7, #4] 8008296: 685b ldr r3, [r3, #4] 8008298: 2b00 cmp r3, #0 800829a: d013 beq.n 80082c4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800829c: f7fc ffa4 bl 80051e8 80082a0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80082a2: e008 b.n 80082b6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80082a4: f7fc ffa0 bl 80051e8 80082a8: 4602 mov r2, r0 80082aa: 693b ldr r3, [r7, #16] 80082ac: 1ad3 subs r3, r2, r3 80082ae: 2b64 cmp r3, #100 @ 0x64 80082b0: d901 bls.n 80082b6 { return HAL_TIMEOUT; 80082b2: 2303 movs r3, #3 80082b4: e200 b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80082b6: 4b5d ldr r3, [pc, #372] @ (800842c ) 80082b8: 681b ldr r3, [r3, #0] 80082ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 80082be: 2b00 cmp r3, #0 80082c0: d0f0 beq.n 80082a4 80082c2: e014 b.n 80082ee } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80082c4: f7fc ff90 bl 80051e8 80082c8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80082ca: e008 b.n 80082de { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80082cc: f7fc ff8c bl 80051e8 80082d0: 4602 mov r2, r0 80082d2: 693b ldr r3, [r7, #16] 80082d4: 1ad3 subs r3, r2, r3 80082d6: 2b64 cmp r3, #100 @ 0x64 80082d8: d901 bls.n 80082de { return HAL_TIMEOUT; 80082da: 2303 movs r3, #3 80082dc: e1ec b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80082de: 4b53 ldr r3, [pc, #332] @ (800842c ) 80082e0: 681b ldr r3, [r3, #0] 80082e2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80082e6: 2b00 cmp r3, #0 80082e8: d1f0 bne.n 80082cc 80082ea: e000 b.n 80082ee if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80082ec: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80082ee: 687b ldr r3, [r7, #4] 80082f0: 681b ldr r3, [r3, #0] 80082f2: f003 0302 and.w r3, r3, #2 80082f6: 2b00 cmp r3, #0 80082f8: d063 beq.n 80083c2 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80082fa: 4b4c ldr r3, [pc, #304] @ (800842c ) 80082fc: 685b ldr r3, [r3, #4] 80082fe: f003 030c and.w r3, r3, #12 8008302: 2b00 cmp r3, #0 8008304: d00b beq.n 800831e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8008306: 4b49 ldr r3, [pc, #292] @ (800842c ) 8008308: 685b ldr r3, [r3, #4] 800830a: f003 030c and.w r3, r3, #12 800830e: 2b08 cmp r3, #8 8008310: d11c bne.n 800834c 8008312: 4b46 ldr r3, [pc, #280] @ (800842c ) 8008314: 685b ldr r3, [r3, #4] 8008316: f403 3380 and.w r3, r3, #65536 @ 0x10000 800831a: 2b00 cmp r3, #0 800831c: d116 bne.n 800834c { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800831e: 4b43 ldr r3, [pc, #268] @ (800842c ) 8008320: 681b ldr r3, [r3, #0] 8008322: f003 0302 and.w r3, r3, #2 8008326: 2b00 cmp r3, #0 8008328: d005 beq.n 8008336 800832a: 687b ldr r3, [r7, #4] 800832c: 691b ldr r3, [r3, #16] 800832e: 2b01 cmp r3, #1 8008330: d001 beq.n 8008336 { return HAL_ERROR; 8008332: 2301 movs r3, #1 8008334: e1c0 b.n 80086b8 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8008336: 4b3d ldr r3, [pc, #244] @ (800842c ) 8008338: 681b ldr r3, [r3, #0] 800833a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800833e: 687b ldr r3, [r7, #4] 8008340: 695b ldr r3, [r3, #20] 8008342: 00db lsls r3, r3, #3 8008344: 4939 ldr r1, [pc, #228] @ (800842c ) 8008346: 4313 orrs r3, r2 8008348: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800834a: e03a b.n 80083c2 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800834c: 687b ldr r3, [r7, #4] 800834e: 691b ldr r3, [r3, #16] 8008350: 2b00 cmp r3, #0 8008352: d020 beq.n 8008396 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8008354: 4b36 ldr r3, [pc, #216] @ (8008430 ) 8008356: 2201 movs r2, #1 8008358: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800835a: f7fc ff45 bl 80051e8 800835e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8008360: e008 b.n 8008374 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8008362: f7fc ff41 bl 80051e8 8008366: 4602 mov r2, r0 8008368: 693b ldr r3, [r7, #16] 800836a: 1ad3 subs r3, r2, r3 800836c: 2b02 cmp r3, #2 800836e: d901 bls.n 8008374 { return HAL_TIMEOUT; 8008370: 2303 movs r3, #3 8008372: e1a1 b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8008374: 4b2d ldr r3, [pc, #180] @ (800842c ) 8008376: 681b ldr r3, [r3, #0] 8008378: f003 0302 and.w r3, r3, #2 800837c: 2b00 cmp r3, #0 800837e: d0f0 beq.n 8008362 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8008380: 4b2a ldr r3, [pc, #168] @ (800842c ) 8008382: 681b ldr r3, [r3, #0] 8008384: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8008388: 687b ldr r3, [r7, #4] 800838a: 695b ldr r3, [r3, #20] 800838c: 00db lsls r3, r3, #3 800838e: 4927 ldr r1, [pc, #156] @ (800842c ) 8008390: 4313 orrs r3, r2 8008392: 600b str r3, [r1, #0] 8008394: e015 b.n 80083c2 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8008396: 4b26 ldr r3, [pc, #152] @ (8008430 ) 8008398: 2200 movs r2, #0 800839a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800839c: f7fc ff24 bl 80051e8 80083a0: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80083a2: e008 b.n 80083b6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80083a4: f7fc ff20 bl 80051e8 80083a8: 4602 mov r2, r0 80083aa: 693b ldr r3, [r7, #16] 80083ac: 1ad3 subs r3, r2, r3 80083ae: 2b02 cmp r3, #2 80083b0: d901 bls.n 80083b6 { return HAL_TIMEOUT; 80083b2: 2303 movs r3, #3 80083b4: e180 b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80083b6: 4b1d ldr r3, [pc, #116] @ (800842c ) 80083b8: 681b ldr r3, [r3, #0] 80083ba: f003 0302 and.w r3, r3, #2 80083be: 2b00 cmp r3, #0 80083c0: d1f0 bne.n 80083a4 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80083c2: 687b ldr r3, [r7, #4] 80083c4: 681b ldr r3, [r3, #0] 80083c6: f003 0308 and.w r3, r3, #8 80083ca: 2b00 cmp r3, #0 80083cc: d03a beq.n 8008444 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80083ce: 687b ldr r3, [r7, #4] 80083d0: 699b ldr r3, [r3, #24] 80083d2: 2b00 cmp r3, #0 80083d4: d019 beq.n 800840a { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80083d6: 4b17 ldr r3, [pc, #92] @ (8008434 ) 80083d8: 2201 movs r2, #1 80083da: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80083dc: f7fc ff04 bl 80051e8 80083e0: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80083e2: e008 b.n 80083f6 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80083e4: f7fc ff00 bl 80051e8 80083e8: 4602 mov r2, r0 80083ea: 693b ldr r3, [r7, #16] 80083ec: 1ad3 subs r3, r2, r3 80083ee: 2b02 cmp r3, #2 80083f0: d901 bls.n 80083f6 { return HAL_TIMEOUT; 80083f2: 2303 movs r3, #3 80083f4: e160 b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80083f6: 4b0d ldr r3, [pc, #52] @ (800842c ) 80083f8: 6a5b ldr r3, [r3, #36] @ 0x24 80083fa: f003 0302 and.w r3, r3, #2 80083fe: 2b00 cmp r3, #0 8008400: d0f0 beq.n 80083e4 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8008402: 2001 movs r0, #1 8008404: f000 fad0 bl 80089a8 8008408: e01c b.n 8008444 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800840a: 4b0a ldr r3, [pc, #40] @ (8008434 ) 800840c: 2200 movs r2, #0 800840e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8008410: f7fc feea bl 80051e8 8008414: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8008416: e00f b.n 8008438 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8008418: f7fc fee6 bl 80051e8 800841c: 4602 mov r2, r0 800841e: 693b ldr r3, [r7, #16] 8008420: 1ad3 subs r3, r2, r3 8008422: 2b02 cmp r3, #2 8008424: d908 bls.n 8008438 { return HAL_TIMEOUT; 8008426: 2303 movs r3, #3 8008428: e146 b.n 80086b8 800842a: bf00 nop 800842c: 40021000 .word 0x40021000 8008430: 42420000 .word 0x42420000 8008434: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8008438: 4b92 ldr r3, [pc, #584] @ (8008684 ) 800843a: 6a5b ldr r3, [r3, #36] @ 0x24 800843c: f003 0302 and.w r3, r3, #2 8008440: 2b00 cmp r3, #0 8008442: d1e9 bne.n 8008418 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8008444: 687b ldr r3, [r7, #4] 8008446: 681b ldr r3, [r3, #0] 8008448: f003 0304 and.w r3, r3, #4 800844c: 2b00 cmp r3, #0 800844e: f000 80a6 beq.w 800859e { FlagStatus pwrclkchanged = RESET; 8008452: 2300 movs r3, #0 8008454: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8008456: 4b8b ldr r3, [pc, #556] @ (8008684 ) 8008458: 69db ldr r3, [r3, #28] 800845a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800845e: 2b00 cmp r3, #0 8008460: d10d bne.n 800847e { __HAL_RCC_PWR_CLK_ENABLE(); 8008462: 4b88 ldr r3, [pc, #544] @ (8008684 ) 8008464: 69db ldr r3, [r3, #28] 8008466: 4a87 ldr r2, [pc, #540] @ (8008684 ) 8008468: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800846c: 61d3 str r3, [r2, #28] 800846e: 4b85 ldr r3, [pc, #532] @ (8008684 ) 8008470: 69db ldr r3, [r3, #28] 8008472: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008476: 60bb str r3, [r7, #8] 8008478: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800847a: 2301 movs r3, #1 800847c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800847e: 4b82 ldr r3, [pc, #520] @ (8008688 ) 8008480: 681b ldr r3, [r3, #0] 8008482: f403 7380 and.w r3, r3, #256 @ 0x100 8008486: 2b00 cmp r3, #0 8008488: d118 bne.n 80084bc { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800848a: 4b7f ldr r3, [pc, #508] @ (8008688 ) 800848c: 681b ldr r3, [r3, #0] 800848e: 4a7e ldr r2, [pc, #504] @ (8008688 ) 8008490: f443 7380 orr.w r3, r3, #256 @ 0x100 8008494: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8008496: f7fc fea7 bl 80051e8 800849a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800849c: e008 b.n 80084b0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800849e: f7fc fea3 bl 80051e8 80084a2: 4602 mov r2, r0 80084a4: 693b ldr r3, [r7, #16] 80084a6: 1ad3 subs r3, r2, r3 80084a8: 2b64 cmp r3, #100 @ 0x64 80084aa: d901 bls.n 80084b0 { return HAL_TIMEOUT; 80084ac: 2303 movs r3, #3 80084ae: e103 b.n 80086b8 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80084b0: 4b75 ldr r3, [pc, #468] @ (8008688 ) 80084b2: 681b ldr r3, [r3, #0] 80084b4: f403 7380 and.w r3, r3, #256 @ 0x100 80084b8: 2b00 cmp r3, #0 80084ba: d0f0 beq.n 800849e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80084bc: 687b ldr r3, [r7, #4] 80084be: 68db ldr r3, [r3, #12] 80084c0: 2b01 cmp r3, #1 80084c2: d106 bne.n 80084d2 80084c4: 4b6f ldr r3, [pc, #444] @ (8008684 ) 80084c6: 6a1b ldr r3, [r3, #32] 80084c8: 4a6e ldr r2, [pc, #440] @ (8008684 ) 80084ca: f043 0301 orr.w r3, r3, #1 80084ce: 6213 str r3, [r2, #32] 80084d0: e02d b.n 800852e 80084d2: 687b ldr r3, [r7, #4] 80084d4: 68db ldr r3, [r3, #12] 80084d6: 2b00 cmp r3, #0 80084d8: d10c bne.n 80084f4 80084da: 4b6a ldr r3, [pc, #424] @ (8008684 ) 80084dc: 6a1b ldr r3, [r3, #32] 80084de: 4a69 ldr r2, [pc, #420] @ (8008684 ) 80084e0: f023 0301 bic.w r3, r3, #1 80084e4: 6213 str r3, [r2, #32] 80084e6: 4b67 ldr r3, [pc, #412] @ (8008684 ) 80084e8: 6a1b ldr r3, [r3, #32] 80084ea: 4a66 ldr r2, [pc, #408] @ (8008684 ) 80084ec: f023 0304 bic.w r3, r3, #4 80084f0: 6213 str r3, [r2, #32] 80084f2: e01c b.n 800852e 80084f4: 687b ldr r3, [r7, #4] 80084f6: 68db ldr r3, [r3, #12] 80084f8: 2b05 cmp r3, #5 80084fa: d10c bne.n 8008516 80084fc: 4b61 ldr r3, [pc, #388] @ (8008684 ) 80084fe: 6a1b ldr r3, [r3, #32] 8008500: 4a60 ldr r2, [pc, #384] @ (8008684 ) 8008502: f043 0304 orr.w r3, r3, #4 8008506: 6213 str r3, [r2, #32] 8008508: 4b5e ldr r3, [pc, #376] @ (8008684 ) 800850a: 6a1b ldr r3, [r3, #32] 800850c: 4a5d ldr r2, [pc, #372] @ (8008684 ) 800850e: f043 0301 orr.w r3, r3, #1 8008512: 6213 str r3, [r2, #32] 8008514: e00b b.n 800852e 8008516: 4b5b ldr r3, [pc, #364] @ (8008684 ) 8008518: 6a1b ldr r3, [r3, #32] 800851a: 4a5a ldr r2, [pc, #360] @ (8008684 ) 800851c: f023 0301 bic.w r3, r3, #1 8008520: 6213 str r3, [r2, #32] 8008522: 4b58 ldr r3, [pc, #352] @ (8008684 ) 8008524: 6a1b ldr r3, [r3, #32] 8008526: 4a57 ldr r2, [pc, #348] @ (8008684 ) 8008528: f023 0304 bic.w r3, r3, #4 800852c: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800852e: 687b ldr r3, [r7, #4] 8008530: 68db ldr r3, [r3, #12] 8008532: 2b00 cmp r3, #0 8008534: d015 beq.n 8008562 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8008536: f7fc fe57 bl 80051e8 800853a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800853c: e00a b.n 8008554 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800853e: f7fc fe53 bl 80051e8 8008542: 4602 mov r2, r0 8008544: 693b ldr r3, [r7, #16] 8008546: 1ad3 subs r3, r2, r3 8008548: f241 3288 movw r2, #5000 @ 0x1388 800854c: 4293 cmp r3, r2 800854e: d901 bls.n 8008554 { return HAL_TIMEOUT; 8008550: 2303 movs r3, #3 8008552: e0b1 b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8008554: 4b4b ldr r3, [pc, #300] @ (8008684 ) 8008556: 6a1b ldr r3, [r3, #32] 8008558: f003 0302 and.w r3, r3, #2 800855c: 2b00 cmp r3, #0 800855e: d0ee beq.n 800853e 8008560: e014 b.n 800858c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8008562: f7fc fe41 bl 80051e8 8008566: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8008568: e00a b.n 8008580 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800856a: f7fc fe3d bl 80051e8 800856e: 4602 mov r2, r0 8008570: 693b ldr r3, [r7, #16] 8008572: 1ad3 subs r3, r2, r3 8008574: f241 3288 movw r2, #5000 @ 0x1388 8008578: 4293 cmp r3, r2 800857a: d901 bls.n 8008580 { return HAL_TIMEOUT; 800857c: 2303 movs r3, #3 800857e: e09b b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8008580: 4b40 ldr r3, [pc, #256] @ (8008684 ) 8008582: 6a1b ldr r3, [r3, #32] 8008584: f003 0302 and.w r3, r3, #2 8008588: 2b00 cmp r3, #0 800858a: d1ee bne.n 800856a } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800858c: 7dfb ldrb r3, [r7, #23] 800858e: 2b01 cmp r3, #1 8008590: d105 bne.n 800859e { __HAL_RCC_PWR_CLK_DISABLE(); 8008592: 4b3c ldr r3, [pc, #240] @ (8008684 ) 8008594: 69db ldr r3, [r3, #28] 8008596: 4a3b ldr r2, [pc, #236] @ (8008684 ) 8008598: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800859c: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800859e: 687b ldr r3, [r7, #4] 80085a0: 69db ldr r3, [r3, #28] 80085a2: 2b00 cmp r3, #0 80085a4: f000 8087 beq.w 80086b6 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80085a8: 4b36 ldr r3, [pc, #216] @ (8008684 ) 80085aa: 685b ldr r3, [r3, #4] 80085ac: f003 030c and.w r3, r3, #12 80085b0: 2b08 cmp r3, #8 80085b2: d061 beq.n 8008678 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80085b4: 687b ldr r3, [r7, #4] 80085b6: 69db ldr r3, [r3, #28] 80085b8: 2b02 cmp r3, #2 80085ba: d146 bne.n 800864a /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80085bc: 4b33 ldr r3, [pc, #204] @ (800868c ) 80085be: 2200 movs r2, #0 80085c0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80085c2: f7fc fe11 bl 80051e8 80085c6: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80085c8: e008 b.n 80085dc { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80085ca: f7fc fe0d bl 80051e8 80085ce: 4602 mov r2, r0 80085d0: 693b ldr r3, [r7, #16] 80085d2: 1ad3 subs r3, r2, r3 80085d4: 2b02 cmp r3, #2 80085d6: d901 bls.n 80085dc { return HAL_TIMEOUT; 80085d8: 2303 movs r3, #3 80085da: e06d b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80085dc: 4b29 ldr r3, [pc, #164] @ (8008684 ) 80085de: 681b ldr r3, [r3, #0] 80085e0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80085e4: 2b00 cmp r3, #0 80085e6: d1f0 bne.n 80085ca } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80085e8: 687b ldr r3, [r7, #4] 80085ea: 6a1b ldr r3, [r3, #32] 80085ec: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80085f0: d108 bne.n 8008604 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80085f2: 4b24 ldr r3, [pc, #144] @ (8008684 ) 80085f4: 685b ldr r3, [r3, #4] 80085f6: f423 3200 bic.w r2, r3, #131072 @ 0x20000 80085fa: 687b ldr r3, [r7, #4] 80085fc: 689b ldr r3, [r3, #8] 80085fe: 4921 ldr r1, [pc, #132] @ (8008684 ) 8008600: 4313 orrs r3, r2 8008602: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8008604: 4b1f ldr r3, [pc, #124] @ (8008684 ) 8008606: 685b ldr r3, [r3, #4] 8008608: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 800860c: 687b ldr r3, [r7, #4] 800860e: 6a19 ldr r1, [r3, #32] 8008610: 687b ldr r3, [r7, #4] 8008612: 6a5b ldr r3, [r3, #36] @ 0x24 8008614: 430b orrs r3, r1 8008616: 491b ldr r1, [pc, #108] @ (8008684 ) 8008618: 4313 orrs r3, r2 800861a: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800861c: 4b1b ldr r3, [pc, #108] @ (800868c ) 800861e: 2201 movs r2, #1 8008620: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8008622: f7fc fde1 bl 80051e8 8008626: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8008628: e008 b.n 800863c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800862a: f7fc fddd bl 80051e8 800862e: 4602 mov r2, r0 8008630: 693b ldr r3, [r7, #16] 8008632: 1ad3 subs r3, r2, r3 8008634: 2b02 cmp r3, #2 8008636: d901 bls.n 800863c { return HAL_TIMEOUT; 8008638: 2303 movs r3, #3 800863a: e03d b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800863c: 4b11 ldr r3, [pc, #68] @ (8008684 ) 800863e: 681b ldr r3, [r3, #0] 8008640: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8008644: 2b00 cmp r3, #0 8008646: d0f0 beq.n 800862a 8008648: e035 b.n 80086b6 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800864a: 4b10 ldr r3, [pc, #64] @ (800868c ) 800864c: 2200 movs r2, #0 800864e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8008650: f7fc fdca bl 80051e8 8008654: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8008656: e008 b.n 800866a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8008658: f7fc fdc6 bl 80051e8 800865c: 4602 mov r2, r0 800865e: 693b ldr r3, [r7, #16] 8008660: 1ad3 subs r3, r2, r3 8008662: 2b02 cmp r3, #2 8008664: d901 bls.n 800866a { return HAL_TIMEOUT; 8008666: 2303 movs r3, #3 8008668: e026 b.n 80086b8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800866a: 4b06 ldr r3, [pc, #24] @ (8008684 ) 800866c: 681b ldr r3, [r3, #0] 800866e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8008672: 2b00 cmp r3, #0 8008674: d1f0 bne.n 8008658 8008676: e01e b.n 80086b6 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8008678: 687b ldr r3, [r7, #4] 800867a: 69db ldr r3, [r3, #28] 800867c: 2b01 cmp r3, #1 800867e: d107 bne.n 8008690 { return HAL_ERROR; 8008680: 2301 movs r3, #1 8008682: e019 b.n 80086b8 8008684: 40021000 .word 0x40021000 8008688: 40007000 .word 0x40007000 800868c: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8008690: 4b0b ldr r3, [pc, #44] @ (80086c0 ) 8008692: 685b ldr r3, [r3, #4] 8008694: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8008696: 68fb ldr r3, [r7, #12] 8008698: f403 3280 and.w r2, r3, #65536 @ 0x10000 800869c: 687b ldr r3, [r7, #4] 800869e: 6a1b ldr r3, [r3, #32] 80086a0: 429a cmp r2, r3 80086a2: d106 bne.n 80086b2 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80086a4: 68fb ldr r3, [r7, #12] 80086a6: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 80086aa: 687b ldr r3, [r7, #4] 80086ac: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80086ae: 429a cmp r2, r3 80086b0: d001 beq.n 80086b6 { return HAL_ERROR; 80086b2: 2301 movs r3, #1 80086b4: e000 b.n 80086b8 } } } } return HAL_OK; 80086b6: 2300 movs r3, #0 } 80086b8: 4618 mov r0, r3 80086ba: 3718 adds r7, #24 80086bc: 46bd mov sp, r7 80086be: bd80 pop {r7, pc} 80086c0: 40021000 .word 0x40021000 080086c4 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80086c4: b580 push {r7, lr} 80086c6: b084 sub sp, #16 80086c8: af00 add r7, sp, #0 80086ca: 6078 str r0, [r7, #4] 80086cc: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80086ce: 687b ldr r3, [r7, #4] 80086d0: 2b00 cmp r3, #0 80086d2: d101 bne.n 80086d8 { return HAL_ERROR; 80086d4: 2301 movs r3, #1 80086d6: e0d0 b.n 800887a must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80086d8: 4b6a ldr r3, [pc, #424] @ (8008884 ) 80086da: 681b ldr r3, [r3, #0] 80086dc: f003 0307 and.w r3, r3, #7 80086e0: 683a ldr r2, [r7, #0] 80086e2: 429a cmp r2, r3 80086e4: d910 bls.n 8008708 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80086e6: 4b67 ldr r3, [pc, #412] @ (8008884 ) 80086e8: 681b ldr r3, [r3, #0] 80086ea: f023 0207 bic.w r2, r3, #7 80086ee: 4965 ldr r1, [pc, #404] @ (8008884 ) 80086f0: 683b ldr r3, [r7, #0] 80086f2: 4313 orrs r3, r2 80086f4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80086f6: 4b63 ldr r3, [pc, #396] @ (8008884 ) 80086f8: 681b ldr r3, [r3, #0] 80086fa: f003 0307 and.w r3, r3, #7 80086fe: 683a ldr r2, [r7, #0] 8008700: 429a cmp r2, r3 8008702: d001 beq.n 8008708 { return HAL_ERROR; 8008704: 2301 movs r3, #1 8008706: e0b8 b.n 800887a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8008708: 687b ldr r3, [r7, #4] 800870a: 681b ldr r3, [r3, #0] 800870c: f003 0302 and.w r3, r3, #2 8008710: 2b00 cmp r3, #0 8008712: d020 beq.n 8008756 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8008714: 687b ldr r3, [r7, #4] 8008716: 681b ldr r3, [r3, #0] 8008718: f003 0304 and.w r3, r3, #4 800871c: 2b00 cmp r3, #0 800871e: d005 beq.n 800872c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8008720: 4b59 ldr r3, [pc, #356] @ (8008888 ) 8008722: 685b ldr r3, [r3, #4] 8008724: 4a58 ldr r2, [pc, #352] @ (8008888 ) 8008726: f443 63e0 orr.w r3, r3, #1792 @ 0x700 800872a: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800872c: 687b ldr r3, [r7, #4] 800872e: 681b ldr r3, [r3, #0] 8008730: f003 0308 and.w r3, r3, #8 8008734: 2b00 cmp r3, #0 8008736: d005 beq.n 8008744 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8008738: 4b53 ldr r3, [pc, #332] @ (8008888 ) 800873a: 685b ldr r3, [r3, #4] 800873c: 4a52 ldr r2, [pc, #328] @ (8008888 ) 800873e: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8008742: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8008744: 4b50 ldr r3, [pc, #320] @ (8008888 ) 8008746: 685b ldr r3, [r3, #4] 8008748: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800874c: 687b ldr r3, [r7, #4] 800874e: 689b ldr r3, [r3, #8] 8008750: 494d ldr r1, [pc, #308] @ (8008888 ) 8008752: 4313 orrs r3, r2 8008754: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8008756: 687b ldr r3, [r7, #4] 8008758: 681b ldr r3, [r3, #0] 800875a: f003 0301 and.w r3, r3, #1 800875e: 2b00 cmp r3, #0 8008760: d040 beq.n 80087e4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8008762: 687b ldr r3, [r7, #4] 8008764: 685b ldr r3, [r3, #4] 8008766: 2b01 cmp r3, #1 8008768: d107 bne.n 800877a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800876a: 4b47 ldr r3, [pc, #284] @ (8008888 ) 800876c: 681b ldr r3, [r3, #0] 800876e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8008772: 2b00 cmp r3, #0 8008774: d115 bne.n 80087a2 { return HAL_ERROR; 8008776: 2301 movs r3, #1 8008778: e07f b.n 800887a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800877a: 687b ldr r3, [r7, #4] 800877c: 685b ldr r3, [r3, #4] 800877e: 2b02 cmp r3, #2 8008780: d107 bne.n 8008792 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8008782: 4b41 ldr r3, [pc, #260] @ (8008888 ) 8008784: 681b ldr r3, [r3, #0] 8008786: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800878a: 2b00 cmp r3, #0 800878c: d109 bne.n 80087a2 { return HAL_ERROR; 800878e: 2301 movs r3, #1 8008790: e073 b.n 800887a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8008792: 4b3d ldr r3, [pc, #244] @ (8008888 ) 8008794: 681b ldr r3, [r3, #0] 8008796: f003 0302 and.w r3, r3, #2 800879a: 2b00 cmp r3, #0 800879c: d101 bne.n 80087a2 { return HAL_ERROR; 800879e: 2301 movs r3, #1 80087a0: e06b b.n 800887a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80087a2: 4b39 ldr r3, [pc, #228] @ (8008888 ) 80087a4: 685b ldr r3, [r3, #4] 80087a6: f023 0203 bic.w r2, r3, #3 80087aa: 687b ldr r3, [r7, #4] 80087ac: 685b ldr r3, [r3, #4] 80087ae: 4936 ldr r1, [pc, #216] @ (8008888 ) 80087b0: 4313 orrs r3, r2 80087b2: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80087b4: f7fc fd18 bl 80051e8 80087b8: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80087ba: e00a b.n 80087d2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80087bc: f7fc fd14 bl 80051e8 80087c0: 4602 mov r2, r0 80087c2: 68fb ldr r3, [r7, #12] 80087c4: 1ad3 subs r3, r2, r3 80087c6: f241 3288 movw r2, #5000 @ 0x1388 80087ca: 4293 cmp r3, r2 80087cc: d901 bls.n 80087d2 { return HAL_TIMEOUT; 80087ce: 2303 movs r3, #3 80087d0: e053 b.n 800887a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80087d2: 4b2d ldr r3, [pc, #180] @ (8008888 ) 80087d4: 685b ldr r3, [r3, #4] 80087d6: f003 020c and.w r2, r3, #12 80087da: 687b ldr r3, [r7, #4] 80087dc: 685b ldr r3, [r3, #4] 80087de: 009b lsls r3, r3, #2 80087e0: 429a cmp r2, r3 80087e2: d1eb bne.n 80087bc } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80087e4: 4b27 ldr r3, [pc, #156] @ (8008884 ) 80087e6: 681b ldr r3, [r3, #0] 80087e8: f003 0307 and.w r3, r3, #7 80087ec: 683a ldr r2, [r7, #0] 80087ee: 429a cmp r2, r3 80087f0: d210 bcs.n 8008814 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80087f2: 4b24 ldr r3, [pc, #144] @ (8008884 ) 80087f4: 681b ldr r3, [r3, #0] 80087f6: f023 0207 bic.w r2, r3, #7 80087fa: 4922 ldr r1, [pc, #136] @ (8008884 ) 80087fc: 683b ldr r3, [r7, #0] 80087fe: 4313 orrs r3, r2 8008800: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8008802: 4b20 ldr r3, [pc, #128] @ (8008884 ) 8008804: 681b ldr r3, [r3, #0] 8008806: f003 0307 and.w r3, r3, #7 800880a: 683a ldr r2, [r7, #0] 800880c: 429a cmp r2, r3 800880e: d001 beq.n 8008814 { return HAL_ERROR; 8008810: 2301 movs r3, #1 8008812: e032 b.n 800887a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8008814: 687b ldr r3, [r7, #4] 8008816: 681b ldr r3, [r3, #0] 8008818: f003 0304 and.w r3, r3, #4 800881c: 2b00 cmp r3, #0 800881e: d008 beq.n 8008832 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8008820: 4b19 ldr r3, [pc, #100] @ (8008888 ) 8008822: 685b ldr r3, [r3, #4] 8008824: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8008828: 687b ldr r3, [r7, #4] 800882a: 68db ldr r3, [r3, #12] 800882c: 4916 ldr r1, [pc, #88] @ (8008888 ) 800882e: 4313 orrs r3, r2 8008830: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8008832: 687b ldr r3, [r7, #4] 8008834: 681b ldr r3, [r3, #0] 8008836: f003 0308 and.w r3, r3, #8 800883a: 2b00 cmp r3, #0 800883c: d009 beq.n 8008852 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 800883e: 4b12 ldr r3, [pc, #72] @ (8008888 ) 8008840: 685b ldr r3, [r3, #4] 8008842: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8008846: 687b ldr r3, [r7, #4] 8008848: 691b ldr r3, [r3, #16] 800884a: 00db lsls r3, r3, #3 800884c: 490e ldr r1, [pc, #56] @ (8008888 ) 800884e: 4313 orrs r3, r2 8008850: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8008852: f000 f821 bl 8008898 8008856: 4602 mov r2, r0 8008858: 4b0b ldr r3, [pc, #44] @ (8008888 ) 800885a: 685b ldr r3, [r3, #4] 800885c: 091b lsrs r3, r3, #4 800885e: f003 030f and.w r3, r3, #15 8008862: 490a ldr r1, [pc, #40] @ (800888c ) 8008864: 5ccb ldrb r3, [r1, r3] 8008866: fa22 f303 lsr.w r3, r2, r3 800886a: 4a09 ldr r2, [pc, #36] @ (8008890 ) 800886c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 800886e: 4b09 ldr r3, [pc, #36] @ (8008894 ) 8008870: 681b ldr r3, [r3, #0] 8008872: 4618 mov r0, r3 8008874: f7fc fc76 bl 8005164 return HAL_OK; 8008878: 2300 movs r3, #0 } 800887a: 4618 mov r0, r3 800887c: 3710 adds r7, #16 800887e: 46bd mov sp, r7 8008880: bd80 pop {r7, pc} 8008882: bf00 nop 8008884: 40022000 .word 0x40022000 8008888: 40021000 .word 0x40021000 800888c: 0800f5b0 .word 0x0800f5b0 8008890: 20000010 .word 0x20000010 8008894: 20000014 .word 0x20000014 08008898 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8008898: b480 push {r7} 800889a: b087 sub sp, #28 800889c: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 800889e: 2300 movs r3, #0 80088a0: 60fb str r3, [r7, #12] 80088a2: 2300 movs r3, #0 80088a4: 60bb str r3, [r7, #8] 80088a6: 2300 movs r3, #0 80088a8: 617b str r3, [r7, #20] 80088aa: 2300 movs r3, #0 80088ac: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 80088ae: 2300 movs r3, #0 80088b0: 613b str r3, [r7, #16] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80088b2: 4b1e ldr r3, [pc, #120] @ (800892c ) 80088b4: 685b ldr r3, [r3, #4] 80088b6: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80088b8: 68fb ldr r3, [r7, #12] 80088ba: f003 030c and.w r3, r3, #12 80088be: 2b04 cmp r3, #4 80088c0: d002 beq.n 80088c8 80088c2: 2b08 cmp r3, #8 80088c4: d003 beq.n 80088ce 80088c6: e027 b.n 8008918 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80088c8: 4b19 ldr r3, [pc, #100] @ (8008930 ) 80088ca: 613b str r3, [r7, #16] break; 80088cc: e027 b.n 800891e } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80088ce: 68fb ldr r3, [r7, #12] 80088d0: 0c9b lsrs r3, r3, #18 80088d2: f003 030f and.w r3, r3, #15 80088d6: 4a17 ldr r2, [pc, #92] @ (8008934 ) 80088d8: 5cd3 ldrb r3, [r2, r3] 80088da: 607b str r3, [r7, #4] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80088dc: 68fb ldr r3, [r7, #12] 80088de: f403 3380 and.w r3, r3, #65536 @ 0x10000 80088e2: 2b00 cmp r3, #0 80088e4: d010 beq.n 8008908 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 80088e6: 4b11 ldr r3, [pc, #68] @ (800892c ) 80088e8: 685b ldr r3, [r3, #4] 80088ea: 0c5b lsrs r3, r3, #17 80088ec: f003 0301 and.w r3, r3, #1 80088f0: 4a11 ldr r2, [pc, #68] @ (8008938 ) 80088f2: 5cd3 ldrb r3, [r2, r3] 80088f4: 60bb str r3, [r7, #8] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80088f6: 687b ldr r3, [r7, #4] 80088f8: 4a0d ldr r2, [pc, #52] @ (8008930 ) 80088fa: fb03 f202 mul.w r2, r3, r2 80088fe: 68bb ldr r3, [r7, #8] 8008900: fbb2 f3f3 udiv r3, r2, r3 8008904: 617b str r3, [r7, #20] 8008906: e004 b.n 8008912 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8008908: 687b ldr r3, [r7, #4] 800890a: 4a0c ldr r2, [pc, #48] @ (800893c ) 800890c: fb02 f303 mul.w r3, r2, r3 8008910: 617b str r3, [r7, #20] } sysclockfreq = pllclk; 8008912: 697b ldr r3, [r7, #20] 8008914: 613b str r3, [r7, #16] break; 8008916: e002 b.n 800891e } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8008918: 4b09 ldr r3, [pc, #36] @ (8008940 ) 800891a: 613b str r3, [r7, #16] break; 800891c: bf00 nop } } return sysclockfreq; 800891e: 693b ldr r3, [r7, #16] } 8008920: 4618 mov r0, r3 8008922: 371c adds r7, #28 8008924: 46bd mov sp, r7 8008926: bc80 pop {r7} 8008928: 4770 bx lr 800892a: bf00 nop 800892c: 40021000 .word 0x40021000 8008930: 00b71b00 .word 0x00b71b00 8008934: 0800f5c8 .word 0x0800f5c8 8008938: 0800f5d8 .word 0x0800f5d8 800893c: 003d0900 .word 0x003d0900 8008940: 007a1200 .word 0x007a1200 08008944 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8008944: b480 push {r7} 8008946: af00 add r7, sp, #0 return SystemCoreClock; 8008948: 4b02 ldr r3, [pc, #8] @ (8008954 ) 800894a: 681b ldr r3, [r3, #0] } 800894c: 4618 mov r0, r3 800894e: 46bd mov sp, r7 8008950: bc80 pop {r7} 8008952: 4770 bx lr 8008954: 20000010 .word 0x20000010 08008958 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8008958: b580 push {r7, lr} 800895a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 800895c: f7ff fff2 bl 8008944 8008960: 4602 mov r2, r0 8008962: 4b05 ldr r3, [pc, #20] @ (8008978 ) 8008964: 685b ldr r3, [r3, #4] 8008966: 0a1b lsrs r3, r3, #8 8008968: f003 0307 and.w r3, r3, #7 800896c: 4903 ldr r1, [pc, #12] @ (800897c ) 800896e: 5ccb ldrb r3, [r1, r3] 8008970: fa22 f303 lsr.w r3, r2, r3 } 8008974: 4618 mov r0, r3 8008976: bd80 pop {r7, pc} 8008978: 40021000 .word 0x40021000 800897c: 0800f5c0 .word 0x0800f5c0 08008980 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8008980: b580 push {r7, lr} 8008982: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8008984: f7ff ffde bl 8008944 8008988: 4602 mov r2, r0 800898a: 4b05 ldr r3, [pc, #20] @ (80089a0 ) 800898c: 685b ldr r3, [r3, #4] 800898e: 0adb lsrs r3, r3, #11 8008990: f003 0307 and.w r3, r3, #7 8008994: 4903 ldr r1, [pc, #12] @ (80089a4 ) 8008996: 5ccb ldrb r3, [r1, r3] 8008998: fa22 f303 lsr.w r3, r2, r3 } 800899c: 4618 mov r0, r3 800899e: bd80 pop {r7, pc} 80089a0: 40021000 .word 0x40021000 80089a4: 0800f5c0 .word 0x0800f5c0 080089a8 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 80089a8: b480 push {r7} 80089aa: b085 sub sp, #20 80089ac: af00 add r7, sp, #0 80089ae: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 80089b0: 4b0a ldr r3, [pc, #40] @ (80089dc ) 80089b2: 681b ldr r3, [r3, #0] 80089b4: 4a0a ldr r2, [pc, #40] @ (80089e0 ) 80089b6: fba2 2303 umull r2, r3, r2, r3 80089ba: 0a5b lsrs r3, r3, #9 80089bc: 687a ldr r2, [r7, #4] 80089be: fb02 f303 mul.w r3, r2, r3 80089c2: 60fb str r3, [r7, #12] do { __NOP(); 80089c4: bf00 nop } while (Delay --); 80089c6: 68fb ldr r3, [r7, #12] 80089c8: 1e5a subs r2, r3, #1 80089ca: 60fa str r2, [r7, #12] 80089cc: 2b00 cmp r3, #0 80089ce: d1f9 bne.n 80089c4 } 80089d0: bf00 nop 80089d2: bf00 nop 80089d4: 3714 adds r7, #20 80089d6: 46bd mov sp, r7 80089d8: bc80 pop {r7} 80089da: 4770 bx lr 80089dc: 20000010 .word 0x20000010 80089e0: 10624dd3 .word 0x10624dd3 080089e4 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80089e4: b580 push {r7, lr} 80089e6: b086 sub sp, #24 80089e8: af00 add r7, sp, #0 80089ea: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 80089ec: 2300 movs r3, #0 80089ee: 613b str r3, [r7, #16] 80089f0: 2300 movs r3, #0 80089f2: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80089f4: 687b ldr r3, [r7, #4] 80089f6: 681b ldr r3, [r3, #0] 80089f8: f003 0301 and.w r3, r3, #1 80089fc: 2b00 cmp r3, #0 80089fe: d07d beq.n 8008afc { FlagStatus pwrclkchanged = RESET; 8008a00: 2300 movs r3, #0 8008a02: 75fb strb r3, [r7, #23] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8008a04: 4b4f ldr r3, [pc, #316] @ (8008b44 ) 8008a06: 69db ldr r3, [r3, #28] 8008a08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008a0c: 2b00 cmp r3, #0 8008a0e: d10d bne.n 8008a2c { __HAL_RCC_PWR_CLK_ENABLE(); 8008a10: 4b4c ldr r3, [pc, #304] @ (8008b44 ) 8008a12: 69db ldr r3, [r3, #28] 8008a14: 4a4b ldr r2, [pc, #300] @ (8008b44 ) 8008a16: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008a1a: 61d3 str r3, [r2, #28] 8008a1c: 4b49 ldr r3, [pc, #292] @ (8008b44 ) 8008a1e: 69db ldr r3, [r3, #28] 8008a20: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008a24: 60bb str r3, [r7, #8] 8008a26: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8008a28: 2301 movs r3, #1 8008a2a: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8008a2c: 4b46 ldr r3, [pc, #280] @ (8008b48 ) 8008a2e: 681b ldr r3, [r3, #0] 8008a30: f403 7380 and.w r3, r3, #256 @ 0x100 8008a34: 2b00 cmp r3, #0 8008a36: d118 bne.n 8008a6a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8008a38: 4b43 ldr r3, [pc, #268] @ (8008b48 ) 8008a3a: 681b ldr r3, [r3, #0] 8008a3c: 4a42 ldr r2, [pc, #264] @ (8008b48 ) 8008a3e: f443 7380 orr.w r3, r3, #256 @ 0x100 8008a42: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8008a44: f7fc fbd0 bl 80051e8 8008a48: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8008a4a: e008 b.n 8008a5e { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8008a4c: f7fc fbcc bl 80051e8 8008a50: 4602 mov r2, r0 8008a52: 693b ldr r3, [r7, #16] 8008a54: 1ad3 subs r3, r2, r3 8008a56: 2b64 cmp r3, #100 @ 0x64 8008a58: d901 bls.n 8008a5e { return HAL_TIMEOUT; 8008a5a: 2303 movs r3, #3 8008a5c: e06d b.n 8008b3a while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8008a5e: 4b3a ldr r3, [pc, #232] @ (8008b48 ) 8008a60: 681b ldr r3, [r3, #0] 8008a62: f403 7380 and.w r3, r3, #256 @ 0x100 8008a66: 2b00 cmp r3, #0 8008a68: d0f0 beq.n 8008a4c } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8008a6a: 4b36 ldr r3, [pc, #216] @ (8008b44 ) 8008a6c: 6a1b ldr r3, [r3, #32] 8008a6e: f403 7340 and.w r3, r3, #768 @ 0x300 8008a72: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8008a74: 68fb ldr r3, [r7, #12] 8008a76: 2b00 cmp r3, #0 8008a78: d02e beq.n 8008ad8 8008a7a: 687b ldr r3, [r7, #4] 8008a7c: 685b ldr r3, [r3, #4] 8008a7e: f403 7340 and.w r3, r3, #768 @ 0x300 8008a82: 68fa ldr r2, [r7, #12] 8008a84: 429a cmp r2, r3 8008a86: d027 beq.n 8008ad8 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8008a88: 4b2e ldr r3, [pc, #184] @ (8008b44 ) 8008a8a: 6a1b ldr r3, [r3, #32] 8008a8c: f423 7340 bic.w r3, r3, #768 @ 0x300 8008a90: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8008a92: 4b2e ldr r3, [pc, #184] @ (8008b4c ) 8008a94: 2201 movs r2, #1 8008a96: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8008a98: 4b2c ldr r3, [pc, #176] @ (8008b4c ) 8008a9a: 2200 movs r2, #0 8008a9c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8008a9e: 4a29 ldr r2, [pc, #164] @ (8008b44 ) 8008aa0: 68fb ldr r3, [r7, #12] 8008aa2: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8008aa4: 68fb ldr r3, [r7, #12] 8008aa6: f003 0301 and.w r3, r3, #1 8008aaa: 2b00 cmp r3, #0 8008aac: d014 beq.n 8008ad8 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8008aae: f7fc fb9b bl 80051e8 8008ab2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8008ab4: e00a b.n 8008acc { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8008ab6: f7fc fb97 bl 80051e8 8008aba: 4602 mov r2, r0 8008abc: 693b ldr r3, [r7, #16] 8008abe: 1ad3 subs r3, r2, r3 8008ac0: f241 3288 movw r2, #5000 @ 0x1388 8008ac4: 4293 cmp r3, r2 8008ac6: d901 bls.n 8008acc { return HAL_TIMEOUT; 8008ac8: 2303 movs r3, #3 8008aca: e036 b.n 8008b3a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8008acc: 4b1d ldr r3, [pc, #116] @ (8008b44 ) 8008ace: 6a1b ldr r3, [r3, #32] 8008ad0: f003 0302 and.w r3, r3, #2 8008ad4: 2b00 cmp r3, #0 8008ad6: d0ee beq.n 8008ab6 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8008ad8: 4b1a ldr r3, [pc, #104] @ (8008b44 ) 8008ada: 6a1b ldr r3, [r3, #32] 8008adc: f423 7240 bic.w r2, r3, #768 @ 0x300 8008ae0: 687b ldr r3, [r7, #4] 8008ae2: 685b ldr r3, [r3, #4] 8008ae4: 4917 ldr r1, [pc, #92] @ (8008b44 ) 8008ae6: 4313 orrs r3, r2 8008ae8: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8008aea: 7dfb ldrb r3, [r7, #23] 8008aec: 2b01 cmp r3, #1 8008aee: d105 bne.n 8008afc { __HAL_RCC_PWR_CLK_DISABLE(); 8008af0: 4b14 ldr r3, [pc, #80] @ (8008b44 ) 8008af2: 69db ldr r3, [r3, #28] 8008af4: 4a13 ldr r2, [pc, #76] @ (8008b44 ) 8008af6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8008afa: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8008afc: 687b ldr r3, [r7, #4] 8008afe: 681b ldr r3, [r3, #0] 8008b00: f003 0302 and.w r3, r3, #2 8008b04: 2b00 cmp r3, #0 8008b06: d008 beq.n 8008b1a { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8008b08: 4b0e ldr r3, [pc, #56] @ (8008b44 ) 8008b0a: 685b ldr r3, [r3, #4] 8008b0c: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8008b10: 687b ldr r3, [r7, #4] 8008b12: 689b ldr r3, [r3, #8] 8008b14: 490b ldr r1, [pc, #44] @ (8008b44 ) 8008b16: 4313 orrs r3, r2 8008b18: 604b str r3, [r1, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8008b1a: 687b ldr r3, [r7, #4] 8008b1c: 681b ldr r3, [r3, #0] 8008b1e: f003 0310 and.w r3, r3, #16 8008b22: 2b00 cmp r3, #0 8008b24: d008 beq.n 8008b38 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8008b26: 4b07 ldr r3, [pc, #28] @ (8008b44 ) 8008b28: 685b ldr r3, [r3, #4] 8008b2a: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8008b2e: 687b ldr r3, [r7, #4] 8008b30: 68db ldr r3, [r3, #12] 8008b32: 4904 ldr r1, [pc, #16] @ (8008b44 ) 8008b34: 4313 orrs r3, r2 8008b36: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8008b38: 2300 movs r3, #0 } 8008b3a: 4618 mov r0, r3 8008b3c: 3718 adds r7, #24 8008b3e: 46bd mov sp, r7 8008b40: bd80 pop {r7, pc} 8008b42: bf00 nop 8008b44: 40021000 .word 0x40021000 8008b48: 40007000 .word 0x40007000 8008b4c: 42420440 .word 0x42420440 08008b50 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8008b50: b580 push {r7, lr} 8008b52: b082 sub sp, #8 8008b54: af00 add r7, sp, #0 8008b56: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8008b58: 687b ldr r3, [r7, #4] 8008b5a: 2b00 cmp r3, #0 8008b5c: d101 bne.n 8008b62 { return HAL_ERROR; 8008b5e: 2301 movs r3, #1 8008b60: e041 b.n 8008be6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8008b62: 687b ldr r3, [r7, #4] 8008b64: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8008b68: b2db uxtb r3, r3 8008b6a: 2b00 cmp r3, #0 8008b6c: d106 bne.n 8008b7c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8008b6e: 687b ldr r3, [r7, #4] 8008b70: 2200 movs r2, #0 8008b72: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8008b76: 6878 ldr r0, [r7, #4] 8008b78: f7fc f96a bl 8004e50 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8008b7c: 687b ldr r3, [r7, #4] 8008b7e: 2202 movs r2, #2 8008b80: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8008b84: 687b ldr r3, [r7, #4] 8008b86: 681a ldr r2, [r3, #0] 8008b88: 687b ldr r3, [r7, #4] 8008b8a: 3304 adds r3, #4 8008b8c: 4619 mov r1, r3 8008b8e: 4610 mov r0, r2 8008b90: f000 fb3e bl 8009210 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8008b94: 687b ldr r3, [r7, #4] 8008b96: 2201 movs r2, #1 8008b98: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008b9c: 687b ldr r3, [r7, #4] 8008b9e: 2201 movs r2, #1 8008ba0: f883 203e strb.w r2, [r3, #62] @ 0x3e 8008ba4: 687b ldr r3, [r7, #4] 8008ba6: 2201 movs r2, #1 8008ba8: f883 203f strb.w r2, [r3, #63] @ 0x3f 8008bac: 687b ldr r3, [r7, #4] 8008bae: 2201 movs r2, #1 8008bb0: f883 2040 strb.w r2, [r3, #64] @ 0x40 8008bb4: 687b ldr r3, [r7, #4] 8008bb6: 2201 movs r2, #1 8008bb8: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008bbc: 687b ldr r3, [r7, #4] 8008bbe: 2201 movs r2, #1 8008bc0: f883 2042 strb.w r2, [r3, #66] @ 0x42 8008bc4: 687b ldr r3, [r7, #4] 8008bc6: 2201 movs r2, #1 8008bc8: f883 2043 strb.w r2, [r3, #67] @ 0x43 8008bcc: 687b ldr r3, [r7, #4] 8008bce: 2201 movs r2, #1 8008bd0: f883 2044 strb.w r2, [r3, #68] @ 0x44 8008bd4: 687b ldr r3, [r7, #4] 8008bd6: 2201 movs r2, #1 8008bd8: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8008bdc: 687b ldr r3, [r7, #4] 8008bde: 2201 movs r2, #1 8008be0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8008be4: 2300 movs r3, #0 } 8008be6: 4618 mov r0, r3 8008be8: 3708 adds r7, #8 8008bea: 46bd mov sp, r7 8008bec: bd80 pop {r7, pc} 08008bee : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8008bee: b580 push {r7, lr} 8008bf0: b082 sub sp, #8 8008bf2: af00 add r7, sp, #0 8008bf4: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8008bf6: 687b ldr r3, [r7, #4] 8008bf8: 2b00 cmp r3, #0 8008bfa: d101 bne.n 8008c00 { return HAL_ERROR; 8008bfc: 2301 movs r3, #1 8008bfe: e041 b.n 8008c84 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8008c00: 687b ldr r3, [r7, #4] 8008c02: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8008c06: b2db uxtb r3, r3 8008c08: 2b00 cmp r3, #0 8008c0a: d106 bne.n 8008c1a { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8008c0c: 687b ldr r3, [r7, #4] 8008c0e: 2200 movs r2, #0 8008c10: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8008c14: 6878 ldr r0, [r7, #4] 8008c16: f000 f839 bl 8008c8c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8008c1a: 687b ldr r3, [r7, #4] 8008c1c: 2202 movs r2, #2 8008c1e: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8008c22: 687b ldr r3, [r7, #4] 8008c24: 681a ldr r2, [r3, #0] 8008c26: 687b ldr r3, [r7, #4] 8008c28: 3304 adds r3, #4 8008c2a: 4619 mov r1, r3 8008c2c: 4610 mov r0, r2 8008c2e: f000 faef bl 8009210 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8008c32: 687b ldr r3, [r7, #4] 8008c34: 2201 movs r2, #1 8008c36: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008c3a: 687b ldr r3, [r7, #4] 8008c3c: 2201 movs r2, #1 8008c3e: f883 203e strb.w r2, [r3, #62] @ 0x3e 8008c42: 687b ldr r3, [r7, #4] 8008c44: 2201 movs r2, #1 8008c46: f883 203f strb.w r2, [r3, #63] @ 0x3f 8008c4a: 687b ldr r3, [r7, #4] 8008c4c: 2201 movs r2, #1 8008c4e: f883 2040 strb.w r2, [r3, #64] @ 0x40 8008c52: 687b ldr r3, [r7, #4] 8008c54: 2201 movs r2, #1 8008c56: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008c5a: 687b ldr r3, [r7, #4] 8008c5c: 2201 movs r2, #1 8008c5e: f883 2042 strb.w r2, [r3, #66] @ 0x42 8008c62: 687b ldr r3, [r7, #4] 8008c64: 2201 movs r2, #1 8008c66: f883 2043 strb.w r2, [r3, #67] @ 0x43 8008c6a: 687b ldr r3, [r7, #4] 8008c6c: 2201 movs r2, #1 8008c6e: f883 2044 strb.w r2, [r3, #68] @ 0x44 8008c72: 687b ldr r3, [r7, #4] 8008c74: 2201 movs r2, #1 8008c76: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8008c7a: 687b ldr r3, [r7, #4] 8008c7c: 2201 movs r2, #1 8008c7e: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8008c82: 2300 movs r3, #0 } 8008c84: 4618 mov r0, r3 8008c86: 3708 adds r7, #8 8008c88: 46bd mov sp, r7 8008c8a: bd80 pop {r7, pc} 08008c8c : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8008c8c: b480 push {r7} 8008c8e: b083 sub sp, #12 8008c90: af00 add r7, sp, #0 8008c92: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8008c94: bf00 nop 8008c96: 370c adds r7, #12 8008c98: 46bd mov sp, r7 8008c9a: bc80 pop {r7} 8008c9c: 4770 bx lr ... 08008ca0 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8008ca0: b580 push {r7, lr} 8008ca2: b084 sub sp, #16 8008ca4: af00 add r7, sp, #0 8008ca6: 6078 str r0, [r7, #4] 8008ca8: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8008caa: 683b ldr r3, [r7, #0] 8008cac: 2b00 cmp r3, #0 8008cae: d109 bne.n 8008cc4 8008cb0: 687b ldr r3, [r7, #4] 8008cb2: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8008cb6: b2db uxtb r3, r3 8008cb8: 2b01 cmp r3, #1 8008cba: bf14 ite ne 8008cbc: 2301 movne r3, #1 8008cbe: 2300 moveq r3, #0 8008cc0: b2db uxtb r3, r3 8008cc2: e022 b.n 8008d0a 8008cc4: 683b ldr r3, [r7, #0] 8008cc6: 2b04 cmp r3, #4 8008cc8: d109 bne.n 8008cde 8008cca: 687b ldr r3, [r7, #4] 8008ccc: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8008cd0: b2db uxtb r3, r3 8008cd2: 2b01 cmp r3, #1 8008cd4: bf14 ite ne 8008cd6: 2301 movne r3, #1 8008cd8: 2300 moveq r3, #0 8008cda: b2db uxtb r3, r3 8008cdc: e015 b.n 8008d0a 8008cde: 683b ldr r3, [r7, #0] 8008ce0: 2b08 cmp r3, #8 8008ce2: d109 bne.n 8008cf8 8008ce4: 687b ldr r3, [r7, #4] 8008ce6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008cea: b2db uxtb r3, r3 8008cec: 2b01 cmp r3, #1 8008cee: bf14 ite ne 8008cf0: 2301 movne r3, #1 8008cf2: 2300 moveq r3, #0 8008cf4: b2db uxtb r3, r3 8008cf6: e008 b.n 8008d0a 8008cf8: 687b ldr r3, [r7, #4] 8008cfa: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008cfe: b2db uxtb r3, r3 8008d00: 2b01 cmp r3, #1 8008d02: bf14 ite ne 8008d04: 2301 movne r3, #1 8008d06: 2300 moveq r3, #0 8008d08: b2db uxtb r3, r3 8008d0a: 2b00 cmp r3, #0 8008d0c: d001 beq.n 8008d12 { return HAL_ERROR; 8008d0e: 2301 movs r3, #1 8008d10: e05e b.n 8008dd0 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8008d12: 683b ldr r3, [r7, #0] 8008d14: 2b00 cmp r3, #0 8008d16: d104 bne.n 8008d22 8008d18: 687b ldr r3, [r7, #4] 8008d1a: 2202 movs r2, #2 8008d1c: f883 203e strb.w r2, [r3, #62] @ 0x3e 8008d20: e013 b.n 8008d4a 8008d22: 683b ldr r3, [r7, #0] 8008d24: 2b04 cmp r3, #4 8008d26: d104 bne.n 8008d32 8008d28: 687b ldr r3, [r7, #4] 8008d2a: 2202 movs r2, #2 8008d2c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8008d30: e00b b.n 8008d4a 8008d32: 683b ldr r3, [r7, #0] 8008d34: 2b08 cmp r3, #8 8008d36: d104 bne.n 8008d42 8008d38: 687b ldr r3, [r7, #4] 8008d3a: 2202 movs r2, #2 8008d3c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8008d40: e003 b.n 8008d4a 8008d42: 687b ldr r3, [r7, #4] 8008d44: 2202 movs r2, #2 8008d46: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8008d4a: 687b ldr r3, [r7, #4] 8008d4c: 681b ldr r3, [r3, #0] 8008d4e: 2201 movs r2, #1 8008d50: 6839 ldr r1, [r7, #0] 8008d52: 4618 mov r0, r3 8008d54: f000 fce8 bl 8009728 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8008d58: 687b ldr r3, [r7, #4] 8008d5a: 681b ldr r3, [r3, #0] 8008d5c: 4a1e ldr r2, [pc, #120] @ (8008dd8 ) 8008d5e: 4293 cmp r3, r2 8008d60: d107 bne.n 8008d72 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8008d62: 687b ldr r3, [r7, #4] 8008d64: 681b ldr r3, [r3, #0] 8008d66: 6c5a ldr r2, [r3, #68] @ 0x44 8008d68: 687b ldr r3, [r7, #4] 8008d6a: 681b ldr r3, [r3, #0] 8008d6c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8008d70: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8008d72: 687b ldr r3, [r7, #4] 8008d74: 681b ldr r3, [r3, #0] 8008d76: 4a18 ldr r2, [pc, #96] @ (8008dd8 ) 8008d78: 4293 cmp r3, r2 8008d7a: d00e beq.n 8008d9a 8008d7c: 687b ldr r3, [r7, #4] 8008d7e: 681b ldr r3, [r3, #0] 8008d80: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8008d84: d009 beq.n 8008d9a 8008d86: 687b ldr r3, [r7, #4] 8008d88: 681b ldr r3, [r3, #0] 8008d8a: 4a14 ldr r2, [pc, #80] @ (8008ddc ) 8008d8c: 4293 cmp r3, r2 8008d8e: d004 beq.n 8008d9a 8008d90: 687b ldr r3, [r7, #4] 8008d92: 681b ldr r3, [r3, #0] 8008d94: 4a12 ldr r2, [pc, #72] @ (8008de0 ) 8008d96: 4293 cmp r3, r2 8008d98: d111 bne.n 8008dbe { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8008d9a: 687b ldr r3, [r7, #4] 8008d9c: 681b ldr r3, [r3, #0] 8008d9e: 689b ldr r3, [r3, #8] 8008da0: f003 0307 and.w r3, r3, #7 8008da4: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8008da6: 68fb ldr r3, [r7, #12] 8008da8: 2b06 cmp r3, #6 8008daa: d010 beq.n 8008dce { __HAL_TIM_ENABLE(htim); 8008dac: 687b ldr r3, [r7, #4] 8008dae: 681b ldr r3, [r3, #0] 8008db0: 681a ldr r2, [r3, #0] 8008db2: 687b ldr r3, [r7, #4] 8008db4: 681b ldr r3, [r3, #0] 8008db6: f042 0201 orr.w r2, r2, #1 8008dba: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8008dbc: e007 b.n 8008dce } } else { __HAL_TIM_ENABLE(htim); 8008dbe: 687b ldr r3, [r7, #4] 8008dc0: 681b ldr r3, [r3, #0] 8008dc2: 681a ldr r2, [r3, #0] 8008dc4: 687b ldr r3, [r7, #4] 8008dc6: 681b ldr r3, [r3, #0] 8008dc8: f042 0201 orr.w r2, r2, #1 8008dcc: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8008dce: 2300 movs r3, #0 } 8008dd0: 4618 mov r0, r3 8008dd2: 3710 adds r7, #16 8008dd4: 46bd mov sp, r7 8008dd6: bd80 pop {r7, pc} 8008dd8: 40012c00 .word 0x40012c00 8008ddc: 40000400 .word 0x40000400 8008de0: 40000800 .word 0x40000800 08008de4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 8008de4: b580 push {r7, lr} 8008de6: b082 sub sp, #8 8008de8: af00 add r7, sp, #0 8008dea: 6078 str r0, [r7, #4] 8008dec: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 8008dee: 687b ldr r3, [r7, #4] 8008df0: 681b ldr r3, [r3, #0] 8008df2: 2200 movs r2, #0 8008df4: 6839 ldr r1, [r7, #0] 8008df6: 4618 mov r0, r3 8008df8: f000 fc96 bl 8009728 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8008dfc: 687b ldr r3, [r7, #4] 8008dfe: 681b ldr r3, [r3, #0] 8008e00: 4a29 ldr r2, [pc, #164] @ (8008ea8 ) 8008e02: 4293 cmp r3, r2 8008e04: d117 bne.n 8008e36 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 8008e06: 687b ldr r3, [r7, #4] 8008e08: 681b ldr r3, [r3, #0] 8008e0a: 6a1a ldr r2, [r3, #32] 8008e0c: f241 1311 movw r3, #4369 @ 0x1111 8008e10: 4013 ands r3, r2 8008e12: 2b00 cmp r3, #0 8008e14: d10f bne.n 8008e36 8008e16: 687b ldr r3, [r7, #4] 8008e18: 681b ldr r3, [r3, #0] 8008e1a: 6a1a ldr r2, [r3, #32] 8008e1c: f240 4344 movw r3, #1092 @ 0x444 8008e20: 4013 ands r3, r2 8008e22: 2b00 cmp r3, #0 8008e24: d107 bne.n 8008e36 8008e26: 687b ldr r3, [r7, #4] 8008e28: 681b ldr r3, [r3, #0] 8008e2a: 6c5a ldr r2, [r3, #68] @ 0x44 8008e2c: 687b ldr r3, [r7, #4] 8008e2e: 681b ldr r3, [r3, #0] 8008e30: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8008e34: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 8008e36: 687b ldr r3, [r7, #4] 8008e38: 681b ldr r3, [r3, #0] 8008e3a: 6a1a ldr r2, [r3, #32] 8008e3c: f241 1311 movw r3, #4369 @ 0x1111 8008e40: 4013 ands r3, r2 8008e42: 2b00 cmp r3, #0 8008e44: d10f bne.n 8008e66 8008e46: 687b ldr r3, [r7, #4] 8008e48: 681b ldr r3, [r3, #0] 8008e4a: 6a1a ldr r2, [r3, #32] 8008e4c: f240 4344 movw r3, #1092 @ 0x444 8008e50: 4013 ands r3, r2 8008e52: 2b00 cmp r3, #0 8008e54: d107 bne.n 8008e66 8008e56: 687b ldr r3, [r7, #4] 8008e58: 681b ldr r3, [r3, #0] 8008e5a: 681a ldr r2, [r3, #0] 8008e5c: 687b ldr r3, [r7, #4] 8008e5e: 681b ldr r3, [r3, #0] 8008e60: f022 0201 bic.w r2, r2, #1 8008e64: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 8008e66: 683b ldr r3, [r7, #0] 8008e68: 2b00 cmp r3, #0 8008e6a: d104 bne.n 8008e76 8008e6c: 687b ldr r3, [r7, #4] 8008e6e: 2201 movs r2, #1 8008e70: f883 203e strb.w r2, [r3, #62] @ 0x3e 8008e74: e013 b.n 8008e9e 8008e76: 683b ldr r3, [r7, #0] 8008e78: 2b04 cmp r3, #4 8008e7a: d104 bne.n 8008e86 8008e7c: 687b ldr r3, [r7, #4] 8008e7e: 2201 movs r2, #1 8008e80: f883 203f strb.w r2, [r3, #63] @ 0x3f 8008e84: e00b b.n 8008e9e 8008e86: 683b ldr r3, [r7, #0] 8008e88: 2b08 cmp r3, #8 8008e8a: d104 bne.n 8008e96 8008e8c: 687b ldr r3, [r7, #4] 8008e8e: 2201 movs r2, #1 8008e90: f883 2040 strb.w r2, [r3, #64] @ 0x40 8008e94: e003 b.n 8008e9e 8008e96: 687b ldr r3, [r7, #4] 8008e98: 2201 movs r2, #1 8008e9a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Return function status */ return HAL_OK; 8008e9e: 2300 movs r3, #0 } 8008ea0: 4618 mov r0, r3 8008ea2: 3708 adds r7, #8 8008ea4: 46bd mov sp, r7 8008ea6: bd80 pop {r7, pc} 8008ea8: 40012c00 .word 0x40012c00 08008eac : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8008eac: b580 push {r7, lr} 8008eae: b086 sub sp, #24 8008eb0: af00 add r7, sp, #0 8008eb2: 60f8 str r0, [r7, #12] 8008eb4: 60b9 str r1, [r7, #8] 8008eb6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8008eb8: 2300 movs r3, #0 8008eba: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8008ebc: 68fb ldr r3, [r7, #12] 8008ebe: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8008ec2: 2b01 cmp r3, #1 8008ec4: d101 bne.n 8008eca 8008ec6: 2302 movs r3, #2 8008ec8: e0ae b.n 8009028 8008eca: 68fb ldr r3, [r7, #12] 8008ecc: 2201 movs r2, #1 8008ece: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8008ed2: 687b ldr r3, [r7, #4] 8008ed4: 2b0c cmp r3, #12 8008ed6: f200 809f bhi.w 8009018 8008eda: a201 add r2, pc, #4 @ (adr r2, 8008ee0 ) 8008edc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008ee0: 08008f15 .word 0x08008f15 8008ee4: 08009019 .word 0x08009019 8008ee8: 08009019 .word 0x08009019 8008eec: 08009019 .word 0x08009019 8008ef0: 08008f55 .word 0x08008f55 8008ef4: 08009019 .word 0x08009019 8008ef8: 08009019 .word 0x08009019 8008efc: 08009019 .word 0x08009019 8008f00: 08008f97 .word 0x08008f97 8008f04: 08009019 .word 0x08009019 8008f08: 08009019 .word 0x08009019 8008f0c: 08009019 .word 0x08009019 8008f10: 08008fd7 .word 0x08008fd7 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8008f14: 68fb ldr r3, [r7, #12] 8008f16: 681b ldr r3, [r3, #0] 8008f18: 68b9 ldr r1, [r7, #8] 8008f1a: 4618 mov r0, r3 8008f1c: f000 f9e6 bl 80092ec /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8008f20: 68fb ldr r3, [r7, #12] 8008f22: 681b ldr r3, [r3, #0] 8008f24: 699a ldr r2, [r3, #24] 8008f26: 68fb ldr r3, [r7, #12] 8008f28: 681b ldr r3, [r3, #0] 8008f2a: f042 0208 orr.w r2, r2, #8 8008f2e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8008f30: 68fb ldr r3, [r7, #12] 8008f32: 681b ldr r3, [r3, #0] 8008f34: 699a ldr r2, [r3, #24] 8008f36: 68fb ldr r3, [r7, #12] 8008f38: 681b ldr r3, [r3, #0] 8008f3a: f022 0204 bic.w r2, r2, #4 8008f3e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8008f40: 68fb ldr r3, [r7, #12] 8008f42: 681b ldr r3, [r3, #0] 8008f44: 6999 ldr r1, [r3, #24] 8008f46: 68bb ldr r3, [r7, #8] 8008f48: 691a ldr r2, [r3, #16] 8008f4a: 68fb ldr r3, [r7, #12] 8008f4c: 681b ldr r3, [r3, #0] 8008f4e: 430a orrs r2, r1 8008f50: 619a str r2, [r3, #24] break; 8008f52: e064 b.n 800901e { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8008f54: 68fb ldr r3, [r7, #12] 8008f56: 681b ldr r3, [r3, #0] 8008f58: 68b9 ldr r1, [r7, #8] 8008f5a: 4618 mov r0, r3 8008f5c: f000 fa2c bl 80093b8 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8008f60: 68fb ldr r3, [r7, #12] 8008f62: 681b ldr r3, [r3, #0] 8008f64: 699a ldr r2, [r3, #24] 8008f66: 68fb ldr r3, [r7, #12] 8008f68: 681b ldr r3, [r3, #0] 8008f6a: f442 6200 orr.w r2, r2, #2048 @ 0x800 8008f6e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8008f70: 68fb ldr r3, [r7, #12] 8008f72: 681b ldr r3, [r3, #0] 8008f74: 699a ldr r2, [r3, #24] 8008f76: 68fb ldr r3, [r7, #12] 8008f78: 681b ldr r3, [r3, #0] 8008f7a: f422 6280 bic.w r2, r2, #1024 @ 0x400 8008f7e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8008f80: 68fb ldr r3, [r7, #12] 8008f82: 681b ldr r3, [r3, #0] 8008f84: 6999 ldr r1, [r3, #24] 8008f86: 68bb ldr r3, [r7, #8] 8008f88: 691b ldr r3, [r3, #16] 8008f8a: 021a lsls r2, r3, #8 8008f8c: 68fb ldr r3, [r7, #12] 8008f8e: 681b ldr r3, [r3, #0] 8008f90: 430a orrs r2, r1 8008f92: 619a str r2, [r3, #24] break; 8008f94: e043 b.n 800901e { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8008f96: 68fb ldr r3, [r7, #12] 8008f98: 681b ldr r3, [r3, #0] 8008f9a: 68b9 ldr r1, [r7, #8] 8008f9c: 4618 mov r0, r3 8008f9e: f000 fa75 bl 800948c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8008fa2: 68fb ldr r3, [r7, #12] 8008fa4: 681b ldr r3, [r3, #0] 8008fa6: 69da ldr r2, [r3, #28] 8008fa8: 68fb ldr r3, [r7, #12] 8008faa: 681b ldr r3, [r3, #0] 8008fac: f042 0208 orr.w r2, r2, #8 8008fb0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8008fb2: 68fb ldr r3, [r7, #12] 8008fb4: 681b ldr r3, [r3, #0] 8008fb6: 69da ldr r2, [r3, #28] 8008fb8: 68fb ldr r3, [r7, #12] 8008fba: 681b ldr r3, [r3, #0] 8008fbc: f022 0204 bic.w r2, r2, #4 8008fc0: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8008fc2: 68fb ldr r3, [r7, #12] 8008fc4: 681b ldr r3, [r3, #0] 8008fc6: 69d9 ldr r1, [r3, #28] 8008fc8: 68bb ldr r3, [r7, #8] 8008fca: 691a ldr r2, [r3, #16] 8008fcc: 68fb ldr r3, [r7, #12] 8008fce: 681b ldr r3, [r3, #0] 8008fd0: 430a orrs r2, r1 8008fd2: 61da str r2, [r3, #28] break; 8008fd4: e023 b.n 800901e { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8008fd6: 68fb ldr r3, [r7, #12] 8008fd8: 681b ldr r3, [r3, #0] 8008fda: 68b9 ldr r1, [r7, #8] 8008fdc: 4618 mov r0, r3 8008fde: f000 fabf bl 8009560 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8008fe2: 68fb ldr r3, [r7, #12] 8008fe4: 681b ldr r3, [r3, #0] 8008fe6: 69da ldr r2, [r3, #28] 8008fe8: 68fb ldr r3, [r7, #12] 8008fea: 681b ldr r3, [r3, #0] 8008fec: f442 6200 orr.w r2, r2, #2048 @ 0x800 8008ff0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8008ff2: 68fb ldr r3, [r7, #12] 8008ff4: 681b ldr r3, [r3, #0] 8008ff6: 69da ldr r2, [r3, #28] 8008ff8: 68fb ldr r3, [r7, #12] 8008ffa: 681b ldr r3, [r3, #0] 8008ffc: f422 6280 bic.w r2, r2, #1024 @ 0x400 8009000: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8009002: 68fb ldr r3, [r7, #12] 8009004: 681b ldr r3, [r3, #0] 8009006: 69d9 ldr r1, [r3, #28] 8009008: 68bb ldr r3, [r7, #8] 800900a: 691b ldr r3, [r3, #16] 800900c: 021a lsls r2, r3, #8 800900e: 68fb ldr r3, [r7, #12] 8009010: 681b ldr r3, [r3, #0] 8009012: 430a orrs r2, r1 8009014: 61da str r2, [r3, #28] break; 8009016: e002 b.n 800901e } default: status = HAL_ERROR; 8009018: 2301 movs r3, #1 800901a: 75fb strb r3, [r7, #23] break; 800901c: bf00 nop } __HAL_UNLOCK(htim); 800901e: 68fb ldr r3, [r7, #12] 8009020: 2200 movs r2, #0 8009022: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8009026: 7dfb ldrb r3, [r7, #23] } 8009028: 4618 mov r0, r3 800902a: 3718 adds r7, #24 800902c: 46bd mov sp, r7 800902e: bd80 pop {r7, pc} 08009030 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8009030: b580 push {r7, lr} 8009032: b084 sub sp, #16 8009034: af00 add r7, sp, #0 8009036: 6078 str r0, [r7, #4] 8009038: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800903a: 2300 movs r3, #0 800903c: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800903e: 687b ldr r3, [r7, #4] 8009040: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8009044: 2b01 cmp r3, #1 8009046: d101 bne.n 800904c 8009048: 2302 movs r3, #2 800904a: e0b4 b.n 80091b6 800904c: 687b ldr r3, [r7, #4] 800904e: 2201 movs r2, #1 8009050: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8009054: 687b ldr r3, [r7, #4] 8009056: 2202 movs r2, #2 8009058: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800905c: 687b ldr r3, [r7, #4] 800905e: 681b ldr r3, [r3, #0] 8009060: 689b ldr r3, [r3, #8] 8009062: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8009064: 68bb ldr r3, [r7, #8] 8009066: f023 0377 bic.w r3, r3, #119 @ 0x77 800906a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800906c: 68bb ldr r3, [r7, #8] 800906e: f423 437f bic.w r3, r3, #65280 @ 0xff00 8009072: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8009074: 687b ldr r3, [r7, #4] 8009076: 681b ldr r3, [r3, #0] 8009078: 68ba ldr r2, [r7, #8] 800907a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800907c: 683b ldr r3, [r7, #0] 800907e: 681b ldr r3, [r3, #0] 8009080: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8009084: d03e beq.n 8009104 8009086: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800908a: f200 8087 bhi.w 800919c 800908e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8009092: f000 8086 beq.w 80091a2 8009096: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800909a: d87f bhi.n 800919c 800909c: 2b70 cmp r3, #112 @ 0x70 800909e: d01a beq.n 80090d6 80090a0: 2b70 cmp r3, #112 @ 0x70 80090a2: d87b bhi.n 800919c 80090a4: 2b60 cmp r3, #96 @ 0x60 80090a6: d050 beq.n 800914a 80090a8: 2b60 cmp r3, #96 @ 0x60 80090aa: d877 bhi.n 800919c 80090ac: 2b50 cmp r3, #80 @ 0x50 80090ae: d03c beq.n 800912a 80090b0: 2b50 cmp r3, #80 @ 0x50 80090b2: d873 bhi.n 800919c 80090b4: 2b40 cmp r3, #64 @ 0x40 80090b6: d058 beq.n 800916a 80090b8: 2b40 cmp r3, #64 @ 0x40 80090ba: d86f bhi.n 800919c 80090bc: 2b30 cmp r3, #48 @ 0x30 80090be: d064 beq.n 800918a 80090c0: 2b30 cmp r3, #48 @ 0x30 80090c2: d86b bhi.n 800919c 80090c4: 2b20 cmp r3, #32 80090c6: d060 beq.n 800918a 80090c8: 2b20 cmp r3, #32 80090ca: d867 bhi.n 800919c 80090cc: 2b00 cmp r3, #0 80090ce: d05c beq.n 800918a 80090d0: 2b10 cmp r3, #16 80090d2: d05a beq.n 800918a 80090d4: e062 b.n 800919c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80090d6: 687b ldr r3, [r7, #4] 80090d8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80090da: 683b ldr r3, [r7, #0] 80090dc: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80090de: 683b ldr r3, [r7, #0] 80090e0: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80090e2: 683b ldr r3, [r7, #0] 80090e4: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80090e6: f000 fb00 bl 80096ea /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80090ea: 687b ldr r3, [r7, #4] 80090ec: 681b ldr r3, [r3, #0] 80090ee: 689b ldr r3, [r3, #8] 80090f0: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80090f2: 68bb ldr r3, [r7, #8] 80090f4: f043 0377 orr.w r3, r3, #119 @ 0x77 80090f8: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80090fa: 687b ldr r3, [r7, #4] 80090fc: 681b ldr r3, [r3, #0] 80090fe: 68ba ldr r2, [r7, #8] 8009100: 609a str r2, [r3, #8] break; 8009102: e04f b.n 80091a4 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8009104: 687b ldr r3, [r7, #4] 8009106: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8009108: 683b ldr r3, [r7, #0] 800910a: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800910c: 683b ldr r3, [r7, #0] 800910e: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8009110: 683b ldr r3, [r7, #0] 8009112: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8009114: f000 fae9 bl 80096ea /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8009118: 687b ldr r3, [r7, #4] 800911a: 681b ldr r3, [r3, #0] 800911c: 689a ldr r2, [r3, #8] 800911e: 687b ldr r3, [r7, #4] 8009120: 681b ldr r3, [r3, #0] 8009122: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8009126: 609a str r2, [r3, #8] break; 8009128: e03c b.n 80091a4 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800912a: 687b ldr r3, [r7, #4] 800912c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800912e: 683b ldr r3, [r7, #0] 8009130: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8009132: 683b ldr r3, [r7, #0] 8009134: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8009136: 461a mov r2, r3 8009138: f000 fa60 bl 80095fc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800913c: 687b ldr r3, [r7, #4] 800913e: 681b ldr r3, [r3, #0] 8009140: 2150 movs r1, #80 @ 0x50 8009142: 4618 mov r0, r3 8009144: f000 fab7 bl 80096b6 break; 8009148: e02c b.n 80091a4 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800914a: 687b ldr r3, [r7, #4] 800914c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800914e: 683b ldr r3, [r7, #0] 8009150: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8009152: 683b ldr r3, [r7, #0] 8009154: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8009156: 461a mov r2, r3 8009158: f000 fa7e bl 8009658 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800915c: 687b ldr r3, [r7, #4] 800915e: 681b ldr r3, [r3, #0] 8009160: 2160 movs r1, #96 @ 0x60 8009162: 4618 mov r0, r3 8009164: f000 faa7 bl 80096b6 break; 8009168: e01c b.n 80091a4 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800916a: 687b ldr r3, [r7, #4] 800916c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800916e: 683b ldr r3, [r7, #0] 8009170: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8009172: 683b ldr r3, [r7, #0] 8009174: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8009176: 461a mov r2, r3 8009178: f000 fa40 bl 80095fc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800917c: 687b ldr r3, [r7, #4] 800917e: 681b ldr r3, [r3, #0] 8009180: 2140 movs r1, #64 @ 0x40 8009182: 4618 mov r0, r3 8009184: f000 fa97 bl 80096b6 break; 8009188: e00c b.n 80091a4 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800918a: 687b ldr r3, [r7, #4] 800918c: 681a ldr r2, [r3, #0] 800918e: 683b ldr r3, [r7, #0] 8009190: 681b ldr r3, [r3, #0] 8009192: 4619 mov r1, r3 8009194: 4610 mov r0, r2 8009196: f000 fa8e bl 80096b6 break; 800919a: e003 b.n 80091a4 } default: status = HAL_ERROR; 800919c: 2301 movs r3, #1 800919e: 73fb strb r3, [r7, #15] break; 80091a0: e000 b.n 80091a4 break; 80091a2: bf00 nop } htim->State = HAL_TIM_STATE_READY; 80091a4: 687b ldr r3, [r7, #4] 80091a6: 2201 movs r2, #1 80091a8: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80091ac: 687b ldr r3, [r7, #4] 80091ae: 2200 movs r2, #0 80091b0: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80091b4: 7bfb ldrb r3, [r7, #15] } 80091b6: 4618 mov r0, r3 80091b8: 3710 adds r7, #16 80091ba: 46bd mov sp, r7 80091bc: bd80 pop {r7, pc} 080091be : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 80091be: b480 push {r7} 80091c0: b085 sub sp, #20 80091c2: af00 add r7, sp, #0 80091c4: 6078 str r0, [r7, #4] 80091c6: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 80091c8: 683b ldr r3, [r7, #0] 80091ca: 2b00 cmp r3, #0 80091cc: d104 bne.n 80091d8 80091ce: 687b ldr r3, [r7, #4] 80091d0: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80091d4: b2db uxtb r3, r3 80091d6: e013 b.n 8009200 80091d8: 683b ldr r3, [r7, #0] 80091da: 2b04 cmp r3, #4 80091dc: d104 bne.n 80091e8 80091de: 687b ldr r3, [r7, #4] 80091e0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 80091e4: b2db uxtb r3, r3 80091e6: e00b b.n 8009200 80091e8: 683b ldr r3, [r7, #0] 80091ea: 2b08 cmp r3, #8 80091ec: d104 bne.n 80091f8 80091ee: 687b ldr r3, [r7, #4] 80091f0: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80091f4: b2db uxtb r3, r3 80091f6: e003 b.n 8009200 80091f8: 687b ldr r3, [r7, #4] 80091fa: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80091fe: b2db uxtb r3, r3 8009200: 73fb strb r3, [r7, #15] return channel_state; 8009202: 7bfb ldrb r3, [r7, #15] } 8009204: 4618 mov r0, r3 8009206: 3714 adds r7, #20 8009208: 46bd mov sp, r7 800920a: bc80 pop {r7} 800920c: 4770 bx lr ... 08009210 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8009210: b480 push {r7} 8009212: b085 sub sp, #20 8009214: af00 add r7, sp, #0 8009216: 6078 str r0, [r7, #4] 8009218: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800921a: 687b ldr r3, [r7, #4] 800921c: 681b ldr r3, [r3, #0] 800921e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009220: 687b ldr r3, [r7, #4] 8009222: 4a2f ldr r2, [pc, #188] @ (80092e0 ) 8009224: 4293 cmp r3, r2 8009226: d00b beq.n 8009240 8009228: 687b ldr r3, [r7, #4] 800922a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800922e: d007 beq.n 8009240 8009230: 687b ldr r3, [r7, #4] 8009232: 4a2c ldr r2, [pc, #176] @ (80092e4 ) 8009234: 4293 cmp r3, r2 8009236: d003 beq.n 8009240 8009238: 687b ldr r3, [r7, #4] 800923a: 4a2b ldr r2, [pc, #172] @ (80092e8 ) 800923c: 4293 cmp r3, r2 800923e: d108 bne.n 8009252 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8009240: 68fb ldr r3, [r7, #12] 8009242: f023 0370 bic.w r3, r3, #112 @ 0x70 8009246: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8009248: 683b ldr r3, [r7, #0] 800924a: 685b ldr r3, [r3, #4] 800924c: 68fa ldr r2, [r7, #12] 800924e: 4313 orrs r3, r2 8009250: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8009252: 687b ldr r3, [r7, #4] 8009254: 4a22 ldr r2, [pc, #136] @ (80092e0 ) 8009256: 4293 cmp r3, r2 8009258: d00b beq.n 8009272 800925a: 687b ldr r3, [r7, #4] 800925c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8009260: d007 beq.n 8009272 8009262: 687b ldr r3, [r7, #4] 8009264: 4a1f ldr r2, [pc, #124] @ (80092e4 ) 8009266: 4293 cmp r3, r2 8009268: d003 beq.n 8009272 800926a: 687b ldr r3, [r7, #4] 800926c: 4a1e ldr r2, [pc, #120] @ (80092e8 ) 800926e: 4293 cmp r3, r2 8009270: d108 bne.n 8009284 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8009272: 68fb ldr r3, [r7, #12] 8009274: f423 7340 bic.w r3, r3, #768 @ 0x300 8009278: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800927a: 683b ldr r3, [r7, #0] 800927c: 68db ldr r3, [r3, #12] 800927e: 68fa ldr r2, [r7, #12] 8009280: 4313 orrs r3, r2 8009282: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009284: 68fb ldr r3, [r7, #12] 8009286: f023 0280 bic.w r2, r3, #128 @ 0x80 800928a: 683b ldr r3, [r7, #0] 800928c: 695b ldr r3, [r3, #20] 800928e: 4313 orrs r3, r2 8009290: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8009292: 687b ldr r3, [r7, #4] 8009294: 68fa ldr r2, [r7, #12] 8009296: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8009298: 683b ldr r3, [r7, #0] 800929a: 689a ldr r2, [r3, #8] 800929c: 687b ldr r3, [r7, #4] 800929e: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80092a0: 683b ldr r3, [r7, #0] 80092a2: 681a ldr r2, [r3, #0] 80092a4: 687b ldr r3, [r7, #4] 80092a6: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80092a8: 687b ldr r3, [r7, #4] 80092aa: 4a0d ldr r2, [pc, #52] @ (80092e0 ) 80092ac: 4293 cmp r3, r2 80092ae: d103 bne.n 80092b8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80092b0: 683b ldr r3, [r7, #0] 80092b2: 691a ldr r2, [r3, #16] 80092b4: 687b ldr r3, [r7, #4] 80092b6: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80092b8: 687b ldr r3, [r7, #4] 80092ba: 2201 movs r2, #1 80092bc: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80092be: 687b ldr r3, [r7, #4] 80092c0: 691b ldr r3, [r3, #16] 80092c2: f003 0301 and.w r3, r3, #1 80092c6: 2b00 cmp r3, #0 80092c8: d005 beq.n 80092d6 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80092ca: 687b ldr r3, [r7, #4] 80092cc: 691b ldr r3, [r3, #16] 80092ce: f023 0201 bic.w r2, r3, #1 80092d2: 687b ldr r3, [r7, #4] 80092d4: 611a str r2, [r3, #16] } } 80092d6: bf00 nop 80092d8: 3714 adds r7, #20 80092da: 46bd mov sp, r7 80092dc: bc80 pop {r7} 80092de: 4770 bx lr 80092e0: 40012c00 .word 0x40012c00 80092e4: 40000400 .word 0x40000400 80092e8: 40000800 .word 0x40000800 080092ec : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80092ec: b480 push {r7} 80092ee: b087 sub sp, #28 80092f0: af00 add r7, sp, #0 80092f2: 6078 str r0, [r7, #4] 80092f4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80092f6: 687b ldr r3, [r7, #4] 80092f8: 6a1b ldr r3, [r3, #32] 80092fa: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80092fc: 687b ldr r3, [r7, #4] 80092fe: 6a1b ldr r3, [r3, #32] 8009300: f023 0201 bic.w r2, r3, #1 8009304: 687b ldr r3, [r7, #4] 8009306: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8009308: 687b ldr r3, [r7, #4] 800930a: 685b ldr r3, [r3, #4] 800930c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800930e: 687b ldr r3, [r7, #4] 8009310: 699b ldr r3, [r3, #24] 8009312: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8009314: 68fb ldr r3, [r7, #12] 8009316: f023 0370 bic.w r3, r3, #112 @ 0x70 800931a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800931c: 68fb ldr r3, [r7, #12] 800931e: f023 0303 bic.w r3, r3, #3 8009322: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8009324: 683b ldr r3, [r7, #0] 8009326: 681b ldr r3, [r3, #0] 8009328: 68fa ldr r2, [r7, #12] 800932a: 4313 orrs r3, r2 800932c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800932e: 697b ldr r3, [r7, #20] 8009330: f023 0302 bic.w r3, r3, #2 8009334: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8009336: 683b ldr r3, [r7, #0] 8009338: 689b ldr r3, [r3, #8] 800933a: 697a ldr r2, [r7, #20] 800933c: 4313 orrs r3, r2 800933e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8009340: 687b ldr r3, [r7, #4] 8009342: 4a1c ldr r2, [pc, #112] @ (80093b4 ) 8009344: 4293 cmp r3, r2 8009346: d10c bne.n 8009362 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8009348: 697b ldr r3, [r7, #20] 800934a: f023 0308 bic.w r3, r3, #8 800934e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8009350: 683b ldr r3, [r7, #0] 8009352: 68db ldr r3, [r3, #12] 8009354: 697a ldr r2, [r7, #20] 8009356: 4313 orrs r3, r2 8009358: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800935a: 697b ldr r3, [r7, #20] 800935c: f023 0304 bic.w r3, r3, #4 8009360: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8009362: 687b ldr r3, [r7, #4] 8009364: 4a13 ldr r2, [pc, #76] @ (80093b4 ) 8009366: 4293 cmp r3, r2 8009368: d111 bne.n 800938e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800936a: 693b ldr r3, [r7, #16] 800936c: f423 7380 bic.w r3, r3, #256 @ 0x100 8009370: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8009372: 693b ldr r3, [r7, #16] 8009374: f423 7300 bic.w r3, r3, #512 @ 0x200 8009378: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800937a: 683b ldr r3, [r7, #0] 800937c: 695b ldr r3, [r3, #20] 800937e: 693a ldr r2, [r7, #16] 8009380: 4313 orrs r3, r2 8009382: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8009384: 683b ldr r3, [r7, #0] 8009386: 699b ldr r3, [r3, #24] 8009388: 693a ldr r2, [r7, #16] 800938a: 4313 orrs r3, r2 800938c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800938e: 687b ldr r3, [r7, #4] 8009390: 693a ldr r2, [r7, #16] 8009392: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8009394: 687b ldr r3, [r7, #4] 8009396: 68fa ldr r2, [r7, #12] 8009398: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800939a: 683b ldr r3, [r7, #0] 800939c: 685a ldr r2, [r3, #4] 800939e: 687b ldr r3, [r7, #4] 80093a0: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80093a2: 687b ldr r3, [r7, #4] 80093a4: 697a ldr r2, [r7, #20] 80093a6: 621a str r2, [r3, #32] } 80093a8: bf00 nop 80093aa: 371c adds r7, #28 80093ac: 46bd mov sp, r7 80093ae: bc80 pop {r7} 80093b0: 4770 bx lr 80093b2: bf00 nop 80093b4: 40012c00 .word 0x40012c00 080093b8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80093b8: b480 push {r7} 80093ba: b087 sub sp, #28 80093bc: af00 add r7, sp, #0 80093be: 6078 str r0, [r7, #4] 80093c0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80093c2: 687b ldr r3, [r7, #4] 80093c4: 6a1b ldr r3, [r3, #32] 80093c6: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80093c8: 687b ldr r3, [r7, #4] 80093ca: 6a1b ldr r3, [r3, #32] 80093cc: f023 0210 bic.w r2, r3, #16 80093d0: 687b ldr r3, [r7, #4] 80093d2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80093d4: 687b ldr r3, [r7, #4] 80093d6: 685b ldr r3, [r3, #4] 80093d8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80093da: 687b ldr r3, [r7, #4] 80093dc: 699b ldr r3, [r3, #24] 80093de: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80093e0: 68fb ldr r3, [r7, #12] 80093e2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80093e6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80093e8: 68fb ldr r3, [r7, #12] 80093ea: f423 7340 bic.w r3, r3, #768 @ 0x300 80093ee: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80093f0: 683b ldr r3, [r7, #0] 80093f2: 681b ldr r3, [r3, #0] 80093f4: 021b lsls r3, r3, #8 80093f6: 68fa ldr r2, [r7, #12] 80093f8: 4313 orrs r3, r2 80093fa: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80093fc: 697b ldr r3, [r7, #20] 80093fe: f023 0320 bic.w r3, r3, #32 8009402: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8009404: 683b ldr r3, [r7, #0] 8009406: 689b ldr r3, [r3, #8] 8009408: 011b lsls r3, r3, #4 800940a: 697a ldr r2, [r7, #20] 800940c: 4313 orrs r3, r2 800940e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8009410: 687b ldr r3, [r7, #4] 8009412: 4a1d ldr r2, [pc, #116] @ (8009488 ) 8009414: 4293 cmp r3, r2 8009416: d10d bne.n 8009434 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8009418: 697b ldr r3, [r7, #20] 800941a: f023 0380 bic.w r3, r3, #128 @ 0x80 800941e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8009420: 683b ldr r3, [r7, #0] 8009422: 68db ldr r3, [r3, #12] 8009424: 011b lsls r3, r3, #4 8009426: 697a ldr r2, [r7, #20] 8009428: 4313 orrs r3, r2 800942a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 800942c: 697b ldr r3, [r7, #20] 800942e: f023 0340 bic.w r3, r3, #64 @ 0x40 8009432: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8009434: 687b ldr r3, [r7, #4] 8009436: 4a14 ldr r2, [pc, #80] @ (8009488 ) 8009438: 4293 cmp r3, r2 800943a: d113 bne.n 8009464 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800943c: 693b ldr r3, [r7, #16] 800943e: f423 6380 bic.w r3, r3, #1024 @ 0x400 8009442: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8009444: 693b ldr r3, [r7, #16] 8009446: f423 6300 bic.w r3, r3, #2048 @ 0x800 800944a: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 800944c: 683b ldr r3, [r7, #0] 800944e: 695b ldr r3, [r3, #20] 8009450: 009b lsls r3, r3, #2 8009452: 693a ldr r2, [r7, #16] 8009454: 4313 orrs r3, r2 8009456: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8009458: 683b ldr r3, [r7, #0] 800945a: 699b ldr r3, [r3, #24] 800945c: 009b lsls r3, r3, #2 800945e: 693a ldr r2, [r7, #16] 8009460: 4313 orrs r3, r2 8009462: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8009464: 687b ldr r3, [r7, #4] 8009466: 693a ldr r2, [r7, #16] 8009468: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800946a: 687b ldr r3, [r7, #4] 800946c: 68fa ldr r2, [r7, #12] 800946e: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8009470: 683b ldr r3, [r7, #0] 8009472: 685a ldr r2, [r3, #4] 8009474: 687b ldr r3, [r7, #4] 8009476: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8009478: 687b ldr r3, [r7, #4] 800947a: 697a ldr r2, [r7, #20] 800947c: 621a str r2, [r3, #32] } 800947e: bf00 nop 8009480: 371c adds r7, #28 8009482: 46bd mov sp, r7 8009484: bc80 pop {r7} 8009486: 4770 bx lr 8009488: 40012c00 .word 0x40012c00 0800948c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800948c: b480 push {r7} 800948e: b087 sub sp, #28 8009490: af00 add r7, sp, #0 8009492: 6078 str r0, [r7, #4] 8009494: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8009496: 687b ldr r3, [r7, #4] 8009498: 6a1b ldr r3, [r3, #32] 800949a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 800949c: 687b ldr r3, [r7, #4] 800949e: 6a1b ldr r3, [r3, #32] 80094a0: f423 7280 bic.w r2, r3, #256 @ 0x100 80094a4: 687b ldr r3, [r7, #4] 80094a6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80094a8: 687b ldr r3, [r7, #4] 80094aa: 685b ldr r3, [r3, #4] 80094ac: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80094ae: 687b ldr r3, [r7, #4] 80094b0: 69db ldr r3, [r3, #28] 80094b2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80094b4: 68fb ldr r3, [r7, #12] 80094b6: f023 0370 bic.w r3, r3, #112 @ 0x70 80094ba: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80094bc: 68fb ldr r3, [r7, #12] 80094be: f023 0303 bic.w r3, r3, #3 80094c2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80094c4: 683b ldr r3, [r7, #0] 80094c6: 681b ldr r3, [r3, #0] 80094c8: 68fa ldr r2, [r7, #12] 80094ca: 4313 orrs r3, r2 80094cc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80094ce: 697b ldr r3, [r7, #20] 80094d0: f423 7300 bic.w r3, r3, #512 @ 0x200 80094d4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80094d6: 683b ldr r3, [r7, #0] 80094d8: 689b ldr r3, [r3, #8] 80094da: 021b lsls r3, r3, #8 80094dc: 697a ldr r2, [r7, #20] 80094de: 4313 orrs r3, r2 80094e0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80094e2: 687b ldr r3, [r7, #4] 80094e4: 4a1d ldr r2, [pc, #116] @ (800955c ) 80094e6: 4293 cmp r3, r2 80094e8: d10d bne.n 8009506 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80094ea: 697b ldr r3, [r7, #20] 80094ec: f423 6300 bic.w r3, r3, #2048 @ 0x800 80094f0: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80094f2: 683b ldr r3, [r7, #0] 80094f4: 68db ldr r3, [r3, #12] 80094f6: 021b lsls r3, r3, #8 80094f8: 697a ldr r2, [r7, #20] 80094fa: 4313 orrs r3, r2 80094fc: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80094fe: 697b ldr r3, [r7, #20] 8009500: f423 6380 bic.w r3, r3, #1024 @ 0x400 8009504: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8009506: 687b ldr r3, [r7, #4] 8009508: 4a14 ldr r2, [pc, #80] @ (800955c ) 800950a: 4293 cmp r3, r2 800950c: d113 bne.n 8009536 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800950e: 693b ldr r3, [r7, #16] 8009510: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8009514: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8009516: 693b ldr r3, [r7, #16] 8009518: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800951c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800951e: 683b ldr r3, [r7, #0] 8009520: 695b ldr r3, [r3, #20] 8009522: 011b lsls r3, r3, #4 8009524: 693a ldr r2, [r7, #16] 8009526: 4313 orrs r3, r2 8009528: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800952a: 683b ldr r3, [r7, #0] 800952c: 699b ldr r3, [r3, #24] 800952e: 011b lsls r3, r3, #4 8009530: 693a ldr r2, [r7, #16] 8009532: 4313 orrs r3, r2 8009534: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8009536: 687b ldr r3, [r7, #4] 8009538: 693a ldr r2, [r7, #16] 800953a: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800953c: 687b ldr r3, [r7, #4] 800953e: 68fa ldr r2, [r7, #12] 8009540: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8009542: 683b ldr r3, [r7, #0] 8009544: 685a ldr r2, [r3, #4] 8009546: 687b ldr r3, [r7, #4] 8009548: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800954a: 687b ldr r3, [r7, #4] 800954c: 697a ldr r2, [r7, #20] 800954e: 621a str r2, [r3, #32] } 8009550: bf00 nop 8009552: 371c adds r7, #28 8009554: 46bd mov sp, r7 8009556: bc80 pop {r7} 8009558: 4770 bx lr 800955a: bf00 nop 800955c: 40012c00 .word 0x40012c00 08009560 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8009560: b480 push {r7} 8009562: b087 sub sp, #28 8009564: af00 add r7, sp, #0 8009566: 6078 str r0, [r7, #4] 8009568: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800956a: 687b ldr r3, [r7, #4] 800956c: 6a1b ldr r3, [r3, #32] 800956e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8009570: 687b ldr r3, [r7, #4] 8009572: 6a1b ldr r3, [r3, #32] 8009574: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8009578: 687b ldr r3, [r7, #4] 800957a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800957c: 687b ldr r3, [r7, #4] 800957e: 685b ldr r3, [r3, #4] 8009580: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8009582: 687b ldr r3, [r7, #4] 8009584: 69db ldr r3, [r3, #28] 8009586: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8009588: 68fb ldr r3, [r7, #12] 800958a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800958e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8009590: 68fb ldr r3, [r7, #12] 8009592: f423 7340 bic.w r3, r3, #768 @ 0x300 8009596: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8009598: 683b ldr r3, [r7, #0] 800959a: 681b ldr r3, [r3, #0] 800959c: 021b lsls r3, r3, #8 800959e: 68fa ldr r2, [r7, #12] 80095a0: 4313 orrs r3, r2 80095a2: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80095a4: 693b ldr r3, [r7, #16] 80095a6: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80095aa: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80095ac: 683b ldr r3, [r7, #0] 80095ae: 689b ldr r3, [r3, #8] 80095b0: 031b lsls r3, r3, #12 80095b2: 693a ldr r2, [r7, #16] 80095b4: 4313 orrs r3, r2 80095b6: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80095b8: 687b ldr r3, [r7, #4] 80095ba: 4a0f ldr r2, [pc, #60] @ (80095f8 ) 80095bc: 4293 cmp r3, r2 80095be: d109 bne.n 80095d4 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80095c0: 697b ldr r3, [r7, #20] 80095c2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80095c6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80095c8: 683b ldr r3, [r7, #0] 80095ca: 695b ldr r3, [r3, #20] 80095cc: 019b lsls r3, r3, #6 80095ce: 697a ldr r2, [r7, #20] 80095d0: 4313 orrs r3, r2 80095d2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80095d4: 687b ldr r3, [r7, #4] 80095d6: 697a ldr r2, [r7, #20] 80095d8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80095da: 687b ldr r3, [r7, #4] 80095dc: 68fa ldr r2, [r7, #12] 80095de: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 80095e0: 683b ldr r3, [r7, #0] 80095e2: 685a ldr r2, [r3, #4] 80095e4: 687b ldr r3, [r7, #4] 80095e6: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80095e8: 687b ldr r3, [r7, #4] 80095ea: 693a ldr r2, [r7, #16] 80095ec: 621a str r2, [r3, #32] } 80095ee: bf00 nop 80095f0: 371c adds r7, #28 80095f2: 46bd mov sp, r7 80095f4: bc80 pop {r7} 80095f6: 4770 bx lr 80095f8: 40012c00 .word 0x40012c00 080095fc : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80095fc: b480 push {r7} 80095fe: b087 sub sp, #28 8009600: af00 add r7, sp, #0 8009602: 60f8 str r0, [r7, #12] 8009604: 60b9 str r1, [r7, #8] 8009606: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8009608: 68fb ldr r3, [r7, #12] 800960a: 6a1b ldr r3, [r3, #32] 800960c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 800960e: 68fb ldr r3, [r7, #12] 8009610: 6a1b ldr r3, [r3, #32] 8009612: f023 0201 bic.w r2, r3, #1 8009616: 68fb ldr r3, [r7, #12] 8009618: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 800961a: 68fb ldr r3, [r7, #12] 800961c: 699b ldr r3, [r3, #24] 800961e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8009620: 693b ldr r3, [r7, #16] 8009622: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8009626: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8009628: 687b ldr r3, [r7, #4] 800962a: 011b lsls r3, r3, #4 800962c: 693a ldr r2, [r7, #16] 800962e: 4313 orrs r3, r2 8009630: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8009632: 697b ldr r3, [r7, #20] 8009634: f023 030a bic.w r3, r3, #10 8009638: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 800963a: 697a ldr r2, [r7, #20] 800963c: 68bb ldr r3, [r7, #8] 800963e: 4313 orrs r3, r2 8009640: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8009642: 68fb ldr r3, [r7, #12] 8009644: 693a ldr r2, [r7, #16] 8009646: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8009648: 68fb ldr r3, [r7, #12] 800964a: 697a ldr r2, [r7, #20] 800964c: 621a str r2, [r3, #32] } 800964e: bf00 nop 8009650: 371c adds r7, #28 8009652: 46bd mov sp, r7 8009654: bc80 pop {r7} 8009656: 4770 bx lr 08009658 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8009658: b480 push {r7} 800965a: b087 sub sp, #28 800965c: af00 add r7, sp, #0 800965e: 60f8 str r0, [r7, #12] 8009660: 60b9 str r1, [r7, #8] 8009662: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8009664: 68fb ldr r3, [r7, #12] 8009666: 6a1b ldr r3, [r3, #32] 8009668: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 800966a: 68fb ldr r3, [r7, #12] 800966c: 6a1b ldr r3, [r3, #32] 800966e: f023 0210 bic.w r2, r3, #16 8009672: 68fb ldr r3, [r7, #12] 8009674: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8009676: 68fb ldr r3, [r7, #12] 8009678: 699b ldr r3, [r3, #24] 800967a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 800967c: 693b ldr r3, [r7, #16] 800967e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8009682: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8009684: 687b ldr r3, [r7, #4] 8009686: 031b lsls r3, r3, #12 8009688: 693a ldr r2, [r7, #16] 800968a: 4313 orrs r3, r2 800968c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 800968e: 697b ldr r3, [r7, #20] 8009690: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8009694: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8009696: 68bb ldr r3, [r7, #8] 8009698: 011b lsls r3, r3, #4 800969a: 697a ldr r2, [r7, #20] 800969c: 4313 orrs r3, r2 800969e: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80096a0: 68fb ldr r3, [r7, #12] 80096a2: 693a ldr r2, [r7, #16] 80096a4: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80096a6: 68fb ldr r3, [r7, #12] 80096a8: 697a ldr r2, [r7, #20] 80096aa: 621a str r2, [r3, #32] } 80096ac: bf00 nop 80096ae: 371c adds r7, #28 80096b0: 46bd mov sp, r7 80096b2: bc80 pop {r7} 80096b4: 4770 bx lr 080096b6 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80096b6: b480 push {r7} 80096b8: b085 sub sp, #20 80096ba: af00 add r7, sp, #0 80096bc: 6078 str r0, [r7, #4] 80096be: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80096c0: 687b ldr r3, [r7, #4] 80096c2: 689b ldr r3, [r3, #8] 80096c4: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80096c6: 68fb ldr r3, [r7, #12] 80096c8: f023 0370 bic.w r3, r3, #112 @ 0x70 80096cc: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80096ce: 683a ldr r2, [r7, #0] 80096d0: 68fb ldr r3, [r7, #12] 80096d2: 4313 orrs r3, r2 80096d4: f043 0307 orr.w r3, r3, #7 80096d8: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80096da: 687b ldr r3, [r7, #4] 80096dc: 68fa ldr r2, [r7, #12] 80096de: 609a str r2, [r3, #8] } 80096e0: bf00 nop 80096e2: 3714 adds r7, #20 80096e4: 46bd mov sp, r7 80096e6: bc80 pop {r7} 80096e8: 4770 bx lr 080096ea : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80096ea: b480 push {r7} 80096ec: b087 sub sp, #28 80096ee: af00 add r7, sp, #0 80096f0: 60f8 str r0, [r7, #12] 80096f2: 60b9 str r1, [r7, #8] 80096f4: 607a str r2, [r7, #4] 80096f6: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80096f8: 68fb ldr r3, [r7, #12] 80096fa: 689b ldr r3, [r3, #8] 80096fc: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80096fe: 697b ldr r3, [r7, #20] 8009700: f423 437f bic.w r3, r3, #65280 @ 0xff00 8009704: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8009706: 683b ldr r3, [r7, #0] 8009708: 021a lsls r2, r3, #8 800970a: 687b ldr r3, [r7, #4] 800970c: 431a orrs r2, r3 800970e: 68bb ldr r3, [r7, #8] 8009710: 4313 orrs r3, r2 8009712: 697a ldr r2, [r7, #20] 8009714: 4313 orrs r3, r2 8009716: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8009718: 68fb ldr r3, [r7, #12] 800971a: 697a ldr r2, [r7, #20] 800971c: 609a str r2, [r3, #8] } 800971e: bf00 nop 8009720: 371c adds r7, #28 8009722: 46bd mov sp, r7 8009724: bc80 pop {r7} 8009726: 4770 bx lr 08009728 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8009728: b480 push {r7} 800972a: b087 sub sp, #28 800972c: af00 add r7, sp, #0 800972e: 60f8 str r0, [r7, #12] 8009730: 60b9 str r1, [r7, #8] 8009732: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8009734: 68bb ldr r3, [r7, #8] 8009736: f003 031f and.w r3, r3, #31 800973a: 2201 movs r2, #1 800973c: fa02 f303 lsl.w r3, r2, r3 8009740: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8009742: 68fb ldr r3, [r7, #12] 8009744: 6a1a ldr r2, [r3, #32] 8009746: 697b ldr r3, [r7, #20] 8009748: 43db mvns r3, r3 800974a: 401a ands r2, r3 800974c: 68fb ldr r3, [r7, #12] 800974e: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8009750: 68fb ldr r3, [r7, #12] 8009752: 6a1a ldr r2, [r3, #32] 8009754: 68bb ldr r3, [r7, #8] 8009756: f003 031f and.w r3, r3, #31 800975a: 6879 ldr r1, [r7, #4] 800975c: fa01 f303 lsl.w r3, r1, r3 8009760: 431a orrs r2, r3 8009762: 68fb ldr r3, [r7, #12] 8009764: 621a str r2, [r3, #32] } 8009766: bf00 nop 8009768: 371c adds r7, #28 800976a: 46bd mov sp, r7 800976c: bc80 pop {r7} 800976e: 4770 bx lr 08009770 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8009770: b480 push {r7} 8009772: b085 sub sp, #20 8009774: af00 add r7, sp, #0 8009776: 6078 str r0, [r7, #4] 8009778: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800977a: 687b ldr r3, [r7, #4] 800977c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8009780: 2b01 cmp r3, #1 8009782: d101 bne.n 8009788 8009784: 2302 movs r3, #2 8009786: e046 b.n 8009816 8009788: 687b ldr r3, [r7, #4] 800978a: 2201 movs r2, #1 800978c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8009790: 687b ldr r3, [r7, #4] 8009792: 2202 movs r2, #2 8009794: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8009798: 687b ldr r3, [r7, #4] 800979a: 681b ldr r3, [r3, #0] 800979c: 685b ldr r3, [r3, #4] 800979e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80097a0: 687b ldr r3, [r7, #4] 80097a2: 681b ldr r3, [r3, #0] 80097a4: 689b ldr r3, [r3, #8] 80097a6: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80097a8: 68fb ldr r3, [r7, #12] 80097aa: f023 0370 bic.w r3, r3, #112 @ 0x70 80097ae: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80097b0: 683b ldr r3, [r7, #0] 80097b2: 681b ldr r3, [r3, #0] 80097b4: 68fa ldr r2, [r7, #12] 80097b6: 4313 orrs r3, r2 80097b8: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80097ba: 687b ldr r3, [r7, #4] 80097bc: 681b ldr r3, [r3, #0] 80097be: 68fa ldr r2, [r7, #12] 80097c0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80097c2: 687b ldr r3, [r7, #4] 80097c4: 681b ldr r3, [r3, #0] 80097c6: 4a16 ldr r2, [pc, #88] @ (8009820 ) 80097c8: 4293 cmp r3, r2 80097ca: d00e beq.n 80097ea 80097cc: 687b ldr r3, [r7, #4] 80097ce: 681b ldr r3, [r3, #0] 80097d0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80097d4: d009 beq.n 80097ea 80097d6: 687b ldr r3, [r7, #4] 80097d8: 681b ldr r3, [r3, #0] 80097da: 4a12 ldr r2, [pc, #72] @ (8009824 ) 80097dc: 4293 cmp r3, r2 80097de: d004 beq.n 80097ea 80097e0: 687b ldr r3, [r7, #4] 80097e2: 681b ldr r3, [r3, #0] 80097e4: 4a10 ldr r2, [pc, #64] @ (8009828 ) 80097e6: 4293 cmp r3, r2 80097e8: d10c bne.n 8009804 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80097ea: 68bb ldr r3, [r7, #8] 80097ec: f023 0380 bic.w r3, r3, #128 @ 0x80 80097f0: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80097f2: 683b ldr r3, [r7, #0] 80097f4: 685b ldr r3, [r3, #4] 80097f6: 68ba ldr r2, [r7, #8] 80097f8: 4313 orrs r3, r2 80097fa: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80097fc: 687b ldr r3, [r7, #4] 80097fe: 681b ldr r3, [r3, #0] 8009800: 68ba ldr r2, [r7, #8] 8009802: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8009804: 687b ldr r3, [r7, #4] 8009806: 2201 movs r2, #1 8009808: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800980c: 687b ldr r3, [r7, #4] 800980e: 2200 movs r2, #0 8009810: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8009814: 2300 movs r3, #0 } 8009816: 4618 mov r0, r3 8009818: 3714 adds r7, #20 800981a: 46bd mov sp, r7 800981c: bc80 pop {r7} 800981e: 4770 bx lr 8009820: 40012c00 .word 0x40012c00 8009824: 40000400 .word 0x40000400 8009828: 40000800 .word 0x40000800 0800982c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800982c: b580 push {r7, lr} 800982e: b082 sub sp, #8 8009830: af00 add r7, sp, #0 8009832: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8009834: 687b ldr r3, [r7, #4] 8009836: 2b00 cmp r3, #0 8009838: d101 bne.n 800983e { return HAL_ERROR; 800983a: 2301 movs r3, #1 800983c: e042 b.n 80098c4 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 800983e: 687b ldr r3, [r7, #4] 8009840: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8009844: b2db uxtb r3, r3 8009846: 2b00 cmp r3, #0 8009848: d106 bne.n 8009858 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800984a: 687b ldr r3, [r7, #4] 800984c: 2200 movs r2, #0 800984e: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8009852: 6878 ldr r0, [r7, #4] 8009854: f7fb fb80 bl 8004f58 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8009858: 687b ldr r3, [r7, #4] 800985a: 2224 movs r2, #36 @ 0x24 800985c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8009860: 687b ldr r3, [r7, #4] 8009862: 681b ldr r3, [r3, #0] 8009864: 68da ldr r2, [r3, #12] 8009866: 687b ldr r3, [r7, #4] 8009868: 681b ldr r3, [r3, #0] 800986a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800986e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8009870: 6878 ldr r0, [r7, #4] 8009872: f000 f971 bl 8009b58 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8009876: 687b ldr r3, [r7, #4] 8009878: 681b ldr r3, [r3, #0] 800987a: 691a ldr r2, [r3, #16] 800987c: 687b ldr r3, [r7, #4] 800987e: 681b ldr r3, [r3, #0] 8009880: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8009884: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8009886: 687b ldr r3, [r7, #4] 8009888: 681b ldr r3, [r3, #0] 800988a: 695a ldr r2, [r3, #20] 800988c: 687b ldr r3, [r7, #4] 800988e: 681b ldr r3, [r3, #0] 8009890: f022 022a bic.w r2, r2, #42 @ 0x2a 8009894: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8009896: 687b ldr r3, [r7, #4] 8009898: 681b ldr r3, [r3, #0] 800989a: 68da ldr r2, [r3, #12] 800989c: 687b ldr r3, [r7, #4] 800989e: 681b ldr r3, [r3, #0] 80098a0: f442 5200 orr.w r2, r2, #8192 @ 0x2000 80098a4: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80098a6: 687b ldr r3, [r7, #4] 80098a8: 2200 movs r2, #0 80098aa: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 80098ac: 687b ldr r3, [r7, #4] 80098ae: 2220 movs r2, #32 80098b0: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80098b4: 687b ldr r3, [r7, #4] 80098b6: 2220 movs r2, #32 80098b8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 80098bc: 687b ldr r3, [r7, #4] 80098be: 2200 movs r2, #0 80098c0: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 80098c2: 2300 movs r3, #0 } 80098c4: 4618 mov r0, r3 80098c6: 3708 adds r7, #8 80098c8: 46bd mov sp, r7 80098ca: bd80 pop {r7, pc} 080098cc : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80098cc: b580 push {r7, lr} 80098ce: b08a sub sp, #40 @ 0x28 80098d0: af02 add r7, sp, #8 80098d2: 60f8 str r0, [r7, #12] 80098d4: 60b9 str r1, [r7, #8] 80098d6: 603b str r3, [r7, #0] 80098d8: 4613 mov r3, r2 80098da: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 80098dc: 2300 movs r3, #0 80098de: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80098e0: 68fb ldr r3, [r7, #12] 80098e2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80098e6: b2db uxtb r3, r3 80098e8: 2b20 cmp r3, #32 80098ea: d175 bne.n 80099d8 { if ((pData == NULL) || (Size == 0U)) 80098ec: 68bb ldr r3, [r7, #8] 80098ee: 2b00 cmp r3, #0 80098f0: d002 beq.n 80098f8 80098f2: 88fb ldrh r3, [r7, #6] 80098f4: 2b00 cmp r3, #0 80098f6: d101 bne.n 80098fc { return HAL_ERROR; 80098f8: 2301 movs r3, #1 80098fa: e06e b.n 80099da } huart->ErrorCode = HAL_UART_ERROR_NONE; 80098fc: 68fb ldr r3, [r7, #12] 80098fe: 2200 movs r2, #0 8009900: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8009902: 68fb ldr r3, [r7, #12] 8009904: 2221 movs r2, #33 @ 0x21 8009906: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800990a: f7fb fc6d bl 80051e8 800990e: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8009910: 68fb ldr r3, [r7, #12] 8009912: 88fa ldrh r2, [r7, #6] 8009914: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8009916: 68fb ldr r3, [r7, #12] 8009918: 88fa ldrh r2, [r7, #6] 800991a: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800991c: 68fb ldr r3, [r7, #12] 800991e: 689b ldr r3, [r3, #8] 8009920: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8009924: d108 bne.n 8009938 8009926: 68fb ldr r3, [r7, #12] 8009928: 691b ldr r3, [r3, #16] 800992a: 2b00 cmp r3, #0 800992c: d104 bne.n 8009938 { pdata8bits = NULL; 800992e: 2300 movs r3, #0 8009930: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8009932: 68bb ldr r3, [r7, #8] 8009934: 61bb str r3, [r7, #24] 8009936: e003 b.n 8009940 } else { pdata8bits = pData; 8009938: 68bb ldr r3, [r7, #8] 800993a: 61fb str r3, [r7, #28] pdata16bits = NULL; 800993c: 2300 movs r3, #0 800993e: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8009940: e02e b.n 80099a0 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8009942: 683b ldr r3, [r7, #0] 8009944: 9300 str r3, [sp, #0] 8009946: 697b ldr r3, [r7, #20] 8009948: 2200 movs r2, #0 800994a: 2180 movs r1, #128 @ 0x80 800994c: 68f8 ldr r0, [r7, #12] 800994e: f000 f848 bl 80099e2 8009952: 4603 mov r3, r0 8009954: 2b00 cmp r3, #0 8009956: d005 beq.n 8009964 { huart->gState = HAL_UART_STATE_READY; 8009958: 68fb ldr r3, [r7, #12] 800995a: 2220 movs r2, #32 800995c: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8009960: 2303 movs r3, #3 8009962: e03a b.n 80099da } if (pdata8bits == NULL) 8009964: 69fb ldr r3, [r7, #28] 8009966: 2b00 cmp r3, #0 8009968: d10b bne.n 8009982 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 800996a: 69bb ldr r3, [r7, #24] 800996c: 881b ldrh r3, [r3, #0] 800996e: 461a mov r2, r3 8009970: 68fb ldr r3, [r7, #12] 8009972: 681b ldr r3, [r3, #0] 8009974: f3c2 0208 ubfx r2, r2, #0, #9 8009978: 605a str r2, [r3, #4] pdata16bits++; 800997a: 69bb ldr r3, [r7, #24] 800997c: 3302 adds r3, #2 800997e: 61bb str r3, [r7, #24] 8009980: e007 b.n 8009992 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8009982: 69fb ldr r3, [r7, #28] 8009984: 781a ldrb r2, [r3, #0] 8009986: 68fb ldr r3, [r7, #12] 8009988: 681b ldr r3, [r3, #0] 800998a: 605a str r2, [r3, #4] pdata8bits++; 800998c: 69fb ldr r3, [r7, #28] 800998e: 3301 adds r3, #1 8009990: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8009992: 68fb ldr r3, [r7, #12] 8009994: 8cdb ldrh r3, [r3, #38] @ 0x26 8009996: b29b uxth r3, r3 8009998: 3b01 subs r3, #1 800999a: b29a uxth r2, r3 800999c: 68fb ldr r3, [r7, #12] 800999e: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 80099a0: 68fb ldr r3, [r7, #12] 80099a2: 8cdb ldrh r3, [r3, #38] @ 0x26 80099a4: b29b uxth r3, r3 80099a6: 2b00 cmp r3, #0 80099a8: d1cb bne.n 8009942 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80099aa: 683b ldr r3, [r7, #0] 80099ac: 9300 str r3, [sp, #0] 80099ae: 697b ldr r3, [r7, #20] 80099b0: 2200 movs r2, #0 80099b2: 2140 movs r1, #64 @ 0x40 80099b4: 68f8 ldr r0, [r7, #12] 80099b6: f000 f814 bl 80099e2 80099ba: 4603 mov r3, r0 80099bc: 2b00 cmp r3, #0 80099be: d005 beq.n 80099cc { huart->gState = HAL_UART_STATE_READY; 80099c0: 68fb ldr r3, [r7, #12] 80099c2: 2220 movs r2, #32 80099c4: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 80099c8: 2303 movs r3, #3 80099ca: e006 b.n 80099da } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80099cc: 68fb ldr r3, [r7, #12] 80099ce: 2220 movs r2, #32 80099d0: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 80099d4: 2300 movs r3, #0 80099d6: e000 b.n 80099da } else { return HAL_BUSY; 80099d8: 2302 movs r3, #2 } } 80099da: 4618 mov r0, r3 80099dc: 3720 adds r7, #32 80099de: 46bd mov sp, r7 80099e0: bd80 pop {r7, pc} 080099e2 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80099e2: b580 push {r7, lr} 80099e4: b086 sub sp, #24 80099e6: af00 add r7, sp, #0 80099e8: 60f8 str r0, [r7, #12] 80099ea: 60b9 str r1, [r7, #8] 80099ec: 603b str r3, [r7, #0] 80099ee: 4613 mov r3, r2 80099f0: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80099f2: e03b b.n 8009a6c { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80099f4: 6a3b ldr r3, [r7, #32] 80099f6: f1b3 3fff cmp.w r3, #4294967295 80099fa: d037 beq.n 8009a6c { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80099fc: f7fb fbf4 bl 80051e8 8009a00: 4602 mov r2, r0 8009a02: 683b ldr r3, [r7, #0] 8009a04: 1ad3 subs r3, r2, r3 8009a06: 6a3a ldr r2, [r7, #32] 8009a08: 429a cmp r2, r3 8009a0a: d302 bcc.n 8009a12 8009a0c: 6a3b ldr r3, [r7, #32] 8009a0e: 2b00 cmp r3, #0 8009a10: d101 bne.n 8009a16 { return HAL_TIMEOUT; 8009a12: 2303 movs r3, #3 8009a14: e03a b.n 8009a8c } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8009a16: 68fb ldr r3, [r7, #12] 8009a18: 681b ldr r3, [r3, #0] 8009a1a: 68db ldr r3, [r3, #12] 8009a1c: f003 0304 and.w r3, r3, #4 8009a20: 2b00 cmp r3, #0 8009a22: d023 beq.n 8009a6c 8009a24: 68bb ldr r3, [r7, #8] 8009a26: 2b80 cmp r3, #128 @ 0x80 8009a28: d020 beq.n 8009a6c 8009a2a: 68bb ldr r3, [r7, #8] 8009a2c: 2b40 cmp r3, #64 @ 0x40 8009a2e: d01d beq.n 8009a6c { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8009a30: 68fb ldr r3, [r7, #12] 8009a32: 681b ldr r3, [r3, #0] 8009a34: 681b ldr r3, [r3, #0] 8009a36: f003 0308 and.w r3, r3, #8 8009a3a: 2b08 cmp r3, #8 8009a3c: d116 bne.n 8009a6c { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 8009a3e: 2300 movs r3, #0 8009a40: 617b str r3, [r7, #20] 8009a42: 68fb ldr r3, [r7, #12] 8009a44: 681b ldr r3, [r3, #0] 8009a46: 681b ldr r3, [r3, #0] 8009a48: 617b str r3, [r7, #20] 8009a4a: 68fb ldr r3, [r7, #12] 8009a4c: 681b ldr r3, [r3, #0] 8009a4e: 685b ldr r3, [r3, #4] 8009a50: 617b str r3, [r7, #20] 8009a52: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8009a54: 68f8 ldr r0, [r7, #12] 8009a56: f000 f81d bl 8009a94 huart->ErrorCode = HAL_UART_ERROR_ORE; 8009a5a: 68fb ldr r3, [r7, #12] 8009a5c: 2208 movs r2, #8 8009a5e: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 8009a60: 68fb ldr r3, [r7, #12] 8009a62: 2200 movs r2, #0 8009a64: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 8009a68: 2301 movs r3, #1 8009a6a: e00f b.n 8009a8c while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8009a6c: 68fb ldr r3, [r7, #12] 8009a6e: 681b ldr r3, [r3, #0] 8009a70: 681a ldr r2, [r3, #0] 8009a72: 68bb ldr r3, [r7, #8] 8009a74: 4013 ands r3, r2 8009a76: 68ba ldr r2, [r7, #8] 8009a78: 429a cmp r2, r3 8009a7a: bf0c ite eq 8009a7c: 2301 moveq r3, #1 8009a7e: 2300 movne r3, #0 8009a80: b2db uxtb r3, r3 8009a82: 461a mov r2, r3 8009a84: 79fb ldrb r3, [r7, #7] 8009a86: 429a cmp r2, r3 8009a88: d0b4 beq.n 80099f4 } } } } return HAL_OK; 8009a8a: 2300 movs r3, #0 } 8009a8c: 4618 mov r0, r3 8009a8e: 3718 adds r7, #24 8009a90: 46bd mov sp, r7 8009a92: bd80 pop {r7, pc} 08009a94 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8009a94: b480 push {r7} 8009a96: b095 sub sp, #84 @ 0x54 8009a98: af00 add r7, sp, #0 8009a9a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8009a9c: 687b ldr r3, [r7, #4] 8009a9e: 681b ldr r3, [r3, #0] 8009aa0: 330c adds r3, #12 8009aa2: 637b str r3, [r7, #52] @ 0x34 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009aa4: 6b7b ldr r3, [r7, #52] @ 0x34 8009aa6: e853 3f00 ldrex r3, [r3] 8009aaa: 633b str r3, [r7, #48] @ 0x30 return(result); 8009aac: 6b3b ldr r3, [r7, #48] @ 0x30 8009aae: f423 7390 bic.w r3, r3, #288 @ 0x120 8009ab2: 64fb str r3, [r7, #76] @ 0x4c 8009ab4: 687b ldr r3, [r7, #4] 8009ab6: 681b ldr r3, [r3, #0] 8009ab8: 330c adds r3, #12 8009aba: 6cfa ldr r2, [r7, #76] @ 0x4c 8009abc: 643a str r2, [r7, #64] @ 0x40 8009abe: 63fb str r3, [r7, #60] @ 0x3c */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009ac0: 6bf9 ldr r1, [r7, #60] @ 0x3c 8009ac2: 6c3a ldr r2, [r7, #64] @ 0x40 8009ac4: e841 2300 strex r3, r2, [r1] 8009ac8: 63bb str r3, [r7, #56] @ 0x38 return(result); 8009aca: 6bbb ldr r3, [r7, #56] @ 0x38 8009acc: 2b00 cmp r3, #0 8009ace: d1e5 bne.n 8009a9c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8009ad0: 687b ldr r3, [r7, #4] 8009ad2: 681b ldr r3, [r3, #0] 8009ad4: 3314 adds r3, #20 8009ad6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009ad8: 6a3b ldr r3, [r7, #32] 8009ada: e853 3f00 ldrex r3, [r3] 8009ade: 61fb str r3, [r7, #28] return(result); 8009ae0: 69fb ldr r3, [r7, #28] 8009ae2: f023 0301 bic.w r3, r3, #1 8009ae6: 64bb str r3, [r7, #72] @ 0x48 8009ae8: 687b ldr r3, [r7, #4] 8009aea: 681b ldr r3, [r3, #0] 8009aec: 3314 adds r3, #20 8009aee: 6cba ldr r2, [r7, #72] @ 0x48 8009af0: 62fa str r2, [r7, #44] @ 0x2c 8009af2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009af4: 6ab9 ldr r1, [r7, #40] @ 0x28 8009af6: 6afa ldr r2, [r7, #44] @ 0x2c 8009af8: e841 2300 strex r3, r2, [r1] 8009afc: 627b str r3, [r7, #36] @ 0x24 return(result); 8009afe: 6a7b ldr r3, [r7, #36] @ 0x24 8009b00: 2b00 cmp r3, #0 8009b02: d1e5 bne.n 8009ad0 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8009b04: 687b ldr r3, [r7, #4] 8009b06: 6b1b ldr r3, [r3, #48] @ 0x30 8009b08: 2b01 cmp r3, #1 8009b0a: d119 bne.n 8009b40 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8009b0c: 687b ldr r3, [r7, #4] 8009b0e: 681b ldr r3, [r3, #0] 8009b10: 330c adds r3, #12 8009b12: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009b14: 68fb ldr r3, [r7, #12] 8009b16: e853 3f00 ldrex r3, [r3] 8009b1a: 60bb str r3, [r7, #8] return(result); 8009b1c: 68bb ldr r3, [r7, #8] 8009b1e: f023 0310 bic.w r3, r3, #16 8009b22: 647b str r3, [r7, #68] @ 0x44 8009b24: 687b ldr r3, [r7, #4] 8009b26: 681b ldr r3, [r3, #0] 8009b28: 330c adds r3, #12 8009b2a: 6c7a ldr r2, [r7, #68] @ 0x44 8009b2c: 61ba str r2, [r7, #24] 8009b2e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009b30: 6979 ldr r1, [r7, #20] 8009b32: 69ba ldr r2, [r7, #24] 8009b34: e841 2300 strex r3, r2, [r1] 8009b38: 613b str r3, [r7, #16] return(result); 8009b3a: 693b ldr r3, [r7, #16] 8009b3c: 2b00 cmp r3, #0 8009b3e: d1e5 bne.n 8009b0c } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8009b40: 687b ldr r3, [r7, #4] 8009b42: 2220 movs r2, #32 8009b44: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8009b48: 687b ldr r3, [r7, #4] 8009b4a: 2200 movs r2, #0 8009b4c: 631a str r2, [r3, #48] @ 0x30 } 8009b4e: bf00 nop 8009b50: 3754 adds r7, #84 @ 0x54 8009b52: 46bd mov sp, r7 8009b54: bc80 pop {r7} 8009b56: 4770 bx lr 08009b58 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8009b58: b580 push {r7, lr} 8009b5a: b084 sub sp, #16 8009b5c: af00 add r7, sp, #0 8009b5e: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8009b60: 687b ldr r3, [r7, #4] 8009b62: 681b ldr r3, [r3, #0] 8009b64: 691b ldr r3, [r3, #16] 8009b66: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8009b6a: 687b ldr r3, [r7, #4] 8009b6c: 68da ldr r2, [r3, #12] 8009b6e: 687b ldr r3, [r7, #4] 8009b70: 681b ldr r3, [r3, #0] 8009b72: 430a orrs r2, r1 8009b74: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8009b76: 687b ldr r3, [r7, #4] 8009b78: 689a ldr r2, [r3, #8] 8009b7a: 687b ldr r3, [r7, #4] 8009b7c: 691b ldr r3, [r3, #16] 8009b7e: 431a orrs r2, r3 8009b80: 687b ldr r3, [r7, #4] 8009b82: 695b ldr r3, [r3, #20] 8009b84: 4313 orrs r3, r2 8009b86: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8009b88: 687b ldr r3, [r7, #4] 8009b8a: 681b ldr r3, [r3, #0] 8009b8c: 68db ldr r3, [r3, #12] 8009b8e: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8009b92: f023 030c bic.w r3, r3, #12 8009b96: 687a ldr r2, [r7, #4] 8009b98: 6812 ldr r2, [r2, #0] 8009b9a: 68b9 ldr r1, [r7, #8] 8009b9c: 430b orrs r3, r1 8009b9e: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8009ba0: 687b ldr r3, [r7, #4] 8009ba2: 681b ldr r3, [r3, #0] 8009ba4: 695b ldr r3, [r3, #20] 8009ba6: f423 7140 bic.w r1, r3, #768 @ 0x300 8009baa: 687b ldr r3, [r7, #4] 8009bac: 699a ldr r2, [r3, #24] 8009bae: 687b ldr r3, [r7, #4] 8009bb0: 681b ldr r3, [r3, #0] 8009bb2: 430a orrs r2, r1 8009bb4: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8009bb6: 687b ldr r3, [r7, #4] 8009bb8: 681b ldr r3, [r3, #0] 8009bba: 4a2c ldr r2, [pc, #176] @ (8009c6c ) 8009bbc: 4293 cmp r3, r2 8009bbe: d103 bne.n 8009bc8 { pclk = HAL_RCC_GetPCLK2Freq(); 8009bc0: f7fe fede bl 8008980 8009bc4: 60f8 str r0, [r7, #12] 8009bc6: e002 b.n 8009bce } else { pclk = HAL_RCC_GetPCLK1Freq(); 8009bc8: f7fe fec6 bl 8008958 8009bcc: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8009bce: 68fa ldr r2, [r7, #12] 8009bd0: 4613 mov r3, r2 8009bd2: 009b lsls r3, r3, #2 8009bd4: 4413 add r3, r2 8009bd6: 009a lsls r2, r3, #2 8009bd8: 441a add r2, r3 8009bda: 687b ldr r3, [r7, #4] 8009bdc: 685b ldr r3, [r3, #4] 8009bde: 009b lsls r3, r3, #2 8009be0: fbb2 f3f3 udiv r3, r2, r3 8009be4: 4a22 ldr r2, [pc, #136] @ (8009c70 ) 8009be6: fba2 2303 umull r2, r3, r2, r3 8009bea: 095b lsrs r3, r3, #5 8009bec: 0119 lsls r1, r3, #4 8009bee: 68fa ldr r2, [r7, #12] 8009bf0: 4613 mov r3, r2 8009bf2: 009b lsls r3, r3, #2 8009bf4: 4413 add r3, r2 8009bf6: 009a lsls r2, r3, #2 8009bf8: 441a add r2, r3 8009bfa: 687b ldr r3, [r7, #4] 8009bfc: 685b ldr r3, [r3, #4] 8009bfe: 009b lsls r3, r3, #2 8009c00: fbb2 f2f3 udiv r2, r2, r3 8009c04: 4b1a ldr r3, [pc, #104] @ (8009c70 ) 8009c06: fba3 0302 umull r0, r3, r3, r2 8009c0a: 095b lsrs r3, r3, #5 8009c0c: 2064 movs r0, #100 @ 0x64 8009c0e: fb00 f303 mul.w r3, r0, r3 8009c12: 1ad3 subs r3, r2, r3 8009c14: 011b lsls r3, r3, #4 8009c16: 3332 adds r3, #50 @ 0x32 8009c18: 4a15 ldr r2, [pc, #84] @ (8009c70 ) 8009c1a: fba2 2303 umull r2, r3, r2, r3 8009c1e: 095b lsrs r3, r3, #5 8009c20: f003 03f0 and.w r3, r3, #240 @ 0xf0 8009c24: 4419 add r1, r3 8009c26: 68fa ldr r2, [r7, #12] 8009c28: 4613 mov r3, r2 8009c2a: 009b lsls r3, r3, #2 8009c2c: 4413 add r3, r2 8009c2e: 009a lsls r2, r3, #2 8009c30: 441a add r2, r3 8009c32: 687b ldr r3, [r7, #4] 8009c34: 685b ldr r3, [r3, #4] 8009c36: 009b lsls r3, r3, #2 8009c38: fbb2 f2f3 udiv r2, r2, r3 8009c3c: 4b0c ldr r3, [pc, #48] @ (8009c70 ) 8009c3e: fba3 0302 umull r0, r3, r3, r2 8009c42: 095b lsrs r3, r3, #5 8009c44: 2064 movs r0, #100 @ 0x64 8009c46: fb00 f303 mul.w r3, r0, r3 8009c4a: 1ad3 subs r3, r2, r3 8009c4c: 011b lsls r3, r3, #4 8009c4e: 3332 adds r3, #50 @ 0x32 8009c50: 4a07 ldr r2, [pc, #28] @ (8009c70 ) 8009c52: fba2 2303 umull r2, r3, r2, r3 8009c56: 095b lsrs r3, r3, #5 8009c58: f003 020f and.w r2, r3, #15 8009c5c: 687b ldr r3, [r7, #4] 8009c5e: 681b ldr r3, [r3, #0] 8009c60: 440a add r2, r1 8009c62: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8009c64: bf00 nop 8009c66: 3710 adds r7, #16 8009c68: 46bd mov sp, r7 8009c6a: bd80 pop {r7, pc} 8009c6c: 40013800 .word 0x40013800 8009c70: 51eb851f .word 0x51eb851f 08009c74 : * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { 8009c74: b480 push {r7} 8009c76: b085 sub sp, #20 8009c78: af00 add r7, sp, #0 8009c7a: 60f8 str r0, [r7, #12] 8009c7c: 4638 mov r0, r7 8009c7e: e880 000e stmia.w r0, {r1, r2, r3} /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; 8009c82: 2300 movs r3, #0 } 8009c84: 4618 mov r0, r3 8009c86: 3714 adds r7, #20 8009c88: 46bd mov sp, r7 8009c8a: bc80 pop {r7} 8009c8c: 4770 bx lr 08009c8e : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { 8009c8e: b480 push {r7} 8009c90: b085 sub sp, #20 8009c92: af00 add r7, sp, #0 8009c94: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Clear pending interrupts */ USBx->ISTR = 0U; 8009c96: 687b ldr r3, [r7, #4] 8009c98: 2200 movs r2, #0 8009c9a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | 8009c9e: f44f 433f mov.w r3, #48896 @ 0xbf00 8009ca2: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; /* Set interrupt mask */ USBx->CNTR = (uint16_t)winterruptmask; 8009ca4: 68fb ldr r3, [r7, #12] 8009ca6: b29a uxth r2, r3 8009ca8: 687b ldr r3, [r7, #4] 8009caa: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 return HAL_OK; 8009cae: 2300 movs r3, #0 } 8009cb0: 4618 mov r0, r3 8009cb2: 3714 adds r7, #20 8009cb4: 46bd mov sp, r7 8009cb6: bc80 pop {r7} 8009cb8: 4770 bx lr 08009cba : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { 8009cba: b480 push {r7} 8009cbc: b085 sub sp, #20 8009cbe: af00 add r7, sp, #0 8009cc0: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | 8009cc2: f44f 433f mov.w r3, #48896 @ 0xbf00 8009cc6: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; /* Clear interrupt mask */ USBx->CNTR &= (uint16_t)(~winterruptmask); 8009cc8: 687b ldr r3, [r7, #4] 8009cca: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8009cce: b29a uxth r2, r3 8009cd0: 68fb ldr r3, [r7, #12] 8009cd2: b29b uxth r3, r3 8009cd4: 43db mvns r3, r3 8009cd6: b29b uxth r3, r3 8009cd8: 4013 ands r3, r2 8009cda: b29a uxth r2, r3 8009cdc: 687b ldr r3, [r7, #4] 8009cde: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 return HAL_OK; 8009ce2: 2300 movs r3, #0 } 8009ce4: 4618 mov r0, r3 8009ce6: 3714 adds r7, #20 8009ce8: 46bd mov sp, r7 8009cea: bc80 pop {r7} 8009cec: 4770 bx lr 08009cee : * This parameter can be one of the these values: * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) { 8009cee: b480 push {r7} 8009cf0: b083 sub sp, #12 8009cf2: af00 add r7, sp, #0 8009cf4: 6078 str r0, [r7, #4] 8009cf6: 460b mov r3, r1 8009cf8: 70fb strb r3, [r7, #3] /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; 8009cfa: 2300 movs r3, #0 } 8009cfc: 4618 mov r0, r3 8009cfe: 370c adds r7, #12 8009d00: 46bd mov sp, r7 8009d02: bc80 pop {r7} 8009d04: 4770 bx lr 08009d06 : * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { 8009d06: b480 push {r7} 8009d08: b085 sub sp, #20 8009d0a: af00 add r7, sp, #0 8009d0c: 60f8 str r0, [r7, #12] 8009d0e: 4638 mov r0, r7 8009d10: e880 000e stmia.w r0, {r1, r2, r3} /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); /* Init Device */ /* CNTR_FRES = 1 */ USBx->CNTR = (uint16_t)USB_CNTR_FRES; 8009d14: 68fb ldr r3, [r7, #12] 8009d16: 2201 movs r2, #1 8009d18: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* CNTR_FRES = 0 */ USBx->CNTR = 0U; 8009d1c: 68fb ldr r3, [r7, #12] 8009d1e: 2200 movs r2, #0 8009d20: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* Clear pending interrupts */ USBx->ISTR = 0U; 8009d24: 68fb ldr r3, [r7, #12] 8009d26: 2200 movs r2, #0 8009d28: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; 8009d2c: 68fb ldr r3, [r7, #12] 8009d2e: 2200 movs r2, #0 8009d30: f8a3 2050 strh.w r2, [r3, #80] @ 0x50 return HAL_OK; 8009d34: 2300 movs r3, #0 } 8009d36: 4618 mov r0, r3 8009d38: 3714 adds r7, #20 8009d3a: 46bd mov sp, r7 8009d3c: bc80 pop {r7} 8009d3e: 4770 bx lr 08009d40 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 8009d40: b480 push {r7} 8009d42: b09d sub sp, #116 @ 0x74 8009d44: af00 add r7, sp, #0 8009d46: 6078 str r0, [r7, #4] 8009d48: 6039 str r1, [r7, #0] HAL_StatusTypeDef ret = HAL_OK; 8009d4a: 2300 movs r3, #0 8009d4c: f887 306f strb.w r3, [r7, #111] @ 0x6f uint16_t wEpRegVal; wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; 8009d50: 687a ldr r2, [r7, #4] 8009d52: 683b ldr r3, [r7, #0] 8009d54: 781b ldrb r3, [r3, #0] 8009d56: 009b lsls r3, r3, #2 8009d58: 4413 add r3, r2 8009d5a: 881b ldrh r3, [r3, #0] 8009d5c: b29b uxth r3, r3 8009d5e: f423 43ec bic.w r3, r3, #30208 @ 0x7600 8009d62: f023 0370 bic.w r3, r3, #112 @ 0x70 8009d66: f8a7 306c strh.w r3, [r7, #108] @ 0x6c /* initialize Endpoint */ switch (ep->type) 8009d6a: 683b ldr r3, [r7, #0] 8009d6c: 78db ldrb r3, [r3, #3] 8009d6e: 2b03 cmp r3, #3 8009d70: d81f bhi.n 8009db2 8009d72: a201 add r2, pc, #4 @ (adr r2, 8009d78 ) 8009d74: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009d78: 08009d89 .word 0x08009d89 8009d7c: 08009da5 .word 0x08009da5 8009d80: 08009dbb .word 0x08009dbb 8009d84: 08009d97 .word 0x08009d97 { case EP_TYPE_CTRL: wEpRegVal |= USB_EP_CONTROL; 8009d88: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8009d8c: f443 7300 orr.w r3, r3, #512 @ 0x200 8009d90: f8a7 306c strh.w r3, [r7, #108] @ 0x6c break; 8009d94: e012 b.n 8009dbc case EP_TYPE_BULK: wEpRegVal |= USB_EP_BULK; break; case EP_TYPE_INTR: wEpRegVal |= USB_EP_INTERRUPT; 8009d96: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8009d9a: f443 63c0 orr.w r3, r3, #1536 @ 0x600 8009d9e: f8a7 306c strh.w r3, [r7, #108] @ 0x6c break; 8009da2: e00b b.n 8009dbc case EP_TYPE_ISOC: wEpRegVal |= USB_EP_ISOCHRONOUS; 8009da4: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8009da8: f443 6380 orr.w r3, r3, #1024 @ 0x400 8009dac: f8a7 306c strh.w r3, [r7, #108] @ 0x6c break; 8009db0: e004 b.n 8009dbc default: ret = HAL_ERROR; 8009db2: 2301 movs r3, #1 8009db4: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8009db8: e000 b.n 8009dbc break; 8009dba: bf00 nop } PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); 8009dbc: 687a ldr r2, [r7, #4] 8009dbe: 683b ldr r3, [r7, #0] 8009dc0: 781b ldrb r3, [r3, #0] 8009dc2: 009b lsls r3, r3, #2 8009dc4: 441a add r2, r3 8009dc6: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8009dca: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009dce: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009dd2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009dd6: f043 0380 orr.w r3, r3, #128 @ 0x80 8009dda: b29b uxth r3, r3 8009ddc: 8013 strh r3, [r2, #0] PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); 8009dde: 687a ldr r2, [r7, #4] 8009de0: 683b ldr r3, [r7, #0] 8009de2: 781b ldrb r3, [r3, #0] 8009de4: 009b lsls r3, r3, #2 8009de6: 4413 add r3, r2 8009de8: 881b ldrh r3, [r3, #0] 8009dea: b29b uxth r3, r3 8009dec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009df0: f023 0370 bic.w r3, r3, #112 @ 0x70 8009df4: b29b uxth r3, r3 8009df6: 683a ldr r2, [r7, #0] 8009df8: 7812 ldrb r2, [r2, #0] 8009dfa: 4313 orrs r3, r2 8009dfc: f8a7 3066 strh.w r3, [r7, #102] @ 0x66 8009e00: 687a ldr r2, [r7, #4] 8009e02: 683b ldr r3, [r7, #0] 8009e04: 781b ldrb r3, [r3, #0] 8009e06: 009b lsls r3, r3, #2 8009e08: 441a add r2, r3 8009e0a: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66 8009e0e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009e12: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009e16: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009e1a: f043 0380 orr.w r3, r3, #128 @ 0x80 8009e1e: b29b uxth r3, r3 8009e20: 8013 strh r3, [r2, #0] if (ep->doublebuffer == 0U) 8009e22: 683b ldr r3, [r7, #0] 8009e24: 7b1b ldrb r3, [r3, #12] 8009e26: 2b00 cmp r3, #0 8009e28: f040 8178 bne.w 800a11c { if (ep->is_in != 0U) 8009e2c: 683b ldr r3, [r7, #0] 8009e2e: 785b ldrb r3, [r3, #1] 8009e30: 2b00 cmp r3, #0 8009e32: f000 8084 beq.w 8009f3e { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); 8009e36: 687b ldr r3, [r7, #4] 8009e38: 61bb str r3, [r7, #24] 8009e3a: 687b ldr r3, [r7, #4] 8009e3c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009e40: b29b uxth r3, r3 8009e42: 461a mov r2, r3 8009e44: 69bb ldr r3, [r7, #24] 8009e46: 4413 add r3, r2 8009e48: 61bb str r3, [r7, #24] 8009e4a: 683b ldr r3, [r7, #0] 8009e4c: 781b ldrb r3, [r3, #0] 8009e4e: 011a lsls r2, r3, #4 8009e50: 69bb ldr r3, [r7, #24] 8009e52: 4413 add r3, r2 8009e54: f503 6380 add.w r3, r3, #1024 @ 0x400 8009e58: 617b str r3, [r7, #20] 8009e5a: 683b ldr r3, [r7, #0] 8009e5c: 88db ldrh r3, [r3, #6] 8009e5e: 085b lsrs r3, r3, #1 8009e60: b29b uxth r3, r3 8009e62: 005b lsls r3, r3, #1 8009e64: b29a uxth r2, r3 8009e66: 697b ldr r3, [r7, #20] 8009e68: 801a strh r2, [r3, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 8009e6a: 687a ldr r2, [r7, #4] 8009e6c: 683b ldr r3, [r7, #0] 8009e6e: 781b ldrb r3, [r3, #0] 8009e70: 009b lsls r3, r3, #2 8009e72: 4413 add r3, r2 8009e74: 881b ldrh r3, [r3, #0] 8009e76: 827b strh r3, [r7, #18] 8009e78: 8a7b ldrh r3, [r7, #18] 8009e7a: f003 0340 and.w r3, r3, #64 @ 0x40 8009e7e: 2b00 cmp r3, #0 8009e80: d01b beq.n 8009eba 8009e82: 687a ldr r2, [r7, #4] 8009e84: 683b ldr r3, [r7, #0] 8009e86: 781b ldrb r3, [r3, #0] 8009e88: 009b lsls r3, r3, #2 8009e8a: 4413 add r3, r2 8009e8c: 881b ldrh r3, [r3, #0] 8009e8e: b29b uxth r3, r3 8009e90: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009e94: f023 0370 bic.w r3, r3, #112 @ 0x70 8009e98: 823b strh r3, [r7, #16] 8009e9a: 687a ldr r2, [r7, #4] 8009e9c: 683b ldr r3, [r7, #0] 8009e9e: 781b ldrb r3, [r3, #0] 8009ea0: 009b lsls r3, r3, #2 8009ea2: 441a add r2, r3 8009ea4: 8a3b ldrh r3, [r7, #16] 8009ea6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009eaa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009eae: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009eb2: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8009eb6: b29b uxth r3, r3 8009eb8: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8009eba: 683b ldr r3, [r7, #0] 8009ebc: 78db ldrb r3, [r3, #3] 8009ebe: 2b01 cmp r3, #1 8009ec0: d020 beq.n 8009f04 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 8009ec2: 687a ldr r2, [r7, #4] 8009ec4: 683b ldr r3, [r7, #0] 8009ec6: 781b ldrb r3, [r3, #0] 8009ec8: 009b lsls r3, r3, #2 8009eca: 4413 add r3, r2 8009ecc: 881b ldrh r3, [r3, #0] 8009ece: b29b uxth r3, r3 8009ed0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009ed4: f023 0340 bic.w r3, r3, #64 @ 0x40 8009ed8: 81bb strh r3, [r7, #12] 8009eda: 89bb ldrh r3, [r7, #12] 8009edc: f083 0320 eor.w r3, r3, #32 8009ee0: 81bb strh r3, [r7, #12] 8009ee2: 687a ldr r2, [r7, #4] 8009ee4: 683b ldr r3, [r7, #0] 8009ee6: 781b ldrb r3, [r3, #0] 8009ee8: 009b lsls r3, r3, #2 8009eea: 441a add r2, r3 8009eec: 89bb ldrh r3, [r7, #12] 8009eee: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009ef2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009ef6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009efa: f043 0380 orr.w r3, r3, #128 @ 0x80 8009efe: b29b uxth r3, r3 8009f00: 8013 strh r3, [r2, #0] 8009f02: e2d5 b.n 800a4b0 } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 8009f04: 687a ldr r2, [r7, #4] 8009f06: 683b ldr r3, [r7, #0] 8009f08: 781b ldrb r3, [r3, #0] 8009f0a: 009b lsls r3, r3, #2 8009f0c: 4413 add r3, r2 8009f0e: 881b ldrh r3, [r3, #0] 8009f10: b29b uxth r3, r3 8009f12: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009f16: f023 0340 bic.w r3, r3, #64 @ 0x40 8009f1a: 81fb strh r3, [r7, #14] 8009f1c: 687a ldr r2, [r7, #4] 8009f1e: 683b ldr r3, [r7, #0] 8009f20: 781b ldrb r3, [r3, #0] 8009f22: 009b lsls r3, r3, #2 8009f24: 441a add r2, r3 8009f26: 89fb ldrh r3, [r7, #14] 8009f28: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009f2c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009f30: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009f34: f043 0380 orr.w r3, r3, #128 @ 0x80 8009f38: b29b uxth r3, r3 8009f3a: 8013 strh r3, [r2, #0] 8009f3c: e2b8 b.n 800a4b0 } } else { /* Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); 8009f3e: 687b ldr r3, [r7, #4] 8009f40: 633b str r3, [r7, #48] @ 0x30 8009f42: 687b ldr r3, [r7, #4] 8009f44: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009f48: b29b uxth r3, r3 8009f4a: 461a mov r2, r3 8009f4c: 6b3b ldr r3, [r7, #48] @ 0x30 8009f4e: 4413 add r3, r2 8009f50: 633b str r3, [r7, #48] @ 0x30 8009f52: 683b ldr r3, [r7, #0] 8009f54: 781b ldrb r3, [r3, #0] 8009f56: 011a lsls r2, r3, #4 8009f58: 6b3b ldr r3, [r7, #48] @ 0x30 8009f5a: 4413 add r3, r2 8009f5c: f503 6381 add.w r3, r3, #1032 @ 0x408 8009f60: 62fb str r3, [r7, #44] @ 0x2c 8009f62: 683b ldr r3, [r7, #0] 8009f64: 88db ldrh r3, [r3, #6] 8009f66: 085b lsrs r3, r3, #1 8009f68: b29b uxth r3, r3 8009f6a: 005b lsls r3, r3, #1 8009f6c: b29a uxth r2, r3 8009f6e: 6afb ldr r3, [r7, #44] @ 0x2c 8009f70: 801a strh r2, [r3, #0] /* Set the endpoint Receive buffer counter */ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); 8009f72: 687b ldr r3, [r7, #4] 8009f74: 62bb str r3, [r7, #40] @ 0x28 8009f76: 687b ldr r3, [r7, #4] 8009f78: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009f7c: b29b uxth r3, r3 8009f7e: 461a mov r2, r3 8009f80: 6abb ldr r3, [r7, #40] @ 0x28 8009f82: 4413 add r3, r2 8009f84: 62bb str r3, [r7, #40] @ 0x28 8009f86: 683b ldr r3, [r7, #0] 8009f88: 781b ldrb r3, [r3, #0] 8009f8a: 011a lsls r2, r3, #4 8009f8c: 6abb ldr r3, [r7, #40] @ 0x28 8009f8e: 4413 add r3, r2 8009f90: f203 430c addw r3, r3, #1036 @ 0x40c 8009f94: 627b str r3, [r7, #36] @ 0x24 8009f96: 6a7b ldr r3, [r7, #36] @ 0x24 8009f98: 881b ldrh r3, [r3, #0] 8009f9a: b29b uxth r3, r3 8009f9c: f3c3 0309 ubfx r3, r3, #0, #10 8009fa0: b29a uxth r2, r3 8009fa2: 6a7b ldr r3, [r7, #36] @ 0x24 8009fa4: 801a strh r2, [r3, #0] 8009fa6: 683b ldr r3, [r7, #0] 8009fa8: 691b ldr r3, [r3, #16] 8009faa: 2b3e cmp r3, #62 @ 0x3e 8009fac: d91d bls.n 8009fea 8009fae: 683b ldr r3, [r7, #0] 8009fb0: 691b ldr r3, [r3, #16] 8009fb2: 095b lsrs r3, r3, #5 8009fb4: 66bb str r3, [r7, #104] @ 0x68 8009fb6: 683b ldr r3, [r7, #0] 8009fb8: 691b ldr r3, [r3, #16] 8009fba: f003 031f and.w r3, r3, #31 8009fbe: 2b00 cmp r3, #0 8009fc0: d102 bne.n 8009fc8 8009fc2: 6ebb ldr r3, [r7, #104] @ 0x68 8009fc4: 3b01 subs r3, #1 8009fc6: 66bb str r3, [r7, #104] @ 0x68 8009fc8: 6a7b ldr r3, [r7, #36] @ 0x24 8009fca: 881b ldrh r3, [r3, #0] 8009fcc: b29a uxth r2, r3 8009fce: 6ebb ldr r3, [r7, #104] @ 0x68 8009fd0: b29b uxth r3, r3 8009fd2: 029b lsls r3, r3, #10 8009fd4: b29b uxth r3, r3 8009fd6: 4313 orrs r3, r2 8009fd8: b29b uxth r3, r3 8009fda: ea6f 4343 mvn.w r3, r3, lsl #17 8009fde: ea6f 4353 mvn.w r3, r3, lsr #17 8009fe2: b29a uxth r2, r3 8009fe4: 6a7b ldr r3, [r7, #36] @ 0x24 8009fe6: 801a strh r2, [r3, #0] 8009fe8: e026 b.n 800a038 8009fea: 683b ldr r3, [r7, #0] 8009fec: 691b ldr r3, [r3, #16] 8009fee: 2b00 cmp r3, #0 8009ff0: d10a bne.n 800a008 8009ff2: 6a7b ldr r3, [r7, #36] @ 0x24 8009ff4: 881b ldrh r3, [r3, #0] 8009ff6: b29b uxth r3, r3 8009ff8: ea6f 4343 mvn.w r3, r3, lsl #17 8009ffc: ea6f 4353 mvn.w r3, r3, lsr #17 800a000: b29a uxth r2, r3 800a002: 6a7b ldr r3, [r7, #36] @ 0x24 800a004: 801a strh r2, [r3, #0] 800a006: e017 b.n 800a038 800a008: 683b ldr r3, [r7, #0] 800a00a: 691b ldr r3, [r3, #16] 800a00c: 085b lsrs r3, r3, #1 800a00e: 66bb str r3, [r7, #104] @ 0x68 800a010: 683b ldr r3, [r7, #0] 800a012: 691b ldr r3, [r3, #16] 800a014: f003 0301 and.w r3, r3, #1 800a018: 2b00 cmp r3, #0 800a01a: d002 beq.n 800a022 800a01c: 6ebb ldr r3, [r7, #104] @ 0x68 800a01e: 3301 adds r3, #1 800a020: 66bb str r3, [r7, #104] @ 0x68 800a022: 6a7b ldr r3, [r7, #36] @ 0x24 800a024: 881b ldrh r3, [r3, #0] 800a026: b29a uxth r2, r3 800a028: 6ebb ldr r3, [r7, #104] @ 0x68 800a02a: b29b uxth r3, r3 800a02c: 029b lsls r3, r3, #10 800a02e: b29b uxth r3, r3 800a030: 4313 orrs r3, r2 800a032: b29a uxth r2, r3 800a034: 6a7b ldr r3, [r7, #36] @ 0x24 800a036: 801a strh r2, [r3, #0] PCD_CLEAR_RX_DTOG(USBx, ep->num); 800a038: 687a ldr r2, [r7, #4] 800a03a: 683b ldr r3, [r7, #0] 800a03c: 781b ldrb r3, [r3, #0] 800a03e: 009b lsls r3, r3, #2 800a040: 4413 add r3, r2 800a042: 881b ldrh r3, [r3, #0] 800a044: 847b strh r3, [r7, #34] @ 0x22 800a046: 8c7b ldrh r3, [r7, #34] @ 0x22 800a048: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a04c: 2b00 cmp r3, #0 800a04e: d01b beq.n 800a088 800a050: 687a ldr r2, [r7, #4] 800a052: 683b ldr r3, [r7, #0] 800a054: 781b ldrb r3, [r3, #0] 800a056: 009b lsls r3, r3, #2 800a058: 4413 add r3, r2 800a05a: 881b ldrh r3, [r3, #0] 800a05c: b29b uxth r3, r3 800a05e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a062: f023 0370 bic.w r3, r3, #112 @ 0x70 800a066: 843b strh r3, [r7, #32] 800a068: 687a ldr r2, [r7, #4] 800a06a: 683b ldr r3, [r7, #0] 800a06c: 781b ldrb r3, [r3, #0] 800a06e: 009b lsls r3, r3, #2 800a070: 441a add r2, r3 800a072: 8c3b ldrh r3, [r7, #32] 800a074: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a078: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a07c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a080: f043 0380 orr.w r3, r3, #128 @ 0x80 800a084: b29b uxth r3, r3 800a086: 8013 strh r3, [r2, #0] if (ep->num == 0U) 800a088: 683b ldr r3, [r7, #0] 800a08a: 781b ldrb r3, [r3, #0] 800a08c: 2b00 cmp r3, #0 800a08e: d124 bne.n 800a0da { /* Configure VALID status for EP0 */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800a090: 687a ldr r2, [r7, #4] 800a092: 683b ldr r3, [r7, #0] 800a094: 781b ldrb r3, [r3, #0] 800a096: 009b lsls r3, r3, #2 800a098: 4413 add r3, r2 800a09a: 881b ldrh r3, [r3, #0] 800a09c: b29b uxth r3, r3 800a09e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a0a2: f023 0370 bic.w r3, r3, #112 @ 0x70 800a0a6: 83bb strh r3, [r7, #28] 800a0a8: 8bbb ldrh r3, [r7, #28] 800a0aa: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800a0ae: 83bb strh r3, [r7, #28] 800a0b0: 8bbb ldrh r3, [r7, #28] 800a0b2: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800a0b6: 83bb strh r3, [r7, #28] 800a0b8: 687a ldr r2, [r7, #4] 800a0ba: 683b ldr r3, [r7, #0] 800a0bc: 781b ldrb r3, [r3, #0] 800a0be: 009b lsls r3, r3, #2 800a0c0: 441a add r2, r3 800a0c2: 8bbb ldrh r3, [r7, #28] 800a0c4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a0c8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a0cc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a0d0: f043 0380 orr.w r3, r3, #128 @ 0x80 800a0d4: b29b uxth r3, r3 800a0d6: 8013 strh r3, [r2, #0] 800a0d8: e1ea b.n 800a4b0 } else { /* Configure NAK status for OUT Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); 800a0da: 687a ldr r2, [r7, #4] 800a0dc: 683b ldr r3, [r7, #0] 800a0de: 781b ldrb r3, [r3, #0] 800a0e0: 009b lsls r3, r3, #2 800a0e2: 4413 add r3, r2 800a0e4: 881b ldrh r3, [r3, #0] 800a0e6: b29b uxth r3, r3 800a0e8: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a0ec: f023 0370 bic.w r3, r3, #112 @ 0x70 800a0f0: 83fb strh r3, [r7, #30] 800a0f2: 8bfb ldrh r3, [r7, #30] 800a0f4: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800a0f8: 83fb strh r3, [r7, #30] 800a0fa: 687a ldr r2, [r7, #4] 800a0fc: 683b ldr r3, [r7, #0] 800a0fe: 781b ldrb r3, [r3, #0] 800a100: 009b lsls r3, r3, #2 800a102: 441a add r2, r3 800a104: 8bfb ldrh r3, [r7, #30] 800a106: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a10a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a10e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a112: f043 0380 orr.w r3, r3, #128 @ 0x80 800a116: b29b uxth r3, r3 800a118: 8013 strh r3, [r2, #0] 800a11a: e1c9 b.n 800a4b0 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->type == EP_TYPE_BULK) 800a11c: 683b ldr r3, [r7, #0] 800a11e: 78db ldrb r3, [r3, #3] 800a120: 2b02 cmp r3, #2 800a122: d11e bne.n 800a162 { /* Set bulk endpoint as double buffered */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); 800a124: 687a ldr r2, [r7, #4] 800a126: 683b ldr r3, [r7, #0] 800a128: 781b ldrb r3, [r3, #0] 800a12a: 009b lsls r3, r3, #2 800a12c: 4413 add r3, r2 800a12e: 881b ldrh r3, [r3, #0] 800a130: b29b uxth r3, r3 800a132: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a136: f023 0370 bic.w r3, r3, #112 @ 0x70 800a13a: f8a7 3062 strh.w r3, [r7, #98] @ 0x62 800a13e: 687a ldr r2, [r7, #4] 800a140: 683b ldr r3, [r7, #0] 800a142: 781b ldrb r3, [r3, #0] 800a144: 009b lsls r3, r3, #2 800a146: 441a add r2, r3 800a148: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62 800a14c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a150: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a154: f443 4301 orr.w r3, r3, #33024 @ 0x8100 800a158: f043 0380 orr.w r3, r3, #128 @ 0x80 800a15c: b29b uxth r3, r3 800a15e: 8013 strh r3, [r2, #0] 800a160: e01d b.n 800a19e } else { /* Set the ISOC endpoint in double buffer mode */ PCD_CLEAR_EP_KIND(USBx, ep->num); 800a162: 687a ldr r2, [r7, #4] 800a164: 683b ldr r3, [r7, #0] 800a166: 781b ldrb r3, [r3, #0] 800a168: 009b lsls r3, r3, #2 800a16a: 4413 add r3, r2 800a16c: 881b ldrh r3, [r3, #0] 800a16e: b29b uxth r3, r3 800a170: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 800a174: f023 0370 bic.w r3, r3, #112 @ 0x70 800a178: f8a7 3064 strh.w r3, [r7, #100] @ 0x64 800a17c: 687a ldr r2, [r7, #4] 800a17e: 683b ldr r3, [r7, #0] 800a180: 781b ldrb r3, [r3, #0] 800a182: 009b lsls r3, r3, #2 800a184: 441a add r2, r3 800a186: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64 800a18a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a18e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a192: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a196: f043 0380 orr.w r3, r3, #128 @ 0x80 800a19a: b29b uxth r3, r3 800a19c: 8013 strh r3, [r2, #0] } /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); 800a19e: 687b ldr r3, [r7, #4] 800a1a0: 65fb str r3, [r7, #92] @ 0x5c 800a1a2: 687b ldr r3, [r7, #4] 800a1a4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a1a8: b29b uxth r3, r3 800a1aa: 461a mov r2, r3 800a1ac: 6dfb ldr r3, [r7, #92] @ 0x5c 800a1ae: 4413 add r3, r2 800a1b0: 65fb str r3, [r7, #92] @ 0x5c 800a1b2: 683b ldr r3, [r7, #0] 800a1b4: 781b ldrb r3, [r3, #0] 800a1b6: 011a lsls r2, r3, #4 800a1b8: 6dfb ldr r3, [r7, #92] @ 0x5c 800a1ba: 4413 add r3, r2 800a1bc: f503 6380 add.w r3, r3, #1024 @ 0x400 800a1c0: 65bb str r3, [r7, #88] @ 0x58 800a1c2: 683b ldr r3, [r7, #0] 800a1c4: 891b ldrh r3, [r3, #8] 800a1c6: 085b lsrs r3, r3, #1 800a1c8: b29b uxth r3, r3 800a1ca: 005b lsls r3, r3, #1 800a1cc: b29a uxth r2, r3 800a1ce: 6dbb ldr r3, [r7, #88] @ 0x58 800a1d0: 801a strh r2, [r3, #0] 800a1d2: 687b ldr r3, [r7, #4] 800a1d4: 657b str r3, [r7, #84] @ 0x54 800a1d6: 687b ldr r3, [r7, #4] 800a1d8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a1dc: b29b uxth r3, r3 800a1de: 461a mov r2, r3 800a1e0: 6d7b ldr r3, [r7, #84] @ 0x54 800a1e2: 4413 add r3, r2 800a1e4: 657b str r3, [r7, #84] @ 0x54 800a1e6: 683b ldr r3, [r7, #0] 800a1e8: 781b ldrb r3, [r3, #0] 800a1ea: 011a lsls r2, r3, #4 800a1ec: 6d7b ldr r3, [r7, #84] @ 0x54 800a1ee: 4413 add r3, r2 800a1f0: f503 6381 add.w r3, r3, #1032 @ 0x408 800a1f4: 653b str r3, [r7, #80] @ 0x50 800a1f6: 683b ldr r3, [r7, #0] 800a1f8: 895b ldrh r3, [r3, #10] 800a1fa: 085b lsrs r3, r3, #1 800a1fc: b29b uxth r3, r3 800a1fe: 005b lsls r3, r3, #1 800a200: b29a uxth r2, r3 800a202: 6d3b ldr r3, [r7, #80] @ 0x50 800a204: 801a strh r2, [r3, #0] if (ep->is_in == 0U) 800a206: 683b ldr r3, [r7, #0] 800a208: 785b ldrb r3, [r3, #1] 800a20a: 2b00 cmp r3, #0 800a20c: f040 8093 bne.w 800a336 { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800a210: 687a ldr r2, [r7, #4] 800a212: 683b ldr r3, [r7, #0] 800a214: 781b ldrb r3, [r3, #0] 800a216: 009b lsls r3, r3, #2 800a218: 4413 add r3, r2 800a21a: 881b ldrh r3, [r3, #0] 800a21c: f8a7 3040 strh.w r3, [r7, #64] @ 0x40 800a220: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40 800a224: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a228: 2b00 cmp r3, #0 800a22a: d01b beq.n 800a264 800a22c: 687a ldr r2, [r7, #4] 800a22e: 683b ldr r3, [r7, #0] 800a230: 781b ldrb r3, [r3, #0] 800a232: 009b lsls r3, r3, #2 800a234: 4413 add r3, r2 800a236: 881b ldrh r3, [r3, #0] 800a238: b29b uxth r3, r3 800a23a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a23e: f023 0370 bic.w r3, r3, #112 @ 0x70 800a242: 87fb strh r3, [r7, #62] @ 0x3e 800a244: 687a ldr r2, [r7, #4] 800a246: 683b ldr r3, [r7, #0] 800a248: 781b ldrb r3, [r3, #0] 800a24a: 009b lsls r3, r3, #2 800a24c: 441a add r2, r3 800a24e: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a250: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a254: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a258: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a25c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a260: b29b uxth r3, r3 800a262: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800a264: 687a ldr r2, [r7, #4] 800a266: 683b ldr r3, [r7, #0] 800a268: 781b ldrb r3, [r3, #0] 800a26a: 009b lsls r3, r3, #2 800a26c: 4413 add r3, r2 800a26e: 881b ldrh r3, [r3, #0] 800a270: 87bb strh r3, [r7, #60] @ 0x3c 800a272: 8fbb ldrh r3, [r7, #60] @ 0x3c 800a274: f003 0340 and.w r3, r3, #64 @ 0x40 800a278: 2b00 cmp r3, #0 800a27a: d01b beq.n 800a2b4 800a27c: 687a ldr r2, [r7, #4] 800a27e: 683b ldr r3, [r7, #0] 800a280: 781b ldrb r3, [r3, #0] 800a282: 009b lsls r3, r3, #2 800a284: 4413 add r3, r2 800a286: 881b ldrh r3, [r3, #0] 800a288: b29b uxth r3, r3 800a28a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a28e: f023 0370 bic.w r3, r3, #112 @ 0x70 800a292: 877b strh r3, [r7, #58] @ 0x3a 800a294: 687a ldr r2, [r7, #4] 800a296: 683b ldr r3, [r7, #0] 800a298: 781b ldrb r3, [r3, #0] 800a29a: 009b lsls r3, r3, #2 800a29c: 441a add r2, r3 800a29e: 8f7b ldrh r3, [r7, #58] @ 0x3a 800a2a0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a2a4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a2a8: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a2ac: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a2b0: b29b uxth r3, r3 800a2b2: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800a2b4: 687a ldr r2, [r7, #4] 800a2b6: 683b ldr r3, [r7, #0] 800a2b8: 781b ldrb r3, [r3, #0] 800a2ba: 009b lsls r3, r3, #2 800a2bc: 4413 add r3, r2 800a2be: 881b ldrh r3, [r3, #0] 800a2c0: b29b uxth r3, r3 800a2c2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a2c6: f023 0370 bic.w r3, r3, #112 @ 0x70 800a2ca: 873b strh r3, [r7, #56] @ 0x38 800a2cc: 8f3b ldrh r3, [r7, #56] @ 0x38 800a2ce: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800a2d2: 873b strh r3, [r7, #56] @ 0x38 800a2d4: 8f3b ldrh r3, [r7, #56] @ 0x38 800a2d6: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800a2da: 873b strh r3, [r7, #56] @ 0x38 800a2dc: 687a ldr r2, [r7, #4] 800a2de: 683b ldr r3, [r7, #0] 800a2e0: 781b ldrb r3, [r3, #0] 800a2e2: 009b lsls r3, r3, #2 800a2e4: 441a add r2, r3 800a2e6: 8f3b ldrh r3, [r7, #56] @ 0x38 800a2e8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a2ec: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a2f0: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a2f4: f043 0380 orr.w r3, r3, #128 @ 0x80 800a2f8: b29b uxth r3, r3 800a2fa: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800a2fc: 687a ldr r2, [r7, #4] 800a2fe: 683b ldr r3, [r7, #0] 800a300: 781b ldrb r3, [r3, #0] 800a302: 009b lsls r3, r3, #2 800a304: 4413 add r3, r2 800a306: 881b ldrh r3, [r3, #0] 800a308: b29b uxth r3, r3 800a30a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a30e: f023 0340 bic.w r3, r3, #64 @ 0x40 800a312: 86fb strh r3, [r7, #54] @ 0x36 800a314: 687a ldr r2, [r7, #4] 800a316: 683b ldr r3, [r7, #0] 800a318: 781b ldrb r3, [r3, #0] 800a31a: 009b lsls r3, r3, #2 800a31c: 441a add r2, r3 800a31e: 8efb ldrh r3, [r7, #54] @ 0x36 800a320: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a324: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a328: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a32c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a330: b29b uxth r3, r3 800a332: 8013 strh r3, [r2, #0] 800a334: e0bc b.n 800a4b0 } else { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800a336: 687a ldr r2, [r7, #4] 800a338: 683b ldr r3, [r7, #0] 800a33a: 781b ldrb r3, [r3, #0] 800a33c: 009b lsls r3, r3, #2 800a33e: 4413 add r3, r2 800a340: 881b ldrh r3, [r3, #0] 800a342: f8a7 304e strh.w r3, [r7, #78] @ 0x4e 800a346: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a34a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a34e: 2b00 cmp r3, #0 800a350: d01d beq.n 800a38e 800a352: 687a ldr r2, [r7, #4] 800a354: 683b ldr r3, [r7, #0] 800a356: 781b ldrb r3, [r3, #0] 800a358: 009b lsls r3, r3, #2 800a35a: 4413 add r3, r2 800a35c: 881b ldrh r3, [r3, #0] 800a35e: b29b uxth r3, r3 800a360: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a364: f023 0370 bic.w r3, r3, #112 @ 0x70 800a368: f8a7 304c strh.w r3, [r7, #76] @ 0x4c 800a36c: 687a ldr r2, [r7, #4] 800a36e: 683b ldr r3, [r7, #0] 800a370: 781b ldrb r3, [r3, #0] 800a372: 009b lsls r3, r3, #2 800a374: 441a add r2, r3 800a376: f8b7 304c ldrh.w r3, [r7, #76] @ 0x4c 800a37a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a37e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a382: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a386: f043 0380 orr.w r3, r3, #128 @ 0x80 800a38a: b29b uxth r3, r3 800a38c: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800a38e: 687a ldr r2, [r7, #4] 800a390: 683b ldr r3, [r7, #0] 800a392: 781b ldrb r3, [r3, #0] 800a394: 009b lsls r3, r3, #2 800a396: 4413 add r3, r2 800a398: 881b ldrh r3, [r3, #0] 800a39a: f8a7 304a strh.w r3, [r7, #74] @ 0x4a 800a39e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 800a3a2: f003 0340 and.w r3, r3, #64 @ 0x40 800a3a6: 2b00 cmp r3, #0 800a3a8: d01d beq.n 800a3e6 800a3aa: 687a ldr r2, [r7, #4] 800a3ac: 683b ldr r3, [r7, #0] 800a3ae: 781b ldrb r3, [r3, #0] 800a3b0: 009b lsls r3, r3, #2 800a3b2: 4413 add r3, r2 800a3b4: 881b ldrh r3, [r3, #0] 800a3b6: b29b uxth r3, r3 800a3b8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a3bc: f023 0370 bic.w r3, r3, #112 @ 0x70 800a3c0: f8a7 3048 strh.w r3, [r7, #72] @ 0x48 800a3c4: 687a ldr r2, [r7, #4] 800a3c6: 683b ldr r3, [r7, #0] 800a3c8: 781b ldrb r3, [r3, #0] 800a3ca: 009b lsls r3, r3, #2 800a3cc: 441a add r2, r3 800a3ce: f8b7 3048 ldrh.w r3, [r7, #72] @ 0x48 800a3d2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a3d6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a3da: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a3de: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a3e2: b29b uxth r3, r3 800a3e4: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800a3e6: 683b ldr r3, [r7, #0] 800a3e8: 78db ldrb r3, [r3, #3] 800a3ea: 2b01 cmp r3, #1 800a3ec: d024 beq.n 800a438 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 800a3ee: 687a ldr r2, [r7, #4] 800a3f0: 683b ldr r3, [r7, #0] 800a3f2: 781b ldrb r3, [r3, #0] 800a3f4: 009b lsls r3, r3, #2 800a3f6: 4413 add r3, r2 800a3f8: 881b ldrh r3, [r3, #0] 800a3fa: b29b uxth r3, r3 800a3fc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a400: f023 0340 bic.w r3, r3, #64 @ 0x40 800a404: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 800a408: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44 800a40c: f083 0320 eor.w r3, r3, #32 800a410: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 800a414: 687a ldr r2, [r7, #4] 800a416: 683b ldr r3, [r7, #0] 800a418: 781b ldrb r3, [r3, #0] 800a41a: 009b lsls r3, r3, #2 800a41c: 441a add r2, r3 800a41e: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44 800a422: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a426: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a42a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a42e: f043 0380 orr.w r3, r3, #128 @ 0x80 800a432: b29b uxth r3, r3 800a434: 8013 strh r3, [r2, #0] 800a436: e01d b.n 800a474 } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800a438: 687a ldr r2, [r7, #4] 800a43a: 683b ldr r3, [r7, #0] 800a43c: 781b ldrb r3, [r3, #0] 800a43e: 009b lsls r3, r3, #2 800a440: 4413 add r3, r2 800a442: 881b ldrh r3, [r3, #0] 800a444: b29b uxth r3, r3 800a446: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a44a: f023 0340 bic.w r3, r3, #64 @ 0x40 800a44e: f8a7 3046 strh.w r3, [r7, #70] @ 0x46 800a452: 687a ldr r2, [r7, #4] 800a454: 683b ldr r3, [r7, #0] 800a456: 781b ldrb r3, [r3, #0] 800a458: 009b lsls r3, r3, #2 800a45a: 441a add r2, r3 800a45c: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46 800a460: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a464: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a468: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a46c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a470: b29b uxth r3, r3 800a472: 8013 strh r3, [r2, #0] } PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800a474: 687a ldr r2, [r7, #4] 800a476: 683b ldr r3, [r7, #0] 800a478: 781b ldrb r3, [r3, #0] 800a47a: 009b lsls r3, r3, #2 800a47c: 4413 add r3, r2 800a47e: 881b ldrh r3, [r3, #0] 800a480: b29b uxth r3, r3 800a482: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a486: f023 0370 bic.w r3, r3, #112 @ 0x70 800a48a: f8a7 3042 strh.w r3, [r7, #66] @ 0x42 800a48e: 687a ldr r2, [r7, #4] 800a490: 683b ldr r3, [r7, #0] 800a492: 781b ldrb r3, [r3, #0] 800a494: 009b lsls r3, r3, #2 800a496: 441a add r2, r3 800a498: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42 800a49c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a4a0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a4a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a4a8: f043 0380 orr.w r3, r3, #128 @ 0x80 800a4ac: b29b uxth r3, r3 800a4ae: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return ret; 800a4b0: f897 306f ldrb.w r3, [r7, #111] @ 0x6f } 800a4b4: 4618 mov r0, r3 800a4b6: 3774 adds r7, #116 @ 0x74 800a4b8: 46bd mov sp, r7 800a4ba: bc80 pop {r7} 800a4bc: 4770 bx lr 800a4be: bf00 nop 0800a4c0 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800a4c0: b480 push {r7} 800a4c2: b08d sub sp, #52 @ 0x34 800a4c4: af00 add r7, sp, #0 800a4c6: 6078 str r0, [r7, #4] 800a4c8: 6039 str r1, [r7, #0] if (ep->doublebuffer == 0U) 800a4ca: 683b ldr r3, [r7, #0] 800a4cc: 7b1b ldrb r3, [r3, #12] 800a4ce: 2b00 cmp r3, #0 800a4d0: f040 808e bne.w 800a5f0 { if (ep->is_in != 0U) 800a4d4: 683b ldr r3, [r7, #0] 800a4d6: 785b ldrb r3, [r3, #1] 800a4d8: 2b00 cmp r3, #0 800a4da: d044 beq.n 800a566 { PCD_CLEAR_TX_DTOG(USBx, ep->num); 800a4dc: 687a ldr r2, [r7, #4] 800a4de: 683b ldr r3, [r7, #0] 800a4e0: 781b ldrb r3, [r3, #0] 800a4e2: 009b lsls r3, r3, #2 800a4e4: 4413 add r3, r2 800a4e6: 881b ldrh r3, [r3, #0] 800a4e8: 81bb strh r3, [r7, #12] 800a4ea: 89bb ldrh r3, [r7, #12] 800a4ec: f003 0340 and.w r3, r3, #64 @ 0x40 800a4f0: 2b00 cmp r3, #0 800a4f2: d01b beq.n 800a52c 800a4f4: 687a ldr r2, [r7, #4] 800a4f6: 683b ldr r3, [r7, #0] 800a4f8: 781b ldrb r3, [r3, #0] 800a4fa: 009b lsls r3, r3, #2 800a4fc: 4413 add r3, r2 800a4fe: 881b ldrh r3, [r3, #0] 800a500: b29b uxth r3, r3 800a502: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a506: f023 0370 bic.w r3, r3, #112 @ 0x70 800a50a: 817b strh r3, [r7, #10] 800a50c: 687a ldr r2, [r7, #4] 800a50e: 683b ldr r3, [r7, #0] 800a510: 781b ldrb r3, [r3, #0] 800a512: 009b lsls r3, r3, #2 800a514: 441a add r2, r3 800a516: 897b ldrh r3, [r7, #10] 800a518: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a51c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a520: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a524: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a528: b29b uxth r3, r3 800a52a: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800a52c: 687a ldr r2, [r7, #4] 800a52e: 683b ldr r3, [r7, #0] 800a530: 781b ldrb r3, [r3, #0] 800a532: 009b lsls r3, r3, #2 800a534: 4413 add r3, r2 800a536: 881b ldrh r3, [r3, #0] 800a538: b29b uxth r3, r3 800a53a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a53e: f023 0340 bic.w r3, r3, #64 @ 0x40 800a542: 813b strh r3, [r7, #8] 800a544: 687a ldr r2, [r7, #4] 800a546: 683b ldr r3, [r7, #0] 800a548: 781b ldrb r3, [r3, #0] 800a54a: 009b lsls r3, r3, #2 800a54c: 441a add r2, r3 800a54e: 893b ldrh r3, [r7, #8] 800a550: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a554: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a558: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a55c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a560: b29b uxth r3, r3 800a562: 8013 strh r3, [r2, #0] 800a564: e192 b.n 800a88c } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); 800a566: 687a ldr r2, [r7, #4] 800a568: 683b ldr r3, [r7, #0] 800a56a: 781b ldrb r3, [r3, #0] 800a56c: 009b lsls r3, r3, #2 800a56e: 4413 add r3, r2 800a570: 881b ldrh r3, [r3, #0] 800a572: 827b strh r3, [r7, #18] 800a574: 8a7b ldrh r3, [r7, #18] 800a576: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a57a: 2b00 cmp r3, #0 800a57c: d01b beq.n 800a5b6 800a57e: 687a ldr r2, [r7, #4] 800a580: 683b ldr r3, [r7, #0] 800a582: 781b ldrb r3, [r3, #0] 800a584: 009b lsls r3, r3, #2 800a586: 4413 add r3, r2 800a588: 881b ldrh r3, [r3, #0] 800a58a: b29b uxth r3, r3 800a58c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a590: f023 0370 bic.w r3, r3, #112 @ 0x70 800a594: 823b strh r3, [r7, #16] 800a596: 687a ldr r2, [r7, #4] 800a598: 683b ldr r3, [r7, #0] 800a59a: 781b ldrb r3, [r3, #0] 800a59c: 009b lsls r3, r3, #2 800a59e: 441a add r2, r3 800a5a0: 8a3b ldrh r3, [r7, #16] 800a5a2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a5a6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a5aa: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a5ae: f043 0380 orr.w r3, r3, #128 @ 0x80 800a5b2: b29b uxth r3, r3 800a5b4: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800a5b6: 687a ldr r2, [r7, #4] 800a5b8: 683b ldr r3, [r7, #0] 800a5ba: 781b ldrb r3, [r3, #0] 800a5bc: 009b lsls r3, r3, #2 800a5be: 4413 add r3, r2 800a5c0: 881b ldrh r3, [r3, #0] 800a5c2: b29b uxth r3, r3 800a5c4: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a5c8: f023 0370 bic.w r3, r3, #112 @ 0x70 800a5cc: 81fb strh r3, [r7, #14] 800a5ce: 687a ldr r2, [r7, #4] 800a5d0: 683b ldr r3, [r7, #0] 800a5d2: 781b ldrb r3, [r3, #0] 800a5d4: 009b lsls r3, r3, #2 800a5d6: 441a add r2, r3 800a5d8: 89fb ldrh r3, [r7, #14] 800a5da: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a5de: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a5e2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a5e6: f043 0380 orr.w r3, r3, #128 @ 0x80 800a5ea: b29b uxth r3, r3 800a5ec: 8013 strh r3, [r2, #0] 800a5ee: e14d b.n 800a88c } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->is_in == 0U) 800a5f0: 683b ldr r3, [r7, #0] 800a5f2: 785b ldrb r3, [r3, #1] 800a5f4: 2b00 cmp r3, #0 800a5f6: f040 80a5 bne.w 800a744 { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800a5fa: 687a ldr r2, [r7, #4] 800a5fc: 683b ldr r3, [r7, #0] 800a5fe: 781b ldrb r3, [r3, #0] 800a600: 009b lsls r3, r3, #2 800a602: 4413 add r3, r2 800a604: 881b ldrh r3, [r3, #0] 800a606: 843b strh r3, [r7, #32] 800a608: 8c3b ldrh r3, [r7, #32] 800a60a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a60e: 2b00 cmp r3, #0 800a610: d01b beq.n 800a64a 800a612: 687a ldr r2, [r7, #4] 800a614: 683b ldr r3, [r7, #0] 800a616: 781b ldrb r3, [r3, #0] 800a618: 009b lsls r3, r3, #2 800a61a: 4413 add r3, r2 800a61c: 881b ldrh r3, [r3, #0] 800a61e: b29b uxth r3, r3 800a620: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a624: f023 0370 bic.w r3, r3, #112 @ 0x70 800a628: 83fb strh r3, [r7, #30] 800a62a: 687a ldr r2, [r7, #4] 800a62c: 683b ldr r3, [r7, #0] 800a62e: 781b ldrb r3, [r3, #0] 800a630: 009b lsls r3, r3, #2 800a632: 441a add r2, r3 800a634: 8bfb ldrh r3, [r7, #30] 800a636: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a63a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a63e: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a642: f043 0380 orr.w r3, r3, #128 @ 0x80 800a646: b29b uxth r3, r3 800a648: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800a64a: 687a ldr r2, [r7, #4] 800a64c: 683b ldr r3, [r7, #0] 800a64e: 781b ldrb r3, [r3, #0] 800a650: 009b lsls r3, r3, #2 800a652: 4413 add r3, r2 800a654: 881b ldrh r3, [r3, #0] 800a656: 83bb strh r3, [r7, #28] 800a658: 8bbb ldrh r3, [r7, #28] 800a65a: f003 0340 and.w r3, r3, #64 @ 0x40 800a65e: 2b00 cmp r3, #0 800a660: d01b beq.n 800a69a 800a662: 687a ldr r2, [r7, #4] 800a664: 683b ldr r3, [r7, #0] 800a666: 781b ldrb r3, [r3, #0] 800a668: 009b lsls r3, r3, #2 800a66a: 4413 add r3, r2 800a66c: 881b ldrh r3, [r3, #0] 800a66e: b29b uxth r3, r3 800a670: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a674: f023 0370 bic.w r3, r3, #112 @ 0x70 800a678: 837b strh r3, [r7, #26] 800a67a: 687a ldr r2, [r7, #4] 800a67c: 683b ldr r3, [r7, #0] 800a67e: 781b ldrb r3, [r3, #0] 800a680: 009b lsls r3, r3, #2 800a682: 441a add r2, r3 800a684: 8b7b ldrh r3, [r7, #26] 800a686: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a68a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a68e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a692: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a696: b29b uxth r3, r3 800a698: 8013 strh r3, [r2, #0] /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); 800a69a: 687a ldr r2, [r7, #4] 800a69c: 683b ldr r3, [r7, #0] 800a69e: 781b ldrb r3, [r3, #0] 800a6a0: 009b lsls r3, r3, #2 800a6a2: 4413 add r3, r2 800a6a4: 881b ldrh r3, [r3, #0] 800a6a6: b29b uxth r3, r3 800a6a8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a6ac: f023 0370 bic.w r3, r3, #112 @ 0x70 800a6b0: 833b strh r3, [r7, #24] 800a6b2: 687a ldr r2, [r7, #4] 800a6b4: 683b ldr r3, [r7, #0] 800a6b6: 781b ldrb r3, [r3, #0] 800a6b8: 009b lsls r3, r3, #2 800a6ba: 441a add r2, r3 800a6bc: 8b3b ldrh r3, [r7, #24] 800a6be: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a6c2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a6c6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a6ca: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a6ce: b29b uxth r3, r3 800a6d0: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800a6d2: 687a ldr r2, [r7, #4] 800a6d4: 683b ldr r3, [r7, #0] 800a6d6: 781b ldrb r3, [r3, #0] 800a6d8: 009b lsls r3, r3, #2 800a6da: 4413 add r3, r2 800a6dc: 881b ldrh r3, [r3, #0] 800a6de: b29b uxth r3, r3 800a6e0: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a6e4: f023 0370 bic.w r3, r3, #112 @ 0x70 800a6e8: 82fb strh r3, [r7, #22] 800a6ea: 687a ldr r2, [r7, #4] 800a6ec: 683b ldr r3, [r7, #0] 800a6ee: 781b ldrb r3, [r3, #0] 800a6f0: 009b lsls r3, r3, #2 800a6f2: 441a add r2, r3 800a6f4: 8afb ldrh r3, [r7, #22] 800a6f6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a6fa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a6fe: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a702: f043 0380 orr.w r3, r3, #128 @ 0x80 800a706: b29b uxth r3, r3 800a708: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800a70a: 687a ldr r2, [r7, #4] 800a70c: 683b ldr r3, [r7, #0] 800a70e: 781b ldrb r3, [r3, #0] 800a710: 009b lsls r3, r3, #2 800a712: 4413 add r3, r2 800a714: 881b ldrh r3, [r3, #0] 800a716: b29b uxth r3, r3 800a718: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a71c: f023 0340 bic.w r3, r3, #64 @ 0x40 800a720: 82bb strh r3, [r7, #20] 800a722: 687a ldr r2, [r7, #4] 800a724: 683b ldr r3, [r7, #0] 800a726: 781b ldrb r3, [r3, #0] 800a728: 009b lsls r3, r3, #2 800a72a: 441a add r2, r3 800a72c: 8abb ldrh r3, [r7, #20] 800a72e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a732: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a736: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a73a: f043 0380 orr.w r3, r3, #128 @ 0x80 800a73e: b29b uxth r3, r3 800a740: 8013 strh r3, [r2, #0] 800a742: e0a3 b.n 800a88c } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800a744: 687a ldr r2, [r7, #4] 800a746: 683b ldr r3, [r7, #0] 800a748: 781b ldrb r3, [r3, #0] 800a74a: 009b lsls r3, r3, #2 800a74c: 4413 add r3, r2 800a74e: 881b ldrh r3, [r3, #0] 800a750: 85fb strh r3, [r7, #46] @ 0x2e 800a752: 8dfb ldrh r3, [r7, #46] @ 0x2e 800a754: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a758: 2b00 cmp r3, #0 800a75a: d01b beq.n 800a794 800a75c: 687a ldr r2, [r7, #4] 800a75e: 683b ldr r3, [r7, #0] 800a760: 781b ldrb r3, [r3, #0] 800a762: 009b lsls r3, r3, #2 800a764: 4413 add r3, r2 800a766: 881b ldrh r3, [r3, #0] 800a768: b29b uxth r3, r3 800a76a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a76e: f023 0370 bic.w r3, r3, #112 @ 0x70 800a772: 85bb strh r3, [r7, #44] @ 0x2c 800a774: 687a ldr r2, [r7, #4] 800a776: 683b ldr r3, [r7, #0] 800a778: 781b ldrb r3, [r3, #0] 800a77a: 009b lsls r3, r3, #2 800a77c: 441a add r2, r3 800a77e: 8dbb ldrh r3, [r7, #44] @ 0x2c 800a780: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a784: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a788: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a78c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a790: b29b uxth r3, r3 800a792: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800a794: 687a ldr r2, [r7, #4] 800a796: 683b ldr r3, [r7, #0] 800a798: 781b ldrb r3, [r3, #0] 800a79a: 009b lsls r3, r3, #2 800a79c: 4413 add r3, r2 800a79e: 881b ldrh r3, [r3, #0] 800a7a0: 857b strh r3, [r7, #42] @ 0x2a 800a7a2: 8d7b ldrh r3, [r7, #42] @ 0x2a 800a7a4: f003 0340 and.w r3, r3, #64 @ 0x40 800a7a8: 2b00 cmp r3, #0 800a7aa: d01b beq.n 800a7e4 800a7ac: 687a ldr r2, [r7, #4] 800a7ae: 683b ldr r3, [r7, #0] 800a7b0: 781b ldrb r3, [r3, #0] 800a7b2: 009b lsls r3, r3, #2 800a7b4: 4413 add r3, r2 800a7b6: 881b ldrh r3, [r3, #0] 800a7b8: b29b uxth r3, r3 800a7ba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a7be: f023 0370 bic.w r3, r3, #112 @ 0x70 800a7c2: 853b strh r3, [r7, #40] @ 0x28 800a7c4: 687a ldr r2, [r7, #4] 800a7c6: 683b ldr r3, [r7, #0] 800a7c8: 781b ldrb r3, [r3, #0] 800a7ca: 009b lsls r3, r3, #2 800a7cc: 441a add r2, r3 800a7ce: 8d3b ldrh r3, [r7, #40] @ 0x28 800a7d0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a7d4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a7d8: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a7dc: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a7e0: b29b uxth r3, r3 800a7e2: 8013 strh r3, [r2, #0] PCD_RX_DTOG(USBx, ep->num); 800a7e4: 687a ldr r2, [r7, #4] 800a7e6: 683b ldr r3, [r7, #0] 800a7e8: 781b ldrb r3, [r3, #0] 800a7ea: 009b lsls r3, r3, #2 800a7ec: 4413 add r3, r2 800a7ee: 881b ldrh r3, [r3, #0] 800a7f0: b29b uxth r3, r3 800a7f2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a7f6: f023 0370 bic.w r3, r3, #112 @ 0x70 800a7fa: 84fb strh r3, [r7, #38] @ 0x26 800a7fc: 687a ldr r2, [r7, #4] 800a7fe: 683b ldr r3, [r7, #0] 800a800: 781b ldrb r3, [r3, #0] 800a802: 009b lsls r3, r3, #2 800a804: 441a add r2, r3 800a806: 8cfb ldrh r3, [r7, #38] @ 0x26 800a808: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a80c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a810: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a814: f043 0380 orr.w r3, r3, #128 @ 0x80 800a818: b29b uxth r3, r3 800a81a: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800a81c: 687a ldr r2, [r7, #4] 800a81e: 683b ldr r3, [r7, #0] 800a820: 781b ldrb r3, [r3, #0] 800a822: 009b lsls r3, r3, #2 800a824: 4413 add r3, r2 800a826: 881b ldrh r3, [r3, #0] 800a828: b29b uxth r3, r3 800a82a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a82e: f023 0340 bic.w r3, r3, #64 @ 0x40 800a832: 84bb strh r3, [r7, #36] @ 0x24 800a834: 687a ldr r2, [r7, #4] 800a836: 683b ldr r3, [r7, #0] 800a838: 781b ldrb r3, [r3, #0] 800a83a: 009b lsls r3, r3, #2 800a83c: 441a add r2, r3 800a83e: 8cbb ldrh r3, [r7, #36] @ 0x24 800a840: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a844: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a848: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a84c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a850: b29b uxth r3, r3 800a852: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800a854: 687a ldr r2, [r7, #4] 800a856: 683b ldr r3, [r7, #0] 800a858: 781b ldrb r3, [r3, #0] 800a85a: 009b lsls r3, r3, #2 800a85c: 4413 add r3, r2 800a85e: 881b ldrh r3, [r3, #0] 800a860: b29b uxth r3, r3 800a862: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a866: f023 0370 bic.w r3, r3, #112 @ 0x70 800a86a: 847b strh r3, [r7, #34] @ 0x22 800a86c: 687a ldr r2, [r7, #4] 800a86e: 683b ldr r3, [r7, #0] 800a870: 781b ldrb r3, [r3, #0] 800a872: 009b lsls r3, r3, #2 800a874: 441a add r2, r3 800a876: 8c7b ldrh r3, [r7, #34] @ 0x22 800a878: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a87c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a880: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a884: f043 0380 orr.w r3, r3, #128 @ 0x80 800a888: b29b uxth r3, r3 800a88a: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; 800a88c: 2300 movs r3, #0 } 800a88e: 4618 mov r0, r3 800a890: 3734 adds r7, #52 @ 0x34 800a892: 46bd mov sp, r7 800a894: bc80 pop {r7} 800a896: 4770 bx lr 0800a898 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800a898: b580 push {r7, lr} 800a89a: b0c2 sub sp, #264 @ 0x108 800a89c: af00 add r7, sp, #0 800a89e: f507 7384 add.w r3, r7, #264 @ 0x108 800a8a2: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800a8a6: 6018 str r0, [r3, #0] 800a8a8: f507 7384 add.w r3, r7, #264 @ 0x108 800a8ac: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a8b0: 6019 str r1, [r3, #0] uint16_t pmabuffer; uint16_t wEPVal; #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* IN endpoint */ if (ep->is_in == 1U) 800a8b2: f507 7384 add.w r3, r7, #264 @ 0x108 800a8b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a8ba: 681b ldr r3, [r3, #0] 800a8bc: 785b ldrb r3, [r3, #1] 800a8be: 2b01 cmp r3, #1 800a8c0: f040 86b7 bne.w 800b632 { /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) 800a8c4: f507 7384 add.w r3, r7, #264 @ 0x108 800a8c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a8cc: 681b ldr r3, [r3, #0] 800a8ce: 699a ldr r2, [r3, #24] 800a8d0: f507 7384 add.w r3, r7, #264 @ 0x108 800a8d4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a8d8: 681b ldr r3, [r3, #0] 800a8da: 691b ldr r3, [r3, #16] 800a8dc: 429a cmp r2, r3 800a8de: d908 bls.n 800a8f2 { len = ep->maxpacket; 800a8e0: f507 7384 add.w r3, r7, #264 @ 0x108 800a8e4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a8e8: 681b ldr r3, [r3, #0] 800a8ea: 691b ldr r3, [r3, #16] 800a8ec: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800a8f0: e007 b.n 800a902 } else { len = ep->xfer_len; 800a8f2: f507 7384 add.w r3, r7, #264 @ 0x108 800a8f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a8fa: 681b ldr r3, [r3, #0] 800a8fc: 699b ldr r3, [r3, #24] 800a8fe: f8c7 3104 str.w r3, [r7, #260] @ 0x104 } /* configure and validate Tx endpoint */ if (ep->doublebuffer == 0U) 800a902: f507 7384 add.w r3, r7, #264 @ 0x108 800a906: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a90a: 681b ldr r3, [r3, #0] 800a90c: 7b1b ldrb r3, [r3, #12] 800a90e: 2b00 cmp r3, #0 800a910: d13a bne.n 800a988 { USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); 800a912: f507 7384 add.w r3, r7, #264 @ 0x108 800a916: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a91a: 681b ldr r3, [r3, #0] 800a91c: 6959 ldr r1, [r3, #20] 800a91e: f507 7384 add.w r3, r7, #264 @ 0x108 800a922: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a926: 681b ldr r3, [r3, #0] 800a928: 88da ldrh r2, [r3, #6] 800a92a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800a92e: b29b uxth r3, r3 800a930: f507 7084 add.w r0, r7, #264 @ 0x108 800a934: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800a938: 6800 ldr r0, [r0, #0] 800a93a: f001 fc9c bl 800c276 PCD_SET_EP_TX_CNT(USBx, ep->num, len); 800a93e: f507 7384 add.w r3, r7, #264 @ 0x108 800a942: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800a946: 681b ldr r3, [r3, #0] 800a948: 613b str r3, [r7, #16] 800a94a: f507 7384 add.w r3, r7, #264 @ 0x108 800a94e: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800a952: 681b ldr r3, [r3, #0] 800a954: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a958: b29b uxth r3, r3 800a95a: 461a mov r2, r3 800a95c: 693b ldr r3, [r7, #16] 800a95e: 4413 add r3, r2 800a960: 613b str r3, [r7, #16] 800a962: f507 7384 add.w r3, r7, #264 @ 0x108 800a966: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a96a: 681b ldr r3, [r3, #0] 800a96c: 781b ldrb r3, [r3, #0] 800a96e: 011a lsls r2, r3, #4 800a970: 693b ldr r3, [r7, #16] 800a972: 4413 add r3, r2 800a974: f203 4304 addw r3, r3, #1028 @ 0x404 800a978: 60fb str r3, [r7, #12] 800a97a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800a97e: b29a uxth r2, r3 800a980: 68fb ldr r3, [r7, #12] 800a982: 801a strh r2, [r3, #0] 800a984: f000 be1f b.w 800b5c6 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* double buffer bulk management */ if (ep->type == EP_TYPE_BULK) 800a988: f507 7384 add.w r3, r7, #264 @ 0x108 800a98c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a990: 681b ldr r3, [r3, #0] 800a992: 78db ldrb r3, [r3, #3] 800a994: 2b02 cmp r3, #2 800a996: f040 8462 bne.w 800b25e { if (ep->xfer_len_db > ep->maxpacket) 800a99a: f507 7384 add.w r3, r7, #264 @ 0x108 800a99e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a9a2: 681b ldr r3, [r3, #0] 800a9a4: 6a1a ldr r2, [r3, #32] 800a9a6: f507 7384 add.w r3, r7, #264 @ 0x108 800a9aa: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a9ae: 681b ldr r3, [r3, #0] 800a9b0: 691b ldr r3, [r3, #16] 800a9b2: 429a cmp r2, r3 800a9b4: f240 83df bls.w 800b176 { /* enable double buffer */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); 800a9b8: f507 7384 add.w r3, r7, #264 @ 0x108 800a9bc: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800a9c0: 681a ldr r2, [r3, #0] 800a9c2: f507 7384 add.w r3, r7, #264 @ 0x108 800a9c6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a9ca: 681b ldr r3, [r3, #0] 800a9cc: 781b ldrb r3, [r3, #0] 800a9ce: 009b lsls r3, r3, #2 800a9d0: 4413 add r3, r2 800a9d2: 881b ldrh r3, [r3, #0] 800a9d4: b29b uxth r3, r3 800a9d6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a9da: f023 0370 bic.w r3, r3, #112 @ 0x70 800a9de: f8a7 3056 strh.w r3, [r7, #86] @ 0x56 800a9e2: f507 7384 add.w r3, r7, #264 @ 0x108 800a9e6: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800a9ea: 681a ldr r2, [r3, #0] 800a9ec: f507 7384 add.w r3, r7, #264 @ 0x108 800a9f0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800a9f4: 681b ldr r3, [r3, #0] 800a9f6: 781b ldrb r3, [r3, #0] 800a9f8: 009b lsls r3, r3, #2 800a9fa: 441a add r2, r3 800a9fc: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56 800aa00: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800aa04: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800aa08: f443 4301 orr.w r3, r3, #33024 @ 0x8100 800aa0c: f043 0380 orr.w r3, r3, #128 @ 0x80 800aa10: b29b uxth r3, r3 800aa12: 8013 strh r3, [r2, #0] /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; 800aa14: f507 7384 add.w r3, r7, #264 @ 0x108 800aa18: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800aa1c: 681b ldr r3, [r3, #0] 800aa1e: 6a1a ldr r2, [r3, #32] 800aa20: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800aa24: 1ad2 subs r2, r2, r3 800aa26: f507 7384 add.w r3, r7, #264 @ 0x108 800aa2a: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800aa2e: 681b ldr r3, [r3, #0] 800aa30: 621a str r2, [r3, #32] /* Fill the two first buffer in the Buffer0 & Buffer1 */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) 800aa32: f507 7384 add.w r3, r7, #264 @ 0x108 800aa36: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800aa3a: 681a ldr r2, [r3, #0] 800aa3c: f507 7384 add.w r3, r7, #264 @ 0x108 800aa40: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800aa44: 681b ldr r3, [r3, #0] 800aa46: 781b ldrb r3, [r3, #0] 800aa48: 009b lsls r3, r3, #2 800aa4a: 4413 add r3, r2 800aa4c: 881b ldrh r3, [r3, #0] 800aa4e: b29b uxth r3, r3 800aa50: f003 0340 and.w r3, r3, #64 @ 0x40 800aa54: 2b00 cmp r3, #0 800aa56: f000 81c7 beq.w 800ade8 { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 800aa5a: f507 7384 add.w r3, r7, #264 @ 0x108 800aa5e: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800aa62: 681b ldr r3, [r3, #0] 800aa64: 633b str r3, [r7, #48] @ 0x30 800aa66: f507 7384 add.w r3, r7, #264 @ 0x108 800aa6a: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800aa6e: 681b ldr r3, [r3, #0] 800aa70: 785b ldrb r3, [r3, #1] 800aa72: 2b00 cmp r3, #0 800aa74: d177 bne.n 800ab66 800aa76: f507 7384 add.w r3, r7, #264 @ 0x108 800aa7a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800aa7e: 681b ldr r3, [r3, #0] 800aa80: 62bb str r3, [r7, #40] @ 0x28 800aa82: f507 7384 add.w r3, r7, #264 @ 0x108 800aa86: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800aa8a: 681b ldr r3, [r3, #0] 800aa8c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800aa90: b29b uxth r3, r3 800aa92: 461a mov r2, r3 800aa94: 6abb ldr r3, [r7, #40] @ 0x28 800aa96: 4413 add r3, r2 800aa98: 62bb str r3, [r7, #40] @ 0x28 800aa9a: f507 7384 add.w r3, r7, #264 @ 0x108 800aa9e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800aaa2: 681b ldr r3, [r3, #0] 800aaa4: 781b ldrb r3, [r3, #0] 800aaa6: 011a lsls r2, r3, #4 800aaa8: 6abb ldr r3, [r7, #40] @ 0x28 800aaaa: 4413 add r3, r2 800aaac: f203 430c addw r3, r3, #1036 @ 0x40c 800aab0: 627b str r3, [r7, #36] @ 0x24 800aab2: 6a7b ldr r3, [r7, #36] @ 0x24 800aab4: 881b ldrh r3, [r3, #0] 800aab6: b29b uxth r3, r3 800aab8: f3c3 0309 ubfx r3, r3, #0, #10 800aabc: b29a uxth r2, r3 800aabe: 6a7b ldr r3, [r7, #36] @ 0x24 800aac0: 801a strh r2, [r3, #0] 800aac2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800aac6: 2b3e cmp r3, #62 @ 0x3e 800aac8: d921 bls.n 800ab0e 800aaca: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800aace: 095b lsrs r3, r3, #5 800aad0: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800aad4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800aad8: f003 031f and.w r3, r3, #31 800aadc: 2b00 cmp r3, #0 800aade: d104 bne.n 800aaea 800aae0: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100 800aae4: 3b01 subs r3, #1 800aae6: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800aaea: 6a7b ldr r3, [r7, #36] @ 0x24 800aaec: 881b ldrh r3, [r3, #0] 800aaee: b29a uxth r2, r3 800aaf0: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100 800aaf4: b29b uxth r3, r3 800aaf6: 029b lsls r3, r3, #10 800aaf8: b29b uxth r3, r3 800aafa: 4313 orrs r3, r2 800aafc: b29b uxth r3, r3 800aafe: ea6f 4343 mvn.w r3, r3, lsl #17 800ab02: ea6f 4353 mvn.w r3, r3, lsr #17 800ab06: b29a uxth r2, r3 800ab08: 6a7b ldr r3, [r7, #36] @ 0x24 800ab0a: 801a strh r2, [r3, #0] 800ab0c: e050 b.n 800abb0 800ab0e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ab12: 2b00 cmp r3, #0 800ab14: d10a bne.n 800ab2c 800ab16: 6a7b ldr r3, [r7, #36] @ 0x24 800ab18: 881b ldrh r3, [r3, #0] 800ab1a: b29b uxth r3, r3 800ab1c: ea6f 4343 mvn.w r3, r3, lsl #17 800ab20: ea6f 4353 mvn.w r3, r3, lsr #17 800ab24: b29a uxth r2, r3 800ab26: 6a7b ldr r3, [r7, #36] @ 0x24 800ab28: 801a strh r2, [r3, #0] 800ab2a: e041 b.n 800abb0 800ab2c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ab30: 085b lsrs r3, r3, #1 800ab32: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800ab36: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ab3a: f003 0301 and.w r3, r3, #1 800ab3e: 2b00 cmp r3, #0 800ab40: d004 beq.n 800ab4c 800ab42: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100 800ab46: 3301 adds r3, #1 800ab48: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800ab4c: 6a7b ldr r3, [r7, #36] @ 0x24 800ab4e: 881b ldrh r3, [r3, #0] 800ab50: b29a uxth r2, r3 800ab52: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100 800ab56: b29b uxth r3, r3 800ab58: 029b lsls r3, r3, #10 800ab5a: b29b uxth r3, r3 800ab5c: 4313 orrs r3, r2 800ab5e: b29a uxth r2, r3 800ab60: 6a7b ldr r3, [r7, #36] @ 0x24 800ab62: 801a strh r2, [r3, #0] 800ab64: e024 b.n 800abb0 800ab66: f507 7384 add.w r3, r7, #264 @ 0x108 800ab6a: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ab6e: 681b ldr r3, [r3, #0] 800ab70: 785b ldrb r3, [r3, #1] 800ab72: 2b01 cmp r3, #1 800ab74: d11c bne.n 800abb0 800ab76: f507 7384 add.w r3, r7, #264 @ 0x108 800ab7a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ab7e: 681b ldr r3, [r3, #0] 800ab80: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ab84: b29b uxth r3, r3 800ab86: 461a mov r2, r3 800ab88: 6b3b ldr r3, [r7, #48] @ 0x30 800ab8a: 4413 add r3, r2 800ab8c: 633b str r3, [r7, #48] @ 0x30 800ab8e: f507 7384 add.w r3, r7, #264 @ 0x108 800ab92: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ab96: 681b ldr r3, [r3, #0] 800ab98: 781b ldrb r3, [r3, #0] 800ab9a: 011a lsls r2, r3, #4 800ab9c: 6b3b ldr r3, [r7, #48] @ 0x30 800ab9e: 4413 add r3, r2 800aba0: f203 430c addw r3, r3, #1036 @ 0x40c 800aba4: 62fb str r3, [r7, #44] @ 0x2c 800aba6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800abaa: b29a uxth r2, r3 800abac: 6afb ldr r3, [r7, #44] @ 0x2c 800abae: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 800abb0: f507 7384 add.w r3, r7, #264 @ 0x108 800abb4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800abb8: 681b ldr r3, [r3, #0] 800abba: 895b ldrh r3, [r3, #10] 800abbc: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800abc0: f507 7384 add.w r3, r7, #264 @ 0x108 800abc4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800abc8: 681b ldr r3, [r3, #0] 800abca: 6959 ldr r1, [r3, #20] 800abcc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800abd0: b29b uxth r3, r3 800abd2: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800abd6: f507 7084 add.w r0, r7, #264 @ 0x108 800abda: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800abde: 6800 ldr r0, [r0, #0] 800abe0: f001 fb49 bl 800c276 ep->xfer_buff += len; 800abe4: f507 7384 add.w r3, r7, #264 @ 0x108 800abe8: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800abec: 681b ldr r3, [r3, #0] 800abee: 695a ldr r2, [r3, #20] 800abf0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800abf4: 441a add r2, r3 800abf6: f507 7384 add.w r3, r7, #264 @ 0x108 800abfa: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800abfe: 681b ldr r3, [r3, #0] 800ac00: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) 800ac02: f507 7384 add.w r3, r7, #264 @ 0x108 800ac06: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac0a: 681b ldr r3, [r3, #0] 800ac0c: 6a1a ldr r2, [r3, #32] 800ac0e: f507 7384 add.w r3, r7, #264 @ 0x108 800ac12: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac16: 681b ldr r3, [r3, #0] 800ac18: 691b ldr r3, [r3, #16] 800ac1a: 429a cmp r2, r3 800ac1c: d90f bls.n 800ac3e { ep->xfer_len_db -= len; 800ac1e: f507 7384 add.w r3, r7, #264 @ 0x108 800ac22: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac26: 681b ldr r3, [r3, #0] 800ac28: 6a1a ldr r2, [r3, #32] 800ac2a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ac2e: 1ad2 subs r2, r2, r3 800ac30: f507 7384 add.w r3, r7, #264 @ 0x108 800ac34: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac38: 681b ldr r3, [r3, #0] 800ac3a: 621a str r2, [r3, #32] 800ac3c: e00e b.n 800ac5c } else { len = ep->xfer_len_db; 800ac3e: f507 7384 add.w r3, r7, #264 @ 0x108 800ac42: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac46: 681b ldr r3, [r3, #0] 800ac48: 6a1b ldr r3, [r3, #32] 800ac4a: f8c7 3104 str.w r3, [r7, #260] @ 0x104 ep->xfer_len_db = 0U; 800ac4e: f507 7384 add.w r3, r7, #264 @ 0x108 800ac52: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac56: 681b ldr r3, [r3, #0] 800ac58: 2200 movs r2, #0 800ac5a: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 800ac5c: f507 7384 add.w r3, r7, #264 @ 0x108 800ac60: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac64: 681b ldr r3, [r3, #0] 800ac66: 785b ldrb r3, [r3, #1] 800ac68: 2b00 cmp r3, #0 800ac6a: d177 bne.n 800ad5c 800ac6c: f507 7384 add.w r3, r7, #264 @ 0x108 800ac70: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ac74: 681b ldr r3, [r3, #0] 800ac76: 61bb str r3, [r7, #24] 800ac78: f507 7384 add.w r3, r7, #264 @ 0x108 800ac7c: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ac80: 681b ldr r3, [r3, #0] 800ac82: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ac86: b29b uxth r3, r3 800ac88: 461a mov r2, r3 800ac8a: 69bb ldr r3, [r7, #24] 800ac8c: 4413 add r3, r2 800ac8e: 61bb str r3, [r7, #24] 800ac90: f507 7384 add.w r3, r7, #264 @ 0x108 800ac94: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ac98: 681b ldr r3, [r3, #0] 800ac9a: 781b ldrb r3, [r3, #0] 800ac9c: 011a lsls r2, r3, #4 800ac9e: 69bb ldr r3, [r7, #24] 800aca0: 4413 add r3, r2 800aca2: f203 4304 addw r3, r3, #1028 @ 0x404 800aca6: 617b str r3, [r7, #20] 800aca8: 697b ldr r3, [r7, #20] 800acaa: 881b ldrh r3, [r3, #0] 800acac: b29b uxth r3, r3 800acae: f3c3 0309 ubfx r3, r3, #0, #10 800acb2: b29a uxth r2, r3 800acb4: 697b ldr r3, [r7, #20] 800acb6: 801a strh r2, [r3, #0] 800acb8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800acbc: 2b3e cmp r3, #62 @ 0x3e 800acbe: d921 bls.n 800ad04 800acc0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800acc4: 095b lsrs r3, r3, #5 800acc6: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800acca: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800acce: f003 031f and.w r3, r3, #31 800acd2: 2b00 cmp r3, #0 800acd4: d104 bne.n 800ace0 800acd6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800acda: 3b01 subs r3, #1 800acdc: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800ace0: 697b ldr r3, [r7, #20] 800ace2: 881b ldrh r3, [r3, #0] 800ace4: b29a uxth r2, r3 800ace6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800acea: b29b uxth r3, r3 800acec: 029b lsls r3, r3, #10 800acee: b29b uxth r3, r3 800acf0: 4313 orrs r3, r2 800acf2: b29b uxth r3, r3 800acf4: ea6f 4343 mvn.w r3, r3, lsl #17 800acf8: ea6f 4353 mvn.w r3, r3, lsr #17 800acfc: b29a uxth r2, r3 800acfe: 697b ldr r3, [r7, #20] 800ad00: 801a strh r2, [r3, #0] 800ad02: e056 b.n 800adb2 800ad04: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ad08: 2b00 cmp r3, #0 800ad0a: d10a bne.n 800ad22 800ad0c: 697b ldr r3, [r7, #20] 800ad0e: 881b ldrh r3, [r3, #0] 800ad10: b29b uxth r3, r3 800ad12: ea6f 4343 mvn.w r3, r3, lsl #17 800ad16: ea6f 4353 mvn.w r3, r3, lsr #17 800ad1a: b29a uxth r2, r3 800ad1c: 697b ldr r3, [r7, #20] 800ad1e: 801a strh r2, [r3, #0] 800ad20: e047 b.n 800adb2 800ad22: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ad26: 085b lsrs r3, r3, #1 800ad28: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800ad2c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ad30: f003 0301 and.w r3, r3, #1 800ad34: 2b00 cmp r3, #0 800ad36: d004 beq.n 800ad42 800ad38: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800ad3c: 3301 adds r3, #1 800ad3e: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800ad42: 697b ldr r3, [r7, #20] 800ad44: 881b ldrh r3, [r3, #0] 800ad46: b29a uxth r2, r3 800ad48: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800ad4c: b29b uxth r3, r3 800ad4e: 029b lsls r3, r3, #10 800ad50: b29b uxth r3, r3 800ad52: 4313 orrs r3, r2 800ad54: b29a uxth r2, r3 800ad56: 697b ldr r3, [r7, #20] 800ad58: 801a strh r2, [r3, #0] 800ad5a: e02a b.n 800adb2 800ad5c: f507 7384 add.w r3, r7, #264 @ 0x108 800ad60: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ad64: 681b ldr r3, [r3, #0] 800ad66: 785b ldrb r3, [r3, #1] 800ad68: 2b01 cmp r3, #1 800ad6a: d122 bne.n 800adb2 800ad6c: f507 7384 add.w r3, r7, #264 @ 0x108 800ad70: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ad74: 681b ldr r3, [r3, #0] 800ad76: 623b str r3, [r7, #32] 800ad78: f507 7384 add.w r3, r7, #264 @ 0x108 800ad7c: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ad80: 681b ldr r3, [r3, #0] 800ad82: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ad86: b29b uxth r3, r3 800ad88: 461a mov r2, r3 800ad8a: 6a3b ldr r3, [r7, #32] 800ad8c: 4413 add r3, r2 800ad8e: 623b str r3, [r7, #32] 800ad90: f507 7384 add.w r3, r7, #264 @ 0x108 800ad94: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ad98: 681b ldr r3, [r3, #0] 800ad9a: 781b ldrb r3, [r3, #0] 800ad9c: 011a lsls r2, r3, #4 800ad9e: 6a3b ldr r3, [r7, #32] 800ada0: 4413 add r3, r2 800ada2: f203 4304 addw r3, r3, #1028 @ 0x404 800ada6: 61fb str r3, [r7, #28] 800ada8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800adac: b29a uxth r2, r3 800adae: 69fb ldr r3, [r7, #28] 800adb0: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800adb2: f507 7384 add.w r3, r7, #264 @ 0x108 800adb6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800adba: 681b ldr r3, [r3, #0] 800adbc: 891b ldrh r3, [r3, #8] 800adbe: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800adc2: f507 7384 add.w r3, r7, #264 @ 0x108 800adc6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800adca: 681b ldr r3, [r3, #0] 800adcc: 6959 ldr r1, [r3, #20] 800adce: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800add2: b29b uxth r3, r3 800add4: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800add8: f507 7084 add.w r0, r7, #264 @ 0x108 800addc: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800ade0: 6800 ldr r0, [r0, #0] 800ade2: f001 fa48 bl 800c276 800ade6: e3ee b.n 800b5c6 } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 800ade8: f507 7384 add.w r3, r7, #264 @ 0x108 800adec: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800adf0: 681b ldr r3, [r3, #0] 800adf2: 785b ldrb r3, [r3, #1] 800adf4: 2b00 cmp r3, #0 800adf6: d177 bne.n 800aee8 800adf8: f507 7384 add.w r3, r7, #264 @ 0x108 800adfc: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ae00: 681b ldr r3, [r3, #0] 800ae02: 64bb str r3, [r7, #72] @ 0x48 800ae04: f507 7384 add.w r3, r7, #264 @ 0x108 800ae08: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800ae0c: 681b ldr r3, [r3, #0] 800ae0e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ae12: b29b uxth r3, r3 800ae14: 461a mov r2, r3 800ae16: 6cbb ldr r3, [r7, #72] @ 0x48 800ae18: 4413 add r3, r2 800ae1a: 64bb str r3, [r7, #72] @ 0x48 800ae1c: f507 7384 add.w r3, r7, #264 @ 0x108 800ae20: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ae24: 681b ldr r3, [r3, #0] 800ae26: 781b ldrb r3, [r3, #0] 800ae28: 011a lsls r2, r3, #4 800ae2a: 6cbb ldr r3, [r7, #72] @ 0x48 800ae2c: 4413 add r3, r2 800ae2e: f203 4304 addw r3, r3, #1028 @ 0x404 800ae32: 647b str r3, [r7, #68] @ 0x44 800ae34: 6c7b ldr r3, [r7, #68] @ 0x44 800ae36: 881b ldrh r3, [r3, #0] 800ae38: b29b uxth r3, r3 800ae3a: f3c3 0309 ubfx r3, r3, #0, #10 800ae3e: b29a uxth r2, r3 800ae40: 6c7b ldr r3, [r7, #68] @ 0x44 800ae42: 801a strh r2, [r3, #0] 800ae44: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ae48: 2b3e cmp r3, #62 @ 0x3e 800ae4a: d921 bls.n 800ae90 800ae4c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ae50: 095b lsrs r3, r3, #5 800ae52: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800ae56: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ae5a: f003 031f and.w r3, r3, #31 800ae5e: 2b00 cmp r3, #0 800ae60: d104 bne.n 800ae6c 800ae62: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 800ae66: 3b01 subs r3, #1 800ae68: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800ae6c: 6c7b ldr r3, [r7, #68] @ 0x44 800ae6e: 881b ldrh r3, [r3, #0] 800ae70: b29a uxth r2, r3 800ae72: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 800ae76: b29b uxth r3, r3 800ae78: 029b lsls r3, r3, #10 800ae7a: b29b uxth r3, r3 800ae7c: 4313 orrs r3, r2 800ae7e: b29b uxth r3, r3 800ae80: ea6f 4343 mvn.w r3, r3, lsl #17 800ae84: ea6f 4353 mvn.w r3, r3, lsr #17 800ae88: b29a uxth r2, r3 800ae8a: 6c7b ldr r3, [r7, #68] @ 0x44 800ae8c: 801a strh r2, [r3, #0] 800ae8e: e056 b.n 800af3e 800ae90: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800ae94: 2b00 cmp r3, #0 800ae96: d10a bne.n 800aeae 800ae98: 6c7b ldr r3, [r7, #68] @ 0x44 800ae9a: 881b ldrh r3, [r3, #0] 800ae9c: b29b uxth r3, r3 800ae9e: ea6f 4343 mvn.w r3, r3, lsl #17 800aea2: ea6f 4353 mvn.w r3, r3, lsr #17 800aea6: b29a uxth r2, r3 800aea8: 6c7b ldr r3, [r7, #68] @ 0x44 800aeaa: 801a strh r2, [r3, #0] 800aeac: e047 b.n 800af3e 800aeae: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800aeb2: 085b lsrs r3, r3, #1 800aeb4: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800aeb8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800aebc: f003 0301 and.w r3, r3, #1 800aec0: 2b00 cmp r3, #0 800aec2: d004 beq.n 800aece 800aec4: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 800aec8: 3301 adds r3, #1 800aeca: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800aece: 6c7b ldr r3, [r7, #68] @ 0x44 800aed0: 881b ldrh r3, [r3, #0] 800aed2: b29a uxth r2, r3 800aed4: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 800aed8: b29b uxth r3, r3 800aeda: 029b lsls r3, r3, #10 800aedc: b29b uxth r3, r3 800aede: 4313 orrs r3, r2 800aee0: b29a uxth r2, r3 800aee2: 6c7b ldr r3, [r7, #68] @ 0x44 800aee4: 801a strh r2, [r3, #0] 800aee6: e02a b.n 800af3e 800aee8: f507 7384 add.w r3, r7, #264 @ 0x108 800aeec: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800aef0: 681b ldr r3, [r3, #0] 800aef2: 785b ldrb r3, [r3, #1] 800aef4: 2b01 cmp r3, #1 800aef6: d122 bne.n 800af3e 800aef8: f507 7384 add.w r3, r7, #264 @ 0x108 800aefc: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800af00: 681b ldr r3, [r3, #0] 800af02: 653b str r3, [r7, #80] @ 0x50 800af04: f507 7384 add.w r3, r7, #264 @ 0x108 800af08: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800af0c: 681b ldr r3, [r3, #0] 800af0e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800af12: b29b uxth r3, r3 800af14: 461a mov r2, r3 800af16: 6d3b ldr r3, [r7, #80] @ 0x50 800af18: 4413 add r3, r2 800af1a: 653b str r3, [r7, #80] @ 0x50 800af1c: f507 7384 add.w r3, r7, #264 @ 0x108 800af20: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800af24: 681b ldr r3, [r3, #0] 800af26: 781b ldrb r3, [r3, #0] 800af28: 011a lsls r2, r3, #4 800af2a: 6d3b ldr r3, [r7, #80] @ 0x50 800af2c: 4413 add r3, r2 800af2e: f203 4304 addw r3, r3, #1028 @ 0x404 800af32: 64fb str r3, [r7, #76] @ 0x4c 800af34: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800af38: b29a uxth r2, r3 800af3a: 6cfb ldr r3, [r7, #76] @ 0x4c 800af3c: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800af3e: f507 7384 add.w r3, r7, #264 @ 0x108 800af42: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800af46: 681b ldr r3, [r3, #0] 800af48: 891b ldrh r3, [r3, #8] 800af4a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800af4e: f507 7384 add.w r3, r7, #264 @ 0x108 800af52: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800af56: 681b ldr r3, [r3, #0] 800af58: 6959 ldr r1, [r3, #20] 800af5a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800af5e: b29b uxth r3, r3 800af60: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800af64: f507 7084 add.w r0, r7, #264 @ 0x108 800af68: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800af6c: 6800 ldr r0, [r0, #0] 800af6e: f001 f982 bl 800c276 ep->xfer_buff += len; 800af72: f507 7384 add.w r3, r7, #264 @ 0x108 800af76: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800af7a: 681b ldr r3, [r3, #0] 800af7c: 695a ldr r2, [r3, #20] 800af7e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800af82: 441a add r2, r3 800af84: f507 7384 add.w r3, r7, #264 @ 0x108 800af88: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800af8c: 681b ldr r3, [r3, #0] 800af8e: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) 800af90: f507 7384 add.w r3, r7, #264 @ 0x108 800af94: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800af98: 681b ldr r3, [r3, #0] 800af9a: 6a1a ldr r2, [r3, #32] 800af9c: f507 7384 add.w r3, r7, #264 @ 0x108 800afa0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800afa4: 681b ldr r3, [r3, #0] 800afa6: 691b ldr r3, [r3, #16] 800afa8: 429a cmp r2, r3 800afaa: d90f bls.n 800afcc { ep->xfer_len_db -= len; 800afac: f507 7384 add.w r3, r7, #264 @ 0x108 800afb0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800afb4: 681b ldr r3, [r3, #0] 800afb6: 6a1a ldr r2, [r3, #32] 800afb8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800afbc: 1ad2 subs r2, r2, r3 800afbe: f507 7384 add.w r3, r7, #264 @ 0x108 800afc2: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800afc6: 681b ldr r3, [r3, #0] 800afc8: 621a str r2, [r3, #32] 800afca: e00e b.n 800afea } else { len = ep->xfer_len_db; 800afcc: f507 7384 add.w r3, r7, #264 @ 0x108 800afd0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800afd4: 681b ldr r3, [r3, #0] 800afd6: 6a1b ldr r3, [r3, #32] 800afd8: f8c7 3104 str.w r3, [r7, #260] @ 0x104 ep->xfer_len_db = 0U; 800afdc: f507 7384 add.w r3, r7, #264 @ 0x108 800afe0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800afe4: 681b ldr r3, [r3, #0] 800afe6: 2200 movs r2, #0 800afe8: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 800afea: f507 7384 add.w r3, r7, #264 @ 0x108 800afee: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800aff2: 681b ldr r3, [r3, #0] 800aff4: 643b str r3, [r7, #64] @ 0x40 800aff6: f507 7384 add.w r3, r7, #264 @ 0x108 800affa: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800affe: 681b ldr r3, [r3, #0] 800b000: 785b ldrb r3, [r3, #1] 800b002: 2b00 cmp r3, #0 800b004: d177 bne.n 800b0f6 800b006: f507 7384 add.w r3, r7, #264 @ 0x108 800b00a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b00e: 681b ldr r3, [r3, #0] 800b010: 63bb str r3, [r7, #56] @ 0x38 800b012: f507 7384 add.w r3, r7, #264 @ 0x108 800b016: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b01a: 681b ldr r3, [r3, #0] 800b01c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b020: b29b uxth r3, r3 800b022: 461a mov r2, r3 800b024: 6bbb ldr r3, [r7, #56] @ 0x38 800b026: 4413 add r3, r2 800b028: 63bb str r3, [r7, #56] @ 0x38 800b02a: f507 7384 add.w r3, r7, #264 @ 0x108 800b02e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b032: 681b ldr r3, [r3, #0] 800b034: 781b ldrb r3, [r3, #0] 800b036: 011a lsls r2, r3, #4 800b038: 6bbb ldr r3, [r7, #56] @ 0x38 800b03a: 4413 add r3, r2 800b03c: f203 430c addw r3, r3, #1036 @ 0x40c 800b040: 637b str r3, [r7, #52] @ 0x34 800b042: 6b7b ldr r3, [r7, #52] @ 0x34 800b044: 881b ldrh r3, [r3, #0] 800b046: b29b uxth r3, r3 800b048: f3c3 0309 ubfx r3, r3, #0, #10 800b04c: b29a uxth r2, r3 800b04e: 6b7b ldr r3, [r7, #52] @ 0x34 800b050: 801a strh r2, [r3, #0] 800b052: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b056: 2b3e cmp r3, #62 @ 0x3e 800b058: d921 bls.n 800b09e 800b05a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b05e: 095b lsrs r3, r3, #5 800b060: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800b064: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b068: f003 031f and.w r3, r3, #31 800b06c: 2b00 cmp r3, #0 800b06e: d104 bne.n 800b07a 800b070: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800b074: 3b01 subs r3, #1 800b076: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800b07a: 6b7b ldr r3, [r7, #52] @ 0x34 800b07c: 881b ldrh r3, [r3, #0] 800b07e: b29a uxth r2, r3 800b080: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800b084: b29b uxth r3, r3 800b086: 029b lsls r3, r3, #10 800b088: b29b uxth r3, r3 800b08a: 4313 orrs r3, r2 800b08c: b29b uxth r3, r3 800b08e: ea6f 4343 mvn.w r3, r3, lsl #17 800b092: ea6f 4353 mvn.w r3, r3, lsr #17 800b096: b29a uxth r2, r3 800b098: 6b7b ldr r3, [r7, #52] @ 0x34 800b09a: 801a strh r2, [r3, #0] 800b09c: e050 b.n 800b140 800b09e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b0a2: 2b00 cmp r3, #0 800b0a4: d10a bne.n 800b0bc 800b0a6: 6b7b ldr r3, [r7, #52] @ 0x34 800b0a8: 881b ldrh r3, [r3, #0] 800b0aa: b29b uxth r3, r3 800b0ac: ea6f 4343 mvn.w r3, r3, lsl #17 800b0b0: ea6f 4353 mvn.w r3, r3, lsr #17 800b0b4: b29a uxth r2, r3 800b0b6: 6b7b ldr r3, [r7, #52] @ 0x34 800b0b8: 801a strh r2, [r3, #0] 800b0ba: e041 b.n 800b140 800b0bc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b0c0: 085b lsrs r3, r3, #1 800b0c2: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800b0c6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b0ca: f003 0301 and.w r3, r3, #1 800b0ce: 2b00 cmp r3, #0 800b0d0: d004 beq.n 800b0dc 800b0d2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800b0d6: 3301 adds r3, #1 800b0d8: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800b0dc: 6b7b ldr r3, [r7, #52] @ 0x34 800b0de: 881b ldrh r3, [r3, #0] 800b0e0: b29a uxth r2, r3 800b0e2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800b0e6: b29b uxth r3, r3 800b0e8: 029b lsls r3, r3, #10 800b0ea: b29b uxth r3, r3 800b0ec: 4313 orrs r3, r2 800b0ee: b29a uxth r2, r3 800b0f0: 6b7b ldr r3, [r7, #52] @ 0x34 800b0f2: 801a strh r2, [r3, #0] 800b0f4: e024 b.n 800b140 800b0f6: f507 7384 add.w r3, r7, #264 @ 0x108 800b0fa: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b0fe: 681b ldr r3, [r3, #0] 800b100: 785b ldrb r3, [r3, #1] 800b102: 2b01 cmp r3, #1 800b104: d11c bne.n 800b140 800b106: f507 7384 add.w r3, r7, #264 @ 0x108 800b10a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b10e: 681b ldr r3, [r3, #0] 800b110: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b114: b29b uxth r3, r3 800b116: 461a mov r2, r3 800b118: 6c3b ldr r3, [r7, #64] @ 0x40 800b11a: 4413 add r3, r2 800b11c: 643b str r3, [r7, #64] @ 0x40 800b11e: f507 7384 add.w r3, r7, #264 @ 0x108 800b122: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b126: 681b ldr r3, [r3, #0] 800b128: 781b ldrb r3, [r3, #0] 800b12a: 011a lsls r2, r3, #4 800b12c: 6c3b ldr r3, [r7, #64] @ 0x40 800b12e: 4413 add r3, r2 800b130: f203 430c addw r3, r3, #1036 @ 0x40c 800b134: 63fb str r3, [r7, #60] @ 0x3c 800b136: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b13a: b29a uxth r2, r3 800b13c: 6bfb ldr r3, [r7, #60] @ 0x3c 800b13e: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 800b140: f507 7384 add.w r3, r7, #264 @ 0x108 800b144: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b148: 681b ldr r3, [r3, #0] 800b14a: 895b ldrh r3, [r3, #10] 800b14c: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800b150: f507 7384 add.w r3, r7, #264 @ 0x108 800b154: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b158: 681b ldr r3, [r3, #0] 800b15a: 6959 ldr r1, [r3, #20] 800b15c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b160: b29b uxth r3, r3 800b162: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800b166: f507 7084 add.w r0, r7, #264 @ 0x108 800b16a: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800b16e: 6800 ldr r0, [r0, #0] 800b170: f001 f881 bl 800c276 800b174: e227 b.n 800b5c6 } } /* auto Switch to single buffer mode when transfer xfer_len_db; 800b176: f507 7384 add.w r3, r7, #264 @ 0x108 800b17a: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b17e: 681b ldr r3, [r3, #0] 800b180: 6a1b ldr r3, [r3, #32] 800b182: f8c7 3104 str.w r3, [r7, #260] @ 0x104 /* disable double buffer mode for Bulk endpoint */ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); 800b186: f507 7384 add.w r3, r7, #264 @ 0x108 800b18a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b18e: 681a ldr r2, [r3, #0] 800b190: f507 7384 add.w r3, r7, #264 @ 0x108 800b194: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b198: 681b ldr r3, [r3, #0] 800b19a: 781b ldrb r3, [r3, #0] 800b19c: 009b lsls r3, r3, #2 800b19e: 4413 add r3, r2 800b1a0: 881b ldrh r3, [r3, #0] 800b1a2: b29b uxth r3, r3 800b1a4: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 800b1a8: f023 0370 bic.w r3, r3, #112 @ 0x70 800b1ac: f8a7 3062 strh.w r3, [r7, #98] @ 0x62 800b1b0: f507 7384 add.w r3, r7, #264 @ 0x108 800b1b4: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b1b8: 681a ldr r2, [r3, #0] 800b1ba: f507 7384 add.w r3, r7, #264 @ 0x108 800b1be: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b1c2: 681b ldr r3, [r3, #0] 800b1c4: 781b ldrb r3, [r3, #0] 800b1c6: 009b lsls r3, r3, #2 800b1c8: 441a add r2, r3 800b1ca: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62 800b1ce: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800b1d2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800b1d6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800b1da: f043 0380 orr.w r3, r3, #128 @ 0x80 800b1de: b29b uxth r3, r3 800b1e0: 8013 strh r3, [r2, #0] /* Set Tx count with nbre of byte to be transmitted */ PCD_SET_EP_TX_CNT(USBx, ep->num, len); 800b1e2: f507 7384 add.w r3, r7, #264 @ 0x108 800b1e6: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b1ea: 681b ldr r3, [r3, #0] 800b1ec: 65fb str r3, [r7, #92] @ 0x5c 800b1ee: f507 7384 add.w r3, r7, #264 @ 0x108 800b1f2: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b1f6: 681b ldr r3, [r3, #0] 800b1f8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b1fc: b29b uxth r3, r3 800b1fe: 461a mov r2, r3 800b200: 6dfb ldr r3, [r7, #92] @ 0x5c 800b202: 4413 add r3, r2 800b204: 65fb str r3, [r7, #92] @ 0x5c 800b206: f507 7384 add.w r3, r7, #264 @ 0x108 800b20a: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b20e: 681b ldr r3, [r3, #0] 800b210: 781b ldrb r3, [r3, #0] 800b212: 011a lsls r2, r3, #4 800b214: 6dfb ldr r3, [r7, #92] @ 0x5c 800b216: 4413 add r3, r2 800b218: f203 4304 addw r3, r3, #1028 @ 0x404 800b21c: 65bb str r3, [r7, #88] @ 0x58 800b21e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b222: b29a uxth r2, r3 800b224: 6dbb ldr r3, [r7, #88] @ 0x58 800b226: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800b228: f507 7384 add.w r3, r7, #264 @ 0x108 800b22c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b230: 681b ldr r3, [r3, #0] 800b232: 891b ldrh r3, [r3, #8] 800b234: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800b238: f507 7384 add.w r3, r7, #264 @ 0x108 800b23c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b240: 681b ldr r3, [r3, #0] 800b242: 6959 ldr r1, [r3, #20] 800b244: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b248: b29b uxth r3, r3 800b24a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800b24e: f507 7084 add.w r0, r7, #264 @ 0x108 800b252: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800b256: 6800 ldr r0, [r0, #0] 800b258: f001 f80d bl 800c276 800b25c: e1b3 b.n 800b5c6 } } else /* manage isochronous double buffer IN mode */ { /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; 800b25e: f507 7384 add.w r3, r7, #264 @ 0x108 800b262: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b266: 681b ldr r3, [r3, #0] 800b268: 6a1a ldr r2, [r3, #32] 800b26a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b26e: 1ad2 subs r2, r2, r3 800b270: f507 7384 add.w r3, r7, #264 @ 0x108 800b274: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b278: 681b ldr r3, [r3, #0] 800b27a: 621a str r2, [r3, #32] /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) 800b27c: f507 7384 add.w r3, r7, #264 @ 0x108 800b280: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b284: 681a ldr r2, [r3, #0] 800b286: f507 7384 add.w r3, r7, #264 @ 0x108 800b28a: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b28e: 681b ldr r3, [r3, #0] 800b290: 781b ldrb r3, [r3, #0] 800b292: 009b lsls r3, r3, #2 800b294: 4413 add r3, r2 800b296: 881b ldrh r3, [r3, #0] 800b298: b29b uxth r3, r3 800b29a: f003 0340 and.w r3, r3, #64 @ 0x40 800b29e: 2b00 cmp r3, #0 800b2a0: f000 80c6 beq.w 800b430 { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 800b2a4: f507 7384 add.w r3, r7, #264 @ 0x108 800b2a8: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b2ac: 681b ldr r3, [r3, #0] 800b2ae: 673b str r3, [r7, #112] @ 0x70 800b2b0: f507 7384 add.w r3, r7, #264 @ 0x108 800b2b4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b2b8: 681b ldr r3, [r3, #0] 800b2ba: 785b ldrb r3, [r3, #1] 800b2bc: 2b00 cmp r3, #0 800b2be: d177 bne.n 800b3b0 800b2c0: f507 7384 add.w r3, r7, #264 @ 0x108 800b2c4: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b2c8: 681b ldr r3, [r3, #0] 800b2ca: 66bb str r3, [r7, #104] @ 0x68 800b2cc: f507 7384 add.w r3, r7, #264 @ 0x108 800b2d0: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b2d4: 681b ldr r3, [r3, #0] 800b2d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b2da: b29b uxth r3, r3 800b2dc: 461a mov r2, r3 800b2de: 6ebb ldr r3, [r7, #104] @ 0x68 800b2e0: 4413 add r3, r2 800b2e2: 66bb str r3, [r7, #104] @ 0x68 800b2e4: f507 7384 add.w r3, r7, #264 @ 0x108 800b2e8: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b2ec: 681b ldr r3, [r3, #0] 800b2ee: 781b ldrb r3, [r3, #0] 800b2f0: 011a lsls r2, r3, #4 800b2f2: 6ebb ldr r3, [r7, #104] @ 0x68 800b2f4: 4413 add r3, r2 800b2f6: f203 430c addw r3, r3, #1036 @ 0x40c 800b2fa: 667b str r3, [r7, #100] @ 0x64 800b2fc: 6e7b ldr r3, [r7, #100] @ 0x64 800b2fe: 881b ldrh r3, [r3, #0] 800b300: b29b uxth r3, r3 800b302: f3c3 0309 ubfx r3, r3, #0, #10 800b306: b29a uxth r2, r3 800b308: 6e7b ldr r3, [r7, #100] @ 0x64 800b30a: 801a strh r2, [r3, #0] 800b30c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b310: 2b3e cmp r3, #62 @ 0x3e 800b312: d921 bls.n 800b358 800b314: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b318: 095b lsrs r3, r3, #5 800b31a: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800b31e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b322: f003 031f and.w r3, r3, #31 800b326: 2b00 cmp r3, #0 800b328: d104 bne.n 800b334 800b32a: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0 800b32e: 3b01 subs r3, #1 800b330: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800b334: 6e7b ldr r3, [r7, #100] @ 0x64 800b336: 881b ldrh r3, [r3, #0] 800b338: b29a uxth r2, r3 800b33a: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0 800b33e: b29b uxth r3, r3 800b340: 029b lsls r3, r3, #10 800b342: b29b uxth r3, r3 800b344: 4313 orrs r3, r2 800b346: b29b uxth r3, r3 800b348: ea6f 4343 mvn.w r3, r3, lsl #17 800b34c: ea6f 4353 mvn.w r3, r3, lsr #17 800b350: b29a uxth r2, r3 800b352: 6e7b ldr r3, [r7, #100] @ 0x64 800b354: 801a strh r2, [r3, #0] 800b356: e050 b.n 800b3fa 800b358: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b35c: 2b00 cmp r3, #0 800b35e: d10a bne.n 800b376 800b360: 6e7b ldr r3, [r7, #100] @ 0x64 800b362: 881b ldrh r3, [r3, #0] 800b364: b29b uxth r3, r3 800b366: ea6f 4343 mvn.w r3, r3, lsl #17 800b36a: ea6f 4353 mvn.w r3, r3, lsr #17 800b36e: b29a uxth r2, r3 800b370: 6e7b ldr r3, [r7, #100] @ 0x64 800b372: 801a strh r2, [r3, #0] 800b374: e041 b.n 800b3fa 800b376: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b37a: 085b lsrs r3, r3, #1 800b37c: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800b380: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b384: f003 0301 and.w r3, r3, #1 800b388: 2b00 cmp r3, #0 800b38a: d004 beq.n 800b396 800b38c: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0 800b390: 3301 adds r3, #1 800b392: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800b396: 6e7b ldr r3, [r7, #100] @ 0x64 800b398: 881b ldrh r3, [r3, #0] 800b39a: b29a uxth r2, r3 800b39c: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0 800b3a0: b29b uxth r3, r3 800b3a2: 029b lsls r3, r3, #10 800b3a4: b29b uxth r3, r3 800b3a6: 4313 orrs r3, r2 800b3a8: b29a uxth r2, r3 800b3aa: 6e7b ldr r3, [r7, #100] @ 0x64 800b3ac: 801a strh r2, [r3, #0] 800b3ae: e024 b.n 800b3fa 800b3b0: f507 7384 add.w r3, r7, #264 @ 0x108 800b3b4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b3b8: 681b ldr r3, [r3, #0] 800b3ba: 785b ldrb r3, [r3, #1] 800b3bc: 2b01 cmp r3, #1 800b3be: d11c bne.n 800b3fa 800b3c0: f507 7384 add.w r3, r7, #264 @ 0x108 800b3c4: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b3c8: 681b ldr r3, [r3, #0] 800b3ca: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b3ce: b29b uxth r3, r3 800b3d0: 461a mov r2, r3 800b3d2: 6f3b ldr r3, [r7, #112] @ 0x70 800b3d4: 4413 add r3, r2 800b3d6: 673b str r3, [r7, #112] @ 0x70 800b3d8: f507 7384 add.w r3, r7, #264 @ 0x108 800b3dc: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b3e0: 681b ldr r3, [r3, #0] 800b3e2: 781b ldrb r3, [r3, #0] 800b3e4: 011a lsls r2, r3, #4 800b3e6: 6f3b ldr r3, [r7, #112] @ 0x70 800b3e8: 4413 add r3, r2 800b3ea: f203 430c addw r3, r3, #1036 @ 0x40c 800b3ee: 66fb str r3, [r7, #108] @ 0x6c 800b3f0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b3f4: b29a uxth r2, r3 800b3f6: 6efb ldr r3, [r7, #108] @ 0x6c 800b3f8: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 800b3fa: f507 7384 add.w r3, r7, #264 @ 0x108 800b3fe: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b402: 681b ldr r3, [r3, #0] 800b404: 895b ldrh r3, [r3, #10] 800b406: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800b40a: f507 7384 add.w r3, r7, #264 @ 0x108 800b40e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b412: 681b ldr r3, [r3, #0] 800b414: 6959 ldr r1, [r3, #20] 800b416: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b41a: b29b uxth r3, r3 800b41c: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800b420: f507 7084 add.w r0, r7, #264 @ 0x108 800b424: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800b428: 6800 ldr r0, [r0, #0] 800b42a: f000 ff24 bl 800c276 800b42e: e0ca b.n 800b5c6 } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 800b430: f507 7384 add.w r3, r7, #264 @ 0x108 800b434: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b438: 681b ldr r3, [r3, #0] 800b43a: 785b ldrb r3, [r3, #1] 800b43c: 2b00 cmp r3, #0 800b43e: d177 bne.n 800b530 800b440: f507 7384 add.w r3, r7, #264 @ 0x108 800b444: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b448: 681b ldr r3, [r3, #0] 800b44a: 67fb str r3, [r7, #124] @ 0x7c 800b44c: f507 7384 add.w r3, r7, #264 @ 0x108 800b450: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b454: 681b ldr r3, [r3, #0] 800b456: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b45a: b29b uxth r3, r3 800b45c: 461a mov r2, r3 800b45e: 6ffb ldr r3, [r7, #124] @ 0x7c 800b460: 4413 add r3, r2 800b462: 67fb str r3, [r7, #124] @ 0x7c 800b464: f507 7384 add.w r3, r7, #264 @ 0x108 800b468: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b46c: 681b ldr r3, [r3, #0] 800b46e: 781b ldrb r3, [r3, #0] 800b470: 011a lsls r2, r3, #4 800b472: 6ffb ldr r3, [r7, #124] @ 0x7c 800b474: 4413 add r3, r2 800b476: f203 4304 addw r3, r3, #1028 @ 0x404 800b47a: 67bb str r3, [r7, #120] @ 0x78 800b47c: 6fbb ldr r3, [r7, #120] @ 0x78 800b47e: 881b ldrh r3, [r3, #0] 800b480: b29b uxth r3, r3 800b482: f3c3 0309 ubfx r3, r3, #0, #10 800b486: b29a uxth r2, r3 800b488: 6fbb ldr r3, [r7, #120] @ 0x78 800b48a: 801a strh r2, [r3, #0] 800b48c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b490: 2b3e cmp r3, #62 @ 0x3e 800b492: d921 bls.n 800b4d8 800b494: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b498: 095b lsrs r3, r3, #5 800b49a: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800b49e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b4a2: f003 031f and.w r3, r3, #31 800b4a6: 2b00 cmp r3, #0 800b4a8: d104 bne.n 800b4b4 800b4aa: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800b4ae: 3b01 subs r3, #1 800b4b0: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800b4b4: 6fbb ldr r3, [r7, #120] @ 0x78 800b4b6: 881b ldrh r3, [r3, #0] 800b4b8: b29a uxth r2, r3 800b4ba: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800b4be: b29b uxth r3, r3 800b4c0: 029b lsls r3, r3, #10 800b4c2: b29b uxth r3, r3 800b4c4: 4313 orrs r3, r2 800b4c6: b29b uxth r3, r3 800b4c8: ea6f 4343 mvn.w r3, r3, lsl #17 800b4cc: ea6f 4353 mvn.w r3, r3, lsr #17 800b4d0: b29a uxth r2, r3 800b4d2: 6fbb ldr r3, [r7, #120] @ 0x78 800b4d4: 801a strh r2, [r3, #0] 800b4d6: e05c b.n 800b592 800b4d8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b4dc: 2b00 cmp r3, #0 800b4de: d10a bne.n 800b4f6 800b4e0: 6fbb ldr r3, [r7, #120] @ 0x78 800b4e2: 881b ldrh r3, [r3, #0] 800b4e4: b29b uxth r3, r3 800b4e6: ea6f 4343 mvn.w r3, r3, lsl #17 800b4ea: ea6f 4353 mvn.w r3, r3, lsr #17 800b4ee: b29a uxth r2, r3 800b4f0: 6fbb ldr r3, [r7, #120] @ 0x78 800b4f2: 801a strh r2, [r3, #0] 800b4f4: e04d b.n 800b592 800b4f6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b4fa: 085b lsrs r3, r3, #1 800b4fc: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800b500: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b504: f003 0301 and.w r3, r3, #1 800b508: 2b00 cmp r3, #0 800b50a: d004 beq.n 800b516 800b50c: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800b510: 3301 adds r3, #1 800b512: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800b516: 6fbb ldr r3, [r7, #120] @ 0x78 800b518: 881b ldrh r3, [r3, #0] 800b51a: b29a uxth r2, r3 800b51c: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 800b520: b29b uxth r3, r3 800b522: 029b lsls r3, r3, #10 800b524: b29b uxth r3, r3 800b526: 4313 orrs r3, r2 800b528: b29a uxth r2, r3 800b52a: 6fbb ldr r3, [r7, #120] @ 0x78 800b52c: 801a strh r2, [r3, #0] 800b52e: e030 b.n 800b592 800b530: f507 7384 add.w r3, r7, #264 @ 0x108 800b534: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b538: 681b ldr r3, [r3, #0] 800b53a: 785b ldrb r3, [r3, #1] 800b53c: 2b01 cmp r3, #1 800b53e: d128 bne.n 800b592 800b540: f507 7384 add.w r3, r7, #264 @ 0x108 800b544: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b548: 681b ldr r3, [r3, #0] 800b54a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800b54e: f507 7384 add.w r3, r7, #264 @ 0x108 800b552: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b556: 681b ldr r3, [r3, #0] 800b558: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b55c: b29b uxth r3, r3 800b55e: 461a mov r2, r3 800b560: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800b564: 4413 add r3, r2 800b566: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800b56a: f507 7384 add.w r3, r7, #264 @ 0x108 800b56e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b572: 681b ldr r3, [r3, #0] 800b574: 781b ldrb r3, [r3, #0] 800b576: 011a lsls r2, r3, #4 800b578: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800b57c: 4413 add r3, r2 800b57e: f203 4304 addw r3, r3, #1028 @ 0x404 800b582: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800b586: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b58a: b29a uxth r2, r3 800b58c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800b590: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800b592: f507 7384 add.w r3, r7, #264 @ 0x108 800b596: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b59a: 681b ldr r3, [r3, #0] 800b59c: 891b ldrh r3, [r3, #8] 800b59e: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800b5a2: f507 7384 add.w r3, r7, #264 @ 0x108 800b5a6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b5aa: 681b ldr r3, [r3, #0] 800b5ac: 6959 ldr r1, [r3, #20] 800b5ae: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b5b2: b29b uxth r3, r3 800b5b4: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800b5b8: f507 7084 add.w r0, r7, #264 @ 0x108 800b5bc: f5a0 7082 sub.w r0, r0, #260 @ 0x104 800b5c0: 6800 ldr r0, [r0, #0] 800b5c2: f000 fe58 bl 800c276 } } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); 800b5c6: f507 7384 add.w r3, r7, #264 @ 0x108 800b5ca: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b5ce: 681a ldr r2, [r3, #0] 800b5d0: f507 7384 add.w r3, r7, #264 @ 0x108 800b5d4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b5d8: 681b ldr r3, [r3, #0] 800b5da: 781b ldrb r3, [r3, #0] 800b5dc: 009b lsls r3, r3, #2 800b5de: 4413 add r3, r2 800b5e0: 881b ldrh r3, [r3, #0] 800b5e2: b29b uxth r3, r3 800b5e4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800b5e8: f023 0340 bic.w r3, r3, #64 @ 0x40 800b5ec: 817b strh r3, [r7, #10] 800b5ee: 897b ldrh r3, [r7, #10] 800b5f0: f083 0310 eor.w r3, r3, #16 800b5f4: 817b strh r3, [r7, #10] 800b5f6: 897b ldrh r3, [r7, #10] 800b5f8: f083 0320 eor.w r3, r3, #32 800b5fc: 817b strh r3, [r7, #10] 800b5fe: f507 7384 add.w r3, r7, #264 @ 0x108 800b602: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b606: 681a ldr r2, [r3, #0] 800b608: f507 7384 add.w r3, r7, #264 @ 0x108 800b60c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b610: 681b ldr r3, [r3, #0] 800b612: 781b ldrb r3, [r3, #0] 800b614: 009b lsls r3, r3, #2 800b616: 441a add r2, r3 800b618: 897b ldrh r3, [r7, #10] 800b61a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800b61e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800b622: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800b626: f043 0380 orr.w r3, r3, #128 @ 0x80 800b62a: b29b uxth r3, r3 800b62c: 8013 strh r3, [r2, #0] 800b62e: f000 bcde b.w 800bfee } else /* OUT endpoint */ { if (ep->doublebuffer == 0U) 800b632: f507 7384 add.w r3, r7, #264 @ 0x108 800b636: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b63a: 681b ldr r3, [r3, #0] 800b63c: 7b1b ldrb r3, [r3, #12] 800b63e: 2b00 cmp r3, #0 800b640: f040 80bb bne.w 800b7ba { /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) 800b644: f507 7384 add.w r3, r7, #264 @ 0x108 800b648: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b64c: 681b ldr r3, [r3, #0] 800b64e: 699a ldr r2, [r3, #24] 800b650: f507 7384 add.w r3, r7, #264 @ 0x108 800b654: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b658: 681b ldr r3, [r3, #0] 800b65a: 691b ldr r3, [r3, #16] 800b65c: 429a cmp r2, r3 800b65e: d917 bls.n 800b690 { len = ep->maxpacket; 800b660: f507 7384 add.w r3, r7, #264 @ 0x108 800b664: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b668: 681b ldr r3, [r3, #0] 800b66a: 691b ldr r3, [r3, #16] 800b66c: f8c7 3104 str.w r3, [r7, #260] @ 0x104 ep->xfer_len -= len; 800b670: f507 7384 add.w r3, r7, #264 @ 0x108 800b674: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b678: 681b ldr r3, [r3, #0] 800b67a: 699a ldr r2, [r3, #24] 800b67c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b680: 1ad2 subs r2, r2, r3 800b682: f507 7384 add.w r3, r7, #264 @ 0x108 800b686: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b68a: 681b ldr r3, [r3, #0] 800b68c: 619a str r2, [r3, #24] 800b68e: e00e b.n 800b6ae } else { len = ep->xfer_len; 800b690: f507 7384 add.w r3, r7, #264 @ 0x108 800b694: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b698: 681b ldr r3, [r3, #0] 800b69a: 699b ldr r3, [r3, #24] 800b69c: f8c7 3104 str.w r3, [r7, #260] @ 0x104 ep->xfer_len = 0U; 800b6a0: f507 7384 add.w r3, r7, #264 @ 0x108 800b6a4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b6a8: 681b ldr r3, [r3, #0] 800b6aa: 2200 movs r2, #0 800b6ac: 619a str r2, [r3, #24] } /* configure and validate Rx endpoint */ PCD_SET_EP_RX_CNT(USBx, ep->num, len); 800b6ae: f507 7384 add.w r3, r7, #264 @ 0x108 800b6b2: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b6b6: 681b ldr r3, [r3, #0] 800b6b8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800b6bc: f507 7384 add.w r3, r7, #264 @ 0x108 800b6c0: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b6c4: 681b ldr r3, [r3, #0] 800b6c6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b6ca: b29b uxth r3, r3 800b6cc: 461a mov r2, r3 800b6ce: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800b6d2: 4413 add r3, r2 800b6d4: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800b6d8: f507 7384 add.w r3, r7, #264 @ 0x108 800b6dc: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b6e0: 681b ldr r3, [r3, #0] 800b6e2: 781b ldrb r3, [r3, #0] 800b6e4: 011a lsls r2, r3, #4 800b6e6: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800b6ea: 4413 add r3, r2 800b6ec: f203 430c addw r3, r3, #1036 @ 0x40c 800b6f0: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800b6f4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b6f8: 881b ldrh r3, [r3, #0] 800b6fa: b29b uxth r3, r3 800b6fc: f3c3 0309 ubfx r3, r3, #0, #10 800b700: b29a uxth r2, r3 800b702: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b706: 801a strh r2, [r3, #0] 800b708: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b70c: 2b3e cmp r3, #62 @ 0x3e 800b70e: d924 bls.n 800b75a 800b710: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b714: 095b lsrs r3, r3, #5 800b716: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800b71a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b71e: f003 031f and.w r3, r3, #31 800b722: 2b00 cmp r3, #0 800b724: d104 bne.n 800b730 800b726: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 800b72a: 3b01 subs r3, #1 800b72c: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800b730: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b734: 881b ldrh r3, [r3, #0] 800b736: b29a uxth r2, r3 800b738: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 800b73c: b29b uxth r3, r3 800b73e: 029b lsls r3, r3, #10 800b740: b29b uxth r3, r3 800b742: 4313 orrs r3, r2 800b744: b29b uxth r3, r3 800b746: ea6f 4343 mvn.w r3, r3, lsl #17 800b74a: ea6f 4353 mvn.w r3, r3, lsr #17 800b74e: b29a uxth r2, r3 800b750: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b754: 801a strh r2, [r3, #0] 800b756: f000 bc10 b.w 800bf7a 800b75a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b75e: 2b00 cmp r3, #0 800b760: d10c bne.n 800b77c 800b762: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b766: 881b ldrh r3, [r3, #0] 800b768: b29b uxth r3, r3 800b76a: ea6f 4343 mvn.w r3, r3, lsl #17 800b76e: ea6f 4353 mvn.w r3, r3, lsr #17 800b772: b29a uxth r2, r3 800b774: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b778: 801a strh r2, [r3, #0] 800b77a: e3fe b.n 800bf7a 800b77c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b780: 085b lsrs r3, r3, #1 800b782: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800b786: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800b78a: f003 0301 and.w r3, r3, #1 800b78e: 2b00 cmp r3, #0 800b790: d004 beq.n 800b79c 800b792: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 800b796: 3301 adds r3, #1 800b798: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800b79c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b7a0: 881b ldrh r3, [r3, #0] 800b7a2: b29a uxth r2, r3 800b7a4: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 800b7a8: b29b uxth r3, r3 800b7aa: 029b lsls r3, r3, #10 800b7ac: b29b uxth r3, r3 800b7ae: 4313 orrs r3, r2 800b7b0: b29a uxth r2, r3 800b7b2: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800b7b6: 801a strh r2, [r3, #0] 800b7b8: e3df b.n 800bf7a #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) 800b7ba: f507 7384 add.w r3, r7, #264 @ 0x108 800b7be: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b7c2: 681b ldr r3, [r3, #0] 800b7c4: 78db ldrb r3, [r3, #3] 800b7c6: 2b02 cmp r3, #2 800b7c8: f040 8218 bne.w 800bbfc { PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); 800b7cc: f507 7384 add.w r3, r7, #264 @ 0x108 800b7d0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b7d4: 681b ldr r3, [r3, #0] 800b7d6: 785b ldrb r3, [r3, #1] 800b7d8: 2b00 cmp r3, #0 800b7da: f040 809d bne.w 800b918 800b7de: f507 7384 add.w r3, r7, #264 @ 0x108 800b7e2: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b7e6: 681b ldr r3, [r3, #0] 800b7e8: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800b7ec: f507 7384 add.w r3, r7, #264 @ 0x108 800b7f0: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b7f4: 681b ldr r3, [r3, #0] 800b7f6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b7fa: b29b uxth r3, r3 800b7fc: 461a mov r2, r3 800b7fe: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800b802: 4413 add r3, r2 800b804: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800b808: f507 7384 add.w r3, r7, #264 @ 0x108 800b80c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b810: 681b ldr r3, [r3, #0] 800b812: 781b ldrb r3, [r3, #0] 800b814: 011a lsls r2, r3, #4 800b816: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800b81a: 4413 add r3, r2 800b81c: f203 4304 addw r3, r3, #1028 @ 0x404 800b820: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800b824: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b828: 881b ldrh r3, [r3, #0] 800b82a: b29b uxth r3, r3 800b82c: f3c3 0309 ubfx r3, r3, #0, #10 800b830: b29a uxth r2, r3 800b832: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b836: 801a strh r2, [r3, #0] 800b838: f507 7384 add.w r3, r7, #264 @ 0x108 800b83c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b840: 681b ldr r3, [r3, #0] 800b842: 691b ldr r3, [r3, #16] 800b844: 2b3e cmp r3, #62 @ 0x3e 800b846: d92b bls.n 800b8a0 800b848: f507 7384 add.w r3, r7, #264 @ 0x108 800b84c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b850: 681b ldr r3, [r3, #0] 800b852: 691b ldr r3, [r3, #16] 800b854: 095b lsrs r3, r3, #5 800b856: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800b85a: f507 7384 add.w r3, r7, #264 @ 0x108 800b85e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b862: 681b ldr r3, [r3, #0] 800b864: 691b ldr r3, [r3, #16] 800b866: f003 031f and.w r3, r3, #31 800b86a: 2b00 cmp r3, #0 800b86c: d104 bne.n 800b878 800b86e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800b872: 3b01 subs r3, #1 800b874: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800b878: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b87c: 881b ldrh r3, [r3, #0] 800b87e: b29a uxth r2, r3 800b880: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800b884: b29b uxth r3, r3 800b886: 029b lsls r3, r3, #10 800b888: b29b uxth r3, r3 800b88a: 4313 orrs r3, r2 800b88c: b29b uxth r3, r3 800b88e: ea6f 4343 mvn.w r3, r3, lsl #17 800b892: ea6f 4353 mvn.w r3, r3, lsr #17 800b896: b29a uxth r2, r3 800b898: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b89c: 801a strh r2, [r3, #0] 800b89e: e070 b.n 800b982 800b8a0: f507 7384 add.w r3, r7, #264 @ 0x108 800b8a4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b8a8: 681b ldr r3, [r3, #0] 800b8aa: 691b ldr r3, [r3, #16] 800b8ac: 2b00 cmp r3, #0 800b8ae: d10c bne.n 800b8ca 800b8b0: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b8b4: 881b ldrh r3, [r3, #0] 800b8b6: b29b uxth r3, r3 800b8b8: ea6f 4343 mvn.w r3, r3, lsl #17 800b8bc: ea6f 4353 mvn.w r3, r3, lsr #17 800b8c0: b29a uxth r2, r3 800b8c2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b8c6: 801a strh r2, [r3, #0] 800b8c8: e05b b.n 800b982 800b8ca: f507 7384 add.w r3, r7, #264 @ 0x108 800b8ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b8d2: 681b ldr r3, [r3, #0] 800b8d4: 691b ldr r3, [r3, #16] 800b8d6: 085b lsrs r3, r3, #1 800b8d8: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800b8dc: f507 7384 add.w r3, r7, #264 @ 0x108 800b8e0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b8e4: 681b ldr r3, [r3, #0] 800b8e6: 691b ldr r3, [r3, #16] 800b8e8: f003 0301 and.w r3, r3, #1 800b8ec: 2b00 cmp r3, #0 800b8ee: d004 beq.n 800b8fa 800b8f0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800b8f4: 3301 adds r3, #1 800b8f6: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800b8fa: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b8fe: 881b ldrh r3, [r3, #0] 800b900: b29a uxth r2, r3 800b902: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800b906: b29b uxth r3, r3 800b908: 029b lsls r3, r3, #10 800b90a: b29b uxth r3, r3 800b90c: 4313 orrs r3, r2 800b90e: b29a uxth r2, r3 800b910: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800b914: 801a strh r2, [r3, #0] 800b916: e034 b.n 800b982 800b918: f507 7384 add.w r3, r7, #264 @ 0x108 800b91c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b920: 681b ldr r3, [r3, #0] 800b922: 785b ldrb r3, [r3, #1] 800b924: 2b01 cmp r3, #1 800b926: d12c bne.n 800b982 800b928: f507 7384 add.w r3, r7, #264 @ 0x108 800b92c: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b930: 681b ldr r3, [r3, #0] 800b932: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800b936: f507 7384 add.w r3, r7, #264 @ 0x108 800b93a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b93e: 681b ldr r3, [r3, #0] 800b940: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b944: b29b uxth r3, r3 800b946: 461a mov r2, r3 800b948: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800b94c: 4413 add r3, r2 800b94e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800b952: f507 7384 add.w r3, r7, #264 @ 0x108 800b956: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b95a: 681b ldr r3, [r3, #0] 800b95c: 781b ldrb r3, [r3, #0] 800b95e: 011a lsls r2, r3, #4 800b960: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800b964: 4413 add r3, r2 800b966: f203 4304 addw r3, r3, #1028 @ 0x404 800b96a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800b96e: f507 7384 add.w r3, r7, #264 @ 0x108 800b972: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b976: 681b ldr r3, [r3, #0] 800b978: 691b ldr r3, [r3, #16] 800b97a: b29a uxth r2, r3 800b97c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 800b980: 801a strh r2, [r3, #0] 800b982: f507 7384 add.w r3, r7, #264 @ 0x108 800b986: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b98a: 681b ldr r3, [r3, #0] 800b98c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800b990: f507 7384 add.w r3, r7, #264 @ 0x108 800b994: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b998: 681b ldr r3, [r3, #0] 800b99a: 785b ldrb r3, [r3, #1] 800b99c: 2b00 cmp r3, #0 800b99e: f040 809d bne.w 800badc 800b9a2: f507 7384 add.w r3, r7, #264 @ 0x108 800b9a6: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b9aa: 681b ldr r3, [r3, #0] 800b9ac: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800b9b0: f507 7384 add.w r3, r7, #264 @ 0x108 800b9b4: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800b9b8: 681b ldr r3, [r3, #0] 800b9ba: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800b9be: b29b uxth r3, r3 800b9c0: 461a mov r2, r3 800b9c2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800b9c6: 4413 add r3, r2 800b9c8: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800b9cc: f507 7384 add.w r3, r7, #264 @ 0x108 800b9d0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800b9d4: 681b ldr r3, [r3, #0] 800b9d6: 781b ldrb r3, [r3, #0] 800b9d8: 011a lsls r2, r3, #4 800b9da: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800b9de: 4413 add r3, r2 800b9e0: f203 430c addw r3, r3, #1036 @ 0x40c 800b9e4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800b9e8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800b9ec: 881b ldrh r3, [r3, #0] 800b9ee: b29b uxth r3, r3 800b9f0: f3c3 0309 ubfx r3, r3, #0, #10 800b9f4: b29a uxth r2, r3 800b9f6: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800b9fa: 801a strh r2, [r3, #0] 800b9fc: f507 7384 add.w r3, r7, #264 @ 0x108 800ba00: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ba04: 681b ldr r3, [r3, #0] 800ba06: 691b ldr r3, [r3, #16] 800ba08: 2b3e cmp r3, #62 @ 0x3e 800ba0a: d92b bls.n 800ba64 800ba0c: f507 7384 add.w r3, r7, #264 @ 0x108 800ba10: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ba14: 681b ldr r3, [r3, #0] 800ba16: 691b ldr r3, [r3, #16] 800ba18: 095b lsrs r3, r3, #5 800ba1a: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800ba1e: f507 7384 add.w r3, r7, #264 @ 0x108 800ba22: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ba26: 681b ldr r3, [r3, #0] 800ba28: 691b ldr r3, [r3, #16] 800ba2a: f003 031f and.w r3, r3, #31 800ba2e: 2b00 cmp r3, #0 800ba30: d104 bne.n 800ba3c 800ba32: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800ba36: 3b01 subs r3, #1 800ba38: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800ba3c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800ba40: 881b ldrh r3, [r3, #0] 800ba42: b29a uxth r2, r3 800ba44: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800ba48: b29b uxth r3, r3 800ba4a: 029b lsls r3, r3, #10 800ba4c: b29b uxth r3, r3 800ba4e: 4313 orrs r3, r2 800ba50: b29b uxth r3, r3 800ba52: ea6f 4343 mvn.w r3, r3, lsl #17 800ba56: ea6f 4353 mvn.w r3, r3, lsr #17 800ba5a: b29a uxth r2, r3 800ba5c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800ba60: 801a strh r2, [r3, #0] 800ba62: e069 b.n 800bb38 800ba64: f507 7384 add.w r3, r7, #264 @ 0x108 800ba68: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ba6c: 681b ldr r3, [r3, #0] 800ba6e: 691b ldr r3, [r3, #16] 800ba70: 2b00 cmp r3, #0 800ba72: d10c bne.n 800ba8e 800ba74: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800ba78: 881b ldrh r3, [r3, #0] 800ba7a: b29b uxth r3, r3 800ba7c: ea6f 4343 mvn.w r3, r3, lsl #17 800ba80: ea6f 4353 mvn.w r3, r3, lsr #17 800ba84: b29a uxth r2, r3 800ba86: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800ba8a: 801a strh r2, [r3, #0] 800ba8c: e054 b.n 800bb38 800ba8e: f507 7384 add.w r3, r7, #264 @ 0x108 800ba92: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800ba96: 681b ldr r3, [r3, #0] 800ba98: 691b ldr r3, [r3, #16] 800ba9a: 085b lsrs r3, r3, #1 800ba9c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800baa0: f507 7384 add.w r3, r7, #264 @ 0x108 800baa4: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800baa8: 681b ldr r3, [r3, #0] 800baaa: 691b ldr r3, [r3, #16] 800baac: f003 0301 and.w r3, r3, #1 800bab0: 2b00 cmp r3, #0 800bab2: d004 beq.n 800babe 800bab4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800bab8: 3301 adds r3, #1 800baba: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800babe: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800bac2: 881b ldrh r3, [r3, #0] 800bac4: b29a uxth r2, r3 800bac6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800baca: b29b uxth r3, r3 800bacc: 029b lsls r3, r3, #10 800bace: b29b uxth r3, r3 800bad0: 4313 orrs r3, r2 800bad2: b29a uxth r2, r3 800bad4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800bad8: 801a strh r2, [r3, #0] 800bada: e02d b.n 800bb38 800badc: f507 7384 add.w r3, r7, #264 @ 0x108 800bae0: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bae4: 681b ldr r3, [r3, #0] 800bae6: 785b ldrb r3, [r3, #1] 800bae8: 2b01 cmp r3, #1 800baea: d125 bne.n 800bb38 800baec: f507 7384 add.w r3, r7, #264 @ 0x108 800baf0: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800baf4: 681b ldr r3, [r3, #0] 800baf6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800bafa: b29b uxth r3, r3 800bafc: 461a mov r2, r3 800bafe: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800bb02: 4413 add r3, r2 800bb04: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800bb08: f507 7384 add.w r3, r7, #264 @ 0x108 800bb0c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bb10: 681b ldr r3, [r3, #0] 800bb12: 781b ldrb r3, [r3, #0] 800bb14: 011a lsls r2, r3, #4 800bb16: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800bb1a: 4413 add r3, r2 800bb1c: f203 430c addw r3, r3, #1036 @ 0x40c 800bb20: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800bb24: f507 7384 add.w r3, r7, #264 @ 0x108 800bb28: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bb2c: 681b ldr r3, [r3, #0] 800bb2e: 691b ldr r3, [r3, #16] 800bb30: b29a uxth r2, r3 800bb32: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800bb36: 801a strh r2, [r3, #0] /* Coming from ISR */ if (ep->xfer_count != 0U) 800bb38: f507 7384 add.w r3, r7, #264 @ 0x108 800bb3c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bb40: 681b ldr r3, [r3, #0] 800bb42: 69db ldr r3, [r3, #28] 800bb44: 2b00 cmp r3, #0 800bb46: f000 8218 beq.w 800bf7a { /* update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); 800bb4a: f507 7384 add.w r3, r7, #264 @ 0x108 800bb4e: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bb52: 681a ldr r2, [r3, #0] 800bb54: f507 7384 add.w r3, r7, #264 @ 0x108 800bb58: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bb5c: 681b ldr r3, [r3, #0] 800bb5e: 781b ldrb r3, [r3, #0] 800bb60: 009b lsls r3, r3, #2 800bb62: 4413 add r3, r2 800bb64: 881b ldrh r3, [r3, #0] 800bb66: f8a7 3096 strh.w r3, [r7, #150] @ 0x96 /*Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || 800bb6a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800bb6e: f403 4380 and.w r3, r3, #16384 @ 0x4000 800bb72: 2b00 cmp r3, #0 800bb74: d005 beq.n 800bb82 800bb76: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800bb7a: f003 0340 and.w r3, r3, #64 @ 0x40 800bb7e: 2b00 cmp r3, #0 800bb80: d10d bne.n 800bb9e (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) 800bb82: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800bb86: f403 4380 and.w r3, r3, #16384 @ 0x4000 if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || 800bb8a: 2b00 cmp r3, #0 800bb8c: f040 81f5 bne.w 800bf7a (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) 800bb90: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800bb94: f003 0340 and.w r3, r3, #64 @ 0x40 800bb98: 2b00 cmp r3, #0 800bb9a: f040 81ee bne.w 800bf7a { PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); 800bb9e: f507 7384 add.w r3, r7, #264 @ 0x108 800bba2: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bba6: 681a ldr r2, [r3, #0] 800bba8: f507 7384 add.w r3, r7, #264 @ 0x108 800bbac: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bbb0: 681b ldr r3, [r3, #0] 800bbb2: 781b ldrb r3, [r3, #0] 800bbb4: 009b lsls r3, r3, #2 800bbb6: 4413 add r3, r2 800bbb8: 881b ldrh r3, [r3, #0] 800bbba: b29b uxth r3, r3 800bbbc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800bbc0: f023 0370 bic.w r3, r3, #112 @ 0x70 800bbc4: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 800bbc8: f507 7384 add.w r3, r7, #264 @ 0x108 800bbcc: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bbd0: 681a ldr r2, [r3, #0] 800bbd2: f507 7384 add.w r3, r7, #264 @ 0x108 800bbd6: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bbda: 681b ldr r3, [r3, #0] 800bbdc: 781b ldrb r3, [r3, #0] 800bbde: 009b lsls r3, r3, #2 800bbe0: 441a add r2, r3 800bbe2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800bbe6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800bbea: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800bbee: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800bbf2: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800bbf6: b29b uxth r3, r3 800bbf8: 8013 strh r3, [r2, #0] 800bbfa: e1be b.n 800bf7a } } } /* iso out double */ else if (ep->type == EP_TYPE_ISOC) 800bbfc: f507 7384 add.w r3, r7, #264 @ 0x108 800bc00: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc04: 681b ldr r3, [r3, #0] 800bc06: 78db ldrb r3, [r3, #3] 800bc08: 2b01 cmp r3, #1 800bc0a: f040 81b4 bne.w 800bf76 { /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) 800bc0e: f507 7384 add.w r3, r7, #264 @ 0x108 800bc12: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc16: 681b ldr r3, [r3, #0] 800bc18: 699a ldr r2, [r3, #24] 800bc1a: f507 7384 add.w r3, r7, #264 @ 0x108 800bc1e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc22: 681b ldr r3, [r3, #0] 800bc24: 691b ldr r3, [r3, #16] 800bc26: 429a cmp r2, r3 800bc28: d917 bls.n 800bc5a { len = ep->maxpacket; 800bc2a: f507 7384 add.w r3, r7, #264 @ 0x108 800bc2e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc32: 681b ldr r3, [r3, #0] 800bc34: 691b ldr r3, [r3, #16] 800bc36: f8c7 3104 str.w r3, [r7, #260] @ 0x104 ep->xfer_len -= len; 800bc3a: f507 7384 add.w r3, r7, #264 @ 0x108 800bc3e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc42: 681b ldr r3, [r3, #0] 800bc44: 699a ldr r2, [r3, #24] 800bc46: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bc4a: 1ad2 subs r2, r2, r3 800bc4c: f507 7384 add.w r3, r7, #264 @ 0x108 800bc50: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc54: 681b ldr r3, [r3, #0] 800bc56: 619a str r2, [r3, #24] 800bc58: e00e b.n 800bc78 } else { len = ep->xfer_len; 800bc5a: f507 7384 add.w r3, r7, #264 @ 0x108 800bc5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc62: 681b ldr r3, [r3, #0] 800bc64: 699b ldr r3, [r3, #24] 800bc66: f8c7 3104 str.w r3, [r7, #260] @ 0x104 ep->xfer_len = 0U; 800bc6a: f507 7384 add.w r3, r7, #264 @ 0x108 800bc6e: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc72: 681b ldr r3, [r3, #0] 800bc74: 2200 movs r2, #0 800bc76: 619a str r2, [r3, #24] } PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); 800bc78: f507 7384 add.w r3, r7, #264 @ 0x108 800bc7c: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bc80: 681b ldr r3, [r3, #0] 800bc82: 785b ldrb r3, [r3, #1] 800bc84: 2b00 cmp r3, #0 800bc86: f040 8085 bne.w 800bd94 800bc8a: f507 7384 add.w r3, r7, #264 @ 0x108 800bc8e: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bc92: 681b ldr r3, [r3, #0] 800bc94: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800bc98: f507 7384 add.w r3, r7, #264 @ 0x108 800bc9c: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bca0: 681b ldr r3, [r3, #0] 800bca2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800bca6: b29b uxth r3, r3 800bca8: 461a mov r2, r3 800bcaa: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 800bcae: 4413 add r3, r2 800bcb0: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800bcb4: f507 7384 add.w r3, r7, #264 @ 0x108 800bcb8: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bcbc: 681b ldr r3, [r3, #0] 800bcbe: 781b ldrb r3, [r3, #0] 800bcc0: 011a lsls r2, r3, #4 800bcc2: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 800bcc6: 4413 add r3, r2 800bcc8: f203 4304 addw r3, r3, #1028 @ 0x404 800bccc: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800bcd0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bcd4: 881b ldrh r3, [r3, #0] 800bcd6: b29b uxth r3, r3 800bcd8: f3c3 0309 ubfx r3, r3, #0, #10 800bcdc: b29a uxth r2, r3 800bcde: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bce2: 801a strh r2, [r3, #0] 800bce4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bce8: 2b3e cmp r3, #62 @ 0x3e 800bcea: d923 bls.n 800bd34 800bcec: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bcf0: 095b lsrs r3, r3, #5 800bcf2: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800bcf6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bcfa: f003 031f and.w r3, r3, #31 800bcfe: 2b00 cmp r3, #0 800bd00: d104 bne.n 800bd0c 800bd02: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800bd06: 3b01 subs r3, #1 800bd08: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800bd0c: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bd10: 881b ldrh r3, [r3, #0] 800bd12: b29a uxth r2, r3 800bd14: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800bd18: b29b uxth r3, r3 800bd1a: 029b lsls r3, r3, #10 800bd1c: b29b uxth r3, r3 800bd1e: 4313 orrs r3, r2 800bd20: b29b uxth r3, r3 800bd22: ea6f 4343 mvn.w r3, r3, lsl #17 800bd26: ea6f 4353 mvn.w r3, r3, lsr #17 800bd2a: b29a uxth r2, r3 800bd2c: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bd30: 801a strh r2, [r3, #0] 800bd32: e060 b.n 800bdf6 800bd34: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bd38: 2b00 cmp r3, #0 800bd3a: d10c bne.n 800bd56 800bd3c: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bd40: 881b ldrh r3, [r3, #0] 800bd42: b29b uxth r3, r3 800bd44: ea6f 4343 mvn.w r3, r3, lsl #17 800bd48: ea6f 4353 mvn.w r3, r3, lsr #17 800bd4c: b29a uxth r2, r3 800bd4e: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bd52: 801a strh r2, [r3, #0] 800bd54: e04f b.n 800bdf6 800bd56: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bd5a: 085b lsrs r3, r3, #1 800bd5c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800bd60: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bd64: f003 0301 and.w r3, r3, #1 800bd68: 2b00 cmp r3, #0 800bd6a: d004 beq.n 800bd76 800bd6c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800bd70: 3301 adds r3, #1 800bd72: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800bd76: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bd7a: 881b ldrh r3, [r3, #0] 800bd7c: b29a uxth r2, r3 800bd7e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800bd82: b29b uxth r3, r3 800bd84: 029b lsls r3, r3, #10 800bd86: b29b uxth r3, r3 800bd88: 4313 orrs r3, r2 800bd8a: b29a uxth r2, r3 800bd8c: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 800bd90: 801a strh r2, [r3, #0] 800bd92: e030 b.n 800bdf6 800bd94: f507 7384 add.w r3, r7, #264 @ 0x108 800bd98: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bd9c: 681b ldr r3, [r3, #0] 800bd9e: 785b ldrb r3, [r3, #1] 800bda0: 2b01 cmp r3, #1 800bda2: d128 bne.n 800bdf6 800bda4: f507 7384 add.w r3, r7, #264 @ 0x108 800bda8: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bdac: 681b ldr r3, [r3, #0] 800bdae: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800bdb2: f507 7384 add.w r3, r7, #264 @ 0x108 800bdb6: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bdba: 681b ldr r3, [r3, #0] 800bdbc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800bdc0: b29b uxth r3, r3 800bdc2: 461a mov r2, r3 800bdc4: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 800bdc8: 4413 add r3, r2 800bdca: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800bdce: f507 7384 add.w r3, r7, #264 @ 0x108 800bdd2: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bdd6: 681b ldr r3, [r3, #0] 800bdd8: 781b ldrb r3, [r3, #0] 800bdda: 011a lsls r2, r3, #4 800bddc: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 800bde0: 4413 add r3, r2 800bde2: f203 4304 addw r3, r3, #1028 @ 0x404 800bde6: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800bdea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bdee: b29a uxth r2, r3 800bdf0: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 800bdf4: 801a strh r2, [r3, #0] 800bdf6: f507 7384 add.w r3, r7, #264 @ 0x108 800bdfa: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bdfe: 681b ldr r3, [r3, #0] 800be00: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800be04: f507 7384 add.w r3, r7, #264 @ 0x108 800be08: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800be0c: 681b ldr r3, [r3, #0] 800be0e: 785b ldrb r3, [r3, #1] 800be10: 2b00 cmp r3, #0 800be12: f040 8085 bne.w 800bf20 800be16: f507 7384 add.w r3, r7, #264 @ 0x108 800be1a: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800be1e: 681b ldr r3, [r3, #0] 800be20: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800be24: f507 7384 add.w r3, r7, #264 @ 0x108 800be28: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800be2c: 681b ldr r3, [r3, #0] 800be2e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800be32: b29b uxth r3, r3 800be34: 461a mov r2, r3 800be36: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc 800be3a: 4413 add r3, r2 800be3c: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800be40: f507 7384 add.w r3, r7, #264 @ 0x108 800be44: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800be48: 681b ldr r3, [r3, #0] 800be4a: 781b ldrb r3, [r3, #0] 800be4c: 011a lsls r2, r3, #4 800be4e: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc 800be52: 4413 add r3, r2 800be54: f203 430c addw r3, r3, #1036 @ 0x40c 800be58: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800be5c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800be60: 881b ldrh r3, [r3, #0] 800be62: b29b uxth r3, r3 800be64: f3c3 0309 ubfx r3, r3, #0, #10 800be68: b29a uxth r2, r3 800be6a: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800be6e: 801a strh r2, [r3, #0] 800be70: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800be74: 2b3e cmp r3, #62 @ 0x3e 800be76: d923 bls.n 800bec0 800be78: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800be7c: 095b lsrs r3, r3, #5 800be7e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800be82: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800be86: f003 031f and.w r3, r3, #31 800be8a: 2b00 cmp r3, #0 800be8c: d104 bne.n 800be98 800be8e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 800be92: 3b01 subs r3, #1 800be94: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800be98: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800be9c: 881b ldrh r3, [r3, #0] 800be9e: b29a uxth r2, r3 800bea0: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 800bea4: b29b uxth r3, r3 800bea6: 029b lsls r3, r3, #10 800bea8: b29b uxth r3, r3 800beaa: 4313 orrs r3, r2 800beac: b29b uxth r3, r3 800beae: ea6f 4343 mvn.w r3, r3, lsl #17 800beb2: ea6f 4353 mvn.w r3, r3, lsr #17 800beb6: b29a uxth r2, r3 800beb8: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800bebc: 801a strh r2, [r3, #0] 800bebe: e05c b.n 800bf7a 800bec0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bec4: 2b00 cmp r3, #0 800bec6: d10c bne.n 800bee2 800bec8: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800becc: 881b ldrh r3, [r3, #0] 800bece: b29b uxth r3, r3 800bed0: ea6f 4343 mvn.w r3, r3, lsl #17 800bed4: ea6f 4353 mvn.w r3, r3, lsr #17 800bed8: b29a uxth r2, r3 800beda: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800bede: 801a strh r2, [r3, #0] 800bee0: e04b b.n 800bf7a 800bee2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bee6: 085b lsrs r3, r3, #1 800bee8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800beec: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bef0: f003 0301 and.w r3, r3, #1 800bef4: 2b00 cmp r3, #0 800bef6: d004 beq.n 800bf02 800bef8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 800befc: 3301 adds r3, #1 800befe: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800bf02: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800bf06: 881b ldrh r3, [r3, #0] 800bf08: b29a uxth r2, r3 800bf0a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 800bf0e: b29b uxth r3, r3 800bf10: 029b lsls r3, r3, #10 800bf12: b29b uxth r3, r3 800bf14: 4313 orrs r3, r2 800bf16: b29a uxth r2, r3 800bf18: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800bf1c: 801a strh r2, [r3, #0] 800bf1e: e02c b.n 800bf7a 800bf20: f507 7384 add.w r3, r7, #264 @ 0x108 800bf24: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bf28: 681b ldr r3, [r3, #0] 800bf2a: 785b ldrb r3, [r3, #1] 800bf2c: 2b01 cmp r3, #1 800bf2e: d124 bne.n 800bf7a 800bf30: f507 7384 add.w r3, r7, #264 @ 0x108 800bf34: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bf38: 681b ldr r3, [r3, #0] 800bf3a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800bf3e: b29b uxth r3, r3 800bf40: 461a mov r2, r3 800bf42: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800bf46: 4413 add r3, r2 800bf48: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800bf4c: f507 7384 add.w r3, r7, #264 @ 0x108 800bf50: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bf54: 681b ldr r3, [r3, #0] 800bf56: 781b ldrb r3, [r3, #0] 800bf58: 011a lsls r2, r3, #4 800bf5a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 800bf5e: 4413 add r3, r2 800bf60: f203 430c addw r3, r3, #1036 @ 0x40c 800bf64: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800bf68: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104 800bf6c: b29a uxth r2, r3 800bf6e: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 800bf72: 801a strh r2, [r3, #0] 800bf74: e001 b.n 800bf7a } else { return HAL_ERROR; 800bf76: 2301 movs r3, #1 800bf78: e03a b.n 800bff0 } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800bf7a: f507 7384 add.w r3, r7, #264 @ 0x108 800bf7e: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bf82: 681a ldr r2, [r3, #0] 800bf84: f507 7384 add.w r3, r7, #264 @ 0x108 800bf88: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bf8c: 681b ldr r3, [r3, #0] 800bf8e: 781b ldrb r3, [r3, #0] 800bf90: 009b lsls r3, r3, #2 800bf92: 4413 add r3, r2 800bf94: 881b ldrh r3, [r3, #0] 800bf96: b29b uxth r3, r3 800bf98: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800bf9c: f023 0370 bic.w r3, r3, #112 @ 0x70 800bfa0: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 800bfa4: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 800bfa8: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800bfac: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 800bfb0: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 800bfb4: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800bfb8: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 800bfbc: f507 7384 add.w r3, r7, #264 @ 0x108 800bfc0: f5a3 7382 sub.w r3, r3, #260 @ 0x104 800bfc4: 681a ldr r2, [r3, #0] 800bfc6: f507 7384 add.w r3, r7, #264 @ 0x108 800bfca: f5a3 7384 sub.w r3, r3, #264 @ 0x108 800bfce: 681b ldr r3, [r3, #0] 800bfd0: 781b ldrb r3, [r3, #0] 800bfd2: 009b lsls r3, r3, #2 800bfd4: 441a add r2, r3 800bfd6: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 800bfda: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800bfde: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800bfe2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800bfe6: f043 0380 orr.w r3, r3, #128 @ 0x80 800bfea: b29b uxth r3, r3 800bfec: 8013 strh r3, [r2, #0] } return HAL_OK; 800bfee: 2300 movs r3, #0 } 800bff0: 4618 mov r0, r3 800bff2: f507 7784 add.w r7, r7, #264 @ 0x108 800bff6: 46bd mov sp, r7 800bff8: bd80 pop {r7, pc} 0800bffa : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800bffa: b480 push {r7} 800bffc: b085 sub sp, #20 800bffe: af00 add r7, sp, #0 800c000: 6078 str r0, [r7, #4] 800c002: 6039 str r1, [r7, #0] if (ep->is_in != 0U) 800c004: 683b ldr r3, [r7, #0] 800c006: 785b ldrb r3, [r3, #1] 800c008: 2b00 cmp r3, #0 800c00a: d020 beq.n 800c04e { PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); 800c00c: 687a ldr r2, [r7, #4] 800c00e: 683b ldr r3, [r7, #0] 800c010: 781b ldrb r3, [r3, #0] 800c012: 009b lsls r3, r3, #2 800c014: 4413 add r3, r2 800c016: 881b ldrh r3, [r3, #0] 800c018: b29b uxth r3, r3 800c01a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800c01e: f023 0340 bic.w r3, r3, #64 @ 0x40 800c022: 81bb strh r3, [r7, #12] 800c024: 89bb ldrh r3, [r7, #12] 800c026: f083 0310 eor.w r3, r3, #16 800c02a: 81bb strh r3, [r7, #12] 800c02c: 687a ldr r2, [r7, #4] 800c02e: 683b ldr r3, [r7, #0] 800c030: 781b ldrb r3, [r3, #0] 800c032: 009b lsls r3, r3, #2 800c034: 441a add r2, r3 800c036: 89bb ldrh r3, [r7, #12] 800c038: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c03c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c040: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800c044: f043 0380 orr.w r3, r3, #128 @ 0x80 800c048: b29b uxth r3, r3 800c04a: 8013 strh r3, [r2, #0] 800c04c: e01f b.n 800c08e } else { PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); 800c04e: 687a ldr r2, [r7, #4] 800c050: 683b ldr r3, [r7, #0] 800c052: 781b ldrb r3, [r3, #0] 800c054: 009b lsls r3, r3, #2 800c056: 4413 add r3, r2 800c058: 881b ldrh r3, [r3, #0] 800c05a: b29b uxth r3, r3 800c05c: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800c060: f023 0370 bic.w r3, r3, #112 @ 0x70 800c064: 81fb strh r3, [r7, #14] 800c066: 89fb ldrh r3, [r7, #14] 800c068: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800c06c: 81fb strh r3, [r7, #14] 800c06e: 687a ldr r2, [r7, #4] 800c070: 683b ldr r3, [r7, #0] 800c072: 781b ldrb r3, [r3, #0] 800c074: 009b lsls r3, r3, #2 800c076: 441a add r2, r3 800c078: 89fb ldrh r3, [r7, #14] 800c07a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c07e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c082: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800c086: f043 0380 orr.w r3, r3, #128 @ 0x80 800c08a: b29b uxth r3, r3 800c08c: 8013 strh r3, [r2, #0] } return HAL_OK; 800c08e: 2300 movs r3, #0 } 800c090: 4618 mov r0, r3 800c092: 3714 adds r7, #20 800c094: 46bd mov sp, r7 800c096: bc80 pop {r7} 800c098: 4770 bx lr 0800c09a : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800c09a: b480 push {r7} 800c09c: b087 sub sp, #28 800c09e: af00 add r7, sp, #0 800c0a0: 6078 str r0, [r7, #4] 800c0a2: 6039 str r1, [r7, #0] if (ep->doublebuffer == 0U) 800c0a4: 683b ldr r3, [r7, #0] 800c0a6: 7b1b ldrb r3, [r3, #12] 800c0a8: 2b00 cmp r3, #0 800c0aa: f040 809d bne.w 800c1e8 { if (ep->is_in != 0U) 800c0ae: 683b ldr r3, [r7, #0] 800c0b0: 785b ldrb r3, [r3, #1] 800c0b2: 2b00 cmp r3, #0 800c0b4: d04c beq.n 800c150 { PCD_CLEAR_TX_DTOG(USBx, ep->num); 800c0b6: 687a ldr r2, [r7, #4] 800c0b8: 683b ldr r3, [r7, #0] 800c0ba: 781b ldrb r3, [r3, #0] 800c0bc: 009b lsls r3, r3, #2 800c0be: 4413 add r3, r2 800c0c0: 881b ldrh r3, [r3, #0] 800c0c2: 823b strh r3, [r7, #16] 800c0c4: 8a3b ldrh r3, [r7, #16] 800c0c6: f003 0340 and.w r3, r3, #64 @ 0x40 800c0ca: 2b00 cmp r3, #0 800c0cc: d01b beq.n 800c106 800c0ce: 687a ldr r2, [r7, #4] 800c0d0: 683b ldr r3, [r7, #0] 800c0d2: 781b ldrb r3, [r3, #0] 800c0d4: 009b lsls r3, r3, #2 800c0d6: 4413 add r3, r2 800c0d8: 881b ldrh r3, [r3, #0] 800c0da: b29b uxth r3, r3 800c0dc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800c0e0: f023 0370 bic.w r3, r3, #112 @ 0x70 800c0e4: 81fb strh r3, [r7, #14] 800c0e6: 687a ldr r2, [r7, #4] 800c0e8: 683b ldr r3, [r7, #0] 800c0ea: 781b ldrb r3, [r3, #0] 800c0ec: 009b lsls r3, r3, #2 800c0ee: 441a add r2, r3 800c0f0: 89fb ldrh r3, [r7, #14] 800c0f2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c0f6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c0fa: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800c0fe: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800c102: b29b uxth r3, r3 800c104: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800c106: 683b ldr r3, [r7, #0] 800c108: 78db ldrb r3, [r3, #3] 800c10a: 2b01 cmp r3, #1 800c10c: d06c beq.n 800c1e8 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 800c10e: 687a ldr r2, [r7, #4] 800c110: 683b ldr r3, [r7, #0] 800c112: 781b ldrb r3, [r3, #0] 800c114: 009b lsls r3, r3, #2 800c116: 4413 add r3, r2 800c118: 881b ldrh r3, [r3, #0] 800c11a: b29b uxth r3, r3 800c11c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800c120: f023 0340 bic.w r3, r3, #64 @ 0x40 800c124: 81bb strh r3, [r7, #12] 800c126: 89bb ldrh r3, [r7, #12] 800c128: f083 0320 eor.w r3, r3, #32 800c12c: 81bb strh r3, [r7, #12] 800c12e: 687a ldr r2, [r7, #4] 800c130: 683b ldr r3, [r7, #0] 800c132: 781b ldrb r3, [r3, #0] 800c134: 009b lsls r3, r3, #2 800c136: 441a add r2, r3 800c138: 89bb ldrh r3, [r7, #12] 800c13a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c13e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c142: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800c146: f043 0380 orr.w r3, r3, #128 @ 0x80 800c14a: b29b uxth r3, r3 800c14c: 8013 strh r3, [r2, #0] 800c14e: e04b b.n 800c1e8 } } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); 800c150: 687a ldr r2, [r7, #4] 800c152: 683b ldr r3, [r7, #0] 800c154: 781b ldrb r3, [r3, #0] 800c156: 009b lsls r3, r3, #2 800c158: 4413 add r3, r2 800c15a: 881b ldrh r3, [r3, #0] 800c15c: 82fb strh r3, [r7, #22] 800c15e: 8afb ldrh r3, [r7, #22] 800c160: f403 4380 and.w r3, r3, #16384 @ 0x4000 800c164: 2b00 cmp r3, #0 800c166: d01b beq.n 800c1a0 800c168: 687a ldr r2, [r7, #4] 800c16a: 683b ldr r3, [r7, #0] 800c16c: 781b ldrb r3, [r3, #0] 800c16e: 009b lsls r3, r3, #2 800c170: 4413 add r3, r2 800c172: 881b ldrh r3, [r3, #0] 800c174: b29b uxth r3, r3 800c176: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800c17a: f023 0370 bic.w r3, r3, #112 @ 0x70 800c17e: 82bb strh r3, [r7, #20] 800c180: 687a ldr r2, [r7, #4] 800c182: 683b ldr r3, [r7, #0] 800c184: 781b ldrb r3, [r3, #0] 800c186: 009b lsls r3, r3, #2 800c188: 441a add r2, r3 800c18a: 8abb ldrh r3, [r7, #20] 800c18c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c190: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c194: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800c198: f043 0380 orr.w r3, r3, #128 @ 0x80 800c19c: b29b uxth r3, r3 800c19e: 8013 strh r3, [r2, #0] /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800c1a0: 687a ldr r2, [r7, #4] 800c1a2: 683b ldr r3, [r7, #0] 800c1a4: 781b ldrb r3, [r3, #0] 800c1a6: 009b lsls r3, r3, #2 800c1a8: 4413 add r3, r2 800c1aa: 881b ldrh r3, [r3, #0] 800c1ac: b29b uxth r3, r3 800c1ae: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800c1b2: f023 0370 bic.w r3, r3, #112 @ 0x70 800c1b6: 827b strh r3, [r7, #18] 800c1b8: 8a7b ldrh r3, [r7, #18] 800c1ba: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800c1be: 827b strh r3, [r7, #18] 800c1c0: 8a7b ldrh r3, [r7, #18] 800c1c2: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800c1c6: 827b strh r3, [r7, #18] 800c1c8: 687a ldr r2, [r7, #4] 800c1ca: 683b ldr r3, [r7, #0] 800c1cc: 781b ldrb r3, [r3, #0] 800c1ce: 009b lsls r3, r3, #2 800c1d0: 441a add r2, r3 800c1d2: 8a7b ldrh r3, [r7, #18] 800c1d4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c1d8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c1dc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800c1e0: f043 0380 orr.w r3, r3, #128 @ 0x80 800c1e4: b29b uxth r3, r3 800c1e6: 8013 strh r3, [r2, #0] } } return HAL_OK; 800c1e8: 2300 movs r3, #0 } 800c1ea: 4618 mov r0, r3 800c1ec: 371c adds r7, #28 800c1ee: 46bd mov sp, r7 800c1f0: bc80 pop {r7} 800c1f2: 4770 bx lr 0800c1f4 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) { 800c1f4: b480 push {r7} 800c1f6: b083 sub sp, #12 800c1f8: af00 add r7, sp, #0 800c1fa: 6078 str r0, [r7, #4] 800c1fc: 460b mov r3, r1 800c1fe: 70fb strb r3, [r7, #3] if (address == 0U) 800c200: 78fb ldrb r3, [r7, #3] 800c202: 2b00 cmp r3, #0 800c204: d103 bne.n 800c20e { /* set device address and enable function */ USBx->DADDR = (uint16_t)USB_DADDR_EF; 800c206: 687b ldr r3, [r7, #4] 800c208: 2280 movs r2, #128 @ 0x80 800c20a: f8a3 204c strh.w r2, [r3, #76] @ 0x4c } return HAL_OK; 800c20e: 2300 movs r3, #0 } 800c210: 4618 mov r0, r3 800c212: 370c adds r7, #12 800c214: 46bd mov sp, r7 800c216: bc80 pop {r7} 800c218: 4770 bx lr 0800c21a : * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { 800c21a: b480 push {r7} 800c21c: b083 sub sp, #12 800c21e: af00 add r7, sp, #0 800c220: 6078 str r0, [r7, #4] /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; 800c222: 2300 movs r3, #0 } 800c224: 4618 mov r0, r3 800c226: 370c adds r7, #12 800c228: 46bd mov sp, r7 800c22a: bc80 pop {r7} 800c22c: 4770 bx lr 0800c22e : * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) { 800c22e: b480 push {r7} 800c230: b083 sub sp, #12 800c232: af00 add r7, sp, #0 800c234: 6078 str r0, [r7, #4] /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; 800c236: 2300 movs r3, #0 } 800c238: 4618 mov r0, r3 800c23a: 370c adds r7, #12 800c23c: 46bd mov sp, r7 800c23e: bc80 pop {r7} 800c240: 4770 bx lr 0800c242 : * @brief USB_ReadInterrupts return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { 800c242: b480 push {r7} 800c244: b085 sub sp, #20 800c246: af00 add r7, sp, #0 800c248: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->ISTR; 800c24a: 687b ldr r3, [r7, #4] 800c24c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800c250: b29b uxth r3, r3 800c252: 60fb str r3, [r7, #12] return tmpreg; 800c254: 68fb ldr r3, [r7, #12] } 800c256: 4618 mov r0, r3 800c258: 3714 adds r7, #20 800c25a: 46bd mov sp, r7 800c25c: bc80 pop {r7} 800c25e: 4770 bx lr 0800c260 : * @param USBx Selected device * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { 800c260: b480 push {r7} 800c262: b083 sub sp, #12 800c264: af00 add r7, sp, #0 800c266: 6078 str r0, [r7, #4] 800c268: 6039 str r1, [r7, #0] UNUSED(psetup); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; 800c26a: 2300 movs r3, #0 } 800c26c: 4618 mov r0, r3 800c26e: 370c adds r7, #12 800c270: 46bd mov sp, r7 800c272: bc80 pop {r7} 800c274: 4770 bx lr 0800c276 : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { 800c276: b480 push {r7} 800c278: b08b sub sp, #44 @ 0x2c 800c27a: af00 add r7, sp, #0 800c27c: 60f8 str r0, [r7, #12] 800c27e: 60b9 str r1, [r7, #8] 800c280: 4611 mov r1, r2 800c282: 461a mov r2, r3 800c284: 460b mov r3, r1 800c286: 80fb strh r3, [r7, #6] 800c288: 4613 mov r3, r2 800c28a: 80bb strh r3, [r7, #4] uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; 800c28c: 88bb ldrh r3, [r7, #4] 800c28e: 3301 adds r3, #1 800c290: 085b lsrs r3, r3, #1 800c292: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; 800c294: 68fb ldr r3, [r7, #12] 800c296: 617b str r3, [r7, #20] uint32_t count; uint16_t WrVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; 800c298: 68bb ldr r3, [r7, #8] 800c29a: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); 800c29c: 88fb ldrh r3, [r7, #6] 800c29e: 005a lsls r2, r3, #1 800c2a0: 697b ldr r3, [r7, #20] 800c2a2: 4413 add r3, r2 800c2a4: f503 6380 add.w r3, r3, #1024 @ 0x400 800c2a8: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 800c2aa: 69bb ldr r3, [r7, #24] 800c2ac: 627b str r3, [r7, #36] @ 0x24 800c2ae: e01f b.n 800c2f0 { WrVal = pBuf[0]; 800c2b0: 69fb ldr r3, [r7, #28] 800c2b2: 781b ldrb r3, [r3, #0] 800c2b4: 827b strh r3, [r7, #18] WrVal |= (uint16_t)pBuf[1] << 8; 800c2b6: 69fb ldr r3, [r7, #28] 800c2b8: 3301 adds r3, #1 800c2ba: 781b ldrb r3, [r3, #0] 800c2bc: b21b sxth r3, r3 800c2be: 021b lsls r3, r3, #8 800c2c0: b21a sxth r2, r3 800c2c2: f9b7 3012 ldrsh.w r3, [r7, #18] 800c2c6: 4313 orrs r3, r2 800c2c8: b21b sxth r3, r3 800c2ca: 827b strh r3, [r7, #18] *pdwVal = (WrVal & 0xFFFFU); 800c2cc: 6a3b ldr r3, [r7, #32] 800c2ce: 8a7a ldrh r2, [r7, #18] 800c2d0: 801a strh r2, [r3, #0] pdwVal++; 800c2d2: 6a3b ldr r3, [r7, #32] 800c2d4: 3302 adds r3, #2 800c2d6: 623b str r3, [r7, #32] #if PMA_ACCESS > 1U pdwVal++; 800c2d8: 6a3b ldr r3, [r7, #32] 800c2da: 3302 adds r3, #2 800c2dc: 623b str r3, [r7, #32] #endif /* PMA_ACCESS */ pBuf++; 800c2de: 69fb ldr r3, [r7, #28] 800c2e0: 3301 adds r3, #1 800c2e2: 61fb str r3, [r7, #28] pBuf++; 800c2e4: 69fb ldr r3, [r7, #28] 800c2e6: 3301 adds r3, #1 800c2e8: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) 800c2ea: 6a7b ldr r3, [r7, #36] @ 0x24 800c2ec: 3b01 subs r3, #1 800c2ee: 627b str r3, [r7, #36] @ 0x24 800c2f0: 6a7b ldr r3, [r7, #36] @ 0x24 800c2f2: 2b00 cmp r3, #0 800c2f4: d1dc bne.n 800c2b0 } } 800c2f6: bf00 nop 800c2f8: bf00 nop 800c2fa: 372c adds r7, #44 @ 0x2c 800c2fc: 46bd mov sp, r7 800c2fe: bc80 pop {r7} 800c300: 4770 bx lr 0800c302 : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { 800c302: b480 push {r7} 800c304: b08b sub sp, #44 @ 0x2c 800c306: af00 add r7, sp, #0 800c308: 60f8 str r0, [r7, #12] 800c30a: 60b9 str r1, [r7, #8] 800c30c: 4611 mov r1, r2 800c30e: 461a mov r2, r3 800c310: 460b mov r3, r1 800c312: 80fb strh r3, [r7, #6] 800c314: 4613 mov r3, r2 800c316: 80bb strh r3, [r7, #4] uint32_t n = (uint32_t)wNBytes >> 1; 800c318: 88bb ldrh r3, [r7, #4] 800c31a: 085b lsrs r3, r3, #1 800c31c: b29b uxth r3, r3 800c31e: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; 800c320: 68fb ldr r3, [r7, #12] 800c322: 617b str r3, [r7, #20] uint32_t count; uint32_t RdVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; 800c324: 68bb ldr r3, [r7, #8] 800c326: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); 800c328: 88fb ldrh r3, [r7, #6] 800c32a: 005a lsls r2, r3, #1 800c32c: 697b ldr r3, [r7, #20] 800c32e: 4413 add r3, r2 800c330: f503 6380 add.w r3, r3, #1024 @ 0x400 800c334: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 800c336: 69bb ldr r3, [r7, #24] 800c338: 627b str r3, [r7, #36] @ 0x24 800c33a: e01b b.n 800c374 { RdVal = *(__IO uint16_t *)pdwVal; 800c33c: 6a3b ldr r3, [r7, #32] 800c33e: 881b ldrh r3, [r3, #0] 800c340: b29b uxth r3, r3 800c342: 613b str r3, [r7, #16] pdwVal++; 800c344: 6a3b ldr r3, [r7, #32] 800c346: 3302 adds r3, #2 800c348: 623b str r3, [r7, #32] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); 800c34a: 693b ldr r3, [r7, #16] 800c34c: b2da uxtb r2, r3 800c34e: 69fb ldr r3, [r7, #28] 800c350: 701a strb r2, [r3, #0] pBuf++; 800c352: 69fb ldr r3, [r7, #28] 800c354: 3301 adds r3, #1 800c356: 61fb str r3, [r7, #28] *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); 800c358: 693b ldr r3, [r7, #16] 800c35a: 0a1b lsrs r3, r3, #8 800c35c: b2da uxtb r2, r3 800c35e: 69fb ldr r3, [r7, #28] 800c360: 701a strb r2, [r3, #0] pBuf++; 800c362: 69fb ldr r3, [r7, #28] 800c364: 3301 adds r3, #1 800c366: 61fb str r3, [r7, #28] #if PMA_ACCESS > 1U pdwVal++; 800c368: 6a3b ldr r3, [r7, #32] 800c36a: 3302 adds r3, #2 800c36c: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 800c36e: 6a7b ldr r3, [r7, #36] @ 0x24 800c370: 3b01 subs r3, #1 800c372: 627b str r3, [r7, #36] @ 0x24 800c374: 6a7b ldr r3, [r7, #36] @ 0x24 800c376: 2b00 cmp r3, #0 800c378: d1e0 bne.n 800c33c #endif /* PMA_ACCESS */ } if ((wNBytes % 2U) != 0U) 800c37a: 88bb ldrh r3, [r7, #4] 800c37c: f003 0301 and.w r3, r3, #1 800c380: b29b uxth r3, r3 800c382: 2b00 cmp r3, #0 800c384: d007 beq.n 800c396 { RdVal = *pdwVal; 800c386: 6a3b ldr r3, [r7, #32] 800c388: 881b ldrh r3, [r3, #0] 800c38a: b29b uxth r3, r3 800c38c: 613b str r3, [r7, #16] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); 800c38e: 693b ldr r3, [r7, #16] 800c390: b2da uxtb r2, r3 800c392: 69fb ldr r3, [r7, #28] 800c394: 701a strb r2, [r3, #0] } } 800c396: bf00 nop 800c398: 372c adds r7, #44 @ 0x2c 800c39a: 46bd mov sp, r7 800c39c: bc80 pop {r7} 800c39e: 4770 bx lr 0800c3a0 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800c3a0: b580 push {r7, lr} 800c3a2: b084 sub sp, #16 800c3a4: af00 add r7, sp, #0 800c3a6: 6078 str r0, [r7, #4] 800c3a8: 460b mov r3, r1 800c3aa: 70fb strb r3, [r7, #3] uint8_t ret = 0U; 800c3ac: 2300 movs r3, #0 800c3ae: 73fb strb r3, [r7, #15] USBD_CDC_HandleTypeDef *hcdc; if (pdev->dev_speed == USBD_SPEED_HIGH) 800c3b0: 687b ldr r3, [r7, #4] 800c3b2: 7c1b ldrb r3, [r3, #16] 800c3b4: 2b00 cmp r3, #0 800c3b6: d115 bne.n 800c3e4 { /* Open EP IN */ USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 800c3b8: f44f 7300 mov.w r3, #512 @ 0x200 800c3bc: 2202 movs r2, #2 800c3be: 2181 movs r1, #129 @ 0x81 800c3c0: 6878 ldr r0, [r7, #4] 800c3c2: f001 ff00 bl 800e1c6 CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 800c3c6: 687b ldr r3, [r7, #4] 800c3c8: 2201 movs r2, #1 800c3ca: 62da str r2, [r3, #44] @ 0x2c /* Open EP OUT */ USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 800c3cc: f44f 7300 mov.w r3, #512 @ 0x200 800c3d0: 2202 movs r2, #2 800c3d2: 2101 movs r1, #1 800c3d4: 6878 ldr r0, [r7, #4] 800c3d6: f001 fef6 bl 800e1c6 CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 800c3da: 687b ldr r3, [r7, #4] 800c3dc: 2201 movs r2, #1 800c3de: f8c3 216c str.w r2, [r3, #364] @ 0x16c 800c3e2: e012 b.n 800c40a } else { /* Open EP IN */ USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 800c3e4: 2340 movs r3, #64 @ 0x40 800c3e6: 2202 movs r2, #2 800c3e8: 2181 movs r1, #129 @ 0x81 800c3ea: 6878 ldr r0, [r7, #4] 800c3ec: f001 feeb bl 800e1c6 CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 800c3f0: 687b ldr r3, [r7, #4] 800c3f2: 2201 movs r2, #1 800c3f4: 62da str r2, [r3, #44] @ 0x2c /* Open EP OUT */ USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 800c3f6: 2340 movs r3, #64 @ 0x40 800c3f8: 2202 movs r2, #2 800c3fa: 2101 movs r1, #1 800c3fc: 6878 ldr r0, [r7, #4] 800c3fe: f001 fee2 bl 800e1c6 CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 800c402: 687b ldr r3, [r7, #4] 800c404: 2201 movs r2, #1 800c406: f8c3 216c str.w r2, [r3, #364] @ 0x16c } /* Open Command IN EP */ USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); 800c40a: 2308 movs r3, #8 800c40c: 2203 movs r2, #3 800c40e: 2182 movs r1, #130 @ 0x82 800c410: 6878 ldr r0, [r7, #4] 800c412: f001 fed8 bl 800e1c6 pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; 800c416: 687b ldr r3, [r7, #4] 800c418: 2201 movs r2, #1 800c41a: 641a str r2, [r3, #64] @ 0x40 pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); 800c41c: f44f 7007 mov.w r0, #540 @ 0x21c 800c420: f001 fff8 bl 800e414 800c424: 4602 mov r2, r0 800c426: 687b ldr r3, [r7, #4] 800c428: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClassData == NULL) 800c42c: 687b ldr r3, [r7, #4] 800c42e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c432: 2b00 cmp r3, #0 800c434: d102 bne.n 800c43c { ret = 1U; 800c436: 2301 movs r3, #1 800c438: 73fb strb r3, [r7, #15] 800c43a: e026 b.n 800c48a } else { hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c43c: 687b ldr r3, [r7, #4] 800c43e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c442: 60bb str r3, [r7, #8] /* Init physical Interface components */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); 800c444: 687b ldr r3, [r7, #4] 800c446: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c44a: 681b ldr r3, [r3, #0] 800c44c: 4798 blx r3 /* Init Xfer states */ hcdc->TxState = 0U; 800c44e: 68bb ldr r3, [r7, #8] 800c450: 2200 movs r2, #0 800c452: f8c3 2214 str.w r2, [r3, #532] @ 0x214 hcdc->RxState = 0U; 800c456: 68bb ldr r3, [r7, #8] 800c458: 2200 movs r2, #0 800c45a: f8c3 2218 str.w r2, [r3, #536] @ 0x218 if (pdev->dev_speed == USBD_SPEED_HIGH) 800c45e: 687b ldr r3, [r7, #4] 800c460: 7c1b ldrb r3, [r3, #16] 800c462: 2b00 cmp r3, #0 800c464: d109 bne.n 800c47a { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 800c466: 68bb ldr r3, [r7, #8] 800c468: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800c46c: f44f 7300 mov.w r3, #512 @ 0x200 800c470: 2101 movs r1, #1 800c472: 6878 ldr r0, [r7, #4] 800c474: f001 ff97 bl 800e3a6 800c478: e007 b.n 800c48a CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 800c47a: 68bb ldr r3, [r7, #8] 800c47c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800c480: 2340 movs r3, #64 @ 0x40 800c482: 2101 movs r1, #1 800c484: 6878 ldr r0, [r7, #4] 800c486: f001 ff8e bl 800e3a6 CDC_DATA_FS_OUT_PACKET_SIZE); } } return ret; 800c48a: 7bfb ldrb r3, [r7, #15] } 800c48c: 4618 mov r0, r3 800c48e: 3710 adds r7, #16 800c490: 46bd mov sp, r7 800c492: bd80 pop {r7, pc} 0800c494 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800c494: b580 push {r7, lr} 800c496: b084 sub sp, #16 800c498: af00 add r7, sp, #0 800c49a: 6078 str r0, [r7, #4] 800c49c: 460b mov r3, r1 800c49e: 70fb strb r3, [r7, #3] uint8_t ret = 0U; 800c4a0: 2300 movs r3, #0 800c4a2: 73fb strb r3, [r7, #15] /* Close EP IN */ USBD_LL_CloseEP(pdev, CDC_IN_EP); 800c4a4: 2181 movs r1, #129 @ 0x81 800c4a6: 6878 ldr r0, [r7, #4] 800c4a8: f001 feb3 bl 800e212 pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; 800c4ac: 687b ldr r3, [r7, #4] 800c4ae: 2200 movs r2, #0 800c4b0: 62da str r2, [r3, #44] @ 0x2c /* Close EP OUT */ USBD_LL_CloseEP(pdev, CDC_OUT_EP); 800c4b2: 2101 movs r1, #1 800c4b4: 6878 ldr r0, [r7, #4] 800c4b6: f001 feac bl 800e212 pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; 800c4ba: 687b ldr r3, [r7, #4] 800c4bc: 2200 movs r2, #0 800c4be: f8c3 216c str.w r2, [r3, #364] @ 0x16c /* Close Command IN EP */ USBD_LL_CloseEP(pdev, CDC_CMD_EP); 800c4c2: 2182 movs r1, #130 @ 0x82 800c4c4: 6878 ldr r0, [r7, #4] 800c4c6: f001 fea4 bl 800e212 pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; 800c4ca: 687b ldr r3, [r7, #4] 800c4cc: 2200 movs r2, #0 800c4ce: 641a str r2, [r3, #64] @ 0x40 /* DeInit physical Interface components */ if (pdev->pClassData != NULL) 800c4d0: 687b ldr r3, [r7, #4] 800c4d2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c4d6: 2b00 cmp r3, #0 800c4d8: d00e beq.n 800c4f8 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); 800c4da: 687b ldr r3, [r7, #4] 800c4dc: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c4e0: 685b ldr r3, [r3, #4] 800c4e2: 4798 blx r3 USBD_free(pdev->pClassData); 800c4e4: 687b ldr r3, [r7, #4] 800c4e6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c4ea: 4618 mov r0, r3 800c4ec: f001 ff9e bl 800e42c pdev->pClassData = NULL; 800c4f0: 687b ldr r3, [r7, #4] 800c4f2: 2200 movs r2, #0 800c4f4: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 } return ret; 800c4f8: 7bfb ldrb r3, [r7, #15] } 800c4fa: 4618 mov r0, r3 800c4fc: 3710 adds r7, #16 800c4fe: 46bd mov sp, r7 800c500: bd80 pop {r7, pc} 0800c502 : * @param req: usb requests * @retval status */ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800c502: b580 push {r7, lr} 800c504: b086 sub sp, #24 800c506: af00 add r7, sp, #0 800c508: 6078 str r0, [r7, #4] 800c50a: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c50c: 687b ldr r3, [r7, #4] 800c50e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c512: 613b str r3, [r7, #16] uint8_t ifalt = 0U; 800c514: 2300 movs r3, #0 800c516: 73fb strb r3, [r7, #15] uint16_t status_info = 0U; 800c518: 2300 movs r3, #0 800c51a: 81bb strh r3, [r7, #12] uint8_t ret = USBD_OK; 800c51c: 2300 movs r3, #0 800c51e: 75fb strb r3, [r7, #23] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800c520: 683b ldr r3, [r7, #0] 800c522: 781b ldrb r3, [r3, #0] 800c524: f003 0360 and.w r3, r3, #96 @ 0x60 800c528: 2b00 cmp r3, #0 800c52a: d039 beq.n 800c5a0 800c52c: 2b20 cmp r3, #32 800c52e: d17f bne.n 800c630 { case USB_REQ_TYPE_CLASS : if (req->wLength) 800c530: 683b ldr r3, [r7, #0] 800c532: 88db ldrh r3, [r3, #6] 800c534: 2b00 cmp r3, #0 800c536: d029 beq.n 800c58c { if (req->bmRequest & 0x80U) 800c538: 683b ldr r3, [r7, #0] 800c53a: 781b ldrb r3, [r3, #0] 800c53c: b25b sxtb r3, r3 800c53e: 2b00 cmp r3, #0 800c540: da11 bge.n 800c566 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 800c542: 687b ldr r3, [r7, #4] 800c544: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c548: 689b ldr r3, [r3, #8] 800c54a: 683a ldr r2, [r7, #0] 800c54c: 7850 ldrb r0, [r2, #1] (uint8_t *)(void *)hcdc->data, 800c54e: 6939 ldr r1, [r7, #16] ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 800c550: 683a ldr r2, [r7, #0] 800c552: 88d2 ldrh r2, [r2, #6] 800c554: 4798 blx r3 req->wLength); USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); 800c556: 6939 ldr r1, [r7, #16] 800c558: 683b ldr r3, [r7, #0] 800c55a: 88db ldrh r3, [r3, #6] 800c55c: 461a mov r2, r3 800c55e: 6878 ldr r0, [r7, #4] 800c560: f001 fa06 bl 800d970 else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, (uint8_t *)(void *)req, 0U); } break; 800c564: e06b b.n 800c63e hcdc->CmdOpCode = req->bRequest; 800c566: 683b ldr r3, [r7, #0] 800c568: 785a ldrb r2, [r3, #1] 800c56a: 693b ldr r3, [r7, #16] 800c56c: f883 2200 strb.w r2, [r3, #512] @ 0x200 hcdc->CmdLength = (uint8_t)req->wLength; 800c570: 683b ldr r3, [r7, #0] 800c572: 88db ldrh r3, [r3, #6] 800c574: b2da uxtb r2, r3 800c576: 693b ldr r3, [r7, #16] 800c578: f883 2201 strb.w r2, [r3, #513] @ 0x201 USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); 800c57c: 6939 ldr r1, [r7, #16] 800c57e: 683b ldr r3, [r7, #0] 800c580: 88db ldrh r3, [r3, #6] 800c582: 461a mov r2, r3 800c584: 6878 ldr r0, [r7, #4] 800c586: f001 fa21 bl 800d9cc break; 800c58a: e058 b.n 800c63e ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 800c58c: 687b ldr r3, [r7, #4] 800c58e: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c592: 689b ldr r3, [r3, #8] 800c594: 683a ldr r2, [r7, #0] 800c596: 7850 ldrb r0, [r2, #1] 800c598: 2200 movs r2, #0 800c59a: 6839 ldr r1, [r7, #0] 800c59c: 4798 blx r3 break; 800c59e: e04e b.n 800c63e case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800c5a0: 683b ldr r3, [r7, #0] 800c5a2: 785b ldrb r3, [r3, #1] 800c5a4: 2b0b cmp r3, #11 800c5a6: d02e beq.n 800c606 800c5a8: 2b0b cmp r3, #11 800c5aa: dc38 bgt.n 800c61e 800c5ac: 2b00 cmp r3, #0 800c5ae: d002 beq.n 800c5b6 800c5b0: 2b0a cmp r3, #10 800c5b2: d014 beq.n 800c5de 800c5b4: e033 b.n 800c61e { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800c5b6: 687b ldr r3, [r7, #4] 800c5b8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800c5bc: 2b03 cmp r3, #3 800c5be: d107 bne.n 800c5d0 { USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); 800c5c0: f107 030c add.w r3, r7, #12 800c5c4: 2202 movs r2, #2 800c5c6: 4619 mov r1, r3 800c5c8: 6878 ldr r0, [r7, #4] 800c5ca: f001 f9d1 bl 800d970 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 800c5ce: e02e b.n 800c62e USBD_CtlError(pdev, req); 800c5d0: 6839 ldr r1, [r7, #0] 800c5d2: 6878 ldr r0, [r7, #4] 800c5d4: f001 f962 bl 800d89c ret = USBD_FAIL; 800c5d8: 2302 movs r3, #2 800c5da: 75fb strb r3, [r7, #23] break; 800c5dc: e027 b.n 800c62e case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800c5de: 687b ldr r3, [r7, #4] 800c5e0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800c5e4: 2b03 cmp r3, #3 800c5e6: d107 bne.n 800c5f8 { USBD_CtlSendData(pdev, &ifalt, 1U); 800c5e8: f107 030f add.w r3, r7, #15 800c5ec: 2201 movs r2, #1 800c5ee: 4619 mov r1, r3 800c5f0: 6878 ldr r0, [r7, #4] 800c5f2: f001 f9bd bl 800d970 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 800c5f6: e01a b.n 800c62e USBD_CtlError(pdev, req); 800c5f8: 6839 ldr r1, [r7, #0] 800c5fa: 6878 ldr r0, [r7, #4] 800c5fc: f001 f94e bl 800d89c ret = USBD_FAIL; 800c600: 2302 movs r3, #2 800c602: 75fb strb r3, [r7, #23] break; 800c604: e013 b.n 800c62e case USB_REQ_SET_INTERFACE: if (pdev->dev_state != USBD_STATE_CONFIGURED) 800c606: 687b ldr r3, [r7, #4] 800c608: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800c60c: 2b03 cmp r3, #3 800c60e: d00d beq.n 800c62c { USBD_CtlError(pdev, req); 800c610: 6839 ldr r1, [r7, #0] 800c612: 6878 ldr r0, [r7, #4] 800c614: f001 f942 bl 800d89c ret = USBD_FAIL; 800c618: 2302 movs r3, #2 800c61a: 75fb strb r3, [r7, #23] } break; 800c61c: e006 b.n 800c62c default: USBD_CtlError(pdev, req); 800c61e: 6839 ldr r1, [r7, #0] 800c620: 6878 ldr r0, [r7, #4] 800c622: f001 f93b bl 800d89c ret = USBD_FAIL; 800c626: 2302 movs r3, #2 800c628: 75fb strb r3, [r7, #23] break; 800c62a: e000 b.n 800c62e break; 800c62c: bf00 nop } break; 800c62e: e006 b.n 800c63e default: USBD_CtlError(pdev, req); 800c630: 6839 ldr r1, [r7, #0] 800c632: 6878 ldr r0, [r7, #4] 800c634: f001 f932 bl 800d89c ret = USBD_FAIL; 800c638: 2302 movs r3, #2 800c63a: 75fb strb r3, [r7, #23] break; 800c63c: bf00 nop } return ret; 800c63e: 7dfb ldrb r3, [r7, #23] } 800c640: 4618 mov r0, r3 800c642: 3718 adds r7, #24 800c644: 46bd mov sp, r7 800c646: bd80 pop {r7, pc} 0800c648 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 800c648: b580 push {r7, lr} 800c64a: b084 sub sp, #16 800c64c: af00 add r7, sp, #0 800c64e: 6078 str r0, [r7, #4] 800c650: 460b mov r3, r1 800c652: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 800c654: 687b ldr r3, [r7, #4] 800c656: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c65a: 60fb str r3, [r7, #12] PCD_HandleTypeDef *hpcd = pdev->pData; 800c65c: 687b ldr r3, [r7, #4] 800c65e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800c662: 60bb str r3, [r7, #8] if (pdev->pClassData != NULL) 800c664: 687b ldr r3, [r7, #4] 800c666: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c66a: 2b00 cmp r3, #0 800c66c: d03a beq.n 800c6e4 { if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) 800c66e: 78fa ldrb r2, [r7, #3] 800c670: 6879 ldr r1, [r7, #4] 800c672: 4613 mov r3, r2 800c674: 009b lsls r3, r3, #2 800c676: 4413 add r3, r2 800c678: 009b lsls r3, r3, #2 800c67a: 440b add r3, r1 800c67c: 331c adds r3, #28 800c67e: 681b ldr r3, [r3, #0] 800c680: 2b00 cmp r3, #0 800c682: d029 beq.n 800c6d8 800c684: 78fa ldrb r2, [r7, #3] 800c686: 6879 ldr r1, [r7, #4] 800c688: 4613 mov r3, r2 800c68a: 009b lsls r3, r3, #2 800c68c: 4413 add r3, r2 800c68e: 009b lsls r3, r3, #2 800c690: 440b add r3, r1 800c692: 331c adds r3, #28 800c694: 681a ldr r2, [r3, #0] 800c696: 78f9 ldrb r1, [r7, #3] 800c698: 68b8 ldr r0, [r7, #8] 800c69a: 460b mov r3, r1 800c69c: 009b lsls r3, r3, #2 800c69e: 440b add r3, r1 800c6a0: 00db lsls r3, r3, #3 800c6a2: 4403 add r3, r0 800c6a4: 3320 adds r3, #32 800c6a6: 681b ldr r3, [r3, #0] 800c6a8: fbb2 f1f3 udiv r1, r2, r3 800c6ac: fb01 f303 mul.w r3, r1, r3 800c6b0: 1ad3 subs r3, r2, r3 800c6b2: 2b00 cmp r3, #0 800c6b4: d110 bne.n 800c6d8 { /* Update the packet total length */ pdev->ep_in[epnum].total_length = 0U; 800c6b6: 78fa ldrb r2, [r7, #3] 800c6b8: 6879 ldr r1, [r7, #4] 800c6ba: 4613 mov r3, r2 800c6bc: 009b lsls r3, r3, #2 800c6be: 4413 add r3, r2 800c6c0: 009b lsls r3, r3, #2 800c6c2: 440b add r3, r1 800c6c4: 331c adds r3, #28 800c6c6: 2200 movs r2, #0 800c6c8: 601a str r2, [r3, #0] /* Send ZLP */ USBD_LL_Transmit(pdev, epnum, NULL, 0U); 800c6ca: 78f9 ldrb r1, [r7, #3] 800c6cc: 2300 movs r3, #0 800c6ce: 2200 movs r2, #0 800c6d0: 6878 ldr r0, [r7, #4] 800c6d2: f001 fe45 bl 800e360 800c6d6: e003 b.n 800c6e0 } else { hcdc->TxState = 0U; 800c6d8: 68fb ldr r3, [r7, #12] 800c6da: 2200 movs r2, #0 800c6dc: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } return USBD_OK; 800c6e0: 2300 movs r3, #0 800c6e2: e000 b.n 800c6e6 } else { return USBD_FAIL; 800c6e4: 2302 movs r3, #2 } } 800c6e6: 4618 mov r0, r3 800c6e8: 3710 adds r7, #16 800c6ea: 46bd mov sp, r7 800c6ec: bd80 pop {r7, pc} 0800c6ee : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { 800c6ee: b580 push {r7, lr} 800c6f0: b084 sub sp, #16 800c6f2: af00 add r7, sp, #0 800c6f4: 6078 str r0, [r7, #4] 800c6f6: 460b mov r3, r1 800c6f8: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c6fa: 687b ldr r3, [r7, #4] 800c6fc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c700: 60fb str r3, [r7, #12] /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); 800c702: 78fb ldrb r3, [r7, #3] 800c704: 4619 mov r1, r3 800c706: 6878 ldr r0, [r7, #4] 800c708: f001 fe70 bl 800e3ec 800c70c: 4602 mov r2, r0 800c70e: 68fb ldr r3, [r7, #12] 800c710: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ if (pdev->pClassData != NULL) 800c714: 687b ldr r3, [r7, #4] 800c716: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c71a: 2b00 cmp r3, #0 800c71c: d00d beq.n 800c73a { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); 800c71e: 687b ldr r3, [r7, #4] 800c720: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c724: 68db ldr r3, [r3, #12] 800c726: 68fa ldr r2, [r7, #12] 800c728: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204 800c72c: 68fa ldr r2, [r7, #12] 800c72e: f502 7203 add.w r2, r2, #524 @ 0x20c 800c732: 4611 mov r1, r2 800c734: 4798 blx r3 return USBD_OK; 800c736: 2300 movs r3, #0 800c738: e000 b.n 800c73c } else { return USBD_FAIL; 800c73a: 2302 movs r3, #2 } } 800c73c: 4618 mov r0, r3 800c73e: 3710 adds r7, #16 800c740: 46bd mov sp, r7 800c742: bd80 pop {r7, pc} 0800c744 : * Handle EP0 Rx Ready event * @param pdev: device instance * @retval status */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { 800c744: b580 push {r7, lr} 800c746: b084 sub sp, #16 800c748: af00 add r7, sp, #0 800c74a: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c74c: 687b ldr r3, [r7, #4] 800c74e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c752: 60fb str r3, [r7, #12] if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) 800c754: 687b ldr r3, [r7, #4] 800c756: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c75a: 2b00 cmp r3, #0 800c75c: d014 beq.n 800c788 800c75e: 68fb ldr r3, [r7, #12] 800c760: f893 3200 ldrb.w r3, [r3, #512] @ 0x200 800c764: 2bff cmp r3, #255 @ 0xff 800c766: d00f beq.n 800c788 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 800c768: 687b ldr r3, [r7, #4] 800c76a: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 800c76e: 689b ldr r3, [r3, #8] 800c770: 68fa ldr r2, [r7, #12] 800c772: f892 0200 ldrb.w r0, [r2, #512] @ 0x200 (uint8_t *)(void *)hcdc->data, 800c776: 68f9 ldr r1, [r7, #12] (uint16_t)hcdc->CmdLength); 800c778: 68fa ldr r2, [r7, #12] 800c77a: f892 2201 ldrb.w r2, [r2, #513] @ 0x201 ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 800c77e: 4798 blx r3 hcdc->CmdOpCode = 0xFFU; 800c780: 68fb ldr r3, [r7, #12] 800c782: 22ff movs r2, #255 @ 0xff 800c784: f883 2200 strb.w r2, [r3, #512] @ 0x200 } return USBD_OK; 800c788: 2300 movs r3, #0 } 800c78a: 4618 mov r0, r3 800c78c: 3710 adds r7, #16 800c78e: 46bd mov sp, r7 800c790: bd80 pop {r7, pc} ... 0800c794 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { 800c794: b480 push {r7} 800c796: b083 sub sp, #12 800c798: af00 add r7, sp, #0 800c79a: 6078 str r0, [r7, #4] *length = sizeof(USBD_CDC_CfgFSDesc); 800c79c: 687b ldr r3, [r7, #4] 800c79e: 2243 movs r2, #67 @ 0x43 800c7a0: 801a strh r2, [r3, #0] return USBD_CDC_CfgFSDesc; 800c7a2: 4b03 ldr r3, [pc, #12] @ (800c7b0 ) } 800c7a4: 4618 mov r0, r3 800c7a6: 370c adds r7, #12 800c7a8: 46bd mov sp, r7 800c7aa: bc80 pop {r7} 800c7ac: 4770 bx lr 800c7ae: bf00 nop 800c7b0: 200000a4 .word 0x200000a4 0800c7b4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { 800c7b4: b480 push {r7} 800c7b6: b083 sub sp, #12 800c7b8: af00 add r7, sp, #0 800c7ba: 6078 str r0, [r7, #4] *length = sizeof(USBD_CDC_CfgHSDesc); 800c7bc: 687b ldr r3, [r7, #4] 800c7be: 2243 movs r2, #67 @ 0x43 800c7c0: 801a strh r2, [r3, #0] return USBD_CDC_CfgHSDesc; 800c7c2: 4b03 ldr r3, [pc, #12] @ (800c7d0 ) } 800c7c4: 4618 mov r0, r3 800c7c6: 370c adds r7, #12 800c7c8: 46bd mov sp, r7 800c7ca: bc80 pop {r7} 800c7cc: 4770 bx lr 800c7ce: bf00 nop 800c7d0: 20000060 .word 0x20000060 0800c7d4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { 800c7d4: b480 push {r7} 800c7d6: b083 sub sp, #12 800c7d8: af00 add r7, sp, #0 800c7da: 6078 str r0, [r7, #4] *length = sizeof(USBD_CDC_OtherSpeedCfgDesc); 800c7dc: 687b ldr r3, [r7, #4] 800c7de: 2243 movs r2, #67 @ 0x43 800c7e0: 801a strh r2, [r3, #0] return USBD_CDC_OtherSpeedCfgDesc; 800c7e2: 4b03 ldr r3, [pc, #12] @ (800c7f0 ) } 800c7e4: 4618 mov r0, r3 800c7e6: 370c adds r7, #12 800c7e8: 46bd mov sp, r7 800c7ea: bc80 pop {r7} 800c7ec: 4770 bx lr 800c7ee: bf00 nop 800c7f0: 200000e8 .word 0x200000e8 0800c7f4 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { 800c7f4: b480 push {r7} 800c7f6: b083 sub sp, #12 800c7f8: af00 add r7, sp, #0 800c7fa: 6078 str r0, [r7, #4] *length = sizeof(USBD_CDC_DeviceQualifierDesc); 800c7fc: 687b ldr r3, [r7, #4] 800c7fe: 220a movs r2, #10 800c800: 801a strh r2, [r3, #0] return USBD_CDC_DeviceQualifierDesc; 800c802: 4b03 ldr r3, [pc, #12] @ (800c810 ) } 800c804: 4618 mov r0, r3 800c806: 370c adds r7, #12 800c808: 46bd mov sp, r7 800c80a: bc80 pop {r7} 800c80c: 4770 bx lr 800c80e: bf00 nop 800c810: 2000001c .word 0x2000001c 0800c814 : * @param fops: CD Interface callback * @retval status */ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { 800c814: b480 push {r7} 800c816: b085 sub sp, #20 800c818: af00 add r7, sp, #0 800c81a: 6078 str r0, [r7, #4] 800c81c: 6039 str r1, [r7, #0] uint8_t ret = USBD_FAIL; 800c81e: 2302 movs r3, #2 800c820: 73fb strb r3, [r7, #15] if (fops != NULL) 800c822: 683b ldr r3, [r7, #0] 800c824: 2b00 cmp r3, #0 800c826: d005 beq.n 800c834 { pdev->pUserData = fops; 800c828: 687b ldr r3, [r7, #4] 800c82a: 683a ldr r2, [r7, #0] 800c82c: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc ret = USBD_OK; 800c830: 2300 movs r3, #0 800c832: 73fb strb r3, [r7, #15] } return ret; 800c834: 7bfb ldrb r3, [r7, #15] } 800c836: 4618 mov r0, r3 800c838: 3714 adds r7, #20 800c83a: 46bd mov sp, r7 800c83c: bc80 pop {r7} 800c83e: 4770 bx lr 0800c840 : * @retval status */ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint16_t length) { 800c840: b480 push {r7} 800c842: b087 sub sp, #28 800c844: af00 add r7, sp, #0 800c846: 60f8 str r0, [r7, #12] 800c848: 60b9 str r1, [r7, #8] 800c84a: 4613 mov r3, r2 800c84c: 80fb strh r3, [r7, #6] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c84e: 68fb ldr r3, [r7, #12] 800c850: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c854: 617b str r3, [r7, #20] hcdc->TxBuffer = pbuff; 800c856: 697b ldr r3, [r7, #20] 800c858: 68ba ldr r2, [r7, #8] 800c85a: f8c3 2208 str.w r2, [r3, #520] @ 0x208 hcdc->TxLength = length; 800c85e: 88fa ldrh r2, [r7, #6] 800c860: 697b ldr r3, [r7, #20] 800c862: f8c3 2210 str.w r2, [r3, #528] @ 0x210 return USBD_OK; 800c866: 2300 movs r3, #0 } 800c868: 4618 mov r0, r3 800c86a: 371c adds r7, #28 800c86c: 46bd mov sp, r7 800c86e: bc80 pop {r7} 800c870: 4770 bx lr 0800c872 : * @param pbuff: Rx Buffer * @retval status */ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { 800c872: b480 push {r7} 800c874: b085 sub sp, #20 800c876: af00 add r7, sp, #0 800c878: 6078 str r0, [r7, #4] 800c87a: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c87c: 687b ldr r3, [r7, #4] 800c87e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c882: 60fb str r3, [r7, #12] hcdc->RxBuffer = pbuff; 800c884: 68fb ldr r3, [r7, #12] 800c886: 683a ldr r2, [r7, #0] 800c888: f8c3 2204 str.w r2, [r3, #516] @ 0x204 return USBD_OK; 800c88c: 2300 movs r3, #0 } 800c88e: 4618 mov r0, r3 800c890: 3714 adds r7, #20 800c892: 46bd mov sp, r7 800c894: bc80 pop {r7} 800c896: 4770 bx lr 0800c898 : * Transmit packet on IN endpoint * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { 800c898: b580 push {r7, lr} 800c89a: b084 sub sp, #16 800c89c: af00 add r7, sp, #0 800c89e: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c8a0: 687b ldr r3, [r7, #4] 800c8a2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c8a6: 60fb str r3, [r7, #12] if (pdev->pClassData != NULL) 800c8a8: 687b ldr r3, [r7, #4] 800c8aa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c8ae: 2b00 cmp r3, #0 800c8b0: d01c beq.n 800c8ec { if (hcdc->TxState == 0U) 800c8b2: 68fb ldr r3, [r7, #12] 800c8b4: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214 800c8b8: 2b00 cmp r3, #0 800c8ba: d115 bne.n 800c8e8 { /* Tx Transfer in progress */ hcdc->TxState = 1U; 800c8bc: 68fb ldr r3, [r7, #12] 800c8be: 2201 movs r2, #1 800c8c0: f8c3 2214 str.w r2, [r3, #532] @ 0x214 /* Update the packet total length */ pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; 800c8c4: 68fb ldr r3, [r7, #12] 800c8c6: f8d3 2210 ldr.w r2, [r3, #528] @ 0x210 800c8ca: 687b ldr r3, [r7, #4] 800c8cc: 631a str r2, [r3, #48] @ 0x30 /* Transmit next packet */ USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, 800c8ce: 68fb ldr r3, [r7, #12] 800c8d0: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208 (uint16_t)hcdc->TxLength); 800c8d4: 68fb ldr r3, [r7, #12] 800c8d6: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210 USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, 800c8da: b29b uxth r3, r3 800c8dc: 2181 movs r1, #129 @ 0x81 800c8de: 6878 ldr r0, [r7, #4] 800c8e0: f001 fd3e bl 800e360 return USBD_OK; 800c8e4: 2300 movs r3, #0 800c8e6: e002 b.n 800c8ee } else { return USBD_BUSY; 800c8e8: 2301 movs r3, #1 800c8ea: e000 b.n 800c8ee } } else { return USBD_FAIL; 800c8ec: 2302 movs r3, #2 } } 800c8ee: 4618 mov r0, r3 800c8f0: 3710 adds r7, #16 800c8f2: 46bd mov sp, r7 800c8f4: bd80 pop {r7, pc} 0800c8f6 : * prepare OUT Endpoint for reception * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { 800c8f6: b580 push {r7, lr} 800c8f8: b084 sub sp, #16 800c8fa: af00 add r7, sp, #0 800c8fc: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; 800c8fe: 687b ldr r3, [r7, #4] 800c900: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c904: 60fb str r3, [r7, #12] /* Suspend or Resume USB Out process */ if (pdev->pClassData != NULL) 800c906: 687b ldr r3, [r7, #4] 800c908: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800c90c: 2b00 cmp r3, #0 800c90e: d017 beq.n 800c940 { if (pdev->dev_speed == USBD_SPEED_HIGH) 800c910: 687b ldr r3, [r7, #4] 800c912: 7c1b ldrb r3, [r3, #16] 800c914: 2b00 cmp r3, #0 800c916: d109 bne.n 800c92c { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, 800c918: 68fb ldr r3, [r7, #12] 800c91a: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800c91e: f44f 7300 mov.w r3, #512 @ 0x200 800c922: 2101 movs r1, #1 800c924: 6878 ldr r0, [r7, #4] 800c926: f001 fd3e bl 800e3a6 800c92a: e007 b.n 800c93c CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, 800c92c: 68fb ldr r3, [r7, #12] 800c92e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800c932: 2340 movs r3, #64 @ 0x40 800c934: 2101 movs r1, #1 800c936: 6878 ldr r0, [r7, #4] 800c938: f001 fd35 bl 800e3a6 CDC_OUT_EP, hcdc->RxBuffer, CDC_DATA_FS_OUT_PACKET_SIZE); } return USBD_OK; 800c93c: 2300 movs r3, #0 800c93e: e000 b.n 800c942 } else { return USBD_FAIL; 800c940: 2302 movs r3, #2 } } 800c942: 4618 mov r0, r3 800c944: 3710 adds r7, #16 800c946: 46bd mov sp, r7 800c948: bd80 pop {r7, pc} 0800c94a : * @param id: Low level core index * @retval None */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 800c94a: b580 push {r7, lr} 800c94c: b084 sub sp, #16 800c94e: af00 add r7, sp, #0 800c950: 60f8 str r0, [r7, #12] 800c952: 60b9 str r1, [r7, #8] 800c954: 4613 mov r3, r2 800c956: 71fb strb r3, [r7, #7] /* Check whether the USB Host handle is valid */ if (pdev == NULL) 800c958: 68fb ldr r3, [r7, #12] 800c95a: 2b00 cmp r3, #0 800c95c: d101 bne.n 800c962 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif return USBD_FAIL; 800c95e: 2302 movs r3, #2 800c960: e01a b.n 800c998 } /* Unlink previous class*/ if (pdev->pClass != NULL) 800c962: 68fb ldr r3, [r7, #12] 800c964: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800c968: 2b00 cmp r3, #0 800c96a: d003 beq.n 800c974 { pdev->pClass = NULL; 800c96c: 68fb ldr r3, [r7, #12] 800c96e: 2200 movs r2, #0 800c970: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Assign USBD Descriptors */ if (pdesc != NULL) 800c974: 68bb ldr r3, [r7, #8] 800c976: 2b00 cmp r3, #0 800c978: d003 beq.n 800c982 { pdev->pDesc = pdesc; 800c97a: 68fb ldr r3, [r7, #12] 800c97c: 68ba ldr r2, [r7, #8] 800c97e: f8c3 22b0 str.w r2, [r3, #688] @ 0x2b0 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 800c982: 68fb ldr r3, [r7, #12] 800c984: 2201 movs r2, #1 800c986: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 800c98a: 68fb ldr r3, [r7, #12] 800c98c: 79fa ldrb r2, [r7, #7] 800c98e: 701a strb r2, [r3, #0] /* Initialize low level driver */ USBD_LL_Init(pdev); 800c990: 68f8 ldr r0, [r7, #12] 800c992: f001 fba3 bl 800e0dc return USBD_OK; 800c996: 2300 movs r3, #0 } 800c998: 4618 mov r0, r3 800c99a: 3710 adds r7, #16 800c99c: 46bd mov sp, r7 800c99e: bd80 pop {r7, pc} 0800c9a0 : * @param pDevice : Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 800c9a0: b480 push {r7} 800c9a2: b085 sub sp, #20 800c9a4: af00 add r7, sp, #0 800c9a6: 6078 str r0, [r7, #4] 800c9a8: 6039 str r1, [r7, #0] USBD_StatusTypeDef status = USBD_OK; 800c9aa: 2300 movs r3, #0 800c9ac: 73fb strb r3, [r7, #15] if (pclass != NULL) 800c9ae: 683b ldr r3, [r7, #0] 800c9b0: 2b00 cmp r3, #0 800c9b2: d006 beq.n 800c9c2 { /* link the class to the USB Device handle */ pdev->pClass = pclass; 800c9b4: 687b ldr r3, [r7, #4] 800c9b6: 683a ldr r2, [r7, #0] 800c9b8: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 status = USBD_OK; 800c9bc: 2300 movs r3, #0 800c9be: 73fb strb r3, [r7, #15] 800c9c0: e001 b.n 800c9c6 else { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif status = USBD_FAIL; 800c9c2: 2302 movs r3, #2 800c9c4: 73fb strb r3, [r7, #15] } return status; 800c9c6: 7bfb ldrb r3, [r7, #15] } 800c9c8: 4618 mov r0, r3 800c9ca: 3714 adds r7, #20 800c9cc: 46bd mov sp, r7 800c9ce: bc80 pop {r7} 800c9d0: 4770 bx lr 0800c9d2 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 800c9d2: b580 push {r7, lr} 800c9d4: b082 sub sp, #8 800c9d6: af00 add r7, sp, #0 800c9d8: 6078 str r0, [r7, #4] /* Start the low level driver */ USBD_LL_Start(pdev); 800c9da: 6878 ldr r0, [r7, #4] 800c9dc: f001 fbd8 bl 800e190 return USBD_OK; 800c9e0: 2300 movs r3, #0 } 800c9e2: 4618 mov r0, r3 800c9e4: 3708 adds r7, #8 800c9e6: 46bd mov sp, r7 800c9e8: bd80 pop {r7, pc} 0800c9ea : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 800c9ea: b480 push {r7} 800c9ec: b083 sub sp, #12 800c9ee: af00 add r7, sp, #0 800c9f0: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 800c9f2: 2300 movs r3, #0 } 800c9f4: 4618 mov r0, r3 800c9f6: 370c adds r7, #12 800c9f8: 46bd mov sp, r7 800c9fa: bc80 pop {r7} 800c9fc: 4770 bx lr 0800c9fe : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800c9fe: b580 push {r7, lr} 800ca00: b084 sub sp, #16 800ca02: af00 add r7, sp, #0 800ca04: 6078 str r0, [r7, #4] 800ca06: 460b mov r3, r1 800ca08: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_FAIL; 800ca0a: 2302 movs r3, #2 800ca0c: 73fb strb r3, [r7, #15] if (pdev->pClass != NULL) 800ca0e: 687b ldr r3, [r7, #4] 800ca10: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ca14: 2b00 cmp r3, #0 800ca16: d00c beq.n 800ca32 { /* Set configuration and Start the Class*/ if (pdev->pClass->Init(pdev, cfgidx) == 0U) 800ca18: 687b ldr r3, [r7, #4] 800ca1a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ca1e: 681b ldr r3, [r3, #0] 800ca20: 78fa ldrb r2, [r7, #3] 800ca22: 4611 mov r1, r2 800ca24: 6878 ldr r0, [r7, #4] 800ca26: 4798 blx r3 800ca28: 4603 mov r3, r0 800ca2a: 2b00 cmp r3, #0 800ca2c: d101 bne.n 800ca32 { ret = USBD_OK; 800ca2e: 2300 movs r3, #0 800ca30: 73fb strb r3, [r7, #15] } } return ret; 800ca32: 7bfb ldrb r3, [r7, #15] } 800ca34: 4618 mov r0, r3 800ca36: 3710 adds r7, #16 800ca38: 46bd mov sp, r7 800ca3a: bd80 pop {r7, pc} 0800ca3c : * @param pdev: device instance * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800ca3c: b580 push {r7, lr} 800ca3e: b082 sub sp, #8 800ca40: af00 add r7, sp, #0 800ca42: 6078 str r0, [r7, #4] 800ca44: 460b mov r3, r1 800ca46: 70fb strb r3, [r7, #3] /* Clear configuration and De-initialize the Class process*/ pdev->pClass->DeInit(pdev, cfgidx); 800ca48: 687b ldr r3, [r7, #4] 800ca4a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ca4e: 685b ldr r3, [r3, #4] 800ca50: 78fa ldrb r2, [r7, #3] 800ca52: 4611 mov r1, r2 800ca54: 6878 ldr r0, [r7, #4] 800ca56: 4798 blx r3 return USBD_OK; 800ca58: 2300 movs r3, #0 } 800ca5a: 4618 mov r0, r3 800ca5c: 3708 adds r7, #8 800ca5e: 46bd mov sp, r7 800ca60: bd80 pop {r7, pc} 0800ca62 : * Handle the setup stage * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 800ca62: b580 push {r7, lr} 800ca64: b082 sub sp, #8 800ca66: af00 add r7, sp, #0 800ca68: 6078 str r0, [r7, #4] 800ca6a: 6039 str r1, [r7, #0] USBD_ParseSetupRequest(&pdev->request, psetup); 800ca6c: 687b ldr r3, [r7, #4] 800ca6e: f503 732a add.w r3, r3, #680 @ 0x2a8 800ca72: 6839 ldr r1, [r7, #0] 800ca74: 4618 mov r0, r3 800ca76: f000 fed8 bl 800d82a pdev->ep0_state = USBD_EP0_SETUP; 800ca7a: 687b ldr r3, [r7, #4] 800ca7c: 2201 movs r2, #1 800ca7e: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 800ca82: 687b ldr r3, [r7, #4] 800ca84: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 800ca88: 461a mov r2, r3 800ca8a: 687b ldr r3, [r7, #4] 800ca8c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 800ca90: 687b ldr r3, [r7, #4] 800ca92: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8 800ca96: f003 031f and.w r3, r3, #31 800ca9a: 2b02 cmp r3, #2 800ca9c: d016 beq.n 800cacc 800ca9e: 2b02 cmp r3, #2 800caa0: d81c bhi.n 800cadc 800caa2: 2b00 cmp r3, #0 800caa4: d002 beq.n 800caac 800caa6: 2b01 cmp r3, #1 800caa8: d008 beq.n 800cabc 800caaa: e017 b.n 800cadc { case USB_REQ_RECIPIENT_DEVICE: USBD_StdDevReq(pdev, &pdev->request); 800caac: 687b ldr r3, [r7, #4] 800caae: f503 732a add.w r3, r3, #680 @ 0x2a8 800cab2: 4619 mov r1, r3 800cab4: 6878 ldr r0, [r7, #4] 800cab6: f000 f9cb bl 800ce50 break; 800caba: e01a b.n 800caf2 case USB_REQ_RECIPIENT_INTERFACE: USBD_StdItfReq(pdev, &pdev->request); 800cabc: 687b ldr r3, [r7, #4] 800cabe: f503 732a add.w r3, r3, #680 @ 0x2a8 800cac2: 4619 mov r1, r3 800cac4: 6878 ldr r0, [r7, #4] 800cac6: f000 fa2d bl 800cf24 break; 800caca: e012 b.n 800caf2 case USB_REQ_RECIPIENT_ENDPOINT: USBD_StdEPReq(pdev, &pdev->request); 800cacc: 687b ldr r3, [r7, #4] 800cace: f503 732a add.w r3, r3, #680 @ 0x2a8 800cad2: 4619 mov r1, r3 800cad4: 6878 ldr r0, [r7, #4] 800cad6: f000 fa6d bl 800cfb4 break; 800cada: e00a b.n 800caf2 default: USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 800cadc: 687b ldr r3, [r7, #4] 800cade: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8 800cae2: f023 037f bic.w r3, r3, #127 @ 0x7f 800cae6: b2db uxtb r3, r3 800cae8: 4619 mov r1, r3 800caea: 6878 ldr r0, [r7, #4] 800caec: f001 fbb0 bl 800e250 break; 800caf0: bf00 nop } return USBD_OK; 800caf2: 2300 movs r3, #0 } 800caf4: 4618 mov r0, r3 800caf6: 3708 adds r7, #8 800caf8: 46bd mov sp, r7 800cafa: bd80 pop {r7, pc} 0800cafc : * @param epnum: endpoint index * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 800cafc: b580 push {r7, lr} 800cafe: b086 sub sp, #24 800cb00: af00 add r7, sp, #0 800cb02: 60f8 str r0, [r7, #12] 800cb04: 460b mov r3, r1 800cb06: 607a str r2, [r7, #4] 800cb08: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; if (epnum == 0U) 800cb0a: 7afb ldrb r3, [r7, #11] 800cb0c: 2b00 cmp r3, #0 800cb0e: d14b bne.n 800cba8 { pep = &pdev->ep_out[0]; 800cb10: 68fb ldr r3, [r7, #12] 800cb12: f503 73aa add.w r3, r3, #340 @ 0x154 800cb16: 617b str r3, [r7, #20] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 800cb18: 68fb ldr r3, [r7, #12] 800cb1a: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 800cb1e: 2b03 cmp r3, #3 800cb20: d134 bne.n 800cb8c { if (pep->rem_length > pep->maxpacket) 800cb22: 697b ldr r3, [r7, #20] 800cb24: 68da ldr r2, [r3, #12] 800cb26: 697b ldr r3, [r7, #20] 800cb28: 691b ldr r3, [r3, #16] 800cb2a: 429a cmp r2, r3 800cb2c: d919 bls.n 800cb62 { pep->rem_length -= pep->maxpacket; 800cb2e: 697b ldr r3, [r7, #20] 800cb30: 68da ldr r2, [r3, #12] 800cb32: 697b ldr r3, [r7, #20] 800cb34: 691b ldr r3, [r3, #16] 800cb36: 1ad2 subs r2, r2, r3 800cb38: 697b ldr r3, [r7, #20] 800cb3a: 60da str r2, [r3, #12] USBD_CtlContinueRx(pdev, pdata, (uint16_t)MIN(pep->rem_length, pep->maxpacket)); 800cb3c: 697b ldr r3, [r7, #20] 800cb3e: 68da ldr r2, [r3, #12] 800cb40: 697b ldr r3, [r7, #20] 800cb42: 691b ldr r3, [r3, #16] USBD_CtlContinueRx(pdev, pdata, 800cb44: 429a cmp r2, r3 800cb46: d203 bcs.n 800cb50 (uint16_t)MIN(pep->rem_length, pep->maxpacket)); 800cb48: 697b ldr r3, [r7, #20] 800cb4a: 68db ldr r3, [r3, #12] USBD_CtlContinueRx(pdev, pdata, 800cb4c: b29b uxth r3, r3 800cb4e: e002 b.n 800cb56 (uint16_t)MIN(pep->rem_length, pep->maxpacket)); 800cb50: 697b ldr r3, [r7, #20] 800cb52: 691b ldr r3, [r3, #16] USBD_CtlContinueRx(pdev, pdata, 800cb54: b29b uxth r3, r3 800cb56: 461a mov r2, r3 800cb58: 6879 ldr r1, [r7, #4] 800cb5a: 68f8 ldr r0, [r7, #12] 800cb5c: f000 ff54 bl 800da08 800cb60: e038 b.n 800cbd4 } else { if ((pdev->pClass->EP0_RxReady != NULL) && 800cb62: 68fb ldr r3, [r7, #12] 800cb64: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cb68: 691b ldr r3, [r3, #16] 800cb6a: 2b00 cmp r3, #0 800cb6c: d00a beq.n 800cb84 (pdev->dev_state == USBD_STATE_CONFIGURED)) 800cb6e: 68fb ldr r3, [r7, #12] 800cb70: f893 329c ldrb.w r3, [r3, #668] @ 0x29c if ((pdev->pClass->EP0_RxReady != NULL) && 800cb74: 2b03 cmp r3, #3 800cb76: d105 bne.n 800cb84 { pdev->pClass->EP0_RxReady(pdev); 800cb78: 68fb ldr r3, [r7, #12] 800cb7a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cb7e: 691b ldr r3, [r3, #16] 800cb80: 68f8 ldr r0, [r7, #12] 800cb82: 4798 blx r3 } USBD_CtlSendStatus(pdev); 800cb84: 68f8 ldr r0, [r7, #12] 800cb86: f000 ff51 bl 800da2c 800cb8a: e023 b.n 800cbd4 } } else { if (pdev->ep0_state == USBD_EP0_STATUS_OUT) 800cb8c: 68fb ldr r3, [r7, #12] 800cb8e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 800cb92: 2b05 cmp r3, #5 800cb94: d11e bne.n 800cbd4 { /* * STATUS PHASE completed, update ep0_state to idle */ pdev->ep0_state = USBD_EP0_IDLE; 800cb96: 68fb ldr r3, [r7, #12] 800cb98: 2200 movs r2, #0 800cb9a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 USBD_LL_StallEP(pdev, 0U); 800cb9e: 2100 movs r1, #0 800cba0: 68f8 ldr r0, [r7, #12] 800cba2: f001 fb55 bl 800e250 800cba6: e015 b.n 800cbd4 } } } else if ((pdev->pClass->DataOut != NULL) && 800cba8: 68fb ldr r3, [r7, #12] 800cbaa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cbae: 699b ldr r3, [r3, #24] 800cbb0: 2b00 cmp r3, #0 800cbb2: d00d beq.n 800cbd0 (pdev->dev_state == USBD_STATE_CONFIGURED)) 800cbb4: 68fb ldr r3, [r7, #12] 800cbb6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c else if ((pdev->pClass->DataOut != NULL) && 800cbba: 2b03 cmp r3, #3 800cbbc: d108 bne.n 800cbd0 { pdev->pClass->DataOut(pdev, epnum); 800cbbe: 68fb ldr r3, [r7, #12] 800cbc0: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cbc4: 699b ldr r3, [r3, #24] 800cbc6: 7afa ldrb r2, [r7, #11] 800cbc8: 4611 mov r1, r2 800cbca: 68f8 ldr r0, [r7, #12] 800cbcc: 4798 blx r3 800cbce: e001 b.n 800cbd4 } else { /* should never be in this condition */ return USBD_FAIL; 800cbd0: 2302 movs r3, #2 800cbd2: e000 b.n 800cbd6 } return USBD_OK; 800cbd4: 2300 movs r3, #0 } 800cbd6: 4618 mov r0, r3 800cbd8: 3718 adds r7, #24 800cbda: 46bd mov sp, r7 800cbdc: bd80 pop {r7, pc} 0800cbde : * @param epnum: endpoint index * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 800cbde: b580 push {r7, lr} 800cbe0: b086 sub sp, #24 800cbe2: af00 add r7, sp, #0 800cbe4: 60f8 str r0, [r7, #12] 800cbe6: 460b mov r3, r1 800cbe8: 607a str r2, [r7, #4] 800cbea: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; if (epnum == 0U) 800cbec: 7afb ldrb r3, [r7, #11] 800cbee: 2b00 cmp r3, #0 800cbf0: d17f bne.n 800ccf2 { pep = &pdev->ep_in[0]; 800cbf2: 68fb ldr r3, [r7, #12] 800cbf4: 3314 adds r3, #20 800cbf6: 617b str r3, [r7, #20] if (pdev->ep0_state == USBD_EP0_DATA_IN) 800cbf8: 68fb ldr r3, [r7, #12] 800cbfa: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 800cbfe: 2b02 cmp r3, #2 800cc00: d15c bne.n 800ccbc { if (pep->rem_length > pep->maxpacket) 800cc02: 697b ldr r3, [r7, #20] 800cc04: 68da ldr r2, [r3, #12] 800cc06: 697b ldr r3, [r7, #20] 800cc08: 691b ldr r3, [r3, #16] 800cc0a: 429a cmp r2, r3 800cc0c: d915 bls.n 800cc3a { pep->rem_length -= pep->maxpacket; 800cc0e: 697b ldr r3, [r7, #20] 800cc10: 68da ldr r2, [r3, #12] 800cc12: 697b ldr r3, [r7, #20] 800cc14: 691b ldr r3, [r3, #16] 800cc16: 1ad2 subs r2, r2, r3 800cc18: 697b ldr r3, [r7, #20] 800cc1a: 60da str r2, [r3, #12] USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length); 800cc1c: 697b ldr r3, [r7, #20] 800cc1e: 68db ldr r3, [r3, #12] 800cc20: b29b uxth r3, r3 800cc22: 461a mov r2, r3 800cc24: 6879 ldr r1, [r7, #4] 800cc26: 68f8 ldr r0, [r7, #12] 800cc28: f000 febe bl 800d9a8 /* Prepare endpoint for premature end of transfer */ USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800cc2c: 2300 movs r3, #0 800cc2e: 2200 movs r2, #0 800cc30: 2100 movs r1, #0 800cc32: 68f8 ldr r0, [r7, #12] 800cc34: f001 fbb7 bl 800e3a6 800cc38: e04e b.n 800ccd8 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->total_length % pep->maxpacket == 0U) && 800cc3a: 697b ldr r3, [r7, #20] 800cc3c: 689b ldr r3, [r3, #8] 800cc3e: 697a ldr r2, [r7, #20] 800cc40: 6912 ldr r2, [r2, #16] 800cc42: fbb3 f1f2 udiv r1, r3, r2 800cc46: fb01 f202 mul.w r2, r1, r2 800cc4a: 1a9b subs r3, r3, r2 800cc4c: 2b00 cmp r3, #0 800cc4e: d11c bne.n 800cc8a (pep->total_length >= pep->maxpacket) && 800cc50: 697b ldr r3, [r7, #20] 800cc52: 689a ldr r2, [r3, #8] 800cc54: 697b ldr r3, [r7, #20] 800cc56: 691b ldr r3, [r3, #16] if ((pep->total_length % pep->maxpacket == 0U) && 800cc58: 429a cmp r2, r3 800cc5a: d316 bcc.n 800cc8a (pep->total_length < pdev->ep0_data_len)) 800cc5c: 697b ldr r3, [r7, #20] 800cc5e: 689a ldr r2, [r3, #8] 800cc60: 68fb ldr r3, [r7, #12] 800cc62: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 800cc66: 429a cmp r2, r3 800cc68: d20f bcs.n 800cc8a { USBD_CtlContinueSendData(pdev, NULL, 0U); 800cc6a: 2200 movs r2, #0 800cc6c: 2100 movs r1, #0 800cc6e: 68f8 ldr r0, [r7, #12] 800cc70: f000 fe9a bl 800d9a8 pdev->ep0_data_len = 0U; 800cc74: 68fb ldr r3, [r7, #12] 800cc76: 2200 movs r2, #0 800cc78: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800cc7c: 2300 movs r3, #0 800cc7e: 2200 movs r2, #0 800cc80: 2100 movs r1, #0 800cc82: 68f8 ldr r0, [r7, #12] 800cc84: f001 fb8f bl 800e3a6 800cc88: e026 b.n 800ccd8 } else { if ((pdev->pClass->EP0_TxSent != NULL) && 800cc8a: 68fb ldr r3, [r7, #12] 800cc8c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cc90: 68db ldr r3, [r3, #12] 800cc92: 2b00 cmp r3, #0 800cc94: d00a beq.n 800ccac (pdev->dev_state == USBD_STATE_CONFIGURED)) 800cc96: 68fb ldr r3, [r7, #12] 800cc98: f893 329c ldrb.w r3, [r3, #668] @ 0x29c if ((pdev->pClass->EP0_TxSent != NULL) && 800cc9c: 2b03 cmp r3, #3 800cc9e: d105 bne.n 800ccac { pdev->pClass->EP0_TxSent(pdev); 800cca0: 68fb ldr r3, [r7, #12] 800cca2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cca6: 68db ldr r3, [r3, #12] 800cca8: 68f8 ldr r0, [r7, #12] 800ccaa: 4798 blx r3 } USBD_LL_StallEP(pdev, 0x80U); 800ccac: 2180 movs r1, #128 @ 0x80 800ccae: 68f8 ldr r0, [r7, #12] 800ccb0: f001 face bl 800e250 USBD_CtlReceiveStatus(pdev); 800ccb4: 68f8 ldr r0, [r7, #12] 800ccb6: f000 fecc bl 800da52 800ccba: e00d b.n 800ccd8 } } } else { if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || 800ccbc: 68fb ldr r3, [r7, #12] 800ccbe: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 800ccc2: 2b04 cmp r3, #4 800ccc4: d004 beq.n 800ccd0 (pdev->ep0_state == USBD_EP0_IDLE)) 800ccc6: 68fb ldr r3, [r7, #12] 800ccc8: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || 800cccc: 2b00 cmp r3, #0 800ccce: d103 bne.n 800ccd8 { USBD_LL_StallEP(pdev, 0x80U); 800ccd0: 2180 movs r1, #128 @ 0x80 800ccd2: 68f8 ldr r0, [r7, #12] 800ccd4: f001 fabc bl 800e250 } } if (pdev->dev_test_mode == 1U) 800ccd8: 68fb ldr r3, [r7, #12] 800ccda: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 800ccde: 2b01 cmp r3, #1 800cce0: d11d bne.n 800cd1e { USBD_RunTestMode(pdev); 800cce2: 68f8 ldr r0, [r7, #12] 800cce4: f7ff fe81 bl 800c9ea pdev->dev_test_mode = 0U; 800cce8: 68fb ldr r3, [r7, #12] 800ccea: 2200 movs r2, #0 800ccec: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 800ccf0: e015 b.n 800cd1e } } else if ((pdev->pClass->DataIn != NULL) && 800ccf2: 68fb ldr r3, [r7, #12] 800ccf4: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ccf8: 695b ldr r3, [r3, #20] 800ccfa: 2b00 cmp r3, #0 800ccfc: d00d beq.n 800cd1a (pdev->dev_state == USBD_STATE_CONFIGURED)) 800ccfe: 68fb ldr r3, [r7, #12] 800cd00: f893 329c ldrb.w r3, [r3, #668] @ 0x29c else if ((pdev->pClass->DataIn != NULL) && 800cd04: 2b03 cmp r3, #3 800cd06: d108 bne.n 800cd1a { pdev->pClass->DataIn(pdev, epnum); 800cd08: 68fb ldr r3, [r7, #12] 800cd0a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cd0e: 695b ldr r3, [r3, #20] 800cd10: 7afa ldrb r2, [r7, #11] 800cd12: 4611 mov r1, r2 800cd14: 68f8 ldr r0, [r7, #12] 800cd16: 4798 blx r3 800cd18: e001 b.n 800cd1e } else { /* should never be in this condition */ return USBD_FAIL; 800cd1a: 2302 movs r3, #2 800cd1c: e000 b.n 800cd20 } return USBD_OK; 800cd1e: 2300 movs r3, #0 } 800cd20: 4618 mov r0, r3 800cd22: 3718 adds r7, #24 800cd24: 46bd mov sp, r7 800cd26: bd80 pop {r7, pc} 0800cd28 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 800cd28: b580 push {r7, lr} 800cd2a: b082 sub sp, #8 800cd2c: af00 add r7, sp, #0 800cd2e: 6078 str r0, [r7, #4] /* Open EP0 OUT */ USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 800cd30: 2340 movs r3, #64 @ 0x40 800cd32: 2200 movs r2, #0 800cd34: 2100 movs r1, #0 800cd36: 6878 ldr r0, [r7, #4] 800cd38: f001 fa45 bl 800e1c6 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 800cd3c: 687b ldr r3, [r7, #4] 800cd3e: 2201 movs r2, #1 800cd40: f8c3 2158 str.w r2, [r3, #344] @ 0x158 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 800cd44: 687b ldr r3, [r7, #4] 800cd46: 2240 movs r2, #64 @ 0x40 800cd48: f8c3 2164 str.w r2, [r3, #356] @ 0x164 /* Open EP0 IN */ USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 800cd4c: 2340 movs r3, #64 @ 0x40 800cd4e: 2200 movs r2, #0 800cd50: 2180 movs r1, #128 @ 0x80 800cd52: 6878 ldr r0, [r7, #4] 800cd54: f001 fa37 bl 800e1c6 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 800cd58: 687b ldr r3, [r7, #4] 800cd5a: 2201 movs r2, #1 800cd5c: 619a str r2, [r3, #24] pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 800cd5e: 687b ldr r3, [r7, #4] 800cd60: 2240 movs r2, #64 @ 0x40 800cd62: 625a str r2, [r3, #36] @ 0x24 /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 800cd64: 687b ldr r3, [r7, #4] 800cd66: 2201 movs r2, #1 800cd68: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 800cd6c: 687b ldr r3, [r7, #4] 800cd6e: 2200 movs r2, #0 800cd70: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 800cd74: 687b ldr r3, [r7, #4] 800cd76: 2200 movs r2, #0 800cd78: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 800cd7a: 687b ldr r3, [r7, #4] 800cd7c: 2200 movs r2, #0 800cd7e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 if (pdev->pClassData) 800cd82: 687b ldr r3, [r7, #4] 800cd84: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800cd88: 2b00 cmp r3, #0 800cd8a: d009 beq.n 800cda0 { pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 800cd8c: 687b ldr r3, [r7, #4] 800cd8e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cd92: 685b ldr r3, [r3, #4] 800cd94: 687a ldr r2, [r7, #4] 800cd96: 6852 ldr r2, [r2, #4] 800cd98: b2d2 uxtb r2, r2 800cd9a: 4611 mov r1, r2 800cd9c: 6878 ldr r0, [r7, #4] 800cd9e: 4798 blx r3 } return USBD_OK; 800cda0: 2300 movs r3, #0 } 800cda2: 4618 mov r0, r3 800cda4: 3708 adds r7, #8 800cda6: 46bd mov sp, r7 800cda8: bd80 pop {r7, pc} 0800cdaa : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 800cdaa: b480 push {r7} 800cdac: b083 sub sp, #12 800cdae: af00 add r7, sp, #0 800cdb0: 6078 str r0, [r7, #4] 800cdb2: 460b mov r3, r1 800cdb4: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 800cdb6: 687b ldr r3, [r7, #4] 800cdb8: 78fa ldrb r2, [r7, #3] 800cdba: 741a strb r2, [r3, #16] return USBD_OK; 800cdbc: 2300 movs r3, #0 } 800cdbe: 4618 mov r0, r3 800cdc0: 370c adds r7, #12 800cdc2: 46bd mov sp, r7 800cdc4: bc80 pop {r7} 800cdc6: 4770 bx lr 0800cdc8 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 800cdc8: b480 push {r7} 800cdca: b083 sub sp, #12 800cdcc: af00 add r7, sp, #0 800cdce: 6078 str r0, [r7, #4] pdev->dev_old_state = pdev->dev_state; 800cdd0: 687b ldr r3, [r7, #4] 800cdd2: f893 229c ldrb.w r2, [r3, #668] @ 0x29c 800cdd6: 687b ldr r3, [r7, #4] 800cdd8: f883 229d strb.w r2, [r3, #669] @ 0x29d pdev->dev_state = USBD_STATE_SUSPENDED; 800cddc: 687b ldr r3, [r7, #4] 800cdde: 2204 movs r2, #4 800cde0: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 800cde4: 2300 movs r3, #0 } 800cde6: 4618 mov r0, r3 800cde8: 370c adds r7, #12 800cdea: 46bd mov sp, r7 800cdec: bc80 pop {r7} 800cdee: 4770 bx lr 0800cdf0 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 800cdf0: b480 push {r7} 800cdf2: b083 sub sp, #12 800cdf4: af00 add r7, sp, #0 800cdf6: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 800cdf8: 687b ldr r3, [r7, #4] 800cdfa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800cdfe: 2b04 cmp r3, #4 800ce00: d105 bne.n 800ce0e { pdev->dev_state = pdev->dev_old_state; 800ce02: 687b ldr r3, [r7, #4] 800ce04: f893 229d ldrb.w r2, [r3, #669] @ 0x29d 800ce08: 687b ldr r3, [r7, #4] 800ce0a: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 800ce0e: 2300 movs r3, #0 } 800ce10: 4618 mov r0, r3 800ce12: 370c adds r7, #12 800ce14: 46bd mov sp, r7 800ce16: bc80 pop {r7} 800ce18: 4770 bx lr 0800ce1a : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 800ce1a: b580 push {r7, lr} 800ce1c: b082 sub sp, #8 800ce1e: af00 add r7, sp, #0 800ce20: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_CONFIGURED) 800ce22: 687b ldr r3, [r7, #4] 800ce24: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800ce28: 2b03 cmp r3, #3 800ce2a: d10b bne.n 800ce44 { if (pdev->pClass->SOF != NULL) 800ce2c: 687b ldr r3, [r7, #4] 800ce2e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ce32: 69db ldr r3, [r3, #28] 800ce34: 2b00 cmp r3, #0 800ce36: d005 beq.n 800ce44 { pdev->pClass->SOF(pdev); 800ce38: 687b ldr r3, [r7, #4] 800ce3a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ce3e: 69db ldr r3, [r3, #28] 800ce40: 6878 ldr r0, [r7, #4] 800ce42: 4798 blx r3 } } return USBD_OK; 800ce44: 2300 movs r3, #0 } 800ce46: 4618 mov r0, r3 800ce48: 3708 adds r7, #8 800ce4a: 46bd mov sp, r7 800ce4c: bd80 pop {r7, pc} ... 0800ce50 : * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800ce50: b580 push {r7, lr} 800ce52: b084 sub sp, #16 800ce54: af00 add r7, sp, #0 800ce56: 6078 str r0, [r7, #4] 800ce58: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800ce5a: 2300 movs r3, #0 800ce5c: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800ce5e: 683b ldr r3, [r7, #0] 800ce60: 781b ldrb r3, [r3, #0] 800ce62: f003 0360 and.w r3, r3, #96 @ 0x60 800ce66: 2b40 cmp r3, #64 @ 0x40 800ce68: d005 beq.n 800ce76 800ce6a: 2b40 cmp r3, #64 @ 0x40 800ce6c: d84f bhi.n 800cf0e 800ce6e: 2b00 cmp r3, #0 800ce70: d009 beq.n 800ce86 800ce72: 2b20 cmp r3, #32 800ce74: d14b bne.n 800cf0e { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: pdev->pClass->Setup(pdev, req); 800ce76: 687b ldr r3, [r7, #4] 800ce78: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800ce7c: 689b ldr r3, [r3, #8] 800ce7e: 6839 ldr r1, [r7, #0] 800ce80: 6878 ldr r0, [r7, #4] 800ce82: 4798 blx r3 break; 800ce84: e048 b.n 800cf18 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800ce86: 683b ldr r3, [r7, #0] 800ce88: 785b ldrb r3, [r3, #1] 800ce8a: 2b09 cmp r3, #9 800ce8c: d839 bhi.n 800cf02 800ce8e: a201 add r2, pc, #4 @ (adr r2, 800ce94 ) 800ce90: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ce94: 0800cee5 .word 0x0800cee5 800ce98: 0800cef9 .word 0x0800cef9 800ce9c: 0800cf03 .word 0x0800cf03 800cea0: 0800ceef .word 0x0800ceef 800cea4: 0800cf03 .word 0x0800cf03 800cea8: 0800cec7 .word 0x0800cec7 800ceac: 0800cebd .word 0x0800cebd 800ceb0: 0800cf03 .word 0x0800cf03 800ceb4: 0800cedb .word 0x0800cedb 800ceb8: 0800ced1 .word 0x0800ced1 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 800cebc: 6839 ldr r1, [r7, #0] 800cebe: 6878 ldr r0, [r7, #4] 800cec0: f000 f9dc bl 800d27c break; 800cec4: e022 b.n 800cf0c case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 800cec6: 6839 ldr r1, [r7, #0] 800cec8: 6878 ldr r0, [r7, #4] 800ceca: f000 fb3f bl 800d54c break; 800cece: e01d b.n 800cf0c case USB_REQ_SET_CONFIGURATION: USBD_SetConfig(pdev, req); 800ced0: 6839 ldr r1, [r7, #0] 800ced2: 6878 ldr r0, [r7, #4] 800ced4: f000 fb7e bl 800d5d4 break; 800ced8: e018 b.n 800cf0c case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 800ceda: 6839 ldr r1, [r7, #0] 800cedc: 6878 ldr r0, [r7, #4] 800cede: f000 fc07 bl 800d6f0 break; 800cee2: e013 b.n 800cf0c case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 800cee4: 6839 ldr r1, [r7, #0] 800cee6: 6878 ldr r0, [r7, #4] 800cee8: f000 fc37 bl 800d75a break; 800ceec: e00e b.n 800cf0c case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 800ceee: 6839 ldr r1, [r7, #0] 800cef0: 6878 ldr r0, [r7, #4] 800cef2: f000 fc65 bl 800d7c0 break; 800cef6: e009 b.n 800cf0c case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 800cef8: 6839 ldr r1, [r7, #0] 800cefa: 6878 ldr r0, [r7, #4] 800cefc: f000 fc74 bl 800d7e8 break; 800cf00: e004 b.n 800cf0c default: USBD_CtlError(pdev, req); 800cf02: 6839 ldr r1, [r7, #0] 800cf04: 6878 ldr r0, [r7, #4] 800cf06: f000 fcc9 bl 800d89c break; 800cf0a: bf00 nop } break; 800cf0c: e004 b.n 800cf18 default: USBD_CtlError(pdev, req); 800cf0e: 6839 ldr r1, [r7, #0] 800cf10: 6878 ldr r0, [r7, #4] 800cf12: f000 fcc3 bl 800d89c break; 800cf16: bf00 nop } return ret; 800cf18: 7bfb ldrb r3, [r7, #15] } 800cf1a: 4618 mov r0, r3 800cf1c: 3710 adds r7, #16 800cf1e: 46bd mov sp, r7 800cf20: bd80 pop {r7, pc} 800cf22: bf00 nop 0800cf24 : * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800cf24: b580 push {r7, lr} 800cf26: b084 sub sp, #16 800cf28: af00 add r7, sp, #0 800cf2a: 6078 str r0, [r7, #4] 800cf2c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800cf2e: 2300 movs r3, #0 800cf30: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800cf32: 683b ldr r3, [r7, #0] 800cf34: 781b ldrb r3, [r3, #0] 800cf36: f003 0360 and.w r3, r3, #96 @ 0x60 800cf3a: 2b40 cmp r3, #64 @ 0x40 800cf3c: d005 beq.n 800cf4a 800cf3e: 2b40 cmp r3, #64 @ 0x40 800cf40: d82e bhi.n 800cfa0 800cf42: 2b00 cmp r3, #0 800cf44: d001 beq.n 800cf4a 800cf46: 2b20 cmp r3, #32 800cf48: d12a bne.n 800cfa0 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800cf4a: 687b ldr r3, [r7, #4] 800cf4c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800cf50: 3b01 subs r3, #1 800cf52: 2b02 cmp r3, #2 800cf54: d81d bhi.n 800cf92 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 800cf56: 683b ldr r3, [r7, #0] 800cf58: 889b ldrh r3, [r3, #4] 800cf5a: b2db uxtb r3, r3 800cf5c: 2b01 cmp r3, #1 800cf5e: d813 bhi.n 800cf88 { ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 800cf60: 687b ldr r3, [r7, #4] 800cf62: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cf66: 689b ldr r3, [r3, #8] 800cf68: 6839 ldr r1, [r7, #0] 800cf6a: 6878 ldr r0, [r7, #4] 800cf6c: 4798 blx r3 800cf6e: 4603 mov r3, r0 800cf70: 73fb strb r3, [r7, #15] if ((req->wLength == 0U) && (ret == USBD_OK)) 800cf72: 683b ldr r3, [r7, #0] 800cf74: 88db ldrh r3, [r3, #6] 800cf76: 2b00 cmp r3, #0 800cf78: d110 bne.n 800cf9c 800cf7a: 7bfb ldrb r3, [r7, #15] 800cf7c: 2b00 cmp r3, #0 800cf7e: d10d bne.n 800cf9c { USBD_CtlSendStatus(pdev); 800cf80: 6878 ldr r0, [r7, #4] 800cf82: f000 fd53 bl 800da2c } else { USBD_CtlError(pdev, req); } break; 800cf86: e009 b.n 800cf9c USBD_CtlError(pdev, req); 800cf88: 6839 ldr r1, [r7, #0] 800cf8a: 6878 ldr r0, [r7, #4] 800cf8c: f000 fc86 bl 800d89c break; 800cf90: e004 b.n 800cf9c default: USBD_CtlError(pdev, req); 800cf92: 6839 ldr r1, [r7, #0] 800cf94: 6878 ldr r0, [r7, #4] 800cf96: f000 fc81 bl 800d89c break; 800cf9a: e000 b.n 800cf9e break; 800cf9c: bf00 nop } break; 800cf9e: e004 b.n 800cfaa default: USBD_CtlError(pdev, req); 800cfa0: 6839 ldr r1, [r7, #0] 800cfa2: 6878 ldr r0, [r7, #4] 800cfa4: f000 fc7a bl 800d89c break; 800cfa8: bf00 nop } return USBD_OK; 800cfaa: 2300 movs r3, #0 } 800cfac: 4618 mov r0, r3 800cfae: 3710 adds r7, #16 800cfb0: 46bd mov sp, r7 800cfb2: bd80 pop {r7, pc} 0800cfb4 : * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800cfb4: b580 push {r7, lr} 800cfb6: b084 sub sp, #16 800cfb8: af00 add r7, sp, #0 800cfba: 6078 str r0, [r7, #4] 800cfbc: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; USBD_StatusTypeDef ret = USBD_OK; 800cfbe: 2300 movs r3, #0 800cfc0: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 800cfc2: 683b ldr r3, [r7, #0] 800cfc4: 889b ldrh r3, [r3, #4] 800cfc6: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800cfc8: 683b ldr r3, [r7, #0] 800cfca: 781b ldrb r3, [r3, #0] 800cfcc: f003 0360 and.w r3, r3, #96 @ 0x60 800cfd0: 2b40 cmp r3, #64 @ 0x40 800cfd2: d007 beq.n 800cfe4 800cfd4: 2b40 cmp r3, #64 @ 0x40 800cfd6: f200 8146 bhi.w 800d266 800cfda: 2b00 cmp r3, #0 800cfdc: d00a beq.n 800cff4 800cfde: 2b20 cmp r3, #32 800cfe0: f040 8141 bne.w 800d266 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: pdev->pClass->Setup(pdev, req); 800cfe4: 687b ldr r3, [r7, #4] 800cfe6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800cfea: 689b ldr r3, [r3, #8] 800cfec: 6839 ldr r1, [r7, #0] 800cfee: 6878 ldr r0, [r7, #4] 800cff0: 4798 blx r3 break; 800cff2: e13d b.n 800d270 case USB_REQ_TYPE_STANDARD: /* Check if it is a class request */ if ((req->bmRequest & 0x60U) == 0x20U) 800cff4: 683b ldr r3, [r7, #0] 800cff6: 781b ldrb r3, [r3, #0] 800cff8: f003 0360 and.w r3, r3, #96 @ 0x60 800cffc: 2b20 cmp r3, #32 800cffe: d10a bne.n 800d016 { ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 800d000: 687b ldr r3, [r7, #4] 800d002: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800d006: 689b ldr r3, [r3, #8] 800d008: 6839 ldr r1, [r7, #0] 800d00a: 6878 ldr r0, [r7, #4] 800d00c: 4798 blx r3 800d00e: 4603 mov r3, r0 800d010: 73fb strb r3, [r7, #15] return ret; 800d012: 7bfb ldrb r3, [r7, #15] 800d014: e12d b.n 800d272 } switch (req->bRequest) 800d016: 683b ldr r3, [r7, #0] 800d018: 785b ldrb r3, [r3, #1] 800d01a: 2b03 cmp r3, #3 800d01c: d007 beq.n 800d02e 800d01e: 2b03 cmp r3, #3 800d020: f300 811b bgt.w 800d25a 800d024: 2b00 cmp r3, #0 800d026: d072 beq.n 800d10e 800d028: 2b01 cmp r3, #1 800d02a: d03a beq.n 800d0a2 800d02c: e115 b.n 800d25a { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 800d02e: 687b ldr r3, [r7, #4] 800d030: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d034: 2b02 cmp r3, #2 800d036: d002 beq.n 800d03e 800d038: 2b03 cmp r3, #3 800d03a: d015 beq.n 800d068 800d03c: e02b b.n 800d096 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800d03e: 7bbb ldrb r3, [r7, #14] 800d040: 2b00 cmp r3, #0 800d042: d00c beq.n 800d05e 800d044: 7bbb ldrb r3, [r7, #14] 800d046: 2b80 cmp r3, #128 @ 0x80 800d048: d009 beq.n 800d05e { USBD_LL_StallEP(pdev, ep_addr); 800d04a: 7bbb ldrb r3, [r7, #14] 800d04c: 4619 mov r1, r3 800d04e: 6878 ldr r0, [r7, #4] 800d050: f001 f8fe bl 800e250 USBD_LL_StallEP(pdev, 0x80U); 800d054: 2180 movs r1, #128 @ 0x80 800d056: 6878 ldr r0, [r7, #4] 800d058: f001 f8fa bl 800e250 } else { USBD_CtlError(pdev, req); } break; 800d05c: e020 b.n 800d0a0 USBD_CtlError(pdev, req); 800d05e: 6839 ldr r1, [r7, #0] 800d060: 6878 ldr r0, [r7, #4] 800d062: f000 fc1b bl 800d89c break; 800d066: e01b b.n 800d0a0 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800d068: 683b ldr r3, [r7, #0] 800d06a: 885b ldrh r3, [r3, #2] 800d06c: 2b00 cmp r3, #0 800d06e: d10e bne.n 800d08e { if ((ep_addr != 0x00U) && 800d070: 7bbb ldrb r3, [r7, #14] 800d072: 2b00 cmp r3, #0 800d074: d00b beq.n 800d08e 800d076: 7bbb ldrb r3, [r7, #14] 800d078: 2b80 cmp r3, #128 @ 0x80 800d07a: d008 beq.n 800d08e (ep_addr != 0x80U) && (req->wLength == 0x00U)) 800d07c: 683b ldr r3, [r7, #0] 800d07e: 88db ldrh r3, [r3, #6] 800d080: 2b00 cmp r3, #0 800d082: d104 bne.n 800d08e { USBD_LL_StallEP(pdev, ep_addr); 800d084: 7bbb ldrb r3, [r7, #14] 800d086: 4619 mov r1, r3 800d088: 6878 ldr r0, [r7, #4] 800d08a: f001 f8e1 bl 800e250 } } USBD_CtlSendStatus(pdev); 800d08e: 6878 ldr r0, [r7, #4] 800d090: f000 fccc bl 800da2c break; 800d094: e004 b.n 800d0a0 default: USBD_CtlError(pdev, req); 800d096: 6839 ldr r1, [r7, #0] 800d098: 6878 ldr r0, [r7, #4] 800d09a: f000 fbff bl 800d89c break; 800d09e: bf00 nop } break; 800d0a0: e0e0 b.n 800d264 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 800d0a2: 687b ldr r3, [r7, #4] 800d0a4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d0a8: 2b02 cmp r3, #2 800d0aa: d002 beq.n 800d0b2 800d0ac: 2b03 cmp r3, #3 800d0ae: d015 beq.n 800d0dc 800d0b0: e026 b.n 800d100 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800d0b2: 7bbb ldrb r3, [r7, #14] 800d0b4: 2b00 cmp r3, #0 800d0b6: d00c beq.n 800d0d2 800d0b8: 7bbb ldrb r3, [r7, #14] 800d0ba: 2b80 cmp r3, #128 @ 0x80 800d0bc: d009 beq.n 800d0d2 { USBD_LL_StallEP(pdev, ep_addr); 800d0be: 7bbb ldrb r3, [r7, #14] 800d0c0: 4619 mov r1, r3 800d0c2: 6878 ldr r0, [r7, #4] 800d0c4: f001 f8c4 bl 800e250 USBD_LL_StallEP(pdev, 0x80U); 800d0c8: 2180 movs r1, #128 @ 0x80 800d0ca: 6878 ldr r0, [r7, #4] 800d0cc: f001 f8c0 bl 800e250 } else { USBD_CtlError(pdev, req); } break; 800d0d0: e01c b.n 800d10c USBD_CtlError(pdev, req); 800d0d2: 6839 ldr r1, [r7, #0] 800d0d4: 6878 ldr r0, [r7, #4] 800d0d6: f000 fbe1 bl 800d89c break; 800d0da: e017 b.n 800d10c case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800d0dc: 683b ldr r3, [r7, #0] 800d0de: 885b ldrh r3, [r3, #2] 800d0e0: 2b00 cmp r3, #0 800d0e2: d112 bne.n 800d10a { if ((ep_addr & 0x7FU) != 0x00U) 800d0e4: 7bbb ldrb r3, [r7, #14] 800d0e6: f003 037f and.w r3, r3, #127 @ 0x7f 800d0ea: 2b00 cmp r3, #0 800d0ec: d004 beq.n 800d0f8 { USBD_LL_ClearStallEP(pdev, ep_addr); 800d0ee: 7bbb ldrb r3, [r7, #14] 800d0f0: 4619 mov r1, r3 800d0f2: 6878 ldr r0, [r7, #4] 800d0f4: f001 f8cb bl 800e28e } USBD_CtlSendStatus(pdev); 800d0f8: 6878 ldr r0, [r7, #4] 800d0fa: f000 fc97 bl 800da2c } break; 800d0fe: e004 b.n 800d10a default: USBD_CtlError(pdev, req); 800d100: 6839 ldr r1, [r7, #0] 800d102: 6878 ldr r0, [r7, #4] 800d104: f000 fbca bl 800d89c break; 800d108: e000 b.n 800d10c break; 800d10a: bf00 nop } break; 800d10c: e0aa b.n 800d264 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 800d10e: 687b ldr r3, [r7, #4] 800d110: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d114: 2b02 cmp r3, #2 800d116: d002 beq.n 800d11e 800d118: 2b03 cmp r3, #3 800d11a: d032 beq.n 800d182 800d11c: e097 b.n 800d24e { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800d11e: 7bbb ldrb r3, [r7, #14] 800d120: 2b00 cmp r3, #0 800d122: d007 beq.n 800d134 800d124: 7bbb ldrb r3, [r7, #14] 800d126: 2b80 cmp r3, #128 @ 0x80 800d128: d004 beq.n 800d134 { USBD_CtlError(pdev, req); 800d12a: 6839 ldr r1, [r7, #0] 800d12c: 6878 ldr r0, [r7, #4] 800d12e: f000 fbb5 bl 800d89c break; 800d132: e091 b.n 800d258 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800d134: f997 300e ldrsb.w r3, [r7, #14] 800d138: 2b00 cmp r3, #0 800d13a: da0b bge.n 800d154 800d13c: 7bbb ldrb r3, [r7, #14] 800d13e: f003 027f and.w r2, r3, #127 @ 0x7f 800d142: 4613 mov r3, r2 800d144: 009b lsls r3, r3, #2 800d146: 4413 add r3, r2 800d148: 009b lsls r3, r3, #2 800d14a: 3310 adds r3, #16 800d14c: 687a ldr r2, [r7, #4] 800d14e: 4413 add r3, r2 800d150: 3304 adds r3, #4 800d152: e00b b.n 800d16c &pdev->ep_out[ep_addr & 0x7FU]; 800d154: 7bbb ldrb r3, [r7, #14] 800d156: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800d15a: 4613 mov r3, r2 800d15c: 009b lsls r3, r3, #2 800d15e: 4413 add r3, r2 800d160: 009b lsls r3, r3, #2 800d162: f503 73a8 add.w r3, r3, #336 @ 0x150 800d166: 687a ldr r2, [r7, #4] 800d168: 4413 add r3, r2 800d16a: 3304 adds r3, #4 800d16c: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800d16e: 68bb ldr r3, [r7, #8] 800d170: 2200 movs r2, #0 800d172: 601a str r2, [r3, #0] USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); 800d174: 68bb ldr r3, [r7, #8] 800d176: 2202 movs r2, #2 800d178: 4619 mov r1, r3 800d17a: 6878 ldr r0, [r7, #4] 800d17c: f000 fbf8 bl 800d970 break; 800d180: e06a b.n 800d258 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800d182: f997 300e ldrsb.w r3, [r7, #14] 800d186: 2b00 cmp r3, #0 800d188: da11 bge.n 800d1ae { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800d18a: 7bbb ldrb r3, [r7, #14] 800d18c: f003 020f and.w r2, r3, #15 800d190: 6879 ldr r1, [r7, #4] 800d192: 4613 mov r3, r2 800d194: 009b lsls r3, r3, #2 800d196: 4413 add r3, r2 800d198: 009b lsls r3, r3, #2 800d19a: 440b add r3, r1 800d19c: 3318 adds r3, #24 800d19e: 681b ldr r3, [r3, #0] 800d1a0: 2b00 cmp r3, #0 800d1a2: d117 bne.n 800d1d4 { USBD_CtlError(pdev, req); 800d1a4: 6839 ldr r1, [r7, #0] 800d1a6: 6878 ldr r0, [r7, #4] 800d1a8: f000 fb78 bl 800d89c break; 800d1ac: e054 b.n 800d258 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800d1ae: 7bbb ldrb r3, [r7, #14] 800d1b0: f003 020f and.w r2, r3, #15 800d1b4: 6879 ldr r1, [r7, #4] 800d1b6: 4613 mov r3, r2 800d1b8: 009b lsls r3, r3, #2 800d1ba: 4413 add r3, r2 800d1bc: 009b lsls r3, r3, #2 800d1be: 440b add r3, r1 800d1c0: f503 73ac add.w r3, r3, #344 @ 0x158 800d1c4: 681b ldr r3, [r3, #0] 800d1c6: 2b00 cmp r3, #0 800d1c8: d104 bne.n 800d1d4 { USBD_CtlError(pdev, req); 800d1ca: 6839 ldr r1, [r7, #0] 800d1cc: 6878 ldr r0, [r7, #4] 800d1ce: f000 fb65 bl 800d89c break; 800d1d2: e041 b.n 800d258 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800d1d4: f997 300e ldrsb.w r3, [r7, #14] 800d1d8: 2b00 cmp r3, #0 800d1da: da0b bge.n 800d1f4 800d1dc: 7bbb ldrb r3, [r7, #14] 800d1de: f003 027f and.w r2, r3, #127 @ 0x7f 800d1e2: 4613 mov r3, r2 800d1e4: 009b lsls r3, r3, #2 800d1e6: 4413 add r3, r2 800d1e8: 009b lsls r3, r3, #2 800d1ea: 3310 adds r3, #16 800d1ec: 687a ldr r2, [r7, #4] 800d1ee: 4413 add r3, r2 800d1f0: 3304 adds r3, #4 800d1f2: e00b b.n 800d20c &pdev->ep_out[ep_addr & 0x7FU]; 800d1f4: 7bbb ldrb r3, [r7, #14] 800d1f6: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800d1fa: 4613 mov r3, r2 800d1fc: 009b lsls r3, r3, #2 800d1fe: 4413 add r3, r2 800d200: 009b lsls r3, r3, #2 800d202: f503 73a8 add.w r3, r3, #336 @ 0x150 800d206: 687a ldr r2, [r7, #4] 800d208: 4413 add r3, r2 800d20a: 3304 adds r3, #4 800d20c: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 800d20e: 7bbb ldrb r3, [r7, #14] 800d210: 2b00 cmp r3, #0 800d212: d002 beq.n 800d21a 800d214: 7bbb ldrb r3, [r7, #14] 800d216: 2b80 cmp r3, #128 @ 0x80 800d218: d103 bne.n 800d222 { pep->status = 0x0000U; 800d21a: 68bb ldr r3, [r7, #8] 800d21c: 2200 movs r2, #0 800d21e: 601a str r2, [r3, #0] 800d220: e00e b.n 800d240 } else if (USBD_LL_IsStallEP(pdev, ep_addr)) 800d222: 7bbb ldrb r3, [r7, #14] 800d224: 4619 mov r1, r3 800d226: 6878 ldr r0, [r7, #4] 800d228: f001 f850 bl 800e2cc 800d22c: 4603 mov r3, r0 800d22e: 2b00 cmp r3, #0 800d230: d003 beq.n 800d23a { pep->status = 0x0001U; 800d232: 68bb ldr r3, [r7, #8] 800d234: 2201 movs r2, #1 800d236: 601a str r2, [r3, #0] 800d238: e002 b.n 800d240 } else { pep->status = 0x0000U; 800d23a: 68bb ldr r3, [r7, #8] 800d23c: 2200 movs r2, #0 800d23e: 601a str r2, [r3, #0] } USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); 800d240: 68bb ldr r3, [r7, #8] 800d242: 2202 movs r2, #2 800d244: 4619 mov r1, r3 800d246: 6878 ldr r0, [r7, #4] 800d248: f000 fb92 bl 800d970 break; 800d24c: e004 b.n 800d258 default: USBD_CtlError(pdev, req); 800d24e: 6839 ldr r1, [r7, #0] 800d250: 6878 ldr r0, [r7, #4] 800d252: f000 fb23 bl 800d89c break; 800d256: bf00 nop } break; 800d258: e004 b.n 800d264 default: USBD_CtlError(pdev, req); 800d25a: 6839 ldr r1, [r7, #0] 800d25c: 6878 ldr r0, [r7, #4] 800d25e: f000 fb1d bl 800d89c break; 800d262: bf00 nop } break; 800d264: e004 b.n 800d270 default: USBD_CtlError(pdev, req); 800d266: 6839 ldr r1, [r7, #0] 800d268: 6878 ldr r0, [r7, #4] 800d26a: f000 fb17 bl 800d89c break; 800d26e: bf00 nop } return ret; 800d270: 7bfb ldrb r3, [r7, #15] } 800d272: 4618 mov r0, r3 800d274: 3710 adds r7, #16 800d276: 46bd mov sp, r7 800d278: bd80 pop {r7, pc} ... 0800d27c : * @param req: usb request * @retval status */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d27c: b580 push {r7, lr} 800d27e: b084 sub sp, #16 800d280: af00 add r7, sp, #0 800d282: 6078 str r0, [r7, #4] 800d284: 6039 str r1, [r7, #0] uint16_t len = 0U; 800d286: 2300 movs r3, #0 800d288: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800d28a: 2300 movs r3, #0 800d28c: 60fb str r3, [r7, #12] uint8_t err = 0U; 800d28e: 2300 movs r3, #0 800d290: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800d292: 683b ldr r3, [r7, #0] 800d294: 885b ldrh r3, [r3, #2] 800d296: 0a1b lsrs r3, r3, #8 800d298: b29b uxth r3, r3 800d29a: 3b01 subs r3, #1 800d29c: 2b06 cmp r3, #6 800d29e: f200 8128 bhi.w 800d4f2 800d2a2: a201 add r2, pc, #4 @ (adr r2, 800d2a8 ) 800d2a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d2a8: 0800d2c5 .word 0x0800d2c5 800d2ac: 0800d2dd .word 0x0800d2dd 800d2b0: 0800d31d .word 0x0800d31d 800d2b4: 0800d4f3 .word 0x0800d4f3 800d2b8: 0800d4f3 .word 0x0800d4f3 800d2bc: 0800d493 .word 0x0800d493 800d2c0: 0800d4bf .word 0x0800d4bf err++; } break; #endif case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 800d2c4: 687b ldr r3, [r7, #4] 800d2c6: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d2ca: 681b ldr r3, [r3, #0] 800d2cc: 687a ldr r2, [r7, #4] 800d2ce: 7c12 ldrb r2, [r2, #16] 800d2d0: f107 0108 add.w r1, r7, #8 800d2d4: 4610 mov r0, r2 800d2d6: 4798 blx r3 800d2d8: 60f8 str r0, [r7, #12] break; 800d2da: e112 b.n 800d502 case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800d2dc: 687b ldr r3, [r7, #4] 800d2de: 7c1b ldrb r3, [r3, #16] 800d2e0: 2b00 cmp r3, #0 800d2e2: d10d bne.n 800d300 { pbuf = pdev->pClass->GetHSConfigDescriptor(&len); 800d2e4: 687b ldr r3, [r7, #4] 800d2e6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800d2ea: 6a9b ldr r3, [r3, #40] @ 0x28 800d2ec: f107 0208 add.w r2, r7, #8 800d2f0: 4610 mov r0, r2 800d2f2: 4798 blx r3 800d2f4: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800d2f6: 68fb ldr r3, [r7, #12] 800d2f8: 3301 adds r3, #1 800d2fa: 2202 movs r2, #2 800d2fc: 701a strb r2, [r3, #0] else { pbuf = pdev->pClass->GetFSConfigDescriptor(&len); pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 800d2fe: e100 b.n 800d502 pbuf = pdev->pClass->GetFSConfigDescriptor(&len); 800d300: 687b ldr r3, [r7, #4] 800d302: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800d306: 6adb ldr r3, [r3, #44] @ 0x2c 800d308: f107 0208 add.w r2, r7, #8 800d30c: 4610 mov r0, r2 800d30e: 4798 blx r3 800d310: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800d312: 68fb ldr r3, [r7, #12] 800d314: 3301 adds r3, #1 800d316: 2202 movs r2, #2 800d318: 701a strb r2, [r3, #0] break; 800d31a: e0f2 b.n 800d502 case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 800d31c: 683b ldr r3, [r7, #0] 800d31e: 885b ldrh r3, [r3, #2] 800d320: b2db uxtb r3, r3 800d322: 2b05 cmp r3, #5 800d324: f200 80ac bhi.w 800d480 800d328: a201 add r2, pc, #4 @ (adr r2, 800d330 ) 800d32a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d32e: bf00 nop 800d330: 0800d349 .word 0x0800d349 800d334: 0800d37d .word 0x0800d37d 800d338: 0800d3b1 .word 0x0800d3b1 800d33c: 0800d3e5 .word 0x0800d3e5 800d340: 0800d419 .word 0x0800d419 800d344: 0800d44d .word 0x0800d44d { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 800d348: 687b ldr r3, [r7, #4] 800d34a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d34e: 685b ldr r3, [r3, #4] 800d350: 2b00 cmp r3, #0 800d352: d00b beq.n 800d36c { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 800d354: 687b ldr r3, [r7, #4] 800d356: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d35a: 685b ldr r3, [r3, #4] 800d35c: 687a ldr r2, [r7, #4] 800d35e: 7c12 ldrb r2, [r2, #16] 800d360: f107 0108 add.w r1, r7, #8 800d364: 4610 mov r0, r2 800d366: 4798 blx r3 800d368: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d36a: e091 b.n 800d490 USBD_CtlError(pdev, req); 800d36c: 6839 ldr r1, [r7, #0] 800d36e: 6878 ldr r0, [r7, #4] 800d370: f000 fa94 bl 800d89c err++; 800d374: 7afb ldrb r3, [r7, #11] 800d376: 3301 adds r3, #1 800d378: 72fb strb r3, [r7, #11] break; 800d37a: e089 b.n 800d490 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 800d37c: 687b ldr r3, [r7, #4] 800d37e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d382: 689b ldr r3, [r3, #8] 800d384: 2b00 cmp r3, #0 800d386: d00b beq.n 800d3a0 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 800d388: 687b ldr r3, [r7, #4] 800d38a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d38e: 689b ldr r3, [r3, #8] 800d390: 687a ldr r2, [r7, #4] 800d392: 7c12 ldrb r2, [r2, #16] 800d394: f107 0108 add.w r1, r7, #8 800d398: 4610 mov r0, r2 800d39a: 4798 blx r3 800d39c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d39e: e077 b.n 800d490 USBD_CtlError(pdev, req); 800d3a0: 6839 ldr r1, [r7, #0] 800d3a2: 6878 ldr r0, [r7, #4] 800d3a4: f000 fa7a bl 800d89c err++; 800d3a8: 7afb ldrb r3, [r7, #11] 800d3aa: 3301 adds r3, #1 800d3ac: 72fb strb r3, [r7, #11] break; 800d3ae: e06f b.n 800d490 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 800d3b0: 687b ldr r3, [r7, #4] 800d3b2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d3b6: 68db ldr r3, [r3, #12] 800d3b8: 2b00 cmp r3, #0 800d3ba: d00b beq.n 800d3d4 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 800d3bc: 687b ldr r3, [r7, #4] 800d3be: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d3c2: 68db ldr r3, [r3, #12] 800d3c4: 687a ldr r2, [r7, #4] 800d3c6: 7c12 ldrb r2, [r2, #16] 800d3c8: f107 0108 add.w r1, r7, #8 800d3cc: 4610 mov r0, r2 800d3ce: 4798 blx r3 800d3d0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d3d2: e05d b.n 800d490 USBD_CtlError(pdev, req); 800d3d4: 6839 ldr r1, [r7, #0] 800d3d6: 6878 ldr r0, [r7, #4] 800d3d8: f000 fa60 bl 800d89c err++; 800d3dc: 7afb ldrb r3, [r7, #11] 800d3de: 3301 adds r3, #1 800d3e0: 72fb strb r3, [r7, #11] break; 800d3e2: e055 b.n 800d490 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 800d3e4: 687b ldr r3, [r7, #4] 800d3e6: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d3ea: 691b ldr r3, [r3, #16] 800d3ec: 2b00 cmp r3, #0 800d3ee: d00b beq.n 800d408 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 800d3f0: 687b ldr r3, [r7, #4] 800d3f2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d3f6: 691b ldr r3, [r3, #16] 800d3f8: 687a ldr r2, [r7, #4] 800d3fa: 7c12 ldrb r2, [r2, #16] 800d3fc: f107 0108 add.w r1, r7, #8 800d400: 4610 mov r0, r2 800d402: 4798 blx r3 800d404: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d406: e043 b.n 800d490 USBD_CtlError(pdev, req); 800d408: 6839 ldr r1, [r7, #0] 800d40a: 6878 ldr r0, [r7, #4] 800d40c: f000 fa46 bl 800d89c err++; 800d410: 7afb ldrb r3, [r7, #11] 800d412: 3301 adds r3, #1 800d414: 72fb strb r3, [r7, #11] break; 800d416: e03b b.n 800d490 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 800d418: 687b ldr r3, [r7, #4] 800d41a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d41e: 695b ldr r3, [r3, #20] 800d420: 2b00 cmp r3, #0 800d422: d00b beq.n 800d43c { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 800d424: 687b ldr r3, [r7, #4] 800d426: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d42a: 695b ldr r3, [r3, #20] 800d42c: 687a ldr r2, [r7, #4] 800d42e: 7c12 ldrb r2, [r2, #16] 800d430: f107 0108 add.w r1, r7, #8 800d434: 4610 mov r0, r2 800d436: 4798 blx r3 800d438: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d43a: e029 b.n 800d490 USBD_CtlError(pdev, req); 800d43c: 6839 ldr r1, [r7, #0] 800d43e: 6878 ldr r0, [r7, #4] 800d440: f000 fa2c bl 800d89c err++; 800d444: 7afb ldrb r3, [r7, #11] 800d446: 3301 adds r3, #1 800d448: 72fb strb r3, [r7, #11] break; 800d44a: e021 b.n 800d490 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 800d44c: 687b ldr r3, [r7, #4] 800d44e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d452: 699b ldr r3, [r3, #24] 800d454: 2b00 cmp r3, #0 800d456: d00b beq.n 800d470 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 800d458: 687b ldr r3, [r7, #4] 800d45a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0 800d45e: 699b ldr r3, [r3, #24] 800d460: 687a ldr r2, [r7, #4] 800d462: 7c12 ldrb r2, [r2, #16] 800d464: f107 0108 add.w r1, r7, #8 800d468: 4610 mov r0, r2 800d46a: 4798 blx r3 800d46c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d46e: e00f b.n 800d490 USBD_CtlError(pdev, req); 800d470: 6839 ldr r1, [r7, #0] 800d472: 6878 ldr r0, [r7, #4] 800d474: f000 fa12 bl 800d89c err++; 800d478: 7afb ldrb r3, [r7, #11] 800d47a: 3301 adds r3, #1 800d47c: 72fb strb r3, [r7, #11] break; 800d47e: e007 b.n 800d490 USBD_CtlError(pdev, req); err++; } break; #else USBD_CtlError(pdev, req); 800d480: 6839 ldr r1, [r7, #0] 800d482: 6878 ldr r0, [r7, #4] 800d484: f000 fa0a bl 800d89c err++; 800d488: 7afb ldrb r3, [r7, #11] 800d48a: 3301 adds r3, #1 800d48c: 72fb strb r3, [r7, #11] #endif } break; 800d48e: e038 b.n 800d502 800d490: e037 b.n 800d502 case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800d492: 687b ldr r3, [r7, #4] 800d494: 7c1b ldrb r3, [r3, #16] 800d496: 2b00 cmp r3, #0 800d498: d109 bne.n 800d4ae { pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); 800d49a: 687b ldr r3, [r7, #4] 800d49c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800d4a0: 6b5b ldr r3, [r3, #52] @ 0x34 800d4a2: f107 0208 add.w r2, r7, #8 800d4a6: 4610 mov r0, r2 800d4a8: 4798 blx r3 800d4aa: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800d4ac: e029 b.n 800d502 USBD_CtlError(pdev, req); 800d4ae: 6839 ldr r1, [r7, #0] 800d4b0: 6878 ldr r0, [r7, #4] 800d4b2: f000 f9f3 bl 800d89c err++; 800d4b6: 7afb ldrb r3, [r7, #11] 800d4b8: 3301 adds r3, #1 800d4ba: 72fb strb r3, [r7, #11] break; 800d4bc: e021 b.n 800d502 case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800d4be: 687b ldr r3, [r7, #4] 800d4c0: 7c1b ldrb r3, [r3, #16] 800d4c2: 2b00 cmp r3, #0 800d4c4: d10d bne.n 800d4e2 { pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); 800d4c6: 687b ldr r3, [r7, #4] 800d4c8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800d4cc: 6b1b ldr r3, [r3, #48] @ 0x30 800d4ce: f107 0208 add.w r2, r7, #8 800d4d2: 4610 mov r0, r2 800d4d4: 4798 blx r3 800d4d6: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 800d4d8: 68fb ldr r3, [r7, #12] 800d4da: 3301 adds r3, #1 800d4dc: 2207 movs r2, #7 800d4de: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 800d4e0: e00f b.n 800d502 USBD_CtlError(pdev, req); 800d4e2: 6839 ldr r1, [r7, #0] 800d4e4: 6878 ldr r0, [r7, #4] 800d4e6: f000 f9d9 bl 800d89c err++; 800d4ea: 7afb ldrb r3, [r7, #11] 800d4ec: 3301 adds r3, #1 800d4ee: 72fb strb r3, [r7, #11] break; 800d4f0: e007 b.n 800d502 default: USBD_CtlError(pdev, req); 800d4f2: 6839 ldr r1, [r7, #0] 800d4f4: 6878 ldr r0, [r7, #4] 800d4f6: f000 f9d1 bl 800d89c err++; 800d4fa: 7afb ldrb r3, [r7, #11] 800d4fc: 3301 adds r3, #1 800d4fe: 72fb strb r3, [r7, #11] break; 800d500: bf00 nop } if (err != 0U) 800d502: 7afb ldrb r3, [r7, #11] 800d504: 2b00 cmp r3, #0 800d506: d11c bne.n 800d542 { return; } else { if ((len != 0U) && (req->wLength != 0U)) 800d508: 893b ldrh r3, [r7, #8] 800d50a: 2b00 cmp r3, #0 800d50c: d011 beq.n 800d532 800d50e: 683b ldr r3, [r7, #0] 800d510: 88db ldrh r3, [r3, #6] 800d512: 2b00 cmp r3, #0 800d514: d00d beq.n 800d532 { len = MIN(len, req->wLength); 800d516: 683b ldr r3, [r7, #0] 800d518: 88da ldrh r2, [r3, #6] 800d51a: 893b ldrh r3, [r7, #8] 800d51c: 4293 cmp r3, r2 800d51e: bf28 it cs 800d520: 4613 movcs r3, r2 800d522: b29b uxth r3, r3 800d524: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 800d526: 893b ldrh r3, [r7, #8] 800d528: 461a mov r2, r3 800d52a: 68f9 ldr r1, [r7, #12] 800d52c: 6878 ldr r0, [r7, #4] 800d52e: f000 fa1f bl 800d970 } if (req->wLength == 0U) 800d532: 683b ldr r3, [r7, #0] 800d534: 88db ldrh r3, [r3, #6] 800d536: 2b00 cmp r3, #0 800d538: d104 bne.n 800d544 { (void)USBD_CtlSendStatus(pdev); 800d53a: 6878 ldr r0, [r7, #4] 800d53c: f000 fa76 bl 800da2c 800d540: e000 b.n 800d544 return; 800d542: bf00 nop } } } 800d544: 3710 adds r7, #16 800d546: 46bd mov sp, r7 800d548: bd80 pop {r7, pc} 800d54a: bf00 nop 0800d54c : * @param req: usb request * @retval status */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d54c: b580 push {r7, lr} 800d54e: b084 sub sp, #16 800d550: af00 add r7, sp, #0 800d552: 6078 str r0, [r7, #4] 800d554: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 800d556: 683b ldr r3, [r7, #0] 800d558: 889b ldrh r3, [r3, #4] 800d55a: 2b00 cmp r3, #0 800d55c: d130 bne.n 800d5c0 800d55e: 683b ldr r3, [r7, #0] 800d560: 88db ldrh r3, [r3, #6] 800d562: 2b00 cmp r3, #0 800d564: d12c bne.n 800d5c0 800d566: 683b ldr r3, [r7, #0] 800d568: 885b ldrh r3, [r3, #2] 800d56a: 2b7f cmp r3, #127 @ 0x7f 800d56c: d828 bhi.n 800d5c0 { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 800d56e: 683b ldr r3, [r7, #0] 800d570: 885b ldrh r3, [r3, #2] 800d572: b2db uxtb r3, r3 800d574: f003 037f and.w r3, r3, #127 @ 0x7f 800d578: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 800d57a: 687b ldr r3, [r7, #4] 800d57c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d580: 2b03 cmp r3, #3 800d582: d104 bne.n 800d58e { USBD_CtlError(pdev, req); 800d584: 6839 ldr r1, [r7, #0] 800d586: 6878 ldr r0, [r7, #4] 800d588: f000 f988 bl 800d89c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800d58c: e01d b.n 800d5ca } else { pdev->dev_address = dev_addr; 800d58e: 687b ldr r3, [r7, #4] 800d590: 7bfa ldrb r2, [r7, #15] 800d592: f883 229e strb.w r2, [r3, #670] @ 0x29e USBD_LL_SetUSBAddress(pdev, dev_addr); 800d596: 7bfb ldrb r3, [r7, #15] 800d598: 4619 mov r1, r3 800d59a: 6878 ldr r0, [r7, #4] 800d59c: f000 fec1 bl 800e322 USBD_CtlSendStatus(pdev); 800d5a0: 6878 ldr r0, [r7, #4] 800d5a2: f000 fa43 bl 800da2c if (dev_addr != 0U) 800d5a6: 7bfb ldrb r3, [r7, #15] 800d5a8: 2b00 cmp r3, #0 800d5aa: d004 beq.n 800d5b6 { pdev->dev_state = USBD_STATE_ADDRESSED; 800d5ac: 687b ldr r3, [r7, #4] 800d5ae: 2202 movs r2, #2 800d5b0: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800d5b4: e009 b.n 800d5ca } else { pdev->dev_state = USBD_STATE_DEFAULT; 800d5b6: 687b ldr r3, [r7, #4] 800d5b8: 2201 movs r2, #1 800d5ba: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800d5be: e004 b.n 800d5ca } } } else { USBD_CtlError(pdev, req); 800d5c0: 6839 ldr r1, [r7, #0] 800d5c2: 6878 ldr r0, [r7, #4] 800d5c4: f000 f96a bl 800d89c } } 800d5c8: bf00 nop 800d5ca: bf00 nop 800d5cc: 3710 adds r7, #16 800d5ce: 46bd mov sp, r7 800d5d0: bd80 pop {r7, pc} ... 0800d5d4 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d5d4: b580 push {r7, lr} 800d5d6: b082 sub sp, #8 800d5d8: af00 add r7, sp, #0 800d5da: 6078 str r0, [r7, #4] 800d5dc: 6039 str r1, [r7, #0] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 800d5de: 683b ldr r3, [r7, #0] 800d5e0: 885b ldrh r3, [r3, #2] 800d5e2: b2da uxtb r2, r3 800d5e4: 4b41 ldr r3, [pc, #260] @ (800d6ec ) 800d5e6: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 800d5e8: 4b40 ldr r3, [pc, #256] @ (800d6ec ) 800d5ea: 781b ldrb r3, [r3, #0] 800d5ec: 2b01 cmp r3, #1 800d5ee: d904 bls.n 800d5fa { USBD_CtlError(pdev, req); 800d5f0: 6839 ldr r1, [r7, #0] 800d5f2: 6878 ldr r0, [r7, #4] 800d5f4: f000 f952 bl 800d89c 800d5f8: e075 b.n 800d6e6 } else { switch (pdev->dev_state) 800d5fa: 687b ldr r3, [r7, #4] 800d5fc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d600: 2b02 cmp r3, #2 800d602: d002 beq.n 800d60a 800d604: 2b03 cmp r3, #3 800d606: d023 beq.n 800d650 800d608: e062 b.n 800d6d0 { case USBD_STATE_ADDRESSED: if (cfgidx) 800d60a: 4b38 ldr r3, [pc, #224] @ (800d6ec ) 800d60c: 781b ldrb r3, [r3, #0] 800d60e: 2b00 cmp r3, #0 800d610: d01a beq.n 800d648 { pdev->dev_config = cfgidx; 800d612: 4b36 ldr r3, [pc, #216] @ (800d6ec ) 800d614: 781b ldrb r3, [r3, #0] 800d616: 461a mov r2, r3 800d618: 687b ldr r3, [r7, #4] 800d61a: 605a str r2, [r3, #4] pdev->dev_state = USBD_STATE_CONFIGURED; 800d61c: 687b ldr r3, [r7, #4] 800d61e: 2203 movs r2, #3 800d620: f883 229c strb.w r2, [r3, #668] @ 0x29c if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) 800d624: 4b31 ldr r3, [pc, #196] @ (800d6ec ) 800d626: 781b ldrb r3, [r3, #0] 800d628: 4619 mov r1, r3 800d62a: 6878 ldr r0, [r7, #4] 800d62c: f7ff f9e7 bl 800c9fe 800d630: 4603 mov r3, r0 800d632: 2b02 cmp r3, #2 800d634: d104 bne.n 800d640 { USBD_CtlError(pdev, req); 800d636: 6839 ldr r1, [r7, #0] 800d638: 6878 ldr r0, [r7, #4] 800d63a: f000 f92f bl 800d89c return; 800d63e: e052 b.n 800d6e6 } USBD_CtlSendStatus(pdev); 800d640: 6878 ldr r0, [r7, #4] 800d642: f000 f9f3 bl 800da2c } else { USBD_CtlSendStatus(pdev); } break; 800d646: e04e b.n 800d6e6 USBD_CtlSendStatus(pdev); 800d648: 6878 ldr r0, [r7, #4] 800d64a: f000 f9ef bl 800da2c break; 800d64e: e04a b.n 800d6e6 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 800d650: 4b26 ldr r3, [pc, #152] @ (800d6ec ) 800d652: 781b ldrb r3, [r3, #0] 800d654: 2b00 cmp r3, #0 800d656: d112 bne.n 800d67e { pdev->dev_state = USBD_STATE_ADDRESSED; 800d658: 687b ldr r3, [r7, #4] 800d65a: 2202 movs r2, #2 800d65c: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 800d660: 4b22 ldr r3, [pc, #136] @ (800d6ec ) 800d662: 781b ldrb r3, [r3, #0] 800d664: 461a mov r2, r3 800d666: 687b ldr r3, [r7, #4] 800d668: 605a str r2, [r3, #4] USBD_ClrClassConfig(pdev, cfgidx); 800d66a: 4b20 ldr r3, [pc, #128] @ (800d6ec ) 800d66c: 781b ldrb r3, [r3, #0] 800d66e: 4619 mov r1, r3 800d670: 6878 ldr r0, [r7, #4] 800d672: f7ff f9e3 bl 800ca3c USBD_CtlSendStatus(pdev); 800d676: 6878 ldr r0, [r7, #4] 800d678: f000 f9d8 bl 800da2c } else { USBD_CtlSendStatus(pdev); } break; 800d67c: e033 b.n 800d6e6 else if (cfgidx != pdev->dev_config) 800d67e: 4b1b ldr r3, [pc, #108] @ (800d6ec ) 800d680: 781b ldrb r3, [r3, #0] 800d682: 461a mov r2, r3 800d684: 687b ldr r3, [r7, #4] 800d686: 685b ldr r3, [r3, #4] 800d688: 429a cmp r2, r3 800d68a: d01d beq.n 800d6c8 USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800d68c: 687b ldr r3, [r7, #4] 800d68e: 685b ldr r3, [r3, #4] 800d690: b2db uxtb r3, r3 800d692: 4619 mov r1, r3 800d694: 6878 ldr r0, [r7, #4] 800d696: f7ff f9d1 bl 800ca3c pdev->dev_config = cfgidx; 800d69a: 4b14 ldr r3, [pc, #80] @ (800d6ec ) 800d69c: 781b ldrb r3, [r3, #0] 800d69e: 461a mov r2, r3 800d6a0: 687b ldr r3, [r7, #4] 800d6a2: 605a str r2, [r3, #4] if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) 800d6a4: 4b11 ldr r3, [pc, #68] @ (800d6ec ) 800d6a6: 781b ldrb r3, [r3, #0] 800d6a8: 4619 mov r1, r3 800d6aa: 6878 ldr r0, [r7, #4] 800d6ac: f7ff f9a7 bl 800c9fe 800d6b0: 4603 mov r3, r0 800d6b2: 2b02 cmp r3, #2 800d6b4: d104 bne.n 800d6c0 USBD_CtlError(pdev, req); 800d6b6: 6839 ldr r1, [r7, #0] 800d6b8: 6878 ldr r0, [r7, #4] 800d6ba: f000 f8ef bl 800d89c return; 800d6be: e012 b.n 800d6e6 USBD_CtlSendStatus(pdev); 800d6c0: 6878 ldr r0, [r7, #4] 800d6c2: f000 f9b3 bl 800da2c break; 800d6c6: e00e b.n 800d6e6 USBD_CtlSendStatus(pdev); 800d6c8: 6878 ldr r0, [r7, #4] 800d6ca: f000 f9af bl 800da2c break; 800d6ce: e00a b.n 800d6e6 default: USBD_CtlError(pdev, req); 800d6d0: 6839 ldr r1, [r7, #0] 800d6d2: 6878 ldr r0, [r7, #4] 800d6d4: f000 f8e2 bl 800d89c USBD_ClrClassConfig(pdev, cfgidx); 800d6d8: 4b04 ldr r3, [pc, #16] @ (800d6ec ) 800d6da: 781b ldrb r3, [r3, #0] 800d6dc: 4619 mov r1, r3 800d6de: 6878 ldr r0, [r7, #4] 800d6e0: f7ff f9ac bl 800ca3c break; 800d6e4: bf00 nop } } } 800d6e6: 3708 adds r7, #8 800d6e8: 46bd mov sp, r7 800d6ea: bd80 pop {r7, pc} 800d6ec: 20000498 .word 0x20000498 0800d6f0 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d6f0: b580 push {r7, lr} 800d6f2: b082 sub sp, #8 800d6f4: af00 add r7, sp, #0 800d6f6: 6078 str r0, [r7, #4] 800d6f8: 6039 str r1, [r7, #0] if (req->wLength != 1U) 800d6fa: 683b ldr r3, [r7, #0] 800d6fc: 88db ldrh r3, [r3, #6] 800d6fe: 2b01 cmp r3, #1 800d700: d004 beq.n 800d70c { USBD_CtlError(pdev, req); 800d702: 6839 ldr r1, [r7, #0] 800d704: 6878 ldr r0, [r7, #4] 800d706: f000 f8c9 bl 800d89c default: USBD_CtlError(pdev, req); break; } } } 800d70a: e022 b.n 800d752 switch (pdev->dev_state) 800d70c: 687b ldr r3, [r7, #4] 800d70e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d712: 2b02 cmp r3, #2 800d714: dc02 bgt.n 800d71c 800d716: 2b00 cmp r3, #0 800d718: dc03 bgt.n 800d722 800d71a: e015 b.n 800d748 800d71c: 2b03 cmp r3, #3 800d71e: d00b beq.n 800d738 800d720: e012 b.n 800d748 pdev->dev_default_config = 0U; 800d722: 687b ldr r3, [r7, #4] 800d724: 2200 movs r2, #0 800d726: 609a str r2, [r3, #8] USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U); 800d728: 687b ldr r3, [r7, #4] 800d72a: 3308 adds r3, #8 800d72c: 2201 movs r2, #1 800d72e: 4619 mov r1, r3 800d730: 6878 ldr r0, [r7, #4] 800d732: f000 f91d bl 800d970 break; 800d736: e00c b.n 800d752 USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U); 800d738: 687b ldr r3, [r7, #4] 800d73a: 3304 adds r3, #4 800d73c: 2201 movs r2, #1 800d73e: 4619 mov r1, r3 800d740: 6878 ldr r0, [r7, #4] 800d742: f000 f915 bl 800d970 break; 800d746: e004 b.n 800d752 USBD_CtlError(pdev, req); 800d748: 6839 ldr r1, [r7, #0] 800d74a: 6878 ldr r0, [r7, #4] 800d74c: f000 f8a6 bl 800d89c break; 800d750: bf00 nop } 800d752: bf00 nop 800d754: 3708 adds r7, #8 800d756: 46bd mov sp, r7 800d758: bd80 pop {r7, pc} 0800d75a : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d75a: b580 push {r7, lr} 800d75c: b082 sub sp, #8 800d75e: af00 add r7, sp, #0 800d760: 6078 str r0, [r7, #4] 800d762: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800d764: 687b ldr r3, [r7, #4] 800d766: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d76a: 3b01 subs r3, #1 800d76c: 2b02 cmp r3, #2 800d76e: d81e bhi.n 800d7ae { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 800d770: 683b ldr r3, [r7, #0] 800d772: 88db ldrh r3, [r3, #6] 800d774: 2b02 cmp r3, #2 800d776: d004 beq.n 800d782 { USBD_CtlError(pdev, req); 800d778: 6839 ldr r1, [r7, #0] 800d77a: 6878 ldr r0, [r7, #4] 800d77c: f000 f88e bl 800d89c break; 800d780: e01a b.n 800d7b8 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 800d782: 687b ldr r3, [r7, #4] 800d784: 2201 movs r2, #1 800d786: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif if (pdev->dev_remote_wakeup) 800d788: 687b ldr r3, [r7, #4] 800d78a: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 800d78e: 2b00 cmp r3, #0 800d790: d005 beq.n 800d79e { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 800d792: 687b ldr r3, [r7, #4] 800d794: 68db ldr r3, [r3, #12] 800d796: f043 0202 orr.w r2, r3, #2 800d79a: 687b ldr r3, [r7, #4] 800d79c: 60da str r2, [r3, #12] } USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U); 800d79e: 687b ldr r3, [r7, #4] 800d7a0: 330c adds r3, #12 800d7a2: 2202 movs r2, #2 800d7a4: 4619 mov r1, r3 800d7a6: 6878 ldr r0, [r7, #4] 800d7a8: f000 f8e2 bl 800d970 break; 800d7ac: e004 b.n 800d7b8 default: USBD_CtlError(pdev, req); 800d7ae: 6839 ldr r1, [r7, #0] 800d7b0: 6878 ldr r0, [r7, #4] 800d7b2: f000 f873 bl 800d89c break; 800d7b6: bf00 nop } } 800d7b8: bf00 nop 800d7ba: 3708 adds r7, #8 800d7bc: 46bd mov sp, r7 800d7be: bd80 pop {r7, pc} 0800d7c0 : * @param req: usb request * @retval status */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d7c0: b580 push {r7, lr} 800d7c2: b082 sub sp, #8 800d7c4: af00 add r7, sp, #0 800d7c6: 6078 str r0, [r7, #4] 800d7c8: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800d7ca: 683b ldr r3, [r7, #0] 800d7cc: 885b ldrh r3, [r3, #2] 800d7ce: 2b01 cmp r3, #1 800d7d0: d106 bne.n 800d7e0 { pdev->dev_remote_wakeup = 1U; 800d7d2: 687b ldr r3, [r7, #4] 800d7d4: 2201 movs r2, #1 800d7d6: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 USBD_CtlSendStatus(pdev); 800d7da: 6878 ldr r0, [r7, #4] 800d7dc: f000 f926 bl 800da2c } } 800d7e0: bf00 nop 800d7e2: 3708 adds r7, #8 800d7e4: 46bd mov sp, r7 800d7e6: bd80 pop {r7, pc} 0800d7e8 : * @param req: usb request * @retval status */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d7e8: b580 push {r7, lr} 800d7ea: b082 sub sp, #8 800d7ec: af00 add r7, sp, #0 800d7ee: 6078 str r0, [r7, #4] 800d7f0: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800d7f2: 687b ldr r3, [r7, #4] 800d7f4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800d7f8: 3b01 subs r3, #1 800d7fa: 2b02 cmp r3, #2 800d7fc: d80b bhi.n 800d816 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800d7fe: 683b ldr r3, [r7, #0] 800d800: 885b ldrh r3, [r3, #2] 800d802: 2b01 cmp r3, #1 800d804: d10c bne.n 800d820 { pdev->dev_remote_wakeup = 0U; 800d806: 687b ldr r3, [r7, #4] 800d808: 2200 movs r2, #0 800d80a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 USBD_CtlSendStatus(pdev); 800d80e: 6878 ldr r0, [r7, #4] 800d810: f000 f90c bl 800da2c } break; 800d814: e004 b.n 800d820 default: USBD_CtlError(pdev, req); 800d816: 6839 ldr r1, [r7, #0] 800d818: 6878 ldr r0, [r7, #4] 800d81a: f000 f83f bl 800d89c break; 800d81e: e000 b.n 800d822 break; 800d820: bf00 nop } } 800d822: bf00 nop 800d824: 3708 adds r7, #8 800d826: 46bd mov sp, r7 800d828: bd80 pop {r7, pc} 0800d82a : * @param req: usb request * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 800d82a: b480 push {r7} 800d82c: b083 sub sp, #12 800d82e: af00 add r7, sp, #0 800d830: 6078 str r0, [r7, #4] 800d832: 6039 str r1, [r7, #0] req->bmRequest = *(uint8_t *)(pdata); 800d834: 683b ldr r3, [r7, #0] 800d836: 781a ldrb r2, [r3, #0] 800d838: 687b ldr r3, [r7, #4] 800d83a: 701a strb r2, [r3, #0] req->bRequest = *(uint8_t *)(pdata + 1U); 800d83c: 683b ldr r3, [r7, #0] 800d83e: 785a ldrb r2, [r3, #1] 800d840: 687b ldr r3, [r7, #4] 800d842: 705a strb r2, [r3, #1] req->wValue = SWAPBYTE(pdata + 2U); 800d844: 683b ldr r3, [r7, #0] 800d846: 3302 adds r3, #2 800d848: 781b ldrb r3, [r3, #0] 800d84a: 461a mov r2, r3 800d84c: 683b ldr r3, [r7, #0] 800d84e: 3303 adds r3, #3 800d850: 781b ldrb r3, [r3, #0] 800d852: 021b lsls r3, r3, #8 800d854: b29b uxth r3, r3 800d856: 4413 add r3, r2 800d858: b29a uxth r2, r3 800d85a: 687b ldr r3, [r7, #4] 800d85c: 805a strh r2, [r3, #2] req->wIndex = SWAPBYTE(pdata + 4U); 800d85e: 683b ldr r3, [r7, #0] 800d860: 3304 adds r3, #4 800d862: 781b ldrb r3, [r3, #0] 800d864: 461a mov r2, r3 800d866: 683b ldr r3, [r7, #0] 800d868: 3305 adds r3, #5 800d86a: 781b ldrb r3, [r3, #0] 800d86c: 021b lsls r3, r3, #8 800d86e: b29b uxth r3, r3 800d870: 4413 add r3, r2 800d872: b29a uxth r2, r3 800d874: 687b ldr r3, [r7, #4] 800d876: 809a strh r2, [r3, #4] req->wLength = SWAPBYTE(pdata + 6U); 800d878: 683b ldr r3, [r7, #0] 800d87a: 3306 adds r3, #6 800d87c: 781b ldrb r3, [r3, #0] 800d87e: 461a mov r2, r3 800d880: 683b ldr r3, [r7, #0] 800d882: 3307 adds r3, #7 800d884: 781b ldrb r3, [r3, #0] 800d886: 021b lsls r3, r3, #8 800d888: b29b uxth r3, r3 800d88a: 4413 add r3, r2 800d88c: b29a uxth r2, r3 800d88e: 687b ldr r3, [r7, #4] 800d890: 80da strh r2, [r3, #6] } 800d892: bf00 nop 800d894: 370c adds r7, #12 800d896: 46bd mov sp, r7 800d898: bc80 pop {r7} 800d89a: 4770 bx lr 0800d89c : * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800d89c: b580 push {r7, lr} 800d89e: b082 sub sp, #8 800d8a0: af00 add r7, sp, #0 800d8a2: 6078 str r0, [r7, #4] 800d8a4: 6039 str r1, [r7, #0] USBD_LL_StallEP(pdev, 0x80U); 800d8a6: 2180 movs r1, #128 @ 0x80 800d8a8: 6878 ldr r0, [r7, #4] 800d8aa: f000 fcd1 bl 800e250 USBD_LL_StallEP(pdev, 0U); 800d8ae: 2100 movs r1, #0 800d8b0: 6878 ldr r0, [r7, #4] 800d8b2: f000 fccd bl 800e250 } 800d8b6: bf00 nop 800d8b8: 3708 adds r7, #8 800d8ba: 46bd mov sp, r7 800d8bc: bd80 pop {r7, pc} 0800d8be : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 800d8be: b580 push {r7, lr} 800d8c0: b086 sub sp, #24 800d8c2: af00 add r7, sp, #0 800d8c4: 60f8 str r0, [r7, #12] 800d8c6: 60b9 str r1, [r7, #8] 800d8c8: 607a str r2, [r7, #4] uint8_t idx = 0U; 800d8ca: 2300 movs r3, #0 800d8cc: 75fb strb r3, [r7, #23] if (desc != NULL) 800d8ce: 68fb ldr r3, [r7, #12] 800d8d0: 2b00 cmp r3, #0 800d8d2: d032 beq.n 800d93a { *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U; 800d8d4: 68f8 ldr r0, [r7, #12] 800d8d6: f000 f834 bl 800d942 800d8da: 4603 mov r3, r0 800d8dc: 3301 adds r3, #1 800d8de: b29b uxth r3, r3 800d8e0: 005b lsls r3, r3, #1 800d8e2: b29a uxth r2, r3 800d8e4: 687b ldr r3, [r7, #4] 800d8e6: 801a strh r2, [r3, #0] unicode[idx++] = *(uint8_t *)(void *)len; 800d8e8: 7dfb ldrb r3, [r7, #23] 800d8ea: 1c5a adds r2, r3, #1 800d8ec: 75fa strb r2, [r7, #23] 800d8ee: 461a mov r2, r3 800d8f0: 68bb ldr r3, [r7, #8] 800d8f2: 4413 add r3, r2 800d8f4: 687a ldr r2, [r7, #4] 800d8f6: 7812 ldrb r2, [r2, #0] 800d8f8: 701a strb r2, [r3, #0] unicode[idx++] = USB_DESC_TYPE_STRING; 800d8fa: 7dfb ldrb r3, [r7, #23] 800d8fc: 1c5a adds r2, r3, #1 800d8fe: 75fa strb r2, [r7, #23] 800d900: 461a mov r2, r3 800d902: 68bb ldr r3, [r7, #8] 800d904: 4413 add r3, r2 800d906: 2203 movs r2, #3 800d908: 701a strb r2, [r3, #0] while (*desc != '\0') 800d90a: e012 b.n 800d932 { unicode[idx++] = *desc++; 800d90c: 68fb ldr r3, [r7, #12] 800d90e: 1c5a adds r2, r3, #1 800d910: 60fa str r2, [r7, #12] 800d912: 7dfa ldrb r2, [r7, #23] 800d914: 1c51 adds r1, r2, #1 800d916: 75f9 strb r1, [r7, #23] 800d918: 4611 mov r1, r2 800d91a: 68ba ldr r2, [r7, #8] 800d91c: 440a add r2, r1 800d91e: 781b ldrb r3, [r3, #0] 800d920: 7013 strb r3, [r2, #0] unicode[idx++] = 0U; 800d922: 7dfb ldrb r3, [r7, #23] 800d924: 1c5a adds r2, r3, #1 800d926: 75fa strb r2, [r7, #23] 800d928: 461a mov r2, r3 800d92a: 68bb ldr r3, [r7, #8] 800d92c: 4413 add r3, r2 800d92e: 2200 movs r2, #0 800d930: 701a strb r2, [r3, #0] while (*desc != '\0') 800d932: 68fb ldr r3, [r7, #12] 800d934: 781b ldrb r3, [r3, #0] 800d936: 2b00 cmp r3, #0 800d938: d1e8 bne.n 800d90c } } } 800d93a: bf00 nop 800d93c: 3718 adds r7, #24 800d93e: 46bd mov sp, r7 800d940: bd80 pop {r7, pc} 0800d942 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800d942: b480 push {r7} 800d944: b085 sub sp, #20 800d946: af00 add r7, sp, #0 800d948: 6078 str r0, [r7, #4] uint8_t len = 0U; 800d94a: 2300 movs r3, #0 800d94c: 73fb strb r3, [r7, #15] while (*buf != '\0') 800d94e: e005 b.n 800d95c { len++; 800d950: 7bfb ldrb r3, [r7, #15] 800d952: 3301 adds r3, #1 800d954: 73fb strb r3, [r7, #15] buf++; 800d956: 687b ldr r3, [r7, #4] 800d958: 3301 adds r3, #1 800d95a: 607b str r3, [r7, #4] while (*buf != '\0') 800d95c: 687b ldr r3, [r7, #4] 800d95e: 781b ldrb r3, [r3, #0] 800d960: 2b00 cmp r3, #0 800d962: d1f5 bne.n 800d950 } return len; 800d964: 7bfb ldrb r3, [r7, #15] } 800d966: 4618 mov r0, r3 800d968: 3714 adds r7, #20 800d96a: 46bd mov sp, r7 800d96c: bc80 pop {r7} 800d96e: 4770 bx lr 0800d970 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint16_t len) { 800d970: b580 push {r7, lr} 800d972: b084 sub sp, #16 800d974: af00 add r7, sp, #0 800d976: 60f8 str r0, [r7, #12] 800d978: 60b9 str r1, [r7, #8] 800d97a: 4613 mov r3, r2 800d97c: 80fb strh r3, [r7, #6] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800d97e: 68fb ldr r3, [r7, #12] 800d980: 2202 movs r2, #2 800d982: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800d986: 88fa ldrh r2, [r7, #6] 800d988: 68fb ldr r3, [r7, #12] 800d98a: 61da str r2, [r3, #28] pdev->ep_in[0].rem_length = len; 800d98c: 88fa ldrh r2, [r7, #6] 800d98e: 68fb ldr r3, [r7, #12] 800d990: 621a str r2, [r3, #32] /* Start the transfer */ USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800d992: 88fb ldrh r3, [r7, #6] 800d994: 68ba ldr r2, [r7, #8] 800d996: 2100 movs r1, #0 800d998: 68f8 ldr r0, [r7, #12] 800d99a: f000 fce1 bl 800e360 return USBD_OK; 800d99e: 2300 movs r3, #0 } 800d9a0: 4618 mov r0, r3 800d9a2: 3710 adds r7, #16 800d9a4: 46bd mov sp, r7 800d9a6: bd80 pop {r7, pc} 0800d9a8 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint16_t len) { 800d9a8: b580 push {r7, lr} 800d9aa: b084 sub sp, #16 800d9ac: af00 add r7, sp, #0 800d9ae: 60f8 str r0, [r7, #12] 800d9b0: 60b9 str r1, [r7, #8] 800d9b2: 4613 mov r3, r2 800d9b4: 80fb strh r3, [r7, #6] /* Start the next transfer */ USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800d9b6: 88fb ldrh r3, [r7, #6] 800d9b8: 68ba ldr r2, [r7, #8] 800d9ba: 2100 movs r1, #0 800d9bc: 68f8 ldr r0, [r7, #12] 800d9be: f000 fccf bl 800e360 return USBD_OK; 800d9c2: 2300 movs r3, #0 } 800d9c4: 4618 mov r0, r3 800d9c6: 3710 adds r7, #16 800d9c8: 46bd mov sp, r7 800d9ca: bd80 pop {r7, pc} 0800d9cc : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint16_t len) { 800d9cc: b580 push {r7, lr} 800d9ce: b084 sub sp, #16 800d9d0: af00 add r7, sp, #0 800d9d2: 60f8 str r0, [r7, #12] 800d9d4: 60b9 str r1, [r7, #8] 800d9d6: 4613 mov r3, r2 800d9d8: 80fb strh r3, [r7, #6] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; 800d9da: 68fb ldr r3, [r7, #12] 800d9dc: 2203 movs r2, #3 800d9de: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_out[0].total_length = len; 800d9e2: 88fa ldrh r2, [r7, #6] 800d9e4: 68fb ldr r3, [r7, #12] 800d9e6: f8c3 215c str.w r2, [r3, #348] @ 0x15c pdev->ep_out[0].rem_length = len; 800d9ea: 88fa ldrh r2, [r7, #6] 800d9ec: 68fb ldr r3, [r7, #12] 800d9ee: f8c3 2160 str.w r2, [r3, #352] @ 0x160 /* Start the transfer */ USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800d9f2: 88fb ldrh r3, [r7, #6] 800d9f4: 68ba ldr r2, [r7, #8] 800d9f6: 2100 movs r1, #0 800d9f8: 68f8 ldr r0, [r7, #12] 800d9fa: f000 fcd4 bl 800e3a6 return USBD_OK; 800d9fe: 2300 movs r3, #0 } 800da00: 4618 mov r0, r3 800da02: 3710 adds r7, #16 800da04: 46bd mov sp, r7 800da06: bd80 pop {r7, pc} 0800da08 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint16_t len) { 800da08: b580 push {r7, lr} 800da0a: b084 sub sp, #16 800da0c: af00 add r7, sp, #0 800da0e: 60f8 str r0, [r7, #12] 800da10: 60b9 str r1, [r7, #8] 800da12: 4613 mov r3, r2 800da14: 80fb strh r3, [r7, #6] USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800da16: 88fb ldrh r3, [r7, #6] 800da18: 68ba ldr r2, [r7, #8] 800da1a: 2100 movs r1, #0 800da1c: 68f8 ldr r0, [r7, #12] 800da1e: f000 fcc2 bl 800e3a6 return USBD_OK; 800da22: 2300 movs r3, #0 } 800da24: 4618 mov r0, r3 800da26: 3710 adds r7, #16 800da28: 46bd mov sp, r7 800da2a: bd80 pop {r7, pc} 0800da2c : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800da2c: b580 push {r7, lr} 800da2e: b082 sub sp, #8 800da30: af00 add r7, sp, #0 800da32: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800da34: 687b ldr r3, [r7, #4] 800da36: 2204 movs r2, #4 800da38: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800da3c: 2300 movs r3, #0 800da3e: 2200 movs r2, #0 800da40: 2100 movs r1, #0 800da42: 6878 ldr r0, [r7, #4] 800da44: f000 fc8c bl 800e360 return USBD_OK; 800da48: 2300 movs r3, #0 } 800da4a: 4618 mov r0, r3 800da4c: 3708 adds r7, #8 800da4e: 46bd mov sp, r7 800da50: bd80 pop {r7, pc} 0800da52 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800da52: b580 push {r7, lr} 800da54: b082 sub sp, #8 800da56: af00 add r7, sp, #0 800da58: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800da5a: 687b ldr r3, [r7, #4] 800da5c: 2205 movs r2, #5 800da5e: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800da62: 2300 movs r3, #0 800da64: 2200 movs r2, #0 800da66: 2100 movs r1, #0 800da68: 6878 ldr r0, [r7, #4] 800da6a: f000 fc9c bl 800e3a6 return USBD_OK; 800da6e: 2300 movs r3, #0 } 800da70: 4618 mov r0, r3 800da72: 3708 adds r7, #8 800da74: 46bd mov sp, r7 800da76: bd80 pop {r7, pc} 0800da78 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800da78: b580 push {r7, lr} 800da7a: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800da7c: 2200 movs r2, #0 800da7e: 4912 ldr r1, [pc, #72] @ (800dac8 ) 800da80: 4812 ldr r0, [pc, #72] @ (800dacc ) 800da82: f7fe ff62 bl 800c94a 800da86: 4603 mov r3, r0 800da88: 2b00 cmp r3, #0 800da8a: d001 beq.n 800da90 { Error_Handler(); 800da8c: f7f5 fe6c bl 8003768 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) 800da90: 490f ldr r1, [pc, #60] @ (800dad0 ) 800da92: 480e ldr r0, [pc, #56] @ (800dacc ) 800da94: f7fe ff84 bl 800c9a0 800da98: 4603 mov r3, r0 800da9a: 2b00 cmp r3, #0 800da9c: d001 beq.n 800daa2 { Error_Handler(); 800da9e: f7f5 fe63 bl 8003768 } if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) 800daa2: 490c ldr r1, [pc, #48] @ (800dad4 ) 800daa4: 4809 ldr r0, [pc, #36] @ (800dacc ) 800daa6: f7fe feb5 bl 800c814 800daaa: 4603 mov r3, r0 800daac: 2b00 cmp r3, #0 800daae: d001 beq.n 800dab4 { Error_Handler(); 800dab0: f7f5 fe5a bl 8003768 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800dab4: 4805 ldr r0, [pc, #20] @ (800dacc ) 800dab6: f7fe ff8c bl 800c9d2 800daba: 4603 mov r3, r0 800dabc: 2b00 cmp r3, #0 800dabe: d001 beq.n 800dac4 { Error_Handler(); 800dac0: f7f5 fe52 bl 8003768 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800dac4: bf00 nop 800dac6: bd80 pop {r7, pc} 800dac8: 2000013c .word 0x2000013c 800dacc: 2000049c .word 0x2000049c 800dad0: 20000028 .word 0x20000028 800dad4: 2000012c .word 0x2000012c 0800dad8 : /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ #define RX_FIFO_SZ 256 static uint8_t rx_fifo[RX_FIFO_SZ]; static volatile uint16_t rx_head = 0, rx_tail = 0; static void fifo_push(const uint8_t* data, uint32_t len) { 800dad8: b480 push {r7} 800dada: b085 sub sp, #20 800dadc: af00 add r7, sp, #0 800dade: 6078 str r0, [r7, #4] 800dae0: 6039 str r1, [r7, #0] while (len--) { 800dae2: e01e b.n 800db22 uint16_t next = (rx_head + 1u) & (RX_FIFO_SZ - 1u); 800dae4: 4b14 ldr r3, [pc, #80] @ (800db38 ) 800dae6: 881b ldrh r3, [r3, #0] 800dae8: b29b uxth r3, r3 800daea: 3301 adds r3, #1 800daec: b29b uxth r3, r3 800daee: b2db uxtb r3, r3 800daf0: 81fb strh r3, [r7, #14] if (next == (rx_tail & (RX_FIFO_SZ - 1u))) { 800daf2: 89fa ldrh r2, [r7, #14] 800daf4: 4b11 ldr r3, [pc, #68] @ (800db3c ) 800daf6: 881b ldrh r3, [r3, #0] 800daf8: b29b uxth r3, r3 800dafa: b2db uxtb r3, r3 800dafc: 429a cmp r2, r3 800dafe: d103 bne.n 800db08 /* overflow — drop byte (or set a flag) */ data++; 800db00: 687b ldr r3, [r7, #4] 800db02: 3301 adds r3, #1 800db04: 607b str r3, [r7, #4] continue; 800db06: e00c b.n 800db22 } rx_fifo[rx_head & (RX_FIFO_SZ - 1u)] = *data++; 800db08: 687b ldr r3, [r7, #4] 800db0a: 1c5a adds r2, r3, #1 800db0c: 607a str r2, [r7, #4] 800db0e: 4a0a ldr r2, [pc, #40] @ (800db38 ) 800db10: 8812 ldrh r2, [r2, #0] 800db12: b292 uxth r2, r2 800db14: b2d2 uxtb r2, r2 800db16: 7819 ldrb r1, [r3, #0] 800db18: 4b09 ldr r3, [pc, #36] @ (800db40 ) 800db1a: 5499 strb r1, [r3, r2] rx_head = next; 800db1c: 4a06 ldr r2, [pc, #24] @ (800db38 ) 800db1e: 89fb ldrh r3, [r7, #14] 800db20: 8013 strh r3, [r2, #0] while (len--) { 800db22: 683b ldr r3, [r7, #0] 800db24: 1e5a subs r2, r3, #1 800db26: 603a str r2, [r7, #0] 800db28: 2b00 cmp r3, #0 800db2a: d1db bne.n 800dae4 } } 800db2c: bf00 nop 800db2e: bf00 nop 800db30: 3714 adds r7, #20 800db32: 46bd mov sp, r7 800db34: bc80 pop {r7} 800db36: 4770 bx lr 800db38: 20001060 .word 0x20001060 800db3c: 20001062 .word 0x20001062 800db40: 20000f60 .word 0x20000f60 0800db44 : uint32_t CDC_Available(void) { 800db44: b480 push {r7} 800db46: af00 add r7, sp, #0 return (uint16_t)((rx_head - rx_tail) & (RX_FIFO_SZ - 1u)); 800db48: 4b06 ldr r3, [pc, #24] @ (800db64 ) 800db4a: 881b ldrh r3, [r3, #0] 800db4c: b29a uxth r2, r3 800db4e: 4b06 ldr r3, [pc, #24] @ (800db68 ) 800db50: 881b ldrh r3, [r3, #0] 800db52: b29b uxth r3, r3 800db54: 1ad3 subs r3, r2, r3 800db56: b29b uxth r3, r3 800db58: b2db uxtb r3, r3 } 800db5a: 4618 mov r0, r3 800db5c: 46bd mov sp, r7 800db5e: bc80 pop {r7} 800db60: 4770 bx lr 800db62: bf00 nop 800db64: 20001060 .word 0x20001060 800db68: 20001062 .word 0x20001062 0800db6c : int CDC_ReadByte(void) { 800db6c: b480 push {r7} 800db6e: b083 sub sp, #12 800db70: af00 add r7, sp, #0 if (rx_tail == rx_head) return -1; 800db72: 4b10 ldr r3, [pc, #64] @ (800dbb4 ) 800db74: 881b ldrh r3, [r3, #0] 800db76: b29a uxth r2, r3 800db78: 4b0f ldr r3, [pc, #60] @ (800dbb8 ) 800db7a: 881b ldrh r3, [r3, #0] 800db7c: b29b uxth r3, r3 800db7e: 429a cmp r2, r3 800db80: d102 bne.n 800db88 800db82: f04f 33ff mov.w r3, #4294967295 800db86: e010 b.n 800dbaa int b = rx_fifo[rx_tail & (RX_FIFO_SZ - 1u)]; 800db88: 4b0a ldr r3, [pc, #40] @ (800dbb4 ) 800db8a: 881b ldrh r3, [r3, #0] 800db8c: b29b uxth r3, r3 800db8e: b2db uxtb r3, r3 800db90: 4a0a ldr r2, [pc, #40] @ (800dbbc ) 800db92: 5cd3 ldrb r3, [r2, r3] 800db94: 607b str r3, [r7, #4] rx_tail = (rx_tail + 1u) & (RX_FIFO_SZ - 1u); 800db96: 4b07 ldr r3, [pc, #28] @ (800dbb4 ) 800db98: 881b ldrh r3, [r3, #0] 800db9a: b29b uxth r3, r3 800db9c: 3301 adds r3, #1 800db9e: b29b uxth r3, r3 800dba0: b2db uxtb r3, r3 800dba2: b29a uxth r2, r3 800dba4: 4b03 ldr r3, [pc, #12] @ (800dbb4 ) 800dba6: 801a strh r2, [r3, #0] return b; 800dba8: 687b ldr r3, [r7, #4] } 800dbaa: 4618 mov r0, r3 800dbac: 370c adds r7, #12 800dbae: 46bd mov sp, r7 800dbb0: bc80 pop {r7} 800dbb2: 4770 bx lr 800dbb4: 20001062 .word 0x20001062 800dbb8: 20001060 .word 0x20001060 800dbbc: 20000f60 .word 0x20000f60 0800dbc0 : /** * @brief Initializes the CDC media low layer over the FS USB IP * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_FS(void) { 800dbc0: b580 push {r7, lr} 800dbc2: af00 add r7, sp, #0 /* USER CODE BEGIN 3 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); 800dbc4: 2200 movs r2, #0 800dbc6: 4905 ldr r1, [pc, #20] @ (800dbdc ) 800dbc8: 4805 ldr r0, [pc, #20] @ (800dbe0 ) 800dbca: f7fe fe39 bl 800c840 USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); 800dbce: 4905 ldr r1, [pc, #20] @ (800dbe4 ) 800dbd0: 4803 ldr r0, [pc, #12] @ (800dbe0 ) 800dbd2: f7fe fe4e bl 800c872 return (USBD_OK); 800dbd6: 2300 movs r3, #0 /* USER CODE END 3 */ } 800dbd8: 4618 mov r0, r3 800dbda: bd80 pop {r7, pc} 800dbdc: 20000b60 .word 0x20000b60 800dbe0: 2000049c .word 0x2000049c 800dbe4: 20000760 .word 0x20000760 0800dbe8 : /** * @brief DeInitializes the CDC media low layer * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_FS(void) { 800dbe8: b480 push {r7} 800dbea: af00 add r7, sp, #0 /* USER CODE BEGIN 4 */ return (USBD_OK); 800dbec: 2300 movs r3, #0 /* USER CODE END 4 */ } 800dbee: 4618 mov r0, r3 800dbf0: 46bd mov sp, r7 800dbf2: bc80 pop {r7} 800dbf4: 4770 bx lr ... 0800dbf8 : * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { 800dbf8: b480 push {r7} 800dbfa: b083 sub sp, #12 800dbfc: af00 add r7, sp, #0 800dbfe: 4603 mov r3, r0 800dc00: 6039 str r1, [r7, #0] 800dc02: 71fb strb r3, [r7, #7] 800dc04: 4613 mov r3, r2 800dc06: 80bb strh r3, [r7, #4] /* USER CODE BEGIN 5 */ switch(cmd) 800dc08: 79fb ldrb r3, [r7, #7] 800dc0a: 2b23 cmp r3, #35 @ 0x23 800dc0c: d84a bhi.n 800dca4 800dc0e: a201 add r2, pc, #4 @ (adr r2, 800dc14 ) 800dc10: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800dc14: 0800dca5 .word 0x0800dca5 800dc18: 0800dca5 .word 0x0800dca5 800dc1c: 0800dca5 .word 0x0800dca5 800dc20: 0800dca5 .word 0x0800dca5 800dc24: 0800dca5 .word 0x0800dca5 800dc28: 0800dca5 .word 0x0800dca5 800dc2c: 0800dca5 .word 0x0800dca5 800dc30: 0800dca5 .word 0x0800dca5 800dc34: 0800dca5 .word 0x0800dca5 800dc38: 0800dca5 .word 0x0800dca5 800dc3c: 0800dca5 .word 0x0800dca5 800dc40: 0800dca5 .word 0x0800dca5 800dc44: 0800dca5 .word 0x0800dca5 800dc48: 0800dca5 .word 0x0800dca5 800dc4c: 0800dca5 .word 0x0800dca5 800dc50: 0800dca5 .word 0x0800dca5 800dc54: 0800dca5 .word 0x0800dca5 800dc58: 0800dca5 .word 0x0800dca5 800dc5c: 0800dca5 .word 0x0800dca5 800dc60: 0800dca5 .word 0x0800dca5 800dc64: 0800dca5 .word 0x0800dca5 800dc68: 0800dca5 .word 0x0800dca5 800dc6c: 0800dca5 .word 0x0800dca5 800dc70: 0800dca5 .word 0x0800dca5 800dc74: 0800dca5 .word 0x0800dca5 800dc78: 0800dca5 .word 0x0800dca5 800dc7c: 0800dca5 .word 0x0800dca5 800dc80: 0800dca5 .word 0x0800dca5 800dc84: 0800dca5 .word 0x0800dca5 800dc88: 0800dca5 .word 0x0800dca5 800dc8c: 0800dca5 .word 0x0800dca5 800dc90: 0800dca5 .word 0x0800dca5 800dc94: 0800dca5 .word 0x0800dca5 800dc98: 0800dca5 .word 0x0800dca5 800dc9c: 0800dca5 .word 0x0800dca5 800dca0: 0800dca5 .word 0x0800dca5 case CDC_SEND_BREAK: break; default: break; 800dca4: bf00 nop } return (USBD_OK); 800dca6: 2300 movs r3, #0 /* USER CODE END 5 */ } 800dca8: 4618 mov r0, r3 800dcaa: 370c adds r7, #12 800dcac: 46bd mov sp, r7 800dcae: bc80 pop {r7} 800dcb0: 4770 bx lr 800dcb2: bf00 nop 0800dcb4 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { 800dcb4: b580 push {r7, lr} 800dcb6: b082 sub sp, #8 800dcb8: af00 add r7, sp, #0 800dcba: 6078 str r0, [r7, #4] 800dcbc: 6039 str r1, [r7, #0] /* USER CODE BEGIN 6 */ if (*Len) fifo_push(Buf, *Len); 800dcbe: 683b ldr r3, [r7, #0] 800dcc0: 681b ldr r3, [r3, #0] 800dcc2: 2b00 cmp r3, #0 800dcc4: d005 beq.n 800dcd2 800dcc6: 683b ldr r3, [r7, #0] 800dcc8: 681b ldr r3, [r3, #0] 800dcca: 4619 mov r1, r3 800dccc: 6878 ldr r0, [r7, #4] 800dcce: f7ff ff03 bl 800dad8 USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); 800dcd2: 6879 ldr r1, [r7, #4] 800dcd4: 4805 ldr r0, [pc, #20] @ (800dcec ) 800dcd6: f7fe fdcc bl 800c872 USBD_CDC_ReceivePacket(&hUsbDeviceFS); 800dcda: 4804 ldr r0, [pc, #16] @ (800dcec ) 800dcdc: f7fe fe0b bl 800c8f6 return (USBD_OK); 800dce0: 2300 movs r3, #0 /* USER CODE END 6 */ } 800dce2: 4618 mov r0, r3 800dce4: 3708 adds r7, #8 800dce6: 46bd mov sp, r7 800dce8: bd80 pop {r7, pc} 800dcea: bf00 nop 800dcec: 2000049c .word 0x2000049c 0800dcf0 : * @param Buf: Buffer of data to be sent * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { 800dcf0: b580 push {r7, lr} 800dcf2: b084 sub sp, #16 800dcf4: af00 add r7, sp, #0 800dcf6: 6078 str r0, [r7, #4] 800dcf8: 460b mov r3, r1 800dcfa: 807b strh r3, [r7, #2] uint8_t result = USBD_OK; 800dcfc: 2300 movs r3, #0 800dcfe: 73fb strb r3, [r7, #15] /* USER CODE BEGIN 7 */ USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; 800dd00: 4b0d ldr r3, [pc, #52] @ (800dd38 ) 800dd02: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800dd06: 60bb str r3, [r7, #8] if (hcdc->TxState != 0){ 800dd08: 68bb ldr r3, [r7, #8] 800dd0a: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214 800dd0e: 2b00 cmp r3, #0 800dd10: d001 beq.n 800dd16 return USBD_BUSY; 800dd12: 2301 movs r3, #1 800dd14: e00b b.n 800dd2e } USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); 800dd16: 887b ldrh r3, [r7, #2] 800dd18: 461a mov r2, r3 800dd1a: 6879 ldr r1, [r7, #4] 800dd1c: 4806 ldr r0, [pc, #24] @ (800dd38 ) 800dd1e: f7fe fd8f bl 800c840 result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); 800dd22: 4805 ldr r0, [pc, #20] @ (800dd38 ) 800dd24: f7fe fdb8 bl 800c898 800dd28: 4603 mov r3, r0 800dd2a: 73fb strb r3, [r7, #15] /* USER CODE END 7 */ return result; 800dd2c: 7bfb ldrb r3, [r7, #15] } 800dd2e: 4618 mov r0, r3 800dd30: 3710 adds r7, #16 800dd32: 46bd mov sp, r7 800dd34: bd80 pop {r7, pc} 800dd36: bf00 nop 800dd38: 2000049c .word 0x2000049c 0800dd3c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800dd3c: b480 push {r7} 800dd3e: b083 sub sp, #12 800dd40: af00 add r7, sp, #0 800dd42: 4603 mov r3, r0 800dd44: 6039 str r1, [r7, #0] 800dd46: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800dd48: 683b ldr r3, [r7, #0] 800dd4a: 2212 movs r2, #18 800dd4c: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800dd4e: 4b03 ldr r3, [pc, #12] @ (800dd5c ) } 800dd50: 4618 mov r0, r3 800dd52: 370c adds r7, #12 800dd54: 46bd mov sp, r7 800dd56: bc80 pop {r7} 800dd58: 4770 bx lr 800dd5a: bf00 nop 800dd5c: 20000158 .word 0x20000158 0800dd60 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800dd60: b480 push {r7} 800dd62: b083 sub sp, #12 800dd64: af00 add r7, sp, #0 800dd66: 4603 mov r3, r0 800dd68: 6039 str r1, [r7, #0] 800dd6a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800dd6c: 683b ldr r3, [r7, #0] 800dd6e: 2204 movs r2, #4 800dd70: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800dd72: 4b03 ldr r3, [pc, #12] @ (800dd80 ) } 800dd74: 4618 mov r0, r3 800dd76: 370c adds r7, #12 800dd78: 46bd mov sp, r7 800dd7a: bc80 pop {r7} 800dd7c: 4770 bx lr 800dd7e: bf00 nop 800dd80: 2000016c .word 0x2000016c 0800dd84 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800dd84: b580 push {r7, lr} 800dd86: b082 sub sp, #8 800dd88: af00 add r7, sp, #0 800dd8a: 4603 mov r3, r0 800dd8c: 6039 str r1, [r7, #0] 800dd8e: 71fb strb r3, [r7, #7] if(speed == 0) 800dd90: 79fb ldrb r3, [r7, #7] 800dd92: 2b00 cmp r3, #0 800dd94: d105 bne.n 800dda2 { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800dd96: 683a ldr r2, [r7, #0] 800dd98: 4907 ldr r1, [pc, #28] @ (800ddb8 ) 800dd9a: 4808 ldr r0, [pc, #32] @ (800ddbc ) 800dd9c: f7ff fd8f bl 800d8be 800dda0: e004 b.n 800ddac } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800dda2: 683a ldr r2, [r7, #0] 800dda4: 4904 ldr r1, [pc, #16] @ (800ddb8 ) 800dda6: 4805 ldr r0, [pc, #20] @ (800ddbc ) 800dda8: f7ff fd89 bl 800d8be } return USBD_StrDesc; 800ddac: 4b02 ldr r3, [pc, #8] @ (800ddb8 ) } 800ddae: 4618 mov r0, r3 800ddb0: 3708 adds r7, #8 800ddb2: 46bd mov sp, r7 800ddb4: bd80 pop {r7, pc} 800ddb6: bf00 nop 800ddb8: 20001064 .word 0x20001064 800ddbc: 0800f468 .word 0x0800f468 0800ddc0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ddc0: b580 push {r7, lr} 800ddc2: b082 sub sp, #8 800ddc4: af00 add r7, sp, #0 800ddc6: 4603 mov r3, r0 800ddc8: 6039 str r1, [r7, #0] 800ddca: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800ddcc: 683a ldr r2, [r7, #0] 800ddce: 4904 ldr r1, [pc, #16] @ (800dde0 ) 800ddd0: 4804 ldr r0, [pc, #16] @ (800dde4 ) 800ddd2: f7ff fd74 bl 800d8be return USBD_StrDesc; 800ddd6: 4b02 ldr r3, [pc, #8] @ (800dde0 ) } 800ddd8: 4618 mov r0, r3 800ddda: 3708 adds r7, #8 800dddc: 46bd mov sp, r7 800ddde: bd80 pop {r7, pc} 800dde0: 20001064 .word 0x20001064 800dde4: 0800f480 .word 0x0800f480 0800dde8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800dde8: b580 push {r7, lr} 800ddea: b082 sub sp, #8 800ddec: af00 add r7, sp, #0 800ddee: 4603 mov r3, r0 800ddf0: 6039 str r1, [r7, #0] 800ddf2: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800ddf4: 683b ldr r3, [r7, #0] 800ddf6: 221a movs r2, #26 800ddf8: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800ddfa: f000 f843 bl 800de84 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800ddfe: 4b02 ldr r3, [pc, #8] @ (800de08 ) } 800de00: 4618 mov r0, r3 800de02: 3708 adds r7, #8 800de04: 46bd mov sp, r7 800de06: bd80 pop {r7, pc} 800de08: 20000170 .word 0x20000170 0800de0c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800de0c: b580 push {r7, lr} 800de0e: b082 sub sp, #8 800de10: af00 add r7, sp, #0 800de12: 4603 mov r3, r0 800de14: 6039 str r1, [r7, #0] 800de16: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800de18: 79fb ldrb r3, [r7, #7] 800de1a: 2b00 cmp r3, #0 800de1c: d105 bne.n 800de2a { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800de1e: 683a ldr r2, [r7, #0] 800de20: 4907 ldr r1, [pc, #28] @ (800de40 ) 800de22: 4808 ldr r0, [pc, #32] @ (800de44 ) 800de24: f7ff fd4b bl 800d8be 800de28: e004 b.n 800de34 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800de2a: 683a ldr r2, [r7, #0] 800de2c: 4904 ldr r1, [pc, #16] @ (800de40 ) 800de2e: 4805 ldr r0, [pc, #20] @ (800de44 ) 800de30: f7ff fd45 bl 800d8be } return USBD_StrDesc; 800de34: 4b02 ldr r3, [pc, #8] @ (800de40 ) } 800de36: 4618 mov r0, r3 800de38: 3708 adds r7, #8 800de3a: 46bd mov sp, r7 800de3c: bd80 pop {r7, pc} 800de3e: bf00 nop 800de40: 20001064 .word 0x20001064 800de44: 0800f494 .word 0x0800f494 0800de48 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800de48: b580 push {r7, lr} 800de4a: b082 sub sp, #8 800de4c: af00 add r7, sp, #0 800de4e: 4603 mov r3, r0 800de50: 6039 str r1, [r7, #0] 800de52: 71fb strb r3, [r7, #7] if(speed == 0) 800de54: 79fb ldrb r3, [r7, #7] 800de56: 2b00 cmp r3, #0 800de58: d105 bne.n 800de66 { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800de5a: 683a ldr r2, [r7, #0] 800de5c: 4907 ldr r1, [pc, #28] @ (800de7c ) 800de5e: 4808 ldr r0, [pc, #32] @ (800de80 ) 800de60: f7ff fd2d bl 800d8be 800de64: e004 b.n 800de70 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800de66: 683a ldr r2, [r7, #0] 800de68: 4904 ldr r1, [pc, #16] @ (800de7c ) 800de6a: 4805 ldr r0, [pc, #20] @ (800de80 ) 800de6c: f7ff fd27 bl 800d8be } return USBD_StrDesc; 800de70: 4b02 ldr r3, [pc, #8] @ (800de7c ) } 800de72: 4618 mov r0, r3 800de74: 3708 adds r7, #8 800de76: 46bd mov sp, r7 800de78: bd80 pop {r7, pc} 800de7a: bf00 nop 800de7c: 20001064 .word 0x20001064 800de80: 0800f4a0 .word 0x0800f4a0 0800de84 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800de84: b580 push {r7, lr} 800de86: b084 sub sp, #16 800de88: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800de8a: 4b0f ldr r3, [pc, #60] @ (800dec8 ) 800de8c: 681b ldr r3, [r3, #0] 800de8e: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800de90: 4b0e ldr r3, [pc, #56] @ (800decc ) 800de92: 681b ldr r3, [r3, #0] 800de94: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800de96: 4b0e ldr r3, [pc, #56] @ (800ded0 ) 800de98: 681b ldr r3, [r3, #0] 800de9a: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800de9c: 68fa ldr r2, [r7, #12] 800de9e: 687b ldr r3, [r7, #4] 800dea0: 4413 add r3, r2 800dea2: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800dea4: 68fb ldr r3, [r7, #12] 800dea6: 2b00 cmp r3, #0 800dea8: d009 beq.n 800debe { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800deaa: 2208 movs r2, #8 800deac: 4909 ldr r1, [pc, #36] @ (800ded4 ) 800deae: 68f8 ldr r0, [r7, #12] 800deb0: f000 f814 bl 800dedc IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800deb4: 2204 movs r2, #4 800deb6: 4908 ldr r1, [pc, #32] @ (800ded8 ) 800deb8: 68b8 ldr r0, [r7, #8] 800deba: f000 f80f bl 800dedc } } 800debe: bf00 nop 800dec0: 3710 adds r7, #16 800dec2: 46bd mov sp, r7 800dec4: bd80 pop {r7, pc} 800dec6: bf00 nop 800dec8: 1ffff7e8 .word 0x1ffff7e8 800decc: 1ffff7ec .word 0x1ffff7ec 800ded0: 1ffff7f0 .word 0x1ffff7f0 800ded4: 20000172 .word 0x20000172 800ded8: 20000182 .word 0x20000182 0800dedc : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800dedc: b480 push {r7} 800dede: b087 sub sp, #28 800dee0: af00 add r7, sp, #0 800dee2: 60f8 str r0, [r7, #12] 800dee4: 60b9 str r1, [r7, #8] 800dee6: 4613 mov r3, r2 800dee8: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800deea: 2300 movs r3, #0 800deec: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800deee: 2300 movs r3, #0 800def0: 75fb strb r3, [r7, #23] 800def2: e027 b.n 800df44 { if (((value >> 28)) < 0xA) 800def4: 68fb ldr r3, [r7, #12] 800def6: 0f1b lsrs r3, r3, #28 800def8: 2b09 cmp r3, #9 800defa: d80b bhi.n 800df14 { pbuf[2 * idx] = (value >> 28) + '0'; 800defc: 68fb ldr r3, [r7, #12] 800defe: 0f1b lsrs r3, r3, #28 800df00: b2da uxtb r2, r3 800df02: 7dfb ldrb r3, [r7, #23] 800df04: 005b lsls r3, r3, #1 800df06: 4619 mov r1, r3 800df08: 68bb ldr r3, [r7, #8] 800df0a: 440b add r3, r1 800df0c: 3230 adds r2, #48 @ 0x30 800df0e: b2d2 uxtb r2, r2 800df10: 701a strb r2, [r3, #0] 800df12: e00a b.n 800df2a } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800df14: 68fb ldr r3, [r7, #12] 800df16: 0f1b lsrs r3, r3, #28 800df18: b2da uxtb r2, r3 800df1a: 7dfb ldrb r3, [r7, #23] 800df1c: 005b lsls r3, r3, #1 800df1e: 4619 mov r1, r3 800df20: 68bb ldr r3, [r7, #8] 800df22: 440b add r3, r1 800df24: 3237 adds r2, #55 @ 0x37 800df26: b2d2 uxtb r2, r2 800df28: 701a strb r2, [r3, #0] } value = value << 4; 800df2a: 68fb ldr r3, [r7, #12] 800df2c: 011b lsls r3, r3, #4 800df2e: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800df30: 7dfb ldrb r3, [r7, #23] 800df32: 005b lsls r3, r3, #1 800df34: 3301 adds r3, #1 800df36: 68ba ldr r2, [r7, #8] 800df38: 4413 add r3, r2 800df3a: 2200 movs r2, #0 800df3c: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800df3e: 7dfb ldrb r3, [r7, #23] 800df40: 3301 adds r3, #1 800df42: 75fb strb r3, [r7, #23] 800df44: 7dfa ldrb r2, [r7, #23] 800df46: 79fb ldrb r3, [r7, #7] 800df48: 429a cmp r2, r3 800df4a: d3d3 bcc.n 800def4 } } 800df4c: bf00 nop 800df4e: bf00 nop 800df50: 371c adds r7, #28 800df52: 46bd mov sp, r7 800df54: bc80 pop {r7} 800df56: 4770 bx lr 0800df58 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800df58: b580 push {r7, lr} 800df5a: b084 sub sp, #16 800df5c: af00 add r7, sp, #0 800df5e: 6078 str r0, [r7, #4] if(pcdHandle->Instance==USB) 800df60: 687b ldr r3, [r7, #4] 800df62: 681b ldr r3, [r3, #0] 800df64: 4a0d ldr r2, [pc, #52] @ (800df9c ) 800df66: 4293 cmp r3, r2 800df68: d113 bne.n 800df92 { /* USER CODE BEGIN USB_MspInit 0 */ /* USER CODE END USB_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USB_CLK_ENABLE(); 800df6a: 4b0d ldr r3, [pc, #52] @ (800dfa0 ) 800df6c: 69db ldr r3, [r3, #28] 800df6e: 4a0c ldr r2, [pc, #48] @ (800dfa0 ) 800df70: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800df74: 61d3 str r3, [r2, #28] 800df76: 4b0a ldr r3, [pc, #40] @ (800dfa0 ) 800df78: 69db ldr r3, [r3, #28] 800df7a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800df7e: 60fb str r3, [r7, #12] 800df80: 68fb ldr r3, [r7, #12] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0); 800df82: 2200 movs r2, #0 800df84: 2100 movs r1, #0 800df86: 2014 movs r0, #20 800df88: f7f7 fddb bl 8005b42 HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); 800df8c: 2014 movs r0, #20 800df8e: f7f7 fdf4 bl 8005b7a /* USER CODE BEGIN USB_MspInit 1 */ /* USER CODE END USB_MspInit 1 */ } } 800df92: bf00 nop 800df94: 3710 adds r7, #16 800df96: 46bd mov sp, r7 800df98: bd80 pop {r7, pc} 800df9a: bf00 nop 800df9c: 40005c00 .word 0x40005c00 800dfa0: 40021000 .word 0x40021000 0800dfa4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800dfa4: b580 push {r7, lr} 800dfa6: b082 sub sp, #8 800dfa8: af00 add r7, sp, #0 800dfaa: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800dfac: 687b ldr r3, [r7, #4] 800dfae: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800dfb2: 687b ldr r3, [r7, #4] 800dfb4: f503 7326 add.w r3, r3, #664 @ 0x298 800dfb8: 4619 mov r1, r3 800dfba: 4610 mov r0, r2 800dfbc: f7fe fd51 bl 800ca62 } 800dfc0: bf00 nop 800dfc2: 3708 adds r7, #8 800dfc4: 46bd mov sp, r7 800dfc6: bd80 pop {r7, pc} 0800dfc8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800dfc8: b580 push {r7, lr} 800dfca: b082 sub sp, #8 800dfcc: af00 add r7, sp, #0 800dfce: 6078 str r0, [r7, #4] 800dfd0: 460b mov r3, r1 800dfd2: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800dfd4: 687b ldr r3, [r7, #4] 800dfd6: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4 800dfda: 78fa ldrb r2, [r7, #3] 800dfdc: 6879 ldr r1, [r7, #4] 800dfde: 4613 mov r3, r2 800dfe0: 009b lsls r3, r3, #2 800dfe2: 4413 add r3, r2 800dfe4: 00db lsls r3, r3, #3 800dfe6: 440b add r3, r1 800dfe8: f503 73b2 add.w r3, r3, #356 @ 0x164 800dfec: 681a ldr r2, [r3, #0] 800dfee: 78fb ldrb r3, [r7, #3] 800dff0: 4619 mov r1, r3 800dff2: f7fe fd83 bl 800cafc } 800dff6: bf00 nop 800dff8: 3708 adds r7, #8 800dffa: 46bd mov sp, r7 800dffc: bd80 pop {r7, pc} 0800dffe : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800dffe: b580 push {r7, lr} 800e000: b082 sub sp, #8 800e002: af00 add r7, sp, #0 800e004: 6078 str r0, [r7, #4] 800e006: 460b mov r3, r1 800e008: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800e00a: 687b ldr r3, [r7, #4] 800e00c: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4 800e010: 78fa ldrb r2, [r7, #3] 800e012: 6879 ldr r1, [r7, #4] 800e014: 4613 mov r3, r2 800e016: 009b lsls r3, r3, #2 800e018: 4413 add r3, r2 800e01a: 00db lsls r3, r3, #3 800e01c: 440b add r3, r1 800e01e: 3324 adds r3, #36 @ 0x24 800e020: 681a ldr r2, [r3, #0] 800e022: 78fb ldrb r3, [r7, #3] 800e024: 4619 mov r1, r3 800e026: f7fe fdda bl 800cbde } 800e02a: bf00 nop 800e02c: 3708 adds r7, #8 800e02e: 46bd mov sp, r7 800e030: bd80 pop {r7, pc} 0800e032 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800e032: b580 push {r7, lr} 800e034: b082 sub sp, #8 800e036: af00 add r7, sp, #0 800e038: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800e03a: 687b ldr r3, [r7, #4] 800e03c: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 800e040: 4618 mov r0, r3 800e042: f7fe feea bl 800ce1a } 800e046: bf00 nop 800e048: 3708 adds r7, #8 800e04a: 46bd mov sp, r7 800e04c: bd80 pop {r7, pc} 0800e04e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800e04e: b580 push {r7, lr} 800e050: b084 sub sp, #16 800e052: af00 add r7, sp, #0 800e054: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800e056: 2301 movs r3, #1 800e058: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed != PCD_SPEED_FULL) 800e05a: 687b ldr r3, [r7, #4] 800e05c: 799b ldrb r3, [r3, #6] 800e05e: 2b02 cmp r3, #2 800e060: d001 beq.n 800e066 { Error_Handler(); 800e062: f7f5 fb81 bl 8003768 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800e066: 687b ldr r3, [r7, #4] 800e068: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 800e06c: 7bfa ldrb r2, [r7, #15] 800e06e: 4611 mov r1, r2 800e070: 4618 mov r0, r3 800e072: f7fe fe9a bl 800cdaa /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800e076: 687b ldr r3, [r7, #4] 800e078: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 800e07c: 4618 mov r0, r3 800e07e: f7fe fe53 bl 800cd28 } 800e082: bf00 nop 800e084: 3710 adds r7, #16 800e086: 46bd mov sp, r7 800e088: bd80 pop {r7, pc} ... 0800e08c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800e08c: b580 push {r7, lr} 800e08e: b082 sub sp, #8 800e090: af00 add r7, sp, #0 800e092: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800e094: 687b ldr r3, [r7, #4] 800e096: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 800e09a: 4618 mov r0, r3 800e09c: f7fe fe94 bl 800cdc8 /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800e0a0: 687b ldr r3, [r7, #4] 800e0a2: 7a9b ldrb r3, [r3, #10] 800e0a4: 2b00 cmp r3, #0 800e0a6: d005 beq.n 800e0b4 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800e0a8: 4b04 ldr r3, [pc, #16] @ (800e0bc ) 800e0aa: 691b ldr r3, [r3, #16] 800e0ac: 4a03 ldr r2, [pc, #12] @ (800e0bc ) 800e0ae: f043 0306 orr.w r3, r3, #6 800e0b2: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800e0b4: bf00 nop 800e0b6: 3708 adds r7, #8 800e0b8: 46bd mov sp, r7 800e0ba: bd80 pop {r7, pc} 800e0bc: e000ed00 .word 0xe000ed00 0800e0c0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800e0c0: b580 push {r7, lr} 800e0c2: b082 sub sp, #8 800e0c4: af00 add r7, sp, #0 800e0c6: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800e0c8: 687b ldr r3, [r7, #4] 800e0ca: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 800e0ce: 4618 mov r0, r3 800e0d0: f7fe fe8e bl 800cdf0 } 800e0d4: bf00 nop 800e0d6: 3708 adds r7, #8 800e0d8: 46bd mov sp, r7 800e0da: bd80 pop {r7, pc} 0800e0dc : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800e0dc: b580 push {r7, lr} 800e0de: b082 sub sp, #8 800e0e0: af00 add r7, sp, #0 800e0e2: 6078 str r0, [r7, #4] /* Init USB Ip. */ /* Link the driver to the stack. */ hpcd_USB_FS.pData = pdev; 800e0e4: 4a28 ldr r2, [pc, #160] @ (800e188 ) 800e0e6: 687b ldr r3, [r7, #4] 800e0e8: f8c2 32d4 str.w r3, [r2, #724] @ 0x2d4 pdev->pData = &hpcd_USB_FS; 800e0ec: 687b ldr r3, [r7, #4] 800e0ee: 4a26 ldr r2, [pc, #152] @ (800e188 ) 800e0f0: f8c3 22c0 str.w r2, [r3, #704] @ 0x2c0 hpcd_USB_FS.Instance = USB; 800e0f4: 4b24 ldr r3, [pc, #144] @ (800e188 ) 800e0f6: 4a25 ldr r2, [pc, #148] @ (800e18c ) 800e0f8: 601a str r2, [r3, #0] hpcd_USB_FS.Init.dev_endpoints = 8; 800e0fa: 4b23 ldr r3, [pc, #140] @ (800e188 ) 800e0fc: 2208 movs r2, #8 800e0fe: 711a strb r2, [r3, #4] hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; 800e100: 4b21 ldr r3, [pc, #132] @ (800e188 ) 800e102: 2202 movs r2, #2 800e104: 719a strb r2, [r3, #6] hpcd_USB_FS.Init.low_power_enable = DISABLE; 800e106: 4b20 ldr r3, [pc, #128] @ (800e188 ) 800e108: 2200 movs r2, #0 800e10a: 729a strb r2, [r3, #10] hpcd_USB_FS.Init.lpm_enable = DISABLE; 800e10c: 4b1e ldr r3, [pc, #120] @ (800e188 ) 800e10e: 2200 movs r2, #0 800e110: 72da strb r2, [r3, #11] hpcd_USB_FS.Init.battery_charging_enable = DISABLE; 800e112: 4b1d ldr r3, [pc, #116] @ (800e188 ) 800e114: 2200 movs r2, #0 800e116: 731a strb r2, [r3, #12] if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) 800e118: 481b ldr r0, [pc, #108] @ (800e188 ) 800e11a: f7f8 faf0 bl 80066fe 800e11e: 4603 mov r3, r0 800e120: 2b00 cmp r3, #0 800e122: d001 beq.n 800e128 { Error_Handler( ); 800e124: f7f5 fb20 bl 8003768 HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* USER CODE BEGIN EndPoint_Configuration */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); 800e128: 687b ldr r3, [r7, #4] 800e12a: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e12e: 2318 movs r3, #24 800e130: 2200 movs r2, #0 800e132: 2100 movs r1, #0 800e134: f7fa f801 bl 800813a HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); 800e138: 687b ldr r3, [r7, #4] 800e13a: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e13e: 2358 movs r3, #88 @ 0x58 800e140: 2200 movs r2, #0 800e142: 2180 movs r1, #128 @ 0x80 800e144: f7f9 fff9 bl 800813a /* USER CODE END EndPoint_Configuration */ /* USER CODE BEGIN EndPoint_Configuration_CDC */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); 800e148: 687b ldr r3, [r7, #4] 800e14a: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e14e: 23c0 movs r3, #192 @ 0xc0 800e150: 2200 movs r2, #0 800e152: 2181 movs r1, #129 @ 0x81 800e154: f7f9 fff1 bl 800813a HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); 800e158: 687b ldr r3, [r7, #4] 800e15a: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e15e: f44f 7388 mov.w r3, #272 @ 0x110 800e162: 2200 movs r2, #0 800e164: 2101 movs r1, #1 800e166: f7f9 ffe8 bl 800813a HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); 800e16a: 687b ldr r3, [r7, #4] 800e16c: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e170: f44f 7380 mov.w r3, #256 @ 0x100 800e174: 2200 movs r2, #0 800e176: 2182 movs r1, #130 @ 0x82 800e178: f7f9 ffdf bl 800813a /* USER CODE END EndPoint_Configuration_CDC */ return USBD_OK; 800e17c: 2300 movs r3, #0 } 800e17e: 4618 mov r0, r3 800e180: 3708 adds r7, #8 800e182: 46bd mov sp, r7 800e184: bd80 pop {r7, pc} 800e186: bf00 nop 800e188: 20001264 .word 0x20001264 800e18c: 40005c00 .word 0x40005c00 0800e190 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800e190: b580 push {r7, lr} 800e192: b084 sub sp, #16 800e194: af00 add r7, sp, #0 800e196: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800e198: 2300 movs r3, #0 800e19a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800e19c: 2300 movs r3, #0 800e19e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800e1a0: 687b ldr r3, [r7, #4] 800e1a2: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e1a6: 4618 mov r0, r3 800e1a8: f7f8 fb9f bl 80068ea 800e1ac: 4603 mov r3, r0 800e1ae: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800e1b0: 7bfb ldrb r3, [r7, #15] 800e1b2: 4618 mov r0, r3 800e1b4: f000 f94e bl 800e454 800e1b8: 4603 mov r3, r0 800e1ba: 73bb strb r3, [r7, #14] return usb_status; 800e1bc: 7bbb ldrb r3, [r7, #14] } 800e1be: 4618 mov r0, r3 800e1c0: 3710 adds r7, #16 800e1c2: 46bd mov sp, r7 800e1c4: bd80 pop {r7, pc} 0800e1c6 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800e1c6: b580 push {r7, lr} 800e1c8: b084 sub sp, #16 800e1ca: af00 add r7, sp, #0 800e1cc: 6078 str r0, [r7, #4] 800e1ce: 4608 mov r0, r1 800e1d0: 4611 mov r1, r2 800e1d2: 461a mov r2, r3 800e1d4: 4603 mov r3, r0 800e1d6: 70fb strb r3, [r7, #3] 800e1d8: 460b mov r3, r1 800e1da: 70bb strb r3, [r7, #2] 800e1dc: 4613 mov r3, r2 800e1de: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800e1e0: 2300 movs r3, #0 800e1e2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800e1e4: 2300 movs r3, #0 800e1e6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800e1e8: 687b ldr r3, [r7, #4] 800e1ea: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e1ee: 78bb ldrb r3, [r7, #2] 800e1f0: 883a ldrh r2, [r7, #0] 800e1f2: 78f9 ldrb r1, [r7, #3] 800e1f4: f7f8 fcf3 bl 8006bde 800e1f8: 4603 mov r3, r0 800e1fa: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800e1fc: 7bfb ldrb r3, [r7, #15] 800e1fe: 4618 mov r0, r3 800e200: f000 f928 bl 800e454 800e204: 4603 mov r3, r0 800e206: 73bb strb r3, [r7, #14] return usb_status; 800e208: 7bbb ldrb r3, [r7, #14] } 800e20a: 4618 mov r0, r3 800e20c: 3710 adds r7, #16 800e20e: 46bd mov sp, r7 800e210: bd80 pop {r7, pc} 0800e212 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800e212: b580 push {r7, lr} 800e214: b084 sub sp, #16 800e216: af00 add r7, sp, #0 800e218: 6078 str r0, [r7, #4] 800e21a: 460b mov r3, r1 800e21c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800e21e: 2300 movs r3, #0 800e220: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800e222: 2300 movs r3, #0 800e224: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800e226: 687b ldr r3, [r7, #4] 800e228: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e22c: 78fa ldrb r2, [r7, #3] 800e22e: 4611 mov r1, r2 800e230: 4618 mov r0, r3 800e232: f7f8 fd31 bl 8006c98 800e236: 4603 mov r3, r0 800e238: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800e23a: 7bfb ldrb r3, [r7, #15] 800e23c: 4618 mov r0, r3 800e23e: f000 f909 bl 800e454 800e242: 4603 mov r3, r0 800e244: 73bb strb r3, [r7, #14] return usb_status; 800e246: 7bbb ldrb r3, [r7, #14] } 800e248: 4618 mov r0, r3 800e24a: 3710 adds r7, #16 800e24c: 46bd mov sp, r7 800e24e: bd80 pop {r7, pc} 0800e250 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800e250: b580 push {r7, lr} 800e252: b084 sub sp, #16 800e254: af00 add r7, sp, #0 800e256: 6078 str r0, [r7, #4] 800e258: 460b mov r3, r1 800e25a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800e25c: 2300 movs r3, #0 800e25e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800e260: 2300 movs r3, #0 800e262: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800e264: 687b ldr r3, [r7, #4] 800e266: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e26a: 78fa ldrb r2, [r7, #3] 800e26c: 4611 mov r1, r2 800e26e: 4618 mov r0, r3 800e270: f7f8 fdd9 bl 8006e26 800e274: 4603 mov r3, r0 800e276: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800e278: 7bfb ldrb r3, [r7, #15] 800e27a: 4618 mov r0, r3 800e27c: f000 f8ea bl 800e454 800e280: 4603 mov r3, r0 800e282: 73bb strb r3, [r7, #14] return usb_status; 800e284: 7bbb ldrb r3, [r7, #14] } 800e286: 4618 mov r0, r3 800e288: 3710 adds r7, #16 800e28a: 46bd mov sp, r7 800e28c: bd80 pop {r7, pc} 0800e28e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800e28e: b580 push {r7, lr} 800e290: b084 sub sp, #16 800e292: af00 add r7, sp, #0 800e294: 6078 str r0, [r7, #4] 800e296: 460b mov r3, r1 800e298: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800e29a: 2300 movs r3, #0 800e29c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800e29e: 2300 movs r3, #0 800e2a0: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800e2a2: 687b ldr r3, [r7, #4] 800e2a4: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e2a8: 78fa ldrb r2, [r7, #3] 800e2aa: 4611 mov r1, r2 800e2ac: 4618 mov r0, r3 800e2ae: f7f8 fe1a bl 8006ee6 800e2b2: 4603 mov r3, r0 800e2b4: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800e2b6: 7bfb ldrb r3, [r7, #15] 800e2b8: 4618 mov r0, r3 800e2ba: f000 f8cb bl 800e454 800e2be: 4603 mov r3, r0 800e2c0: 73bb strb r3, [r7, #14] return usb_status; 800e2c2: 7bbb ldrb r3, [r7, #14] } 800e2c4: 4618 mov r0, r3 800e2c6: 3710 adds r7, #16 800e2c8: 46bd mov sp, r7 800e2ca: bd80 pop {r7, pc} 0800e2cc : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800e2cc: b480 push {r7} 800e2ce: b085 sub sp, #20 800e2d0: af00 add r7, sp, #0 800e2d2: 6078 str r0, [r7, #4] 800e2d4: 460b mov r3, r1 800e2d6: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800e2d8: 687b ldr r3, [r7, #4] 800e2da: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e2de: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800e2e0: f997 3003 ldrsb.w r3, [r7, #3] 800e2e4: 2b00 cmp r3, #0 800e2e6: da0b bge.n 800e300 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800e2e8: 78fb ldrb r3, [r7, #3] 800e2ea: f003 027f and.w r2, r3, #127 @ 0x7f 800e2ee: 68f9 ldr r1, [r7, #12] 800e2f0: 4613 mov r3, r2 800e2f2: 009b lsls r3, r3, #2 800e2f4: 4413 add r3, r2 800e2f6: 00db lsls r3, r3, #3 800e2f8: 440b add r3, r1 800e2fa: 3312 adds r3, #18 800e2fc: 781b ldrb r3, [r3, #0] 800e2fe: e00b b.n 800e318 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800e300: 78fb ldrb r3, [r7, #3] 800e302: f003 027f and.w r2, r3, #127 @ 0x7f 800e306: 68f9 ldr r1, [r7, #12] 800e308: 4613 mov r3, r2 800e30a: 009b lsls r3, r3, #2 800e30c: 4413 add r3, r2 800e30e: 00db lsls r3, r3, #3 800e310: 440b add r3, r1 800e312: f503 73a9 add.w r3, r3, #338 @ 0x152 800e316: 781b ldrb r3, [r3, #0] } } 800e318: 4618 mov r0, r3 800e31a: 3714 adds r7, #20 800e31c: 46bd mov sp, r7 800e31e: bc80 pop {r7} 800e320: 4770 bx lr 0800e322 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800e322: b580 push {r7, lr} 800e324: b084 sub sp, #16 800e326: af00 add r7, sp, #0 800e328: 6078 str r0, [r7, #4] 800e32a: 460b mov r3, r1 800e32c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800e32e: 2300 movs r3, #0 800e330: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800e332: 2300 movs r3, #0 800e334: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800e336: 687b ldr r3, [r7, #4] 800e338: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e33c: 78fa ldrb r2, [r7, #3] 800e33e: 4611 mov r1, r2 800e340: 4618 mov r0, r3 800e342: f7f8 fc28 bl 8006b96 800e346: 4603 mov r3, r0 800e348: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800e34a: 7bfb ldrb r3, [r7, #15] 800e34c: 4618 mov r0, r3 800e34e: f000 f881 bl 800e454 800e352: 4603 mov r3, r0 800e354: 73bb strb r3, [r7, #14] return usb_status; 800e356: 7bbb ldrb r3, [r7, #14] } 800e358: 4618 mov r0, r3 800e35a: 3710 adds r7, #16 800e35c: 46bd mov sp, r7 800e35e: bd80 pop {r7, pc} 0800e360 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) { 800e360: b580 push {r7, lr} 800e362: b086 sub sp, #24 800e364: af00 add r7, sp, #0 800e366: 60f8 str r0, [r7, #12] 800e368: 607a str r2, [r7, #4] 800e36a: 461a mov r2, r3 800e36c: 460b mov r3, r1 800e36e: 72fb strb r3, [r7, #11] 800e370: 4613 mov r3, r2 800e372: 813b strh r3, [r7, #8] HAL_StatusTypeDef hal_status = HAL_OK; 800e374: 2300 movs r3, #0 800e376: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800e378: 2300 movs r3, #0 800e37a: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800e37c: 68fb ldr r3, [r7, #12] 800e37e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e382: 893b ldrh r3, [r7, #8] 800e384: 7af9 ldrb r1, [r7, #11] 800e386: 687a ldr r2, [r7, #4] 800e388: f7f8 fd16 bl 8006db8 800e38c: 4603 mov r3, r0 800e38e: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800e390: 7dfb ldrb r3, [r7, #23] 800e392: 4618 mov r0, r3 800e394: f000 f85e bl 800e454 800e398: 4603 mov r3, r0 800e39a: 75bb strb r3, [r7, #22] return usb_status; 800e39c: 7dbb ldrb r3, [r7, #22] } 800e39e: 4618 mov r0, r3 800e3a0: 3718 adds r7, #24 800e3a2: 46bd mov sp, r7 800e3a4: bd80 pop {r7, pc} 0800e3a6 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) { 800e3a6: b580 push {r7, lr} 800e3a8: b086 sub sp, #24 800e3aa: af00 add r7, sp, #0 800e3ac: 60f8 str r0, [r7, #12] 800e3ae: 607a str r2, [r7, #4] 800e3b0: 461a mov r2, r3 800e3b2: 460b mov r3, r1 800e3b4: 72fb strb r3, [r7, #11] 800e3b6: 4613 mov r3, r2 800e3b8: 813b strh r3, [r7, #8] HAL_StatusTypeDef hal_status = HAL_OK; 800e3ba: 2300 movs r3, #0 800e3bc: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800e3be: 2300 movs r3, #0 800e3c0: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800e3c2: 68fb ldr r3, [r7, #12] 800e3c4: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0 800e3c8: 893b ldrh r3, [r7, #8] 800e3ca: 7af9 ldrb r1, [r7, #11] 800e3cc: 687a ldr r2, [r7, #4] 800e3ce: f7f8 fcab bl 8006d28 800e3d2: 4603 mov r3, r0 800e3d4: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800e3d6: 7dfb ldrb r3, [r7, #23] 800e3d8: 4618 mov r0, r3 800e3da: f000 f83b bl 800e454 800e3de: 4603 mov r3, r0 800e3e0: 75bb strb r3, [r7, #22] return usb_status; 800e3e2: 7dbb ldrb r3, [r7, #22] } 800e3e4: 4618 mov r0, r3 800e3e6: 3718 adds r7, #24 800e3e8: 46bd mov sp, r7 800e3ea: bd80 pop {r7, pc} 0800e3ec : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Received Data Size */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800e3ec: b580 push {r7, lr} 800e3ee: b082 sub sp, #8 800e3f0: af00 add r7, sp, #0 800e3f2: 6078 str r0, [r7, #4] 800e3f4: 460b mov r3, r1 800e3f6: 70fb strb r3, [r7, #3] return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); 800e3f8: 687b ldr r3, [r7, #4] 800e3fa: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0 800e3fe: 78fa ldrb r2, [r7, #3] 800e400: 4611 mov r1, r2 800e402: 4618 mov r0, r3 800e404: f7f8 fcc1 bl 8006d8a 800e408: 4603 mov r3, r0 } 800e40a: 4618 mov r0, r3 800e40c: 3708 adds r7, #8 800e40e: 46bd mov sp, r7 800e410: bd80 pop {r7, pc} ... 0800e414 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800e414: b480 push {r7} 800e416: b083 sub sp, #12 800e418: af00 add r7, sp, #0 800e41a: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800e41c: 4b02 ldr r3, [pc, #8] @ (800e428 ) } 800e41e: 4618 mov r0, r3 800e420: 370c adds r7, #12 800e422: 46bd mov sp, r7 800e424: bc80 pop {r7} 800e426: 4770 bx lr 800e428: 2000153c .word 0x2000153c 0800e42c : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800e42c: b480 push {r7} 800e42e: b083 sub sp, #12 800e430: af00 add r7, sp, #0 800e432: 6078 str r0, [r7, #4] } 800e434: bf00 nop 800e436: 370c adds r7, #12 800e438: 46bd mov sp, r7 800e43a: bc80 pop {r7} 800e43c: 4770 bx lr 0800e43e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) #else void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800e43e: b480 push {r7} 800e440: b083 sub sp, #12 800e442: af00 add r7, sp, #0 800e444: 6078 str r0, [r7, #4] 800e446: 460b mov r3, r1 800e448: 70fb strb r3, [r7, #3] { /* Configure High connection state. */ } /* USER CODE END 6 */ } 800e44a: bf00 nop 800e44c: 370c adds r7, #12 800e44e: 46bd mov sp, r7 800e450: bc80 pop {r7} 800e452: 4770 bx lr 0800e454 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800e454: b480 push {r7} 800e456: b085 sub sp, #20 800e458: af00 add r7, sp, #0 800e45a: 4603 mov r3, r0 800e45c: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800e45e: 2300 movs r3, #0 800e460: 73fb strb r3, [r7, #15] switch (hal_status) 800e462: 79fb ldrb r3, [r7, #7] 800e464: 2b03 cmp r3, #3 800e466: d817 bhi.n 800e498 800e468: a201 add r2, pc, #4 @ (adr r2, 800e470 ) 800e46a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800e46e: bf00 nop 800e470: 0800e481 .word 0x0800e481 800e474: 0800e487 .word 0x0800e487 800e478: 0800e48d .word 0x0800e48d 800e47c: 0800e493 .word 0x0800e493 { case HAL_OK : usb_status = USBD_OK; 800e480: 2300 movs r3, #0 800e482: 73fb strb r3, [r7, #15] break; 800e484: e00b b.n 800e49e case HAL_ERROR : usb_status = USBD_FAIL; 800e486: 2302 movs r3, #2 800e488: 73fb strb r3, [r7, #15] break; 800e48a: e008 b.n 800e49e case HAL_BUSY : usb_status = USBD_BUSY; 800e48c: 2301 movs r3, #1 800e48e: 73fb strb r3, [r7, #15] break; 800e490: e005 b.n 800e49e case HAL_TIMEOUT : usb_status = USBD_FAIL; 800e492: 2302 movs r3, #2 800e494: 73fb strb r3, [r7, #15] break; 800e496: e002 b.n 800e49e default : usb_status = USBD_FAIL; 800e498: 2302 movs r3, #2 800e49a: 73fb strb r3, [r7, #15] break; 800e49c: bf00 nop } return usb_status; 800e49e: 7bfb ldrb r3, [r7, #15] } 800e4a0: 4618 mov r0, r3 800e4a2: 3714 adds r7, #20 800e4a4: 46bd mov sp, r7 800e4a6: bc80 pop {r7} 800e4a8: 4770 bx lr 800e4aa: bf00 nop 0800e4ac : 800e4ac: b40e push {r1, r2, r3} 800e4ae: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000 800e4b2: b510 push {r4, lr} 800e4b4: 2400 movs r4, #0 800e4b6: b09d sub sp, #116 @ 0x74 800e4b8: ab1f add r3, sp, #124 @ 0x7c 800e4ba: 9002 str r0, [sp, #8] 800e4bc: 9006 str r0, [sp, #24] 800e4be: 9107 str r1, [sp, #28] 800e4c0: 9104 str r1, [sp, #16] 800e4c2: 4809 ldr r0, [pc, #36] @ (800e4e8 ) 800e4c4: 4909 ldr r1, [pc, #36] @ (800e4ec ) 800e4c6: f853 2b04 ldr.w r2, [r3], #4 800e4ca: 9105 str r1, [sp, #20] 800e4cc: 6800 ldr r0, [r0, #0] 800e4ce: a902 add r1, sp, #8 800e4d0: 9301 str r3, [sp, #4] 800e4d2: 941b str r4, [sp, #108] @ 0x6c 800e4d4: f000 f992 bl 800e7fc <_svfiprintf_r> 800e4d8: 9b02 ldr r3, [sp, #8] 800e4da: 701c strb r4, [r3, #0] 800e4dc: b01d add sp, #116 @ 0x74 800e4de: e8bd 4010 ldmia.w sp!, {r4, lr} 800e4e2: b003 add sp, #12 800e4e4: 4770 bx lr 800e4e6: bf00 nop 800e4e8: 2000018c .word 0x2000018c 800e4ec: ffff0208 .word 0xffff0208 0800e4f0 : 800e4f0: 4603 mov r3, r0 800e4f2: 4402 add r2, r0 800e4f4: 4293 cmp r3, r2 800e4f6: d100 bne.n 800e4fa 800e4f8: 4770 bx lr 800e4fa: f803 1b01 strb.w r1, [r3], #1 800e4fe: e7f9 b.n 800e4f4 0800e500 <__errno>: 800e500: 4b01 ldr r3, [pc, #4] @ (800e508 <__errno+0x8>) 800e502: 6818 ldr r0, [r3, #0] 800e504: 4770 bx lr 800e506: bf00 nop 800e508: 2000018c .word 0x2000018c 0800e50c <__libc_init_array>: 800e50c: b570 push {r4, r5, r6, lr} 800e50e: 2600 movs r6, #0 800e510: 4d0c ldr r5, [pc, #48] @ (800e544 <__libc_init_array+0x38>) 800e512: 4c0d ldr r4, [pc, #52] @ (800e548 <__libc_init_array+0x3c>) 800e514: 1b64 subs r4, r4, r5 800e516: 10a4 asrs r4, r4, #2 800e518: 42a6 cmp r6, r4 800e51a: d109 bne.n 800e530 <__libc_init_array+0x24> 800e51c: f000 fc76 bl 800ee0c <_init> 800e520: 2600 movs r6, #0 800e522: 4d0a ldr r5, [pc, #40] @ (800e54c <__libc_init_array+0x40>) 800e524: 4c0a ldr r4, [pc, #40] @ (800e550 <__libc_init_array+0x44>) 800e526: 1b64 subs r4, r4, r5 800e528: 10a4 asrs r4, r4, #2 800e52a: 42a6 cmp r6, r4 800e52c: d105 bne.n 800e53a <__libc_init_array+0x2e> 800e52e: bd70 pop {r4, r5, r6, pc} 800e530: f855 3b04 ldr.w r3, [r5], #4 800e534: 4798 blx r3 800e536: 3601 adds r6, #1 800e538: e7ee b.n 800e518 <__libc_init_array+0xc> 800e53a: f855 3b04 ldr.w r3, [r5], #4 800e53e: 4798 blx r3 800e540: 3601 adds r6, #1 800e542: e7f2 b.n 800e52a <__libc_init_array+0x1e> 800e544: 0800f618 .word 0x0800f618 800e548: 0800f618 .word 0x0800f618 800e54c: 0800f618 .word 0x0800f618 800e550: 0800f61c .word 0x0800f61c 0800e554 <__retarget_lock_acquire_recursive>: 800e554: 4770 bx lr 0800e556 <__retarget_lock_release_recursive>: 800e556: 4770 bx lr 0800e558 <_free_r>: 800e558: b538 push {r3, r4, r5, lr} 800e55a: 4605 mov r5, r0 800e55c: 2900 cmp r1, #0 800e55e: d040 beq.n 800e5e2 <_free_r+0x8a> 800e560: f851 3c04 ldr.w r3, [r1, #-4] 800e564: 1f0c subs r4, r1, #4 800e566: 2b00 cmp r3, #0 800e568: bfb8 it lt 800e56a: 18e4 addlt r4, r4, r3 800e56c: f000 f8de bl 800e72c <__malloc_lock> 800e570: 4a1c ldr r2, [pc, #112] @ (800e5e4 <_free_r+0x8c>) 800e572: 6813 ldr r3, [r2, #0] 800e574: b933 cbnz r3, 800e584 <_free_r+0x2c> 800e576: 6063 str r3, [r4, #4] 800e578: 6014 str r4, [r2, #0] 800e57a: 4628 mov r0, r5 800e57c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800e580: f000 b8da b.w 800e738 <__malloc_unlock> 800e584: 42a3 cmp r3, r4 800e586: d908 bls.n 800e59a <_free_r+0x42> 800e588: 6820 ldr r0, [r4, #0] 800e58a: 1821 adds r1, r4, r0 800e58c: 428b cmp r3, r1 800e58e: bf01 itttt eq 800e590: 6819 ldreq r1, [r3, #0] 800e592: 685b ldreq r3, [r3, #4] 800e594: 1809 addeq r1, r1, r0 800e596: 6021 streq r1, [r4, #0] 800e598: e7ed b.n 800e576 <_free_r+0x1e> 800e59a: 461a mov r2, r3 800e59c: 685b ldr r3, [r3, #4] 800e59e: b10b cbz r3, 800e5a4 <_free_r+0x4c> 800e5a0: 42a3 cmp r3, r4 800e5a2: d9fa bls.n 800e59a <_free_r+0x42> 800e5a4: 6811 ldr r1, [r2, #0] 800e5a6: 1850 adds r0, r2, r1 800e5a8: 42a0 cmp r0, r4 800e5aa: d10b bne.n 800e5c4 <_free_r+0x6c> 800e5ac: 6820 ldr r0, [r4, #0] 800e5ae: 4401 add r1, r0 800e5b0: 1850 adds r0, r2, r1 800e5b2: 4283 cmp r3, r0 800e5b4: 6011 str r1, [r2, #0] 800e5b6: d1e0 bne.n 800e57a <_free_r+0x22> 800e5b8: 6818 ldr r0, [r3, #0] 800e5ba: 685b ldr r3, [r3, #4] 800e5bc: 4408 add r0, r1 800e5be: 6010 str r0, [r2, #0] 800e5c0: 6053 str r3, [r2, #4] 800e5c2: e7da b.n 800e57a <_free_r+0x22> 800e5c4: d902 bls.n 800e5cc <_free_r+0x74> 800e5c6: 230c movs r3, #12 800e5c8: 602b str r3, [r5, #0] 800e5ca: e7d6 b.n 800e57a <_free_r+0x22> 800e5cc: 6820 ldr r0, [r4, #0] 800e5ce: 1821 adds r1, r4, r0 800e5d0: 428b cmp r3, r1 800e5d2: bf01 itttt eq 800e5d4: 6819 ldreq r1, [r3, #0] 800e5d6: 685b ldreq r3, [r3, #4] 800e5d8: 1809 addeq r1, r1, r0 800e5da: 6021 streq r1, [r4, #0] 800e5dc: 6063 str r3, [r4, #4] 800e5de: 6054 str r4, [r2, #4] 800e5e0: e7cb b.n 800e57a <_free_r+0x22> 800e5e2: bd38 pop {r3, r4, r5, pc} 800e5e4: 200018a0 .word 0x200018a0 0800e5e8 : 800e5e8: b570 push {r4, r5, r6, lr} 800e5ea: 4e0f ldr r6, [pc, #60] @ (800e628 ) 800e5ec: 460c mov r4, r1 800e5ee: 6831 ldr r1, [r6, #0] 800e5f0: 4605 mov r5, r0 800e5f2: b911 cbnz r1, 800e5fa 800e5f4: f000 fba8 bl 800ed48 <_sbrk_r> 800e5f8: 6030 str r0, [r6, #0] 800e5fa: 4621 mov r1, r4 800e5fc: 4628 mov r0, r5 800e5fe: f000 fba3 bl 800ed48 <_sbrk_r> 800e602: 1c43 adds r3, r0, #1 800e604: d103 bne.n 800e60e 800e606: f04f 34ff mov.w r4, #4294967295 800e60a: 4620 mov r0, r4 800e60c: bd70 pop {r4, r5, r6, pc} 800e60e: 1cc4 adds r4, r0, #3 800e610: f024 0403 bic.w r4, r4, #3 800e614: 42a0 cmp r0, r4 800e616: d0f8 beq.n 800e60a 800e618: 1a21 subs r1, r4, r0 800e61a: 4628 mov r0, r5 800e61c: f000 fb94 bl 800ed48 <_sbrk_r> 800e620: 3001 adds r0, #1 800e622: d1f2 bne.n 800e60a 800e624: e7ef b.n 800e606 800e626: bf00 nop 800e628: 2000189c .word 0x2000189c 0800e62c <_malloc_r>: 800e62c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800e630: 1ccd adds r5, r1, #3 800e632: f025 0503 bic.w r5, r5, #3 800e636: 3508 adds r5, #8 800e638: 2d0c cmp r5, #12 800e63a: bf38 it cc 800e63c: 250c movcc r5, #12 800e63e: 2d00 cmp r5, #0 800e640: 4606 mov r6, r0 800e642: db01 blt.n 800e648 <_malloc_r+0x1c> 800e644: 42a9 cmp r1, r5 800e646: d904 bls.n 800e652 <_malloc_r+0x26> 800e648: 230c movs r3, #12 800e64a: 6033 str r3, [r6, #0] 800e64c: 2000 movs r0, #0 800e64e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800e652: f8df 80d4 ldr.w r8, [pc, #212] @ 800e728 <_malloc_r+0xfc> 800e656: f000 f869 bl 800e72c <__malloc_lock> 800e65a: f8d8 3000 ldr.w r3, [r8] 800e65e: 461c mov r4, r3 800e660: bb44 cbnz r4, 800e6b4 <_malloc_r+0x88> 800e662: 4629 mov r1, r5 800e664: 4630 mov r0, r6 800e666: f7ff ffbf bl 800e5e8 800e66a: 1c43 adds r3, r0, #1 800e66c: 4604 mov r4, r0 800e66e: d158 bne.n 800e722 <_malloc_r+0xf6> 800e670: f8d8 4000 ldr.w r4, [r8] 800e674: 4627 mov r7, r4 800e676: 2f00 cmp r7, #0 800e678: d143 bne.n 800e702 <_malloc_r+0xd6> 800e67a: 2c00 cmp r4, #0 800e67c: d04b beq.n 800e716 <_malloc_r+0xea> 800e67e: 6823 ldr r3, [r4, #0] 800e680: 4639 mov r1, r7 800e682: 4630 mov r0, r6 800e684: eb04 0903 add.w r9, r4, r3 800e688: f000 fb5e bl 800ed48 <_sbrk_r> 800e68c: 4581 cmp r9, r0 800e68e: d142 bne.n 800e716 <_malloc_r+0xea> 800e690: 6821 ldr r1, [r4, #0] 800e692: 4630 mov r0, r6 800e694: 1a6d subs r5, r5, r1 800e696: 4629 mov r1, r5 800e698: f7ff ffa6 bl 800e5e8 800e69c: 3001 adds r0, #1 800e69e: d03a beq.n 800e716 <_malloc_r+0xea> 800e6a0: 6823 ldr r3, [r4, #0] 800e6a2: 442b add r3, r5 800e6a4: 6023 str r3, [r4, #0] 800e6a6: f8d8 3000 ldr.w r3, [r8] 800e6aa: 685a ldr r2, [r3, #4] 800e6ac: bb62 cbnz r2, 800e708 <_malloc_r+0xdc> 800e6ae: f8c8 7000 str.w r7, [r8] 800e6b2: e00f b.n 800e6d4 <_malloc_r+0xa8> 800e6b4: 6822 ldr r2, [r4, #0] 800e6b6: 1b52 subs r2, r2, r5 800e6b8: d420 bmi.n 800e6fc <_malloc_r+0xd0> 800e6ba: 2a0b cmp r2, #11 800e6bc: d917 bls.n 800e6ee <_malloc_r+0xc2> 800e6be: 1961 adds r1, r4, r5 800e6c0: 42a3 cmp r3, r4 800e6c2: 6025 str r5, [r4, #0] 800e6c4: bf18 it ne 800e6c6: 6059 strne r1, [r3, #4] 800e6c8: 6863 ldr r3, [r4, #4] 800e6ca: bf08 it eq 800e6cc: f8c8 1000 streq.w r1, [r8] 800e6d0: 5162 str r2, [r4, r5] 800e6d2: 604b str r3, [r1, #4] 800e6d4: 4630 mov r0, r6 800e6d6: f000 f82f bl 800e738 <__malloc_unlock> 800e6da: f104 000b add.w r0, r4, #11 800e6de: 1d23 adds r3, r4, #4 800e6e0: f020 0007 bic.w r0, r0, #7 800e6e4: 1ac2 subs r2, r0, r3 800e6e6: bf1c itt ne 800e6e8: 1a1b subne r3, r3, r0 800e6ea: 50a3 strne r3, [r4, r2] 800e6ec: e7af b.n 800e64e <_malloc_r+0x22> 800e6ee: 6862 ldr r2, [r4, #4] 800e6f0: 42a3 cmp r3, r4 800e6f2: bf0c ite eq 800e6f4: f8c8 2000 streq.w r2, [r8] 800e6f8: 605a strne r2, [r3, #4] 800e6fa: e7eb b.n 800e6d4 <_malloc_r+0xa8> 800e6fc: 4623 mov r3, r4 800e6fe: 6864 ldr r4, [r4, #4] 800e700: e7ae b.n 800e660 <_malloc_r+0x34> 800e702: 463c mov r4, r7 800e704: 687f ldr r7, [r7, #4] 800e706: e7b6 b.n 800e676 <_malloc_r+0x4a> 800e708: 461a mov r2, r3 800e70a: 685b ldr r3, [r3, #4] 800e70c: 42a3 cmp r3, r4 800e70e: d1fb bne.n 800e708 <_malloc_r+0xdc> 800e710: 2300 movs r3, #0 800e712: 6053 str r3, [r2, #4] 800e714: e7de b.n 800e6d4 <_malloc_r+0xa8> 800e716: 230c movs r3, #12 800e718: 4630 mov r0, r6 800e71a: 6033 str r3, [r6, #0] 800e71c: f000 f80c bl 800e738 <__malloc_unlock> 800e720: e794 b.n 800e64c <_malloc_r+0x20> 800e722: 6005 str r5, [r0, #0] 800e724: e7d6 b.n 800e6d4 <_malloc_r+0xa8> 800e726: bf00 nop 800e728: 200018a0 .word 0x200018a0 0800e72c <__malloc_lock>: 800e72c: 4801 ldr r0, [pc, #4] @ (800e734 <__malloc_lock+0x8>) 800e72e: f7ff bf11 b.w 800e554 <__retarget_lock_acquire_recursive> 800e732: bf00 nop 800e734: 20001898 .word 0x20001898 0800e738 <__malloc_unlock>: 800e738: 4801 ldr r0, [pc, #4] @ (800e740 <__malloc_unlock+0x8>) 800e73a: f7ff bf0c b.w 800e556 <__retarget_lock_release_recursive> 800e73e: bf00 nop 800e740: 20001898 .word 0x20001898 0800e744 <__ssputs_r>: 800e744: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800e748: 461f mov r7, r3 800e74a: 688e ldr r6, [r1, #8] 800e74c: 4682 mov sl, r0 800e74e: 42be cmp r6, r7 800e750: 460c mov r4, r1 800e752: 4690 mov r8, r2 800e754: 680b ldr r3, [r1, #0] 800e756: d82d bhi.n 800e7b4 <__ssputs_r+0x70> 800e758: f9b1 200c ldrsh.w r2, [r1, #12] 800e75c: f412 6f90 tst.w r2, #1152 @ 0x480 800e760: d026 beq.n 800e7b0 <__ssputs_r+0x6c> 800e762: 6965 ldr r5, [r4, #20] 800e764: 6909 ldr r1, [r1, #16] 800e766: eb05 0545 add.w r5, r5, r5, lsl #1 800e76a: eba3 0901 sub.w r9, r3, r1 800e76e: eb05 75d5 add.w r5, r5, r5, lsr #31 800e772: 1c7b adds r3, r7, #1 800e774: 444b add r3, r9 800e776: 106d asrs r5, r5, #1 800e778: 429d cmp r5, r3 800e77a: bf38 it cc 800e77c: 461d movcc r5, r3 800e77e: 0553 lsls r3, r2, #21 800e780: d527 bpl.n 800e7d2 <__ssputs_r+0x8e> 800e782: 4629 mov r1, r5 800e784: f7ff ff52 bl 800e62c <_malloc_r> 800e788: 4606 mov r6, r0 800e78a: b360 cbz r0, 800e7e6 <__ssputs_r+0xa2> 800e78c: 464a mov r2, r9 800e78e: 6921 ldr r1, [r4, #16] 800e790: f000 faf8 bl 800ed84 800e794: 89a3 ldrh r3, [r4, #12] 800e796: f423 6390 bic.w r3, r3, #1152 @ 0x480 800e79a: f043 0380 orr.w r3, r3, #128 @ 0x80 800e79e: 81a3 strh r3, [r4, #12] 800e7a0: 6126 str r6, [r4, #16] 800e7a2: 444e add r6, r9 800e7a4: 6026 str r6, [r4, #0] 800e7a6: 463e mov r6, r7 800e7a8: 6165 str r5, [r4, #20] 800e7aa: eba5 0509 sub.w r5, r5, r9 800e7ae: 60a5 str r5, [r4, #8] 800e7b0: 42be cmp r6, r7 800e7b2: d900 bls.n 800e7b6 <__ssputs_r+0x72> 800e7b4: 463e mov r6, r7 800e7b6: 4632 mov r2, r6 800e7b8: 4641 mov r1, r8 800e7ba: 6820 ldr r0, [r4, #0] 800e7bc: f000 faaa bl 800ed14 800e7c0: 2000 movs r0, #0 800e7c2: 68a3 ldr r3, [r4, #8] 800e7c4: 1b9b subs r3, r3, r6 800e7c6: 60a3 str r3, [r4, #8] 800e7c8: 6823 ldr r3, [r4, #0] 800e7ca: 4433 add r3, r6 800e7cc: 6023 str r3, [r4, #0] 800e7ce: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800e7d2: 462a mov r2, r5 800e7d4: f000 fae4 bl 800eda0 <_realloc_r> 800e7d8: 4606 mov r6, r0 800e7da: 2800 cmp r0, #0 800e7dc: d1e0 bne.n 800e7a0 <__ssputs_r+0x5c> 800e7de: 4650 mov r0, sl 800e7e0: 6921 ldr r1, [r4, #16] 800e7e2: f7ff feb9 bl 800e558 <_free_r> 800e7e6: 230c movs r3, #12 800e7e8: f8ca 3000 str.w r3, [sl] 800e7ec: 89a3 ldrh r3, [r4, #12] 800e7ee: f04f 30ff mov.w r0, #4294967295 800e7f2: f043 0340 orr.w r3, r3, #64 @ 0x40 800e7f6: 81a3 strh r3, [r4, #12] 800e7f8: e7e9 b.n 800e7ce <__ssputs_r+0x8a> ... 0800e7fc <_svfiprintf_r>: 800e7fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800e800: 4698 mov r8, r3 800e802: 898b ldrh r3, [r1, #12] 800e804: 4607 mov r7, r0 800e806: 061b lsls r3, r3, #24 800e808: 460d mov r5, r1 800e80a: 4614 mov r4, r2 800e80c: b09d sub sp, #116 @ 0x74 800e80e: d510 bpl.n 800e832 <_svfiprintf_r+0x36> 800e810: 690b ldr r3, [r1, #16] 800e812: b973 cbnz r3, 800e832 <_svfiprintf_r+0x36> 800e814: 2140 movs r1, #64 @ 0x40 800e816: f7ff ff09 bl 800e62c <_malloc_r> 800e81a: 6028 str r0, [r5, #0] 800e81c: 6128 str r0, [r5, #16] 800e81e: b930 cbnz r0, 800e82e <_svfiprintf_r+0x32> 800e820: 230c movs r3, #12 800e822: 603b str r3, [r7, #0] 800e824: f04f 30ff mov.w r0, #4294967295 800e828: b01d add sp, #116 @ 0x74 800e82a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800e82e: 2340 movs r3, #64 @ 0x40 800e830: 616b str r3, [r5, #20] 800e832: 2300 movs r3, #0 800e834: 9309 str r3, [sp, #36] @ 0x24 800e836: 2320 movs r3, #32 800e838: f88d 3029 strb.w r3, [sp, #41] @ 0x29 800e83c: 2330 movs r3, #48 @ 0x30 800e83e: f04f 0901 mov.w r9, #1 800e842: f8cd 800c str.w r8, [sp, #12] 800e846: f8df 8198 ldr.w r8, [pc, #408] @ 800e9e0 <_svfiprintf_r+0x1e4> 800e84a: f88d 302a strb.w r3, [sp, #42] @ 0x2a 800e84e: 4623 mov r3, r4 800e850: 469a mov sl, r3 800e852: f813 2b01 ldrb.w r2, [r3], #1 800e856: b10a cbz r2, 800e85c <_svfiprintf_r+0x60> 800e858: 2a25 cmp r2, #37 @ 0x25 800e85a: d1f9 bne.n 800e850 <_svfiprintf_r+0x54> 800e85c: ebba 0b04 subs.w fp, sl, r4 800e860: d00b beq.n 800e87a <_svfiprintf_r+0x7e> 800e862: 465b mov r3, fp 800e864: 4622 mov r2, r4 800e866: 4629 mov r1, r5 800e868: 4638 mov r0, r7 800e86a: f7ff ff6b bl 800e744 <__ssputs_r> 800e86e: 3001 adds r0, #1 800e870: f000 80a7 beq.w 800e9c2 <_svfiprintf_r+0x1c6> 800e874: 9a09 ldr r2, [sp, #36] @ 0x24 800e876: 445a add r2, fp 800e878: 9209 str r2, [sp, #36] @ 0x24 800e87a: f89a 3000 ldrb.w r3, [sl] 800e87e: 2b00 cmp r3, #0 800e880: f000 809f beq.w 800e9c2 <_svfiprintf_r+0x1c6> 800e884: 2300 movs r3, #0 800e886: f04f 32ff mov.w r2, #4294967295 800e88a: e9cd 2305 strd r2, r3, [sp, #20] 800e88e: f10a 0a01 add.w sl, sl, #1 800e892: 9304 str r3, [sp, #16] 800e894: 9307 str r3, [sp, #28] 800e896: f88d 3053 strb.w r3, [sp, #83] @ 0x53 800e89a: 931a str r3, [sp, #104] @ 0x68 800e89c: 4654 mov r4, sl 800e89e: 2205 movs r2, #5 800e8a0: f814 1b01 ldrb.w r1, [r4], #1 800e8a4: 484e ldr r0, [pc, #312] @ (800e9e0 <_svfiprintf_r+0x1e4>) 800e8a6: f000 fa5f bl 800ed68 800e8aa: 9a04 ldr r2, [sp, #16] 800e8ac: b9d8 cbnz r0, 800e8e6 <_svfiprintf_r+0xea> 800e8ae: 06d0 lsls r0, r2, #27 800e8b0: bf44 itt mi 800e8b2: 2320 movmi r3, #32 800e8b4: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800e8b8: 0711 lsls r1, r2, #28 800e8ba: bf44 itt mi 800e8bc: 232b movmi r3, #43 @ 0x2b 800e8be: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800e8c2: f89a 3000 ldrb.w r3, [sl] 800e8c6: 2b2a cmp r3, #42 @ 0x2a 800e8c8: d015 beq.n 800e8f6 <_svfiprintf_r+0xfa> 800e8ca: 4654 mov r4, sl 800e8cc: 2000 movs r0, #0 800e8ce: f04f 0c0a mov.w ip, #10 800e8d2: 9a07 ldr r2, [sp, #28] 800e8d4: 4621 mov r1, r4 800e8d6: f811 3b01 ldrb.w r3, [r1], #1 800e8da: 3b30 subs r3, #48 @ 0x30 800e8dc: 2b09 cmp r3, #9 800e8de: d94b bls.n 800e978 <_svfiprintf_r+0x17c> 800e8e0: b1b0 cbz r0, 800e910 <_svfiprintf_r+0x114> 800e8e2: 9207 str r2, [sp, #28] 800e8e4: e014 b.n 800e910 <_svfiprintf_r+0x114> 800e8e6: eba0 0308 sub.w r3, r0, r8 800e8ea: fa09 f303 lsl.w r3, r9, r3 800e8ee: 4313 orrs r3, r2 800e8f0: 46a2 mov sl, r4 800e8f2: 9304 str r3, [sp, #16] 800e8f4: e7d2 b.n 800e89c <_svfiprintf_r+0xa0> 800e8f6: 9b03 ldr r3, [sp, #12] 800e8f8: 1d19 adds r1, r3, #4 800e8fa: 681b ldr r3, [r3, #0] 800e8fc: 9103 str r1, [sp, #12] 800e8fe: 2b00 cmp r3, #0 800e900: bfbb ittet lt 800e902: 425b neglt r3, r3 800e904: f042 0202 orrlt.w r2, r2, #2 800e908: 9307 strge r3, [sp, #28] 800e90a: 9307 strlt r3, [sp, #28] 800e90c: bfb8 it lt 800e90e: 9204 strlt r2, [sp, #16] 800e910: 7823 ldrb r3, [r4, #0] 800e912: 2b2e cmp r3, #46 @ 0x2e 800e914: d10a bne.n 800e92c <_svfiprintf_r+0x130> 800e916: 7863 ldrb r3, [r4, #1] 800e918: 2b2a cmp r3, #42 @ 0x2a 800e91a: d132 bne.n 800e982 <_svfiprintf_r+0x186> 800e91c: 9b03 ldr r3, [sp, #12] 800e91e: 3402 adds r4, #2 800e920: 1d1a adds r2, r3, #4 800e922: 681b ldr r3, [r3, #0] 800e924: 9203 str r2, [sp, #12] 800e926: ea43 73e3 orr.w r3, r3, r3, asr #31 800e92a: 9305 str r3, [sp, #20] 800e92c: f8df a0b4 ldr.w sl, [pc, #180] @ 800e9e4 <_svfiprintf_r+0x1e8> 800e930: 2203 movs r2, #3 800e932: 4650 mov r0, sl 800e934: 7821 ldrb r1, [r4, #0] 800e936: f000 fa17 bl 800ed68 800e93a: b138 cbz r0, 800e94c <_svfiprintf_r+0x150> 800e93c: 2240 movs r2, #64 @ 0x40 800e93e: 9b04 ldr r3, [sp, #16] 800e940: eba0 000a sub.w r0, r0, sl 800e944: 4082 lsls r2, r0 800e946: 4313 orrs r3, r2 800e948: 3401 adds r4, #1 800e94a: 9304 str r3, [sp, #16] 800e94c: f814 1b01 ldrb.w r1, [r4], #1 800e950: 2206 movs r2, #6 800e952: 4825 ldr r0, [pc, #148] @ (800e9e8 <_svfiprintf_r+0x1ec>) 800e954: f88d 1028 strb.w r1, [sp, #40] @ 0x28 800e958: f000 fa06 bl 800ed68 800e95c: 2800 cmp r0, #0 800e95e: d036 beq.n 800e9ce <_svfiprintf_r+0x1d2> 800e960: 4b22 ldr r3, [pc, #136] @ (800e9ec <_svfiprintf_r+0x1f0>) 800e962: bb1b cbnz r3, 800e9ac <_svfiprintf_r+0x1b0> 800e964: 9b03 ldr r3, [sp, #12] 800e966: 3307 adds r3, #7 800e968: f023 0307 bic.w r3, r3, #7 800e96c: 3308 adds r3, #8 800e96e: 9303 str r3, [sp, #12] 800e970: 9b09 ldr r3, [sp, #36] @ 0x24 800e972: 4433 add r3, r6 800e974: 9309 str r3, [sp, #36] @ 0x24 800e976: e76a b.n 800e84e <_svfiprintf_r+0x52> 800e978: 460c mov r4, r1 800e97a: 2001 movs r0, #1 800e97c: fb0c 3202 mla r2, ip, r2, r3 800e980: e7a8 b.n 800e8d4 <_svfiprintf_r+0xd8> 800e982: 2300 movs r3, #0 800e984: f04f 0c0a mov.w ip, #10 800e988: 4619 mov r1, r3 800e98a: 3401 adds r4, #1 800e98c: 9305 str r3, [sp, #20] 800e98e: 4620 mov r0, r4 800e990: f810 2b01 ldrb.w r2, [r0], #1 800e994: 3a30 subs r2, #48 @ 0x30 800e996: 2a09 cmp r2, #9 800e998: d903 bls.n 800e9a2 <_svfiprintf_r+0x1a6> 800e99a: 2b00 cmp r3, #0 800e99c: d0c6 beq.n 800e92c <_svfiprintf_r+0x130> 800e99e: 9105 str r1, [sp, #20] 800e9a0: e7c4 b.n 800e92c <_svfiprintf_r+0x130> 800e9a2: 4604 mov r4, r0 800e9a4: 2301 movs r3, #1 800e9a6: fb0c 2101 mla r1, ip, r1, r2 800e9aa: e7f0 b.n 800e98e <_svfiprintf_r+0x192> 800e9ac: ab03 add r3, sp, #12 800e9ae: 9300 str r3, [sp, #0] 800e9b0: 462a mov r2, r5 800e9b2: 4638 mov r0, r7 800e9b4: 4b0e ldr r3, [pc, #56] @ (800e9f0 <_svfiprintf_r+0x1f4>) 800e9b6: a904 add r1, sp, #16 800e9b8: f3af 8000 nop.w 800e9bc: 1c42 adds r2, r0, #1 800e9be: 4606 mov r6, r0 800e9c0: d1d6 bne.n 800e970 <_svfiprintf_r+0x174> 800e9c2: 89ab ldrh r3, [r5, #12] 800e9c4: 065b lsls r3, r3, #25 800e9c6: f53f af2d bmi.w 800e824 <_svfiprintf_r+0x28> 800e9ca: 9809 ldr r0, [sp, #36] @ 0x24 800e9cc: e72c b.n 800e828 <_svfiprintf_r+0x2c> 800e9ce: ab03 add r3, sp, #12 800e9d0: 9300 str r3, [sp, #0] 800e9d2: 462a mov r2, r5 800e9d4: 4638 mov r0, r7 800e9d6: 4b06 ldr r3, [pc, #24] @ (800e9f0 <_svfiprintf_r+0x1f4>) 800e9d8: a904 add r1, sp, #16 800e9da: f000 f87d bl 800ead8 <_printf_i> 800e9de: e7ed b.n 800e9bc <_svfiprintf_r+0x1c0> 800e9e0: 0800f5da .word 0x0800f5da 800e9e4: 0800f5e0 .word 0x0800f5e0 800e9e8: 0800f5e4 .word 0x0800f5e4 800e9ec: 00000000 .word 0x00000000 800e9f0: 0800e745 .word 0x0800e745 0800e9f4 <_printf_common>: 800e9f4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800e9f8: 4616 mov r6, r2 800e9fa: 4698 mov r8, r3 800e9fc: 688a ldr r2, [r1, #8] 800e9fe: 690b ldr r3, [r1, #16] 800ea00: 4607 mov r7, r0 800ea02: 4293 cmp r3, r2 800ea04: bfb8 it lt 800ea06: 4613 movlt r3, r2 800ea08: 6033 str r3, [r6, #0] 800ea0a: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 800ea0e: 460c mov r4, r1 800ea10: f8dd 9020 ldr.w r9, [sp, #32] 800ea14: b10a cbz r2, 800ea1a <_printf_common+0x26> 800ea16: 3301 adds r3, #1 800ea18: 6033 str r3, [r6, #0] 800ea1a: 6823 ldr r3, [r4, #0] 800ea1c: 0699 lsls r1, r3, #26 800ea1e: bf42 ittt mi 800ea20: 6833 ldrmi r3, [r6, #0] 800ea22: 3302 addmi r3, #2 800ea24: 6033 strmi r3, [r6, #0] 800ea26: 6825 ldr r5, [r4, #0] 800ea28: f015 0506 ands.w r5, r5, #6 800ea2c: d106 bne.n 800ea3c <_printf_common+0x48> 800ea2e: f104 0a19 add.w sl, r4, #25 800ea32: 68e3 ldr r3, [r4, #12] 800ea34: 6832 ldr r2, [r6, #0] 800ea36: 1a9b subs r3, r3, r2 800ea38: 42ab cmp r3, r5 800ea3a: dc2b bgt.n 800ea94 <_printf_common+0xa0> 800ea3c: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 800ea40: 6822 ldr r2, [r4, #0] 800ea42: 3b00 subs r3, #0 800ea44: bf18 it ne 800ea46: 2301 movne r3, #1 800ea48: 0692 lsls r2, r2, #26 800ea4a: d430 bmi.n 800eaae <_printf_common+0xba> 800ea4c: 4641 mov r1, r8 800ea4e: 4638 mov r0, r7 800ea50: f104 0243 add.w r2, r4, #67 @ 0x43 800ea54: 47c8 blx r9 800ea56: 3001 adds r0, #1 800ea58: d023 beq.n 800eaa2 <_printf_common+0xae> 800ea5a: 6823 ldr r3, [r4, #0] 800ea5c: 6922 ldr r2, [r4, #16] 800ea5e: f003 0306 and.w r3, r3, #6 800ea62: 2b04 cmp r3, #4 800ea64: bf14 ite ne 800ea66: 2500 movne r5, #0 800ea68: 6833 ldreq r3, [r6, #0] 800ea6a: f04f 0600 mov.w r6, #0 800ea6e: bf08 it eq 800ea70: 68e5 ldreq r5, [r4, #12] 800ea72: f104 041a add.w r4, r4, #26 800ea76: bf08 it eq 800ea78: 1aed subeq r5, r5, r3 800ea7a: f854 3c12 ldr.w r3, [r4, #-18] 800ea7e: bf08 it eq 800ea80: ea25 75e5 biceq.w r5, r5, r5, asr #31 800ea84: 4293 cmp r3, r2 800ea86: bfc4 itt gt 800ea88: 1a9b subgt r3, r3, r2 800ea8a: 18ed addgt r5, r5, r3 800ea8c: 42b5 cmp r5, r6 800ea8e: d11a bne.n 800eac6 <_printf_common+0xd2> 800ea90: 2000 movs r0, #0 800ea92: e008 b.n 800eaa6 <_printf_common+0xb2> 800ea94: 2301 movs r3, #1 800ea96: 4652 mov r2, sl 800ea98: 4641 mov r1, r8 800ea9a: 4638 mov r0, r7 800ea9c: 47c8 blx r9 800ea9e: 3001 adds r0, #1 800eaa0: d103 bne.n 800eaaa <_printf_common+0xb6> 800eaa2: f04f 30ff mov.w r0, #4294967295 800eaa6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800eaaa: 3501 adds r5, #1 800eaac: e7c1 b.n 800ea32 <_printf_common+0x3e> 800eaae: 2030 movs r0, #48 @ 0x30 800eab0: 18e1 adds r1, r4, r3 800eab2: f881 0043 strb.w r0, [r1, #67] @ 0x43 800eab6: 1c5a adds r2, r3, #1 800eab8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 800eabc: 4422 add r2, r4 800eabe: 3302 adds r3, #2 800eac0: f882 1043 strb.w r1, [r2, #67] @ 0x43 800eac4: e7c2 b.n 800ea4c <_printf_common+0x58> 800eac6: 2301 movs r3, #1 800eac8: 4622 mov r2, r4 800eaca: 4641 mov r1, r8 800eacc: 4638 mov r0, r7 800eace: 47c8 blx r9 800ead0: 3001 adds r0, #1 800ead2: d0e6 beq.n 800eaa2 <_printf_common+0xae> 800ead4: 3601 adds r6, #1 800ead6: e7d9 b.n 800ea8c <_printf_common+0x98> 0800ead8 <_printf_i>: 800ead8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 800eadc: 7e0f ldrb r7, [r1, #24] 800eade: 4691 mov r9, r2 800eae0: 2f78 cmp r7, #120 @ 0x78 800eae2: 4680 mov r8, r0 800eae4: 460c mov r4, r1 800eae6: 469a mov sl, r3 800eae8: 9e0c ldr r6, [sp, #48] @ 0x30 800eaea: f101 0243 add.w r2, r1, #67 @ 0x43 800eaee: d807 bhi.n 800eb00 <_printf_i+0x28> 800eaf0: 2f62 cmp r7, #98 @ 0x62 800eaf2: d80a bhi.n 800eb0a <_printf_i+0x32> 800eaf4: 2f00 cmp r7, #0 800eaf6: f000 80d1 beq.w 800ec9c <_printf_i+0x1c4> 800eafa: 2f58 cmp r7, #88 @ 0x58 800eafc: f000 80b8 beq.w 800ec70 <_printf_i+0x198> 800eb00: f104 0642 add.w r6, r4, #66 @ 0x42 800eb04: f884 7042 strb.w r7, [r4, #66] @ 0x42 800eb08: e03a b.n 800eb80 <_printf_i+0xa8> 800eb0a: f1a7 0363 sub.w r3, r7, #99 @ 0x63 800eb0e: 2b15 cmp r3, #21 800eb10: d8f6 bhi.n 800eb00 <_printf_i+0x28> 800eb12: a101 add r1, pc, #4 @ (adr r1, 800eb18 <_printf_i+0x40>) 800eb14: f851 f023 ldr.w pc, [r1, r3, lsl #2] 800eb18: 0800eb71 .word 0x0800eb71 800eb1c: 0800eb85 .word 0x0800eb85 800eb20: 0800eb01 .word 0x0800eb01 800eb24: 0800eb01 .word 0x0800eb01 800eb28: 0800eb01 .word 0x0800eb01 800eb2c: 0800eb01 .word 0x0800eb01 800eb30: 0800eb85 .word 0x0800eb85 800eb34: 0800eb01 .word 0x0800eb01 800eb38: 0800eb01 .word 0x0800eb01 800eb3c: 0800eb01 .word 0x0800eb01 800eb40: 0800eb01 .word 0x0800eb01 800eb44: 0800ec83 .word 0x0800ec83 800eb48: 0800ebaf .word 0x0800ebaf 800eb4c: 0800ec3d .word 0x0800ec3d 800eb50: 0800eb01 .word 0x0800eb01 800eb54: 0800eb01 .word 0x0800eb01 800eb58: 0800eca5 .word 0x0800eca5 800eb5c: 0800eb01 .word 0x0800eb01 800eb60: 0800ebaf .word 0x0800ebaf 800eb64: 0800eb01 .word 0x0800eb01 800eb68: 0800eb01 .word 0x0800eb01 800eb6c: 0800ec45 .word 0x0800ec45 800eb70: 6833 ldr r3, [r6, #0] 800eb72: 1d1a adds r2, r3, #4 800eb74: 681b ldr r3, [r3, #0] 800eb76: 6032 str r2, [r6, #0] 800eb78: f104 0642 add.w r6, r4, #66 @ 0x42 800eb7c: f884 3042 strb.w r3, [r4, #66] @ 0x42 800eb80: 2301 movs r3, #1 800eb82: e09c b.n 800ecbe <_printf_i+0x1e6> 800eb84: 6833 ldr r3, [r6, #0] 800eb86: 6820 ldr r0, [r4, #0] 800eb88: 1d19 adds r1, r3, #4 800eb8a: 6031 str r1, [r6, #0] 800eb8c: 0606 lsls r6, r0, #24 800eb8e: d501 bpl.n 800eb94 <_printf_i+0xbc> 800eb90: 681d ldr r5, [r3, #0] 800eb92: e003 b.n 800eb9c <_printf_i+0xc4> 800eb94: 0645 lsls r5, r0, #25 800eb96: d5fb bpl.n 800eb90 <_printf_i+0xb8> 800eb98: f9b3 5000 ldrsh.w r5, [r3] 800eb9c: 2d00 cmp r5, #0 800eb9e: da03 bge.n 800eba8 <_printf_i+0xd0> 800eba0: 232d movs r3, #45 @ 0x2d 800eba2: 426d negs r5, r5 800eba4: f884 3043 strb.w r3, [r4, #67] @ 0x43 800eba8: 230a movs r3, #10 800ebaa: 4858 ldr r0, [pc, #352] @ (800ed0c <_printf_i+0x234>) 800ebac: e011 b.n 800ebd2 <_printf_i+0xfa> 800ebae: 6821 ldr r1, [r4, #0] 800ebb0: 6833 ldr r3, [r6, #0] 800ebb2: 0608 lsls r0, r1, #24 800ebb4: f853 5b04 ldr.w r5, [r3], #4 800ebb8: d402 bmi.n 800ebc0 <_printf_i+0xe8> 800ebba: 0649 lsls r1, r1, #25 800ebbc: bf48 it mi 800ebbe: b2ad uxthmi r5, r5 800ebc0: 2f6f cmp r7, #111 @ 0x6f 800ebc2: 6033 str r3, [r6, #0] 800ebc4: bf14 ite ne 800ebc6: 230a movne r3, #10 800ebc8: 2308 moveq r3, #8 800ebca: 4850 ldr r0, [pc, #320] @ (800ed0c <_printf_i+0x234>) 800ebcc: 2100 movs r1, #0 800ebce: f884 1043 strb.w r1, [r4, #67] @ 0x43 800ebd2: 6866 ldr r6, [r4, #4] 800ebd4: 2e00 cmp r6, #0 800ebd6: 60a6 str r6, [r4, #8] 800ebd8: db05 blt.n 800ebe6 <_printf_i+0x10e> 800ebda: 6821 ldr r1, [r4, #0] 800ebdc: 432e orrs r6, r5 800ebde: f021 0104 bic.w r1, r1, #4 800ebe2: 6021 str r1, [r4, #0] 800ebe4: d04b beq.n 800ec7e <_printf_i+0x1a6> 800ebe6: 4616 mov r6, r2 800ebe8: fbb5 f1f3 udiv r1, r5, r3 800ebec: fb03 5711 mls r7, r3, r1, r5 800ebf0: 5dc7 ldrb r7, [r0, r7] 800ebf2: f806 7d01 strb.w r7, [r6, #-1]! 800ebf6: 462f mov r7, r5 800ebf8: 42bb cmp r3, r7 800ebfa: 460d mov r5, r1 800ebfc: d9f4 bls.n 800ebe8 <_printf_i+0x110> 800ebfe: 2b08 cmp r3, #8 800ec00: d10b bne.n 800ec1a <_printf_i+0x142> 800ec02: 6823 ldr r3, [r4, #0] 800ec04: 07df lsls r7, r3, #31 800ec06: d508 bpl.n 800ec1a <_printf_i+0x142> 800ec08: 6923 ldr r3, [r4, #16] 800ec0a: 6861 ldr r1, [r4, #4] 800ec0c: 4299 cmp r1, r3 800ec0e: bfde ittt le 800ec10: 2330 movle r3, #48 @ 0x30 800ec12: f806 3c01 strble.w r3, [r6, #-1] 800ec16: f106 36ff addle.w r6, r6, #4294967295 800ec1a: 1b92 subs r2, r2, r6 800ec1c: 6122 str r2, [r4, #16] 800ec1e: 464b mov r3, r9 800ec20: 4621 mov r1, r4 800ec22: 4640 mov r0, r8 800ec24: f8cd a000 str.w sl, [sp] 800ec28: aa03 add r2, sp, #12 800ec2a: f7ff fee3 bl 800e9f4 <_printf_common> 800ec2e: 3001 adds r0, #1 800ec30: d14a bne.n 800ecc8 <_printf_i+0x1f0> 800ec32: f04f 30ff mov.w r0, #4294967295 800ec36: b004 add sp, #16 800ec38: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800ec3c: 6823 ldr r3, [r4, #0] 800ec3e: f043 0320 orr.w r3, r3, #32 800ec42: 6023 str r3, [r4, #0] 800ec44: 2778 movs r7, #120 @ 0x78 800ec46: 4832 ldr r0, [pc, #200] @ (800ed10 <_printf_i+0x238>) 800ec48: f884 7045 strb.w r7, [r4, #69] @ 0x45 800ec4c: 6823 ldr r3, [r4, #0] 800ec4e: 6831 ldr r1, [r6, #0] 800ec50: 061f lsls r7, r3, #24 800ec52: f851 5b04 ldr.w r5, [r1], #4 800ec56: d402 bmi.n 800ec5e <_printf_i+0x186> 800ec58: 065f lsls r7, r3, #25 800ec5a: bf48 it mi 800ec5c: b2ad uxthmi r5, r5 800ec5e: 6031 str r1, [r6, #0] 800ec60: 07d9 lsls r1, r3, #31 800ec62: bf44 itt mi 800ec64: f043 0320 orrmi.w r3, r3, #32 800ec68: 6023 strmi r3, [r4, #0] 800ec6a: b11d cbz r5, 800ec74 <_printf_i+0x19c> 800ec6c: 2310 movs r3, #16 800ec6e: e7ad b.n 800ebcc <_printf_i+0xf4> 800ec70: 4826 ldr r0, [pc, #152] @ (800ed0c <_printf_i+0x234>) 800ec72: e7e9 b.n 800ec48 <_printf_i+0x170> 800ec74: 6823 ldr r3, [r4, #0] 800ec76: f023 0320 bic.w r3, r3, #32 800ec7a: 6023 str r3, [r4, #0] 800ec7c: e7f6 b.n 800ec6c <_printf_i+0x194> 800ec7e: 4616 mov r6, r2 800ec80: e7bd b.n 800ebfe <_printf_i+0x126> 800ec82: 6833 ldr r3, [r6, #0] 800ec84: 6825 ldr r5, [r4, #0] 800ec86: 1d18 adds r0, r3, #4 800ec88: 6961 ldr r1, [r4, #20] 800ec8a: 6030 str r0, [r6, #0] 800ec8c: 062e lsls r6, r5, #24 800ec8e: 681b ldr r3, [r3, #0] 800ec90: d501 bpl.n 800ec96 <_printf_i+0x1be> 800ec92: 6019 str r1, [r3, #0] 800ec94: e002 b.n 800ec9c <_printf_i+0x1c4> 800ec96: 0668 lsls r0, r5, #25 800ec98: d5fb bpl.n 800ec92 <_printf_i+0x1ba> 800ec9a: 8019 strh r1, [r3, #0] 800ec9c: 2300 movs r3, #0 800ec9e: 4616 mov r6, r2 800eca0: 6123 str r3, [r4, #16] 800eca2: e7bc b.n 800ec1e <_printf_i+0x146> 800eca4: 6833 ldr r3, [r6, #0] 800eca6: 2100 movs r1, #0 800eca8: 1d1a adds r2, r3, #4 800ecaa: 6032 str r2, [r6, #0] 800ecac: 681e ldr r6, [r3, #0] 800ecae: 6862 ldr r2, [r4, #4] 800ecb0: 4630 mov r0, r6 800ecb2: f000 f859 bl 800ed68 800ecb6: b108 cbz r0, 800ecbc <_printf_i+0x1e4> 800ecb8: 1b80 subs r0, r0, r6 800ecba: 6060 str r0, [r4, #4] 800ecbc: 6863 ldr r3, [r4, #4] 800ecbe: 6123 str r3, [r4, #16] 800ecc0: 2300 movs r3, #0 800ecc2: f884 3043 strb.w r3, [r4, #67] @ 0x43 800ecc6: e7aa b.n 800ec1e <_printf_i+0x146> 800ecc8: 4632 mov r2, r6 800ecca: 4649 mov r1, r9 800eccc: 4640 mov r0, r8 800ecce: 6923 ldr r3, [r4, #16] 800ecd0: 47d0 blx sl 800ecd2: 3001 adds r0, #1 800ecd4: d0ad beq.n 800ec32 <_printf_i+0x15a> 800ecd6: 6823 ldr r3, [r4, #0] 800ecd8: 079b lsls r3, r3, #30 800ecda: d413 bmi.n 800ed04 <_printf_i+0x22c> 800ecdc: 68e0 ldr r0, [r4, #12] 800ecde: 9b03 ldr r3, [sp, #12] 800ece0: 4298 cmp r0, r3 800ece2: bfb8 it lt 800ece4: 4618 movlt r0, r3 800ece6: e7a6 b.n 800ec36 <_printf_i+0x15e> 800ece8: 2301 movs r3, #1 800ecea: 4632 mov r2, r6 800ecec: 4649 mov r1, r9 800ecee: 4640 mov r0, r8 800ecf0: 47d0 blx sl 800ecf2: 3001 adds r0, #1 800ecf4: d09d beq.n 800ec32 <_printf_i+0x15a> 800ecf6: 3501 adds r5, #1 800ecf8: 68e3 ldr r3, [r4, #12] 800ecfa: 9903 ldr r1, [sp, #12] 800ecfc: 1a5b subs r3, r3, r1 800ecfe: 42ab cmp r3, r5 800ed00: dcf2 bgt.n 800ece8 <_printf_i+0x210> 800ed02: e7eb b.n 800ecdc <_printf_i+0x204> 800ed04: 2500 movs r5, #0 800ed06: f104 0619 add.w r6, r4, #25 800ed0a: e7f5 b.n 800ecf8 <_printf_i+0x220> 800ed0c: 0800f5eb .word 0x0800f5eb 800ed10: 0800f5fc .word 0x0800f5fc 0800ed14 : 800ed14: 4288 cmp r0, r1 800ed16: b510 push {r4, lr} 800ed18: eb01 0402 add.w r4, r1, r2 800ed1c: d902 bls.n 800ed24 800ed1e: 4284 cmp r4, r0 800ed20: 4623 mov r3, r4 800ed22: d807 bhi.n 800ed34 800ed24: 1e43 subs r3, r0, #1 800ed26: 42a1 cmp r1, r4 800ed28: d008 beq.n 800ed3c 800ed2a: f811 2b01 ldrb.w r2, [r1], #1 800ed2e: f803 2f01 strb.w r2, [r3, #1]! 800ed32: e7f8 b.n 800ed26 800ed34: 4601 mov r1, r0 800ed36: 4402 add r2, r0 800ed38: 428a cmp r2, r1 800ed3a: d100 bne.n 800ed3e 800ed3c: bd10 pop {r4, pc} 800ed3e: f813 4d01 ldrb.w r4, [r3, #-1]! 800ed42: f802 4d01 strb.w r4, [r2, #-1]! 800ed46: e7f7 b.n 800ed38 0800ed48 <_sbrk_r>: 800ed48: b538 push {r3, r4, r5, lr} 800ed4a: 2300 movs r3, #0 800ed4c: 4d05 ldr r5, [pc, #20] @ (800ed64 <_sbrk_r+0x1c>) 800ed4e: 4604 mov r4, r0 800ed50: 4608 mov r0, r1 800ed52: 602b str r3, [r5, #0] 800ed54: f7f6 f98e bl 8005074 <_sbrk> 800ed58: 1c43 adds r3, r0, #1 800ed5a: d102 bne.n 800ed62 <_sbrk_r+0x1a> 800ed5c: 682b ldr r3, [r5, #0] 800ed5e: b103 cbz r3, 800ed62 <_sbrk_r+0x1a> 800ed60: 6023 str r3, [r4, #0] 800ed62: bd38 pop {r3, r4, r5, pc} 800ed64: 20001894 .word 0x20001894 0800ed68 : 800ed68: 4603 mov r3, r0 800ed6a: b510 push {r4, lr} 800ed6c: b2c9 uxtb r1, r1 800ed6e: 4402 add r2, r0 800ed70: 4293 cmp r3, r2 800ed72: 4618 mov r0, r3 800ed74: d101 bne.n 800ed7a 800ed76: 2000 movs r0, #0 800ed78: e003 b.n 800ed82 800ed7a: 7804 ldrb r4, [r0, #0] 800ed7c: 3301 adds r3, #1 800ed7e: 428c cmp r4, r1 800ed80: d1f6 bne.n 800ed70 800ed82: bd10 pop {r4, pc} 0800ed84 : 800ed84: 440a add r2, r1 800ed86: 4291 cmp r1, r2 800ed88: f100 33ff add.w r3, r0, #4294967295 800ed8c: d100 bne.n 800ed90 800ed8e: 4770 bx lr 800ed90: b510 push {r4, lr} 800ed92: f811 4b01 ldrb.w r4, [r1], #1 800ed96: 4291 cmp r1, r2 800ed98: f803 4f01 strb.w r4, [r3, #1]! 800ed9c: d1f9 bne.n 800ed92 800ed9e: bd10 pop {r4, pc} 0800eda0 <_realloc_r>: 800eda0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800eda4: 4607 mov r7, r0 800eda6: 4614 mov r4, r2 800eda8: 460d mov r5, r1 800edaa: b921 cbnz r1, 800edb6 <_realloc_r+0x16> 800edac: 4611 mov r1, r2 800edae: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800edb2: f7ff bc3b b.w 800e62c <_malloc_r> 800edb6: b92a cbnz r2, 800edc4 <_realloc_r+0x24> 800edb8: f7ff fbce bl 800e558 <_free_r> 800edbc: 4625 mov r5, r4 800edbe: 4628 mov r0, r5 800edc0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800edc4: f000 f81a bl 800edfc <_malloc_usable_size_r> 800edc8: 4284 cmp r4, r0 800edca: 4606 mov r6, r0 800edcc: d802 bhi.n 800edd4 <_realloc_r+0x34> 800edce: ebb4 0f50 cmp.w r4, r0, lsr #1 800edd2: d8f4 bhi.n 800edbe <_realloc_r+0x1e> 800edd4: 4621 mov r1, r4 800edd6: 4638 mov r0, r7 800edd8: f7ff fc28 bl 800e62c <_malloc_r> 800eddc: 4680 mov r8, r0 800edde: b908 cbnz r0, 800ede4 <_realloc_r+0x44> 800ede0: 4645 mov r5, r8 800ede2: e7ec b.n 800edbe <_realloc_r+0x1e> 800ede4: 42b4 cmp r4, r6 800ede6: 4622 mov r2, r4 800ede8: 4629 mov r1, r5 800edea: bf28 it cs 800edec: 4632 movcs r2, r6 800edee: f7ff ffc9 bl 800ed84 800edf2: 4629 mov r1, r5 800edf4: 4638 mov r0, r7 800edf6: f7ff fbaf bl 800e558 <_free_r> 800edfa: e7f1 b.n 800ede0 <_realloc_r+0x40> 0800edfc <_malloc_usable_size_r>: 800edfc: f851 3c04 ldr.w r3, [r1, #-4] 800ee00: 1f18 subs r0, r3, #4 800ee02: 2b00 cmp r3, #0 800ee04: bfbc itt lt 800ee06: 580b ldrlt r3, [r1, r0] 800ee08: 18c0 addlt r0, r0, r3 800ee0a: 4770 bx lr 0800ee0c <_init>: 800ee0c: b5f8 push {r3, r4, r5, r6, r7, lr} 800ee0e: bf00 nop 800ee10: bcf8 pop {r3, r4, r5, r6, r7} 800ee12: bc08 pop {r3} 800ee14: 469e mov lr, r3 800ee16: 4770 bx lr 0800ee18 <_fini>: 800ee18: b5f8 push {r3, r4, r5, r6, r7, lr} 800ee1a: bf00 nop 800ee1c: bcf8 pop {r3, r4, r5, r6, r7} 800ee1e: bc08 pop {r3} 800ee20: 469e mov lr, r3 800ee22: 4770 bx lr