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0eafe60ccb9f0b3d59f3f05cb7d05062ac8705f2
AUTOM/workspace/AUTOM3/Debug/AUTOM3.list
andrea 53391bffc6 wip
2025-08-27 23:29:38 +02:00

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AUTOM3.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000b8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000025bc 080000b8 080000b8 000010b8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000094 08002674 08002674 00003674 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002708 08002708 0000400c 2**0
CONTENTS, READONLY
4 .ARM 00000000 08002708 08002708 0000400c 2**0
CONTENTS, READONLY
5 .preinit_array 00000000 08002708 08002708 0000400c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002708 08002708 00003708 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800270c 0800270c 0000370c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08002710 00004000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000b8 2000000c 0800271c 0000400c 2**2
ALLOC
10 ._user_heap_stack 00000604 200000c4 0800271c 000040c4 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0000400c 2**0
CONTENTS, READONLY
12 .debug_info 00008981 00000000 00000000 00004034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001714 00000000 00000000 0000c9b5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000a08 00000000 00000000 0000e0d0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000007c6 00000000 00000000 0000ead8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00013d8b 00000000 00000000 0000f29e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000b379 00000000 00000000 00023029 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008077d 00000000 00000000 0002e3a2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000aeb1f 2**0
CONTENTS, READONLY
20 .debug_frame 000023e0 00000000 00000000 000aeb64 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000b0f44 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000b8 <__do_global_dtors_aux>:
80000b8: b510 push {r4, lr}
80000ba: 4c06 ldr r4, [pc, #24] @ (80000d4 <__do_global_dtors_aux+0x1c>)
80000bc: 7823 ldrb r3, [r4, #0]
80000be: 2b00 cmp r3, #0
80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a>
80000c2: 4b05 ldr r3, [pc, #20] @ (80000d8 <__do_global_dtors_aux+0x20>)
80000c4: 2b00 cmp r3, #0
80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16>
80000c8: 4804 ldr r0, [pc, #16] @ (80000dc <__do_global_dtors_aux+0x24>)
80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16>
80000cc: bf00 nop
80000ce: 2301 movs r3, #1
80000d0: 7023 strb r3, [r4, #0]
80000d2: bd10 pop {r4, pc}
80000d4: 2000000c .word 0x2000000c
80000d8: 00000000 .word 0x00000000
80000dc: 0800265c .word 0x0800265c
080000e0 <frame_dummy>:
80000e0: 4b04 ldr r3, [pc, #16] @ (80000f4 <frame_dummy+0x14>)
80000e2: b510 push {r4, lr}
80000e4: 2b00 cmp r3, #0
80000e6: d003 beq.n 80000f0 <frame_dummy+0x10>
80000e8: 4903 ldr r1, [pc, #12] @ (80000f8 <frame_dummy+0x18>)
80000ea: 4804 ldr r0, [pc, #16] @ (80000fc <frame_dummy+0x1c>)
80000ec: e000 b.n 80000f0 <frame_dummy+0x10>
80000ee: bf00 nop
80000f0: bd10 pop {r4, pc}
80000f2: 46c0 nop @ (mov r8, r8)
80000f4: 00000000 .word 0x00000000
80000f8: 20000010 .word 0x20000010
80000fc: 0800265c .word 0x0800265c
08000100 <__udivsi3>:
8000100: 2200 movs r2, #0
8000102: 0843 lsrs r3, r0, #1
8000104: 428b cmp r3, r1
8000106: d374 bcc.n 80001f2 <__udivsi3+0xf2>
8000108: 0903 lsrs r3, r0, #4
800010a: 428b cmp r3, r1
800010c: d35f bcc.n 80001ce <__udivsi3+0xce>
800010e: 0a03 lsrs r3, r0, #8
8000110: 428b cmp r3, r1
8000112: d344 bcc.n 800019e <__udivsi3+0x9e>
8000114: 0b03 lsrs r3, r0, #12
8000116: 428b cmp r3, r1
8000118: d328 bcc.n 800016c <__udivsi3+0x6c>
800011a: 0c03 lsrs r3, r0, #16
800011c: 428b cmp r3, r1
800011e: d30d bcc.n 800013c <__udivsi3+0x3c>
8000120: 22ff movs r2, #255 @ 0xff
8000122: 0209 lsls r1, r1, #8
8000124: ba12 rev r2, r2
8000126: 0c03 lsrs r3, r0, #16
8000128: 428b cmp r3, r1
800012a: d302 bcc.n 8000132 <__udivsi3+0x32>
800012c: 1212 asrs r2, r2, #8
800012e: 0209 lsls r1, r1, #8
8000130: d065 beq.n 80001fe <__udivsi3+0xfe>
8000132: 0b03 lsrs r3, r0, #12
8000134: 428b cmp r3, r1
8000136: d319 bcc.n 800016c <__udivsi3+0x6c>
8000138: e000 b.n 800013c <__udivsi3+0x3c>
800013a: 0a09 lsrs r1, r1, #8
800013c: 0bc3 lsrs r3, r0, #15
800013e: 428b cmp r3, r1
8000140: d301 bcc.n 8000146 <__udivsi3+0x46>
8000142: 03cb lsls r3, r1, #15
8000144: 1ac0 subs r0, r0, r3
8000146: 4152 adcs r2, r2
8000148: 0b83 lsrs r3, r0, #14
800014a: 428b cmp r3, r1
800014c: d301 bcc.n 8000152 <__udivsi3+0x52>
800014e: 038b lsls r3, r1, #14
8000150: 1ac0 subs r0, r0, r3
8000152: 4152 adcs r2, r2
8000154: 0b43 lsrs r3, r0, #13
8000156: 428b cmp r3, r1
8000158: d301 bcc.n 800015e <__udivsi3+0x5e>
800015a: 034b lsls r3, r1, #13
800015c: 1ac0 subs r0, r0, r3
800015e: 4152 adcs r2, r2
8000160: 0b03 lsrs r3, r0, #12
8000162: 428b cmp r3, r1
8000164: d301 bcc.n 800016a <__udivsi3+0x6a>
8000166: 030b lsls r3, r1, #12
8000168: 1ac0 subs r0, r0, r3
800016a: 4152 adcs r2, r2
800016c: 0ac3 lsrs r3, r0, #11
800016e: 428b cmp r3, r1
8000170: d301 bcc.n 8000176 <__udivsi3+0x76>
8000172: 02cb lsls r3, r1, #11
8000174: 1ac0 subs r0, r0, r3
8000176: 4152 adcs r2, r2
8000178: 0a83 lsrs r3, r0, #10
800017a: 428b cmp r3, r1
800017c: d301 bcc.n 8000182 <__udivsi3+0x82>
800017e: 028b lsls r3, r1, #10
8000180: 1ac0 subs r0, r0, r3
8000182: 4152 adcs r2, r2
8000184: 0a43 lsrs r3, r0, #9
8000186: 428b cmp r3, r1
8000188: d301 bcc.n 800018e <__udivsi3+0x8e>
800018a: 024b lsls r3, r1, #9
800018c: 1ac0 subs r0, r0, r3
800018e: 4152 adcs r2, r2
8000190: 0a03 lsrs r3, r0, #8
8000192: 428b cmp r3, r1
8000194: d301 bcc.n 800019a <__udivsi3+0x9a>
8000196: 020b lsls r3, r1, #8
8000198: 1ac0 subs r0, r0, r3
800019a: 4152 adcs r2, r2
800019c: d2cd bcs.n 800013a <__udivsi3+0x3a>
800019e: 09c3 lsrs r3, r0, #7
80001a0: 428b cmp r3, r1
80001a2: d301 bcc.n 80001a8 <__udivsi3+0xa8>
80001a4: 01cb lsls r3, r1, #7
80001a6: 1ac0 subs r0, r0, r3
80001a8: 4152 adcs r2, r2
80001aa: 0983 lsrs r3, r0, #6
80001ac: 428b cmp r3, r1
80001ae: d301 bcc.n 80001b4 <__udivsi3+0xb4>
80001b0: 018b lsls r3, r1, #6
80001b2: 1ac0 subs r0, r0, r3
80001b4: 4152 adcs r2, r2
80001b6: 0943 lsrs r3, r0, #5
80001b8: 428b cmp r3, r1
80001ba: d301 bcc.n 80001c0 <__udivsi3+0xc0>
80001bc: 014b lsls r3, r1, #5
80001be: 1ac0 subs r0, r0, r3
80001c0: 4152 adcs r2, r2
80001c2: 0903 lsrs r3, r0, #4
80001c4: 428b cmp r3, r1
80001c6: d301 bcc.n 80001cc <__udivsi3+0xcc>
80001c8: 010b lsls r3, r1, #4
80001ca: 1ac0 subs r0, r0, r3
80001cc: 4152 adcs r2, r2
80001ce: 08c3 lsrs r3, r0, #3
80001d0: 428b cmp r3, r1
80001d2: d301 bcc.n 80001d8 <__udivsi3+0xd8>
80001d4: 00cb lsls r3, r1, #3
80001d6: 1ac0 subs r0, r0, r3
80001d8: 4152 adcs r2, r2
80001da: 0883 lsrs r3, r0, #2
80001dc: 428b cmp r3, r1
80001de: d301 bcc.n 80001e4 <__udivsi3+0xe4>
80001e0: 008b lsls r3, r1, #2
80001e2: 1ac0 subs r0, r0, r3
80001e4: 4152 adcs r2, r2
80001e6: 0843 lsrs r3, r0, #1
80001e8: 428b cmp r3, r1
80001ea: d301 bcc.n 80001f0 <__udivsi3+0xf0>
80001ec: 004b lsls r3, r1, #1
80001ee: 1ac0 subs r0, r0, r3
80001f0: 4152 adcs r2, r2
80001f2: 1a41 subs r1, r0, r1
80001f4: d200 bcs.n 80001f8 <__udivsi3+0xf8>
80001f6: 4601 mov r1, r0
80001f8: 4152 adcs r2, r2
80001fa: 4610 mov r0, r2
80001fc: 4770 bx lr
80001fe: e7ff b.n 8000200 <__udivsi3+0x100>
8000200: b501 push {r0, lr}
8000202: 2000 movs r0, #0
8000204: f000 f806 bl 8000214 <__aeabi_idiv0>
8000208: bd02 pop {r1, pc}
800020a: 46c0 nop @ (mov r8, r8)
0800020c <__aeabi_uidivmod>:
800020c: 2900 cmp r1, #0
800020e: d0f7 beq.n 8000200 <__udivsi3+0x100>
8000210: e776 b.n 8000100 <__udivsi3>
8000212: 4770 bx lr
08000214 <__aeabi_idiv0>:
8000214: 4770 bx lr
8000216: 46c0 nop @ (mov r8, r8)
08000218 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000218: b580 push {r7, lr}
800021a: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800021c: f000 fb3c bl 8000898 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000220: f000 f808 bl 8000234 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000224: f000 f9d8 bl 80005d8 <MX_GPIO_Init>
MX_TIM1_Init();
8000228: f000 f84c bl 80002c4 <MX_TIM1_Init>
MX_TIM3_Init();
800022c: f000 f936 bl 800049c <MX_TIM3_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000230: 46c0 nop @ (mov r8, r8)
8000232: e7fd b.n 8000230 <main+0x18>
08000234 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000234: b590 push {r4, r7, lr}
8000236: b093 sub sp, #76 @ 0x4c
8000238: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800023a: 2414 movs r4, #20
800023c: 193b adds r3, r7, r4
800023e: 0018 movs r0, r3
8000240: 2334 movs r3, #52 @ 0x34
8000242: 001a movs r2, r3
8000244: 2100 movs r1, #0
8000246: f002 f9dd bl 8002604 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800024a: 1d3b adds r3, r7, #4
800024c: 0018 movs r0, r3
800024e: 2310 movs r3, #16
8000250: 001a movs r2, r3
8000252: 2100 movs r1, #0
8000254: f002 f9d6 bl 8002604 <memset>
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000258: 2380 movs r3, #128 @ 0x80
800025a: 009b lsls r3, r3, #2
800025c: 0018 movs r0, r3
800025e: f000 fdb9 bl 8000dd4 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000262: 193b adds r3, r7, r4
8000264: 2202 movs r2, #2
8000266: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000268: 193b adds r3, r7, r4
800026a: 2280 movs r2, #128 @ 0x80
800026c: 0052 lsls r2, r2, #1
800026e: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
8000270: 193b adds r3, r7, r4
8000272: 2200 movs r2, #0
8000274: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000276: 193b adds r3, r7, r4
8000278: 2240 movs r2, #64 @ 0x40
800027a: 615a str r2, [r3, #20]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
800027c: 193b adds r3, r7, r4
800027e: 2200 movs r2, #0
8000280: 61da str r2, [r3, #28]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000282: 193b adds r3, r7, r4
8000284: 0018 movs r0, r3
8000286: f000 fde5 bl 8000e54 <HAL_RCC_OscConfig>
800028a: 1e03 subs r3, r0, #0
800028c: d001 beq.n 8000292 <SystemClock_Config+0x5e>
{
Error_Handler();
800028e: f000 f9d1 bl 8000634 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000292: 1d3b adds r3, r7, #4
8000294: 2207 movs r2, #7
8000296: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8000298: 1d3b adds r3, r7, #4
800029a: 2200 movs r2, #0
800029c: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800029e: 1d3b adds r3, r7, #4
80002a0: 2200 movs r2, #0
80002a2: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80002a4: 1d3b adds r3, r7, #4
80002a6: 2200 movs r2, #0
80002a8: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80002aa: 1d3b adds r3, r7, #4
80002ac: 2100 movs r1, #0
80002ae: 0018 movs r0, r3
80002b0: f001 f8e0 bl 8001474 <HAL_RCC_ClockConfig>
80002b4: 1e03 subs r3, r0, #0
80002b6: d001 beq.n 80002bc <SystemClock_Config+0x88>
{
Error_Handler();
80002b8: f000 f9bc bl 8000634 <Error_Handler>
}
}
80002bc: 46c0 nop @ (mov r8, r8)
80002be: 46bd mov sp, r7
80002c0: b013 add sp, #76 @ 0x4c
80002c2: bd90 pop {r4, r7, pc}
080002c4 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
80002c4: b580 push {r7, lr}
80002c6: b09c sub sp, #112 @ 0x70
80002c8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80002ca: 2360 movs r3, #96 @ 0x60
80002cc: 18fb adds r3, r7, r3
80002ce: 0018 movs r0, r3
80002d0: 2310 movs r3, #16
80002d2: 001a movs r2, r3
80002d4: 2100 movs r1, #0
80002d6: f002 f995 bl 8002604 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
80002da: 2354 movs r3, #84 @ 0x54
80002dc: 18fb adds r3, r7, r3
80002de: 0018 movs r0, r3
80002e0: 230c movs r3, #12
80002e2: 001a movs r2, r3
80002e4: 2100 movs r1, #0
80002e6: f002 f98d bl 8002604 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
80002ea: 2338 movs r3, #56 @ 0x38
80002ec: 18fb adds r3, r7, r3
80002ee: 0018 movs r0, r3
80002f0: 231c movs r3, #28
80002f2: 001a movs r2, r3
80002f4: 2100 movs r1, #0
80002f6: f002 f985 bl 8002604 <memset>
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
80002fa: 1d3b adds r3, r7, #4
80002fc: 0018 movs r0, r3
80002fe: 2334 movs r3, #52 @ 0x34
8000300: 001a movs r2, r3
8000302: 2100 movs r1, #0
8000304: f002 f97e bl 8002604 <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000308: 4b61 ldr r3, [pc, #388] @ (8000490 <MX_TIM1_Init+0x1cc>)
800030a: 4a62 ldr r2, [pc, #392] @ (8000494 <MX_TIM1_Init+0x1d0>)
800030c: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
800030e: 4b60 ldr r3, [pc, #384] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000310: 2200 movs r2, #0
8000312: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000314: 4b5e ldr r3, [pc, #376] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000316: 2200 movs r2, #0
8000318: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
800031a: 4b5d ldr r3, [pc, #372] @ (8000490 <MX_TIM1_Init+0x1cc>)
800031c: 4a5e ldr r2, [pc, #376] @ (8000498 <MX_TIM1_Init+0x1d4>)
800031e: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000320: 4b5b ldr r3, [pc, #364] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000322: 2200 movs r2, #0
8000324: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8000326: 4b5a ldr r3, [pc, #360] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000328: 2200 movs r2, #0
800032a: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800032c: 4b58 ldr r3, [pc, #352] @ (8000490 <MX_TIM1_Init+0x1cc>)
800032e: 2200 movs r2, #0
8000330: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8000332: 4b57 ldr r3, [pc, #348] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000334: 0018 movs r0, r3
8000336: f001 fa27 bl 8001788 <HAL_TIM_Base_Init>
800033a: 1e03 subs r3, r0, #0
800033c: d001 beq.n 8000342 <MX_TIM1_Init+0x7e>
{
Error_Handler();
800033e: f000 f979 bl 8000634 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000342: 2160 movs r1, #96 @ 0x60
8000344: 187b adds r3, r7, r1
8000346: 2280 movs r2, #128 @ 0x80
8000348: 0152 lsls r2, r2, #5
800034a: 601a str r2, [r3, #0]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
800034c: 187a adds r2, r7, r1
800034e: 4b50 ldr r3, [pc, #320] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000350: 0011 movs r1, r2
8000352: 0018 movs r0, r3
8000354: f001 fbd0 bl 8001af8 <HAL_TIM_ConfigClockSource>
8000358: 1e03 subs r3, r0, #0
800035a: d001 beq.n 8000360 <MX_TIM1_Init+0x9c>
{
Error_Handler();
800035c: f000 f96a bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
8000360: 4b4b ldr r3, [pc, #300] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000362: 0018 movs r0, r3
8000364: f001 fa68 bl 8001838 <HAL_TIM_PWM_Init>
8000368: 1e03 subs r3, r0, #0
800036a: d001 beq.n 8000370 <MX_TIM1_Init+0xac>
{
Error_Handler();
800036c: f000 f962 bl 8000634 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000370: 2154 movs r1, #84 @ 0x54
8000372: 187b adds r3, r7, r1
8000374: 2200 movs r2, #0
8000376: 601a str r2, [r3, #0]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8000378: 187b adds r3, r7, r1
800037a: 2200 movs r2, #0
800037c: 605a str r2, [r3, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800037e: 187b adds r3, r7, r1
8000380: 2200 movs r2, #0
8000382: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000384: 187a adds r2, r7, r1
8000386: 4b42 ldr r3, [pc, #264] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000388: 0011 movs r1, r2
800038a: 0018 movs r0, r3
800038c: f002 f83c bl 8002408 <HAL_TIMEx_MasterConfigSynchronization>
8000390: 1e03 subs r3, r0, #0
8000392: d001 beq.n 8000398 <MX_TIM1_Init+0xd4>
{
Error_Handler();
8000394: f000 f94e bl 8000634 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000398: 2138 movs r1, #56 @ 0x38
800039a: 187b adds r3, r7, r1
800039c: 2260 movs r2, #96 @ 0x60
800039e: 601a str r2, [r3, #0]
sConfigOC.Pulse = 0;
80003a0: 187b adds r3, r7, r1
80003a2: 2200 movs r2, #0
80003a4: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80003a6: 187b adds r3, r7, r1
80003a8: 2200 movs r2, #0
80003aa: 609a str r2, [r3, #8]
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80003ac: 187b adds r3, r7, r1
80003ae: 2200 movs r2, #0
80003b0: 60da str r2, [r3, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80003b2: 187b adds r3, r7, r1
80003b4: 2200 movs r2, #0
80003b6: 611a str r2, [r3, #16]
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80003b8: 187b adds r3, r7, r1
80003ba: 2200 movs r2, #0
80003bc: 615a str r2, [r3, #20]
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80003be: 187b adds r3, r7, r1
80003c0: 2200 movs r2, #0
80003c2: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80003c4: 1879 adds r1, r7, r1
80003c6: 4b32 ldr r3, [pc, #200] @ (8000490 <MX_TIM1_Init+0x1cc>)
80003c8: 2200 movs r2, #0
80003ca: 0018 movs r0, r3
80003cc: f001 fa94 bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
80003d0: 1e03 subs r3, r0, #0
80003d2: d001 beq.n 80003d8 <MX_TIM1_Init+0x114>
{
Error_Handler();
80003d4: f000 f92e bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80003d8: 2338 movs r3, #56 @ 0x38
80003da: 18f9 adds r1, r7, r3
80003dc: 4b2c ldr r3, [pc, #176] @ (8000490 <MX_TIM1_Init+0x1cc>)
80003de: 2204 movs r2, #4
80003e0: 0018 movs r0, r3
80003e2: f001 fa89 bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
80003e6: 1e03 subs r3, r0, #0
80003e8: d001 beq.n 80003ee <MX_TIM1_Init+0x12a>
{
Error_Handler();
80003ea: f000 f923 bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80003ee: 2338 movs r3, #56 @ 0x38
80003f0: 18f9 adds r1, r7, r3
80003f2: 4b27 ldr r3, [pc, #156] @ (8000490 <MX_TIM1_Init+0x1cc>)
80003f4: 2208 movs r2, #8
80003f6: 0018 movs r0, r3
80003f8: f001 fa7e bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
80003fc: 1e03 subs r3, r0, #0
80003fe: d001 beq.n 8000404 <MX_TIM1_Init+0x140>
{
Error_Handler();
8000400: f000 f918 bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8000404: 2338 movs r3, #56 @ 0x38
8000406: 18f9 adds r1, r7, r3
8000408: 4b21 ldr r3, [pc, #132] @ (8000490 <MX_TIM1_Init+0x1cc>)
800040a: 220c movs r2, #12
800040c: 0018 movs r0, r3
800040e: f001 fa73 bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
8000412: 1e03 subs r3, r0, #0
8000414: d001 beq.n 800041a <MX_TIM1_Init+0x156>
{
Error_Handler();
8000416: f000 f90d bl 8000634 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800041a: 1d3b adds r3, r7, #4
800041c: 2200 movs r2, #0
800041e: 601a str r2, [r3, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8000420: 1d3b adds r3, r7, #4
8000422: 2200 movs r2, #0
8000424: 605a str r2, [r3, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8000426: 1d3b adds r3, r7, #4
8000428: 2200 movs r2, #0
800042a: 609a str r2, [r3, #8]
sBreakDeadTimeConfig.DeadTime = 0;
800042c: 1d3b adds r3, r7, #4
800042e: 2200 movs r2, #0
8000430: 60da str r2, [r3, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8000432: 1d3b adds r3, r7, #4
8000434: 2200 movs r2, #0
8000436: 611a str r2, [r3, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000438: 1d3b adds r3, r7, #4
800043a: 2280 movs r2, #128 @ 0x80
800043c: 0192 lsls r2, r2, #6
800043e: 615a str r2, [r3, #20]
sBreakDeadTimeConfig.BreakFilter = 0;
8000440: 1d3b adds r3, r7, #4
8000442: 2200 movs r2, #0
8000444: 619a str r2, [r3, #24]
sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
8000446: 1d3b adds r3, r7, #4
8000448: 2200 movs r2, #0
800044a: 61da str r2, [r3, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
800044c: 1d3b adds r3, r7, #4
800044e: 2200 movs r2, #0
8000450: 621a str r2, [r3, #32]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
8000452: 1d3b adds r3, r7, #4
8000454: 2280 movs r2, #128 @ 0x80
8000456: 0492 lsls r2, r2, #18
8000458: 625a str r2, [r3, #36] @ 0x24
sBreakDeadTimeConfig.Break2Filter = 0;
800045a: 1d3b adds r3, r7, #4
800045c: 2200 movs r2, #0
800045e: 629a str r2, [r3, #40] @ 0x28
sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
8000460: 1d3b adds r3, r7, #4
8000462: 2200 movs r2, #0
8000464: 62da str r2, [r3, #44] @ 0x2c
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8000466: 1d3b adds r3, r7, #4
8000468: 2200 movs r2, #0
800046a: 631a str r2, [r3, #48] @ 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
800046c: 1d3a adds r2, r7, #4
800046e: 4b08 ldr r3, [pc, #32] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000470: 0011 movs r1, r2
8000472: 0018 movs r0, r3
8000474: f002 f82a bl 80024cc <HAL_TIMEx_ConfigBreakDeadTime>
8000478: 1e03 subs r3, r0, #0
800047a: d001 beq.n 8000480 <MX_TIM1_Init+0x1bc>
{
Error_Handler();
800047c: f000 f8da bl 8000634 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
8000480: 4b03 ldr r3, [pc, #12] @ (8000490 <MX_TIM1_Init+0x1cc>)
8000482: 0018 movs r0, r3
8000484: f000 f934 bl 80006f0 <HAL_TIM_MspPostInit>
}
8000488: 46c0 nop @ (mov r8, r8)
800048a: 46bd mov sp, r7
800048c: b01c add sp, #112 @ 0x70
800048e: bd80 pop {r7, pc}
8000490: 20000028 .word 0x20000028
8000494: 40012c00 .word 0x40012c00
8000498: 0000ffff .word 0x0000ffff
0800049c <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
800049c: b580 push {r7, lr}
800049e: b08e sub sp, #56 @ 0x38
80004a0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80004a2: 2328 movs r3, #40 @ 0x28
80004a4: 18fb adds r3, r7, r3
80004a6: 0018 movs r0, r3
80004a8: 2310 movs r3, #16
80004aa: 001a movs r2, r3
80004ac: 2100 movs r1, #0
80004ae: f002 f8a9 bl 8002604 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
80004b2: 231c movs r3, #28
80004b4: 18fb adds r3, r7, r3
80004b6: 0018 movs r0, r3
80004b8: 230c movs r3, #12
80004ba: 001a movs r2, r3
80004bc: 2100 movs r1, #0
80004be: f002 f8a1 bl 8002604 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
80004c2: 003b movs r3, r7
80004c4: 0018 movs r0, r3
80004c6: 231c movs r3, #28
80004c8: 001a movs r2, r3
80004ca: 2100 movs r1, #0
80004cc: f002 f89a bl 8002604 <memset>
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80004d0: 4b3e ldr r3, [pc, #248] @ (80005cc <MX_TIM3_Init+0x130>)
80004d2: 4a3f ldr r2, [pc, #252] @ (80005d0 <MX_TIM3_Init+0x134>)
80004d4: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80004d6: 4b3d ldr r3, [pc, #244] @ (80005cc <MX_TIM3_Init+0x130>)
80004d8: 2200 movs r2, #0
80004da: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80004dc: 4b3b ldr r3, [pc, #236] @ (80005cc <MX_TIM3_Init+0x130>)
80004de: 2200 movs r2, #0
80004e0: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
80004e2: 4b3a ldr r3, [pc, #232] @ (80005cc <MX_TIM3_Init+0x130>)
80004e4: 4a3b ldr r2, [pc, #236] @ (80005d4 <MX_TIM3_Init+0x138>)
80004e6: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80004e8: 4b38 ldr r3, [pc, #224] @ (80005cc <MX_TIM3_Init+0x130>)
80004ea: 2200 movs r2, #0
80004ec: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80004ee: 4b37 ldr r3, [pc, #220] @ (80005cc <MX_TIM3_Init+0x130>)
80004f0: 2200 movs r2, #0
80004f2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
80004f4: 4b35 ldr r3, [pc, #212] @ (80005cc <MX_TIM3_Init+0x130>)
80004f6: 0018 movs r0, r3
80004f8: f001 f946 bl 8001788 <HAL_TIM_Base_Init>
80004fc: 1e03 subs r3, r0, #0
80004fe: d001 beq.n 8000504 <MX_TIM3_Init+0x68>
{
Error_Handler();
8000500: f000 f898 bl 8000634 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000504: 2128 movs r1, #40 @ 0x28
8000506: 187b adds r3, r7, r1
8000508: 2280 movs r2, #128 @ 0x80
800050a: 0152 lsls r2, r2, #5
800050c: 601a str r2, [r3, #0]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
800050e: 187a adds r2, r7, r1
8000510: 4b2e ldr r3, [pc, #184] @ (80005cc <MX_TIM3_Init+0x130>)
8000512: 0011 movs r1, r2
8000514: 0018 movs r0, r3
8000516: f001 faef bl 8001af8 <HAL_TIM_ConfigClockSource>
800051a: 1e03 subs r3, r0, #0
800051c: d001 beq.n 8000522 <MX_TIM3_Init+0x86>
{
Error_Handler();
800051e: f000 f889 bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8000522: 4b2a ldr r3, [pc, #168] @ (80005cc <MX_TIM3_Init+0x130>)
8000524: 0018 movs r0, r3
8000526: f001 f987 bl 8001838 <HAL_TIM_PWM_Init>
800052a: 1e03 subs r3, r0, #0
800052c: d001 beq.n 8000532 <MX_TIM3_Init+0x96>
{
Error_Handler();
800052e: f000 f881 bl 8000634 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000532: 211c movs r1, #28
8000534: 187b adds r3, r7, r1
8000536: 2200 movs r2, #0
8000538: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800053a: 187b adds r3, r7, r1
800053c: 2200 movs r2, #0
800053e: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000540: 187a adds r2, r7, r1
8000542: 4b22 ldr r3, [pc, #136] @ (80005cc <MX_TIM3_Init+0x130>)
8000544: 0011 movs r1, r2
8000546: 0018 movs r0, r3
8000548: f001 ff5e bl 8002408 <HAL_TIMEx_MasterConfigSynchronization>
800054c: 1e03 subs r3, r0, #0
800054e: d001 beq.n 8000554 <MX_TIM3_Init+0xb8>
{
Error_Handler();
8000550: f000 f870 bl 8000634 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000554: 003b movs r3, r7
8000556: 2260 movs r2, #96 @ 0x60
8000558: 601a str r2, [r3, #0]
sConfigOC.Pulse = 0;
800055a: 003b movs r3, r7
800055c: 2200 movs r2, #0
800055e: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000560: 003b movs r3, r7
8000562: 2200 movs r2, #0
8000564: 609a str r2, [r3, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000566: 003b movs r3, r7
8000568: 2200 movs r2, #0
800056a: 611a str r2, [r3, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800056c: 0039 movs r1, r7
800056e: 4b17 ldr r3, [pc, #92] @ (80005cc <MX_TIM3_Init+0x130>)
8000570: 2200 movs r2, #0
8000572: 0018 movs r0, r3
8000574: f001 f9c0 bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
8000578: 1e03 subs r3, r0, #0
800057a: d001 beq.n 8000580 <MX_TIM3_Init+0xe4>
{
Error_Handler();
800057c: f000 f85a bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000580: 0039 movs r1, r7
8000582: 4b12 ldr r3, [pc, #72] @ (80005cc <MX_TIM3_Init+0x130>)
8000584: 2204 movs r2, #4
8000586: 0018 movs r0, r3
8000588: f001 f9b6 bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
800058c: 1e03 subs r3, r0, #0
800058e: d001 beq.n 8000594 <MX_TIM3_Init+0xf8>
{
Error_Handler();
8000590: f000 f850 bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000594: 0039 movs r1, r7
8000596: 4b0d ldr r3, [pc, #52] @ (80005cc <MX_TIM3_Init+0x130>)
8000598: 2208 movs r2, #8
800059a: 0018 movs r0, r3
800059c: f001 f9ac bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
80005a0: 1e03 subs r3, r0, #0
80005a2: d001 beq.n 80005a8 <MX_TIM3_Init+0x10c>
{
Error_Handler();
80005a4: f000 f846 bl 8000634 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
80005a8: 0039 movs r1, r7
80005aa: 4b08 ldr r3, [pc, #32] @ (80005cc <MX_TIM3_Init+0x130>)
80005ac: 220c movs r2, #12
80005ae: 0018 movs r0, r3
80005b0: f001 f9a2 bl 80018f8 <HAL_TIM_PWM_ConfigChannel>
80005b4: 1e03 subs r3, r0, #0
80005b6: d001 beq.n 80005bc <MX_TIM3_Init+0x120>
{
Error_Handler();
80005b8: f000 f83c bl 8000634 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
80005bc: 4b03 ldr r3, [pc, #12] @ (80005cc <MX_TIM3_Init+0x130>)
80005be: 0018 movs r0, r3
80005c0: f000 f896 bl 80006f0 <HAL_TIM_MspPostInit>
}
80005c4: 46c0 nop @ (mov r8, r8)
80005c6: 46bd mov sp, r7
80005c8: b00e add sp, #56 @ 0x38
80005ca: bd80 pop {r7, pc}
80005cc: 20000074 .word 0x20000074
80005d0: 40000400 .word 0x40000400
80005d4: 0000ffff .word 0x0000ffff
080005d8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80005d8: b580 push {r7, lr}
80005da: b084 sub sp, #16
80005dc: af00 add r7, sp, #0
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80005de: 4b14 ldr r3, [pc, #80] @ (8000630 <MX_GPIO_Init+0x58>)
80005e0: 6b5a ldr r2, [r3, #52] @ 0x34
80005e2: 4b13 ldr r3, [pc, #76] @ (8000630 <MX_GPIO_Init+0x58>)
80005e4: 2120 movs r1, #32
80005e6: 430a orrs r2, r1
80005e8: 635a str r2, [r3, #52] @ 0x34
80005ea: 4b11 ldr r3, [pc, #68] @ (8000630 <MX_GPIO_Init+0x58>)
80005ec: 6b5b ldr r3, [r3, #52] @ 0x34
80005ee: 2220 movs r2, #32
80005f0: 4013 ands r3, r2
80005f2: 60fb str r3, [r7, #12]
80005f4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80005f6: 4b0e ldr r3, [pc, #56] @ (8000630 <MX_GPIO_Init+0x58>)
80005f8: 6b5a ldr r2, [r3, #52] @ 0x34
80005fa: 4b0d ldr r3, [pc, #52] @ (8000630 <MX_GPIO_Init+0x58>)
80005fc: 2101 movs r1, #1
80005fe: 430a orrs r2, r1
8000600: 635a str r2, [r3, #52] @ 0x34
8000602: 4b0b ldr r3, [pc, #44] @ (8000630 <MX_GPIO_Init+0x58>)
8000604: 6b5b ldr r3, [r3, #52] @ 0x34
8000606: 2201 movs r2, #1
8000608: 4013 ands r3, r2
800060a: 60bb str r3, [r7, #8]
800060c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
800060e: 4b08 ldr r3, [pc, #32] @ (8000630 <MX_GPIO_Init+0x58>)
8000610: 6b5a ldr r2, [r3, #52] @ 0x34
8000612: 4b07 ldr r3, [pc, #28] @ (8000630 <MX_GPIO_Init+0x58>)
8000614: 2102 movs r1, #2
8000616: 430a orrs r2, r1
8000618: 635a str r2, [r3, #52] @ 0x34
800061a: 4b05 ldr r3, [pc, #20] @ (8000630 <MX_GPIO_Init+0x58>)
800061c: 6b5b ldr r3, [r3, #52] @ 0x34
800061e: 2202 movs r2, #2
8000620: 4013 ands r3, r2
8000622: 607b str r3, [r7, #4]
8000624: 687b ldr r3, [r7, #4]
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000626: 46c0 nop @ (mov r8, r8)
8000628: 46bd mov sp, r7
800062a: b004 add sp, #16
800062c: bd80 pop {r7, pc}
800062e: 46c0 nop @ (mov r8, r8)
8000630: 40021000 .word 0x40021000
08000634 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000634: b580 push {r7, lr}
8000636: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000638: b672 cpsid i
}
800063a: 46c0 nop @ (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800063c: 46c0 nop @ (mov r8, r8)
800063e: e7fd b.n 800063c <Error_Handler+0x8>
08000640 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000640: b580 push {r7, lr}
8000642: b082 sub sp, #8
8000644: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000646: 4b0f ldr r3, [pc, #60] @ (8000684 <HAL_MspInit+0x44>)
8000648: 6c1a ldr r2, [r3, #64] @ 0x40
800064a: 4b0e ldr r3, [pc, #56] @ (8000684 <HAL_MspInit+0x44>)
800064c: 2101 movs r1, #1
800064e: 430a orrs r2, r1
8000650: 641a str r2, [r3, #64] @ 0x40
8000652: 4b0c ldr r3, [pc, #48] @ (8000684 <HAL_MspInit+0x44>)
8000654: 6c1b ldr r3, [r3, #64] @ 0x40
8000656: 2201 movs r2, #1
8000658: 4013 ands r3, r2
800065a: 607b str r3, [r7, #4]
800065c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800065e: 4b09 ldr r3, [pc, #36] @ (8000684 <HAL_MspInit+0x44>)
8000660: 6bda ldr r2, [r3, #60] @ 0x3c
8000662: 4b08 ldr r3, [pc, #32] @ (8000684 <HAL_MspInit+0x44>)
8000664: 2180 movs r1, #128 @ 0x80
8000666: 0549 lsls r1, r1, #21
8000668: 430a orrs r2, r1
800066a: 63da str r2, [r3, #60] @ 0x3c
800066c: 4b05 ldr r3, [pc, #20] @ (8000684 <HAL_MspInit+0x44>)
800066e: 6bda ldr r2, [r3, #60] @ 0x3c
8000670: 2380 movs r3, #128 @ 0x80
8000672: 055b lsls r3, r3, #21
8000674: 4013 ands r3, r2
8000676: 603b str r3, [r7, #0]
8000678: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800067a: 46c0 nop @ (mov r8, r8)
800067c: 46bd mov sp, r7
800067e: b002 add sp, #8
8000680: bd80 pop {r7, pc}
8000682: 46c0 nop @ (mov r8, r8)
8000684: 40021000 .word 0x40021000
08000688 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000688: b580 push {r7, lr}
800068a: b084 sub sp, #16
800068c: af00 add r7, sp, #0
800068e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000690: 687b ldr r3, [r7, #4]
8000692: 681b ldr r3, [r3, #0]
8000694: 4a13 ldr r2, [pc, #76] @ (80006e4 <HAL_TIM_Base_MspInit+0x5c>)
8000696: 4293 cmp r3, r2
8000698: d10e bne.n 80006b8 <HAL_TIM_Base_MspInit+0x30>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
800069a: 4b13 ldr r3, [pc, #76] @ (80006e8 <HAL_TIM_Base_MspInit+0x60>)
800069c: 6c1a ldr r2, [r3, #64] @ 0x40
800069e: 4b12 ldr r3, [pc, #72] @ (80006e8 <HAL_TIM_Base_MspInit+0x60>)
80006a0: 2180 movs r1, #128 @ 0x80
80006a2: 0109 lsls r1, r1, #4
80006a4: 430a orrs r2, r1
80006a6: 641a str r2, [r3, #64] @ 0x40
80006a8: 4b0f ldr r3, [pc, #60] @ (80006e8 <HAL_TIM_Base_MspInit+0x60>)
80006aa: 6c1a ldr r2, [r3, #64] @ 0x40
80006ac: 2380 movs r3, #128 @ 0x80
80006ae: 011b lsls r3, r3, #4
80006b0: 4013 ands r3, r2
80006b2: 60fb str r3, [r7, #12]
80006b4: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
80006b6: e010 b.n 80006da <HAL_TIM_Base_MspInit+0x52>
else if(htim_base->Instance==TIM3)
80006b8: 687b ldr r3, [r7, #4]
80006ba: 681b ldr r3, [r3, #0]
80006bc: 4a0b ldr r2, [pc, #44] @ (80006ec <HAL_TIM_Base_MspInit+0x64>)
80006be: 4293 cmp r3, r2
80006c0: d10b bne.n 80006da <HAL_TIM_Base_MspInit+0x52>
__HAL_RCC_TIM3_CLK_ENABLE();
80006c2: 4b09 ldr r3, [pc, #36] @ (80006e8 <HAL_TIM_Base_MspInit+0x60>)
80006c4: 6bda ldr r2, [r3, #60] @ 0x3c
80006c6: 4b08 ldr r3, [pc, #32] @ (80006e8 <HAL_TIM_Base_MspInit+0x60>)
80006c8: 2102 movs r1, #2
80006ca: 430a orrs r2, r1
80006cc: 63da str r2, [r3, #60] @ 0x3c
80006ce: 4b06 ldr r3, [pc, #24] @ (80006e8 <HAL_TIM_Base_MspInit+0x60>)
80006d0: 6bdb ldr r3, [r3, #60] @ 0x3c
80006d2: 2202 movs r2, #2
80006d4: 4013 ands r3, r2
80006d6: 60bb str r3, [r7, #8]
80006d8: 68bb ldr r3, [r7, #8]
}
80006da: 46c0 nop @ (mov r8, r8)
80006dc: 46bd mov sp, r7
80006de: b004 add sp, #16
80006e0: bd80 pop {r7, pc}
80006e2: 46c0 nop @ (mov r8, r8)
80006e4: 40012c00 .word 0x40012c00
80006e8: 40021000 .word 0x40021000
80006ec: 40000400 .word 0x40000400
080006f0 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
80006f0: b590 push {r4, r7, lr}
80006f2: b08b sub sp, #44 @ 0x2c
80006f4: af00 add r7, sp, #0
80006f6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006f8: 2414 movs r4, #20
80006fa: 193b adds r3, r7, r4
80006fc: 0018 movs r0, r3
80006fe: 2314 movs r3, #20
8000700: 001a movs r2, r3
8000702: 2100 movs r1, #0
8000704: f001 ff7e bl 8002604 <memset>
if(htim->Instance==TIM1)
8000708: 687b ldr r3, [r7, #4]
800070a: 681b ldr r3, [r3, #0]
800070c: 4a3a ldr r2, [pc, #232] @ (80007f8 <HAL_TIM_MspPostInit+0x108>)
800070e: 4293 cmp r3, r2
8000710: d124 bne.n 800075c <HAL_TIM_MspPostInit+0x6c>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000712: 4b3a ldr r3, [pc, #232] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000714: 6b5a ldr r2, [r3, #52] @ 0x34
8000716: 4b39 ldr r3, [pc, #228] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000718: 2101 movs r1, #1
800071a: 430a orrs r2, r1
800071c: 635a str r2, [r3, #52] @ 0x34
800071e: 4b37 ldr r3, [pc, #220] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000720: 6b5b ldr r3, [r3, #52] @ 0x34
8000722: 2201 movs r2, #1
8000724: 4013 ands r3, r2
8000726: 613b str r3, [r7, #16]
8000728: 693b ldr r3, [r7, #16]
PA8 ------> TIM1_CH1
PA9 ------> TIM1_CH2
PA10 ------> TIM1_CH3
PA11 [PA9] ------> TIM1_CH4
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11;
800072a: 193b adds r3, r7, r4
800072c: 22f0 movs r2, #240 @ 0xf0
800072e: 0112 lsls r2, r2, #4
8000730: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000732: 0021 movs r1, r4
8000734: 187b adds r3, r7, r1
8000736: 2202 movs r2, #2
8000738: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800073a: 187b adds r3, r7, r1
800073c: 2200 movs r2, #0
800073e: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000740: 187b adds r3, r7, r1
8000742: 2200 movs r2, #0
8000744: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
8000746: 187b adds r3, r7, r1
8000748: 2202 movs r2, #2
800074a: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800074c: 187a adds r2, r7, r1
800074e: 23a0 movs r3, #160 @ 0xa0
8000750: 05db lsls r3, r3, #23
8000752: 0011 movs r1, r2
8000754: 0018 movs r0, r3
8000756: f000 f9d9 bl 8000b0c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
800075a: e049 b.n 80007f0 <HAL_TIM_MspPostInit+0x100>
else if(htim->Instance==TIM3)
800075c: 687b ldr r3, [r7, #4]
800075e: 681b ldr r3, [r3, #0]
8000760: 4a27 ldr r2, [pc, #156] @ (8000800 <HAL_TIM_MspPostInit+0x110>)
8000762: 4293 cmp r3, r2
8000764: d144 bne.n 80007f0 <HAL_TIM_MspPostInit+0x100>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000766: 4b25 ldr r3, [pc, #148] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000768: 6b5a ldr r2, [r3, #52] @ 0x34
800076a: 4b24 ldr r3, [pc, #144] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
800076c: 2101 movs r1, #1
800076e: 430a orrs r2, r1
8000770: 635a str r2, [r3, #52] @ 0x34
8000772: 4b22 ldr r3, [pc, #136] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000774: 6b5b ldr r3, [r3, #52] @ 0x34
8000776: 2201 movs r2, #1
8000778: 4013 ands r3, r2
800077a: 60fb str r3, [r7, #12]
800077c: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
800077e: 4b1f ldr r3, [pc, #124] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000780: 6b5a ldr r2, [r3, #52] @ 0x34
8000782: 4b1e ldr r3, [pc, #120] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
8000784: 2102 movs r1, #2
8000786: 430a orrs r2, r1
8000788: 635a str r2, [r3, #52] @ 0x34
800078a: 4b1c ldr r3, [pc, #112] @ (80007fc <HAL_TIM_MspPostInit+0x10c>)
800078c: 6b5b ldr r3, [r3, #52] @ 0x34
800078e: 2202 movs r2, #2
8000790: 4013 ands r3, r2
8000792: 60bb str r3, [r7, #8]
8000794: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8000796: 2414 movs r4, #20
8000798: 193b adds r3, r7, r4
800079a: 22c0 movs r2, #192 @ 0xc0
800079c: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800079e: 193b adds r3, r7, r4
80007a0: 2202 movs r2, #2
80007a2: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80007a4: 193b adds r3, r7, r4
80007a6: 2200 movs r2, #0
80007a8: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80007aa: 193b adds r3, r7, r4
80007ac: 2200 movs r2, #0
80007ae: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
80007b0: 193b adds r3, r7, r4
80007b2: 2201 movs r2, #1
80007b4: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80007b6: 193a adds r2, r7, r4
80007b8: 23a0 movs r3, #160 @ 0xa0
80007ba: 05db lsls r3, r3, #23
80007bc: 0011 movs r1, r2
80007be: 0018 movs r0, r3
80007c0: f000 f9a4 bl 8000b0c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
80007c4: 0021 movs r1, r4
80007c6: 187b adds r3, r7, r1
80007c8: 2203 movs r2, #3
80007ca: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80007cc: 187b adds r3, r7, r1
80007ce: 2202 movs r2, #2
80007d0: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80007d2: 187b adds r3, r7, r1
80007d4: 2200 movs r2, #0
80007d6: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80007d8: 187b adds r3, r7, r1
80007da: 2200 movs r2, #0
80007dc: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
80007de: 187b adds r3, r7, r1
80007e0: 2201 movs r2, #1
80007e2: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80007e4: 187b adds r3, r7, r1
80007e6: 4a07 ldr r2, [pc, #28] @ (8000804 <HAL_TIM_MspPostInit+0x114>)
80007e8: 0019 movs r1, r3
80007ea: 0010 movs r0, r2
80007ec: f000 f98e bl 8000b0c <HAL_GPIO_Init>
}
80007f0: 46c0 nop @ (mov r8, r8)
80007f2: 46bd mov sp, r7
80007f4: b00b add sp, #44 @ 0x2c
80007f6: bd90 pop {r4, r7, pc}
80007f8: 40012c00 .word 0x40012c00
80007fc: 40021000 .word 0x40021000
8000800: 40000400 .word 0x40000400
8000804: 50000400 .word 0x50000400
08000808 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000808: b580 push {r7, lr}
800080a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800080c: 46c0 nop @ (mov r8, r8)
800080e: e7fd b.n 800080c <NMI_Handler+0x4>
08000810 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000810: b580 push {r7, lr}
8000812: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000814: 46c0 nop @ (mov r8, r8)
8000816: e7fd b.n 8000814 <HardFault_Handler+0x4>
08000818 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000818: b580 push {r7, lr}
800081a: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
800081c: 46c0 nop @ (mov r8, r8)
800081e: 46bd mov sp, r7
8000820: bd80 pop {r7, pc}
08000822 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000822: b580 push {r7, lr}
8000824: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000826: 46c0 nop @ (mov r8, r8)
8000828: 46bd mov sp, r7
800082a: bd80 pop {r7, pc}
0800082c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800082c: b580 push {r7, lr}
800082e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000830: f000 f89c bl 800096c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000834: 46c0 nop @ (mov r8, r8)
8000836: 46bd mov sp, r7
8000838: bd80 pop {r7, pc}
0800083a <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
800083a: b580 push {r7, lr}
800083c: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
800083e: 46c0 nop @ (mov r8, r8)
8000840: 46bd mov sp, r7
8000842: bd80 pop {r7, pc}
08000844 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000844: 480d ldr r0, [pc, #52] @ (800087c <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000846: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8000848: f7ff fff7 bl 800083a <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800084c: 480c ldr r0, [pc, #48] @ (8000880 <LoopForever+0x6>)
ldr r1, =_edata
800084e: 490d ldr r1, [pc, #52] @ (8000884 <LoopForever+0xa>)
ldr r2, =_sidata
8000850: 4a0d ldr r2, [pc, #52] @ (8000888 <LoopForever+0xe>)
movs r3, #0
8000852: 2300 movs r3, #0
b LoopCopyDataInit
8000854: e002 b.n 800085c <LoopCopyDataInit>
08000856 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000856: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000858: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800085a: 3304 adds r3, #4
0800085c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800085c: 18c4 adds r4, r0, r3
cmp r4, r1
800085e: 428c cmp r4, r1
bcc CopyDataInit
8000860: d3f9 bcc.n 8000856 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000862: 4a0a ldr r2, [pc, #40] @ (800088c <LoopForever+0x12>)
ldr r4, =_ebss
8000864: 4c0a ldr r4, [pc, #40] @ (8000890 <LoopForever+0x16>)
movs r3, #0
8000866: 2300 movs r3, #0
b LoopFillZerobss
8000868: e001 b.n 800086e <LoopFillZerobss>
0800086a <FillZerobss>:
FillZerobss:
str r3, [r2]
800086a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800086c: 3204 adds r2, #4
0800086e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800086e: 42a2 cmp r2, r4
bcc FillZerobss
8000870: d3fb bcc.n 800086a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000872: f001 fecf bl 8002614 <__libc_init_array>
/* Call the application s entry point.*/
bl main
8000876: f7ff fccf bl 8000218 <main>
0800087a <LoopForever>:
LoopForever:
b LoopForever
800087a: e7fe b.n 800087a <LoopForever>
ldr r0, =_estack
800087c: 20002000 .word 0x20002000
ldr r0, =_sdata
8000880: 20000000 .word 0x20000000
ldr r1, =_edata
8000884: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000888: 08002710 .word 0x08002710
ldr r2, =_sbss
800088c: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000890: 200000c4 .word 0x200000c4
08000894 <ADC1_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000894: e7fe b.n 8000894 <ADC1_IRQHandler>
...
08000898 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000898: b580 push {r7, lr}
800089a: b082 sub sp, #8
800089c: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
800089e: 1dfb adds r3, r7, #7
80008a0: 2200 movs r2, #0
80008a2: 701a strb r2, [r3, #0]
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80008a4: 4b0b ldr r3, [pc, #44] @ (80008d4 <HAL_Init+0x3c>)
80008a6: 681a ldr r2, [r3, #0]
80008a8: 4b0a ldr r3, [pc, #40] @ (80008d4 <HAL_Init+0x3c>)
80008aa: 2180 movs r1, #128 @ 0x80
80008ac: 0049 lsls r1, r1, #1
80008ae: 430a orrs r2, r1
80008b0: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
80008b2: 2003 movs r0, #3
80008b4: f000 f810 bl 80008d8 <HAL_InitTick>
80008b8: 1e03 subs r3, r0, #0
80008ba: d003 beq.n 80008c4 <HAL_Init+0x2c>
{
status = HAL_ERROR;
80008bc: 1dfb adds r3, r7, #7
80008be: 2201 movs r2, #1
80008c0: 701a strb r2, [r3, #0]
80008c2: e001 b.n 80008c8 <HAL_Init+0x30>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
80008c4: f7ff febc bl 8000640 <HAL_MspInit>
}
/* Return function status */
return status;
80008c8: 1dfb adds r3, r7, #7
80008ca: 781b ldrb r3, [r3, #0]
}
80008cc: 0018 movs r0, r3
80008ce: 46bd mov sp, r7
80008d0: b002 add sp, #8
80008d2: bd80 pop {r7, pc}
80008d4: 40022000 .word 0x40022000
080008d8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80008d8: b590 push {r4, r7, lr}
80008da: b085 sub sp, #20
80008dc: af00 add r7, sp, #0
80008de: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80008e0: 230f movs r3, #15
80008e2: 18fb adds r3, r7, r3
80008e4: 2200 movs r2, #0
80008e6: 701a strb r2, [r3, #0]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
80008e8: 4b1d ldr r3, [pc, #116] @ (8000960 <HAL_InitTick+0x88>)
80008ea: 781b ldrb r3, [r3, #0]
80008ec: 2b00 cmp r3, #0
80008ee: d02b beq.n 8000948 <HAL_InitTick+0x70>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
80008f0: 4b1c ldr r3, [pc, #112] @ (8000964 <HAL_InitTick+0x8c>)
80008f2: 681c ldr r4, [r3, #0]
80008f4: 4b1a ldr r3, [pc, #104] @ (8000960 <HAL_InitTick+0x88>)
80008f6: 781b ldrb r3, [r3, #0]
80008f8: 0019 movs r1, r3
80008fa: 23fa movs r3, #250 @ 0xfa
80008fc: 0098 lsls r0, r3, #2
80008fe: f7ff fbff bl 8000100 <__udivsi3>
8000902: 0003 movs r3, r0
8000904: 0019 movs r1, r3
8000906: 0020 movs r0, r4
8000908: f7ff fbfa bl 8000100 <__udivsi3>
800090c: 0003 movs r3, r0
800090e: 0018 movs r0, r3
8000910: f000 f8ef bl 8000af2 <HAL_SYSTICK_Config>
8000914: 1e03 subs r3, r0, #0
8000916: d112 bne.n 800093e <HAL_InitTick+0x66>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000918: 687b ldr r3, [r7, #4]
800091a: 2b03 cmp r3, #3
800091c: d80a bhi.n 8000934 <HAL_InitTick+0x5c>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800091e: 6879 ldr r1, [r7, #4]
8000920: 2301 movs r3, #1
8000922: 425b negs r3, r3
8000924: 2200 movs r2, #0
8000926: 0018 movs r0, r3
8000928: f000 f8ce bl 8000ac8 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800092c: 4b0e ldr r3, [pc, #56] @ (8000968 <HAL_InitTick+0x90>)
800092e: 687a ldr r2, [r7, #4]
8000930: 601a str r2, [r3, #0]
8000932: e00d b.n 8000950 <HAL_InitTick+0x78>
}
else
{
status = HAL_ERROR;
8000934: 230f movs r3, #15
8000936: 18fb adds r3, r7, r3
8000938: 2201 movs r2, #1
800093a: 701a strb r2, [r3, #0]
800093c: e008 b.n 8000950 <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
800093e: 230f movs r3, #15
8000940: 18fb adds r3, r7, r3
8000942: 2201 movs r2, #1
8000944: 701a strb r2, [r3, #0]
8000946: e003 b.n 8000950 <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8000948: 230f movs r3, #15
800094a: 18fb adds r3, r7, r3
800094c: 2201 movs r2, #1
800094e: 701a strb r2, [r3, #0]
}
/* Return function status */
return status;
8000950: 230f movs r3, #15
8000952: 18fb adds r3, r7, r3
8000954: 781b ldrb r3, [r3, #0]
}
8000956: 0018 movs r0, r3
8000958: 46bd mov sp, r7
800095a: b005 add sp, #20
800095c: bd90 pop {r4, r7, pc}
800095e: 46c0 nop @ (mov r8, r8)
8000960: 20000008 .word 0x20000008
8000964: 20000000 .word 0x20000000
8000968: 20000004 .word 0x20000004
0800096c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800096c: b580 push {r7, lr}
800096e: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8000970: 4b05 ldr r3, [pc, #20] @ (8000988 <HAL_IncTick+0x1c>)
8000972: 781b ldrb r3, [r3, #0]
8000974: 001a movs r2, r3
8000976: 4b05 ldr r3, [pc, #20] @ (800098c <HAL_IncTick+0x20>)
8000978: 681b ldr r3, [r3, #0]
800097a: 18d2 adds r2, r2, r3
800097c: 4b03 ldr r3, [pc, #12] @ (800098c <HAL_IncTick+0x20>)
800097e: 601a str r2, [r3, #0]
}
8000980: 46c0 nop @ (mov r8, r8)
8000982: 46bd mov sp, r7
8000984: bd80 pop {r7, pc}
8000986: 46c0 nop @ (mov r8, r8)
8000988: 20000008 .word 0x20000008
800098c: 200000c0 .word 0x200000c0
08000990 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000990: b580 push {r7, lr}
8000992: af00 add r7, sp, #0
return uwTick;
8000994: 4b02 ldr r3, [pc, #8] @ (80009a0 <HAL_GetTick+0x10>)
8000996: 681b ldr r3, [r3, #0]
}
8000998: 0018 movs r0, r3
800099a: 46bd mov sp, r7
800099c: bd80 pop {r7, pc}
800099e: 46c0 nop @ (mov r8, r8)
80009a0: 200000c0 .word 0x200000c0
080009a4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80009a4: b590 push {r4, r7, lr}
80009a6: b083 sub sp, #12
80009a8: af00 add r7, sp, #0
80009aa: 0002 movs r2, r0
80009ac: 6039 str r1, [r7, #0]
80009ae: 1dfb adds r3, r7, #7
80009b0: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80009b2: 1dfb adds r3, r7, #7
80009b4: 781b ldrb r3, [r3, #0]
80009b6: 2b7f cmp r3, #127 @ 0x7f
80009b8: d828 bhi.n 8000a0c <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80009ba: 4a2f ldr r2, [pc, #188] @ (8000a78 <__NVIC_SetPriority+0xd4>)
80009bc: 1dfb adds r3, r7, #7
80009be: 781b ldrb r3, [r3, #0]
80009c0: b25b sxtb r3, r3
80009c2: 089b lsrs r3, r3, #2
80009c4: 33c0 adds r3, #192 @ 0xc0
80009c6: 009b lsls r3, r3, #2
80009c8: 589b ldr r3, [r3, r2]
80009ca: 1dfa adds r2, r7, #7
80009cc: 7812 ldrb r2, [r2, #0]
80009ce: 0011 movs r1, r2
80009d0: 2203 movs r2, #3
80009d2: 400a ands r2, r1
80009d4: 00d2 lsls r2, r2, #3
80009d6: 21ff movs r1, #255 @ 0xff
80009d8: 4091 lsls r1, r2
80009da: 000a movs r2, r1
80009dc: 43d2 mvns r2, r2
80009de: 401a ands r2, r3
80009e0: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80009e2: 683b ldr r3, [r7, #0]
80009e4: 019b lsls r3, r3, #6
80009e6: 22ff movs r2, #255 @ 0xff
80009e8: 401a ands r2, r3
80009ea: 1dfb adds r3, r7, #7
80009ec: 781b ldrb r3, [r3, #0]
80009ee: 0018 movs r0, r3
80009f0: 2303 movs r3, #3
80009f2: 4003 ands r3, r0
80009f4: 00db lsls r3, r3, #3
80009f6: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80009f8: 481f ldr r0, [pc, #124] @ (8000a78 <__NVIC_SetPriority+0xd4>)
80009fa: 1dfb adds r3, r7, #7
80009fc: 781b ldrb r3, [r3, #0]
80009fe: b25b sxtb r3, r3
8000a00: 089b lsrs r3, r3, #2
8000a02: 430a orrs r2, r1
8000a04: 33c0 adds r3, #192 @ 0xc0
8000a06: 009b lsls r3, r3, #2
8000a08: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000a0a: e031 b.n 8000a70 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000a0c: 4a1b ldr r2, [pc, #108] @ (8000a7c <__NVIC_SetPriority+0xd8>)
8000a0e: 1dfb adds r3, r7, #7
8000a10: 781b ldrb r3, [r3, #0]
8000a12: 0019 movs r1, r3
8000a14: 230f movs r3, #15
8000a16: 400b ands r3, r1
8000a18: 3b08 subs r3, #8
8000a1a: 089b lsrs r3, r3, #2
8000a1c: 3306 adds r3, #6
8000a1e: 009b lsls r3, r3, #2
8000a20: 18d3 adds r3, r2, r3
8000a22: 3304 adds r3, #4
8000a24: 681b ldr r3, [r3, #0]
8000a26: 1dfa adds r2, r7, #7
8000a28: 7812 ldrb r2, [r2, #0]
8000a2a: 0011 movs r1, r2
8000a2c: 2203 movs r2, #3
8000a2e: 400a ands r2, r1
8000a30: 00d2 lsls r2, r2, #3
8000a32: 21ff movs r1, #255 @ 0xff
8000a34: 4091 lsls r1, r2
8000a36: 000a movs r2, r1
8000a38: 43d2 mvns r2, r2
8000a3a: 401a ands r2, r3
8000a3c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000a3e: 683b ldr r3, [r7, #0]
8000a40: 019b lsls r3, r3, #6
8000a42: 22ff movs r2, #255 @ 0xff
8000a44: 401a ands r2, r3
8000a46: 1dfb adds r3, r7, #7
8000a48: 781b ldrb r3, [r3, #0]
8000a4a: 0018 movs r0, r3
8000a4c: 2303 movs r3, #3
8000a4e: 4003 ands r3, r0
8000a50: 00db lsls r3, r3, #3
8000a52: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000a54: 4809 ldr r0, [pc, #36] @ (8000a7c <__NVIC_SetPriority+0xd8>)
8000a56: 1dfb adds r3, r7, #7
8000a58: 781b ldrb r3, [r3, #0]
8000a5a: 001c movs r4, r3
8000a5c: 230f movs r3, #15
8000a5e: 4023 ands r3, r4
8000a60: 3b08 subs r3, #8
8000a62: 089b lsrs r3, r3, #2
8000a64: 430a orrs r2, r1
8000a66: 3306 adds r3, #6
8000a68: 009b lsls r3, r3, #2
8000a6a: 18c3 adds r3, r0, r3
8000a6c: 3304 adds r3, #4
8000a6e: 601a str r2, [r3, #0]
}
8000a70: 46c0 nop @ (mov r8, r8)
8000a72: 46bd mov sp, r7
8000a74: b003 add sp, #12
8000a76: bd90 pop {r4, r7, pc}
8000a78: e000e100 .word 0xe000e100
8000a7c: e000ed00 .word 0xe000ed00
08000a80 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000a80: b580 push {r7, lr}
8000a82: b082 sub sp, #8
8000a84: af00 add r7, sp, #0
8000a86: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000a88: 687b ldr r3, [r7, #4]
8000a8a: 1e5a subs r2, r3, #1
8000a8c: 2380 movs r3, #128 @ 0x80
8000a8e: 045b lsls r3, r3, #17
8000a90: 429a cmp r2, r3
8000a92: d301 bcc.n 8000a98 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8000a94: 2301 movs r3, #1
8000a96: e010 b.n 8000aba <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000a98: 4b0a ldr r3, [pc, #40] @ (8000ac4 <SysTick_Config+0x44>)
8000a9a: 687a ldr r2, [r7, #4]
8000a9c: 3a01 subs r2, #1
8000a9e: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000aa0: 2301 movs r3, #1
8000aa2: 425b negs r3, r3
8000aa4: 2103 movs r1, #3
8000aa6: 0018 movs r0, r3
8000aa8: f7ff ff7c bl 80009a4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000aac: 4b05 ldr r3, [pc, #20] @ (8000ac4 <SysTick_Config+0x44>)
8000aae: 2200 movs r2, #0
8000ab0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000ab2: 4b04 ldr r3, [pc, #16] @ (8000ac4 <SysTick_Config+0x44>)
8000ab4: 2207 movs r2, #7
8000ab6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000ab8: 2300 movs r3, #0
}
8000aba: 0018 movs r0, r3
8000abc: 46bd mov sp, r7
8000abe: b002 add sp, #8
8000ac0: bd80 pop {r7, pc}
8000ac2: 46c0 nop @ (mov r8, r8)
8000ac4: e000e010 .word 0xe000e010
08000ac8 <HAL_NVIC_SetPriority>:
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ac8: b580 push {r7, lr}
8000aca: b084 sub sp, #16
8000acc: af00 add r7, sp, #0
8000ace: 60b9 str r1, [r7, #8]
8000ad0: 607a str r2, [r7, #4]
8000ad2: 210f movs r1, #15
8000ad4: 187b adds r3, r7, r1
8000ad6: 1c02 adds r2, r0, #0
8000ad8: 701a strb r2, [r3, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn, PreemptPriority);
8000ada: 68ba ldr r2, [r7, #8]
8000adc: 187b adds r3, r7, r1
8000ade: 781b ldrb r3, [r3, #0]
8000ae0: b25b sxtb r3, r3
8000ae2: 0011 movs r1, r2
8000ae4: 0018 movs r0, r3
8000ae6: f7ff ff5d bl 80009a4 <__NVIC_SetPriority>
}
8000aea: 46c0 nop @ (mov r8, r8)
8000aec: 46bd mov sp, r7
8000aee: b004 add sp, #16
8000af0: bd80 pop {r7, pc}
08000af2 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000af2: b580 push {r7, lr}
8000af4: b082 sub sp, #8
8000af6: af00 add r7, sp, #0
8000af8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000afa: 687b ldr r3, [r7, #4]
8000afc: 0018 movs r0, r3
8000afe: f7ff ffbf bl 8000a80 <SysTick_Config>
8000b02: 0003 movs r3, r0
}
8000b04: 0018 movs r0, r3
8000b06: 46bd mov sp, r7
8000b08: b002 add sp, #8
8000b0a: bd80 pop {r7, pc}
08000b0c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000b0c: b580 push {r7, lr}
8000b0e: b086 sub sp, #24
8000b10: af00 add r7, sp, #0
8000b12: 6078 str r0, [r7, #4]
8000b14: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000b16: 2300 movs r3, #0
8000b18: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000b1a: e147 b.n 8000dac <HAL_GPIO_Init+0x2a0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8000b1c: 683b ldr r3, [r7, #0]
8000b1e: 681b ldr r3, [r3, #0]
8000b20: 2101 movs r1, #1
8000b22: 697a ldr r2, [r7, #20]
8000b24: 4091 lsls r1, r2
8000b26: 000a movs r2, r1
8000b28: 4013 ands r3, r2
8000b2a: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8000b2c: 68fb ldr r3, [r7, #12]
8000b2e: 2b00 cmp r3, #0
8000b30: d100 bne.n 8000b34 <HAL_GPIO_Init+0x28>
8000b32: e138 b.n 8000da6 <HAL_GPIO_Init+0x29a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8000b34: 683b ldr r3, [r7, #0]
8000b36: 685b ldr r3, [r3, #4]
8000b38: 2203 movs r2, #3
8000b3a: 4013 ands r3, r2
8000b3c: 2b01 cmp r3, #1
8000b3e: d005 beq.n 8000b4c <HAL_GPIO_Init+0x40>
8000b40: 683b ldr r3, [r7, #0]
8000b42: 685b ldr r3, [r3, #4]
8000b44: 2203 movs r2, #3
8000b46: 4013 ands r3, r2
8000b48: 2b02 cmp r3, #2
8000b4a: d130 bne.n 8000bae <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000b4c: 687b ldr r3, [r7, #4]
8000b4e: 689b ldr r3, [r3, #8]
8000b50: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
8000b52: 697b ldr r3, [r7, #20]
8000b54: 005b lsls r3, r3, #1
8000b56: 2203 movs r2, #3
8000b58: 409a lsls r2, r3
8000b5a: 0013 movs r3, r2
8000b5c: 43da mvns r2, r3
8000b5e: 693b ldr r3, [r7, #16]
8000b60: 4013 ands r3, r2
8000b62: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8000b64: 683b ldr r3, [r7, #0]
8000b66: 68da ldr r2, [r3, #12]
8000b68: 697b ldr r3, [r7, #20]
8000b6a: 005b lsls r3, r3, #1
8000b6c: 409a lsls r2, r3
8000b6e: 0013 movs r3, r2
8000b70: 693a ldr r2, [r7, #16]
8000b72: 4313 orrs r3, r2
8000b74: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000b76: 687b ldr r3, [r7, #4]
8000b78: 693a ldr r2, [r7, #16]
8000b7a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000b7c: 687b ldr r3, [r7, #4]
8000b7e: 685b ldr r3, [r3, #4]
8000b80: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8000b82: 2201 movs r2, #1
8000b84: 697b ldr r3, [r7, #20]
8000b86: 409a lsls r2, r3
8000b88: 0013 movs r3, r2
8000b8a: 43da mvns r2, r3
8000b8c: 693b ldr r3, [r7, #16]
8000b8e: 4013 ands r3, r2
8000b90: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000b92: 683b ldr r3, [r7, #0]
8000b94: 685b ldr r3, [r3, #4]
8000b96: 091b lsrs r3, r3, #4
8000b98: 2201 movs r2, #1
8000b9a: 401a ands r2, r3
8000b9c: 697b ldr r3, [r7, #20]
8000b9e: 409a lsls r2, r3
8000ba0: 0013 movs r3, r2
8000ba2: 693a ldr r2, [r7, #16]
8000ba4: 4313 orrs r3, r2
8000ba6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000ba8: 687b ldr r3, [r7, #4]
8000baa: 693a ldr r2, [r7, #16]
8000bac: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000bae: 683b ldr r3, [r7, #0]
8000bb0: 685b ldr r3, [r3, #4]
8000bb2: 2203 movs r2, #3
8000bb4: 4013 ands r3, r2
8000bb6: 2b03 cmp r3, #3
8000bb8: d017 beq.n 8000bea <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000bba: 687b ldr r3, [r7, #4]
8000bbc: 68db ldr r3, [r3, #12]
8000bbe: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
8000bc0: 697b ldr r3, [r7, #20]
8000bc2: 005b lsls r3, r3, #1
8000bc4: 2203 movs r2, #3
8000bc6: 409a lsls r2, r3
8000bc8: 0013 movs r3, r2
8000bca: 43da mvns r2, r3
8000bcc: 693b ldr r3, [r7, #16]
8000bce: 4013 ands r3, r2
8000bd0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8000bd2: 683b ldr r3, [r7, #0]
8000bd4: 689a ldr r2, [r3, #8]
8000bd6: 697b ldr r3, [r7, #20]
8000bd8: 005b lsls r3, r3, #1
8000bda: 409a lsls r2, r3
8000bdc: 0013 movs r3, r2
8000bde: 693a ldr r2, [r7, #16]
8000be0: 4313 orrs r3, r2
8000be2: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000be4: 687b ldr r3, [r7, #4]
8000be6: 693a ldr r2, [r7, #16]
8000be8: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000bea: 683b ldr r3, [r7, #0]
8000bec: 685b ldr r3, [r3, #4]
8000bee: 2203 movs r2, #3
8000bf0: 4013 ands r3, r2
8000bf2: 2b02 cmp r3, #2
8000bf4: d123 bne.n 8000c3e <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8000bf6: 697b ldr r3, [r7, #20]
8000bf8: 08da lsrs r2, r3, #3
8000bfa: 687b ldr r3, [r7, #4]
8000bfc: 3208 adds r2, #8
8000bfe: 0092 lsls r2, r2, #2
8000c00: 58d3 ldr r3, [r2, r3]
8000c02: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8000c04: 697b ldr r3, [r7, #20]
8000c06: 2207 movs r2, #7
8000c08: 4013 ands r3, r2
8000c0a: 009b lsls r3, r3, #2
8000c0c: 220f movs r2, #15
8000c0e: 409a lsls r2, r3
8000c10: 0013 movs r3, r2
8000c12: 43da mvns r2, r3
8000c14: 693b ldr r3, [r7, #16]
8000c16: 4013 ands r3, r2
8000c18: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8000c1a: 683b ldr r3, [r7, #0]
8000c1c: 691a ldr r2, [r3, #16]
8000c1e: 697b ldr r3, [r7, #20]
8000c20: 2107 movs r1, #7
8000c22: 400b ands r3, r1
8000c24: 009b lsls r3, r3, #2
8000c26: 409a lsls r2, r3
8000c28: 0013 movs r3, r2
8000c2a: 693a ldr r2, [r7, #16]
8000c2c: 4313 orrs r3, r2
8000c2e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8000c30: 697b ldr r3, [r7, #20]
8000c32: 08da lsrs r2, r3, #3
8000c34: 687b ldr r3, [r7, #4]
8000c36: 3208 adds r2, #8
8000c38: 0092 lsls r2, r2, #2
8000c3a: 6939 ldr r1, [r7, #16]
8000c3c: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000c3e: 687b ldr r3, [r7, #4]
8000c40: 681b ldr r3, [r3, #0]
8000c42: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8000c44: 697b ldr r3, [r7, #20]
8000c46: 005b lsls r3, r3, #1
8000c48: 2203 movs r2, #3
8000c4a: 409a lsls r2, r3
8000c4c: 0013 movs r3, r2
8000c4e: 43da mvns r2, r3
8000c50: 693b ldr r3, [r7, #16]
8000c52: 4013 ands r3, r2
8000c54: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8000c56: 683b ldr r3, [r7, #0]
8000c58: 685b ldr r3, [r3, #4]
8000c5a: 2203 movs r2, #3
8000c5c: 401a ands r2, r3
8000c5e: 697b ldr r3, [r7, #20]
8000c60: 005b lsls r3, r3, #1
8000c62: 409a lsls r2, r3
8000c64: 0013 movs r3, r2
8000c66: 693a ldr r2, [r7, #16]
8000c68: 4313 orrs r3, r2
8000c6a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000c6c: 687b ldr r3, [r7, #4]
8000c6e: 693a ldr r2, [r7, #16]
8000c70: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8000c72: 683b ldr r3, [r7, #0]
8000c74: 685a ldr r2, [r3, #4]
8000c76: 23c0 movs r3, #192 @ 0xc0
8000c78: 029b lsls r3, r3, #10
8000c7a: 4013 ands r3, r2
8000c7c: d100 bne.n 8000c80 <HAL_GPIO_Init+0x174>
8000c7e: e092 b.n 8000da6 <HAL_GPIO_Init+0x29a>
{
temp = EXTI->EXTICR[position >> 2u];
8000c80: 4a50 ldr r2, [pc, #320] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000c82: 697b ldr r3, [r7, #20]
8000c84: 089b lsrs r3, r3, #2
8000c86: 3318 adds r3, #24
8000c88: 009b lsls r3, r3, #2
8000c8a: 589b ldr r3, [r3, r2]
8000c8c: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
8000c8e: 697b ldr r3, [r7, #20]
8000c90: 2203 movs r2, #3
8000c92: 4013 ands r3, r2
8000c94: 00db lsls r3, r3, #3
8000c96: 220f movs r2, #15
8000c98: 409a lsls r2, r3
8000c9a: 0013 movs r3, r2
8000c9c: 43da mvns r2, r3
8000c9e: 693b ldr r3, [r7, #16]
8000ca0: 4013 ands r3, r2
8000ca2: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
8000ca4: 687a ldr r2, [r7, #4]
8000ca6: 23a0 movs r3, #160 @ 0xa0
8000ca8: 05db lsls r3, r3, #23
8000caa: 429a cmp r2, r3
8000cac: d013 beq.n 8000cd6 <HAL_GPIO_Init+0x1ca>
8000cae: 687b ldr r3, [r7, #4]
8000cb0: 4a45 ldr r2, [pc, #276] @ (8000dc8 <HAL_GPIO_Init+0x2bc>)
8000cb2: 4293 cmp r3, r2
8000cb4: d00d beq.n 8000cd2 <HAL_GPIO_Init+0x1c6>
8000cb6: 687b ldr r3, [r7, #4]
8000cb8: 4a44 ldr r2, [pc, #272] @ (8000dcc <HAL_GPIO_Init+0x2c0>)
8000cba: 4293 cmp r3, r2
8000cbc: d007 beq.n 8000cce <HAL_GPIO_Init+0x1c2>
8000cbe: 687b ldr r3, [r7, #4]
8000cc0: 4a43 ldr r2, [pc, #268] @ (8000dd0 <HAL_GPIO_Init+0x2c4>)
8000cc2: 4293 cmp r3, r2
8000cc4: d101 bne.n 8000cca <HAL_GPIO_Init+0x1be>
8000cc6: 2303 movs r3, #3
8000cc8: e006 b.n 8000cd8 <HAL_GPIO_Init+0x1cc>
8000cca: 2305 movs r3, #5
8000ccc: e004 b.n 8000cd8 <HAL_GPIO_Init+0x1cc>
8000cce: 2302 movs r3, #2
8000cd0: e002 b.n 8000cd8 <HAL_GPIO_Init+0x1cc>
8000cd2: 2301 movs r3, #1
8000cd4: e000 b.n 8000cd8 <HAL_GPIO_Init+0x1cc>
8000cd6: 2300 movs r3, #0
8000cd8: 697a ldr r2, [r7, #20]
8000cda: 2103 movs r1, #3
8000cdc: 400a ands r2, r1
8000cde: 00d2 lsls r2, r2, #3
8000ce0: 4093 lsls r3, r2
8000ce2: 693a ldr r2, [r7, #16]
8000ce4: 4313 orrs r3, r2
8000ce6: 613b str r3, [r7, #16]
EXTI->EXTICR[position >> 2u] = temp;
8000ce8: 4936 ldr r1, [pc, #216] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000cea: 697b ldr r3, [r7, #20]
8000cec: 089b lsrs r3, r3, #2
8000cee: 3318 adds r3, #24
8000cf0: 009b lsls r3, r3, #2
8000cf2: 693a ldr r2, [r7, #16]
8000cf4: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8000cf6: 4b33 ldr r3, [pc, #204] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000cf8: 681b ldr r3, [r3, #0]
8000cfa: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000cfc: 68fb ldr r3, [r7, #12]
8000cfe: 43da mvns r2, r3
8000d00: 693b ldr r3, [r7, #16]
8000d02: 4013 ands r3, r2
8000d04: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8000d06: 683b ldr r3, [r7, #0]
8000d08: 685a ldr r2, [r3, #4]
8000d0a: 2380 movs r3, #128 @ 0x80
8000d0c: 035b lsls r3, r3, #13
8000d0e: 4013 ands r3, r2
8000d10: d003 beq.n 8000d1a <HAL_GPIO_Init+0x20e>
{
temp |= iocurrent;
8000d12: 693a ldr r2, [r7, #16]
8000d14: 68fb ldr r3, [r7, #12]
8000d16: 4313 orrs r3, r2
8000d18: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8000d1a: 4b2a ldr r3, [pc, #168] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000d1c: 693a ldr r2, [r7, #16]
8000d1e: 601a str r2, [r3, #0]
temp = EXTI->FTSR1;
8000d20: 4b28 ldr r3, [pc, #160] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000d22: 685b ldr r3, [r3, #4]
8000d24: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000d26: 68fb ldr r3, [r7, #12]
8000d28: 43da mvns r2, r3
8000d2a: 693b ldr r3, [r7, #16]
8000d2c: 4013 ands r3, r2
8000d2e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8000d30: 683b ldr r3, [r7, #0]
8000d32: 685a ldr r2, [r3, #4]
8000d34: 2380 movs r3, #128 @ 0x80
8000d36: 039b lsls r3, r3, #14
8000d38: 4013 ands r3, r2
8000d3a: d003 beq.n 8000d44 <HAL_GPIO_Init+0x238>
{
temp |= iocurrent;
8000d3c: 693a ldr r2, [r7, #16]
8000d3e: 68fb ldr r3, [r7, #12]
8000d40: 4313 orrs r3, r2
8000d42: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8000d44: 4b1f ldr r3, [pc, #124] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000d46: 693a ldr r2, [r7, #16]
8000d48: 605a str r2, [r3, #4]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8000d4a: 4a1e ldr r2, [pc, #120] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000d4c: 2384 movs r3, #132 @ 0x84
8000d4e: 58d3 ldr r3, [r2, r3]
8000d50: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000d52: 68fb ldr r3, [r7, #12]
8000d54: 43da mvns r2, r3
8000d56: 693b ldr r3, [r7, #16]
8000d58: 4013 ands r3, r2
8000d5a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8000d5c: 683b ldr r3, [r7, #0]
8000d5e: 685a ldr r2, [r3, #4]
8000d60: 2380 movs r3, #128 @ 0x80
8000d62: 029b lsls r3, r3, #10
8000d64: 4013 ands r3, r2
8000d66: d003 beq.n 8000d70 <HAL_GPIO_Init+0x264>
{
temp |= iocurrent;
8000d68: 693a ldr r2, [r7, #16]
8000d6a: 68fb ldr r3, [r7, #12]
8000d6c: 4313 orrs r3, r2
8000d6e: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8000d70: 4914 ldr r1, [pc, #80] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000d72: 2284 movs r2, #132 @ 0x84
8000d74: 693b ldr r3, [r7, #16]
8000d76: 508b str r3, [r1, r2]
temp = EXTI->IMR1;
8000d78: 4a12 ldr r2, [pc, #72] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000d7a: 2380 movs r3, #128 @ 0x80
8000d7c: 58d3 ldr r3, [r2, r3]
8000d7e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000d80: 68fb ldr r3, [r7, #12]
8000d82: 43da mvns r2, r3
8000d84: 693b ldr r3, [r7, #16]
8000d86: 4013 ands r3, r2
8000d88: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8000d8a: 683b ldr r3, [r7, #0]
8000d8c: 685a ldr r2, [r3, #4]
8000d8e: 2380 movs r3, #128 @ 0x80
8000d90: 025b lsls r3, r3, #9
8000d92: 4013 ands r3, r2
8000d94: d003 beq.n 8000d9e <HAL_GPIO_Init+0x292>
{
temp |= iocurrent;
8000d96: 693a ldr r2, [r7, #16]
8000d98: 68fb ldr r3, [r7, #12]
8000d9a: 4313 orrs r3, r2
8000d9c: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8000d9e: 4909 ldr r1, [pc, #36] @ (8000dc4 <HAL_GPIO_Init+0x2b8>)
8000da0: 2280 movs r2, #128 @ 0x80
8000da2: 693b ldr r3, [r7, #16]
8000da4: 508b str r3, [r1, r2]
}
}
position++;
8000da6: 697b ldr r3, [r7, #20]
8000da8: 3301 adds r3, #1
8000daa: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000dac: 683b ldr r3, [r7, #0]
8000dae: 681a ldr r2, [r3, #0]
8000db0: 697b ldr r3, [r7, #20]
8000db2: 40da lsrs r2, r3
8000db4: 1e13 subs r3, r2, #0
8000db6: d000 beq.n 8000dba <HAL_GPIO_Init+0x2ae>
8000db8: e6b0 b.n 8000b1c <HAL_GPIO_Init+0x10>
}
}
8000dba: 46c0 nop @ (mov r8, r8)
8000dbc: 46c0 nop @ (mov r8, r8)
8000dbe: 46bd mov sp, r7
8000dc0: b006 add sp, #24
8000dc2: bd80 pop {r7, pc}
8000dc4: 40021800 .word 0x40021800
8000dc8: 50000400 .word 0x50000400
8000dcc: 50000800 .word 0x50000800
8000dd0: 50000c00 .word 0x50000c00
08000dd4 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 6 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8000dd4: b580 push {r7, lr}
8000dd6: b084 sub sp, #16
8000dd8: af00 add r7, sp, #0
8000dda: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Modify voltage scaling range */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
8000ddc: 4b19 ldr r3, [pc, #100] @ (8000e44 <HAL_PWREx_ControlVoltageScaling+0x70>)
8000dde: 681b ldr r3, [r3, #0]
8000de0: 4a19 ldr r2, [pc, #100] @ (8000e48 <HAL_PWREx_ControlVoltageScaling+0x74>)
8000de2: 4013 ands r3, r2
8000de4: 0019 movs r1, r3
8000de6: 4b17 ldr r3, [pc, #92] @ (8000e44 <HAL_PWREx_ControlVoltageScaling+0x70>)
8000de8: 687a ldr r2, [r7, #4]
8000dea: 430a orrs r2, r1
8000dec: 601a str r2, [r3, #0]
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8000dee: 687a ldr r2, [r7, #4]
8000df0: 2380 movs r3, #128 @ 0x80
8000df2: 009b lsls r3, r3, #2
8000df4: 429a cmp r2, r3
8000df6: d11f bne.n 8000e38 <HAL_PWREx_ControlVoltageScaling+0x64>
{
/* Set timeout value */
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
8000df8: 4b14 ldr r3, [pc, #80] @ (8000e4c <HAL_PWREx_ControlVoltageScaling+0x78>)
8000dfa: 681a ldr r2, [r3, #0]
8000dfc: 0013 movs r3, r2
8000dfe: 005b lsls r3, r3, #1
8000e00: 189b adds r3, r3, r2
8000e02: 005b lsls r3, r3, #1
8000e04: 4912 ldr r1, [pc, #72] @ (8000e50 <HAL_PWREx_ControlVoltageScaling+0x7c>)
8000e06: 0018 movs r0, r3
8000e08: f7ff f97a bl 8000100 <__udivsi3>
8000e0c: 0003 movs r3, r0
8000e0e: 3301 adds r3, #1
8000e10: 60fb str r3, [r7, #12]
/* Wait until VOSF is reset */
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8000e12: e008 b.n 8000e26 <HAL_PWREx_ControlVoltageScaling+0x52>
{
if (wait_loop_index != 0U)
8000e14: 68fb ldr r3, [r7, #12]
8000e16: 2b00 cmp r3, #0
8000e18: d003 beq.n 8000e22 <HAL_PWREx_ControlVoltageScaling+0x4e>
{
wait_loop_index--;
8000e1a: 68fb ldr r3, [r7, #12]
8000e1c: 3b01 subs r3, #1
8000e1e: 60fb str r3, [r7, #12]
8000e20: e001 b.n 8000e26 <HAL_PWREx_ControlVoltageScaling+0x52>
}
else
{
return HAL_TIMEOUT;
8000e22: 2303 movs r3, #3
8000e24: e009 b.n 8000e3a <HAL_PWREx_ControlVoltageScaling+0x66>
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8000e26: 4b07 ldr r3, [pc, #28] @ (8000e44 <HAL_PWREx_ControlVoltageScaling+0x70>)
8000e28: 695a ldr r2, [r3, #20]
8000e2a: 2380 movs r3, #128 @ 0x80
8000e2c: 00db lsls r3, r3, #3
8000e2e: 401a ands r2, r3
8000e30: 2380 movs r3, #128 @ 0x80
8000e32: 00db lsls r3, r3, #3
8000e34: 429a cmp r2, r3
8000e36: d0ed beq.n 8000e14 <HAL_PWREx_ControlVoltageScaling+0x40>
}
}
}
return HAL_OK;
8000e38: 2300 movs r3, #0
}
8000e3a: 0018 movs r0, r3
8000e3c: 46bd mov sp, r7
8000e3e: b004 add sp, #16
8000e40: bd80 pop {r7, pc}
8000e42: 46c0 nop @ (mov r8, r8)
8000e44: 40007000 .word 0x40007000
8000e48: fffff9ff .word 0xfffff9ff
8000e4c: 20000000 .word 0x20000000
8000e50: 000f4240 .word 0x000f4240
08000e54 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to LSE Off
* first and then to LSE On or LSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000e54: b580 push {r7, lr}
8000e56: b088 sub sp, #32
8000e58: af00 add r7, sp, #0
8000e5a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000e5c: 687b ldr r3, [r7, #4]
8000e5e: 2b00 cmp r3, #0
8000e60: d101 bne.n 8000e66 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000e62: 2301 movs r3, #1
8000e64: e2f3 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000e66: 687b ldr r3, [r7, #4]
8000e68: 681b ldr r3, [r3, #0]
8000e6a: 2201 movs r2, #1
8000e6c: 4013 ands r3, r2
8000e6e: d100 bne.n 8000e72 <HAL_RCC_OscConfig+0x1e>
8000e70: e07c b.n 8000f6c <HAL_RCC_OscConfig+0x118>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8000e72: 4bc3 ldr r3, [pc, #780] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000e74: 689b ldr r3, [r3, #8]
8000e76: 2238 movs r2, #56 @ 0x38
8000e78: 4013 ands r3, r2
8000e7a: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8000e7c: 4bc0 ldr r3, [pc, #768] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000e7e: 68db ldr r3, [r3, #12]
8000e80: 2203 movs r2, #3
8000e82: 4013 ands r3, r2
8000e84: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
8000e86: 69bb ldr r3, [r7, #24]
8000e88: 2b10 cmp r3, #16
8000e8a: d102 bne.n 8000e92 <HAL_RCC_OscConfig+0x3e>
8000e8c: 697b ldr r3, [r7, #20]
8000e8e: 2b03 cmp r3, #3
8000e90: d002 beq.n 8000e98 <HAL_RCC_OscConfig+0x44>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
8000e92: 69bb ldr r3, [r7, #24]
8000e94: 2b08 cmp r3, #8
8000e96: d10b bne.n 8000eb0 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000e98: 4bb9 ldr r3, [pc, #740] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000e9a: 681a ldr r2, [r3, #0]
8000e9c: 2380 movs r3, #128 @ 0x80
8000e9e: 029b lsls r3, r3, #10
8000ea0: 4013 ands r3, r2
8000ea2: d062 beq.n 8000f6a <HAL_RCC_OscConfig+0x116>
8000ea4: 687b ldr r3, [r7, #4]
8000ea6: 685b ldr r3, [r3, #4]
8000ea8: 2b00 cmp r3, #0
8000eaa: d15e bne.n 8000f6a <HAL_RCC_OscConfig+0x116>
{
return HAL_ERROR;
8000eac: 2301 movs r3, #1
8000eae: e2ce b.n 800144e <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000eb0: 687b ldr r3, [r7, #4]
8000eb2: 685a ldr r2, [r3, #4]
8000eb4: 2380 movs r3, #128 @ 0x80
8000eb6: 025b lsls r3, r3, #9
8000eb8: 429a cmp r2, r3
8000eba: d107 bne.n 8000ecc <HAL_RCC_OscConfig+0x78>
8000ebc: 4bb0 ldr r3, [pc, #704] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000ebe: 681a ldr r2, [r3, #0]
8000ec0: 4baf ldr r3, [pc, #700] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000ec2: 2180 movs r1, #128 @ 0x80
8000ec4: 0249 lsls r1, r1, #9
8000ec6: 430a orrs r2, r1
8000ec8: 601a str r2, [r3, #0]
8000eca: e020 b.n 8000f0e <HAL_RCC_OscConfig+0xba>
8000ecc: 687b ldr r3, [r7, #4]
8000ece: 685a ldr r2, [r3, #4]
8000ed0: 23a0 movs r3, #160 @ 0xa0
8000ed2: 02db lsls r3, r3, #11
8000ed4: 429a cmp r2, r3
8000ed6: d10e bne.n 8000ef6 <HAL_RCC_OscConfig+0xa2>
8000ed8: 4ba9 ldr r3, [pc, #676] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000eda: 681a ldr r2, [r3, #0]
8000edc: 4ba8 ldr r3, [pc, #672] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000ede: 2180 movs r1, #128 @ 0x80
8000ee0: 02c9 lsls r1, r1, #11
8000ee2: 430a orrs r2, r1
8000ee4: 601a str r2, [r3, #0]
8000ee6: 4ba6 ldr r3, [pc, #664] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000ee8: 681a ldr r2, [r3, #0]
8000eea: 4ba5 ldr r3, [pc, #660] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000eec: 2180 movs r1, #128 @ 0x80
8000eee: 0249 lsls r1, r1, #9
8000ef0: 430a orrs r2, r1
8000ef2: 601a str r2, [r3, #0]
8000ef4: e00b b.n 8000f0e <HAL_RCC_OscConfig+0xba>
8000ef6: 4ba2 ldr r3, [pc, #648] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000ef8: 681a ldr r2, [r3, #0]
8000efa: 4ba1 ldr r3, [pc, #644] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000efc: 49a1 ldr r1, [pc, #644] @ (8001184 <HAL_RCC_OscConfig+0x330>)
8000efe: 400a ands r2, r1
8000f00: 601a str r2, [r3, #0]
8000f02: 4b9f ldr r3, [pc, #636] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000f04: 681a ldr r2, [r3, #0]
8000f06: 4b9e ldr r3, [pc, #632] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000f08: 499f ldr r1, [pc, #636] @ (8001188 <HAL_RCC_OscConfig+0x334>)
8000f0a: 400a ands r2, r1
8000f0c: 601a str r2, [r3, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000f0e: 687b ldr r3, [r7, #4]
8000f10: 685b ldr r3, [r3, #4]
8000f12: 2b00 cmp r3, #0
8000f14: d014 beq.n 8000f40 <HAL_RCC_OscConfig+0xec>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8000f16: f7ff fd3b bl 8000990 <HAL_GetTick>
8000f1a: 0003 movs r3, r0
8000f1c: 613b str r3, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8000f1e: e008 b.n 8000f32 <HAL_RCC_OscConfig+0xde>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000f20: f7ff fd36 bl 8000990 <HAL_GetTick>
8000f24: 0002 movs r2, r0
8000f26: 693b ldr r3, [r7, #16]
8000f28: 1ad3 subs r3, r2, r3
8000f2a: 2b64 cmp r3, #100 @ 0x64
8000f2c: d901 bls.n 8000f32 <HAL_RCC_OscConfig+0xde>
{
return HAL_TIMEOUT;
8000f2e: 2303 movs r3, #3
8000f30: e28d b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8000f32: 4b93 ldr r3, [pc, #588] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000f34: 681a ldr r2, [r3, #0]
8000f36: 2380 movs r3, #128 @ 0x80
8000f38: 029b lsls r3, r3, #10
8000f3a: 4013 ands r3, r2
8000f3c: d0f0 beq.n 8000f20 <HAL_RCC_OscConfig+0xcc>
8000f3e: e015 b.n 8000f6c <HAL_RCC_OscConfig+0x118>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8000f40: f7ff fd26 bl 8000990 <HAL_GetTick>
8000f44: 0003 movs r3, r0
8000f46: 613b str r3, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8000f48: e008 b.n 8000f5c <HAL_RCC_OscConfig+0x108>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000f4a: f7ff fd21 bl 8000990 <HAL_GetTick>
8000f4e: 0002 movs r2, r0
8000f50: 693b ldr r3, [r7, #16]
8000f52: 1ad3 subs r3, r2, r3
8000f54: 2b64 cmp r3, #100 @ 0x64
8000f56: d901 bls.n 8000f5c <HAL_RCC_OscConfig+0x108>
{
return HAL_TIMEOUT;
8000f58: 2303 movs r3, #3
8000f5a: e278 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8000f5c: 4b88 ldr r3, [pc, #544] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000f5e: 681a ldr r2, [r3, #0]
8000f60: 2380 movs r3, #128 @ 0x80
8000f62: 029b lsls r3, r3, #10
8000f64: 4013 ands r3, r2
8000f66: d1f0 bne.n 8000f4a <HAL_RCC_OscConfig+0xf6>
8000f68: e000 b.n 8000f6c <HAL_RCC_OscConfig+0x118>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000f6a: 46c0 nop @ (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000f6c: 687b ldr r3, [r7, #4]
8000f6e: 681b ldr r3, [r3, #0]
8000f70: 2202 movs r2, #2
8000f72: 4013 ands r3, r2
8000f74: d100 bne.n 8000f78 <HAL_RCC_OscConfig+0x124>
8000f76: e099 b.n 80010ac <HAL_RCC_OscConfig+0x258>
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8000f78: 4b81 ldr r3, [pc, #516] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000f7a: 689b ldr r3, [r3, #8]
8000f7c: 2238 movs r2, #56 @ 0x38
8000f7e: 4013 ands r3, r2
8000f80: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8000f82: 4b7f ldr r3, [pc, #508] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000f84: 68db ldr r3, [r3, #12]
8000f86: 2203 movs r2, #3
8000f88: 4013 ands r3, r2
8000f8a: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
8000f8c: 69bb ldr r3, [r7, #24]
8000f8e: 2b10 cmp r3, #16
8000f90: d102 bne.n 8000f98 <HAL_RCC_OscConfig+0x144>
8000f92: 697b ldr r3, [r7, #20]
8000f94: 2b02 cmp r3, #2
8000f96: d002 beq.n 8000f9e <HAL_RCC_OscConfig+0x14a>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
8000f98: 69bb ldr r3, [r7, #24]
8000f9a: 2b00 cmp r3, #0
8000f9c: d135 bne.n 800100a <HAL_RCC_OscConfig+0x1b6>
{
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8000f9e: 4b78 ldr r3, [pc, #480] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000fa0: 681a ldr r2, [r3, #0]
8000fa2: 2380 movs r3, #128 @ 0x80
8000fa4: 00db lsls r3, r3, #3
8000fa6: 4013 ands r3, r2
8000fa8: d005 beq.n 8000fb6 <HAL_RCC_OscConfig+0x162>
8000faa: 687b ldr r3, [r7, #4]
8000fac: 68db ldr r3, [r3, #12]
8000fae: 2b00 cmp r3, #0
8000fb0: d101 bne.n 8000fb6 <HAL_RCC_OscConfig+0x162>
{
return HAL_ERROR;
8000fb2: 2301 movs r3, #1
8000fb4: e24b b.n 800144e <HAL_RCC_OscConfig+0x5fa>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000fb6: 4b72 ldr r3, [pc, #456] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000fb8: 685b ldr r3, [r3, #4]
8000fba: 4a74 ldr r2, [pc, #464] @ (800118c <HAL_RCC_OscConfig+0x338>)
8000fbc: 4013 ands r3, r2
8000fbe: 0019 movs r1, r3
8000fc0: 687b ldr r3, [r7, #4]
8000fc2: 695b ldr r3, [r3, #20]
8000fc4: 021a lsls r2, r3, #8
8000fc6: 4b6e ldr r3, [pc, #440] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000fc8: 430a orrs r2, r1
8000fca: 605a str r2, [r3, #4]
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
8000fcc: 69bb ldr r3, [r7, #24]
8000fce: 2b00 cmp r3, #0
8000fd0: d112 bne.n 8000ff8 <HAL_RCC_OscConfig+0x1a4>
{
/* Adjust the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8000fd2: 4b6b ldr r3, [pc, #428] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000fd4: 681b ldr r3, [r3, #0]
8000fd6: 4a6e ldr r2, [pc, #440] @ (8001190 <HAL_RCC_OscConfig+0x33c>)
8000fd8: 4013 ands r3, r2
8000fda: 0019 movs r1, r3
8000fdc: 687b ldr r3, [r7, #4]
8000fde: 691a ldr r2, [r3, #16]
8000fe0: 4b67 ldr r3, [pc, #412] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000fe2: 430a orrs r2, r1
8000fe4: 601a str r2, [r3, #0]
/* Update the SystemCoreClock global variable with HSISYS value */
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
8000fe6: 4b66 ldr r3, [pc, #408] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8000fe8: 681b ldr r3, [r3, #0]
8000fea: 0adb lsrs r3, r3, #11
8000fec: 2207 movs r2, #7
8000fee: 4013 ands r3, r2
8000ff0: 4a68 ldr r2, [pc, #416] @ (8001194 <HAL_RCC_OscConfig+0x340>)
8000ff2: 40da lsrs r2, r3
8000ff4: 4b68 ldr r3, [pc, #416] @ (8001198 <HAL_RCC_OscConfig+0x344>)
8000ff6: 601a str r2, [r3, #0]
}
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8000ff8: 4b68 ldr r3, [pc, #416] @ (800119c <HAL_RCC_OscConfig+0x348>)
8000ffa: 681b ldr r3, [r3, #0]
8000ffc: 0018 movs r0, r3
8000ffe: f7ff fc6b bl 80008d8 <HAL_InitTick>
8001002: 1e03 subs r3, r0, #0
8001004: d051 beq.n 80010aa <HAL_RCC_OscConfig+0x256>
{
return HAL_ERROR;
8001006: 2301 movs r3, #1
8001008: e221 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800100a: 687b ldr r3, [r7, #4]
800100c: 68db ldr r3, [r3, #12]
800100e: 2b00 cmp r3, #0
8001010: d030 beq.n 8001074 <HAL_RCC_OscConfig+0x220>
{
/* Configure the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8001012: 4b5b ldr r3, [pc, #364] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001014: 681b ldr r3, [r3, #0]
8001016: 4a5e ldr r2, [pc, #376] @ (8001190 <HAL_RCC_OscConfig+0x33c>)
8001018: 4013 ands r3, r2
800101a: 0019 movs r1, r3
800101c: 687b ldr r3, [r7, #4]
800101e: 691a ldr r2, [r3, #16]
8001020: 4b57 ldr r3, [pc, #348] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001022: 430a orrs r2, r1
8001024: 601a str r2, [r3, #0]
/* Enable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_ENABLE();
8001026: 4b56 ldr r3, [pc, #344] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001028: 681a ldr r2, [r3, #0]
800102a: 4b55 ldr r3, [pc, #340] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800102c: 2180 movs r1, #128 @ 0x80
800102e: 0049 lsls r1, r1, #1
8001030: 430a orrs r2, r1
8001032: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001034: f7ff fcac bl 8000990 <HAL_GetTick>
8001038: 0003 movs r3, r0
800103a: 613b str r3, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800103c: e008 b.n 8001050 <HAL_RCC_OscConfig+0x1fc>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800103e: f7ff fca7 bl 8000990 <HAL_GetTick>
8001042: 0002 movs r2, r0
8001044: 693b ldr r3, [r7, #16]
8001046: 1ad3 subs r3, r2, r3
8001048: 2b02 cmp r3, #2
800104a: d901 bls.n 8001050 <HAL_RCC_OscConfig+0x1fc>
{
return HAL_TIMEOUT;
800104c: 2303 movs r3, #3
800104e: e1fe b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001050: 4b4b ldr r3, [pc, #300] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001052: 681a ldr r2, [r3, #0]
8001054: 2380 movs r3, #128 @ 0x80
8001056: 00db lsls r3, r3, #3
8001058: 4013 ands r3, r2
800105a: d0f0 beq.n 800103e <HAL_RCC_OscConfig+0x1ea>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800105c: 4b48 ldr r3, [pc, #288] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800105e: 685b ldr r3, [r3, #4]
8001060: 4a4a ldr r2, [pc, #296] @ (800118c <HAL_RCC_OscConfig+0x338>)
8001062: 4013 ands r3, r2
8001064: 0019 movs r1, r3
8001066: 687b ldr r3, [r7, #4]
8001068: 695b ldr r3, [r3, #20]
800106a: 021a lsls r2, r3, #8
800106c: 4b44 ldr r3, [pc, #272] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800106e: 430a orrs r2, r1
8001070: 605a str r2, [r3, #4]
8001072: e01b b.n 80010ac <HAL_RCC_OscConfig+0x258>
}
else
{
/* Disable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_DISABLE();
8001074: 4b42 ldr r3, [pc, #264] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001076: 681a ldr r2, [r3, #0]
8001078: 4b41 ldr r3, [pc, #260] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800107a: 4949 ldr r1, [pc, #292] @ (80011a0 <HAL_RCC_OscConfig+0x34c>)
800107c: 400a ands r2, r1
800107e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001080: f7ff fc86 bl 8000990 <HAL_GetTick>
8001084: 0003 movs r3, r0
8001086: 613b str r3, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8001088: e008 b.n 800109c <HAL_RCC_OscConfig+0x248>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800108a: f7ff fc81 bl 8000990 <HAL_GetTick>
800108e: 0002 movs r2, r0
8001090: 693b ldr r3, [r7, #16]
8001092: 1ad3 subs r3, r2, r3
8001094: 2b02 cmp r3, #2
8001096: d901 bls.n 800109c <HAL_RCC_OscConfig+0x248>
{
return HAL_TIMEOUT;
8001098: 2303 movs r3, #3
800109a: e1d8 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
800109c: 4b38 ldr r3, [pc, #224] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800109e: 681a ldr r2, [r3, #0]
80010a0: 2380 movs r3, #128 @ 0x80
80010a2: 00db lsls r3, r3, #3
80010a4: 4013 ands r3, r2
80010a6: d1f0 bne.n 800108a <HAL_RCC_OscConfig+0x236>
80010a8: e000 b.n 80010ac <HAL_RCC_OscConfig+0x258>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80010aa: 46c0 nop @ (mov r8, r8)
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80010ac: 687b ldr r3, [r7, #4]
80010ae: 681b ldr r3, [r3, #0]
80010b0: 2208 movs r2, #8
80010b2: 4013 ands r3, r2
80010b4: d047 beq.n 8001146 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check if LSI is used as system clock */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
80010b6: 4b32 ldr r3, [pc, #200] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
80010b8: 689b ldr r3, [r3, #8]
80010ba: 2238 movs r2, #56 @ 0x38
80010bc: 4013 ands r3, r2
80010be: 2b18 cmp r3, #24
80010c0: d10a bne.n 80010d8 <HAL_RCC_OscConfig+0x284>
{
/* When LSI is used as system clock it will not be disabled */
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
80010c2: 4b2f ldr r3, [pc, #188] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
80010c4: 6e1b ldr r3, [r3, #96] @ 0x60
80010c6: 2202 movs r2, #2
80010c8: 4013 ands r3, r2
80010ca: d03c beq.n 8001146 <HAL_RCC_OscConfig+0x2f2>
80010cc: 687b ldr r3, [r7, #4]
80010ce: 699b ldr r3, [r3, #24]
80010d0: 2b00 cmp r3, #0
80010d2: d138 bne.n 8001146 <HAL_RCC_OscConfig+0x2f2>
{
return HAL_ERROR;
80010d4: 2301 movs r3, #1
80010d6: e1ba b.n 800144e <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80010d8: 687b ldr r3, [r7, #4]
80010da: 699b ldr r3, [r3, #24]
80010dc: 2b00 cmp r3, #0
80010de: d019 beq.n 8001114 <HAL_RCC_OscConfig+0x2c0>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80010e0: 4b27 ldr r3, [pc, #156] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
80010e2: 6e1a ldr r2, [r3, #96] @ 0x60
80010e4: 4b26 ldr r3, [pc, #152] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
80010e6: 2101 movs r1, #1
80010e8: 430a orrs r2, r1
80010ea: 661a str r2, [r3, #96] @ 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
80010ec: f7ff fc50 bl 8000990 <HAL_GetTick>
80010f0: 0003 movs r3, r0
80010f2: 613b str r3, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80010f4: e008 b.n 8001108 <HAL_RCC_OscConfig+0x2b4>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80010f6: f7ff fc4b bl 8000990 <HAL_GetTick>
80010fa: 0002 movs r2, r0
80010fc: 693b ldr r3, [r7, #16]
80010fe: 1ad3 subs r3, r2, r3
8001100: 2b02 cmp r3, #2
8001102: d901 bls.n 8001108 <HAL_RCC_OscConfig+0x2b4>
{
return HAL_TIMEOUT;
8001104: 2303 movs r3, #3
8001106: e1a2 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001108: 4b1d ldr r3, [pc, #116] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800110a: 6e1b ldr r3, [r3, #96] @ 0x60
800110c: 2202 movs r2, #2
800110e: 4013 ands r3, r2
8001110: d0f1 beq.n 80010f6 <HAL_RCC_OscConfig+0x2a2>
8001112: e018 b.n 8001146 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001114: 4b1a ldr r3, [pc, #104] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001116: 6e1a ldr r2, [r3, #96] @ 0x60
8001118: 4b19 ldr r3, [pc, #100] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800111a: 2101 movs r1, #1
800111c: 438a bics r2, r1
800111e: 661a str r2, [r3, #96] @ 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001120: f7ff fc36 bl 8000990 <HAL_GetTick>
8001124: 0003 movs r3, r0
8001126: 613b str r3, [r7, #16]
/* Wait till LSI is disabled */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8001128: e008 b.n 800113c <HAL_RCC_OscConfig+0x2e8>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800112a: f7ff fc31 bl 8000990 <HAL_GetTick>
800112e: 0002 movs r2, r0
8001130: 693b ldr r3, [r7, #16]
8001132: 1ad3 subs r3, r2, r3
8001134: 2b02 cmp r3, #2
8001136: d901 bls.n 800113c <HAL_RCC_OscConfig+0x2e8>
{
return HAL_TIMEOUT;
8001138: 2303 movs r3, #3
800113a: e188 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
800113c: 4b10 ldr r3, [pc, #64] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800113e: 6e1b ldr r3, [r3, #96] @ 0x60
8001140: 2202 movs r2, #2
8001142: 4013 ands r3, r2
8001144: d1f1 bne.n 800112a <HAL_RCC_OscConfig+0x2d6>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001146: 687b ldr r3, [r7, #4]
8001148: 681b ldr r3, [r3, #0]
800114a: 2204 movs r2, #4
800114c: 4013 ands r3, r2
800114e: d100 bne.n 8001152 <HAL_RCC_OscConfig+0x2fe>
8001150: e0c6 b.n 80012e0 <HAL_RCC_OscConfig+0x48c>
{
FlagStatus pwrclkchanged = RESET;
8001152: 231f movs r3, #31
8001154: 18fb adds r3, r7, r3
8001156: 2200 movs r2, #0
8001158: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* When the LSE is used as system clock, it is not allowed disable it */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
800115a: 4b09 ldr r3, [pc, #36] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
800115c: 689b ldr r3, [r3, #8]
800115e: 2238 movs r2, #56 @ 0x38
8001160: 4013 ands r3, r2
8001162: 2b20 cmp r3, #32
8001164: d11e bne.n 80011a4 <HAL_RCC_OscConfig+0x350>
{
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
8001166: 4b06 ldr r3, [pc, #24] @ (8001180 <HAL_RCC_OscConfig+0x32c>)
8001168: 6ddb ldr r3, [r3, #92] @ 0x5c
800116a: 2202 movs r2, #2
800116c: 4013 ands r3, r2
800116e: d100 bne.n 8001172 <HAL_RCC_OscConfig+0x31e>
8001170: e0b6 b.n 80012e0 <HAL_RCC_OscConfig+0x48c>
8001172: 687b ldr r3, [r7, #4]
8001174: 689b ldr r3, [r3, #8]
8001176: 2b00 cmp r3, #0
8001178: d000 beq.n 800117c <HAL_RCC_OscConfig+0x328>
800117a: e0b1 b.n 80012e0 <HAL_RCC_OscConfig+0x48c>
{
return HAL_ERROR;
800117c: 2301 movs r3, #1
800117e: e166 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
8001180: 40021000 .word 0x40021000
8001184: fffeffff .word 0xfffeffff
8001188: fffbffff .word 0xfffbffff
800118c: ffff80ff .word 0xffff80ff
8001190: ffffc7ff .word 0xffffc7ff
8001194: 00f42400 .word 0x00f42400
8001198: 20000000 .word 0x20000000
800119c: 20000004 .word 0x20000004
80011a0: fffffeff .word 0xfffffeff
}
else
{
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
80011a4: 4bac ldr r3, [pc, #688] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80011a6: 6bda ldr r2, [r3, #60] @ 0x3c
80011a8: 2380 movs r3, #128 @ 0x80
80011aa: 055b lsls r3, r3, #21
80011ac: 4013 ands r3, r2
80011ae: d101 bne.n 80011b4 <HAL_RCC_OscConfig+0x360>
80011b0: 2301 movs r3, #1
80011b2: e000 b.n 80011b6 <HAL_RCC_OscConfig+0x362>
80011b4: 2300 movs r3, #0
80011b6: 2b00 cmp r3, #0
80011b8: d011 beq.n 80011de <HAL_RCC_OscConfig+0x38a>
{
__HAL_RCC_PWR_CLK_ENABLE();
80011ba: 4ba7 ldr r3, [pc, #668] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80011bc: 6bda ldr r2, [r3, #60] @ 0x3c
80011be: 4ba6 ldr r3, [pc, #664] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80011c0: 2180 movs r1, #128 @ 0x80
80011c2: 0549 lsls r1, r1, #21
80011c4: 430a orrs r2, r1
80011c6: 63da str r2, [r3, #60] @ 0x3c
80011c8: 4ba3 ldr r3, [pc, #652] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80011ca: 6bda ldr r2, [r3, #60] @ 0x3c
80011cc: 2380 movs r3, #128 @ 0x80
80011ce: 055b lsls r3, r3, #21
80011d0: 4013 ands r3, r2
80011d2: 60fb str r3, [r7, #12]
80011d4: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
80011d6: 231f movs r3, #31
80011d8: 18fb adds r3, r7, r3
80011da: 2201 movs r2, #1
80011dc: 701a strb r2, [r3, #0]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80011de: 4b9f ldr r3, [pc, #636] @ (800145c <HAL_RCC_OscConfig+0x608>)
80011e0: 681a ldr r2, [r3, #0]
80011e2: 2380 movs r3, #128 @ 0x80
80011e4: 005b lsls r3, r3, #1
80011e6: 4013 ands r3, r2
80011e8: d11a bne.n 8001220 <HAL_RCC_OscConfig+0x3cc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80011ea: 4b9c ldr r3, [pc, #624] @ (800145c <HAL_RCC_OscConfig+0x608>)
80011ec: 681a ldr r2, [r3, #0]
80011ee: 4b9b ldr r3, [pc, #620] @ (800145c <HAL_RCC_OscConfig+0x608>)
80011f0: 2180 movs r1, #128 @ 0x80
80011f2: 0049 lsls r1, r1, #1
80011f4: 430a orrs r2, r1
80011f6: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80011f8: f7ff fbca bl 8000990 <HAL_GetTick>
80011fc: 0003 movs r3, r0
80011fe: 613b str r3, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001200: e008 b.n 8001214 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001202: f7ff fbc5 bl 8000990 <HAL_GetTick>
8001206: 0002 movs r2, r0
8001208: 693b ldr r3, [r7, #16]
800120a: 1ad3 subs r3, r2, r3
800120c: 2b02 cmp r3, #2
800120e: d901 bls.n 8001214 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8001210: 2303 movs r3, #3
8001212: e11c b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001214: 4b91 ldr r3, [pc, #580] @ (800145c <HAL_RCC_OscConfig+0x608>)
8001216: 681a ldr r2, [r3, #0]
8001218: 2380 movs r3, #128 @ 0x80
800121a: 005b lsls r3, r3, #1
800121c: 4013 ands r3, r2
800121e: d0f0 beq.n 8001202 <HAL_RCC_OscConfig+0x3ae>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001220: 687b ldr r3, [r7, #4]
8001222: 689b ldr r3, [r3, #8]
8001224: 2b01 cmp r3, #1
8001226: d106 bne.n 8001236 <HAL_RCC_OscConfig+0x3e2>
8001228: 4b8b ldr r3, [pc, #556] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800122a: 6dda ldr r2, [r3, #92] @ 0x5c
800122c: 4b8a ldr r3, [pc, #552] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800122e: 2101 movs r1, #1
8001230: 430a orrs r2, r1
8001232: 65da str r2, [r3, #92] @ 0x5c
8001234: e01c b.n 8001270 <HAL_RCC_OscConfig+0x41c>
8001236: 687b ldr r3, [r7, #4]
8001238: 689b ldr r3, [r3, #8]
800123a: 2b05 cmp r3, #5
800123c: d10c bne.n 8001258 <HAL_RCC_OscConfig+0x404>
800123e: 4b86 ldr r3, [pc, #536] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001240: 6dda ldr r2, [r3, #92] @ 0x5c
8001242: 4b85 ldr r3, [pc, #532] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001244: 2104 movs r1, #4
8001246: 430a orrs r2, r1
8001248: 65da str r2, [r3, #92] @ 0x5c
800124a: 4b83 ldr r3, [pc, #524] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800124c: 6dda ldr r2, [r3, #92] @ 0x5c
800124e: 4b82 ldr r3, [pc, #520] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001250: 2101 movs r1, #1
8001252: 430a orrs r2, r1
8001254: 65da str r2, [r3, #92] @ 0x5c
8001256: e00b b.n 8001270 <HAL_RCC_OscConfig+0x41c>
8001258: 4b7f ldr r3, [pc, #508] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800125a: 6dda ldr r2, [r3, #92] @ 0x5c
800125c: 4b7e ldr r3, [pc, #504] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800125e: 2101 movs r1, #1
8001260: 438a bics r2, r1
8001262: 65da str r2, [r3, #92] @ 0x5c
8001264: 4b7c ldr r3, [pc, #496] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001266: 6dda ldr r2, [r3, #92] @ 0x5c
8001268: 4b7b ldr r3, [pc, #492] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800126a: 2104 movs r1, #4
800126c: 438a bics r2, r1
800126e: 65da str r2, [r3, #92] @ 0x5c
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001270: 687b ldr r3, [r7, #4]
8001272: 689b ldr r3, [r3, #8]
8001274: 2b00 cmp r3, #0
8001276: d014 beq.n 80012a2 <HAL_RCC_OscConfig+0x44e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001278: f7ff fb8a bl 8000990 <HAL_GetTick>
800127c: 0003 movs r3, r0
800127e: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001280: e009 b.n 8001296 <HAL_RCC_OscConfig+0x442>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001282: f7ff fb85 bl 8000990 <HAL_GetTick>
8001286: 0002 movs r2, r0
8001288: 693b ldr r3, [r7, #16]
800128a: 1ad3 subs r3, r2, r3
800128c: 4a74 ldr r2, [pc, #464] @ (8001460 <HAL_RCC_OscConfig+0x60c>)
800128e: 4293 cmp r3, r2
8001290: d901 bls.n 8001296 <HAL_RCC_OscConfig+0x442>
{
return HAL_TIMEOUT;
8001292: 2303 movs r3, #3
8001294: e0db b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001296: 4b70 ldr r3, [pc, #448] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001298: 6ddb ldr r3, [r3, #92] @ 0x5c
800129a: 2202 movs r2, #2
800129c: 4013 ands r3, r2
800129e: d0f0 beq.n 8001282 <HAL_RCC_OscConfig+0x42e>
80012a0: e013 b.n 80012ca <HAL_RCC_OscConfig+0x476>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80012a2: f7ff fb75 bl 8000990 <HAL_GetTick>
80012a6: 0003 movs r3, r0
80012a8: 613b str r3, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80012aa: e009 b.n 80012c0 <HAL_RCC_OscConfig+0x46c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80012ac: f7ff fb70 bl 8000990 <HAL_GetTick>
80012b0: 0002 movs r2, r0
80012b2: 693b ldr r3, [r7, #16]
80012b4: 1ad3 subs r3, r2, r3
80012b6: 4a6a ldr r2, [pc, #424] @ (8001460 <HAL_RCC_OscConfig+0x60c>)
80012b8: 4293 cmp r3, r2
80012ba: d901 bls.n 80012c0 <HAL_RCC_OscConfig+0x46c>
{
return HAL_TIMEOUT;
80012bc: 2303 movs r3, #3
80012be: e0c6 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80012c0: 4b65 ldr r3, [pc, #404] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80012c2: 6ddb ldr r3, [r3, #92] @ 0x5c
80012c4: 2202 movs r2, #2
80012c6: 4013 ands r3, r2
80012c8: d1f0 bne.n 80012ac <HAL_RCC_OscConfig+0x458>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80012ca: 231f movs r3, #31
80012cc: 18fb adds r3, r7, r3
80012ce: 781b ldrb r3, [r3, #0]
80012d0: 2b01 cmp r3, #1
80012d2: d105 bne.n 80012e0 <HAL_RCC_OscConfig+0x48c>
{
__HAL_RCC_PWR_CLK_DISABLE();
80012d4: 4b60 ldr r3, [pc, #384] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80012d6: 6bda ldr r2, [r3, #60] @ 0x3c
80012d8: 4b5f ldr r3, [pc, #380] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80012da: 4962 ldr r1, [pc, #392] @ (8001464 <HAL_RCC_OscConfig+0x610>)
80012dc: 400a ands r2, r1
80012de: 63da str r2, [r3, #60] @ 0x3c
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
80012e0: 687b ldr r3, [r7, #4]
80012e2: 69db ldr r3, [r3, #28]
80012e4: 2b00 cmp r3, #0
80012e6: d100 bne.n 80012ea <HAL_RCC_OscConfig+0x496>
80012e8: e0b0 b.n 800144c <HAL_RCC_OscConfig+0x5f8>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80012ea: 4b5b ldr r3, [pc, #364] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80012ec: 689b ldr r3, [r3, #8]
80012ee: 2238 movs r2, #56 @ 0x38
80012f0: 4013 ands r3, r2
80012f2: 2b10 cmp r3, #16
80012f4: d100 bne.n 80012f8 <HAL_RCC_OscConfig+0x4a4>
80012f6: e078 b.n 80013ea <HAL_RCC_OscConfig+0x596>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
80012f8: 687b ldr r3, [r7, #4]
80012fa: 69db ldr r3, [r3, #28]
80012fc: 2b02 cmp r3, #2
80012fe: d153 bne.n 80013a8 <HAL_RCC_OscConfig+0x554>
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
#endif /* RCC_PLLQ_SUPPORT */
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001300: 4b55 ldr r3, [pc, #340] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001302: 681a ldr r2, [r3, #0]
8001304: 4b54 ldr r3, [pc, #336] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001306: 4958 ldr r1, [pc, #352] @ (8001468 <HAL_RCC_OscConfig+0x614>)
8001308: 400a ands r2, r1
800130a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800130c: f7ff fb40 bl 8000990 <HAL_GetTick>
8001310: 0003 movs r3, r0
8001312: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001314: e008 b.n 8001328 <HAL_RCC_OscConfig+0x4d4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001316: f7ff fb3b bl 8000990 <HAL_GetTick>
800131a: 0002 movs r2, r0
800131c: 693b ldr r3, [r7, #16]
800131e: 1ad3 subs r3, r2, r3
8001320: 2b02 cmp r3, #2
8001322: d901 bls.n 8001328 <HAL_RCC_OscConfig+0x4d4>
{
return HAL_TIMEOUT;
8001324: 2303 movs r3, #3
8001326: e092 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8001328: 4b4b ldr r3, [pc, #300] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800132a: 681a ldr r2, [r3, #0]
800132c: 2380 movs r3, #128 @ 0x80
800132e: 049b lsls r3, r3, #18
8001330: 4013 ands r3, r2
8001332: d1f0 bne.n 8001316 <HAL_RCC_OscConfig+0x4c2>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else /* !RCC_PLLQ_SUPPORT */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001334: 4b48 ldr r3, [pc, #288] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001336: 68db ldr r3, [r3, #12]
8001338: 4a4c ldr r2, [pc, #304] @ (800146c <HAL_RCC_OscConfig+0x618>)
800133a: 4013 ands r3, r2
800133c: 0019 movs r1, r3
800133e: 687b ldr r3, [r7, #4]
8001340: 6a1a ldr r2, [r3, #32]
8001342: 687b ldr r3, [r7, #4]
8001344: 6a5b ldr r3, [r3, #36] @ 0x24
8001346: 431a orrs r2, r3
8001348: 687b ldr r3, [r7, #4]
800134a: 6a9b ldr r3, [r3, #40] @ 0x28
800134c: 021b lsls r3, r3, #8
800134e: 431a orrs r2, r3
8001350: 687b ldr r3, [r7, #4]
8001352: 6adb ldr r3, [r3, #44] @ 0x2c
8001354: 431a orrs r2, r3
8001356: 687b ldr r3, [r7, #4]
8001358: 6b1b ldr r3, [r3, #48] @ 0x30
800135a: 431a orrs r2, r3
800135c: 4b3e ldr r3, [pc, #248] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800135e: 430a orrs r2, r1
8001360: 60da str r2, [r3, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLR);
#endif /* RCC_PLLQ_SUPPORT */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001362: 4b3d ldr r3, [pc, #244] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001364: 681a ldr r2, [r3, #0]
8001366: 4b3c ldr r3, [pc, #240] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001368: 2180 movs r1, #128 @ 0x80
800136a: 0449 lsls r1, r1, #17
800136c: 430a orrs r2, r1
800136e: 601a str r2, [r3, #0]
/* Enable PLLR Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
8001370: 4b39 ldr r3, [pc, #228] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001372: 68da ldr r2, [r3, #12]
8001374: 4b38 ldr r3, [pc, #224] @ (8001458 <HAL_RCC_OscConfig+0x604>)
8001376: 2180 movs r1, #128 @ 0x80
8001378: 0549 lsls r1, r1, #21
800137a: 430a orrs r2, r1
800137c: 60da str r2, [r3, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800137e: f7ff fb07 bl 8000990 <HAL_GetTick>
8001382: 0003 movs r3, r0
8001384: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8001386: e008 b.n 800139a <HAL_RCC_OscConfig+0x546>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001388: f7ff fb02 bl 8000990 <HAL_GetTick>
800138c: 0002 movs r2, r0
800138e: 693b ldr r3, [r7, #16]
8001390: 1ad3 subs r3, r2, r3
8001392: 2b02 cmp r3, #2
8001394: d901 bls.n 800139a <HAL_RCC_OscConfig+0x546>
{
return HAL_TIMEOUT;
8001396: 2303 movs r3, #3
8001398: e059 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800139a: 4b2f ldr r3, [pc, #188] @ (8001458 <HAL_RCC_OscConfig+0x604>)
800139c: 681a ldr r2, [r3, #0]
800139e: 2380 movs r3, #128 @ 0x80
80013a0: 049b lsls r3, r3, #18
80013a2: 4013 ands r3, r2
80013a4: d0f0 beq.n 8001388 <HAL_RCC_OscConfig+0x534>
80013a6: e051 b.n 800144c <HAL_RCC_OscConfig+0x5f8>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80013a8: 4b2b ldr r3, [pc, #172] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80013aa: 681a ldr r2, [r3, #0]
80013ac: 4b2a ldr r3, [pc, #168] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80013ae: 492e ldr r1, [pc, #184] @ (8001468 <HAL_RCC_OscConfig+0x614>)
80013b0: 400a ands r2, r1
80013b2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80013b4: f7ff faec bl 8000990 <HAL_GetTick>
80013b8: 0003 movs r3, r0
80013ba: 613b str r3, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80013bc: e008 b.n 80013d0 <HAL_RCC_OscConfig+0x57c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80013be: f7ff fae7 bl 8000990 <HAL_GetTick>
80013c2: 0002 movs r2, r0
80013c4: 693b ldr r3, [r7, #16]
80013c6: 1ad3 subs r3, r2, r3
80013c8: 2b02 cmp r3, #2
80013ca: d901 bls.n 80013d0 <HAL_RCC_OscConfig+0x57c>
{
return HAL_TIMEOUT;
80013cc: 2303 movs r3, #3
80013ce: e03e b.n 800144e <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80013d0: 4b21 ldr r3, [pc, #132] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80013d2: 681a ldr r2, [r3, #0]
80013d4: 2380 movs r3, #128 @ 0x80
80013d6: 049b lsls r3, r3, #18
80013d8: 4013 ands r3, r2
80013da: d1f0 bne.n 80013be <HAL_RCC_OscConfig+0x56a>
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLQ_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
#else
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN);
80013dc: 4b1e ldr r3, [pc, #120] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80013de: 68da ldr r2, [r3, #12]
80013e0: 4b1d ldr r3, [pc, #116] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80013e2: 4923 ldr r1, [pc, #140] @ (8001470 <HAL_RCC_OscConfig+0x61c>)
80013e4: 400a ands r2, r1
80013e6: 60da str r2, [r3, #12]
80013e8: e030 b.n 800144c <HAL_RCC_OscConfig+0x5f8>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80013ea: 687b ldr r3, [r7, #4]
80013ec: 69db ldr r3, [r3, #28]
80013ee: 2b01 cmp r3, #1
80013f0: d101 bne.n 80013f6 <HAL_RCC_OscConfig+0x5a2>
{
return HAL_ERROR;
80013f2: 2301 movs r3, #1
80013f4: e02b b.n 800144e <HAL_RCC_OscConfig+0x5fa>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
80013f6: 4b18 ldr r3, [pc, #96] @ (8001458 <HAL_RCC_OscConfig+0x604>)
80013f8: 68db ldr r3, [r3, #12]
80013fa: 617b str r3, [r7, #20]
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80013fc: 697b ldr r3, [r7, #20]
80013fe: 2203 movs r2, #3
8001400: 401a ands r2, r3
8001402: 687b ldr r3, [r7, #4]
8001404: 6a1b ldr r3, [r3, #32]
8001406: 429a cmp r2, r3
8001408: d11e bne.n 8001448 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
800140a: 697b ldr r3, [r7, #20]
800140c: 2270 movs r2, #112 @ 0x70
800140e: 401a ands r2, r3
8001410: 687b ldr r3, [r7, #4]
8001412: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001414: 429a cmp r2, r3
8001416: d117 bne.n 8001448 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001418: 697a ldr r2, [r7, #20]
800141a: 23fe movs r3, #254 @ 0xfe
800141c: 01db lsls r3, r3, #7
800141e: 401a ands r2, r3
8001420: 687b ldr r3, [r7, #4]
8001422: 6a9b ldr r3, [r3, #40] @ 0x28
8001424: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8001426: 429a cmp r2, r3
8001428: d10e bne.n 8001448 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
800142a: 697a ldr r2, [r7, #20]
800142c: 23f8 movs r3, #248 @ 0xf8
800142e: 039b lsls r3, r3, #14
8001430: 401a ands r2, r3
8001432: 687b ldr r3, [r7, #4]
8001434: 6adb ldr r3, [r3, #44] @ 0x2c
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8001436: 429a cmp r2, r3
8001438: d106 bne.n 8001448 <HAL_RCC_OscConfig+0x5f4>
#if defined (RCC_PLLQ_SUPPORT)
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
#endif /* RCC_PLLQ_SUPPORT */
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
800143a: 697b ldr r3, [r7, #20]
800143c: 0f5b lsrs r3, r3, #29
800143e: 075a lsls r2, r3, #29
8001440: 687b ldr r3, [r7, #4]
8001442: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8001444: 429a cmp r2, r3
8001446: d001 beq.n 800144c <HAL_RCC_OscConfig+0x5f8>
{
return HAL_ERROR;
8001448: 2301 movs r3, #1
800144a: e000 b.n 800144e <HAL_RCC_OscConfig+0x5fa>
}
}
}
}
return HAL_OK;
800144c: 2300 movs r3, #0
}
800144e: 0018 movs r0, r3
8001450: 46bd mov sp, r7
8001452: b008 add sp, #32
8001454: bd80 pop {r7, pc}
8001456: 46c0 nop @ (mov r8, r8)
8001458: 40021000 .word 0x40021000
800145c: 40007000 .word 0x40007000
8001460: 00001388 .word 0x00001388
8001464: efffffff .word 0xefffffff
8001468: feffffff .word 0xfeffffff
800146c: 1fc1808c .word 0x1fc1808c
8001470: effefffc .word 0xeffefffc
08001474 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001474: b580 push {r7, lr}
8001476: b084 sub sp, #16
8001478: af00 add r7, sp, #0
800147a: 6078 str r0, [r7, #4]
800147c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
800147e: 687b ldr r3, [r7, #4]
8001480: 2b00 cmp r3, #0
8001482: d101 bne.n 8001488 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001484: 2301 movs r3, #1
8001486: e0e9 b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the FLASH clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8001488: 4b76 ldr r3, [pc, #472] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
800148a: 681b ldr r3, [r3, #0]
800148c: 2207 movs r2, #7
800148e: 4013 ands r3, r2
8001490: 683a ldr r2, [r7, #0]
8001492: 429a cmp r2, r3
8001494: d91e bls.n 80014d4 <HAL_RCC_ClockConfig+0x60>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001496: 4b73 ldr r3, [pc, #460] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
8001498: 681b ldr r3, [r3, #0]
800149a: 2207 movs r2, #7
800149c: 4393 bics r3, r2
800149e: 0019 movs r1, r3
80014a0: 4b70 ldr r3, [pc, #448] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
80014a2: 683a ldr r2, [r7, #0]
80014a4: 430a orrs r2, r1
80014a6: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
80014a8: f7ff fa72 bl 8000990 <HAL_GetTick>
80014ac: 0003 movs r3, r0
80014ae: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
80014b0: e009 b.n 80014c6 <HAL_RCC_ClockConfig+0x52>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80014b2: f7ff fa6d bl 8000990 <HAL_GetTick>
80014b6: 0002 movs r2, r0
80014b8: 68fb ldr r3, [r7, #12]
80014ba: 1ad3 subs r3, r2, r3
80014bc: 4a6a ldr r2, [pc, #424] @ (8001668 <HAL_RCC_ClockConfig+0x1f4>)
80014be: 4293 cmp r3, r2
80014c0: d901 bls.n 80014c6 <HAL_RCC_ClockConfig+0x52>
{
return HAL_TIMEOUT;
80014c2: 2303 movs r3, #3
80014c4: e0ca b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
80014c6: 4b67 ldr r3, [pc, #412] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
80014c8: 681b ldr r3, [r3, #0]
80014ca: 2207 movs r2, #7
80014cc: 4013 ands r3, r2
80014ce: 683a ldr r2, [r7, #0]
80014d0: 429a cmp r2, r3
80014d2: d1ee bne.n 80014b2 <HAL_RCC_ClockConfig+0x3e>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80014d4: 687b ldr r3, [r7, #4]
80014d6: 681b ldr r3, [r3, #0]
80014d8: 2202 movs r2, #2
80014da: 4013 ands r3, r2
80014dc: d015 beq.n 800150a <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80014de: 687b ldr r3, [r7, #4]
80014e0: 681b ldr r3, [r3, #0]
80014e2: 2204 movs r2, #4
80014e4: 4013 ands r3, r2
80014e6: d006 beq.n 80014f6 <HAL_RCC_ClockConfig+0x82>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
80014e8: 4b60 ldr r3, [pc, #384] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
80014ea: 689a ldr r2, [r3, #8]
80014ec: 4b5f ldr r3, [pc, #380] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
80014ee: 21e0 movs r1, #224 @ 0xe0
80014f0: 01c9 lsls r1, r1, #7
80014f2: 430a orrs r2, r1
80014f4: 609a str r2, [r3, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80014f6: 4b5d ldr r3, [pc, #372] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
80014f8: 689b ldr r3, [r3, #8]
80014fa: 4a5d ldr r2, [pc, #372] @ (8001670 <HAL_RCC_ClockConfig+0x1fc>)
80014fc: 4013 ands r3, r2
80014fe: 0019 movs r1, r3
8001500: 687b ldr r3, [r7, #4]
8001502: 689a ldr r2, [r3, #8]
8001504: 4b59 ldr r3, [pc, #356] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001506: 430a orrs r2, r1
8001508: 609a str r2, [r3, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800150a: 687b ldr r3, [r7, #4]
800150c: 681b ldr r3, [r3, #0]
800150e: 2201 movs r2, #1
8001510: 4013 ands r3, r2
8001512: d057 beq.n 80015c4 <HAL_RCC_ClockConfig+0x150>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001514: 687b ldr r3, [r7, #4]
8001516: 685b ldr r3, [r3, #4]
8001518: 2b01 cmp r3, #1
800151a: d107 bne.n 800152c <HAL_RCC_ClockConfig+0xb8>
{
/* Check the HSE ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800151c: 4b53 ldr r3, [pc, #332] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
800151e: 681a ldr r2, [r3, #0]
8001520: 2380 movs r3, #128 @ 0x80
8001522: 029b lsls r3, r3, #10
8001524: 4013 ands r3, r2
8001526: d12b bne.n 8001580 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001528: 2301 movs r3, #1
800152a: e097 b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800152c: 687b ldr r3, [r7, #4]
800152e: 685b ldr r3, [r3, #4]
8001530: 2b02 cmp r3, #2
8001532: d107 bne.n 8001544 <HAL_RCC_ClockConfig+0xd0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8001534: 4b4d ldr r3, [pc, #308] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001536: 681a ldr r2, [r3, #0]
8001538: 2380 movs r3, #128 @ 0x80
800153a: 049b lsls r3, r3, #18
800153c: 4013 ands r3, r2
800153e: d11f bne.n 8001580 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001540: 2301 movs r3, #1
8001542: e08b b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
}
}
/* HSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001544: 687b ldr r3, [r7, #4]
8001546: 685b ldr r3, [r3, #4]
8001548: 2b00 cmp r3, #0
800154a: d107 bne.n 800155c <HAL_RCC_ClockConfig+0xe8>
{
/* Check the HSI ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800154c: 4b47 ldr r3, [pc, #284] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
800154e: 681a ldr r2, [r3, #0]
8001550: 2380 movs r3, #128 @ 0x80
8001552: 00db lsls r3, r3, #3
8001554: 4013 ands r3, r2
8001556: d113 bne.n 8001580 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8001558: 2301 movs r3, #1
800155a: e07f b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
}
}
/* LSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
800155c: 687b ldr r3, [r7, #4]
800155e: 685b ldr r3, [r3, #4]
8001560: 2b03 cmp r3, #3
8001562: d106 bne.n 8001572 <HAL_RCC_ClockConfig+0xfe>
{
/* Check the LSI ready flag */
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001564: 4b41 ldr r3, [pc, #260] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001566: 6e1b ldr r3, [r3, #96] @ 0x60
8001568: 2202 movs r2, #2
800156a: 4013 ands r3, r2
800156c: d108 bne.n 8001580 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
800156e: 2301 movs r3, #1
8001570: e074 b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
}
/* LSE is selected as System Clock Source */
else
{
/* Check the LSE ready flag */
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001572: 4b3e ldr r3, [pc, #248] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001574: 6ddb ldr r3, [r3, #92] @ 0x5c
8001576: 2202 movs r2, #2
8001578: 4013 ands r3, r2
800157a: d101 bne.n 8001580 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
800157c: 2301 movs r3, #1
800157e: e06d b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8001580: 4b3a ldr r3, [pc, #232] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001582: 689b ldr r3, [r3, #8]
8001584: 2207 movs r2, #7
8001586: 4393 bics r3, r2
8001588: 0019 movs r1, r3
800158a: 687b ldr r3, [r7, #4]
800158c: 685a ldr r2, [r3, #4]
800158e: 4b37 ldr r3, [pc, #220] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001590: 430a orrs r2, r1
8001592: 609a str r2, [r3, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001594: f7ff f9fc bl 8000990 <HAL_GetTick>
8001598: 0003 movs r3, r0
800159a: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800159c: e009 b.n 80015b2 <HAL_RCC_ClockConfig+0x13e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800159e: f7ff f9f7 bl 8000990 <HAL_GetTick>
80015a2: 0002 movs r2, r0
80015a4: 68fb ldr r3, [r7, #12]
80015a6: 1ad3 subs r3, r2, r3
80015a8: 4a2f ldr r2, [pc, #188] @ (8001668 <HAL_RCC_ClockConfig+0x1f4>)
80015aa: 4293 cmp r3, r2
80015ac: d901 bls.n 80015b2 <HAL_RCC_ClockConfig+0x13e>
{
return HAL_TIMEOUT;
80015ae: 2303 movs r3, #3
80015b0: e054 b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80015b2: 4b2e ldr r3, [pc, #184] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
80015b4: 689b ldr r3, [r3, #8]
80015b6: 2238 movs r2, #56 @ 0x38
80015b8: 401a ands r2, r3
80015ba: 687b ldr r3, [r7, #4]
80015bc: 685b ldr r3, [r3, #4]
80015be: 00db lsls r3, r3, #3
80015c0: 429a cmp r2, r3
80015c2: d1ec bne.n 800159e <HAL_RCC_ClockConfig+0x12a>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80015c4: 4b27 ldr r3, [pc, #156] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
80015c6: 681b ldr r3, [r3, #0]
80015c8: 2207 movs r2, #7
80015ca: 4013 ands r3, r2
80015cc: 683a ldr r2, [r7, #0]
80015ce: 429a cmp r2, r3
80015d0: d21e bcs.n 8001610 <HAL_RCC_ClockConfig+0x19c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80015d2: 4b24 ldr r3, [pc, #144] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
80015d4: 681b ldr r3, [r3, #0]
80015d6: 2207 movs r2, #7
80015d8: 4393 bics r3, r2
80015da: 0019 movs r1, r3
80015dc: 4b21 ldr r3, [pc, #132] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
80015de: 683a ldr r2, [r7, #0]
80015e0: 430a orrs r2, r1
80015e2: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
80015e4: f7ff f9d4 bl 8000990 <HAL_GetTick>
80015e8: 0003 movs r3, r0
80015ea: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
80015ec: e009 b.n 8001602 <HAL_RCC_ClockConfig+0x18e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80015ee: f7ff f9cf bl 8000990 <HAL_GetTick>
80015f2: 0002 movs r2, r0
80015f4: 68fb ldr r3, [r7, #12]
80015f6: 1ad3 subs r3, r2, r3
80015f8: 4a1b ldr r2, [pc, #108] @ (8001668 <HAL_RCC_ClockConfig+0x1f4>)
80015fa: 4293 cmp r3, r2
80015fc: d901 bls.n 8001602 <HAL_RCC_ClockConfig+0x18e>
{
return HAL_TIMEOUT;
80015fe: 2303 movs r3, #3
8001600: e02c b.n 800165c <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8001602: 4b18 ldr r3, [pc, #96] @ (8001664 <HAL_RCC_ClockConfig+0x1f0>)
8001604: 681b ldr r3, [r3, #0]
8001606: 2207 movs r2, #7
8001608: 4013 ands r3, r2
800160a: 683a ldr r2, [r7, #0]
800160c: 429a cmp r2, r3
800160e: d1ee bne.n 80015ee <HAL_RCC_ClockConfig+0x17a>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001610: 687b ldr r3, [r7, #4]
8001612: 681b ldr r3, [r3, #0]
8001614: 2204 movs r2, #4
8001616: 4013 ands r3, r2
8001618: d009 beq.n 800162e <HAL_RCC_ClockConfig+0x1ba>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
800161a: 4b14 ldr r3, [pc, #80] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
800161c: 689b ldr r3, [r3, #8]
800161e: 4a15 ldr r2, [pc, #84] @ (8001674 <HAL_RCC_ClockConfig+0x200>)
8001620: 4013 ands r3, r2
8001622: 0019 movs r1, r3
8001624: 687b ldr r3, [r7, #4]
8001626: 68da ldr r2, [r3, #12]
8001628: 4b10 ldr r3, [pc, #64] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
800162a: 430a orrs r2, r1
800162c: 609a str r2, [r3, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
800162e: f000 f829 bl 8001684 <HAL_RCC_GetSysClockFreq>
8001632: 0001 movs r1, r0
8001634: 4b0d ldr r3, [pc, #52] @ (800166c <HAL_RCC_ClockConfig+0x1f8>)
8001636: 689b ldr r3, [r3, #8]
8001638: 0a1b lsrs r3, r3, #8
800163a: 220f movs r2, #15
800163c: 401a ands r2, r3
800163e: 4b0e ldr r3, [pc, #56] @ (8001678 <HAL_RCC_ClockConfig+0x204>)
8001640: 0092 lsls r2, r2, #2
8001642: 58d3 ldr r3, [r2, r3]
8001644: 221f movs r2, #31
8001646: 4013 ands r3, r2
8001648: 000a movs r2, r1
800164a: 40da lsrs r2, r3
800164c: 4b0b ldr r3, [pc, #44] @ (800167c <HAL_RCC_ClockConfig+0x208>)
800164e: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8001650: 4b0b ldr r3, [pc, #44] @ (8001680 <HAL_RCC_ClockConfig+0x20c>)
8001652: 681b ldr r3, [r3, #0]
8001654: 0018 movs r0, r3
8001656: f7ff f93f bl 80008d8 <HAL_InitTick>
800165a: 0003 movs r3, r0
}
800165c: 0018 movs r0, r3
800165e: 46bd mov sp, r7
8001660: b004 add sp, #16
8001662: bd80 pop {r7, pc}
8001664: 40022000 .word 0x40022000
8001668: 00001388 .word 0x00001388
800166c: 40021000 .word 0x40021000
8001670: fffff0ff .word 0xfffff0ff
8001674: ffff8fff .word 0xffff8fff
8001678: 08002674 .word 0x08002674
800167c: 20000000 .word 0x20000000
8001680: 20000004 .word 0x20000004
08001684 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001684: b580 push {r7, lr}
8001686: b086 sub sp, #24
8001688: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800168a: 4b3c ldr r3, [pc, #240] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
800168c: 689b ldr r3, [r3, #8]
800168e: 2238 movs r2, #56 @ 0x38
8001690: 4013 ands r3, r2
8001692: d10f bne.n 80016b4 <HAL_RCC_GetSysClockFreq+0x30>
{
/* HSISYS can be derived for HSI16 */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
8001694: 4b39 ldr r3, [pc, #228] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
8001696: 681b ldr r3, [r3, #0]
8001698: 0adb lsrs r3, r3, #11
800169a: 2207 movs r2, #7
800169c: 4013 ands r3, r2
800169e: 2201 movs r2, #1
80016a0: 409a lsls r2, r3
80016a2: 0013 movs r3, r2
80016a4: 603b str r3, [r7, #0]
/* HSI used as system clock source */
sysclockfreq = (HSI_VALUE / hsidiv);
80016a6: 6839 ldr r1, [r7, #0]
80016a8: 4835 ldr r0, [pc, #212] @ (8001780 <HAL_RCC_GetSysClockFreq+0xfc>)
80016aa: f7fe fd29 bl 8000100 <__udivsi3>
80016ae: 0003 movs r3, r0
80016b0: 613b str r3, [r7, #16]
80016b2: e05d b.n 8001770 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80016b4: 4b31 ldr r3, [pc, #196] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
80016b6: 689b ldr r3, [r3, #8]
80016b8: 2238 movs r2, #56 @ 0x38
80016ba: 4013 ands r3, r2
80016bc: 2b08 cmp r3, #8
80016be: d102 bne.n 80016c6 <HAL_RCC_GetSysClockFreq+0x42>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
80016c0: 4b30 ldr r3, [pc, #192] @ (8001784 <HAL_RCC_GetSysClockFreq+0x100>)
80016c2: 613b str r3, [r7, #16]
80016c4: e054 b.n 8001770 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80016c6: 4b2d ldr r3, [pc, #180] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
80016c8: 689b ldr r3, [r3, #8]
80016ca: 2238 movs r2, #56 @ 0x38
80016cc: 4013 ands r3, r2
80016ce: 2b10 cmp r3, #16
80016d0: d138 bne.n 8001744 <HAL_RCC_GetSysClockFreq+0xc0>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
80016d2: 4b2a ldr r3, [pc, #168] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
80016d4: 68db ldr r3, [r3, #12]
80016d6: 2203 movs r2, #3
80016d8: 4013 ands r3, r2
80016da: 60fb str r3, [r7, #12]
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
80016dc: 4b27 ldr r3, [pc, #156] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
80016de: 68db ldr r3, [r3, #12]
80016e0: 091b lsrs r3, r3, #4
80016e2: 2207 movs r2, #7
80016e4: 4013 ands r3, r2
80016e6: 3301 adds r3, #1
80016e8: 60bb str r3, [r7, #8]
switch (pllsource)
80016ea: 68fb ldr r3, [r7, #12]
80016ec: 2b03 cmp r3, #3
80016ee: d10d bne.n 800170c <HAL_RCC_GetSysClockFreq+0x88>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80016f0: 68b9 ldr r1, [r7, #8]
80016f2: 4824 ldr r0, [pc, #144] @ (8001784 <HAL_RCC_GetSysClockFreq+0x100>)
80016f4: f7fe fd04 bl 8000100 <__udivsi3>
80016f8: 0003 movs r3, r0
80016fa: 0019 movs r1, r3
80016fc: 4b1f ldr r3, [pc, #124] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
80016fe: 68db ldr r3, [r3, #12]
8001700: 0a1b lsrs r3, r3, #8
8001702: 227f movs r2, #127 @ 0x7f
8001704: 4013 ands r3, r2
8001706: 434b muls r3, r1
8001708: 617b str r3, [r7, #20]
break;
800170a: e00d b.n 8001728 <HAL_RCC_GetSysClockFreq+0xa4>
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
default: /* HSI16 used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
800170c: 68b9 ldr r1, [r7, #8]
800170e: 481c ldr r0, [pc, #112] @ (8001780 <HAL_RCC_GetSysClockFreq+0xfc>)
8001710: f7fe fcf6 bl 8000100 <__udivsi3>
8001714: 0003 movs r3, r0
8001716: 0019 movs r1, r3
8001718: 4b18 ldr r3, [pc, #96] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
800171a: 68db ldr r3, [r3, #12]
800171c: 0a1b lsrs r3, r3, #8
800171e: 227f movs r2, #127 @ 0x7f
8001720: 4013 ands r3, r2
8001722: 434b muls r3, r1
8001724: 617b str r3, [r7, #20]
break;
8001726: 46c0 nop @ (mov r8, r8)
}
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
8001728: 4b14 ldr r3, [pc, #80] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
800172a: 68db ldr r3, [r3, #12]
800172c: 0f5b lsrs r3, r3, #29
800172e: 2207 movs r2, #7
8001730: 4013 ands r3, r2
8001732: 3301 adds r3, #1
8001734: 607b str r3, [r7, #4]
sysclockfreq = pllvco / pllr;
8001736: 6879 ldr r1, [r7, #4]
8001738: 6978 ldr r0, [r7, #20]
800173a: f7fe fce1 bl 8000100 <__udivsi3>
800173e: 0003 movs r3, r0
8001740: 613b str r3, [r7, #16]
8001742: e015 b.n 8001770 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
8001744: 4b0d ldr r3, [pc, #52] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
8001746: 689b ldr r3, [r3, #8]
8001748: 2238 movs r2, #56 @ 0x38
800174a: 4013 ands r3, r2
800174c: 2b20 cmp r3, #32
800174e: d103 bne.n 8001758 <HAL_RCC_GetSysClockFreq+0xd4>
{
/* LSE used as system clock source */
sysclockfreq = LSE_VALUE;
8001750: 2380 movs r3, #128 @ 0x80
8001752: 021b lsls r3, r3, #8
8001754: 613b str r3, [r7, #16]
8001756: e00b b.n 8001770 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
8001758: 4b08 ldr r3, [pc, #32] @ (800177c <HAL_RCC_GetSysClockFreq+0xf8>)
800175a: 689b ldr r3, [r3, #8]
800175c: 2238 movs r2, #56 @ 0x38
800175e: 4013 ands r3, r2
8001760: 2b18 cmp r3, #24
8001762: d103 bne.n 800176c <HAL_RCC_GetSysClockFreq+0xe8>
{
/* LSI used as system clock source */
sysclockfreq = LSI_VALUE;
8001764: 23fa movs r3, #250 @ 0xfa
8001766: 01db lsls r3, r3, #7
8001768: 613b str r3, [r7, #16]
800176a: e001 b.n 8001770 <HAL_RCC_GetSysClockFreq+0xec>
}
else
{
sysclockfreq = 0U;
800176c: 2300 movs r3, #0
800176e: 613b str r3, [r7, #16]
}
return sysclockfreq;
8001770: 693b ldr r3, [r7, #16]
}
8001772: 0018 movs r0, r3
8001774: 46bd mov sp, r7
8001776: b006 add sp, #24
8001778: bd80 pop {r7, pc}
800177a: 46c0 nop @ (mov r8, r8)
800177c: 40021000 .word 0x40021000
8001780: 00f42400 .word 0x00f42400
8001784: 007a1200 .word 0x007a1200
08001788 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001788: b580 push {r7, lr}
800178a: b082 sub sp, #8
800178c: af00 add r7, sp, #0
800178e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001790: 687b ldr r3, [r7, #4]
8001792: 2b00 cmp r3, #0
8001794: d101 bne.n 800179a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8001796: 2301 movs r3, #1
8001798: e04a b.n 8001830 <HAL_TIM_Base_Init+0xa8>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800179a: 687b ldr r3, [r7, #4]
800179c: 223d movs r2, #61 @ 0x3d
800179e: 5c9b ldrb r3, [r3, r2]
80017a0: b2db uxtb r3, r3
80017a2: 2b00 cmp r3, #0
80017a4: d107 bne.n 80017b6 <HAL_TIM_Base_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80017a6: 687b ldr r3, [r7, #4]
80017a8: 223c movs r2, #60 @ 0x3c
80017aa: 2100 movs r1, #0
80017ac: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80017ae: 687b ldr r3, [r7, #4]
80017b0: 0018 movs r0, r3
80017b2: f7fe ff69 bl 8000688 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80017b6: 687b ldr r3, [r7, #4]
80017b8: 223d movs r2, #61 @ 0x3d
80017ba: 2102 movs r1, #2
80017bc: 5499 strb r1, [r3, r2]
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80017be: 687b ldr r3, [r7, #4]
80017c0: 681a ldr r2, [r3, #0]
80017c2: 687b ldr r3, [r7, #4]
80017c4: 3304 adds r3, #4
80017c6: 0019 movs r1, r3
80017c8: 0010 movs r0, r2
80017ca: f000 fa6b bl 8001ca4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80017ce: 687b ldr r3, [r7, #4]
80017d0: 2248 movs r2, #72 @ 0x48
80017d2: 2101 movs r1, #1
80017d4: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80017d6: 687b ldr r3, [r7, #4]
80017d8: 223e movs r2, #62 @ 0x3e
80017da: 2101 movs r1, #1
80017dc: 5499 strb r1, [r3, r2]
80017de: 687b ldr r3, [r7, #4]
80017e0: 223f movs r2, #63 @ 0x3f
80017e2: 2101 movs r1, #1
80017e4: 5499 strb r1, [r3, r2]
80017e6: 687b ldr r3, [r7, #4]
80017e8: 2240 movs r2, #64 @ 0x40
80017ea: 2101 movs r1, #1
80017ec: 5499 strb r1, [r3, r2]
80017ee: 687b ldr r3, [r7, #4]
80017f0: 2241 movs r2, #65 @ 0x41
80017f2: 2101 movs r1, #1
80017f4: 5499 strb r1, [r3, r2]
80017f6: 687b ldr r3, [r7, #4]
80017f8: 2242 movs r2, #66 @ 0x42
80017fa: 2101 movs r1, #1
80017fc: 5499 strb r1, [r3, r2]
80017fe: 687b ldr r3, [r7, #4]
8001800: 2243 movs r2, #67 @ 0x43
8001802: 2101 movs r1, #1
8001804: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001806: 687b ldr r3, [r7, #4]
8001808: 2244 movs r2, #68 @ 0x44
800180a: 2101 movs r1, #1
800180c: 5499 strb r1, [r3, r2]
800180e: 687b ldr r3, [r7, #4]
8001810: 2245 movs r2, #69 @ 0x45
8001812: 2101 movs r1, #1
8001814: 5499 strb r1, [r3, r2]
8001816: 687b ldr r3, [r7, #4]
8001818: 2246 movs r2, #70 @ 0x46
800181a: 2101 movs r1, #1
800181c: 5499 strb r1, [r3, r2]
800181e: 687b ldr r3, [r7, #4]
8001820: 2247 movs r2, #71 @ 0x47
8001822: 2101 movs r1, #1
8001824: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001826: 687b ldr r3, [r7, #4]
8001828: 223d movs r2, #61 @ 0x3d
800182a: 2101 movs r1, #1
800182c: 5499 strb r1, [r3, r2]
return HAL_OK;
800182e: 2300 movs r3, #0
}
8001830: 0018 movs r0, r3
8001832: 46bd mov sp, r7
8001834: b002 add sp, #8
8001836: bd80 pop {r7, pc}
08001838 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8001838: b580 push {r7, lr}
800183a: b082 sub sp, #8
800183c: af00 add r7, sp, #0
800183e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001840: 687b ldr r3, [r7, #4]
8001842: 2b00 cmp r3, #0
8001844: d101 bne.n 800184a <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8001846: 2301 movs r3, #1
8001848: e04a b.n 80018e0 <HAL_TIM_PWM_Init+0xa8>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800184a: 687b ldr r3, [r7, #4]
800184c: 223d movs r2, #61 @ 0x3d
800184e: 5c9b ldrb r3, [r3, r2]
8001850: b2db uxtb r3, r3
8001852: 2b00 cmp r3, #0
8001854: d107 bne.n 8001866 <HAL_TIM_PWM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001856: 687b ldr r3, [r7, #4]
8001858: 223c movs r2, #60 @ 0x3c
800185a: 2100 movs r1, #0
800185c: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
800185e: 687b ldr r3, [r7, #4]
8001860: 0018 movs r0, r3
8001862: f000 f841 bl 80018e8 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001866: 687b ldr r3, [r7, #4]
8001868: 223d movs r2, #61 @ 0x3d
800186a: 2102 movs r1, #2
800186c: 5499 strb r1, [r3, r2]
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800186e: 687b ldr r3, [r7, #4]
8001870: 681a ldr r2, [r3, #0]
8001872: 687b ldr r3, [r7, #4]
8001874: 3304 adds r3, #4
8001876: 0019 movs r1, r3
8001878: 0010 movs r0, r2
800187a: f000 fa13 bl 8001ca4 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800187e: 687b ldr r3, [r7, #4]
8001880: 2248 movs r2, #72 @ 0x48
8001882: 2101 movs r1, #1
8001884: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001886: 687b ldr r3, [r7, #4]
8001888: 223e movs r2, #62 @ 0x3e
800188a: 2101 movs r1, #1
800188c: 5499 strb r1, [r3, r2]
800188e: 687b ldr r3, [r7, #4]
8001890: 223f movs r2, #63 @ 0x3f
8001892: 2101 movs r1, #1
8001894: 5499 strb r1, [r3, r2]
8001896: 687b ldr r3, [r7, #4]
8001898: 2240 movs r2, #64 @ 0x40
800189a: 2101 movs r1, #1
800189c: 5499 strb r1, [r3, r2]
800189e: 687b ldr r3, [r7, #4]
80018a0: 2241 movs r2, #65 @ 0x41
80018a2: 2101 movs r1, #1
80018a4: 5499 strb r1, [r3, r2]
80018a6: 687b ldr r3, [r7, #4]
80018a8: 2242 movs r2, #66 @ 0x42
80018aa: 2101 movs r1, #1
80018ac: 5499 strb r1, [r3, r2]
80018ae: 687b ldr r3, [r7, #4]
80018b0: 2243 movs r2, #67 @ 0x43
80018b2: 2101 movs r1, #1
80018b4: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80018b6: 687b ldr r3, [r7, #4]
80018b8: 2244 movs r2, #68 @ 0x44
80018ba: 2101 movs r1, #1
80018bc: 5499 strb r1, [r3, r2]
80018be: 687b ldr r3, [r7, #4]
80018c0: 2245 movs r2, #69 @ 0x45
80018c2: 2101 movs r1, #1
80018c4: 5499 strb r1, [r3, r2]
80018c6: 687b ldr r3, [r7, #4]
80018c8: 2246 movs r2, #70 @ 0x46
80018ca: 2101 movs r1, #1
80018cc: 5499 strb r1, [r3, r2]
80018ce: 687b ldr r3, [r7, #4]
80018d0: 2247 movs r2, #71 @ 0x47
80018d2: 2101 movs r1, #1
80018d4: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80018d6: 687b ldr r3, [r7, #4]
80018d8: 223d movs r2, #61 @ 0x3d
80018da: 2101 movs r1, #1
80018dc: 5499 strb r1, [r3, r2]
return HAL_OK;
80018de: 2300 movs r3, #0
}
80018e0: 0018 movs r0, r3
80018e2: 46bd mov sp, r7
80018e4: b002 add sp, #8
80018e6: bd80 pop {r7, pc}
080018e8 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80018e8: b580 push {r7, lr}
80018ea: b082 sub sp, #8
80018ec: af00 add r7, sp, #0
80018ee: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80018f0: 46c0 nop @ (mov r8, r8)
80018f2: 46bd mov sp, r7
80018f4: b002 add sp, #8
80018f6: bd80 pop {r7, pc}
080018f8 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80018f8: b580 push {r7, lr}
80018fa: b086 sub sp, #24
80018fc: af00 add r7, sp, #0
80018fe: 60f8 str r0, [r7, #12]
8001900: 60b9 str r1, [r7, #8]
8001902: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001904: 2317 movs r3, #23
8001906: 18fb adds r3, r7, r3
8001908: 2200 movs r2, #0
800190a: 701a strb r2, [r3, #0]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
800190c: 68fb ldr r3, [r7, #12]
800190e: 223c movs r2, #60 @ 0x3c
8001910: 5c9b ldrb r3, [r3, r2]
8001912: 2b01 cmp r3, #1
8001914: d101 bne.n 800191a <HAL_TIM_PWM_ConfigChannel+0x22>
8001916: 2302 movs r3, #2
8001918: e0e5 b.n 8001ae6 <HAL_TIM_PWM_ConfigChannel+0x1ee>
800191a: 68fb ldr r3, [r7, #12]
800191c: 223c movs r2, #60 @ 0x3c
800191e: 2101 movs r1, #1
8001920: 5499 strb r1, [r3, r2]
switch (Channel)
8001922: 687b ldr r3, [r7, #4]
8001924: 2b14 cmp r3, #20
8001926: d900 bls.n 800192a <HAL_TIM_PWM_ConfigChannel+0x32>
8001928: e0d1 b.n 8001ace <HAL_TIM_PWM_ConfigChannel+0x1d6>
800192a: 687b ldr r3, [r7, #4]
800192c: 009a lsls r2, r3, #2
800192e: 4b70 ldr r3, [pc, #448] @ (8001af0 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
8001930: 18d3 adds r3, r2, r3
8001932: 681b ldr r3, [r3, #0]
8001934: 469f mov pc, r3
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8001936: 68fb ldr r3, [r7, #12]
8001938: 681b ldr r3, [r3, #0]
800193a: 68ba ldr r2, [r7, #8]
800193c: 0011 movs r1, r2
800193e: 0018 movs r0, r3
8001940: f000 fa2a bl 8001d98 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8001944: 68fb ldr r3, [r7, #12]
8001946: 681b ldr r3, [r3, #0]
8001948: 699a ldr r2, [r3, #24]
800194a: 68fb ldr r3, [r7, #12]
800194c: 681b ldr r3, [r3, #0]
800194e: 2108 movs r1, #8
8001950: 430a orrs r2, r1
8001952: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8001954: 68fb ldr r3, [r7, #12]
8001956: 681b ldr r3, [r3, #0]
8001958: 699a ldr r2, [r3, #24]
800195a: 68fb ldr r3, [r7, #12]
800195c: 681b ldr r3, [r3, #0]
800195e: 2104 movs r1, #4
8001960: 438a bics r2, r1
8001962: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8001964: 68fb ldr r3, [r7, #12]
8001966: 681b ldr r3, [r3, #0]
8001968: 6999 ldr r1, [r3, #24]
800196a: 68bb ldr r3, [r7, #8]
800196c: 691a ldr r2, [r3, #16]
800196e: 68fb ldr r3, [r7, #12]
8001970: 681b ldr r3, [r3, #0]
8001972: 430a orrs r2, r1
8001974: 619a str r2, [r3, #24]
break;
8001976: e0af b.n 8001ad8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8001978: 68fb ldr r3, [r7, #12]
800197a: 681b ldr r3, [r3, #0]
800197c: 68ba ldr r2, [r7, #8]
800197e: 0011 movs r1, r2
8001980: 0018 movs r0, r3
8001982: f000 fa89 bl 8001e98 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8001986: 68fb ldr r3, [r7, #12]
8001988: 681b ldr r3, [r3, #0]
800198a: 699a ldr r2, [r3, #24]
800198c: 68fb ldr r3, [r7, #12]
800198e: 681b ldr r3, [r3, #0]
8001990: 2180 movs r1, #128 @ 0x80
8001992: 0109 lsls r1, r1, #4
8001994: 430a orrs r2, r1
8001996: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8001998: 68fb ldr r3, [r7, #12]
800199a: 681b ldr r3, [r3, #0]
800199c: 699a ldr r2, [r3, #24]
800199e: 68fb ldr r3, [r7, #12]
80019a0: 681b ldr r3, [r3, #0]
80019a2: 4954 ldr r1, [pc, #336] @ (8001af4 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
80019a4: 400a ands r2, r1
80019a6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80019a8: 68fb ldr r3, [r7, #12]
80019aa: 681b ldr r3, [r3, #0]
80019ac: 6999 ldr r1, [r3, #24]
80019ae: 68bb ldr r3, [r7, #8]
80019b0: 691b ldr r3, [r3, #16]
80019b2: 021a lsls r2, r3, #8
80019b4: 68fb ldr r3, [r7, #12]
80019b6: 681b ldr r3, [r3, #0]
80019b8: 430a orrs r2, r1
80019ba: 619a str r2, [r3, #24]
break;
80019bc: e08c b.n 8001ad8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80019be: 68fb ldr r3, [r7, #12]
80019c0: 681b ldr r3, [r3, #0]
80019c2: 68ba ldr r2, [r7, #8]
80019c4: 0011 movs r1, r2
80019c6: 0018 movs r0, r3
80019c8: f000 fae4 bl 8001f94 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80019cc: 68fb ldr r3, [r7, #12]
80019ce: 681b ldr r3, [r3, #0]
80019d0: 69da ldr r2, [r3, #28]
80019d2: 68fb ldr r3, [r7, #12]
80019d4: 681b ldr r3, [r3, #0]
80019d6: 2108 movs r1, #8
80019d8: 430a orrs r2, r1
80019da: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80019dc: 68fb ldr r3, [r7, #12]
80019de: 681b ldr r3, [r3, #0]
80019e0: 69da ldr r2, [r3, #28]
80019e2: 68fb ldr r3, [r7, #12]
80019e4: 681b ldr r3, [r3, #0]
80019e6: 2104 movs r1, #4
80019e8: 438a bics r2, r1
80019ea: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80019ec: 68fb ldr r3, [r7, #12]
80019ee: 681b ldr r3, [r3, #0]
80019f0: 69d9 ldr r1, [r3, #28]
80019f2: 68bb ldr r3, [r7, #8]
80019f4: 691a ldr r2, [r3, #16]
80019f6: 68fb ldr r3, [r7, #12]
80019f8: 681b ldr r3, [r3, #0]
80019fa: 430a orrs r2, r1
80019fc: 61da str r2, [r3, #28]
break;
80019fe: e06b b.n 8001ad8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8001a00: 68fb ldr r3, [r7, #12]
8001a02: 681b ldr r3, [r3, #0]
8001a04: 68ba ldr r2, [r7, #8]
8001a06: 0011 movs r1, r2
8001a08: 0018 movs r0, r3
8001a0a: f000 fb45 bl 8002098 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8001a0e: 68fb ldr r3, [r7, #12]
8001a10: 681b ldr r3, [r3, #0]
8001a12: 69da ldr r2, [r3, #28]
8001a14: 68fb ldr r3, [r7, #12]
8001a16: 681b ldr r3, [r3, #0]
8001a18: 2180 movs r1, #128 @ 0x80
8001a1a: 0109 lsls r1, r1, #4
8001a1c: 430a orrs r2, r1
8001a1e: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8001a20: 68fb ldr r3, [r7, #12]
8001a22: 681b ldr r3, [r3, #0]
8001a24: 69da ldr r2, [r3, #28]
8001a26: 68fb ldr r3, [r7, #12]
8001a28: 681b ldr r3, [r3, #0]
8001a2a: 4932 ldr r1, [pc, #200] @ (8001af4 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8001a2c: 400a ands r2, r1
8001a2e: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8001a30: 68fb ldr r3, [r7, #12]
8001a32: 681b ldr r3, [r3, #0]
8001a34: 69d9 ldr r1, [r3, #28]
8001a36: 68bb ldr r3, [r7, #8]
8001a38: 691b ldr r3, [r3, #16]
8001a3a: 021a lsls r2, r3, #8
8001a3c: 68fb ldr r3, [r7, #12]
8001a3e: 681b ldr r3, [r3, #0]
8001a40: 430a orrs r2, r1
8001a42: 61da str r2, [r3, #28]
break;
8001a44: e048 b.n 8001ad8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8001a46: 68fb ldr r3, [r7, #12]
8001a48: 681b ldr r3, [r3, #0]
8001a4a: 68ba ldr r2, [r7, #8]
8001a4c: 0011 movs r1, r2
8001a4e: 0018 movs r0, r3
8001a50: f000 fb86 bl 8002160 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8001a54: 68fb ldr r3, [r7, #12]
8001a56: 681b ldr r3, [r3, #0]
8001a58: 6d5a ldr r2, [r3, #84] @ 0x54
8001a5a: 68fb ldr r3, [r7, #12]
8001a5c: 681b ldr r3, [r3, #0]
8001a5e: 2108 movs r1, #8
8001a60: 430a orrs r2, r1
8001a62: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8001a64: 68fb ldr r3, [r7, #12]
8001a66: 681b ldr r3, [r3, #0]
8001a68: 6d5a ldr r2, [r3, #84] @ 0x54
8001a6a: 68fb ldr r3, [r7, #12]
8001a6c: 681b ldr r3, [r3, #0]
8001a6e: 2104 movs r1, #4
8001a70: 438a bics r2, r1
8001a72: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8001a74: 68fb ldr r3, [r7, #12]
8001a76: 681b ldr r3, [r3, #0]
8001a78: 6d59 ldr r1, [r3, #84] @ 0x54
8001a7a: 68bb ldr r3, [r7, #8]
8001a7c: 691a ldr r2, [r3, #16]
8001a7e: 68fb ldr r3, [r7, #12]
8001a80: 681b ldr r3, [r3, #0]
8001a82: 430a orrs r2, r1
8001a84: 655a str r2, [r3, #84] @ 0x54
break;
8001a86: e027 b.n 8001ad8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8001a88: 68fb ldr r3, [r7, #12]
8001a8a: 681b ldr r3, [r3, #0]
8001a8c: 68ba ldr r2, [r7, #8]
8001a8e: 0011 movs r1, r2
8001a90: 0018 movs r0, r3
8001a92: f000 fbbf bl 8002214 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8001a96: 68fb ldr r3, [r7, #12]
8001a98: 681b ldr r3, [r3, #0]
8001a9a: 6d5a ldr r2, [r3, #84] @ 0x54
8001a9c: 68fb ldr r3, [r7, #12]
8001a9e: 681b ldr r3, [r3, #0]
8001aa0: 2180 movs r1, #128 @ 0x80
8001aa2: 0109 lsls r1, r1, #4
8001aa4: 430a orrs r2, r1
8001aa6: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8001aa8: 68fb ldr r3, [r7, #12]
8001aaa: 681b ldr r3, [r3, #0]
8001aac: 6d5a ldr r2, [r3, #84] @ 0x54
8001aae: 68fb ldr r3, [r7, #12]
8001ab0: 681b ldr r3, [r3, #0]
8001ab2: 4910 ldr r1, [pc, #64] @ (8001af4 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8001ab4: 400a ands r2, r1
8001ab6: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8001ab8: 68fb ldr r3, [r7, #12]
8001aba: 681b ldr r3, [r3, #0]
8001abc: 6d59 ldr r1, [r3, #84] @ 0x54
8001abe: 68bb ldr r3, [r7, #8]
8001ac0: 691b ldr r3, [r3, #16]
8001ac2: 021a lsls r2, r3, #8
8001ac4: 68fb ldr r3, [r7, #12]
8001ac6: 681b ldr r3, [r3, #0]
8001ac8: 430a orrs r2, r1
8001aca: 655a str r2, [r3, #84] @ 0x54
break;
8001acc: e004 b.n 8001ad8 <HAL_TIM_PWM_ConfigChannel+0x1e0>
}
default:
status = HAL_ERROR;
8001ace: 2317 movs r3, #23
8001ad0: 18fb adds r3, r7, r3
8001ad2: 2201 movs r2, #1
8001ad4: 701a strb r2, [r3, #0]
break;
8001ad6: 46c0 nop @ (mov r8, r8)
}
__HAL_UNLOCK(htim);
8001ad8: 68fb ldr r3, [r7, #12]
8001ada: 223c movs r2, #60 @ 0x3c
8001adc: 2100 movs r1, #0
8001ade: 5499 strb r1, [r3, r2]
return status;
8001ae0: 2317 movs r3, #23
8001ae2: 18fb adds r3, r7, r3
8001ae4: 781b ldrb r3, [r3, #0]
}
8001ae6: 0018 movs r0, r3
8001ae8: 46bd mov sp, r7
8001aea: b006 add sp, #24
8001aec: bd80 pop {r7, pc}
8001aee: 46c0 nop @ (mov r8, r8)
8001af0: 080026b4 .word 0x080026b4
8001af4: fffffbff .word 0xfffffbff
08001af8 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8001af8: b580 push {r7, lr}
8001afa: b084 sub sp, #16
8001afc: af00 add r7, sp, #0
8001afe: 6078 str r0, [r7, #4]
8001b00: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8001b02: 230f movs r3, #15
8001b04: 18fb adds r3, r7, r3
8001b06: 2200 movs r2, #0
8001b08: 701a strb r2, [r3, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8001b0a: 687b ldr r3, [r7, #4]
8001b0c: 223c movs r2, #60 @ 0x3c
8001b0e: 5c9b ldrb r3, [r3, r2]
8001b10: 2b01 cmp r3, #1
8001b12: d101 bne.n 8001b18 <HAL_TIM_ConfigClockSource+0x20>
8001b14: 2302 movs r3, #2
8001b16: e0bc b.n 8001c92 <HAL_TIM_ConfigClockSource+0x19a>
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 223c movs r2, #60 @ 0x3c
8001b1c: 2101 movs r1, #1
8001b1e: 5499 strb r1, [r3, r2]
htim->State = HAL_TIM_STATE_BUSY;
8001b20: 687b ldr r3, [r7, #4]
8001b22: 223d movs r2, #61 @ 0x3d
8001b24: 2102 movs r1, #2
8001b26: 5499 strb r1, [r3, r2]
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8001b28: 687b ldr r3, [r7, #4]
8001b2a: 681b ldr r3, [r3, #0]
8001b2c: 689b ldr r3, [r3, #8]
8001b2e: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8001b30: 68bb ldr r3, [r7, #8]
8001b32: 4a5a ldr r2, [pc, #360] @ (8001c9c <HAL_TIM_ConfigClockSource+0x1a4>)
8001b34: 4013 ands r3, r2
8001b36: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8001b38: 68bb ldr r3, [r7, #8]
8001b3a: 4a59 ldr r2, [pc, #356] @ (8001ca0 <HAL_TIM_ConfigClockSource+0x1a8>)
8001b3c: 4013 ands r3, r2
8001b3e: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8001b40: 687b ldr r3, [r7, #4]
8001b42: 681b ldr r3, [r3, #0]
8001b44: 68ba ldr r2, [r7, #8]
8001b46: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8001b48: 683b ldr r3, [r7, #0]
8001b4a: 681b ldr r3, [r3, #0]
8001b4c: 2280 movs r2, #128 @ 0x80
8001b4e: 0192 lsls r2, r2, #6
8001b50: 4293 cmp r3, r2
8001b52: d040 beq.n 8001bd6 <HAL_TIM_ConfigClockSource+0xde>
8001b54: 2280 movs r2, #128 @ 0x80
8001b56: 0192 lsls r2, r2, #6
8001b58: 4293 cmp r3, r2
8001b5a: d900 bls.n 8001b5e <HAL_TIM_ConfigClockSource+0x66>
8001b5c: e088 b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b5e: 2280 movs r2, #128 @ 0x80
8001b60: 0152 lsls r2, r2, #5
8001b62: 4293 cmp r3, r2
8001b64: d100 bne.n 8001b68 <HAL_TIM_ConfigClockSource+0x70>
8001b66: e088 b.n 8001c7a <HAL_TIM_ConfigClockSource+0x182>
8001b68: 2280 movs r2, #128 @ 0x80
8001b6a: 0152 lsls r2, r2, #5
8001b6c: 4293 cmp r3, r2
8001b6e: d900 bls.n 8001b72 <HAL_TIM_ConfigClockSource+0x7a>
8001b70: e07e b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b72: 2b70 cmp r3, #112 @ 0x70
8001b74: d018 beq.n 8001ba8 <HAL_TIM_ConfigClockSource+0xb0>
8001b76: d900 bls.n 8001b7a <HAL_TIM_ConfigClockSource+0x82>
8001b78: e07a b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b7a: 2b60 cmp r3, #96 @ 0x60
8001b7c: d04f beq.n 8001c1e <HAL_TIM_ConfigClockSource+0x126>
8001b7e: d900 bls.n 8001b82 <HAL_TIM_ConfigClockSource+0x8a>
8001b80: e076 b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b82: 2b50 cmp r3, #80 @ 0x50
8001b84: d03b beq.n 8001bfe <HAL_TIM_ConfigClockSource+0x106>
8001b86: d900 bls.n 8001b8a <HAL_TIM_ConfigClockSource+0x92>
8001b88: e072 b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b8a: 2b40 cmp r3, #64 @ 0x40
8001b8c: d057 beq.n 8001c3e <HAL_TIM_ConfigClockSource+0x146>
8001b8e: d900 bls.n 8001b92 <HAL_TIM_ConfigClockSource+0x9a>
8001b90: e06e b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b92: 2b30 cmp r3, #48 @ 0x30
8001b94: d063 beq.n 8001c5e <HAL_TIM_ConfigClockSource+0x166>
8001b96: d86b bhi.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b98: 2b20 cmp r3, #32
8001b9a: d060 beq.n 8001c5e <HAL_TIM_ConfigClockSource+0x166>
8001b9c: d868 bhi.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
8001b9e: 2b00 cmp r3, #0
8001ba0: d05d beq.n 8001c5e <HAL_TIM_ConfigClockSource+0x166>
8001ba2: 2b10 cmp r3, #16
8001ba4: d05b beq.n 8001c5e <HAL_TIM_ConfigClockSource+0x166>
8001ba6: e063 b.n 8001c70 <HAL_TIM_ConfigClockSource+0x178>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8001bac: 683b ldr r3, [r7, #0]
8001bae: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8001bb0: 683b ldr r3, [r7, #0]
8001bb2: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8001bb4: 683b ldr r3, [r7, #0]
8001bb6: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8001bb8: f000 fc06 bl 80023c8 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8001bbc: 687b ldr r3, [r7, #4]
8001bbe: 681b ldr r3, [r3, #0]
8001bc0: 689b ldr r3, [r3, #8]
8001bc2: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8001bc4: 68bb ldr r3, [r7, #8]
8001bc6: 2277 movs r2, #119 @ 0x77
8001bc8: 4313 orrs r3, r2
8001bca: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8001bcc: 687b ldr r3, [r7, #4]
8001bce: 681b ldr r3, [r3, #0]
8001bd0: 68ba ldr r2, [r7, #8]
8001bd2: 609a str r2, [r3, #8]
break;
8001bd4: e052 b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8001bd6: 687b ldr r3, [r7, #4]
8001bd8: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8001bda: 683b ldr r3, [r7, #0]
8001bdc: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8001bde: 683b ldr r3, [r7, #0]
8001be0: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8001be2: 683b ldr r3, [r7, #0]
8001be4: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8001be6: f000 fbef bl 80023c8 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8001bea: 687b ldr r3, [r7, #4]
8001bec: 681b ldr r3, [r3, #0]
8001bee: 689a ldr r2, [r3, #8]
8001bf0: 687b ldr r3, [r7, #4]
8001bf2: 681b ldr r3, [r3, #0]
8001bf4: 2180 movs r1, #128 @ 0x80
8001bf6: 01c9 lsls r1, r1, #7
8001bf8: 430a orrs r2, r1
8001bfa: 609a str r2, [r3, #8]
break;
8001bfc: e03e b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8001bfe: 687b ldr r3, [r7, #4]
8001c00: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8001c02: 683b ldr r3, [r7, #0]
8001c04: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8001c06: 683b ldr r3, [r7, #0]
8001c08: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8001c0a: 001a movs r2, r3
8001c0c: f000 fb60 bl 80022d0 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8001c10: 687b ldr r3, [r7, #4]
8001c12: 681b ldr r3, [r3, #0]
8001c14: 2150 movs r1, #80 @ 0x50
8001c16: 0018 movs r0, r3
8001c18: f000 fbba bl 8002390 <TIM_ITRx_SetConfig>
break;
8001c1c: e02e b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8001c1e: 687b ldr r3, [r7, #4]
8001c20: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8001c22: 683b ldr r3, [r7, #0]
8001c24: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8001c26: 683b ldr r3, [r7, #0]
8001c28: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8001c2a: 001a movs r2, r3
8001c2c: f000 fb7e bl 800232c <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8001c30: 687b ldr r3, [r7, #4]
8001c32: 681b ldr r3, [r3, #0]
8001c34: 2160 movs r1, #96 @ 0x60
8001c36: 0018 movs r0, r3
8001c38: f000 fbaa bl 8002390 <TIM_ITRx_SetConfig>
break;
8001c3c: e01e b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8001c42: 683b ldr r3, [r7, #0]
8001c44: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8001c46: 683b ldr r3, [r7, #0]
8001c48: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8001c4a: 001a movs r2, r3
8001c4c: f000 fb40 bl 80022d0 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8001c50: 687b ldr r3, [r7, #4]
8001c52: 681b ldr r3, [r3, #0]
8001c54: 2140 movs r1, #64 @ 0x40
8001c56: 0018 movs r0, r3
8001c58: f000 fb9a bl 8002390 <TIM_ITRx_SetConfig>
break;
8001c5c: e00e b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8001c5e: 687b ldr r3, [r7, #4]
8001c60: 681a ldr r2, [r3, #0]
8001c62: 683b ldr r3, [r7, #0]
8001c64: 681b ldr r3, [r3, #0]
8001c66: 0019 movs r1, r3
8001c68: 0010 movs r0, r2
8001c6a: f000 fb91 bl 8002390 <TIM_ITRx_SetConfig>
break;
8001c6e: e005 b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
}
default:
status = HAL_ERROR;
8001c70: 230f movs r3, #15
8001c72: 18fb adds r3, r7, r3
8001c74: 2201 movs r2, #1
8001c76: 701a strb r2, [r3, #0]
break;
8001c78: e000 b.n 8001c7c <HAL_TIM_ConfigClockSource+0x184>
break;
8001c7a: 46c0 nop @ (mov r8, r8)
}
htim->State = HAL_TIM_STATE_READY;
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 223d movs r2, #61 @ 0x3d
8001c80: 2101 movs r1, #1
8001c82: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
8001c84: 687b ldr r3, [r7, #4]
8001c86: 223c movs r2, #60 @ 0x3c
8001c88: 2100 movs r1, #0
8001c8a: 5499 strb r1, [r3, r2]
return status;
8001c8c: 230f movs r3, #15
8001c8e: 18fb adds r3, r7, r3
8001c90: 781b ldrb r3, [r3, #0]
}
8001c92: 0018 movs r0, r3
8001c94: 46bd mov sp, r7
8001c96: b004 add sp, #16
8001c98: bd80 pop {r7, pc}
8001c9a: 46c0 nop @ (mov r8, r8)
8001c9c: ffceff88 .word 0xffceff88
8001ca0: ffff00ff .word 0xffff00ff
08001ca4 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8001ca4: b580 push {r7, lr}
8001ca6: b084 sub sp, #16
8001ca8: af00 add r7, sp, #0
8001caa: 6078 str r0, [r7, #4]
8001cac: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8001cae: 687b ldr r3, [r7, #4]
8001cb0: 681b ldr r3, [r3, #0]
8001cb2: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8001cb4: 687b ldr r3, [r7, #4]
8001cb6: 4a32 ldr r2, [pc, #200] @ (8001d80 <TIM_Base_SetConfig+0xdc>)
8001cb8: 4293 cmp r3, r2
8001cba: d003 beq.n 8001cc4 <TIM_Base_SetConfig+0x20>
8001cbc: 687b ldr r3, [r7, #4]
8001cbe: 4a31 ldr r2, [pc, #196] @ (8001d84 <TIM_Base_SetConfig+0xe0>)
8001cc0: 4293 cmp r3, r2
8001cc2: d108 bne.n 8001cd6 <TIM_Base_SetConfig+0x32>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8001cc4: 68fb ldr r3, [r7, #12]
8001cc6: 2270 movs r2, #112 @ 0x70
8001cc8: 4393 bics r3, r2
8001cca: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8001ccc: 683b ldr r3, [r7, #0]
8001cce: 685b ldr r3, [r3, #4]
8001cd0: 68fa ldr r2, [r7, #12]
8001cd2: 4313 orrs r3, r2
8001cd4: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8001cd6: 687b ldr r3, [r7, #4]
8001cd8: 4a29 ldr r2, [pc, #164] @ (8001d80 <TIM_Base_SetConfig+0xdc>)
8001cda: 4293 cmp r3, r2
8001cdc: d00f beq.n 8001cfe <TIM_Base_SetConfig+0x5a>
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 4a28 ldr r2, [pc, #160] @ (8001d84 <TIM_Base_SetConfig+0xe0>)
8001ce2: 4293 cmp r3, r2
8001ce4: d00b beq.n 8001cfe <TIM_Base_SetConfig+0x5a>
8001ce6: 687b ldr r3, [r7, #4]
8001ce8: 4a27 ldr r2, [pc, #156] @ (8001d88 <TIM_Base_SetConfig+0xe4>)
8001cea: 4293 cmp r3, r2
8001cec: d007 beq.n 8001cfe <TIM_Base_SetConfig+0x5a>
8001cee: 687b ldr r3, [r7, #4]
8001cf0: 4a26 ldr r2, [pc, #152] @ (8001d8c <TIM_Base_SetConfig+0xe8>)
8001cf2: 4293 cmp r3, r2
8001cf4: d003 beq.n 8001cfe <TIM_Base_SetConfig+0x5a>
8001cf6: 687b ldr r3, [r7, #4]
8001cf8: 4a25 ldr r2, [pc, #148] @ (8001d90 <TIM_Base_SetConfig+0xec>)
8001cfa: 4293 cmp r3, r2
8001cfc: d108 bne.n 8001d10 <TIM_Base_SetConfig+0x6c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8001cfe: 68fb ldr r3, [r7, #12]
8001d00: 4a24 ldr r2, [pc, #144] @ (8001d94 <TIM_Base_SetConfig+0xf0>)
8001d02: 4013 ands r3, r2
8001d04: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8001d06: 683b ldr r3, [r7, #0]
8001d08: 68db ldr r3, [r3, #12]
8001d0a: 68fa ldr r2, [r7, #12]
8001d0c: 4313 orrs r3, r2
8001d0e: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8001d10: 68fb ldr r3, [r7, #12]
8001d12: 2280 movs r2, #128 @ 0x80
8001d14: 4393 bics r3, r2
8001d16: 001a movs r2, r3
8001d18: 683b ldr r3, [r7, #0]
8001d1a: 695b ldr r3, [r3, #20]
8001d1c: 4313 orrs r3, r2
8001d1e: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8001d20: 687b ldr r3, [r7, #4]
8001d22: 68fa ldr r2, [r7, #12]
8001d24: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8001d26: 683b ldr r3, [r7, #0]
8001d28: 689a ldr r2, [r3, #8]
8001d2a: 687b ldr r3, [r7, #4]
8001d2c: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8001d2e: 683b ldr r3, [r7, #0]
8001d30: 681a ldr r2, [r3, #0]
8001d32: 687b ldr r3, [r7, #4]
8001d34: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8001d36: 687b ldr r3, [r7, #4]
8001d38: 4a11 ldr r2, [pc, #68] @ (8001d80 <TIM_Base_SetConfig+0xdc>)
8001d3a: 4293 cmp r3, r2
8001d3c: d007 beq.n 8001d4e <TIM_Base_SetConfig+0xaa>
8001d3e: 687b ldr r3, [r7, #4]
8001d40: 4a12 ldr r2, [pc, #72] @ (8001d8c <TIM_Base_SetConfig+0xe8>)
8001d42: 4293 cmp r3, r2
8001d44: d003 beq.n 8001d4e <TIM_Base_SetConfig+0xaa>
8001d46: 687b ldr r3, [r7, #4]
8001d48: 4a11 ldr r2, [pc, #68] @ (8001d90 <TIM_Base_SetConfig+0xec>)
8001d4a: 4293 cmp r3, r2
8001d4c: d103 bne.n 8001d56 <TIM_Base_SetConfig+0xb2>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8001d4e: 683b ldr r3, [r7, #0]
8001d50: 691a ldr r2, [r3, #16]
8001d52: 687b ldr r3, [r7, #4]
8001d54: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8001d56: 687b ldr r3, [r7, #4]
8001d58: 2201 movs r2, #1
8001d5a: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 691b ldr r3, [r3, #16]
8001d60: 2201 movs r2, #1
8001d62: 4013 ands r3, r2
8001d64: 2b01 cmp r3, #1
8001d66: d106 bne.n 8001d76 <TIM_Base_SetConfig+0xd2>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8001d68: 687b ldr r3, [r7, #4]
8001d6a: 691b ldr r3, [r3, #16]
8001d6c: 2201 movs r2, #1
8001d6e: 4393 bics r3, r2
8001d70: 001a movs r2, r3
8001d72: 687b ldr r3, [r7, #4]
8001d74: 611a str r2, [r3, #16]
}
}
8001d76: 46c0 nop @ (mov r8, r8)
8001d78: 46bd mov sp, r7
8001d7a: b004 add sp, #16
8001d7c: bd80 pop {r7, pc}
8001d7e: 46c0 nop @ (mov r8, r8)
8001d80: 40012c00 .word 0x40012c00
8001d84: 40000400 .word 0x40000400
8001d88: 40002000 .word 0x40002000
8001d8c: 40014400 .word 0x40014400
8001d90: 40014800 .word 0x40014800
8001d94: fffffcff .word 0xfffffcff
08001d98 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001d98: b580 push {r7, lr}
8001d9a: b086 sub sp, #24
8001d9c: af00 add r7, sp, #0
8001d9e: 6078 str r0, [r7, #4]
8001da0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001da2: 687b ldr r3, [r7, #4]
8001da4: 6a1b ldr r3, [r3, #32]
8001da6: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8001da8: 687b ldr r3, [r7, #4]
8001daa: 6a1b ldr r3, [r3, #32]
8001dac: 2201 movs r2, #1
8001dae: 4393 bics r3, r2
8001db0: 001a movs r2, r3
8001db2: 687b ldr r3, [r7, #4]
8001db4: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001db6: 687b ldr r3, [r7, #4]
8001db8: 685b ldr r3, [r3, #4]
8001dba: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001dbc: 687b ldr r3, [r7, #4]
8001dbe: 699b ldr r3, [r3, #24]
8001dc0: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8001dc2: 68fb ldr r3, [r7, #12]
8001dc4: 4a2e ldr r2, [pc, #184] @ (8001e80 <TIM_OC1_SetConfig+0xe8>)
8001dc6: 4013 ands r3, r2
8001dc8: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8001dca: 68fb ldr r3, [r7, #12]
8001dcc: 2203 movs r2, #3
8001dce: 4393 bics r3, r2
8001dd0: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001dd2: 683b ldr r3, [r7, #0]
8001dd4: 681b ldr r3, [r3, #0]
8001dd6: 68fa ldr r2, [r7, #12]
8001dd8: 4313 orrs r3, r2
8001dda: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8001ddc: 697b ldr r3, [r7, #20]
8001dde: 2202 movs r2, #2
8001de0: 4393 bics r3, r2
8001de2: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8001de4: 683b ldr r3, [r7, #0]
8001de6: 689b ldr r3, [r3, #8]
8001de8: 697a ldr r2, [r7, #20]
8001dea: 4313 orrs r3, r2
8001dec: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8001dee: 687b ldr r3, [r7, #4]
8001df0: 4a24 ldr r2, [pc, #144] @ (8001e84 <TIM_OC1_SetConfig+0xec>)
8001df2: 4293 cmp r3, r2
8001df4: d007 beq.n 8001e06 <TIM_OC1_SetConfig+0x6e>
8001df6: 687b ldr r3, [r7, #4]
8001df8: 4a23 ldr r2, [pc, #140] @ (8001e88 <TIM_OC1_SetConfig+0xf0>)
8001dfa: 4293 cmp r3, r2
8001dfc: d003 beq.n 8001e06 <TIM_OC1_SetConfig+0x6e>
8001dfe: 687b ldr r3, [r7, #4]
8001e00: 4a22 ldr r2, [pc, #136] @ (8001e8c <TIM_OC1_SetConfig+0xf4>)
8001e02: 4293 cmp r3, r2
8001e04: d10c bne.n 8001e20 <TIM_OC1_SetConfig+0x88>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8001e06: 697b ldr r3, [r7, #20]
8001e08: 2208 movs r2, #8
8001e0a: 4393 bics r3, r2
8001e0c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8001e0e: 683b ldr r3, [r7, #0]
8001e10: 68db ldr r3, [r3, #12]
8001e12: 697a ldr r2, [r7, #20]
8001e14: 4313 orrs r3, r2
8001e16: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8001e18: 697b ldr r3, [r7, #20]
8001e1a: 2204 movs r2, #4
8001e1c: 4393 bics r3, r2
8001e1e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001e20: 687b ldr r3, [r7, #4]
8001e22: 4a18 ldr r2, [pc, #96] @ (8001e84 <TIM_OC1_SetConfig+0xec>)
8001e24: 4293 cmp r3, r2
8001e26: d007 beq.n 8001e38 <TIM_OC1_SetConfig+0xa0>
8001e28: 687b ldr r3, [r7, #4]
8001e2a: 4a17 ldr r2, [pc, #92] @ (8001e88 <TIM_OC1_SetConfig+0xf0>)
8001e2c: 4293 cmp r3, r2
8001e2e: d003 beq.n 8001e38 <TIM_OC1_SetConfig+0xa0>
8001e30: 687b ldr r3, [r7, #4]
8001e32: 4a16 ldr r2, [pc, #88] @ (8001e8c <TIM_OC1_SetConfig+0xf4>)
8001e34: 4293 cmp r3, r2
8001e36: d111 bne.n 8001e5c <TIM_OC1_SetConfig+0xc4>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8001e38: 693b ldr r3, [r7, #16]
8001e3a: 4a15 ldr r2, [pc, #84] @ (8001e90 <TIM_OC1_SetConfig+0xf8>)
8001e3c: 4013 ands r3, r2
8001e3e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8001e40: 693b ldr r3, [r7, #16]
8001e42: 4a14 ldr r2, [pc, #80] @ (8001e94 <TIM_OC1_SetConfig+0xfc>)
8001e44: 4013 ands r3, r2
8001e46: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8001e48: 683b ldr r3, [r7, #0]
8001e4a: 695b ldr r3, [r3, #20]
8001e4c: 693a ldr r2, [r7, #16]
8001e4e: 4313 orrs r3, r2
8001e50: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8001e52: 683b ldr r3, [r7, #0]
8001e54: 699b ldr r3, [r3, #24]
8001e56: 693a ldr r2, [r7, #16]
8001e58: 4313 orrs r3, r2
8001e5a: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001e5c: 687b ldr r3, [r7, #4]
8001e5e: 693a ldr r2, [r7, #16]
8001e60: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001e62: 687b ldr r3, [r7, #4]
8001e64: 68fa ldr r2, [r7, #12]
8001e66: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8001e68: 683b ldr r3, [r7, #0]
8001e6a: 685a ldr r2, [r3, #4]
8001e6c: 687b ldr r3, [r7, #4]
8001e6e: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001e70: 687b ldr r3, [r7, #4]
8001e72: 697a ldr r2, [r7, #20]
8001e74: 621a str r2, [r3, #32]
}
8001e76: 46c0 nop @ (mov r8, r8)
8001e78: 46bd mov sp, r7
8001e7a: b006 add sp, #24
8001e7c: bd80 pop {r7, pc}
8001e7e: 46c0 nop @ (mov r8, r8)
8001e80: fffeff8f .word 0xfffeff8f
8001e84: 40012c00 .word 0x40012c00
8001e88: 40014400 .word 0x40014400
8001e8c: 40014800 .word 0x40014800
8001e90: fffffeff .word 0xfffffeff
8001e94: fffffdff .word 0xfffffdff
08001e98 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001e98: b580 push {r7, lr}
8001e9a: b086 sub sp, #24
8001e9c: af00 add r7, sp, #0
8001e9e: 6078 str r0, [r7, #4]
8001ea0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 6a1b ldr r3, [r3, #32]
8001ea6: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8001ea8: 687b ldr r3, [r7, #4]
8001eaa: 6a1b ldr r3, [r3, #32]
8001eac: 2210 movs r2, #16
8001eae: 4393 bics r3, r2
8001eb0: 001a movs r2, r3
8001eb2: 687b ldr r3, [r7, #4]
8001eb4: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001eb6: 687b ldr r3, [r7, #4]
8001eb8: 685b ldr r3, [r3, #4]
8001eba: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001ebc: 687b ldr r3, [r7, #4]
8001ebe: 699b ldr r3, [r3, #24]
8001ec0: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8001ec2: 68fb ldr r3, [r7, #12]
8001ec4: 4a2c ldr r2, [pc, #176] @ (8001f78 <TIM_OC2_SetConfig+0xe0>)
8001ec6: 4013 ands r3, r2
8001ec8: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8001eca: 68fb ldr r3, [r7, #12]
8001ecc: 4a2b ldr r2, [pc, #172] @ (8001f7c <TIM_OC2_SetConfig+0xe4>)
8001ece: 4013 ands r3, r2
8001ed0: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001ed2: 683b ldr r3, [r7, #0]
8001ed4: 681b ldr r3, [r3, #0]
8001ed6: 021b lsls r3, r3, #8
8001ed8: 68fa ldr r2, [r7, #12]
8001eda: 4313 orrs r3, r2
8001edc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8001ede: 697b ldr r3, [r7, #20]
8001ee0: 2220 movs r2, #32
8001ee2: 4393 bics r3, r2
8001ee4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8001ee6: 683b ldr r3, [r7, #0]
8001ee8: 689b ldr r3, [r3, #8]
8001eea: 011b lsls r3, r3, #4
8001eec: 697a ldr r2, [r7, #20]
8001eee: 4313 orrs r3, r2
8001ef0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8001ef2: 687b ldr r3, [r7, #4]
8001ef4: 4a22 ldr r2, [pc, #136] @ (8001f80 <TIM_OC2_SetConfig+0xe8>)
8001ef6: 4293 cmp r3, r2
8001ef8: d10d bne.n 8001f16 <TIM_OC2_SetConfig+0x7e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8001efa: 697b ldr r3, [r7, #20]
8001efc: 2280 movs r2, #128 @ 0x80
8001efe: 4393 bics r3, r2
8001f00: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8001f02: 683b ldr r3, [r7, #0]
8001f04: 68db ldr r3, [r3, #12]
8001f06: 011b lsls r3, r3, #4
8001f08: 697a ldr r2, [r7, #20]
8001f0a: 4313 orrs r3, r2
8001f0c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8001f0e: 697b ldr r3, [r7, #20]
8001f10: 2240 movs r2, #64 @ 0x40
8001f12: 4393 bics r3, r2
8001f14: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001f16: 687b ldr r3, [r7, #4]
8001f18: 4a19 ldr r2, [pc, #100] @ (8001f80 <TIM_OC2_SetConfig+0xe8>)
8001f1a: 4293 cmp r3, r2
8001f1c: d007 beq.n 8001f2e <TIM_OC2_SetConfig+0x96>
8001f1e: 687b ldr r3, [r7, #4]
8001f20: 4a18 ldr r2, [pc, #96] @ (8001f84 <TIM_OC2_SetConfig+0xec>)
8001f22: 4293 cmp r3, r2
8001f24: d003 beq.n 8001f2e <TIM_OC2_SetConfig+0x96>
8001f26: 687b ldr r3, [r7, #4]
8001f28: 4a17 ldr r2, [pc, #92] @ (8001f88 <TIM_OC2_SetConfig+0xf0>)
8001f2a: 4293 cmp r3, r2
8001f2c: d113 bne.n 8001f56 <TIM_OC2_SetConfig+0xbe>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8001f2e: 693b ldr r3, [r7, #16]
8001f30: 4a16 ldr r2, [pc, #88] @ (8001f8c <TIM_OC2_SetConfig+0xf4>)
8001f32: 4013 ands r3, r2
8001f34: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8001f36: 693b ldr r3, [r7, #16]
8001f38: 4a15 ldr r2, [pc, #84] @ (8001f90 <TIM_OC2_SetConfig+0xf8>)
8001f3a: 4013 ands r3, r2
8001f3c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8001f3e: 683b ldr r3, [r7, #0]
8001f40: 695b ldr r3, [r3, #20]
8001f42: 009b lsls r3, r3, #2
8001f44: 693a ldr r2, [r7, #16]
8001f46: 4313 orrs r3, r2
8001f48: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8001f4a: 683b ldr r3, [r7, #0]
8001f4c: 699b ldr r3, [r3, #24]
8001f4e: 009b lsls r3, r3, #2
8001f50: 693a ldr r2, [r7, #16]
8001f52: 4313 orrs r3, r2
8001f54: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001f56: 687b ldr r3, [r7, #4]
8001f58: 693a ldr r2, [r7, #16]
8001f5a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001f5c: 687b ldr r3, [r7, #4]
8001f5e: 68fa ldr r2, [r7, #12]
8001f60: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8001f62: 683b ldr r3, [r7, #0]
8001f64: 685a ldr r2, [r3, #4]
8001f66: 687b ldr r3, [r7, #4]
8001f68: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 697a ldr r2, [r7, #20]
8001f6e: 621a str r2, [r3, #32]
}
8001f70: 46c0 nop @ (mov r8, r8)
8001f72: 46bd mov sp, r7
8001f74: b006 add sp, #24
8001f76: bd80 pop {r7, pc}
8001f78: feff8fff .word 0xfeff8fff
8001f7c: fffffcff .word 0xfffffcff
8001f80: 40012c00 .word 0x40012c00
8001f84: 40014400 .word 0x40014400
8001f88: 40014800 .word 0x40014800
8001f8c: fffffbff .word 0xfffffbff
8001f90: fffff7ff .word 0xfffff7ff
08001f94 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001f94: b580 push {r7, lr}
8001f96: b086 sub sp, #24
8001f98: af00 add r7, sp, #0
8001f9a: 6078 str r0, [r7, #4]
8001f9c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001f9e: 687b ldr r3, [r7, #4]
8001fa0: 6a1b ldr r3, [r3, #32]
8001fa2: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 6a1b ldr r3, [r3, #32]
8001fa8: 4a31 ldr r2, [pc, #196] @ (8002070 <TIM_OC3_SetConfig+0xdc>)
8001faa: 401a ands r2, r3
8001fac: 687b ldr r3, [r7, #4]
8001fae: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 685b ldr r3, [r3, #4]
8001fb4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001fb6: 687b ldr r3, [r7, #4]
8001fb8: 69db ldr r3, [r3, #28]
8001fba: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8001fbc: 68fb ldr r3, [r7, #12]
8001fbe: 4a2d ldr r2, [pc, #180] @ (8002074 <TIM_OC3_SetConfig+0xe0>)
8001fc0: 4013 ands r3, r2
8001fc2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8001fc4: 68fb ldr r3, [r7, #12]
8001fc6: 2203 movs r2, #3
8001fc8: 4393 bics r3, r2
8001fca: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001fcc: 683b ldr r3, [r7, #0]
8001fce: 681b ldr r3, [r3, #0]
8001fd0: 68fa ldr r2, [r7, #12]
8001fd2: 4313 orrs r3, r2
8001fd4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8001fd6: 697b ldr r3, [r7, #20]
8001fd8: 4a27 ldr r2, [pc, #156] @ (8002078 <TIM_OC3_SetConfig+0xe4>)
8001fda: 4013 ands r3, r2
8001fdc: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8001fde: 683b ldr r3, [r7, #0]
8001fe0: 689b ldr r3, [r3, #8]
8001fe2: 021b lsls r3, r3, #8
8001fe4: 697a ldr r2, [r7, #20]
8001fe6: 4313 orrs r3, r2
8001fe8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8001fea: 687b ldr r3, [r7, #4]
8001fec: 4a23 ldr r2, [pc, #140] @ (800207c <TIM_OC3_SetConfig+0xe8>)
8001fee: 4293 cmp r3, r2
8001ff0: d10d bne.n 800200e <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8001ff2: 697b ldr r3, [r7, #20]
8001ff4: 4a22 ldr r2, [pc, #136] @ (8002080 <TIM_OC3_SetConfig+0xec>)
8001ff6: 4013 ands r3, r2
8001ff8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8001ffa: 683b ldr r3, [r7, #0]
8001ffc: 68db ldr r3, [r3, #12]
8001ffe: 021b lsls r3, r3, #8
8002000: 697a ldr r2, [r7, #20]
8002002: 4313 orrs r3, r2
8002004: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8002006: 697b ldr r3, [r7, #20]
8002008: 4a1e ldr r2, [pc, #120] @ (8002084 <TIM_OC3_SetConfig+0xf0>)
800200a: 4013 ands r3, r2
800200c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800200e: 687b ldr r3, [r7, #4]
8002010: 4a1a ldr r2, [pc, #104] @ (800207c <TIM_OC3_SetConfig+0xe8>)
8002012: 4293 cmp r3, r2
8002014: d007 beq.n 8002026 <TIM_OC3_SetConfig+0x92>
8002016: 687b ldr r3, [r7, #4]
8002018: 4a1b ldr r2, [pc, #108] @ (8002088 <TIM_OC3_SetConfig+0xf4>)
800201a: 4293 cmp r3, r2
800201c: d003 beq.n 8002026 <TIM_OC3_SetConfig+0x92>
800201e: 687b ldr r3, [r7, #4]
8002020: 4a1a ldr r2, [pc, #104] @ (800208c <TIM_OC3_SetConfig+0xf8>)
8002022: 4293 cmp r3, r2
8002024: d113 bne.n 800204e <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8002026: 693b ldr r3, [r7, #16]
8002028: 4a19 ldr r2, [pc, #100] @ (8002090 <TIM_OC3_SetConfig+0xfc>)
800202a: 4013 ands r3, r2
800202c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800202e: 693b ldr r3, [r7, #16]
8002030: 4a18 ldr r2, [pc, #96] @ (8002094 <TIM_OC3_SetConfig+0x100>)
8002032: 4013 ands r3, r2
8002034: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8002036: 683b ldr r3, [r7, #0]
8002038: 695b ldr r3, [r3, #20]
800203a: 011b lsls r3, r3, #4
800203c: 693a ldr r2, [r7, #16]
800203e: 4313 orrs r3, r2
8002040: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8002042: 683b ldr r3, [r7, #0]
8002044: 699b ldr r3, [r3, #24]
8002046: 011b lsls r3, r3, #4
8002048: 693a ldr r2, [r7, #16]
800204a: 4313 orrs r3, r2
800204c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800204e: 687b ldr r3, [r7, #4]
8002050: 693a ldr r2, [r7, #16]
8002052: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002054: 687b ldr r3, [r7, #4]
8002056: 68fa ldr r2, [r7, #12]
8002058: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800205a: 683b ldr r3, [r7, #0]
800205c: 685a ldr r2, [r3, #4]
800205e: 687b ldr r3, [r7, #4]
8002060: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002062: 687b ldr r3, [r7, #4]
8002064: 697a ldr r2, [r7, #20]
8002066: 621a str r2, [r3, #32]
}
8002068: 46c0 nop @ (mov r8, r8)
800206a: 46bd mov sp, r7
800206c: b006 add sp, #24
800206e: bd80 pop {r7, pc}
8002070: fffffeff .word 0xfffffeff
8002074: fffeff8f .word 0xfffeff8f
8002078: fffffdff .word 0xfffffdff
800207c: 40012c00 .word 0x40012c00
8002080: fffff7ff .word 0xfffff7ff
8002084: fffffbff .word 0xfffffbff
8002088: 40014400 .word 0x40014400
800208c: 40014800 .word 0x40014800
8002090: ffffefff .word 0xffffefff
8002094: ffffdfff .word 0xffffdfff
08002098 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8002098: b580 push {r7, lr}
800209a: b086 sub sp, #24
800209c: af00 add r7, sp, #0
800209e: 6078 str r0, [r7, #4]
80020a0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80020a2: 687b ldr r3, [r7, #4]
80020a4: 6a1b ldr r3, [r3, #32]
80020a6: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
80020a8: 687b ldr r3, [r7, #4]
80020aa: 6a1b ldr r3, [r3, #32]
80020ac: 4a24 ldr r2, [pc, #144] @ (8002140 <TIM_OC4_SetConfig+0xa8>)
80020ae: 401a ands r2, r3
80020b0: 687b ldr r3, [r7, #4]
80020b2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80020b4: 687b ldr r3, [r7, #4]
80020b6: 685b ldr r3, [r3, #4]
80020b8: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80020ba: 687b ldr r3, [r7, #4]
80020bc: 69db ldr r3, [r3, #28]
80020be: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
80020c0: 68fb ldr r3, [r7, #12]
80020c2: 4a20 ldr r2, [pc, #128] @ (8002144 <TIM_OC4_SetConfig+0xac>)
80020c4: 4013 ands r3, r2
80020c6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80020c8: 68fb ldr r3, [r7, #12]
80020ca: 4a1f ldr r2, [pc, #124] @ (8002148 <TIM_OC4_SetConfig+0xb0>)
80020cc: 4013 ands r3, r2
80020ce: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80020d0: 683b ldr r3, [r7, #0]
80020d2: 681b ldr r3, [r3, #0]
80020d4: 021b lsls r3, r3, #8
80020d6: 68fa ldr r2, [r7, #12]
80020d8: 4313 orrs r3, r2
80020da: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80020dc: 693b ldr r3, [r7, #16]
80020de: 4a1b ldr r2, [pc, #108] @ (800214c <TIM_OC4_SetConfig+0xb4>)
80020e0: 4013 ands r3, r2
80020e2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80020e4: 683b ldr r3, [r7, #0]
80020e6: 689b ldr r3, [r3, #8]
80020e8: 031b lsls r3, r3, #12
80020ea: 693a ldr r2, [r7, #16]
80020ec: 4313 orrs r3, r2
80020ee: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80020f0: 687b ldr r3, [r7, #4]
80020f2: 4a17 ldr r2, [pc, #92] @ (8002150 <TIM_OC4_SetConfig+0xb8>)
80020f4: 4293 cmp r3, r2
80020f6: d007 beq.n 8002108 <TIM_OC4_SetConfig+0x70>
80020f8: 687b ldr r3, [r7, #4]
80020fa: 4a16 ldr r2, [pc, #88] @ (8002154 <TIM_OC4_SetConfig+0xbc>)
80020fc: 4293 cmp r3, r2
80020fe: d003 beq.n 8002108 <TIM_OC4_SetConfig+0x70>
8002100: 687b ldr r3, [r7, #4]
8002102: 4a15 ldr r2, [pc, #84] @ (8002158 <TIM_OC4_SetConfig+0xc0>)
8002104: 4293 cmp r3, r2
8002106: d109 bne.n 800211c <TIM_OC4_SetConfig+0x84>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8002108: 697b ldr r3, [r7, #20]
800210a: 4a14 ldr r2, [pc, #80] @ (800215c <TIM_OC4_SetConfig+0xc4>)
800210c: 4013 ands r3, r2
800210e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8002110: 683b ldr r3, [r7, #0]
8002112: 695b ldr r3, [r3, #20]
8002114: 019b lsls r3, r3, #6
8002116: 697a ldr r2, [r7, #20]
8002118: 4313 orrs r3, r2
800211a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800211c: 687b ldr r3, [r7, #4]
800211e: 697a ldr r2, [r7, #20]
8002120: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002122: 687b ldr r3, [r7, #4]
8002124: 68fa ldr r2, [r7, #12]
8002126: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8002128: 683b ldr r3, [r7, #0]
800212a: 685a ldr r2, [r3, #4]
800212c: 687b ldr r3, [r7, #4]
800212e: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002130: 687b ldr r3, [r7, #4]
8002132: 693a ldr r2, [r7, #16]
8002134: 621a str r2, [r3, #32]
}
8002136: 46c0 nop @ (mov r8, r8)
8002138: 46bd mov sp, r7
800213a: b006 add sp, #24
800213c: bd80 pop {r7, pc}
800213e: 46c0 nop @ (mov r8, r8)
8002140: ffffefff .word 0xffffefff
8002144: feff8fff .word 0xfeff8fff
8002148: fffffcff .word 0xfffffcff
800214c: ffffdfff .word 0xffffdfff
8002150: 40012c00 .word 0x40012c00
8002154: 40014400 .word 0x40014400
8002158: 40014800 .word 0x40014800
800215c: ffffbfff .word 0xffffbfff
08002160 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8002160: b580 push {r7, lr}
8002162: b086 sub sp, #24
8002164: af00 add r7, sp, #0
8002166: 6078 str r0, [r7, #4]
8002168: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800216a: 687b ldr r3, [r7, #4]
800216c: 6a1b ldr r3, [r3, #32]
800216e: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8002170: 687b ldr r3, [r7, #4]
8002172: 6a1b ldr r3, [r3, #32]
8002174: 4a21 ldr r2, [pc, #132] @ (80021fc <TIM_OC5_SetConfig+0x9c>)
8002176: 401a ands r2, r3
8002178: 687b ldr r3, [r7, #4]
800217a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800217c: 687b ldr r3, [r7, #4]
800217e: 685b ldr r3, [r3, #4]
8002180: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8002182: 687b ldr r3, [r7, #4]
8002184: 6d5b ldr r3, [r3, #84] @ 0x54
8002186: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8002188: 68fb ldr r3, [r7, #12]
800218a: 4a1d ldr r2, [pc, #116] @ (8002200 <TIM_OC5_SetConfig+0xa0>)
800218c: 4013 ands r3, r2
800218e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002190: 683b ldr r3, [r7, #0]
8002192: 681b ldr r3, [r3, #0]
8002194: 68fa ldr r2, [r7, #12]
8002196: 4313 orrs r3, r2
8002198: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800219a: 693b ldr r3, [r7, #16]
800219c: 4a19 ldr r2, [pc, #100] @ (8002204 <TIM_OC5_SetConfig+0xa4>)
800219e: 4013 ands r3, r2
80021a0: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
80021a2: 683b ldr r3, [r7, #0]
80021a4: 689b ldr r3, [r3, #8]
80021a6: 041b lsls r3, r3, #16
80021a8: 693a ldr r2, [r7, #16]
80021aa: 4313 orrs r3, r2
80021ac: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80021ae: 687b ldr r3, [r7, #4]
80021b0: 4a15 ldr r2, [pc, #84] @ (8002208 <TIM_OC5_SetConfig+0xa8>)
80021b2: 4293 cmp r3, r2
80021b4: d007 beq.n 80021c6 <TIM_OC5_SetConfig+0x66>
80021b6: 687b ldr r3, [r7, #4]
80021b8: 4a14 ldr r2, [pc, #80] @ (800220c <TIM_OC5_SetConfig+0xac>)
80021ba: 4293 cmp r3, r2
80021bc: d003 beq.n 80021c6 <TIM_OC5_SetConfig+0x66>
80021be: 687b ldr r3, [r7, #4]
80021c0: 4a13 ldr r2, [pc, #76] @ (8002210 <TIM_OC5_SetConfig+0xb0>)
80021c2: 4293 cmp r3, r2
80021c4: d109 bne.n 80021da <TIM_OC5_SetConfig+0x7a>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
80021c6: 697b ldr r3, [r7, #20]
80021c8: 4a0c ldr r2, [pc, #48] @ (80021fc <TIM_OC5_SetConfig+0x9c>)
80021ca: 4013 ands r3, r2
80021cc: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
80021ce: 683b ldr r3, [r7, #0]
80021d0: 695b ldr r3, [r3, #20]
80021d2: 021b lsls r3, r3, #8
80021d4: 697a ldr r2, [r7, #20]
80021d6: 4313 orrs r3, r2
80021d8: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80021da: 687b ldr r3, [r7, #4]
80021dc: 697a ldr r2, [r7, #20]
80021de: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
80021e0: 687b ldr r3, [r7, #4]
80021e2: 68fa ldr r2, [r7, #12]
80021e4: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
80021e6: 683b ldr r3, [r7, #0]
80021e8: 685a ldr r2, [r3, #4]
80021ea: 687b ldr r3, [r7, #4]
80021ec: 659a str r2, [r3, #88] @ 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80021ee: 687b ldr r3, [r7, #4]
80021f0: 693a ldr r2, [r7, #16]
80021f2: 621a str r2, [r3, #32]
}
80021f4: 46c0 nop @ (mov r8, r8)
80021f6: 46bd mov sp, r7
80021f8: b006 add sp, #24
80021fa: bd80 pop {r7, pc}
80021fc: fffeffff .word 0xfffeffff
8002200: fffeff8f .word 0xfffeff8f
8002204: fffdffff .word 0xfffdffff
8002208: 40012c00 .word 0x40012c00
800220c: 40014400 .word 0x40014400
8002210: 40014800 .word 0x40014800
08002214 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8002214: b580 push {r7, lr}
8002216: b086 sub sp, #24
8002218: af00 add r7, sp, #0
800221a: 6078 str r0, [r7, #4]
800221c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800221e: 687b ldr r3, [r7, #4]
8002220: 6a1b ldr r3, [r3, #32]
8002222: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8002224: 687b ldr r3, [r7, #4]
8002226: 6a1b ldr r3, [r3, #32]
8002228: 4a22 ldr r2, [pc, #136] @ (80022b4 <TIM_OC6_SetConfig+0xa0>)
800222a: 401a ands r2, r3
800222c: 687b ldr r3, [r7, #4]
800222e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002230: 687b ldr r3, [r7, #4]
8002232: 685b ldr r3, [r3, #4]
8002234: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8002236: 687b ldr r3, [r7, #4]
8002238: 6d5b ldr r3, [r3, #84] @ 0x54
800223a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
800223c: 68fb ldr r3, [r7, #12]
800223e: 4a1e ldr r2, [pc, #120] @ (80022b8 <TIM_OC6_SetConfig+0xa4>)
8002240: 4013 ands r3, r2
8002242: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002244: 683b ldr r3, [r7, #0]
8002246: 681b ldr r3, [r3, #0]
8002248: 021b lsls r3, r3, #8
800224a: 68fa ldr r2, [r7, #12]
800224c: 4313 orrs r3, r2
800224e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8002250: 693b ldr r3, [r7, #16]
8002252: 4a1a ldr r2, [pc, #104] @ (80022bc <TIM_OC6_SetConfig+0xa8>)
8002254: 4013 ands r3, r2
8002256: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8002258: 683b ldr r3, [r7, #0]
800225a: 689b ldr r3, [r3, #8]
800225c: 051b lsls r3, r3, #20
800225e: 693a ldr r2, [r7, #16]
8002260: 4313 orrs r3, r2
8002262: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8002264: 687b ldr r3, [r7, #4]
8002266: 4a16 ldr r2, [pc, #88] @ (80022c0 <TIM_OC6_SetConfig+0xac>)
8002268: 4293 cmp r3, r2
800226a: d007 beq.n 800227c <TIM_OC6_SetConfig+0x68>
800226c: 687b ldr r3, [r7, #4]
800226e: 4a15 ldr r2, [pc, #84] @ (80022c4 <TIM_OC6_SetConfig+0xb0>)
8002270: 4293 cmp r3, r2
8002272: d003 beq.n 800227c <TIM_OC6_SetConfig+0x68>
8002274: 687b ldr r3, [r7, #4]
8002276: 4a14 ldr r2, [pc, #80] @ (80022c8 <TIM_OC6_SetConfig+0xb4>)
8002278: 4293 cmp r3, r2
800227a: d109 bne.n 8002290 <TIM_OC6_SetConfig+0x7c>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
800227c: 697b ldr r3, [r7, #20]
800227e: 4a13 ldr r2, [pc, #76] @ (80022cc <TIM_OC6_SetConfig+0xb8>)
8002280: 4013 ands r3, r2
8002282: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8002284: 683b ldr r3, [r7, #0]
8002286: 695b ldr r3, [r3, #20]
8002288: 029b lsls r3, r3, #10
800228a: 697a ldr r2, [r7, #20]
800228c: 4313 orrs r3, r2
800228e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002290: 687b ldr r3, [r7, #4]
8002292: 697a ldr r2, [r7, #20]
8002294: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8002296: 687b ldr r3, [r7, #4]
8002298: 68fa ldr r2, [r7, #12]
800229a: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
800229c: 683b ldr r3, [r7, #0]
800229e: 685a ldr r2, [r3, #4]
80022a0: 687b ldr r3, [r7, #4]
80022a2: 65da str r2, [r3, #92] @ 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80022a4: 687b ldr r3, [r7, #4]
80022a6: 693a ldr r2, [r7, #16]
80022a8: 621a str r2, [r3, #32]
}
80022aa: 46c0 nop @ (mov r8, r8)
80022ac: 46bd mov sp, r7
80022ae: b006 add sp, #24
80022b0: bd80 pop {r7, pc}
80022b2: 46c0 nop @ (mov r8, r8)
80022b4: ffefffff .word 0xffefffff
80022b8: feff8fff .word 0xfeff8fff
80022bc: ffdfffff .word 0xffdfffff
80022c0: 40012c00 .word 0x40012c00
80022c4: 40014400 .word 0x40014400
80022c8: 40014800 .word 0x40014800
80022cc: fffbffff .word 0xfffbffff
080022d0 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80022d0: b580 push {r7, lr}
80022d2: b086 sub sp, #24
80022d4: af00 add r7, sp, #0
80022d6: 60f8 str r0, [r7, #12]
80022d8: 60b9 str r1, [r7, #8]
80022da: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
80022dc: 68fb ldr r3, [r7, #12]
80022de: 6a1b ldr r3, [r3, #32]
80022e0: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
80022e2: 68fb ldr r3, [r7, #12]
80022e4: 6a1b ldr r3, [r3, #32]
80022e6: 2201 movs r2, #1
80022e8: 4393 bics r3, r2
80022ea: 001a movs r2, r3
80022ec: 68fb ldr r3, [r7, #12]
80022ee: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80022f0: 68fb ldr r3, [r7, #12]
80022f2: 699b ldr r3, [r3, #24]
80022f4: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
80022f6: 693b ldr r3, [r7, #16]
80022f8: 22f0 movs r2, #240 @ 0xf0
80022fa: 4393 bics r3, r2
80022fc: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
80022fe: 687b ldr r3, [r7, #4]
8002300: 011b lsls r3, r3, #4
8002302: 693a ldr r2, [r7, #16]
8002304: 4313 orrs r3, r2
8002306: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8002308: 697b ldr r3, [r7, #20]
800230a: 220a movs r2, #10
800230c: 4393 bics r3, r2
800230e: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8002310: 697a ldr r2, [r7, #20]
8002312: 68bb ldr r3, [r7, #8]
8002314: 4313 orrs r3, r2
8002316: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8002318: 68fb ldr r3, [r7, #12]
800231a: 693a ldr r2, [r7, #16]
800231c: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800231e: 68fb ldr r3, [r7, #12]
8002320: 697a ldr r2, [r7, #20]
8002322: 621a str r2, [r3, #32]
}
8002324: 46c0 nop @ (mov r8, r8)
8002326: 46bd mov sp, r7
8002328: b006 add sp, #24
800232a: bd80 pop {r7, pc}
0800232c <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800232c: b580 push {r7, lr}
800232e: b086 sub sp, #24
8002330: af00 add r7, sp, #0
8002332: 60f8 str r0, [r7, #12]
8002334: 60b9 str r1, [r7, #8]
8002336: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8002338: 68fb ldr r3, [r7, #12]
800233a: 6a1b ldr r3, [r3, #32]
800233c: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
800233e: 68fb ldr r3, [r7, #12]
8002340: 6a1b ldr r3, [r3, #32]
8002342: 2210 movs r2, #16
8002344: 4393 bics r3, r2
8002346: 001a movs r2, r3
8002348: 68fb ldr r3, [r7, #12]
800234a: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800234c: 68fb ldr r3, [r7, #12]
800234e: 699b ldr r3, [r3, #24]
8002350: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8002352: 693b ldr r3, [r7, #16]
8002354: 4a0d ldr r2, [pc, #52] @ (800238c <TIM_TI2_ConfigInputStage+0x60>)
8002356: 4013 ands r3, r2
8002358: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
800235a: 687b ldr r3, [r7, #4]
800235c: 031b lsls r3, r3, #12
800235e: 693a ldr r2, [r7, #16]
8002360: 4313 orrs r3, r2
8002362: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8002364: 697b ldr r3, [r7, #20]
8002366: 22a0 movs r2, #160 @ 0xa0
8002368: 4393 bics r3, r2
800236a: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
800236c: 68bb ldr r3, [r7, #8]
800236e: 011b lsls r3, r3, #4
8002370: 697a ldr r2, [r7, #20]
8002372: 4313 orrs r3, r2
8002374: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8002376: 68fb ldr r3, [r7, #12]
8002378: 693a ldr r2, [r7, #16]
800237a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800237c: 68fb ldr r3, [r7, #12]
800237e: 697a ldr r2, [r7, #20]
8002380: 621a str r2, [r3, #32]
}
8002382: 46c0 nop @ (mov r8, r8)
8002384: 46bd mov sp, r7
8002386: b006 add sp, #24
8002388: bd80 pop {r7, pc}
800238a: 46c0 nop @ (mov r8, r8)
800238c: ffff0fff .word 0xffff0fff
08002390 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8002390: b580 push {r7, lr}
8002392: b084 sub sp, #16
8002394: af00 add r7, sp, #0
8002396: 6078 str r0, [r7, #4]
8002398: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800239a: 687b ldr r3, [r7, #4]
800239c: 689b ldr r3, [r3, #8]
800239e: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80023a0: 68fb ldr r3, [r7, #12]
80023a2: 4a08 ldr r2, [pc, #32] @ (80023c4 <TIM_ITRx_SetConfig+0x34>)
80023a4: 4013 ands r3, r2
80023a6: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80023a8: 683a ldr r2, [r7, #0]
80023aa: 68fb ldr r3, [r7, #12]
80023ac: 4313 orrs r3, r2
80023ae: 2207 movs r2, #7
80023b0: 4313 orrs r3, r2
80023b2: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80023b4: 687b ldr r3, [r7, #4]
80023b6: 68fa ldr r2, [r7, #12]
80023b8: 609a str r2, [r3, #8]
}
80023ba: 46c0 nop @ (mov r8, r8)
80023bc: 46bd mov sp, r7
80023be: b004 add sp, #16
80023c0: bd80 pop {r7, pc}
80023c2: 46c0 nop @ (mov r8, r8)
80023c4: ffcfff8f .word 0xffcfff8f
080023c8 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
80023c8: b580 push {r7, lr}
80023ca: b086 sub sp, #24
80023cc: af00 add r7, sp, #0
80023ce: 60f8 str r0, [r7, #12]
80023d0: 60b9 str r1, [r7, #8]
80023d2: 607a str r2, [r7, #4]
80023d4: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
80023d6: 68fb ldr r3, [r7, #12]
80023d8: 689b ldr r3, [r3, #8]
80023da: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80023dc: 697b ldr r3, [r7, #20]
80023de: 4a09 ldr r2, [pc, #36] @ (8002404 <TIM_ETR_SetConfig+0x3c>)
80023e0: 4013 ands r3, r2
80023e2: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
80023e4: 683b ldr r3, [r7, #0]
80023e6: 021a lsls r2, r3, #8
80023e8: 687b ldr r3, [r7, #4]
80023ea: 431a orrs r2, r3
80023ec: 68bb ldr r3, [r7, #8]
80023ee: 4313 orrs r3, r2
80023f0: 697a ldr r2, [r7, #20]
80023f2: 4313 orrs r3, r2
80023f4: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80023f6: 68fb ldr r3, [r7, #12]
80023f8: 697a ldr r2, [r7, #20]
80023fa: 609a str r2, [r3, #8]
}
80023fc: 46c0 nop @ (mov r8, r8)
80023fe: 46bd mov sp, r7
8002400: b006 add sp, #24
8002402: bd80 pop {r7, pc}
8002404: ffff00ff .word 0xffff00ff
08002408 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8002408: b580 push {r7, lr}
800240a: b084 sub sp, #16
800240c: af00 add r7, sp, #0
800240e: 6078 str r0, [r7, #4]
8002410: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8002412: 687b ldr r3, [r7, #4]
8002414: 223c movs r2, #60 @ 0x3c
8002416: 5c9b ldrb r3, [r3, r2]
8002418: 2b01 cmp r3, #1
800241a: d101 bne.n 8002420 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800241c: 2302 movs r3, #2
800241e: e04a b.n 80024b6 <HAL_TIMEx_MasterConfigSynchronization+0xae>
8002420: 687b ldr r3, [r7, #4]
8002422: 223c movs r2, #60 @ 0x3c
8002424: 2101 movs r1, #1
8002426: 5499 strb r1, [r3, r2]
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8002428: 687b ldr r3, [r7, #4]
800242a: 223d movs r2, #61 @ 0x3d
800242c: 2102 movs r1, #2
800242e: 5499 strb r1, [r3, r2]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8002430: 687b ldr r3, [r7, #4]
8002432: 681b ldr r3, [r3, #0]
8002434: 685b ldr r3, [r3, #4]
8002436: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8002438: 687b ldr r3, [r7, #4]
800243a: 681b ldr r3, [r3, #0]
800243c: 689b ldr r3, [r3, #8]
800243e: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8002440: 687b ldr r3, [r7, #4]
8002442: 681b ldr r3, [r3, #0]
8002444: 4a1e ldr r2, [pc, #120] @ (80024c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8002446: 4293 cmp r3, r2
8002448: d108 bne.n 800245c <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
800244a: 68fb ldr r3, [r7, #12]
800244c: 4a1d ldr r2, [pc, #116] @ (80024c4 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
800244e: 4013 ands r3, r2
8002450: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8002452: 683b ldr r3, [r7, #0]
8002454: 685b ldr r3, [r3, #4]
8002456: 68fa ldr r2, [r7, #12]
8002458: 4313 orrs r3, r2
800245a: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800245c: 68fb ldr r3, [r7, #12]
800245e: 2270 movs r2, #112 @ 0x70
8002460: 4393 bics r3, r2
8002462: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8002464: 683b ldr r3, [r7, #0]
8002466: 681b ldr r3, [r3, #0]
8002468: 68fa ldr r2, [r7, #12]
800246a: 4313 orrs r3, r2
800246c: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800246e: 687b ldr r3, [r7, #4]
8002470: 681b ldr r3, [r3, #0]
8002472: 68fa ldr r2, [r7, #12]
8002474: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002476: 687b ldr r3, [r7, #4]
8002478: 681b ldr r3, [r3, #0]
800247a: 4a11 ldr r2, [pc, #68] @ (80024c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
800247c: 4293 cmp r3, r2
800247e: d004 beq.n 800248a <HAL_TIMEx_MasterConfigSynchronization+0x82>
8002480: 687b ldr r3, [r7, #4]
8002482: 681b ldr r3, [r3, #0]
8002484: 4a10 ldr r2, [pc, #64] @ (80024c8 <HAL_TIMEx_MasterConfigSynchronization+0xc0>)
8002486: 4293 cmp r3, r2
8002488: d10c bne.n 80024a4 <HAL_TIMEx_MasterConfigSynchronization+0x9c>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800248a: 68bb ldr r3, [r7, #8]
800248c: 2280 movs r2, #128 @ 0x80
800248e: 4393 bics r3, r2
8002490: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8002492: 683b ldr r3, [r7, #0]
8002494: 689b ldr r3, [r3, #8]
8002496: 68ba ldr r2, [r7, #8]
8002498: 4313 orrs r3, r2
800249a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800249c: 687b ldr r3, [r7, #4]
800249e: 681b ldr r3, [r3, #0]
80024a0: 68ba ldr r2, [r7, #8]
80024a2: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
80024a4: 687b ldr r3, [r7, #4]
80024a6: 223d movs r2, #61 @ 0x3d
80024a8: 2101 movs r1, #1
80024aa: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
80024ac: 687b ldr r3, [r7, #4]
80024ae: 223c movs r2, #60 @ 0x3c
80024b0: 2100 movs r1, #0
80024b2: 5499 strb r1, [r3, r2]
return HAL_OK;
80024b4: 2300 movs r3, #0
}
80024b6: 0018 movs r0, r3
80024b8: 46bd mov sp, r7
80024ba: b004 add sp, #16
80024bc: bd80 pop {r7, pc}
80024be: 46c0 nop @ (mov r8, r8)
80024c0: 40012c00 .word 0x40012c00
80024c4: ff0fffff .word 0xff0fffff
80024c8: 40000400 .word 0x40000400
080024cc <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
80024cc: b580 push {r7, lr}
80024ce: b084 sub sp, #16
80024d0: af00 add r7, sp, #0
80024d2: 6078 str r0, [r7, #4]
80024d4: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
80024d6: 2300 movs r3, #0
80024d8: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
80024da: 687b ldr r3, [r7, #4]
80024dc: 223c movs r2, #60 @ 0x3c
80024de: 5c9b ldrb r3, [r3, r2]
80024e0: 2b01 cmp r3, #1
80024e2: d101 bne.n 80024e8 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
80024e4: 2302 movs r3, #2
80024e6: e06f b.n 80025c8 <HAL_TIMEx_ConfigBreakDeadTime+0xfc>
80024e8: 687b ldr r3, [r7, #4]
80024ea: 223c movs r2, #60 @ 0x3c
80024ec: 2101 movs r1, #1
80024ee: 5499 strb r1, [r3, r2]
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
80024f0: 68fb ldr r3, [r7, #12]
80024f2: 22ff movs r2, #255 @ 0xff
80024f4: 4393 bics r3, r2
80024f6: 001a movs r2, r3
80024f8: 683b ldr r3, [r7, #0]
80024fa: 68db ldr r3, [r3, #12]
80024fc: 4313 orrs r3, r2
80024fe: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8002500: 68fb ldr r3, [r7, #12]
8002502: 4a33 ldr r2, [pc, #204] @ (80025d0 <HAL_TIMEx_ConfigBreakDeadTime+0x104>)
8002504: 401a ands r2, r3
8002506: 683b ldr r3, [r7, #0]
8002508: 689b ldr r3, [r3, #8]
800250a: 4313 orrs r3, r2
800250c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
800250e: 68fb ldr r3, [r7, #12]
8002510: 4a30 ldr r2, [pc, #192] @ (80025d4 <HAL_TIMEx_ConfigBreakDeadTime+0x108>)
8002512: 401a ands r2, r3
8002514: 683b ldr r3, [r7, #0]
8002516: 685b ldr r3, [r3, #4]
8002518: 4313 orrs r3, r2
800251a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
800251c: 68fb ldr r3, [r7, #12]
800251e: 4a2e ldr r2, [pc, #184] @ (80025d8 <HAL_TIMEx_ConfigBreakDeadTime+0x10c>)
8002520: 401a ands r2, r3
8002522: 683b ldr r3, [r7, #0]
8002524: 681b ldr r3, [r3, #0]
8002526: 4313 orrs r3, r2
8002528: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
800252a: 68fb ldr r3, [r7, #12]
800252c: 4a2b ldr r2, [pc, #172] @ (80025dc <HAL_TIMEx_ConfigBreakDeadTime+0x110>)
800252e: 401a ands r2, r3
8002530: 683b ldr r3, [r7, #0]
8002532: 691b ldr r3, [r3, #16]
8002534: 4313 orrs r3, r2
8002536: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8002538: 68fb ldr r3, [r7, #12]
800253a: 4a29 ldr r2, [pc, #164] @ (80025e0 <HAL_TIMEx_ConfigBreakDeadTime+0x114>)
800253c: 401a ands r2, r3
800253e: 683b ldr r3, [r7, #0]
8002540: 695b ldr r3, [r3, #20]
8002542: 4313 orrs r3, r2
8002544: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8002546: 68fb ldr r3, [r7, #12]
8002548: 4a26 ldr r2, [pc, #152] @ (80025e4 <HAL_TIMEx_ConfigBreakDeadTime+0x118>)
800254a: 401a ands r2, r3
800254c: 683b ldr r3, [r7, #0]
800254e: 6b1b ldr r3, [r3, #48] @ 0x30
8002550: 4313 orrs r3, r2
8002552: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
8002554: 68fb ldr r3, [r7, #12]
8002556: 4a24 ldr r2, [pc, #144] @ (80025e8 <HAL_TIMEx_ConfigBreakDeadTime+0x11c>)
8002558: 401a ands r2, r3
800255a: 683b ldr r3, [r7, #0]
800255c: 699b ldr r3, [r3, #24]
800255e: 041b lsls r3, r3, #16
8002560: 4313 orrs r3, r2
8002562: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
8002564: 68fb ldr r3, [r7, #12]
8002566: 4a21 ldr r2, [pc, #132] @ (80025ec <HAL_TIMEx_ConfigBreakDeadTime+0x120>)
8002568: 401a ands r2, r3
800256a: 683b ldr r3, [r7, #0]
800256c: 69db ldr r3, [r3, #28]
800256e: 4313 orrs r3, r2
8002570: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
8002572: 687b ldr r3, [r7, #4]
8002574: 681b ldr r3, [r3, #0]
8002576: 4a1e ldr r2, [pc, #120] @ (80025f0 <HAL_TIMEx_ConfigBreakDeadTime+0x124>)
8002578: 4293 cmp r3, r2
800257a: d11c bne.n 80025b6 <HAL_TIMEx_ConfigBreakDeadTime+0xea>
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
800257c: 68fb ldr r3, [r7, #12]
800257e: 4a1d ldr r2, [pc, #116] @ (80025f4 <HAL_TIMEx_ConfigBreakDeadTime+0x128>)
8002580: 401a ands r2, r3
8002582: 683b ldr r3, [r7, #0]
8002584: 6a9b ldr r3, [r3, #40] @ 0x28
8002586: 051b lsls r3, r3, #20
8002588: 4313 orrs r3, r2
800258a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
800258c: 68fb ldr r3, [r7, #12]
800258e: 4a1a ldr r2, [pc, #104] @ (80025f8 <HAL_TIMEx_ConfigBreakDeadTime+0x12c>)
8002590: 401a ands r2, r3
8002592: 683b ldr r3, [r7, #0]
8002594: 6a1b ldr r3, [r3, #32]
8002596: 4313 orrs r3, r2
8002598: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
800259a: 68fb ldr r3, [r7, #12]
800259c: 4a17 ldr r2, [pc, #92] @ (80025fc <HAL_TIMEx_ConfigBreakDeadTime+0x130>)
800259e: 401a ands r2, r3
80025a0: 683b ldr r3, [r7, #0]
80025a2: 6a5b ldr r3, [r3, #36] @ 0x24
80025a4: 4313 orrs r3, r2
80025a6: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
80025a8: 68fb ldr r3, [r7, #12]
80025aa: 4a15 ldr r2, [pc, #84] @ (8002600 <HAL_TIMEx_ConfigBreakDeadTime+0x134>)
80025ac: 401a ands r2, r3
80025ae: 683b ldr r3, [r7, #0]
80025b0: 6adb ldr r3, [r3, #44] @ 0x2c
80025b2: 4313 orrs r3, r2
80025b4: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
80025b6: 687b ldr r3, [r7, #4]
80025b8: 681b ldr r3, [r3, #0]
80025ba: 68fa ldr r2, [r7, #12]
80025bc: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
80025be: 687b ldr r3, [r7, #4]
80025c0: 223c movs r2, #60 @ 0x3c
80025c2: 2100 movs r1, #0
80025c4: 5499 strb r1, [r3, r2]
return HAL_OK;
80025c6: 2300 movs r3, #0
}
80025c8: 0018 movs r0, r3
80025ca: 46bd mov sp, r7
80025cc: b004 add sp, #16
80025ce: bd80 pop {r7, pc}
80025d0: fffffcff .word 0xfffffcff
80025d4: fffffbff .word 0xfffffbff
80025d8: fffff7ff .word 0xfffff7ff
80025dc: ffffefff .word 0xffffefff
80025e0: ffffdfff .word 0xffffdfff
80025e4: ffffbfff .word 0xffffbfff
80025e8: fff0ffff .word 0xfff0ffff
80025ec: efffffff .word 0xefffffff
80025f0: 40012c00 .word 0x40012c00
80025f4: ff0fffff .word 0xff0fffff
80025f8: feffffff .word 0xfeffffff
80025fc: fdffffff .word 0xfdffffff
8002600: dfffffff .word 0xdfffffff
08002604 <memset>:
8002604: 0003 movs r3, r0
8002606: 1882 adds r2, r0, r2
8002608: 4293 cmp r3, r2
800260a: d100 bne.n 800260e <memset+0xa>
800260c: 4770 bx lr
800260e: 7019 strb r1, [r3, #0]
8002610: 3301 adds r3, #1
8002612: e7f9 b.n 8002608 <memset+0x4>
08002614 <__libc_init_array>:
8002614: b570 push {r4, r5, r6, lr}
8002616: 2600 movs r6, #0
8002618: 4c0c ldr r4, [pc, #48] @ (800264c <__libc_init_array+0x38>)
800261a: 4d0d ldr r5, [pc, #52] @ (8002650 <__libc_init_array+0x3c>)
800261c: 1b64 subs r4, r4, r5
800261e: 10a4 asrs r4, r4, #2
8002620: 42a6 cmp r6, r4
8002622: d109 bne.n 8002638 <__libc_init_array+0x24>
8002624: 2600 movs r6, #0
8002626: f000 f819 bl 800265c <_init>
800262a: 4c0a ldr r4, [pc, #40] @ (8002654 <__libc_init_array+0x40>)
800262c: 4d0a ldr r5, [pc, #40] @ (8002658 <__libc_init_array+0x44>)
800262e: 1b64 subs r4, r4, r5
8002630: 10a4 asrs r4, r4, #2
8002632: 42a6 cmp r6, r4
8002634: d105 bne.n 8002642 <__libc_init_array+0x2e>
8002636: bd70 pop {r4, r5, r6, pc}
8002638: 00b3 lsls r3, r6, #2
800263a: 58eb ldr r3, [r5, r3]
800263c: 4798 blx r3
800263e: 3601 adds r6, #1
8002640: e7ee b.n 8002620 <__libc_init_array+0xc>
8002642: 00b3 lsls r3, r6, #2
8002644: 58eb ldr r3, [r5, r3]
8002646: 4798 blx r3
8002648: 3601 adds r6, #1
800264a: e7f2 b.n 8002632 <__libc_init_array+0x1e>
800264c: 08002708 .word 0x08002708
8002650: 08002708 .word 0x08002708
8002654: 0800270c .word 0x0800270c
8002658: 08002708 .word 0x08002708
0800265c <_init>:
800265c: b5f8 push {r3, r4, r5, r6, r7, lr}
800265e: 46c0 nop @ (mov r8, r8)
8002660: bcf8 pop {r3, r4, r5, r6, r7}
8002662: bc08 pop {r3}
8002664: 469e mov lr, r3
8002666: 4770 bx lr
08002668 <_fini>:
8002668: b5f8 push {r3, r4, r5, r6, r7, lr}
800266a: 46c0 nop @ (mov r8, r8)
800266c: bcf8 pop {r3, r4, r5, r6, r7}
800266e: bc08 pop {r3}
8002670: 469e mov lr, r3
8002672: 4770 bx lr
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