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3cb8b7d5057f03ef29bc32c7e040eaa81ca1baf0
AUTOM/workspace/AUTOM1/Debug/AUTOM1.list
andrea 53391bffc6 wip
2025-08-27 23:29:38 +02:00

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AUTOM1.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001c20 080000c0 080000c0 000010c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 08001ce0 08001ce0 00002ce0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08001d10 08001d10 0000300c 2**0
CONTENTS, READONLY
4 .ARM 00000000 08001d10 08001d10 0000300c 2**0
CONTENTS, READONLY
5 .preinit_array 00000000 08001d10 08001d10 0000300c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08001d10 08001d10 00002d10 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08001d14 08001d14 00002d14 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08001d18 00003000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000068 2000000c 08001d24 0000300c 2**2
ALLOC
10 ._user_heap_stack 00000604 20000074 08001d24 00003074 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0000300c 2**0
CONTENTS, READONLY
12 .debug_info 0000715f 00000000 00000000 00003034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001440 00000000 00000000 0000a193 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000008a8 00000000 00000000 0000b5d8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000006b6 00000000 00000000 0000be80 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0000ec07 00000000 00000000 0000c536 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00009b84 00000000 00000000 0001b13d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0005bd2c 00000000 00000000 00024cc1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000809ed 2**0
CONTENTS, READONLY
20 .debug_frame 00001ed8 00000000 00000000 00080a30 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 00082908 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 08001cc8 .word 0x08001cc8
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] @ (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] @ (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop @ (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 08001cc8 .word 0x08001cc8
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 @ 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop @ (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__aeabi_idiv0>:
800021c: 4770 bx lr
800021e: 46c0 nop @ (mov r8, r8)
08000220 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000220: b580 push {r7, lr}
8000222: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000224: f000 fa20 bl 8000668 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000228: f000 f806 bl 8000238 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800022c: f000 f8e6 bl 80003fc <MX_GPIO_Init>
MX_TIM1_Init();
8000230: f000 f842 bl 80002b8 <MX_TIM1_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000234: 46c0 nop @ (mov r8, r8)
8000236: e7fd b.n 8000234 <main+0x14>
08000238 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000238: b590 push {r4, r7, lr}
800023a: b091 sub sp, #68 @ 0x44
800023c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800023e: 2410 movs r4, #16
8000240: 193b adds r3, r7, r4
8000242: 0018 movs r0, r3
8000244: 2330 movs r3, #48 @ 0x30
8000246: 001a movs r2, r3
8000248: 2100 movs r1, #0
800024a: f001 fd11 bl 8001c70 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800024e: 003b movs r3, r7
8000250: 0018 movs r0, r3
8000252: 2310 movs r3, #16
8000254: 001a movs r2, r3
8000256: 2100 movs r1, #0
8000258: f001 fd0a bl 8001c70 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800025c: 0021 movs r1, r4
800025e: 187b adds r3, r7, r1
8000260: 2202 movs r2, #2
8000262: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000264: 187b adds r3, r7, r1
8000266: 2201 movs r2, #1
8000268: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800026a: 187b adds r3, r7, r1
800026c: 2210 movs r2, #16
800026e: 611a str r2, [r3, #16]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000270: 187b adds r3, r7, r1
8000272: 2200 movs r2, #0
8000274: 621a str r2, [r3, #32]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000276: 187b adds r3, r7, r1
8000278: 0018 movs r0, r3
800027a: f000 fc9b bl 8000bb4 <HAL_RCC_OscConfig>
800027e: 1e03 subs r3, r0, #0
8000280: d001 beq.n 8000286 <SystemClock_Config+0x4e>
{
Error_Handler();
8000282: f000 f91f bl 80004c4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000286: 003b movs r3, r7
8000288: 2207 movs r2, #7
800028a: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
800028c: 003b movs r3, r7
800028e: 2200 movs r2, #0
8000290: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000292: 003b movs r3, r7
8000294: 2200 movs r2, #0
8000296: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000298: 003b movs r3, r7
800029a: 2200 movs r2, #0
800029c: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
800029e: 003b movs r3, r7
80002a0: 2100 movs r1, #0
80002a2: 0018 movs r0, r3
80002a4: f000 ffa0 bl 80011e8 <HAL_RCC_ClockConfig>
80002a8: 1e03 subs r3, r0, #0
80002aa: d001 beq.n 80002b0 <SystemClock_Config+0x78>
{
Error_Handler();
80002ac: f000 f90a bl 80004c4 <Error_Handler>
}
}
80002b0: 46c0 nop @ (mov r8, r8)
80002b2: 46bd mov sp, r7
80002b4: b011 add sp, #68 @ 0x44
80002b6: bd90 pop {r4, r7, pc}
080002b8 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
80002b8: b580 push {r7, lr}
80002ba: b092 sub sp, #72 @ 0x48
80002bc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80002be: 2340 movs r3, #64 @ 0x40
80002c0: 18fb adds r3, r7, r3
80002c2: 0018 movs r0, r3
80002c4: 2308 movs r3, #8
80002c6: 001a movs r2, r3
80002c8: 2100 movs r1, #0
80002ca: f001 fcd1 bl 8001c70 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
80002ce: 2324 movs r3, #36 @ 0x24
80002d0: 18fb adds r3, r7, r3
80002d2: 0018 movs r0, r3
80002d4: 231c movs r3, #28
80002d6: 001a movs r2, r3
80002d8: 2100 movs r1, #0
80002da: f001 fcc9 bl 8001c70 <memset>
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
80002de: 1d3b adds r3, r7, #4
80002e0: 0018 movs r0, r3
80002e2: 2320 movs r3, #32
80002e4: 001a movs r2, r3
80002e6: 2100 movs r1, #0
80002e8: f001 fcc2 bl 8001c70 <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
80002ec: 4b40 ldr r3, [pc, #256] @ (80003f0 <MX_TIM1_Init+0x138>)
80002ee: 4a41 ldr r2, [pc, #260] @ (80003f4 <MX_TIM1_Init+0x13c>)
80002f0: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
80002f2: 4b3f ldr r3, [pc, #252] @ (80003f0 <MX_TIM1_Init+0x138>)
80002f4: 2200 movs r2, #0
80002f6: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80002f8: 4b3d ldr r3, [pc, #244] @ (80003f0 <MX_TIM1_Init+0x138>)
80002fa: 2200 movs r2, #0
80002fc: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
80002fe: 4b3c ldr r3, [pc, #240] @ (80003f0 <MX_TIM1_Init+0x138>)
8000300: 4a3d ldr r2, [pc, #244] @ (80003f8 <MX_TIM1_Init+0x140>)
8000302: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000304: 4b3a ldr r3, [pc, #232] @ (80003f0 <MX_TIM1_Init+0x138>)
8000306: 2200 movs r2, #0
8000308: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
800030a: 4b39 ldr r3, [pc, #228] @ (80003f0 <MX_TIM1_Init+0x138>)
800030c: 2200 movs r2, #0
800030e: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000310: 4b37 ldr r3, [pc, #220] @ (80003f0 <MX_TIM1_Init+0x138>)
8000312: 2200 movs r2, #0
8000314: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
8000316: 4b36 ldr r3, [pc, #216] @ (80003f0 <MX_TIM1_Init+0x138>)
8000318: 0018 movs r0, r3
800031a: f001 f889 bl 8001430 <HAL_TIM_PWM_Init>
800031e: 1e03 subs r3, r0, #0
8000320: d001 beq.n 8000326 <MX_TIM1_Init+0x6e>
{
Error_Handler();
8000322: f000 f8cf bl 80004c4 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000326: 2140 movs r1, #64 @ 0x40
8000328: 187b adds r3, r7, r1
800032a: 2200 movs r2, #0
800032c: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800032e: 187b adds r3, r7, r1
8000330: 2200 movs r2, #0
8000332: 605a str r2, [r3, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000334: 187a adds r2, r7, r1
8000336: 4b2e ldr r3, [pc, #184] @ (80003f0 <MX_TIM1_Init+0x138>)
8000338: 0011 movs r1, r2
800033a: 0018 movs r0, r3
800033c: f001 fbe8 bl 8001b10 <HAL_TIMEx_MasterConfigSynchronization>
8000340: 1e03 subs r3, r0, #0
8000342: d001 beq.n 8000348 <MX_TIM1_Init+0x90>
{
Error_Handler();
8000344: f000 f8be bl 80004c4 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000348: 2124 movs r1, #36 @ 0x24
800034a: 187b adds r3, r7, r1
800034c: 2260 movs r2, #96 @ 0x60
800034e: 601a str r2, [r3, #0]
sConfigOC.Pulse = 0;
8000350: 187b adds r3, r7, r1
8000352: 2200 movs r2, #0
8000354: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000356: 187b adds r3, r7, r1
8000358: 2200 movs r2, #0
800035a: 609a str r2, [r3, #8]
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
800035c: 187b adds r3, r7, r1
800035e: 2200 movs r2, #0
8000360: 60da str r2, [r3, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000362: 187b adds r3, r7, r1
8000364: 2200 movs r2, #0
8000366: 611a str r2, [r3, #16]
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8000368: 187b adds r3, r7, r1
800036a: 2200 movs r2, #0
800036c: 615a str r2, [r3, #20]
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
800036e: 187b adds r3, r7, r1
8000370: 2200 movs r2, #0
8000372: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000374: 1879 adds r1, r7, r1
8000376: 4b1e ldr r3, [pc, #120] @ (80003f0 <MX_TIM1_Init+0x138>)
8000378: 2204 movs r2, #4
800037a: 0018 movs r0, r3
800037c: f001 f8a8 bl 80014d0 <HAL_TIM_PWM_ConfigChannel>
8000380: 1e03 subs r3, r0, #0
8000382: d001 beq.n 8000388 <MX_TIM1_Init+0xd0>
{
Error_Handler();
8000384: f000 f89e bl 80004c4 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000388: 2324 movs r3, #36 @ 0x24
800038a: 18f9 adds r1, r7, r3
800038c: 4b18 ldr r3, [pc, #96] @ (80003f0 <MX_TIM1_Init+0x138>)
800038e: 2208 movs r2, #8
8000390: 0018 movs r0, r3
8000392: f001 f89d bl 80014d0 <HAL_TIM_PWM_ConfigChannel>
8000396: 1e03 subs r3, r0, #0
8000398: d001 beq.n 800039e <MX_TIM1_Init+0xe6>
{
Error_Handler();
800039a: f000 f893 bl 80004c4 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800039e: 1d3b adds r3, r7, #4
80003a0: 2200 movs r2, #0
80003a2: 601a str r2, [r3, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
80003a4: 1d3b adds r3, r7, #4
80003a6: 2200 movs r2, #0
80003a8: 605a str r2, [r3, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
80003aa: 1d3b adds r3, r7, #4
80003ac: 2200 movs r2, #0
80003ae: 609a str r2, [r3, #8]
sBreakDeadTimeConfig.DeadTime = 0;
80003b0: 1d3b adds r3, r7, #4
80003b2: 2200 movs r2, #0
80003b4: 60da str r2, [r3, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
80003b6: 1d3b adds r3, r7, #4
80003b8: 2200 movs r2, #0
80003ba: 611a str r2, [r3, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
80003bc: 1d3b adds r3, r7, #4
80003be: 2280 movs r2, #128 @ 0x80
80003c0: 0192 lsls r2, r2, #6
80003c2: 615a str r2, [r3, #20]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
80003c4: 1d3b adds r3, r7, #4
80003c6: 2200 movs r2, #0
80003c8: 61da str r2, [r3, #28]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
80003ca: 1d3a adds r2, r7, #4
80003cc: 4b08 ldr r3, [pc, #32] @ (80003f0 <MX_TIM1_Init+0x138>)
80003ce: 0011 movs r1, r2
80003d0: 0018 movs r0, r3
80003d2: f001 fbef bl 8001bb4 <HAL_TIMEx_ConfigBreakDeadTime>
80003d6: 1e03 subs r3, r0, #0
80003d8: d001 beq.n 80003de <MX_TIM1_Init+0x126>
{
Error_Handler();
80003da: f000 f873 bl 80004c4 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
80003de: 4b04 ldr r3, [pc, #16] @ (80003f0 <MX_TIM1_Init+0x138>)
80003e0: 0018 movs r0, r3
80003e2: f000 f8b9 bl 8000558 <HAL_TIM_MspPostInit>
}
80003e6: 46c0 nop @ (mov r8, r8)
80003e8: 46bd mov sp, r7
80003ea: b012 add sp, #72 @ 0x48
80003ec: bd80 pop {r7, pc}
80003ee: 46c0 nop @ (mov r8, r8)
80003f0: 20000028 .word 0x20000028
80003f4: 40012c00 .word 0x40012c00
80003f8: 0000ffff .word 0x0000ffff
080003fc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80003fc: b590 push {r4, r7, lr}
80003fe: b089 sub sp, #36 @ 0x24
8000400: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000402: 240c movs r4, #12
8000404: 193b adds r3, r7, r4
8000406: 0018 movs r0, r3
8000408: 2314 movs r3, #20
800040a: 001a movs r2, r3
800040c: 2100 movs r1, #0
800040e: f001 fc2f bl 8001c70 <memset>
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000412: 4b29 ldr r3, [pc, #164] @ (80004b8 <MX_GPIO_Init+0xbc>)
8000414: 695a ldr r2, [r3, #20]
8000416: 4b28 ldr r3, [pc, #160] @ (80004b8 <MX_GPIO_Init+0xbc>)
8000418: 2180 movs r1, #128 @ 0x80
800041a: 0289 lsls r1, r1, #10
800041c: 430a orrs r2, r1
800041e: 615a str r2, [r3, #20]
8000420: 4b25 ldr r3, [pc, #148] @ (80004b8 <MX_GPIO_Init+0xbc>)
8000422: 695a ldr r2, [r3, #20]
8000424: 2380 movs r3, #128 @ 0x80
8000426: 029b lsls r3, r3, #10
8000428: 4013 ands r3, r2
800042a: 60bb str r3, [r7, #8]
800042c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
800042e: 4b22 ldr r3, [pc, #136] @ (80004b8 <MX_GPIO_Init+0xbc>)
8000430: 695a ldr r2, [r3, #20]
8000432: 4b21 ldr r3, [pc, #132] @ (80004b8 <MX_GPIO_Init+0xbc>)
8000434: 2180 movs r1, #128 @ 0x80
8000436: 02c9 lsls r1, r1, #11
8000438: 430a orrs r2, r1
800043a: 615a str r2, [r3, #20]
800043c: 4b1e ldr r3, [pc, #120] @ (80004b8 <MX_GPIO_Init+0xbc>)
800043e: 695a ldr r2, [r3, #20]
8000440: 2380 movs r3, #128 @ 0x80
8000442: 02db lsls r3, r3, #11
8000444: 4013 ands r3, r2
8000446: 607b str r3, [r7, #4]
8000448: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_13
800044a: 491c ldr r1, [pc, #112] @ (80004bc <MX_GPIO_Init+0xc0>)
800044c: 2390 movs r3, #144 @ 0x90
800044e: 05db lsls r3, r3, #23
8000450: 2200 movs r2, #0
8000452: 0018 movs r0, r3
8000454: f000 fb90 bl 8000b78 <HAL_GPIO_WritePin>
|GPIO_PIN_14, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_RESET);
8000458: 4b19 ldr r3, [pc, #100] @ (80004c0 <MX_GPIO_Init+0xc4>)
800045a: 2200 movs r2, #0
800045c: 2102 movs r1, #2
800045e: 0018 movs r0, r3
8000460: f000 fb8a bl 8000b78 <HAL_GPIO_WritePin>
/*Configure GPIO pins : PA5 PA6 PA7 PA13
PA14 */
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_13
8000464: 193b adds r3, r7, r4
8000466: 4a15 ldr r2, [pc, #84] @ (80004bc <MX_GPIO_Init+0xc0>)
8000468: 601a str r2, [r3, #0]
|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800046a: 193b adds r3, r7, r4
800046c: 2201 movs r2, #1
800046e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000470: 193b adds r3, r7, r4
8000472: 2200 movs r2, #0
8000474: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000476: 193b adds r3, r7, r4
8000478: 2200 movs r2, #0
800047a: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800047c: 193a adds r2, r7, r4
800047e: 2390 movs r3, #144 @ 0x90
8000480: 05db lsls r3, r3, #23
8000482: 0011 movs r1, r2
8000484: 0018 movs r0, r3
8000486: f000 fa07 bl 8000898 <HAL_GPIO_Init>
/*Configure GPIO pin : PB1 */
GPIO_InitStruct.Pin = GPIO_PIN_1;
800048a: 0021 movs r1, r4
800048c: 187b adds r3, r7, r1
800048e: 2202 movs r2, #2
8000490: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000492: 187b adds r3, r7, r1
8000494: 2201 movs r2, #1
8000496: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000498: 187b adds r3, r7, r1
800049a: 2200 movs r2, #0
800049c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800049e: 187b adds r3, r7, r1
80004a0: 2200 movs r2, #0
80004a2: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80004a4: 187b adds r3, r7, r1
80004a6: 4a06 ldr r2, [pc, #24] @ (80004c0 <MX_GPIO_Init+0xc4>)
80004a8: 0019 movs r1, r3
80004aa: 0010 movs r0, r2
80004ac: f000 f9f4 bl 8000898 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80004b0: 46c0 nop @ (mov r8, r8)
80004b2: 46bd mov sp, r7
80004b4: b009 add sp, #36 @ 0x24
80004b6: bd90 pop {r4, r7, pc}
80004b8: 40021000 .word 0x40021000
80004bc: 000060e0 .word 0x000060e0
80004c0: 48000400 .word 0x48000400
080004c4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80004c4: b580 push {r7, lr}
80004c6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80004c8: b672 cpsid i
}
80004ca: 46c0 nop @ (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80004cc: 46c0 nop @ (mov r8, r8)
80004ce: e7fd b.n 80004cc <Error_Handler+0x8>
080004d0 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80004d0: b580 push {r7, lr}
80004d2: b082 sub sp, #8
80004d4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80004d6: 4b0f ldr r3, [pc, #60] @ (8000514 <HAL_MspInit+0x44>)
80004d8: 699a ldr r2, [r3, #24]
80004da: 4b0e ldr r3, [pc, #56] @ (8000514 <HAL_MspInit+0x44>)
80004dc: 2101 movs r1, #1
80004de: 430a orrs r2, r1
80004e0: 619a str r2, [r3, #24]
80004e2: 4b0c ldr r3, [pc, #48] @ (8000514 <HAL_MspInit+0x44>)
80004e4: 699b ldr r3, [r3, #24]
80004e6: 2201 movs r2, #1
80004e8: 4013 ands r3, r2
80004ea: 607b str r3, [r7, #4]
80004ec: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80004ee: 4b09 ldr r3, [pc, #36] @ (8000514 <HAL_MspInit+0x44>)
80004f0: 69da ldr r2, [r3, #28]
80004f2: 4b08 ldr r3, [pc, #32] @ (8000514 <HAL_MspInit+0x44>)
80004f4: 2180 movs r1, #128 @ 0x80
80004f6: 0549 lsls r1, r1, #21
80004f8: 430a orrs r2, r1
80004fa: 61da str r2, [r3, #28]
80004fc: 4b05 ldr r3, [pc, #20] @ (8000514 <HAL_MspInit+0x44>)
80004fe: 69da ldr r2, [r3, #28]
8000500: 2380 movs r3, #128 @ 0x80
8000502: 055b lsls r3, r3, #21
8000504: 4013 ands r3, r2
8000506: 603b str r3, [r7, #0]
8000508: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800050a: 46c0 nop @ (mov r8, r8)
800050c: 46bd mov sp, r7
800050e: b002 add sp, #8
8000510: bd80 pop {r7, pc}
8000512: 46c0 nop @ (mov r8, r8)
8000514: 40021000 .word 0x40021000
08000518 <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
8000518: b580 push {r7, lr}
800051a: b084 sub sp, #16
800051c: af00 add r7, sp, #0
800051e: 6078 str r0, [r7, #4]
if(htim_pwm->Instance==TIM1)
8000520: 687b ldr r3, [r7, #4]
8000522: 681b ldr r3, [r3, #0]
8000524: 4a0a ldr r2, [pc, #40] @ (8000550 <HAL_TIM_PWM_MspInit+0x38>)
8000526: 4293 cmp r3, r2
8000528: d10d bne.n 8000546 <HAL_TIM_PWM_MspInit+0x2e>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
800052a: 4b0a ldr r3, [pc, #40] @ (8000554 <HAL_TIM_PWM_MspInit+0x3c>)
800052c: 699a ldr r2, [r3, #24]
800052e: 4b09 ldr r3, [pc, #36] @ (8000554 <HAL_TIM_PWM_MspInit+0x3c>)
8000530: 2180 movs r1, #128 @ 0x80
8000532: 0109 lsls r1, r1, #4
8000534: 430a orrs r2, r1
8000536: 619a str r2, [r3, #24]
8000538: 4b06 ldr r3, [pc, #24] @ (8000554 <HAL_TIM_PWM_MspInit+0x3c>)
800053a: 699a ldr r2, [r3, #24]
800053c: 2380 movs r3, #128 @ 0x80
800053e: 011b lsls r3, r3, #4
8000540: 4013 ands r3, r2
8000542: 60fb str r3, [r7, #12]
8000544: 68fb ldr r3, [r7, #12]
/* USER CODE END TIM1_MspInit 1 */
}
}
8000546: 46c0 nop @ (mov r8, r8)
8000548: 46bd mov sp, r7
800054a: b004 add sp, #16
800054c: bd80 pop {r7, pc}
800054e: 46c0 nop @ (mov r8, r8)
8000550: 40012c00 .word 0x40012c00
8000554: 40021000 .word 0x40021000
08000558 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000558: b590 push {r4, r7, lr}
800055a: b089 sub sp, #36 @ 0x24
800055c: af00 add r7, sp, #0
800055e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000560: 240c movs r4, #12
8000562: 193b adds r3, r7, r4
8000564: 0018 movs r0, r3
8000566: 2314 movs r3, #20
8000568: 001a movs r2, r3
800056a: 2100 movs r1, #0
800056c: f001 fb80 bl 8001c70 <memset>
if(htim->Instance==TIM1)
8000570: 687b ldr r3, [r7, #4]
8000572: 681b ldr r3, [r3, #0]
8000574: 4a16 ldr r2, [pc, #88] @ (80005d0 <HAL_TIM_MspPostInit+0x78>)
8000576: 4293 cmp r3, r2
8000578: d125 bne.n 80005c6 <HAL_TIM_MspPostInit+0x6e>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
800057a: 4b16 ldr r3, [pc, #88] @ (80005d4 <HAL_TIM_MspPostInit+0x7c>)
800057c: 695a ldr r2, [r3, #20]
800057e: 4b15 ldr r3, [pc, #84] @ (80005d4 <HAL_TIM_MspPostInit+0x7c>)
8000580: 2180 movs r1, #128 @ 0x80
8000582: 0289 lsls r1, r1, #10
8000584: 430a orrs r2, r1
8000586: 615a str r2, [r3, #20]
8000588: 4b12 ldr r3, [pc, #72] @ (80005d4 <HAL_TIM_MspPostInit+0x7c>)
800058a: 695a ldr r2, [r3, #20]
800058c: 2380 movs r3, #128 @ 0x80
800058e: 029b lsls r3, r3, #10
8000590: 4013 ands r3, r2
8000592: 60bb str r3, [r7, #8]
8000594: 68bb ldr r3, [r7, #8]
/**TIM1 GPIO Configuration
PA9 ------> TIM1_CH2
PA10 ------> TIM1_CH3
*/
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
8000596: 193b adds r3, r7, r4
8000598: 22c0 movs r2, #192 @ 0xc0
800059a: 00d2 lsls r2, r2, #3
800059c: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800059e: 0021 movs r1, r4
80005a0: 187b adds r3, r7, r1
80005a2: 2202 movs r2, #2
80005a4: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005a6: 187b adds r3, r7, r1
80005a8: 2200 movs r2, #0
80005aa: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80005ac: 187b adds r3, r7, r1
80005ae: 2200 movs r2, #0
80005b0: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
80005b2: 187b adds r3, r7, r1
80005b4: 2202 movs r2, #2
80005b6: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80005b8: 187a adds r2, r7, r1
80005ba: 2390 movs r3, #144 @ 0x90
80005bc: 05db lsls r3, r3, #23
80005be: 0011 movs r1, r2
80005c0: 0018 movs r0, r3
80005c2: f000 f969 bl 8000898 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
80005c6: 46c0 nop @ (mov r8, r8)
80005c8: 46bd mov sp, r7
80005ca: b009 add sp, #36 @ 0x24
80005cc: bd90 pop {r4, r7, pc}
80005ce: 46c0 nop @ (mov r8, r8)
80005d0: 40012c00 .word 0x40012c00
80005d4: 40021000 .word 0x40021000
080005d8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80005d8: b580 push {r7, lr}
80005da: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80005dc: 46c0 nop @ (mov r8, r8)
80005de: e7fd b.n 80005dc <NMI_Handler+0x4>
080005e0 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80005e0: b580 push {r7, lr}
80005e2: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80005e4: 46c0 nop @ (mov r8, r8)
80005e6: e7fd b.n 80005e4 <HardFault_Handler+0x4>
080005e8 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80005e8: b580 push {r7, lr}
80005ea: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
80005ec: 46c0 nop @ (mov r8, r8)
80005ee: 46bd mov sp, r7
80005f0: bd80 pop {r7, pc}
080005f2 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80005f2: b580 push {r7, lr}
80005f4: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80005f6: 46c0 nop @ (mov r8, r8)
80005f8: 46bd mov sp, r7
80005fa: bd80 pop {r7, pc}
080005fc <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80005fc: b580 push {r7, lr}
80005fe: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000600: f000 f87a bl 80006f8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000604: 46c0 nop @ (mov r8, r8)
8000606: 46bd mov sp, r7
8000608: bd80 pop {r7, pc}
0800060a <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
800060a: b580 push {r7, lr}
800060c: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
800060e: 46c0 nop @ (mov r8, r8)
8000610: 46bd mov sp, r7
8000612: bd80 pop {r7, pc}
08000614 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000614: 480d ldr r0, [pc, #52] @ (800064c <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000616: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8000618: f7ff fff7 bl 800060a <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800061c: 480c ldr r0, [pc, #48] @ (8000650 <LoopForever+0x6>)
ldr r1, =_edata
800061e: 490d ldr r1, [pc, #52] @ (8000654 <LoopForever+0xa>)
ldr r2, =_sidata
8000620: 4a0d ldr r2, [pc, #52] @ (8000658 <LoopForever+0xe>)
movs r3, #0
8000622: 2300 movs r3, #0
b LoopCopyDataInit
8000624: e002 b.n 800062c <LoopCopyDataInit>
08000626 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000626: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000628: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800062a: 3304 adds r3, #4
0800062c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800062c: 18c4 adds r4, r0, r3
cmp r4, r1
800062e: 428c cmp r4, r1
bcc CopyDataInit
8000630: d3f9 bcc.n 8000626 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000632: 4a0a ldr r2, [pc, #40] @ (800065c <LoopForever+0x12>)
ldr r4, =_ebss
8000634: 4c0a ldr r4, [pc, #40] @ (8000660 <LoopForever+0x16>)
movs r3, #0
8000636: 2300 movs r3, #0
b LoopFillZerobss
8000638: e001 b.n 800063e <LoopFillZerobss>
0800063a <FillZerobss>:
FillZerobss:
str r3, [r2]
800063a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800063c: 3204 adds r2, #4
0800063e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800063e: 42a2 cmp r2, r4
bcc FillZerobss
8000640: d3fb bcc.n 800063a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000642: f001 fb1d bl 8001c80 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000646: f7ff fdeb bl 8000220 <main>
0800064a <LoopForever>:
LoopForever:
b LoopForever
800064a: e7fe b.n 800064a <LoopForever>
ldr r0, =_estack
800064c: 20001000 .word 0x20001000
ldr r0, =_sdata
8000650: 20000000 .word 0x20000000
ldr r1, =_edata
8000654: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000658: 08001d18 .word 0x08001d18
ldr r2, =_sbss
800065c: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000660: 20000074 .word 0x20000074
08000664 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000664: e7fe b.n 8000664 <ADC1_IRQHandler>
...
08000668 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000668: b580 push {r7, lr}
800066a: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
800066c: 4b07 ldr r3, [pc, #28] @ (800068c <HAL_Init+0x24>)
800066e: 681a ldr r2, [r3, #0]
8000670: 4b06 ldr r3, [pc, #24] @ (800068c <HAL_Init+0x24>)
8000672: 2110 movs r1, #16
8000674: 430a orrs r2, r1
8000676: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000678: 2003 movs r0, #3
800067a: f000 f809 bl 8000690 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800067e: f7ff ff27 bl 80004d0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000682: 2300 movs r3, #0
}
8000684: 0018 movs r0, r3
8000686: 46bd mov sp, r7
8000688: bd80 pop {r7, pc}
800068a: 46c0 nop @ (mov r8, r8)
800068c: 40022000 .word 0x40022000
08000690 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000690: b590 push {r4, r7, lr}
8000692: b083 sub sp, #12
8000694: af00 add r7, sp, #0
8000696: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000698: 4b14 ldr r3, [pc, #80] @ (80006ec <HAL_InitTick+0x5c>)
800069a: 681c ldr r4, [r3, #0]
800069c: 4b14 ldr r3, [pc, #80] @ (80006f0 <HAL_InitTick+0x60>)
800069e: 781b ldrb r3, [r3, #0]
80006a0: 0019 movs r1, r3
80006a2: 23fa movs r3, #250 @ 0xfa
80006a4: 0098 lsls r0, r3, #2
80006a6: f7ff fd2f bl 8000108 <__udivsi3>
80006aa: 0003 movs r3, r0
80006ac: 0019 movs r1, r3
80006ae: 0020 movs r0, r4
80006b0: f7ff fd2a bl 8000108 <__udivsi3>
80006b4: 0003 movs r3, r0
80006b6: 0018 movs r0, r3
80006b8: f000 f8e1 bl 800087e <HAL_SYSTICK_Config>
80006bc: 1e03 subs r3, r0, #0
80006be: d001 beq.n 80006c4 <HAL_InitTick+0x34>
{
return HAL_ERROR;
80006c0: 2301 movs r3, #1
80006c2: e00f b.n 80006e4 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80006c4: 687b ldr r3, [r7, #4]
80006c6: 2b03 cmp r3, #3
80006c8: d80b bhi.n 80006e2 <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80006ca: 6879 ldr r1, [r7, #4]
80006cc: 2301 movs r3, #1
80006ce: 425b negs r3, r3
80006d0: 2200 movs r2, #0
80006d2: 0018 movs r0, r3
80006d4: f000 f8be bl 8000854 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80006d8: 4b06 ldr r3, [pc, #24] @ (80006f4 <HAL_InitTick+0x64>)
80006da: 687a ldr r2, [r7, #4]
80006dc: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80006de: 2300 movs r3, #0
80006e0: e000 b.n 80006e4 <HAL_InitTick+0x54>
return HAL_ERROR;
80006e2: 2301 movs r3, #1
}
80006e4: 0018 movs r0, r3
80006e6: 46bd mov sp, r7
80006e8: b003 add sp, #12
80006ea: bd90 pop {r4, r7, pc}
80006ec: 20000000 .word 0x20000000
80006f0: 20000008 .word 0x20000008
80006f4: 20000004 .word 0x20000004
080006f8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80006f8: b580 push {r7, lr}
80006fa: af00 add r7, sp, #0
uwTick += uwTickFreq;
80006fc: 4b05 ldr r3, [pc, #20] @ (8000714 <HAL_IncTick+0x1c>)
80006fe: 781b ldrb r3, [r3, #0]
8000700: 001a movs r2, r3
8000702: 4b05 ldr r3, [pc, #20] @ (8000718 <HAL_IncTick+0x20>)
8000704: 681b ldr r3, [r3, #0]
8000706: 18d2 adds r2, r2, r3
8000708: 4b03 ldr r3, [pc, #12] @ (8000718 <HAL_IncTick+0x20>)
800070a: 601a str r2, [r3, #0]
}
800070c: 46c0 nop @ (mov r8, r8)
800070e: 46bd mov sp, r7
8000710: bd80 pop {r7, pc}
8000712: 46c0 nop @ (mov r8, r8)
8000714: 20000008 .word 0x20000008
8000718: 20000070 .word 0x20000070
0800071c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800071c: b580 push {r7, lr}
800071e: af00 add r7, sp, #0
return uwTick;
8000720: 4b02 ldr r3, [pc, #8] @ (800072c <HAL_GetTick+0x10>)
8000722: 681b ldr r3, [r3, #0]
}
8000724: 0018 movs r0, r3
8000726: 46bd mov sp, r7
8000728: bd80 pop {r7, pc}
800072a: 46c0 nop @ (mov r8, r8)
800072c: 20000070 .word 0x20000070
08000730 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000730: b590 push {r4, r7, lr}
8000732: b083 sub sp, #12
8000734: af00 add r7, sp, #0
8000736: 0002 movs r2, r0
8000738: 6039 str r1, [r7, #0]
800073a: 1dfb adds r3, r7, #7
800073c: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
800073e: 1dfb adds r3, r7, #7
8000740: 781b ldrb r3, [r3, #0]
8000742: 2b7f cmp r3, #127 @ 0x7f
8000744: d828 bhi.n 8000798 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000746: 4a2f ldr r2, [pc, #188] @ (8000804 <__NVIC_SetPriority+0xd4>)
8000748: 1dfb adds r3, r7, #7
800074a: 781b ldrb r3, [r3, #0]
800074c: b25b sxtb r3, r3
800074e: 089b lsrs r3, r3, #2
8000750: 33c0 adds r3, #192 @ 0xc0
8000752: 009b lsls r3, r3, #2
8000754: 589b ldr r3, [r3, r2]
8000756: 1dfa adds r2, r7, #7
8000758: 7812 ldrb r2, [r2, #0]
800075a: 0011 movs r1, r2
800075c: 2203 movs r2, #3
800075e: 400a ands r2, r1
8000760: 00d2 lsls r2, r2, #3
8000762: 21ff movs r1, #255 @ 0xff
8000764: 4091 lsls r1, r2
8000766: 000a movs r2, r1
8000768: 43d2 mvns r2, r2
800076a: 401a ands r2, r3
800076c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800076e: 683b ldr r3, [r7, #0]
8000770: 019b lsls r3, r3, #6
8000772: 22ff movs r2, #255 @ 0xff
8000774: 401a ands r2, r3
8000776: 1dfb adds r3, r7, #7
8000778: 781b ldrb r3, [r3, #0]
800077a: 0018 movs r0, r3
800077c: 2303 movs r3, #3
800077e: 4003 ands r3, r0
8000780: 00db lsls r3, r3, #3
8000782: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000784: 481f ldr r0, [pc, #124] @ (8000804 <__NVIC_SetPriority+0xd4>)
8000786: 1dfb adds r3, r7, #7
8000788: 781b ldrb r3, [r3, #0]
800078a: b25b sxtb r3, r3
800078c: 089b lsrs r3, r3, #2
800078e: 430a orrs r2, r1
8000790: 33c0 adds r3, #192 @ 0xc0
8000792: 009b lsls r3, r3, #2
8000794: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000796: e031 b.n 80007fc <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000798: 4a1b ldr r2, [pc, #108] @ (8000808 <__NVIC_SetPriority+0xd8>)
800079a: 1dfb adds r3, r7, #7
800079c: 781b ldrb r3, [r3, #0]
800079e: 0019 movs r1, r3
80007a0: 230f movs r3, #15
80007a2: 400b ands r3, r1
80007a4: 3b08 subs r3, #8
80007a6: 089b lsrs r3, r3, #2
80007a8: 3306 adds r3, #6
80007aa: 009b lsls r3, r3, #2
80007ac: 18d3 adds r3, r2, r3
80007ae: 3304 adds r3, #4
80007b0: 681b ldr r3, [r3, #0]
80007b2: 1dfa adds r2, r7, #7
80007b4: 7812 ldrb r2, [r2, #0]
80007b6: 0011 movs r1, r2
80007b8: 2203 movs r2, #3
80007ba: 400a ands r2, r1
80007bc: 00d2 lsls r2, r2, #3
80007be: 21ff movs r1, #255 @ 0xff
80007c0: 4091 lsls r1, r2
80007c2: 000a movs r2, r1
80007c4: 43d2 mvns r2, r2
80007c6: 401a ands r2, r3
80007c8: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80007ca: 683b ldr r3, [r7, #0]
80007cc: 019b lsls r3, r3, #6
80007ce: 22ff movs r2, #255 @ 0xff
80007d0: 401a ands r2, r3
80007d2: 1dfb adds r3, r7, #7
80007d4: 781b ldrb r3, [r3, #0]
80007d6: 0018 movs r0, r3
80007d8: 2303 movs r3, #3
80007da: 4003 ands r3, r0
80007dc: 00db lsls r3, r3, #3
80007de: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80007e0: 4809 ldr r0, [pc, #36] @ (8000808 <__NVIC_SetPriority+0xd8>)
80007e2: 1dfb adds r3, r7, #7
80007e4: 781b ldrb r3, [r3, #0]
80007e6: 001c movs r4, r3
80007e8: 230f movs r3, #15
80007ea: 4023 ands r3, r4
80007ec: 3b08 subs r3, #8
80007ee: 089b lsrs r3, r3, #2
80007f0: 430a orrs r2, r1
80007f2: 3306 adds r3, #6
80007f4: 009b lsls r3, r3, #2
80007f6: 18c3 adds r3, r0, r3
80007f8: 3304 adds r3, #4
80007fa: 601a str r2, [r3, #0]
}
80007fc: 46c0 nop @ (mov r8, r8)
80007fe: 46bd mov sp, r7
8000800: b003 add sp, #12
8000802: bd90 pop {r4, r7, pc}
8000804: e000e100 .word 0xe000e100
8000808: e000ed00 .word 0xe000ed00
0800080c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800080c: b580 push {r7, lr}
800080e: b082 sub sp, #8
8000810: af00 add r7, sp, #0
8000812: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000814: 687b ldr r3, [r7, #4]
8000816: 1e5a subs r2, r3, #1
8000818: 2380 movs r3, #128 @ 0x80
800081a: 045b lsls r3, r3, #17
800081c: 429a cmp r2, r3
800081e: d301 bcc.n 8000824 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8000820: 2301 movs r3, #1
8000822: e010 b.n 8000846 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000824: 4b0a ldr r3, [pc, #40] @ (8000850 <SysTick_Config+0x44>)
8000826: 687a ldr r2, [r7, #4]
8000828: 3a01 subs r2, #1
800082a: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800082c: 2301 movs r3, #1
800082e: 425b negs r3, r3
8000830: 2103 movs r1, #3
8000832: 0018 movs r0, r3
8000834: f7ff ff7c bl 8000730 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000838: 4b05 ldr r3, [pc, #20] @ (8000850 <SysTick_Config+0x44>)
800083a: 2200 movs r2, #0
800083c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800083e: 4b04 ldr r3, [pc, #16] @ (8000850 <SysTick_Config+0x44>)
8000840: 2207 movs r2, #7
8000842: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000844: 2300 movs r3, #0
}
8000846: 0018 movs r0, r3
8000848: 46bd mov sp, r7
800084a: b002 add sp, #8
800084c: bd80 pop {r7, pc}
800084e: 46c0 nop @ (mov r8, r8)
8000850: e000e010 .word 0xe000e010
08000854 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000854: b580 push {r7, lr}
8000856: b084 sub sp, #16
8000858: af00 add r7, sp, #0
800085a: 60b9 str r1, [r7, #8]
800085c: 607a str r2, [r7, #4]
800085e: 210f movs r1, #15
8000860: 187b adds r3, r7, r1
8000862: 1c02 adds r2, r0, #0
8000864: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
8000866: 68ba ldr r2, [r7, #8]
8000868: 187b adds r3, r7, r1
800086a: 781b ldrb r3, [r3, #0]
800086c: b25b sxtb r3, r3
800086e: 0011 movs r1, r2
8000870: 0018 movs r0, r3
8000872: f7ff ff5d bl 8000730 <__NVIC_SetPriority>
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
}
8000876: 46c0 nop @ (mov r8, r8)
8000878: 46bd mov sp, r7
800087a: b004 add sp, #16
800087c: bd80 pop {r7, pc}
0800087e <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800087e: b580 push {r7, lr}
8000880: b082 sub sp, #8
8000882: af00 add r7, sp, #0
8000884: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000886: 687b ldr r3, [r7, #4]
8000888: 0018 movs r0, r3
800088a: f7ff ffbf bl 800080c <SysTick_Config>
800088e: 0003 movs r3, r0
}
8000890: 0018 movs r0, r3
8000892: 46bd mov sp, r7
8000894: b002 add sp, #8
8000896: bd80 pop {r7, pc}
08000898 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000898: b580 push {r7, lr}
800089a: b086 sub sp, #24
800089c: af00 add r7, sp, #0
800089e: 6078 str r0, [r7, #4]
80008a0: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80008a2: 2300 movs r3, #0
80008a4: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80008a6: e14f b.n 8000b48 <HAL_GPIO_Init+0x2b0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80008a8: 683b ldr r3, [r7, #0]
80008aa: 681b ldr r3, [r3, #0]
80008ac: 2101 movs r1, #1
80008ae: 697a ldr r2, [r7, #20]
80008b0: 4091 lsls r1, r2
80008b2: 000a movs r2, r1
80008b4: 4013 ands r3, r2
80008b6: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
80008b8: 68fb ldr r3, [r7, #12]
80008ba: 2b00 cmp r3, #0
80008bc: d100 bne.n 80008c0 <HAL_GPIO_Init+0x28>
80008be: e140 b.n 8000b42 <HAL_GPIO_Init+0x2aa>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
80008c0: 683b ldr r3, [r7, #0]
80008c2: 685b ldr r3, [r3, #4]
80008c4: 2203 movs r2, #3
80008c6: 4013 ands r3, r2
80008c8: 2b01 cmp r3, #1
80008ca: d005 beq.n 80008d8 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80008cc: 683b ldr r3, [r7, #0]
80008ce: 685b ldr r3, [r3, #4]
80008d0: 2203 movs r2, #3
80008d2: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
80008d4: 2b02 cmp r3, #2
80008d6: d130 bne.n 800093a <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80008d8: 687b ldr r3, [r7, #4]
80008da: 689b ldr r3, [r3, #8]
80008dc: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
80008de: 697b ldr r3, [r7, #20]
80008e0: 005b lsls r3, r3, #1
80008e2: 2203 movs r2, #3
80008e4: 409a lsls r2, r3
80008e6: 0013 movs r3, r2
80008e8: 43da mvns r2, r3
80008ea: 693b ldr r3, [r7, #16]
80008ec: 4013 ands r3, r2
80008ee: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
80008f0: 683b ldr r3, [r7, #0]
80008f2: 68da ldr r2, [r3, #12]
80008f4: 697b ldr r3, [r7, #20]
80008f6: 005b lsls r3, r3, #1
80008f8: 409a lsls r2, r3
80008fa: 0013 movs r3, r2
80008fc: 693a ldr r2, [r7, #16]
80008fe: 4313 orrs r3, r2
8000900: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000902: 687b ldr r3, [r7, #4]
8000904: 693a ldr r2, [r7, #16]
8000906: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000908: 687b ldr r3, [r7, #4]
800090a: 685b ldr r3, [r3, #4]
800090c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800090e: 2201 movs r2, #1
8000910: 697b ldr r3, [r7, #20]
8000912: 409a lsls r2, r3
8000914: 0013 movs r3, r2
8000916: 43da mvns r2, r3
8000918: 693b ldr r3, [r7, #16]
800091a: 4013 ands r3, r2
800091c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800091e: 683b ldr r3, [r7, #0]
8000920: 685b ldr r3, [r3, #4]
8000922: 091b lsrs r3, r3, #4
8000924: 2201 movs r2, #1
8000926: 401a ands r2, r3
8000928: 697b ldr r3, [r7, #20]
800092a: 409a lsls r2, r3
800092c: 0013 movs r3, r2
800092e: 693a ldr r2, [r7, #16]
8000930: 4313 orrs r3, r2
8000932: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000934: 687b ldr r3, [r7, #4]
8000936: 693a ldr r2, [r7, #16]
8000938: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
800093a: 683b ldr r3, [r7, #0]
800093c: 685b ldr r3, [r3, #4]
800093e: 2203 movs r2, #3
8000940: 4013 ands r3, r2
8000942: 2b03 cmp r3, #3
8000944: d017 beq.n 8000976 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000946: 687b ldr r3, [r7, #4]
8000948: 68db ldr r3, [r3, #12]
800094a: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
800094c: 697b ldr r3, [r7, #20]
800094e: 005b lsls r3, r3, #1
8000950: 2203 movs r2, #3
8000952: 409a lsls r2, r3
8000954: 0013 movs r3, r2
8000956: 43da mvns r2, r3
8000958: 693b ldr r3, [r7, #16]
800095a: 4013 ands r3, r2
800095c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
800095e: 683b ldr r3, [r7, #0]
8000960: 689a ldr r2, [r3, #8]
8000962: 697b ldr r3, [r7, #20]
8000964: 005b lsls r3, r3, #1
8000966: 409a lsls r2, r3
8000968: 0013 movs r3, r2
800096a: 693a ldr r2, [r7, #16]
800096c: 4313 orrs r3, r2
800096e: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000970: 687b ldr r3, [r7, #4]
8000972: 693a ldr r2, [r7, #16]
8000974: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000976: 683b ldr r3, [r7, #0]
8000978: 685b ldr r3, [r3, #4]
800097a: 2203 movs r2, #3
800097c: 4013 ands r3, r2
800097e: 2b02 cmp r3, #2
8000980: d123 bne.n 80009ca <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8000982: 697b ldr r3, [r7, #20]
8000984: 08da lsrs r2, r3, #3
8000986: 687b ldr r3, [r7, #4]
8000988: 3208 adds r2, #8
800098a: 0092 lsls r2, r2, #2
800098c: 58d3 ldr r3, [r2, r3]
800098e: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8000990: 697b ldr r3, [r7, #20]
8000992: 2207 movs r2, #7
8000994: 4013 ands r3, r2
8000996: 009b lsls r3, r3, #2
8000998: 220f movs r2, #15
800099a: 409a lsls r2, r3
800099c: 0013 movs r3, r2
800099e: 43da mvns r2, r3
80009a0: 693b ldr r3, [r7, #16]
80009a2: 4013 ands r3, r2
80009a4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80009a6: 683b ldr r3, [r7, #0]
80009a8: 691a ldr r2, [r3, #16]
80009aa: 697b ldr r3, [r7, #20]
80009ac: 2107 movs r1, #7
80009ae: 400b ands r3, r1
80009b0: 009b lsls r3, r3, #2
80009b2: 409a lsls r2, r3
80009b4: 0013 movs r3, r2
80009b6: 693a ldr r2, [r7, #16]
80009b8: 4313 orrs r3, r2
80009ba: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
80009bc: 697b ldr r3, [r7, #20]
80009be: 08da lsrs r2, r3, #3
80009c0: 687b ldr r3, [r7, #4]
80009c2: 3208 adds r2, #8
80009c4: 0092 lsls r2, r2, #2
80009c6: 6939 ldr r1, [r7, #16]
80009c8: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80009ca: 687b ldr r3, [r7, #4]
80009cc: 681b ldr r3, [r3, #0]
80009ce: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
80009d0: 697b ldr r3, [r7, #20]
80009d2: 005b lsls r3, r3, #1
80009d4: 2203 movs r2, #3
80009d6: 409a lsls r2, r3
80009d8: 0013 movs r3, r2
80009da: 43da mvns r2, r3
80009dc: 693b ldr r3, [r7, #16]
80009de: 4013 ands r3, r2
80009e0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
80009e2: 683b ldr r3, [r7, #0]
80009e4: 685b ldr r3, [r3, #4]
80009e6: 2203 movs r2, #3
80009e8: 401a ands r2, r3
80009ea: 697b ldr r3, [r7, #20]
80009ec: 005b lsls r3, r3, #1
80009ee: 409a lsls r2, r3
80009f0: 0013 movs r3, r2
80009f2: 693a ldr r2, [r7, #16]
80009f4: 4313 orrs r3, r2
80009f6: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
80009f8: 687b ldr r3, [r7, #4]
80009fa: 693a ldr r2, [r7, #16]
80009fc: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
80009fe: 683b ldr r3, [r7, #0]
8000a00: 685a ldr r2, [r3, #4]
8000a02: 23c0 movs r3, #192 @ 0xc0
8000a04: 029b lsls r3, r3, #10
8000a06: 4013 ands r3, r2
8000a08: d100 bne.n 8000a0c <HAL_GPIO_Init+0x174>
8000a0a: e09a b.n 8000b42 <HAL_GPIO_Init+0x2aa>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000a0c: 4b54 ldr r3, [pc, #336] @ (8000b60 <HAL_GPIO_Init+0x2c8>)
8000a0e: 699a ldr r2, [r3, #24]
8000a10: 4b53 ldr r3, [pc, #332] @ (8000b60 <HAL_GPIO_Init+0x2c8>)
8000a12: 2101 movs r1, #1
8000a14: 430a orrs r2, r1
8000a16: 619a str r2, [r3, #24]
8000a18: 4b51 ldr r3, [pc, #324] @ (8000b60 <HAL_GPIO_Init+0x2c8>)
8000a1a: 699b ldr r3, [r3, #24]
8000a1c: 2201 movs r2, #1
8000a1e: 4013 ands r3, r2
8000a20: 60bb str r3, [r7, #8]
8000a22: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8000a24: 4a4f ldr r2, [pc, #316] @ (8000b64 <HAL_GPIO_Init+0x2cc>)
8000a26: 697b ldr r3, [r7, #20]
8000a28: 089b lsrs r3, r3, #2
8000a2a: 3302 adds r3, #2
8000a2c: 009b lsls r3, r3, #2
8000a2e: 589b ldr r3, [r3, r2]
8000a30: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8000a32: 697b ldr r3, [r7, #20]
8000a34: 2203 movs r2, #3
8000a36: 4013 ands r3, r2
8000a38: 009b lsls r3, r3, #2
8000a3a: 220f movs r2, #15
8000a3c: 409a lsls r2, r3
8000a3e: 0013 movs r3, r2
8000a40: 43da mvns r2, r3
8000a42: 693b ldr r3, [r7, #16]
8000a44: 4013 ands r3, r2
8000a46: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8000a48: 687a ldr r2, [r7, #4]
8000a4a: 2390 movs r3, #144 @ 0x90
8000a4c: 05db lsls r3, r3, #23
8000a4e: 429a cmp r2, r3
8000a50: d013 beq.n 8000a7a <HAL_GPIO_Init+0x1e2>
8000a52: 687b ldr r3, [r7, #4]
8000a54: 4a44 ldr r2, [pc, #272] @ (8000b68 <HAL_GPIO_Init+0x2d0>)
8000a56: 4293 cmp r3, r2
8000a58: d00d beq.n 8000a76 <HAL_GPIO_Init+0x1de>
8000a5a: 687b ldr r3, [r7, #4]
8000a5c: 4a43 ldr r2, [pc, #268] @ (8000b6c <HAL_GPIO_Init+0x2d4>)
8000a5e: 4293 cmp r3, r2
8000a60: d007 beq.n 8000a72 <HAL_GPIO_Init+0x1da>
8000a62: 687b ldr r3, [r7, #4]
8000a64: 4a42 ldr r2, [pc, #264] @ (8000b70 <HAL_GPIO_Init+0x2d8>)
8000a66: 4293 cmp r3, r2
8000a68: d101 bne.n 8000a6e <HAL_GPIO_Init+0x1d6>
8000a6a: 2303 movs r3, #3
8000a6c: e006 b.n 8000a7c <HAL_GPIO_Init+0x1e4>
8000a6e: 2305 movs r3, #5
8000a70: e004 b.n 8000a7c <HAL_GPIO_Init+0x1e4>
8000a72: 2302 movs r3, #2
8000a74: e002 b.n 8000a7c <HAL_GPIO_Init+0x1e4>
8000a76: 2301 movs r3, #1
8000a78: e000 b.n 8000a7c <HAL_GPIO_Init+0x1e4>
8000a7a: 2300 movs r3, #0
8000a7c: 697a ldr r2, [r7, #20]
8000a7e: 2103 movs r1, #3
8000a80: 400a ands r2, r1
8000a82: 0092 lsls r2, r2, #2
8000a84: 4093 lsls r3, r2
8000a86: 693a ldr r2, [r7, #16]
8000a88: 4313 orrs r3, r2
8000a8a: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8000a8c: 4935 ldr r1, [pc, #212] @ (8000b64 <HAL_GPIO_Init+0x2cc>)
8000a8e: 697b ldr r3, [r7, #20]
8000a90: 089b lsrs r3, r3, #2
8000a92: 3302 adds r3, #2
8000a94: 009b lsls r3, r3, #2
8000a96: 693a ldr r2, [r7, #16]
8000a98: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000a9a: 4b36 ldr r3, [pc, #216] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000a9c: 689b ldr r3, [r3, #8]
8000a9e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000aa0: 68fb ldr r3, [r7, #12]
8000aa2: 43da mvns r2, r3
8000aa4: 693b ldr r3, [r7, #16]
8000aa6: 4013 ands r3, r2
8000aa8: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8000aaa: 683b ldr r3, [r7, #0]
8000aac: 685a ldr r2, [r3, #4]
8000aae: 2380 movs r3, #128 @ 0x80
8000ab0: 035b lsls r3, r3, #13
8000ab2: 4013 ands r3, r2
8000ab4: d003 beq.n 8000abe <HAL_GPIO_Init+0x226>
{
temp |= iocurrent;
8000ab6: 693a ldr r2, [r7, #16]
8000ab8: 68fb ldr r3, [r7, #12]
8000aba: 4313 orrs r3, r2
8000abc: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8000abe: 4b2d ldr r3, [pc, #180] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000ac0: 693a ldr r2, [r7, #16]
8000ac2: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
8000ac4: 4b2b ldr r3, [pc, #172] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000ac6: 68db ldr r3, [r3, #12]
8000ac8: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000aca: 68fb ldr r3, [r7, #12]
8000acc: 43da mvns r2, r3
8000ace: 693b ldr r3, [r7, #16]
8000ad0: 4013 ands r3, r2
8000ad2: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8000ad4: 683b ldr r3, [r7, #0]
8000ad6: 685a ldr r2, [r3, #4]
8000ad8: 2380 movs r3, #128 @ 0x80
8000ada: 039b lsls r3, r3, #14
8000adc: 4013 ands r3, r2
8000ade: d003 beq.n 8000ae8 <HAL_GPIO_Init+0x250>
{
temp |= iocurrent;
8000ae0: 693a ldr r2, [r7, #16]
8000ae2: 68fb ldr r3, [r7, #12]
8000ae4: 4313 orrs r3, r2
8000ae6: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8000ae8: 4b22 ldr r3, [pc, #136] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000aea: 693a ldr r2, [r7, #16]
8000aec: 60da str r2, [r3, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR;
8000aee: 4b21 ldr r3, [pc, #132] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000af0: 685b ldr r3, [r3, #4]
8000af2: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000af4: 68fb ldr r3, [r7, #12]
8000af6: 43da mvns r2, r3
8000af8: 693b ldr r3, [r7, #16]
8000afa: 4013 ands r3, r2
8000afc: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8000afe: 683b ldr r3, [r7, #0]
8000b00: 685a ldr r2, [r3, #4]
8000b02: 2380 movs r3, #128 @ 0x80
8000b04: 029b lsls r3, r3, #10
8000b06: 4013 ands r3, r2
8000b08: d003 beq.n 8000b12 <HAL_GPIO_Init+0x27a>
{
temp |= iocurrent;
8000b0a: 693a ldr r2, [r7, #16]
8000b0c: 68fb ldr r3, [r7, #12]
8000b0e: 4313 orrs r3, r2
8000b10: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8000b12: 4b18 ldr r3, [pc, #96] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000b14: 693a ldr r2, [r7, #16]
8000b16: 605a str r2, [r3, #4]
temp = EXTI->IMR;
8000b18: 4b16 ldr r3, [pc, #88] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000b1a: 681b ldr r3, [r3, #0]
8000b1c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000b1e: 68fb ldr r3, [r7, #12]
8000b20: 43da mvns r2, r3
8000b22: 693b ldr r3, [r7, #16]
8000b24: 4013 ands r3, r2
8000b26: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8000b28: 683b ldr r3, [r7, #0]
8000b2a: 685a ldr r2, [r3, #4]
8000b2c: 2380 movs r3, #128 @ 0x80
8000b2e: 025b lsls r3, r3, #9
8000b30: 4013 ands r3, r2
8000b32: d003 beq.n 8000b3c <HAL_GPIO_Init+0x2a4>
{
temp |= iocurrent;
8000b34: 693a ldr r2, [r7, #16]
8000b36: 68fb ldr r3, [r7, #12]
8000b38: 4313 orrs r3, r2
8000b3a: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8000b3c: 4b0d ldr r3, [pc, #52] @ (8000b74 <HAL_GPIO_Init+0x2dc>)
8000b3e: 693a ldr r2, [r7, #16]
8000b40: 601a str r2, [r3, #0]
}
}
position++;
8000b42: 697b ldr r3, [r7, #20]
8000b44: 3301 adds r3, #1
8000b46: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000b48: 683b ldr r3, [r7, #0]
8000b4a: 681a ldr r2, [r3, #0]
8000b4c: 697b ldr r3, [r7, #20]
8000b4e: 40da lsrs r2, r3
8000b50: 1e13 subs r3, r2, #0
8000b52: d000 beq.n 8000b56 <HAL_GPIO_Init+0x2be>
8000b54: e6a8 b.n 80008a8 <HAL_GPIO_Init+0x10>
}
}
8000b56: 46c0 nop @ (mov r8, r8)
8000b58: 46c0 nop @ (mov r8, r8)
8000b5a: 46bd mov sp, r7
8000b5c: b006 add sp, #24
8000b5e: bd80 pop {r7, pc}
8000b60: 40021000 .word 0x40021000
8000b64: 40010000 .word 0x40010000
8000b68: 48000400 .word 0x48000400
8000b6c: 48000800 .word 0x48000800
8000b70: 48000c00 .word 0x48000c00
8000b74: 40010400 .word 0x40010400
08000b78 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000b78: b580 push {r7, lr}
8000b7a: b082 sub sp, #8
8000b7c: af00 add r7, sp, #0
8000b7e: 6078 str r0, [r7, #4]
8000b80: 0008 movs r0, r1
8000b82: 0011 movs r1, r2
8000b84: 1cbb adds r3, r7, #2
8000b86: 1c02 adds r2, r0, #0
8000b88: 801a strh r2, [r3, #0]
8000b8a: 1c7b adds r3, r7, #1
8000b8c: 1c0a adds r2, r1, #0
8000b8e: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8000b90: 1c7b adds r3, r7, #1
8000b92: 781b ldrb r3, [r3, #0]
8000b94: 2b00 cmp r3, #0
8000b96: d004 beq.n 8000ba2 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8000b98: 1cbb adds r3, r7, #2
8000b9a: 881a ldrh r2, [r3, #0]
8000b9c: 687b ldr r3, [r7, #4]
8000b9e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8000ba0: e003 b.n 8000baa <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8000ba2: 1cbb adds r3, r7, #2
8000ba4: 881a ldrh r2, [r3, #0]
8000ba6: 687b ldr r3, [r7, #4]
8000ba8: 629a str r2, [r3, #40] @ 0x28
}
8000baa: 46c0 nop @ (mov r8, r8)
8000bac: 46bd mov sp, r7
8000bae: b002 add sp, #8
8000bb0: bd80 pop {r7, pc}
...
08000bb4 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000bb4: b580 push {r7, lr}
8000bb6: b088 sub sp, #32
8000bb8: af00 add r7, sp, #0
8000bba: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000bbc: 687b ldr r3, [r7, #4]
8000bbe: 2b00 cmp r3, #0
8000bc0: d101 bne.n 8000bc6 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000bc2: 2301 movs r3, #1
8000bc4: e301 b.n 80011ca <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000bc6: 687b ldr r3, [r7, #4]
8000bc8: 681b ldr r3, [r3, #0]
8000bca: 2201 movs r2, #1
8000bcc: 4013 ands r3, r2
8000bce: d100 bne.n 8000bd2 <HAL_RCC_OscConfig+0x1e>
8000bd0: e08d b.n 8000cee <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000bd2: 4bc3 ldr r3, [pc, #780] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000bd4: 685b ldr r3, [r3, #4]
8000bd6: 220c movs r2, #12
8000bd8: 4013 ands r3, r2
8000bda: 2b04 cmp r3, #4
8000bdc: d00e beq.n 8000bfc <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000bde: 4bc0 ldr r3, [pc, #768] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000be0: 685b ldr r3, [r3, #4]
8000be2: 220c movs r2, #12
8000be4: 4013 ands r3, r2
8000be6: 2b08 cmp r3, #8
8000be8: d116 bne.n 8000c18 <HAL_RCC_OscConfig+0x64>
8000bea: 4bbd ldr r3, [pc, #756] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000bec: 685a ldr r2, [r3, #4]
8000bee: 2380 movs r3, #128 @ 0x80
8000bf0: 025b lsls r3, r3, #9
8000bf2: 401a ands r2, r3
8000bf4: 2380 movs r3, #128 @ 0x80
8000bf6: 025b lsls r3, r3, #9
8000bf8: 429a cmp r2, r3
8000bfa: d10d bne.n 8000c18 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000bfc: 4bb8 ldr r3, [pc, #736] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000bfe: 681a ldr r2, [r3, #0]
8000c00: 2380 movs r3, #128 @ 0x80
8000c02: 029b lsls r3, r3, #10
8000c04: 4013 ands r3, r2
8000c06: d100 bne.n 8000c0a <HAL_RCC_OscConfig+0x56>
8000c08: e070 b.n 8000cec <HAL_RCC_OscConfig+0x138>
8000c0a: 687b ldr r3, [r7, #4]
8000c0c: 685b ldr r3, [r3, #4]
8000c0e: 2b00 cmp r3, #0
8000c10: d000 beq.n 8000c14 <HAL_RCC_OscConfig+0x60>
8000c12: e06b b.n 8000cec <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
8000c14: 2301 movs r3, #1
8000c16: e2d8 b.n 80011ca <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 685b ldr r3, [r3, #4]
8000c1c: 2b01 cmp r3, #1
8000c1e: d107 bne.n 8000c30 <HAL_RCC_OscConfig+0x7c>
8000c20: 4baf ldr r3, [pc, #700] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c22: 681a ldr r2, [r3, #0]
8000c24: 4bae ldr r3, [pc, #696] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c26: 2180 movs r1, #128 @ 0x80
8000c28: 0249 lsls r1, r1, #9
8000c2a: 430a orrs r2, r1
8000c2c: 601a str r2, [r3, #0]
8000c2e: e02f b.n 8000c90 <HAL_RCC_OscConfig+0xdc>
8000c30: 687b ldr r3, [r7, #4]
8000c32: 685b ldr r3, [r3, #4]
8000c34: 2b00 cmp r3, #0
8000c36: d10c bne.n 8000c52 <HAL_RCC_OscConfig+0x9e>
8000c38: 4ba9 ldr r3, [pc, #676] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c3a: 681a ldr r2, [r3, #0]
8000c3c: 4ba8 ldr r3, [pc, #672] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c3e: 49a9 ldr r1, [pc, #676] @ (8000ee4 <HAL_RCC_OscConfig+0x330>)
8000c40: 400a ands r2, r1
8000c42: 601a str r2, [r3, #0]
8000c44: 4ba6 ldr r3, [pc, #664] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c46: 681a ldr r2, [r3, #0]
8000c48: 4ba5 ldr r3, [pc, #660] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c4a: 49a7 ldr r1, [pc, #668] @ (8000ee8 <HAL_RCC_OscConfig+0x334>)
8000c4c: 400a ands r2, r1
8000c4e: 601a str r2, [r3, #0]
8000c50: e01e b.n 8000c90 <HAL_RCC_OscConfig+0xdc>
8000c52: 687b ldr r3, [r7, #4]
8000c54: 685b ldr r3, [r3, #4]
8000c56: 2b05 cmp r3, #5
8000c58: d10e bne.n 8000c78 <HAL_RCC_OscConfig+0xc4>
8000c5a: 4ba1 ldr r3, [pc, #644] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c5c: 681a ldr r2, [r3, #0]
8000c5e: 4ba0 ldr r3, [pc, #640] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c60: 2180 movs r1, #128 @ 0x80
8000c62: 02c9 lsls r1, r1, #11
8000c64: 430a orrs r2, r1
8000c66: 601a str r2, [r3, #0]
8000c68: 4b9d ldr r3, [pc, #628] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c6a: 681a ldr r2, [r3, #0]
8000c6c: 4b9c ldr r3, [pc, #624] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c6e: 2180 movs r1, #128 @ 0x80
8000c70: 0249 lsls r1, r1, #9
8000c72: 430a orrs r2, r1
8000c74: 601a str r2, [r3, #0]
8000c76: e00b b.n 8000c90 <HAL_RCC_OscConfig+0xdc>
8000c78: 4b99 ldr r3, [pc, #612] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c7a: 681a ldr r2, [r3, #0]
8000c7c: 4b98 ldr r3, [pc, #608] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c7e: 4999 ldr r1, [pc, #612] @ (8000ee4 <HAL_RCC_OscConfig+0x330>)
8000c80: 400a ands r2, r1
8000c82: 601a str r2, [r3, #0]
8000c84: 4b96 ldr r3, [pc, #600] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c86: 681a ldr r2, [r3, #0]
8000c88: 4b95 ldr r3, [pc, #596] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000c8a: 4997 ldr r1, [pc, #604] @ (8000ee8 <HAL_RCC_OscConfig+0x334>)
8000c8c: 400a ands r2, r1
8000c8e: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000c90: 687b ldr r3, [r7, #4]
8000c92: 685b ldr r3, [r3, #4]
8000c94: 2b00 cmp r3, #0
8000c96: d014 beq.n 8000cc2 <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c98: f7ff fd40 bl 800071c <HAL_GetTick>
8000c9c: 0003 movs r3, r0
8000c9e: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000ca0: e008 b.n 8000cb4 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000ca2: f7ff fd3b bl 800071c <HAL_GetTick>
8000ca6: 0002 movs r2, r0
8000ca8: 69bb ldr r3, [r7, #24]
8000caa: 1ad3 subs r3, r2, r3
8000cac: 2b64 cmp r3, #100 @ 0x64
8000cae: d901 bls.n 8000cb4 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
8000cb0: 2303 movs r3, #3
8000cb2: e28a b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000cb4: 4b8a ldr r3, [pc, #552] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000cb6: 681a ldr r2, [r3, #0]
8000cb8: 2380 movs r3, #128 @ 0x80
8000cba: 029b lsls r3, r3, #10
8000cbc: 4013 ands r3, r2
8000cbe: d0f0 beq.n 8000ca2 <HAL_RCC_OscConfig+0xee>
8000cc0: e015 b.n 8000cee <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000cc2: f7ff fd2b bl 800071c <HAL_GetTick>
8000cc6: 0003 movs r3, r0
8000cc8: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000cca: e008 b.n 8000cde <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000ccc: f7ff fd26 bl 800071c <HAL_GetTick>
8000cd0: 0002 movs r2, r0
8000cd2: 69bb ldr r3, [r7, #24]
8000cd4: 1ad3 subs r3, r2, r3
8000cd6: 2b64 cmp r3, #100 @ 0x64
8000cd8: d901 bls.n 8000cde <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
8000cda: 2303 movs r3, #3
8000cdc: e275 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000cde: 4b80 ldr r3, [pc, #512] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000ce0: 681a ldr r2, [r3, #0]
8000ce2: 2380 movs r3, #128 @ 0x80
8000ce4: 029b lsls r3, r3, #10
8000ce6: 4013 ands r3, r2
8000ce8: d1f0 bne.n 8000ccc <HAL_RCC_OscConfig+0x118>
8000cea: e000 b.n 8000cee <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000cec: 46c0 nop @ (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000cee: 687b ldr r3, [r7, #4]
8000cf0: 681b ldr r3, [r3, #0]
8000cf2: 2202 movs r2, #2
8000cf4: 4013 ands r3, r2
8000cf6: d100 bne.n 8000cfa <HAL_RCC_OscConfig+0x146>
8000cf8: e069 b.n 8000dce <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000cfa: 4b79 ldr r3, [pc, #484] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000cfc: 685b ldr r3, [r3, #4]
8000cfe: 220c movs r2, #12
8000d00: 4013 ands r3, r2
8000d02: d00b beq.n 8000d1c <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8000d04: 4b76 ldr r3, [pc, #472] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d06: 685b ldr r3, [r3, #4]
8000d08: 220c movs r2, #12
8000d0a: 4013 ands r3, r2
8000d0c: 2b08 cmp r3, #8
8000d0e: d11c bne.n 8000d4a <HAL_RCC_OscConfig+0x196>
8000d10: 4b73 ldr r3, [pc, #460] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d12: 685a ldr r2, [r3, #4]
8000d14: 2380 movs r3, #128 @ 0x80
8000d16: 025b lsls r3, r3, #9
8000d18: 4013 ands r3, r2
8000d1a: d116 bne.n 8000d4a <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d1c: 4b70 ldr r3, [pc, #448] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d1e: 681b ldr r3, [r3, #0]
8000d20: 2202 movs r2, #2
8000d22: 4013 ands r3, r2
8000d24: d005 beq.n 8000d32 <HAL_RCC_OscConfig+0x17e>
8000d26: 687b ldr r3, [r7, #4]
8000d28: 68db ldr r3, [r3, #12]
8000d2a: 2b01 cmp r3, #1
8000d2c: d001 beq.n 8000d32 <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
8000d2e: 2301 movs r3, #1
8000d30: e24b b.n 80011ca <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d32: 4b6b ldr r3, [pc, #428] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d34: 681b ldr r3, [r3, #0]
8000d36: 22f8 movs r2, #248 @ 0xf8
8000d38: 4393 bics r3, r2
8000d3a: 0019 movs r1, r3
8000d3c: 687b ldr r3, [r7, #4]
8000d3e: 691b ldr r3, [r3, #16]
8000d40: 00da lsls r2, r3, #3
8000d42: 4b67 ldr r3, [pc, #412] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d44: 430a orrs r2, r1
8000d46: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d48: e041 b.n 8000dce <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000d4a: 687b ldr r3, [r7, #4]
8000d4c: 68db ldr r3, [r3, #12]
8000d4e: 2b00 cmp r3, #0
8000d50: d024 beq.n 8000d9c <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000d52: 4b63 ldr r3, [pc, #396] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d54: 681a ldr r2, [r3, #0]
8000d56: 4b62 ldr r3, [pc, #392] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d58: 2101 movs r1, #1
8000d5a: 430a orrs r2, r1
8000d5c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d5e: f7ff fcdd bl 800071c <HAL_GetTick>
8000d62: 0003 movs r3, r0
8000d64: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000d66: e008 b.n 8000d7a <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000d68: f7ff fcd8 bl 800071c <HAL_GetTick>
8000d6c: 0002 movs r2, r0
8000d6e: 69bb ldr r3, [r7, #24]
8000d70: 1ad3 subs r3, r2, r3
8000d72: 2b02 cmp r3, #2
8000d74: d901 bls.n 8000d7a <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
8000d76: 2303 movs r3, #3
8000d78: e227 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000d7a: 4b59 ldr r3, [pc, #356] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d7c: 681b ldr r3, [r3, #0]
8000d7e: 2202 movs r2, #2
8000d80: 4013 ands r3, r2
8000d82: d0f1 beq.n 8000d68 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d84: 4b56 ldr r3, [pc, #344] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d86: 681b ldr r3, [r3, #0]
8000d88: 22f8 movs r2, #248 @ 0xf8
8000d8a: 4393 bics r3, r2
8000d8c: 0019 movs r1, r3
8000d8e: 687b ldr r3, [r7, #4]
8000d90: 691b ldr r3, [r3, #16]
8000d92: 00da lsls r2, r3, #3
8000d94: 4b52 ldr r3, [pc, #328] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d96: 430a orrs r2, r1
8000d98: 601a str r2, [r3, #0]
8000d9a: e018 b.n 8000dce <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000d9c: 4b50 ldr r3, [pc, #320] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000d9e: 681a ldr r2, [r3, #0]
8000da0: 4b4f ldr r3, [pc, #316] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000da2: 2101 movs r1, #1
8000da4: 438a bics r2, r1
8000da6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000da8: f7ff fcb8 bl 800071c <HAL_GetTick>
8000dac: 0003 movs r3, r0
8000dae: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000db0: e008 b.n 8000dc4 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000db2: f7ff fcb3 bl 800071c <HAL_GetTick>
8000db6: 0002 movs r2, r0
8000db8: 69bb ldr r3, [r7, #24]
8000dba: 1ad3 subs r3, r2, r3
8000dbc: 2b02 cmp r3, #2
8000dbe: d901 bls.n 8000dc4 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
8000dc0: 2303 movs r3, #3
8000dc2: e202 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000dc4: 4b46 ldr r3, [pc, #280] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000dc6: 681b ldr r3, [r3, #0]
8000dc8: 2202 movs r2, #2
8000dca: 4013 ands r3, r2
8000dcc: d1f1 bne.n 8000db2 <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000dce: 687b ldr r3, [r7, #4]
8000dd0: 681b ldr r3, [r3, #0]
8000dd2: 2208 movs r2, #8
8000dd4: 4013 ands r3, r2
8000dd6: d036 beq.n 8000e46 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000dd8: 687b ldr r3, [r7, #4]
8000dda: 69db ldr r3, [r3, #28]
8000ddc: 2b00 cmp r3, #0
8000dde: d019 beq.n 8000e14 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000de0: 4b3f ldr r3, [pc, #252] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000de2: 6a5a ldr r2, [r3, #36] @ 0x24
8000de4: 4b3e ldr r3, [pc, #248] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000de6: 2101 movs r1, #1
8000de8: 430a orrs r2, r1
8000dea: 625a str r2, [r3, #36] @ 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000dec: f7ff fc96 bl 800071c <HAL_GetTick>
8000df0: 0003 movs r3, r0
8000df2: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000df4: e008 b.n 8000e08 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000df6: f7ff fc91 bl 800071c <HAL_GetTick>
8000dfa: 0002 movs r2, r0
8000dfc: 69bb ldr r3, [r7, #24]
8000dfe: 1ad3 subs r3, r2, r3
8000e00: 2b02 cmp r3, #2
8000e02: d901 bls.n 8000e08 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
8000e04: 2303 movs r3, #3
8000e06: e1e0 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000e08: 4b35 ldr r3, [pc, #212] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e0a: 6a5b ldr r3, [r3, #36] @ 0x24
8000e0c: 2202 movs r2, #2
8000e0e: 4013 ands r3, r2
8000e10: d0f1 beq.n 8000df6 <HAL_RCC_OscConfig+0x242>
8000e12: e018 b.n 8000e46 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000e14: 4b32 ldr r3, [pc, #200] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e16: 6a5a ldr r2, [r3, #36] @ 0x24
8000e18: 4b31 ldr r3, [pc, #196] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e1a: 2101 movs r1, #1
8000e1c: 438a bics r2, r1
8000e1e: 625a str r2, [r3, #36] @ 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e20: f7ff fc7c bl 800071c <HAL_GetTick>
8000e24: 0003 movs r3, r0
8000e26: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e28: e008 b.n 8000e3c <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000e2a: f7ff fc77 bl 800071c <HAL_GetTick>
8000e2e: 0002 movs r2, r0
8000e30: 69bb ldr r3, [r7, #24]
8000e32: 1ad3 subs r3, r2, r3
8000e34: 2b02 cmp r3, #2
8000e36: d901 bls.n 8000e3c <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
8000e38: 2303 movs r3, #3
8000e3a: e1c6 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e3c: 4b28 ldr r3, [pc, #160] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e3e: 6a5b ldr r3, [r3, #36] @ 0x24
8000e40: 2202 movs r2, #2
8000e42: 4013 ands r3, r2
8000e44: d1f1 bne.n 8000e2a <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000e46: 687b ldr r3, [r7, #4]
8000e48: 681b ldr r3, [r3, #0]
8000e4a: 2204 movs r2, #4
8000e4c: 4013 ands r3, r2
8000e4e: d100 bne.n 8000e52 <HAL_RCC_OscConfig+0x29e>
8000e50: e0b4 b.n 8000fbc <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
8000e52: 201f movs r0, #31
8000e54: 183b adds r3, r7, r0
8000e56: 2200 movs r2, #0
8000e58: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8000e5a: 4b21 ldr r3, [pc, #132] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e5c: 69da ldr r2, [r3, #28]
8000e5e: 2380 movs r3, #128 @ 0x80
8000e60: 055b lsls r3, r3, #21
8000e62: 4013 ands r3, r2
8000e64: d110 bne.n 8000e88 <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000e66: 4b1e ldr r3, [pc, #120] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e68: 69da ldr r2, [r3, #28]
8000e6a: 4b1d ldr r3, [pc, #116] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e6c: 2180 movs r1, #128 @ 0x80
8000e6e: 0549 lsls r1, r1, #21
8000e70: 430a orrs r2, r1
8000e72: 61da str r2, [r3, #28]
8000e74: 4b1a ldr r3, [pc, #104] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000e76: 69da ldr r2, [r3, #28]
8000e78: 2380 movs r3, #128 @ 0x80
8000e7a: 055b lsls r3, r3, #21
8000e7c: 4013 ands r3, r2
8000e7e: 60fb str r3, [r7, #12]
8000e80: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8000e82: 183b adds r3, r7, r0
8000e84: 2201 movs r2, #1
8000e86: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000e88: 4b18 ldr r3, [pc, #96] @ (8000eec <HAL_RCC_OscConfig+0x338>)
8000e8a: 681a ldr r2, [r3, #0]
8000e8c: 2380 movs r3, #128 @ 0x80
8000e8e: 005b lsls r3, r3, #1
8000e90: 4013 ands r3, r2
8000e92: d11a bne.n 8000eca <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000e94: 4b15 ldr r3, [pc, #84] @ (8000eec <HAL_RCC_OscConfig+0x338>)
8000e96: 681a ldr r2, [r3, #0]
8000e98: 4b14 ldr r3, [pc, #80] @ (8000eec <HAL_RCC_OscConfig+0x338>)
8000e9a: 2180 movs r1, #128 @ 0x80
8000e9c: 0049 lsls r1, r1, #1
8000e9e: 430a orrs r2, r1
8000ea0: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000ea2: f7ff fc3b bl 800071c <HAL_GetTick>
8000ea6: 0003 movs r3, r0
8000ea8: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000eaa: e008 b.n 8000ebe <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000eac: f7ff fc36 bl 800071c <HAL_GetTick>
8000eb0: 0002 movs r2, r0
8000eb2: 69bb ldr r3, [r7, #24]
8000eb4: 1ad3 subs r3, r2, r3
8000eb6: 2b64 cmp r3, #100 @ 0x64
8000eb8: d901 bls.n 8000ebe <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8000eba: 2303 movs r3, #3
8000ebc: e185 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000ebe: 4b0b ldr r3, [pc, #44] @ (8000eec <HAL_RCC_OscConfig+0x338>)
8000ec0: 681a ldr r2, [r3, #0]
8000ec2: 2380 movs r3, #128 @ 0x80
8000ec4: 005b lsls r3, r3, #1
8000ec6: 4013 ands r3, r2
8000ec8: d0f0 beq.n 8000eac <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000eca: 687b ldr r3, [r7, #4]
8000ecc: 689b ldr r3, [r3, #8]
8000ece: 2b01 cmp r3, #1
8000ed0: d10e bne.n 8000ef0 <HAL_RCC_OscConfig+0x33c>
8000ed2: 4b03 ldr r3, [pc, #12] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000ed4: 6a1a ldr r2, [r3, #32]
8000ed6: 4b02 ldr r3, [pc, #8] @ (8000ee0 <HAL_RCC_OscConfig+0x32c>)
8000ed8: 2101 movs r1, #1
8000eda: 430a orrs r2, r1
8000edc: 621a str r2, [r3, #32]
8000ede: e035 b.n 8000f4c <HAL_RCC_OscConfig+0x398>
8000ee0: 40021000 .word 0x40021000
8000ee4: fffeffff .word 0xfffeffff
8000ee8: fffbffff .word 0xfffbffff
8000eec: 40007000 .word 0x40007000
8000ef0: 687b ldr r3, [r7, #4]
8000ef2: 689b ldr r3, [r3, #8]
8000ef4: 2b00 cmp r3, #0
8000ef6: d10c bne.n 8000f12 <HAL_RCC_OscConfig+0x35e>
8000ef8: 4bb6 ldr r3, [pc, #728] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000efa: 6a1a ldr r2, [r3, #32]
8000efc: 4bb5 ldr r3, [pc, #724] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000efe: 2101 movs r1, #1
8000f00: 438a bics r2, r1
8000f02: 621a str r2, [r3, #32]
8000f04: 4bb3 ldr r3, [pc, #716] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f06: 6a1a ldr r2, [r3, #32]
8000f08: 4bb2 ldr r3, [pc, #712] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f0a: 2104 movs r1, #4
8000f0c: 438a bics r2, r1
8000f0e: 621a str r2, [r3, #32]
8000f10: e01c b.n 8000f4c <HAL_RCC_OscConfig+0x398>
8000f12: 687b ldr r3, [r7, #4]
8000f14: 689b ldr r3, [r3, #8]
8000f16: 2b05 cmp r3, #5
8000f18: d10c bne.n 8000f34 <HAL_RCC_OscConfig+0x380>
8000f1a: 4bae ldr r3, [pc, #696] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f1c: 6a1a ldr r2, [r3, #32]
8000f1e: 4bad ldr r3, [pc, #692] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f20: 2104 movs r1, #4
8000f22: 430a orrs r2, r1
8000f24: 621a str r2, [r3, #32]
8000f26: 4bab ldr r3, [pc, #684] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f28: 6a1a ldr r2, [r3, #32]
8000f2a: 4baa ldr r3, [pc, #680] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f2c: 2101 movs r1, #1
8000f2e: 430a orrs r2, r1
8000f30: 621a str r2, [r3, #32]
8000f32: e00b b.n 8000f4c <HAL_RCC_OscConfig+0x398>
8000f34: 4ba7 ldr r3, [pc, #668] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f36: 6a1a ldr r2, [r3, #32]
8000f38: 4ba6 ldr r3, [pc, #664] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f3a: 2101 movs r1, #1
8000f3c: 438a bics r2, r1
8000f3e: 621a str r2, [r3, #32]
8000f40: 4ba4 ldr r3, [pc, #656] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f42: 6a1a ldr r2, [r3, #32]
8000f44: 4ba3 ldr r3, [pc, #652] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f46: 2104 movs r1, #4
8000f48: 438a bics r2, r1
8000f4a: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000f4c: 687b ldr r3, [r7, #4]
8000f4e: 689b ldr r3, [r3, #8]
8000f50: 2b00 cmp r3, #0
8000f52: d014 beq.n 8000f7e <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f54: f7ff fbe2 bl 800071c <HAL_GetTick>
8000f58: 0003 movs r3, r0
8000f5a: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f5c: e009 b.n 8000f72 <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8000f5e: f7ff fbdd bl 800071c <HAL_GetTick>
8000f62: 0002 movs r2, r0
8000f64: 69bb ldr r3, [r7, #24]
8000f66: 1ad3 subs r3, r2, r3
8000f68: 4a9b ldr r2, [pc, #620] @ (80011d8 <HAL_RCC_OscConfig+0x624>)
8000f6a: 4293 cmp r3, r2
8000f6c: d901 bls.n 8000f72 <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
8000f6e: 2303 movs r3, #3
8000f70: e12b b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f72: 4b98 ldr r3, [pc, #608] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f74: 6a1b ldr r3, [r3, #32]
8000f76: 2202 movs r2, #2
8000f78: 4013 ands r3, r2
8000f7a: d0f0 beq.n 8000f5e <HAL_RCC_OscConfig+0x3aa>
8000f7c: e013 b.n 8000fa6 <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f7e: f7ff fbcd bl 800071c <HAL_GetTick>
8000f82: 0003 movs r3, r0
8000f84: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000f86: e009 b.n 8000f9c <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8000f88: f7ff fbc8 bl 800071c <HAL_GetTick>
8000f8c: 0002 movs r2, r0
8000f8e: 69bb ldr r3, [r7, #24]
8000f90: 1ad3 subs r3, r2, r3
8000f92: 4a91 ldr r2, [pc, #580] @ (80011d8 <HAL_RCC_OscConfig+0x624>)
8000f94: 4293 cmp r3, r2
8000f96: d901 bls.n 8000f9c <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
8000f98: 2303 movs r3, #3
8000f9a: e116 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000f9c: 4b8d ldr r3, [pc, #564] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000f9e: 6a1b ldr r3, [r3, #32]
8000fa0: 2202 movs r2, #2
8000fa2: 4013 ands r3, r2
8000fa4: d1f0 bne.n 8000f88 <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8000fa6: 231f movs r3, #31
8000fa8: 18fb adds r3, r7, r3
8000faa: 781b ldrb r3, [r3, #0]
8000fac: 2b01 cmp r3, #1
8000fae: d105 bne.n 8000fbc <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000fb0: 4b88 ldr r3, [pc, #544] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000fb2: 69da ldr r2, [r3, #28]
8000fb4: 4b87 ldr r3, [pc, #540] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000fb6: 4989 ldr r1, [pc, #548] @ (80011dc <HAL_RCC_OscConfig+0x628>)
8000fb8: 400a ands r2, r1
8000fba: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8000fbc: 687b ldr r3, [r7, #4]
8000fbe: 681b ldr r3, [r3, #0]
8000fc0: 2210 movs r2, #16
8000fc2: 4013 ands r3, r2
8000fc4: d063 beq.n 800108e <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8000fc6: 687b ldr r3, [r7, #4]
8000fc8: 695b ldr r3, [r3, #20]
8000fca: 2b01 cmp r3, #1
8000fcc: d12a bne.n 8001024 <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000fce: 4b81 ldr r3, [pc, #516] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000fd0: 6b5a ldr r2, [r3, #52] @ 0x34
8000fd2: 4b80 ldr r3, [pc, #512] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000fd4: 2104 movs r1, #4
8000fd6: 430a orrs r2, r1
8000fd8: 635a str r2, [r3, #52] @ 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8000fda: 4b7e ldr r3, [pc, #504] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000fdc: 6b5a ldr r2, [r3, #52] @ 0x34
8000fde: 4b7d ldr r3, [pc, #500] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8000fe0: 2101 movs r1, #1
8000fe2: 430a orrs r2, r1
8000fe4: 635a str r2, [r3, #52] @ 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fe6: f7ff fb99 bl 800071c <HAL_GetTick>
8000fea: 0003 movs r3, r0
8000fec: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000fee: e008 b.n 8001002 <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000ff0: f7ff fb94 bl 800071c <HAL_GetTick>
8000ff4: 0002 movs r2, r0
8000ff6: 69bb ldr r3, [r7, #24]
8000ff8: 1ad3 subs r3, r2, r3
8000ffa: 2b02 cmp r3, #2
8000ffc: d901 bls.n 8001002 <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
8000ffe: 2303 movs r3, #3
8001000: e0e3 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001002: 4b74 ldr r3, [pc, #464] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001004: 6b5b ldr r3, [r3, #52] @ 0x34
8001006: 2202 movs r2, #2
8001008: 4013 ands r3, r2
800100a: d0f1 beq.n 8000ff0 <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
800100c: 4b71 ldr r3, [pc, #452] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800100e: 6b5b ldr r3, [r3, #52] @ 0x34
8001010: 22f8 movs r2, #248 @ 0xf8
8001012: 4393 bics r3, r2
8001014: 0019 movs r1, r3
8001016: 687b ldr r3, [r7, #4]
8001018: 699b ldr r3, [r3, #24]
800101a: 00da lsls r2, r3, #3
800101c: 4b6d ldr r3, [pc, #436] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800101e: 430a orrs r2, r1
8001020: 635a str r2, [r3, #52] @ 0x34
8001022: e034 b.n 800108e <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8001024: 687b ldr r3, [r7, #4]
8001026: 695b ldr r3, [r3, #20]
8001028: 3305 adds r3, #5
800102a: d111 bne.n 8001050 <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
800102c: 4b69 ldr r3, [pc, #420] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800102e: 6b5a ldr r2, [r3, #52] @ 0x34
8001030: 4b68 ldr r3, [pc, #416] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001032: 2104 movs r1, #4
8001034: 438a bics r2, r1
8001036: 635a str r2, [r3, #52] @ 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8001038: 4b66 ldr r3, [pc, #408] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800103a: 6b5b ldr r3, [r3, #52] @ 0x34
800103c: 22f8 movs r2, #248 @ 0xf8
800103e: 4393 bics r3, r2
8001040: 0019 movs r1, r3
8001042: 687b ldr r3, [r7, #4]
8001044: 699b ldr r3, [r3, #24]
8001046: 00da lsls r2, r3, #3
8001048: 4b62 ldr r3, [pc, #392] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800104a: 430a orrs r2, r1
800104c: 635a str r2, [r3, #52] @ 0x34
800104e: e01e b.n 800108e <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001050: 4b60 ldr r3, [pc, #384] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001052: 6b5a ldr r2, [r3, #52] @ 0x34
8001054: 4b5f ldr r3, [pc, #380] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001056: 2104 movs r1, #4
8001058: 430a orrs r2, r1
800105a: 635a str r2, [r3, #52] @ 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
800105c: 4b5d ldr r3, [pc, #372] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800105e: 6b5a ldr r2, [r3, #52] @ 0x34
8001060: 4b5c ldr r3, [pc, #368] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001062: 2101 movs r1, #1
8001064: 438a bics r2, r1
8001066: 635a str r2, [r3, #52] @ 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001068: f7ff fb58 bl 800071c <HAL_GetTick>
800106c: 0003 movs r3, r0
800106e: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001070: e008 b.n 8001084 <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001072: f7ff fb53 bl 800071c <HAL_GetTick>
8001076: 0002 movs r2, r0
8001078: 69bb ldr r3, [r7, #24]
800107a: 1ad3 subs r3, r2, r3
800107c: 2b02 cmp r3, #2
800107e: d901 bls.n 8001084 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
8001080: 2303 movs r3, #3
8001082: e0a2 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001084: 4b53 ldr r3, [pc, #332] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001086: 6b5b ldr r3, [r3, #52] @ 0x34
8001088: 2202 movs r2, #2
800108a: 4013 ands r3, r2
800108c: d1f1 bne.n 8001072 <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
800108e: 687b ldr r3, [r7, #4]
8001090: 6a1b ldr r3, [r3, #32]
8001092: 2b00 cmp r3, #0
8001094: d100 bne.n 8001098 <HAL_RCC_OscConfig+0x4e4>
8001096: e097 b.n 80011c8 <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001098: 4b4e ldr r3, [pc, #312] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800109a: 685b ldr r3, [r3, #4]
800109c: 220c movs r2, #12
800109e: 4013 ands r3, r2
80010a0: 2b08 cmp r3, #8
80010a2: d100 bne.n 80010a6 <HAL_RCC_OscConfig+0x4f2>
80010a4: e06b b.n 800117e <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80010a6: 687b ldr r3, [r7, #4]
80010a8: 6a1b ldr r3, [r3, #32]
80010aa: 2b02 cmp r3, #2
80010ac: d14c bne.n 8001148 <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80010ae: 4b49 ldr r3, [pc, #292] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
80010b0: 681a ldr r2, [r3, #0]
80010b2: 4b48 ldr r3, [pc, #288] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
80010b4: 494a ldr r1, [pc, #296] @ (80011e0 <HAL_RCC_OscConfig+0x62c>)
80010b6: 400a ands r2, r1
80010b8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80010ba: f7ff fb2f bl 800071c <HAL_GetTick>
80010be: 0003 movs r3, r0
80010c0: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80010c2: e008 b.n 80010d6 <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80010c4: f7ff fb2a bl 800071c <HAL_GetTick>
80010c8: 0002 movs r2, r0
80010ca: 69bb ldr r3, [r7, #24]
80010cc: 1ad3 subs r3, r2, r3
80010ce: 2b02 cmp r3, #2
80010d0: d901 bls.n 80010d6 <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
80010d2: 2303 movs r3, #3
80010d4: e079 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80010d6: 4b3f ldr r3, [pc, #252] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
80010d8: 681a ldr r2, [r3, #0]
80010da: 2380 movs r3, #128 @ 0x80
80010dc: 049b lsls r3, r3, #18
80010de: 4013 ands r3, r2
80010e0: d1f0 bne.n 80010c4 <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80010e2: 4b3c ldr r3, [pc, #240] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
80010e4: 6adb ldr r3, [r3, #44] @ 0x2c
80010e6: 220f movs r2, #15
80010e8: 4393 bics r3, r2
80010ea: 0019 movs r1, r3
80010ec: 687b ldr r3, [r7, #4]
80010ee: 6ada ldr r2, [r3, #44] @ 0x2c
80010f0: 4b38 ldr r3, [pc, #224] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
80010f2: 430a orrs r2, r1
80010f4: 62da str r2, [r3, #44] @ 0x2c
80010f6: 4b37 ldr r3, [pc, #220] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
80010f8: 685b ldr r3, [r3, #4]
80010fa: 4a3a ldr r2, [pc, #232] @ (80011e4 <HAL_RCC_OscConfig+0x630>)
80010fc: 4013 ands r3, r2
80010fe: 0019 movs r1, r3
8001100: 687b ldr r3, [r7, #4]
8001102: 6a9a ldr r2, [r3, #40] @ 0x28
8001104: 687b ldr r3, [r7, #4]
8001106: 6a5b ldr r3, [r3, #36] @ 0x24
8001108: 431a orrs r2, r3
800110a: 4b32 ldr r3, [pc, #200] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800110c: 430a orrs r2, r1
800110e: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001110: 4b30 ldr r3, [pc, #192] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001112: 681a ldr r2, [r3, #0]
8001114: 4b2f ldr r3, [pc, #188] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001116: 2180 movs r1, #128 @ 0x80
8001118: 0449 lsls r1, r1, #17
800111a: 430a orrs r2, r1
800111c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800111e: f7ff fafd bl 800071c <HAL_GetTick>
8001122: 0003 movs r3, r0
8001124: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001126: e008 b.n 800113a <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001128: f7ff faf8 bl 800071c <HAL_GetTick>
800112c: 0002 movs r2, r0
800112e: 69bb ldr r3, [r7, #24]
8001130: 1ad3 subs r3, r2, r3
8001132: 2b02 cmp r3, #2
8001134: d901 bls.n 800113a <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001136: 2303 movs r3, #3
8001138: e047 b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800113a: 4b26 ldr r3, [pc, #152] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800113c: 681a ldr r2, [r3, #0]
800113e: 2380 movs r3, #128 @ 0x80
8001140: 049b lsls r3, r3, #18
8001142: 4013 ands r3, r2
8001144: d0f0 beq.n 8001128 <HAL_RCC_OscConfig+0x574>
8001146: e03f b.n 80011c8 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001148: 4b22 ldr r3, [pc, #136] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800114a: 681a ldr r2, [r3, #0]
800114c: 4b21 ldr r3, [pc, #132] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800114e: 4924 ldr r1, [pc, #144] @ (80011e0 <HAL_RCC_OscConfig+0x62c>)
8001150: 400a ands r2, r1
8001152: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001154: f7ff fae2 bl 800071c <HAL_GetTick>
8001158: 0003 movs r3, r0
800115a: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800115c: e008 b.n 8001170 <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800115e: f7ff fadd bl 800071c <HAL_GetTick>
8001162: 0002 movs r2, r0
8001164: 69bb ldr r3, [r7, #24]
8001166: 1ad3 subs r3, r2, r3
8001168: 2b02 cmp r3, #2
800116a: d901 bls.n 8001170 <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
800116c: 2303 movs r3, #3
800116e: e02c b.n 80011ca <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001170: 4b18 ldr r3, [pc, #96] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001172: 681a ldr r2, [r3, #0]
8001174: 2380 movs r3, #128 @ 0x80
8001176: 049b lsls r3, r3, #18
8001178: 4013 ands r3, r2
800117a: d1f0 bne.n 800115e <HAL_RCC_OscConfig+0x5aa>
800117c: e024 b.n 80011c8 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800117e: 687b ldr r3, [r7, #4]
8001180: 6a1b ldr r3, [r3, #32]
8001182: 2b01 cmp r3, #1
8001184: d101 bne.n 800118a <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
8001186: 2301 movs r3, #1
8001188: e01f b.n 80011ca <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800118a: 4b12 ldr r3, [pc, #72] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
800118c: 685b ldr r3, [r3, #4]
800118e: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8001190: 4b10 ldr r3, [pc, #64] @ (80011d4 <HAL_RCC_OscConfig+0x620>)
8001192: 6adb ldr r3, [r3, #44] @ 0x2c
8001194: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001196: 697a ldr r2, [r7, #20]
8001198: 2380 movs r3, #128 @ 0x80
800119a: 025b lsls r3, r3, #9
800119c: 401a ands r2, r3
800119e: 687b ldr r3, [r7, #4]
80011a0: 6a5b ldr r3, [r3, #36] @ 0x24
80011a2: 429a cmp r2, r3
80011a4: d10e bne.n 80011c4 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
80011a6: 693b ldr r3, [r7, #16]
80011a8: 220f movs r2, #15
80011aa: 401a ands r2, r3
80011ac: 687b ldr r3, [r7, #4]
80011ae: 6adb ldr r3, [r3, #44] @ 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80011b0: 429a cmp r2, r3
80011b2: d107 bne.n 80011c4 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
80011b4: 697a ldr r2, [r7, #20]
80011b6: 23f0 movs r3, #240 @ 0xf0
80011b8: 039b lsls r3, r3, #14
80011ba: 401a ands r2, r3
80011bc: 687b ldr r3, [r7, #4]
80011be: 6a9b ldr r3, [r3, #40] @ 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
80011c0: 429a cmp r2, r3
80011c2: d001 beq.n 80011c8 <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
80011c4: 2301 movs r3, #1
80011c6: e000 b.n 80011ca <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
80011c8: 2300 movs r3, #0
}
80011ca: 0018 movs r0, r3
80011cc: 46bd mov sp, r7
80011ce: b008 add sp, #32
80011d0: bd80 pop {r7, pc}
80011d2: 46c0 nop @ (mov r8, r8)
80011d4: 40021000 .word 0x40021000
80011d8: 00001388 .word 0x00001388
80011dc: efffffff .word 0xefffffff
80011e0: feffffff .word 0xfeffffff
80011e4: ffc2ffff .word 0xffc2ffff
080011e8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80011e8: b580 push {r7, lr}
80011ea: b084 sub sp, #16
80011ec: af00 add r7, sp, #0
80011ee: 6078 str r0, [r7, #4]
80011f0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
80011f2: 687b ldr r3, [r7, #4]
80011f4: 2b00 cmp r3, #0
80011f6: d101 bne.n 80011fc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80011f8: 2301 movs r3, #1
80011fa: e0b3 b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80011fc: 4b5b ldr r3, [pc, #364] @ (800136c <HAL_RCC_ClockConfig+0x184>)
80011fe: 681b ldr r3, [r3, #0]
8001200: 2201 movs r2, #1
8001202: 4013 ands r3, r2
8001204: 683a ldr r2, [r7, #0]
8001206: 429a cmp r2, r3
8001208: d911 bls.n 800122e <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800120a: 4b58 ldr r3, [pc, #352] @ (800136c <HAL_RCC_ClockConfig+0x184>)
800120c: 681b ldr r3, [r3, #0]
800120e: 2201 movs r2, #1
8001210: 4393 bics r3, r2
8001212: 0019 movs r1, r3
8001214: 4b55 ldr r3, [pc, #340] @ (800136c <HAL_RCC_ClockConfig+0x184>)
8001216: 683a ldr r2, [r7, #0]
8001218: 430a orrs r2, r1
800121a: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800121c: 4b53 ldr r3, [pc, #332] @ (800136c <HAL_RCC_ClockConfig+0x184>)
800121e: 681b ldr r3, [r3, #0]
8001220: 2201 movs r2, #1
8001222: 4013 ands r3, r2
8001224: 683a ldr r2, [r7, #0]
8001226: 429a cmp r2, r3
8001228: d001 beq.n 800122e <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
800122a: 2301 movs r3, #1
800122c: e09a b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800122e: 687b ldr r3, [r7, #4]
8001230: 681b ldr r3, [r3, #0]
8001232: 2202 movs r2, #2
8001234: 4013 ands r3, r2
8001236: d015 beq.n 8001264 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001238: 687b ldr r3, [r7, #4]
800123a: 681b ldr r3, [r3, #0]
800123c: 2204 movs r2, #4
800123e: 4013 ands r3, r2
8001240: d006 beq.n 8001250 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8001242: 4b4b ldr r3, [pc, #300] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001244: 685a ldr r2, [r3, #4]
8001246: 4b4a ldr r3, [pc, #296] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001248: 21e0 movs r1, #224 @ 0xe0
800124a: 00c9 lsls r1, r1, #3
800124c: 430a orrs r2, r1
800124e: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001250: 4b47 ldr r3, [pc, #284] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001252: 685b ldr r3, [r3, #4]
8001254: 22f0 movs r2, #240 @ 0xf0
8001256: 4393 bics r3, r2
8001258: 0019 movs r1, r3
800125a: 687b ldr r3, [r7, #4]
800125c: 689a ldr r2, [r3, #8]
800125e: 4b44 ldr r3, [pc, #272] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001260: 430a orrs r2, r1
8001262: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001264: 687b ldr r3, [r7, #4]
8001266: 681b ldr r3, [r3, #0]
8001268: 2201 movs r2, #1
800126a: 4013 ands r3, r2
800126c: d040 beq.n 80012f0 <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800126e: 687b ldr r3, [r7, #4]
8001270: 685b ldr r3, [r3, #4]
8001272: 2b01 cmp r3, #1
8001274: d107 bne.n 8001286 <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001276: 4b3e ldr r3, [pc, #248] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001278: 681a ldr r2, [r3, #0]
800127a: 2380 movs r3, #128 @ 0x80
800127c: 029b lsls r3, r3, #10
800127e: 4013 ands r3, r2
8001280: d114 bne.n 80012ac <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001282: 2301 movs r3, #1
8001284: e06e b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001286: 687b ldr r3, [r7, #4]
8001288: 685b ldr r3, [r3, #4]
800128a: 2b02 cmp r3, #2
800128c: d107 bne.n 800129e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800128e: 4b38 ldr r3, [pc, #224] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001290: 681a ldr r2, [r3, #0]
8001292: 2380 movs r3, #128 @ 0x80
8001294: 049b lsls r3, r3, #18
8001296: 4013 ands r3, r2
8001298: d108 bne.n 80012ac <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
800129a: 2301 movs r3, #1
800129c: e062 b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800129e: 4b34 ldr r3, [pc, #208] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
80012a0: 681b ldr r3, [r3, #0]
80012a2: 2202 movs r2, #2
80012a4: 4013 ands r3, r2
80012a6: d101 bne.n 80012ac <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
80012a8: 2301 movs r3, #1
80012aa: e05b b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80012ac: 4b30 ldr r3, [pc, #192] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
80012ae: 685b ldr r3, [r3, #4]
80012b0: 2203 movs r2, #3
80012b2: 4393 bics r3, r2
80012b4: 0019 movs r1, r3
80012b6: 687b ldr r3, [r7, #4]
80012b8: 685a ldr r2, [r3, #4]
80012ba: 4b2d ldr r3, [pc, #180] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
80012bc: 430a orrs r2, r1
80012be: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80012c0: f7ff fa2c bl 800071c <HAL_GetTick>
80012c4: 0003 movs r3, r0
80012c6: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80012c8: e009 b.n 80012de <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80012ca: f7ff fa27 bl 800071c <HAL_GetTick>
80012ce: 0002 movs r2, r0
80012d0: 68fb ldr r3, [r7, #12]
80012d2: 1ad3 subs r3, r2, r3
80012d4: 4a27 ldr r2, [pc, #156] @ (8001374 <HAL_RCC_ClockConfig+0x18c>)
80012d6: 4293 cmp r3, r2
80012d8: d901 bls.n 80012de <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
80012da: 2303 movs r3, #3
80012dc: e042 b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80012de: 4b24 ldr r3, [pc, #144] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
80012e0: 685b ldr r3, [r3, #4]
80012e2: 220c movs r2, #12
80012e4: 401a ands r2, r3
80012e6: 687b ldr r3, [r7, #4]
80012e8: 685b ldr r3, [r3, #4]
80012ea: 009b lsls r3, r3, #2
80012ec: 429a cmp r2, r3
80012ee: d1ec bne.n 80012ca <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80012f0: 4b1e ldr r3, [pc, #120] @ (800136c <HAL_RCC_ClockConfig+0x184>)
80012f2: 681b ldr r3, [r3, #0]
80012f4: 2201 movs r2, #1
80012f6: 4013 ands r3, r2
80012f8: 683a ldr r2, [r7, #0]
80012fa: 429a cmp r2, r3
80012fc: d211 bcs.n 8001322 <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80012fe: 4b1b ldr r3, [pc, #108] @ (800136c <HAL_RCC_ClockConfig+0x184>)
8001300: 681b ldr r3, [r3, #0]
8001302: 2201 movs r2, #1
8001304: 4393 bics r3, r2
8001306: 0019 movs r1, r3
8001308: 4b18 ldr r3, [pc, #96] @ (800136c <HAL_RCC_ClockConfig+0x184>)
800130a: 683a ldr r2, [r7, #0]
800130c: 430a orrs r2, r1
800130e: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001310: 4b16 ldr r3, [pc, #88] @ (800136c <HAL_RCC_ClockConfig+0x184>)
8001312: 681b ldr r3, [r3, #0]
8001314: 2201 movs r2, #1
8001316: 4013 ands r3, r2
8001318: 683a ldr r2, [r7, #0]
800131a: 429a cmp r2, r3
800131c: d001 beq.n 8001322 <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
800131e: 2301 movs r3, #1
8001320: e020 b.n 8001364 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001322: 687b ldr r3, [r7, #4]
8001324: 681b ldr r3, [r3, #0]
8001326: 2204 movs r2, #4
8001328: 4013 ands r3, r2
800132a: d009 beq.n 8001340 <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
800132c: 4b10 ldr r3, [pc, #64] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
800132e: 685b ldr r3, [r3, #4]
8001330: 4a11 ldr r2, [pc, #68] @ (8001378 <HAL_RCC_ClockConfig+0x190>)
8001332: 4013 ands r3, r2
8001334: 0019 movs r1, r3
8001336: 687b ldr r3, [r7, #4]
8001338: 68da ldr r2, [r3, #12]
800133a: 4b0d ldr r3, [pc, #52] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
800133c: 430a orrs r2, r1
800133e: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8001340: f000 f820 bl 8001384 <HAL_RCC_GetSysClockFreq>
8001344: 0001 movs r1, r0
8001346: 4b0a ldr r3, [pc, #40] @ (8001370 <HAL_RCC_ClockConfig+0x188>)
8001348: 685b ldr r3, [r3, #4]
800134a: 091b lsrs r3, r3, #4
800134c: 220f movs r2, #15
800134e: 4013 ands r3, r2
8001350: 4a0a ldr r2, [pc, #40] @ (800137c <HAL_RCC_ClockConfig+0x194>)
8001352: 5cd3 ldrb r3, [r2, r3]
8001354: 000a movs r2, r1
8001356: 40da lsrs r2, r3
8001358: 4b09 ldr r3, [pc, #36] @ (8001380 <HAL_RCC_ClockConfig+0x198>)
800135a: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
800135c: 2003 movs r0, #3
800135e: f7ff f997 bl 8000690 <HAL_InitTick>
return HAL_OK;
8001362: 2300 movs r3, #0
}
8001364: 0018 movs r0, r3
8001366: 46bd mov sp, r7
8001368: b004 add sp, #16
800136a: bd80 pop {r7, pc}
800136c: 40022000 .word 0x40022000
8001370: 40021000 .word 0x40021000
8001374: 00001388 .word 0x00001388
8001378: fffff8ff .word 0xfffff8ff
800137c: 08001ce0 .word 0x08001ce0
8001380: 20000000 .word 0x20000000
08001384 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001384: b580 push {r7, lr}
8001386: b086 sub sp, #24
8001388: af00 add r7, sp, #0
static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800138a: 2300 movs r3, #0
800138c: 60fb str r3, [r7, #12]
800138e: 2300 movs r3, #0
8001390: 60bb str r3, [r7, #8]
8001392: 2300 movs r3, #0
8001394: 617b str r3, [r7, #20]
8001396: 2300 movs r3, #0
8001398: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
800139a: 2300 movs r3, #0
800139c: 613b str r3, [r7, #16]
tmpreg = RCC->CFGR;
800139e: 4b20 ldr r3, [pc, #128] @ (8001420 <HAL_RCC_GetSysClockFreq+0x9c>)
80013a0: 685b ldr r3, [r3, #4]
80013a2: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80013a4: 68fb ldr r3, [r7, #12]
80013a6: 220c movs r2, #12
80013a8: 4013 ands r3, r2
80013aa: 2b04 cmp r3, #4
80013ac: d002 beq.n 80013b4 <HAL_RCC_GetSysClockFreq+0x30>
80013ae: 2b08 cmp r3, #8
80013b0: d003 beq.n 80013ba <HAL_RCC_GetSysClockFreq+0x36>
80013b2: e02c b.n 800140e <HAL_RCC_GetSysClockFreq+0x8a>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80013b4: 4b1b ldr r3, [pc, #108] @ (8001424 <HAL_RCC_GetSysClockFreq+0xa0>)
80013b6: 613b str r3, [r7, #16]
break;
80013b8: e02c b.n 8001414 <HAL_RCC_GetSysClockFreq+0x90>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
80013ba: 68fb ldr r3, [r7, #12]
80013bc: 0c9b lsrs r3, r3, #18
80013be: 220f movs r2, #15
80013c0: 4013 ands r3, r2
80013c2: 4a19 ldr r2, [pc, #100] @ (8001428 <HAL_RCC_GetSysClockFreq+0xa4>)
80013c4: 5cd3 ldrb r3, [r2, r3]
80013c6: 607b str r3, [r7, #4]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
80013c8: 4b15 ldr r3, [pc, #84] @ (8001420 <HAL_RCC_GetSysClockFreq+0x9c>)
80013ca: 6adb ldr r3, [r3, #44] @ 0x2c
80013cc: 220f movs r2, #15
80013ce: 4013 ands r3, r2
80013d0: 4a16 ldr r2, [pc, #88] @ (800142c <HAL_RCC_GetSysClockFreq+0xa8>)
80013d2: 5cd3 ldrb r3, [r2, r3]
80013d4: 60bb str r3, [r7, #8]
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
80013d6: 68fa ldr r2, [r7, #12]
80013d8: 2380 movs r3, #128 @ 0x80
80013da: 025b lsls r3, r3, #9
80013dc: 4013 ands r3, r2
80013de: d009 beq.n 80013f4 <HAL_RCC_GetSysClockFreq+0x70>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80013e0: 68b9 ldr r1, [r7, #8]
80013e2: 4810 ldr r0, [pc, #64] @ (8001424 <HAL_RCC_GetSysClockFreq+0xa0>)
80013e4: f7fe fe90 bl 8000108 <__udivsi3>
80013e8: 0003 movs r3, r0
80013ea: 001a movs r2, r3
80013ec: 687b ldr r3, [r7, #4]
80013ee: 4353 muls r3, r2
80013f0: 617b str r3, [r7, #20]
80013f2: e009 b.n 8001408 <HAL_RCC_GetSysClockFreq+0x84>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
80013f4: 6879 ldr r1, [r7, #4]
80013f6: 000a movs r2, r1
80013f8: 0152 lsls r2, r2, #5
80013fa: 1a52 subs r2, r2, r1
80013fc: 0193 lsls r3, r2, #6
80013fe: 1a9b subs r3, r3, r2
8001400: 00db lsls r3, r3, #3
8001402: 185b adds r3, r3, r1
8001404: 021b lsls r3, r3, #8
8001406: 617b str r3, [r7, #20]
#endif
}
sysclockfreq = pllclk;
8001408: 697b ldr r3, [r7, #20]
800140a: 613b str r3, [r7, #16]
break;
800140c: e002 b.n 8001414 <HAL_RCC_GetSysClockFreq+0x90>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800140e: 4b05 ldr r3, [pc, #20] @ (8001424 <HAL_RCC_GetSysClockFreq+0xa0>)
8001410: 613b str r3, [r7, #16]
break;
8001412: 46c0 nop @ (mov r8, r8)
}
}
return sysclockfreq;
8001414: 693b ldr r3, [r7, #16]
}
8001416: 0018 movs r0, r3
8001418: 46bd mov sp, r7
800141a: b006 add sp, #24
800141c: bd80 pop {r7, pc}
800141e: 46c0 nop @ (mov r8, r8)
8001420: 40021000 .word 0x40021000
8001424: 007a1200 .word 0x007a1200
8001428: 08001cf0 .word 0x08001cf0
800142c: 08001d00 .word 0x08001d00
08001430 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8001430: b580 push {r7, lr}
8001432: b082 sub sp, #8
8001434: af00 add r7, sp, #0
8001436: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001438: 687b ldr r3, [r7, #4]
800143a: 2b00 cmp r3, #0
800143c: d101 bne.n 8001442 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
800143e: 2301 movs r3, #1
8001440: e042 b.n 80014c8 <HAL_TIM_PWM_Init+0x98>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001442: 687b ldr r3, [r7, #4]
8001444: 223d movs r2, #61 @ 0x3d
8001446: 5c9b ldrb r3, [r3, r2]
8001448: b2db uxtb r3, r3
800144a: 2b00 cmp r3, #0
800144c: d107 bne.n 800145e <HAL_TIM_PWM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800144e: 687b ldr r3, [r7, #4]
8001450: 223c movs r2, #60 @ 0x3c
8001452: 2100 movs r1, #0
8001454: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8001456: 687b ldr r3, [r7, #4]
8001458: 0018 movs r0, r3
800145a: f7ff f85d bl 8000518 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800145e: 687b ldr r3, [r7, #4]
8001460: 223d movs r2, #61 @ 0x3d
8001462: 2102 movs r1, #2
8001464: 5499 strb r1, [r3, r2]
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001466: 687b ldr r3, [r7, #4]
8001468: 681a ldr r2, [r3, #0]
800146a: 687b ldr r3, [r7, #4]
800146c: 3304 adds r3, #4
800146e: 0019 movs r1, r3
8001470: 0010 movs r0, r2
8001472: f000 f8f3 bl 800165c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001476: 687b ldr r3, [r7, #4]
8001478: 2246 movs r2, #70 @ 0x46
800147a: 2101 movs r1, #1
800147c: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800147e: 687b ldr r3, [r7, #4]
8001480: 223e movs r2, #62 @ 0x3e
8001482: 2101 movs r1, #1
8001484: 5499 strb r1, [r3, r2]
8001486: 687b ldr r3, [r7, #4]
8001488: 223f movs r2, #63 @ 0x3f
800148a: 2101 movs r1, #1
800148c: 5499 strb r1, [r3, r2]
800148e: 687b ldr r3, [r7, #4]
8001490: 2240 movs r2, #64 @ 0x40
8001492: 2101 movs r1, #1
8001494: 5499 strb r1, [r3, r2]
8001496: 687b ldr r3, [r7, #4]
8001498: 2241 movs r2, #65 @ 0x41
800149a: 2101 movs r1, #1
800149c: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800149e: 687b ldr r3, [r7, #4]
80014a0: 2242 movs r2, #66 @ 0x42
80014a2: 2101 movs r1, #1
80014a4: 5499 strb r1, [r3, r2]
80014a6: 687b ldr r3, [r7, #4]
80014a8: 2243 movs r2, #67 @ 0x43
80014aa: 2101 movs r1, #1
80014ac: 5499 strb r1, [r3, r2]
80014ae: 687b ldr r3, [r7, #4]
80014b0: 2244 movs r2, #68 @ 0x44
80014b2: 2101 movs r1, #1
80014b4: 5499 strb r1, [r3, r2]
80014b6: 687b ldr r3, [r7, #4]
80014b8: 2245 movs r2, #69 @ 0x45
80014ba: 2101 movs r1, #1
80014bc: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80014be: 687b ldr r3, [r7, #4]
80014c0: 223d movs r2, #61 @ 0x3d
80014c2: 2101 movs r1, #1
80014c4: 5499 strb r1, [r3, r2]
return HAL_OK;
80014c6: 2300 movs r3, #0
}
80014c8: 0018 movs r0, r3
80014ca: 46bd mov sp, r7
80014cc: b002 add sp, #8
80014ce: bd80 pop {r7, pc}
080014d0 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80014d0: b580 push {r7, lr}
80014d2: b086 sub sp, #24
80014d4: af00 add r7, sp, #0
80014d6: 60f8 str r0, [r7, #12]
80014d8: 60b9 str r1, [r7, #8]
80014da: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80014dc: 2317 movs r3, #23
80014de: 18fb adds r3, r7, r3
80014e0: 2200 movs r2, #0
80014e2: 701a strb r2, [r3, #0]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
80014e4: 68fb ldr r3, [r7, #12]
80014e6: 223c movs r2, #60 @ 0x3c
80014e8: 5c9b ldrb r3, [r3, r2]
80014ea: 2b01 cmp r3, #1
80014ec: d101 bne.n 80014f2 <HAL_TIM_PWM_ConfigChannel+0x22>
80014ee: 2302 movs r3, #2
80014f0: e0ad b.n 800164e <HAL_TIM_PWM_ConfigChannel+0x17e>
80014f2: 68fb ldr r3, [r7, #12]
80014f4: 223c movs r2, #60 @ 0x3c
80014f6: 2101 movs r1, #1
80014f8: 5499 strb r1, [r3, r2]
switch (Channel)
80014fa: 687b ldr r3, [r7, #4]
80014fc: 2b0c cmp r3, #12
80014fe: d100 bne.n 8001502 <HAL_TIM_PWM_ConfigChannel+0x32>
8001500: e076 b.n 80015f0 <HAL_TIM_PWM_ConfigChannel+0x120>
8001502: 687b ldr r3, [r7, #4]
8001504: 2b0c cmp r3, #12
8001506: d900 bls.n 800150a <HAL_TIM_PWM_ConfigChannel+0x3a>
8001508: e095 b.n 8001636 <HAL_TIM_PWM_ConfigChannel+0x166>
800150a: 687b ldr r3, [r7, #4]
800150c: 2b08 cmp r3, #8
800150e: d04e beq.n 80015ae <HAL_TIM_PWM_ConfigChannel+0xde>
8001510: 687b ldr r3, [r7, #4]
8001512: 2b08 cmp r3, #8
8001514: d900 bls.n 8001518 <HAL_TIM_PWM_ConfigChannel+0x48>
8001516: e08e b.n 8001636 <HAL_TIM_PWM_ConfigChannel+0x166>
8001518: 687b ldr r3, [r7, #4]
800151a: 2b00 cmp r3, #0
800151c: d003 beq.n 8001526 <HAL_TIM_PWM_ConfigChannel+0x56>
800151e: 687b ldr r3, [r7, #4]
8001520: 2b04 cmp r3, #4
8001522: d021 beq.n 8001568 <HAL_TIM_PWM_ConfigChannel+0x98>
8001524: e087 b.n 8001636 <HAL_TIM_PWM_ConfigChannel+0x166>
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8001526: 68fb ldr r3, [r7, #12]
8001528: 681b ldr r3, [r3, #0]
800152a: 68ba ldr r2, [r7, #8]
800152c: 0011 movs r1, r2
800152e: 0018 movs r0, r3
8001530: f000 f90e bl 8001750 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8001534: 68fb ldr r3, [r7, #12]
8001536: 681b ldr r3, [r3, #0]
8001538: 699a ldr r2, [r3, #24]
800153a: 68fb ldr r3, [r7, #12]
800153c: 681b ldr r3, [r3, #0]
800153e: 2108 movs r1, #8
8001540: 430a orrs r2, r1
8001542: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8001544: 68fb ldr r3, [r7, #12]
8001546: 681b ldr r3, [r3, #0]
8001548: 699a ldr r2, [r3, #24]
800154a: 68fb ldr r3, [r7, #12]
800154c: 681b ldr r3, [r3, #0]
800154e: 2104 movs r1, #4
8001550: 438a bics r2, r1
8001552: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8001554: 68fb ldr r3, [r7, #12]
8001556: 681b ldr r3, [r3, #0]
8001558: 6999 ldr r1, [r3, #24]
800155a: 68bb ldr r3, [r7, #8]
800155c: 691a ldr r2, [r3, #16]
800155e: 68fb ldr r3, [r7, #12]
8001560: 681b ldr r3, [r3, #0]
8001562: 430a orrs r2, r1
8001564: 619a str r2, [r3, #24]
break;
8001566: e06b b.n 8001640 <HAL_TIM_PWM_ConfigChannel+0x170>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8001568: 68fb ldr r3, [r7, #12]
800156a: 681b ldr r3, [r3, #0]
800156c: 68ba ldr r2, [r7, #8]
800156e: 0011 movs r1, r2
8001570: 0018 movs r0, r3
8001572: f000 f96b bl 800184c <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8001576: 68fb ldr r3, [r7, #12]
8001578: 681b ldr r3, [r3, #0]
800157a: 699a ldr r2, [r3, #24]
800157c: 68fb ldr r3, [r7, #12]
800157e: 681b ldr r3, [r3, #0]
8001580: 2180 movs r1, #128 @ 0x80
8001582: 0109 lsls r1, r1, #4
8001584: 430a orrs r2, r1
8001586: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8001588: 68fb ldr r3, [r7, #12]
800158a: 681b ldr r3, [r3, #0]
800158c: 699a ldr r2, [r3, #24]
800158e: 68fb ldr r3, [r7, #12]
8001590: 681b ldr r3, [r3, #0]
8001592: 4931 ldr r1, [pc, #196] @ (8001658 <HAL_TIM_PWM_ConfigChannel+0x188>)
8001594: 400a ands r2, r1
8001596: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8001598: 68fb ldr r3, [r7, #12]
800159a: 681b ldr r3, [r3, #0]
800159c: 6999 ldr r1, [r3, #24]
800159e: 68bb ldr r3, [r7, #8]
80015a0: 691b ldr r3, [r3, #16]
80015a2: 021a lsls r2, r3, #8
80015a4: 68fb ldr r3, [r7, #12]
80015a6: 681b ldr r3, [r3, #0]
80015a8: 430a orrs r2, r1
80015aa: 619a str r2, [r3, #24]
break;
80015ac: e048 b.n 8001640 <HAL_TIM_PWM_ConfigChannel+0x170>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80015ae: 68fb ldr r3, [r7, #12]
80015b0: 681b ldr r3, [r3, #0]
80015b2: 68ba ldr r2, [r7, #8]
80015b4: 0011 movs r1, r2
80015b6: 0018 movs r0, r3
80015b8: f000 f9c6 bl 8001948 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80015bc: 68fb ldr r3, [r7, #12]
80015be: 681b ldr r3, [r3, #0]
80015c0: 69da ldr r2, [r3, #28]
80015c2: 68fb ldr r3, [r7, #12]
80015c4: 681b ldr r3, [r3, #0]
80015c6: 2108 movs r1, #8
80015c8: 430a orrs r2, r1
80015ca: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80015cc: 68fb ldr r3, [r7, #12]
80015ce: 681b ldr r3, [r3, #0]
80015d0: 69da ldr r2, [r3, #28]
80015d2: 68fb ldr r3, [r7, #12]
80015d4: 681b ldr r3, [r3, #0]
80015d6: 2104 movs r1, #4
80015d8: 438a bics r2, r1
80015da: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80015dc: 68fb ldr r3, [r7, #12]
80015de: 681b ldr r3, [r3, #0]
80015e0: 69d9 ldr r1, [r3, #28]
80015e2: 68bb ldr r3, [r7, #8]
80015e4: 691a ldr r2, [r3, #16]
80015e6: 68fb ldr r3, [r7, #12]
80015e8: 681b ldr r3, [r3, #0]
80015ea: 430a orrs r2, r1
80015ec: 61da str r2, [r3, #28]
break;
80015ee: e027 b.n 8001640 <HAL_TIM_PWM_ConfigChannel+0x170>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
80015f0: 68fb ldr r3, [r7, #12]
80015f2: 681b ldr r3, [r3, #0]
80015f4: 68ba ldr r2, [r7, #8]
80015f6: 0011 movs r1, r2
80015f8: 0018 movs r0, r3
80015fa: f000 fa25 bl 8001a48 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
80015fe: 68fb ldr r3, [r7, #12]
8001600: 681b ldr r3, [r3, #0]
8001602: 69da ldr r2, [r3, #28]
8001604: 68fb ldr r3, [r7, #12]
8001606: 681b ldr r3, [r3, #0]
8001608: 2180 movs r1, #128 @ 0x80
800160a: 0109 lsls r1, r1, #4
800160c: 430a orrs r2, r1
800160e: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8001610: 68fb ldr r3, [r7, #12]
8001612: 681b ldr r3, [r3, #0]
8001614: 69da ldr r2, [r3, #28]
8001616: 68fb ldr r3, [r7, #12]
8001618: 681b ldr r3, [r3, #0]
800161a: 490f ldr r1, [pc, #60] @ (8001658 <HAL_TIM_PWM_ConfigChannel+0x188>)
800161c: 400a ands r2, r1
800161e: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8001620: 68fb ldr r3, [r7, #12]
8001622: 681b ldr r3, [r3, #0]
8001624: 69d9 ldr r1, [r3, #28]
8001626: 68bb ldr r3, [r7, #8]
8001628: 691b ldr r3, [r3, #16]
800162a: 021a lsls r2, r3, #8
800162c: 68fb ldr r3, [r7, #12]
800162e: 681b ldr r3, [r3, #0]
8001630: 430a orrs r2, r1
8001632: 61da str r2, [r3, #28]
break;
8001634: e004 b.n 8001640 <HAL_TIM_PWM_ConfigChannel+0x170>
}
default:
status = HAL_ERROR;
8001636: 2317 movs r3, #23
8001638: 18fb adds r3, r7, r3
800163a: 2201 movs r2, #1
800163c: 701a strb r2, [r3, #0]
break;
800163e: 46c0 nop @ (mov r8, r8)
}
__HAL_UNLOCK(htim);
8001640: 68fb ldr r3, [r7, #12]
8001642: 223c movs r2, #60 @ 0x3c
8001644: 2100 movs r1, #0
8001646: 5499 strb r1, [r3, r2]
return status;
8001648: 2317 movs r3, #23
800164a: 18fb adds r3, r7, r3
800164c: 781b ldrb r3, [r3, #0]
}
800164e: 0018 movs r0, r3
8001650: 46bd mov sp, r7
8001652: b006 add sp, #24
8001654: bd80 pop {r7, pc}
8001656: 46c0 nop @ (mov r8, r8)
8001658: fffffbff .word 0xfffffbff
0800165c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
800165c: b580 push {r7, lr}
800165e: b084 sub sp, #16
8001660: af00 add r7, sp, #0
8001662: 6078 str r0, [r7, #4]
8001664: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8001666: 687b ldr r3, [r7, #4]
8001668: 681b ldr r3, [r3, #0]
800166a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800166c: 687b ldr r3, [r7, #4]
800166e: 4a32 ldr r2, [pc, #200] @ (8001738 <TIM_Base_SetConfig+0xdc>)
8001670: 4293 cmp r3, r2
8001672: d003 beq.n 800167c <TIM_Base_SetConfig+0x20>
8001674: 687b ldr r3, [r7, #4]
8001676: 4a31 ldr r2, [pc, #196] @ (800173c <TIM_Base_SetConfig+0xe0>)
8001678: 4293 cmp r3, r2
800167a: d108 bne.n 800168e <TIM_Base_SetConfig+0x32>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800167c: 68fb ldr r3, [r7, #12]
800167e: 2270 movs r2, #112 @ 0x70
8001680: 4393 bics r3, r2
8001682: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8001684: 683b ldr r3, [r7, #0]
8001686: 685b ldr r3, [r3, #4]
8001688: 68fa ldr r2, [r7, #12]
800168a: 4313 orrs r3, r2
800168c: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800168e: 687b ldr r3, [r7, #4]
8001690: 4a29 ldr r2, [pc, #164] @ (8001738 <TIM_Base_SetConfig+0xdc>)
8001692: 4293 cmp r3, r2
8001694: d00f beq.n 80016b6 <TIM_Base_SetConfig+0x5a>
8001696: 687b ldr r3, [r7, #4]
8001698: 4a28 ldr r2, [pc, #160] @ (800173c <TIM_Base_SetConfig+0xe0>)
800169a: 4293 cmp r3, r2
800169c: d00b beq.n 80016b6 <TIM_Base_SetConfig+0x5a>
800169e: 687b ldr r3, [r7, #4]
80016a0: 4a27 ldr r2, [pc, #156] @ (8001740 <TIM_Base_SetConfig+0xe4>)
80016a2: 4293 cmp r3, r2
80016a4: d007 beq.n 80016b6 <TIM_Base_SetConfig+0x5a>
80016a6: 687b ldr r3, [r7, #4]
80016a8: 4a26 ldr r2, [pc, #152] @ (8001744 <TIM_Base_SetConfig+0xe8>)
80016aa: 4293 cmp r3, r2
80016ac: d003 beq.n 80016b6 <TIM_Base_SetConfig+0x5a>
80016ae: 687b ldr r3, [r7, #4]
80016b0: 4a25 ldr r2, [pc, #148] @ (8001748 <TIM_Base_SetConfig+0xec>)
80016b2: 4293 cmp r3, r2
80016b4: d108 bne.n 80016c8 <TIM_Base_SetConfig+0x6c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80016b6: 68fb ldr r3, [r7, #12]
80016b8: 4a24 ldr r2, [pc, #144] @ (800174c <TIM_Base_SetConfig+0xf0>)
80016ba: 4013 ands r3, r2
80016bc: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80016be: 683b ldr r3, [r7, #0]
80016c0: 68db ldr r3, [r3, #12]
80016c2: 68fa ldr r2, [r7, #12]
80016c4: 4313 orrs r3, r2
80016c6: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80016c8: 68fb ldr r3, [r7, #12]
80016ca: 2280 movs r2, #128 @ 0x80
80016cc: 4393 bics r3, r2
80016ce: 001a movs r2, r3
80016d0: 683b ldr r3, [r7, #0]
80016d2: 695b ldr r3, [r3, #20]
80016d4: 4313 orrs r3, r2
80016d6: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80016d8: 687b ldr r3, [r7, #4]
80016da: 68fa ldr r2, [r7, #12]
80016dc: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80016de: 683b ldr r3, [r7, #0]
80016e0: 689a ldr r2, [r3, #8]
80016e2: 687b ldr r3, [r7, #4]
80016e4: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80016e6: 683b ldr r3, [r7, #0]
80016e8: 681a ldr r2, [r3, #0]
80016ea: 687b ldr r3, [r7, #4]
80016ec: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80016ee: 687b ldr r3, [r7, #4]
80016f0: 4a11 ldr r2, [pc, #68] @ (8001738 <TIM_Base_SetConfig+0xdc>)
80016f2: 4293 cmp r3, r2
80016f4: d007 beq.n 8001706 <TIM_Base_SetConfig+0xaa>
80016f6: 687b ldr r3, [r7, #4]
80016f8: 4a12 ldr r2, [pc, #72] @ (8001744 <TIM_Base_SetConfig+0xe8>)
80016fa: 4293 cmp r3, r2
80016fc: d003 beq.n 8001706 <TIM_Base_SetConfig+0xaa>
80016fe: 687b ldr r3, [r7, #4]
8001700: 4a11 ldr r2, [pc, #68] @ (8001748 <TIM_Base_SetConfig+0xec>)
8001702: 4293 cmp r3, r2
8001704: d103 bne.n 800170e <TIM_Base_SetConfig+0xb2>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8001706: 683b ldr r3, [r7, #0]
8001708: 691a ldr r2, [r3, #16]
800170a: 687b ldr r3, [r7, #4]
800170c: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800170e: 687b ldr r3, [r7, #4]
8001710: 2201 movs r2, #1
8001712: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8001714: 687b ldr r3, [r7, #4]
8001716: 691b ldr r3, [r3, #16]
8001718: 2201 movs r2, #1
800171a: 4013 ands r3, r2
800171c: 2b01 cmp r3, #1
800171e: d106 bne.n 800172e <TIM_Base_SetConfig+0xd2>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8001720: 687b ldr r3, [r7, #4]
8001722: 691b ldr r3, [r3, #16]
8001724: 2201 movs r2, #1
8001726: 4393 bics r3, r2
8001728: 001a movs r2, r3
800172a: 687b ldr r3, [r7, #4]
800172c: 611a str r2, [r3, #16]
}
}
800172e: 46c0 nop @ (mov r8, r8)
8001730: 46bd mov sp, r7
8001732: b004 add sp, #16
8001734: bd80 pop {r7, pc}
8001736: 46c0 nop @ (mov r8, r8)
8001738: 40012c00 .word 0x40012c00
800173c: 40000400 .word 0x40000400
8001740: 40002000 .word 0x40002000
8001744: 40014400 .word 0x40014400
8001748: 40014800 .word 0x40014800
800174c: fffffcff .word 0xfffffcff
08001750 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001750: b580 push {r7, lr}
8001752: b086 sub sp, #24
8001754: af00 add r7, sp, #0
8001756: 6078 str r0, [r7, #4]
8001758: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800175a: 687b ldr r3, [r7, #4]
800175c: 6a1b ldr r3, [r3, #32]
800175e: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8001760: 687b ldr r3, [r7, #4]
8001762: 6a1b ldr r3, [r3, #32]
8001764: 2201 movs r2, #1
8001766: 4393 bics r3, r2
8001768: 001a movs r2, r3
800176a: 687b ldr r3, [r7, #4]
800176c: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800176e: 687b ldr r3, [r7, #4]
8001770: 685b ldr r3, [r3, #4]
8001772: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001774: 687b ldr r3, [r7, #4]
8001776: 699b ldr r3, [r3, #24]
8001778: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800177a: 68fb ldr r3, [r7, #12]
800177c: 2270 movs r2, #112 @ 0x70
800177e: 4393 bics r3, r2
8001780: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8001782: 68fb ldr r3, [r7, #12]
8001784: 2203 movs r2, #3
8001786: 4393 bics r3, r2
8001788: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800178a: 683b ldr r3, [r7, #0]
800178c: 681b ldr r3, [r3, #0]
800178e: 68fa ldr r2, [r7, #12]
8001790: 4313 orrs r3, r2
8001792: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8001794: 697b ldr r3, [r7, #20]
8001796: 2202 movs r2, #2
8001798: 4393 bics r3, r2
800179a: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800179c: 683b ldr r3, [r7, #0]
800179e: 689b ldr r3, [r3, #8]
80017a0: 697a ldr r2, [r7, #20]
80017a2: 4313 orrs r3, r2
80017a4: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
80017a6: 687b ldr r3, [r7, #4]
80017a8: 4a23 ldr r2, [pc, #140] @ (8001838 <TIM_OC1_SetConfig+0xe8>)
80017aa: 4293 cmp r3, r2
80017ac: d007 beq.n 80017be <TIM_OC1_SetConfig+0x6e>
80017ae: 687b ldr r3, [r7, #4]
80017b0: 4a22 ldr r2, [pc, #136] @ (800183c <TIM_OC1_SetConfig+0xec>)
80017b2: 4293 cmp r3, r2
80017b4: d003 beq.n 80017be <TIM_OC1_SetConfig+0x6e>
80017b6: 687b ldr r3, [r7, #4]
80017b8: 4a21 ldr r2, [pc, #132] @ (8001840 <TIM_OC1_SetConfig+0xf0>)
80017ba: 4293 cmp r3, r2
80017bc: d10c bne.n 80017d8 <TIM_OC1_SetConfig+0x88>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
80017be: 697b ldr r3, [r7, #20]
80017c0: 2208 movs r2, #8
80017c2: 4393 bics r3, r2
80017c4: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
80017c6: 683b ldr r3, [r7, #0]
80017c8: 68db ldr r3, [r3, #12]
80017ca: 697a ldr r2, [r7, #20]
80017cc: 4313 orrs r3, r2
80017ce: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
80017d0: 697b ldr r3, [r7, #20]
80017d2: 2204 movs r2, #4
80017d4: 4393 bics r3, r2
80017d6: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80017d8: 687b ldr r3, [r7, #4]
80017da: 4a17 ldr r2, [pc, #92] @ (8001838 <TIM_OC1_SetConfig+0xe8>)
80017dc: 4293 cmp r3, r2
80017de: d007 beq.n 80017f0 <TIM_OC1_SetConfig+0xa0>
80017e0: 687b ldr r3, [r7, #4]
80017e2: 4a16 ldr r2, [pc, #88] @ (800183c <TIM_OC1_SetConfig+0xec>)
80017e4: 4293 cmp r3, r2
80017e6: d003 beq.n 80017f0 <TIM_OC1_SetConfig+0xa0>
80017e8: 687b ldr r3, [r7, #4]
80017ea: 4a15 ldr r2, [pc, #84] @ (8001840 <TIM_OC1_SetConfig+0xf0>)
80017ec: 4293 cmp r3, r2
80017ee: d111 bne.n 8001814 <TIM_OC1_SetConfig+0xc4>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
80017f0: 693b ldr r3, [r7, #16]
80017f2: 4a14 ldr r2, [pc, #80] @ (8001844 <TIM_OC1_SetConfig+0xf4>)
80017f4: 4013 ands r3, r2
80017f6: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
80017f8: 693b ldr r3, [r7, #16]
80017fa: 4a13 ldr r2, [pc, #76] @ (8001848 <TIM_OC1_SetConfig+0xf8>)
80017fc: 4013 ands r3, r2
80017fe: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8001800: 683b ldr r3, [r7, #0]
8001802: 695b ldr r3, [r3, #20]
8001804: 693a ldr r2, [r7, #16]
8001806: 4313 orrs r3, r2
8001808: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800180a: 683b ldr r3, [r7, #0]
800180c: 699b ldr r3, [r3, #24]
800180e: 693a ldr r2, [r7, #16]
8001810: 4313 orrs r3, r2
8001812: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001814: 687b ldr r3, [r7, #4]
8001816: 693a ldr r2, [r7, #16]
8001818: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800181a: 687b ldr r3, [r7, #4]
800181c: 68fa ldr r2, [r7, #12]
800181e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8001820: 683b ldr r3, [r7, #0]
8001822: 685a ldr r2, [r3, #4]
8001824: 687b ldr r3, [r7, #4]
8001826: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001828: 687b ldr r3, [r7, #4]
800182a: 697a ldr r2, [r7, #20]
800182c: 621a str r2, [r3, #32]
}
800182e: 46c0 nop @ (mov r8, r8)
8001830: 46bd mov sp, r7
8001832: b006 add sp, #24
8001834: bd80 pop {r7, pc}
8001836: 46c0 nop @ (mov r8, r8)
8001838: 40012c00 .word 0x40012c00
800183c: 40014400 .word 0x40014400
8001840: 40014800 .word 0x40014800
8001844: fffffeff .word 0xfffffeff
8001848: fffffdff .word 0xfffffdff
0800184c <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800184c: b580 push {r7, lr}
800184e: b086 sub sp, #24
8001850: af00 add r7, sp, #0
8001852: 6078 str r0, [r7, #4]
8001854: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001856: 687b ldr r3, [r7, #4]
8001858: 6a1b ldr r3, [r3, #32]
800185a: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800185c: 687b ldr r3, [r7, #4]
800185e: 6a1b ldr r3, [r3, #32]
8001860: 2210 movs r2, #16
8001862: 4393 bics r3, r2
8001864: 001a movs r2, r3
8001866: 687b ldr r3, [r7, #4]
8001868: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800186a: 687b ldr r3, [r7, #4]
800186c: 685b ldr r3, [r3, #4]
800186e: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001870: 687b ldr r3, [r7, #4]
8001872: 699b ldr r3, [r3, #24]
8001874: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8001876: 68fb ldr r3, [r7, #12]
8001878: 4a2c ldr r2, [pc, #176] @ (800192c <TIM_OC2_SetConfig+0xe0>)
800187a: 4013 ands r3, r2
800187c: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800187e: 68fb ldr r3, [r7, #12]
8001880: 4a2b ldr r2, [pc, #172] @ (8001930 <TIM_OC2_SetConfig+0xe4>)
8001882: 4013 ands r3, r2
8001884: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001886: 683b ldr r3, [r7, #0]
8001888: 681b ldr r3, [r3, #0]
800188a: 021b lsls r3, r3, #8
800188c: 68fa ldr r2, [r7, #12]
800188e: 4313 orrs r3, r2
8001890: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8001892: 697b ldr r3, [r7, #20]
8001894: 2220 movs r2, #32
8001896: 4393 bics r3, r2
8001898: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
800189a: 683b ldr r3, [r7, #0]
800189c: 689b ldr r3, [r3, #8]
800189e: 011b lsls r3, r3, #4
80018a0: 697a ldr r2, [r7, #20]
80018a2: 4313 orrs r3, r2
80018a4: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
80018a6: 687b ldr r3, [r7, #4]
80018a8: 4a22 ldr r2, [pc, #136] @ (8001934 <TIM_OC2_SetConfig+0xe8>)
80018aa: 4293 cmp r3, r2
80018ac: d10d bne.n 80018ca <TIM_OC2_SetConfig+0x7e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
80018ae: 697b ldr r3, [r7, #20]
80018b0: 2280 movs r2, #128 @ 0x80
80018b2: 4393 bics r3, r2
80018b4: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
80018b6: 683b ldr r3, [r7, #0]
80018b8: 68db ldr r3, [r3, #12]
80018ba: 011b lsls r3, r3, #4
80018bc: 697a ldr r2, [r7, #20]
80018be: 4313 orrs r3, r2
80018c0: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
80018c2: 697b ldr r3, [r7, #20]
80018c4: 2240 movs r2, #64 @ 0x40
80018c6: 4393 bics r3, r2
80018c8: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80018ca: 687b ldr r3, [r7, #4]
80018cc: 4a19 ldr r2, [pc, #100] @ (8001934 <TIM_OC2_SetConfig+0xe8>)
80018ce: 4293 cmp r3, r2
80018d0: d007 beq.n 80018e2 <TIM_OC2_SetConfig+0x96>
80018d2: 687b ldr r3, [r7, #4]
80018d4: 4a18 ldr r2, [pc, #96] @ (8001938 <TIM_OC2_SetConfig+0xec>)
80018d6: 4293 cmp r3, r2
80018d8: d003 beq.n 80018e2 <TIM_OC2_SetConfig+0x96>
80018da: 687b ldr r3, [r7, #4]
80018dc: 4a17 ldr r2, [pc, #92] @ (800193c <TIM_OC2_SetConfig+0xf0>)
80018de: 4293 cmp r3, r2
80018e0: d113 bne.n 800190a <TIM_OC2_SetConfig+0xbe>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
80018e2: 693b ldr r3, [r7, #16]
80018e4: 4a16 ldr r2, [pc, #88] @ (8001940 <TIM_OC2_SetConfig+0xf4>)
80018e6: 4013 ands r3, r2
80018e8: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
80018ea: 693b ldr r3, [r7, #16]
80018ec: 4a15 ldr r2, [pc, #84] @ (8001944 <TIM_OC2_SetConfig+0xf8>)
80018ee: 4013 ands r3, r2
80018f0: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
80018f2: 683b ldr r3, [r7, #0]
80018f4: 695b ldr r3, [r3, #20]
80018f6: 009b lsls r3, r3, #2
80018f8: 693a ldr r2, [r7, #16]
80018fa: 4313 orrs r3, r2
80018fc: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
80018fe: 683b ldr r3, [r7, #0]
8001900: 699b ldr r3, [r3, #24]
8001902: 009b lsls r3, r3, #2
8001904: 693a ldr r2, [r7, #16]
8001906: 4313 orrs r3, r2
8001908: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800190a: 687b ldr r3, [r7, #4]
800190c: 693a ldr r2, [r7, #16]
800190e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001910: 687b ldr r3, [r7, #4]
8001912: 68fa ldr r2, [r7, #12]
8001914: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8001916: 683b ldr r3, [r7, #0]
8001918: 685a ldr r2, [r3, #4]
800191a: 687b ldr r3, [r7, #4]
800191c: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800191e: 687b ldr r3, [r7, #4]
8001920: 697a ldr r2, [r7, #20]
8001922: 621a str r2, [r3, #32]
}
8001924: 46c0 nop @ (mov r8, r8)
8001926: 46bd mov sp, r7
8001928: b006 add sp, #24
800192a: bd80 pop {r7, pc}
800192c: ffff8fff .word 0xffff8fff
8001930: fffffcff .word 0xfffffcff
8001934: 40012c00 .word 0x40012c00
8001938: 40014400 .word 0x40014400
800193c: 40014800 .word 0x40014800
8001940: fffffbff .word 0xfffffbff
8001944: fffff7ff .word 0xfffff7ff
08001948 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001948: b580 push {r7, lr}
800194a: b086 sub sp, #24
800194c: af00 add r7, sp, #0
800194e: 6078 str r0, [r7, #4]
8001950: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001952: 687b ldr r3, [r7, #4]
8001954: 6a1b ldr r3, [r3, #32]
8001956: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8001958: 687b ldr r3, [r7, #4]
800195a: 6a1b ldr r3, [r3, #32]
800195c: 4a31 ldr r2, [pc, #196] @ (8001a24 <TIM_OC3_SetConfig+0xdc>)
800195e: 401a ands r2, r3
8001960: 687b ldr r3, [r7, #4]
8001962: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001964: 687b ldr r3, [r7, #4]
8001966: 685b ldr r3, [r3, #4]
8001968: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800196a: 687b ldr r3, [r7, #4]
800196c: 69db ldr r3, [r3, #28]
800196e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8001970: 68fb ldr r3, [r7, #12]
8001972: 2270 movs r2, #112 @ 0x70
8001974: 4393 bics r3, r2
8001976: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8001978: 68fb ldr r3, [r7, #12]
800197a: 2203 movs r2, #3
800197c: 4393 bics r3, r2
800197e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001980: 683b ldr r3, [r7, #0]
8001982: 681b ldr r3, [r3, #0]
8001984: 68fa ldr r2, [r7, #12]
8001986: 4313 orrs r3, r2
8001988: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800198a: 697b ldr r3, [r7, #20]
800198c: 4a26 ldr r2, [pc, #152] @ (8001a28 <TIM_OC3_SetConfig+0xe0>)
800198e: 4013 ands r3, r2
8001990: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8001992: 683b ldr r3, [r7, #0]
8001994: 689b ldr r3, [r3, #8]
8001996: 021b lsls r3, r3, #8
8001998: 697a ldr r2, [r7, #20]
800199a: 4313 orrs r3, r2
800199c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800199e: 687b ldr r3, [r7, #4]
80019a0: 4a22 ldr r2, [pc, #136] @ (8001a2c <TIM_OC3_SetConfig+0xe4>)
80019a2: 4293 cmp r3, r2
80019a4: d10d bne.n 80019c2 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
80019a6: 697b ldr r3, [r7, #20]
80019a8: 4a21 ldr r2, [pc, #132] @ (8001a30 <TIM_OC3_SetConfig+0xe8>)
80019aa: 4013 ands r3, r2
80019ac: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80019ae: 683b ldr r3, [r7, #0]
80019b0: 68db ldr r3, [r3, #12]
80019b2: 021b lsls r3, r3, #8
80019b4: 697a ldr r2, [r7, #20]
80019b6: 4313 orrs r3, r2
80019b8: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
80019ba: 697b ldr r3, [r7, #20]
80019bc: 4a1d ldr r2, [pc, #116] @ (8001a34 <TIM_OC3_SetConfig+0xec>)
80019be: 4013 ands r3, r2
80019c0: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80019c2: 687b ldr r3, [r7, #4]
80019c4: 4a19 ldr r2, [pc, #100] @ (8001a2c <TIM_OC3_SetConfig+0xe4>)
80019c6: 4293 cmp r3, r2
80019c8: d007 beq.n 80019da <TIM_OC3_SetConfig+0x92>
80019ca: 687b ldr r3, [r7, #4]
80019cc: 4a1a ldr r2, [pc, #104] @ (8001a38 <TIM_OC3_SetConfig+0xf0>)
80019ce: 4293 cmp r3, r2
80019d0: d003 beq.n 80019da <TIM_OC3_SetConfig+0x92>
80019d2: 687b ldr r3, [r7, #4]
80019d4: 4a19 ldr r2, [pc, #100] @ (8001a3c <TIM_OC3_SetConfig+0xf4>)
80019d6: 4293 cmp r3, r2
80019d8: d113 bne.n 8001a02 <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
80019da: 693b ldr r3, [r7, #16]
80019dc: 4a18 ldr r2, [pc, #96] @ (8001a40 <TIM_OC3_SetConfig+0xf8>)
80019de: 4013 ands r3, r2
80019e0: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
80019e2: 693b ldr r3, [r7, #16]
80019e4: 4a17 ldr r2, [pc, #92] @ (8001a44 <TIM_OC3_SetConfig+0xfc>)
80019e6: 4013 ands r3, r2
80019e8: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
80019ea: 683b ldr r3, [r7, #0]
80019ec: 695b ldr r3, [r3, #20]
80019ee: 011b lsls r3, r3, #4
80019f0: 693a ldr r2, [r7, #16]
80019f2: 4313 orrs r3, r2
80019f4: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
80019f6: 683b ldr r3, [r7, #0]
80019f8: 699b ldr r3, [r3, #24]
80019fa: 011b lsls r3, r3, #4
80019fc: 693a ldr r2, [r7, #16]
80019fe: 4313 orrs r3, r2
8001a00: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001a02: 687b ldr r3, [r7, #4]
8001a04: 693a ldr r2, [r7, #16]
8001a06: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 68fa ldr r2, [r7, #12]
8001a0c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8001a0e: 683b ldr r3, [r7, #0]
8001a10: 685a ldr r2, [r3, #4]
8001a12: 687b ldr r3, [r7, #4]
8001a14: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001a16: 687b ldr r3, [r7, #4]
8001a18: 697a ldr r2, [r7, #20]
8001a1a: 621a str r2, [r3, #32]
}
8001a1c: 46c0 nop @ (mov r8, r8)
8001a1e: 46bd mov sp, r7
8001a20: b006 add sp, #24
8001a22: bd80 pop {r7, pc}
8001a24: fffffeff .word 0xfffffeff
8001a28: fffffdff .word 0xfffffdff
8001a2c: 40012c00 .word 0x40012c00
8001a30: fffff7ff .word 0xfffff7ff
8001a34: fffffbff .word 0xfffffbff
8001a38: 40014400 .word 0x40014400
8001a3c: 40014800 .word 0x40014800
8001a40: ffffefff .word 0xffffefff
8001a44: ffffdfff .word 0xffffdfff
08001a48 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8001a48: b580 push {r7, lr}
8001a4a: b086 sub sp, #24
8001a4c: af00 add r7, sp, #0
8001a4e: 6078 str r0, [r7, #4]
8001a50: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001a52: 687b ldr r3, [r7, #4]
8001a54: 6a1b ldr r3, [r3, #32]
8001a56: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8001a58: 687b ldr r3, [r7, #4]
8001a5a: 6a1b ldr r3, [r3, #32]
8001a5c: 4a24 ldr r2, [pc, #144] @ (8001af0 <TIM_OC4_SetConfig+0xa8>)
8001a5e: 401a ands r2, r3
8001a60: 687b ldr r3, [r7, #4]
8001a62: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001a64: 687b ldr r3, [r7, #4]
8001a66: 685b ldr r3, [r3, #4]
8001a68: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001a6a: 687b ldr r3, [r7, #4]
8001a6c: 69db ldr r3, [r3, #28]
8001a6e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8001a70: 68fb ldr r3, [r7, #12]
8001a72: 4a20 ldr r2, [pc, #128] @ (8001af4 <TIM_OC4_SetConfig+0xac>)
8001a74: 4013 ands r3, r2
8001a76: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8001a78: 68fb ldr r3, [r7, #12]
8001a7a: 4a1f ldr r2, [pc, #124] @ (8001af8 <TIM_OC4_SetConfig+0xb0>)
8001a7c: 4013 ands r3, r2
8001a7e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001a80: 683b ldr r3, [r7, #0]
8001a82: 681b ldr r3, [r3, #0]
8001a84: 021b lsls r3, r3, #8
8001a86: 68fa ldr r2, [r7, #12]
8001a88: 4313 orrs r3, r2
8001a8a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8001a8c: 693b ldr r3, [r7, #16]
8001a8e: 4a1b ldr r2, [pc, #108] @ (8001afc <TIM_OC4_SetConfig+0xb4>)
8001a90: 4013 ands r3, r2
8001a92: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8001a94: 683b ldr r3, [r7, #0]
8001a96: 689b ldr r3, [r3, #8]
8001a98: 031b lsls r3, r3, #12
8001a9a: 693a ldr r2, [r7, #16]
8001a9c: 4313 orrs r3, r2
8001a9e: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001aa0: 687b ldr r3, [r7, #4]
8001aa2: 4a17 ldr r2, [pc, #92] @ (8001b00 <TIM_OC4_SetConfig+0xb8>)
8001aa4: 4293 cmp r3, r2
8001aa6: d007 beq.n 8001ab8 <TIM_OC4_SetConfig+0x70>
8001aa8: 687b ldr r3, [r7, #4]
8001aaa: 4a16 ldr r2, [pc, #88] @ (8001b04 <TIM_OC4_SetConfig+0xbc>)
8001aac: 4293 cmp r3, r2
8001aae: d003 beq.n 8001ab8 <TIM_OC4_SetConfig+0x70>
8001ab0: 687b ldr r3, [r7, #4]
8001ab2: 4a15 ldr r2, [pc, #84] @ (8001b08 <TIM_OC4_SetConfig+0xc0>)
8001ab4: 4293 cmp r3, r2
8001ab6: d109 bne.n 8001acc <TIM_OC4_SetConfig+0x84>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8001ab8: 697b ldr r3, [r7, #20]
8001aba: 4a14 ldr r2, [pc, #80] @ (8001b0c <TIM_OC4_SetConfig+0xc4>)
8001abc: 4013 ands r3, r2
8001abe: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8001ac0: 683b ldr r3, [r7, #0]
8001ac2: 695b ldr r3, [r3, #20]
8001ac4: 019b lsls r3, r3, #6
8001ac6: 697a ldr r2, [r7, #20]
8001ac8: 4313 orrs r3, r2
8001aca: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001acc: 687b ldr r3, [r7, #4]
8001ace: 697a ldr r2, [r7, #20]
8001ad0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001ad2: 687b ldr r3, [r7, #4]
8001ad4: 68fa ldr r2, [r7, #12]
8001ad6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8001ad8: 683b ldr r3, [r7, #0]
8001ada: 685a ldr r2, [r3, #4]
8001adc: 687b ldr r3, [r7, #4]
8001ade: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001ae0: 687b ldr r3, [r7, #4]
8001ae2: 693a ldr r2, [r7, #16]
8001ae4: 621a str r2, [r3, #32]
}
8001ae6: 46c0 nop @ (mov r8, r8)
8001ae8: 46bd mov sp, r7
8001aea: b006 add sp, #24
8001aec: bd80 pop {r7, pc}
8001aee: 46c0 nop @ (mov r8, r8)
8001af0: ffffefff .word 0xffffefff
8001af4: ffff8fff .word 0xffff8fff
8001af8: fffffcff .word 0xfffffcff
8001afc: ffffdfff .word 0xffffdfff
8001b00: 40012c00 .word 0x40012c00
8001b04: 40014400 .word 0x40014400
8001b08: 40014800 .word 0x40014800
8001b0c: ffffbfff .word 0xffffbfff
08001b10 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8001b10: b580 push {r7, lr}
8001b12: b084 sub sp, #16
8001b14: af00 add r7, sp, #0
8001b16: 6078 str r0, [r7, #4]
8001b18: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8001b1a: 687b ldr r3, [r7, #4]
8001b1c: 223c movs r2, #60 @ 0x3c
8001b1e: 5c9b ldrb r3, [r3, r2]
8001b20: 2b01 cmp r3, #1
8001b22: d101 bne.n 8001b28 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8001b24: 2302 movs r3, #2
8001b26: e03c b.n 8001ba2 <HAL_TIMEx_MasterConfigSynchronization+0x92>
8001b28: 687b ldr r3, [r7, #4]
8001b2a: 223c movs r2, #60 @ 0x3c
8001b2c: 2101 movs r1, #1
8001b2e: 5499 strb r1, [r3, r2]
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8001b30: 687b ldr r3, [r7, #4]
8001b32: 223d movs r2, #61 @ 0x3d
8001b34: 2102 movs r1, #2
8001b36: 5499 strb r1, [r3, r2]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 681b ldr r3, [r3, #0]
8001b3c: 685b ldr r3, [r3, #4]
8001b3e: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8001b40: 687b ldr r3, [r7, #4]
8001b42: 681b ldr r3, [r3, #0]
8001b44: 689b ldr r3, [r3, #8]
8001b46: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8001b48: 68fb ldr r3, [r7, #12]
8001b4a: 2270 movs r2, #112 @ 0x70
8001b4c: 4393 bics r3, r2
8001b4e: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8001b50: 683b ldr r3, [r7, #0]
8001b52: 681b ldr r3, [r3, #0]
8001b54: 68fa ldr r2, [r7, #12]
8001b56: 4313 orrs r3, r2
8001b58: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 681b ldr r3, [r3, #0]
8001b5e: 68fa ldr r2, [r7, #12]
8001b60: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001b62: 687b ldr r3, [r7, #4]
8001b64: 681b ldr r3, [r3, #0]
8001b66: 4a11 ldr r2, [pc, #68] @ (8001bac <HAL_TIMEx_MasterConfigSynchronization+0x9c>)
8001b68: 4293 cmp r3, r2
8001b6a: d004 beq.n 8001b76 <HAL_TIMEx_MasterConfigSynchronization+0x66>
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 681b ldr r3, [r3, #0]
8001b70: 4a0f ldr r2, [pc, #60] @ (8001bb0 <HAL_TIMEx_MasterConfigSynchronization+0xa0>)
8001b72: 4293 cmp r3, r2
8001b74: d10c bne.n 8001b90 <HAL_TIMEx_MasterConfigSynchronization+0x80>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8001b76: 68bb ldr r3, [r7, #8]
8001b78: 2280 movs r2, #128 @ 0x80
8001b7a: 4393 bics r3, r2
8001b7c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8001b7e: 683b ldr r3, [r7, #0]
8001b80: 685b ldr r3, [r3, #4]
8001b82: 68ba ldr r2, [r7, #8]
8001b84: 4313 orrs r3, r2
8001b86: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8001b88: 687b ldr r3, [r7, #4]
8001b8a: 681b ldr r3, [r3, #0]
8001b8c: 68ba ldr r2, [r7, #8]
8001b8e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8001b90: 687b ldr r3, [r7, #4]
8001b92: 223d movs r2, #61 @ 0x3d
8001b94: 2101 movs r1, #1
8001b96: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
8001b98: 687b ldr r3, [r7, #4]
8001b9a: 223c movs r2, #60 @ 0x3c
8001b9c: 2100 movs r1, #0
8001b9e: 5499 strb r1, [r3, r2]
return HAL_OK;
8001ba0: 2300 movs r3, #0
}
8001ba2: 0018 movs r0, r3
8001ba4: 46bd mov sp, r7
8001ba6: b004 add sp, #16
8001ba8: bd80 pop {r7, pc}
8001baa: 46c0 nop @ (mov r8, r8)
8001bac: 40012c00 .word 0x40012c00
8001bb0: 40000400 .word 0x40000400
08001bb4 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8001bb4: b580 push {r7, lr}
8001bb6: b084 sub sp, #16
8001bb8: af00 add r7, sp, #0
8001bba: 6078 str r0, [r7, #4]
8001bbc: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8001bbe: 2300 movs r3, #0
8001bc0: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8001bc2: 687b ldr r3, [r7, #4]
8001bc4: 223c movs r2, #60 @ 0x3c
8001bc6: 5c9b ldrb r3, [r3, r2]
8001bc8: 2b01 cmp r3, #1
8001bca: d101 bne.n 8001bd0 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8001bcc: 2302 movs r3, #2
8001bce: e03e b.n 8001c4e <HAL_TIMEx_ConfigBreakDeadTime+0x9a>
8001bd0: 687b ldr r3, [r7, #4]
8001bd2: 223c movs r2, #60 @ 0x3c
8001bd4: 2101 movs r1, #1
8001bd6: 5499 strb r1, [r3, r2]
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8001bd8: 68fb ldr r3, [r7, #12]
8001bda: 22ff movs r2, #255 @ 0xff
8001bdc: 4393 bics r3, r2
8001bde: 001a movs r2, r3
8001be0: 683b ldr r3, [r7, #0]
8001be2: 68db ldr r3, [r3, #12]
8001be4: 4313 orrs r3, r2
8001be6: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8001be8: 68fb ldr r3, [r7, #12]
8001bea: 4a1b ldr r2, [pc, #108] @ (8001c58 <HAL_TIMEx_ConfigBreakDeadTime+0xa4>)
8001bec: 401a ands r2, r3
8001bee: 683b ldr r3, [r7, #0]
8001bf0: 689b ldr r3, [r3, #8]
8001bf2: 4313 orrs r3, r2
8001bf4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8001bf6: 68fb ldr r3, [r7, #12]
8001bf8: 4a18 ldr r2, [pc, #96] @ (8001c5c <HAL_TIMEx_ConfigBreakDeadTime+0xa8>)
8001bfa: 401a ands r2, r3
8001bfc: 683b ldr r3, [r7, #0]
8001bfe: 685b ldr r3, [r3, #4]
8001c00: 4313 orrs r3, r2
8001c02: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8001c04: 68fb ldr r3, [r7, #12]
8001c06: 4a16 ldr r2, [pc, #88] @ (8001c60 <HAL_TIMEx_ConfigBreakDeadTime+0xac>)
8001c08: 401a ands r2, r3
8001c0a: 683b ldr r3, [r7, #0]
8001c0c: 681b ldr r3, [r3, #0]
8001c0e: 4313 orrs r3, r2
8001c10: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8001c12: 68fb ldr r3, [r7, #12]
8001c14: 4a13 ldr r2, [pc, #76] @ (8001c64 <HAL_TIMEx_ConfigBreakDeadTime+0xb0>)
8001c16: 401a ands r2, r3
8001c18: 683b ldr r3, [r7, #0]
8001c1a: 691b ldr r3, [r3, #16]
8001c1c: 4313 orrs r3, r2
8001c1e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8001c20: 68fb ldr r3, [r7, #12]
8001c22: 4a11 ldr r2, [pc, #68] @ (8001c68 <HAL_TIMEx_ConfigBreakDeadTime+0xb4>)
8001c24: 401a ands r2, r3
8001c26: 683b ldr r3, [r7, #0]
8001c28: 695b ldr r3, [r3, #20]
8001c2a: 4313 orrs r3, r2
8001c2c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8001c2e: 68fb ldr r3, [r7, #12]
8001c30: 4a0e ldr r2, [pc, #56] @ (8001c6c <HAL_TIMEx_ConfigBreakDeadTime+0xb8>)
8001c32: 401a ands r2, r3
8001c34: 683b ldr r3, [r7, #0]
8001c36: 69db ldr r3, [r3, #28]
8001c38: 4313 orrs r3, r2
8001c3a: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8001c3c: 687b ldr r3, [r7, #4]
8001c3e: 681b ldr r3, [r3, #0]
8001c40: 68fa ldr r2, [r7, #12]
8001c42: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
8001c44: 687b ldr r3, [r7, #4]
8001c46: 223c movs r2, #60 @ 0x3c
8001c48: 2100 movs r1, #0
8001c4a: 5499 strb r1, [r3, r2]
return HAL_OK;
8001c4c: 2300 movs r3, #0
}
8001c4e: 0018 movs r0, r3
8001c50: 46bd mov sp, r7
8001c52: b004 add sp, #16
8001c54: bd80 pop {r7, pc}
8001c56: 46c0 nop @ (mov r8, r8)
8001c58: fffffcff .word 0xfffffcff
8001c5c: fffffbff .word 0xfffffbff
8001c60: fffff7ff .word 0xfffff7ff
8001c64: ffffefff .word 0xffffefff
8001c68: ffffdfff .word 0xffffdfff
8001c6c: ffffbfff .word 0xffffbfff
08001c70 <memset>:
8001c70: 0003 movs r3, r0
8001c72: 1882 adds r2, r0, r2
8001c74: 4293 cmp r3, r2
8001c76: d100 bne.n 8001c7a <memset+0xa>
8001c78: 4770 bx lr
8001c7a: 7019 strb r1, [r3, #0]
8001c7c: 3301 adds r3, #1
8001c7e: e7f9 b.n 8001c74 <memset+0x4>
08001c80 <__libc_init_array>:
8001c80: b570 push {r4, r5, r6, lr}
8001c82: 2600 movs r6, #0
8001c84: 4c0c ldr r4, [pc, #48] @ (8001cb8 <__libc_init_array+0x38>)
8001c86: 4d0d ldr r5, [pc, #52] @ (8001cbc <__libc_init_array+0x3c>)
8001c88: 1b64 subs r4, r4, r5
8001c8a: 10a4 asrs r4, r4, #2
8001c8c: 42a6 cmp r6, r4
8001c8e: d109 bne.n 8001ca4 <__libc_init_array+0x24>
8001c90: 2600 movs r6, #0
8001c92: f000 f819 bl 8001cc8 <_init>
8001c96: 4c0a ldr r4, [pc, #40] @ (8001cc0 <__libc_init_array+0x40>)
8001c98: 4d0a ldr r5, [pc, #40] @ (8001cc4 <__libc_init_array+0x44>)
8001c9a: 1b64 subs r4, r4, r5
8001c9c: 10a4 asrs r4, r4, #2
8001c9e: 42a6 cmp r6, r4
8001ca0: d105 bne.n 8001cae <__libc_init_array+0x2e>
8001ca2: bd70 pop {r4, r5, r6, pc}
8001ca4: 00b3 lsls r3, r6, #2
8001ca6: 58eb ldr r3, [r5, r3]
8001ca8: 4798 blx r3
8001caa: 3601 adds r6, #1
8001cac: e7ee b.n 8001c8c <__libc_init_array+0xc>
8001cae: 00b3 lsls r3, r6, #2
8001cb0: 58eb ldr r3, [r5, r3]
8001cb2: 4798 blx r3
8001cb4: 3601 adds r6, #1
8001cb6: e7f2 b.n 8001c9e <__libc_init_array+0x1e>
8001cb8: 08001d10 .word 0x08001d10
8001cbc: 08001d10 .word 0x08001d10
8001cc0: 08001d14 .word 0x08001d14
8001cc4: 08001d10 .word 0x08001d10
08001cc8 <_init>:
8001cc8: b5f8 push {r3, r4, r5, r6, r7, lr}
8001cca: 46c0 nop @ (mov r8, r8)
8001ccc: bcf8 pop {r3, r4, r5, r6, r7}
8001cce: bc08 pop {r3}
8001cd0: 469e mov lr, r3
8001cd2: 4770 bx lr
08001cd4 <_fini>:
8001cd4: b5f8 push {r3, r4, r5, r6, r7, lr}
8001cd6: 46c0 nop @ (mov r8, r8)
8001cd8: bcf8 pop {r3, r4, r5, r6, r7}
8001cda: bc08 pop {r3}
8001cdc: 469e mov lr, r3
8001cde: 4770 bx lr
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