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3cb8b7d5057f03ef29bc32c7e040eaa81ca1baf0
AUTOM/workspace/AUTOM10/Debug/AUTOM10.list
andrea 3cb8b7d505 wip
2025-12-24 16:37:21 +01:00

29177 lines
1.1 MiB
Raw Blame History

AUTOM10.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000baac 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000002cc 0800bbb8 0800bbb8 0000cbb8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800be84 0800be84 0000d1d0 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800be84 0800be84 0000ce84 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800be8c 0800be8c 0000d1d0 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800be8c 0800be8c 0000ce8c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800be90 0800be90 0000ce90 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 000001d0 20000000 0800be94 0000d000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000164c 200001d0 0800c064 0000d1d0 2**3
ALLOC
10 ._user_heap_stack 00000604 2000181c 0800c064 0000d81c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000d1d0 2**0
CONTENTS, READONLY
12 .debug_info 000184fb 00000000 00000000 0000d1f9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000452e 00000000 00000000 000256f4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000015f8 00000000 00000000 00029c28 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000010d9 00000000 00000000 0002b220 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001c730 00000000 00000000 0002c2f9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001cc8c 00000000 00000000 00048a29 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00095753 00000000 00000000 000656b5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000fae08 2**0
CONTENTS, READONLY
20 .debug_frame 00005ef8 00000000 00000000 000fae4c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 00100d44 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 200001d0 .word 0x200001d0
8000128: 00000000 .word 0x00000000
800012c: 0800bba0 .word 0x0800bba0
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 200001d4 .word 0x200001d4
8000148: 0800bba0 .word 0x0800bba0
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <manageAdc>:
uint16_t ch5 ;
uint16_t ch6 ;
uint16_t ch7 ;
uint16_t ch8 ;
void manageAdc(void){
800015c: b480 push {r7}
800015e: af00 add r7, sp, #0
if (adc_avg_ready)
8000160: 4b12 ldr r3, [pc, #72] @ (80001ac <manageAdc+0x50>)
8000162: 781b ldrb r3, [r3, #0]
8000164: b2db uxtb r3, r3
8000166: 2b00 cmp r3, #0
8000168: d01b beq.n 80001a2 <manageAdc+0x46>
{
adc_avg_ready = 0;
800016a: 4b10 ldr r3, [pc, #64] @ (80001ac <manageAdc+0x50>)
800016c: 2200 movs r2, #0
800016e: 701a strb r2, [r3, #0]
// Read averaged channels (example mapping)
ch4 = adc_avg[0];
8000170: 4b0f ldr r3, [pc, #60] @ (80001b0 <manageAdc+0x54>)
8000172: 881b ldrh r3, [r3, #0]
8000174: b29a uxth r2, r3
8000176: 4b0f ldr r3, [pc, #60] @ (80001b4 <manageAdc+0x58>)
8000178: 801a strh r2, [r3, #0]
ch5 = adc_avg[1];
800017a: 4b0d ldr r3, [pc, #52] @ (80001b0 <manageAdc+0x54>)
800017c: 885b ldrh r3, [r3, #2]
800017e: b29a uxth r2, r3
8000180: 4b0d ldr r3, [pc, #52] @ (80001b8 <manageAdc+0x5c>)
8000182: 801a strh r2, [r3, #0]
ch6 = adc_avg[2];
8000184: 4b0a ldr r3, [pc, #40] @ (80001b0 <manageAdc+0x54>)
8000186: 889b ldrh r3, [r3, #4]
8000188: b29a uxth r2, r3
800018a: 4b0c ldr r3, [pc, #48] @ (80001bc <manageAdc+0x60>)
800018c: 801a strh r2, [r3, #0]
ch7 = adc_avg[3];
800018e: 4b08 ldr r3, [pc, #32] @ (80001b0 <manageAdc+0x54>)
8000190: 88db ldrh r3, [r3, #6]
8000192: b29a uxth r2, r3
8000194: 4b0a ldr r3, [pc, #40] @ (80001c0 <manageAdc+0x64>)
8000196: 801a strh r2, [r3, #0]
ch8 = adc_avg[4];
8000198: 4b05 ldr r3, [pc, #20] @ (80001b0 <manageAdc+0x54>)
800019a: 891b ldrh r3, [r3, #8]
800019c: b29a uxth r2, r3
800019e: 4b09 ldr r3, [pc, #36] @ (80001c4 <manageAdc+0x68>)
80001a0: 801a strh r2, [r3, #0]
// Use them (convert to volts, control, etc.)
// float v4 = (3.3f * ch4) / 4095.0f;
}
}
80001a2: bf00 nop
80001a4: 46bd mov sp, r7
80001a6: bc80 pop {r7}
80001a8: 4770 bx lr
80001aa: bf00 nop
80001ac: 20000219 .word 0x20000219
80001b0: 200001f8 .word 0x200001f8
80001b4: 2000021a .word 0x2000021a
80001b8: 2000021c .word 0x2000021c
80001bc: 2000021e .word 0x2000021e
80001c0: 20000220 .word 0x20000220
80001c4: 20000222 .word 0x20000222
080001c8 <readAdc>:
void readAdc(void){
80001c8: b480 push {r7}
80001ca: b083 sub sp, #12
80001cc: af00 add r7, sp, #0
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
80001ce: 2300 movs r3, #0
80001d0: 71fb strb r3, [r7, #7]
80001d2: e010 b.n 80001f6 <readAdc+0x2e>
{
adc_sum[i] += adc_dma_buf[i];
80001d4: 79fb ldrb r3, [r7, #7]
80001d6: 4a21 ldr r2, [pc, #132] @ (800025c <readAdc+0x94>)
80001d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80001dc: b299 uxth r1, r3
80001de: 79fb ldrb r3, [r7, #7]
80001e0: 4a1f ldr r2, [pc, #124] @ (8000260 <readAdc+0x98>)
80001e2: f852 2023 ldr.w r2, [r2, r3, lsl #2]
80001e6: 79fb ldrb r3, [r7, #7]
80001e8: 440a add r2, r1
80001ea: 491d ldr r1, [pc, #116] @ (8000260 <readAdc+0x98>)
80001ec: f841 2023 str.w r2, [r1, r3, lsl #2]
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
80001f0: 79fb ldrb r3, [r7, #7]
80001f2: 3301 adds r3, #1
80001f4: 71fb strb r3, [r7, #7]
80001f6: 79fb ldrb r3, [r7, #7]
80001f8: 2b04 cmp r3, #4
80001fa: d9eb bls.n 80001d4 <readAdc+0xc>
}
adc_sum_count++;
80001fc: 4b19 ldr r3, [pc, #100] @ (8000264 <readAdc+0x9c>)
80001fe: 781b ldrb r3, [r3, #0]
8000200: 3301 adds r3, #1
8000202: b2da uxtb r2, r3
8000204: 4b17 ldr r3, [pc, #92] @ (8000264 <readAdc+0x9c>)
8000206: 701a strb r2, [r3, #0]
/* When we collected ADC_AVG_WINDOW samples → compute average */
if (adc_sum_count >= ADC_AVG_WINDOW)
8000208: 4b16 ldr r3, [pc, #88] @ (8000264 <readAdc+0x9c>)
800020a: 781b ldrb r3, [r3, #0]
800020c: 2b04 cmp r3, #4
800020e: d920 bls.n 8000252 <readAdc+0x8a>
{
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
8000210: 2300 movs r3, #0
8000212: 71bb strb r3, [r7, #6]
8000214: e014 b.n 8000240 <readAdc+0x78>
{
adc_avg[i] = (uint16_t)(adc_sum[i] / ADC_AVG_WINDOW);
8000216: 79bb ldrb r3, [r7, #6]
8000218: 4a11 ldr r2, [pc, #68] @ (8000260 <readAdc+0x98>)
800021a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800021e: 4a12 ldr r2, [pc, #72] @ (8000268 <readAdc+0xa0>)
8000220: fba2 2303 umull r2, r3, r2, r3
8000224: 089a lsrs r2, r3, #2
8000226: 79bb ldrb r3, [r7, #6]
8000228: b291 uxth r1, r2
800022a: 4a10 ldr r2, [pc, #64] @ (800026c <readAdc+0xa4>)
800022c: f822 1013 strh.w r1, [r2, r3, lsl #1]
adc_sum[i] = 0;
8000230: 79bb ldrb r3, [r7, #6]
8000232: 4a0b ldr r2, [pc, #44] @ (8000260 <readAdc+0x98>)
8000234: 2100 movs r1, #0
8000236: f842 1023 str.w r1, [r2, r3, lsl #2]
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
800023a: 79bb ldrb r3, [r7, #6]
800023c: 3301 adds r3, #1
800023e: 71bb strb r3, [r7, #6]
8000240: 79bb ldrb r3, [r7, #6]
8000242: 2b04 cmp r3, #4
8000244: d9e7 bls.n 8000216 <readAdc+0x4e>
}
adc_sum_count = 0;
8000246: 4b07 ldr r3, [pc, #28] @ (8000264 <readAdc+0x9c>)
8000248: 2200 movs r2, #0
800024a: 701a strb r2, [r3, #0]
adc_avg_ready = 1; // tell main loop new data is ready
800024c: 4b08 ldr r3, [pc, #32] @ (8000270 <readAdc+0xa8>)
800024e: 2201 movs r2, #1
8000250: 701a strb r2, [r3, #0]
}
}
8000252: bf00 nop
8000254: 370c adds r7, #12
8000256: 46bd mov sp, r7
8000258: bc80 pop {r7}
800025a: 4770 bx lr
800025c: 200001ec .word 0x200001ec
8000260: 20000204 .word 0x20000204
8000264: 20000218 .word 0x20000218
8000268: cccccccd .word 0xcccccccd
800026c: 200001f8 .word 0x200001f8
8000270: 20000219 .word 0x20000219
08000274 <EEW_Read>:
uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data);
uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data);
/* Pseudo-array accessor EEW[idx] */
static inline uint16_t EEW_Read(uint8_t idx, uint16_t *value)
{
8000274: b580 push {r7, lr}
8000276: b082 sub sp, #8
8000278: af00 add r7, sp, #0
800027a: 4603 mov r3, r0
800027c: 6039 str r1, [r7, #0]
800027e: 71fb strb r3, [r7, #7]
return EE_ReadVariable(EEW_ADDR(idx), value);
8000280: 79fb ldrb r3, [r7, #7]
8000282: b29b uxth r3, r3
8000284: 3301 adds r3, #1
8000286: b29b uxth r3, r3
8000288: 6839 ldr r1, [r7, #0]
800028a: 4618 mov r0, r3
800028c: f000 fec6 bl 800101c <EE_ReadVariable>
8000290: 4603 mov r3, r0
}
8000292: 4618 mov r0, r3
8000294: 3708 adds r7, #8
8000296: 46bd mov sp, r7
8000298: bd80 pop {r7, pc}
0800029a <EEW_Write>:
static inline uint16_t EEW_Write(uint8_t idx, uint16_t value)
{
800029a: b580 push {r7, lr}
800029c: b082 sub sp, #8
800029e: af00 add r7, sp, #0
80002a0: 4603 mov r3, r0
80002a2: 460a mov r2, r1
80002a4: 71fb strb r3, [r7, #7]
80002a6: 4613 mov r3, r2
80002a8: 80bb strh r3, [r7, #4]
return EE_WriteVariable(EEW_ADDR(idx), value);
80002aa: 79fb ldrb r3, [r7, #7]
80002ac: b29b uxth r3, r3
80002ae: 3301 adds r3, #1
80002b0: b29b uxth r3, r3
80002b2: 88ba ldrh r2, [r7, #4]
80002b4: 4611 mov r1, r2
80002b6: 4618 mov r0, r3
80002b8: f000 fecc bl 8001054 <EE_WriteVariable>
80002bc: 4603 mov r3, r0
}
80002be: 4618 mov r0, r3
80002c0: 3708 adds r7, #8
80002c2: 46bd mov sp, r7
80002c4: bd80 pop {r7, pc}
080002c6 <toHex>:
extern uint16_t ch5 ;
extern uint16_t ch6 ;
extern uint16_t ch7 ;
extern uint16_t ch8 ;
bool toHex(char c1,char c2,char c3,char c4,uint16_t* retval){
80002c6: b490 push {r4, r7}
80002c8: b082 sub sp, #8
80002ca: af00 add r7, sp, #0
80002cc: 4604 mov r4, r0
80002ce: 4608 mov r0, r1
80002d0: 4611 mov r1, r2
80002d2: 461a mov r2, r3
80002d4: 4623 mov r3, r4
80002d6: 71fb strb r3, [r7, #7]
80002d8: 4603 mov r3, r0
80002da: 71bb strb r3, [r7, #6]
80002dc: 460b mov r3, r1
80002de: 717b strb r3, [r7, #5]
80002e0: 4613 mov r3, r2
80002e2: 713b strb r3, [r7, #4]
if((c1>='0')&&(c1<='9')){
80002e4: 79fb ldrb r3, [r7, #7]
80002e6: 2b2f cmp r3, #47 @ 0x2f
80002e8: d906 bls.n 80002f8 <toHex+0x32>
80002ea: 79fb ldrb r3, [r7, #7]
80002ec: 2b39 cmp r3, #57 @ 0x39
80002ee: d803 bhi.n 80002f8 <toHex+0x32>
c1-='0';
80002f0: 79fb ldrb r3, [r7, #7]
80002f2: 3b30 subs r3, #48 @ 0x30
80002f4: 71fb strb r3, [r7, #7]
80002f6: e00b b.n 8000310 <toHex+0x4a>
}else if((c1>='a')&&(c1<='f')){
80002f8: 79fb ldrb r3, [r7, #7]
80002fa: 2b60 cmp r3, #96 @ 0x60
80002fc: d906 bls.n 800030c <toHex+0x46>
80002fe: 79fb ldrb r3, [r7, #7]
8000300: 2b66 cmp r3, #102 @ 0x66
8000302: d803 bhi.n 800030c <toHex+0x46>
c1=(c1-'a')+10;
8000304: 79fb ldrb r3, [r7, #7]
8000306: 3b57 subs r3, #87 @ 0x57
8000308: 71fb strb r3, [r7, #7]
800030a: e001 b.n 8000310 <toHex+0x4a>
}else return false;
800030c: 2300 movs r3, #0
800030e: e070 b.n 80003f2 <toHex+0x12c>
if((c2>='0')&&(c2<='9')){
8000310: 79bb ldrb r3, [r7, #6]
8000312: 2b2f cmp r3, #47 @ 0x2f
8000314: d906 bls.n 8000324 <toHex+0x5e>
8000316: 79bb ldrb r3, [r7, #6]
8000318: 2b39 cmp r3, #57 @ 0x39
800031a: d803 bhi.n 8000324 <toHex+0x5e>
c2-='0';
800031c: 79bb ldrb r3, [r7, #6]
800031e: 3b30 subs r3, #48 @ 0x30
8000320: 71bb strb r3, [r7, #6]
8000322: e00b b.n 800033c <toHex+0x76>
}else if((c2>='a')&&(c2<='f')){
8000324: 79bb ldrb r3, [r7, #6]
8000326: 2b60 cmp r3, #96 @ 0x60
8000328: d906 bls.n 8000338 <toHex+0x72>
800032a: 79bb ldrb r3, [r7, #6]
800032c: 2b66 cmp r3, #102 @ 0x66
800032e: d803 bhi.n 8000338 <toHex+0x72>
c2=(c2-'a')+10;
8000330: 79bb ldrb r3, [r7, #6]
8000332: 3b57 subs r3, #87 @ 0x57
8000334: 71bb strb r3, [r7, #6]
8000336: e001 b.n 800033c <toHex+0x76>
}else return false;
8000338: 2300 movs r3, #0
800033a: e05a b.n 80003f2 <toHex+0x12c>
if((c3>='0')&&(c3<='9')){
800033c: 797b ldrb r3, [r7, #5]
800033e: 2b2f cmp r3, #47 @ 0x2f
8000340: d906 bls.n 8000350 <toHex+0x8a>
8000342: 797b ldrb r3, [r7, #5]
8000344: 2b39 cmp r3, #57 @ 0x39
8000346: d803 bhi.n 8000350 <toHex+0x8a>
c3-='0';
8000348: 797b ldrb r3, [r7, #5]
800034a: 3b30 subs r3, #48 @ 0x30
800034c: 717b strb r3, [r7, #5]
800034e: e00b b.n 8000368 <toHex+0xa2>
}else if((c3>='a')&&(c3<='f')){
8000350: 797b ldrb r3, [r7, #5]
8000352: 2b60 cmp r3, #96 @ 0x60
8000354: d906 bls.n 8000364 <toHex+0x9e>
8000356: 797b ldrb r3, [r7, #5]
8000358: 2b66 cmp r3, #102 @ 0x66
800035a: d803 bhi.n 8000364 <toHex+0x9e>
c3=(c3-'a')+10;
800035c: 797b ldrb r3, [r7, #5]
800035e: 3b57 subs r3, #87 @ 0x57
8000360: 717b strb r3, [r7, #5]
8000362: e001 b.n 8000368 <toHex+0xa2>
}else return false;
8000364: 2300 movs r3, #0
8000366: e044 b.n 80003f2 <toHex+0x12c>
if((c4>='0')&&(c4<='9')){
8000368: 793b ldrb r3, [r7, #4]
800036a: 2b2f cmp r3, #47 @ 0x2f
800036c: d906 bls.n 800037c <toHex+0xb6>
800036e: 793b ldrb r3, [r7, #4]
8000370: 2b39 cmp r3, #57 @ 0x39
8000372: d803 bhi.n 800037c <toHex+0xb6>
c4-='0';
8000374: 793b ldrb r3, [r7, #4]
8000376: 3b30 subs r3, #48 @ 0x30
8000378: 713b strb r3, [r7, #4]
800037a: e00b b.n 8000394 <toHex+0xce>
}else if((c4>='a')&&(c4<='f')){
800037c: 793b ldrb r3, [r7, #4]
800037e: 2b60 cmp r3, #96 @ 0x60
8000380: d906 bls.n 8000390 <toHex+0xca>
8000382: 793b ldrb r3, [r7, #4]
8000384: 2b66 cmp r3, #102 @ 0x66
8000386: d803 bhi.n 8000390 <toHex+0xca>
c4=(c4-'a')+10;
8000388: 793b ldrb r3, [r7, #4]
800038a: 3b57 subs r3, #87 @ 0x57
800038c: 713b strb r3, [r7, #4]
800038e: e001 b.n 8000394 <toHex+0xce>
}else return false;
8000390: 2300 movs r3, #0
8000392: e02e b.n 80003f2 <toHex+0x12c>
*retval=c1;
8000394: 79fb ldrb r3, [r7, #7]
8000396: b29a uxth r2, r3
8000398: 693b ldr r3, [r7, #16]
800039a: 801a strh r2, [r3, #0]
*retval*=16;
800039c: 693b ldr r3, [r7, #16]
800039e: 881b ldrh r3, [r3, #0]
80003a0: 011b lsls r3, r3, #4
80003a2: b29a uxth r2, r3
80003a4: 693b ldr r3, [r7, #16]
80003a6: 801a strh r2, [r3, #0]
*retval+=c2;
80003a8: 693b ldr r3, [r7, #16]
80003aa: 881a ldrh r2, [r3, #0]
80003ac: 79bb ldrb r3, [r7, #6]
80003ae: b29b uxth r3, r3
80003b0: 4413 add r3, r2
80003b2: b29a uxth r2, r3
80003b4: 693b ldr r3, [r7, #16]
80003b6: 801a strh r2, [r3, #0]
*retval*=16;
80003b8: 693b ldr r3, [r7, #16]
80003ba: 881b ldrh r3, [r3, #0]
80003bc: 011b lsls r3, r3, #4
80003be: b29a uxth r2, r3
80003c0: 693b ldr r3, [r7, #16]
80003c2: 801a strh r2, [r3, #0]
*retval+=c3;
80003c4: 693b ldr r3, [r7, #16]
80003c6: 881a ldrh r2, [r3, #0]
80003c8: 797b ldrb r3, [r7, #5]
80003ca: b29b uxth r3, r3
80003cc: 4413 add r3, r2
80003ce: b29a uxth r2, r3
80003d0: 693b ldr r3, [r7, #16]
80003d2: 801a strh r2, [r3, #0]
*retval*=16;
80003d4: 693b ldr r3, [r7, #16]
80003d6: 881b ldrh r3, [r3, #0]
80003d8: 011b lsls r3, r3, #4
80003da: b29a uxth r2, r3
80003dc: 693b ldr r3, [r7, #16]
80003de: 801a strh r2, [r3, #0]
*retval+=c4;
80003e0: 693b ldr r3, [r7, #16]
80003e2: 881a ldrh r2, [r3, #0]
80003e4: 793b ldrb r3, [r7, #4]
80003e6: b29b uxth r3, r3
80003e8: 4413 add r3, r2
80003ea: b29a uxth r2, r3
80003ec: 693b ldr r3, [r7, #16]
80003ee: 801a strh r2, [r3, #0]
return true;
80003f0: 2301 movs r3, #1
}
80003f2: 4618 mov r0, r3
80003f4: 3708 adds r7, #8
80003f6: 46bd mov sp, r7
80003f8: bc90 pop {r4, r7}
80003fa: 4770 bx lr
080003fc <manageCDC>:
void manageCDC(void){
80003fc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
8000400: b0a7 sub sp, #156 @ 0x9c
8000402: af06 add r7, sp, #24
uint16_t val;
uint16_t st;
uint16_t eeadd;
uint8_t i;
if (CDC_Available()) {
8000404: f00a fa68 bl 800a8d8 <CDC_Available>
8000408: 4603 mov r3, r0
800040a: 2b00 cmp r3, #0
800040c: f000 8432 beq.w 8000c74 <manageCDC+0x878>
int rx = CDC_ReadByte();
8000410: f00a fa76 bl 800a900 <CDC_ReadByte>
8000414: 67b8 str r0, [r7, #120] @ 0x78
if (rx < 0) return;
8000416: 6fbb ldr r3, [r7, #120] @ 0x78
8000418: 2b00 cmp r3, #0
800041a: f2c0 842a blt.w 8000c72 <manageCDC+0x876>
//uint8_t out = (uint8_t)c;
//if (out >= 'a' && out <= 'z') out -= 32; // to upper
rxbuf[rxidx]=rx;
800041e: 4ba2 ldr r3, [pc, #648] @ (80006a8 <manageCDC+0x2ac>)
8000420: 781b ldrb r3, [r3, #0]
8000422: 461a mov r2, r3
8000424: 6fbb ldr r3, [r7, #120] @ 0x78
8000426: b2d9 uxtb r1, r3
8000428: 4ba0 ldr r3, [pc, #640] @ (80006ac <manageCDC+0x2b0>)
800042a: 5499 strb r1, [r3, r2]
while (CDC_Transmit_FS(&rxbuf[rxidx], 1) == USBD_BUSY);//echo
800042c: bf00 nop
800042e: 4b9e ldr r3, [pc, #632] @ (80006a8 <manageCDC+0x2ac>)
8000430: 781b ldrb r3, [r3, #0]
8000432: 461a mov r2, r3
8000434: 4b9d ldr r3, [pc, #628] @ (80006ac <manageCDC+0x2b0>)
8000436: 4413 add r3, r2
8000438: 2101 movs r1, #1
800043a: 4618 mov r0, r3
800043c: f00a fb22 bl 800aa84 <CDC_Transmit_FS>
8000440: 4603 mov r3, r0
8000442: 2b01 cmp r3, #1
8000444: d0f3 beq.n 800042e <manageCDC+0x32>
if((rx==0x0d)||(rx==0x0a)){
8000446: 6fbb ldr r3, [r7, #120] @ 0x78
8000448: 2b0d cmp r3, #13
800044a: d003 beq.n 8000454 <manageCDC+0x58>
800044c: 6fbb ldr r3, [r7, #120] @ 0x78
800044e: 2b0a cmp r3, #10
8000450: f040 8408 bne.w 8000c64 <manageCDC+0x868>
if(rxidx){
8000454: 4b94 ldr r3, [pc, #592] @ (80006a8 <manageCDC+0x2ac>)
8000456: 781b ldrb r3, [r3, #0]
8000458: 2b00 cmp r3, #0
800045a: f000 83ff beq.w 8000c5c <manageCDC+0x860>
switch(rxbuf[0]){
800045e: 4b93 ldr r3, [pc, #588] @ (80006ac <manageCDC+0x2b0>)
8000460: 781b ldrb r3, [r3, #0]
8000462: 2b6d cmp r3, #109 @ 0x6d
8000464: f000 80e6 beq.w 8000634 <manageCDC+0x238>
8000468: 2b6d cmp r3, #109 @ 0x6d
800046a: f300 83e6 bgt.w 8000c3a <manageCDC+0x83e>
800046e: 2b69 cmp r3, #105 @ 0x69
8000470: d009 beq.n 8000486 <manageCDC+0x8a>
8000472: 2b69 cmp r3, #105 @ 0x69
8000474: f300 83e1 bgt.w 8000c3a <manageCDC+0x83e>
8000478: 2b49 cmp r3, #73 @ 0x49
800047a: f000 80ca beq.w 8000612 <manageCDC+0x216>
800047e: 2b65 cmp r3, #101 @ 0x65
8000480: f000 820c beq.w 800089c <manageCDC+0x4a0>
8000484: e3d9 b.n 8000c3a <manageCDC+0x83e>
case 'i':
sprintf((char*)s,"\ninfo");
8000486: f107 030c add.w r3, r7, #12
800048a: 4989 ldr r1, [pc, #548] @ (80006b0 <manageCDC+0x2b4>)
800048c: 4618 mov r0, r3
800048e: f00a fed7 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 5) == USBD_BUSY);
8000492: bf00 nop
8000494: f107 030c add.w r3, r7, #12
8000498: 2105 movs r1, #5
800049a: 4618 mov r0, r3
800049c: f00a faf2 bl 800aa84 <CDC_Transmit_FS>
80004a0: 4603 mov r3, r0
80004a2: 2b01 cmp r3, #1
80004a4: d0f6 beq.n 8000494 <manageCDC+0x98>
sprintf((char*)s,"\npwm %d%d%d%d%d%d%d%d",IsPwmRunning(timMot1,FWMot1),IsPwmRunning(timMot1,BWMot1),IsPwmRunning(timMot2,FWMot2),IsPwmRunning(timMot2,BWMot2),IsPwmRunning(timMot3,FWMot3),IsPwmRunning(timMot3,BWMot3),IsPwmRunning(timMot4,FWMot4),IsPwmRunning(timMot4,BWMot4));
80004a6: 2100 movs r1, #0
80004a8: 4882 ldr r0, [pc, #520] @ (80006b4 <manageCDC+0x2b8>)
80004aa: f001 fa31 bl 8001910 <IsPwmRunning>
80004ae: 4603 mov r3, r0
80004b0: 4698 mov r8, r3
80004b2: 2104 movs r1, #4
80004b4: 487f ldr r0, [pc, #508] @ (80006b4 <manageCDC+0x2b8>)
80004b6: f001 fa2b bl 8001910 <IsPwmRunning>
80004ba: 4603 mov r3, r0
80004bc: 4699 mov r9, r3
80004be: 2108 movs r1, #8
80004c0: 487c ldr r0, [pc, #496] @ (80006b4 <manageCDC+0x2b8>)
80004c2: f001 fa25 bl 8001910 <IsPwmRunning>
80004c6: 4603 mov r3, r0
80004c8: 461c mov r4, r3
80004ca: 210c movs r1, #12
80004cc: 4879 ldr r0, [pc, #484] @ (80006b4 <manageCDC+0x2b8>)
80004ce: f001 fa1f bl 8001910 <IsPwmRunning>
80004d2: 4603 mov r3, r0
80004d4: 461d mov r5, r3
80004d6: 2100 movs r1, #0
80004d8: 4877 ldr r0, [pc, #476] @ (80006b8 <manageCDC+0x2bc>)
80004da: f001 fa19 bl 8001910 <IsPwmRunning>
80004de: 4603 mov r3, r0
80004e0: 461e mov r6, r3
80004e2: 2104 movs r1, #4
80004e4: 4874 ldr r0, [pc, #464] @ (80006b8 <manageCDC+0x2bc>)
80004e6: f001 fa13 bl 8001910 <IsPwmRunning>
80004ea: 4603 mov r3, r0
80004ec: 607b str r3, [r7, #4]
80004ee: 2108 movs r1, #8
80004f0: 4871 ldr r0, [pc, #452] @ (80006b8 <manageCDC+0x2bc>)
80004f2: f001 fa0d bl 8001910 <IsPwmRunning>
80004f6: 4603 mov r3, r0
80004f8: 603b str r3, [r7, #0]
80004fa: 210c movs r1, #12
80004fc: 486e ldr r0, [pc, #440] @ (80006b8 <manageCDC+0x2bc>)
80004fe: f001 fa07 bl 8001910 <IsPwmRunning>
8000502: 4603 mov r3, r0
8000504: f107 000c add.w r0, r7, #12
8000508: 9305 str r3, [sp, #20]
800050a: 683a ldr r2, [r7, #0]
800050c: 9204 str r2, [sp, #16]
800050e: 687b ldr r3, [r7, #4]
8000510: 9303 str r3, [sp, #12]
8000512: 9602 str r6, [sp, #8]
8000514: 9501 str r5, [sp, #4]
8000516: 9400 str r4, [sp, #0]
8000518: 464b mov r3, r9
800051a: 4642 mov r2, r8
800051c: 4967 ldr r1, [pc, #412] @ (80006bc <manageCDC+0x2c0>)
800051e: f00a fe8f bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000522: bf00 nop
8000524: f107 030c add.w r3, r7, #12
8000528: 4618 mov r0, r3
800052a: f7ff fe0f bl 800014c <strlen>
800052e: 4603 mov r3, r0
8000530: b29a uxth r2, r3
8000532: f107 030c add.w r3, r7, #12
8000536: 4611 mov r1, r2
8000538: 4618 mov r0, r3
800053a: f00a faa3 bl 800aa84 <CDC_Transmit_FS>
800053e: 4603 mov r3, r0
8000540: 2b01 cmp r3, #1
8000542: d0ef beq.n 8000524 <manageCDC+0x128>
sprintf((char*)s,"\n0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx",(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,FWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,BWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,FWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,BWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,FWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,BWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,FWMot4),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,BWMot4));
8000544: 4b5b ldr r3, [pc, #364] @ (80006b4 <manageCDC+0x2b8>)
8000546: 681b ldr r3, [r3, #0]
8000548: 6b5b ldr r3, [r3, #52] @ 0x34
800054a: 607b str r3, [r7, #4]
800054c: 4b59 ldr r3, [pc, #356] @ (80006b4 <manageCDC+0x2b8>)
800054e: 681b ldr r3, [r3, #0]
8000550: 6b99 ldr r1, [r3, #56] @ 0x38
8000552: 6039 str r1, [r7, #0]
8000554: 4b57 ldr r3, [pc, #348] @ (80006b4 <manageCDC+0x2b8>)
8000556: 681b ldr r3, [r3, #0]
8000558: 6bdb ldr r3, [r3, #60] @ 0x3c
800055a: 4a56 ldr r2, [pc, #344] @ (80006b4 <manageCDC+0x2b8>)
800055c: 6812 ldr r2, [r2, #0]
800055e: 6c12 ldr r2, [r2, #64] @ 0x40
8000560: 4955 ldr r1, [pc, #340] @ (80006b8 <manageCDC+0x2bc>)
8000562: 6809 ldr r1, [r1, #0]
8000564: 6b49 ldr r1, [r1, #52] @ 0x34
8000566: 4854 ldr r0, [pc, #336] @ (80006b8 <manageCDC+0x2bc>)
8000568: 6800 ldr r0, [r0, #0]
800056a: 6b80 ldr r0, [r0, #56] @ 0x38
800056c: 4c52 ldr r4, [pc, #328] @ (80006b8 <manageCDC+0x2bc>)
800056e: 6824 ldr r4, [r4, #0]
8000570: 6be4 ldr r4, [r4, #60] @ 0x3c
8000572: 4d51 ldr r5, [pc, #324] @ (80006b8 <manageCDC+0x2bc>)
8000574: 682d ldr r5, [r5, #0]
8000576: 6c2d ldr r5, [r5, #64] @ 0x40
8000578: f107 060c add.w r6, r7, #12
800057c: 9505 str r5, [sp, #20]
800057e: 9404 str r4, [sp, #16]
8000580: 9003 str r0, [sp, #12]
8000582: 9102 str r1, [sp, #8]
8000584: 9201 str r2, [sp, #4]
8000586: 9300 str r3, [sp, #0]
8000588: 683b ldr r3, [r7, #0]
800058a: 687a ldr r2, [r7, #4]
800058c: 494c ldr r1, [pc, #304] @ (80006c0 <manageCDC+0x2c4>)
800058e: 4630 mov r0, r6
8000590: f00a fe56 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000594: bf00 nop
8000596: f107 030c add.w r3, r7, #12
800059a: 4618 mov r0, r3
800059c: f7ff fdd6 bl 800014c <strlen>
80005a0: 4603 mov r3, r0
80005a2: b29a uxth r2, r3
80005a4: f107 030c add.w r3, r7, #12
80005a8: 4611 mov r1, r2
80005aa: 4618 mov r0, r3
80005ac: f00a fa6a bl 800aa84 <CDC_Transmit_FS>
80005b0: 4603 mov r3, r0
80005b2: 2b01 cmp r3, #1
80005b4: d0ef beq.n 8000596 <manageCDC+0x19a>
sprintf((char*)s,"\nP=0x%x ch4=%05d ch5=%05d ch6=%05d ch7=%05d ch8=%05d",pulsanti,ch4,ch5,ch6,ch7,ch8);
80005b6: 4b43 ldr r3, [pc, #268] @ (80006c4 <manageCDC+0x2c8>)
80005b8: 781b ldrb r3, [r3, #0]
80005ba: 461d mov r5, r3
80005bc: 4b42 ldr r3, [pc, #264] @ (80006c8 <manageCDC+0x2cc>)
80005be: 881b ldrh r3, [r3, #0]
80005c0: 461e mov r6, r3
80005c2: 4b42 ldr r3, [pc, #264] @ (80006cc <manageCDC+0x2d0>)
80005c4: 881b ldrh r3, [r3, #0]
80005c6: 461a mov r2, r3
80005c8: 4b41 ldr r3, [pc, #260] @ (80006d0 <manageCDC+0x2d4>)
80005ca: 881b ldrh r3, [r3, #0]
80005cc: 4619 mov r1, r3
80005ce: 4b41 ldr r3, [pc, #260] @ (80006d4 <manageCDC+0x2d8>)
80005d0: 881b ldrh r3, [r3, #0]
80005d2: 461c mov r4, r3
80005d4: 4b40 ldr r3, [pc, #256] @ (80006d8 <manageCDC+0x2dc>)
80005d6: 881b ldrh r3, [r3, #0]
80005d8: f107 000c add.w r0, r7, #12
80005dc: 9303 str r3, [sp, #12]
80005de: 9402 str r4, [sp, #8]
80005e0: 9101 str r1, [sp, #4]
80005e2: 9200 str r2, [sp, #0]
80005e4: 4633 mov r3, r6
80005e6: 462a mov r2, r5
80005e8: 493c ldr r1, [pc, #240] @ (80006dc <manageCDC+0x2e0>)
80005ea: f00a fe29 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
80005ee: bf00 nop
80005f0: f107 030c add.w r3, r7, #12
80005f4: 4618 mov r0, r3
80005f6: f7ff fda9 bl 800014c <strlen>
80005fa: 4603 mov r3, r0
80005fc: b29a uxth r2, r3
80005fe: f107 030c add.w r3, r7, #12
8000602: 4611 mov r1, r2
8000604: 4618 mov r0, r3
8000606: f00a fa3d bl 800aa84 <CDC_Transmit_FS>
800060a: 4603 mov r3, r0
800060c: 2b01 cmp r3, #1
800060e: d0ef beq.n 80005f0 <manageCDC+0x1f4>
break;
8000610: e324 b.n 8000c5c <manageCDC+0x860>
case 'I':
sprintf((char*)s,"\nID000000");
8000612: f107 030c add.w r3, r7, #12
8000616: 4932 ldr r1, [pc, #200] @ (80006e0 <manageCDC+0x2e4>)
8000618: 4618 mov r0, r3
800061a: f00a fe11 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 9) == USBD_BUSY);
800061e: bf00 nop
8000620: f107 030c add.w r3, r7, #12
8000624: 2109 movs r1, #9
8000626: 4618 mov r0, r3
8000628: f00a fa2c bl 800aa84 <CDC_Transmit_FS>
800062c: 4603 mov r3, r0
800062e: 2b01 cmp r3, #1
8000630: d0f6 beq.n 8000620 <manageCDC+0x224>
break;
8000632: e313 b.n 8000c5c <manageCDC+0x860>
case 'm':
if(rxidx==8){
8000634: 4b1c ldr r3, [pc, #112] @ (80006a8 <manageCDC+0x2ac>)
8000636: 781b ldrb r3, [r3, #0]
8000638: 2b08 cmp r3, #8
800063a: f040 811d bne.w 8000878 <manageCDC+0x47c>
if((rxbuf[1]>='1')&&(rxbuf[1]<='4')){
800063e: 4b1b ldr r3, [pc, #108] @ (80006ac <manageCDC+0x2b0>)
8000640: 785b ldrb r3, [r3, #1]
8000642: 2b30 cmp r3, #48 @ 0x30
8000644: f240 8107 bls.w 8000856 <manageCDC+0x45a>
8000648: 4b18 ldr r3, [pc, #96] @ (80006ac <manageCDC+0x2b0>)
800064a: 785b ldrb r3, [r3, #1]
800064c: 2b34 cmp r3, #52 @ 0x34
800064e: f200 8102 bhi.w 8000856 <manageCDC+0x45a>
mot=rxbuf[1]-='0';
8000652: 4b16 ldr r3, [pc, #88] @ (80006ac <manageCDC+0x2b0>)
8000654: 785b ldrb r3, [r3, #1]
8000656: 3b30 subs r3, #48 @ 0x30
8000658: b2da uxtb r2, r3
800065a: 4b14 ldr r3, [pc, #80] @ (80006ac <manageCDC+0x2b0>)
800065c: 705a strb r2, [r3, #1]
800065e: 4b13 ldr r3, [pc, #76] @ (80006ac <manageCDC+0x2b0>)
8000660: 785b ldrb r3, [r3, #1]
8000662: f887 3077 strb.w r3, [r7, #119] @ 0x77
if(rxbuf[2]=='f'){
8000666: 4b11 ldr r3, [pc, #68] @ (80006ac <manageCDC+0x2b0>)
8000668: 789b ldrb r3, [r3, #2]
800066a: 2b66 cmp r3, #102 @ 0x66
800066c: d103 bne.n 8000676 <manageCDC+0x27a>
dir=FW;
800066e: 2300 movs r3, #0
8000670: f887 307f strb.w r3, [r7, #127] @ 0x7f
8000674: e038 b.n 80006e8 <manageCDC+0x2ec>
}else if(rxbuf[2]=='b'){
8000676: 4b0d ldr r3, [pc, #52] @ (80006ac <manageCDC+0x2b0>)
8000678: 789b ldrb r3, [r3, #2]
800067a: 2b62 cmp r3, #98 @ 0x62
800067c: d103 bne.n 8000686 <manageCDC+0x28a>
dir=BW;
800067e: 2301 movs r3, #1
8000680: f887 307f strb.w r3, [r7, #127] @ 0x7f
8000684: e030 b.n 80006e8 <manageCDC+0x2ec>
}else{
sprintf((char*)s,"\n?mnsvvvvv s=f|b");//m nmotore senso valore
8000686: f107 030c add.w r3, r7, #12
800068a: 4916 ldr r1, [pc, #88] @ (80006e4 <manageCDC+0x2e8>)
800068c: 4618 mov r0, r3
800068e: f00a fdd7 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 16) == USBD_BUSY);
8000692: bf00 nop
8000694: f107 030c add.w r3, r7, #12
8000698: 2110 movs r1, #16
800069a: 4618 mov r0, r3
800069c: f00a f9f2 bl 800aa84 <CDC_Transmit_FS>
80006a0: 4603 mov r3, r0
80006a2: 2b01 cmp r3, #1
80006a4: d0f6 beq.n 8000694 <manageCDC+0x298>
break;
80006a6: e2d9 b.n 8000c5c <manageCDC+0x860>
80006a8: 20000224 .word 0x20000224
80006ac: 20000228 .word 0x20000228
80006b0: 0800bbb8 .word 0x0800bbb8
80006b4: 20000300 .word 0x20000300
80006b8: 20000348 .word 0x20000348
80006bc: 0800bbc0 .word 0x0800bbc0
80006c0: 0800bbd8 .word 0x0800bbd8
80006c4: 200003d8 .word 0x200003d8
80006c8: 2000021a .word 0x2000021a
80006cc: 2000021c .word 0x2000021c
80006d0: 2000021e .word 0x2000021e
80006d4: 20000220 .word 0x20000220
80006d8: 20000222 .word 0x20000222
80006dc: 0800bc0c .word 0x0800bc0c
80006e0: 0800bc44 .word 0x0800bc44
80006e4: 0800bc50 .word 0x0800bc50
}
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
80006e8: 4bb4 ldr r3, [pc, #720] @ (80009bc <manageCDC+0x5c0>)
80006ea: 78db ldrb r3, [r3, #3]
80006ec: 2b2f cmp r3, #47 @ 0x2f
80006ee: f240 80a1 bls.w 8000834 <manageCDC+0x438>
80006f2: 4bb2 ldr r3, [pc, #712] @ (80009bc <manageCDC+0x5c0>)
80006f4: 78db ldrb r3, [r3, #3]
80006f6: 2b39 cmp r3, #57 @ 0x39
80006f8: f200 809c bhi.w 8000834 <manageCDC+0x438>
80006fc: 4baf ldr r3, [pc, #700] @ (80009bc <manageCDC+0x5c0>)
80006fe: 791b ldrb r3, [r3, #4]
8000700: 2b2f cmp r3, #47 @ 0x2f
8000702: f240 8097 bls.w 8000834 <manageCDC+0x438>
8000706: 4bad ldr r3, [pc, #692] @ (80009bc <manageCDC+0x5c0>)
8000708: 791b ldrb r3, [r3, #4]
800070a: 2b39 cmp r3, #57 @ 0x39
800070c: f200 8092 bhi.w 8000834 <manageCDC+0x438>
8000710: 4baa ldr r3, [pc, #680] @ (80009bc <manageCDC+0x5c0>)
8000712: 795b ldrb r3, [r3, #5]
8000714: 2b2f cmp r3, #47 @ 0x2f
8000716: f240 808d bls.w 8000834 <manageCDC+0x438>
800071a: 4ba8 ldr r3, [pc, #672] @ (80009bc <manageCDC+0x5c0>)
800071c: 795b ldrb r3, [r3, #5]
800071e: 2b39 cmp r3, #57 @ 0x39
8000720: f200 8088 bhi.w 8000834 <manageCDC+0x438>
8000724: 4ba5 ldr r3, [pc, #660] @ (80009bc <manageCDC+0x5c0>)
8000726: 799b ldrb r3, [r3, #6]
8000728: 2b2f cmp r3, #47 @ 0x2f
800072a: f240 8083 bls.w 8000834 <manageCDC+0x438>
800072e: 4ba3 ldr r3, [pc, #652] @ (80009bc <manageCDC+0x5c0>)
8000730: 799b ldrb r3, [r3, #6]
8000732: 2b39 cmp r3, #57 @ 0x39
8000734: d87e bhi.n 8000834 <manageCDC+0x438>
8000736: 4ba1 ldr r3, [pc, #644] @ (80009bc <manageCDC+0x5c0>)
8000738: 79db ldrb r3, [r3, #7]
800073a: 2b2f cmp r3, #47 @ 0x2f
800073c: d97a bls.n 8000834 <manageCDC+0x438>
800073e: 4b9f ldr r3, [pc, #636] @ (80009bc <manageCDC+0x5c0>)
8000740: 79db ldrb r3, [r3, #7]
8000742: 2b39 cmp r3, #57 @ 0x39
8000744: d876 bhi.n 8000834 <manageCDC+0x438>
dm=rxbuf[3]-='0';
8000746: 4b9d ldr r3, [pc, #628] @ (80009bc <manageCDC+0x5c0>)
8000748: 78db ldrb r3, [r3, #3]
800074a: 3b30 subs r3, #48 @ 0x30
800074c: b2da uxtb r2, r3
800074e: 4b9b ldr r3, [pc, #620] @ (80009bc <manageCDC+0x5c0>)
8000750: 70da strb r2, [r3, #3]
8000752: 4b9a ldr r3, [pc, #616] @ (80009bc <manageCDC+0x5c0>)
8000754: 78db ldrb r3, [r3, #3]
8000756: f887 3076 strb.w r3, [r7, #118] @ 0x76
m=rxbuf[4]-='0';
800075a: 4b98 ldr r3, [pc, #608] @ (80009bc <manageCDC+0x5c0>)
800075c: 791b ldrb r3, [r3, #4]
800075e: 3b30 subs r3, #48 @ 0x30
8000760: b2da uxtb r2, r3
8000762: 4b96 ldr r3, [pc, #600] @ (80009bc <manageCDC+0x5c0>)
8000764: 711a strb r2, [r3, #4]
8000766: 4b95 ldr r3, [pc, #596] @ (80009bc <manageCDC+0x5c0>)
8000768: 791b ldrb r3, [r3, #4]
800076a: f887 3075 strb.w r3, [r7, #117] @ 0x75
c=rxbuf[5]-='0';
800076e: 4b93 ldr r3, [pc, #588] @ (80009bc <manageCDC+0x5c0>)
8000770: 795b ldrb r3, [r3, #5]
8000772: 3b30 subs r3, #48 @ 0x30
8000774: b2da uxtb r2, r3
8000776: 4b91 ldr r3, [pc, #580] @ (80009bc <manageCDC+0x5c0>)
8000778: 715a strb r2, [r3, #5]
800077a: 4b90 ldr r3, [pc, #576] @ (80009bc <manageCDC+0x5c0>)
800077c: 795b ldrb r3, [r3, #5]
800077e: f887 3074 strb.w r3, [r7, #116] @ 0x74
d=rxbuf[6]-='0';
8000782: 4b8e ldr r3, [pc, #568] @ (80009bc <manageCDC+0x5c0>)
8000784: 799b ldrb r3, [r3, #6]
8000786: 3b30 subs r3, #48 @ 0x30
8000788: b2da uxtb r2, r3
800078a: 4b8c ldr r3, [pc, #560] @ (80009bc <manageCDC+0x5c0>)
800078c: 719a strb r2, [r3, #6]
800078e: 4b8b ldr r3, [pc, #556] @ (80009bc <manageCDC+0x5c0>)
8000790: 799b ldrb r3, [r3, #6]
8000792: f887 3073 strb.w r3, [r7, #115] @ 0x73
u=rxbuf[7]-='0';
8000796: 4b89 ldr r3, [pc, #548] @ (80009bc <manageCDC+0x5c0>)
8000798: 79db ldrb r3, [r3, #7]
800079a: 3b30 subs r3, #48 @ 0x30
800079c: b2da uxtb r2, r3
800079e: 4b87 ldr r3, [pc, #540] @ (80009bc <manageCDC+0x5c0>)
80007a0: 71da strb r2, [r3, #7]
80007a2: 4b86 ldr r3, [pc, #536] @ (80009bc <manageCDC+0x5c0>)
80007a4: 79db ldrb r3, [r3, #7]
80007a6: f887 3072 strb.w r3, [r7, #114] @ 0x72
val=dm;
80007aa: f897 3076 ldrb.w r3, [r7, #118] @ 0x76
80007ae: b29b uxth r3, r3
80007b0: 817b strh r3, [r7, #10]
val*=10;
80007b2: 897b ldrh r3, [r7, #10]
80007b4: 461a mov r2, r3
80007b6: 0092 lsls r2, r2, #2
80007b8: 4413 add r3, r2
80007ba: 005b lsls r3, r3, #1
80007bc: b29b uxth r3, r3
80007be: 817b strh r3, [r7, #10]
val+=m;
80007c0: f897 3075 ldrb.w r3, [r7, #117] @ 0x75
80007c4: b29a uxth r2, r3
80007c6: 897b ldrh r3, [r7, #10]
80007c8: 4413 add r3, r2
80007ca: b29b uxth r3, r3
80007cc: 817b strh r3, [r7, #10]
val*=10;
80007ce: 897b ldrh r3, [r7, #10]
80007d0: 461a mov r2, r3
80007d2: 0092 lsls r2, r2, #2
80007d4: 4413 add r3, r2
80007d6: 005b lsls r3, r3, #1
80007d8: b29b uxth r3, r3
80007da: 817b strh r3, [r7, #10]
val+=c;
80007dc: f897 3074 ldrb.w r3, [r7, #116] @ 0x74
80007e0: b29a uxth r2, r3
80007e2: 897b ldrh r3, [r7, #10]
80007e4: 4413 add r3, r2
80007e6: b29b uxth r3, r3
80007e8: 817b strh r3, [r7, #10]
val*=10;
80007ea: 897b ldrh r3, [r7, #10]
80007ec: 461a mov r2, r3
80007ee: 0092 lsls r2, r2, #2
80007f0: 4413 add r3, r2
80007f2: 005b lsls r3, r3, #1
80007f4: b29b uxth r3, r3
80007f6: 817b strh r3, [r7, #10]
val+=d;
80007f8: f897 3073 ldrb.w r3, [r7, #115] @ 0x73
80007fc: b29a uxth r2, r3
80007fe: 897b ldrh r3, [r7, #10]
8000800: 4413 add r3, r2
8000802: b29b uxth r3, r3
8000804: 817b strh r3, [r7, #10]
val*=10;
8000806: 897b ldrh r3, [r7, #10]
8000808: 461a mov r2, r3
800080a: 0092 lsls r2, r2, #2
800080c: 4413 add r3, r2
800080e: 005b lsls r3, r3, #1
8000810: b29b uxth r3, r3
8000812: 817b strh r3, [r7, #10]
val+=u;
8000814: f897 3072 ldrb.w r3, [r7, #114] @ 0x72
8000818: b29a uxth r2, r3
800081a: 897b ldrh r3, [r7, #10]
800081c: 4413 add r3, r2
800081e: b29b uxth r3, r3
8000820: 817b strh r3, [r7, #10]
SetMot(mot,dir,val);
8000822: 897a ldrh r2, [r7, #10]
8000824: f897 107f ldrb.w r1, [r7, #127] @ 0x7f
8000828: f897 3077 ldrb.w r3, [r7, #119] @ 0x77
800082c: 4618 mov r0, r3
800082e: f001 f8e5 bl 80019fc <SetMot>
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
8000832: e032 b.n 800089a <manageCDC+0x49e>
}else{
sprintf((char*)s,"\n?mnsvvvvv 00000>=vvvvv<=99999");//m nmotore senso valore
8000834: f107 030c add.w r3, r7, #12
8000838: 4961 ldr r1, [pc, #388] @ (80009c0 <manageCDC+0x5c4>)
800083a: 4618 mov r0, r3
800083c: f00a fd00 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
8000840: bf00 nop
8000842: f107 030c add.w r3, r7, #12
8000846: 2113 movs r1, #19
8000848: 4618 mov r0, r3
800084a: f00a f91b bl 800aa84 <CDC_Transmit_FS>
800084e: 4603 mov r3, r0
8000850: 2b01 cmp r3, #1
8000852: d0f6 beq.n 8000842 <manageCDC+0x446>
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
8000854: e021 b.n 800089a <manageCDC+0x49e>
}
}else{
sprintf((char*)s,"\n?mnsvvvvv 1>=m<=4");//m nmotore senso valore
8000856: f107 030c add.w r3, r7, #12
800085a: 495a ldr r1, [pc, #360] @ (80009c4 <manageCDC+0x5c8>)
800085c: 4618 mov r0, r3
800085e: f00a fcef bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
8000862: bf00 nop
8000864: f107 030c add.w r3, r7, #12
8000868: 2113 movs r1, #19
800086a: 4618 mov r0, r3
800086c: f00a f90a bl 800aa84 <CDC_Transmit_FS>
8000870: 4603 mov r3, r0
8000872: 2b01 cmp r3, #1
8000874: d0f6 beq.n 8000864 <manageCDC+0x468>
}
}else{
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
}
break;
8000876: e1f1 b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
8000878: f107 030c add.w r3, r7, #12
800087c: 4952 ldr r1, [pc, #328] @ (80009c8 <manageCDC+0x5cc>)
800087e: 4618 mov r0, r3
8000880: f00a fcde bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
8000884: bf00 nop
8000886: f107 030c add.w r3, r7, #12
800088a: 210a movs r1, #10
800088c: 4618 mov r0, r3
800088e: f00a f8f9 bl 800aa84 <CDC_Transmit_FS>
8000892: 4603 mov r3, r0
8000894: 2b01 cmp r3, #1
8000896: d0f6 beq.n 8000886 <manageCDC+0x48a>
break;
8000898: e1e0 b.n 8000c5c <manageCDC+0x860>
800089a: e1df b.n 8000c5c <manageCDC+0x860>
case 'e':
if(rxidx>1){
800089c: 4b4b ldr r3, [pc, #300] @ (80009cc <manageCDC+0x5d0>)
800089e: 781b ldrb r3, [r3, #0]
80008a0: 2b01 cmp r3, #1
80008a2: f240 81b2 bls.w 8000c0a <manageCDC+0x80e>
if(rxbuf[1]=='r'){
80008a6: 4b45 ldr r3, [pc, #276] @ (80009bc <manageCDC+0x5c0>)
80008a8: 785b ldrb r3, [r3, #1]
80008aa: 2b72 cmp r3, #114 @ 0x72
80008ac: f040 8098 bne.w 80009e0 <manageCDC+0x5e4>
if(rxidx==4){
80008b0: 4b46 ldr r3, [pc, #280] @ (80009cc <manageCDC+0x5d0>)
80008b2: 781b ldrb r3, [r3, #0]
80008b4: 2b04 cmp r3, #4
80008b6: d169 bne.n 800098c <manageCDC+0x590>
if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){
80008b8: 4b40 ldr r3, [pc, #256] @ (80009bc <manageCDC+0x5c0>)
80008ba: 789a ldrb r2, [r3, #2]
80008bc: 4b3f ldr r3, [pc, #252] @ (80009bc <manageCDC+0x5c0>)
80008be: 78d9 ldrb r1, [r3, #3]
80008c0: f107 0308 add.w r3, r7, #8
80008c4: 9300 str r3, [sp, #0]
80008c6: 460b mov r3, r1
80008c8: 2130 movs r1, #48 @ 0x30
80008ca: 2030 movs r0, #48 @ 0x30
80008cc: f7ff fcfb bl 80002c6 <toHex>
80008d0: 4603 mov r3, r0
80008d2: 2b00 cmp r3, #0
80008d4: d042 beq.n 800095c <manageCDC+0x560>
st=EEW_Read(eeadd, &val);
80008d6: 893b ldrh r3, [r7, #8]
80008d8: b2db uxtb r3, r3
80008da: f107 020a add.w r2, r7, #10
80008de: 4611 mov r1, r2
80008e0: 4618 mov r0, r3
80008e2: f7ff fcc7 bl 8000274 <EEW_Read>
80008e6: 4603 mov r3, r0
80008e8: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK){
80008ec: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
80008f0: 2b00 cmp r3, #0
80008f2: d119 bne.n 8000928 <manageCDC+0x52c>
sprintf((char*)s,"\nee 0x%02x=0x%04x",eeadd,val);
80008f4: 893b ldrh r3, [r7, #8]
80008f6: 461a mov r2, r3
80008f8: 897b ldrh r3, [r7, #10]
80008fa: f107 000c add.w r0, r7, #12
80008fe: 4934 ldr r1, [pc, #208] @ (80009d0 <manageCDC+0x5d4>)
8000900: f00a fc9e bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000904: bf00 nop
8000906: f107 030c add.w r3, r7, #12
800090a: 4618 mov r0, r3
800090c: f7ff fc1e bl 800014c <strlen>
8000910: 4603 mov r3, r0
8000912: b29a uxth r2, r3
8000914: f107 030c add.w r3, r7, #12
8000918: 4611 mov r1, r2
800091a: 4618 mov r0, r3
800091c: f00a f8b2 bl 800aa84 <CDC_Transmit_FS>
8000920: 4603 mov r3, r0
8000922: 2b01 cmp r3, #1
8000924: d0ef beq.n 8000906 <manageCDC+0x50a>
}
}else{
sprintf((char*)s,"\n?eraa | ewaavvvv");
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
}
break;
8000926: e199 b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\nee read error %d",st);
8000928: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
800092c: f107 030c add.w r3, r7, #12
8000930: 4928 ldr r1, [pc, #160] @ (80009d4 <manageCDC+0x5d8>)
8000932: 4618 mov r0, r3
8000934: f00a fc84 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000938: bf00 nop
800093a: f107 030c add.w r3, r7, #12
800093e: 4618 mov r0, r3
8000940: f7ff fc04 bl 800014c <strlen>
8000944: 4603 mov r3, r0
8000946: b29a uxth r2, r3
8000948: f107 030c add.w r3, r7, #12
800094c: 4611 mov r1, r2
800094e: 4618 mov r0, r3
8000950: f00a f898 bl 800aa84 <CDC_Transmit_FS>
8000954: 4603 mov r3, r0
8000956: 2b01 cmp r3, #1
8000958: d0ef beq.n 800093a <manageCDC+0x53e>
break;
800095a: e17f b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\n?eraa hex values");
800095c: f107 030c add.w r3, r7, #12
8000960: 491d ldr r1, [pc, #116] @ (80009d8 <manageCDC+0x5dc>)
8000962: 4618 mov r0, r3
8000964: f00a fc6c bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000968: bf00 nop
800096a: f107 030c add.w r3, r7, #12
800096e: 4618 mov r0, r3
8000970: f7ff fbec bl 800014c <strlen>
8000974: 4603 mov r3, r0
8000976: b29a uxth r2, r3
8000978: f107 030c add.w r3, r7, #12
800097c: 4611 mov r1, r2
800097e: 4618 mov r0, r3
8000980: f00a f880 bl 800aa84 <CDC_Transmit_FS>
8000984: 4603 mov r3, r0
8000986: 2b01 cmp r3, #1
8000988: d0ef beq.n 800096a <manageCDC+0x56e>
break;
800098a: e167 b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\n?eraa");
800098c: f107 030c add.w r3, r7, #12
8000990: 4912 ldr r1, [pc, #72] @ (80009dc <manageCDC+0x5e0>)
8000992: 4618 mov r0, r3
8000994: f00a fc54 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000998: bf00 nop
800099a: f107 030c add.w r3, r7, #12
800099e: 4618 mov r0, r3
80009a0: f7ff fbd4 bl 800014c <strlen>
80009a4: 4603 mov r3, r0
80009a6: b29a uxth r2, r3
80009a8: f107 030c add.w r3, r7, #12
80009ac: 4611 mov r1, r2
80009ae: 4618 mov r0, r3
80009b0: f00a f868 bl 800aa84 <CDC_Transmit_FS>
80009b4: 4603 mov r3, r0
80009b6: 2b01 cmp r3, #1
80009b8: d0ef beq.n 800099a <manageCDC+0x59e>
break;
80009ba: e14f b.n 8000c5c <manageCDC+0x860>
80009bc: 20000228 .word 0x20000228
80009c0: 0800bc64 .word 0x0800bc64
80009c4: 0800bc84 .word 0x0800bc84
80009c8: 0800bc98 .word 0x0800bc98
80009cc: 20000224 .word 0x20000224
80009d0: 0800bca4 .word 0x0800bca4
80009d4: 0800bcb8 .word 0x0800bcb8
80009d8: 0800bccc .word 0x0800bccc
80009dc: 0800bce0 .word 0x0800bce0
}else if(rxbuf[1]=='w'){
80009e0: 4ba6 ldr r3, [pc, #664] @ (8000c7c <manageCDC+0x880>)
80009e2: 785b ldrb r3, [r3, #1]
80009e4: 2b77 cmp r3, #119 @ 0x77
80009e6: d169 bne.n 8000abc <manageCDC+0x6c0>
if(rxidx==8){
80009e8: 4ba5 ldr r3, [pc, #660] @ (8000c80 <manageCDC+0x884>)
80009ea: 781b ldrb r3, [r3, #0]
80009ec: 2b08 cmp r3, #8
80009ee: d14d bne.n 8000a8c <manageCDC+0x690>
if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){
80009f0: 4ba2 ldr r3, [pc, #648] @ (8000c7c <manageCDC+0x880>)
80009f2: 789a ldrb r2, [r3, #2]
80009f4: 4ba1 ldr r3, [pc, #644] @ (8000c7c <manageCDC+0x880>)
80009f6: 78d9 ldrb r1, [r3, #3]
80009f8: f107 0308 add.w r3, r7, #8
80009fc: 9300 str r3, [sp, #0]
80009fe: 460b mov r3, r1
8000a00: 2130 movs r1, #48 @ 0x30
8000a02: 2030 movs r0, #48 @ 0x30
8000a04: f7ff fc5f bl 80002c6 <toHex>
8000a08: 4603 mov r3, r0
8000a0a: 2b00 cmp r3, #0
8000a0c: d037 beq.n 8000a7e <manageCDC+0x682>
if(toHex(rxbuf[4],rxbuf[5],rxbuf[6],rxbuf[7],&val)){
8000a0e: 4b9b ldr r3, [pc, #620] @ (8000c7c <manageCDC+0x880>)
8000a10: 7918 ldrb r0, [r3, #4]
8000a12: 4b9a ldr r3, [pc, #616] @ (8000c7c <manageCDC+0x880>)
8000a14: 7959 ldrb r1, [r3, #5]
8000a16: 4b99 ldr r3, [pc, #612] @ (8000c7c <manageCDC+0x880>)
8000a18: 799a ldrb r2, [r3, #6]
8000a1a: 4b98 ldr r3, [pc, #608] @ (8000c7c <manageCDC+0x880>)
8000a1c: 79dc ldrb r4, [r3, #7]
8000a1e: f107 030a add.w r3, r7, #10
8000a22: 9300 str r3, [sp, #0]
8000a24: 4623 mov r3, r4
8000a26: f7ff fc4e bl 80002c6 <toHex>
8000a2a: 4603 mov r3, r0
8000a2c: 2b00 cmp r3, #0
8000a2e: d01f beq.n 8000a70 <manageCDC+0x674>
st=EEW_Write(eeadd, val);
8000a30: 893b ldrh r3, [r7, #8]
8000a32: b2db uxtb r3, r3
8000a34: 897a ldrh r2, [r7, #10]
8000a36: 4611 mov r1, r2
8000a38: 4618 mov r0, r3
8000a3a: f7ff fc2e bl 800029a <EEW_Write>
8000a3e: 4603 mov r3, r0
8000a40: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK)sprintf((char*)s,"\ndone 0x%02x=0x%04x",eeadd,val);
8000a44: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000a48: 2b00 cmp r3, #0
8000a4a: d108 bne.n 8000a5e <manageCDC+0x662>
8000a4c: 893b ldrh r3, [r7, #8]
8000a4e: 461a mov r2, r3
8000a50: 897b ldrh r3, [r7, #10]
8000a52: f107 000c add.w r0, r7, #12
8000a56: 498b ldr r1, [pc, #556] @ (8000c84 <manageCDC+0x888>)
8000a58: f00a fbf2 bl 800b240 <siprintf>
8000a5c: e01c b.n 8000a98 <manageCDC+0x69c>
else sprintf((char*)s,"\nee write error %d", st);
8000a5e: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000a62: f107 030c add.w r3, r7, #12
8000a66: 4988 ldr r1, [pc, #544] @ (8000c88 <manageCDC+0x88c>)
8000a68: 4618 mov r0, r3
8000a6a: f00a fbe9 bl 800b240 <siprintf>
8000a6e: e013 b.n 8000a98 <manageCDC+0x69c>
}else sprintf((char*)s,"\n?ewaavvvv hex values");
8000a70: f107 030c add.w r3, r7, #12
8000a74: 4985 ldr r1, [pc, #532] @ (8000c8c <manageCDC+0x890>)
8000a76: 4618 mov r0, r3
8000a78: f00a fbe2 bl 800b240 <siprintf>
8000a7c: e00c b.n 8000a98 <manageCDC+0x69c>
}else sprintf((char*)s,"\n?ewaa hex values");
8000a7e: f107 030c add.w r3, r7, #12
8000a82: 4983 ldr r1, [pc, #524] @ (8000c90 <manageCDC+0x894>)
8000a84: 4618 mov r0, r3
8000a86: f00a fbdb bl 800b240 <siprintf>
8000a8a: e005 b.n 8000a98 <manageCDC+0x69c>
}else sprintf((char*)s,"\n?ewaavvvv");
8000a8c: f107 030c add.w r3, r7, #12
8000a90: 4980 ldr r1, [pc, #512] @ (8000c94 <manageCDC+0x898>)
8000a92: 4618 mov r0, r3
8000a94: f00a fbd4 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000a98: bf00 nop
8000a9a: f107 030c add.w r3, r7, #12
8000a9e: 4618 mov r0, r3
8000aa0: f7ff fb54 bl 800014c <strlen>
8000aa4: 4603 mov r3, r0
8000aa6: b29a uxth r2, r3
8000aa8: f107 030c add.w r3, r7, #12
8000aac: 4611 mov r1, r2
8000aae: 4618 mov r0, r3
8000ab0: f009 ffe8 bl 800aa84 <CDC_Transmit_FS>
8000ab4: 4603 mov r3, r0
8000ab6: 2b01 cmp r3, #1
8000ab8: d0ef beq.n 8000a9a <manageCDC+0x69e>
break;
8000aba: e0cf b.n 8000c5c <manageCDC+0x860>
}else if(rxbuf[1]=='d'){
8000abc: 4b6f ldr r3, [pc, #444] @ (8000c7c <manageCDC+0x880>)
8000abe: 785b ldrb r3, [r3, #1]
8000ac0: 2b64 cmp r3, #100 @ 0x64
8000ac2: f040 808a bne.w 8000bda <manageCDC+0x7de>
if(rxidx==2){
8000ac6: 4b6e ldr r3, [pc, #440] @ (8000c80 <manageCDC+0x884>)
8000ac8: 781b ldrb r3, [r3, #0]
8000aca: 2b02 cmp r3, #2
8000acc: d16d bne.n 8000baa <manageCDC+0x7ae>
for(i=0;i<32;i++){
8000ace: 2300 movs r3, #0
8000ad0: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000ad4: e064 b.n 8000ba0 <manageCDC+0x7a4>
if((i%4)==0){
8000ad6: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000ada: f003 0303 and.w r3, r3, #3
8000ade: b2db uxtb r3, r3
8000ae0: 2b00 cmp r3, #0
8000ae2: d116 bne.n 8000b12 <manageCDC+0x716>
sprintf((char*)s,"\n");
8000ae4: f107 030c add.w r3, r7, #12
8000ae8: 496b ldr r1, [pc, #428] @ (8000c98 <manageCDC+0x89c>)
8000aea: 4618 mov r0, r3
8000aec: f00a fba8 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000af0: bf00 nop
8000af2: f107 030c add.w r3, r7, #12
8000af6: 4618 mov r0, r3
8000af8: f7ff fb28 bl 800014c <strlen>
8000afc: 4603 mov r3, r0
8000afe: b29a uxth r2, r3
8000b00: f107 030c add.w r3, r7, #12
8000b04: 4611 mov r1, r2
8000b06: 4618 mov r0, r3
8000b08: f009 ffbc bl 800aa84 <CDC_Transmit_FS>
8000b0c: 4603 mov r3, r0
8000b0e: 2b01 cmp r3, #1
8000b10: d0ef beq.n 8000af2 <manageCDC+0x6f6>
st=EEW_Read(i, &val);
8000b12: f107 020a add.w r2, r7, #10
8000b16: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000b1a: 4611 mov r1, r2
8000b1c: 4618 mov r0, r3
8000b1e: f7ff fba9 bl 8000274 <EEW_Read>
8000b22: 4603 mov r3, r0
8000b24: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK){
8000b28: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000b2c: 2b00 cmp r3, #0
8000b2e: d119 bne.n 8000b64 <manageCDC+0x768>
sprintf((char*)s,"0x%02x=0x%04x ",i,val);
8000b30: f897 207e ldrb.w r2, [r7, #126] @ 0x7e
8000b34: 897b ldrh r3, [r7, #10]
8000b36: f107 000c add.w r0, r7, #12
8000b3a: 4958 ldr r1, [pc, #352] @ (8000c9c <manageCDC+0x8a0>)
8000b3c: f00a fb80 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b40: bf00 nop
8000b42: f107 030c add.w r3, r7, #12
8000b46: 4618 mov r0, r3
8000b48: f7ff fb00 bl 800014c <strlen>
8000b4c: 4603 mov r3, r0
8000b4e: b29a uxth r2, r3
8000b50: f107 030c add.w r3, r7, #12
8000b54: 4611 mov r1, r2
8000b56: 4618 mov r0, r3
8000b58: f009 ff94 bl 800aa84 <CDC_Transmit_FS>
8000b5c: 4603 mov r3, r0
8000b5e: 2b01 cmp r3, #1
8000b60: d0ef beq.n 8000b42 <manageCDC+0x746>
8000b62: e018 b.n 8000b96 <manageCDC+0x79a>
sprintf((char*)s,"rderr %d ",st);
8000b64: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000b68: f107 030c add.w r3, r7, #12
8000b6c: 494c ldr r1, [pc, #304] @ (8000ca0 <manageCDC+0x8a4>)
8000b6e: 4618 mov r0, r3
8000b70: f00a fb66 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b74: bf00 nop
8000b76: f107 030c add.w r3, r7, #12
8000b7a: 4618 mov r0, r3
8000b7c: f7ff fae6 bl 800014c <strlen>
8000b80: 4603 mov r3, r0
8000b82: b29a uxth r2, r3
8000b84: f107 030c add.w r3, r7, #12
8000b88: 4611 mov r1, r2
8000b8a: 4618 mov r0, r3
8000b8c: f009 ff7a bl 800aa84 <CDC_Transmit_FS>
8000b90: 4603 mov r3, r0
8000b92: 2b01 cmp r3, #1
8000b94: d0ef beq.n 8000b76 <manageCDC+0x77a>
for(i=0;i<32;i++){
8000b96: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000b9a: 3301 adds r3, #1
8000b9c: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000ba0: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000ba4: 2b1f cmp r3, #31
8000ba6: d996 bls.n 8000ad6 <manageCDC+0x6da>
break;
8000ba8: e058 b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\n?ed");
8000baa: f107 030c add.w r3, r7, #12
8000bae: 493d ldr r1, [pc, #244] @ (8000ca4 <manageCDC+0x8a8>)
8000bb0: 4618 mov r0, r3
8000bb2: f00a fb45 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000bb6: bf00 nop
8000bb8: f107 030c add.w r3, r7, #12
8000bbc: 4618 mov r0, r3
8000bbe: f7ff fac5 bl 800014c <strlen>
8000bc2: 4603 mov r3, r0
8000bc4: b29a uxth r2, r3
8000bc6: f107 030c add.w r3, r7, #12
8000bca: 4611 mov r1, r2
8000bcc: 4618 mov r0, r3
8000bce: f009 ff59 bl 800aa84 <CDC_Transmit_FS>
8000bd2: 4603 mov r3, r0
8000bd4: 2b01 cmp r3, #1
8000bd6: d0ef beq.n 8000bb8 <manageCDC+0x7bc>
break;
8000bd8: e040 b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\n?er|w|d");
8000bda: f107 030c add.w r3, r7, #12
8000bde: 4932 ldr r1, [pc, #200] @ (8000ca8 <manageCDC+0x8ac>)
8000be0: 4618 mov r0, r3
8000be2: f00a fb2d bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000be6: bf00 nop
8000be8: f107 030c add.w r3, r7, #12
8000bec: 4618 mov r0, r3
8000bee: f7ff faad bl 800014c <strlen>
8000bf2: 4603 mov r3, r0
8000bf4: b29a uxth r2, r3
8000bf6: f107 030c add.w r3, r7, #12
8000bfa: 4611 mov r1, r2
8000bfc: 4618 mov r0, r3
8000bfe: f009 ff41 bl 800aa84 <CDC_Transmit_FS>
8000c02: 4603 mov r3, r0
8000c04: 2b01 cmp r3, #1
8000c06: d0ef beq.n 8000be8 <manageCDC+0x7ec>
break;
8000c08: e028 b.n 8000c5c <manageCDC+0x860>
sprintf((char*)s,"\n?eraa | ewaavvvv");
8000c0a: f107 030c add.w r3, r7, #12
8000c0e: 4927 ldr r1, [pc, #156] @ (8000cac <manageCDC+0x8b0>)
8000c10: 4618 mov r0, r3
8000c12: f00a fb15 bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000c16: bf00 nop
8000c18: f107 030c add.w r3, r7, #12
8000c1c: 4618 mov r0, r3
8000c1e: f7ff fa95 bl 800014c <strlen>
8000c22: 4603 mov r3, r0
8000c24: b29a uxth r2, r3
8000c26: f107 030c add.w r3, r7, #12
8000c2a: 4611 mov r1, r2
8000c2c: 4618 mov r0, r3
8000c2e: f009 ff29 bl 800aa84 <CDC_Transmit_FS>
8000c32: 4603 mov r3, r0
8000c34: 2b01 cmp r3, #1
8000c36: d0ef beq.n 8000c18 <manageCDC+0x81c>
break;
8000c38: e010 b.n 8000c5c <manageCDC+0x860>
default:
sprintf((char*)s,"\n?");
8000c3a: f107 030c add.w r3, r7, #12
8000c3e: 491c ldr r1, [pc, #112] @ (8000cb0 <manageCDC+0x8b4>)
8000c40: 4618 mov r0, r3
8000c42: f00a fafd bl 800b240 <siprintf>
while (CDC_Transmit_FS(s, 2) == USBD_BUSY);
8000c46: bf00 nop
8000c48: f107 030c add.w r3, r7, #12
8000c4c: 2102 movs r1, #2
8000c4e: 4618 mov r0, r3
8000c50: f009 ff18 bl 800aa84 <CDC_Transmit_FS>
8000c54: 4603 mov r3, r0
8000c56: 2b01 cmp r3, #1
8000c58: d0f6 beq.n 8000c48 <manageCDC+0x84c>
break;
8000c5a: bf00 nop
}
}
rxidx=0;
8000c5c: 4b08 ldr r3, [pc, #32] @ (8000c80 <manageCDC+0x884>)
8000c5e: 2200 movs r2, #0
8000c60: 701a strb r2, [r3, #0]
8000c62: e007 b.n 8000c74 <manageCDC+0x878>
}else rxidx++;
8000c64: 4b06 ldr r3, [pc, #24] @ (8000c80 <manageCDC+0x884>)
8000c66: 781b ldrb r3, [r3, #0]
8000c68: 3301 adds r3, #1
8000c6a: b2da uxtb r2, r3
8000c6c: 4b04 ldr r3, [pc, #16] @ (8000c80 <manageCDC+0x884>)
8000c6e: 701a strb r2, [r3, #0]
8000c70: e000 b.n 8000c74 <manageCDC+0x878>
if (rx < 0) return;
8000c72: bf00 nop
// tiny spin or yield
}
}
8000c74: 3784 adds r7, #132 @ 0x84
8000c76: 46bd mov sp, r7
8000c78: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8000c7c: 20000228 .word 0x20000228
8000c80: 20000224 .word 0x20000224
8000c84: 0800bce8 .word 0x0800bce8
8000c88: 0800bcfc .word 0x0800bcfc
8000c8c: 0800bd10 .word 0x0800bd10
8000c90: 0800bd28 .word 0x0800bd28
8000c94: 0800bd3c .word 0x0800bd3c
8000c98: 0800bd48 .word 0x0800bd48
8000c9c: 0800bd4c .word 0x0800bd4c
8000ca0: 0800bd5c .word 0x0800bd5c
8000ca4: 0800bd68 .word 0x0800bd68
8000ca8: 0800bd70 .word 0x0800bd70
8000cac: 0800bd7c .word 0x0800bd7c
8000cb0: 0800bd90 .word 0x0800bd90
08000cb4 <EE_GetPageStatus>:
/* ========================================================================= */
/* --- Internal helpers ---------------------------------------------------- */
static uint16_t EE_GetPageStatus(uint32_t pageBase)
{
8000cb4: b480 push {r7}
8000cb6: b083 sub sp, #12
8000cb8: af00 add r7, sp, #0
8000cba: 6078 str r0, [r7, #4]
return *(__IO uint16_t *)pageBase;
8000cbc: 687b ldr r3, [r7, #4]
8000cbe: 881b ldrh r3, [r3, #0]
8000cc0: b29b uxth r3, r3
}
8000cc2: 4618 mov r0, r3
8000cc4: 370c adds r7, #12
8000cc6: 46bd mov sp, r7
8000cc8: bc80 pop {r7}
8000cca: 4770 bx lr
08000ccc <EE_FlashProgramHalfWord>:
static HAL_StatusTypeDef EE_FlashProgramHalfWord(uint32_t Address, uint16_t Data)
{
8000ccc: b5b0 push {r4, r5, r7, lr}
8000cce: b084 sub sp, #16
8000cd0: af00 add r7, sp, #0
8000cd2: 6078 str r0, [r7, #4]
8000cd4: 460b mov r3, r1
8000cd6: 807b strh r3, [r7, #2]
HAL_StatusTypeDef status;
HAL_FLASH_Unlock();
8000cd8: f002 f9c8 bl 800306c <HAL_FLASH_Unlock>
status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, Address, Data);
8000cdc: 887b ldrh r3, [r7, #2]
8000cde: 2200 movs r2, #0
8000ce0: 461c mov r4, r3
8000ce2: 4615 mov r5, r2
8000ce4: 4622 mov r2, r4
8000ce6: 462b mov r3, r5
8000ce8: 6879 ldr r1, [r7, #4]
8000cea: 2001 movs r0, #1
8000cec: f002 f94e bl 8002f8c <HAL_FLASH_Program>
8000cf0: 4603 mov r3, r0
8000cf2: 73fb strb r3, [r7, #15]
HAL_FLASH_Lock();
8000cf4: f002 f9e0 bl 80030b8 <HAL_FLASH_Lock>
return status;
8000cf8: 7bfb ldrb r3, [r7, #15]
}
8000cfa: 4618 mov r0, r3
8000cfc: 3710 adds r7, #16
8000cfe: 46bd mov sp, r7
8000d00: bdb0 pop {r4, r5, r7, pc}
08000d02 <EE_FlashErasePage>:
static HAL_StatusTypeDef EE_FlashErasePage(uint32_t PageAddress)
{
8000d02: b580 push {r7, lr}
8000d04: b088 sub sp, #32
8000d06: af00 add r7, sp, #0
8000d08: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
FLASH_EraseInitTypeDef EraseInit;
uint32_t PageError = 0;
8000d0a: 2300 movs r3, #0
8000d0c: 60bb str r3, [r7, #8]
HAL_FLASH_Unlock();
8000d0e: f002 f9ad bl 800306c <HAL_FLASH_Unlock>
EraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
8000d12: 2300 movs r3, #0
8000d14: 60fb str r3, [r7, #12]
EraseInit.PageAddress = PageAddress;
8000d16: 687b ldr r3, [r7, #4]
8000d18: 617b str r3, [r7, #20]
EraseInit.NbPages = 1;
8000d1a: 2301 movs r3, #1
8000d1c: 61bb str r3, [r7, #24]
status = HAL_FLASHEx_Erase(&EraseInit, &PageError);
8000d1e: f107 0208 add.w r2, r7, #8
8000d22: f107 030c add.w r3, r7, #12
8000d26: 4611 mov r1, r2
8000d28: 4618 mov r0, r3
8000d2a: f002 fa87 bl 800323c <HAL_FLASHEx_Erase>
8000d2e: 4603 mov r3, r0
8000d30: 77fb strb r3, [r7, #31]
HAL_FLASH_Lock();
8000d32: f002 f9c1 bl 80030b8 <HAL_FLASH_Lock>
return status;
8000d36: 7ffb ldrb r3, [r7, #31]
}
8000d38: 4618 mov r0, r3
8000d3a: 3720 adds r7, #32
8000d3c: 46bd mov sp, r7
8000d3e: bd80 pop {r7, pc}
08000d40 <EE_FindFreeAddress>:
/* Find first free record address in given page (returns 0 if full) */
static uint32_t EE_FindFreeAddress(uint32_t pageBase)
{
8000d40: b480 push {r7}
8000d42: b087 sub sp, #28
8000d44: af00 add r7, sp, #0
8000d46: 6078 str r0, [r7, #4]
uint32_t addr = pageBase + 2U; /* Skip status word */
8000d48: 687b ldr r3, [r7, #4]
8000d4a: 3302 adds r3, #2
8000d4c: 617b str r3, [r7, #20]
uint32_t pageEnd = pageBase + EE_PAGE_SIZE;
8000d4e: 687b ldr r3, [r7, #4]
8000d50: f503 6380 add.w r3, r3, #1024 @ 0x400
8000d54: 613b str r3, [r7, #16]
while (addr < (pageEnd - sizeof(EE_Record_t) + 1U))
8000d56: e00c b.n 8000d72 <EE_FindFreeAddress+0x32>
{
uint16_t vaddr = *(__IO uint16_t *)addr;
8000d58: 697b ldr r3, [r7, #20]
8000d5a: 881b ldrh r3, [r3, #0]
8000d5c: 81fb strh r3, [r7, #14]
if (vaddr == 0xFFFFU)
8000d5e: 89fb ldrh r3, [r7, #14]
8000d60: f64f 72ff movw r2, #65535 @ 0xffff
8000d64: 4293 cmp r3, r2
8000d66: d101 bne.n 8000d6c <EE_FindFreeAddress+0x2c>
{
/* Empty slot */
return addr;
8000d68: 697b ldr r3, [r7, #20]
8000d6a: e008 b.n 8000d7e <EE_FindFreeAddress+0x3e>
}
addr += sizeof(EE_Record_t);
8000d6c: 697b ldr r3, [r7, #20]
8000d6e: 3304 adds r3, #4
8000d70: 617b str r3, [r7, #20]
while (addr < (pageEnd - sizeof(EE_Record_t) + 1U))
8000d72: 693b ldr r3, [r7, #16]
8000d74: 3b03 subs r3, #3
8000d76: 697a ldr r2, [r7, #20]
8000d78: 429a cmp r2, r3
8000d7a: d3ed bcc.n 8000d58 <EE_FindFreeAddress+0x18>
}
return 0U; /* No space */
8000d7c: 2300 movs r3, #0
}
8000d7e: 4618 mov r0, r3
8000d80: 371c adds r7, #28
8000d82: 46bd mov sp, r7
8000d84: bc80 pop {r7}
8000d86: 4770 bx lr
08000d88 <EE_FindInPage>:
/* Find latest value of VirtAddress in a specific page (internal, uses EE_Status) */
/* Find latest value of VirtAddress in a specific page (scan forward) */
static EE_Status EE_FindInPage(uint32_t pageBase, uint16_t VirtAddress, uint16_t *Data)
{
8000d88: b480 push {r7}
8000d8a: b089 sub sp, #36 @ 0x24
8000d8c: af00 add r7, sp, #0
8000d8e: 60f8 str r0, [r7, #12]
8000d90: 460b mov r3, r1
8000d92: 607a str r2, [r7, #4]
8000d94: 817b strh r3, [r7, #10]
uint32_t addr = pageBase + 2U; // skip status halfword
8000d96: 68fb ldr r3, [r7, #12]
8000d98: 3302 adds r3, #2
8000d9a: 61fb str r3, [r7, #28]
uint32_t pageEnd = pageBase + EE_PAGE_SIZE;
8000d9c: 68fb ldr r3, [r7, #12]
8000d9e: f503 6380 add.w r3, r3, #1024 @ 0x400
8000da2: 617b str r3, [r7, #20]
EE_Status result = EE_NOT_FOUND;
8000da4: 2302 movs r3, #2
8000da6: 76fb strb r3, [r7, #27]
uint16_t lastVal = 0;
8000da8: 2300 movs r3, #0
8000daa: 833b strh r3, [r7, #24]
if (Data == NULL)
8000dac: 687b ldr r3, [r7, #4]
8000dae: 2b00 cmp r3, #0
8000db0: d118 bne.n 8000de4 <EE_FindInPage+0x5c>
return EE_ERROR;
8000db2: 2301 movs r3, #1
8000db4: e024 b.n 8000e00 <EE_FindInPage+0x78>
while (addr <= (pageEnd - sizeof(EE_Record_t)))
{
uint16_t vaddr = *(__IO uint16_t *)addr;
8000db6: 69fb ldr r3, [r7, #28]
8000db8: 881b ldrh r3, [r3, #0]
8000dba: 827b strh r3, [r7, #18]
if (vaddr == 0xFFFFU)
8000dbc: 8a7b ldrh r3, [r7, #18]
8000dbe: f64f 72ff movw r2, #65535 @ 0xffff
8000dc2: 4293 cmp r3, r2
8000dc4: d014 beq.n 8000df0 <EE_FindInPage+0x68>
{
// First empty slot => no more records in this page
break;
}
uint16_t value = *(__IO uint16_t *)(addr + 2U);
8000dc6: 69fb ldr r3, [r7, #28]
8000dc8: 3302 adds r3, #2
8000dca: 881b ldrh r3, [r3, #0]
8000dcc: 823b strh r3, [r7, #16]
if (vaddr == VirtAddress)
8000dce: 8a7a ldrh r2, [r7, #18]
8000dd0: 897b ldrh r3, [r7, #10]
8000dd2: 429a cmp r2, r3
8000dd4: d103 bne.n 8000dde <EE_FindInPage+0x56>
{
lastVal = value; // keep most recent
8000dd6: 8a3b ldrh r3, [r7, #16]
8000dd8: 833b strh r3, [r7, #24]
result = EE_OK;
8000dda: 2300 movs r3, #0
8000ddc: 76fb strb r3, [r7, #27]
}
addr += sizeof(EE_Record_t); // move 4 bytes forward
8000dde: 69fb ldr r3, [r7, #28]
8000de0: 3304 adds r3, #4
8000de2: 61fb str r3, [r7, #28]
while (addr <= (pageEnd - sizeof(EE_Record_t)))
8000de4: 697b ldr r3, [r7, #20]
8000de6: 3b04 subs r3, #4
8000de8: 69fa ldr r2, [r7, #28]
8000dea: 429a cmp r2, r3
8000dec: d9e3 bls.n 8000db6 <EE_FindInPage+0x2e>
8000dee: e000 b.n 8000df2 <EE_FindInPage+0x6a>
break;
8000df0: bf00 nop
}
if (result == EE_OK)
8000df2: 7efb ldrb r3, [r7, #27]
8000df4: 2b00 cmp r3, #0
8000df6: d102 bne.n 8000dfe <EE_FindInPage+0x76>
*Data = lastVal;
8000df8: 687b ldr r3, [r7, #4]
8000dfa: 8b3a ldrh r2, [r7, #24]
8000dfc: 801a strh r2, [r3, #0]
return result;
8000dfe: 7efb ldrb r3, [r7, #27]
}
8000e00: 4618 mov r0, r3
8000e02: 3724 adds r7, #36 @ 0x24
8000e04: 46bd mov sp, r7
8000e06: bc80 pop {r7}
8000e08: 4770 bx lr
...
08000e0c <EE_Format>:
/* Format both pages: erase and set PAGE0 as VALID */
static EE_Status EE_Format(void)
{
8000e0c: b580 push {r7, lr}
8000e0e: af00 add r7, sp, #0
if (EE_FlashErasePage(EE_PAGE0_BASE) != HAL_OK)
8000e10: 480f ldr r0, [pc, #60] @ (8000e50 <EE_Format+0x44>)
8000e12: f7ff ff76 bl 8000d02 <EE_FlashErasePage>
8000e16: 4603 mov r3, r0
8000e18: 2b00 cmp r3, #0
8000e1a: d001 beq.n 8000e20 <EE_Format+0x14>
return EE_STATUS_ERROR;
8000e1c: 2301 movs r3, #1
8000e1e: e015 b.n 8000e4c <EE_Format+0x40>
if (EE_FlashErasePage(EE_PAGE1_BASE) != HAL_OK)
8000e20: 480c ldr r0, [pc, #48] @ (8000e54 <EE_Format+0x48>)
8000e22: f7ff ff6e bl 8000d02 <EE_FlashErasePage>
8000e26: 4603 mov r3, r0
8000e28: 2b00 cmp r3, #0
8000e2a: d001 beq.n 8000e30 <EE_Format+0x24>
return EE_STATUS_ERROR;
8000e2c: 2301 movs r3, #1
8000e2e: e00d b.n 8000e4c <EE_Format+0x40>
if (EE_FlashProgramHalfWord(EE_PAGE0_BASE, EE_PAGE_STATUS_VALID) != HAL_OK)
8000e30: f64a 21aa movw r1, #43690 @ 0xaaaa
8000e34: 4806 ldr r0, [pc, #24] @ (8000e50 <EE_Format+0x44>)
8000e36: f7ff ff49 bl 8000ccc <EE_FlashProgramHalfWord>
8000e3a: 4603 mov r3, r0
8000e3c: 2b00 cmp r3, #0
8000e3e: d001 beq.n 8000e44 <EE_Format+0x38>
return EE_STATUS_ERROR;
8000e40: 2301 movs r3, #1
8000e42: e003 b.n 8000e4c <EE_Format+0x40>
/* PAGE1 will remain erased (status = 0xFFFF) */
EE_ActivePageBase = EE_PAGE0_BASE;
8000e44: 4b04 ldr r3, [pc, #16] @ (8000e58 <EE_Format+0x4c>)
8000e46: 4a02 ldr r2, [pc, #8] @ (8000e50 <EE_Format+0x44>)
8000e48: 601a str r2, [r3, #0]
return EE_STATUS_OK;
8000e4a: 2300 movs r3, #0
}
8000e4c: 4618 mov r0, r3
8000e4e: bd80 pop {r7, pc}
8000e50: 0800f800 .word 0x0800f800
8000e54: 0800fc00 .word 0x0800fc00
8000e58: 20000000 .word 0x20000000
08000e5c <EE_GetOtherPageBase>:
/* Get the base of the other page */
static uint32_t EE_GetOtherPageBase(uint32_t pageBase)
{
8000e5c: b480 push {r7}
8000e5e: b083 sub sp, #12
8000e60: af00 add r7, sp, #0
8000e62: 6078 str r0, [r7, #4]
return (pageBase == EE_PAGE0_BASE) ? EE_PAGE1_BASE : EE_PAGE0_BASE;
8000e64: 687b ldr r3, [r7, #4]
8000e66: 4a05 ldr r2, [pc, #20] @ (8000e7c <EE_GetOtherPageBase+0x20>)
8000e68: 4293 cmp r3, r2
8000e6a: d101 bne.n 8000e70 <EE_GetOtherPageBase+0x14>
8000e6c: 4b04 ldr r3, [pc, #16] @ (8000e80 <EE_GetOtherPageBase+0x24>)
8000e6e: e000 b.n 8000e72 <EE_GetOtherPageBase+0x16>
8000e70: 4b02 ldr r3, [pc, #8] @ (8000e7c <EE_GetOtherPageBase+0x20>)
}
8000e72: 4618 mov r0, r3
8000e74: 370c adds r7, #12
8000e76: 46bd mov sp, r7
8000e78: bc80 pop {r7}
8000e7a: 4770 bx lr
8000e7c: 0800f800 .word 0x0800f800
8000e80: 0800fc00 .word 0x0800fc00
08000e84 <EE_PageTransfer>:
/* Page transfer (garbage collection + new write) */
static EE_Status EE_PageTransfer(uint16_t VirtAddress, uint16_t Data)
{
8000e84: b580 push {r7, lr}
8000e86: b088 sub sp, #32
8000e88: af00 add r7, sp, #0
8000e8a: 4603 mov r3, r0
8000e8c: 460a mov r2, r1
8000e8e: 80fb strh r3, [r7, #6]
8000e90: 4613 mov r3, r2
8000e92: 80bb strh r3, [r7, #4]
uint32_t oldBase = EE_ActivePageBase;
8000e94: 4b3c ldr r3, [pc, #240] @ (8000f88 <EE_PageTransfer+0x104>)
8000e96: 681b ldr r3, [r3, #0]
8000e98: 617b str r3, [r7, #20]
uint32_t newBase = EE_GetOtherPageBase(oldBase);
8000e9a: 6978 ldr r0, [r7, #20]
8000e9c: f7ff ffde bl 8000e5c <EE_GetOtherPageBase>
8000ea0: 6138 str r0, [r7, #16]
uint32_t addr;
uint16_t value;
EE_Status st;
/* Erase new page */
if (EE_FlashErasePage(newBase) != HAL_OK)
8000ea2: 6938 ldr r0, [r7, #16]
8000ea4: f7ff ff2d bl 8000d02 <EE_FlashErasePage>
8000ea8: 4603 mov r3, r0
8000eaa: 2b00 cmp r3, #0
8000eac: d001 beq.n 8000eb2 <EE_PageTransfer+0x2e>
return EE_STATUS_ERROR;
8000eae: 2301 movs r3, #1
8000eb0: e065 b.n 8000f7e <EE_PageTransfer+0xfa>
/* Mark new page as RECEIVE */
if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_RECEIVE) != HAL_OK)
8000eb2: f245 5155 movw r1, #21845 @ 0x5555
8000eb6: 6938 ldr r0, [r7, #16]
8000eb8: f7ff ff08 bl 8000ccc <EE_FlashProgramHalfWord>
8000ebc: 4603 mov r3, r0
8000ebe: 2b00 cmp r3, #0
8000ec0: d001 beq.n 8000ec6 <EE_PageTransfer+0x42>
return EE_STATUS_ERROR;
8000ec2: 2301 movs r3, #1
8000ec4: e05b b.n 8000f7e <EE_PageTransfer+0xfa>
/* Start writing records just after status */
addr = newBase + 2U;
8000ec6: 693b ldr r3, [r7, #16]
8000ec8: 3302 adds r3, #2
8000eca: 61fb str r3, [r7, #28]
/* For each known virtual variable */
for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++)
8000ecc: 2300 movs r3, #0
8000ece: 837b strh r3, [r7, #26]
8000ed0: e03c b.n 8000f4c <EE_PageTransfer+0xc8>
{
uint16_t vaddr = EE_VirtAddrs[i];
8000ed2: 8b7b ldrh r3, [r7, #26]
8000ed4: 4a2d ldr r2, [pc, #180] @ (8000f8c <EE_PageTransfer+0x108>)
8000ed6: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8000eda: 81fb strh r3, [r7, #14]
if (vaddr == VirtAddress)
8000edc: 89fa ldrh r2, [r7, #14]
8000ede: 88fb ldrh r3, [r7, #6]
8000ee0: 429a cmp r2, r3
8000ee2: d102 bne.n 8000eea <EE_PageTransfer+0x66>
{
/* Use the new data passed into PageTransfer */
value = Data;
8000ee4: 88bb ldrh r3, [r7, #4]
8000ee6: 817b strh r3, [r7, #10]
8000ee8: e00b b.n 8000f02 <EE_PageTransfer+0x7e>
}
else
{
/* Read latest value from old active page */
st = EE_FindInPage(oldBase, vaddr, &value);
8000eea: f107 020a add.w r2, r7, #10
8000eee: 89fb ldrh r3, [r7, #14]
8000ef0: 4619 mov r1, r3
8000ef2: 6978 ldr r0, [r7, #20]
8000ef4: f7ff ff48 bl 8000d88 <EE_FindInPage>
8000ef8: 4603 mov r3, r0
8000efa: 737b strb r3, [r7, #13]
if (st != EE_STATUS_OK)
8000efc: 7b7b ldrb r3, [r7, #13]
8000efe: 2b00 cmp r3, #0
8000f00: d120 bne.n 8000f44 <EE_PageTransfer+0xc0>
continue;
}
}
/* Write record to new page */
if (EE_FlashProgramHalfWord(addr, vaddr) != HAL_OK)
8000f02: 89fb ldrh r3, [r7, #14]
8000f04: 4619 mov r1, r3
8000f06: 69f8 ldr r0, [r7, #28]
8000f08: f7ff fee0 bl 8000ccc <EE_FlashProgramHalfWord>
8000f0c: 4603 mov r3, r0
8000f0e: 2b00 cmp r3, #0
8000f10: d001 beq.n 8000f16 <EE_PageTransfer+0x92>
return EE_STATUS_ERROR;
8000f12: 2301 movs r3, #1
8000f14: e033 b.n 8000f7e <EE_PageTransfer+0xfa>
if (EE_FlashProgramHalfWord(addr + 2U, value) != HAL_OK)
8000f16: 69fb ldr r3, [r7, #28]
8000f18: 3302 adds r3, #2
8000f1a: 897a ldrh r2, [r7, #10]
8000f1c: 4611 mov r1, r2
8000f1e: 4618 mov r0, r3
8000f20: f7ff fed4 bl 8000ccc <EE_FlashProgramHalfWord>
8000f24: 4603 mov r3, r0
8000f26: 2b00 cmp r3, #0
8000f28: d001 beq.n 8000f2e <EE_PageTransfer+0xaa>
return EE_STATUS_ERROR;
8000f2a: 2301 movs r3, #1
8000f2c: e027 b.n 8000f7e <EE_PageTransfer+0xfa>
addr += sizeof(EE_Record_t);
8000f2e: 69fb ldr r3, [r7, #28]
8000f30: 3304 adds r3, #4
8000f32: 61fb str r3, [r7, #28]
if (addr >= (newBase + EE_PAGE_SIZE))
8000f34: 693b ldr r3, [r7, #16]
8000f36: f503 6380 add.w r3, r3, #1024 @ 0x400
8000f3a: 69fa ldr r2, [r7, #28]
8000f3c: 429a cmp r2, r3
8000f3e: d302 bcc.n 8000f46 <EE_PageTransfer+0xc2>
return EE_STATUS_NO_SPACE;
8000f40: 2303 movs r3, #3
8000f42: e01c b.n 8000f7e <EE_PageTransfer+0xfa>
continue;
8000f44: bf00 nop
for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++)
8000f46: 8b7b ldrh r3, [r7, #26]
8000f48: 3301 adds r3, #1
8000f4a: 837b strh r3, [r7, #26]
8000f4c: 8b7b ldrh r3, [r7, #26]
8000f4e: 2b1f cmp r3, #31
8000f50: d9bf bls.n 8000ed2 <EE_PageTransfer+0x4e>
}
/* Erase old page */
if (EE_FlashErasePage(oldBase) != HAL_OK)
8000f52: 6978 ldr r0, [r7, #20]
8000f54: f7ff fed5 bl 8000d02 <EE_FlashErasePage>
8000f58: 4603 mov r3, r0
8000f5a: 2b00 cmp r3, #0
8000f5c: d001 beq.n 8000f62 <EE_PageTransfer+0xde>
return EE_STATUS_ERROR;
8000f5e: 2301 movs r3, #1
8000f60: e00d b.n 8000f7e <EE_PageTransfer+0xfa>
/* Mark new page as VALID */
if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_VALID) != HAL_OK)
8000f62: f64a 21aa movw r1, #43690 @ 0xaaaa
8000f66: 6938 ldr r0, [r7, #16]
8000f68: f7ff feb0 bl 8000ccc <EE_FlashProgramHalfWord>
8000f6c: 4603 mov r3, r0
8000f6e: 2b00 cmp r3, #0
8000f70: d001 beq.n 8000f76 <EE_PageTransfer+0xf2>
return EE_STATUS_ERROR;
8000f72: 2301 movs r3, #1
8000f74: e003 b.n 8000f7e <EE_PageTransfer+0xfa>
/* Update active page */
EE_ActivePageBase = newBase;
8000f76: 4a04 ldr r2, [pc, #16] @ (8000f88 <EE_PageTransfer+0x104>)
8000f78: 693b ldr r3, [r7, #16]
8000f7a: 6013 str r3, [r2, #0]
return EE_STATUS_OK;
8000f7c: 2300 movs r3, #0
}
8000f7e: 4618 mov r0, r3
8000f80: 3720 adds r7, #32
8000f82: 46bd mov sp, r7
8000f84: bd80 pop {r7, pc}
8000f86: bf00 nop
8000f88: 20000000 .word 0x20000000
8000f8c: 0800bde4 .word 0x0800bde4
08000f90 <EE_Init>:
* - Checks page statuses and chooses the active page.
* - If inconsistent or blank, formats pages.
* PUBLIC RETURN TYPE: uint16_t (EE_OK / EE_ERROR / ...)
*/
uint16_t EE_Init(void)
{
8000f90: b580 push {r7, lr}
8000f92: b082 sub sp, #8
8000f94: af00 add r7, sp, #0
uint16_t status0 = EE_GetPageStatus(EE_PAGE0_BASE);
8000f96: 481e ldr r0, [pc, #120] @ (8001010 <EE_Init+0x80>)
8000f98: f7ff fe8c bl 8000cb4 <EE_GetPageStatus>
8000f9c: 4603 mov r3, r0
8000f9e: 80fb strh r3, [r7, #6]
uint16_t status1 = EE_GetPageStatus(EE_PAGE1_BASE);
8000fa0: 481c ldr r0, [pc, #112] @ (8001014 <EE_Init+0x84>)
8000fa2: f7ff fe87 bl 8000cb4 <EE_GetPageStatus>
8000fa6: 4603 mov r3, r0
8000fa8: 80bb strh r3, [r7, #4]
if ((status0 == EE_PAGE_STATUS_ERASED) && (status1 == EE_PAGE_STATUS_ERASED))
8000faa: 88fb ldrh r3, [r7, #6]
8000fac: f64f 72ff movw r2, #65535 @ 0xffff
8000fb0: 4293 cmp r3, r2
8000fb2: d108 bne.n 8000fc6 <EE_Init+0x36>
8000fb4: 88bb ldrh r3, [r7, #4]
8000fb6: f64f 72ff movw r2, #65535 @ 0xffff
8000fba: 4293 cmp r3, r2
8000fbc: d103 bne.n 8000fc6 <EE_Init+0x36>
{
/* Fresh device -> format */
return (uint16_t)EE_Format();
8000fbe: f7ff ff25 bl 8000e0c <EE_Format>
8000fc2: 4603 mov r3, r0
8000fc4: e020 b.n 8001008 <EE_Init+0x78>
}
else if ((status0 == EE_PAGE_STATUS_VALID) && (status1 == EE_PAGE_STATUS_ERASED))
8000fc6: 88fb ldrh r3, [r7, #6]
8000fc8: f64a 22aa movw r2, #43690 @ 0xaaaa
8000fcc: 4293 cmp r3, r2
8000fce: d109 bne.n 8000fe4 <EE_Init+0x54>
8000fd0: 88bb ldrh r3, [r7, #4]
8000fd2: f64f 72ff movw r2, #65535 @ 0xffff
8000fd6: 4293 cmp r3, r2
8000fd8: d104 bne.n 8000fe4 <EE_Init+0x54>
{
EE_ActivePageBase = EE_PAGE0_BASE;
8000fda: 4b0f ldr r3, [pc, #60] @ (8001018 <EE_Init+0x88>)
8000fdc: 4a0c ldr r2, [pc, #48] @ (8001010 <EE_Init+0x80>)
8000fde: 601a str r2, [r3, #0]
return EE_OK;
8000fe0: 2300 movs r3, #0
8000fe2: e011 b.n 8001008 <EE_Init+0x78>
}
else if ((status1 == EE_PAGE_STATUS_VALID) && (status0 == EE_PAGE_STATUS_ERASED))
8000fe4: 88bb ldrh r3, [r7, #4]
8000fe6: f64a 22aa movw r2, #43690 @ 0xaaaa
8000fea: 4293 cmp r3, r2
8000fec: d109 bne.n 8001002 <EE_Init+0x72>
8000fee: 88fb ldrh r3, [r7, #6]
8000ff0: f64f 72ff movw r2, #65535 @ 0xffff
8000ff4: 4293 cmp r3, r2
8000ff6: d104 bne.n 8001002 <EE_Init+0x72>
{
EE_ActivePageBase = EE_PAGE1_BASE;
8000ff8: 4b07 ldr r3, [pc, #28] @ (8001018 <EE_Init+0x88>)
8000ffa: 4a06 ldr r2, [pc, #24] @ (8001014 <EE_Init+0x84>)
8000ffc: 601a str r2, [r3, #0]
return EE_OK;
8000ffe: 2300 movs r3, #0
8001000: e002 b.n 8001008 <EE_Init+0x78>
}
else
{
/* Any weird or inconsistent state -> reformat */
return (uint16_t)EE_Format();
8001002: f7ff ff03 bl 8000e0c <EE_Format>
8001006: 4603 mov r3, r0
}
}
8001008: 4618 mov r0, r3
800100a: 3708 adds r7, #8
800100c: 46bd mov sp, r7
800100e: bd80 pop {r7, pc}
8001010: 0800f800 .word 0x0800f800
8001014: 0800fc00 .word 0x0800fc00
8001018: 20000000 .word 0x20000000
0800101c <EE_ReadVariable>:
/*
* Read a 16-bit variable by its virtual address.
* PUBLIC RETURN: EE_OK / EE_NOT_FOUND / EE_ERROR (as uint16_t)
*/
uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data)
{
800101c: b580 push {r7, lr}
800101e: b084 sub sp, #16
8001020: af00 add r7, sp, #0
8001022: 4603 mov r3, r0
8001024: 6039 str r1, [r7, #0]
8001026: 80fb strh r3, [r7, #6]
EE_Status st;
if (Data == NULL)
8001028: 683b ldr r3, [r7, #0]
800102a: 2b00 cmp r3, #0
800102c: d101 bne.n 8001032 <EE_ReadVariable+0x16>
return EE_ERROR;
800102e: 2301 movs r3, #1
8001030: e00a b.n 8001048 <EE_ReadVariable+0x2c>
st = EE_FindInPage(EE_ActivePageBase, VirtAddress, Data);
8001032: 4b07 ldr r3, [pc, #28] @ (8001050 <EE_ReadVariable+0x34>)
8001034: 681b ldr r3, [r3, #0]
8001036: 88f9 ldrh r1, [r7, #6]
8001038: 683a ldr r2, [r7, #0]
800103a: 4618 mov r0, r3
800103c: f7ff fea4 bl 8000d88 <EE_FindInPage>
8001040: 4603 mov r3, r0
8001042: 73fb strb r3, [r7, #15]
return (uint16_t)st;
8001044: 7bfb ldrb r3, [r7, #15]
8001046: b29b uxth r3, r3
}
8001048: 4618 mov r0, r3
800104a: 3710 adds r7, #16
800104c: 46bd mov sp, r7
800104e: bd80 pop {r7, pc}
8001050: 20000000 .word 0x20000000
08001054 <EE_WriteVariable>:
* - Writes a new record in the active page.
* - If the page is full, triggers a page transfer (GC).
* PUBLIC RETURN: EE_OK / EE_ERROR / EE_NO_SPACE (as uint16_t)
*/
uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data)
{
8001054: b580 push {r7, lr}
8001056: b084 sub sp, #16
8001058: af00 add r7, sp, #0
800105a: 4603 mov r3, r0
800105c: 460a mov r2, r1
800105e: 80fb strh r3, [r7, #6]
8001060: 4613 mov r3, r2
8001062: 80bb strh r3, [r7, #4]
uint32_t freeAddr;
EE_Status st;
/* Find free space in active page */
freeAddr = EE_FindFreeAddress(EE_ActivePageBase);
8001064: 4b17 ldr r3, [pc, #92] @ (80010c4 <EE_WriteVariable+0x70>)
8001066: 681b ldr r3, [r3, #0]
8001068: 4618 mov r0, r3
800106a: f7ff fe69 bl 8000d40 <EE_FindFreeAddress>
800106e: 60f8 str r0, [r7, #12]
if (freeAddr != 0U)
8001070: 68fb ldr r3, [r7, #12]
8001072: 2b00 cmp r3, #0
8001074: d017 beq.n 80010a6 <EE_WriteVariable+0x52>
{
/* Write new record */
if (EE_FlashProgramHalfWord(freeAddr, VirtAddress) != HAL_OK)
8001076: 88fb ldrh r3, [r7, #6]
8001078: 4619 mov r1, r3
800107a: 68f8 ldr r0, [r7, #12]
800107c: f7ff fe26 bl 8000ccc <EE_FlashProgramHalfWord>
8001080: 4603 mov r3, r0
8001082: 2b00 cmp r3, #0
8001084: d001 beq.n 800108a <EE_WriteVariable+0x36>
return EE_ERROR;
8001086: 2301 movs r3, #1
8001088: e017 b.n 80010ba <EE_WriteVariable+0x66>
if (EE_FlashProgramHalfWord(freeAddr + 2U, Data) != HAL_OK)
800108a: 68fb ldr r3, [r7, #12]
800108c: 3302 adds r3, #2
800108e: 88ba ldrh r2, [r7, #4]
8001090: 4611 mov r1, r2
8001092: 4618 mov r0, r3
8001094: f7ff fe1a bl 8000ccc <EE_FlashProgramHalfWord>
8001098: 4603 mov r3, r0
800109a: 2b00 cmp r3, #0
800109c: d001 beq.n 80010a2 <EE_WriteVariable+0x4e>
return EE_ERROR;
800109e: 2301 movs r3, #1
80010a0: e00b b.n 80010ba <EE_WriteVariable+0x66>
return EE_OK;
80010a2: 2300 movs r3, #0
80010a4: e009 b.n 80010ba <EE_WriteVariable+0x66>
}
/* No space -> page transfer */
st = EE_PageTransfer(VirtAddress, Data);
80010a6: 88ba ldrh r2, [r7, #4]
80010a8: 88fb ldrh r3, [r7, #6]
80010aa: 4611 mov r1, r2
80010ac: 4618 mov r0, r3
80010ae: f7ff fee9 bl 8000e84 <EE_PageTransfer>
80010b2: 4603 mov r3, r0
80010b4: 72fb strb r3, [r7, #11]
return (uint16_t)st;
80010b6: 7afb ldrb r3, [r7, #11]
80010b8: b29b uxth r3, r3
}
80010ba: 4618 mov r0, r3
80010bc: 3710 adds r7, #16
80010be: 46bd mov sp, r7
80010c0: bd80 pop {r7, pc}
80010c2: bf00 nop
80010c4: 20000000 .word 0x20000000
080010c8 <HAL_SYSTICK_Callback>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_SYSTICK_Callback(void){
80010c8: b580 push {r7, lr}
80010ca: af00 add r7, sp, #0
static uint8_t c100ms = 0;
static uint8_t c1s = 0;
static uint8_t inidx=0;
static uint8_t inbuf[4];
if (++c10ms >= 10) { // 10 ms
80010cc: 4b53 ldr r3, [pc, #332] @ (800121c <HAL_SYSTICK_Callback+0x154>)
80010ce: 781b ldrb r3, [r3, #0]
80010d0: 3301 adds r3, #1
80010d2: b2da uxtb r2, r3
80010d4: 4b51 ldr r3, [pc, #324] @ (800121c <HAL_SYSTICK_Callback+0x154>)
80010d6: 701a strb r2, [r3, #0]
80010d8: 4b50 ldr r3, [pc, #320] @ (800121c <HAL_SYSTICK_Callback+0x154>)
80010da: 781b ldrb r3, [r3, #0]
80010dc: 2b09 cmp r3, #9
80010de: f240 809b bls.w 8001218 <HAL_SYSTICK_Callback+0x150>
c10ms = 0;
80010e2: 4b4e ldr r3, [pc, #312] @ (800121c <HAL_SYSTICK_Callback+0x154>)
80010e4: 2200 movs r2, #0
80010e6: 701a strb r2, [r3, #0]
//**** legge i tasti********************************************************************************
inidx++;
80010e8: 4b4d ldr r3, [pc, #308] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
80010ea: 781b ldrb r3, [r3, #0]
80010ec: 3301 adds r3, #1
80010ee: b2da uxtb r2, r3
80010f0: 4b4b ldr r3, [pc, #300] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
80010f2: 701a strb r2, [r3, #0]
inidx&=0x03;
80010f4: 4b4a ldr r3, [pc, #296] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
80010f6: 781b ldrb r3, [r3, #0]
80010f8: f003 0303 and.w r3, r3, #3
80010fc: b2da uxtb r2, r3
80010fe: 4b48 ldr r3, [pc, #288] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
8001100: 701a strb r2, [r3, #0]
if(HAL_GPIO_ReadPin(P1_GPIO_Port, P1_Pin)==GPIO_PIN_SET)inbuf[inidx]|=INP1;else inbuf[inidx]&=(~INP1);
8001102: f44f 4180 mov.w r1, #16384 @ 0x4000
8001106: 4847 ldr r0, [pc, #284] @ (8001224 <HAL_SYSTICK_Callback+0x15c>)
8001108: f002 fac4 bl 8003694 <HAL_GPIO_ReadPin>
800110c: 4603 mov r3, r0
800110e: 2b01 cmp r3, #1
8001110: d10c bne.n 800112c <HAL_SYSTICK_Callback+0x64>
8001112: 4b43 ldr r3, [pc, #268] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
8001114: 781b ldrb r3, [r3, #0]
8001116: 461a mov r2, r3
8001118: 4b43 ldr r3, [pc, #268] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
800111a: 5c9b ldrb r3, [r3, r2]
800111c: 4a40 ldr r2, [pc, #256] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
800111e: 7812 ldrb r2, [r2, #0]
8001120: f043 0301 orr.w r3, r3, #1
8001124: b2d9 uxtb r1, r3
8001126: 4b40 ldr r3, [pc, #256] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001128: 5499 strb r1, [r3, r2]
800112a: e00b b.n 8001144 <HAL_SYSTICK_Callback+0x7c>
800112c: 4b3c ldr r3, [pc, #240] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
800112e: 781b ldrb r3, [r3, #0]
8001130: 461a mov r2, r3
8001132: 4b3d ldr r3, [pc, #244] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001134: 5c9b ldrb r3, [r3, r2]
8001136: 4a3a ldr r2, [pc, #232] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
8001138: 7812 ldrb r2, [r2, #0]
800113a: f023 0301 bic.w r3, r3, #1
800113e: b2d9 uxtb r1, r3
8001140: 4b39 ldr r3, [pc, #228] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001142: 5499 strb r1, [r3, r2]
if(HAL_GPIO_ReadPin(P2_GPIO_Port, P2_Pin)==GPIO_PIN_SET)inbuf[inidx]|=INP2;else inbuf[inidx]&=(~INP2);
8001144: f44f 4100 mov.w r1, #32768 @ 0x8000
8001148: 4836 ldr r0, [pc, #216] @ (8001224 <HAL_SYSTICK_Callback+0x15c>)
800114a: f002 faa3 bl 8003694 <HAL_GPIO_ReadPin>
800114e: 4603 mov r3, r0
8001150: 2b01 cmp r3, #1
8001152: d10c bne.n 800116e <HAL_SYSTICK_Callback+0xa6>
8001154: 4b32 ldr r3, [pc, #200] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
8001156: 781b ldrb r3, [r3, #0]
8001158: 461a mov r2, r3
800115a: 4b33 ldr r3, [pc, #204] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
800115c: 5c9b ldrb r3, [r3, r2]
800115e: 4a30 ldr r2, [pc, #192] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
8001160: 7812 ldrb r2, [r2, #0]
8001162: f043 0302 orr.w r3, r3, #2
8001166: b2d9 uxtb r1, r3
8001168: 4b2f ldr r3, [pc, #188] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
800116a: 5499 strb r1, [r3, r2]
800116c: e00b b.n 8001186 <HAL_SYSTICK_Callback+0xbe>
800116e: 4b2c ldr r3, [pc, #176] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
8001170: 781b ldrb r3, [r3, #0]
8001172: 461a mov r2, r3
8001174: 4b2c ldr r3, [pc, #176] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001176: 5c9b ldrb r3, [r3, r2]
8001178: 4a29 ldr r2, [pc, #164] @ (8001220 <HAL_SYSTICK_Callback+0x158>)
800117a: 7812 ldrb r2, [r2, #0]
800117c: f023 0302 bic.w r3, r3, #2
8001180: b2d9 uxtb r1, r3
8001182: 4b29 ldr r3, [pc, #164] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001184: 5499 strb r1, [r3, r2]
pulsanti|=(inbuf[0]&inbuf[1]&inbuf[2]&inbuf[3]);
8001186: 4b28 ldr r3, [pc, #160] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001188: 781a ldrb r2, [r3, #0]
800118a: 4b27 ldr r3, [pc, #156] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
800118c: 785b ldrb r3, [r3, #1]
800118e: 4013 ands r3, r2
8001190: b2da uxtb r2, r3
8001192: 4b25 ldr r3, [pc, #148] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
8001194: 789b ldrb r3, [r3, #2]
8001196: 4013 ands r3, r2
8001198: b2da uxtb r2, r3
800119a: 4b23 ldr r3, [pc, #140] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
800119c: 78db ldrb r3, [r3, #3]
800119e: 4013 ands r3, r2
80011a0: b2da uxtb r2, r3
80011a2: 4b22 ldr r3, [pc, #136] @ (800122c <HAL_SYSTICK_Callback+0x164>)
80011a4: 781b ldrb r3, [r3, #0]
80011a6: 4313 orrs r3, r2
80011a8: b2da uxtb r2, r3
80011aa: 4b20 ldr r3, [pc, #128] @ (800122c <HAL_SYSTICK_Callback+0x164>)
80011ac: 701a strb r2, [r3, #0]
pulsanti&=(inbuf[0]|inbuf[1]|inbuf[2]|inbuf[3]);
80011ae: 4b1e ldr r3, [pc, #120] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
80011b0: 781a ldrb r2, [r3, #0]
80011b2: 4b1d ldr r3, [pc, #116] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
80011b4: 785b ldrb r3, [r3, #1]
80011b6: 4313 orrs r3, r2
80011b8: b2da uxtb r2, r3
80011ba: 4b1b ldr r3, [pc, #108] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
80011bc: 789b ldrb r3, [r3, #2]
80011be: 4313 orrs r3, r2
80011c0: b2da uxtb r2, r3
80011c2: 4b19 ldr r3, [pc, #100] @ (8001228 <HAL_SYSTICK_Callback+0x160>)
80011c4: 78db ldrb r3, [r3, #3]
80011c6: 4313 orrs r3, r2
80011c8: b2da uxtb r2, r3
80011ca: 4b18 ldr r3, [pc, #96] @ (800122c <HAL_SYSTICK_Callback+0x164>)
80011cc: 781b ldrb r3, [r3, #0]
80011ce: 4013 ands r3, r2
80011d0: b2da uxtb r2, r3
80011d2: 4b16 ldr r3, [pc, #88] @ (800122c <HAL_SYSTICK_Callback+0x164>)
80011d4: 701a strb r2, [r3, #0]
//**** legge adc ***********************************************************************************
readAdc();
80011d6: f7fe fff7 bl 80001c8 <readAdc>
if (++c100ms >= 10) { // 10 ms
80011da: 4b15 ldr r3, [pc, #84] @ (8001230 <HAL_SYSTICK_Callback+0x168>)
80011dc: 781b ldrb r3, [r3, #0]
80011de: 3301 adds r3, #1
80011e0: b2da uxtb r2, r3
80011e2: 4b13 ldr r3, [pc, #76] @ (8001230 <HAL_SYSTICK_Callback+0x168>)
80011e4: 701a strb r2, [r3, #0]
80011e6: 4b12 ldr r3, [pc, #72] @ (8001230 <HAL_SYSTICK_Callback+0x168>)
80011e8: 781b ldrb r3, [r3, #0]
80011ea: 2b09 cmp r3, #9
80011ec: d914 bls.n 8001218 <HAL_SYSTICK_Callback+0x150>
c100ms = 0; //flag_10ms = 1; // set a flag; do real work in main loop
80011ee: 4b10 ldr r3, [pc, #64] @ (8001230 <HAL_SYSTICK_Callback+0x168>)
80011f0: 2200 movs r2, #0
80011f2: 701a strb r2, [r3, #0]
if (++c1s >= 10) { // 10 ms
80011f4: 4b0f ldr r3, [pc, #60] @ (8001234 <HAL_SYSTICK_Callback+0x16c>)
80011f6: 781b ldrb r3, [r3, #0]
80011f8: 3301 adds r3, #1
80011fa: b2da uxtb r2, r3
80011fc: 4b0d ldr r3, [pc, #52] @ (8001234 <HAL_SYSTICK_Callback+0x16c>)
80011fe: 701a strb r2, [r3, #0]
8001200: 4b0c ldr r3, [pc, #48] @ (8001234 <HAL_SYSTICK_Callback+0x16c>)
8001202: 781b ldrb r3, [r3, #0]
8001204: 2b09 cmp r3, #9
8001206: d907 bls.n 8001218 <HAL_SYSTICK_Callback+0x150>
c1s = 0;
8001208: 4b0a ldr r3, [pc, #40] @ (8001234 <HAL_SYSTICK_Callback+0x16c>)
800120a: 2200 movs r2, #0
800120c: 701a strb r2, [r3, #0]
HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
800120e: f44f 5100 mov.w r1, #8192 @ 0x2000
8001212: 4804 ldr r0, [pc, #16] @ (8001224 <HAL_SYSTICK_Callback+0x15c>)
8001214: f002 fa6d bl 80036f2 <HAL_GPIO_TogglePin>
}
}
}
}
8001218: bf00 nop
800121a: bd80 pop {r7, pc}
800121c: 200003d9 .word 0x200003d9
8001220: 200003da .word 0x200003da
8001224: 40011000 .word 0x40011000
8001228: 200003dc .word 0x200003dc
800122c: 200003d8 .word 0x200003d8
8001230: 200003e0 .word 0x200003e0
8001234: 200003e1 .word 0x200003e1
08001238 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8001238: b580 push {r7, lr}
800123a: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800123c: f000 ff76 bl 800212c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8001240: f000 f852 bl 80012e8 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8001244: f000 fab4 bl 80017b0 <MX_GPIO_Init>
MX_DMA_Init();
8001248: f000 fa94 bl 8001774 <MX_DMA_Init>
MX_USB_DEVICE_Init();
800124c: f009 fade bl 800a80c <MX_USB_DEVICE_Init>
MX_TIM2_Init();
8001250: f000 f920 bl 8001494 <MX_TIM2_Init>
MX_TIM4_Init();
8001254: f000 f9c2 bl 80015dc <MX_TIM4_Init>
MX_ADC1_Init();
8001258: f000 f8a4 bl 80013a4 <MX_ADC1_Init>
MX_USART1_UART_Init();
800125c: f000 fa60 bl 8001720 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_buf, ADC_NUM_CHANNELS);
8001260: 2205 movs r2, #5
8001262: 491c ldr r1, [pc, #112] @ (80012d4 <main+0x9c>)
8001264: 481c ldr r0, [pc, #112] @ (80012d8 <main+0xa0>)
8001266: f001 f89b bl 80023a0 <HAL_ADC_Start_DMA>
StopMot(timMot1,FWMot1);
800126a: 2100 movs r1, #0
800126c: 481b ldr r0, [pc, #108] @ (80012dc <main+0xa4>)
800126e: f000 fb64 bl 800193a <StopMot>
StopMot(timMot1,BWMot1);
8001272: 2104 movs r1, #4
8001274: 4819 ldr r0, [pc, #100] @ (80012dc <main+0xa4>)
8001276: f000 fb60 bl 800193a <StopMot>
StopMot(timMot2,FWMot2);
800127a: 2108 movs r1, #8
800127c: 4817 ldr r0, [pc, #92] @ (80012dc <main+0xa4>)
800127e: f000 fb5c bl 800193a <StopMot>
StopMot(timMot2,BWMot2);
8001282: 210c movs r1, #12
8001284: 4815 ldr r0, [pc, #84] @ (80012dc <main+0xa4>)
8001286: f000 fb58 bl 800193a <StopMot>
StopMot(timMot3,FWMot3);
800128a: 2100 movs r1, #0
800128c: 4814 ldr r0, [pc, #80] @ (80012e0 <main+0xa8>)
800128e: f000 fb54 bl 800193a <StopMot>
StopMot(timMot3,BWMot3);
8001292: 2104 movs r1, #4
8001294: 4812 ldr r0, [pc, #72] @ (80012e0 <main+0xa8>)
8001296: f000 fb50 bl 800193a <StopMot>
StopMot(timMot4,FWMot4);
800129a: 2108 movs r1, #8
800129c: 4810 ldr r0, [pc, #64] @ (80012e0 <main+0xa8>)
800129e: f000 fb4c bl 800193a <StopMot>
StopMot(timMot4,BWMot4);
80012a2: 210c movs r1, #12
80012a4: 480e ldr r0, [pc, #56] @ (80012e0 <main+0xa8>)
80012a6: f000 fb48 bl 800193a <StopMot>
//CDC_Transmit_FS((uint8_t*)"Start\r\n", 7);
while (CDC_Transmit_FS((uint8_t*)"Start\r\n", 7) == USBD_BUSY);
80012aa: bf00 nop
80012ac: 2107 movs r1, #7
80012ae: 480d ldr r0, [pc, #52] @ (80012e4 <main+0xac>)
80012b0: f009 fbe8 bl 800aa84 <CDC_Transmit_FS>
80012b4: 4603 mov r3, r0
80012b6: 2b01 cmp r3, #1
80012b8: d0f8 beq.n 80012ac <main+0x74>
if (EE_Init() != EE_OK){
80012ba: f7ff fe69 bl 8000f90 <EE_Init>
80012be: 4603 mov r3, r0
80012c0: 2b00 cmp r3, #0
80012c2: d001 beq.n 80012c8 <main+0x90>
for(;;);//errore eeprom
80012c4: bf00 nop
80012c6: e7fd b.n 80012c4 <main+0x8c>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1){
manageCDC();
80012c8: f7ff f898 bl 80003fc <manageCDC>
manageAdc();
80012cc: f7fe ff46 bl 800015c <manageAdc>
manageCDC();
80012d0: e7fa b.n 80012c8 <main+0x90>
80012d2: bf00 nop
80012d4: 200001ec .word 0x200001ec
80012d8: 2000028c .word 0x2000028c
80012dc: 20000300 .word 0x20000300
80012e0: 20000348 .word 0x20000348
80012e4: 0800bd94 .word 0x0800bd94
080012e8 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80012e8: b580 push {r7, lr}
80012ea: b094 sub sp, #80 @ 0x50
80012ec: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80012ee: f107 0328 add.w r3, r7, #40 @ 0x28
80012f2: 2228 movs r2, #40 @ 0x28
80012f4: 2100 movs r1, #0
80012f6: 4618 mov r0, r3
80012f8: f009 ffc4 bl 800b284 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80012fc: f107 0314 add.w r3, r7, #20
8001300: 2200 movs r2, #0
8001302: 601a str r2, [r3, #0]
8001304: 605a str r2, [r3, #4]
8001306: 609a str r2, [r3, #8]
8001308: 60da str r2, [r3, #12]
800130a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800130c: 1d3b adds r3, r7, #4
800130e: 2200 movs r2, #0
8001310: 601a str r2, [r3, #0]
8001312: 605a str r2, [r3, #4]
8001314: 609a str r2, [r3, #8]
8001316: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8001318: 2301 movs r3, #1
800131a: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
800131c: f44f 3380 mov.w r3, #65536 @ 0x10000
8001320: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
8001322: 2300 movs r3, #0
8001324: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8001326: 2301 movs r3, #1
8001328: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800132a: 2302 movs r3, #2
800132c: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
800132e: f44f 3380 mov.w r3, #65536 @ 0x10000
8001332: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
8001334: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000
8001338: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800133a: f107 0328 add.w r3, r7, #40 @ 0x28
800133e: 4618 mov r0, r3
8001340: f003 ff50 bl 80051e4 <HAL_RCC_OscConfig>
8001344: 4603 mov r3, r0
8001346: 2b00 cmp r3, #0
8001348: d001 beq.n 800134e <SystemClock_Config+0x66>
{
Error_Handler();
800134a: f000 fadb bl 8001904 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800134e: 230f movs r3, #15
8001350: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8001352: 2302 movs r3, #2
8001354: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8001356: 2300 movs r3, #0
8001358: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
800135a: f44f 6380 mov.w r3, #1024 @ 0x400
800135e: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8001360: 2300 movs r3, #0
8001362: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
8001364: f107 0314 add.w r3, r7, #20
8001368: 2102 movs r1, #2
800136a: 4618 mov r0, r3
800136c: f004 f9bc bl 80056e8 <HAL_RCC_ClockConfig>
8001370: 4603 mov r3, r0
8001372: 2b00 cmp r3, #0
8001374: d001 beq.n 800137a <SystemClock_Config+0x92>
{
Error_Handler();
8001376: f000 fac5 bl 8001904 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
800137a: 2312 movs r3, #18
800137c: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
800137e: f44f 4300 mov.w r3, #32768 @ 0x8000
8001382: 60fb str r3, [r7, #12]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
8001384: 2300 movs r3, #0
8001386: 613b str r3, [r7, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001388: 1d3b adds r3, r7, #4
800138a: 4618 mov r0, r3
800138c: f004 fb3a bl 8005a04 <HAL_RCCEx_PeriphCLKConfig>
8001390: 4603 mov r3, r0
8001392: 2b00 cmp r3, #0
8001394: d001 beq.n 800139a <SystemClock_Config+0xb2>
{
Error_Handler();
8001396: f000 fab5 bl 8001904 <Error_Handler>
}
}
800139a: bf00 nop
800139c: 3750 adds r7, #80 @ 0x50
800139e: 46bd mov sp, r7
80013a0: bd80 pop {r7, pc}
...
080013a4 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
80013a4: b580 push {r7, lr}
80013a6: b084 sub sp, #16
80013a8: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80013aa: 1d3b adds r3, r7, #4
80013ac: 2200 movs r2, #0
80013ae: 601a str r2, [r3, #0]
80013b0: 605a str r2, [r3, #4]
80013b2: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
80013b4: 4b35 ldr r3, [pc, #212] @ (800148c <MX_ADC1_Init+0xe8>)
80013b6: 4a36 ldr r2, [pc, #216] @ (8001490 <MX_ADC1_Init+0xec>)
80013b8: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
80013ba: 4b34 ldr r3, [pc, #208] @ (800148c <MX_ADC1_Init+0xe8>)
80013bc: f44f 7280 mov.w r2, #256 @ 0x100
80013c0: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
80013c2: 4b32 ldr r3, [pc, #200] @ (800148c <MX_ADC1_Init+0xe8>)
80013c4: 2201 movs r2, #1
80013c6: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
80013c8: 4b30 ldr r3, [pc, #192] @ (800148c <MX_ADC1_Init+0xe8>)
80013ca: 2200 movs r2, #0
80013cc: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80013ce: 4b2f ldr r3, [pc, #188] @ (800148c <MX_ADC1_Init+0xe8>)
80013d0: f44f 2260 mov.w r2, #917504 @ 0xe0000
80013d4: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80013d6: 4b2d ldr r3, [pc, #180] @ (800148c <MX_ADC1_Init+0xe8>)
80013d8: 2200 movs r2, #0
80013da: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 5;
80013dc: 4b2b ldr r3, [pc, #172] @ (800148c <MX_ADC1_Init+0xe8>)
80013de: 2205 movs r2, #5
80013e0: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80013e2: 482a ldr r0, [pc, #168] @ (800148c <MX_ADC1_Init+0xe8>)
80013e4: f000 ff04 bl 80021f0 <HAL_ADC_Init>
80013e8: 4603 mov r3, r0
80013ea: 2b00 cmp r3, #0
80013ec: d001 beq.n 80013f2 <MX_ADC1_Init+0x4e>
{
Error_Handler();
80013ee: f000 fa89 bl 8001904 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
80013f2: 2304 movs r3, #4
80013f4: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80013f6: 2301 movs r3, #1
80013f8: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_28CYCLES_5;
80013fa: 2303 movs r3, #3
80013fc: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80013fe: 1d3b adds r3, r7, #4
8001400: 4619 mov r1, r3
8001402: 4822 ldr r0, [pc, #136] @ (800148c <MX_ADC1_Init+0xe8>)
8001404: f001 f8c6 bl 8002594 <HAL_ADC_ConfigChannel>
8001408: 4603 mov r3, r0
800140a: 2b00 cmp r3, #0
800140c: d001 beq.n 8001412 <MX_ADC1_Init+0x6e>
{
Error_Handler();
800140e: f000 fa79 bl 8001904 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
8001412: 2305 movs r3, #5
8001414: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_2;
8001416: 2302 movs r3, #2
8001418: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
800141a: 1d3b adds r3, r7, #4
800141c: 4619 mov r1, r3
800141e: 481b ldr r0, [pc, #108] @ (800148c <MX_ADC1_Init+0xe8>)
8001420: f001 f8b8 bl 8002594 <HAL_ADC_ConfigChannel>
8001424: 4603 mov r3, r0
8001426: 2b00 cmp r3, #0
8001428: d001 beq.n 800142e <MX_ADC1_Init+0x8a>
{
Error_Handler();
800142a: f000 fa6b bl 8001904 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_6;
800142e: 2306 movs r3, #6
8001430: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_3;
8001432: 2303 movs r3, #3
8001434: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001436: 1d3b adds r3, r7, #4
8001438: 4619 mov r1, r3
800143a: 4814 ldr r0, [pc, #80] @ (800148c <MX_ADC1_Init+0xe8>)
800143c: f001 f8aa bl 8002594 <HAL_ADC_ConfigChannel>
8001440: 4603 mov r3, r0
8001442: 2b00 cmp r3, #0
8001444: d001 beq.n 800144a <MX_ADC1_Init+0xa6>
{
Error_Handler();
8001446: f000 fa5d bl 8001904 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_7;
800144a: 2307 movs r3, #7
800144c: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_4;
800144e: 2304 movs r3, #4
8001450: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001452: 1d3b adds r3, r7, #4
8001454: 4619 mov r1, r3
8001456: 480d ldr r0, [pc, #52] @ (800148c <MX_ADC1_Init+0xe8>)
8001458: f001 f89c bl 8002594 <HAL_ADC_ConfigChannel>
800145c: 4603 mov r3, r0
800145e: 2b00 cmp r3, #0
8001460: d001 beq.n 8001466 <MX_ADC1_Init+0xc2>
{
Error_Handler();
8001462: f000 fa4f bl 8001904 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_8;
8001466: 2308 movs r3, #8
8001468: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_5;
800146a: 2305 movs r3, #5
800146c: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
800146e: 1d3b adds r3, r7, #4
8001470: 4619 mov r1, r3
8001472: 4806 ldr r0, [pc, #24] @ (800148c <MX_ADC1_Init+0xe8>)
8001474: f001 f88e bl 8002594 <HAL_ADC_ConfigChannel>
8001478: 4603 mov r3, r0
800147a: 2b00 cmp r3, #0
800147c: d001 beq.n 8001482 <MX_ADC1_Init+0xde>
{
Error_Handler();
800147e: f000 fa41 bl 8001904 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8001482: bf00 nop
8001484: 3710 adds r7, #16
8001486: 46bd mov sp, r7
8001488: bd80 pop {r7, pc}
800148a: bf00 nop
800148c: 2000028c .word 0x2000028c
8001490: 40012400 .word 0x40012400
08001494 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8001494: b580 push {r7, lr}
8001496: b08e sub sp, #56 @ 0x38
8001498: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800149a: f107 0328 add.w r3, r7, #40 @ 0x28
800149e: 2200 movs r2, #0
80014a0: 601a str r2, [r3, #0]
80014a2: 605a str r2, [r3, #4]
80014a4: 609a str r2, [r3, #8]
80014a6: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80014a8: f107 0320 add.w r3, r7, #32
80014ac: 2200 movs r2, #0
80014ae: 601a str r2, [r3, #0]
80014b0: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80014b2: 1d3b adds r3, r7, #4
80014b4: 2200 movs r2, #0
80014b6: 601a str r2, [r3, #0]
80014b8: 605a str r2, [r3, #4]
80014ba: 609a str r2, [r3, #8]
80014bc: 60da str r2, [r3, #12]
80014be: 611a str r2, [r3, #16]
80014c0: 615a str r2, [r3, #20]
80014c2: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
80014c4: 4b44 ldr r3, [pc, #272] @ (80015d8 <MX_TIM2_Init+0x144>)
80014c6: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
80014ca: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80014cc: 4b42 ldr r3, [pc, #264] @ (80015d8 <MX_TIM2_Init+0x144>)
80014ce: 2200 movs r2, #0
80014d0: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
80014d2: 4b41 ldr r3, [pc, #260] @ (80015d8 <MX_TIM2_Init+0x144>)
80014d4: 2200 movs r2, #0
80014d6: 609a str r2, [r3, #8]
htim2.Init.Period = 17999;
80014d8: 4b3f ldr r3, [pc, #252] @ (80015d8 <MX_TIM2_Init+0x144>)
80014da: f244 624f movw r2, #17999 @ 0x464f
80014de: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80014e0: 4b3d ldr r3, [pc, #244] @ (80015d8 <MX_TIM2_Init+0x144>)
80014e2: 2200 movs r2, #0
80014e4: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80014e6: 4b3c ldr r3, [pc, #240] @ (80015d8 <MX_TIM2_Init+0x144>)
80014e8: 2200 movs r2, #0
80014ea: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
80014ec: 483a ldr r0, [pc, #232] @ (80015d8 <MX_TIM2_Init+0x144>)
80014ee: f004 fb3f bl 8005b70 <HAL_TIM_Base_Init>
80014f2: 4603 mov r3, r0
80014f4: 2b00 cmp r3, #0
80014f6: d001 beq.n 80014fc <MX_TIM2_Init+0x68>
{
Error_Handler();
80014f8: f000 fa04 bl 8001904 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80014fc: f44f 5380 mov.w r3, #4096 @ 0x1000
8001500: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8001502: f107 0328 add.w r3, r7, #40 @ 0x28
8001506: 4619 mov r1, r3
8001508: 4833 ldr r0, [pc, #204] @ (80015d8 <MX_TIM2_Init+0x144>)
800150a: f004 fda1 bl 8006050 <HAL_TIM_ConfigClockSource>
800150e: 4603 mov r3, r0
8001510: 2b00 cmp r3, #0
8001512: d001 beq.n 8001518 <MX_TIM2_Init+0x84>
{
Error_Handler();
8001514: f000 f9f6 bl 8001904 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8001518: 482f ldr r0, [pc, #188] @ (80015d8 <MX_TIM2_Init+0x144>)
800151a: f004 fb78 bl 8005c0e <HAL_TIM_PWM_Init>
800151e: 4603 mov r3, r0
8001520: 2b00 cmp r3, #0
8001522: d001 beq.n 8001528 <MX_TIM2_Init+0x94>
{
Error_Handler();
8001524: f000 f9ee bl 8001904 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001528: 2300 movs r3, #0
800152a: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800152c: 2300 movs r3, #0
800152e: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8001530: f107 0320 add.w r3, r7, #32
8001534: 4619 mov r1, r3
8001536: 4828 ldr r0, [pc, #160] @ (80015d8 <MX_TIM2_Init+0x144>)
8001538: f005 f92a bl 8006790 <HAL_TIMEx_MasterConfigSynchronization>
800153c: 4603 mov r3, r0
800153e: 2b00 cmp r3, #0
8001540: d001 beq.n 8001546 <MX_TIM2_Init+0xb2>
{
Error_Handler();
8001542: f000 f9df bl 8001904 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001546: 2360 movs r3, #96 @ 0x60
8001548: 607b str r3, [r7, #4]
sConfigOC.Pulse = 1000;
800154a: f44f 737a mov.w r3, #1000 @ 0x3e8
800154e: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001550: 2300 movs r3, #0
8001552: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8001554: 2304 movs r3, #4
8001556: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001558: 1d3b adds r3, r7, #4
800155a: 2200 movs r2, #0
800155c: 4619 mov r1, r3
800155e: 481e ldr r0, [pc, #120] @ (80015d8 <MX_TIM2_Init+0x144>)
8001560: f004 fcb4 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
8001564: 4603 mov r3, r0
8001566: 2b00 cmp r3, #0
8001568: d001 beq.n 800156e <MX_TIM2_Init+0xda>
{
Error_Handler();
800156a: f000 f9cb bl 8001904 <Error_Handler>
}
sConfigOC.Pulse = 2000;
800156e: f44f 63fa mov.w r3, #2000 @ 0x7d0
8001572: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8001574: 1d3b adds r3, r7, #4
8001576: 2204 movs r2, #4
8001578: 4619 mov r1, r3
800157a: 4817 ldr r0, [pc, #92] @ (80015d8 <MX_TIM2_Init+0x144>)
800157c: f004 fca6 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
8001580: 4603 mov r3, r0
8001582: 2b00 cmp r3, #0
8001584: d001 beq.n 800158a <MX_TIM2_Init+0xf6>
{
Error_Handler();
8001586: f000 f9bd bl 8001904 <Error_Handler>
}
sConfigOC.Pulse = 3000;
800158a: f640 33b8 movw r3, #3000 @ 0xbb8
800158e: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001590: 2300 movs r3, #0
8001592: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8001594: 1d3b adds r3, r7, #4
8001596: 2208 movs r2, #8
8001598: 4619 mov r1, r3
800159a: 480f ldr r0, [pc, #60] @ (80015d8 <MX_TIM2_Init+0x144>)
800159c: f004 fc96 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
80015a0: 4603 mov r3, r0
80015a2: 2b00 cmp r3, #0
80015a4: d001 beq.n 80015aa <MX_TIM2_Init+0x116>
{
Error_Handler();
80015a6: f000 f9ad bl 8001904 <Error_Handler>
}
sConfigOC.Pulse = 4000;
80015aa: f44f 637a mov.w r3, #4000 @ 0xfa0
80015ae: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
80015b0: 2304 movs r3, #4
80015b2: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
80015b4: 1d3b adds r3, r7, #4
80015b6: 220c movs r2, #12
80015b8: 4619 mov r1, r3
80015ba: 4807 ldr r0, [pc, #28] @ (80015d8 <MX_TIM2_Init+0x144>)
80015bc: f004 fc86 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
80015c0: 4603 mov r3, r0
80015c2: 2b00 cmp r3, #0
80015c4: d001 beq.n 80015ca <MX_TIM2_Init+0x136>
{
Error_Handler();
80015c6: f000 f99d bl 8001904 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
80015ca: 4803 ldr r0, [pc, #12] @ (80015d8 <MX_TIM2_Init+0x144>)
80015cc: f000 fc6a bl 8001ea4 <HAL_TIM_MspPostInit>
}
80015d0: bf00 nop
80015d2: 3738 adds r7, #56 @ 0x38
80015d4: 46bd mov sp, r7
80015d6: bd80 pop {r7, pc}
80015d8: 20000300 .word 0x20000300
080015dc <MX_TIM4_Init>:
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
80015dc: b580 push {r7, lr}
80015de: b08e sub sp, #56 @ 0x38
80015e0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80015e2: f107 0328 add.w r3, r7, #40 @ 0x28
80015e6: 2200 movs r2, #0
80015e8: 601a str r2, [r3, #0]
80015ea: 605a str r2, [r3, #4]
80015ec: 609a str r2, [r3, #8]
80015ee: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80015f0: f107 0320 add.w r3, r7, #32
80015f4: 2200 movs r2, #0
80015f6: 601a str r2, [r3, #0]
80015f8: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80015fa: 1d3b adds r3, r7, #4
80015fc: 2200 movs r2, #0
80015fe: 601a str r2, [r3, #0]
8001600: 605a str r2, [r3, #4]
8001602: 609a str r2, [r3, #8]
8001604: 60da str r2, [r3, #12]
8001606: 611a str r2, [r3, #16]
8001608: 615a str r2, [r3, #20]
800160a: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
800160c: 4b42 ldr r3, [pc, #264] @ (8001718 <MX_TIM4_Init+0x13c>)
800160e: 4a43 ldr r2, [pc, #268] @ (800171c <MX_TIM4_Init+0x140>)
8001610: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 0;
8001612: 4b41 ldr r3, [pc, #260] @ (8001718 <MX_TIM4_Init+0x13c>)
8001614: 2200 movs r2, #0
8001616: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
8001618: 4b3f ldr r3, [pc, #252] @ (8001718 <MX_TIM4_Init+0x13c>)
800161a: 2200 movs r2, #0
800161c: 609a str r2, [r3, #8]
htim4.Init.Period = 17999;
800161e: 4b3e ldr r3, [pc, #248] @ (8001718 <MX_TIM4_Init+0x13c>)
8001620: f244 624f movw r2, #17999 @ 0x464f
8001624: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001626: 4b3c ldr r3, [pc, #240] @ (8001718 <MX_TIM4_Init+0x13c>)
8001628: 2200 movs r2, #0
800162a: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800162c: 4b3a ldr r3, [pc, #232] @ (8001718 <MX_TIM4_Init+0x13c>)
800162e: 2200 movs r2, #0
8001630: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
8001632: 4839 ldr r0, [pc, #228] @ (8001718 <MX_TIM4_Init+0x13c>)
8001634: f004 fa9c bl 8005b70 <HAL_TIM_Base_Init>
8001638: 4603 mov r3, r0
800163a: 2b00 cmp r3, #0
800163c: d001 beq.n 8001642 <MX_TIM4_Init+0x66>
{
Error_Handler();
800163e: f000 f961 bl 8001904 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001642: f44f 5380 mov.w r3, #4096 @ 0x1000
8001646: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
8001648: f107 0328 add.w r3, r7, #40 @ 0x28
800164c: 4619 mov r1, r3
800164e: 4832 ldr r0, [pc, #200] @ (8001718 <MX_TIM4_Init+0x13c>)
8001650: f004 fcfe bl 8006050 <HAL_TIM_ConfigClockSource>
8001654: 4603 mov r3, r0
8001656: 2b00 cmp r3, #0
8001658: d001 beq.n 800165e <MX_TIM4_Init+0x82>
{
Error_Handler();
800165a: f000 f953 bl 8001904 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
800165e: 482e ldr r0, [pc, #184] @ (8001718 <MX_TIM4_Init+0x13c>)
8001660: f004 fad5 bl 8005c0e <HAL_TIM_PWM_Init>
8001664: 4603 mov r3, r0
8001666: 2b00 cmp r3, #0
8001668: d001 beq.n 800166e <MX_TIM4_Init+0x92>
{
Error_Handler();
800166a: f000 f94b bl 8001904 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800166e: 2300 movs r3, #0
8001670: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001672: 2300 movs r3, #0
8001674: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
8001676: f107 0320 add.w r3, r7, #32
800167a: 4619 mov r1, r3
800167c: 4826 ldr r0, [pc, #152] @ (8001718 <MX_TIM4_Init+0x13c>)
800167e: f005 f887 bl 8006790 <HAL_TIMEx_MasterConfigSynchronization>
8001682: 4603 mov r3, r0
8001684: 2b00 cmp r3, #0
8001686: d001 beq.n 800168c <MX_TIM4_Init+0xb0>
{
Error_Handler();
8001688: f000 f93c bl 8001904 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800168c: 2360 movs r3, #96 @ 0x60
800168e: 607b str r3, [r7, #4]
sConfigOC.Pulse = 5000;
8001690: f241 3388 movw r3, #5000 @ 0x1388
8001694: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001696: 2300 movs r3, #0
8001698: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
800169a: 2304 movs r3, #4
800169c: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800169e: 1d3b adds r3, r7, #4
80016a0: 2200 movs r2, #0
80016a2: 4619 mov r1, r3
80016a4: 481c ldr r0, [pc, #112] @ (8001718 <MX_TIM4_Init+0x13c>)
80016a6: f004 fc11 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
80016aa: 4603 mov r3, r0
80016ac: 2b00 cmp r3, #0
80016ae: d001 beq.n 80016b4 <MX_TIM4_Init+0xd8>
{
Error_Handler();
80016b0: f000 f928 bl 8001904 <Error_Handler>
}
sConfigOC.Pulse = 6000;
80016b4: f241 7370 movw r3, #6000 @ 0x1770
80016b8: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80016ba: 1d3b adds r3, r7, #4
80016bc: 2204 movs r2, #4
80016be: 4619 mov r1, r3
80016c0: 4815 ldr r0, [pc, #84] @ (8001718 <MX_TIM4_Init+0x13c>)
80016c2: f004 fc03 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
80016c6: 4603 mov r3, r0
80016c8: 2b00 cmp r3, #0
80016ca: d001 beq.n 80016d0 <MX_TIM4_Init+0xf4>
{
Error_Handler();
80016cc: f000 f91a bl 8001904 <Error_Handler>
}
sConfigOC.Pulse = 7000;
80016d0: f641 3358 movw r3, #7000 @ 0x1b58
80016d4: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80016d6: 1d3b adds r3, r7, #4
80016d8: 2208 movs r2, #8
80016da: 4619 mov r1, r3
80016dc: 480e ldr r0, [pc, #56] @ (8001718 <MX_TIM4_Init+0x13c>)
80016de: f004 fbf5 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
80016e2: 4603 mov r3, r0
80016e4: 2b00 cmp r3, #0
80016e6: d001 beq.n 80016ec <MX_TIM4_Init+0x110>
{
Error_Handler();
80016e8: f000 f90c bl 8001904 <Error_Handler>
}
sConfigOC.Pulse = 8000;
80016ec: f44f 53fa mov.w r3, #8000 @ 0x1f40
80016f0: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
80016f2: 1d3b adds r3, r7, #4
80016f4: 220c movs r2, #12
80016f6: 4619 mov r1, r3
80016f8: 4807 ldr r0, [pc, #28] @ (8001718 <MX_TIM4_Init+0x13c>)
80016fa: f004 fbe7 bl 8005ecc <HAL_TIM_PWM_ConfigChannel>
80016fe: 4603 mov r3, r0
8001700: 2b00 cmp r3, #0
8001702: d001 beq.n 8001708 <MX_TIM4_Init+0x12c>
{
Error_Handler();
8001704: f000 f8fe bl 8001904 <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
8001708: 4803 ldr r0, [pc, #12] @ (8001718 <MX_TIM4_Init+0x13c>)
800170a: f000 fbcb bl 8001ea4 <HAL_TIM_MspPostInit>
}
800170e: bf00 nop
8001710: 3738 adds r7, #56 @ 0x38
8001712: 46bd mov sp, r7
8001714: bd80 pop {r7, pc}
8001716: bf00 nop
8001718: 20000348 .word 0x20000348
800171c: 40000800 .word 0x40000800
08001720 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8001720: b580 push {r7, lr}
8001722: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8001724: 4b11 ldr r3, [pc, #68] @ (800176c <MX_USART1_UART_Init+0x4c>)
8001726: 4a12 ldr r2, [pc, #72] @ (8001770 <MX_USART1_UART_Init+0x50>)
8001728: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
800172a: 4b10 ldr r3, [pc, #64] @ (800176c <MX_USART1_UART_Init+0x4c>)
800172c: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8001730: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8001732: 4b0e ldr r3, [pc, #56] @ (800176c <MX_USART1_UART_Init+0x4c>)
8001734: 2200 movs r2, #0
8001736: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8001738: 4b0c ldr r3, [pc, #48] @ (800176c <MX_USART1_UART_Init+0x4c>)
800173a: 2200 movs r2, #0
800173c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800173e: 4b0b ldr r3, [pc, #44] @ (800176c <MX_USART1_UART_Init+0x4c>)
8001740: 2200 movs r2, #0
8001742: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8001744: 4b09 ldr r3, [pc, #36] @ (800176c <MX_USART1_UART_Init+0x4c>)
8001746: 220c movs r2, #12
8001748: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800174a: 4b08 ldr r3, [pc, #32] @ (800176c <MX_USART1_UART_Init+0x4c>)
800174c: 2200 movs r2, #0
800174e: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8001750: 4b06 ldr r3, [pc, #24] @ (800176c <MX_USART1_UART_Init+0x4c>)
8001752: 2200 movs r2, #0
8001754: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8001756: 4805 ldr r0, [pc, #20] @ (800176c <MX_USART1_UART_Init+0x4c>)
8001758: f005 f878 bl 800684c <HAL_UART_Init>
800175c: 4603 mov r3, r0
800175e: 2b00 cmp r3, #0
8001760: d001 beq.n 8001766 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8001762: f000 f8cf bl 8001904 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8001766: bf00 nop
8001768: bd80 pop {r7, pc}
800176a: bf00 nop
800176c: 20000390 .word 0x20000390
8001770: 40013800 .word 0x40013800
08001774 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8001774: b580 push {r7, lr}
8001776: b082 sub sp, #8
8001778: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
800177a: 4b0c ldr r3, [pc, #48] @ (80017ac <MX_DMA_Init+0x38>)
800177c: 695b ldr r3, [r3, #20]
800177e: 4a0b ldr r2, [pc, #44] @ (80017ac <MX_DMA_Init+0x38>)
8001780: f043 0301 orr.w r3, r3, #1
8001784: 6153 str r3, [r2, #20]
8001786: 4b09 ldr r3, [pc, #36] @ (80017ac <MX_DMA_Init+0x38>)
8001788: 695b ldr r3, [r3, #20]
800178a: f003 0301 and.w r3, r3, #1
800178e: 607b str r3, [r7, #4]
8001790: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8001792: 2200 movs r2, #0
8001794: 2100 movs r1, #0
8001796: 200b movs r0, #11
8001798: f001 f9cd bl 8002b36 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
800179c: 200b movs r0, #11
800179e: f001 f9e6 bl 8002b6e <HAL_NVIC_EnableIRQ>
}
80017a2: bf00 nop
80017a4: 3708 adds r7, #8
80017a6: 46bd mov sp, r7
80017a8: bd80 pop {r7, pc}
80017aa: bf00 nop
80017ac: 40021000 .word 0x40021000
080017b0 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80017b0: b580 push {r7, lr}
80017b2: b088 sub sp, #32
80017b4: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80017b6: f107 0310 add.w r3, r7, #16
80017ba: 2200 movs r2, #0
80017bc: 601a str r2, [r3, #0]
80017be: 605a str r2, [r3, #4]
80017c0: 609a str r2, [r3, #8]
80017c2: 60da str r2, [r3, #12]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80017c4: 4b4b ldr r3, [pc, #300] @ (80018f4 <MX_GPIO_Init+0x144>)
80017c6: 699b ldr r3, [r3, #24]
80017c8: 4a4a ldr r2, [pc, #296] @ (80018f4 <MX_GPIO_Init+0x144>)
80017ca: f043 0310 orr.w r3, r3, #16
80017ce: 6193 str r3, [r2, #24]
80017d0: 4b48 ldr r3, [pc, #288] @ (80018f4 <MX_GPIO_Init+0x144>)
80017d2: 699b ldr r3, [r3, #24]
80017d4: f003 0310 and.w r3, r3, #16
80017d8: 60fb str r3, [r7, #12]
80017da: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
80017dc: 4b45 ldr r3, [pc, #276] @ (80018f4 <MX_GPIO_Init+0x144>)
80017de: 699b ldr r3, [r3, #24]
80017e0: 4a44 ldr r2, [pc, #272] @ (80018f4 <MX_GPIO_Init+0x144>)
80017e2: f043 0320 orr.w r3, r3, #32
80017e6: 6193 str r3, [r2, #24]
80017e8: 4b42 ldr r3, [pc, #264] @ (80018f4 <MX_GPIO_Init+0x144>)
80017ea: 699b ldr r3, [r3, #24]
80017ec: f003 0320 and.w r3, r3, #32
80017f0: 60bb str r3, [r7, #8]
80017f2: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80017f4: 4b3f ldr r3, [pc, #252] @ (80018f4 <MX_GPIO_Init+0x144>)
80017f6: 699b ldr r3, [r3, #24]
80017f8: 4a3e ldr r2, [pc, #248] @ (80018f4 <MX_GPIO_Init+0x144>)
80017fa: f043 0304 orr.w r3, r3, #4
80017fe: 6193 str r3, [r2, #24]
8001800: 4b3c ldr r3, [pc, #240] @ (80018f4 <MX_GPIO_Init+0x144>)
8001802: 699b ldr r3, [r3, #24]
8001804: f003 0304 and.w r3, r3, #4
8001808: 607b str r3, [r7, #4]
800180a: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
800180c: 4b39 ldr r3, [pc, #228] @ (80018f4 <MX_GPIO_Init+0x144>)
800180e: 699b ldr r3, [r3, #24]
8001810: 4a38 ldr r2, [pc, #224] @ (80018f4 <MX_GPIO_Init+0x144>)
8001812: f043 0308 orr.w r3, r3, #8
8001816: 6193 str r3, [r2, #24]
8001818: 4b36 ldr r3, [pc, #216] @ (80018f4 <MX_GPIO_Init+0x144>)
800181a: 699b ldr r3, [r3, #24]
800181c: f003 0308 and.w r3, r3, #8
8001820: 603b str r3, [r7, #0]
8001822: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
8001824: 2200 movs r2, #0
8001826: f44f 5100 mov.w r1, #8192 @ 0x2000
800182a: 4833 ldr r0, [pc, #204] @ (80018f8 <MX_GPIO_Init+0x148>)
800182c: f001 ff49 bl 80036c2 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
8001830: 2200 movs r2, #0
8001832: f640 413e movw r1, #3134 @ 0xc3e
8001836: 4831 ldr r0, [pc, #196] @ (80018fc <MX_GPIO_Init+0x14c>)
8001838: f001 ff43 bl 80036c2 <HAL_GPIO_WritePin>
|EXP1_Pin|EXP2_Pin|EXP3_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, BUZ_Pin|LED1_Pin, GPIO_PIN_RESET);
800183c: 2200 movs r2, #0
800183e: f44f 4101 mov.w r1, #33024 @ 0x8100
8001842: 482f ldr r0, [pc, #188] @ (8001900 <MX_GPIO_Init+0x150>)
8001844: f001 ff3d bl 80036c2 <HAL_GPIO_WritePin>
/*Configure GPIO pin : LED2_Pin */
GPIO_InitStruct.Pin = LED2_Pin;
8001848: f44f 5300 mov.w r3, #8192 @ 0x2000
800184c: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800184e: 2301 movs r3, #1
8001850: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001852: 2300 movs r3, #0
8001854: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001856: 2302 movs r3, #2
8001858: 61fb str r3, [r7, #28]
HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
800185a: f107 0310 add.w r3, r7, #16
800185e: 4619 mov r1, r3
8001860: 4825 ldr r0, [pc, #148] @ (80018f8 <MX_GPIO_Init+0x148>)
8001862: f001 fd93 bl 800338c <HAL_GPIO_Init>
/*Configure GPIO pins : P1_Pin P2_Pin */
GPIO_InitStruct.Pin = P1_Pin|P2_Pin;
8001866: f44f 4340 mov.w r3, #49152 @ 0xc000
800186a: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800186c: 2300 movs r3, #0
800186e: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001870: 2300 movs r3, #0
8001872: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001874: f107 0310 add.w r3, r7, #16
8001878: 4619 mov r1, r3
800187a: 481f ldr r0, [pc, #124] @ (80018f8 <MX_GPIO_Init+0x148>)
800187c: f001 fd86 bl 800338c <HAL_GPIO_Init>
/*Configure GPIO pin : AIN1_Pin */
GPIO_InitStruct.Pin = AIN1_Pin;
8001880: 2310 movs r3, #16
8001882: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001884: 2303 movs r3, #3
8001886: 617b str r3, [r7, #20]
HAL_GPIO_Init(AIN1_GPIO_Port, &GPIO_InitStruct);
8001888: f107 0310 add.w r3, r7, #16
800188c: 4619 mov r1, r3
800188e: 481c ldr r0, [pc, #112] @ (8001900 <MX_GPIO_Init+0x150>)
8001890: f001 fd7c bl 800338c <HAL_GPIO_Init>
/*Configure GPIO pins : INH1_Pin INH2_Pin INH3_Pin INH4_Pin
EXP1_Pin EXP2_Pin EXP3_Pin */
GPIO_InitStruct.Pin = INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
8001894: f640 433e movw r3, #3134 @ 0xc3e
8001898: 613b str r3, [r7, #16]
|EXP1_Pin|EXP2_Pin|EXP3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800189a: 2301 movs r3, #1
800189c: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800189e: 2300 movs r3, #0
80018a0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80018a2: 2302 movs r3, #2
80018a4: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80018a6: f107 0310 add.w r3, r7, #16
80018aa: 4619 mov r1, r3
80018ac: 4813 ldr r0, [pc, #76] @ (80018fc <MX_GPIO_Init+0x14c>)
80018ae: f001 fd6d bl 800338c <HAL_GPIO_Init>
/*Configure GPIO pins : CH1_Pin CH2_Pin CH3_Pin CH4_Pin */
GPIO_InitStruct.Pin = CH1_Pin|CH2_Pin|CH3_Pin|CH4_Pin;
80018b2: f44f 4370 mov.w r3, #61440 @ 0xf000
80018b6: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80018b8: 2300 movs r3, #0
80018ba: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80018bc: 2300 movs r3, #0
80018be: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80018c0: f107 0310 add.w r3, r7, #16
80018c4: 4619 mov r1, r3
80018c6: 480d ldr r0, [pc, #52] @ (80018fc <MX_GPIO_Init+0x14c>)
80018c8: f001 fd60 bl 800338c <HAL_GPIO_Init>
/*Configure GPIO pins : BUZ_Pin LED1_Pin */
GPIO_InitStruct.Pin = BUZ_Pin|LED1_Pin;
80018cc: f44f 4301 mov.w r3, #33024 @ 0x8100
80018d0: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80018d2: 2301 movs r3, #1
80018d4: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80018d6: 2300 movs r3, #0
80018d8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80018da: 2302 movs r3, #2
80018dc: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80018de: f107 0310 add.w r3, r7, #16
80018e2: 4619 mov r1, r3
80018e4: 4806 ldr r0, [pc, #24] @ (8001900 <MX_GPIO_Init+0x150>)
80018e6: f001 fd51 bl 800338c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80018ea: bf00 nop
80018ec: 3720 adds r7, #32
80018ee: 46bd mov sp, r7
80018f0: bd80 pop {r7, pc}
80018f2: bf00 nop
80018f4: 40021000 .word 0x40021000
80018f8: 40011000 .word 0x40011000
80018fc: 40010c00 .word 0x40010c00
8001900: 40010800 .word 0x40010800
08001904 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001904: b480 push {r7}
8001906: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001908: b672 cpsid i
}
800190a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800190c: bf00 nop
800190e: e7fd b.n 800190c <Error_Handler+0x8>
08001910 <IsPwmRunning>:
extern TIM_HandleTypeDef htim2;
extern TIM_HandleTypeDef htim3;
extern TIM_HandleTypeDef htim4;
bool IsPwmRunning(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8001910: b580 push {r7, lr}
8001912: b084 sub sp, #16
8001914: af00 add r7, sp, #0
8001916: 6078 str r0, [r7, #4]
8001918: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef chState = HAL_TIM_GetChannelState(htim, Channel);
800191a: 6839 ldr r1, [r7, #0]
800191c: 6878 ldr r0, [r7, #4]
800191e: f004 fc5e bl 80061de <HAL_TIM_GetChannelState>
8001922: 4603 mov r3, r0
8001924: 73fb strb r3, [r7, #15]
return (chState == HAL_TIM_CHANNEL_STATE_BUSY);
8001926: 7bfb ldrb r3, [r7, #15]
8001928: 2b02 cmp r3, #2
800192a: bf0c ite eq
800192c: 2301 moveq r3, #1
800192e: 2300 movne r3, #0
8001930: b2db uxtb r3, r3
}
8001932: 4618 mov r0, r3
8001934: 3710 adds r7, #16
8001936: 46bd mov sp, r7
8001938: bd80 pop {r7, pc}
0800193a <StopMot>:
void StopMot(TIM_HandleTypeDef *htim,uint32_t Channel){
800193a: b580 push {r7, lr}
800193c: b082 sub sp, #8
800193e: af00 add r7, sp, #0
8001940: 6078 str r0, [r7, #4]
8001942: 6039 str r1, [r7, #0]
HAL_TIM_PWM_Stop(htim, Channel);
8001944: 6839 ldr r1, [r7, #0]
8001946: 6878 ldr r0, [r7, #4]
8001948: f004 fa5c bl 8005e04 <HAL_TIM_PWM_Stop>
}
800194c: bf00 nop
800194e: 3708 adds r7, #8
8001950: 46bd mov sp, r7
8001952: bd80 pop {r7, pc}
08001954 <StartMot>:
void StartMot(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
8001954: b580 push {r7, lr}
8001956: b084 sub sp, #16
8001958: af00 add r7, sp, #0
800195a: 60f8 str r0, [r7, #12]
800195c: 60b9 str r1, [r7, #8]
800195e: 4613 mov r3, r2
8001960: 80fb strh r3, [r7, #6]
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8001962: 68bb ldr r3, [r7, #8]
8001964: 2b00 cmp r3, #0
8001966: d104 bne.n 8001972 <StartMot+0x1e>
8001968: 68fb ldr r3, [r7, #12]
800196a: 681b ldr r3, [r3, #0]
800196c: 88fa ldrh r2, [r7, #6]
800196e: 635a str r2, [r3, #52] @ 0x34
8001970: e013 b.n 800199a <StartMot+0x46>
8001972: 68bb ldr r3, [r7, #8]
8001974: 2b04 cmp r3, #4
8001976: d104 bne.n 8001982 <StartMot+0x2e>
8001978: 68fb ldr r3, [r7, #12]
800197a: 681a ldr r2, [r3, #0]
800197c: 88fb ldrh r3, [r7, #6]
800197e: 6393 str r3, [r2, #56] @ 0x38
8001980: e00b b.n 800199a <StartMot+0x46>
8001982: 68bb ldr r3, [r7, #8]
8001984: 2b08 cmp r3, #8
8001986: d104 bne.n 8001992 <StartMot+0x3e>
8001988: 68fb ldr r3, [r7, #12]
800198a: 681a ldr r2, [r3, #0]
800198c: 88fb ldrh r3, [r7, #6]
800198e: 63d3 str r3, [r2, #60] @ 0x3c
8001990: e003 b.n 800199a <StartMot+0x46>
8001992: 68fb ldr r3, [r7, #12]
8001994: 681a ldr r2, [r3, #0]
8001996: 88fb ldrh r3, [r7, #6]
8001998: 6413 str r3, [r2, #64] @ 0x40
HAL_TIM_PWM_Start(htim, Channel);
800199a: 68b9 ldr r1, [r7, #8]
800199c: 68f8 ldr r0, [r7, #12]
800199e: f004 f98f bl 8005cc0 <HAL_TIM_PWM_Start>
}
80019a2: bf00 nop
80019a4: 3710 adds r7, #16
80019a6: 46bd mov sp, r7
80019a8: bd80 pop {r7, pc}
080019aa <SetMotPwm>:
void SetMotPwm(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
80019aa: b480 push {r7}
80019ac: b085 sub sp, #20
80019ae: af00 add r7, sp, #0
80019b0: 60f8 str r0, [r7, #12]
80019b2: 60b9 str r1, [r7, #8]
80019b4: 4613 mov r3, r2
80019b6: 80fb strh r3, [r7, #6]
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80019b8: 68bb ldr r3, [r7, #8]
80019ba: 2b00 cmp r3, #0
80019bc: d104 bne.n 80019c8 <SetMotPwm+0x1e>
80019be: 68fb ldr r3, [r7, #12]
80019c0: 681b ldr r3, [r3, #0]
80019c2: 88fa ldrh r2, [r7, #6]
80019c4: 635a str r2, [r3, #52] @ 0x34
}
80019c6: e013 b.n 80019f0 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80019c8: 68bb ldr r3, [r7, #8]
80019ca: 2b04 cmp r3, #4
80019cc: d104 bne.n 80019d8 <SetMotPwm+0x2e>
80019ce: 68fb ldr r3, [r7, #12]
80019d0: 681a ldr r2, [r3, #0]
80019d2: 88fb ldrh r3, [r7, #6]
80019d4: 6393 str r3, [r2, #56] @ 0x38
}
80019d6: e00b b.n 80019f0 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80019d8: 68bb ldr r3, [r7, #8]
80019da: 2b08 cmp r3, #8
80019dc: d104 bne.n 80019e8 <SetMotPwm+0x3e>
80019de: 68fb ldr r3, [r7, #12]
80019e0: 681a ldr r2, [r3, #0]
80019e2: 88fb ldrh r3, [r7, #6]
80019e4: 63d3 str r3, [r2, #60] @ 0x3c
}
80019e6: e003 b.n 80019f0 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80019e8: 68fb ldr r3, [r7, #12]
80019ea: 681a ldr r2, [r3, #0]
80019ec: 88fb ldrh r3, [r7, #6]
80019ee: 6413 str r3, [r2, #64] @ 0x40
}
80019f0: bf00 nop
80019f2: 3714 adds r7, #20
80019f4: 46bd mov sp, r7
80019f6: bc80 pop {r7}
80019f8: 4770 bx lr
...
080019fc <SetMot>:
void SetMot(uint8_t mot,uint8_t dir,uint16_t pwmval){
80019fc: b580 push {r7, lr}
80019fe: b082 sub sp, #8
8001a00: af00 add r7, sp, #0
8001a02: 4603 mov r3, r0
8001a04: 71fb strb r3, [r7, #7]
8001a06: 460b mov r3, r1
8001a08: 71bb strb r3, [r7, #6]
8001a0a: 4613 mov r3, r2
8001a0c: 80bb strh r3, [r7, #4]
switch(mot){
8001a0e: 79fb ldrb r3, [r7, #7]
8001a10: 3b01 subs r3, #1
8001a12: 2b03 cmp r3, #3
8001a14: f200 8158 bhi.w 8001cc8 <SetMot+0x2cc>
8001a18: a201 add r2, pc, #4 @ (adr r2, 8001a20 <SetMot+0x24>)
8001a1a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001a1e: bf00 nop
8001a20: 08001a31 .word 0x08001a31
8001a24: 08001ad3 .word 0x08001ad3
8001a28: 08001b75 .word 0x08001b75
8001a2c: 08001c1f .word 0x08001c1f
case 1:
if(dir==FW){
8001a30: 79bb ldrb r3, [r7, #6]
8001a32: 2b00 cmp r3, #0
8001a34: d126 bne.n 8001a84 <SetMot+0x88>
if(pwmval==0){
8001a36: 88bb ldrh r3, [r7, #4]
8001a38: 2b00 cmp r3, #0
8001a3a: d109 bne.n 8001a50 <SetMot+0x54>
StopMot(timMot1,FWMot1);
8001a3c: 2100 movs r1, #0
8001a3e: 48a5 ldr r0, [pc, #660] @ (8001cd4 <SetMot+0x2d8>)
8001a40: f7ff ff7b bl 800193a <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
8001a44: 2200 movs r2, #0
8001a46: 2102 movs r1, #2
8001a48: 48a3 ldr r0, [pc, #652] @ (8001cd8 <SetMot+0x2dc>)
8001a4a: f001 fe3a bl 80036c2 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
StartMot(timMot1,BWMot1,pwmval);
}
}
break;
8001a4e: e13c b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot1, FWMot1)){
8001a50: 2100 movs r1, #0
8001a52: 48a0 ldr r0, [pc, #640] @ (8001cd4 <SetMot+0x2d8>)
8001a54: f7ff ff5c bl 8001910 <IsPwmRunning>
8001a58: 4603 mov r3, r0
8001a5a: 2b00 cmp r3, #0
8001a5c: d006 beq.n 8001a6c <SetMot+0x70>
SetMotPwm(timMot1,FWMot1,pwmval);
8001a5e: 88bb ldrh r3, [r7, #4]
8001a60: 461a mov r2, r3
8001a62: 2100 movs r1, #0
8001a64: 489b ldr r0, [pc, #620] @ (8001cd4 <SetMot+0x2d8>)
8001a66: f7ff ffa0 bl 80019aa <SetMotPwm>
break;
8001a6a: e12e b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8001a6c: 2201 movs r2, #1
8001a6e: 2102 movs r1, #2
8001a70: 4899 ldr r0, [pc, #612] @ (8001cd8 <SetMot+0x2dc>)
8001a72: f001 fe26 bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot1,FWMot1,pwmval);
8001a76: 88bb ldrh r3, [r7, #4]
8001a78: 461a mov r2, r3
8001a7a: 2100 movs r1, #0
8001a7c: 4895 ldr r0, [pc, #596] @ (8001cd4 <SetMot+0x2d8>)
8001a7e: f7ff ff69 bl 8001954 <StartMot>
break;
8001a82: e122 b.n 8001cca <SetMot+0x2ce>
if(pwmval==0){
8001a84: 88bb ldrh r3, [r7, #4]
8001a86: 2b00 cmp r3, #0
8001a88: d109 bne.n 8001a9e <SetMot+0xa2>
StopMot(timMot1,BWMot1);
8001a8a: 2104 movs r1, #4
8001a8c: 4891 ldr r0, [pc, #580] @ (8001cd4 <SetMot+0x2d8>)
8001a8e: f7ff ff54 bl 800193a <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
8001a92: 2200 movs r2, #0
8001a94: 2102 movs r1, #2
8001a96: 4890 ldr r0, [pc, #576] @ (8001cd8 <SetMot+0x2dc>)
8001a98: f001 fe13 bl 80036c2 <HAL_GPIO_WritePin>
break;
8001a9c: e115 b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot1, BWMot1)){
8001a9e: 2104 movs r1, #4
8001aa0: 488c ldr r0, [pc, #560] @ (8001cd4 <SetMot+0x2d8>)
8001aa2: f7ff ff35 bl 8001910 <IsPwmRunning>
8001aa6: 4603 mov r3, r0
8001aa8: 2b00 cmp r3, #0
8001aaa: d006 beq.n 8001aba <SetMot+0xbe>
SetMotPwm(timMot1,BWMot1,pwmval);
8001aac: 88bb ldrh r3, [r7, #4]
8001aae: 461a mov r2, r3
8001ab0: 2104 movs r1, #4
8001ab2: 4888 ldr r0, [pc, #544] @ (8001cd4 <SetMot+0x2d8>)
8001ab4: f7ff ff79 bl 80019aa <SetMotPwm>
break;
8001ab8: e107 b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8001aba: 2201 movs r2, #1
8001abc: 2102 movs r1, #2
8001abe: 4886 ldr r0, [pc, #536] @ (8001cd8 <SetMot+0x2dc>)
8001ac0: f001 fdff bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot1,BWMot1,pwmval);
8001ac4: 88bb ldrh r3, [r7, #4]
8001ac6: 461a mov r2, r3
8001ac8: 2104 movs r1, #4
8001aca: 4882 ldr r0, [pc, #520] @ (8001cd4 <SetMot+0x2d8>)
8001acc: f7ff ff42 bl 8001954 <StartMot>
break;
8001ad0: e0fb b.n 8001cca <SetMot+0x2ce>
case 2:
if(dir==FW){
8001ad2: 79bb ldrb r3, [r7, #6]
8001ad4: 2b00 cmp r3, #0
8001ad6: d126 bne.n 8001b26 <SetMot+0x12a>
if(pwmval==0){
8001ad8: 88bb ldrh r3, [r7, #4]
8001ada: 2b00 cmp r3, #0
8001adc: d109 bne.n 8001af2 <SetMot+0xf6>
StopMot(timMot2,FWMot2);
8001ade: 2108 movs r1, #8
8001ae0: 487c ldr r0, [pc, #496] @ (8001cd4 <SetMot+0x2d8>)
8001ae2: f7ff ff2a bl 800193a <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
8001ae6: 2200 movs r2, #0
8001ae8: 2104 movs r1, #4
8001aea: 487b ldr r0, [pc, #492] @ (8001cd8 <SetMot+0x2dc>)
8001aec: f001 fde9 bl 80036c2 <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
StartMot(timMot2,BWMot2,pwmval);
}
}
break;
8001af0: e0eb b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot2, FWMot2)){
8001af2: 2108 movs r1, #8
8001af4: 4877 ldr r0, [pc, #476] @ (8001cd4 <SetMot+0x2d8>)
8001af6: f7ff ff0b bl 8001910 <IsPwmRunning>
8001afa: 4603 mov r3, r0
8001afc: 2b00 cmp r3, #0
8001afe: d006 beq.n 8001b0e <SetMot+0x112>
SetMotPwm(timMot2,FWMot2,pwmval);
8001b00: 88bb ldrh r3, [r7, #4]
8001b02: 461a mov r2, r3
8001b04: 2108 movs r1, #8
8001b06: 4873 ldr r0, [pc, #460] @ (8001cd4 <SetMot+0x2d8>)
8001b08: f7ff ff4f bl 80019aa <SetMotPwm>
break;
8001b0c: e0dd b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8001b0e: 2201 movs r2, #1
8001b10: 2104 movs r1, #4
8001b12: 4871 ldr r0, [pc, #452] @ (8001cd8 <SetMot+0x2dc>)
8001b14: f001 fdd5 bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot2,FWMot2,pwmval);
8001b18: 88bb ldrh r3, [r7, #4]
8001b1a: 461a mov r2, r3
8001b1c: 2108 movs r1, #8
8001b1e: 486d ldr r0, [pc, #436] @ (8001cd4 <SetMot+0x2d8>)
8001b20: f7ff ff18 bl 8001954 <StartMot>
break;
8001b24: e0d1 b.n 8001cca <SetMot+0x2ce>
if(pwmval==0){
8001b26: 88bb ldrh r3, [r7, #4]
8001b28: 2b00 cmp r3, #0
8001b2a: d109 bne.n 8001b40 <SetMot+0x144>
StopMot(timMot2,BWMot2);
8001b2c: 210c movs r1, #12
8001b2e: 4869 ldr r0, [pc, #420] @ (8001cd4 <SetMot+0x2d8>)
8001b30: f7ff ff03 bl 800193a <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
8001b34: 2200 movs r2, #0
8001b36: 2104 movs r1, #4
8001b38: 4867 ldr r0, [pc, #412] @ (8001cd8 <SetMot+0x2dc>)
8001b3a: f001 fdc2 bl 80036c2 <HAL_GPIO_WritePin>
break;
8001b3e: e0c4 b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot2, BWMot2)){
8001b40: 210c movs r1, #12
8001b42: 4864 ldr r0, [pc, #400] @ (8001cd4 <SetMot+0x2d8>)
8001b44: f7ff fee4 bl 8001910 <IsPwmRunning>
8001b48: 4603 mov r3, r0
8001b4a: 2b00 cmp r3, #0
8001b4c: d006 beq.n 8001b5c <SetMot+0x160>
SetMotPwm(timMot2,BWMot2,pwmval);
8001b4e: 88bb ldrh r3, [r7, #4]
8001b50: 461a mov r2, r3
8001b52: 210c movs r1, #12
8001b54: 485f ldr r0, [pc, #380] @ (8001cd4 <SetMot+0x2d8>)
8001b56: f7ff ff28 bl 80019aa <SetMotPwm>
break;
8001b5a: e0b6 b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8001b5c: 2201 movs r2, #1
8001b5e: 2104 movs r1, #4
8001b60: 485d ldr r0, [pc, #372] @ (8001cd8 <SetMot+0x2dc>)
8001b62: f001 fdae bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot2,BWMot2,pwmval);
8001b66: 88bb ldrh r3, [r7, #4]
8001b68: 461a mov r2, r3
8001b6a: 210c movs r1, #12
8001b6c: 4859 ldr r0, [pc, #356] @ (8001cd4 <SetMot+0x2d8>)
8001b6e: f7ff fef1 bl 8001954 <StartMot>
break;
8001b72: e0aa b.n 8001cca <SetMot+0x2ce>
case 3:
if(dir==FW){
8001b74: 79bb ldrb r3, [r7, #6]
8001b76: 2b00 cmp r3, #0
8001b78: d128 bne.n 8001bcc <SetMot+0x1d0>
if(pwmval==0){
8001b7a: 88bb ldrh r3, [r7, #4]
8001b7c: 2b00 cmp r3, #0
8001b7e: d10a bne.n 8001b96 <SetMot+0x19a>
StopMot(timMot3,FWMot3);
8001b80: 2100 movs r1, #0
8001b82: 4856 ldr r0, [pc, #344] @ (8001cdc <SetMot+0x2e0>)
8001b84: f7ff fed9 bl 800193a <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8001b88: 2200 movs r2, #0
8001b8a: f44f 6180 mov.w r1, #1024 @ 0x400
8001b8e: 4852 ldr r0, [pc, #328] @ (8001cd8 <SetMot+0x2dc>)
8001b90: f001 fd97 bl 80036c2 <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
StartMot(timMot3,BWMot3,pwmval);
}
}
break;
8001b94: e099 b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot3, FWMot3)){
8001b96: 2100 movs r1, #0
8001b98: 4850 ldr r0, [pc, #320] @ (8001cdc <SetMot+0x2e0>)
8001b9a: f7ff feb9 bl 8001910 <IsPwmRunning>
8001b9e: 4603 mov r3, r0
8001ba0: 2b00 cmp r3, #0
8001ba2: d006 beq.n 8001bb2 <SetMot+0x1b6>
SetMotPwm(timMot3,FWMot3,pwmval);
8001ba4: 88bb ldrh r3, [r7, #4]
8001ba6: 461a mov r2, r3
8001ba8: 2100 movs r1, #0
8001baa: 484c ldr r0, [pc, #304] @ (8001cdc <SetMot+0x2e0>)
8001bac: f7ff fefd bl 80019aa <SetMotPwm>
break;
8001bb0: e08b b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8001bb2: 2201 movs r2, #1
8001bb4: f44f 6180 mov.w r1, #1024 @ 0x400
8001bb8: 4847 ldr r0, [pc, #284] @ (8001cd8 <SetMot+0x2dc>)
8001bba: f001 fd82 bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot3,FWMot3,pwmval);
8001bbe: 88bb ldrh r3, [r7, #4]
8001bc0: 461a mov r2, r3
8001bc2: 2100 movs r1, #0
8001bc4: 4845 ldr r0, [pc, #276] @ (8001cdc <SetMot+0x2e0>)
8001bc6: f7ff fec5 bl 8001954 <StartMot>
break;
8001bca: e07e b.n 8001cca <SetMot+0x2ce>
if(pwmval==0){
8001bcc: 88bb ldrh r3, [r7, #4]
8001bce: 2b00 cmp r3, #0
8001bd0: d10a bne.n 8001be8 <SetMot+0x1ec>
StopMot(timMot3,BWMot3);
8001bd2: 2104 movs r1, #4
8001bd4: 4841 ldr r0, [pc, #260] @ (8001cdc <SetMot+0x2e0>)
8001bd6: f7ff feb0 bl 800193a <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8001bda: 2200 movs r2, #0
8001bdc: f44f 6180 mov.w r1, #1024 @ 0x400
8001be0: 483d ldr r0, [pc, #244] @ (8001cd8 <SetMot+0x2dc>)
8001be2: f001 fd6e bl 80036c2 <HAL_GPIO_WritePin>
break;
8001be6: e070 b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot3, BWMot3)){
8001be8: 2104 movs r1, #4
8001bea: 483c ldr r0, [pc, #240] @ (8001cdc <SetMot+0x2e0>)
8001bec: f7ff fe90 bl 8001910 <IsPwmRunning>
8001bf0: 4603 mov r3, r0
8001bf2: 2b00 cmp r3, #0
8001bf4: d006 beq.n 8001c04 <SetMot+0x208>
SetMotPwm(timMot3,BWMot3,pwmval);
8001bf6: 88bb ldrh r3, [r7, #4]
8001bf8: 461a mov r2, r3
8001bfa: 2104 movs r1, #4
8001bfc: 4837 ldr r0, [pc, #220] @ (8001cdc <SetMot+0x2e0>)
8001bfe: f7ff fed4 bl 80019aa <SetMotPwm>
break;
8001c02: e062 b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8001c04: 2201 movs r2, #1
8001c06: f44f 6180 mov.w r1, #1024 @ 0x400
8001c0a: 4833 ldr r0, [pc, #204] @ (8001cd8 <SetMot+0x2dc>)
8001c0c: f001 fd59 bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot3,BWMot3,pwmval);
8001c10: 88bb ldrh r3, [r7, #4]
8001c12: 461a mov r2, r3
8001c14: 2104 movs r1, #4
8001c16: 4831 ldr r0, [pc, #196] @ (8001cdc <SetMot+0x2e0>)
8001c18: f7ff fe9c bl 8001954 <StartMot>
break;
8001c1c: e055 b.n 8001cca <SetMot+0x2ce>
case 4:
if(dir==FW){
8001c1e: 79bb ldrb r3, [r7, #6]
8001c20: 2b00 cmp r3, #0
8001c22: d128 bne.n 8001c76 <SetMot+0x27a>
if(pwmval==0){
8001c24: 88bb ldrh r3, [r7, #4]
8001c26: 2b00 cmp r3, #0
8001c28: d10a bne.n 8001c40 <SetMot+0x244>
StopMot(timMot4,FWMot4);
8001c2a: 2108 movs r1, #8
8001c2c: 482b ldr r0, [pc, #172] @ (8001cdc <SetMot+0x2e0>)
8001c2e: f7ff fe84 bl 800193a <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8001c32: 2200 movs r2, #0
8001c34: f44f 6100 mov.w r1, #2048 @ 0x800
8001c38: 4827 ldr r0, [pc, #156] @ (8001cd8 <SetMot+0x2dc>)
8001c3a: f001 fd42 bl 80036c2 <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
StartMot(timMot4,BWMot4,pwmval);
}
}
break;
8001c3e: e044 b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot4, FWMot4)){
8001c40: 2108 movs r1, #8
8001c42: 4826 ldr r0, [pc, #152] @ (8001cdc <SetMot+0x2e0>)
8001c44: f7ff fe64 bl 8001910 <IsPwmRunning>
8001c48: 4603 mov r3, r0
8001c4a: 2b00 cmp r3, #0
8001c4c: d006 beq.n 8001c5c <SetMot+0x260>
SetMotPwm(timMot4,FWMot4,pwmval);
8001c4e: 88bb ldrh r3, [r7, #4]
8001c50: 461a mov r2, r3
8001c52: 2108 movs r1, #8
8001c54: 4821 ldr r0, [pc, #132] @ (8001cdc <SetMot+0x2e0>)
8001c56: f7ff fea8 bl 80019aa <SetMotPwm>
break;
8001c5a: e036 b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8001c5c: 2201 movs r2, #1
8001c5e: f44f 6100 mov.w r1, #2048 @ 0x800
8001c62: 481d ldr r0, [pc, #116] @ (8001cd8 <SetMot+0x2dc>)
8001c64: f001 fd2d bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot4,FWMot4,pwmval);
8001c68: 88bb ldrh r3, [r7, #4]
8001c6a: 461a mov r2, r3
8001c6c: 2108 movs r1, #8
8001c6e: 481b ldr r0, [pc, #108] @ (8001cdc <SetMot+0x2e0>)
8001c70: f7ff fe70 bl 8001954 <StartMot>
break;
8001c74: e029 b.n 8001cca <SetMot+0x2ce>
if(pwmval==0){
8001c76: 88bb ldrh r3, [r7, #4]
8001c78: 2b00 cmp r3, #0
8001c7a: d10a bne.n 8001c92 <SetMot+0x296>
StopMot(timMot4,BWMot4);
8001c7c: 210c movs r1, #12
8001c7e: 4817 ldr r0, [pc, #92] @ (8001cdc <SetMot+0x2e0>)
8001c80: f7ff fe5b bl 800193a <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8001c84: 2200 movs r2, #0
8001c86: f44f 6100 mov.w r1, #2048 @ 0x800
8001c8a: 4813 ldr r0, [pc, #76] @ (8001cd8 <SetMot+0x2dc>)
8001c8c: f001 fd19 bl 80036c2 <HAL_GPIO_WritePin>
break;
8001c90: e01b b.n 8001cca <SetMot+0x2ce>
}else if(IsPwmRunning(timMot4, BWMot4)){
8001c92: 210c movs r1, #12
8001c94: 4811 ldr r0, [pc, #68] @ (8001cdc <SetMot+0x2e0>)
8001c96: f7ff fe3b bl 8001910 <IsPwmRunning>
8001c9a: 4603 mov r3, r0
8001c9c: 2b00 cmp r3, #0
8001c9e: d006 beq.n 8001cae <SetMot+0x2b2>
SetMotPwm(timMot4,BWMot4,pwmval);
8001ca0: 88bb ldrh r3, [r7, #4]
8001ca2: 461a mov r2, r3
8001ca4: 210c movs r1, #12
8001ca6: 480d ldr r0, [pc, #52] @ (8001cdc <SetMot+0x2e0>)
8001ca8: f7ff fe7f bl 80019aa <SetMotPwm>
break;
8001cac: e00d b.n 8001cca <SetMot+0x2ce>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8001cae: 2201 movs r2, #1
8001cb0: f44f 6100 mov.w r1, #2048 @ 0x800
8001cb4: 4808 ldr r0, [pc, #32] @ (8001cd8 <SetMot+0x2dc>)
8001cb6: f001 fd04 bl 80036c2 <HAL_GPIO_WritePin>
StartMot(timMot4,BWMot4,pwmval);
8001cba: 88bb ldrh r3, [r7, #4]
8001cbc: 461a mov r2, r3
8001cbe: 210c movs r1, #12
8001cc0: 4806 ldr r0, [pc, #24] @ (8001cdc <SetMot+0x2e0>)
8001cc2: f7ff fe47 bl 8001954 <StartMot>
break;
8001cc6: e000 b.n 8001cca <SetMot+0x2ce>
default:
break;
8001cc8: bf00 nop
}
}
8001cca: bf00 nop
8001ccc: 3708 adds r7, #8
8001cce: 46bd mov sp, r7
8001cd0: bd80 pop {r7, pc}
8001cd2: bf00 nop
8001cd4: 20000300 .word 0x20000300
8001cd8: 40010c00 .word 0x40010c00
8001cdc: 20000348 .word 0x20000348
08001ce0 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001ce0: b480 push {r7}
8001ce2: b085 sub sp, #20
8001ce4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8001ce6: 4b15 ldr r3, [pc, #84] @ (8001d3c <HAL_MspInit+0x5c>)
8001ce8: 699b ldr r3, [r3, #24]
8001cea: 4a14 ldr r2, [pc, #80] @ (8001d3c <HAL_MspInit+0x5c>)
8001cec: f043 0301 orr.w r3, r3, #1
8001cf0: 6193 str r3, [r2, #24]
8001cf2: 4b12 ldr r3, [pc, #72] @ (8001d3c <HAL_MspInit+0x5c>)
8001cf4: 699b ldr r3, [r3, #24]
8001cf6: f003 0301 and.w r3, r3, #1
8001cfa: 60bb str r3, [r7, #8]
8001cfc: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8001cfe: 4b0f ldr r3, [pc, #60] @ (8001d3c <HAL_MspInit+0x5c>)
8001d00: 69db ldr r3, [r3, #28]
8001d02: 4a0e ldr r2, [pc, #56] @ (8001d3c <HAL_MspInit+0x5c>)
8001d04: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001d08: 61d3 str r3, [r2, #28]
8001d0a: 4b0c ldr r3, [pc, #48] @ (8001d3c <HAL_MspInit+0x5c>)
8001d0c: 69db ldr r3, [r3, #28]
8001d0e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001d12: 607b str r3, [r7, #4]
8001d14: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8001d16: 4b0a ldr r3, [pc, #40] @ (8001d40 <HAL_MspInit+0x60>)
8001d18: 685b ldr r3, [r3, #4]
8001d1a: 60fb str r3, [r7, #12]
8001d1c: 68fb ldr r3, [r7, #12]
8001d1e: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
8001d22: 60fb str r3, [r7, #12]
8001d24: 68fb ldr r3, [r7, #12]
8001d26: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8001d2a: 60fb str r3, [r7, #12]
8001d2c: 4a04 ldr r2, [pc, #16] @ (8001d40 <HAL_MspInit+0x60>)
8001d2e: 68fb ldr r3, [r7, #12]
8001d30: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001d32: bf00 nop
8001d34: 3714 adds r7, #20
8001d36: 46bd mov sp, r7
8001d38: bc80 pop {r7}
8001d3a: 4770 bx lr
8001d3c: 40021000 .word 0x40021000
8001d40: 40010000 .word 0x40010000
08001d44 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001d44: b580 push {r7, lr}
8001d46: b08a sub sp, #40 @ 0x28
8001d48: af00 add r7, sp, #0
8001d4a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001d4c: f107 0318 add.w r3, r7, #24
8001d50: 2200 movs r2, #0
8001d52: 601a str r2, [r3, #0]
8001d54: 605a str r2, [r3, #4]
8001d56: 609a str r2, [r3, #8]
8001d58: 60da str r2, [r3, #12]
if(hadc->Instance==ADC1)
8001d5a: 687b ldr r3, [r7, #4]
8001d5c: 681b ldr r3, [r3, #0]
8001d5e: 4a33 ldr r2, [pc, #204] @ (8001e2c <HAL_ADC_MspInit+0xe8>)
8001d60: 4293 cmp r3, r2
8001d62: d15f bne.n 8001e24 <HAL_ADC_MspInit+0xe0>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8001d64: 4b32 ldr r3, [pc, #200] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d66: 699b ldr r3, [r3, #24]
8001d68: 4a31 ldr r2, [pc, #196] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d6a: f443 7300 orr.w r3, r3, #512 @ 0x200
8001d6e: 6193 str r3, [r2, #24]
8001d70: 4b2f ldr r3, [pc, #188] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d72: 699b ldr r3, [r3, #24]
8001d74: f403 7300 and.w r3, r3, #512 @ 0x200
8001d78: 617b str r3, [r7, #20]
8001d7a: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001d7c: 4b2c ldr r3, [pc, #176] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d7e: 699b ldr r3, [r3, #24]
8001d80: 4a2b ldr r2, [pc, #172] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d82: f043 0304 orr.w r3, r3, #4
8001d86: 6193 str r3, [r2, #24]
8001d88: 4b29 ldr r3, [pc, #164] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d8a: 699b ldr r3, [r3, #24]
8001d8c: f003 0304 and.w r3, r3, #4
8001d90: 613b str r3, [r7, #16]
8001d92: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001d94: 4b26 ldr r3, [pc, #152] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d96: 699b ldr r3, [r3, #24]
8001d98: 4a25 ldr r2, [pc, #148] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001d9a: f043 0308 orr.w r3, r3, #8
8001d9e: 6193 str r3, [r2, #24]
8001da0: 4b23 ldr r3, [pc, #140] @ (8001e30 <HAL_ADC_MspInit+0xec>)
8001da2: 699b ldr r3, [r3, #24]
8001da4: f003 0308 and.w r3, r3, #8
8001da8: 60fb str r3, [r7, #12]
8001daa: 68fb ldr r3, [r7, #12]
PA5 ------> ADC1_IN5
PA6 ------> ADC1_IN6
PA7 ------> ADC1_IN7
PB0 ------> ADC1_IN8
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin|AIN3_Pin|AIN4_Pin;
8001dac: 23f0 movs r3, #240 @ 0xf0
8001dae: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001db0: 2303 movs r3, #3
8001db2: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001db4: f107 0318 add.w r3, r7, #24
8001db8: 4619 mov r1, r3
8001dba: 481e ldr r0, [pc, #120] @ (8001e34 <HAL_ADC_MspInit+0xf0>)
8001dbc: f001 fae6 bl 800338c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ANEM_Pin;
8001dc0: 2301 movs r3, #1
8001dc2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001dc4: 2303 movs r3, #3
8001dc6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ANEM_GPIO_Port, &GPIO_InitStruct);
8001dc8: f107 0318 add.w r3, r7, #24
8001dcc: 4619 mov r1, r3
8001dce: 481a ldr r0, [pc, #104] @ (8001e38 <HAL_ADC_MspInit+0xf4>)
8001dd0: f001 fadc bl 800338c <HAL_GPIO_Init>
/* ADC1 DMA Init */
/* ADC1 Init */
hdma_adc1.Instance = DMA1_Channel1;
8001dd4: 4b19 ldr r3, [pc, #100] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001dd6: 4a1a ldr r2, [pc, #104] @ (8001e40 <HAL_ADC_MspInit+0xfc>)
8001dd8: 601a str r2, [r3, #0]
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
8001dda: 4b18 ldr r3, [pc, #96] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001ddc: 2200 movs r2, #0
8001dde: 605a str r2, [r3, #4]
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
8001de0: 4b16 ldr r3, [pc, #88] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001de2: 2200 movs r2, #0
8001de4: 609a str r2, [r3, #8]
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
8001de6: 4b15 ldr r3, [pc, #84] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001de8: 2280 movs r2, #128 @ 0x80
8001dea: 60da str r2, [r3, #12]
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
8001dec: 4b13 ldr r3, [pc, #76] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001dee: f44f 7280 mov.w r2, #256 @ 0x100
8001df2: 611a str r2, [r3, #16]
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
8001df4: 4b11 ldr r3, [pc, #68] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001df6: f44f 6280 mov.w r2, #1024 @ 0x400
8001dfa: 615a str r2, [r3, #20]
hdma_adc1.Init.Mode = DMA_CIRCULAR;
8001dfc: 4b0f ldr r3, [pc, #60] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001dfe: 2220 movs r2, #32
8001e00: 619a str r2, [r3, #24]
hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
8001e02: 4b0e ldr r3, [pc, #56] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001e04: 2200 movs r2, #0
8001e06: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
8001e08: 480c ldr r0, [pc, #48] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001e0a: f000 fed1 bl 8002bb0 <HAL_DMA_Init>
8001e0e: 4603 mov r3, r0
8001e10: 2b00 cmp r3, #0
8001e12: d001 beq.n 8001e18 <HAL_ADC_MspInit+0xd4>
{
Error_Handler();
8001e14: f7ff fd76 bl 8001904 <Error_Handler>
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
8001e18: 687b ldr r3, [r7, #4]
8001e1a: 4a08 ldr r2, [pc, #32] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001e1c: 621a str r2, [r3, #32]
8001e1e: 4a07 ldr r2, [pc, #28] @ (8001e3c <HAL_ADC_MspInit+0xf8>)
8001e20: 687b ldr r3, [r7, #4]
8001e22: 6253 str r3, [r2, #36] @ 0x24
/* USER CODE END ADC1_MspInit 1 */
}
}
8001e24: bf00 nop
8001e26: 3728 adds r7, #40 @ 0x28
8001e28: 46bd mov sp, r7
8001e2a: bd80 pop {r7, pc}
8001e2c: 40012400 .word 0x40012400
8001e30: 40021000 .word 0x40021000
8001e34: 40010800 .word 0x40010800
8001e38: 40010c00 .word 0x40010c00
8001e3c: 200002bc .word 0x200002bc
8001e40: 40020008 .word 0x40020008
08001e44 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001e44: b480 push {r7}
8001e46: b085 sub sp, #20
8001e48: af00 add r7, sp, #0
8001e4a: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
8001e4c: 687b ldr r3, [r7, #4]
8001e4e: 681b ldr r3, [r3, #0]
8001e50: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001e54: d10c bne.n 8001e70 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001e56: 4b11 ldr r3, [pc, #68] @ (8001e9c <HAL_TIM_Base_MspInit+0x58>)
8001e58: 69db ldr r3, [r3, #28]
8001e5a: 4a10 ldr r2, [pc, #64] @ (8001e9c <HAL_TIM_Base_MspInit+0x58>)
8001e5c: f043 0301 orr.w r3, r3, #1
8001e60: 61d3 str r3, [r2, #28]
8001e62: 4b0e ldr r3, [pc, #56] @ (8001e9c <HAL_TIM_Base_MspInit+0x58>)
8001e64: 69db ldr r3, [r3, #28]
8001e66: f003 0301 and.w r3, r3, #1
8001e6a: 60fb str r3, [r7, #12]
8001e6c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
8001e6e: e010 b.n 8001e92 <HAL_TIM_Base_MspInit+0x4e>
else if(htim_base->Instance==TIM4)
8001e70: 687b ldr r3, [r7, #4]
8001e72: 681b ldr r3, [r3, #0]
8001e74: 4a0a ldr r2, [pc, #40] @ (8001ea0 <HAL_TIM_Base_MspInit+0x5c>)
8001e76: 4293 cmp r3, r2
8001e78: d10b bne.n 8001e92 <HAL_TIM_Base_MspInit+0x4e>
__HAL_RCC_TIM4_CLK_ENABLE();
8001e7a: 4b08 ldr r3, [pc, #32] @ (8001e9c <HAL_TIM_Base_MspInit+0x58>)
8001e7c: 69db ldr r3, [r3, #28]
8001e7e: 4a07 ldr r2, [pc, #28] @ (8001e9c <HAL_TIM_Base_MspInit+0x58>)
8001e80: f043 0304 orr.w r3, r3, #4
8001e84: 61d3 str r3, [r2, #28]
8001e86: 4b05 ldr r3, [pc, #20] @ (8001e9c <HAL_TIM_Base_MspInit+0x58>)
8001e88: 69db ldr r3, [r3, #28]
8001e8a: f003 0304 and.w r3, r3, #4
8001e8e: 60bb str r3, [r7, #8]
8001e90: 68bb ldr r3, [r7, #8]
}
8001e92: bf00 nop
8001e94: 3714 adds r7, #20
8001e96: 46bd mov sp, r7
8001e98: bc80 pop {r7}
8001e9a: 4770 bx lr
8001e9c: 40021000 .word 0x40021000
8001ea0: 40000800 .word 0x40000800
08001ea4 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001ea4: b580 push {r7, lr}
8001ea6: b088 sub sp, #32
8001ea8: af00 add r7, sp, #0
8001eaa: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001eac: f107 0310 add.w r3, r7, #16
8001eb0: 2200 movs r2, #0
8001eb2: 601a str r2, [r3, #0]
8001eb4: 605a str r2, [r3, #4]
8001eb6: 609a str r2, [r3, #8]
8001eb8: 60da str r2, [r3, #12]
if(htim->Instance==TIM2)
8001eba: 687b ldr r3, [r7, #4]
8001ebc: 681b ldr r3, [r3, #0]
8001ebe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001ec2: d118 bne.n 8001ef6 <HAL_TIM_MspPostInit+0x52>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001ec4: 4b1d ldr r3, [pc, #116] @ (8001f3c <HAL_TIM_MspPostInit+0x98>)
8001ec6: 699b ldr r3, [r3, #24]
8001ec8: 4a1c ldr r2, [pc, #112] @ (8001f3c <HAL_TIM_MspPostInit+0x98>)
8001eca: f043 0304 orr.w r3, r3, #4
8001ece: 6193 str r3, [r2, #24]
8001ed0: 4b1a ldr r3, [pc, #104] @ (8001f3c <HAL_TIM_MspPostInit+0x98>)
8001ed2: 699b ldr r3, [r3, #24]
8001ed4: f003 0304 and.w r3, r3, #4
8001ed8: 60fb str r3, [r7, #12]
8001eda: 68fb ldr r3, [r7, #12]
PA0-WKUP ------> TIM2_CH1
PA1 ------> TIM2_CH2
PA2 ------> TIM2_CH3
PA3 ------> TIM2_CH4
*/
GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|IN3_Pin|IN4_Pin;
8001edc: 230f movs r3, #15
8001ede: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001ee0: 2302 movs r3, #2
8001ee2: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001ee4: 2302 movs r3, #2
8001ee6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001ee8: f107 0310 add.w r3, r7, #16
8001eec: 4619 mov r1, r3
8001eee: 4814 ldr r0, [pc, #80] @ (8001f40 <HAL_TIM_MspPostInit+0x9c>)
8001ef0: f001 fa4c bl 800338c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
8001ef4: e01d b.n 8001f32 <HAL_TIM_MspPostInit+0x8e>
else if(htim->Instance==TIM4)
8001ef6: 687b ldr r3, [r7, #4]
8001ef8: 681b ldr r3, [r3, #0]
8001efa: 4a12 ldr r2, [pc, #72] @ (8001f44 <HAL_TIM_MspPostInit+0xa0>)
8001efc: 4293 cmp r3, r2
8001efe: d118 bne.n 8001f32 <HAL_TIM_MspPostInit+0x8e>
__HAL_RCC_GPIOB_CLK_ENABLE();
8001f00: 4b0e ldr r3, [pc, #56] @ (8001f3c <HAL_TIM_MspPostInit+0x98>)
8001f02: 699b ldr r3, [r3, #24]
8001f04: 4a0d ldr r2, [pc, #52] @ (8001f3c <HAL_TIM_MspPostInit+0x98>)
8001f06: f043 0308 orr.w r3, r3, #8
8001f0a: 6193 str r3, [r2, #24]
8001f0c: 4b0b ldr r3, [pc, #44] @ (8001f3c <HAL_TIM_MspPostInit+0x98>)
8001f0e: 699b ldr r3, [r3, #24]
8001f10: f003 0308 and.w r3, r3, #8
8001f14: 60bb str r3, [r7, #8]
8001f16: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = IN5_Pin|IN6_Pin|IN7_Pin|IN8_Pin;
8001f18: f44f 7370 mov.w r3, #960 @ 0x3c0
8001f1c: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001f1e: 2302 movs r3, #2
8001f20: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f22: 2302 movs r3, #2
8001f24: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001f26: f107 0310 add.w r3, r7, #16
8001f2a: 4619 mov r1, r3
8001f2c: 4806 ldr r0, [pc, #24] @ (8001f48 <HAL_TIM_MspPostInit+0xa4>)
8001f2e: f001 fa2d bl 800338c <HAL_GPIO_Init>
}
8001f32: bf00 nop
8001f34: 3720 adds r7, #32
8001f36: 46bd mov sp, r7
8001f38: bd80 pop {r7, pc}
8001f3a: bf00 nop
8001f3c: 40021000 .word 0x40021000
8001f40: 40010800 .word 0x40010800
8001f44: 40000800 .word 0x40000800
8001f48: 40010c00 .word 0x40010c00
08001f4c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001f4c: b580 push {r7, lr}
8001f4e: b088 sub sp, #32
8001f50: af00 add r7, sp, #0
8001f52: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001f54: f107 0310 add.w r3, r7, #16
8001f58: 2200 movs r2, #0
8001f5a: 601a str r2, [r3, #0]
8001f5c: 605a str r2, [r3, #4]
8001f5e: 609a str r2, [r3, #8]
8001f60: 60da str r2, [r3, #12]
if(huart->Instance==USART1)
8001f62: 687b ldr r3, [r7, #4]
8001f64: 681b ldr r3, [r3, #0]
8001f66: 4a1c ldr r2, [pc, #112] @ (8001fd8 <HAL_UART_MspInit+0x8c>)
8001f68: 4293 cmp r3, r2
8001f6a: d131 bne.n 8001fd0 <HAL_UART_MspInit+0x84>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8001f6c: 4b1b ldr r3, [pc, #108] @ (8001fdc <HAL_UART_MspInit+0x90>)
8001f6e: 699b ldr r3, [r3, #24]
8001f70: 4a1a ldr r2, [pc, #104] @ (8001fdc <HAL_UART_MspInit+0x90>)
8001f72: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001f76: 6193 str r3, [r2, #24]
8001f78: 4b18 ldr r3, [pc, #96] @ (8001fdc <HAL_UART_MspInit+0x90>)
8001f7a: 699b ldr r3, [r3, #24]
8001f7c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001f80: 60fb str r3, [r7, #12]
8001f82: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001f84: 4b15 ldr r3, [pc, #84] @ (8001fdc <HAL_UART_MspInit+0x90>)
8001f86: 699b ldr r3, [r3, #24]
8001f88: 4a14 ldr r2, [pc, #80] @ (8001fdc <HAL_UART_MspInit+0x90>)
8001f8a: f043 0304 orr.w r3, r3, #4
8001f8e: 6193 str r3, [r2, #24]
8001f90: 4b12 ldr r3, [pc, #72] @ (8001fdc <HAL_UART_MspInit+0x90>)
8001f92: 699b ldr r3, [r3, #24]
8001f94: f003 0304 and.w r3, r3, #4
8001f98: 60bb str r3, [r7, #8]
8001f9a: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
8001f9c: f44f 7300 mov.w r3, #512 @ 0x200
8001fa0: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001fa2: 2302 movs r3, #2
8001fa4: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8001fa6: 2303 movs r3, #3
8001fa8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001faa: f107 0310 add.w r3, r7, #16
8001fae: 4619 mov r1, r3
8001fb0: 480b ldr r0, [pc, #44] @ (8001fe0 <HAL_UART_MspInit+0x94>)
8001fb2: f001 f9eb bl 800338c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_10;
8001fb6: f44f 6380 mov.w r3, #1024 @ 0x400
8001fba: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001fbc: 2300 movs r3, #0
8001fbe: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001fc0: 2300 movs r3, #0
8001fc2: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001fc4: f107 0310 add.w r3, r7, #16
8001fc8: 4619 mov r1, r3
8001fca: 4805 ldr r0, [pc, #20] @ (8001fe0 <HAL_UART_MspInit+0x94>)
8001fcc: f001 f9de bl 800338c <HAL_GPIO_Init>
/* USER CODE END USART1_MspInit 1 */
}
}
8001fd0: bf00 nop
8001fd2: 3720 adds r7, #32
8001fd4: 46bd mov sp, r7
8001fd6: bd80 pop {r7, pc}
8001fd8: 40013800 .word 0x40013800
8001fdc: 40021000 .word 0x40021000
8001fe0: 40010800 .word 0x40010800
08001fe4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001fe4: b480 push {r7}
8001fe6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001fe8: bf00 nop
8001fea: e7fd b.n 8001fe8 <NMI_Handler+0x4>
08001fec <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001fec: b480 push {r7}
8001fee: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001ff0: bf00 nop
8001ff2: e7fd b.n 8001ff0 <HardFault_Handler+0x4>
08001ff4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001ff4: b480 push {r7}
8001ff6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001ff8: bf00 nop
8001ffa: e7fd b.n 8001ff8 <MemManage_Handler+0x4>
08001ffc <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001ffc: b480 push {r7}
8001ffe: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8002000: bf00 nop
8002002: e7fd b.n 8002000 <BusFault_Handler+0x4>
08002004 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8002004: b480 push {r7}
8002006: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8002008: bf00 nop
800200a: e7fd b.n 8002008 <UsageFault_Handler+0x4>
0800200c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800200c: b480 push {r7}
800200e: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8002010: bf00 nop
8002012: 46bd mov sp, r7
8002014: bc80 pop {r7}
8002016: 4770 bx lr
08002018 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8002018: b480 push {r7}
800201a: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800201c: bf00 nop
800201e: 46bd mov sp, r7
8002020: bc80 pop {r7}
8002022: 4770 bx lr
08002024 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8002024: b480 push {r7}
8002026: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8002028: bf00 nop
800202a: 46bd mov sp, r7
800202c: bc80 pop {r7}
800202e: 4770 bx lr
08002030 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002030: b580 push {r7, lr}
8002032: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8002034: f000 f8c0 bl 80021b8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
HAL_SYSTICK_IRQHandler();
8002038: f000 fdb3 bl 8002ba2 <HAL_SYSTICK_IRQHandler>
/* USER CODE END SysTick_IRQn 1 */
}
800203c: bf00 nop
800203e: bd80 pop {r7, pc}
08002040 <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
8002040: b580 push {r7, lr}
8002042: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc1);
8002044: 4802 ldr r0, [pc, #8] @ (8002050 <DMA1_Channel1_IRQHandler+0x10>)
8002046: f000 fe6d bl 8002d24 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
800204a: bf00 nop
800204c: bd80 pop {r7, pc}
800204e: bf00 nop
8002050: 200002bc .word 0x200002bc
08002054 <USB_LP_CAN1_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN RX0 interrupts.
*/
void USB_LP_CAN1_RX0_IRQHandler(void)
{
8002054: b580 push {r7, lr}
8002056: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_FS);
8002058: 4802 ldr r0, [pc, #8] @ (8002064 <USB_LP_CAN1_RX0_IRQHandler+0x10>)
800205a: f001 fc7f bl 800395c <HAL_PCD_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
}
800205e: bf00 nop
8002060: bd80 pop {r7, pc}
8002062: bf00 nop
8002064: 200011dc .word 0x200011dc
08002068 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8002068: b580 push {r7, lr}
800206a: b086 sub sp, #24
800206c: af00 add r7, sp, #0
800206e: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8002070: 4a14 ldr r2, [pc, #80] @ (80020c4 <_sbrk+0x5c>)
8002072: 4b15 ldr r3, [pc, #84] @ (80020c8 <_sbrk+0x60>)
8002074: 1ad3 subs r3, r2, r3
8002076: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8002078: 697b ldr r3, [r7, #20]
800207a: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
800207c: 4b13 ldr r3, [pc, #76] @ (80020cc <_sbrk+0x64>)
800207e: 681b ldr r3, [r3, #0]
8002080: 2b00 cmp r3, #0
8002082: d102 bne.n 800208a <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8002084: 4b11 ldr r3, [pc, #68] @ (80020cc <_sbrk+0x64>)
8002086: 4a12 ldr r2, [pc, #72] @ (80020d0 <_sbrk+0x68>)
8002088: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
800208a: 4b10 ldr r3, [pc, #64] @ (80020cc <_sbrk+0x64>)
800208c: 681a ldr r2, [r3, #0]
800208e: 687b ldr r3, [r7, #4]
8002090: 4413 add r3, r2
8002092: 693a ldr r2, [r7, #16]
8002094: 429a cmp r2, r3
8002096: d207 bcs.n 80020a8 <_sbrk+0x40>
{
errno = ENOMEM;
8002098: f009 f8fc bl 800b294 <__errno>
800209c: 4603 mov r3, r0
800209e: 220c movs r2, #12
80020a0: 601a str r2, [r3, #0]
return (void *)-1;
80020a2: f04f 33ff mov.w r3, #4294967295
80020a6: e009 b.n 80020bc <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
80020a8: 4b08 ldr r3, [pc, #32] @ (80020cc <_sbrk+0x64>)
80020aa: 681b ldr r3, [r3, #0]
80020ac: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80020ae: 4b07 ldr r3, [pc, #28] @ (80020cc <_sbrk+0x64>)
80020b0: 681a ldr r2, [r3, #0]
80020b2: 687b ldr r3, [r7, #4]
80020b4: 4413 add r3, r2
80020b6: 4a05 ldr r2, [pc, #20] @ (80020cc <_sbrk+0x64>)
80020b8: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80020ba: 68fb ldr r3, [r7, #12]
}
80020bc: 4618 mov r0, r3
80020be: 3718 adds r7, #24
80020c0: 46bd mov sp, r7
80020c2: bd80 pop {r7, pc}
80020c4: 20005000 .word 0x20005000
80020c8: 00000400 .word 0x00000400
80020cc: 200003e4 .word 0x200003e4
80020d0: 20001820 .word 0x20001820
080020d4 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80020d4: b480 push {r7}
80020d6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80020d8: bf00 nop
80020da: 46bd mov sp, r7
80020dc: bc80 pop {r7}
80020de: 4770 bx lr
080020e0 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80020e0: f7ff fff8 bl 80020d4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80020e4: 480b ldr r0, [pc, #44] @ (8002114 <LoopFillZerobss+0xe>)
ldr r1, =_edata
80020e6: 490c ldr r1, [pc, #48] @ (8002118 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
80020e8: 4a0c ldr r2, [pc, #48] @ (800211c <LoopFillZerobss+0x16>)
movs r3, #0
80020ea: 2300 movs r3, #0
b LoopCopyDataInit
80020ec: e002 b.n 80020f4 <LoopCopyDataInit>
080020ee <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80020ee: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80020f0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80020f2: 3304 adds r3, #4
080020f4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80020f4: 18c4 adds r4, r0, r3
cmp r4, r1
80020f6: 428c cmp r4, r1
bcc CopyDataInit
80020f8: d3f9 bcc.n 80020ee <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80020fa: 4a09 ldr r2, [pc, #36] @ (8002120 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
80020fc: 4c09 ldr r4, [pc, #36] @ (8002124 <LoopFillZerobss+0x1e>)
movs r3, #0
80020fe: 2300 movs r3, #0
b LoopFillZerobss
8002100: e001 b.n 8002106 <LoopFillZerobss>
08002102 <FillZerobss>:
FillZerobss:
str r3, [r2]
8002102: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002104: 3204 adds r2, #4
08002106 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8002106: 42a2 cmp r2, r4
bcc FillZerobss
8002108: d3fb bcc.n 8002102 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800210a: f009 f8c9 bl 800b2a0 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800210e: f7ff f893 bl 8001238 <main>
bx lr
8002112: 4770 bx lr
ldr r0, =_sdata
8002114: 20000000 .word 0x20000000
ldr r1, =_edata
8002118: 200001d0 .word 0x200001d0
ldr r2, =_sidata
800211c: 0800be94 .word 0x0800be94
ldr r2, =_sbss
8002120: 200001d0 .word 0x200001d0
ldr r4, =_ebss
8002124: 2000181c .word 0x2000181c
08002128 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8002128: e7fe b.n 8002128 <ADC1_2_IRQHandler>
...
0800212c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800212c: b580 push {r7, lr}
800212e: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8002130: 4b08 ldr r3, [pc, #32] @ (8002154 <HAL_Init+0x28>)
8002132: 681b ldr r3, [r3, #0]
8002134: 4a07 ldr r2, [pc, #28] @ (8002154 <HAL_Init+0x28>)
8002136: f043 0310 orr.w r3, r3, #16
800213a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800213c: 2003 movs r0, #3
800213e: f000 fcef bl 8002b20 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002142: 200f movs r0, #15
8002144: f000 f808 bl 8002158 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8002148: f7ff fdca bl 8001ce0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800214c: 2300 movs r3, #0
}
800214e: 4618 mov r0, r3
8002150: bd80 pop {r7, pc}
8002152: bf00 nop
8002154: 40022000 .word 0x40022000
08002158 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002158: b580 push {r7, lr}
800215a: b082 sub sp, #8
800215c: af00 add r7, sp, #0
800215e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8002160: 4b12 ldr r3, [pc, #72] @ (80021ac <HAL_InitTick+0x54>)
8002162: 681a ldr r2, [r3, #0]
8002164: 4b12 ldr r3, [pc, #72] @ (80021b0 <HAL_InitTick+0x58>)
8002166: 781b ldrb r3, [r3, #0]
8002168: 4619 mov r1, r3
800216a: f44f 737a mov.w r3, #1000 @ 0x3e8
800216e: fbb3 f3f1 udiv r3, r3, r1
8002172: fbb2 f3f3 udiv r3, r2, r3
8002176: 4618 mov r0, r3
8002178: f000 fd07 bl 8002b8a <HAL_SYSTICK_Config>
800217c: 4603 mov r3, r0
800217e: 2b00 cmp r3, #0
8002180: d001 beq.n 8002186 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8002182: 2301 movs r3, #1
8002184: e00e b.n 80021a4 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8002186: 687b ldr r3, [r7, #4]
8002188: 2b0f cmp r3, #15
800218a: d80a bhi.n 80021a2 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800218c: 2200 movs r2, #0
800218e: 6879 ldr r1, [r7, #4]
8002190: f04f 30ff mov.w r0, #4294967295
8002194: f000 fccf bl 8002b36 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8002198: 4a06 ldr r2, [pc, #24] @ (80021b4 <HAL_InitTick+0x5c>)
800219a: 687b ldr r3, [r7, #4]
800219c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800219e: 2300 movs r3, #0
80021a0: e000 b.n 80021a4 <HAL_InitTick+0x4c>
return HAL_ERROR;
80021a2: 2301 movs r3, #1
}
80021a4: 4618 mov r0, r3
80021a6: 3708 adds r7, #8
80021a8: 46bd mov sp, r7
80021aa: bd80 pop {r7, pc}
80021ac: 20000004 .word 0x20000004
80021b0: 2000000c .word 0x2000000c
80021b4: 20000008 .word 0x20000008
080021b8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80021b8: b480 push {r7}
80021ba: af00 add r7, sp, #0
uwTick += uwTickFreq;
80021bc: 4b05 ldr r3, [pc, #20] @ (80021d4 <HAL_IncTick+0x1c>)
80021be: 781b ldrb r3, [r3, #0]
80021c0: 461a mov r2, r3
80021c2: 4b05 ldr r3, [pc, #20] @ (80021d8 <HAL_IncTick+0x20>)
80021c4: 681b ldr r3, [r3, #0]
80021c6: 4413 add r3, r2
80021c8: 4a03 ldr r2, [pc, #12] @ (80021d8 <HAL_IncTick+0x20>)
80021ca: 6013 str r3, [r2, #0]
}
80021cc: bf00 nop
80021ce: 46bd mov sp, r7
80021d0: bc80 pop {r7}
80021d2: 4770 bx lr
80021d4: 2000000c .word 0x2000000c
80021d8: 200003e8 .word 0x200003e8
080021dc <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80021dc: b480 push {r7}
80021de: af00 add r7, sp, #0
return uwTick;
80021e0: 4b02 ldr r3, [pc, #8] @ (80021ec <HAL_GetTick+0x10>)
80021e2: 681b ldr r3, [r3, #0]
}
80021e4: 4618 mov r0, r3
80021e6: 46bd mov sp, r7
80021e8: bc80 pop {r7}
80021ea: 4770 bx lr
80021ec: 200003e8 .word 0x200003e8
080021f0 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80021f0: b580 push {r7, lr}
80021f2: b086 sub sp, #24
80021f4: af00 add r7, sp, #0
80021f6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80021f8: 2300 movs r3, #0
80021fa: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
80021fc: 2300 movs r3, #0
80021fe: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
8002200: 2300 movs r3, #0
8002202: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
8002204: 2300 movs r3, #0
8002206: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
8002208: 687b ldr r3, [r7, #4]
800220a: 2b00 cmp r3, #0
800220c: d101 bne.n 8002212 <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
800220e: 2301 movs r3, #1
8002210: e0be b.n 8002390 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8002212: 687b ldr r3, [r7, #4]
8002214: 689b ldr r3, [r3, #8]
8002216: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8002218: 687b ldr r3, [r7, #4]
800221a: 6a9b ldr r3, [r3, #40] @ 0x28
800221c: 2b00 cmp r3, #0
800221e: d109 bne.n 8002234 <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8002220: 687b ldr r3, [r7, #4]
8002222: 2200 movs r2, #0
8002224: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8002226: 687b ldr r3, [r7, #4]
8002228: 2200 movs r2, #0
800222a: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
800222e: 6878 ldr r0, [r7, #4]
8002230: f7ff fd88 bl 8001d44 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8002234: 6878 ldr r0, [r7, #4]
8002236: f000 faff bl 8002838 <ADC_ConversionStop_Disable>
800223a: 4603 mov r3, r0
800223c: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
800223e: 687b ldr r3, [r7, #4]
8002240: 6a9b ldr r3, [r3, #40] @ 0x28
8002242: f003 0310 and.w r3, r3, #16
8002246: 2b00 cmp r3, #0
8002248: f040 8099 bne.w 800237e <HAL_ADC_Init+0x18e>
800224c: 7dfb ldrb r3, [r7, #23]
800224e: 2b00 cmp r3, #0
8002250: f040 8095 bne.w 800237e <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002254: 687b ldr r3, [r7, #4]
8002256: 6a9b ldr r3, [r3, #40] @ 0x28
8002258: f423 5388 bic.w r3, r3, #4352 @ 0x1100
800225c: f023 0302 bic.w r3, r3, #2
8002260: f043 0202 orr.w r2, r3, #2
8002264: 687b ldr r3, [r7, #4]
8002266: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8002268: 687b ldr r3, [r7, #4]
800226a: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
800226c: 687b ldr r3, [r7, #4]
800226e: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8002270: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8002272: 687b ldr r3, [r7, #4]
8002274: 7b1b ldrb r3, [r3, #12]
8002276: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002278: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
800227a: 68ba ldr r2, [r7, #8]
800227c: 4313 orrs r3, r2
800227e: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8002280: 687b ldr r3, [r7, #4]
8002282: 689b ldr r3, [r3, #8]
8002284: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002288: d003 beq.n 8002292 <HAL_ADC_Init+0xa2>
800228a: 687b ldr r3, [r7, #4]
800228c: 689b ldr r3, [r3, #8]
800228e: 2b01 cmp r3, #1
8002290: d102 bne.n 8002298 <HAL_ADC_Init+0xa8>
8002292: f44f 7380 mov.w r3, #256 @ 0x100
8002296: e000 b.n 800229a <HAL_ADC_Init+0xaa>
8002298: 2300 movs r3, #0
800229a: 693a ldr r2, [r7, #16]
800229c: 4313 orrs r3, r2
800229e: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80022a0: 687b ldr r3, [r7, #4]
80022a2: 7d1b ldrb r3, [r3, #20]
80022a4: 2b01 cmp r3, #1
80022a6: d119 bne.n 80022dc <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
80022a8: 687b ldr r3, [r7, #4]
80022aa: 7b1b ldrb r3, [r3, #12]
80022ac: 2b00 cmp r3, #0
80022ae: d109 bne.n 80022c4 <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
80022b0: 687b ldr r3, [r7, #4]
80022b2: 699b ldr r3, [r3, #24]
80022b4: 3b01 subs r3, #1
80022b6: 035a lsls r2, r3, #13
80022b8: 693b ldr r3, [r7, #16]
80022ba: 4313 orrs r3, r2
80022bc: f443 6300 orr.w r3, r3, #2048 @ 0x800
80022c0: 613b str r3, [r7, #16]
80022c2: e00b b.n 80022dc <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80022c4: 687b ldr r3, [r7, #4]
80022c6: 6a9b ldr r3, [r3, #40] @ 0x28
80022c8: f043 0220 orr.w r2, r3, #32
80022cc: 687b ldr r3, [r7, #4]
80022ce: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80022d0: 687b ldr r3, [r7, #4]
80022d2: 6adb ldr r3, [r3, #44] @ 0x2c
80022d4: f043 0201 orr.w r2, r3, #1
80022d8: 687b ldr r3, [r7, #4]
80022da: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
80022dc: 687b ldr r3, [r7, #4]
80022de: 681b ldr r3, [r3, #0]
80022e0: 685b ldr r3, [r3, #4]
80022e2: f423 4169 bic.w r1, r3, #59648 @ 0xe900
80022e6: 687b ldr r3, [r7, #4]
80022e8: 681b ldr r3, [r3, #0]
80022ea: 693a ldr r2, [r7, #16]
80022ec: 430a orrs r2, r1
80022ee: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
80022f0: 687b ldr r3, [r7, #4]
80022f2: 681b ldr r3, [r3, #0]
80022f4: 689a ldr r2, [r3, #8]
80022f6: 4b28 ldr r3, [pc, #160] @ (8002398 <HAL_ADC_Init+0x1a8>)
80022f8: 4013 ands r3, r2
80022fa: 687a ldr r2, [r7, #4]
80022fc: 6812 ldr r2, [r2, #0]
80022fe: 68b9 ldr r1, [r7, #8]
8002300: 430b orrs r3, r1
8002302: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
8002304: 687b ldr r3, [r7, #4]
8002306: 689b ldr r3, [r3, #8]
8002308: f5b3 7f80 cmp.w r3, #256 @ 0x100
800230c: d003 beq.n 8002316 <HAL_ADC_Init+0x126>
800230e: 687b ldr r3, [r7, #4]
8002310: 689b ldr r3, [r3, #8]
8002312: 2b01 cmp r3, #1
8002314: d104 bne.n 8002320 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
8002316: 687b ldr r3, [r7, #4]
8002318: 691b ldr r3, [r3, #16]
800231a: 3b01 subs r3, #1
800231c: 051b lsls r3, r3, #20
800231e: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
8002320: 687b ldr r3, [r7, #4]
8002322: 681b ldr r3, [r3, #0]
8002324: 6adb ldr r3, [r3, #44] @ 0x2c
8002326: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
800232a: 687b ldr r3, [r7, #4]
800232c: 681b ldr r3, [r3, #0]
800232e: 68fa ldr r2, [r7, #12]
8002330: 430a orrs r2, r1
8002332: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002334: 687b ldr r3, [r7, #4]
8002336: 681b ldr r3, [r3, #0]
8002338: 689a ldr r2, [r3, #8]
800233a: 4b18 ldr r3, [pc, #96] @ (800239c <HAL_ADC_Init+0x1ac>)
800233c: 4013 ands r3, r2
800233e: 68ba ldr r2, [r7, #8]
8002340: 429a cmp r2, r3
8002342: d10b bne.n 800235c <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002344: 687b ldr r3, [r7, #4]
8002346: 2200 movs r2, #0
8002348: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800234a: 687b ldr r3, [r7, #4]
800234c: 6a9b ldr r3, [r3, #40] @ 0x28
800234e: f023 0303 bic.w r3, r3, #3
8002352: f043 0201 orr.w r2, r3, #1
8002356: 687b ldr r3, [r7, #4]
8002358: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800235a: e018 b.n 800238e <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
800235c: 687b ldr r3, [r7, #4]
800235e: 6a9b ldr r3, [r3, #40] @ 0x28
8002360: f023 0312 bic.w r3, r3, #18
8002364: f043 0210 orr.w r2, r3, #16
8002368: 687b ldr r3, [r7, #4]
800236a: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800236c: 687b ldr r3, [r7, #4]
800236e: 6adb ldr r3, [r3, #44] @ 0x2c
8002370: f043 0201 orr.w r2, r3, #1
8002374: 687b ldr r3, [r7, #4]
8002376: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8002378: 2301 movs r3, #1
800237a: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800237c: e007 b.n 800238e <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800237e: 687b ldr r3, [r7, #4]
8002380: 6a9b ldr r3, [r3, #40] @ 0x28
8002382: f043 0210 orr.w r2, r3, #16
8002386: 687b ldr r3, [r7, #4]
8002388: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
800238a: 2301 movs r3, #1
800238c: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800238e: 7dfb ldrb r3, [r7, #23]
}
8002390: 4618 mov r0, r3
8002392: 3718 adds r7, #24
8002394: 46bd mov sp, r7
8002396: bd80 pop {r7, pc}
8002398: ffe1f7fd .word 0xffe1f7fd
800239c: ff1f0efe .word 0xff1f0efe
080023a0 <HAL_ADC_Start_DMA>:
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
80023a0: b580 push {r7, lr}
80023a2: b086 sub sp, #24
80023a4: af00 add r7, sp, #0
80023a6: 60f8 str r0, [r7, #12]
80023a8: 60b9 str r1, [r7, #8]
80023aa: 607a str r2, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80023ac: 2300 movs r3, #0
80023ae: 75fb strb r3, [r7, #23]
assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
/* Verification if multimode is disabled (for devices with several ADC) */
/* If multimode is enabled, dedicated function multimode conversion */
/* start DMA must be used. */
if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
80023b0: 68fb ldr r3, [r7, #12]
80023b2: 681b ldr r3, [r3, #0]
80023b4: 4a64 ldr r2, [pc, #400] @ (8002548 <HAL_ADC_Start_DMA+0x1a8>)
80023b6: 4293 cmp r3, r2
80023b8: d004 beq.n 80023c4 <HAL_ADC_Start_DMA+0x24>
80023ba: 68fb ldr r3, [r7, #12]
80023bc: 681b ldr r3, [r3, #0]
80023be: 4a63 ldr r2, [pc, #396] @ (800254c <HAL_ADC_Start_DMA+0x1ac>)
80023c0: 4293 cmp r3, r2
80023c2: d106 bne.n 80023d2 <HAL_ADC_Start_DMA+0x32>
80023c4: 4b60 ldr r3, [pc, #384] @ (8002548 <HAL_ADC_Start_DMA+0x1a8>)
80023c6: 685b ldr r3, [r3, #4]
80023c8: f403 2370 and.w r3, r3, #983040 @ 0xf0000
80023cc: 2b00 cmp r3, #0
80023ce: f040 80b3 bne.w 8002538 <HAL_ADC_Start_DMA+0x198>
{
/* Process locked */
__HAL_LOCK(hadc);
80023d2: 68fb ldr r3, [r7, #12]
80023d4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80023d8: 2b01 cmp r3, #1
80023da: d101 bne.n 80023e0 <HAL_ADC_Start_DMA+0x40>
80023dc: 2302 movs r3, #2
80023de: e0ae b.n 800253e <HAL_ADC_Start_DMA+0x19e>
80023e0: 68fb ldr r3, [r7, #12]
80023e2: 2201 movs r2, #1
80023e4: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
80023e8: 68f8 ldr r0, [r7, #12]
80023ea: f000 f9cb bl 8002784 <ADC_Enable>
80023ee: 4603 mov r3, r0
80023f0: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
80023f2: 7dfb ldrb r3, [r7, #23]
80023f4: 2b00 cmp r3, #0
80023f6: f040 809a bne.w 800252e <HAL_ADC_Start_DMA+0x18e>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
80023fa: 68fb ldr r3, [r7, #12]
80023fc: 6a9b ldr r3, [r3, #40] @ 0x28
80023fe: f423 6370 bic.w r3, r3, #3840 @ 0xf00
8002402: f023 0301 bic.w r3, r3, #1
8002406: f443 7280 orr.w r2, r3, #256 @ 0x100
800240a: 68fb ldr r3, [r7, #12]
800240c: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_REG_BUSY);
/* Set group injected state (from auto-injection) and multimode state */
/* for all cases of multimode: independent mode, multimode ADC master */
/* or multimode ADC slave (for devices with several ADCs): */
if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
800240e: 68fb ldr r3, [r7, #12]
8002410: 681b ldr r3, [r3, #0]
8002412: 4a4e ldr r2, [pc, #312] @ (800254c <HAL_ADC_Start_DMA+0x1ac>)
8002414: 4293 cmp r3, r2
8002416: d105 bne.n 8002424 <HAL_ADC_Start_DMA+0x84>
8002418: 4b4b ldr r3, [pc, #300] @ (8002548 <HAL_ADC_Start_DMA+0x1a8>)
800241a: 685b ldr r3, [r3, #4]
800241c: f403 2370 and.w r3, r3, #983040 @ 0xf0000
8002420: 2b00 cmp r3, #0
8002422: d115 bne.n 8002450 <HAL_ADC_Start_DMA+0xb0>
{
/* Set ADC state (ADC independent or master) */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002424: 68fb ldr r3, [r7, #12]
8002426: 6a9b ldr r3, [r3, #40] @ 0x28
8002428: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
800242c: 68fb ldr r3, [r7, #12]
800242e: 629a str r2, [r3, #40] @ 0x28
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8002430: 68fb ldr r3, [r7, #12]
8002432: 681b ldr r3, [r3, #0]
8002434: 685b ldr r3, [r3, #4]
8002436: f403 6380 and.w r3, r3, #1024 @ 0x400
800243a: 2b00 cmp r3, #0
800243c: d026 beq.n 800248c <HAL_ADC_Start_DMA+0xec>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800243e: 68fb ldr r3, [r7, #12]
8002440: 6a9b ldr r3, [r3, #40] @ 0x28
8002442: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002446: f443 5280 orr.w r2, r3, #4096 @ 0x1000
800244a: 68fb ldr r3, [r7, #12]
800244c: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
800244e: e01d b.n 800248c <HAL_ADC_Start_DMA+0xec>
}
}
else
{
/* Set ADC state (ADC slave) */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002450: 68fb ldr r3, [r7, #12]
8002452: 6a9b ldr r3, [r3, #40] @ 0x28
8002454: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
8002458: 68fb ldr r3, [r7, #12]
800245a: 629a str r2, [r3, #40] @ 0x28
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
800245c: 68fb ldr r3, [r7, #12]
800245e: 681b ldr r3, [r3, #0]
8002460: 4a39 ldr r2, [pc, #228] @ (8002548 <HAL_ADC_Start_DMA+0x1a8>)
8002462: 4293 cmp r3, r2
8002464: d004 beq.n 8002470 <HAL_ADC_Start_DMA+0xd0>
8002466: 68fb ldr r3, [r7, #12]
8002468: 681b ldr r3, [r3, #0]
800246a: 4a38 ldr r2, [pc, #224] @ (800254c <HAL_ADC_Start_DMA+0x1ac>)
800246c: 4293 cmp r3, r2
800246e: d10d bne.n 800248c <HAL_ADC_Start_DMA+0xec>
8002470: 4b35 ldr r3, [pc, #212] @ (8002548 <HAL_ADC_Start_DMA+0x1a8>)
8002472: 685b ldr r3, [r3, #4]
8002474: f403 6380 and.w r3, r3, #1024 @ 0x400
8002478: 2b00 cmp r3, #0
800247a: d007 beq.n 800248c <HAL_ADC_Start_DMA+0xec>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800247c: 68fb ldr r3, [r7, #12]
800247e: 6a9b ldr r3, [r3, #40] @ 0x28
8002480: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002484: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8002488: 68fb ldr r3, [r7, #12]
800248a: 629a str r2, [r3, #40] @ 0x28
}
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
800248c: 68fb ldr r3, [r7, #12]
800248e: 6a9b ldr r3, [r3, #40] @ 0x28
8002490: f403 5380 and.w r3, r3, #4096 @ 0x1000
8002494: 2b00 cmp r3, #0
8002496: d006 beq.n 80024a6 <HAL_ADC_Start_DMA+0x106>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8002498: 68fb ldr r3, [r7, #12]
800249a: 6adb ldr r3, [r3, #44] @ 0x2c
800249c: f023 0206 bic.w r2, r3, #6
80024a0: 68fb ldr r3, [r7, #12]
80024a2: 62da str r2, [r3, #44] @ 0x2c
80024a4: e002 b.n 80024ac <HAL_ADC_Start_DMA+0x10c>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80024a6: 68fb ldr r3, [r7, #12]
80024a8: 2200 movs r2, #0
80024aa: 62da str r2, [r3, #44] @ 0x2c
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80024ac: 68fb ldr r3, [r7, #12]
80024ae: 2200 movs r2, #0
80024b0: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
80024b4: 68fb ldr r3, [r7, #12]
80024b6: 6a1b ldr r3, [r3, #32]
80024b8: 4a25 ldr r2, [pc, #148] @ (8002550 <HAL_ADC_Start_DMA+0x1b0>)
80024ba: 629a str r2, [r3, #40] @ 0x28
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
80024bc: 68fb ldr r3, [r7, #12]
80024be: 6a1b ldr r3, [r3, #32]
80024c0: 4a24 ldr r2, [pc, #144] @ (8002554 <HAL_ADC_Start_DMA+0x1b4>)
80024c2: 62da str r2, [r3, #44] @ 0x2c
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
80024c4: 68fb ldr r3, [r7, #12]
80024c6: 6a1b ldr r3, [r3, #32]
80024c8: 4a23 ldr r2, [pc, #140] @ (8002558 <HAL_ADC_Start_DMA+0x1b8>)
80024ca: 631a str r2, [r3, #48] @ 0x30
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
80024cc: 68fb ldr r3, [r7, #12]
80024ce: 681b ldr r3, [r3, #0]
80024d0: f06f 0202 mvn.w r2, #2
80024d4: 601a str r2, [r3, #0]
/* Enable ADC DMA mode */
SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
80024d6: 68fb ldr r3, [r7, #12]
80024d8: 681b ldr r3, [r3, #0]
80024da: 689a ldr r2, [r3, #8]
80024dc: 68fb ldr r3, [r7, #12]
80024de: 681b ldr r3, [r3, #0]
80024e0: f442 7280 orr.w r2, r2, #256 @ 0x100
80024e4: 609a str r2, [r3, #8]
/* Start the DMA channel */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
80024e6: 68fb ldr r3, [r7, #12]
80024e8: 6a18 ldr r0, [r3, #32]
80024ea: 68fb ldr r3, [r7, #12]
80024ec: 681b ldr r3, [r3, #0]
80024ee: 334c adds r3, #76 @ 0x4c
80024f0: 4619 mov r1, r3
80024f2: 68ba ldr r2, [r7, #8]
80024f4: 687b ldr r3, [r7, #4]
80024f6: f000 fbb5 bl 8002c64 <HAL_DMA_Start_IT>
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
80024fa: 68fb ldr r3, [r7, #12]
80024fc: 681b ldr r3, [r3, #0]
80024fe: 689b ldr r3, [r3, #8]
8002500: f403 2360 and.w r3, r3, #917504 @ 0xe0000
8002504: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000
8002508: d108 bne.n 800251c <HAL_ADC_Start_DMA+0x17c>
{
/* Start ADC conversion on regular group with SW start */
SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
800250a: 68fb ldr r3, [r7, #12]
800250c: 681b ldr r3, [r3, #0]
800250e: 689a ldr r2, [r3, #8]
8002510: 68fb ldr r3, [r7, #12]
8002512: 681b ldr r3, [r3, #0]
8002514: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000
8002518: 609a str r2, [r3, #8]
if (tmp_hal_status == HAL_OK)
800251a: e00f b.n 800253c <HAL_ADC_Start_DMA+0x19c>
}
else
{
/* Start ADC conversion on regular group with external trigger */
SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
800251c: 68fb ldr r3, [r7, #12]
800251e: 681b ldr r3, [r3, #0]
8002520: 689a ldr r2, [r3, #8]
8002522: 68fb ldr r3, [r7, #12]
8002524: 681b ldr r3, [r3, #0]
8002526: f442 1280 orr.w r2, r2, #1048576 @ 0x100000
800252a: 609a str r2, [r3, #8]
if (tmp_hal_status == HAL_OK)
800252c: e006 b.n 800253c <HAL_ADC_Start_DMA+0x19c>
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
800252e: 68fb ldr r3, [r7, #12]
8002530: 2200 movs r2, #0
8002532: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (tmp_hal_status == HAL_OK)
8002536: e001 b.n 800253c <HAL_ADC_Start_DMA+0x19c>
}
}
else
{
tmp_hal_status = HAL_ERROR;
8002538: 2301 movs r3, #1
800253a: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800253c: 7dfb ldrb r3, [r7, #23]
}
800253e: 4618 mov r0, r3
8002540: 3718 adds r7, #24
8002542: 46bd mov sp, r7
8002544: bd80 pop {r7, pc}
8002546: bf00 nop
8002548: 40012400 .word 0x40012400
800254c: 40012800 .word 0x40012800
8002550: 080028bb .word 0x080028bb
8002554: 08002937 .word 0x08002937
8002558: 08002953 .word 0x08002953
0800255c <HAL_ADC_ConvCpltCallback>:
* @brief Conversion complete callback in non blocking mode
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
800255c: b480 push {r7}
800255e: b083 sub sp, #12
8002560: af00 add r7, sp, #0
8002562: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
8002564: bf00 nop
8002566: 370c adds r7, #12
8002568: 46bd mov sp, r7
800256a: bc80 pop {r7}
800256c: 4770 bx lr
0800256e <HAL_ADC_ConvHalfCpltCallback>:
* @brief Conversion DMA half-transfer callback in non blocking mode
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
800256e: b480 push {r7}
8002570: b083 sub sp, #12
8002572: af00 add r7, sp, #0
8002574: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
8002576: bf00 nop
8002578: 370c adds r7, #12
800257a: 46bd mov sp, r7
800257c: bc80 pop {r7}
800257e: 4770 bx lr
08002580 <HAL_ADC_ErrorCallback>:
* (ADC conversion with interruption or transfer by DMA)
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
8002580: b480 push {r7}
8002582: b083 sub sp, #12
8002584: af00 add r7, sp, #0
8002586: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
8002588: bf00 nop
800258a: 370c adds r7, #12
800258c: 46bd mov sp, r7
800258e: bc80 pop {r7}
8002590: 4770 bx lr
...
08002594 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8002594: b480 push {r7}
8002596: b085 sub sp, #20
8002598: af00 add r7, sp, #0
800259a: 6078 str r0, [r7, #4]
800259c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800259e: 2300 movs r3, #0
80025a0: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
80025a2: 2300 movs r3, #0
80025a4: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
80025a6: 687b ldr r3, [r7, #4]
80025a8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80025ac: 2b01 cmp r3, #1
80025ae: d101 bne.n 80025b4 <HAL_ADC_ConfigChannel+0x20>
80025b0: 2302 movs r3, #2
80025b2: e0dc b.n 800276e <HAL_ADC_ConfigChannel+0x1da>
80025b4: 687b ldr r3, [r7, #4]
80025b6: 2201 movs r2, #1
80025b8: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
80025bc: 683b ldr r3, [r7, #0]
80025be: 685b ldr r3, [r3, #4]
80025c0: 2b06 cmp r3, #6
80025c2: d81c bhi.n 80025fe <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
80025c4: 687b ldr r3, [r7, #4]
80025c6: 681b ldr r3, [r3, #0]
80025c8: 6b59 ldr r1, [r3, #52] @ 0x34
80025ca: 683b ldr r3, [r7, #0]
80025cc: 685a ldr r2, [r3, #4]
80025ce: 4613 mov r3, r2
80025d0: 009b lsls r3, r3, #2
80025d2: 4413 add r3, r2
80025d4: 3b05 subs r3, #5
80025d6: 221f movs r2, #31
80025d8: fa02 f303 lsl.w r3, r2, r3
80025dc: 43db mvns r3, r3
80025de: 4019 ands r1, r3
80025e0: 683b ldr r3, [r7, #0]
80025e2: 6818 ldr r0, [r3, #0]
80025e4: 683b ldr r3, [r7, #0]
80025e6: 685a ldr r2, [r3, #4]
80025e8: 4613 mov r3, r2
80025ea: 009b lsls r3, r3, #2
80025ec: 4413 add r3, r2
80025ee: 3b05 subs r3, #5
80025f0: fa00 f203 lsl.w r2, r0, r3
80025f4: 687b ldr r3, [r7, #4]
80025f6: 681b ldr r3, [r3, #0]
80025f8: 430a orrs r2, r1
80025fa: 635a str r2, [r3, #52] @ 0x34
80025fc: e03c b.n 8002678 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
80025fe: 683b ldr r3, [r7, #0]
8002600: 685b ldr r3, [r3, #4]
8002602: 2b0c cmp r3, #12
8002604: d81c bhi.n 8002640 <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
8002606: 687b ldr r3, [r7, #4]
8002608: 681b ldr r3, [r3, #0]
800260a: 6b19 ldr r1, [r3, #48] @ 0x30
800260c: 683b ldr r3, [r7, #0]
800260e: 685a ldr r2, [r3, #4]
8002610: 4613 mov r3, r2
8002612: 009b lsls r3, r3, #2
8002614: 4413 add r3, r2
8002616: 3b23 subs r3, #35 @ 0x23
8002618: 221f movs r2, #31
800261a: fa02 f303 lsl.w r3, r2, r3
800261e: 43db mvns r3, r3
8002620: 4019 ands r1, r3
8002622: 683b ldr r3, [r7, #0]
8002624: 6818 ldr r0, [r3, #0]
8002626: 683b ldr r3, [r7, #0]
8002628: 685a ldr r2, [r3, #4]
800262a: 4613 mov r3, r2
800262c: 009b lsls r3, r3, #2
800262e: 4413 add r3, r2
8002630: 3b23 subs r3, #35 @ 0x23
8002632: fa00 f203 lsl.w r2, r0, r3
8002636: 687b ldr r3, [r7, #4]
8002638: 681b ldr r3, [r3, #0]
800263a: 430a orrs r2, r1
800263c: 631a str r2, [r3, #48] @ 0x30
800263e: e01b b.n 8002678 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
8002640: 687b ldr r3, [r7, #4]
8002642: 681b ldr r3, [r3, #0]
8002644: 6ad9 ldr r1, [r3, #44] @ 0x2c
8002646: 683b ldr r3, [r7, #0]
8002648: 685a ldr r2, [r3, #4]
800264a: 4613 mov r3, r2
800264c: 009b lsls r3, r3, #2
800264e: 4413 add r3, r2
8002650: 3b41 subs r3, #65 @ 0x41
8002652: 221f movs r2, #31
8002654: fa02 f303 lsl.w r3, r2, r3
8002658: 43db mvns r3, r3
800265a: 4019 ands r1, r3
800265c: 683b ldr r3, [r7, #0]
800265e: 6818 ldr r0, [r3, #0]
8002660: 683b ldr r3, [r7, #0]
8002662: 685a ldr r2, [r3, #4]
8002664: 4613 mov r3, r2
8002666: 009b lsls r3, r3, #2
8002668: 4413 add r3, r2
800266a: 3b41 subs r3, #65 @ 0x41
800266c: fa00 f203 lsl.w r2, r0, r3
8002670: 687b ldr r3, [r7, #4]
8002672: 681b ldr r3, [r3, #0]
8002674: 430a orrs r2, r1
8002676: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8002678: 683b ldr r3, [r7, #0]
800267a: 681b ldr r3, [r3, #0]
800267c: 2b09 cmp r3, #9
800267e: d91c bls.n 80026ba <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
8002680: 687b ldr r3, [r7, #4]
8002682: 681b ldr r3, [r3, #0]
8002684: 68d9 ldr r1, [r3, #12]
8002686: 683b ldr r3, [r7, #0]
8002688: 681a ldr r2, [r3, #0]
800268a: 4613 mov r3, r2
800268c: 005b lsls r3, r3, #1
800268e: 4413 add r3, r2
8002690: 3b1e subs r3, #30
8002692: 2207 movs r2, #7
8002694: fa02 f303 lsl.w r3, r2, r3
8002698: 43db mvns r3, r3
800269a: 4019 ands r1, r3
800269c: 683b ldr r3, [r7, #0]
800269e: 6898 ldr r0, [r3, #8]
80026a0: 683b ldr r3, [r7, #0]
80026a2: 681a ldr r2, [r3, #0]
80026a4: 4613 mov r3, r2
80026a6: 005b lsls r3, r3, #1
80026a8: 4413 add r3, r2
80026aa: 3b1e subs r3, #30
80026ac: fa00 f203 lsl.w r2, r0, r3
80026b0: 687b ldr r3, [r7, #4]
80026b2: 681b ldr r3, [r3, #0]
80026b4: 430a orrs r2, r1
80026b6: 60da str r2, [r3, #12]
80026b8: e019 b.n 80026ee <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
80026ba: 687b ldr r3, [r7, #4]
80026bc: 681b ldr r3, [r3, #0]
80026be: 6919 ldr r1, [r3, #16]
80026c0: 683b ldr r3, [r7, #0]
80026c2: 681a ldr r2, [r3, #0]
80026c4: 4613 mov r3, r2
80026c6: 005b lsls r3, r3, #1
80026c8: 4413 add r3, r2
80026ca: 2207 movs r2, #7
80026cc: fa02 f303 lsl.w r3, r2, r3
80026d0: 43db mvns r3, r3
80026d2: 4019 ands r1, r3
80026d4: 683b ldr r3, [r7, #0]
80026d6: 6898 ldr r0, [r3, #8]
80026d8: 683b ldr r3, [r7, #0]
80026da: 681a ldr r2, [r3, #0]
80026dc: 4613 mov r3, r2
80026de: 005b lsls r3, r3, #1
80026e0: 4413 add r3, r2
80026e2: fa00 f203 lsl.w r2, r0, r3
80026e6: 687b ldr r3, [r7, #4]
80026e8: 681b ldr r3, [r3, #0]
80026ea: 430a orrs r2, r1
80026ec: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80026ee: 683b ldr r3, [r7, #0]
80026f0: 681b ldr r3, [r3, #0]
80026f2: 2b10 cmp r3, #16
80026f4: d003 beq.n 80026fe <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
80026f6: 683b ldr r3, [r7, #0]
80026f8: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80026fa: 2b11 cmp r3, #17
80026fc: d132 bne.n 8002764 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
80026fe: 687b ldr r3, [r7, #4]
8002700: 681b ldr r3, [r3, #0]
8002702: 4a1d ldr r2, [pc, #116] @ (8002778 <HAL_ADC_ConfigChannel+0x1e4>)
8002704: 4293 cmp r3, r2
8002706: d125 bne.n 8002754 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
8002708: 687b ldr r3, [r7, #4]
800270a: 681b ldr r3, [r3, #0]
800270c: 689b ldr r3, [r3, #8]
800270e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002712: 2b00 cmp r3, #0
8002714: d126 bne.n 8002764 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
8002716: 687b ldr r3, [r7, #4]
8002718: 681b ldr r3, [r3, #0]
800271a: 689a ldr r2, [r3, #8]
800271c: 687b ldr r3, [r7, #4]
800271e: 681b ldr r3, [r3, #0]
8002720: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8002724: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8002726: 683b ldr r3, [r7, #0]
8002728: 681b ldr r3, [r3, #0]
800272a: 2b10 cmp r3, #16
800272c: d11a bne.n 8002764 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
800272e: 4b13 ldr r3, [pc, #76] @ (800277c <HAL_ADC_ConfigChannel+0x1e8>)
8002730: 681b ldr r3, [r3, #0]
8002732: 4a13 ldr r2, [pc, #76] @ (8002780 <HAL_ADC_ConfigChannel+0x1ec>)
8002734: fba2 2303 umull r2, r3, r2, r3
8002738: 0c9a lsrs r2, r3, #18
800273a: 4613 mov r3, r2
800273c: 009b lsls r3, r3, #2
800273e: 4413 add r3, r2
8002740: 005b lsls r3, r3, #1
8002742: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8002744: e002 b.n 800274c <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
8002746: 68bb ldr r3, [r7, #8]
8002748: 3b01 subs r3, #1
800274a: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
800274c: 68bb ldr r3, [r7, #8]
800274e: 2b00 cmp r3, #0
8002750: d1f9 bne.n 8002746 <HAL_ADC_ConfigChannel+0x1b2>
8002752: e007 b.n 8002764 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002754: 687b ldr r3, [r7, #4]
8002756: 6a9b ldr r3, [r3, #40] @ 0x28
8002758: f043 0220 orr.w r2, r3, #32
800275c: 687b ldr r3, [r7, #4]
800275e: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8002760: 2301 movs r3, #1
8002762: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002764: 687b ldr r3, [r7, #4]
8002766: 2200 movs r2, #0
8002768: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
800276c: 7bfb ldrb r3, [r7, #15]
}
800276e: 4618 mov r0, r3
8002770: 3714 adds r7, #20
8002772: 46bd mov sp, r7
8002774: bc80 pop {r7}
8002776: 4770 bx lr
8002778: 40012400 .word 0x40012400
800277c: 20000004 .word 0x20000004
8002780: 431bde83 .word 0x431bde83
08002784 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
8002784: b580 push {r7, lr}
8002786: b084 sub sp, #16
8002788: af00 add r7, sp, #0
800278a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800278c: 2300 movs r3, #0
800278e: 60fb str r3, [r7, #12]
__IO uint32_t wait_loop_index = 0U;
8002790: 2300 movs r3, #0
8002792: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (ADC_IS_ENABLE(hadc) == RESET)
8002794: 687b ldr r3, [r7, #4]
8002796: 681b ldr r3, [r3, #0]
8002798: 689b ldr r3, [r3, #8]
800279a: f003 0301 and.w r3, r3, #1
800279e: 2b01 cmp r3, #1
80027a0: d040 beq.n 8002824 <ADC_Enable+0xa0>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
80027a2: 687b ldr r3, [r7, #4]
80027a4: 681b ldr r3, [r3, #0]
80027a6: 689a ldr r2, [r3, #8]
80027a8: 687b ldr r3, [r7, #4]
80027aa: 681b ldr r3, [r3, #0]
80027ac: f042 0201 orr.w r2, r2, #1
80027b0: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
80027b2: 4b1f ldr r3, [pc, #124] @ (8002830 <ADC_Enable+0xac>)
80027b4: 681b ldr r3, [r3, #0]
80027b6: 4a1f ldr r2, [pc, #124] @ (8002834 <ADC_Enable+0xb0>)
80027b8: fba2 2303 umull r2, r3, r2, r3
80027bc: 0c9b lsrs r3, r3, #18
80027be: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80027c0: e002 b.n 80027c8 <ADC_Enable+0x44>
{
wait_loop_index--;
80027c2: 68bb ldr r3, [r7, #8]
80027c4: 3b01 subs r3, #1
80027c6: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80027c8: 68bb ldr r3, [r7, #8]
80027ca: 2b00 cmp r3, #0
80027cc: d1f9 bne.n 80027c2 <ADC_Enable+0x3e>
}
/* Get tick count */
tickstart = HAL_GetTick();
80027ce: f7ff fd05 bl 80021dc <HAL_GetTick>
80027d2: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively enabled */
while(ADC_IS_ENABLE(hadc) == RESET)
80027d4: e01f b.n 8002816 <ADC_Enable+0x92>
{
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
80027d6: f7ff fd01 bl 80021dc <HAL_GetTick>
80027da: 4602 mov r2, r0
80027dc: 68fb ldr r3, [r7, #12]
80027de: 1ad3 subs r3, r2, r3
80027e0: 2b02 cmp r3, #2
80027e2: d918 bls.n 8002816 <ADC_Enable+0x92>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) == RESET)
80027e4: 687b ldr r3, [r7, #4]
80027e6: 681b ldr r3, [r3, #0]
80027e8: 689b ldr r3, [r3, #8]
80027ea: f003 0301 and.w r3, r3, #1
80027ee: 2b01 cmp r3, #1
80027f0: d011 beq.n 8002816 <ADC_Enable+0x92>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80027f2: 687b ldr r3, [r7, #4]
80027f4: 6a9b ldr r3, [r3, #40] @ 0x28
80027f6: f043 0210 orr.w r2, r3, #16
80027fa: 687b ldr r3, [r7, #4]
80027fc: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80027fe: 687b ldr r3, [r7, #4]
8002800: 6adb ldr r3, [r3, #44] @ 0x2c
8002802: f043 0201 orr.w r2, r3, #1
8002806: 687b ldr r3, [r7, #4]
8002808: 62da str r2, [r3, #44] @ 0x2c
/* Process unlocked */
__HAL_UNLOCK(hadc);
800280a: 687b ldr r3, [r7, #4]
800280c: 2200 movs r2, #0
800280e: f883 2024 strb.w r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002812: 2301 movs r3, #1
8002814: e007 b.n 8002826 <ADC_Enable+0xa2>
while(ADC_IS_ENABLE(hadc) == RESET)
8002816: 687b ldr r3, [r7, #4]
8002818: 681b ldr r3, [r3, #0]
800281a: 689b ldr r3, [r3, #8]
800281c: f003 0301 and.w r3, r3, #1
8002820: 2b01 cmp r3, #1
8002822: d1d8 bne.n 80027d6 <ADC_Enable+0x52>
}
}
}
/* Return HAL status */
return HAL_OK;
8002824: 2300 movs r3, #0
}
8002826: 4618 mov r0, r3
8002828: 3710 adds r7, #16
800282a: 46bd mov sp, r7
800282c: bd80 pop {r7, pc}
800282e: bf00 nop
8002830: 20000004 .word 0x20000004
8002834: 431bde83 .word 0x431bde83
08002838 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8002838: b580 push {r7, lr}
800283a: b084 sub sp, #16
800283c: af00 add r7, sp, #0
800283e: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8002840: 2300 movs r3, #0
8002842: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
8002844: 687b ldr r3, [r7, #4]
8002846: 681b ldr r3, [r3, #0]
8002848: 689b ldr r3, [r3, #8]
800284a: f003 0301 and.w r3, r3, #1
800284e: 2b01 cmp r3, #1
8002850: d12e bne.n 80028b0 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8002852: 687b ldr r3, [r7, #4]
8002854: 681b ldr r3, [r3, #0]
8002856: 689a ldr r2, [r3, #8]
8002858: 687b ldr r3, [r7, #4]
800285a: 681b ldr r3, [r3, #0]
800285c: f022 0201 bic.w r2, r2, #1
8002860: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
8002862: f7ff fcbb bl 80021dc <HAL_GetTick>
8002866: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8002868: e01b b.n 80028a2 <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
800286a: f7ff fcb7 bl 80021dc <HAL_GetTick>
800286e: 4602 mov r2, r0
8002870: 68fb ldr r3, [r7, #12]
8002872: 1ad3 subs r3, r2, r3
8002874: 2b02 cmp r3, #2
8002876: d914 bls.n 80028a2 <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
8002878: 687b ldr r3, [r7, #4]
800287a: 681b ldr r3, [r3, #0]
800287c: 689b ldr r3, [r3, #8]
800287e: f003 0301 and.w r3, r3, #1
8002882: 2b01 cmp r3, #1
8002884: d10d bne.n 80028a2 <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002886: 687b ldr r3, [r7, #4]
8002888: 6a9b ldr r3, [r3, #40] @ 0x28
800288a: f043 0210 orr.w r2, r3, #16
800288e: 687b ldr r3, [r7, #4]
8002890: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002892: 687b ldr r3, [r7, #4]
8002894: 6adb ldr r3, [r3, #44] @ 0x2c
8002896: f043 0201 orr.w r2, r3, #1
800289a: 687b ldr r3, [r7, #4]
800289c: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
800289e: 2301 movs r3, #1
80028a0: e007 b.n 80028b2 <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
80028a2: 687b ldr r3, [r7, #4]
80028a4: 681b ldr r3, [r3, #0]
80028a6: 689b ldr r3, [r3, #8]
80028a8: f003 0301 and.w r3, r3, #1
80028ac: 2b01 cmp r3, #1
80028ae: d0dc beq.n 800286a <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
80028b0: 2300 movs r3, #0
}
80028b2: 4618 mov r0, r3
80028b4: 3710 adds r7, #16
80028b6: 46bd mov sp, r7
80028b8: bd80 pop {r7, pc}
080028ba <ADC_DMAConvCplt>:
* @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
80028ba: b580 push {r7, lr}
80028bc: b084 sub sp, #16
80028be: af00 add r7, sp, #0
80028c0: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
80028c2: 687b ldr r3, [r7, #4]
80028c4: 6a5b ldr r3, [r3, #36] @ 0x24
80028c6: 60fb str r3, [r7, #12]
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
80028c8: 68fb ldr r3, [r7, #12]
80028ca: 6a9b ldr r3, [r3, #40] @ 0x28
80028cc: f003 0350 and.w r3, r3, #80 @ 0x50
80028d0: 2b00 cmp r3, #0
80028d2: d127 bne.n 8002924 <ADC_DMAConvCplt+0x6a>
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
80028d4: 68fb ldr r3, [r7, #12]
80028d6: 6a9b ldr r3, [r3, #40] @ 0x28
80028d8: f443 7200 orr.w r2, r3, #512 @ 0x200
80028dc: 68fb ldr r3, [r7, #12]
80028de: 629a str r2, [r3, #40] @ 0x28
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F1 devices, in case of sequencer enabled */
/* (several ranks selected), end of conversion flag is raised */
/* at the end of the sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
80028e0: 68fb ldr r3, [r7, #12]
80028e2: 681b ldr r3, [r3, #0]
80028e4: 689b ldr r3, [r3, #8]
80028e6: f403 2360 and.w r3, r3, #917504 @ 0xe0000
80028ea: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000
80028ee: d115 bne.n 800291c <ADC_DMAConvCplt+0x62>
(hadc->Init.ContinuousConvMode == DISABLE) )
80028f0: 68fb ldr r3, [r7, #12]
80028f2: 7b1b ldrb r3, [r3, #12]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
80028f4: 2b00 cmp r3, #0
80028f6: d111 bne.n 800291c <ADC_DMAConvCplt+0x62>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80028f8: 68fb ldr r3, [r7, #12]
80028fa: 6a9b ldr r3, [r3, #40] @ 0x28
80028fc: f423 7280 bic.w r2, r3, #256 @ 0x100
8002900: 68fb ldr r3, [r7, #12]
8002902: 629a str r2, [r3, #40] @ 0x28
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8002904: 68fb ldr r3, [r7, #12]
8002906: 6a9b ldr r3, [r3, #40] @ 0x28
8002908: f403 5380 and.w r3, r3, #4096 @ 0x1000
800290c: 2b00 cmp r3, #0
800290e: d105 bne.n 800291c <ADC_DMAConvCplt+0x62>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8002910: 68fb ldr r3, [r7, #12]
8002912: 6a9b ldr r3, [r3, #40] @ 0x28
8002914: f043 0201 orr.w r2, r3, #1
8002918: 68fb ldr r3, [r7, #12]
800291a: 629a str r2, [r3, #40] @ 0x28
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
800291c: 68f8 ldr r0, [r7, #12]
800291e: f7ff fe1d bl 800255c <HAL_ADC_ConvCpltCallback>
else
{
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
8002922: e004 b.n 800292e <ADC_DMAConvCplt+0x74>
hadc->DMA_Handle->XferErrorCallback(hdma);
8002924: 68fb ldr r3, [r7, #12]
8002926: 6a1b ldr r3, [r3, #32]
8002928: 6b1b ldr r3, [r3, #48] @ 0x30
800292a: 6878 ldr r0, [r7, #4]
800292c: 4798 blx r3
}
800292e: bf00 nop
8002930: 3710 adds r7, #16
8002932: 46bd mov sp, r7
8002934: bd80 pop {r7, pc}
08002936 <ADC_DMAHalfConvCplt>:
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
8002936: b580 push {r7, lr}
8002938: b084 sub sp, #16
800293a: af00 add r7, sp, #0
800293c: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
800293e: 687b ldr r3, [r7, #4]
8002940: 6a5b ldr r3, [r3, #36] @ 0x24
8002942: 60fb str r3, [r7, #12]
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc);
8002944: 68f8 ldr r0, [r7, #12]
8002946: f7ff fe12 bl 800256e <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
800294a: bf00 nop
800294c: 3710 adds r7, #16
800294e: 46bd mov sp, r7
8002950: bd80 pop {r7, pc}
08002952 <ADC_DMAError>:
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
8002952: b580 push {r7, lr}
8002954: b084 sub sp, #16
8002956: af00 add r7, sp, #0
8002958: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
800295a: 687b ldr r3, [r7, #4]
800295c: 6a5b ldr r3, [r3, #36] @ 0x24
800295e: 60fb str r3, [r7, #12]
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
8002960: 68fb ldr r3, [r7, #12]
8002962: 6a9b ldr r3, [r3, #40] @ 0x28
8002964: f043 0240 orr.w r2, r3, #64 @ 0x40
8002968: 68fb ldr r3, [r7, #12]
800296a: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to DMA error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
800296c: 68fb ldr r3, [r7, #12]
800296e: 6adb ldr r3, [r3, #44] @ 0x2c
8002970: f043 0204 orr.w r2, r3, #4
8002974: 68fb ldr r3, [r7, #12]
8002976: 62da str r2, [r3, #44] @ 0x2c
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8002978: 68f8 ldr r0, [r7, #12]
800297a: f7ff fe01 bl 8002580 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
800297e: bf00 nop
8002980: 3710 adds r7, #16
8002982: 46bd mov sp, r7
8002984: bd80 pop {r7, pc}
...
08002988 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002988: b480 push {r7}
800298a: b085 sub sp, #20
800298c: af00 add r7, sp, #0
800298e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002990: 687b ldr r3, [r7, #4]
8002992: f003 0307 and.w r3, r3, #7
8002996: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002998: 4b0c ldr r3, [pc, #48] @ (80029cc <__NVIC_SetPriorityGrouping+0x44>)
800299a: 68db ldr r3, [r3, #12]
800299c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800299e: 68ba ldr r2, [r7, #8]
80029a0: f64f 03ff movw r3, #63743 @ 0xf8ff
80029a4: 4013 ands r3, r2
80029a6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80029a8: 68fb ldr r3, [r7, #12]
80029aa: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80029ac: 68bb ldr r3, [r7, #8]
80029ae: 4313 orrs r3, r2
reg_value = (reg_value |
80029b0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80029b4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80029b8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80029ba: 4a04 ldr r2, [pc, #16] @ (80029cc <__NVIC_SetPriorityGrouping+0x44>)
80029bc: 68bb ldr r3, [r7, #8]
80029be: 60d3 str r3, [r2, #12]
}
80029c0: bf00 nop
80029c2: 3714 adds r7, #20
80029c4: 46bd mov sp, r7
80029c6: bc80 pop {r7}
80029c8: 4770 bx lr
80029ca: bf00 nop
80029cc: e000ed00 .word 0xe000ed00
080029d0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80029d0: b480 push {r7}
80029d2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80029d4: 4b04 ldr r3, [pc, #16] @ (80029e8 <__NVIC_GetPriorityGrouping+0x18>)
80029d6: 68db ldr r3, [r3, #12]
80029d8: 0a1b lsrs r3, r3, #8
80029da: f003 0307 and.w r3, r3, #7
}
80029de: 4618 mov r0, r3
80029e0: 46bd mov sp, r7
80029e2: bc80 pop {r7}
80029e4: 4770 bx lr
80029e6: bf00 nop
80029e8: e000ed00 .word 0xe000ed00
080029ec <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80029ec: b480 push {r7}
80029ee: b083 sub sp, #12
80029f0: af00 add r7, sp, #0
80029f2: 4603 mov r3, r0
80029f4: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80029f6: f997 3007 ldrsb.w r3, [r7, #7]
80029fa: 2b00 cmp r3, #0
80029fc: db0b blt.n 8002a16 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80029fe: 79fb ldrb r3, [r7, #7]
8002a00: f003 021f and.w r2, r3, #31
8002a04: 4906 ldr r1, [pc, #24] @ (8002a20 <__NVIC_EnableIRQ+0x34>)
8002a06: f997 3007 ldrsb.w r3, [r7, #7]
8002a0a: 095b lsrs r3, r3, #5
8002a0c: 2001 movs r0, #1
8002a0e: fa00 f202 lsl.w r2, r0, r2
8002a12: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8002a16: bf00 nop
8002a18: 370c adds r7, #12
8002a1a: 46bd mov sp, r7
8002a1c: bc80 pop {r7}
8002a1e: 4770 bx lr
8002a20: e000e100 .word 0xe000e100
08002a24 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002a24: b480 push {r7}
8002a26: b083 sub sp, #12
8002a28: af00 add r7, sp, #0
8002a2a: 4603 mov r3, r0
8002a2c: 6039 str r1, [r7, #0]
8002a2e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002a30: f997 3007 ldrsb.w r3, [r7, #7]
8002a34: 2b00 cmp r3, #0
8002a36: db0a blt.n 8002a4e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002a38: 683b ldr r3, [r7, #0]
8002a3a: b2da uxtb r2, r3
8002a3c: 490c ldr r1, [pc, #48] @ (8002a70 <__NVIC_SetPriority+0x4c>)
8002a3e: f997 3007 ldrsb.w r3, [r7, #7]
8002a42: 0112 lsls r2, r2, #4
8002a44: b2d2 uxtb r2, r2
8002a46: 440b add r3, r1
8002a48: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8002a4c: e00a b.n 8002a64 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002a4e: 683b ldr r3, [r7, #0]
8002a50: b2da uxtb r2, r3
8002a52: 4908 ldr r1, [pc, #32] @ (8002a74 <__NVIC_SetPriority+0x50>)
8002a54: 79fb ldrb r3, [r7, #7]
8002a56: f003 030f and.w r3, r3, #15
8002a5a: 3b04 subs r3, #4
8002a5c: 0112 lsls r2, r2, #4
8002a5e: b2d2 uxtb r2, r2
8002a60: 440b add r3, r1
8002a62: 761a strb r2, [r3, #24]
}
8002a64: bf00 nop
8002a66: 370c adds r7, #12
8002a68: 46bd mov sp, r7
8002a6a: bc80 pop {r7}
8002a6c: 4770 bx lr
8002a6e: bf00 nop
8002a70: e000e100 .word 0xe000e100
8002a74: e000ed00 .word 0xe000ed00
08002a78 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002a78: b480 push {r7}
8002a7a: b089 sub sp, #36 @ 0x24
8002a7c: af00 add r7, sp, #0
8002a7e: 60f8 str r0, [r7, #12]
8002a80: 60b9 str r1, [r7, #8]
8002a82: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002a84: 68fb ldr r3, [r7, #12]
8002a86: f003 0307 and.w r3, r3, #7
8002a8a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8002a8c: 69fb ldr r3, [r7, #28]
8002a8e: f1c3 0307 rsb r3, r3, #7
8002a92: 2b04 cmp r3, #4
8002a94: bf28 it cs
8002a96: 2304 movcs r3, #4
8002a98: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8002a9a: 69fb ldr r3, [r7, #28]
8002a9c: 3304 adds r3, #4
8002a9e: 2b06 cmp r3, #6
8002aa0: d902 bls.n 8002aa8 <NVIC_EncodePriority+0x30>
8002aa2: 69fb ldr r3, [r7, #28]
8002aa4: 3b03 subs r3, #3
8002aa6: e000 b.n 8002aaa <NVIC_EncodePriority+0x32>
8002aa8: 2300 movs r3, #0
8002aaa: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002aac: f04f 32ff mov.w r2, #4294967295
8002ab0: 69bb ldr r3, [r7, #24]
8002ab2: fa02 f303 lsl.w r3, r2, r3
8002ab6: 43da mvns r2, r3
8002ab8: 68bb ldr r3, [r7, #8]
8002aba: 401a ands r2, r3
8002abc: 697b ldr r3, [r7, #20]
8002abe: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002ac0: f04f 31ff mov.w r1, #4294967295
8002ac4: 697b ldr r3, [r7, #20]
8002ac6: fa01 f303 lsl.w r3, r1, r3
8002aca: 43d9 mvns r1, r3
8002acc: 687b ldr r3, [r7, #4]
8002ace: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002ad0: 4313 orrs r3, r2
);
}
8002ad2: 4618 mov r0, r3
8002ad4: 3724 adds r7, #36 @ 0x24
8002ad6: 46bd mov sp, r7
8002ad8: bc80 pop {r7}
8002ada: 4770 bx lr
08002adc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002adc: b580 push {r7, lr}
8002ade: b082 sub sp, #8
8002ae0: af00 add r7, sp, #0
8002ae2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002ae4: 687b ldr r3, [r7, #4]
8002ae6: 3b01 subs r3, #1
8002ae8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8002aec: d301 bcc.n 8002af2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8002aee: 2301 movs r3, #1
8002af0: e00f b.n 8002b12 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002af2: 4a0a ldr r2, [pc, #40] @ (8002b1c <SysTick_Config+0x40>)
8002af4: 687b ldr r3, [r7, #4]
8002af6: 3b01 subs r3, #1
8002af8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8002afa: 210f movs r1, #15
8002afc: f04f 30ff mov.w r0, #4294967295
8002b00: f7ff ff90 bl 8002a24 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002b04: 4b05 ldr r3, [pc, #20] @ (8002b1c <SysTick_Config+0x40>)
8002b06: 2200 movs r2, #0
8002b08: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002b0a: 4b04 ldr r3, [pc, #16] @ (8002b1c <SysTick_Config+0x40>)
8002b0c: 2207 movs r2, #7
8002b0e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002b10: 2300 movs r3, #0
}
8002b12: 4618 mov r0, r3
8002b14: 3708 adds r7, #8
8002b16: 46bd mov sp, r7
8002b18: bd80 pop {r7, pc}
8002b1a: bf00 nop
8002b1c: e000e010 .word 0xe000e010
08002b20 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002b20: b580 push {r7, lr}
8002b22: b082 sub sp, #8
8002b24: af00 add r7, sp, #0
8002b26: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8002b28: 6878 ldr r0, [r7, #4]
8002b2a: f7ff ff2d bl 8002988 <__NVIC_SetPriorityGrouping>
}
8002b2e: bf00 nop
8002b30: 3708 adds r7, #8
8002b32: 46bd mov sp, r7
8002b34: bd80 pop {r7, pc}
08002b36 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002b36: b580 push {r7, lr}
8002b38: b086 sub sp, #24
8002b3a: af00 add r7, sp, #0
8002b3c: 4603 mov r3, r0
8002b3e: 60b9 str r1, [r7, #8]
8002b40: 607a str r2, [r7, #4]
8002b42: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8002b44: 2300 movs r3, #0
8002b46: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8002b48: f7ff ff42 bl 80029d0 <__NVIC_GetPriorityGrouping>
8002b4c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8002b4e: 687a ldr r2, [r7, #4]
8002b50: 68b9 ldr r1, [r7, #8]
8002b52: 6978 ldr r0, [r7, #20]
8002b54: f7ff ff90 bl 8002a78 <NVIC_EncodePriority>
8002b58: 4602 mov r2, r0
8002b5a: f997 300f ldrsb.w r3, [r7, #15]
8002b5e: 4611 mov r1, r2
8002b60: 4618 mov r0, r3
8002b62: f7ff ff5f bl 8002a24 <__NVIC_SetPriority>
}
8002b66: bf00 nop
8002b68: 3718 adds r7, #24
8002b6a: 46bd mov sp, r7
8002b6c: bd80 pop {r7, pc}
08002b6e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002b6e: b580 push {r7, lr}
8002b70: b082 sub sp, #8
8002b72: af00 add r7, sp, #0
8002b74: 4603 mov r3, r0
8002b76: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002b78: f997 3007 ldrsb.w r3, [r7, #7]
8002b7c: 4618 mov r0, r3
8002b7e: f7ff ff35 bl 80029ec <__NVIC_EnableIRQ>
}
8002b82: bf00 nop
8002b84: 3708 adds r7, #8
8002b86: 46bd mov sp, r7
8002b88: bd80 pop {r7, pc}
08002b8a <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8002b8a: b580 push {r7, lr}
8002b8c: b082 sub sp, #8
8002b8e: af00 add r7, sp, #0
8002b90: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002b92: 6878 ldr r0, [r7, #4]
8002b94: f7ff ffa2 bl 8002adc <SysTick_Config>
8002b98: 4603 mov r3, r0
}
8002b9a: 4618 mov r0, r3
8002b9c: 3708 adds r7, #8
8002b9e: 46bd mov sp, r7
8002ba0: bd80 pop {r7, pc}
08002ba2 <HAL_SYSTICK_IRQHandler>:
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
8002ba2: b580 push {r7, lr}
8002ba4: af00 add r7, sp, #0
HAL_SYSTICK_Callback();
8002ba6: f7fe fa8f bl 80010c8 <HAL_SYSTICK_Callback>
}
8002baa: bf00 nop
8002bac: bd80 pop {r7, pc}
...
08002bb0 <HAL_DMA_Init>:
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8002bb0: b480 push {r7}
8002bb2: b085 sub sp, #20
8002bb4: af00 add r7, sp, #0
8002bb6: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
8002bb8: 2300 movs r3, #0
8002bba: 60fb str r3, [r7, #12]
/* Check the DMA handle allocation */
if(hdma == NULL)
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 2b00 cmp r3, #0
8002bc0: d101 bne.n 8002bc6 <HAL_DMA_Init+0x16>
{
return HAL_ERROR;
8002bc2: 2301 movs r3, #1
8002bc4: e043 b.n 8002c4e <HAL_DMA_Init+0x9e>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
8002bc6: 687b ldr r3, [r7, #4]
8002bc8: 681b ldr r3, [r3, #0]
8002bca: 461a mov r2, r3
8002bcc: 4b22 ldr r3, [pc, #136] @ (8002c58 <HAL_DMA_Init+0xa8>)
8002bce: 4413 add r3, r2
8002bd0: 4a22 ldr r2, [pc, #136] @ (8002c5c <HAL_DMA_Init+0xac>)
8002bd2: fba2 2303 umull r2, r3, r2, r3
8002bd6: 091b lsrs r3, r3, #4
8002bd8: 009a lsls r2, r3, #2
8002bda: 687b ldr r3, [r7, #4]
8002bdc: 641a str r2, [r3, #64] @ 0x40
hdma->DmaBaseAddress = DMA1;
8002bde: 687b ldr r3, [r7, #4]
8002be0: 4a1f ldr r2, [pc, #124] @ (8002c60 <HAL_DMA_Init+0xb0>)
8002be2: 63da str r2, [r3, #60] @ 0x3c
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8002be4: 687b ldr r3, [r7, #4]
8002be6: 2202 movs r2, #2
8002be8: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Get the CR register value */
tmp = hdma->Instance->CCR;
8002bec: 687b ldr r3, [r7, #4]
8002bee: 681b ldr r3, [r3, #0]
8002bf0: 681b ldr r3, [r3, #0]
8002bf2: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8002bf4: 68fb ldr r3, [r7, #12]
8002bf6: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8002bfa: f023 0330 bic.w r3, r3, #48 @ 0x30
8002bfe: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
8002c00: 687b ldr r3, [r7, #4]
8002c02: 685a ldr r2, [r3, #4]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8002c04: 687b ldr r3, [r7, #4]
8002c06: 689b ldr r3, [r3, #8]
tmp |= hdma->Init.Direction |
8002c08: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8002c0a: 687b ldr r3, [r7, #4]
8002c0c: 68db ldr r3, [r3, #12]
8002c0e: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8002c10: 687b ldr r3, [r7, #4]
8002c12: 691b ldr r3, [r3, #16]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8002c14: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8002c16: 687b ldr r3, [r7, #4]
8002c18: 695b ldr r3, [r3, #20]
8002c1a: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8002c1c: 687b ldr r3, [r7, #4]
8002c1e: 699b ldr r3, [r3, #24]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8002c20: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8002c22: 687b ldr r3, [r7, #4]
8002c24: 69db ldr r3, [r3, #28]
8002c26: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8002c28: 68fa ldr r2, [r7, #12]
8002c2a: 4313 orrs r3, r2
8002c2c: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
8002c2e: 687b ldr r3, [r7, #4]
8002c30: 681b ldr r3, [r3, #0]
8002c32: 68fa ldr r2, [r7, #12]
8002c34: 601a str r2, [r3, #0]
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002c36: 687b ldr r3, [r7, #4]
8002c38: 2200 movs r2, #0
8002c3a: 639a str r2, [r3, #56] @ 0x38
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8002c3c: 687b ldr r3, [r7, #4]
8002c3e: 2201 movs r2, #1
8002c40: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
8002c44: 687b ldr r3, [r7, #4]
8002c46: 2200 movs r2, #0
8002c48: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
8002c4c: 2300 movs r3, #0
}
8002c4e: 4618 mov r0, r3
8002c50: 3714 adds r7, #20
8002c52: 46bd mov sp, r7
8002c54: bc80 pop {r7}
8002c56: 4770 bx lr
8002c58: bffdfff8 .word 0xbffdfff8
8002c5c: cccccccd .word 0xcccccccd
8002c60: 40020000 .word 0x40020000
08002c64 <HAL_DMA_Start_IT>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8002c64: b580 push {r7, lr}
8002c66: b086 sub sp, #24
8002c68: af00 add r7, sp, #0
8002c6a: 60f8 str r0, [r7, #12]
8002c6c: 60b9 str r1, [r7, #8]
8002c6e: 607a str r2, [r7, #4]
8002c70: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8002c72: 2300 movs r3, #0
8002c74: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8002c76: 68fb ldr r3, [r7, #12]
8002c78: f893 3020 ldrb.w r3, [r3, #32]
8002c7c: 2b01 cmp r3, #1
8002c7e: d101 bne.n 8002c84 <HAL_DMA_Start_IT+0x20>
8002c80: 2302 movs r3, #2
8002c82: e04b b.n 8002d1c <HAL_DMA_Start_IT+0xb8>
8002c84: 68fb ldr r3, [r7, #12]
8002c86: 2201 movs r2, #1
8002c88: f883 2020 strb.w r2, [r3, #32]
if(HAL_DMA_STATE_READY == hdma->State)
8002c8c: 68fb ldr r3, [r7, #12]
8002c8e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8002c92: b2db uxtb r3, r3
8002c94: 2b01 cmp r3, #1
8002c96: d13a bne.n 8002d0e <HAL_DMA_Start_IT+0xaa>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8002c98: 68fb ldr r3, [r7, #12]
8002c9a: 2202 movs r2, #2
8002c9c: f883 2021 strb.w r2, [r3, #33] @ 0x21
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002ca0: 68fb ldr r3, [r7, #12]
8002ca2: 2200 movs r2, #0
8002ca4: 639a str r2, [r3, #56] @ 0x38
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8002ca6: 68fb ldr r3, [r7, #12]
8002ca8: 681b ldr r3, [r3, #0]
8002caa: 681a ldr r2, [r3, #0]
8002cac: 68fb ldr r3, [r7, #12]
8002cae: 681b ldr r3, [r3, #0]
8002cb0: f022 0201 bic.w r2, r2, #1
8002cb4: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8002cb6: 683b ldr r3, [r7, #0]
8002cb8: 687a ldr r2, [r7, #4]
8002cba: 68b9 ldr r1, [r7, #8]
8002cbc: 68f8 ldr r0, [r7, #12]
8002cbe: f000 f937 bl 8002f30 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback)
8002cc2: 68fb ldr r3, [r7, #12]
8002cc4: 6adb ldr r3, [r3, #44] @ 0x2c
8002cc6: 2b00 cmp r3, #0
8002cc8: d008 beq.n 8002cdc <HAL_DMA_Start_IT+0x78>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8002cca: 68fb ldr r3, [r7, #12]
8002ccc: 681b ldr r3, [r3, #0]
8002cce: 681a ldr r2, [r3, #0]
8002cd0: 68fb ldr r3, [r7, #12]
8002cd2: 681b ldr r3, [r3, #0]
8002cd4: f042 020e orr.w r2, r2, #14
8002cd8: 601a str r2, [r3, #0]
8002cda: e00f b.n 8002cfc <HAL_DMA_Start_IT+0x98>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8002cdc: 68fb ldr r3, [r7, #12]
8002cde: 681b ldr r3, [r3, #0]
8002ce0: 681a ldr r2, [r3, #0]
8002ce2: 68fb ldr r3, [r7, #12]
8002ce4: 681b ldr r3, [r3, #0]
8002ce6: f022 0204 bic.w r2, r2, #4
8002cea: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8002cec: 68fb ldr r3, [r7, #12]
8002cee: 681b ldr r3, [r3, #0]
8002cf0: 681a ldr r2, [r3, #0]
8002cf2: 68fb ldr r3, [r7, #12]
8002cf4: 681b ldr r3, [r3, #0]
8002cf6: f042 020a orr.w r2, r2, #10
8002cfa: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8002cfc: 68fb ldr r3, [r7, #12]
8002cfe: 681b ldr r3, [r3, #0]
8002d00: 681a ldr r2, [r3, #0]
8002d02: 68fb ldr r3, [r7, #12]
8002d04: 681b ldr r3, [r3, #0]
8002d06: f042 0201 orr.w r2, r2, #1
8002d0a: 601a str r2, [r3, #0]
8002d0c: e005 b.n 8002d1a <HAL_DMA_Start_IT+0xb6>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002d0e: 68fb ldr r3, [r7, #12]
8002d10: 2200 movs r2, #0
8002d12: f883 2020 strb.w r2, [r3, #32]
/* Remain BUSY */
status = HAL_BUSY;
8002d16: 2302 movs r3, #2
8002d18: 75fb strb r3, [r7, #23]
}
return status;
8002d1a: 7dfb ldrb r3, [r7, #23]
}
8002d1c: 4618 mov r0, r3
8002d1e: 3718 adds r7, #24
8002d20: 46bd mov sp, r7
8002d22: bd80 pop {r7, pc}
08002d24 <HAL_DMA_IRQHandler>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
8002d24: b580 push {r7, lr}
8002d26: b084 sub sp, #16
8002d28: af00 add r7, sp, #0
8002d2a: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8002d2c: 687b ldr r3, [r7, #4]
8002d2e: 6bdb ldr r3, [r3, #60] @ 0x3c
8002d30: 681b ldr r3, [r3, #0]
8002d32: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
8002d34: 687b ldr r3, [r7, #4]
8002d36: 681b ldr r3, [r3, #0]
8002d38: 681b ldr r3, [r3, #0]
8002d3a: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
8002d3c: 687b ldr r3, [r7, #4]
8002d3e: 6c1b ldr r3, [r3, #64] @ 0x40
8002d40: 2204 movs r2, #4
8002d42: 409a lsls r2, r3
8002d44: 68fb ldr r3, [r7, #12]
8002d46: 4013 ands r3, r2
8002d48: 2b00 cmp r3, #0
8002d4a: d04f beq.n 8002dec <HAL_DMA_IRQHandler+0xc8>
8002d4c: 68bb ldr r3, [r7, #8]
8002d4e: f003 0304 and.w r3, r3, #4
8002d52: 2b00 cmp r3, #0
8002d54: d04a beq.n 8002dec <HAL_DMA_IRQHandler+0xc8>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8002d56: 687b ldr r3, [r7, #4]
8002d58: 681b ldr r3, [r3, #0]
8002d5a: 681b ldr r3, [r3, #0]
8002d5c: f003 0320 and.w r3, r3, #32
8002d60: 2b00 cmp r3, #0
8002d62: d107 bne.n 8002d74 <HAL_DMA_IRQHandler+0x50>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8002d64: 687b ldr r3, [r7, #4]
8002d66: 681b ldr r3, [r3, #0]
8002d68: 681a ldr r2, [r3, #0]
8002d6a: 687b ldr r3, [r7, #4]
8002d6c: 681b ldr r3, [r3, #0]
8002d6e: f022 0204 bic.w r2, r2, #4
8002d72: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
8002d74: 687b ldr r3, [r7, #4]
8002d76: 681b ldr r3, [r3, #0]
8002d78: 4a66 ldr r2, [pc, #408] @ (8002f14 <HAL_DMA_IRQHandler+0x1f0>)
8002d7a: 4293 cmp r3, r2
8002d7c: d029 beq.n 8002dd2 <HAL_DMA_IRQHandler+0xae>
8002d7e: 687b ldr r3, [r7, #4]
8002d80: 681b ldr r3, [r3, #0]
8002d82: 4a65 ldr r2, [pc, #404] @ (8002f18 <HAL_DMA_IRQHandler+0x1f4>)
8002d84: 4293 cmp r3, r2
8002d86: d022 beq.n 8002dce <HAL_DMA_IRQHandler+0xaa>
8002d88: 687b ldr r3, [r7, #4]
8002d8a: 681b ldr r3, [r3, #0]
8002d8c: 4a63 ldr r2, [pc, #396] @ (8002f1c <HAL_DMA_IRQHandler+0x1f8>)
8002d8e: 4293 cmp r3, r2
8002d90: d01a beq.n 8002dc8 <HAL_DMA_IRQHandler+0xa4>
8002d92: 687b ldr r3, [r7, #4]
8002d94: 681b ldr r3, [r3, #0]
8002d96: 4a62 ldr r2, [pc, #392] @ (8002f20 <HAL_DMA_IRQHandler+0x1fc>)
8002d98: 4293 cmp r3, r2
8002d9a: d012 beq.n 8002dc2 <HAL_DMA_IRQHandler+0x9e>
8002d9c: 687b ldr r3, [r7, #4]
8002d9e: 681b ldr r3, [r3, #0]
8002da0: 4a60 ldr r2, [pc, #384] @ (8002f24 <HAL_DMA_IRQHandler+0x200>)
8002da2: 4293 cmp r3, r2
8002da4: d00a beq.n 8002dbc <HAL_DMA_IRQHandler+0x98>
8002da6: 687b ldr r3, [r7, #4]
8002da8: 681b ldr r3, [r3, #0]
8002daa: 4a5f ldr r2, [pc, #380] @ (8002f28 <HAL_DMA_IRQHandler+0x204>)
8002dac: 4293 cmp r3, r2
8002dae: d102 bne.n 8002db6 <HAL_DMA_IRQHandler+0x92>
8002db0: f44f 0380 mov.w r3, #4194304 @ 0x400000
8002db4: e00e b.n 8002dd4 <HAL_DMA_IRQHandler+0xb0>
8002db6: f04f 6380 mov.w r3, #67108864 @ 0x4000000
8002dba: e00b b.n 8002dd4 <HAL_DMA_IRQHandler+0xb0>
8002dbc: f44f 2380 mov.w r3, #262144 @ 0x40000
8002dc0: e008 b.n 8002dd4 <HAL_DMA_IRQHandler+0xb0>
8002dc2: f44f 4380 mov.w r3, #16384 @ 0x4000
8002dc6: e005 b.n 8002dd4 <HAL_DMA_IRQHandler+0xb0>
8002dc8: f44f 6380 mov.w r3, #1024 @ 0x400
8002dcc: e002 b.n 8002dd4 <HAL_DMA_IRQHandler+0xb0>
8002dce: 2340 movs r3, #64 @ 0x40
8002dd0: e000 b.n 8002dd4 <HAL_DMA_IRQHandler+0xb0>
8002dd2: 2304 movs r3, #4
8002dd4: 4a55 ldr r2, [pc, #340] @ (8002f2c <HAL_DMA_IRQHandler+0x208>)
8002dd6: 6053 str r3, [r2, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
8002dd8: 687b ldr r3, [r7, #4]
8002dda: 6adb ldr r3, [r3, #44] @ 0x2c
8002ddc: 2b00 cmp r3, #0
8002dde: f000 8094 beq.w 8002f0a <HAL_DMA_IRQHandler+0x1e6>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8002de2: 687b ldr r3, [r7, #4]
8002de4: 6adb ldr r3, [r3, #44] @ 0x2c
8002de6: 6878 ldr r0, [r7, #4]
8002de8: 4798 blx r3
if(hdma->XferHalfCpltCallback != NULL)
8002dea: e08e b.n 8002f0a <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
8002dec: 687b ldr r3, [r7, #4]
8002dee: 6c1b ldr r3, [r3, #64] @ 0x40
8002df0: 2202 movs r2, #2
8002df2: 409a lsls r2, r3
8002df4: 68fb ldr r3, [r7, #12]
8002df6: 4013 ands r3, r2
8002df8: 2b00 cmp r3, #0
8002dfa: d056 beq.n 8002eaa <HAL_DMA_IRQHandler+0x186>
8002dfc: 68bb ldr r3, [r7, #8]
8002dfe: f003 0302 and.w r3, r3, #2
8002e02: 2b00 cmp r3, #0
8002e04: d051 beq.n 8002eaa <HAL_DMA_IRQHandler+0x186>
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8002e06: 687b ldr r3, [r7, #4]
8002e08: 681b ldr r3, [r3, #0]
8002e0a: 681b ldr r3, [r3, #0]
8002e0c: f003 0320 and.w r3, r3, #32
8002e10: 2b00 cmp r3, #0
8002e12: d10b bne.n 8002e2c <HAL_DMA_IRQHandler+0x108>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8002e14: 687b ldr r3, [r7, #4]
8002e16: 681b ldr r3, [r3, #0]
8002e18: 681a ldr r2, [r3, #0]
8002e1a: 687b ldr r3, [r7, #4]
8002e1c: 681b ldr r3, [r3, #0]
8002e1e: f022 020a bic.w r2, r2, #10
8002e22: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8002e24: 687b ldr r3, [r7, #4]
8002e26: 2201 movs r2, #1
8002e28: f883 2021 strb.w r2, [r3, #33] @ 0x21
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
8002e2c: 687b ldr r3, [r7, #4]
8002e2e: 681b ldr r3, [r3, #0]
8002e30: 4a38 ldr r2, [pc, #224] @ (8002f14 <HAL_DMA_IRQHandler+0x1f0>)
8002e32: 4293 cmp r3, r2
8002e34: d029 beq.n 8002e8a <HAL_DMA_IRQHandler+0x166>
8002e36: 687b ldr r3, [r7, #4]
8002e38: 681b ldr r3, [r3, #0]
8002e3a: 4a37 ldr r2, [pc, #220] @ (8002f18 <HAL_DMA_IRQHandler+0x1f4>)
8002e3c: 4293 cmp r3, r2
8002e3e: d022 beq.n 8002e86 <HAL_DMA_IRQHandler+0x162>
8002e40: 687b ldr r3, [r7, #4]
8002e42: 681b ldr r3, [r3, #0]
8002e44: 4a35 ldr r2, [pc, #212] @ (8002f1c <HAL_DMA_IRQHandler+0x1f8>)
8002e46: 4293 cmp r3, r2
8002e48: d01a beq.n 8002e80 <HAL_DMA_IRQHandler+0x15c>
8002e4a: 687b ldr r3, [r7, #4]
8002e4c: 681b ldr r3, [r3, #0]
8002e4e: 4a34 ldr r2, [pc, #208] @ (8002f20 <HAL_DMA_IRQHandler+0x1fc>)
8002e50: 4293 cmp r3, r2
8002e52: d012 beq.n 8002e7a <HAL_DMA_IRQHandler+0x156>
8002e54: 687b ldr r3, [r7, #4]
8002e56: 681b ldr r3, [r3, #0]
8002e58: 4a32 ldr r2, [pc, #200] @ (8002f24 <HAL_DMA_IRQHandler+0x200>)
8002e5a: 4293 cmp r3, r2
8002e5c: d00a beq.n 8002e74 <HAL_DMA_IRQHandler+0x150>
8002e5e: 687b ldr r3, [r7, #4]
8002e60: 681b ldr r3, [r3, #0]
8002e62: 4a31 ldr r2, [pc, #196] @ (8002f28 <HAL_DMA_IRQHandler+0x204>)
8002e64: 4293 cmp r3, r2
8002e66: d102 bne.n 8002e6e <HAL_DMA_IRQHandler+0x14a>
8002e68: f44f 1300 mov.w r3, #2097152 @ 0x200000
8002e6c: e00e b.n 8002e8c <HAL_DMA_IRQHandler+0x168>
8002e6e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002e72: e00b b.n 8002e8c <HAL_DMA_IRQHandler+0x168>
8002e74: f44f 3300 mov.w r3, #131072 @ 0x20000
8002e78: e008 b.n 8002e8c <HAL_DMA_IRQHandler+0x168>
8002e7a: f44f 5300 mov.w r3, #8192 @ 0x2000
8002e7e: e005 b.n 8002e8c <HAL_DMA_IRQHandler+0x168>
8002e80: f44f 7300 mov.w r3, #512 @ 0x200
8002e84: e002 b.n 8002e8c <HAL_DMA_IRQHandler+0x168>
8002e86: 2320 movs r3, #32
8002e88: e000 b.n 8002e8c <HAL_DMA_IRQHandler+0x168>
8002e8a: 2302 movs r3, #2
8002e8c: 4a27 ldr r2, [pc, #156] @ (8002f2c <HAL_DMA_IRQHandler+0x208>)
8002e8e: 6053 str r3, [r2, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002e90: 687b ldr r3, [r7, #4]
8002e92: 2200 movs r2, #0
8002e94: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferCpltCallback != NULL)
8002e98: 687b ldr r3, [r7, #4]
8002e9a: 6a9b ldr r3, [r3, #40] @ 0x28
8002e9c: 2b00 cmp r3, #0
8002e9e: d034 beq.n 8002f0a <HAL_DMA_IRQHandler+0x1e6>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8002ea0: 687b ldr r3, [r7, #4]
8002ea2: 6a9b ldr r3, [r3, #40] @ 0x28
8002ea4: 6878 ldr r0, [r7, #4]
8002ea6: 4798 blx r3
if(hdma->XferCpltCallback != NULL)
8002ea8: e02f b.n 8002f0a <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
8002eaa: 687b ldr r3, [r7, #4]
8002eac: 6c1b ldr r3, [r3, #64] @ 0x40
8002eae: 2208 movs r2, #8
8002eb0: 409a lsls r2, r3
8002eb2: 68fb ldr r3, [r7, #12]
8002eb4: 4013 ands r3, r2
8002eb6: 2b00 cmp r3, #0
8002eb8: d028 beq.n 8002f0c <HAL_DMA_IRQHandler+0x1e8>
8002eba: 68bb ldr r3, [r7, #8]
8002ebc: f003 0308 and.w r3, r3, #8
8002ec0: 2b00 cmp r3, #0
8002ec2: d023 beq.n 8002f0c <HAL_DMA_IRQHandler+0x1e8>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8002ec4: 687b ldr r3, [r7, #4]
8002ec6: 681b ldr r3, [r3, #0]
8002ec8: 681a ldr r2, [r3, #0]
8002eca: 687b ldr r3, [r7, #4]
8002ecc: 681b ldr r3, [r3, #0]
8002ece: f022 020e bic.w r2, r2, #14
8002ed2: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8002ed4: 687b ldr r3, [r7, #4]
8002ed6: 6c1a ldr r2, [r3, #64] @ 0x40
8002ed8: 687b ldr r3, [r7, #4]
8002eda: 6bdb ldr r3, [r3, #60] @ 0x3c
8002edc: 2101 movs r1, #1
8002ede: fa01 f202 lsl.w r2, r1, r2
8002ee2: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8002ee4: 687b ldr r3, [r7, #4]
8002ee6: 2201 movs r2, #1
8002ee8: 639a str r2, [r3, #56] @ 0x38
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8002eea: 687b ldr r3, [r7, #4]
8002eec: 2201 movs r2, #1
8002eee: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002ef2: 687b ldr r3, [r7, #4]
8002ef4: 2200 movs r2, #0
8002ef6: f883 2020 strb.w r2, [r3, #32]
if (hdma->XferErrorCallback != NULL)
8002efa: 687b ldr r3, [r7, #4]
8002efc: 6b1b ldr r3, [r3, #48] @ 0x30
8002efe: 2b00 cmp r3, #0
8002f00: d004 beq.n 8002f0c <HAL_DMA_IRQHandler+0x1e8>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8002f02: 687b ldr r3, [r7, #4]
8002f04: 6b1b ldr r3, [r3, #48] @ 0x30
8002f06: 6878 ldr r0, [r7, #4]
8002f08: 4798 blx r3
}
}
return;
8002f0a: bf00 nop
8002f0c: bf00 nop
}
8002f0e: 3710 adds r7, #16
8002f10: 46bd mov sp, r7
8002f12: bd80 pop {r7, pc}
8002f14: 40020008 .word 0x40020008
8002f18: 4002001c .word 0x4002001c
8002f1c: 40020030 .word 0x40020030
8002f20: 40020044 .word 0x40020044
8002f24: 40020058 .word 0x40020058
8002f28: 4002006c .word 0x4002006c
8002f2c: 40020000 .word 0x40020000
08002f30 <DMA_SetConfig>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8002f30: b480 push {r7}
8002f32: b085 sub sp, #20
8002f34: af00 add r7, sp, #0
8002f36: 60f8 str r0, [r7, #12]
8002f38: 60b9 str r1, [r7, #8]
8002f3a: 607a str r2, [r7, #4]
8002f3c: 603b str r3, [r7, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8002f3e: 68fb ldr r3, [r7, #12]
8002f40: 6c1a ldr r2, [r3, #64] @ 0x40
8002f42: 68fb ldr r3, [r7, #12]
8002f44: 6bdb ldr r3, [r3, #60] @ 0x3c
8002f46: 2101 movs r1, #1
8002f48: fa01 f202 lsl.w r2, r1, r2
8002f4c: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8002f4e: 68fb ldr r3, [r7, #12]
8002f50: 681b ldr r3, [r3, #0]
8002f52: 683a ldr r2, [r7, #0]
8002f54: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8002f56: 68fb ldr r3, [r7, #12]
8002f58: 685b ldr r3, [r3, #4]
8002f5a: 2b10 cmp r3, #16
8002f5c: d108 bne.n 8002f70 <DMA_SetConfig+0x40>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8002f5e: 68fb ldr r3, [r7, #12]
8002f60: 681b ldr r3, [r3, #0]
8002f62: 687a ldr r2, [r7, #4]
8002f64: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8002f66: 68fb ldr r3, [r7, #12]
8002f68: 681b ldr r3, [r3, #0]
8002f6a: 68ba ldr r2, [r7, #8]
8002f6c: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8002f6e: e007 b.n 8002f80 <DMA_SetConfig+0x50>
hdma->Instance->CPAR = SrcAddress;
8002f70: 68fb ldr r3, [r7, #12]
8002f72: 681b ldr r3, [r3, #0]
8002f74: 68ba ldr r2, [r7, #8]
8002f76: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8002f78: 68fb ldr r3, [r7, #12]
8002f7a: 681b ldr r3, [r3, #0]
8002f7c: 687a ldr r2, [r7, #4]
8002f7e: 60da str r2, [r3, #12]
}
8002f80: bf00 nop
8002f82: 3714 adds r7, #20
8002f84: 46bd mov sp, r7
8002f86: bc80 pop {r7}
8002f88: 4770 bx lr
...
08002f8c <HAL_FLASH_Program>:
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
8002f8c: b5f0 push {r4, r5, r6, r7, lr}
8002f8e: b087 sub sp, #28
8002f90: af00 add r7, sp, #0
8002f92: 60f8 str r0, [r7, #12]
8002f94: 60b9 str r1, [r7, #8]
8002f96: e9c7 2300 strd r2, r3, [r7]
HAL_StatusTypeDef status = HAL_ERROR;
8002f9a: 2301 movs r3, #1
8002f9c: 75fb strb r3, [r7, #23]
uint8_t index = 0;
8002f9e: 2300 movs r3, #0
8002fa0: 75bb strb r3, [r7, #22]
uint8_t nbiterations = 0;
8002fa2: 2300 movs r3, #0
8002fa4: 757b strb r3, [r7, #21]
/* Process Locked */
__HAL_LOCK(&pFlash);
8002fa6: 4b2f ldr r3, [pc, #188] @ (8003064 <HAL_FLASH_Program+0xd8>)
8002fa8: 7e1b ldrb r3, [r3, #24]
8002faa: 2b01 cmp r3, #1
8002fac: d101 bne.n 8002fb2 <HAL_FLASH_Program+0x26>
8002fae: 2302 movs r3, #2
8002fb0: e054 b.n 800305c <HAL_FLASH_Program+0xd0>
8002fb2: 4b2c ldr r3, [pc, #176] @ (8003064 <HAL_FLASH_Program+0xd8>)
8002fb4: 2201 movs r2, #1
8002fb6: 761a strb r2, [r3, #24]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8002fb8: f24c 3050 movw r0, #50000 @ 0xc350
8002fbc: f000 f8a8 bl 8003110 <FLASH_WaitForLastOperation>
8002fc0: 4603 mov r3, r0
8002fc2: 75fb strb r3, [r7, #23]
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
if(status == HAL_OK)
8002fc4: 7dfb ldrb r3, [r7, #23]
8002fc6: 2b00 cmp r3, #0
8002fc8: d144 bne.n 8003054 <HAL_FLASH_Program+0xc8>
{
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
8002fca: 68fb ldr r3, [r7, #12]
8002fcc: 2b01 cmp r3, #1
8002fce: d102 bne.n 8002fd6 <HAL_FLASH_Program+0x4a>
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1U;
8002fd0: 2301 movs r3, #1
8002fd2: 757b strb r3, [r7, #21]
8002fd4: e007 b.n 8002fe6 <HAL_FLASH_Program+0x5a>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
8002fd6: 68fb ldr r3, [r7, #12]
8002fd8: 2b02 cmp r3, #2
8002fda: d102 bne.n 8002fe2 <HAL_FLASH_Program+0x56>
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2U;
8002fdc: 2302 movs r3, #2
8002fde: 757b strb r3, [r7, #21]
8002fe0: e001 b.n 8002fe6 <HAL_FLASH_Program+0x5a>
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
nbiterations = 4U;
8002fe2: 2304 movs r3, #4
8002fe4: 757b strb r3, [r7, #21]
}
for (index = 0U; index < nbiterations; index++)
8002fe6: 2300 movs r3, #0
8002fe8: 75bb strb r3, [r7, #22]
8002fea: e02d b.n 8003048 <HAL_FLASH_Program+0xbc>
{
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
8002fec: 7dbb ldrb r3, [r7, #22]
8002fee: 005a lsls r2, r3, #1
8002ff0: 68bb ldr r3, [r7, #8]
8002ff2: eb02 0c03 add.w ip, r2, r3
8002ff6: 7dbb ldrb r3, [r7, #22]
8002ff8: 0119 lsls r1, r3, #4
8002ffa: e9d7 2300 ldrd r2, r3, [r7]
8002ffe: f1c1 0620 rsb r6, r1, #32
8003002: f1a1 0020 sub.w r0, r1, #32
8003006: fa22 f401 lsr.w r4, r2, r1
800300a: fa03 f606 lsl.w r6, r3, r6
800300e: 4334 orrs r4, r6
8003010: fa23 f000 lsr.w r0, r3, r0
8003014: 4304 orrs r4, r0
8003016: fa23 f501 lsr.w r5, r3, r1
800301a: b2a3 uxth r3, r4
800301c: 4619 mov r1, r3
800301e: 4660 mov r0, ip
8003020: f000 f85a bl 80030d8 <FLASH_Program_HalfWord>
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8003024: f24c 3050 movw r0, #50000 @ 0xc350
8003028: f000 f872 bl 8003110 <FLASH_WaitForLastOperation>
800302c: 4603 mov r3, r0
800302e: 75fb strb r3, [r7, #23]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
8003030: 4b0d ldr r3, [pc, #52] @ (8003068 <HAL_FLASH_Program+0xdc>)
8003032: 691b ldr r3, [r3, #16]
8003034: 4a0c ldr r2, [pc, #48] @ (8003068 <HAL_FLASH_Program+0xdc>)
8003036: f023 0301 bic.w r3, r3, #1
800303a: 6113 str r3, [r2, #16]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* In case of error, stop programation procedure */
if (status != HAL_OK)
800303c: 7dfb ldrb r3, [r7, #23]
800303e: 2b00 cmp r3, #0
8003040: d107 bne.n 8003052 <HAL_FLASH_Program+0xc6>
for (index = 0U; index < nbiterations; index++)
8003042: 7dbb ldrb r3, [r7, #22]
8003044: 3301 adds r3, #1
8003046: 75bb strb r3, [r7, #22]
8003048: 7dba ldrb r2, [r7, #22]
800304a: 7d7b ldrb r3, [r7, #21]
800304c: 429a cmp r2, r3
800304e: d3cd bcc.n 8002fec <HAL_FLASH_Program+0x60>
8003050: e000 b.n 8003054 <HAL_FLASH_Program+0xc8>
{
break;
8003052: bf00 nop
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8003054: 4b03 ldr r3, [pc, #12] @ (8003064 <HAL_FLASH_Program+0xd8>)
8003056: 2200 movs r2, #0
8003058: 761a strb r2, [r3, #24]
return status;
800305a: 7dfb ldrb r3, [r7, #23]
}
800305c: 4618 mov r0, r3
800305e: 371c adds r7, #28
8003060: 46bd mov sp, r7
8003062: bdf0 pop {r4, r5, r6, r7, pc}
8003064: 200003f0 .word 0x200003f0
8003068: 40022000 .word 0x40022000
0800306c <HAL_FLASH_Unlock>:
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
800306c: b480 push {r7}
800306e: b083 sub sp, #12
8003070: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8003072: 2300 movs r3, #0
8003074: 71fb strb r3, [r7, #7]
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
8003076: 4b0d ldr r3, [pc, #52] @ (80030ac <HAL_FLASH_Unlock+0x40>)
8003078: 691b ldr r3, [r3, #16]
800307a: f003 0380 and.w r3, r3, #128 @ 0x80
800307e: 2b00 cmp r3, #0
8003080: d00d beq.n 800309e <HAL_FLASH_Unlock+0x32>
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
8003082: 4b0a ldr r3, [pc, #40] @ (80030ac <HAL_FLASH_Unlock+0x40>)
8003084: 4a0a ldr r2, [pc, #40] @ (80030b0 <HAL_FLASH_Unlock+0x44>)
8003086: 605a str r2, [r3, #4]
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
8003088: 4b08 ldr r3, [pc, #32] @ (80030ac <HAL_FLASH_Unlock+0x40>)
800308a: 4a0a ldr r2, [pc, #40] @ (80030b4 <HAL_FLASH_Unlock+0x48>)
800308c: 605a str r2, [r3, #4]
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
800308e: 4b07 ldr r3, [pc, #28] @ (80030ac <HAL_FLASH_Unlock+0x40>)
8003090: 691b ldr r3, [r3, #16]
8003092: f003 0380 and.w r3, r3, #128 @ 0x80
8003096: 2b00 cmp r3, #0
8003098: d001 beq.n 800309e <HAL_FLASH_Unlock+0x32>
{
status = HAL_ERROR;
800309a: 2301 movs r3, #1
800309c: 71fb strb r3, [r7, #7]
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return status;
800309e: 79fb ldrb r3, [r7, #7]
}
80030a0: 4618 mov r0, r3
80030a2: 370c adds r7, #12
80030a4: 46bd mov sp, r7
80030a6: bc80 pop {r7}
80030a8: 4770 bx lr
80030aa: bf00 nop
80030ac: 40022000 .word 0x40022000
80030b0: 45670123 .word 0x45670123
80030b4: cdef89ab .word 0xcdef89ab
080030b8 <HAL_FLASH_Lock>:
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
80030b8: b480 push {r7}
80030ba: af00 add r7, sp, #0
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
80030bc: 4b05 ldr r3, [pc, #20] @ (80030d4 <HAL_FLASH_Lock+0x1c>)
80030be: 691b ldr r3, [r3, #16]
80030c0: 4a04 ldr r2, [pc, #16] @ (80030d4 <HAL_FLASH_Lock+0x1c>)
80030c2: f043 0380 orr.w r3, r3, #128 @ 0x80
80030c6: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
#endif /* FLASH_BANK2_END */
return HAL_OK;
80030c8: 2300 movs r3, #0
}
80030ca: 4618 mov r0, r3
80030cc: 46bd mov sp, r7
80030ce: bc80 pop {r7}
80030d0: 4770 bx lr
80030d2: bf00 nop
80030d4: 40022000 .word 0x40022000
080030d8 <FLASH_Program_HalfWord>:
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
80030d8: b480 push {r7}
80030da: b083 sub sp, #12
80030dc: af00 add r7, sp, #0
80030de: 6078 str r0, [r7, #4]
80030e0: 460b mov r3, r1
80030e2: 807b strh r3, [r7, #2]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
80030e4: 4b08 ldr r3, [pc, #32] @ (8003108 <FLASH_Program_HalfWord+0x30>)
80030e6: 2200 movs r2, #0
80030e8: 61da str r2, [r3, #28]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Proceed to program the new data */
SET_BIT(FLASH->CR, FLASH_CR_PG);
80030ea: 4b08 ldr r3, [pc, #32] @ (800310c <FLASH_Program_HalfWord+0x34>)
80030ec: 691b ldr r3, [r3, #16]
80030ee: 4a07 ldr r2, [pc, #28] @ (800310c <FLASH_Program_HalfWord+0x34>)
80030f0: f043 0301 orr.w r3, r3, #1
80030f4: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* Write data in the address */
*(__IO uint16_t*)Address = Data;
80030f6: 687b ldr r3, [r7, #4]
80030f8: 887a ldrh r2, [r7, #2]
80030fa: 801a strh r2, [r3, #0]
}
80030fc: bf00 nop
80030fe: 370c adds r7, #12
8003100: 46bd mov sp, r7
8003102: bc80 pop {r7}
8003104: 4770 bx lr
8003106: bf00 nop
8003108: 200003f0 .word 0x200003f0
800310c: 40022000 .word 0x40022000
08003110 <FLASH_WaitForLastOperation>:
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
8003110: b580 push {r7, lr}
8003112: b084 sub sp, #16
8003114: af00 add r7, sp, #0
8003116: 6078 str r0, [r7, #4]
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
8003118: f7ff f860 bl 80021dc <HAL_GetTick>
800311c: 60f8 str r0, [r7, #12]
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
800311e: e010 b.n 8003142 <FLASH_WaitForLastOperation+0x32>
{
if (Timeout != HAL_MAX_DELAY)
8003120: 687b ldr r3, [r7, #4]
8003122: f1b3 3fff cmp.w r3, #4294967295
8003126: d00c beq.n 8003142 <FLASH_WaitForLastOperation+0x32>
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
8003128: 687b ldr r3, [r7, #4]
800312a: 2b00 cmp r3, #0
800312c: d007 beq.n 800313e <FLASH_WaitForLastOperation+0x2e>
800312e: f7ff f855 bl 80021dc <HAL_GetTick>
8003132: 4602 mov r2, r0
8003134: 68fb ldr r3, [r7, #12]
8003136: 1ad3 subs r3, r2, r3
8003138: 687a ldr r2, [r7, #4]
800313a: 429a cmp r2, r3
800313c: d201 bcs.n 8003142 <FLASH_WaitForLastOperation+0x32>
{
return HAL_TIMEOUT;
800313e: 2303 movs r3, #3
8003140: e025 b.n 800318e <FLASH_WaitForLastOperation+0x7e>
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
8003142: 4b15 ldr r3, [pc, #84] @ (8003198 <FLASH_WaitForLastOperation+0x88>)
8003144: 68db ldr r3, [r3, #12]
8003146: f003 0301 and.w r3, r3, #1
800314a: 2b00 cmp r3, #0
800314c: d1e8 bne.n 8003120 <FLASH_WaitForLastOperation+0x10>
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
800314e: 4b12 ldr r3, [pc, #72] @ (8003198 <FLASH_WaitForLastOperation+0x88>)
8003150: 68db ldr r3, [r3, #12]
8003152: f003 0320 and.w r3, r3, #32
8003156: 2b00 cmp r3, #0
8003158: d002 beq.n 8003160 <FLASH_WaitForLastOperation+0x50>
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
800315a: 4b0f ldr r3, [pc, #60] @ (8003198 <FLASH_WaitForLastOperation+0x88>)
800315c: 2220 movs r2, #32
800315e: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8003160: 4b0d ldr r3, [pc, #52] @ (8003198 <FLASH_WaitForLastOperation+0x88>)
8003162: 68db ldr r3, [r3, #12]
8003164: f003 0310 and.w r3, r3, #16
8003168: 2b00 cmp r3, #0
800316a: d10b bne.n 8003184 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
800316c: 4b0a ldr r3, [pc, #40] @ (8003198 <FLASH_WaitForLastOperation+0x88>)
800316e: 69db ldr r3, [r3, #28]
8003170: f003 0301 and.w r3, r3, #1
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8003174: 2b00 cmp r3, #0
8003176: d105 bne.n 8003184 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
8003178: 4b07 ldr r3, [pc, #28] @ (8003198 <FLASH_WaitForLastOperation+0x88>)
800317a: 68db ldr r3, [r3, #12]
800317c: f003 0304 and.w r3, r3, #4
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
8003180: 2b00 cmp r3, #0
8003182: d003 beq.n 800318c <FLASH_WaitForLastOperation+0x7c>
{
/*Save the error code*/
FLASH_SetErrorCode();
8003184: f000 f80a bl 800319c <FLASH_SetErrorCode>
return HAL_ERROR;
8003188: 2301 movs r3, #1
800318a: e000 b.n 800318e <FLASH_WaitForLastOperation+0x7e>
}
/* There is no error flag set */
return HAL_OK;
800318c: 2300 movs r3, #0
}
800318e: 4618 mov r0, r3
8003190: 3710 adds r7, #16
8003192: 46bd mov sp, r7
8003194: bd80 pop {r7, pc}
8003196: bf00 nop
8003198: 40022000 .word 0x40022000
0800319c <FLASH_SetErrorCode>:
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
800319c: b480 push {r7}
800319e: b083 sub sp, #12
80031a0: af00 add r7, sp, #0
uint32_t flags = 0U;
80031a2: 2300 movs r3, #0
80031a4: 607b str r3, [r7, #4]
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
80031a6: 4b23 ldr r3, [pc, #140] @ (8003234 <FLASH_SetErrorCode+0x98>)
80031a8: 68db ldr r3, [r3, #12]
80031aa: f003 0310 and.w r3, r3, #16
80031ae: 2b00 cmp r3, #0
80031b0: d009 beq.n 80031c6 <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
80031b2: 4b21 ldr r3, [pc, #132] @ (8003238 <FLASH_SetErrorCode+0x9c>)
80031b4: 69db ldr r3, [r3, #28]
80031b6: f043 0302 orr.w r3, r3, #2
80031ba: 4a1f ldr r2, [pc, #124] @ (8003238 <FLASH_SetErrorCode+0x9c>)
80031bc: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
flags |= FLASH_FLAG_WRPERR;
80031be: 687b ldr r3, [r7, #4]
80031c0: f043 0310 orr.w r3, r3, #16
80031c4: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
80031c6: 4b1b ldr r3, [pc, #108] @ (8003234 <FLASH_SetErrorCode+0x98>)
80031c8: 68db ldr r3, [r3, #12]
80031ca: f003 0304 and.w r3, r3, #4
80031ce: 2b00 cmp r3, #0
80031d0: d009 beq.n 80031e6 <FLASH_SetErrorCode+0x4a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
80031d2: 4b19 ldr r3, [pc, #100] @ (8003238 <FLASH_SetErrorCode+0x9c>)
80031d4: 69db ldr r3, [r3, #28]
80031d6: f043 0301 orr.w r3, r3, #1
80031da: 4a17 ldr r2, [pc, #92] @ (8003238 <FLASH_SetErrorCode+0x9c>)
80031dc: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
flags |= FLASH_FLAG_PGERR;
80031de: 687b ldr r3, [r7, #4]
80031e0: f043 0304 orr.w r3, r3, #4
80031e4: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
80031e6: 4b13 ldr r3, [pc, #76] @ (8003234 <FLASH_SetErrorCode+0x98>)
80031e8: 69db ldr r3, [r3, #28]
80031ea: f003 0301 and.w r3, r3, #1
80031ee: 2b00 cmp r3, #0
80031f0: d00b beq.n 800320a <FLASH_SetErrorCode+0x6e>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
80031f2: 4b11 ldr r3, [pc, #68] @ (8003238 <FLASH_SetErrorCode+0x9c>)
80031f4: 69db ldr r3, [r3, #28]
80031f6: f043 0304 orr.w r3, r3, #4
80031fa: 4a0f ldr r2, [pc, #60] @ (8003238 <FLASH_SetErrorCode+0x9c>)
80031fc: 61d3 str r3, [r2, #28]
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
80031fe: 4b0d ldr r3, [pc, #52] @ (8003234 <FLASH_SetErrorCode+0x98>)
8003200: 69db ldr r3, [r3, #28]
8003202: 4a0c ldr r2, [pc, #48] @ (8003234 <FLASH_SetErrorCode+0x98>)
8003204: f023 0301 bic.w r3, r3, #1
8003208: 61d3 str r3, [r2, #28]
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
800320a: 687b ldr r3, [r7, #4]
800320c: f240 1201 movw r2, #257 @ 0x101
8003210: 4293 cmp r3, r2
8003212: d106 bne.n 8003222 <FLASH_SetErrorCode+0x86>
8003214: 4b07 ldr r3, [pc, #28] @ (8003234 <FLASH_SetErrorCode+0x98>)
8003216: 69db ldr r3, [r3, #28]
8003218: 4a06 ldr r2, [pc, #24] @ (8003234 <FLASH_SetErrorCode+0x98>)
800321a: f023 0301 bic.w r3, r3, #1
800321e: 61d3 str r3, [r2, #28]
}
8003220: e002 b.n 8003228 <FLASH_SetErrorCode+0x8c>
__HAL_FLASH_CLEAR_FLAG(flags);
8003222: 4a04 ldr r2, [pc, #16] @ (8003234 <FLASH_SetErrorCode+0x98>)
8003224: 687b ldr r3, [r7, #4]
8003226: 60d3 str r3, [r2, #12]
}
8003228: bf00 nop
800322a: 370c adds r7, #12
800322c: 46bd mov sp, r7
800322e: bc80 pop {r7}
8003230: 4770 bx lr
8003232: bf00 nop
8003234: 40022000 .word 0x40022000
8003238: 200003f0 .word 0x200003f0
0800323c <HAL_FLASHEx_Erase>:
* (0xFFFFFFFF means that all the pages have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
800323c: b580 push {r7, lr}
800323e: b084 sub sp, #16
8003240: af00 add r7, sp, #0
8003242: 6078 str r0, [r7, #4]
8003244: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_ERROR;
8003246: 2301 movs r3, #1
8003248: 73fb strb r3, [r7, #15]
uint32_t address = 0U;
800324a: 2300 movs r3, #0
800324c: 60bb str r3, [r7, #8]
/* Process Locked */
__HAL_LOCK(&pFlash);
800324e: 4b2f ldr r3, [pc, #188] @ (800330c <HAL_FLASHEx_Erase+0xd0>)
8003250: 7e1b ldrb r3, [r3, #24]
8003252: 2b01 cmp r3, #1
8003254: d101 bne.n 800325a <HAL_FLASHEx_Erase+0x1e>
8003256: 2302 movs r3, #2
8003258: e053 b.n 8003302 <HAL_FLASHEx_Erase+0xc6>
800325a: 4b2c ldr r3, [pc, #176] @ (800330c <HAL_FLASHEx_Erase+0xd0>)
800325c: 2201 movs r2, #1
800325e: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
8003260: 687b ldr r3, [r7, #4]
8003262: 681b ldr r3, [r3, #0]
8003264: 2b02 cmp r3, #2
8003266: d116 bne.n 8003296 <HAL_FLASHEx_Erase+0x5a>
else
#endif /* FLASH_BANK2_END */
{
/* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8003268: f24c 3050 movw r0, #50000 @ 0xc350
800326c: f7ff ff50 bl 8003110 <FLASH_WaitForLastOperation>
8003270: 4603 mov r3, r0
8003272: 2b00 cmp r3, #0
8003274: d141 bne.n 80032fa <HAL_FLASHEx_Erase+0xbe>
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_1);
8003276: 2001 movs r0, #1
8003278: f000 f84c bl 8003314 <FLASH_MassErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
800327c: f24c 3050 movw r0, #50000 @ 0xc350
8003280: f7ff ff46 bl 8003110 <FLASH_WaitForLastOperation>
8003284: 4603 mov r3, r0
8003286: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
8003288: 4b21 ldr r3, [pc, #132] @ (8003310 <HAL_FLASHEx_Erase+0xd4>)
800328a: 691b ldr r3, [r3, #16]
800328c: 4a20 ldr r2, [pc, #128] @ (8003310 <HAL_FLASHEx_Erase+0xd4>)
800328e: f023 0304 bic.w r3, r3, #4
8003292: 6113 str r3, [r2, #16]
8003294: e031 b.n 80032fa <HAL_FLASHEx_Erase+0xbe>
else
#endif /* FLASH_BANK2_END */
{
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8003296: f24c 3050 movw r0, #50000 @ 0xc350
800329a: f7ff ff39 bl 8003110 <FLASH_WaitForLastOperation>
800329e: 4603 mov r3, r0
80032a0: 2b00 cmp r3, #0
80032a2: d12a bne.n 80032fa <HAL_FLASHEx_Erase+0xbe>
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
80032a4: 683b ldr r3, [r7, #0]
80032a6: f04f 32ff mov.w r2, #4294967295
80032aa: 601a str r2, [r3, #0]
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
80032ac: 687b ldr r3, [r7, #4]
80032ae: 689b ldr r3, [r3, #8]
80032b0: 60bb str r3, [r7, #8]
80032b2: e019 b.n 80032e8 <HAL_FLASHEx_Erase+0xac>
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
80032b4: 68b8 ldr r0, [r7, #8]
80032b6: f000 f849 bl 800334c <FLASH_PageErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
80032ba: f24c 3050 movw r0, #50000 @ 0xc350
80032be: f7ff ff27 bl 8003110 <FLASH_WaitForLastOperation>
80032c2: 4603 mov r3, r0
80032c4: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
80032c6: 4b12 ldr r3, [pc, #72] @ (8003310 <HAL_FLASHEx_Erase+0xd4>)
80032c8: 691b ldr r3, [r3, #16]
80032ca: 4a11 ldr r2, [pc, #68] @ (8003310 <HAL_FLASHEx_Erase+0xd4>)
80032cc: f023 0302 bic.w r3, r3, #2
80032d0: 6113 str r3, [r2, #16]
if (status != HAL_OK)
80032d2: 7bfb ldrb r3, [r7, #15]
80032d4: 2b00 cmp r3, #0
80032d6: d003 beq.n 80032e0 <HAL_FLASHEx_Erase+0xa4>
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
80032d8: 683b ldr r3, [r7, #0]
80032da: 68ba ldr r2, [r7, #8]
80032dc: 601a str r2, [r3, #0]
break;
80032de: e00c b.n 80032fa <HAL_FLASHEx_Erase+0xbe>
address += FLASH_PAGE_SIZE)
80032e0: 68bb ldr r3, [r7, #8]
80032e2: f503 6380 add.w r3, r3, #1024 @ 0x400
80032e6: 60bb str r3, [r7, #8]
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
80032e8: 687b ldr r3, [r7, #4]
80032ea: 68db ldr r3, [r3, #12]
80032ec: 029a lsls r2, r3, #10
80032ee: 687b ldr r3, [r7, #4]
80032f0: 689b ldr r3, [r3, #8]
80032f2: 4413 add r3, r2
80032f4: 68ba ldr r2, [r7, #8]
80032f6: 429a cmp r2, r3
80032f8: d3dc bcc.n 80032b4 <HAL_FLASHEx_Erase+0x78>
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
80032fa: 4b04 ldr r3, [pc, #16] @ (800330c <HAL_FLASHEx_Erase+0xd0>)
80032fc: 2200 movs r2, #0
80032fe: 761a strb r2, [r3, #24]
return status;
8003300: 7bfb ldrb r3, [r7, #15]
}
8003302: 4618 mov r0, r3
8003304: 3710 adds r7, #16
8003306: 46bd mov sp, r7
8003308: bd80 pop {r7, pc}
800330a: bf00 nop
800330c: 200003f0 .word 0x200003f0
8003310: 40022000 .word 0x40022000
08003314 <FLASH_MassErase>:
@endif
*
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
8003314: b480 push {r7}
8003316: b083 sub sp, #12
8003318: af00 add r7, sp, #0
800331a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
800331c: 4b09 ldr r3, [pc, #36] @ (8003344 <FLASH_MassErase+0x30>)
800331e: 2200 movs r2, #0
8003320: 61da str r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH->CR, FLASH_CR_MER);
8003322: 4b09 ldr r3, [pc, #36] @ (8003348 <FLASH_MassErase+0x34>)
8003324: 691b ldr r3, [r3, #16]
8003326: 4a08 ldr r2, [pc, #32] @ (8003348 <FLASH_MassErase+0x34>)
8003328: f043 0304 orr.w r3, r3, #4
800332c: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
800332e: 4b06 ldr r3, [pc, #24] @ (8003348 <FLASH_MassErase+0x34>)
8003330: 691b ldr r3, [r3, #16]
8003332: 4a05 ldr r2, [pc, #20] @ (8003348 <FLASH_MassErase+0x34>)
8003334: f043 0340 orr.w r3, r3, #64 @ 0x40
8003338: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
800333a: bf00 nop
800333c: 370c adds r7, #12
800333e: 46bd mov sp, r7
8003340: bc80 pop {r7}
8003342: 4770 bx lr
8003344: 200003f0 .word 0x200003f0
8003348: 40022000 .word 0x40022000
0800334c <FLASH_PageErase>:
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)
{
800334c: b480 push {r7}
800334e: b083 sub sp, #12
8003350: af00 add r7, sp, #0
8003352: 6078 str r0, [r7, #4]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8003354: 4b0b ldr r3, [pc, #44] @ (8003384 <FLASH_PageErase+0x38>)
8003356: 2200 movs r2, #0
8003358: 61da str r2, [r3, #28]
}
else
{
#endif /* FLASH_BANK2_END */
/* Proceed to erase the page */
SET_BIT(FLASH->CR, FLASH_CR_PER);
800335a: 4b0b ldr r3, [pc, #44] @ (8003388 <FLASH_PageErase+0x3c>)
800335c: 691b ldr r3, [r3, #16]
800335e: 4a0a ldr r2, [pc, #40] @ (8003388 <FLASH_PageErase+0x3c>)
8003360: f043 0302 orr.w r3, r3, #2
8003364: 6113 str r3, [r2, #16]
WRITE_REG(FLASH->AR, PageAddress);
8003366: 4a08 ldr r2, [pc, #32] @ (8003388 <FLASH_PageErase+0x3c>)
8003368: 687b ldr r3, [r7, #4]
800336a: 6153 str r3, [r2, #20]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
800336c: 4b06 ldr r3, [pc, #24] @ (8003388 <FLASH_PageErase+0x3c>)
800336e: 691b ldr r3, [r3, #16]
8003370: 4a05 ldr r2, [pc, #20] @ (8003388 <FLASH_PageErase+0x3c>)
8003372: f043 0340 orr.w r3, r3, #64 @ 0x40
8003376: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8003378: bf00 nop
800337a: 370c adds r7, #12
800337c: 46bd mov sp, r7
800337e: bc80 pop {r7}
8003380: 4770 bx lr
8003382: bf00 nop
8003384: 200003f0 .word 0x200003f0
8003388: 40022000 .word 0x40022000
0800338c <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800338c: b480 push {r7}
800338e: b08b sub sp, #44 @ 0x2c
8003390: af00 add r7, sp, #0
8003392: 6078 str r0, [r7, #4]
8003394: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003396: 2300 movs r3, #0
8003398: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
800339a: 2300 movs r3, #0
800339c: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800339e: e169 b.n 8003674 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
80033a0: 2201 movs r2, #1
80033a2: 6a7b ldr r3, [r7, #36] @ 0x24
80033a4: fa02 f303 lsl.w r3, r2, r3
80033a8: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80033aa: 683b ldr r3, [r7, #0]
80033ac: 681b ldr r3, [r3, #0]
80033ae: 69fa ldr r2, [r7, #28]
80033b0: 4013 ands r3, r2
80033b2: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
80033b4: 69ba ldr r2, [r7, #24]
80033b6: 69fb ldr r3, [r7, #28]
80033b8: 429a cmp r2, r3
80033ba: f040 8158 bne.w 800366e <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
80033be: 683b ldr r3, [r7, #0]
80033c0: 685b ldr r3, [r3, #4]
80033c2: 4a9a ldr r2, [pc, #616] @ (800362c <HAL_GPIO_Init+0x2a0>)
80033c4: 4293 cmp r3, r2
80033c6: d05e beq.n 8003486 <HAL_GPIO_Init+0xfa>
80033c8: 4a98 ldr r2, [pc, #608] @ (800362c <HAL_GPIO_Init+0x2a0>)
80033ca: 4293 cmp r3, r2
80033cc: d875 bhi.n 80034ba <HAL_GPIO_Init+0x12e>
80033ce: 4a98 ldr r2, [pc, #608] @ (8003630 <HAL_GPIO_Init+0x2a4>)
80033d0: 4293 cmp r3, r2
80033d2: d058 beq.n 8003486 <HAL_GPIO_Init+0xfa>
80033d4: 4a96 ldr r2, [pc, #600] @ (8003630 <HAL_GPIO_Init+0x2a4>)
80033d6: 4293 cmp r3, r2
80033d8: d86f bhi.n 80034ba <HAL_GPIO_Init+0x12e>
80033da: 4a96 ldr r2, [pc, #600] @ (8003634 <HAL_GPIO_Init+0x2a8>)
80033dc: 4293 cmp r3, r2
80033de: d052 beq.n 8003486 <HAL_GPIO_Init+0xfa>
80033e0: 4a94 ldr r2, [pc, #592] @ (8003634 <HAL_GPIO_Init+0x2a8>)
80033e2: 4293 cmp r3, r2
80033e4: d869 bhi.n 80034ba <HAL_GPIO_Init+0x12e>
80033e6: 4a94 ldr r2, [pc, #592] @ (8003638 <HAL_GPIO_Init+0x2ac>)
80033e8: 4293 cmp r3, r2
80033ea: d04c beq.n 8003486 <HAL_GPIO_Init+0xfa>
80033ec: 4a92 ldr r2, [pc, #584] @ (8003638 <HAL_GPIO_Init+0x2ac>)
80033ee: 4293 cmp r3, r2
80033f0: d863 bhi.n 80034ba <HAL_GPIO_Init+0x12e>
80033f2: 4a92 ldr r2, [pc, #584] @ (800363c <HAL_GPIO_Init+0x2b0>)
80033f4: 4293 cmp r3, r2
80033f6: d046 beq.n 8003486 <HAL_GPIO_Init+0xfa>
80033f8: 4a90 ldr r2, [pc, #576] @ (800363c <HAL_GPIO_Init+0x2b0>)
80033fa: 4293 cmp r3, r2
80033fc: d85d bhi.n 80034ba <HAL_GPIO_Init+0x12e>
80033fe: 2b12 cmp r3, #18
8003400: d82a bhi.n 8003458 <HAL_GPIO_Init+0xcc>
8003402: 2b12 cmp r3, #18
8003404: d859 bhi.n 80034ba <HAL_GPIO_Init+0x12e>
8003406: a201 add r2, pc, #4 @ (adr r2, 800340c <HAL_GPIO_Init+0x80>)
8003408: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800340c: 08003487 .word 0x08003487
8003410: 08003461 .word 0x08003461
8003414: 08003473 .word 0x08003473
8003418: 080034b5 .word 0x080034b5
800341c: 080034bb .word 0x080034bb
8003420: 080034bb .word 0x080034bb
8003424: 080034bb .word 0x080034bb
8003428: 080034bb .word 0x080034bb
800342c: 080034bb .word 0x080034bb
8003430: 080034bb .word 0x080034bb
8003434: 080034bb .word 0x080034bb
8003438: 080034bb .word 0x080034bb
800343c: 080034bb .word 0x080034bb
8003440: 080034bb .word 0x080034bb
8003444: 080034bb .word 0x080034bb
8003448: 080034bb .word 0x080034bb
800344c: 080034bb .word 0x080034bb
8003450: 08003469 .word 0x08003469
8003454: 0800347d .word 0x0800347d
8003458: 4a79 ldr r2, [pc, #484] @ (8003640 <HAL_GPIO_Init+0x2b4>)
800345a: 4293 cmp r3, r2
800345c: d013 beq.n 8003486 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
800345e: e02c b.n 80034ba <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8003460: 683b ldr r3, [r7, #0]
8003462: 68db ldr r3, [r3, #12]
8003464: 623b str r3, [r7, #32]
break;
8003466: e029 b.n 80034bc <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8003468: 683b ldr r3, [r7, #0]
800346a: 68db ldr r3, [r3, #12]
800346c: 3304 adds r3, #4
800346e: 623b str r3, [r7, #32]
break;
8003470: e024 b.n 80034bc <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8003472: 683b ldr r3, [r7, #0]
8003474: 68db ldr r3, [r3, #12]
8003476: 3308 adds r3, #8
8003478: 623b str r3, [r7, #32]
break;
800347a: e01f b.n 80034bc <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
800347c: 683b ldr r3, [r7, #0]
800347e: 68db ldr r3, [r3, #12]
8003480: 330c adds r3, #12
8003482: 623b str r3, [r7, #32]
break;
8003484: e01a b.n 80034bc <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8003486: 683b ldr r3, [r7, #0]
8003488: 689b ldr r3, [r3, #8]
800348a: 2b00 cmp r3, #0
800348c: d102 bne.n 8003494 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800348e: 2304 movs r3, #4
8003490: 623b str r3, [r7, #32]
break;
8003492: e013 b.n 80034bc <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8003494: 683b ldr r3, [r7, #0]
8003496: 689b ldr r3, [r3, #8]
8003498: 2b01 cmp r3, #1
800349a: d105 bne.n 80034a8 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
800349c: 2308 movs r3, #8
800349e: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
80034a0: 687b ldr r3, [r7, #4]
80034a2: 69fa ldr r2, [r7, #28]
80034a4: 611a str r2, [r3, #16]
break;
80034a6: e009 b.n 80034bc <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
80034a8: 2308 movs r3, #8
80034aa: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
80034ac: 687b ldr r3, [r7, #4]
80034ae: 69fa ldr r2, [r7, #28]
80034b0: 615a str r2, [r3, #20]
break;
80034b2: e003 b.n 80034bc <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
80034b4: 2300 movs r3, #0
80034b6: 623b str r3, [r7, #32]
break;
80034b8: e000 b.n 80034bc <HAL_GPIO_Init+0x130>
break;
80034ba: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
80034bc: 69bb ldr r3, [r7, #24]
80034be: 2bff cmp r3, #255 @ 0xff
80034c0: d801 bhi.n 80034c6 <HAL_GPIO_Init+0x13a>
80034c2: 687b ldr r3, [r7, #4]
80034c4: e001 b.n 80034ca <HAL_GPIO_Init+0x13e>
80034c6: 687b ldr r3, [r7, #4]
80034c8: 3304 adds r3, #4
80034ca: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
80034cc: 69bb ldr r3, [r7, #24]
80034ce: 2bff cmp r3, #255 @ 0xff
80034d0: d802 bhi.n 80034d8 <HAL_GPIO_Init+0x14c>
80034d2: 6a7b ldr r3, [r7, #36] @ 0x24
80034d4: 009b lsls r3, r3, #2
80034d6: e002 b.n 80034de <HAL_GPIO_Init+0x152>
80034d8: 6a7b ldr r3, [r7, #36] @ 0x24
80034da: 3b08 subs r3, #8
80034dc: 009b lsls r3, r3, #2
80034de: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80034e0: 697b ldr r3, [r7, #20]
80034e2: 681a ldr r2, [r3, #0]
80034e4: 210f movs r1, #15
80034e6: 693b ldr r3, [r7, #16]
80034e8: fa01 f303 lsl.w r3, r1, r3
80034ec: 43db mvns r3, r3
80034ee: 401a ands r2, r3
80034f0: 6a39 ldr r1, [r7, #32]
80034f2: 693b ldr r3, [r7, #16]
80034f4: fa01 f303 lsl.w r3, r1, r3
80034f8: 431a orrs r2, r3
80034fa: 697b ldr r3, [r7, #20]
80034fc: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80034fe: 683b ldr r3, [r7, #0]
8003500: 685b ldr r3, [r3, #4]
8003502: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003506: 2b00 cmp r3, #0
8003508: f000 80b1 beq.w 800366e <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
800350c: 4b4d ldr r3, [pc, #308] @ (8003644 <HAL_GPIO_Init+0x2b8>)
800350e: 699b ldr r3, [r3, #24]
8003510: 4a4c ldr r2, [pc, #304] @ (8003644 <HAL_GPIO_Init+0x2b8>)
8003512: f043 0301 orr.w r3, r3, #1
8003516: 6193 str r3, [r2, #24]
8003518: 4b4a ldr r3, [pc, #296] @ (8003644 <HAL_GPIO_Init+0x2b8>)
800351a: 699b ldr r3, [r3, #24]
800351c: f003 0301 and.w r3, r3, #1
8003520: 60bb str r3, [r7, #8]
8003522: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8003524: 4a48 ldr r2, [pc, #288] @ (8003648 <HAL_GPIO_Init+0x2bc>)
8003526: 6a7b ldr r3, [r7, #36] @ 0x24
8003528: 089b lsrs r3, r3, #2
800352a: 3302 adds r3, #2
800352c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003530: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8003532: 6a7b ldr r3, [r7, #36] @ 0x24
8003534: f003 0303 and.w r3, r3, #3
8003538: 009b lsls r3, r3, #2
800353a: 220f movs r2, #15
800353c: fa02 f303 lsl.w r3, r2, r3
8003540: 43db mvns r3, r3
8003542: 68fa ldr r2, [r7, #12]
8003544: 4013 ands r3, r2
8003546: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8003548: 687b ldr r3, [r7, #4]
800354a: 4a40 ldr r2, [pc, #256] @ (800364c <HAL_GPIO_Init+0x2c0>)
800354c: 4293 cmp r3, r2
800354e: d013 beq.n 8003578 <HAL_GPIO_Init+0x1ec>
8003550: 687b ldr r3, [r7, #4]
8003552: 4a3f ldr r2, [pc, #252] @ (8003650 <HAL_GPIO_Init+0x2c4>)
8003554: 4293 cmp r3, r2
8003556: d00d beq.n 8003574 <HAL_GPIO_Init+0x1e8>
8003558: 687b ldr r3, [r7, #4]
800355a: 4a3e ldr r2, [pc, #248] @ (8003654 <HAL_GPIO_Init+0x2c8>)
800355c: 4293 cmp r3, r2
800355e: d007 beq.n 8003570 <HAL_GPIO_Init+0x1e4>
8003560: 687b ldr r3, [r7, #4]
8003562: 4a3d ldr r2, [pc, #244] @ (8003658 <HAL_GPIO_Init+0x2cc>)
8003564: 4293 cmp r3, r2
8003566: d101 bne.n 800356c <HAL_GPIO_Init+0x1e0>
8003568: 2303 movs r3, #3
800356a: e006 b.n 800357a <HAL_GPIO_Init+0x1ee>
800356c: 2304 movs r3, #4
800356e: e004 b.n 800357a <HAL_GPIO_Init+0x1ee>
8003570: 2302 movs r3, #2
8003572: e002 b.n 800357a <HAL_GPIO_Init+0x1ee>
8003574: 2301 movs r3, #1
8003576: e000 b.n 800357a <HAL_GPIO_Init+0x1ee>
8003578: 2300 movs r3, #0
800357a: 6a7a ldr r2, [r7, #36] @ 0x24
800357c: f002 0203 and.w r2, r2, #3
8003580: 0092 lsls r2, r2, #2
8003582: 4093 lsls r3, r2
8003584: 68fa ldr r2, [r7, #12]
8003586: 4313 orrs r3, r2
8003588: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
800358a: 492f ldr r1, [pc, #188] @ (8003648 <HAL_GPIO_Init+0x2bc>)
800358c: 6a7b ldr r3, [r7, #36] @ 0x24
800358e: 089b lsrs r3, r3, #2
8003590: 3302 adds r3, #2
8003592: 68fa ldr r2, [r7, #12]
8003594: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8003598: 683b ldr r3, [r7, #0]
800359a: 685b ldr r3, [r3, #4]
800359c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80035a0: 2b00 cmp r3, #0
80035a2: d006 beq.n 80035b2 <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
80035a4: 4b2d ldr r3, [pc, #180] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035a6: 689a ldr r2, [r3, #8]
80035a8: 492c ldr r1, [pc, #176] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035aa: 69bb ldr r3, [r7, #24]
80035ac: 4313 orrs r3, r2
80035ae: 608b str r3, [r1, #8]
80035b0: e006 b.n 80035c0 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
80035b2: 4b2a ldr r3, [pc, #168] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035b4: 689a ldr r2, [r3, #8]
80035b6: 69bb ldr r3, [r7, #24]
80035b8: 43db mvns r3, r3
80035ba: 4928 ldr r1, [pc, #160] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035bc: 4013 ands r3, r2
80035be: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
80035c0: 683b ldr r3, [r7, #0]
80035c2: 685b ldr r3, [r3, #4]
80035c4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80035c8: 2b00 cmp r3, #0
80035ca: d006 beq.n 80035da <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
80035cc: 4b23 ldr r3, [pc, #140] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035ce: 68da ldr r2, [r3, #12]
80035d0: 4922 ldr r1, [pc, #136] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035d2: 69bb ldr r3, [r7, #24]
80035d4: 4313 orrs r3, r2
80035d6: 60cb str r3, [r1, #12]
80035d8: e006 b.n 80035e8 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
80035da: 4b20 ldr r3, [pc, #128] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035dc: 68da ldr r2, [r3, #12]
80035de: 69bb ldr r3, [r7, #24]
80035e0: 43db mvns r3, r3
80035e2: 491e ldr r1, [pc, #120] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035e4: 4013 ands r3, r2
80035e6: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
80035e8: 683b ldr r3, [r7, #0]
80035ea: 685b ldr r3, [r3, #4]
80035ec: f403 3300 and.w r3, r3, #131072 @ 0x20000
80035f0: 2b00 cmp r3, #0
80035f2: d006 beq.n 8003602 <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
80035f4: 4b19 ldr r3, [pc, #100] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035f6: 685a ldr r2, [r3, #4]
80035f8: 4918 ldr r1, [pc, #96] @ (800365c <HAL_GPIO_Init+0x2d0>)
80035fa: 69bb ldr r3, [r7, #24]
80035fc: 4313 orrs r3, r2
80035fe: 604b str r3, [r1, #4]
8003600: e006 b.n 8003610 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8003602: 4b16 ldr r3, [pc, #88] @ (800365c <HAL_GPIO_Init+0x2d0>)
8003604: 685a ldr r2, [r3, #4]
8003606: 69bb ldr r3, [r7, #24]
8003608: 43db mvns r3, r3
800360a: 4914 ldr r1, [pc, #80] @ (800365c <HAL_GPIO_Init+0x2d0>)
800360c: 4013 ands r3, r2
800360e: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8003610: 683b ldr r3, [r7, #0]
8003612: 685b ldr r3, [r3, #4]
8003614: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003618: 2b00 cmp r3, #0
800361a: d021 beq.n 8003660 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
800361c: 4b0f ldr r3, [pc, #60] @ (800365c <HAL_GPIO_Init+0x2d0>)
800361e: 681a ldr r2, [r3, #0]
8003620: 490e ldr r1, [pc, #56] @ (800365c <HAL_GPIO_Init+0x2d0>)
8003622: 69bb ldr r3, [r7, #24]
8003624: 4313 orrs r3, r2
8003626: 600b str r3, [r1, #0]
8003628: e021 b.n 800366e <HAL_GPIO_Init+0x2e2>
800362a: bf00 nop
800362c: 10320000 .word 0x10320000
8003630: 10310000 .word 0x10310000
8003634: 10220000 .word 0x10220000
8003638: 10210000 .word 0x10210000
800363c: 10120000 .word 0x10120000
8003640: 10110000 .word 0x10110000
8003644: 40021000 .word 0x40021000
8003648: 40010000 .word 0x40010000
800364c: 40010800 .word 0x40010800
8003650: 40010c00 .word 0x40010c00
8003654: 40011000 .word 0x40011000
8003658: 40011400 .word 0x40011400
800365c: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8003660: 4b0b ldr r3, [pc, #44] @ (8003690 <HAL_GPIO_Init+0x304>)
8003662: 681a ldr r2, [r3, #0]
8003664: 69bb ldr r3, [r7, #24]
8003666: 43db mvns r3, r3
8003668: 4909 ldr r1, [pc, #36] @ (8003690 <HAL_GPIO_Init+0x304>)
800366a: 4013 ands r3, r2
800366c: 600b str r3, [r1, #0]
}
}
}
position++;
800366e: 6a7b ldr r3, [r7, #36] @ 0x24
8003670: 3301 adds r3, #1
8003672: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003674: 683b ldr r3, [r7, #0]
8003676: 681a ldr r2, [r3, #0]
8003678: 6a7b ldr r3, [r7, #36] @ 0x24
800367a: fa22 f303 lsr.w r3, r2, r3
800367e: 2b00 cmp r3, #0
8003680: f47f ae8e bne.w 80033a0 <HAL_GPIO_Init+0x14>
}
}
8003684: bf00 nop
8003686: bf00 nop
8003688: 372c adds r7, #44 @ 0x2c
800368a: 46bd mov sp, r7
800368c: bc80 pop {r7}
800368e: 4770 bx lr
8003690: 40010400 .word 0x40010400
08003694 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003694: b480 push {r7}
8003696: b085 sub sp, #20
8003698: af00 add r7, sp, #0
800369a: 6078 str r0, [r7, #4]
800369c: 460b mov r3, r1
800369e: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
80036a0: 687b ldr r3, [r7, #4]
80036a2: 689a ldr r2, [r3, #8]
80036a4: 887b ldrh r3, [r7, #2]
80036a6: 4013 ands r3, r2
80036a8: 2b00 cmp r3, #0
80036aa: d002 beq.n 80036b2 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
80036ac: 2301 movs r3, #1
80036ae: 73fb strb r3, [r7, #15]
80036b0: e001 b.n 80036b6 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
80036b2: 2300 movs r3, #0
80036b4: 73fb strb r3, [r7, #15]
}
return bitstatus;
80036b6: 7bfb ldrb r3, [r7, #15]
}
80036b8: 4618 mov r0, r3
80036ba: 3714 adds r7, #20
80036bc: 46bd mov sp, r7
80036be: bc80 pop {r7}
80036c0: 4770 bx lr
080036c2 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80036c2: b480 push {r7}
80036c4: b083 sub sp, #12
80036c6: af00 add r7, sp, #0
80036c8: 6078 str r0, [r7, #4]
80036ca: 460b mov r3, r1
80036cc: 807b strh r3, [r7, #2]
80036ce: 4613 mov r3, r2
80036d0: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80036d2: 787b ldrb r3, [r7, #1]
80036d4: 2b00 cmp r3, #0
80036d6: d003 beq.n 80036e0 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80036d8: 887a ldrh r2, [r7, #2]
80036da: 687b ldr r3, [r7, #4]
80036dc: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
80036de: e003 b.n 80036e8 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
80036e0: 887b ldrh r3, [r7, #2]
80036e2: 041a lsls r2, r3, #16
80036e4: 687b ldr r3, [r7, #4]
80036e6: 611a str r2, [r3, #16]
}
80036e8: bf00 nop
80036ea: 370c adds r7, #12
80036ec: 46bd mov sp, r7
80036ee: bc80 pop {r7}
80036f0: 4770 bx lr
080036f2 <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80036f2: b480 push {r7}
80036f4: b085 sub sp, #20
80036f6: af00 add r7, sp, #0
80036f8: 6078 str r0, [r7, #4]
80036fa: 460b mov r3, r1
80036fc: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
80036fe: 687b ldr r3, [r7, #4]
8003700: 68db ldr r3, [r3, #12]
8003702: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8003704: 887a ldrh r2, [r7, #2]
8003706: 68fb ldr r3, [r7, #12]
8003708: 4013 ands r3, r2
800370a: 041a lsls r2, r3, #16
800370c: 68fb ldr r3, [r7, #12]
800370e: 43d9 mvns r1, r3
8003710: 887b ldrh r3, [r7, #2]
8003712: 400b ands r3, r1
8003714: 431a orrs r2, r3
8003716: 687b ldr r3, [r7, #4]
8003718: 611a str r2, [r3, #16]
}
800371a: bf00 nop
800371c: 3714 adds r7, #20
800371e: 46bd mov sp, r7
8003720: bc80 pop {r7}
8003722: 4770 bx lr
08003724 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8003724: b580 push {r7, lr}
8003726: b084 sub sp, #16
8003728: af00 add r7, sp, #0
800372a: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
800372c: 687b ldr r3, [r7, #4]
800372e: 2b00 cmp r3, #0
8003730: d101 bne.n 8003736 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8003732: 2301 movs r3, #1
8003734: e0e8 b.n 8003908 <HAL_PCD_Init+0x1e4>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8003736: 687b ldr r3, [r7, #4]
8003738: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
800373c: b2db uxtb r3, r3
800373e: 2b00 cmp r3, #0
8003740: d106 bne.n 8003750 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8003742: 687b ldr r3, [r7, #4]
8003744: 2200 movs r2, #0
8003746: f883 2290 strb.w r2, [r3, #656] @ 0x290
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
800374a: 6878 ldr r0, [r7, #4]
800374c: f007 face bl 800acec <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8003750: 687b ldr r3, [r7, #4]
8003752: 2203 movs r2, #3
8003754: f883 2291 strb.w r2, [r3, #657] @ 0x291
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
8003758: 687b ldr r3, [r7, #4]
800375a: 2200 movs r2, #0
800375c: 715a strb r2, [r3, #5]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
800375e: 687b ldr r3, [r7, #4]
8003760: 681b ldr r3, [r3, #0]
8003762: 4618 mov r0, r3
8003764: f003 f973 bl 8006a4e <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8003768: 687b ldr r3, [r7, #4]
800376a: 6818 ldr r0, [r3, #0]
800376c: 687b ldr r3, [r7, #4]
800376e: 3304 adds r3, #4
8003770: cb0e ldmia r3, {r1, r2, r3}
8003772: f003 f949 bl 8006a08 <USB_CoreInit>
8003776: 4603 mov r3, r0
8003778: 2b00 cmp r3, #0
800377a: d005 beq.n 8003788 <HAL_PCD_Init+0x64>
{
hpcd->State = HAL_PCD_STATE_ERROR;
800377c: 687b ldr r3, [r7, #4]
800377e: 2202 movs r2, #2
8003780: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8003784: 2301 movs r3, #1
8003786: e0bf b.n 8003908 <HAL_PCD_Init+0x1e4>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
8003788: 687b ldr r3, [r7, #4]
800378a: 681b ldr r3, [r3, #0]
800378c: 2100 movs r1, #0
800378e: 4618 mov r0, r3
8003790: f003 f977 bl 8006a82 <USB_SetCurrentMode>
8003794: 4603 mov r3, r0
8003796: 2b00 cmp r3, #0
8003798: d005 beq.n 80037a6 <HAL_PCD_Init+0x82>
{
hpcd->State = HAL_PCD_STATE_ERROR;
800379a: 687b ldr r3, [r7, #4]
800379c: 2202 movs r2, #2
800379e: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
80037a2: 2301 movs r3, #1
80037a4: e0b0 b.n 8003908 <HAL_PCD_Init+0x1e4>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80037a6: 2300 movs r3, #0
80037a8: 73fb strb r3, [r7, #15]
80037aa: e03e b.n 800382a <HAL_PCD_Init+0x106>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
80037ac: 7bfa ldrb r2, [r7, #15]
80037ae: 6879 ldr r1, [r7, #4]
80037b0: 4613 mov r3, r2
80037b2: 009b lsls r3, r3, #2
80037b4: 4413 add r3, r2
80037b6: 00db lsls r3, r3, #3
80037b8: 440b add r3, r1
80037ba: 3311 adds r3, #17
80037bc: 2201 movs r2, #1
80037be: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
80037c0: 7bfa ldrb r2, [r7, #15]
80037c2: 6879 ldr r1, [r7, #4]
80037c4: 4613 mov r3, r2
80037c6: 009b lsls r3, r3, #2
80037c8: 4413 add r3, r2
80037ca: 00db lsls r3, r3, #3
80037cc: 440b add r3, r1
80037ce: 3310 adds r3, #16
80037d0: 7bfa ldrb r2, [r7, #15]
80037d2: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
80037d4: 7bfa ldrb r2, [r7, #15]
80037d6: 6879 ldr r1, [r7, #4]
80037d8: 4613 mov r3, r2
80037da: 009b lsls r3, r3, #2
80037dc: 4413 add r3, r2
80037de: 00db lsls r3, r3, #3
80037e0: 440b add r3, r1
80037e2: 3313 adds r3, #19
80037e4: 2200 movs r2, #0
80037e6: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
80037e8: 7bfa ldrb r2, [r7, #15]
80037ea: 6879 ldr r1, [r7, #4]
80037ec: 4613 mov r3, r2
80037ee: 009b lsls r3, r3, #2
80037f0: 4413 add r3, r2
80037f2: 00db lsls r3, r3, #3
80037f4: 440b add r3, r1
80037f6: 3320 adds r3, #32
80037f8: 2200 movs r2, #0
80037fa: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
80037fc: 7bfa ldrb r2, [r7, #15]
80037fe: 6879 ldr r1, [r7, #4]
8003800: 4613 mov r3, r2
8003802: 009b lsls r3, r3, #2
8003804: 4413 add r3, r2
8003806: 00db lsls r3, r3, #3
8003808: 440b add r3, r1
800380a: 3324 adds r3, #36 @ 0x24
800380c: 2200 movs r2, #0
800380e: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8003810: 7bfb ldrb r3, [r7, #15]
8003812: 6879 ldr r1, [r7, #4]
8003814: 1c5a adds r2, r3, #1
8003816: 4613 mov r3, r2
8003818: 009b lsls r3, r3, #2
800381a: 4413 add r3, r2
800381c: 00db lsls r3, r3, #3
800381e: 440b add r3, r1
8003820: 2200 movs r2, #0
8003822: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003824: 7bfb ldrb r3, [r7, #15]
8003826: 3301 adds r3, #1
8003828: 73fb strb r3, [r7, #15]
800382a: 687b ldr r3, [r7, #4]
800382c: 791b ldrb r3, [r3, #4]
800382e: 7bfa ldrb r2, [r7, #15]
8003830: 429a cmp r2, r3
8003832: d3bb bcc.n 80037ac <HAL_PCD_Init+0x88>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003834: 2300 movs r3, #0
8003836: 73fb strb r3, [r7, #15]
8003838: e044 b.n 80038c4 <HAL_PCD_Init+0x1a0>
{
hpcd->OUT_ep[i].is_in = 0U;
800383a: 7bfa ldrb r2, [r7, #15]
800383c: 6879 ldr r1, [r7, #4]
800383e: 4613 mov r3, r2
8003840: 009b lsls r3, r3, #2
8003842: 4413 add r3, r2
8003844: 00db lsls r3, r3, #3
8003846: 440b add r3, r1
8003848: f203 1351 addw r3, r3, #337 @ 0x151
800384c: 2200 movs r2, #0
800384e: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8003850: 7bfa ldrb r2, [r7, #15]
8003852: 6879 ldr r1, [r7, #4]
8003854: 4613 mov r3, r2
8003856: 009b lsls r3, r3, #2
8003858: 4413 add r3, r2
800385a: 00db lsls r3, r3, #3
800385c: 440b add r3, r1
800385e: f503 73a8 add.w r3, r3, #336 @ 0x150
8003862: 7bfa ldrb r2, [r7, #15]
8003864: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8003866: 7bfa ldrb r2, [r7, #15]
8003868: 6879 ldr r1, [r7, #4]
800386a: 4613 mov r3, r2
800386c: 009b lsls r3, r3, #2
800386e: 4413 add r3, r2
8003870: 00db lsls r3, r3, #3
8003872: 440b add r3, r1
8003874: f203 1353 addw r3, r3, #339 @ 0x153
8003878: 2200 movs r2, #0
800387a: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
800387c: 7bfa ldrb r2, [r7, #15]
800387e: 6879 ldr r1, [r7, #4]
8003880: 4613 mov r3, r2
8003882: 009b lsls r3, r3, #2
8003884: 4413 add r3, r2
8003886: 00db lsls r3, r3, #3
8003888: 440b add r3, r1
800388a: f503 73b0 add.w r3, r3, #352 @ 0x160
800388e: 2200 movs r2, #0
8003890: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8003892: 7bfa ldrb r2, [r7, #15]
8003894: 6879 ldr r1, [r7, #4]
8003896: 4613 mov r3, r2
8003898: 009b lsls r3, r3, #2
800389a: 4413 add r3, r2
800389c: 00db lsls r3, r3, #3
800389e: 440b add r3, r1
80038a0: f503 73b2 add.w r3, r3, #356 @ 0x164
80038a4: 2200 movs r2, #0
80038a6: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
80038a8: 7bfa ldrb r2, [r7, #15]
80038aa: 6879 ldr r1, [r7, #4]
80038ac: 4613 mov r3, r2
80038ae: 009b lsls r3, r3, #2
80038b0: 4413 add r3, r2
80038b2: 00db lsls r3, r3, #3
80038b4: 440b add r3, r1
80038b6: f503 73b4 add.w r3, r3, #360 @ 0x168
80038ba: 2200 movs r2, #0
80038bc: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80038be: 7bfb ldrb r3, [r7, #15]
80038c0: 3301 adds r3, #1
80038c2: 73fb strb r3, [r7, #15]
80038c4: 687b ldr r3, [r7, #4]
80038c6: 791b ldrb r3, [r3, #4]
80038c8: 7bfa ldrb r2, [r7, #15]
80038ca: 429a cmp r2, r3
80038cc: d3b5 bcc.n 800383a <HAL_PCD_Init+0x116>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
80038ce: 687b ldr r3, [r7, #4]
80038d0: 6818 ldr r0, [r3, #0]
80038d2: 687b ldr r3, [r7, #4]
80038d4: 3304 adds r3, #4
80038d6: cb0e ldmia r3, {r1, r2, r3}
80038d8: f003 f8df bl 8006a9a <USB_DevInit>
80038dc: 4603 mov r3, r0
80038de: 2b00 cmp r3, #0
80038e0: d005 beq.n 80038ee <HAL_PCD_Init+0x1ca>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80038e2: 687b ldr r3, [r7, #4]
80038e4: 2202 movs r2, #2
80038e6: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
80038ea: 2301 movs r3, #1
80038ec: e00c b.n 8003908 <HAL_PCD_Init+0x1e4>
}
hpcd->USB_Address = 0U;
80038ee: 687b ldr r3, [r7, #4]
80038f0: 2200 movs r2, #0
80038f2: 735a strb r2, [r3, #13]
hpcd->State = HAL_PCD_STATE_READY;
80038f4: 687b ldr r3, [r7, #4]
80038f6: 2201 movs r2, #1
80038f8: f883 2291 strb.w r2, [r3, #657] @ 0x291
(void)USB_DevDisconnect(hpcd->Instance);
80038fc: 687b ldr r3, [r7, #4]
80038fe: 681b ldr r3, [r3, #0]
8003900: 4618 mov r0, r3
8003902: f005 fb5e bl 8008fc2 <USB_DevDisconnect>
return HAL_OK;
8003906: 2300 movs r3, #0
}
8003908: 4618 mov r0, r3
800390a: 3710 adds r7, #16
800390c: 46bd mov sp, r7
800390e: bd80 pop {r7, pc}
08003910 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
8003910: b580 push {r7, lr}
8003912: b082 sub sp, #8
8003914: af00 add r7, sp, #0
8003916: 6078 str r0, [r7, #4]
__HAL_LOCK(hpcd);
8003918: 687b ldr r3, [r7, #4]
800391a: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
800391e: 2b01 cmp r3, #1
8003920: d101 bne.n 8003926 <HAL_PCD_Start+0x16>
8003922: 2302 movs r3, #2
8003924: e016 b.n 8003954 <HAL_PCD_Start+0x44>
8003926: 687b ldr r3, [r7, #4]
8003928: 2201 movs r2, #1
800392a: f883 2290 strb.w r2, [r3, #656] @ 0x290
__HAL_PCD_ENABLE(hpcd);
800392e: 687b ldr r3, [r7, #4]
8003930: 681b ldr r3, [r3, #0]
8003932: 4618 mov r0, r3
8003934: f003 f875 bl 8006a22 <USB_EnableGlobalInt>
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
8003938: 2101 movs r1, #1
800393a: 6878 ldr r0, [r7, #4]
800393c: f007 fc49 bl 800b1d2 <HAL_PCDEx_SetConnectionState>
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
8003940: 687b ldr r3, [r7, #4]
8003942: 681b ldr r3, [r3, #0]
8003944: 4618 mov r0, r3
8003946: f005 fb32 bl 8008fae <USB_DevConnect>
__HAL_UNLOCK(hpcd);
800394a: 687b ldr r3, [r7, #4]
800394c: 2200 movs r2, #0
800394e: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003952: 2300 movs r3, #0
}
8003954: 4618 mov r0, r3
8003956: 3708 adds r7, #8
8003958: 46bd mov sp, r7
800395a: bd80 pop {r7, pc}
0800395c <HAL_PCD_IRQHandler>:
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
800395c: b580 push {r7, lr}
800395e: b088 sub sp, #32
8003960: af00 add r7, sp, #0
8003962: 6078 str r0, [r7, #4]
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
8003964: 687b ldr r3, [r7, #4]
8003966: 681b ldr r3, [r3, #0]
8003968: 4618 mov r0, r3
800396a: f005 fb34 bl 8008fd6 <USB_ReadInterrupts>
800396e: 61b8 str r0, [r7, #24]
uint16_t store_ep[8];
uint8_t i;
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
8003970: 69bb ldr r3, [r7, #24]
8003972: f403 4300 and.w r3, r3, #32768 @ 0x8000
8003976: 2b00 cmp r3, #0
8003978: d003 beq.n 8003982 <HAL_PCD_IRQHandler+0x26>
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
800397a: 6878 ldr r0, [r7, #4]
800397c: f000 fb1a bl 8003fb4 <PCD_EP_ISR_Handler>
return;
8003980: e119 b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
8003982: 69bb ldr r3, [r7, #24]
8003984: f403 6380 and.w r3, r3, #1024 @ 0x400
8003988: 2b00 cmp r3, #0
800398a: d013 beq.n 80039b4 <HAL_PCD_IRQHandler+0x58>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
800398c: 687b ldr r3, [r7, #4]
800398e: 681b ldr r3, [r3, #0]
8003990: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003994: b29a uxth r2, r3
8003996: 687b ldr r3, [r7, #4]
8003998: 681b ldr r3, [r3, #0]
800399a: f422 6280 bic.w r2, r2, #1024 @ 0x400
800399e: b292 uxth r2, r2
80039a0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
80039a4: 6878 ldr r0, [r7, #4]
80039a6: f007 fa1c bl 800ade2 <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
80039aa: 2100 movs r1, #0
80039ac: 6878 ldr r0, [r7, #4]
80039ae: f000 f905 bl 8003bbc <HAL_PCD_SetAddress>
return;
80039b2: e100 b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
80039b4: 69bb ldr r3, [r7, #24]
80039b6: f403 4380 and.w r3, r3, #16384 @ 0x4000
80039ba: 2b00 cmp r3, #0
80039bc: d00c beq.n 80039d8 <HAL_PCD_IRQHandler+0x7c>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
80039be: 687b ldr r3, [r7, #4]
80039c0: 681b ldr r3, [r3, #0]
80039c2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80039c6: b29a uxth r2, r3
80039c8: 687b ldr r3, [r7, #4]
80039ca: 681b ldr r3, [r3, #0]
80039cc: f422 4280 bic.w r2, r2, #16384 @ 0x4000
80039d0: b292 uxth r2, r2
80039d2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
80039d6: e0ee b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
80039d8: 69bb ldr r3, [r7, #24]
80039da: f403 5300 and.w r3, r3, #8192 @ 0x2000
80039de: 2b00 cmp r3, #0
80039e0: d00c beq.n 80039fc <HAL_PCD_IRQHandler+0xa0>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
80039e2: 687b ldr r3, [r7, #4]
80039e4: 681b ldr r3, [r3, #0]
80039e6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80039ea: b29a uxth r2, r3
80039ec: 687b ldr r3, [r7, #4]
80039ee: 681b ldr r3, [r3, #0]
80039f0: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80039f4: b292 uxth r2, r2
80039f6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
80039fa: e0dc b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
80039fc: 69bb ldr r3, [r7, #24]
80039fe: f403 5380 and.w r3, r3, #4096 @ 0x1000
8003a02: 2b00 cmp r3, #0
8003a04: d027 beq.n 8003a56 <HAL_PCD_IRQHandler+0xfa>
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
8003a06: 687b ldr r3, [r7, #4]
8003a08: 681b ldr r3, [r3, #0]
8003a0a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003a0e: b29a uxth r2, r3
8003a10: 687b ldr r3, [r7, #4]
8003a12: 681b ldr r3, [r3, #0]
8003a14: f022 0204 bic.w r2, r2, #4
8003a18: b292 uxth r2, r2
8003a1a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
8003a1e: 687b ldr r3, [r7, #4]
8003a20: 681b ldr r3, [r3, #0]
8003a22: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003a26: b29a uxth r2, r3
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 681b ldr r3, [r3, #0]
8003a2c: f022 0208 bic.w r2, r2, #8
8003a30: b292 uxth r2, r2
8003a32: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
8003a36: 6878 ldr r0, [r7, #4]
8003a38: f007 fa0c bl 800ae54 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
8003a3c: 687b ldr r3, [r7, #4]
8003a3e: 681b ldr r3, [r3, #0]
8003a40: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003a44: b29a uxth r2, r3
8003a46: 687b ldr r3, [r7, #4]
8003a48: 681b ldr r3, [r3, #0]
8003a4a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8003a4e: b292 uxth r2, r2
8003a50: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8003a54: e0af b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
8003a56: 69bb ldr r3, [r7, #24]
8003a58: f403 6300 and.w r3, r3, #2048 @ 0x800
8003a5c: 2b00 cmp r3, #0
8003a5e: f000 8083 beq.w 8003b68 <HAL_PCD_IRQHandler+0x20c>
{
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint registers */
for (i = 0U; i < 8U; i++)
8003a62: 2300 movs r3, #0
8003a64: 77fb strb r3, [r7, #31]
8003a66: e010 b.n 8003a8a <HAL_PCD_IRQHandler+0x12e>
{
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
8003a68: 687b ldr r3, [r7, #4]
8003a6a: 681b ldr r3, [r3, #0]
8003a6c: 461a mov r2, r3
8003a6e: 7ffb ldrb r3, [r7, #31]
8003a70: 009b lsls r3, r3, #2
8003a72: 441a add r2, r3
8003a74: 7ffb ldrb r3, [r7, #31]
8003a76: 8812 ldrh r2, [r2, #0]
8003a78: b292 uxth r2, r2
8003a7a: 005b lsls r3, r3, #1
8003a7c: 3320 adds r3, #32
8003a7e: 443b add r3, r7
8003a80: f823 2c18 strh.w r2, [r3, #-24]
for (i = 0U; i < 8U; i++)
8003a84: 7ffb ldrb r3, [r7, #31]
8003a86: 3301 adds r3, #1
8003a88: 77fb strb r3, [r7, #31]
8003a8a: 7ffb ldrb r3, [r7, #31]
8003a8c: 2b07 cmp r3, #7
8003a8e: d9eb bls.n 8003a68 <HAL_PCD_IRQHandler+0x10c>
}
/* FORCE RESET */
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
8003a90: 687b ldr r3, [r7, #4]
8003a92: 681b ldr r3, [r3, #0]
8003a94: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003a98: b29a uxth r2, r3
8003a9a: 687b ldr r3, [r7, #4]
8003a9c: 681b ldr r3, [r3, #0]
8003a9e: f042 0201 orr.w r2, r2, #1
8003aa2: b292 uxth r2, r2
8003aa4: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CLEAR RESET */
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
8003aa8: 687b ldr r3, [r7, #4]
8003aaa: 681b ldr r3, [r3, #0]
8003aac: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003ab0: b29a uxth r2, r3
8003ab2: 687b ldr r3, [r7, #4]
8003ab4: 681b ldr r3, [r3, #0]
8003ab6: f022 0201 bic.w r2, r2, #1
8003aba: b292 uxth r2, r2
8003abc: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* wait for reset flag in ISTR */
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
8003ac0: bf00 nop
8003ac2: 687b ldr r3, [r7, #4]
8003ac4: 681b ldr r3, [r3, #0]
8003ac6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003aca: b29b uxth r3, r3
8003acc: f403 6380 and.w r3, r3, #1024 @ 0x400
8003ad0: 2b00 cmp r3, #0
8003ad2: d0f6 beq.n 8003ac2 <HAL_PCD_IRQHandler+0x166>
{
}
/* Clear Reset Flag */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8003ad4: 687b ldr r3, [r7, #4]
8003ad6: 681b ldr r3, [r3, #0]
8003ad8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003adc: b29a uxth r2, r3
8003ade: 687b ldr r3, [r7, #4]
8003ae0: 681b ldr r3, [r3, #0]
8003ae2: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003ae6: b292 uxth r2, r2
8003ae8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Restore Registre */
for (i = 0U; i < 8U; i++)
8003aec: 2300 movs r3, #0
8003aee: 77fb strb r3, [r7, #31]
8003af0: e00f b.n 8003b12 <HAL_PCD_IRQHandler+0x1b6>
{
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
8003af2: 7ffb ldrb r3, [r7, #31]
8003af4: 687a ldr r2, [r7, #4]
8003af6: 6812 ldr r2, [r2, #0]
8003af8: 4611 mov r1, r2
8003afa: 7ffa ldrb r2, [r7, #31]
8003afc: 0092 lsls r2, r2, #2
8003afe: 440a add r2, r1
8003b00: 005b lsls r3, r3, #1
8003b02: 3320 adds r3, #32
8003b04: 443b add r3, r7
8003b06: f833 3c18 ldrh.w r3, [r3, #-24]
8003b0a: 8013 strh r3, [r2, #0]
for (i = 0U; i < 8U; i++)
8003b0c: 7ffb ldrb r3, [r7, #31]
8003b0e: 3301 adds r3, #1
8003b10: 77fb strb r3, [r7, #31]
8003b12: 7ffb ldrb r3, [r7, #31]
8003b14: 2b07 cmp r3, #7
8003b16: d9ec bls.n 8003af2 <HAL_PCD_IRQHandler+0x196>
}
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
8003b18: 687b ldr r3, [r7, #4]
8003b1a: 681b ldr r3, [r3, #0]
8003b1c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003b20: b29a uxth r2, r3
8003b22: 687b ldr r3, [r7, #4]
8003b24: 681b ldr r3, [r3, #0]
8003b26: f042 0208 orr.w r2, r2, #8
8003b2a: b292 uxth r2, r2
8003b2c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
8003b30: 687b ldr r3, [r7, #4]
8003b32: 681b ldr r3, [r3, #0]
8003b34: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003b38: b29a uxth r2, r3
8003b3a: 687b ldr r3, [r7, #4]
8003b3c: 681b ldr r3, [r3, #0]
8003b3e: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003b42: b292 uxth r2, r2
8003b44: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 681b ldr r3, [r3, #0]
8003b4c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003b50: b29a uxth r2, r3
8003b52: 687b ldr r3, [r7, #4]
8003b54: 681b ldr r3, [r3, #0]
8003b56: f042 0204 orr.w r2, r2, #4
8003b5a: b292 uxth r2, r2
8003b5c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
8003b60: 6878 ldr r0, [r7, #4]
8003b62: f007 f95d bl 800ae20 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8003b66: e026 b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
8003b68: 69bb ldr r3, [r7, #24]
8003b6a: f403 7300 and.w r3, r3, #512 @ 0x200
8003b6e: 2b00 cmp r3, #0
8003b70: d00f beq.n 8003b92 <HAL_PCD_IRQHandler+0x236>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
8003b72: 687b ldr r3, [r7, #4]
8003b74: 681b ldr r3, [r3, #0]
8003b76: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003b7a: b29a uxth r2, r3
8003b7c: 687b ldr r3, [r7, #4]
8003b7e: 681b ldr r3, [r3, #0]
8003b80: f422 7200 bic.w r2, r2, #512 @ 0x200
8003b84: b292 uxth r2, r2
8003b86: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
8003b8a: 6878 ldr r0, [r7, #4]
8003b8c: f007 f91b bl 800adc6 <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8003b90: e011 b.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
8003b92: 69bb ldr r3, [r7, #24]
8003b94: f403 7380 and.w r3, r3, #256 @ 0x100
8003b98: 2b00 cmp r3, #0
8003b9a: d00c beq.n 8003bb6 <HAL_PCD_IRQHandler+0x25a>
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
8003b9c: 687b ldr r3, [r7, #4]
8003b9e: 681b ldr r3, [r3, #0]
8003ba0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003ba4: b29a uxth r2, r3
8003ba6: 687b ldr r3, [r7, #4]
8003ba8: 681b ldr r3, [r3, #0]
8003baa: f422 7280 bic.w r2, r2, #256 @ 0x100
8003bae: b292 uxth r2, r2
8003bb0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8003bb4: bf00 nop
}
}
8003bb6: 3720 adds r7, #32
8003bb8: 46bd mov sp, r7
8003bba: bd80 pop {r7, pc}
08003bbc <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
8003bbc: b580 push {r7, lr}
8003bbe: b082 sub sp, #8
8003bc0: af00 add r7, sp, #0
8003bc2: 6078 str r0, [r7, #4]
8003bc4: 460b mov r3, r1
8003bc6: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
8003bc8: 687b ldr r3, [r7, #4]
8003bca: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003bce: 2b01 cmp r3, #1
8003bd0: d101 bne.n 8003bd6 <HAL_PCD_SetAddress+0x1a>
8003bd2: 2302 movs r3, #2
8003bd4: e012 b.n 8003bfc <HAL_PCD_SetAddress+0x40>
8003bd6: 687b ldr r3, [r7, #4]
8003bd8: 2201 movs r2, #1
8003bda: f883 2290 strb.w r2, [r3, #656] @ 0x290
hpcd->USB_Address = address;
8003bde: 687b ldr r3, [r7, #4]
8003be0: 78fa ldrb r2, [r7, #3]
8003be2: 735a strb r2, [r3, #13]
(void)USB_SetDevAddress(hpcd->Instance, address);
8003be4: 687b ldr r3, [r7, #4]
8003be6: 681b ldr r3, [r3, #0]
8003be8: 78fa ldrb r2, [r7, #3]
8003bea: 4611 mov r1, r2
8003bec: 4618 mov r0, r3
8003bee: f005 f9cb bl 8008f88 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8003bf2: 687b ldr r3, [r7, #4]
8003bf4: 2200 movs r2, #0
8003bf6: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003bfa: 2300 movs r3, #0
}
8003bfc: 4618 mov r0, r3
8003bfe: 3708 adds r7, #8
8003c00: 46bd mov sp, r7
8003c02: bd80 pop {r7, pc}
08003c04 <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
8003c04: b580 push {r7, lr}
8003c06: b084 sub sp, #16
8003c08: af00 add r7, sp, #0
8003c0a: 6078 str r0, [r7, #4]
8003c0c: 4608 mov r0, r1
8003c0e: 4611 mov r1, r2
8003c10: 461a mov r2, r3
8003c12: 4603 mov r3, r0
8003c14: 70fb strb r3, [r7, #3]
8003c16: 460b mov r3, r1
8003c18: 803b strh r3, [r7, #0]
8003c1a: 4613 mov r3, r2
8003c1c: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8003c1e: 2300 movs r3, #0
8003c20: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8003c22: f997 3003 ldrsb.w r3, [r7, #3]
8003c26: 2b00 cmp r3, #0
8003c28: da0e bge.n 8003c48 <HAL_PCD_EP_Open+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003c2a: 78fb ldrb r3, [r7, #3]
8003c2c: f003 0207 and.w r2, r3, #7
8003c30: 4613 mov r3, r2
8003c32: 009b lsls r3, r3, #2
8003c34: 4413 add r3, r2
8003c36: 00db lsls r3, r3, #3
8003c38: 3310 adds r3, #16
8003c3a: 687a ldr r2, [r7, #4]
8003c3c: 4413 add r3, r2
8003c3e: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003c40: 68fb ldr r3, [r7, #12]
8003c42: 2201 movs r2, #1
8003c44: 705a strb r2, [r3, #1]
8003c46: e00e b.n 8003c66 <HAL_PCD_EP_Open+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003c48: 78fb ldrb r3, [r7, #3]
8003c4a: f003 0207 and.w r2, r3, #7
8003c4e: 4613 mov r3, r2
8003c50: 009b lsls r3, r3, #2
8003c52: 4413 add r3, r2
8003c54: 00db lsls r3, r3, #3
8003c56: f503 73a8 add.w r3, r3, #336 @ 0x150
8003c5a: 687a ldr r2, [r7, #4]
8003c5c: 4413 add r3, r2
8003c5e: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003c60: 68fb ldr r3, [r7, #12]
8003c62: 2200 movs r2, #0
8003c64: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8003c66: 78fb ldrb r3, [r7, #3]
8003c68: f003 0307 and.w r3, r3, #7
8003c6c: b2da uxtb r2, r3
8003c6e: 68fb ldr r3, [r7, #12]
8003c70: 701a strb r2, [r3, #0]
ep->maxpacket = ep_mps;
8003c72: 883a ldrh r2, [r7, #0]
8003c74: 68fb ldr r3, [r7, #12]
8003c76: 611a str r2, [r3, #16]
ep->type = ep_type;
8003c78: 68fb ldr r3, [r7, #12]
8003c7a: 78ba ldrb r2, [r7, #2]
8003c7c: 70da strb r2, [r3, #3]
ep->tx_fifo_num = ep->num;
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
8003c7e: 78bb ldrb r3, [r7, #2]
8003c80: 2b02 cmp r3, #2
8003c82: d102 bne.n 8003c8a <HAL_PCD_EP_Open+0x86>
{
ep->data_pid_start = 0U;
8003c84: 68fb ldr r3, [r7, #12]
8003c86: 2200 movs r2, #0
8003c88: 711a strb r2, [r3, #4]
}
__HAL_LOCK(hpcd);
8003c8a: 687b ldr r3, [r7, #4]
8003c8c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003c90: 2b01 cmp r3, #1
8003c92: d101 bne.n 8003c98 <HAL_PCD_EP_Open+0x94>
8003c94: 2302 movs r3, #2
8003c96: e00e b.n 8003cb6 <HAL_PCD_EP_Open+0xb2>
8003c98: 687b ldr r3, [r7, #4]
8003c9a: 2201 movs r2, #1
8003c9c: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
8003ca0: 687b ldr r3, [r7, #4]
8003ca2: 681b ldr r3, [r3, #0]
8003ca4: 68f9 ldr r1, [r7, #12]
8003ca6: 4618 mov r0, r3
8003ca8: f002 ff14 bl 8006ad4 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
8003cac: 687b ldr r3, [r7, #4]
8003cae: 2200 movs r2, #0
8003cb0: f883 2290 strb.w r2, [r3, #656] @ 0x290
return ret;
8003cb4: 7afb ldrb r3, [r7, #11]
}
8003cb6: 4618 mov r0, r3
8003cb8: 3710 adds r7, #16
8003cba: 46bd mov sp, r7
8003cbc: bd80 pop {r7, pc}
08003cbe <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8003cbe: b580 push {r7, lr}
8003cc0: b084 sub sp, #16
8003cc2: af00 add r7, sp, #0
8003cc4: 6078 str r0, [r7, #4]
8003cc6: 460b mov r3, r1
8003cc8: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8003cca: f997 3003 ldrsb.w r3, [r7, #3]
8003cce: 2b00 cmp r3, #0
8003cd0: da0e bge.n 8003cf0 <HAL_PCD_EP_Close+0x32>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003cd2: 78fb ldrb r3, [r7, #3]
8003cd4: f003 0207 and.w r2, r3, #7
8003cd8: 4613 mov r3, r2
8003cda: 009b lsls r3, r3, #2
8003cdc: 4413 add r3, r2
8003cde: 00db lsls r3, r3, #3
8003ce0: 3310 adds r3, #16
8003ce2: 687a ldr r2, [r7, #4]
8003ce4: 4413 add r3, r2
8003ce6: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003ce8: 68fb ldr r3, [r7, #12]
8003cea: 2201 movs r2, #1
8003cec: 705a strb r2, [r3, #1]
8003cee: e00e b.n 8003d0e <HAL_PCD_EP_Close+0x50>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003cf0: 78fb ldrb r3, [r7, #3]
8003cf2: f003 0207 and.w r2, r3, #7
8003cf6: 4613 mov r3, r2
8003cf8: 009b lsls r3, r3, #2
8003cfa: 4413 add r3, r2
8003cfc: 00db lsls r3, r3, #3
8003cfe: f503 73a8 add.w r3, r3, #336 @ 0x150
8003d02: 687a ldr r2, [r7, #4]
8003d04: 4413 add r3, r2
8003d06: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003d08: 68fb ldr r3, [r7, #12]
8003d0a: 2200 movs r2, #0
8003d0c: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8003d0e: 78fb ldrb r3, [r7, #3]
8003d10: f003 0307 and.w r3, r3, #7
8003d14: b2da uxtb r2, r3
8003d16: 68fb ldr r3, [r7, #12]
8003d18: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8003d1a: 687b ldr r3, [r7, #4]
8003d1c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003d20: 2b01 cmp r3, #1
8003d22: d101 bne.n 8003d28 <HAL_PCD_EP_Close+0x6a>
8003d24: 2302 movs r3, #2
8003d26: e00e b.n 8003d46 <HAL_PCD_EP_Close+0x88>
8003d28: 687b ldr r3, [r7, #4]
8003d2a: 2201 movs r2, #1
8003d2c: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
8003d30: 687b ldr r3, [r7, #4]
8003d32: 681b ldr r3, [r3, #0]
8003d34: 68f9 ldr r1, [r7, #12]
8003d36: 4618 mov r0, r3
8003d38: f003 fa8c bl 8007254 <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
8003d3c: 687b ldr r3, [r7, #4]
8003d3e: 2200 movs r2, #0
8003d40: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003d44: 2300 movs r3, #0
}
8003d46: 4618 mov r0, r3
8003d48: 3710 adds r7, #16
8003d4a: 46bd mov sp, r7
8003d4c: bd80 pop {r7, pc}
08003d4e <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8003d4e: b580 push {r7, lr}
8003d50: b086 sub sp, #24
8003d52: af00 add r7, sp, #0
8003d54: 60f8 str r0, [r7, #12]
8003d56: 607a str r2, [r7, #4]
8003d58: 603b str r3, [r7, #0]
8003d5a: 460b mov r3, r1
8003d5c: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003d5e: 7afb ldrb r3, [r7, #11]
8003d60: f003 0207 and.w r2, r3, #7
8003d64: 4613 mov r3, r2
8003d66: 009b lsls r3, r3, #2
8003d68: 4413 add r3, r2
8003d6a: 00db lsls r3, r3, #3
8003d6c: f503 73a8 add.w r3, r3, #336 @ 0x150
8003d70: 68fa ldr r2, [r7, #12]
8003d72: 4413 add r3, r2
8003d74: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8003d76: 697b ldr r3, [r7, #20]
8003d78: 687a ldr r2, [r7, #4]
8003d7a: 615a str r2, [r3, #20]
ep->xfer_len = len;
8003d7c: 697b ldr r3, [r7, #20]
8003d7e: 683a ldr r2, [r7, #0]
8003d80: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
8003d82: 697b ldr r3, [r7, #20]
8003d84: 2200 movs r2, #0
8003d86: 61da str r2, [r3, #28]
ep->is_in = 0U;
8003d88: 697b ldr r3, [r7, #20]
8003d8a: 2200 movs r2, #0
8003d8c: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8003d8e: 7afb ldrb r3, [r7, #11]
8003d90: f003 0307 and.w r3, r3, #7
8003d94: b2da uxtb r2, r3
8003d96: 697b ldr r3, [r7, #20]
8003d98: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8003d9a: 68fb ldr r3, [r7, #12]
8003d9c: 681b ldr r3, [r3, #0]
8003d9e: 6979 ldr r1, [r7, #20]
8003da0: 4618 mov r0, r3
8003da2: f003 fc43 bl 800762c <USB_EPStartXfer>
return HAL_OK;
8003da6: 2300 movs r3, #0
}
8003da8: 4618 mov r0, r3
8003daa: 3718 adds r7, #24
8003dac: 46bd mov sp, r7
8003dae: bd80 pop {r7, pc}
08003db0 <HAL_PCD_EP_GetRxCount>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
8003db0: b480 push {r7}
8003db2: b083 sub sp, #12
8003db4: af00 add r7, sp, #0
8003db6: 6078 str r0, [r7, #4]
8003db8: 460b mov r3, r1
8003dba: 70fb strb r3, [r7, #3]
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
8003dbc: 78fb ldrb r3, [r7, #3]
8003dbe: f003 0207 and.w r2, r3, #7
8003dc2: 6879 ldr r1, [r7, #4]
8003dc4: 4613 mov r3, r2
8003dc6: 009b lsls r3, r3, #2
8003dc8: 4413 add r3, r2
8003dca: 00db lsls r3, r3, #3
8003dcc: 440b add r3, r1
8003dce: f503 73b6 add.w r3, r3, #364 @ 0x16c
8003dd2: 681b ldr r3, [r3, #0]
}
8003dd4: 4618 mov r0, r3
8003dd6: 370c adds r7, #12
8003dd8: 46bd mov sp, r7
8003dda: bc80 pop {r7}
8003ddc: 4770 bx lr
08003dde <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8003dde: b580 push {r7, lr}
8003de0: b086 sub sp, #24
8003de2: af00 add r7, sp, #0
8003de4: 60f8 str r0, [r7, #12]
8003de6: 607a str r2, [r7, #4]
8003de8: 603b str r3, [r7, #0]
8003dea: 460b mov r3, r1
8003dec: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003dee: 7afb ldrb r3, [r7, #11]
8003df0: f003 0207 and.w r2, r3, #7
8003df4: 4613 mov r3, r2
8003df6: 009b lsls r3, r3, #2
8003df8: 4413 add r3, r2
8003dfa: 00db lsls r3, r3, #3
8003dfc: 3310 adds r3, #16
8003dfe: 68fa ldr r2, [r7, #12]
8003e00: 4413 add r3, r2
8003e02: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8003e04: 697b ldr r3, [r7, #20]
8003e06: 687a ldr r2, [r7, #4]
8003e08: 615a str r2, [r3, #20]
ep->xfer_len = len;
8003e0a: 697b ldr r3, [r7, #20]
8003e0c: 683a ldr r2, [r7, #0]
8003e0e: 619a str r2, [r3, #24]
#if defined (USB)
ep->xfer_fill_db = 1U;
8003e10: 697b ldr r3, [r7, #20]
8003e12: 2201 movs r2, #1
8003e14: f883 2024 strb.w r2, [r3, #36] @ 0x24
ep->xfer_len_db = len;
8003e18: 697b ldr r3, [r7, #20]
8003e1a: 683a ldr r2, [r7, #0]
8003e1c: 621a str r2, [r3, #32]
#endif /* defined (USB) */
ep->xfer_count = 0U;
8003e1e: 697b ldr r3, [r7, #20]
8003e20: 2200 movs r2, #0
8003e22: 61da str r2, [r3, #28]
ep->is_in = 1U;
8003e24: 697b ldr r3, [r7, #20]
8003e26: 2201 movs r2, #1
8003e28: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8003e2a: 7afb ldrb r3, [r7, #11]
8003e2c: f003 0307 and.w r3, r3, #7
8003e30: b2da uxtb r2, r3
8003e32: 697b ldr r3, [r7, #20]
8003e34: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8003e36: 68fb ldr r3, [r7, #12]
8003e38: 681b ldr r3, [r3, #0]
8003e3a: 6979 ldr r1, [r7, #20]
8003e3c: 4618 mov r0, r3
8003e3e: f003 fbf5 bl 800762c <USB_EPStartXfer>
return HAL_OK;
8003e42: 2300 movs r3, #0
}
8003e44: 4618 mov r0, r3
8003e46: 3718 adds r7, #24
8003e48: 46bd mov sp, r7
8003e4a: bd80 pop {r7, pc}
08003e4c <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8003e4c: b580 push {r7, lr}
8003e4e: b084 sub sp, #16
8003e50: af00 add r7, sp, #0
8003e52: 6078 str r0, [r7, #4]
8003e54: 460b mov r3, r1
8003e56: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8003e58: 78fb ldrb r3, [r7, #3]
8003e5a: f003 0307 and.w r3, r3, #7
8003e5e: 687a ldr r2, [r7, #4]
8003e60: 7912 ldrb r2, [r2, #4]
8003e62: 4293 cmp r3, r2
8003e64: d901 bls.n 8003e6a <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
8003e66: 2301 movs r3, #1
8003e68: e04c b.n 8003f04 <HAL_PCD_EP_SetStall+0xb8>
}
if ((0x80U & ep_addr) == 0x80U)
8003e6a: f997 3003 ldrsb.w r3, [r7, #3]
8003e6e: 2b00 cmp r3, #0
8003e70: da0e bge.n 8003e90 <HAL_PCD_EP_SetStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003e72: 78fb ldrb r3, [r7, #3]
8003e74: f003 0207 and.w r2, r3, #7
8003e78: 4613 mov r3, r2
8003e7a: 009b lsls r3, r3, #2
8003e7c: 4413 add r3, r2
8003e7e: 00db lsls r3, r3, #3
8003e80: 3310 adds r3, #16
8003e82: 687a ldr r2, [r7, #4]
8003e84: 4413 add r3, r2
8003e86: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003e88: 68fb ldr r3, [r7, #12]
8003e8a: 2201 movs r2, #1
8003e8c: 705a strb r2, [r3, #1]
8003e8e: e00c b.n 8003eaa <HAL_PCD_EP_SetStall+0x5e>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8003e90: 78fa ldrb r2, [r7, #3]
8003e92: 4613 mov r3, r2
8003e94: 009b lsls r3, r3, #2
8003e96: 4413 add r3, r2
8003e98: 00db lsls r3, r3, #3
8003e9a: f503 73a8 add.w r3, r3, #336 @ 0x150
8003e9e: 687a ldr r2, [r7, #4]
8003ea0: 4413 add r3, r2
8003ea2: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003ea4: 68fb ldr r3, [r7, #12]
8003ea6: 2200 movs r2, #0
8003ea8: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
8003eaa: 68fb ldr r3, [r7, #12]
8003eac: 2201 movs r2, #1
8003eae: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8003eb0: 78fb ldrb r3, [r7, #3]
8003eb2: f003 0307 and.w r3, r3, #7
8003eb6: b2da uxtb r2, r3
8003eb8: 68fb ldr r3, [r7, #12]
8003eba: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8003ebc: 687b ldr r3, [r7, #4]
8003ebe: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003ec2: 2b01 cmp r3, #1
8003ec4: d101 bne.n 8003eca <HAL_PCD_EP_SetStall+0x7e>
8003ec6: 2302 movs r3, #2
8003ec8: e01c b.n 8003f04 <HAL_PCD_EP_SetStall+0xb8>
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 2201 movs r2, #1
8003ece: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPSetStall(hpcd->Instance, ep);
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 681b ldr r3, [r3, #0]
8003ed6: 68f9 ldr r1, [r7, #12]
8003ed8: 4618 mov r0, r3
8003eda: f004 ff58 bl 8008d8e <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
8003ede: 78fb ldrb r3, [r7, #3]
8003ee0: f003 0307 and.w r3, r3, #7
8003ee4: 2b00 cmp r3, #0
8003ee6: d108 bne.n 8003efa <HAL_PCD_EP_SetStall+0xae>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
8003ee8: 687b ldr r3, [r7, #4]
8003eea: 681a ldr r2, [r3, #0]
8003eec: 687b ldr r3, [r7, #4]
8003eee: f503 7326 add.w r3, r3, #664 @ 0x298
8003ef2: 4619 mov r1, r3
8003ef4: 4610 mov r0, r2
8003ef6: f005 f87d bl 8008ff4 <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
8003efa: 687b ldr r3, [r7, #4]
8003efc: 2200 movs r2, #0
8003efe: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003f02: 2300 movs r3, #0
}
8003f04: 4618 mov r0, r3
8003f06: 3710 adds r7, #16
8003f08: 46bd mov sp, r7
8003f0a: bd80 pop {r7, pc}
08003f0c <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8003f0c: b580 push {r7, lr}
8003f0e: b084 sub sp, #16
8003f10: af00 add r7, sp, #0
8003f12: 6078 str r0, [r7, #4]
8003f14: 460b mov r3, r1
8003f16: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
8003f18: 78fb ldrb r3, [r7, #3]
8003f1a: f003 030f and.w r3, r3, #15
8003f1e: 687a ldr r2, [r7, #4]
8003f20: 7912 ldrb r2, [r2, #4]
8003f22: 4293 cmp r3, r2
8003f24: d901 bls.n 8003f2a <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
8003f26: 2301 movs r3, #1
8003f28: e040 b.n 8003fac <HAL_PCD_EP_ClrStall+0xa0>
}
if ((0x80U & ep_addr) == 0x80U)
8003f2a: f997 3003 ldrsb.w r3, [r7, #3]
8003f2e: 2b00 cmp r3, #0
8003f30: da0e bge.n 8003f50 <HAL_PCD_EP_ClrStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003f32: 78fb ldrb r3, [r7, #3]
8003f34: f003 0207 and.w r2, r3, #7
8003f38: 4613 mov r3, r2
8003f3a: 009b lsls r3, r3, #2
8003f3c: 4413 add r3, r2
8003f3e: 00db lsls r3, r3, #3
8003f40: 3310 adds r3, #16
8003f42: 687a ldr r2, [r7, #4]
8003f44: 4413 add r3, r2
8003f46: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003f48: 68fb ldr r3, [r7, #12]
8003f4a: 2201 movs r2, #1
8003f4c: 705a strb r2, [r3, #1]
8003f4e: e00e b.n 8003f6e <HAL_PCD_EP_ClrStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003f50: 78fb ldrb r3, [r7, #3]
8003f52: f003 0207 and.w r2, r3, #7
8003f56: 4613 mov r3, r2
8003f58: 009b lsls r3, r3, #2
8003f5a: 4413 add r3, r2
8003f5c: 00db lsls r3, r3, #3
8003f5e: f503 73a8 add.w r3, r3, #336 @ 0x150
8003f62: 687a ldr r2, [r7, #4]
8003f64: 4413 add r3, r2
8003f66: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003f68: 68fb ldr r3, [r7, #12]
8003f6a: 2200 movs r2, #0
8003f6c: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
8003f6e: 68fb ldr r3, [r7, #12]
8003f70: 2200 movs r2, #0
8003f72: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8003f74: 78fb ldrb r3, [r7, #3]
8003f76: f003 0307 and.w r3, r3, #7
8003f7a: b2da uxtb r2, r3
8003f7c: 68fb ldr r3, [r7, #12]
8003f7e: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8003f80: 687b ldr r3, [r7, #4]
8003f82: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003f86: 2b01 cmp r3, #1
8003f88: d101 bne.n 8003f8e <HAL_PCD_EP_ClrStall+0x82>
8003f8a: 2302 movs r3, #2
8003f8c: e00e b.n 8003fac <HAL_PCD_EP_ClrStall+0xa0>
8003f8e: 687b ldr r3, [r7, #4]
8003f90: 2201 movs r2, #1
8003f92: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPClearStall(hpcd->Instance, ep);
8003f96: 687b ldr r3, [r7, #4]
8003f98: 681b ldr r3, [r3, #0]
8003f9a: 68f9 ldr r1, [r7, #12]
8003f9c: 4618 mov r0, r3
8003f9e: f004 ff46 bl 8008e2e <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
8003fa2: 687b ldr r3, [r7, #4]
8003fa4: 2200 movs r2, #0
8003fa6: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003faa: 2300 movs r3, #0
}
8003fac: 4618 mov r0, r3
8003fae: 3710 adds r7, #16
8003fb0: 46bd mov sp, r7
8003fb2: bd80 pop {r7, pc}
08003fb4 <PCD_EP_ISR_Handler>:
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
8003fb4: b580 push {r7, lr}
8003fb6: b096 sub sp, #88 @ 0x58
8003fb8: af00 add r7, sp, #0
8003fba: 6078 str r0, [r7, #4]
#if (USE_USB_DOUBLE_BUFFER != 1U)
count = 0U;
#endif /* USE_USB_DOUBLE_BUFFER */
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8003fbc: e3bb b.n 8004736 <PCD_EP_ISR_Handler+0x782>
{
wIstr = hpcd->Instance->ISTR;
8003fbe: 687b ldr r3, [r7, #4]
8003fc0: 681b ldr r3, [r3, #0]
8003fc2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003fc6: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
8003fca: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8003fce: b2db uxtb r3, r3
8003fd0: f003 030f and.w r3, r3, #15
8003fd4: f887 304d strb.w r3, [r7, #77] @ 0x4d
if (epindex == 0U)
8003fd8: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8003fdc: 2b00 cmp r3, #0
8003fde: f040 8175 bne.w 80042cc <PCD_EP_ISR_Handler+0x318>
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
8003fe2: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8003fe6: f003 0310 and.w r3, r3, #16
8003fea: 2b00 cmp r3, #0
8003fec: d14e bne.n 800408c <PCD_EP_ISR_Handler+0xd8>
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8003fee: 687b ldr r3, [r7, #4]
8003ff0: 681b ldr r3, [r3, #0]
8003ff2: 881b ldrh r3, [r3, #0]
8003ff4: b29b uxth r3, r3
8003ff6: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
8003ffa: f023 0370 bic.w r3, r3, #112 @ 0x70
8003ffe: 81fb strh r3, [r7, #14]
8004000: 687b ldr r3, [r7, #4]
8004002: 681a ldr r2, [r3, #0]
8004004: 89fb ldrh r3, [r7, #14]
8004006: ea6f 4343 mvn.w r3, r3, lsl #17
800400a: ea6f 4353 mvn.w r3, r3, lsr #17
800400e: b29b uxth r3, r3
8004010: 8013 strh r3, [r2, #0]
ep = &hpcd->IN_ep[0];
8004012: 687b ldr r3, [r7, #4]
8004014: 3310 adds r3, #16
8004016: 657b str r3, [r7, #84] @ 0x54
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
8004018: 687b ldr r3, [r7, #4]
800401a: 681b ldr r3, [r3, #0]
800401c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004020: b29b uxth r3, r3
8004022: 461a mov r2, r3
8004024: 6d7b ldr r3, [r7, #84] @ 0x54
8004026: 781b ldrb r3, [r3, #0]
8004028: 00db lsls r3, r3, #3
800402a: 4413 add r3, r2
800402c: 3302 adds r3, #2
800402e: 005b lsls r3, r3, #1
8004030: 687a ldr r2, [r7, #4]
8004032: 6812 ldr r2, [r2, #0]
8004034: 4413 add r3, r2
8004036: f503 6380 add.w r3, r3, #1024 @ 0x400
800403a: 881b ldrh r3, [r3, #0]
800403c: f3c3 0209 ubfx r2, r3, #0, #10
8004040: 6d7b ldr r3, [r7, #84] @ 0x54
8004042: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
8004044: 6d7b ldr r3, [r7, #84] @ 0x54
8004046: 695a ldr r2, [r3, #20]
8004048: 6d7b ldr r3, [r7, #84] @ 0x54
800404a: 69db ldr r3, [r3, #28]
800404c: 441a add r2, r3
800404e: 6d7b ldr r3, [r7, #84] @ 0x54
8004050: 615a str r2, [r3, #20]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
8004052: 2100 movs r1, #0
8004054: 6878 ldr r0, [r7, #4]
8004056: f006 fe9c bl 800ad92 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
800405a: 687b ldr r3, [r7, #4]
800405c: 7b5b ldrb r3, [r3, #13]
800405e: b2db uxtb r3, r3
8004060: 2b00 cmp r3, #0
8004062: f000 8368 beq.w 8004736 <PCD_EP_ISR_Handler+0x782>
8004066: 6d7b ldr r3, [r7, #84] @ 0x54
8004068: 699b ldr r3, [r3, #24]
800406a: 2b00 cmp r3, #0
800406c: f040 8363 bne.w 8004736 <PCD_EP_ISR_Handler+0x782>
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
8004070: 687b ldr r3, [r7, #4]
8004072: 7b5b ldrb r3, [r3, #13]
8004074: b2db uxtb r3, r3
8004076: f063 037f orn r3, r3, #127 @ 0x7f
800407a: b2da uxtb r2, r3
800407c: 687b ldr r3, [r7, #4]
800407e: 681b ldr r3, [r3, #0]
8004080: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
hpcd->USB_Address = 0U;
8004084: 687b ldr r3, [r7, #4]
8004086: 2200 movs r2, #0
8004088: 735a strb r2, [r3, #13]
800408a: e354 b.n 8004736 <PCD_EP_ISR_Handler+0x782>
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
800408c: 687b ldr r3, [r7, #4]
800408e: f503 73a8 add.w r3, r3, #336 @ 0x150
8004092: 657b str r3, [r7, #84] @ 0x54
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
8004094: 687b ldr r3, [r7, #4]
8004096: 681b ldr r3, [r3, #0]
8004098: 881b ldrh r3, [r3, #0]
800409a: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_SETUP) != 0U)
800409e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80040a2: f403 6300 and.w r3, r3, #2048 @ 0x800
80040a6: 2b00 cmp r3, #0
80040a8: d034 beq.n 8004114 <PCD_EP_ISR_Handler+0x160>
{
/* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
80040aa: 687b ldr r3, [r7, #4]
80040ac: 681b ldr r3, [r3, #0]
80040ae: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80040b2: b29b uxth r3, r3
80040b4: 461a mov r2, r3
80040b6: 6d7b ldr r3, [r7, #84] @ 0x54
80040b8: 781b ldrb r3, [r3, #0]
80040ba: 00db lsls r3, r3, #3
80040bc: 4413 add r3, r2
80040be: 3306 adds r3, #6
80040c0: 005b lsls r3, r3, #1
80040c2: 687a ldr r2, [r7, #4]
80040c4: 6812 ldr r2, [r2, #0]
80040c6: 4413 add r3, r2
80040c8: f503 6380 add.w r3, r3, #1024 @ 0x400
80040cc: 881b ldrh r3, [r3, #0]
80040ce: f3c3 0209 ubfx r2, r3, #0, #10
80040d2: 6d7b ldr r3, [r7, #84] @ 0x54
80040d4: 61da str r2, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
80040d6: 687b ldr r3, [r7, #4]
80040d8: 6818 ldr r0, [r3, #0]
80040da: 687b ldr r3, [r7, #4]
80040dc: f503 7126 add.w r1, r3, #664 @ 0x298
80040e0: 6d7b ldr r3, [r7, #84] @ 0x54
80040e2: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
80040e4: 6d7b ldr r3, [r7, #84] @ 0x54
80040e6: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
80040e8: b29b uxth r3, r3
80040ea: f004 ffd4 bl 8009096 <USB_ReadPMA>
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
80040ee: 687b ldr r3, [r7, #4]
80040f0: 681b ldr r3, [r3, #0]
80040f2: 881b ldrh r3, [r3, #0]
80040f4: b29a uxth r2, r3
80040f6: f640 738f movw r3, #3983 @ 0xf8f
80040fa: 4013 ands r3, r2
80040fc: 823b strh r3, [r7, #16]
80040fe: 687b ldr r3, [r7, #4]
8004100: 681b ldr r3, [r3, #0]
8004102: 8a3a ldrh r2, [r7, #16]
8004104: f042 0280 orr.w r2, r2, #128 @ 0x80
8004108: b292 uxth r2, r2
800410a: 801a strh r2, [r3, #0]
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
800410c: 6878 ldr r0, [r7, #4]
800410e: f006 fe13 bl 800ad38 <HAL_PCD_SetupStageCallback>
8004112: e310 b.n 8004736 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
8004114: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
8004118: 2b00 cmp r3, #0
800411a: f280 830c bge.w 8004736 <PCD_EP_ISR_Handler+0x782>
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
800411e: 687b ldr r3, [r7, #4]
8004120: 681b ldr r3, [r3, #0]
8004122: 881b ldrh r3, [r3, #0]
8004124: b29a uxth r2, r3
8004126: f640 738f movw r3, #3983 @ 0xf8f
800412a: 4013 ands r3, r2
800412c: 83fb strh r3, [r7, #30]
800412e: 687b ldr r3, [r7, #4]
8004130: 681b ldr r3, [r3, #0]
8004132: 8bfa ldrh r2, [r7, #30]
8004134: f042 0280 orr.w r2, r2, #128 @ 0x80
8004138: b292 uxth r2, r2
800413a: 801a strh r2, [r3, #0]
/* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800413c: 687b ldr r3, [r7, #4]
800413e: 681b ldr r3, [r3, #0]
8004140: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004144: b29b uxth r3, r3
8004146: 461a mov r2, r3
8004148: 6d7b ldr r3, [r7, #84] @ 0x54
800414a: 781b ldrb r3, [r3, #0]
800414c: 00db lsls r3, r3, #3
800414e: 4413 add r3, r2
8004150: 3306 adds r3, #6
8004152: 005b lsls r3, r3, #1
8004154: 687a ldr r2, [r7, #4]
8004156: 6812 ldr r2, [r2, #0]
8004158: 4413 add r3, r2
800415a: f503 6380 add.w r3, r3, #1024 @ 0x400
800415e: 881b ldrh r3, [r3, #0]
8004160: f3c3 0209 ubfx r2, r3, #0, #10
8004164: 6d7b ldr r3, [r7, #84] @ 0x54
8004166: 61da str r2, [r3, #28]
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
8004168: 6d7b ldr r3, [r7, #84] @ 0x54
800416a: 69db ldr r3, [r3, #28]
800416c: 2b00 cmp r3, #0
800416e: d019 beq.n 80041a4 <PCD_EP_ISR_Handler+0x1f0>
8004170: 6d7b ldr r3, [r7, #84] @ 0x54
8004172: 695b ldr r3, [r3, #20]
8004174: 2b00 cmp r3, #0
8004176: d015 beq.n 80041a4 <PCD_EP_ISR_Handler+0x1f0>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8004178: 687b ldr r3, [r7, #4]
800417a: 6818 ldr r0, [r3, #0]
800417c: 6d7b ldr r3, [r7, #84] @ 0x54
800417e: 6959 ldr r1, [r3, #20]
8004180: 6d7b ldr r3, [r7, #84] @ 0x54
8004182: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
8004184: 6d7b ldr r3, [r7, #84] @ 0x54
8004186: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8004188: b29b uxth r3, r3
800418a: f004 ff84 bl 8009096 <USB_ReadPMA>
ep->xfer_buff += ep->xfer_count;
800418e: 6d7b ldr r3, [r7, #84] @ 0x54
8004190: 695a ldr r2, [r3, #20]
8004192: 6d7b ldr r3, [r7, #84] @ 0x54
8004194: 69db ldr r3, [r3, #28]
8004196: 441a add r2, r3
8004198: 6d7b ldr r3, [r7, #84] @ 0x54
800419a: 615a str r2, [r3, #20]
/* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
800419c: 2100 movs r1, #0
800419e: 6878 ldr r0, [r7, #4]
80041a0: f006 fddc bl 800ad5c <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
80041a4: 687b ldr r3, [r7, #4]
80041a6: 681b ldr r3, [r3, #0]
80041a8: 881b ldrh r3, [r3, #0]
80041aa: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
80041ae: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80041b2: f403 6300 and.w r3, r3, #2048 @ 0x800
80041b6: 2b00 cmp r3, #0
80041b8: f040 82bd bne.w 8004736 <PCD_EP_ISR_Handler+0x782>
80041bc: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80041c0: f403 5340 and.w r3, r3, #12288 @ 0x3000
80041c4: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80041c8: f000 82b5 beq.w 8004736 <PCD_EP_ISR_Handler+0x782>
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
80041cc: 687b ldr r3, [r7, #4]
80041ce: 681b ldr r3, [r3, #0]
80041d0: 61bb str r3, [r7, #24]
80041d2: 687b ldr r3, [r7, #4]
80041d4: 681b ldr r3, [r3, #0]
80041d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80041da: b29b uxth r3, r3
80041dc: 461a mov r2, r3
80041de: 69bb ldr r3, [r7, #24]
80041e0: 4413 add r3, r2
80041e2: 61bb str r3, [r7, #24]
80041e4: 69bb ldr r3, [r7, #24]
80041e6: f203 430c addw r3, r3, #1036 @ 0x40c
80041ea: 617b str r3, [r7, #20]
80041ec: 697b ldr r3, [r7, #20]
80041ee: 881b ldrh r3, [r3, #0]
80041f0: b29b uxth r3, r3
80041f2: f3c3 0309 ubfx r3, r3, #0, #10
80041f6: b29a uxth r2, r3
80041f8: 697b ldr r3, [r7, #20]
80041fa: 801a strh r2, [r3, #0]
80041fc: 6d7b ldr r3, [r7, #84] @ 0x54
80041fe: 691b ldr r3, [r3, #16]
8004200: 2b3e cmp r3, #62 @ 0x3e
8004202: d91d bls.n 8004240 <PCD_EP_ISR_Handler+0x28c>
8004204: 6d7b ldr r3, [r7, #84] @ 0x54
8004206: 691b ldr r3, [r3, #16]
8004208: 095b lsrs r3, r3, #5
800420a: 647b str r3, [r7, #68] @ 0x44
800420c: 6d7b ldr r3, [r7, #84] @ 0x54
800420e: 691b ldr r3, [r3, #16]
8004210: f003 031f and.w r3, r3, #31
8004214: 2b00 cmp r3, #0
8004216: d102 bne.n 800421e <PCD_EP_ISR_Handler+0x26a>
8004218: 6c7b ldr r3, [r7, #68] @ 0x44
800421a: 3b01 subs r3, #1
800421c: 647b str r3, [r7, #68] @ 0x44
800421e: 697b ldr r3, [r7, #20]
8004220: 881b ldrh r3, [r3, #0]
8004222: b29a uxth r2, r3
8004224: 6c7b ldr r3, [r7, #68] @ 0x44
8004226: b29b uxth r3, r3
8004228: 029b lsls r3, r3, #10
800422a: b29b uxth r3, r3
800422c: 4313 orrs r3, r2
800422e: b29b uxth r3, r3
8004230: ea6f 4343 mvn.w r3, r3, lsl #17
8004234: ea6f 4353 mvn.w r3, r3, lsr #17
8004238: b29a uxth r2, r3
800423a: 697b ldr r3, [r7, #20]
800423c: 801a strh r2, [r3, #0]
800423e: e026 b.n 800428e <PCD_EP_ISR_Handler+0x2da>
8004240: 6d7b ldr r3, [r7, #84] @ 0x54
8004242: 691b ldr r3, [r3, #16]
8004244: 2b00 cmp r3, #0
8004246: d10a bne.n 800425e <PCD_EP_ISR_Handler+0x2aa>
8004248: 697b ldr r3, [r7, #20]
800424a: 881b ldrh r3, [r3, #0]
800424c: b29b uxth r3, r3
800424e: ea6f 4343 mvn.w r3, r3, lsl #17
8004252: ea6f 4353 mvn.w r3, r3, lsr #17
8004256: b29a uxth r2, r3
8004258: 697b ldr r3, [r7, #20]
800425a: 801a strh r2, [r3, #0]
800425c: e017 b.n 800428e <PCD_EP_ISR_Handler+0x2da>
800425e: 6d7b ldr r3, [r7, #84] @ 0x54
8004260: 691b ldr r3, [r3, #16]
8004262: 085b lsrs r3, r3, #1
8004264: 647b str r3, [r7, #68] @ 0x44
8004266: 6d7b ldr r3, [r7, #84] @ 0x54
8004268: 691b ldr r3, [r3, #16]
800426a: f003 0301 and.w r3, r3, #1
800426e: 2b00 cmp r3, #0
8004270: d002 beq.n 8004278 <PCD_EP_ISR_Handler+0x2c4>
8004272: 6c7b ldr r3, [r7, #68] @ 0x44
8004274: 3301 adds r3, #1
8004276: 647b str r3, [r7, #68] @ 0x44
8004278: 697b ldr r3, [r7, #20]
800427a: 881b ldrh r3, [r3, #0]
800427c: b29a uxth r2, r3
800427e: 6c7b ldr r3, [r7, #68] @ 0x44
8004280: b29b uxth r3, r3
8004282: 029b lsls r3, r3, #10
8004284: b29b uxth r3, r3
8004286: 4313 orrs r3, r2
8004288: b29a uxth r2, r3
800428a: 697b ldr r3, [r7, #20]
800428c: 801a strh r2, [r3, #0]
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
800428e: 687b ldr r3, [r7, #4]
8004290: 681b ldr r3, [r3, #0]
8004292: 881b ldrh r3, [r3, #0]
8004294: b29b uxth r3, r3
8004296: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800429a: f023 0370 bic.w r3, r3, #112 @ 0x70
800429e: 827b strh r3, [r7, #18]
80042a0: 8a7b ldrh r3, [r7, #18]
80042a2: f483 5380 eor.w r3, r3, #4096 @ 0x1000
80042a6: 827b strh r3, [r7, #18]
80042a8: 8a7b ldrh r3, [r7, #18]
80042aa: f483 5300 eor.w r3, r3, #8192 @ 0x2000
80042ae: 827b strh r3, [r7, #18]
80042b0: 687b ldr r3, [r7, #4]
80042b2: 681a ldr r2, [r3, #0]
80042b4: 8a7b ldrh r3, [r7, #18]
80042b6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80042ba: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80042be: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80042c2: f043 0380 orr.w r3, r3, #128 @ 0x80
80042c6: b29b uxth r3, r3
80042c8: 8013 strh r3, [r2, #0]
80042ca: e234 b.n 8004736 <PCD_EP_ISR_Handler+0x782>
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
80042cc: 687b ldr r3, [r7, #4]
80042ce: 681b ldr r3, [r3, #0]
80042d0: 461a mov r2, r3
80042d2: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80042d6: 009b lsls r3, r3, #2
80042d8: 4413 add r3, r2
80042da: 881b ldrh r3, [r3, #0]
80042dc: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_CTR_RX) != 0U)
80042e0: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
80042e4: 2b00 cmp r3, #0
80042e6: f280 80fc bge.w 80044e2 <PCD_EP_ISR_Handler+0x52e>
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
80042ea: 687b ldr r3, [r7, #4]
80042ec: 681b ldr r3, [r3, #0]
80042ee: 461a mov r2, r3
80042f0: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80042f4: 009b lsls r3, r3, #2
80042f6: 4413 add r3, r2
80042f8: 881b ldrh r3, [r3, #0]
80042fa: b29a uxth r2, r3
80042fc: f640 738f movw r3, #3983 @ 0xf8f
8004300: 4013 ands r3, r2
8004302: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
8004306: 687b ldr r3, [r7, #4]
8004308: 681b ldr r3, [r3, #0]
800430a: 461a mov r2, r3
800430c: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8004310: 009b lsls r3, r3, #2
8004312: 4413 add r3, r2
8004314: f8b7 2048 ldrh.w r2, [r7, #72] @ 0x48
8004318: f042 0280 orr.w r2, r2, #128 @ 0x80
800431c: b292 uxth r2, r2
800431e: 801a strh r2, [r3, #0]
ep = &hpcd->OUT_ep[epindex];
8004320: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
8004324: 4613 mov r3, r2
8004326: 009b lsls r3, r3, #2
8004328: 4413 add r3, r2
800432a: 00db lsls r3, r3, #3
800432c: f503 73a8 add.w r3, r3, #336 @ 0x150
8004330: 687a ldr r2, [r7, #4]
8004332: 4413 add r3, r2
8004334: 657b str r3, [r7, #84] @ 0x54
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
8004336: 6d7b ldr r3, [r7, #84] @ 0x54
8004338: 7b1b ldrb r3, [r3, #12]
800433a: 2b00 cmp r3, #0
800433c: d125 bne.n 800438a <PCD_EP_ISR_Handler+0x3d6>
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800433e: 687b ldr r3, [r7, #4]
8004340: 681b ldr r3, [r3, #0]
8004342: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004346: b29b uxth r3, r3
8004348: 461a mov r2, r3
800434a: 6d7b ldr r3, [r7, #84] @ 0x54
800434c: 781b ldrb r3, [r3, #0]
800434e: 00db lsls r3, r3, #3
8004350: 4413 add r3, r2
8004352: 3306 adds r3, #6
8004354: 005b lsls r3, r3, #1
8004356: 687a ldr r2, [r7, #4]
8004358: 6812 ldr r2, [r2, #0]
800435a: 4413 add r3, r2
800435c: f503 6380 add.w r3, r3, #1024 @ 0x400
8004360: 881b ldrh r3, [r3, #0]
8004362: f3c3 0309 ubfx r3, r3, #0, #10
8004366: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
800436a: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800436e: 2b00 cmp r3, #0
8004370: f000 8092 beq.w 8004498 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
8004374: 687b ldr r3, [r7, #4]
8004376: 6818 ldr r0, [r3, #0]
8004378: 6d7b ldr r3, [r7, #84] @ 0x54
800437a: 6959 ldr r1, [r3, #20]
800437c: 6d7b ldr r3, [r7, #84] @ 0x54
800437e: 88da ldrh r2, [r3, #6]
8004380: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004384: f004 fe87 bl 8009096 <USB_ReadPMA>
8004388: e086 b.n 8004498 <PCD_EP_ISR_Handler+0x4e4>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
800438a: 6d7b ldr r3, [r7, #84] @ 0x54
800438c: 78db ldrb r3, [r3, #3]
800438e: 2b02 cmp r3, #2
8004390: d10a bne.n 80043a8 <PCD_EP_ISR_Handler+0x3f4>
{
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
8004392: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004396: 461a mov r2, r3
8004398: 6d79 ldr r1, [r7, #84] @ 0x54
800439a: 6878 ldr r0, [r7, #4]
800439c: f000 f9d9 bl 8004752 <HAL_PCD_EP_DB_Receive>
80043a0: 4603 mov r3, r0
80043a2: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
80043a6: e077 b.n 8004498 <PCD_EP_ISR_Handler+0x4e4>
}
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
80043a8: 687b ldr r3, [r7, #4]
80043aa: 681b ldr r3, [r3, #0]
80043ac: 461a mov r2, r3
80043ae: 6d7b ldr r3, [r7, #84] @ 0x54
80043b0: 781b ldrb r3, [r3, #0]
80043b2: 009b lsls r3, r3, #2
80043b4: 4413 add r3, r2
80043b6: 881b ldrh r3, [r3, #0]
80043b8: b29b uxth r3, r3
80043ba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80043be: f023 0370 bic.w r3, r3, #112 @ 0x70
80043c2: f8a7 3052 strh.w r3, [r7, #82] @ 0x52
80043c6: 687b ldr r3, [r7, #4]
80043c8: 681b ldr r3, [r3, #0]
80043ca: 461a mov r2, r3
80043cc: 6d7b ldr r3, [r7, #84] @ 0x54
80043ce: 781b ldrb r3, [r3, #0]
80043d0: 009b lsls r3, r3, #2
80043d2: 441a add r2, r3
80043d4: f8b7 3052 ldrh.w r3, [r7, #82] @ 0x52
80043d8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80043dc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80043e0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80043e4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80043e8: b29b uxth r3, r3
80043ea: 8013 strh r3, [r2, #0]
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
80043ec: 687b ldr r3, [r7, #4]
80043ee: 681b ldr r3, [r3, #0]
80043f0: 461a mov r2, r3
80043f2: 6d7b ldr r3, [r7, #84] @ 0x54
80043f4: 781b ldrb r3, [r3, #0]
80043f6: 009b lsls r3, r3, #2
80043f8: 4413 add r3, r2
80043fa: 881b ldrh r3, [r3, #0]
80043fc: b29b uxth r3, r3
80043fe: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004402: 2b00 cmp r3, #0
8004404: d024 beq.n 8004450 <PCD_EP_ISR_Handler+0x49c>
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8004406: 687b ldr r3, [r7, #4]
8004408: 681b ldr r3, [r3, #0]
800440a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800440e: b29b uxth r3, r3
8004410: 461a mov r2, r3
8004412: 6d7b ldr r3, [r7, #84] @ 0x54
8004414: 781b ldrb r3, [r3, #0]
8004416: 00db lsls r3, r3, #3
8004418: 4413 add r3, r2
800441a: 3302 adds r3, #2
800441c: 005b lsls r3, r3, #1
800441e: 687a ldr r2, [r7, #4]
8004420: 6812 ldr r2, [r2, #0]
8004422: 4413 add r3, r2
8004424: f503 6380 add.w r3, r3, #1024 @ 0x400
8004428: 881b ldrh r3, [r3, #0]
800442a: f3c3 0309 ubfx r3, r3, #0, #10
800442e: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
8004432: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004436: 2b00 cmp r3, #0
8004438: d02e beq.n 8004498 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
800443a: 687b ldr r3, [r7, #4]
800443c: 6818 ldr r0, [r3, #0]
800443e: 6d7b ldr r3, [r7, #84] @ 0x54
8004440: 6959 ldr r1, [r3, #20]
8004442: 6d7b ldr r3, [r7, #84] @ 0x54
8004444: 891a ldrh r2, [r3, #8]
8004446: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800444a: f004 fe24 bl 8009096 <USB_ReadPMA>
800444e: e023 b.n 8004498 <PCD_EP_ISR_Handler+0x4e4>
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8004450: 687b ldr r3, [r7, #4]
8004452: 681b ldr r3, [r3, #0]
8004454: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004458: b29b uxth r3, r3
800445a: 461a mov r2, r3
800445c: 6d7b ldr r3, [r7, #84] @ 0x54
800445e: 781b ldrb r3, [r3, #0]
8004460: 00db lsls r3, r3, #3
8004462: 4413 add r3, r2
8004464: 3306 adds r3, #6
8004466: 005b lsls r3, r3, #1
8004468: 687a ldr r2, [r7, #4]
800446a: 6812 ldr r2, [r2, #0]
800446c: 4413 add r3, r2
800446e: f503 6380 add.w r3, r3, #1024 @ 0x400
8004472: 881b ldrh r3, [r3, #0]
8004474: f3c3 0309 ubfx r3, r3, #0, #10
8004478: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
800447c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004480: 2b00 cmp r3, #0
8004482: d009 beq.n 8004498 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8004484: 687b ldr r3, [r7, #4]
8004486: 6818 ldr r0, [r3, #0]
8004488: 6d7b ldr r3, [r7, #84] @ 0x54
800448a: 6959 ldr r1, [r3, #20]
800448c: 6d7b ldr r3, [r7, #84] @ 0x54
800448e: 895a ldrh r2, [r3, #10]
8004490: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004494: f004 fdff bl 8009096 <USB_ReadPMA>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
8004498: 6d7b ldr r3, [r7, #84] @ 0x54
800449a: 69da ldr r2, [r3, #28]
800449c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80044a0: 441a add r2, r3
80044a2: 6d7b ldr r3, [r7, #84] @ 0x54
80044a4: 61da str r2, [r3, #28]
ep->xfer_buff += count;
80044a6: 6d7b ldr r3, [r7, #84] @ 0x54
80044a8: 695a ldr r2, [r3, #20]
80044aa: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80044ae: 441a add r2, r3
80044b0: 6d7b ldr r3, [r7, #84] @ 0x54
80044b2: 615a str r2, [r3, #20]
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
80044b4: 6d7b ldr r3, [r7, #84] @ 0x54
80044b6: 699b ldr r3, [r3, #24]
80044b8: 2b00 cmp r3, #0
80044ba: d005 beq.n 80044c8 <PCD_EP_ISR_Handler+0x514>
80044bc: f8b7 2050 ldrh.w r2, [r7, #80] @ 0x50
80044c0: 6d7b ldr r3, [r7, #84] @ 0x54
80044c2: 691b ldr r3, [r3, #16]
80044c4: 429a cmp r2, r3
80044c6: d206 bcs.n 80044d6 <PCD_EP_ISR_Handler+0x522>
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
80044c8: 6d7b ldr r3, [r7, #84] @ 0x54
80044ca: 781b ldrb r3, [r3, #0]
80044cc: 4619 mov r1, r3
80044ce: 6878 ldr r0, [r7, #4]
80044d0: f006 fc44 bl 800ad5c <HAL_PCD_DataOutStageCallback>
80044d4: e005 b.n 80044e2 <PCD_EP_ISR_Handler+0x52e>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
80044d6: 687b ldr r3, [r7, #4]
80044d8: 681b ldr r3, [r3, #0]
80044da: 6d79 ldr r1, [r7, #84] @ 0x54
80044dc: 4618 mov r0, r3
80044de: f003 f8a5 bl 800762c <USB_EPStartXfer>
}
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
80044e2: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80044e6: f003 0380 and.w r3, r3, #128 @ 0x80
80044ea: 2b00 cmp r3, #0
80044ec: f000 8123 beq.w 8004736 <PCD_EP_ISR_Handler+0x782>
{
ep = &hpcd->IN_ep[epindex];
80044f0: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
80044f4: 4613 mov r3, r2
80044f6: 009b lsls r3, r3, #2
80044f8: 4413 add r3, r2
80044fa: 00db lsls r3, r3, #3
80044fc: 3310 adds r3, #16
80044fe: 687a ldr r2, [r7, #4]
8004500: 4413 add r3, r2
8004502: 657b str r3, [r7, #84] @ 0x54
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
8004504: 687b ldr r3, [r7, #4]
8004506: 681b ldr r3, [r3, #0]
8004508: 461a mov r2, r3
800450a: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
800450e: 009b lsls r3, r3, #2
8004510: 4413 add r3, r2
8004512: 881b ldrh r3, [r3, #0]
8004514: b29b uxth r3, r3
8004516: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
800451a: f023 0370 bic.w r3, r3, #112 @ 0x70
800451e: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
8004522: 687b ldr r3, [r7, #4]
8004524: 681b ldr r3, [r3, #0]
8004526: 461a mov r2, r3
8004528: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
800452c: 009b lsls r3, r3, #2
800452e: 441a add r2, r3
8004530: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
8004534: ea6f 4343 mvn.w r3, r3, lsl #17
8004538: ea6f 4353 mvn.w r3, r3, lsr #17
800453c: b29b uxth r3, r3
800453e: 8013 strh r3, [r2, #0]
if (ep->type == EP_TYPE_ISOC)
8004540: 6d7b ldr r3, [r7, #84] @ 0x54
8004542: 78db ldrb r3, [r3, #3]
8004544: 2b01 cmp r3, #1
8004546: f040 80a2 bne.w 800468e <PCD_EP_ISR_Handler+0x6da>
{
ep->xfer_len = 0U;
800454a: 6d7b ldr r3, [r7, #84] @ 0x54
800454c: 2200 movs r2, #0
800454e: 619a str r2, [r3, #24]
#if (USE_USB_DOUBLE_BUFFER == 1U)
if (ep->doublebuffer != 0U)
8004550: 6d7b ldr r3, [r7, #84] @ 0x54
8004552: 7b1b ldrb r3, [r3, #12]
8004554: 2b00 cmp r3, #0
8004556: f000 8093 beq.w 8004680 <PCD_EP_ISR_Handler+0x6cc>
{
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
800455a: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
800455e: f003 0340 and.w r3, r3, #64 @ 0x40
8004562: 2b00 cmp r3, #0
8004564: d046 beq.n 80045f4 <PCD_EP_ISR_Handler+0x640>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004566: 6d7b ldr r3, [r7, #84] @ 0x54
8004568: 785b ldrb r3, [r3, #1]
800456a: 2b00 cmp r3, #0
800456c: d126 bne.n 80045bc <PCD_EP_ISR_Handler+0x608>
800456e: 687b ldr r3, [r7, #4]
8004570: 681b ldr r3, [r3, #0]
8004572: 627b str r3, [r7, #36] @ 0x24
8004574: 687b ldr r3, [r7, #4]
8004576: 681b ldr r3, [r3, #0]
8004578: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800457c: b29b uxth r3, r3
800457e: 461a mov r2, r3
8004580: 6a7b ldr r3, [r7, #36] @ 0x24
8004582: 4413 add r3, r2
8004584: 627b str r3, [r7, #36] @ 0x24
8004586: 6d7b ldr r3, [r7, #84] @ 0x54
8004588: 781b ldrb r3, [r3, #0]
800458a: 011a lsls r2, r3, #4
800458c: 6a7b ldr r3, [r7, #36] @ 0x24
800458e: 4413 add r3, r2
8004590: f203 4304 addw r3, r3, #1028 @ 0x404
8004594: 623b str r3, [r7, #32]
8004596: 6a3b ldr r3, [r7, #32]
8004598: 881b ldrh r3, [r3, #0]
800459a: b29b uxth r3, r3
800459c: f3c3 0309 ubfx r3, r3, #0, #10
80045a0: b29a uxth r2, r3
80045a2: 6a3b ldr r3, [r7, #32]
80045a4: 801a strh r2, [r3, #0]
80045a6: 6a3b ldr r3, [r7, #32]
80045a8: 881b ldrh r3, [r3, #0]
80045aa: b29b uxth r3, r3
80045ac: ea6f 4343 mvn.w r3, r3, lsl #17
80045b0: ea6f 4353 mvn.w r3, r3, lsr #17
80045b4: b29a uxth r2, r3
80045b6: 6a3b ldr r3, [r7, #32]
80045b8: 801a strh r2, [r3, #0]
80045ba: e061 b.n 8004680 <PCD_EP_ISR_Handler+0x6cc>
80045bc: 6d7b ldr r3, [r7, #84] @ 0x54
80045be: 785b ldrb r3, [r3, #1]
80045c0: 2b01 cmp r3, #1
80045c2: d15d bne.n 8004680 <PCD_EP_ISR_Handler+0x6cc>
80045c4: 687b ldr r3, [r7, #4]
80045c6: 681b ldr r3, [r3, #0]
80045c8: 62fb str r3, [r7, #44] @ 0x2c
80045ca: 687b ldr r3, [r7, #4]
80045cc: 681b ldr r3, [r3, #0]
80045ce: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80045d2: b29b uxth r3, r3
80045d4: 461a mov r2, r3
80045d6: 6afb ldr r3, [r7, #44] @ 0x2c
80045d8: 4413 add r3, r2
80045da: 62fb str r3, [r7, #44] @ 0x2c
80045dc: 6d7b ldr r3, [r7, #84] @ 0x54
80045de: 781b ldrb r3, [r3, #0]
80045e0: 011a lsls r2, r3, #4
80045e2: 6afb ldr r3, [r7, #44] @ 0x2c
80045e4: 4413 add r3, r2
80045e6: f203 4304 addw r3, r3, #1028 @ 0x404
80045ea: 62bb str r3, [r7, #40] @ 0x28
80045ec: 6abb ldr r3, [r7, #40] @ 0x28
80045ee: 2200 movs r2, #0
80045f0: 801a strh r2, [r3, #0]
80045f2: e045 b.n 8004680 <PCD_EP_ISR_Handler+0x6cc>
}
else
{
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80045f4: 687b ldr r3, [r7, #4]
80045f6: 681b ldr r3, [r3, #0]
80045f8: 63fb str r3, [r7, #60] @ 0x3c
80045fa: 6d7b ldr r3, [r7, #84] @ 0x54
80045fc: 785b ldrb r3, [r3, #1]
80045fe: 2b00 cmp r3, #0
8004600: d126 bne.n 8004650 <PCD_EP_ISR_Handler+0x69c>
8004602: 687b ldr r3, [r7, #4]
8004604: 681b ldr r3, [r3, #0]
8004606: 637b str r3, [r7, #52] @ 0x34
8004608: 687b ldr r3, [r7, #4]
800460a: 681b ldr r3, [r3, #0]
800460c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004610: b29b uxth r3, r3
8004612: 461a mov r2, r3
8004614: 6b7b ldr r3, [r7, #52] @ 0x34
8004616: 4413 add r3, r2
8004618: 637b str r3, [r7, #52] @ 0x34
800461a: 6d7b ldr r3, [r7, #84] @ 0x54
800461c: 781b ldrb r3, [r3, #0]
800461e: 011a lsls r2, r3, #4
8004620: 6b7b ldr r3, [r7, #52] @ 0x34
8004622: 4413 add r3, r2
8004624: f203 430c addw r3, r3, #1036 @ 0x40c
8004628: 633b str r3, [r7, #48] @ 0x30
800462a: 6b3b ldr r3, [r7, #48] @ 0x30
800462c: 881b ldrh r3, [r3, #0]
800462e: b29b uxth r3, r3
8004630: f3c3 0309 ubfx r3, r3, #0, #10
8004634: b29a uxth r2, r3
8004636: 6b3b ldr r3, [r7, #48] @ 0x30
8004638: 801a strh r2, [r3, #0]
800463a: 6b3b ldr r3, [r7, #48] @ 0x30
800463c: 881b ldrh r3, [r3, #0]
800463e: b29b uxth r3, r3
8004640: ea6f 4343 mvn.w r3, r3, lsl #17
8004644: ea6f 4353 mvn.w r3, r3, lsr #17
8004648: b29a uxth r2, r3
800464a: 6b3b ldr r3, [r7, #48] @ 0x30
800464c: 801a strh r2, [r3, #0]
800464e: e017 b.n 8004680 <PCD_EP_ISR_Handler+0x6cc>
8004650: 6d7b ldr r3, [r7, #84] @ 0x54
8004652: 785b ldrb r3, [r3, #1]
8004654: 2b01 cmp r3, #1
8004656: d113 bne.n 8004680 <PCD_EP_ISR_Handler+0x6cc>
8004658: 687b ldr r3, [r7, #4]
800465a: 681b ldr r3, [r3, #0]
800465c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004660: b29b uxth r3, r3
8004662: 461a mov r2, r3
8004664: 6bfb ldr r3, [r7, #60] @ 0x3c
8004666: 4413 add r3, r2
8004668: 63fb str r3, [r7, #60] @ 0x3c
800466a: 6d7b ldr r3, [r7, #84] @ 0x54
800466c: 781b ldrb r3, [r3, #0]
800466e: 011a lsls r2, r3, #4
8004670: 6bfb ldr r3, [r7, #60] @ 0x3c
8004672: 4413 add r3, r2
8004674: f203 430c addw r3, r3, #1036 @ 0x40c
8004678: 63bb str r3, [r7, #56] @ 0x38
800467a: 6bbb ldr r3, [r7, #56] @ 0x38
800467c: 2200 movs r2, #0
800467e: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8004680: 6d7b ldr r3, [r7, #84] @ 0x54
8004682: 781b ldrb r3, [r3, #0]
8004684: 4619 mov r1, r3
8004686: 6878 ldr r0, [r7, #4]
8004688: f006 fb83 bl 800ad92 <HAL_PCD_DataInStageCallback>
800468c: e053 b.n 8004736 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
800468e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004692: f403 7380 and.w r3, r3, #256 @ 0x100
8004696: 2b00 cmp r3, #0
8004698: d146 bne.n 8004728 <PCD_EP_ISR_Handler+0x774>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
800469a: 687b ldr r3, [r7, #4]
800469c: 681b ldr r3, [r3, #0]
800469e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80046a2: b29b uxth r3, r3
80046a4: 461a mov r2, r3
80046a6: 6d7b ldr r3, [r7, #84] @ 0x54
80046a8: 781b ldrb r3, [r3, #0]
80046aa: 00db lsls r3, r3, #3
80046ac: 4413 add r3, r2
80046ae: 3302 adds r3, #2
80046b0: 005b lsls r3, r3, #1
80046b2: 687a ldr r2, [r7, #4]
80046b4: 6812 ldr r2, [r2, #0]
80046b6: 4413 add r3, r2
80046b8: f503 6380 add.w r3, r3, #1024 @ 0x400
80046bc: 881b ldrh r3, [r3, #0]
80046be: f3c3 0309 ubfx r3, r3, #0, #10
80046c2: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
if (ep->xfer_len > TxPctSize)
80046c6: 6d7b ldr r3, [r7, #84] @ 0x54
80046c8: 699a ldr r2, [r3, #24]
80046ca: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80046ce: 429a cmp r2, r3
80046d0: d907 bls.n 80046e2 <PCD_EP_ISR_Handler+0x72e>
{
ep->xfer_len -= TxPctSize;
80046d2: 6d7b ldr r3, [r7, #84] @ 0x54
80046d4: 699a ldr r2, [r3, #24]
80046d6: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80046da: 1ad2 subs r2, r2, r3
80046dc: 6d7b ldr r3, [r7, #84] @ 0x54
80046de: 619a str r2, [r3, #24]
80046e0: e002 b.n 80046e8 <PCD_EP_ISR_Handler+0x734>
}
else
{
ep->xfer_len = 0U;
80046e2: 6d7b ldr r3, [r7, #84] @ 0x54
80046e4: 2200 movs r2, #0
80046e6: 619a str r2, [r3, #24]
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
80046e8: 6d7b ldr r3, [r7, #84] @ 0x54
80046ea: 699b ldr r3, [r3, #24]
80046ec: 2b00 cmp r3, #0
80046ee: d106 bne.n 80046fe <PCD_EP_ISR_Handler+0x74a>
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80046f0: 6d7b ldr r3, [r7, #84] @ 0x54
80046f2: 781b ldrb r3, [r3, #0]
80046f4: 4619 mov r1, r3
80046f6: 6878 ldr r0, [r7, #4]
80046f8: f006 fb4b bl 800ad92 <HAL_PCD_DataInStageCallback>
80046fc: e01b b.n 8004736 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxPctSize;
80046fe: 6d7b ldr r3, [r7, #84] @ 0x54
8004700: 695a ldr r2, [r3, #20]
8004702: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8004706: 441a add r2, r3
8004708: 6d7b ldr r3, [r7, #84] @ 0x54
800470a: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
800470c: 6d7b ldr r3, [r7, #84] @ 0x54
800470e: 69da ldr r2, [r3, #28]
8004710: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8004714: 441a add r2, r3
8004716: 6d7b ldr r3, [r7, #84] @ 0x54
8004718: 61da str r2, [r3, #28]
(void)USB_EPStartXfer(hpcd->Instance, ep);
800471a: 687b ldr r3, [r7, #4]
800471c: 681b ldr r3, [r3, #0]
800471e: 6d79 ldr r1, [r7, #84] @ 0x54
8004720: 4618 mov r0, r3
8004722: f002 ff83 bl 800762c <USB_EPStartXfer>
8004726: e006 b.n 8004736 <PCD_EP_ISR_Handler+0x782>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
8004728: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
800472c: 461a mov r2, r3
800472e: 6d79 ldr r1, [r7, #84] @ 0x54
8004730: 6878 ldr r0, [r7, #4]
8004732: f000 f91b bl 800496c <HAL_PCD_EP_DB_Transmit>
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8004736: 687b ldr r3, [r7, #4]
8004738: 681b ldr r3, [r3, #0]
800473a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
800473e: b29b uxth r3, r3
8004740: b21b sxth r3, r3
8004742: 2b00 cmp r3, #0
8004744: f6ff ac3b blt.w 8003fbe <PCD_EP_ISR_Handler+0xa>
}
}
}
}
return HAL_OK;
8004748: 2300 movs r3, #0
}
800474a: 4618 mov r0, r3
800474c: 3758 adds r7, #88 @ 0x58
800474e: 46bd mov sp, r7
8004750: bd80 pop {r7, pc}
08004752 <HAL_PCD_EP_DB_Receive>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8004752: b580 push {r7, lr}
8004754: b088 sub sp, #32
8004756: af00 add r7, sp, #0
8004758: 60f8 str r0, [r7, #12]
800475a: 60b9 str r1, [r7, #8]
800475c: 4613 mov r3, r2
800475e: 80fb strh r3, [r7, #6]
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8004760: 88fb ldrh r3, [r7, #6]
8004762: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004766: 2b00 cmp r3, #0
8004768: d07e beq.n 8004868 <HAL_PCD_EP_DB_Receive+0x116>
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
800476a: 68fb ldr r3, [r7, #12]
800476c: 681b ldr r3, [r3, #0]
800476e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004772: b29b uxth r3, r3
8004774: 461a mov r2, r3
8004776: 68bb ldr r3, [r7, #8]
8004778: 781b ldrb r3, [r3, #0]
800477a: 00db lsls r3, r3, #3
800477c: 4413 add r3, r2
800477e: 3302 adds r3, #2
8004780: 005b lsls r3, r3, #1
8004782: 68fa ldr r2, [r7, #12]
8004784: 6812 ldr r2, [r2, #0]
8004786: 4413 add r3, r2
8004788: f503 6380 add.w r3, r3, #1024 @ 0x400
800478c: 881b ldrh r3, [r3, #0]
800478e: f3c3 0309 ubfx r3, r3, #0, #10
8004792: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8004794: 68bb ldr r3, [r7, #8]
8004796: 699a ldr r2, [r3, #24]
8004798: 8b7b ldrh r3, [r7, #26]
800479a: 429a cmp r2, r3
800479c: d306 bcc.n 80047ac <HAL_PCD_EP_DB_Receive+0x5a>
{
ep->xfer_len -= count;
800479e: 68bb ldr r3, [r7, #8]
80047a0: 699a ldr r2, [r3, #24]
80047a2: 8b7b ldrh r3, [r7, #26]
80047a4: 1ad2 subs r2, r2, r3
80047a6: 68bb ldr r3, [r7, #8]
80047a8: 619a str r2, [r3, #24]
80047aa: e002 b.n 80047b2 <HAL_PCD_EP_DB_Receive+0x60>
}
else
{
ep->xfer_len = 0U;
80047ac: 68bb ldr r3, [r7, #8]
80047ae: 2200 movs r2, #0
80047b0: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
80047b2: 68bb ldr r3, [r7, #8]
80047b4: 699b ldr r3, [r3, #24]
80047b6: 2b00 cmp r3, #0
80047b8: d123 bne.n 8004802 <HAL_PCD_EP_DB_Receive+0xb0>
{
/* set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
80047ba: 68fb ldr r3, [r7, #12]
80047bc: 681b ldr r3, [r3, #0]
80047be: 461a mov r2, r3
80047c0: 68bb ldr r3, [r7, #8]
80047c2: 781b ldrb r3, [r3, #0]
80047c4: 009b lsls r3, r3, #2
80047c6: 4413 add r3, r2
80047c8: 881b ldrh r3, [r3, #0]
80047ca: b29b uxth r3, r3
80047cc: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80047d0: f023 0370 bic.w r3, r3, #112 @ 0x70
80047d4: 833b strh r3, [r7, #24]
80047d6: 8b3b ldrh r3, [r7, #24]
80047d8: f483 5300 eor.w r3, r3, #8192 @ 0x2000
80047dc: 833b strh r3, [r7, #24]
80047de: 68fb ldr r3, [r7, #12]
80047e0: 681b ldr r3, [r3, #0]
80047e2: 461a mov r2, r3
80047e4: 68bb ldr r3, [r7, #8]
80047e6: 781b ldrb r3, [r3, #0]
80047e8: 009b lsls r3, r3, #2
80047ea: 441a add r2, r3
80047ec: 8b3b ldrh r3, [r7, #24]
80047ee: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80047f2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80047f6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80047fa: f043 0380 orr.w r3, r3, #128 @ 0x80
80047fe: b29b uxth r3, r3
8004800: 8013 strh r3, [r2, #0]
}
/* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8004802: 88fb ldrh r3, [r7, #6]
8004804: f003 0340 and.w r3, r3, #64 @ 0x40
8004808: 2b00 cmp r3, #0
800480a: d01f beq.n 800484c <HAL_PCD_EP_DB_Receive+0xfa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
800480c: 68fb ldr r3, [r7, #12]
800480e: 681b ldr r3, [r3, #0]
8004810: 461a mov r2, r3
8004812: 68bb ldr r3, [r7, #8]
8004814: 781b ldrb r3, [r3, #0]
8004816: 009b lsls r3, r3, #2
8004818: 4413 add r3, r2
800481a: 881b ldrh r3, [r3, #0]
800481c: b29b uxth r3, r3
800481e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004822: f023 0370 bic.w r3, r3, #112 @ 0x70
8004826: 82fb strh r3, [r7, #22]
8004828: 68fb ldr r3, [r7, #12]
800482a: 681b ldr r3, [r3, #0]
800482c: 461a mov r2, r3
800482e: 68bb ldr r3, [r7, #8]
8004830: 781b ldrb r3, [r3, #0]
8004832: 009b lsls r3, r3, #2
8004834: 441a add r2, r3
8004836: 8afb ldrh r3, [r7, #22]
8004838: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800483c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004840: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004844: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8004848: b29b uxth r3, r3
800484a: 8013 strh r3, [r2, #0]
}
if (count != 0U)
800484c: 8b7b ldrh r3, [r7, #26]
800484e: 2b00 cmp r3, #0
8004850: f000 8087 beq.w 8004962 <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
8004854: 68fb ldr r3, [r7, #12]
8004856: 6818 ldr r0, [r3, #0]
8004858: 68bb ldr r3, [r7, #8]
800485a: 6959 ldr r1, [r3, #20]
800485c: 68bb ldr r3, [r7, #8]
800485e: 891a ldrh r2, [r3, #8]
8004860: 8b7b ldrh r3, [r7, #26]
8004862: f004 fc18 bl 8009096 <USB_ReadPMA>
8004866: e07c b.n 8004962 <HAL_PCD_EP_DB_Receive+0x210>
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8004868: 68fb ldr r3, [r7, #12]
800486a: 681b ldr r3, [r3, #0]
800486c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004870: b29b uxth r3, r3
8004872: 461a mov r2, r3
8004874: 68bb ldr r3, [r7, #8]
8004876: 781b ldrb r3, [r3, #0]
8004878: 00db lsls r3, r3, #3
800487a: 4413 add r3, r2
800487c: 3306 adds r3, #6
800487e: 005b lsls r3, r3, #1
8004880: 68fa ldr r2, [r7, #12]
8004882: 6812 ldr r2, [r2, #0]
8004884: 4413 add r3, r2
8004886: f503 6380 add.w r3, r3, #1024 @ 0x400
800488a: 881b ldrh r3, [r3, #0]
800488c: f3c3 0309 ubfx r3, r3, #0, #10
8004890: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8004892: 68bb ldr r3, [r7, #8]
8004894: 699a ldr r2, [r3, #24]
8004896: 8b7b ldrh r3, [r7, #26]
8004898: 429a cmp r2, r3
800489a: d306 bcc.n 80048aa <HAL_PCD_EP_DB_Receive+0x158>
{
ep->xfer_len -= count;
800489c: 68bb ldr r3, [r7, #8]
800489e: 699a ldr r2, [r3, #24]
80048a0: 8b7b ldrh r3, [r7, #26]
80048a2: 1ad2 subs r2, r2, r3
80048a4: 68bb ldr r3, [r7, #8]
80048a6: 619a str r2, [r3, #24]
80048a8: e002 b.n 80048b0 <HAL_PCD_EP_DB_Receive+0x15e>
}
else
{
ep->xfer_len = 0U;
80048aa: 68bb ldr r3, [r7, #8]
80048ac: 2200 movs r2, #0
80048ae: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
80048b0: 68bb ldr r3, [r7, #8]
80048b2: 699b ldr r3, [r3, #24]
80048b4: 2b00 cmp r3, #0
80048b6: d123 bne.n 8004900 <HAL_PCD_EP_DB_Receive+0x1ae>
{
/* set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
80048b8: 68fb ldr r3, [r7, #12]
80048ba: 681b ldr r3, [r3, #0]
80048bc: 461a mov r2, r3
80048be: 68bb ldr r3, [r7, #8]
80048c0: 781b ldrb r3, [r3, #0]
80048c2: 009b lsls r3, r3, #2
80048c4: 4413 add r3, r2
80048c6: 881b ldrh r3, [r3, #0]
80048c8: b29b uxth r3, r3
80048ca: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80048ce: f023 0370 bic.w r3, r3, #112 @ 0x70
80048d2: 83fb strh r3, [r7, #30]
80048d4: 8bfb ldrh r3, [r7, #30]
80048d6: f483 5300 eor.w r3, r3, #8192 @ 0x2000
80048da: 83fb strh r3, [r7, #30]
80048dc: 68fb ldr r3, [r7, #12]
80048de: 681b ldr r3, [r3, #0]
80048e0: 461a mov r2, r3
80048e2: 68bb ldr r3, [r7, #8]
80048e4: 781b ldrb r3, [r3, #0]
80048e6: 009b lsls r3, r3, #2
80048e8: 441a add r2, r3
80048ea: 8bfb ldrh r3, [r7, #30]
80048ec: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80048f0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80048f4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80048f8: f043 0380 orr.w r3, r3, #128 @ 0x80
80048fc: b29b uxth r3, r3
80048fe: 8013 strh r3, [r2, #0]
}
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
8004900: 88fb ldrh r3, [r7, #6]
8004902: f003 0340 and.w r3, r3, #64 @ 0x40
8004906: 2b00 cmp r3, #0
8004908: d11f bne.n 800494a <HAL_PCD_EP_DB_Receive+0x1f8>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
800490a: 68fb ldr r3, [r7, #12]
800490c: 681b ldr r3, [r3, #0]
800490e: 461a mov r2, r3
8004910: 68bb ldr r3, [r7, #8]
8004912: 781b ldrb r3, [r3, #0]
8004914: 009b lsls r3, r3, #2
8004916: 4413 add r3, r2
8004918: 881b ldrh r3, [r3, #0]
800491a: b29b uxth r3, r3
800491c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004920: f023 0370 bic.w r3, r3, #112 @ 0x70
8004924: 83bb strh r3, [r7, #28]
8004926: 68fb ldr r3, [r7, #12]
8004928: 681b ldr r3, [r3, #0]
800492a: 461a mov r2, r3
800492c: 68bb ldr r3, [r7, #8]
800492e: 781b ldrb r3, [r3, #0]
8004930: 009b lsls r3, r3, #2
8004932: 441a add r2, r3
8004934: 8bbb ldrh r3, [r7, #28]
8004936: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800493a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800493e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004942: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8004946: b29b uxth r3, r3
8004948: 8013 strh r3, [r2, #0]
}
if (count != 0U)
800494a: 8b7b ldrh r3, [r7, #26]
800494c: 2b00 cmp r3, #0
800494e: d008 beq.n 8004962 <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8004950: 68fb ldr r3, [r7, #12]
8004952: 6818 ldr r0, [r3, #0]
8004954: 68bb ldr r3, [r7, #8]
8004956: 6959 ldr r1, [r3, #20]
8004958: 68bb ldr r3, [r7, #8]
800495a: 895a ldrh r2, [r3, #10]
800495c: 8b7b ldrh r3, [r7, #26]
800495e: f004 fb9a bl 8009096 <USB_ReadPMA>
}
}
return count;
8004962: 8b7b ldrh r3, [r7, #26]
}
8004964: 4618 mov r0, r3
8004966: 3720 adds r7, #32
8004968: 46bd mov sp, r7
800496a: bd80 pop {r7, pc}
0800496c <HAL_PCD_EP_DB_Transmit>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
800496c: b580 push {r7, lr}
800496e: b0a4 sub sp, #144 @ 0x90
8004970: af00 add r7, sp, #0
8004972: 60f8 str r0, [r7, #12]
8004974: 60b9 str r1, [r7, #8]
8004976: 4613 mov r3, r2
8004978: 80fb strh r3, [r7, #6]
uint32_t len;
uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
800497a: 88fb ldrh r3, [r7, #6]
800497c: f003 0340 and.w r3, r3, #64 @ 0x40
8004980: 2b00 cmp r3, #0
8004982: f000 81dd beq.w 8004d40 <HAL_PCD_EP_DB_Transmit+0x3d4>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8004986: 68fb ldr r3, [r7, #12]
8004988: 681b ldr r3, [r3, #0]
800498a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800498e: b29b uxth r3, r3
8004990: 461a mov r2, r3
8004992: 68bb ldr r3, [r7, #8]
8004994: 781b ldrb r3, [r3, #0]
8004996: 00db lsls r3, r3, #3
8004998: 4413 add r3, r2
800499a: 3302 adds r3, #2
800499c: 005b lsls r3, r3, #1
800499e: 68fa ldr r2, [r7, #12]
80049a0: 6812 ldr r2, [r2, #0]
80049a2: 4413 add r3, r2
80049a4: f503 6380 add.w r3, r3, #1024 @ 0x400
80049a8: 881b ldrh r3, [r3, #0]
80049aa: f3c3 0309 ubfx r3, r3, #0, #10
80049ae: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len > TxPctSize)
80049b2: 68bb ldr r3, [r7, #8]
80049b4: 699a ldr r2, [r3, #24]
80049b6: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
80049ba: 429a cmp r2, r3
80049bc: d907 bls.n 80049ce <HAL_PCD_EP_DB_Transmit+0x62>
{
ep->xfer_len -= TxPctSize;
80049be: 68bb ldr r3, [r7, #8]
80049c0: 699a ldr r2, [r3, #24]
80049c2: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
80049c6: 1ad2 subs r2, r2, r3
80049c8: 68bb ldr r3, [r7, #8]
80049ca: 619a str r2, [r3, #24]
80049cc: e002 b.n 80049d4 <HAL_PCD_EP_DB_Transmit+0x68>
}
else
{
ep->xfer_len = 0U;
80049ce: 68bb ldr r3, [r7, #8]
80049d0: 2200 movs r2, #0
80049d2: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
80049d4: 68bb ldr r3, [r7, #8]
80049d6: 699b ldr r3, [r3, #24]
80049d8: 2b00 cmp r3, #0
80049da: f040 80b9 bne.w 8004b50 <HAL_PCD_EP_DB_Transmit+0x1e4>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80049de: 68bb ldr r3, [r7, #8]
80049e0: 785b ldrb r3, [r3, #1]
80049e2: 2b00 cmp r3, #0
80049e4: d126 bne.n 8004a34 <HAL_PCD_EP_DB_Transmit+0xc8>
80049e6: 68fb ldr r3, [r7, #12]
80049e8: 681b ldr r3, [r3, #0]
80049ea: 62fb str r3, [r7, #44] @ 0x2c
80049ec: 68fb ldr r3, [r7, #12]
80049ee: 681b ldr r3, [r3, #0]
80049f0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80049f4: b29b uxth r3, r3
80049f6: 461a mov r2, r3
80049f8: 6afb ldr r3, [r7, #44] @ 0x2c
80049fa: 4413 add r3, r2
80049fc: 62fb str r3, [r7, #44] @ 0x2c
80049fe: 68bb ldr r3, [r7, #8]
8004a00: 781b ldrb r3, [r3, #0]
8004a02: 011a lsls r2, r3, #4
8004a04: 6afb ldr r3, [r7, #44] @ 0x2c
8004a06: 4413 add r3, r2
8004a08: f203 4304 addw r3, r3, #1028 @ 0x404
8004a0c: 62bb str r3, [r7, #40] @ 0x28
8004a0e: 6abb ldr r3, [r7, #40] @ 0x28
8004a10: 881b ldrh r3, [r3, #0]
8004a12: b29b uxth r3, r3
8004a14: f3c3 0309 ubfx r3, r3, #0, #10
8004a18: b29a uxth r2, r3
8004a1a: 6abb ldr r3, [r7, #40] @ 0x28
8004a1c: 801a strh r2, [r3, #0]
8004a1e: 6abb ldr r3, [r7, #40] @ 0x28
8004a20: 881b ldrh r3, [r3, #0]
8004a22: b29b uxth r3, r3
8004a24: ea6f 4343 mvn.w r3, r3, lsl #17
8004a28: ea6f 4353 mvn.w r3, r3, lsr #17
8004a2c: b29a uxth r2, r3
8004a2e: 6abb ldr r3, [r7, #40] @ 0x28
8004a30: 801a strh r2, [r3, #0]
8004a32: e01a b.n 8004a6a <HAL_PCD_EP_DB_Transmit+0xfe>
8004a34: 68bb ldr r3, [r7, #8]
8004a36: 785b ldrb r3, [r3, #1]
8004a38: 2b01 cmp r3, #1
8004a3a: d116 bne.n 8004a6a <HAL_PCD_EP_DB_Transmit+0xfe>
8004a3c: 68fb ldr r3, [r7, #12]
8004a3e: 681b ldr r3, [r3, #0]
8004a40: 637b str r3, [r7, #52] @ 0x34
8004a42: 68fb ldr r3, [r7, #12]
8004a44: 681b ldr r3, [r3, #0]
8004a46: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004a4a: b29b uxth r3, r3
8004a4c: 461a mov r2, r3
8004a4e: 6b7b ldr r3, [r7, #52] @ 0x34
8004a50: 4413 add r3, r2
8004a52: 637b str r3, [r7, #52] @ 0x34
8004a54: 68bb ldr r3, [r7, #8]
8004a56: 781b ldrb r3, [r3, #0]
8004a58: 011a lsls r2, r3, #4
8004a5a: 6b7b ldr r3, [r7, #52] @ 0x34
8004a5c: 4413 add r3, r2
8004a5e: f203 4304 addw r3, r3, #1028 @ 0x404
8004a62: 633b str r3, [r7, #48] @ 0x30
8004a64: 6b3b ldr r3, [r7, #48] @ 0x30
8004a66: 2200 movs r2, #0
8004a68: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004a6a: 68fb ldr r3, [r7, #12]
8004a6c: 681b ldr r3, [r3, #0]
8004a6e: 627b str r3, [r7, #36] @ 0x24
8004a70: 68bb ldr r3, [r7, #8]
8004a72: 785b ldrb r3, [r3, #1]
8004a74: 2b00 cmp r3, #0
8004a76: d126 bne.n 8004ac6 <HAL_PCD_EP_DB_Transmit+0x15a>
8004a78: 68fb ldr r3, [r7, #12]
8004a7a: 681b ldr r3, [r3, #0]
8004a7c: 61fb str r3, [r7, #28]
8004a7e: 68fb ldr r3, [r7, #12]
8004a80: 681b ldr r3, [r3, #0]
8004a82: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004a86: b29b uxth r3, r3
8004a88: 461a mov r2, r3
8004a8a: 69fb ldr r3, [r7, #28]
8004a8c: 4413 add r3, r2
8004a8e: 61fb str r3, [r7, #28]
8004a90: 68bb ldr r3, [r7, #8]
8004a92: 781b ldrb r3, [r3, #0]
8004a94: 011a lsls r2, r3, #4
8004a96: 69fb ldr r3, [r7, #28]
8004a98: 4413 add r3, r2
8004a9a: f203 430c addw r3, r3, #1036 @ 0x40c
8004a9e: 61bb str r3, [r7, #24]
8004aa0: 69bb ldr r3, [r7, #24]
8004aa2: 881b ldrh r3, [r3, #0]
8004aa4: b29b uxth r3, r3
8004aa6: f3c3 0309 ubfx r3, r3, #0, #10
8004aaa: b29a uxth r2, r3
8004aac: 69bb ldr r3, [r7, #24]
8004aae: 801a strh r2, [r3, #0]
8004ab0: 69bb ldr r3, [r7, #24]
8004ab2: 881b ldrh r3, [r3, #0]
8004ab4: b29b uxth r3, r3
8004ab6: ea6f 4343 mvn.w r3, r3, lsl #17
8004aba: ea6f 4353 mvn.w r3, r3, lsr #17
8004abe: b29a uxth r2, r3
8004ac0: 69bb ldr r3, [r7, #24]
8004ac2: 801a strh r2, [r3, #0]
8004ac4: e017 b.n 8004af6 <HAL_PCD_EP_DB_Transmit+0x18a>
8004ac6: 68bb ldr r3, [r7, #8]
8004ac8: 785b ldrb r3, [r3, #1]
8004aca: 2b01 cmp r3, #1
8004acc: d113 bne.n 8004af6 <HAL_PCD_EP_DB_Transmit+0x18a>
8004ace: 68fb ldr r3, [r7, #12]
8004ad0: 681b ldr r3, [r3, #0]
8004ad2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004ad6: b29b uxth r3, r3
8004ad8: 461a mov r2, r3
8004ada: 6a7b ldr r3, [r7, #36] @ 0x24
8004adc: 4413 add r3, r2
8004ade: 627b str r3, [r7, #36] @ 0x24
8004ae0: 68bb ldr r3, [r7, #8]
8004ae2: 781b ldrb r3, [r3, #0]
8004ae4: 011a lsls r2, r3, #4
8004ae6: 6a7b ldr r3, [r7, #36] @ 0x24
8004ae8: 4413 add r3, r2
8004aea: f203 430c addw r3, r3, #1036 @ 0x40c
8004aee: 623b str r3, [r7, #32]
8004af0: 6a3b ldr r3, [r7, #32]
8004af2: 2200 movs r2, #0
8004af4: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8004af6: 68bb ldr r3, [r7, #8]
8004af8: 781b ldrb r3, [r3, #0]
8004afa: 4619 mov r1, r3
8004afc: 68f8 ldr r0, [r7, #12]
8004afe: f006 f948 bl 800ad92 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8004b02: 88fb ldrh r3, [r7, #6]
8004b04: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004b08: 2b00 cmp r3, #0
8004b0a: f000 82fc beq.w 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004b0e: 68fb ldr r3, [r7, #12]
8004b10: 681b ldr r3, [r3, #0]
8004b12: 461a mov r2, r3
8004b14: 68bb ldr r3, [r7, #8]
8004b16: 781b ldrb r3, [r3, #0]
8004b18: 009b lsls r3, r3, #2
8004b1a: 4413 add r3, r2
8004b1c: 881b ldrh r3, [r3, #0]
8004b1e: b29b uxth r3, r3
8004b20: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004b24: f023 0370 bic.w r3, r3, #112 @ 0x70
8004b28: 82fb strh r3, [r7, #22]
8004b2a: 68fb ldr r3, [r7, #12]
8004b2c: 681b ldr r3, [r3, #0]
8004b2e: 461a mov r2, r3
8004b30: 68bb ldr r3, [r7, #8]
8004b32: 781b ldrb r3, [r3, #0]
8004b34: 009b lsls r3, r3, #2
8004b36: 441a add r2, r3
8004b38: 8afb ldrh r3, [r7, #22]
8004b3a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b3e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b42: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004b46: f043 0380 orr.w r3, r3, #128 @ 0x80
8004b4a: b29b uxth r3, r3
8004b4c: 8013 strh r3, [r2, #0]
8004b4e: e2da b.n 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8004b50: 88fb ldrh r3, [r7, #6]
8004b52: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004b56: 2b00 cmp r3, #0
8004b58: d021 beq.n 8004b9e <HAL_PCD_EP_DB_Transmit+0x232>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004b5a: 68fb ldr r3, [r7, #12]
8004b5c: 681b ldr r3, [r3, #0]
8004b5e: 461a mov r2, r3
8004b60: 68bb ldr r3, [r7, #8]
8004b62: 781b ldrb r3, [r3, #0]
8004b64: 009b lsls r3, r3, #2
8004b66: 4413 add r3, r2
8004b68: 881b ldrh r3, [r3, #0]
8004b6a: b29b uxth r3, r3
8004b6c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004b70: f023 0370 bic.w r3, r3, #112 @ 0x70
8004b74: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8004b78: 68fb ldr r3, [r7, #12]
8004b7a: 681b ldr r3, [r3, #0]
8004b7c: 461a mov r2, r3
8004b7e: 68bb ldr r3, [r7, #8]
8004b80: 781b ldrb r3, [r3, #0]
8004b82: 009b lsls r3, r3, #2
8004b84: 441a add r2, r3
8004b86: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8004b8a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b8e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b92: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004b96: f043 0380 orr.w r3, r3, #128 @ 0x80
8004b9a: b29b uxth r3, r3
8004b9c: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8004b9e: 68bb ldr r3, [r7, #8]
8004ba0: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8004ba4: 2b01 cmp r3, #1
8004ba6: f040 82ae bne.w 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
8004baa: 68bb ldr r3, [r7, #8]
8004bac: 695a ldr r2, [r3, #20]
8004bae: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004bb2: 441a add r2, r3
8004bb4: 68bb ldr r3, [r7, #8]
8004bb6: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8004bb8: 68bb ldr r3, [r7, #8]
8004bba: 69da ldr r2, [r3, #28]
8004bbc: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004bc0: 441a add r2, r3
8004bc2: 68bb ldr r3, [r7, #8]
8004bc4: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8004bc6: 68bb ldr r3, [r7, #8]
8004bc8: 6a1a ldr r2, [r3, #32]
8004bca: 68bb ldr r3, [r7, #8]
8004bcc: 691b ldr r3, [r3, #16]
8004bce: 429a cmp r2, r3
8004bd0: d30b bcc.n 8004bea <HAL_PCD_EP_DB_Transmit+0x27e>
{
len = ep->maxpacket;
8004bd2: 68bb ldr r3, [r7, #8]
8004bd4: 691b ldr r3, [r3, #16]
8004bd6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8004bda: 68bb ldr r3, [r7, #8]
8004bdc: 6a1a ldr r2, [r3, #32]
8004bde: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004be2: 1ad2 subs r2, r2, r3
8004be4: 68bb ldr r3, [r7, #8]
8004be6: 621a str r2, [r3, #32]
8004be8: e017 b.n 8004c1a <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else if (ep->xfer_len_db == 0U)
8004bea: 68bb ldr r3, [r7, #8]
8004bec: 6a1b ldr r3, [r3, #32]
8004bee: 2b00 cmp r3, #0
8004bf0: d108 bne.n 8004c04 <HAL_PCD_EP_DB_Transmit+0x298>
{
len = TxPctSize;
8004bf2: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004bf6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8004bfa: 68bb ldr r3, [r7, #8]
8004bfc: 2200 movs r2, #0
8004bfe: f883 2024 strb.w r2, [r3, #36] @ 0x24
8004c02: e00a b.n 8004c1a <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else
{
ep->xfer_fill_db = 0U;
8004c04: 68bb ldr r3, [r7, #8]
8004c06: 2200 movs r2, #0
8004c08: f883 2024 strb.w r2, [r3, #36] @ 0x24
len = ep->xfer_len_db;
8004c0c: 68bb ldr r3, [r7, #8]
8004c0e: 6a1b ldr r3, [r3, #32]
8004c10: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8004c14: 68bb ldr r3, [r7, #8]
8004c16: 2200 movs r2, #0
8004c18: 621a str r2, [r3, #32]
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8004c1a: 68bb ldr r3, [r7, #8]
8004c1c: 785b ldrb r3, [r3, #1]
8004c1e: 2b00 cmp r3, #0
8004c20: d165 bne.n 8004cee <HAL_PCD_EP_DB_Transmit+0x382>
8004c22: 68fb ldr r3, [r7, #12]
8004c24: 681b ldr r3, [r3, #0]
8004c26: 63fb str r3, [r7, #60] @ 0x3c
8004c28: 68fb ldr r3, [r7, #12]
8004c2a: 681b ldr r3, [r3, #0]
8004c2c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004c30: b29b uxth r3, r3
8004c32: 461a mov r2, r3
8004c34: 6bfb ldr r3, [r7, #60] @ 0x3c
8004c36: 4413 add r3, r2
8004c38: 63fb str r3, [r7, #60] @ 0x3c
8004c3a: 68bb ldr r3, [r7, #8]
8004c3c: 781b ldrb r3, [r3, #0]
8004c3e: 011a lsls r2, r3, #4
8004c40: 6bfb ldr r3, [r7, #60] @ 0x3c
8004c42: 4413 add r3, r2
8004c44: f203 4304 addw r3, r3, #1028 @ 0x404
8004c48: 63bb str r3, [r7, #56] @ 0x38
8004c4a: 6bbb ldr r3, [r7, #56] @ 0x38
8004c4c: 881b ldrh r3, [r3, #0]
8004c4e: b29b uxth r3, r3
8004c50: f3c3 0309 ubfx r3, r3, #0, #10
8004c54: b29a uxth r2, r3
8004c56: 6bbb ldr r3, [r7, #56] @ 0x38
8004c58: 801a strh r2, [r3, #0]
8004c5a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c5e: 2b3e cmp r3, #62 @ 0x3e
8004c60: d91d bls.n 8004c9e <HAL_PCD_EP_DB_Transmit+0x332>
8004c62: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c66: 095b lsrs r3, r3, #5
8004c68: 64bb str r3, [r7, #72] @ 0x48
8004c6a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c6e: f003 031f and.w r3, r3, #31
8004c72: 2b00 cmp r3, #0
8004c74: d102 bne.n 8004c7c <HAL_PCD_EP_DB_Transmit+0x310>
8004c76: 6cbb ldr r3, [r7, #72] @ 0x48
8004c78: 3b01 subs r3, #1
8004c7a: 64bb str r3, [r7, #72] @ 0x48
8004c7c: 6bbb ldr r3, [r7, #56] @ 0x38
8004c7e: 881b ldrh r3, [r3, #0]
8004c80: b29a uxth r2, r3
8004c82: 6cbb ldr r3, [r7, #72] @ 0x48
8004c84: b29b uxth r3, r3
8004c86: 029b lsls r3, r3, #10
8004c88: b29b uxth r3, r3
8004c8a: 4313 orrs r3, r2
8004c8c: b29b uxth r3, r3
8004c8e: ea6f 4343 mvn.w r3, r3, lsl #17
8004c92: ea6f 4353 mvn.w r3, r3, lsr #17
8004c96: b29a uxth r2, r3
8004c98: 6bbb ldr r3, [r7, #56] @ 0x38
8004c9a: 801a strh r2, [r3, #0]
8004c9c: e044 b.n 8004d28 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004c9e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004ca2: 2b00 cmp r3, #0
8004ca4: d10a bne.n 8004cbc <HAL_PCD_EP_DB_Transmit+0x350>
8004ca6: 6bbb ldr r3, [r7, #56] @ 0x38
8004ca8: 881b ldrh r3, [r3, #0]
8004caa: b29b uxth r3, r3
8004cac: ea6f 4343 mvn.w r3, r3, lsl #17
8004cb0: ea6f 4353 mvn.w r3, r3, lsr #17
8004cb4: b29a uxth r2, r3
8004cb6: 6bbb ldr r3, [r7, #56] @ 0x38
8004cb8: 801a strh r2, [r3, #0]
8004cba: e035 b.n 8004d28 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004cbc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004cc0: 085b lsrs r3, r3, #1
8004cc2: 64bb str r3, [r7, #72] @ 0x48
8004cc4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004cc8: f003 0301 and.w r3, r3, #1
8004ccc: 2b00 cmp r3, #0
8004cce: d002 beq.n 8004cd6 <HAL_PCD_EP_DB_Transmit+0x36a>
8004cd0: 6cbb ldr r3, [r7, #72] @ 0x48
8004cd2: 3301 adds r3, #1
8004cd4: 64bb str r3, [r7, #72] @ 0x48
8004cd6: 6bbb ldr r3, [r7, #56] @ 0x38
8004cd8: 881b ldrh r3, [r3, #0]
8004cda: b29a uxth r2, r3
8004cdc: 6cbb ldr r3, [r7, #72] @ 0x48
8004cde: b29b uxth r3, r3
8004ce0: 029b lsls r3, r3, #10
8004ce2: b29b uxth r3, r3
8004ce4: 4313 orrs r3, r2
8004ce6: b29a uxth r2, r3
8004ce8: 6bbb ldr r3, [r7, #56] @ 0x38
8004cea: 801a strh r2, [r3, #0]
8004cec: e01c b.n 8004d28 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004cee: 68bb ldr r3, [r7, #8]
8004cf0: 785b ldrb r3, [r3, #1]
8004cf2: 2b01 cmp r3, #1
8004cf4: d118 bne.n 8004d28 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004cf6: 68fb ldr r3, [r7, #12]
8004cf8: 681b ldr r3, [r3, #0]
8004cfa: 647b str r3, [r7, #68] @ 0x44
8004cfc: 68fb ldr r3, [r7, #12]
8004cfe: 681b ldr r3, [r3, #0]
8004d00: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004d04: b29b uxth r3, r3
8004d06: 461a mov r2, r3
8004d08: 6c7b ldr r3, [r7, #68] @ 0x44
8004d0a: 4413 add r3, r2
8004d0c: 647b str r3, [r7, #68] @ 0x44
8004d0e: 68bb ldr r3, [r7, #8]
8004d10: 781b ldrb r3, [r3, #0]
8004d12: 011a lsls r2, r3, #4
8004d14: 6c7b ldr r3, [r7, #68] @ 0x44
8004d16: 4413 add r3, r2
8004d18: f203 4304 addw r3, r3, #1028 @ 0x404
8004d1c: 643b str r3, [r7, #64] @ 0x40
8004d1e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004d22: b29a uxth r2, r3
8004d24: 6c3b ldr r3, [r7, #64] @ 0x40
8004d26: 801a strh r2, [r3, #0]
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
8004d28: 68fb ldr r3, [r7, #12]
8004d2a: 6818 ldr r0, [r3, #0]
8004d2c: 68bb ldr r3, [r7, #8]
8004d2e: 6959 ldr r1, [r3, #20]
8004d30: 68bb ldr r3, [r7, #8]
8004d32: 891a ldrh r2, [r3, #8]
8004d34: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004d38: b29b uxth r3, r3
8004d3a: f004 f966 bl 800900a <USB_WritePMA>
8004d3e: e1e2 b.n 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8004d40: 68fb ldr r3, [r7, #12]
8004d42: 681b ldr r3, [r3, #0]
8004d44: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004d48: b29b uxth r3, r3
8004d4a: 461a mov r2, r3
8004d4c: 68bb ldr r3, [r7, #8]
8004d4e: 781b ldrb r3, [r3, #0]
8004d50: 00db lsls r3, r3, #3
8004d52: 4413 add r3, r2
8004d54: 3306 adds r3, #6
8004d56: 005b lsls r3, r3, #1
8004d58: 68fa ldr r2, [r7, #12]
8004d5a: 6812 ldr r2, [r2, #0]
8004d5c: 4413 add r3, r2
8004d5e: f503 6380 add.w r3, r3, #1024 @ 0x400
8004d62: 881b ldrh r3, [r3, #0]
8004d64: f3c3 0309 ubfx r3, r3, #0, #10
8004d68: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len >= TxPctSize)
8004d6c: 68bb ldr r3, [r7, #8]
8004d6e: 699a ldr r2, [r3, #24]
8004d70: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004d74: 429a cmp r2, r3
8004d76: d307 bcc.n 8004d88 <HAL_PCD_EP_DB_Transmit+0x41c>
{
ep->xfer_len -= TxPctSize;
8004d78: 68bb ldr r3, [r7, #8]
8004d7a: 699a ldr r2, [r3, #24]
8004d7c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004d80: 1ad2 subs r2, r2, r3
8004d82: 68bb ldr r3, [r7, #8]
8004d84: 619a str r2, [r3, #24]
8004d86: e002 b.n 8004d8e <HAL_PCD_EP_DB_Transmit+0x422>
}
else
{
ep->xfer_len = 0U;
8004d88: 68bb ldr r3, [r7, #8]
8004d8a: 2200 movs r2, #0
8004d8c: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8004d8e: 68bb ldr r3, [r7, #8]
8004d90: 699b ldr r3, [r3, #24]
8004d92: 2b00 cmp r3, #0
8004d94: f040 80c0 bne.w 8004f18 <HAL_PCD_EP_DB_Transmit+0x5ac>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004d98: 68bb ldr r3, [r7, #8]
8004d9a: 785b ldrb r3, [r3, #1]
8004d9c: 2b00 cmp r3, #0
8004d9e: d126 bne.n 8004dee <HAL_PCD_EP_DB_Transmit+0x482>
8004da0: 68fb ldr r3, [r7, #12]
8004da2: 681b ldr r3, [r3, #0]
8004da4: 67fb str r3, [r7, #124] @ 0x7c
8004da6: 68fb ldr r3, [r7, #12]
8004da8: 681b ldr r3, [r3, #0]
8004daa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004dae: b29b uxth r3, r3
8004db0: 461a mov r2, r3
8004db2: 6ffb ldr r3, [r7, #124] @ 0x7c
8004db4: 4413 add r3, r2
8004db6: 67fb str r3, [r7, #124] @ 0x7c
8004db8: 68bb ldr r3, [r7, #8]
8004dba: 781b ldrb r3, [r3, #0]
8004dbc: 011a lsls r2, r3, #4
8004dbe: 6ffb ldr r3, [r7, #124] @ 0x7c
8004dc0: 4413 add r3, r2
8004dc2: f203 4304 addw r3, r3, #1028 @ 0x404
8004dc6: 67bb str r3, [r7, #120] @ 0x78
8004dc8: 6fbb ldr r3, [r7, #120] @ 0x78
8004dca: 881b ldrh r3, [r3, #0]
8004dcc: b29b uxth r3, r3
8004dce: f3c3 0309 ubfx r3, r3, #0, #10
8004dd2: b29a uxth r2, r3
8004dd4: 6fbb ldr r3, [r7, #120] @ 0x78
8004dd6: 801a strh r2, [r3, #0]
8004dd8: 6fbb ldr r3, [r7, #120] @ 0x78
8004dda: 881b ldrh r3, [r3, #0]
8004ddc: b29b uxth r3, r3
8004dde: ea6f 4343 mvn.w r3, r3, lsl #17
8004de2: ea6f 4353 mvn.w r3, r3, lsr #17
8004de6: b29a uxth r2, r3
8004de8: 6fbb ldr r3, [r7, #120] @ 0x78
8004dea: 801a strh r2, [r3, #0]
8004dec: e01a b.n 8004e24 <HAL_PCD_EP_DB_Transmit+0x4b8>
8004dee: 68bb ldr r3, [r7, #8]
8004df0: 785b ldrb r3, [r3, #1]
8004df2: 2b01 cmp r3, #1
8004df4: d116 bne.n 8004e24 <HAL_PCD_EP_DB_Transmit+0x4b8>
8004df6: 68fb ldr r3, [r7, #12]
8004df8: 681b ldr r3, [r3, #0]
8004dfa: 667b str r3, [r7, #100] @ 0x64
8004dfc: 68fb ldr r3, [r7, #12]
8004dfe: 681b ldr r3, [r3, #0]
8004e00: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e04: b29b uxth r3, r3
8004e06: 461a mov r2, r3
8004e08: 6e7b ldr r3, [r7, #100] @ 0x64
8004e0a: 4413 add r3, r2
8004e0c: 667b str r3, [r7, #100] @ 0x64
8004e0e: 68bb ldr r3, [r7, #8]
8004e10: 781b ldrb r3, [r3, #0]
8004e12: 011a lsls r2, r3, #4
8004e14: 6e7b ldr r3, [r7, #100] @ 0x64
8004e16: 4413 add r3, r2
8004e18: f203 4304 addw r3, r3, #1028 @ 0x404
8004e1c: 663b str r3, [r7, #96] @ 0x60
8004e1e: 6e3b ldr r3, [r7, #96] @ 0x60
8004e20: 2200 movs r2, #0
8004e22: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004e24: 68fb ldr r3, [r7, #12]
8004e26: 681b ldr r3, [r3, #0]
8004e28: 677b str r3, [r7, #116] @ 0x74
8004e2a: 68bb ldr r3, [r7, #8]
8004e2c: 785b ldrb r3, [r3, #1]
8004e2e: 2b00 cmp r3, #0
8004e30: d12b bne.n 8004e8a <HAL_PCD_EP_DB_Transmit+0x51e>
8004e32: 68fb ldr r3, [r7, #12]
8004e34: 681b ldr r3, [r3, #0]
8004e36: 66fb str r3, [r7, #108] @ 0x6c
8004e38: 68fb ldr r3, [r7, #12]
8004e3a: 681b ldr r3, [r3, #0]
8004e3c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e40: b29b uxth r3, r3
8004e42: 461a mov r2, r3
8004e44: 6efb ldr r3, [r7, #108] @ 0x6c
8004e46: 4413 add r3, r2
8004e48: 66fb str r3, [r7, #108] @ 0x6c
8004e4a: 68bb ldr r3, [r7, #8]
8004e4c: 781b ldrb r3, [r3, #0]
8004e4e: 011a lsls r2, r3, #4
8004e50: 6efb ldr r3, [r7, #108] @ 0x6c
8004e52: 4413 add r3, r2
8004e54: f203 430c addw r3, r3, #1036 @ 0x40c
8004e58: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8004e5c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e60: 881b ldrh r3, [r3, #0]
8004e62: b29b uxth r3, r3
8004e64: f3c3 0309 ubfx r3, r3, #0, #10
8004e68: b29a uxth r2, r3
8004e6a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e6e: 801a strh r2, [r3, #0]
8004e70: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e74: 881b ldrh r3, [r3, #0]
8004e76: b29b uxth r3, r3
8004e78: ea6f 4343 mvn.w r3, r3, lsl #17
8004e7c: ea6f 4353 mvn.w r3, r3, lsr #17
8004e80: b29a uxth r2, r3
8004e82: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e86: 801a strh r2, [r3, #0]
8004e88: e017 b.n 8004eba <HAL_PCD_EP_DB_Transmit+0x54e>
8004e8a: 68bb ldr r3, [r7, #8]
8004e8c: 785b ldrb r3, [r3, #1]
8004e8e: 2b01 cmp r3, #1
8004e90: d113 bne.n 8004eba <HAL_PCD_EP_DB_Transmit+0x54e>
8004e92: 68fb ldr r3, [r7, #12]
8004e94: 681b ldr r3, [r3, #0]
8004e96: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e9a: b29b uxth r3, r3
8004e9c: 461a mov r2, r3
8004e9e: 6f7b ldr r3, [r7, #116] @ 0x74
8004ea0: 4413 add r3, r2
8004ea2: 677b str r3, [r7, #116] @ 0x74
8004ea4: 68bb ldr r3, [r7, #8]
8004ea6: 781b ldrb r3, [r3, #0]
8004ea8: 011a lsls r2, r3, #4
8004eaa: 6f7b ldr r3, [r7, #116] @ 0x74
8004eac: 4413 add r3, r2
8004eae: f203 430c addw r3, r3, #1036 @ 0x40c
8004eb2: 673b str r3, [r7, #112] @ 0x70
8004eb4: 6f3b ldr r3, [r7, #112] @ 0x70
8004eb6: 2200 movs r2, #0
8004eb8: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8004eba: 68bb ldr r3, [r7, #8]
8004ebc: 781b ldrb r3, [r3, #0]
8004ebe: 4619 mov r1, r3
8004ec0: 68f8 ldr r0, [r7, #12]
8004ec2: f005 ff66 bl 800ad92 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8004ec6: 88fb ldrh r3, [r7, #6]
8004ec8: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004ecc: 2b00 cmp r3, #0
8004ece: f040 811a bne.w 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004ed2: 68fb ldr r3, [r7, #12]
8004ed4: 681b ldr r3, [r3, #0]
8004ed6: 461a mov r2, r3
8004ed8: 68bb ldr r3, [r7, #8]
8004eda: 781b ldrb r3, [r3, #0]
8004edc: 009b lsls r3, r3, #2
8004ede: 4413 add r3, r2
8004ee0: 881b ldrh r3, [r3, #0]
8004ee2: b29b uxth r3, r3
8004ee4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004ee8: f023 0370 bic.w r3, r3, #112 @ 0x70
8004eec: f8a7 3088 strh.w r3, [r7, #136] @ 0x88
8004ef0: 68fb ldr r3, [r7, #12]
8004ef2: 681b ldr r3, [r3, #0]
8004ef4: 461a mov r2, r3
8004ef6: 68bb ldr r3, [r7, #8]
8004ef8: 781b ldrb r3, [r3, #0]
8004efa: 009b lsls r3, r3, #2
8004efc: 441a add r2, r3
8004efe: f8b7 3088 ldrh.w r3, [r7, #136] @ 0x88
8004f02: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004f06: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004f0a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004f0e: f043 0380 orr.w r3, r3, #128 @ 0x80
8004f12: b29b uxth r3, r3
8004f14: 8013 strh r3, [r2, #0]
8004f16: e0f6 b.n 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8004f18: 88fb ldrh r3, [r7, #6]
8004f1a: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004f1e: 2b00 cmp r3, #0
8004f20: d121 bne.n 8004f66 <HAL_PCD_EP_DB_Transmit+0x5fa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004f22: 68fb ldr r3, [r7, #12]
8004f24: 681b ldr r3, [r3, #0]
8004f26: 461a mov r2, r3
8004f28: 68bb ldr r3, [r7, #8]
8004f2a: 781b ldrb r3, [r3, #0]
8004f2c: 009b lsls r3, r3, #2
8004f2e: 4413 add r3, r2
8004f30: 881b ldrh r3, [r3, #0]
8004f32: b29b uxth r3, r3
8004f34: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004f38: f023 0370 bic.w r3, r3, #112 @ 0x70
8004f3c: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
8004f40: 68fb ldr r3, [r7, #12]
8004f42: 681b ldr r3, [r3, #0]
8004f44: 461a mov r2, r3
8004f46: 68bb ldr r3, [r7, #8]
8004f48: 781b ldrb r3, [r3, #0]
8004f4a: 009b lsls r3, r3, #2
8004f4c: 441a add r2, r3
8004f4e: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8004f52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004f56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004f5a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004f5e: f043 0380 orr.w r3, r3, #128 @ 0x80
8004f62: b29b uxth r3, r3
8004f64: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8004f66: 68bb ldr r3, [r7, #8]
8004f68: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8004f6c: 2b01 cmp r3, #1
8004f6e: f040 80ca bne.w 8005106 <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
8004f72: 68bb ldr r3, [r7, #8]
8004f74: 695a ldr r2, [r3, #20]
8004f76: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004f7a: 441a add r2, r3
8004f7c: 68bb ldr r3, [r7, #8]
8004f7e: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8004f80: 68bb ldr r3, [r7, #8]
8004f82: 69da ldr r2, [r3, #28]
8004f84: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004f88: 441a add r2, r3
8004f8a: 68bb ldr r3, [r7, #8]
8004f8c: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8004f8e: 68bb ldr r3, [r7, #8]
8004f90: 6a1a ldr r2, [r3, #32]
8004f92: 68bb ldr r3, [r7, #8]
8004f94: 691b ldr r3, [r3, #16]
8004f96: 429a cmp r2, r3
8004f98: d30b bcc.n 8004fb2 <HAL_PCD_EP_DB_Transmit+0x646>
{
len = ep->maxpacket;
8004f9a: 68bb ldr r3, [r7, #8]
8004f9c: 691b ldr r3, [r3, #16]
8004f9e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8004fa2: 68bb ldr r3, [r7, #8]
8004fa4: 6a1a ldr r2, [r3, #32]
8004fa6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004faa: 1ad2 subs r2, r2, r3
8004fac: 68bb ldr r3, [r7, #8]
8004fae: 621a str r2, [r3, #32]
8004fb0: e017 b.n 8004fe2 <HAL_PCD_EP_DB_Transmit+0x676>
}
else if (ep->xfer_len_db == 0U)
8004fb2: 68bb ldr r3, [r7, #8]
8004fb4: 6a1b ldr r3, [r3, #32]
8004fb6: 2b00 cmp r3, #0
8004fb8: d108 bne.n 8004fcc <HAL_PCD_EP_DB_Transmit+0x660>
{
len = TxPctSize;
8004fba: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004fbe: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8004fc2: 68bb ldr r3, [r7, #8]
8004fc4: 2200 movs r2, #0
8004fc6: f883 2024 strb.w r2, [r3, #36] @ 0x24
8004fca: e00a b.n 8004fe2 <HAL_PCD_EP_DB_Transmit+0x676>
}
else
{
len = ep->xfer_len_db;
8004fcc: 68bb ldr r3, [r7, #8]
8004fce: 6a1b ldr r3, [r3, #32]
8004fd0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8004fd4: 68bb ldr r3, [r7, #8]
8004fd6: 2200 movs r2, #0
8004fd8: 621a str r2, [r3, #32]
ep->xfer_fill_db = 0;
8004fda: 68bb ldr r3, [r7, #8]
8004fdc: 2200 movs r2, #0
8004fde: f883 2024 strb.w r2, [r3, #36] @ 0x24
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8004fe2: 68fb ldr r3, [r7, #12]
8004fe4: 681b ldr r3, [r3, #0]
8004fe6: 657b str r3, [r7, #84] @ 0x54
8004fe8: 68bb ldr r3, [r7, #8]
8004fea: 785b ldrb r3, [r3, #1]
8004fec: 2b00 cmp r3, #0
8004fee: d165 bne.n 80050bc <HAL_PCD_EP_DB_Transmit+0x750>
8004ff0: 68fb ldr r3, [r7, #12]
8004ff2: 681b ldr r3, [r3, #0]
8004ff4: 65fb str r3, [r7, #92] @ 0x5c
8004ff6: 68fb ldr r3, [r7, #12]
8004ff8: 681b ldr r3, [r3, #0]
8004ffa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004ffe: b29b uxth r3, r3
8005000: 461a mov r2, r3
8005002: 6dfb ldr r3, [r7, #92] @ 0x5c
8005004: 4413 add r3, r2
8005006: 65fb str r3, [r7, #92] @ 0x5c
8005008: 68bb ldr r3, [r7, #8]
800500a: 781b ldrb r3, [r3, #0]
800500c: 011a lsls r2, r3, #4
800500e: 6dfb ldr r3, [r7, #92] @ 0x5c
8005010: 4413 add r3, r2
8005012: f203 430c addw r3, r3, #1036 @ 0x40c
8005016: 65bb str r3, [r7, #88] @ 0x58
8005018: 6dbb ldr r3, [r7, #88] @ 0x58
800501a: 881b ldrh r3, [r3, #0]
800501c: b29b uxth r3, r3
800501e: f3c3 0309 ubfx r3, r3, #0, #10
8005022: b29a uxth r2, r3
8005024: 6dbb ldr r3, [r7, #88] @ 0x58
8005026: 801a strh r2, [r3, #0]
8005028: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800502c: 2b3e cmp r3, #62 @ 0x3e
800502e: d91d bls.n 800506c <HAL_PCD_EP_DB_Transmit+0x700>
8005030: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005034: 095b lsrs r3, r3, #5
8005036: 66bb str r3, [r7, #104] @ 0x68
8005038: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800503c: f003 031f and.w r3, r3, #31
8005040: 2b00 cmp r3, #0
8005042: d102 bne.n 800504a <HAL_PCD_EP_DB_Transmit+0x6de>
8005044: 6ebb ldr r3, [r7, #104] @ 0x68
8005046: 3b01 subs r3, #1
8005048: 66bb str r3, [r7, #104] @ 0x68
800504a: 6dbb ldr r3, [r7, #88] @ 0x58
800504c: 881b ldrh r3, [r3, #0]
800504e: b29a uxth r2, r3
8005050: 6ebb ldr r3, [r7, #104] @ 0x68
8005052: b29b uxth r3, r3
8005054: 029b lsls r3, r3, #10
8005056: b29b uxth r3, r3
8005058: 4313 orrs r3, r2
800505a: b29b uxth r3, r3
800505c: ea6f 4343 mvn.w r3, r3, lsl #17
8005060: ea6f 4353 mvn.w r3, r3, lsr #17
8005064: b29a uxth r2, r3
8005066: 6dbb ldr r3, [r7, #88] @ 0x58
8005068: 801a strh r2, [r3, #0]
800506a: e041 b.n 80050f0 <HAL_PCD_EP_DB_Transmit+0x784>
800506c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005070: 2b00 cmp r3, #0
8005072: d10a bne.n 800508a <HAL_PCD_EP_DB_Transmit+0x71e>
8005074: 6dbb ldr r3, [r7, #88] @ 0x58
8005076: 881b ldrh r3, [r3, #0]
8005078: b29b uxth r3, r3
800507a: ea6f 4343 mvn.w r3, r3, lsl #17
800507e: ea6f 4353 mvn.w r3, r3, lsr #17
8005082: b29a uxth r2, r3
8005084: 6dbb ldr r3, [r7, #88] @ 0x58
8005086: 801a strh r2, [r3, #0]
8005088: e032 b.n 80050f0 <HAL_PCD_EP_DB_Transmit+0x784>
800508a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800508e: 085b lsrs r3, r3, #1
8005090: 66bb str r3, [r7, #104] @ 0x68
8005092: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005096: f003 0301 and.w r3, r3, #1
800509a: 2b00 cmp r3, #0
800509c: d002 beq.n 80050a4 <HAL_PCD_EP_DB_Transmit+0x738>
800509e: 6ebb ldr r3, [r7, #104] @ 0x68
80050a0: 3301 adds r3, #1
80050a2: 66bb str r3, [r7, #104] @ 0x68
80050a4: 6dbb ldr r3, [r7, #88] @ 0x58
80050a6: 881b ldrh r3, [r3, #0]
80050a8: b29a uxth r2, r3
80050aa: 6ebb ldr r3, [r7, #104] @ 0x68
80050ac: b29b uxth r3, r3
80050ae: 029b lsls r3, r3, #10
80050b0: b29b uxth r3, r3
80050b2: 4313 orrs r3, r2
80050b4: b29a uxth r2, r3
80050b6: 6dbb ldr r3, [r7, #88] @ 0x58
80050b8: 801a strh r2, [r3, #0]
80050ba: e019 b.n 80050f0 <HAL_PCD_EP_DB_Transmit+0x784>
80050bc: 68bb ldr r3, [r7, #8]
80050be: 785b ldrb r3, [r3, #1]
80050c0: 2b01 cmp r3, #1
80050c2: d115 bne.n 80050f0 <HAL_PCD_EP_DB_Transmit+0x784>
80050c4: 68fb ldr r3, [r7, #12]
80050c6: 681b ldr r3, [r3, #0]
80050c8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80050cc: b29b uxth r3, r3
80050ce: 461a mov r2, r3
80050d0: 6d7b ldr r3, [r7, #84] @ 0x54
80050d2: 4413 add r3, r2
80050d4: 657b str r3, [r7, #84] @ 0x54
80050d6: 68bb ldr r3, [r7, #8]
80050d8: 781b ldrb r3, [r3, #0]
80050da: 011a lsls r2, r3, #4
80050dc: 6d7b ldr r3, [r7, #84] @ 0x54
80050de: 4413 add r3, r2
80050e0: f203 430c addw r3, r3, #1036 @ 0x40c
80050e4: 653b str r3, [r7, #80] @ 0x50
80050e6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80050ea: b29a uxth r2, r3
80050ec: 6d3b ldr r3, [r7, #80] @ 0x50
80050ee: 801a strh r2, [r3, #0]
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
80050f0: 68fb ldr r3, [r7, #12]
80050f2: 6818 ldr r0, [r3, #0]
80050f4: 68bb ldr r3, [r7, #8]
80050f6: 6959 ldr r1, [r3, #20]
80050f8: 68bb ldr r3, [r7, #8]
80050fa: 895a ldrh r2, [r3, #10]
80050fc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005100: b29b uxth r3, r3
8005102: f003 ff82 bl 800900a <USB_WritePMA>
}
}
}
/*enable endpoint IN*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
8005106: 68fb ldr r3, [r7, #12]
8005108: 681b ldr r3, [r3, #0]
800510a: 461a mov r2, r3
800510c: 68bb ldr r3, [r7, #8]
800510e: 781b ldrb r3, [r3, #0]
8005110: 009b lsls r3, r3, #2
8005112: 4413 add r3, r2
8005114: 881b ldrh r3, [r3, #0]
8005116: b29b uxth r3, r3
8005118: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800511c: f023 0340 bic.w r3, r3, #64 @ 0x40
8005120: 82bb strh r3, [r7, #20]
8005122: 8abb ldrh r3, [r7, #20]
8005124: f083 0310 eor.w r3, r3, #16
8005128: 82bb strh r3, [r7, #20]
800512a: 8abb ldrh r3, [r7, #20]
800512c: f083 0320 eor.w r3, r3, #32
8005130: 82bb strh r3, [r7, #20]
8005132: 68fb ldr r3, [r7, #12]
8005134: 681b ldr r3, [r3, #0]
8005136: 461a mov r2, r3
8005138: 68bb ldr r3, [r7, #8]
800513a: 781b ldrb r3, [r3, #0]
800513c: 009b lsls r3, r3, #2
800513e: 441a add r2, r3
8005140: 8abb ldrh r3, [r7, #20]
8005142: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005146: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800514a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800514e: f043 0380 orr.w r3, r3, #128 @ 0x80
8005152: b29b uxth r3, r3
8005154: 8013 strh r3, [r2, #0]
return HAL_OK;
8005156: 2300 movs r3, #0
}
8005158: 4618 mov r0, r3
800515a: 3790 adds r7, #144 @ 0x90
800515c: 46bd mov sp, r7
800515e: bd80 pop {r7, pc}
08005160 <HAL_PCDEx_PMAConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
8005160: b480 push {r7}
8005162: b087 sub sp, #28
8005164: af00 add r7, sp, #0
8005166: 60f8 str r0, [r7, #12]
8005168: 607b str r3, [r7, #4]
800516a: 460b mov r3, r1
800516c: 817b strh r3, [r7, #10]
800516e: 4613 mov r3, r2
8005170: 813b strh r3, [r7, #8]
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
8005172: 897b ldrh r3, [r7, #10]
8005174: f003 0380 and.w r3, r3, #128 @ 0x80
8005178: b29b uxth r3, r3
800517a: 2b00 cmp r3, #0
800517c: d00b beq.n 8005196 <HAL_PCDEx_PMAConfig+0x36>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800517e: 897b ldrh r3, [r7, #10]
8005180: f003 0207 and.w r2, r3, #7
8005184: 4613 mov r3, r2
8005186: 009b lsls r3, r3, #2
8005188: 4413 add r3, r2
800518a: 00db lsls r3, r3, #3
800518c: 3310 adds r3, #16
800518e: 68fa ldr r2, [r7, #12]
8005190: 4413 add r3, r2
8005192: 617b str r3, [r7, #20]
8005194: e009 b.n 80051aa <HAL_PCDEx_PMAConfig+0x4a>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8005196: 897a ldrh r2, [r7, #10]
8005198: 4613 mov r3, r2
800519a: 009b lsls r3, r3, #2
800519c: 4413 add r3, r2
800519e: 00db lsls r3, r3, #3
80051a0: f503 73a8 add.w r3, r3, #336 @ 0x150
80051a4: 68fa ldr r2, [r7, #12]
80051a6: 4413 add r3, r2
80051a8: 617b str r3, [r7, #20]
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
80051aa: 893b ldrh r3, [r7, #8]
80051ac: 2b00 cmp r3, #0
80051ae: d107 bne.n 80051c0 <HAL_PCDEx_PMAConfig+0x60>
{
/* Single Buffer */
ep->doublebuffer = 0U;
80051b0: 697b ldr r3, [r7, #20]
80051b2: 2200 movs r2, #0
80051b4: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
80051b6: 687b ldr r3, [r7, #4]
80051b8: b29a uxth r2, r3
80051ba: 697b ldr r3, [r7, #20]
80051bc: 80da strh r2, [r3, #6]
80051be: e00b b.n 80051d8 <HAL_PCDEx_PMAConfig+0x78>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
80051c0: 697b ldr r3, [r7, #20]
80051c2: 2201 movs r2, #1
80051c4: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
80051c6: 687b ldr r3, [r7, #4]
80051c8: b29a uxth r2, r3
80051ca: 697b ldr r3, [r7, #20]
80051cc: 811a strh r2, [r3, #8]
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
80051ce: 687b ldr r3, [r7, #4]
80051d0: 0c1b lsrs r3, r3, #16
80051d2: b29a uxth r2, r3
80051d4: 697b ldr r3, [r7, #20]
80051d6: 815a strh r2, [r3, #10]
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
80051d8: 2300 movs r3, #0
}
80051da: 4618 mov r0, r3
80051dc: 371c adds r7, #28
80051de: 46bd mov sp, r7
80051e0: bc80 pop {r7}
80051e2: 4770 bx lr
080051e4 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80051e4: b580 push {r7, lr}
80051e6: b086 sub sp, #24
80051e8: af00 add r7, sp, #0
80051ea: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80051ec: 687b ldr r3, [r7, #4]
80051ee: 2b00 cmp r3, #0
80051f0: d101 bne.n 80051f6 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80051f2: 2301 movs r3, #1
80051f4: e272 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80051f6: 687b ldr r3, [r7, #4]
80051f8: 681b ldr r3, [r3, #0]
80051fa: f003 0301 and.w r3, r3, #1
80051fe: 2b00 cmp r3, #0
8005200: f000 8087 beq.w 8005312 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8005204: 4b92 ldr r3, [pc, #584] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005206: 685b ldr r3, [r3, #4]
8005208: f003 030c and.w r3, r3, #12
800520c: 2b04 cmp r3, #4
800520e: d00c beq.n 800522a <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8005210: 4b8f ldr r3, [pc, #572] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005212: 685b ldr r3, [r3, #4]
8005214: f003 030c and.w r3, r3, #12
8005218: 2b08 cmp r3, #8
800521a: d112 bne.n 8005242 <HAL_RCC_OscConfig+0x5e>
800521c: 4b8c ldr r3, [pc, #560] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800521e: 685b ldr r3, [r3, #4]
8005220: f403 3380 and.w r3, r3, #65536 @ 0x10000
8005224: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8005228: d10b bne.n 8005242 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800522a: 4b89 ldr r3, [pc, #548] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800522c: 681b ldr r3, [r3, #0]
800522e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005232: 2b00 cmp r3, #0
8005234: d06c beq.n 8005310 <HAL_RCC_OscConfig+0x12c>
8005236: 687b ldr r3, [r7, #4]
8005238: 685b ldr r3, [r3, #4]
800523a: 2b00 cmp r3, #0
800523c: d168 bne.n 8005310 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
800523e: 2301 movs r3, #1
8005240: e24c b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8005242: 687b ldr r3, [r7, #4]
8005244: 685b ldr r3, [r3, #4]
8005246: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800524a: d106 bne.n 800525a <HAL_RCC_OscConfig+0x76>
800524c: 4b80 ldr r3, [pc, #512] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800524e: 681b ldr r3, [r3, #0]
8005250: 4a7f ldr r2, [pc, #508] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005252: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8005256: 6013 str r3, [r2, #0]
8005258: e02e b.n 80052b8 <HAL_RCC_OscConfig+0xd4>
800525a: 687b ldr r3, [r7, #4]
800525c: 685b ldr r3, [r3, #4]
800525e: 2b00 cmp r3, #0
8005260: d10c bne.n 800527c <HAL_RCC_OscConfig+0x98>
8005262: 4b7b ldr r3, [pc, #492] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005264: 681b ldr r3, [r3, #0]
8005266: 4a7a ldr r2, [pc, #488] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005268: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800526c: 6013 str r3, [r2, #0]
800526e: 4b78 ldr r3, [pc, #480] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005270: 681b ldr r3, [r3, #0]
8005272: 4a77 ldr r2, [pc, #476] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005274: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005278: 6013 str r3, [r2, #0]
800527a: e01d b.n 80052b8 <HAL_RCC_OscConfig+0xd4>
800527c: 687b ldr r3, [r7, #4]
800527e: 685b ldr r3, [r3, #4]
8005280: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8005284: d10c bne.n 80052a0 <HAL_RCC_OscConfig+0xbc>
8005286: 4b72 ldr r3, [pc, #456] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005288: 681b ldr r3, [r3, #0]
800528a: 4a71 ldr r2, [pc, #452] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800528c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8005290: 6013 str r3, [r2, #0]
8005292: 4b6f ldr r3, [pc, #444] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005294: 681b ldr r3, [r3, #0]
8005296: 4a6e ldr r2, [pc, #440] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005298: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800529c: 6013 str r3, [r2, #0]
800529e: e00b b.n 80052b8 <HAL_RCC_OscConfig+0xd4>
80052a0: 4b6b ldr r3, [pc, #428] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80052a2: 681b ldr r3, [r3, #0]
80052a4: 4a6a ldr r2, [pc, #424] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80052a6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80052aa: 6013 str r3, [r2, #0]
80052ac: 4b68 ldr r3, [pc, #416] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80052ae: 681b ldr r3, [r3, #0]
80052b0: 4a67 ldr r2, [pc, #412] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80052b2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80052b6: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80052b8: 687b ldr r3, [r7, #4]
80052ba: 685b ldr r3, [r3, #4]
80052bc: 2b00 cmp r3, #0
80052be: d013 beq.n 80052e8 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80052c0: f7fc ff8c bl 80021dc <HAL_GetTick>
80052c4: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80052c6: e008 b.n 80052da <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80052c8: f7fc ff88 bl 80021dc <HAL_GetTick>
80052cc: 4602 mov r2, r0
80052ce: 693b ldr r3, [r7, #16]
80052d0: 1ad3 subs r3, r2, r3
80052d2: 2b64 cmp r3, #100 @ 0x64
80052d4: d901 bls.n 80052da <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
80052d6: 2303 movs r3, #3
80052d8: e200 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80052da: 4b5d ldr r3, [pc, #372] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80052dc: 681b ldr r3, [r3, #0]
80052de: f403 3300 and.w r3, r3, #131072 @ 0x20000
80052e2: 2b00 cmp r3, #0
80052e4: d0f0 beq.n 80052c8 <HAL_RCC_OscConfig+0xe4>
80052e6: e014 b.n 8005312 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80052e8: f7fc ff78 bl 80021dc <HAL_GetTick>
80052ec: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80052ee: e008 b.n 8005302 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80052f0: f7fc ff74 bl 80021dc <HAL_GetTick>
80052f4: 4602 mov r2, r0
80052f6: 693b ldr r3, [r7, #16]
80052f8: 1ad3 subs r3, r2, r3
80052fa: 2b64 cmp r3, #100 @ 0x64
80052fc: d901 bls.n 8005302 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
80052fe: 2303 movs r3, #3
8005300: e1ec b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8005302: 4b53 ldr r3, [pc, #332] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005304: 681b ldr r3, [r3, #0]
8005306: f403 3300 and.w r3, r3, #131072 @ 0x20000
800530a: 2b00 cmp r3, #0
800530c: d1f0 bne.n 80052f0 <HAL_RCC_OscConfig+0x10c>
800530e: e000 b.n 8005312 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8005310: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8005312: 687b ldr r3, [r7, #4]
8005314: 681b ldr r3, [r3, #0]
8005316: f003 0302 and.w r3, r3, #2
800531a: 2b00 cmp r3, #0
800531c: d063 beq.n 80053e6 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800531e: 4b4c ldr r3, [pc, #304] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005320: 685b ldr r3, [r3, #4]
8005322: f003 030c and.w r3, r3, #12
8005326: 2b00 cmp r3, #0
8005328: d00b beq.n 8005342 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
800532a: 4b49 ldr r3, [pc, #292] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800532c: 685b ldr r3, [r3, #4]
800532e: f003 030c and.w r3, r3, #12
8005332: 2b08 cmp r3, #8
8005334: d11c bne.n 8005370 <HAL_RCC_OscConfig+0x18c>
8005336: 4b46 ldr r3, [pc, #280] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005338: 685b ldr r3, [r3, #4]
800533a: f403 3380 and.w r3, r3, #65536 @ 0x10000
800533e: 2b00 cmp r3, #0
8005340: d116 bne.n 8005370 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8005342: 4b43 ldr r3, [pc, #268] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
8005344: 681b ldr r3, [r3, #0]
8005346: f003 0302 and.w r3, r3, #2
800534a: 2b00 cmp r3, #0
800534c: d005 beq.n 800535a <HAL_RCC_OscConfig+0x176>
800534e: 687b ldr r3, [r7, #4]
8005350: 691b ldr r3, [r3, #16]
8005352: 2b01 cmp r3, #1
8005354: d001 beq.n 800535a <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8005356: 2301 movs r3, #1
8005358: e1c0 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800535a: 4b3d ldr r3, [pc, #244] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800535c: 681b ldr r3, [r3, #0]
800535e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8005362: 687b ldr r3, [r7, #4]
8005364: 695b ldr r3, [r3, #20]
8005366: 00db lsls r3, r3, #3
8005368: 4939 ldr r1, [pc, #228] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800536a: 4313 orrs r3, r2
800536c: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800536e: e03a b.n 80053e6 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8005370: 687b ldr r3, [r7, #4]
8005372: 691b ldr r3, [r3, #16]
8005374: 2b00 cmp r3, #0
8005376: d020 beq.n 80053ba <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8005378: 4b36 ldr r3, [pc, #216] @ (8005454 <HAL_RCC_OscConfig+0x270>)
800537a: 2201 movs r2, #1
800537c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800537e: f7fc ff2d bl 80021dc <HAL_GetTick>
8005382: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005384: e008 b.n 8005398 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8005386: f7fc ff29 bl 80021dc <HAL_GetTick>
800538a: 4602 mov r2, r0
800538c: 693b ldr r3, [r7, #16]
800538e: 1ad3 subs r3, r2, r3
8005390: 2b02 cmp r3, #2
8005392: d901 bls.n 8005398 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8005394: 2303 movs r3, #3
8005396: e1a1 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005398: 4b2d ldr r3, [pc, #180] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800539a: 681b ldr r3, [r3, #0]
800539c: f003 0302 and.w r3, r3, #2
80053a0: 2b00 cmp r3, #0
80053a2: d0f0 beq.n 8005386 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80053a4: 4b2a ldr r3, [pc, #168] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80053a6: 681b ldr r3, [r3, #0]
80053a8: f023 02f8 bic.w r2, r3, #248 @ 0xf8
80053ac: 687b ldr r3, [r7, #4]
80053ae: 695b ldr r3, [r3, #20]
80053b0: 00db lsls r3, r3, #3
80053b2: 4927 ldr r1, [pc, #156] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80053b4: 4313 orrs r3, r2
80053b6: 600b str r3, [r1, #0]
80053b8: e015 b.n 80053e6 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80053ba: 4b26 ldr r3, [pc, #152] @ (8005454 <HAL_RCC_OscConfig+0x270>)
80053bc: 2200 movs r2, #0
80053be: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80053c0: f7fc ff0c bl 80021dc <HAL_GetTick>
80053c4: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80053c6: e008 b.n 80053da <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80053c8: f7fc ff08 bl 80021dc <HAL_GetTick>
80053cc: 4602 mov r2, r0
80053ce: 693b ldr r3, [r7, #16]
80053d0: 1ad3 subs r3, r2, r3
80053d2: 2b02 cmp r3, #2
80053d4: d901 bls.n 80053da <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
80053d6: 2303 movs r3, #3
80053d8: e180 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80053da: 4b1d ldr r3, [pc, #116] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
80053dc: 681b ldr r3, [r3, #0]
80053de: f003 0302 and.w r3, r3, #2
80053e2: 2b00 cmp r3, #0
80053e4: d1f0 bne.n 80053c8 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80053e6: 687b ldr r3, [r7, #4]
80053e8: 681b ldr r3, [r3, #0]
80053ea: f003 0308 and.w r3, r3, #8
80053ee: 2b00 cmp r3, #0
80053f0: d03a beq.n 8005468 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80053f2: 687b ldr r3, [r7, #4]
80053f4: 699b ldr r3, [r3, #24]
80053f6: 2b00 cmp r3, #0
80053f8: d019 beq.n 800542e <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80053fa: 4b17 ldr r3, [pc, #92] @ (8005458 <HAL_RCC_OscConfig+0x274>)
80053fc: 2201 movs r2, #1
80053fe: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005400: f7fc feec bl 80021dc <HAL_GetTick>
8005404: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8005406: e008 b.n 800541a <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8005408: f7fc fee8 bl 80021dc <HAL_GetTick>
800540c: 4602 mov r2, r0
800540e: 693b ldr r3, [r7, #16]
8005410: 1ad3 subs r3, r2, r3
8005412: 2b02 cmp r3, #2
8005414: d901 bls.n 800541a <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8005416: 2303 movs r3, #3
8005418: e160 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800541a: 4b0d ldr r3, [pc, #52] @ (8005450 <HAL_RCC_OscConfig+0x26c>)
800541c: 6a5b ldr r3, [r3, #36] @ 0x24
800541e: f003 0302 and.w r3, r3, #2
8005422: 2b00 cmp r3, #0
8005424: d0f0 beq.n 8005408 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8005426: 2001 movs r0, #1
8005428: f000 face bl 80059c8 <RCC_Delay>
800542c: e01c b.n 8005468 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800542e: 4b0a ldr r3, [pc, #40] @ (8005458 <HAL_RCC_OscConfig+0x274>)
8005430: 2200 movs r2, #0
8005432: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005434: f7fc fed2 bl 80021dc <HAL_GetTick>
8005438: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800543a: e00f b.n 800545c <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800543c: f7fc fece bl 80021dc <HAL_GetTick>
8005440: 4602 mov r2, r0
8005442: 693b ldr r3, [r7, #16]
8005444: 1ad3 subs r3, r2, r3
8005446: 2b02 cmp r3, #2
8005448: d908 bls.n 800545c <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
800544a: 2303 movs r3, #3
800544c: e146 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
800544e: bf00 nop
8005450: 40021000 .word 0x40021000
8005454: 42420000 .word 0x42420000
8005458: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800545c: 4b92 ldr r3, [pc, #584] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800545e: 6a5b ldr r3, [r3, #36] @ 0x24
8005460: f003 0302 and.w r3, r3, #2
8005464: 2b00 cmp r3, #0
8005466: d1e9 bne.n 800543c <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8005468: 687b ldr r3, [r7, #4]
800546a: 681b ldr r3, [r3, #0]
800546c: f003 0304 and.w r3, r3, #4
8005470: 2b00 cmp r3, #0
8005472: f000 80a6 beq.w 80055c2 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8005476: 2300 movs r3, #0
8005478: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800547a: 4b8b ldr r3, [pc, #556] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800547c: 69db ldr r3, [r3, #28]
800547e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005482: 2b00 cmp r3, #0
8005484: d10d bne.n 80054a2 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005486: 4b88 ldr r3, [pc, #544] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005488: 69db ldr r3, [r3, #28]
800548a: 4a87 ldr r2, [pc, #540] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800548c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005490: 61d3 str r3, [r2, #28]
8005492: 4b85 ldr r3, [pc, #532] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005494: 69db ldr r3, [r3, #28]
8005496: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800549a: 60bb str r3, [r7, #8]
800549c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800549e: 2301 movs r3, #1
80054a0: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054a2: 4b82 ldr r3, [pc, #520] @ (80056ac <HAL_RCC_OscConfig+0x4c8>)
80054a4: 681b ldr r3, [r3, #0]
80054a6: f403 7380 and.w r3, r3, #256 @ 0x100
80054aa: 2b00 cmp r3, #0
80054ac: d118 bne.n 80054e0 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80054ae: 4b7f ldr r3, [pc, #508] @ (80056ac <HAL_RCC_OscConfig+0x4c8>)
80054b0: 681b ldr r3, [r3, #0]
80054b2: 4a7e ldr r2, [pc, #504] @ (80056ac <HAL_RCC_OscConfig+0x4c8>)
80054b4: f443 7380 orr.w r3, r3, #256 @ 0x100
80054b8: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80054ba: f7fc fe8f bl 80021dc <HAL_GetTick>
80054be: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054c0: e008 b.n 80054d4 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80054c2: f7fc fe8b bl 80021dc <HAL_GetTick>
80054c6: 4602 mov r2, r0
80054c8: 693b ldr r3, [r7, #16]
80054ca: 1ad3 subs r3, r2, r3
80054cc: 2b64 cmp r3, #100 @ 0x64
80054ce: d901 bls.n 80054d4 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
80054d0: 2303 movs r3, #3
80054d2: e103 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054d4: 4b75 ldr r3, [pc, #468] @ (80056ac <HAL_RCC_OscConfig+0x4c8>)
80054d6: 681b ldr r3, [r3, #0]
80054d8: f403 7380 and.w r3, r3, #256 @ 0x100
80054dc: 2b00 cmp r3, #0
80054de: d0f0 beq.n 80054c2 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80054e0: 687b ldr r3, [r7, #4]
80054e2: 68db ldr r3, [r3, #12]
80054e4: 2b01 cmp r3, #1
80054e6: d106 bne.n 80054f6 <HAL_RCC_OscConfig+0x312>
80054e8: 4b6f ldr r3, [pc, #444] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
80054ea: 6a1b ldr r3, [r3, #32]
80054ec: 4a6e ldr r2, [pc, #440] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
80054ee: f043 0301 orr.w r3, r3, #1
80054f2: 6213 str r3, [r2, #32]
80054f4: e02d b.n 8005552 <HAL_RCC_OscConfig+0x36e>
80054f6: 687b ldr r3, [r7, #4]
80054f8: 68db ldr r3, [r3, #12]
80054fa: 2b00 cmp r3, #0
80054fc: d10c bne.n 8005518 <HAL_RCC_OscConfig+0x334>
80054fe: 4b6a ldr r3, [pc, #424] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005500: 6a1b ldr r3, [r3, #32]
8005502: 4a69 ldr r2, [pc, #420] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005504: f023 0301 bic.w r3, r3, #1
8005508: 6213 str r3, [r2, #32]
800550a: 4b67 ldr r3, [pc, #412] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800550c: 6a1b ldr r3, [r3, #32]
800550e: 4a66 ldr r2, [pc, #408] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005510: f023 0304 bic.w r3, r3, #4
8005514: 6213 str r3, [r2, #32]
8005516: e01c b.n 8005552 <HAL_RCC_OscConfig+0x36e>
8005518: 687b ldr r3, [r7, #4]
800551a: 68db ldr r3, [r3, #12]
800551c: 2b05 cmp r3, #5
800551e: d10c bne.n 800553a <HAL_RCC_OscConfig+0x356>
8005520: 4b61 ldr r3, [pc, #388] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005522: 6a1b ldr r3, [r3, #32]
8005524: 4a60 ldr r2, [pc, #384] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005526: f043 0304 orr.w r3, r3, #4
800552a: 6213 str r3, [r2, #32]
800552c: 4b5e ldr r3, [pc, #376] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800552e: 6a1b ldr r3, [r3, #32]
8005530: 4a5d ldr r2, [pc, #372] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005532: f043 0301 orr.w r3, r3, #1
8005536: 6213 str r3, [r2, #32]
8005538: e00b b.n 8005552 <HAL_RCC_OscConfig+0x36e>
800553a: 4b5b ldr r3, [pc, #364] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800553c: 6a1b ldr r3, [r3, #32]
800553e: 4a5a ldr r2, [pc, #360] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005540: f023 0301 bic.w r3, r3, #1
8005544: 6213 str r3, [r2, #32]
8005546: 4b58 ldr r3, [pc, #352] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005548: 6a1b ldr r3, [r3, #32]
800554a: 4a57 ldr r2, [pc, #348] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800554c: f023 0304 bic.w r3, r3, #4
8005550: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8005552: 687b ldr r3, [r7, #4]
8005554: 68db ldr r3, [r3, #12]
8005556: 2b00 cmp r3, #0
8005558: d015 beq.n 8005586 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800555a: f7fc fe3f bl 80021dc <HAL_GetTick>
800555e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005560: e00a b.n 8005578 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005562: f7fc fe3b bl 80021dc <HAL_GetTick>
8005566: 4602 mov r2, r0
8005568: 693b ldr r3, [r7, #16]
800556a: 1ad3 subs r3, r2, r3
800556c: f241 3288 movw r2, #5000 @ 0x1388
8005570: 4293 cmp r3, r2
8005572: d901 bls.n 8005578 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8005574: 2303 movs r3, #3
8005576: e0b1 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005578: 4b4b ldr r3, [pc, #300] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800557a: 6a1b ldr r3, [r3, #32]
800557c: f003 0302 and.w r3, r3, #2
8005580: 2b00 cmp r3, #0
8005582: d0ee beq.n 8005562 <HAL_RCC_OscConfig+0x37e>
8005584: e014 b.n 80055b0 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005586: f7fc fe29 bl 80021dc <HAL_GetTick>
800558a: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800558c: e00a b.n 80055a4 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800558e: f7fc fe25 bl 80021dc <HAL_GetTick>
8005592: 4602 mov r2, r0
8005594: 693b ldr r3, [r7, #16]
8005596: 1ad3 subs r3, r2, r3
8005598: f241 3288 movw r2, #5000 @ 0x1388
800559c: 4293 cmp r3, r2
800559e: d901 bls.n 80055a4 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
80055a0: 2303 movs r3, #3
80055a2: e09b b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80055a4: 4b40 ldr r3, [pc, #256] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
80055a6: 6a1b ldr r3, [r3, #32]
80055a8: f003 0302 and.w r3, r3, #2
80055ac: 2b00 cmp r3, #0
80055ae: d1ee bne.n 800558e <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
80055b0: 7dfb ldrb r3, [r7, #23]
80055b2: 2b01 cmp r3, #1
80055b4: d105 bne.n 80055c2 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
80055b6: 4b3c ldr r3, [pc, #240] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
80055b8: 69db ldr r3, [r3, #28]
80055ba: 4a3b ldr r2, [pc, #236] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
80055bc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80055c0: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80055c2: 687b ldr r3, [r7, #4]
80055c4: 69db ldr r3, [r3, #28]
80055c6: 2b00 cmp r3, #0
80055c8: f000 8087 beq.w 80056da <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80055cc: 4b36 ldr r3, [pc, #216] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
80055ce: 685b ldr r3, [r3, #4]
80055d0: f003 030c and.w r3, r3, #12
80055d4: 2b08 cmp r3, #8
80055d6: d061 beq.n 800569c <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80055d8: 687b ldr r3, [r7, #4]
80055da: 69db ldr r3, [r3, #28]
80055dc: 2b02 cmp r3, #2
80055de: d146 bne.n 800566e <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80055e0: 4b33 ldr r3, [pc, #204] @ (80056b0 <HAL_RCC_OscConfig+0x4cc>)
80055e2: 2200 movs r2, #0
80055e4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80055e6: f7fc fdf9 bl 80021dc <HAL_GetTick>
80055ea: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80055ec: e008 b.n 8005600 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80055ee: f7fc fdf5 bl 80021dc <HAL_GetTick>
80055f2: 4602 mov r2, r0
80055f4: 693b ldr r3, [r7, #16]
80055f6: 1ad3 subs r3, r2, r3
80055f8: 2b02 cmp r3, #2
80055fa: d901 bls.n 8005600 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
80055fc: 2303 movs r3, #3
80055fe: e06d b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8005600: 4b29 ldr r3, [pc, #164] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005602: 681b ldr r3, [r3, #0]
8005604: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005608: 2b00 cmp r3, #0
800560a: d1f0 bne.n 80055ee <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
800560c: 687b ldr r3, [r7, #4]
800560e: 6a1b ldr r3, [r3, #32]
8005610: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8005614: d108 bne.n 8005628 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8005616: 4b24 ldr r3, [pc, #144] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005618: 685b ldr r3, [r3, #4]
800561a: f423 3200 bic.w r2, r3, #131072 @ 0x20000
800561e: 687b ldr r3, [r7, #4]
8005620: 689b ldr r3, [r3, #8]
8005622: 4921 ldr r1, [pc, #132] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005624: 4313 orrs r3, r2
8005626: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8005628: 4b1f ldr r3, [pc, #124] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800562a: 685b ldr r3, [r3, #4]
800562c: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8005630: 687b ldr r3, [r7, #4]
8005632: 6a19 ldr r1, [r3, #32]
8005634: 687b ldr r3, [r7, #4]
8005636: 6a5b ldr r3, [r3, #36] @ 0x24
8005638: 430b orrs r3, r1
800563a: 491b ldr r1, [pc, #108] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
800563c: 4313 orrs r3, r2
800563e: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8005640: 4b1b ldr r3, [pc, #108] @ (80056b0 <HAL_RCC_OscConfig+0x4cc>)
8005642: 2201 movs r2, #1
8005644: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005646: f7fc fdc9 bl 80021dc <HAL_GetTick>
800564a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800564c: e008 b.n 8005660 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800564e: f7fc fdc5 bl 80021dc <HAL_GetTick>
8005652: 4602 mov r2, r0
8005654: 693b ldr r3, [r7, #16]
8005656: 1ad3 subs r3, r2, r3
8005658: 2b02 cmp r3, #2
800565a: d901 bls.n 8005660 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
800565c: 2303 movs r3, #3
800565e: e03d b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8005660: 4b11 ldr r3, [pc, #68] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005662: 681b ldr r3, [r3, #0]
8005664: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005668: 2b00 cmp r3, #0
800566a: d0f0 beq.n 800564e <HAL_RCC_OscConfig+0x46a>
800566c: e035 b.n 80056da <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800566e: 4b10 ldr r3, [pc, #64] @ (80056b0 <HAL_RCC_OscConfig+0x4cc>)
8005670: 2200 movs r2, #0
8005672: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005674: f7fc fdb2 bl 80021dc <HAL_GetTick>
8005678: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800567a: e008 b.n 800568e <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800567c: f7fc fdae bl 80021dc <HAL_GetTick>
8005680: 4602 mov r2, r0
8005682: 693b ldr r3, [r7, #16]
8005684: 1ad3 subs r3, r2, r3
8005686: 2b02 cmp r3, #2
8005688: d901 bls.n 800568e <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
800568a: 2303 movs r3, #3
800568c: e026 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800568e: 4b06 ldr r3, [pc, #24] @ (80056a8 <HAL_RCC_OscConfig+0x4c4>)
8005690: 681b ldr r3, [r3, #0]
8005692: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005696: 2b00 cmp r3, #0
8005698: d1f0 bne.n 800567c <HAL_RCC_OscConfig+0x498>
800569a: e01e b.n 80056da <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800569c: 687b ldr r3, [r7, #4]
800569e: 69db ldr r3, [r3, #28]
80056a0: 2b01 cmp r3, #1
80056a2: d107 bne.n 80056b4 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
80056a4: 2301 movs r3, #1
80056a6: e019 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
80056a8: 40021000 .word 0x40021000
80056ac: 40007000 .word 0x40007000
80056b0: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80056b4: 4b0b ldr r3, [pc, #44] @ (80056e4 <HAL_RCC_OscConfig+0x500>)
80056b6: 685b ldr r3, [r3, #4]
80056b8: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80056ba: 68fb ldr r3, [r7, #12]
80056bc: f403 3280 and.w r2, r3, #65536 @ 0x10000
80056c0: 687b ldr r3, [r7, #4]
80056c2: 6a1b ldr r3, [r3, #32]
80056c4: 429a cmp r2, r3
80056c6: d106 bne.n 80056d6 <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
80056c8: 68fb ldr r3, [r7, #12]
80056ca: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
80056ce: 687b ldr r3, [r7, #4]
80056d0: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80056d2: 429a cmp r2, r3
80056d4: d001 beq.n 80056da <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80056d6: 2301 movs r3, #1
80056d8: e000 b.n 80056dc <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80056da: 2300 movs r3, #0
}
80056dc: 4618 mov r0, r3
80056de: 3718 adds r7, #24
80056e0: 46bd mov sp, r7
80056e2: bd80 pop {r7, pc}
80056e4: 40021000 .word 0x40021000
080056e8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80056e8: b580 push {r7, lr}
80056ea: b084 sub sp, #16
80056ec: af00 add r7, sp, #0
80056ee: 6078 str r0, [r7, #4]
80056f0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80056f2: 687b ldr r3, [r7, #4]
80056f4: 2b00 cmp r3, #0
80056f6: d101 bne.n 80056fc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80056f8: 2301 movs r3, #1
80056fa: e0d0 b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80056fc: 4b6a ldr r3, [pc, #424] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
80056fe: 681b ldr r3, [r3, #0]
8005700: f003 0307 and.w r3, r3, #7
8005704: 683a ldr r2, [r7, #0]
8005706: 429a cmp r2, r3
8005708: d910 bls.n 800572c <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800570a: 4b67 ldr r3, [pc, #412] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
800570c: 681b ldr r3, [r3, #0]
800570e: f023 0207 bic.w r2, r3, #7
8005712: 4965 ldr r1, [pc, #404] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
8005714: 683b ldr r3, [r7, #0]
8005716: 4313 orrs r3, r2
8005718: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800571a: 4b63 ldr r3, [pc, #396] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
800571c: 681b ldr r3, [r3, #0]
800571e: f003 0307 and.w r3, r3, #7
8005722: 683a ldr r2, [r7, #0]
8005724: 429a cmp r2, r3
8005726: d001 beq.n 800572c <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8005728: 2301 movs r3, #1
800572a: e0b8 b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800572c: 687b ldr r3, [r7, #4]
800572e: 681b ldr r3, [r3, #0]
8005730: f003 0302 and.w r3, r3, #2
8005734: 2b00 cmp r3, #0
8005736: d020 beq.n 800577a <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8005738: 687b ldr r3, [r7, #4]
800573a: 681b ldr r3, [r3, #0]
800573c: f003 0304 and.w r3, r3, #4
8005740: 2b00 cmp r3, #0
8005742: d005 beq.n 8005750 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8005744: 4b59 ldr r3, [pc, #356] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005746: 685b ldr r3, [r3, #4]
8005748: 4a58 ldr r2, [pc, #352] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
800574a: f443 63e0 orr.w r3, r3, #1792 @ 0x700
800574e: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005750: 687b ldr r3, [r7, #4]
8005752: 681b ldr r3, [r3, #0]
8005754: f003 0308 and.w r3, r3, #8
8005758: 2b00 cmp r3, #0
800575a: d005 beq.n 8005768 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800575c: 4b53 ldr r3, [pc, #332] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
800575e: 685b ldr r3, [r3, #4]
8005760: 4a52 ldr r2, [pc, #328] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005762: f443 5360 orr.w r3, r3, #14336 @ 0x3800
8005766: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8005768: 4b50 ldr r3, [pc, #320] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
800576a: 685b ldr r3, [r3, #4]
800576c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8005770: 687b ldr r3, [r7, #4]
8005772: 689b ldr r3, [r3, #8]
8005774: 494d ldr r1, [pc, #308] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005776: 4313 orrs r3, r2
8005778: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800577a: 687b ldr r3, [r7, #4]
800577c: 681b ldr r3, [r3, #0]
800577e: f003 0301 and.w r3, r3, #1
8005782: 2b00 cmp r3, #0
8005784: d040 beq.n 8005808 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8005786: 687b ldr r3, [r7, #4]
8005788: 685b ldr r3, [r3, #4]
800578a: 2b01 cmp r3, #1
800578c: d107 bne.n 800579e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800578e: 4b47 ldr r3, [pc, #284] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005790: 681b ldr r3, [r3, #0]
8005792: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005796: 2b00 cmp r3, #0
8005798: d115 bne.n 80057c6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800579a: 2301 movs r3, #1
800579c: e07f b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800579e: 687b ldr r3, [r7, #4]
80057a0: 685b ldr r3, [r3, #4]
80057a2: 2b02 cmp r3, #2
80057a4: d107 bne.n 80057b6 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80057a6: 4b41 ldr r3, [pc, #260] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
80057a8: 681b ldr r3, [r3, #0]
80057aa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80057ae: 2b00 cmp r3, #0
80057b0: d109 bne.n 80057c6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80057b2: 2301 movs r3, #1
80057b4: e073 b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80057b6: 4b3d ldr r3, [pc, #244] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
80057b8: 681b ldr r3, [r3, #0]
80057ba: f003 0302 and.w r3, r3, #2
80057be: 2b00 cmp r3, #0
80057c0: d101 bne.n 80057c6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80057c2: 2301 movs r3, #1
80057c4: e06b b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80057c6: 4b39 ldr r3, [pc, #228] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
80057c8: 685b ldr r3, [r3, #4]
80057ca: f023 0203 bic.w r2, r3, #3
80057ce: 687b ldr r3, [r7, #4]
80057d0: 685b ldr r3, [r3, #4]
80057d2: 4936 ldr r1, [pc, #216] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
80057d4: 4313 orrs r3, r2
80057d6: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80057d8: f7fc fd00 bl 80021dc <HAL_GetTick>
80057dc: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80057de: e00a b.n 80057f6 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80057e0: f7fc fcfc bl 80021dc <HAL_GetTick>
80057e4: 4602 mov r2, r0
80057e6: 68fb ldr r3, [r7, #12]
80057e8: 1ad3 subs r3, r2, r3
80057ea: f241 3288 movw r2, #5000 @ 0x1388
80057ee: 4293 cmp r3, r2
80057f0: d901 bls.n 80057f6 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80057f2: 2303 movs r3, #3
80057f4: e053 b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80057f6: 4b2d ldr r3, [pc, #180] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
80057f8: 685b ldr r3, [r3, #4]
80057fa: f003 020c and.w r2, r3, #12
80057fe: 687b ldr r3, [r7, #4]
8005800: 685b ldr r3, [r3, #4]
8005802: 009b lsls r3, r3, #2
8005804: 429a cmp r2, r3
8005806: d1eb bne.n 80057e0 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8005808: 4b27 ldr r3, [pc, #156] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
800580a: 681b ldr r3, [r3, #0]
800580c: f003 0307 and.w r3, r3, #7
8005810: 683a ldr r2, [r7, #0]
8005812: 429a cmp r2, r3
8005814: d210 bcs.n 8005838 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8005816: 4b24 ldr r3, [pc, #144] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
8005818: 681b ldr r3, [r3, #0]
800581a: f023 0207 bic.w r2, r3, #7
800581e: 4922 ldr r1, [pc, #136] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
8005820: 683b ldr r3, [r7, #0]
8005822: 4313 orrs r3, r2
8005824: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8005826: 4b20 ldr r3, [pc, #128] @ (80058a8 <HAL_RCC_ClockConfig+0x1c0>)
8005828: 681b ldr r3, [r3, #0]
800582a: f003 0307 and.w r3, r3, #7
800582e: 683a ldr r2, [r7, #0]
8005830: 429a cmp r2, r3
8005832: d001 beq.n 8005838 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8005834: 2301 movs r3, #1
8005836: e032 b.n 800589e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8005838: 687b ldr r3, [r7, #4]
800583a: 681b ldr r3, [r3, #0]
800583c: f003 0304 and.w r3, r3, #4
8005840: 2b00 cmp r3, #0
8005842: d008 beq.n 8005856 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8005844: 4b19 ldr r3, [pc, #100] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005846: 685b ldr r3, [r3, #4]
8005848: f423 62e0 bic.w r2, r3, #1792 @ 0x700
800584c: 687b ldr r3, [r7, #4]
800584e: 68db ldr r3, [r3, #12]
8005850: 4916 ldr r1, [pc, #88] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005852: 4313 orrs r3, r2
8005854: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005856: 687b ldr r3, [r7, #4]
8005858: 681b ldr r3, [r3, #0]
800585a: f003 0308 and.w r3, r3, #8
800585e: 2b00 cmp r3, #0
8005860: d009 beq.n 8005876 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8005862: 4b12 ldr r3, [pc, #72] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005864: 685b ldr r3, [r3, #4]
8005866: f423 5260 bic.w r2, r3, #14336 @ 0x3800
800586a: 687b ldr r3, [r7, #4]
800586c: 691b ldr r3, [r3, #16]
800586e: 00db lsls r3, r3, #3
8005870: 490e ldr r1, [pc, #56] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
8005872: 4313 orrs r3, r2
8005874: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8005876: f000 f821 bl 80058bc <HAL_RCC_GetSysClockFreq>
800587a: 4602 mov r2, r0
800587c: 4b0b ldr r3, [pc, #44] @ (80058ac <HAL_RCC_ClockConfig+0x1c4>)
800587e: 685b ldr r3, [r3, #4]
8005880: 091b lsrs r3, r3, #4
8005882: f003 030f and.w r3, r3, #15
8005886: 490a ldr r1, [pc, #40] @ (80058b0 <HAL_RCC_ClockConfig+0x1c8>)
8005888: 5ccb ldrb r3, [r1, r3]
800588a: fa22 f303 lsr.w r3, r2, r3
800588e: 4a09 ldr r2, [pc, #36] @ (80058b4 <HAL_RCC_ClockConfig+0x1cc>)
8005890: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8005892: 4b09 ldr r3, [pc, #36] @ (80058b8 <HAL_RCC_ClockConfig+0x1d0>)
8005894: 681b ldr r3, [r3, #0]
8005896: 4618 mov r0, r3
8005898: f7fc fc5e bl 8002158 <HAL_InitTick>
return HAL_OK;
800589c: 2300 movs r3, #0
}
800589e: 4618 mov r0, r3
80058a0: 3710 adds r7, #16
80058a2: 46bd mov sp, r7
80058a4: bd80 pop {r7, pc}
80058a6: bf00 nop
80058a8: 40022000 .word 0x40022000
80058ac: 40021000 .word 0x40021000
80058b0: 0800be24 .word 0x0800be24
80058b4: 20000004 .word 0x20000004
80058b8: 20000008 .word 0x20000008
080058bc <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80058bc: b480 push {r7}
80058be: b087 sub sp, #28
80058c0: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80058c2: 2300 movs r3, #0
80058c4: 60fb str r3, [r7, #12]
80058c6: 2300 movs r3, #0
80058c8: 60bb str r3, [r7, #8]
80058ca: 2300 movs r3, #0
80058cc: 617b str r3, [r7, #20]
80058ce: 2300 movs r3, #0
80058d0: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80058d2: 2300 movs r3, #0
80058d4: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80058d6: 4b1e ldr r3, [pc, #120] @ (8005950 <HAL_RCC_GetSysClockFreq+0x94>)
80058d8: 685b ldr r3, [r3, #4]
80058da: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80058dc: 68fb ldr r3, [r7, #12]
80058de: f003 030c and.w r3, r3, #12
80058e2: 2b04 cmp r3, #4
80058e4: d002 beq.n 80058ec <HAL_RCC_GetSysClockFreq+0x30>
80058e6: 2b08 cmp r3, #8
80058e8: d003 beq.n 80058f2 <HAL_RCC_GetSysClockFreq+0x36>
80058ea: e027 b.n 800593c <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80058ec: 4b19 ldr r3, [pc, #100] @ (8005954 <HAL_RCC_GetSysClockFreq+0x98>)
80058ee: 613b str r3, [r7, #16]
break;
80058f0: e027 b.n 8005942 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80058f2: 68fb ldr r3, [r7, #12]
80058f4: 0c9b lsrs r3, r3, #18
80058f6: f003 030f and.w r3, r3, #15
80058fa: 4a17 ldr r2, [pc, #92] @ (8005958 <HAL_RCC_GetSysClockFreq+0x9c>)
80058fc: 5cd3 ldrb r3, [r2, r3]
80058fe: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8005900: 68fb ldr r3, [r7, #12]
8005902: f403 3380 and.w r3, r3, #65536 @ 0x10000
8005906: 2b00 cmp r3, #0
8005908: d010 beq.n 800592c <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
800590a: 4b11 ldr r3, [pc, #68] @ (8005950 <HAL_RCC_GetSysClockFreq+0x94>)
800590c: 685b ldr r3, [r3, #4]
800590e: 0c5b lsrs r3, r3, #17
8005910: f003 0301 and.w r3, r3, #1
8005914: 4a11 ldr r2, [pc, #68] @ (800595c <HAL_RCC_GetSysClockFreq+0xa0>)
8005916: 5cd3 ldrb r3, [r2, r3]
8005918: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
800591a: 687b ldr r3, [r7, #4]
800591c: 4a0d ldr r2, [pc, #52] @ (8005954 <HAL_RCC_GetSysClockFreq+0x98>)
800591e: fb03 f202 mul.w r2, r3, r2
8005922: 68bb ldr r3, [r7, #8]
8005924: fbb2 f3f3 udiv r3, r2, r3
8005928: 617b str r3, [r7, #20]
800592a: e004 b.n 8005936 <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
800592c: 687b ldr r3, [r7, #4]
800592e: 4a0c ldr r2, [pc, #48] @ (8005960 <HAL_RCC_GetSysClockFreq+0xa4>)
8005930: fb02 f303 mul.w r3, r2, r3
8005934: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
8005936: 697b ldr r3, [r7, #20]
8005938: 613b str r3, [r7, #16]
break;
800593a: e002 b.n 8005942 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800593c: 4b05 ldr r3, [pc, #20] @ (8005954 <HAL_RCC_GetSysClockFreq+0x98>)
800593e: 613b str r3, [r7, #16]
break;
8005940: bf00 nop
}
}
return sysclockfreq;
8005942: 693b ldr r3, [r7, #16]
}
8005944: 4618 mov r0, r3
8005946: 371c adds r7, #28
8005948: 46bd mov sp, r7
800594a: bc80 pop {r7}
800594c: 4770 bx lr
800594e: bf00 nop
8005950: 40021000 .word 0x40021000
8005954: 007a1200 .word 0x007a1200
8005958: 0800be3c .word 0x0800be3c
800595c: 0800be4c .word 0x0800be4c
8005960: 003d0900 .word 0x003d0900
08005964 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8005964: b480 push {r7}
8005966: af00 add r7, sp, #0
return SystemCoreClock;
8005968: 4b02 ldr r3, [pc, #8] @ (8005974 <HAL_RCC_GetHCLKFreq+0x10>)
800596a: 681b ldr r3, [r3, #0]
}
800596c: 4618 mov r0, r3
800596e: 46bd mov sp, r7
8005970: bc80 pop {r7}
8005972: 4770 bx lr
8005974: 20000004 .word 0x20000004
08005978 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8005978: b580 push {r7, lr}
800597a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
800597c: f7ff fff2 bl 8005964 <HAL_RCC_GetHCLKFreq>
8005980: 4602 mov r2, r0
8005982: 4b05 ldr r3, [pc, #20] @ (8005998 <HAL_RCC_GetPCLK1Freq+0x20>)
8005984: 685b ldr r3, [r3, #4]
8005986: 0a1b lsrs r3, r3, #8
8005988: f003 0307 and.w r3, r3, #7
800598c: 4903 ldr r1, [pc, #12] @ (800599c <HAL_RCC_GetPCLK1Freq+0x24>)
800598e: 5ccb ldrb r3, [r1, r3]
8005990: fa22 f303 lsr.w r3, r2, r3
}
8005994: 4618 mov r0, r3
8005996: bd80 pop {r7, pc}
8005998: 40021000 .word 0x40021000
800599c: 0800be34 .word 0x0800be34
080059a0 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
80059a0: b580 push {r7, lr}
80059a2: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
80059a4: f7ff ffde bl 8005964 <HAL_RCC_GetHCLKFreq>
80059a8: 4602 mov r2, r0
80059aa: 4b05 ldr r3, [pc, #20] @ (80059c0 <HAL_RCC_GetPCLK2Freq+0x20>)
80059ac: 685b ldr r3, [r3, #4]
80059ae: 0adb lsrs r3, r3, #11
80059b0: f003 0307 and.w r3, r3, #7
80059b4: 4903 ldr r1, [pc, #12] @ (80059c4 <HAL_RCC_GetPCLK2Freq+0x24>)
80059b6: 5ccb ldrb r3, [r1, r3]
80059b8: fa22 f303 lsr.w r3, r2, r3
}
80059bc: 4618 mov r0, r3
80059be: bd80 pop {r7, pc}
80059c0: 40021000 .word 0x40021000
80059c4: 0800be34 .word 0x0800be34
080059c8 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
80059c8: b480 push {r7}
80059ca: b085 sub sp, #20
80059cc: af00 add r7, sp, #0
80059ce: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
80059d0: 4b0a ldr r3, [pc, #40] @ (80059fc <RCC_Delay+0x34>)
80059d2: 681b ldr r3, [r3, #0]
80059d4: 4a0a ldr r2, [pc, #40] @ (8005a00 <RCC_Delay+0x38>)
80059d6: fba2 2303 umull r2, r3, r2, r3
80059da: 0a5b lsrs r3, r3, #9
80059dc: 687a ldr r2, [r7, #4]
80059de: fb02 f303 mul.w r3, r2, r3
80059e2: 60fb str r3, [r7, #12]
do
{
__NOP();
80059e4: bf00 nop
}
while (Delay --);
80059e6: 68fb ldr r3, [r7, #12]
80059e8: 1e5a subs r2, r3, #1
80059ea: 60fa str r2, [r7, #12]
80059ec: 2b00 cmp r3, #0
80059ee: d1f9 bne.n 80059e4 <RCC_Delay+0x1c>
}
80059f0: bf00 nop
80059f2: bf00 nop
80059f4: 3714 adds r7, #20
80059f6: 46bd mov sp, r7
80059f8: bc80 pop {r7}
80059fa: 4770 bx lr
80059fc: 20000004 .word 0x20000004
8005a00: 10624dd3 .word 0x10624dd3
08005a04 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8005a04: b580 push {r7, lr}
8005a06: b086 sub sp, #24
8005a08: af00 add r7, sp, #0
8005a0a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8005a0c: 2300 movs r3, #0
8005a0e: 613b str r3, [r7, #16]
8005a10: 2300 movs r3, #0
8005a12: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8005a14: 687b ldr r3, [r7, #4]
8005a16: 681b ldr r3, [r3, #0]
8005a18: f003 0301 and.w r3, r3, #1
8005a1c: 2b00 cmp r3, #0
8005a1e: d07d beq.n 8005b1c <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8005a20: 2300 movs r3, #0
8005a22: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8005a24: 4b4f ldr r3, [pc, #316] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a26: 69db ldr r3, [r3, #28]
8005a28: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005a2c: 2b00 cmp r3, #0
8005a2e: d10d bne.n 8005a4c <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005a30: 4b4c ldr r3, [pc, #304] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a32: 69db ldr r3, [r3, #28]
8005a34: 4a4b ldr r2, [pc, #300] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a36: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005a3a: 61d3 str r3, [r2, #28]
8005a3c: 4b49 ldr r3, [pc, #292] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a3e: 69db ldr r3, [r3, #28]
8005a40: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005a44: 60bb str r3, [r7, #8]
8005a46: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8005a48: 2301 movs r3, #1
8005a4a: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005a4c: 4b46 ldr r3, [pc, #280] @ (8005b68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a4e: 681b ldr r3, [r3, #0]
8005a50: f403 7380 and.w r3, r3, #256 @ 0x100
8005a54: 2b00 cmp r3, #0
8005a56: d118 bne.n 8005a8a <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8005a58: 4b43 ldr r3, [pc, #268] @ (8005b68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a5a: 681b ldr r3, [r3, #0]
8005a5c: 4a42 ldr r2, [pc, #264] @ (8005b68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a5e: f443 7380 orr.w r3, r3, #256 @ 0x100
8005a62: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8005a64: f7fc fbba bl 80021dc <HAL_GetTick>
8005a68: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005a6a: e008 b.n 8005a7e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005a6c: f7fc fbb6 bl 80021dc <HAL_GetTick>
8005a70: 4602 mov r2, r0
8005a72: 693b ldr r3, [r7, #16]
8005a74: 1ad3 subs r3, r2, r3
8005a76: 2b64 cmp r3, #100 @ 0x64
8005a78: d901 bls.n 8005a7e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8005a7a: 2303 movs r3, #3
8005a7c: e06d b.n 8005b5a <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005a7e: 4b3a ldr r3, [pc, #232] @ (8005b68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a80: 681b ldr r3, [r3, #0]
8005a82: f403 7380 and.w r3, r3, #256 @ 0x100
8005a86: 2b00 cmp r3, #0
8005a88: d0f0 beq.n 8005a6c <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8005a8a: 4b36 ldr r3, [pc, #216] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a8c: 6a1b ldr r3, [r3, #32]
8005a8e: f403 7340 and.w r3, r3, #768 @ 0x300
8005a92: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8005a94: 68fb ldr r3, [r7, #12]
8005a96: 2b00 cmp r3, #0
8005a98: d02e beq.n 8005af8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8005a9a: 687b ldr r3, [r7, #4]
8005a9c: 685b ldr r3, [r3, #4]
8005a9e: f403 7340 and.w r3, r3, #768 @ 0x300
8005aa2: 68fa ldr r2, [r7, #12]
8005aa4: 429a cmp r2, r3
8005aa6: d027 beq.n 8005af8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8005aa8: 4b2e ldr r3, [pc, #184] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005aaa: 6a1b ldr r3, [r3, #32]
8005aac: f423 7340 bic.w r3, r3, #768 @ 0x300
8005ab0: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8005ab2: 4b2e ldr r3, [pc, #184] @ (8005b6c <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005ab4: 2201 movs r2, #1
8005ab6: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8005ab8: 4b2c ldr r3, [pc, #176] @ (8005b6c <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005aba: 2200 movs r2, #0
8005abc: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8005abe: 4a29 ldr r2, [pc, #164] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005ac0: 68fb ldr r3, [r7, #12]
8005ac2: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8005ac4: 68fb ldr r3, [r7, #12]
8005ac6: f003 0301 and.w r3, r3, #1
8005aca: 2b00 cmp r3, #0
8005acc: d014 beq.n 8005af8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005ace: f7fc fb85 bl 80021dc <HAL_GetTick>
8005ad2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005ad4: e00a b.n 8005aec <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005ad6: f7fc fb81 bl 80021dc <HAL_GetTick>
8005ada: 4602 mov r2, r0
8005adc: 693b ldr r3, [r7, #16]
8005ade: 1ad3 subs r3, r2, r3
8005ae0: f241 3288 movw r2, #5000 @ 0x1388
8005ae4: 4293 cmp r3, r2
8005ae6: d901 bls.n 8005aec <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8005ae8: 2303 movs r3, #3
8005aea: e036 b.n 8005b5a <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005aec: 4b1d ldr r3, [pc, #116] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005aee: 6a1b ldr r3, [r3, #32]
8005af0: f003 0302 and.w r3, r3, #2
8005af4: 2b00 cmp r3, #0
8005af6: d0ee beq.n 8005ad6 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8005af8: 4b1a ldr r3, [pc, #104] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005afa: 6a1b ldr r3, [r3, #32]
8005afc: f423 7240 bic.w r2, r3, #768 @ 0x300
8005b00: 687b ldr r3, [r7, #4]
8005b02: 685b ldr r3, [r3, #4]
8005b04: 4917 ldr r1, [pc, #92] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b06: 4313 orrs r3, r2
8005b08: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005b0a: 7dfb ldrb r3, [r7, #23]
8005b0c: 2b01 cmp r3, #1
8005b0e: d105 bne.n 8005b1c <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005b10: 4b14 ldr r3, [pc, #80] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b12: 69db ldr r3, [r3, #28]
8005b14: 4a13 ldr r2, [pc, #76] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b16: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005b1a: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8005b1c: 687b ldr r3, [r7, #4]
8005b1e: 681b ldr r3, [r3, #0]
8005b20: f003 0302 and.w r3, r3, #2
8005b24: 2b00 cmp r3, #0
8005b26: d008 beq.n 8005b3a <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8005b28: 4b0e ldr r3, [pc, #56] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b2a: 685b ldr r3, [r3, #4]
8005b2c: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8005b30: 687b ldr r3, [r7, #4]
8005b32: 689b ldr r3, [r3, #8]
8005b34: 490b ldr r1, [pc, #44] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b36: 4313 orrs r3, r2
8005b38: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8005b3a: 687b ldr r3, [r7, #4]
8005b3c: 681b ldr r3, [r3, #0]
8005b3e: f003 0310 and.w r3, r3, #16
8005b42: 2b00 cmp r3, #0
8005b44: d008 beq.n 8005b58 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8005b46: 4b07 ldr r3, [pc, #28] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b48: 685b ldr r3, [r3, #4]
8005b4a: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
8005b4e: 687b ldr r3, [r7, #4]
8005b50: 68db ldr r3, [r3, #12]
8005b52: 4904 ldr r1, [pc, #16] @ (8005b64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b54: 4313 orrs r3, r2
8005b56: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8005b58: 2300 movs r3, #0
}
8005b5a: 4618 mov r0, r3
8005b5c: 3718 adds r7, #24
8005b5e: 46bd mov sp, r7
8005b60: bd80 pop {r7, pc}
8005b62: bf00 nop
8005b64: 40021000 .word 0x40021000
8005b68: 40007000 .word 0x40007000
8005b6c: 42420440 .word 0x42420440
08005b70 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8005b70: b580 push {r7, lr}
8005b72: b082 sub sp, #8
8005b74: af00 add r7, sp, #0
8005b76: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8005b78: 687b ldr r3, [r7, #4]
8005b7a: 2b00 cmp r3, #0
8005b7c: d101 bne.n 8005b82 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8005b7e: 2301 movs r3, #1
8005b80: e041 b.n 8005c06 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8005b82: 687b ldr r3, [r7, #4]
8005b84: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8005b88: b2db uxtb r3, r3
8005b8a: 2b00 cmp r3, #0
8005b8c: d106 bne.n 8005b9c <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005b8e: 687b ldr r3, [r7, #4]
8005b90: 2200 movs r2, #0
8005b92: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8005b96: 6878 ldr r0, [r7, #4]
8005b98: f7fc f954 bl 8001e44 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005b9c: 687b ldr r3, [r7, #4]
8005b9e: 2202 movs r2, #2
8005ba0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8005ba4: 687b ldr r3, [r7, #4]
8005ba6: 681a ldr r2, [r3, #0]
8005ba8: 687b ldr r3, [r7, #4]
8005baa: 3304 adds r3, #4
8005bac: 4619 mov r1, r3
8005bae: 4610 mov r0, r2
8005bb0: f000 fb3e bl 8006230 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8005bb4: 687b ldr r3, [r7, #4]
8005bb6: 2201 movs r2, #1
8005bb8: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005bbc: 687b ldr r3, [r7, #4]
8005bbe: 2201 movs r2, #1
8005bc0: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005bc4: 687b ldr r3, [r7, #4]
8005bc6: 2201 movs r2, #1
8005bc8: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005bcc: 687b ldr r3, [r7, #4]
8005bce: 2201 movs r2, #1
8005bd0: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005bd4: 687b ldr r3, [r7, #4]
8005bd6: 2201 movs r2, #1
8005bd8: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005bdc: 687b ldr r3, [r7, #4]
8005bde: 2201 movs r2, #1
8005be0: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005be4: 687b ldr r3, [r7, #4]
8005be6: 2201 movs r2, #1
8005be8: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005bec: 687b ldr r3, [r7, #4]
8005bee: 2201 movs r2, #1
8005bf0: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005bf4: 687b ldr r3, [r7, #4]
8005bf6: 2201 movs r2, #1
8005bf8: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8005bfc: 687b ldr r3, [r7, #4]
8005bfe: 2201 movs r2, #1
8005c00: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8005c04: 2300 movs r3, #0
}
8005c06: 4618 mov r0, r3
8005c08: 3708 adds r7, #8
8005c0a: 46bd mov sp, r7
8005c0c: bd80 pop {r7, pc}
08005c0e <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8005c0e: b580 push {r7, lr}
8005c10: b082 sub sp, #8
8005c12: af00 add r7, sp, #0
8005c14: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8005c16: 687b ldr r3, [r7, #4]
8005c18: 2b00 cmp r3, #0
8005c1a: d101 bne.n 8005c20 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8005c1c: 2301 movs r3, #1
8005c1e: e041 b.n 8005ca4 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8005c20: 687b ldr r3, [r7, #4]
8005c22: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8005c26: b2db uxtb r3, r3
8005c28: 2b00 cmp r3, #0
8005c2a: d106 bne.n 8005c3a <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005c2c: 687b ldr r3, [r7, #4]
8005c2e: 2200 movs r2, #0
8005c30: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8005c34: 6878 ldr r0, [r7, #4]
8005c36: f000 f839 bl 8005cac <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005c3a: 687b ldr r3, [r7, #4]
8005c3c: 2202 movs r2, #2
8005c3e: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8005c42: 687b ldr r3, [r7, #4]
8005c44: 681a ldr r2, [r3, #0]
8005c46: 687b ldr r3, [r7, #4]
8005c48: 3304 adds r3, #4
8005c4a: 4619 mov r1, r3
8005c4c: 4610 mov r0, r2
8005c4e: f000 faef bl 8006230 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8005c52: 687b ldr r3, [r7, #4]
8005c54: 2201 movs r2, #1
8005c56: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005c5a: 687b ldr r3, [r7, #4]
8005c5c: 2201 movs r2, #1
8005c5e: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005c62: 687b ldr r3, [r7, #4]
8005c64: 2201 movs r2, #1
8005c66: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005c6a: 687b ldr r3, [r7, #4]
8005c6c: 2201 movs r2, #1
8005c6e: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005c72: 687b ldr r3, [r7, #4]
8005c74: 2201 movs r2, #1
8005c76: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005c7a: 687b ldr r3, [r7, #4]
8005c7c: 2201 movs r2, #1
8005c7e: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005c82: 687b ldr r3, [r7, #4]
8005c84: 2201 movs r2, #1
8005c86: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005c8a: 687b ldr r3, [r7, #4]
8005c8c: 2201 movs r2, #1
8005c8e: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005c92: 687b ldr r3, [r7, #4]
8005c94: 2201 movs r2, #1
8005c96: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8005c9a: 687b ldr r3, [r7, #4]
8005c9c: 2201 movs r2, #1
8005c9e: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8005ca2: 2300 movs r3, #0
}
8005ca4: 4618 mov r0, r3
8005ca6: 3708 adds r7, #8
8005ca8: 46bd mov sp, r7
8005caa: bd80 pop {r7, pc}
08005cac <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8005cac: b480 push {r7}
8005cae: b083 sub sp, #12
8005cb0: af00 add r7, sp, #0
8005cb2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8005cb4: bf00 nop
8005cb6: 370c adds r7, #12
8005cb8: 46bd mov sp, r7
8005cba: bc80 pop {r7}
8005cbc: 4770 bx lr
...
08005cc0 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8005cc0: b580 push {r7, lr}
8005cc2: b084 sub sp, #16
8005cc4: af00 add r7, sp, #0
8005cc6: 6078 str r0, [r7, #4]
8005cc8: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8005cca: 683b ldr r3, [r7, #0]
8005ccc: 2b00 cmp r3, #0
8005cce: d109 bne.n 8005ce4 <HAL_TIM_PWM_Start+0x24>
8005cd0: 687b ldr r3, [r7, #4]
8005cd2: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8005cd6: b2db uxtb r3, r3
8005cd8: 2b01 cmp r3, #1
8005cda: bf14 ite ne
8005cdc: 2301 movne r3, #1
8005cde: 2300 moveq r3, #0
8005ce0: b2db uxtb r3, r3
8005ce2: e022 b.n 8005d2a <HAL_TIM_PWM_Start+0x6a>
8005ce4: 683b ldr r3, [r7, #0]
8005ce6: 2b04 cmp r3, #4
8005ce8: d109 bne.n 8005cfe <HAL_TIM_PWM_Start+0x3e>
8005cea: 687b ldr r3, [r7, #4]
8005cec: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8005cf0: b2db uxtb r3, r3
8005cf2: 2b01 cmp r3, #1
8005cf4: bf14 ite ne
8005cf6: 2301 movne r3, #1
8005cf8: 2300 moveq r3, #0
8005cfa: b2db uxtb r3, r3
8005cfc: e015 b.n 8005d2a <HAL_TIM_PWM_Start+0x6a>
8005cfe: 683b ldr r3, [r7, #0]
8005d00: 2b08 cmp r3, #8
8005d02: d109 bne.n 8005d18 <HAL_TIM_PWM_Start+0x58>
8005d04: 687b ldr r3, [r7, #4]
8005d06: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8005d0a: b2db uxtb r3, r3
8005d0c: 2b01 cmp r3, #1
8005d0e: bf14 ite ne
8005d10: 2301 movne r3, #1
8005d12: 2300 moveq r3, #0
8005d14: b2db uxtb r3, r3
8005d16: e008 b.n 8005d2a <HAL_TIM_PWM_Start+0x6a>
8005d18: 687b ldr r3, [r7, #4]
8005d1a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005d1e: b2db uxtb r3, r3
8005d20: 2b01 cmp r3, #1
8005d22: bf14 ite ne
8005d24: 2301 movne r3, #1
8005d26: 2300 moveq r3, #0
8005d28: b2db uxtb r3, r3
8005d2a: 2b00 cmp r3, #0
8005d2c: d001 beq.n 8005d32 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8005d2e: 2301 movs r3, #1
8005d30: e05e b.n 8005df0 <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8005d32: 683b ldr r3, [r7, #0]
8005d34: 2b00 cmp r3, #0
8005d36: d104 bne.n 8005d42 <HAL_TIM_PWM_Start+0x82>
8005d38: 687b ldr r3, [r7, #4]
8005d3a: 2202 movs r2, #2
8005d3c: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005d40: e013 b.n 8005d6a <HAL_TIM_PWM_Start+0xaa>
8005d42: 683b ldr r3, [r7, #0]
8005d44: 2b04 cmp r3, #4
8005d46: d104 bne.n 8005d52 <HAL_TIM_PWM_Start+0x92>
8005d48: 687b ldr r3, [r7, #4]
8005d4a: 2202 movs r2, #2
8005d4c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005d50: e00b b.n 8005d6a <HAL_TIM_PWM_Start+0xaa>
8005d52: 683b ldr r3, [r7, #0]
8005d54: 2b08 cmp r3, #8
8005d56: d104 bne.n 8005d62 <HAL_TIM_PWM_Start+0xa2>
8005d58: 687b ldr r3, [r7, #4]
8005d5a: 2202 movs r2, #2
8005d5c: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005d60: e003 b.n 8005d6a <HAL_TIM_PWM_Start+0xaa>
8005d62: 687b ldr r3, [r7, #4]
8005d64: 2202 movs r2, #2
8005d66: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8005d6a: 687b ldr r3, [r7, #4]
8005d6c: 681b ldr r3, [r3, #0]
8005d6e: 2201 movs r2, #1
8005d70: 6839 ldr r1, [r7, #0]
8005d72: 4618 mov r0, r3
8005d74: f000 fce8 bl 8006748 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8005d78: 687b ldr r3, [r7, #4]
8005d7a: 681b ldr r3, [r3, #0]
8005d7c: 4a1e ldr r2, [pc, #120] @ (8005df8 <HAL_TIM_PWM_Start+0x138>)
8005d7e: 4293 cmp r3, r2
8005d80: d107 bne.n 8005d92 <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8005d82: 687b ldr r3, [r7, #4]
8005d84: 681b ldr r3, [r3, #0]
8005d86: 6c5a ldr r2, [r3, #68] @ 0x44
8005d88: 687b ldr r3, [r7, #4]
8005d8a: 681b ldr r3, [r3, #0]
8005d8c: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8005d90: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005d92: 687b ldr r3, [r7, #4]
8005d94: 681b ldr r3, [r3, #0]
8005d96: 4a18 ldr r2, [pc, #96] @ (8005df8 <HAL_TIM_PWM_Start+0x138>)
8005d98: 4293 cmp r3, r2
8005d9a: d00e beq.n 8005dba <HAL_TIM_PWM_Start+0xfa>
8005d9c: 687b ldr r3, [r7, #4]
8005d9e: 681b ldr r3, [r3, #0]
8005da0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005da4: d009 beq.n 8005dba <HAL_TIM_PWM_Start+0xfa>
8005da6: 687b ldr r3, [r7, #4]
8005da8: 681b ldr r3, [r3, #0]
8005daa: 4a14 ldr r2, [pc, #80] @ (8005dfc <HAL_TIM_PWM_Start+0x13c>)
8005dac: 4293 cmp r3, r2
8005dae: d004 beq.n 8005dba <HAL_TIM_PWM_Start+0xfa>
8005db0: 687b ldr r3, [r7, #4]
8005db2: 681b ldr r3, [r3, #0]
8005db4: 4a12 ldr r2, [pc, #72] @ (8005e00 <HAL_TIM_PWM_Start+0x140>)
8005db6: 4293 cmp r3, r2
8005db8: d111 bne.n 8005dde <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8005dba: 687b ldr r3, [r7, #4]
8005dbc: 681b ldr r3, [r3, #0]
8005dbe: 689b ldr r3, [r3, #8]
8005dc0: f003 0307 and.w r3, r3, #7
8005dc4: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8005dc6: 68fb ldr r3, [r7, #12]
8005dc8: 2b06 cmp r3, #6
8005dca: d010 beq.n 8005dee <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
8005dcc: 687b ldr r3, [r7, #4]
8005dce: 681b ldr r3, [r3, #0]
8005dd0: 681a ldr r2, [r3, #0]
8005dd2: 687b ldr r3, [r7, #4]
8005dd4: 681b ldr r3, [r3, #0]
8005dd6: f042 0201 orr.w r2, r2, #1
8005dda: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8005ddc: e007 b.n 8005dee <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8005dde: 687b ldr r3, [r7, #4]
8005de0: 681b ldr r3, [r3, #0]
8005de2: 681a ldr r2, [r3, #0]
8005de4: 687b ldr r3, [r7, #4]
8005de6: 681b ldr r3, [r3, #0]
8005de8: f042 0201 orr.w r2, r2, #1
8005dec: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8005dee: 2300 movs r3, #0
}
8005df0: 4618 mov r0, r3
8005df2: 3710 adds r7, #16
8005df4: 46bd mov sp, r7
8005df6: bd80 pop {r7, pc}
8005df8: 40012c00 .word 0x40012c00
8005dfc: 40000400 .word 0x40000400
8005e00: 40000800 .word 0x40000800
08005e04 <HAL_TIM_PWM_Stop>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8005e04: b580 push {r7, lr}
8005e06: b082 sub sp, #8
8005e08: af00 add r7, sp, #0
8005e0a: 6078 str r0, [r7, #4]
8005e0c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
8005e0e: 687b ldr r3, [r7, #4]
8005e10: 681b ldr r3, [r3, #0]
8005e12: 2200 movs r2, #0
8005e14: 6839 ldr r1, [r7, #0]
8005e16: 4618 mov r0, r3
8005e18: f000 fc96 bl 8006748 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8005e1c: 687b ldr r3, [r7, #4]
8005e1e: 681b ldr r3, [r3, #0]
8005e20: 4a29 ldr r2, [pc, #164] @ (8005ec8 <HAL_TIM_PWM_Stop+0xc4>)
8005e22: 4293 cmp r3, r2
8005e24: d117 bne.n 8005e56 <HAL_TIM_PWM_Stop+0x52>
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
8005e26: 687b ldr r3, [r7, #4]
8005e28: 681b ldr r3, [r3, #0]
8005e2a: 6a1a ldr r2, [r3, #32]
8005e2c: f241 1311 movw r3, #4369 @ 0x1111
8005e30: 4013 ands r3, r2
8005e32: 2b00 cmp r3, #0
8005e34: d10f bne.n 8005e56 <HAL_TIM_PWM_Stop+0x52>
8005e36: 687b ldr r3, [r7, #4]
8005e38: 681b ldr r3, [r3, #0]
8005e3a: 6a1a ldr r2, [r3, #32]
8005e3c: f240 4344 movw r3, #1092 @ 0x444
8005e40: 4013 ands r3, r2
8005e42: 2b00 cmp r3, #0
8005e44: d107 bne.n 8005e56 <HAL_TIM_PWM_Stop+0x52>
8005e46: 687b ldr r3, [r7, #4]
8005e48: 681b ldr r3, [r3, #0]
8005e4a: 6c5a ldr r2, [r3, #68] @ 0x44
8005e4c: 687b ldr r3, [r7, #4]
8005e4e: 681b ldr r3, [r3, #0]
8005e50: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8005e54: 645a str r2, [r3, #68] @ 0x44
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
8005e56: 687b ldr r3, [r7, #4]
8005e58: 681b ldr r3, [r3, #0]
8005e5a: 6a1a ldr r2, [r3, #32]
8005e5c: f241 1311 movw r3, #4369 @ 0x1111
8005e60: 4013 ands r3, r2
8005e62: 2b00 cmp r3, #0
8005e64: d10f bne.n 8005e86 <HAL_TIM_PWM_Stop+0x82>
8005e66: 687b ldr r3, [r7, #4]
8005e68: 681b ldr r3, [r3, #0]
8005e6a: 6a1a ldr r2, [r3, #32]
8005e6c: f240 4344 movw r3, #1092 @ 0x444
8005e70: 4013 ands r3, r2
8005e72: 2b00 cmp r3, #0
8005e74: d107 bne.n 8005e86 <HAL_TIM_PWM_Stop+0x82>
8005e76: 687b ldr r3, [r7, #4]
8005e78: 681b ldr r3, [r3, #0]
8005e7a: 681a ldr r2, [r3, #0]
8005e7c: 687b ldr r3, [r7, #4]
8005e7e: 681b ldr r3, [r3, #0]
8005e80: f022 0201 bic.w r2, r2, #1
8005e84: 601a str r2, [r3, #0]
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
8005e86: 683b ldr r3, [r7, #0]
8005e88: 2b00 cmp r3, #0
8005e8a: d104 bne.n 8005e96 <HAL_TIM_PWM_Stop+0x92>
8005e8c: 687b ldr r3, [r7, #4]
8005e8e: 2201 movs r2, #1
8005e90: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005e94: e013 b.n 8005ebe <HAL_TIM_PWM_Stop+0xba>
8005e96: 683b ldr r3, [r7, #0]
8005e98: 2b04 cmp r3, #4
8005e9a: d104 bne.n 8005ea6 <HAL_TIM_PWM_Stop+0xa2>
8005e9c: 687b ldr r3, [r7, #4]
8005e9e: 2201 movs r2, #1
8005ea0: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005ea4: e00b b.n 8005ebe <HAL_TIM_PWM_Stop+0xba>
8005ea6: 683b ldr r3, [r7, #0]
8005ea8: 2b08 cmp r3, #8
8005eaa: d104 bne.n 8005eb6 <HAL_TIM_PWM_Stop+0xb2>
8005eac: 687b ldr r3, [r7, #4]
8005eae: 2201 movs r2, #1
8005eb0: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005eb4: e003 b.n 8005ebe <HAL_TIM_PWM_Stop+0xba>
8005eb6: 687b ldr r3, [r7, #4]
8005eb8: 2201 movs r2, #1
8005eba: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Return function status */
return HAL_OK;
8005ebe: 2300 movs r3, #0
}
8005ec0: 4618 mov r0, r3
8005ec2: 3708 adds r7, #8
8005ec4: 46bd mov sp, r7
8005ec6: bd80 pop {r7, pc}
8005ec8: 40012c00 .word 0x40012c00
08005ecc <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8005ecc: b580 push {r7, lr}
8005ece: b086 sub sp, #24
8005ed0: af00 add r7, sp, #0
8005ed2: 60f8 str r0, [r7, #12]
8005ed4: 60b9 str r1, [r7, #8]
8005ed6: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8005ed8: 2300 movs r3, #0
8005eda: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8005edc: 68fb ldr r3, [r7, #12]
8005ede: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005ee2: 2b01 cmp r3, #1
8005ee4: d101 bne.n 8005eea <HAL_TIM_PWM_ConfigChannel+0x1e>
8005ee6: 2302 movs r3, #2
8005ee8: e0ae b.n 8006048 <HAL_TIM_PWM_ConfigChannel+0x17c>
8005eea: 68fb ldr r3, [r7, #12]
8005eec: 2201 movs r2, #1
8005eee: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8005ef2: 687b ldr r3, [r7, #4]
8005ef4: 2b0c cmp r3, #12
8005ef6: f200 809f bhi.w 8006038 <HAL_TIM_PWM_ConfigChannel+0x16c>
8005efa: a201 add r2, pc, #4 @ (adr r2, 8005f00 <HAL_TIM_PWM_ConfigChannel+0x34>)
8005efc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005f00: 08005f35 .word 0x08005f35
8005f04: 08006039 .word 0x08006039
8005f08: 08006039 .word 0x08006039
8005f0c: 08006039 .word 0x08006039
8005f10: 08005f75 .word 0x08005f75
8005f14: 08006039 .word 0x08006039
8005f18: 08006039 .word 0x08006039
8005f1c: 08006039 .word 0x08006039
8005f20: 08005fb7 .word 0x08005fb7
8005f24: 08006039 .word 0x08006039
8005f28: 08006039 .word 0x08006039
8005f2c: 08006039 .word 0x08006039
8005f30: 08005ff7 .word 0x08005ff7
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8005f34: 68fb ldr r3, [r7, #12]
8005f36: 681b ldr r3, [r3, #0]
8005f38: 68b9 ldr r1, [r7, #8]
8005f3a: 4618 mov r0, r3
8005f3c: f000 f9e6 bl 800630c <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8005f40: 68fb ldr r3, [r7, #12]
8005f42: 681b ldr r3, [r3, #0]
8005f44: 699a ldr r2, [r3, #24]
8005f46: 68fb ldr r3, [r7, #12]
8005f48: 681b ldr r3, [r3, #0]
8005f4a: f042 0208 orr.w r2, r2, #8
8005f4e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8005f50: 68fb ldr r3, [r7, #12]
8005f52: 681b ldr r3, [r3, #0]
8005f54: 699a ldr r2, [r3, #24]
8005f56: 68fb ldr r3, [r7, #12]
8005f58: 681b ldr r3, [r3, #0]
8005f5a: f022 0204 bic.w r2, r2, #4
8005f5e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8005f60: 68fb ldr r3, [r7, #12]
8005f62: 681b ldr r3, [r3, #0]
8005f64: 6999 ldr r1, [r3, #24]
8005f66: 68bb ldr r3, [r7, #8]
8005f68: 691a ldr r2, [r3, #16]
8005f6a: 68fb ldr r3, [r7, #12]
8005f6c: 681b ldr r3, [r3, #0]
8005f6e: 430a orrs r2, r1
8005f70: 619a str r2, [r3, #24]
break;
8005f72: e064 b.n 800603e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8005f74: 68fb ldr r3, [r7, #12]
8005f76: 681b ldr r3, [r3, #0]
8005f78: 68b9 ldr r1, [r7, #8]
8005f7a: 4618 mov r0, r3
8005f7c: f000 fa2c bl 80063d8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8005f80: 68fb ldr r3, [r7, #12]
8005f82: 681b ldr r3, [r3, #0]
8005f84: 699a ldr r2, [r3, #24]
8005f86: 68fb ldr r3, [r7, #12]
8005f88: 681b ldr r3, [r3, #0]
8005f8a: f442 6200 orr.w r2, r2, #2048 @ 0x800
8005f8e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8005f90: 68fb ldr r3, [r7, #12]
8005f92: 681b ldr r3, [r3, #0]
8005f94: 699a ldr r2, [r3, #24]
8005f96: 68fb ldr r3, [r7, #12]
8005f98: 681b ldr r3, [r3, #0]
8005f9a: f422 6280 bic.w r2, r2, #1024 @ 0x400
8005f9e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8005fa0: 68fb ldr r3, [r7, #12]
8005fa2: 681b ldr r3, [r3, #0]
8005fa4: 6999 ldr r1, [r3, #24]
8005fa6: 68bb ldr r3, [r7, #8]
8005fa8: 691b ldr r3, [r3, #16]
8005faa: 021a lsls r2, r3, #8
8005fac: 68fb ldr r3, [r7, #12]
8005fae: 681b ldr r3, [r3, #0]
8005fb0: 430a orrs r2, r1
8005fb2: 619a str r2, [r3, #24]
break;
8005fb4: e043 b.n 800603e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8005fb6: 68fb ldr r3, [r7, #12]
8005fb8: 681b ldr r3, [r3, #0]
8005fba: 68b9 ldr r1, [r7, #8]
8005fbc: 4618 mov r0, r3
8005fbe: f000 fa75 bl 80064ac <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8005fc2: 68fb ldr r3, [r7, #12]
8005fc4: 681b ldr r3, [r3, #0]
8005fc6: 69da ldr r2, [r3, #28]
8005fc8: 68fb ldr r3, [r7, #12]
8005fca: 681b ldr r3, [r3, #0]
8005fcc: f042 0208 orr.w r2, r2, #8
8005fd0: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8005fd2: 68fb ldr r3, [r7, #12]
8005fd4: 681b ldr r3, [r3, #0]
8005fd6: 69da ldr r2, [r3, #28]
8005fd8: 68fb ldr r3, [r7, #12]
8005fda: 681b ldr r3, [r3, #0]
8005fdc: f022 0204 bic.w r2, r2, #4
8005fe0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8005fe2: 68fb ldr r3, [r7, #12]
8005fe4: 681b ldr r3, [r3, #0]
8005fe6: 69d9 ldr r1, [r3, #28]
8005fe8: 68bb ldr r3, [r7, #8]
8005fea: 691a ldr r2, [r3, #16]
8005fec: 68fb ldr r3, [r7, #12]
8005fee: 681b ldr r3, [r3, #0]
8005ff0: 430a orrs r2, r1
8005ff2: 61da str r2, [r3, #28]
break;
8005ff4: e023 b.n 800603e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8005ff6: 68fb ldr r3, [r7, #12]
8005ff8: 681b ldr r3, [r3, #0]
8005ffa: 68b9 ldr r1, [r7, #8]
8005ffc: 4618 mov r0, r3
8005ffe: f000 fabf bl 8006580 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8006002: 68fb ldr r3, [r7, #12]
8006004: 681b ldr r3, [r3, #0]
8006006: 69da ldr r2, [r3, #28]
8006008: 68fb ldr r3, [r7, #12]
800600a: 681b ldr r3, [r3, #0]
800600c: f442 6200 orr.w r2, r2, #2048 @ 0x800
8006010: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8006012: 68fb ldr r3, [r7, #12]
8006014: 681b ldr r3, [r3, #0]
8006016: 69da ldr r2, [r3, #28]
8006018: 68fb ldr r3, [r7, #12]
800601a: 681b ldr r3, [r3, #0]
800601c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8006020: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8006022: 68fb ldr r3, [r7, #12]
8006024: 681b ldr r3, [r3, #0]
8006026: 69d9 ldr r1, [r3, #28]
8006028: 68bb ldr r3, [r7, #8]
800602a: 691b ldr r3, [r3, #16]
800602c: 021a lsls r2, r3, #8
800602e: 68fb ldr r3, [r7, #12]
8006030: 681b ldr r3, [r3, #0]
8006032: 430a orrs r2, r1
8006034: 61da str r2, [r3, #28]
break;
8006036: e002 b.n 800603e <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8006038: 2301 movs r3, #1
800603a: 75fb strb r3, [r7, #23]
break;
800603c: bf00 nop
}
__HAL_UNLOCK(htim);
800603e: 68fb ldr r3, [r7, #12]
8006040: 2200 movs r2, #0
8006042: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8006046: 7dfb ldrb r3, [r7, #23]
}
8006048: 4618 mov r0, r3
800604a: 3718 adds r7, #24
800604c: 46bd mov sp, r7
800604e: bd80 pop {r7, pc}
08006050 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8006050: b580 push {r7, lr}
8006052: b084 sub sp, #16
8006054: af00 add r7, sp, #0
8006056: 6078 str r0, [r7, #4]
8006058: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
800605a: 2300 movs r3, #0
800605c: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800605e: 687b ldr r3, [r7, #4]
8006060: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8006064: 2b01 cmp r3, #1
8006066: d101 bne.n 800606c <HAL_TIM_ConfigClockSource+0x1c>
8006068: 2302 movs r3, #2
800606a: e0b4 b.n 80061d6 <HAL_TIM_ConfigClockSource+0x186>
800606c: 687b ldr r3, [r7, #4]
800606e: 2201 movs r2, #1
8006070: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8006074: 687b ldr r3, [r7, #4]
8006076: 2202 movs r2, #2
8006078: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800607c: 687b ldr r3, [r7, #4]
800607e: 681b ldr r3, [r3, #0]
8006080: 689b ldr r3, [r3, #8]
8006082: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8006084: 68bb ldr r3, [r7, #8]
8006086: f023 0377 bic.w r3, r3, #119 @ 0x77
800608a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800608c: 68bb ldr r3, [r7, #8]
800608e: f423 437f bic.w r3, r3, #65280 @ 0xff00
8006092: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8006094: 687b ldr r3, [r7, #4]
8006096: 681b ldr r3, [r3, #0]
8006098: 68ba ldr r2, [r7, #8]
800609a: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800609c: 683b ldr r3, [r7, #0]
800609e: 681b ldr r3, [r3, #0]
80060a0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80060a4: d03e beq.n 8006124 <HAL_TIM_ConfigClockSource+0xd4>
80060a6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80060aa: f200 8087 bhi.w 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060ae: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80060b2: f000 8086 beq.w 80061c2 <HAL_TIM_ConfigClockSource+0x172>
80060b6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80060ba: d87f bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060bc: 2b70 cmp r3, #112 @ 0x70
80060be: d01a beq.n 80060f6 <HAL_TIM_ConfigClockSource+0xa6>
80060c0: 2b70 cmp r3, #112 @ 0x70
80060c2: d87b bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060c4: 2b60 cmp r3, #96 @ 0x60
80060c6: d050 beq.n 800616a <HAL_TIM_ConfigClockSource+0x11a>
80060c8: 2b60 cmp r3, #96 @ 0x60
80060ca: d877 bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060cc: 2b50 cmp r3, #80 @ 0x50
80060ce: d03c beq.n 800614a <HAL_TIM_ConfigClockSource+0xfa>
80060d0: 2b50 cmp r3, #80 @ 0x50
80060d2: d873 bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060d4: 2b40 cmp r3, #64 @ 0x40
80060d6: d058 beq.n 800618a <HAL_TIM_ConfigClockSource+0x13a>
80060d8: 2b40 cmp r3, #64 @ 0x40
80060da: d86f bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060dc: 2b30 cmp r3, #48 @ 0x30
80060de: d064 beq.n 80061aa <HAL_TIM_ConfigClockSource+0x15a>
80060e0: 2b30 cmp r3, #48 @ 0x30
80060e2: d86b bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060e4: 2b20 cmp r3, #32
80060e6: d060 beq.n 80061aa <HAL_TIM_ConfigClockSource+0x15a>
80060e8: 2b20 cmp r3, #32
80060ea: d867 bhi.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
80060ec: 2b00 cmp r3, #0
80060ee: d05c beq.n 80061aa <HAL_TIM_ConfigClockSource+0x15a>
80060f0: 2b10 cmp r3, #16
80060f2: d05a beq.n 80061aa <HAL_TIM_ConfigClockSource+0x15a>
80060f4: e062 b.n 80061bc <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80060f6: 687b ldr r3, [r7, #4]
80060f8: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80060fa: 683b ldr r3, [r7, #0]
80060fc: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80060fe: 683b ldr r3, [r7, #0]
8006100: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8006102: 683b ldr r3, [r7, #0]
8006104: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8006106: f000 fb00 bl 800670a <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800610a: 687b ldr r3, [r7, #4]
800610c: 681b ldr r3, [r3, #0]
800610e: 689b ldr r3, [r3, #8]
8006110: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8006112: 68bb ldr r3, [r7, #8]
8006114: f043 0377 orr.w r3, r3, #119 @ 0x77
8006118: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800611a: 687b ldr r3, [r7, #4]
800611c: 681b ldr r3, [r3, #0]
800611e: 68ba ldr r2, [r7, #8]
8006120: 609a str r2, [r3, #8]
break;
8006122: e04f b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8006124: 687b ldr r3, [r7, #4]
8006126: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8006128: 683b ldr r3, [r7, #0]
800612a: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800612c: 683b ldr r3, [r7, #0]
800612e: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8006130: 683b ldr r3, [r7, #0]
8006132: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8006134: f000 fae9 bl 800670a <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8006138: 687b ldr r3, [r7, #4]
800613a: 681b ldr r3, [r3, #0]
800613c: 689a ldr r2, [r3, #8]
800613e: 687b ldr r3, [r7, #4]
8006140: 681b ldr r3, [r3, #0]
8006142: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8006146: 609a str r2, [r3, #8]
break;
8006148: e03c b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800614a: 687b ldr r3, [r7, #4]
800614c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800614e: 683b ldr r3, [r7, #0]
8006150: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8006152: 683b ldr r3, [r7, #0]
8006154: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8006156: 461a mov r2, r3
8006158: f000 fa60 bl 800661c <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
800615c: 687b ldr r3, [r7, #4]
800615e: 681b ldr r3, [r3, #0]
8006160: 2150 movs r1, #80 @ 0x50
8006162: 4618 mov r0, r3
8006164: f000 fab7 bl 80066d6 <TIM_ITRx_SetConfig>
break;
8006168: e02c b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
800616a: 687b ldr r3, [r7, #4]
800616c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800616e: 683b ldr r3, [r7, #0]
8006170: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8006172: 683b ldr r3, [r7, #0]
8006174: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8006176: 461a mov r2, r3
8006178: f000 fa7e bl 8006678 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800617c: 687b ldr r3, [r7, #4]
800617e: 681b ldr r3, [r3, #0]
8006180: 2160 movs r1, #96 @ 0x60
8006182: 4618 mov r0, r3
8006184: f000 faa7 bl 80066d6 <TIM_ITRx_SetConfig>
break;
8006188: e01c b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800618a: 687b ldr r3, [r7, #4]
800618c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800618e: 683b ldr r3, [r7, #0]
8006190: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8006192: 683b ldr r3, [r7, #0]
8006194: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8006196: 461a mov r2, r3
8006198: f000 fa40 bl 800661c <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800619c: 687b ldr r3, [r7, #4]
800619e: 681b ldr r3, [r3, #0]
80061a0: 2140 movs r1, #64 @ 0x40
80061a2: 4618 mov r0, r3
80061a4: f000 fa97 bl 80066d6 <TIM_ITRx_SetConfig>
break;
80061a8: e00c b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80061aa: 687b ldr r3, [r7, #4]
80061ac: 681a ldr r2, [r3, #0]
80061ae: 683b ldr r3, [r7, #0]
80061b0: 681b ldr r3, [r3, #0]
80061b2: 4619 mov r1, r3
80061b4: 4610 mov r0, r2
80061b6: f000 fa8e bl 80066d6 <TIM_ITRx_SetConfig>
break;
80061ba: e003 b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
80061bc: 2301 movs r3, #1
80061be: 73fb strb r3, [r7, #15]
break;
80061c0: e000 b.n 80061c4 <HAL_TIM_ConfigClockSource+0x174>
break;
80061c2: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
80061c4: 687b ldr r3, [r7, #4]
80061c6: 2201 movs r2, #1
80061c8: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80061cc: 687b ldr r3, [r7, #4]
80061ce: 2200 movs r2, #0
80061d0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80061d4: 7bfb ldrb r3, [r7, #15]
}
80061d6: 4618 mov r0, r3
80061d8: 3710 adds r7, #16
80061da: 46bd mov sp, r7
80061dc: bd80 pop {r7, pc}
080061de <HAL_TIM_GetChannelState>:
* @arg TIM_CHANNEL_5: TIM Channel 5
* @arg TIM_CHANNEL_6: TIM Channel 6
* @retval TIM Channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
80061de: b480 push {r7}
80061e0: b085 sub sp, #20
80061e2: af00 add r7, sp, #0
80061e4: 6078 str r0, [r7, #4]
80061e6: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
80061e8: 683b ldr r3, [r7, #0]
80061ea: 2b00 cmp r3, #0
80061ec: d104 bne.n 80061f8 <HAL_TIM_GetChannelState+0x1a>
80061ee: 687b ldr r3, [r7, #4]
80061f0: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
80061f4: b2db uxtb r3, r3
80061f6: e013 b.n 8006220 <HAL_TIM_GetChannelState+0x42>
80061f8: 683b ldr r3, [r7, #0]
80061fa: 2b04 cmp r3, #4
80061fc: d104 bne.n 8006208 <HAL_TIM_GetChannelState+0x2a>
80061fe: 687b ldr r3, [r7, #4]
8006200: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8006204: b2db uxtb r3, r3
8006206: e00b b.n 8006220 <HAL_TIM_GetChannelState+0x42>
8006208: 683b ldr r3, [r7, #0]
800620a: 2b08 cmp r3, #8
800620c: d104 bne.n 8006218 <HAL_TIM_GetChannelState+0x3a>
800620e: 687b ldr r3, [r7, #4]
8006210: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8006214: b2db uxtb r3, r3
8006216: e003 b.n 8006220 <HAL_TIM_GetChannelState+0x42>
8006218: 687b ldr r3, [r7, #4]
800621a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800621e: b2db uxtb r3, r3
8006220: 73fb strb r3, [r7, #15]
return channel_state;
8006222: 7bfb ldrb r3, [r7, #15]
}
8006224: 4618 mov r0, r3
8006226: 3714 adds r7, #20
8006228: 46bd mov sp, r7
800622a: bc80 pop {r7}
800622c: 4770 bx lr
...
08006230 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8006230: b480 push {r7}
8006232: b085 sub sp, #20
8006234: af00 add r7, sp, #0
8006236: 6078 str r0, [r7, #4]
8006238: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800623a: 687b ldr r3, [r7, #4]
800623c: 681b ldr r3, [r3, #0]
800623e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8006240: 687b ldr r3, [r7, #4]
8006242: 4a2f ldr r2, [pc, #188] @ (8006300 <TIM_Base_SetConfig+0xd0>)
8006244: 4293 cmp r3, r2
8006246: d00b beq.n 8006260 <TIM_Base_SetConfig+0x30>
8006248: 687b ldr r3, [r7, #4]
800624a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800624e: d007 beq.n 8006260 <TIM_Base_SetConfig+0x30>
8006250: 687b ldr r3, [r7, #4]
8006252: 4a2c ldr r2, [pc, #176] @ (8006304 <TIM_Base_SetConfig+0xd4>)
8006254: 4293 cmp r3, r2
8006256: d003 beq.n 8006260 <TIM_Base_SetConfig+0x30>
8006258: 687b ldr r3, [r7, #4]
800625a: 4a2b ldr r2, [pc, #172] @ (8006308 <TIM_Base_SetConfig+0xd8>)
800625c: 4293 cmp r3, r2
800625e: d108 bne.n 8006272 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8006260: 68fb ldr r3, [r7, #12]
8006262: f023 0370 bic.w r3, r3, #112 @ 0x70
8006266: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8006268: 683b ldr r3, [r7, #0]
800626a: 685b ldr r3, [r3, #4]
800626c: 68fa ldr r2, [r7, #12]
800626e: 4313 orrs r3, r2
8006270: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8006272: 687b ldr r3, [r7, #4]
8006274: 4a22 ldr r2, [pc, #136] @ (8006300 <TIM_Base_SetConfig+0xd0>)
8006276: 4293 cmp r3, r2
8006278: d00b beq.n 8006292 <TIM_Base_SetConfig+0x62>
800627a: 687b ldr r3, [r7, #4]
800627c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8006280: d007 beq.n 8006292 <TIM_Base_SetConfig+0x62>
8006282: 687b ldr r3, [r7, #4]
8006284: 4a1f ldr r2, [pc, #124] @ (8006304 <TIM_Base_SetConfig+0xd4>)
8006286: 4293 cmp r3, r2
8006288: d003 beq.n 8006292 <TIM_Base_SetConfig+0x62>
800628a: 687b ldr r3, [r7, #4]
800628c: 4a1e ldr r2, [pc, #120] @ (8006308 <TIM_Base_SetConfig+0xd8>)
800628e: 4293 cmp r3, r2
8006290: d108 bne.n 80062a4 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8006292: 68fb ldr r3, [r7, #12]
8006294: f423 7340 bic.w r3, r3, #768 @ 0x300
8006298: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800629a: 683b ldr r3, [r7, #0]
800629c: 68db ldr r3, [r3, #12]
800629e: 68fa ldr r2, [r7, #12]
80062a0: 4313 orrs r3, r2
80062a2: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80062a4: 68fb ldr r3, [r7, #12]
80062a6: f023 0280 bic.w r2, r3, #128 @ 0x80
80062aa: 683b ldr r3, [r7, #0]
80062ac: 695b ldr r3, [r3, #20]
80062ae: 4313 orrs r3, r2
80062b0: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80062b2: 687b ldr r3, [r7, #4]
80062b4: 68fa ldr r2, [r7, #12]
80062b6: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80062b8: 683b ldr r3, [r7, #0]
80062ba: 689a ldr r2, [r3, #8]
80062bc: 687b ldr r3, [r7, #4]
80062be: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80062c0: 683b ldr r3, [r7, #0]
80062c2: 681a ldr r2, [r3, #0]
80062c4: 687b ldr r3, [r7, #4]
80062c6: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80062c8: 687b ldr r3, [r7, #4]
80062ca: 4a0d ldr r2, [pc, #52] @ (8006300 <TIM_Base_SetConfig+0xd0>)
80062cc: 4293 cmp r3, r2
80062ce: d103 bne.n 80062d8 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80062d0: 683b ldr r3, [r7, #0]
80062d2: 691a ldr r2, [r3, #16]
80062d4: 687b ldr r3, [r7, #4]
80062d6: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80062d8: 687b ldr r3, [r7, #4]
80062da: 2201 movs r2, #1
80062dc: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
80062de: 687b ldr r3, [r7, #4]
80062e0: 691b ldr r3, [r3, #16]
80062e2: f003 0301 and.w r3, r3, #1
80062e6: 2b00 cmp r3, #0
80062e8: d005 beq.n 80062f6 <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
80062ea: 687b ldr r3, [r7, #4]
80062ec: 691b ldr r3, [r3, #16]
80062ee: f023 0201 bic.w r2, r3, #1
80062f2: 687b ldr r3, [r7, #4]
80062f4: 611a str r2, [r3, #16]
}
}
80062f6: bf00 nop
80062f8: 3714 adds r7, #20
80062fa: 46bd mov sp, r7
80062fc: bc80 pop {r7}
80062fe: 4770 bx lr
8006300: 40012c00 .word 0x40012c00
8006304: 40000400 .word 0x40000400
8006308: 40000800 .word 0x40000800
0800630c <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800630c: b480 push {r7}
800630e: b087 sub sp, #28
8006310: af00 add r7, sp, #0
8006312: 6078 str r0, [r7, #4]
8006314: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8006316: 687b ldr r3, [r7, #4]
8006318: 6a1b ldr r3, [r3, #32]
800631a: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
800631c: 687b ldr r3, [r7, #4]
800631e: 6a1b ldr r3, [r3, #32]
8006320: f023 0201 bic.w r2, r3, #1
8006324: 687b ldr r3, [r7, #4]
8006326: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8006328: 687b ldr r3, [r7, #4]
800632a: 685b ldr r3, [r3, #4]
800632c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800632e: 687b ldr r3, [r7, #4]
8006330: 699b ldr r3, [r3, #24]
8006332: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8006334: 68fb ldr r3, [r7, #12]
8006336: f023 0370 bic.w r3, r3, #112 @ 0x70
800633a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800633c: 68fb ldr r3, [r7, #12]
800633e: f023 0303 bic.w r3, r3, #3
8006342: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8006344: 683b ldr r3, [r7, #0]
8006346: 681b ldr r3, [r3, #0]
8006348: 68fa ldr r2, [r7, #12]
800634a: 4313 orrs r3, r2
800634c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800634e: 697b ldr r3, [r7, #20]
8006350: f023 0302 bic.w r3, r3, #2
8006354: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8006356: 683b ldr r3, [r7, #0]
8006358: 689b ldr r3, [r3, #8]
800635a: 697a ldr r2, [r7, #20]
800635c: 4313 orrs r3, r2
800635e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8006360: 687b ldr r3, [r7, #4]
8006362: 4a1c ldr r2, [pc, #112] @ (80063d4 <TIM_OC1_SetConfig+0xc8>)
8006364: 4293 cmp r3, r2
8006366: d10c bne.n 8006382 <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8006368: 697b ldr r3, [r7, #20]
800636a: f023 0308 bic.w r3, r3, #8
800636e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8006370: 683b ldr r3, [r7, #0]
8006372: 68db ldr r3, [r3, #12]
8006374: 697a ldr r2, [r7, #20]
8006376: 4313 orrs r3, r2
8006378: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800637a: 697b ldr r3, [r7, #20]
800637c: f023 0304 bic.w r3, r3, #4
8006380: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8006382: 687b ldr r3, [r7, #4]
8006384: 4a13 ldr r2, [pc, #76] @ (80063d4 <TIM_OC1_SetConfig+0xc8>)
8006386: 4293 cmp r3, r2
8006388: d111 bne.n 80063ae <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800638a: 693b ldr r3, [r7, #16]
800638c: f423 7380 bic.w r3, r3, #256 @ 0x100
8006390: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8006392: 693b ldr r3, [r7, #16]
8006394: f423 7300 bic.w r3, r3, #512 @ 0x200
8006398: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800639a: 683b ldr r3, [r7, #0]
800639c: 695b ldr r3, [r3, #20]
800639e: 693a ldr r2, [r7, #16]
80063a0: 4313 orrs r3, r2
80063a2: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
80063a4: 683b ldr r3, [r7, #0]
80063a6: 699b ldr r3, [r3, #24]
80063a8: 693a ldr r2, [r7, #16]
80063aa: 4313 orrs r3, r2
80063ac: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80063ae: 687b ldr r3, [r7, #4]
80063b0: 693a ldr r2, [r7, #16]
80063b2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80063b4: 687b ldr r3, [r7, #4]
80063b6: 68fa ldr r2, [r7, #12]
80063b8: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80063ba: 683b ldr r3, [r7, #0]
80063bc: 685a ldr r2, [r3, #4]
80063be: 687b ldr r3, [r7, #4]
80063c0: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80063c2: 687b ldr r3, [r7, #4]
80063c4: 697a ldr r2, [r7, #20]
80063c6: 621a str r2, [r3, #32]
}
80063c8: bf00 nop
80063ca: 371c adds r7, #28
80063cc: 46bd mov sp, r7
80063ce: bc80 pop {r7}
80063d0: 4770 bx lr
80063d2: bf00 nop
80063d4: 40012c00 .word 0x40012c00
080063d8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80063d8: b480 push {r7}
80063da: b087 sub sp, #28
80063dc: af00 add r7, sp, #0
80063de: 6078 str r0, [r7, #4]
80063e0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80063e2: 687b ldr r3, [r7, #4]
80063e4: 6a1b ldr r3, [r3, #32]
80063e6: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80063e8: 687b ldr r3, [r7, #4]
80063ea: 6a1b ldr r3, [r3, #32]
80063ec: f023 0210 bic.w r2, r3, #16
80063f0: 687b ldr r3, [r7, #4]
80063f2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80063f4: 687b ldr r3, [r7, #4]
80063f6: 685b ldr r3, [r3, #4]
80063f8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80063fa: 687b ldr r3, [r7, #4]
80063fc: 699b ldr r3, [r3, #24]
80063fe: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8006400: 68fb ldr r3, [r7, #12]
8006402: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006406: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8006408: 68fb ldr r3, [r7, #12]
800640a: f423 7340 bic.w r3, r3, #768 @ 0x300
800640e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8006410: 683b ldr r3, [r7, #0]
8006412: 681b ldr r3, [r3, #0]
8006414: 021b lsls r3, r3, #8
8006416: 68fa ldr r2, [r7, #12]
8006418: 4313 orrs r3, r2
800641a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800641c: 697b ldr r3, [r7, #20]
800641e: f023 0320 bic.w r3, r3, #32
8006422: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8006424: 683b ldr r3, [r7, #0]
8006426: 689b ldr r3, [r3, #8]
8006428: 011b lsls r3, r3, #4
800642a: 697a ldr r2, [r7, #20]
800642c: 4313 orrs r3, r2
800642e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8006430: 687b ldr r3, [r7, #4]
8006432: 4a1d ldr r2, [pc, #116] @ (80064a8 <TIM_OC2_SetConfig+0xd0>)
8006434: 4293 cmp r3, r2
8006436: d10d bne.n 8006454 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8006438: 697b ldr r3, [r7, #20]
800643a: f023 0380 bic.w r3, r3, #128 @ 0x80
800643e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8006440: 683b ldr r3, [r7, #0]
8006442: 68db ldr r3, [r3, #12]
8006444: 011b lsls r3, r3, #4
8006446: 697a ldr r2, [r7, #20]
8006448: 4313 orrs r3, r2
800644a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
800644c: 697b ldr r3, [r7, #20]
800644e: f023 0340 bic.w r3, r3, #64 @ 0x40
8006452: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8006454: 687b ldr r3, [r7, #4]
8006456: 4a14 ldr r2, [pc, #80] @ (80064a8 <TIM_OC2_SetConfig+0xd0>)
8006458: 4293 cmp r3, r2
800645a: d113 bne.n 8006484 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
800645c: 693b ldr r3, [r7, #16]
800645e: f423 6380 bic.w r3, r3, #1024 @ 0x400
8006462: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8006464: 693b ldr r3, [r7, #16]
8006466: f423 6300 bic.w r3, r3, #2048 @ 0x800
800646a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
800646c: 683b ldr r3, [r7, #0]
800646e: 695b ldr r3, [r3, #20]
8006470: 009b lsls r3, r3, #2
8006472: 693a ldr r2, [r7, #16]
8006474: 4313 orrs r3, r2
8006476: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8006478: 683b ldr r3, [r7, #0]
800647a: 699b ldr r3, [r3, #24]
800647c: 009b lsls r3, r3, #2
800647e: 693a ldr r2, [r7, #16]
8006480: 4313 orrs r3, r2
8006482: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8006484: 687b ldr r3, [r7, #4]
8006486: 693a ldr r2, [r7, #16]
8006488: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800648a: 687b ldr r3, [r7, #4]
800648c: 68fa ldr r2, [r7, #12]
800648e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8006490: 683b ldr r3, [r7, #0]
8006492: 685a ldr r2, [r3, #4]
8006494: 687b ldr r3, [r7, #4]
8006496: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8006498: 687b ldr r3, [r7, #4]
800649a: 697a ldr r2, [r7, #20]
800649c: 621a str r2, [r3, #32]
}
800649e: bf00 nop
80064a0: 371c adds r7, #28
80064a2: 46bd mov sp, r7
80064a4: bc80 pop {r7}
80064a6: 4770 bx lr
80064a8: 40012c00 .word 0x40012c00
080064ac <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80064ac: b480 push {r7}
80064ae: b087 sub sp, #28
80064b0: af00 add r7, sp, #0
80064b2: 6078 str r0, [r7, #4]
80064b4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80064b6: 687b ldr r3, [r7, #4]
80064b8: 6a1b ldr r3, [r3, #32]
80064ba: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
80064bc: 687b ldr r3, [r7, #4]
80064be: 6a1b ldr r3, [r3, #32]
80064c0: f423 7280 bic.w r2, r3, #256 @ 0x100
80064c4: 687b ldr r3, [r7, #4]
80064c6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80064c8: 687b ldr r3, [r7, #4]
80064ca: 685b ldr r3, [r3, #4]
80064cc: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80064ce: 687b ldr r3, [r7, #4]
80064d0: 69db ldr r3, [r3, #28]
80064d2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
80064d4: 68fb ldr r3, [r7, #12]
80064d6: f023 0370 bic.w r3, r3, #112 @ 0x70
80064da: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80064dc: 68fb ldr r3, [r7, #12]
80064de: f023 0303 bic.w r3, r3, #3
80064e2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80064e4: 683b ldr r3, [r7, #0]
80064e6: 681b ldr r3, [r3, #0]
80064e8: 68fa ldr r2, [r7, #12]
80064ea: 4313 orrs r3, r2
80064ec: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80064ee: 697b ldr r3, [r7, #20]
80064f0: f423 7300 bic.w r3, r3, #512 @ 0x200
80064f4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80064f6: 683b ldr r3, [r7, #0]
80064f8: 689b ldr r3, [r3, #8]
80064fa: 021b lsls r3, r3, #8
80064fc: 697a ldr r2, [r7, #20]
80064fe: 4313 orrs r3, r2
8006500: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8006502: 687b ldr r3, [r7, #4]
8006504: 4a1d ldr r2, [pc, #116] @ (800657c <TIM_OC3_SetConfig+0xd0>)
8006506: 4293 cmp r3, r2
8006508: d10d bne.n 8006526 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800650a: 697b ldr r3, [r7, #20]
800650c: f423 6300 bic.w r3, r3, #2048 @ 0x800
8006510: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8006512: 683b ldr r3, [r7, #0]
8006514: 68db ldr r3, [r3, #12]
8006516: 021b lsls r3, r3, #8
8006518: 697a ldr r2, [r7, #20]
800651a: 4313 orrs r3, r2
800651c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800651e: 697b ldr r3, [r7, #20]
8006520: f423 6380 bic.w r3, r3, #1024 @ 0x400
8006524: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8006526: 687b ldr r3, [r7, #4]
8006528: 4a14 ldr r2, [pc, #80] @ (800657c <TIM_OC3_SetConfig+0xd0>)
800652a: 4293 cmp r3, r2
800652c: d113 bne.n 8006556 <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800652e: 693b ldr r3, [r7, #16]
8006530: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8006534: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8006536: 693b ldr r3, [r7, #16]
8006538: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800653c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800653e: 683b ldr r3, [r7, #0]
8006540: 695b ldr r3, [r3, #20]
8006542: 011b lsls r3, r3, #4
8006544: 693a ldr r2, [r7, #16]
8006546: 4313 orrs r3, r2
8006548: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800654a: 683b ldr r3, [r7, #0]
800654c: 699b ldr r3, [r3, #24]
800654e: 011b lsls r3, r3, #4
8006550: 693a ldr r2, [r7, #16]
8006552: 4313 orrs r3, r2
8006554: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8006556: 687b ldr r3, [r7, #4]
8006558: 693a ldr r2, [r7, #16]
800655a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800655c: 687b ldr r3, [r7, #4]
800655e: 68fa ldr r2, [r7, #12]
8006560: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8006562: 683b ldr r3, [r7, #0]
8006564: 685a ldr r2, [r3, #4]
8006566: 687b ldr r3, [r7, #4]
8006568: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800656a: 687b ldr r3, [r7, #4]
800656c: 697a ldr r2, [r7, #20]
800656e: 621a str r2, [r3, #32]
}
8006570: bf00 nop
8006572: 371c adds r7, #28
8006574: 46bd mov sp, r7
8006576: bc80 pop {r7}
8006578: 4770 bx lr
800657a: bf00 nop
800657c: 40012c00 .word 0x40012c00
08006580 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8006580: b480 push {r7}
8006582: b087 sub sp, #28
8006584: af00 add r7, sp, #0
8006586: 6078 str r0, [r7, #4]
8006588: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800658a: 687b ldr r3, [r7, #4]
800658c: 6a1b ldr r3, [r3, #32]
800658e: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8006590: 687b ldr r3, [r7, #4]
8006592: 6a1b ldr r3, [r3, #32]
8006594: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8006598: 687b ldr r3, [r7, #4]
800659a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800659c: 687b ldr r3, [r7, #4]
800659e: 685b ldr r3, [r3, #4]
80065a0: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80065a2: 687b ldr r3, [r7, #4]
80065a4: 69db ldr r3, [r3, #28]
80065a6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
80065a8: 68fb ldr r3, [r7, #12]
80065aa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80065ae: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80065b0: 68fb ldr r3, [r7, #12]
80065b2: f423 7340 bic.w r3, r3, #768 @ 0x300
80065b6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80065b8: 683b ldr r3, [r7, #0]
80065ba: 681b ldr r3, [r3, #0]
80065bc: 021b lsls r3, r3, #8
80065be: 68fa ldr r2, [r7, #12]
80065c0: 4313 orrs r3, r2
80065c2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80065c4: 693b ldr r3, [r7, #16]
80065c6: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80065ca: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80065cc: 683b ldr r3, [r7, #0]
80065ce: 689b ldr r3, [r3, #8]
80065d0: 031b lsls r3, r3, #12
80065d2: 693a ldr r2, [r7, #16]
80065d4: 4313 orrs r3, r2
80065d6: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80065d8: 687b ldr r3, [r7, #4]
80065da: 4a0f ldr r2, [pc, #60] @ (8006618 <TIM_OC4_SetConfig+0x98>)
80065dc: 4293 cmp r3, r2
80065de: d109 bne.n 80065f4 <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80065e0: 697b ldr r3, [r7, #20]
80065e2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80065e6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80065e8: 683b ldr r3, [r7, #0]
80065ea: 695b ldr r3, [r3, #20]
80065ec: 019b lsls r3, r3, #6
80065ee: 697a ldr r2, [r7, #20]
80065f0: 4313 orrs r3, r2
80065f2: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80065f4: 687b ldr r3, [r7, #4]
80065f6: 697a ldr r2, [r7, #20]
80065f8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80065fa: 687b ldr r3, [r7, #4]
80065fc: 68fa ldr r2, [r7, #12]
80065fe: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8006600: 683b ldr r3, [r7, #0]
8006602: 685a ldr r2, [r3, #4]
8006604: 687b ldr r3, [r7, #4]
8006606: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8006608: 687b ldr r3, [r7, #4]
800660a: 693a ldr r2, [r7, #16]
800660c: 621a str r2, [r3, #32]
}
800660e: bf00 nop
8006610: 371c adds r7, #28
8006612: 46bd mov sp, r7
8006614: bc80 pop {r7}
8006616: 4770 bx lr
8006618: 40012c00 .word 0x40012c00
0800661c <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800661c: b480 push {r7}
800661e: b087 sub sp, #28
8006620: af00 add r7, sp, #0
8006622: 60f8 str r0, [r7, #12]
8006624: 60b9 str r1, [r7, #8]
8006626: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8006628: 68fb ldr r3, [r7, #12]
800662a: 6a1b ldr r3, [r3, #32]
800662c: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
800662e: 68fb ldr r3, [r7, #12]
8006630: 6a1b ldr r3, [r3, #32]
8006632: f023 0201 bic.w r2, r3, #1
8006636: 68fb ldr r3, [r7, #12]
8006638: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800663a: 68fb ldr r3, [r7, #12]
800663c: 699b ldr r3, [r3, #24]
800663e: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8006640: 693b ldr r3, [r7, #16]
8006642: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8006646: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8006648: 687b ldr r3, [r7, #4]
800664a: 011b lsls r3, r3, #4
800664c: 693a ldr r2, [r7, #16]
800664e: 4313 orrs r3, r2
8006650: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8006652: 697b ldr r3, [r7, #20]
8006654: f023 030a bic.w r3, r3, #10
8006658: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800665a: 697a ldr r2, [r7, #20]
800665c: 68bb ldr r3, [r7, #8]
800665e: 4313 orrs r3, r2
8006660: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8006662: 68fb ldr r3, [r7, #12]
8006664: 693a ldr r2, [r7, #16]
8006666: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8006668: 68fb ldr r3, [r7, #12]
800666a: 697a ldr r2, [r7, #20]
800666c: 621a str r2, [r3, #32]
}
800666e: bf00 nop
8006670: 371c adds r7, #28
8006672: 46bd mov sp, r7
8006674: bc80 pop {r7}
8006676: 4770 bx lr
08006678 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8006678: b480 push {r7}
800667a: b087 sub sp, #28
800667c: af00 add r7, sp, #0
800667e: 60f8 str r0, [r7, #12]
8006680: 60b9 str r1, [r7, #8]
8006682: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8006684: 68fb ldr r3, [r7, #12]
8006686: 6a1b ldr r3, [r3, #32]
8006688: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
800668a: 68fb ldr r3, [r7, #12]
800668c: 6a1b ldr r3, [r3, #32]
800668e: f023 0210 bic.w r2, r3, #16
8006692: 68fb ldr r3, [r7, #12]
8006694: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8006696: 68fb ldr r3, [r7, #12]
8006698: 699b ldr r3, [r3, #24]
800669a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800669c: 693b ldr r3, [r7, #16]
800669e: f423 4370 bic.w r3, r3, #61440 @ 0xf000
80066a2: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
80066a4: 687b ldr r3, [r7, #4]
80066a6: 031b lsls r3, r3, #12
80066a8: 693a ldr r2, [r7, #16]
80066aa: 4313 orrs r3, r2
80066ac: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80066ae: 697b ldr r3, [r7, #20]
80066b0: f023 03a0 bic.w r3, r3, #160 @ 0xa0
80066b4: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
80066b6: 68bb ldr r3, [r7, #8]
80066b8: 011b lsls r3, r3, #4
80066ba: 697a ldr r2, [r7, #20]
80066bc: 4313 orrs r3, r2
80066be: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80066c0: 68fb ldr r3, [r7, #12]
80066c2: 693a ldr r2, [r7, #16]
80066c4: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80066c6: 68fb ldr r3, [r7, #12]
80066c8: 697a ldr r2, [r7, #20]
80066ca: 621a str r2, [r3, #32]
}
80066cc: bf00 nop
80066ce: 371c adds r7, #28
80066d0: 46bd mov sp, r7
80066d2: bc80 pop {r7}
80066d4: 4770 bx lr
080066d6 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80066d6: b480 push {r7}
80066d8: b085 sub sp, #20
80066da: af00 add r7, sp, #0
80066dc: 6078 str r0, [r7, #4]
80066de: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80066e0: 687b ldr r3, [r7, #4]
80066e2: 689b ldr r3, [r3, #8]
80066e4: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80066e6: 68fb ldr r3, [r7, #12]
80066e8: f023 0370 bic.w r3, r3, #112 @ 0x70
80066ec: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80066ee: 683a ldr r2, [r7, #0]
80066f0: 68fb ldr r3, [r7, #12]
80066f2: 4313 orrs r3, r2
80066f4: f043 0307 orr.w r3, r3, #7
80066f8: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80066fa: 687b ldr r3, [r7, #4]
80066fc: 68fa ldr r2, [r7, #12]
80066fe: 609a str r2, [r3, #8]
}
8006700: bf00 nop
8006702: 3714 adds r7, #20
8006704: 46bd mov sp, r7
8006706: bc80 pop {r7}
8006708: 4770 bx lr
0800670a <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800670a: b480 push {r7}
800670c: b087 sub sp, #28
800670e: af00 add r7, sp, #0
8006710: 60f8 str r0, [r7, #12]
8006712: 60b9 str r1, [r7, #8]
8006714: 607a str r2, [r7, #4]
8006716: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8006718: 68fb ldr r3, [r7, #12]
800671a: 689b ldr r3, [r3, #8]
800671c: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800671e: 697b ldr r3, [r7, #20]
8006720: f423 437f bic.w r3, r3, #65280 @ 0xff00
8006724: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8006726: 683b ldr r3, [r7, #0]
8006728: 021a lsls r2, r3, #8
800672a: 687b ldr r3, [r7, #4]
800672c: 431a orrs r2, r3
800672e: 68bb ldr r3, [r7, #8]
8006730: 4313 orrs r3, r2
8006732: 697a ldr r2, [r7, #20]
8006734: 4313 orrs r3, r2
8006736: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8006738: 68fb ldr r3, [r7, #12]
800673a: 697a ldr r2, [r7, #20]
800673c: 609a str r2, [r3, #8]
}
800673e: bf00 nop
8006740: 371c adds r7, #28
8006742: 46bd mov sp, r7
8006744: bc80 pop {r7}
8006746: 4770 bx lr
08006748 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8006748: b480 push {r7}
800674a: b087 sub sp, #28
800674c: af00 add r7, sp, #0
800674e: 60f8 str r0, [r7, #12]
8006750: 60b9 str r1, [r7, #8]
8006752: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8006754: 68bb ldr r3, [r7, #8]
8006756: f003 031f and.w r3, r3, #31
800675a: 2201 movs r2, #1
800675c: fa02 f303 lsl.w r3, r2, r3
8006760: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8006762: 68fb ldr r3, [r7, #12]
8006764: 6a1a ldr r2, [r3, #32]
8006766: 697b ldr r3, [r7, #20]
8006768: 43db mvns r3, r3
800676a: 401a ands r2, r3
800676c: 68fb ldr r3, [r7, #12]
800676e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8006770: 68fb ldr r3, [r7, #12]
8006772: 6a1a ldr r2, [r3, #32]
8006774: 68bb ldr r3, [r7, #8]
8006776: f003 031f and.w r3, r3, #31
800677a: 6879 ldr r1, [r7, #4]
800677c: fa01 f303 lsl.w r3, r1, r3
8006780: 431a orrs r2, r3
8006782: 68fb ldr r3, [r7, #12]
8006784: 621a str r2, [r3, #32]
}
8006786: bf00 nop
8006788: 371c adds r7, #28
800678a: 46bd mov sp, r7
800678c: bc80 pop {r7}
800678e: 4770 bx lr
08006790 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8006790: b480 push {r7}
8006792: b085 sub sp, #20
8006794: af00 add r7, sp, #0
8006796: 6078 str r0, [r7, #4]
8006798: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800679a: 687b ldr r3, [r7, #4]
800679c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80067a0: 2b01 cmp r3, #1
80067a2: d101 bne.n 80067a8 <HAL_TIMEx_MasterConfigSynchronization+0x18>
80067a4: 2302 movs r3, #2
80067a6: e046 b.n 8006836 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
80067a8: 687b ldr r3, [r7, #4]
80067aa: 2201 movs r2, #1
80067ac: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80067b0: 687b ldr r3, [r7, #4]
80067b2: 2202 movs r2, #2
80067b4: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80067b8: 687b ldr r3, [r7, #4]
80067ba: 681b ldr r3, [r3, #0]
80067bc: 685b ldr r3, [r3, #4]
80067be: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80067c0: 687b ldr r3, [r7, #4]
80067c2: 681b ldr r3, [r3, #0]
80067c4: 689b ldr r3, [r3, #8]
80067c6: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80067c8: 68fb ldr r3, [r7, #12]
80067ca: f023 0370 bic.w r3, r3, #112 @ 0x70
80067ce: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80067d0: 683b ldr r3, [r7, #0]
80067d2: 681b ldr r3, [r3, #0]
80067d4: 68fa ldr r2, [r7, #12]
80067d6: 4313 orrs r3, r2
80067d8: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80067da: 687b ldr r3, [r7, #4]
80067dc: 681b ldr r3, [r3, #0]
80067de: 68fa ldr r2, [r7, #12]
80067e0: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80067e2: 687b ldr r3, [r7, #4]
80067e4: 681b ldr r3, [r3, #0]
80067e6: 4a16 ldr r2, [pc, #88] @ (8006840 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
80067e8: 4293 cmp r3, r2
80067ea: d00e beq.n 800680a <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80067ec: 687b ldr r3, [r7, #4]
80067ee: 681b ldr r3, [r3, #0]
80067f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80067f4: d009 beq.n 800680a <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80067f6: 687b ldr r3, [r7, #4]
80067f8: 681b ldr r3, [r3, #0]
80067fa: 4a12 ldr r2, [pc, #72] @ (8006844 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
80067fc: 4293 cmp r3, r2
80067fe: d004 beq.n 800680a <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8006800: 687b ldr r3, [r7, #4]
8006802: 681b ldr r3, [r3, #0]
8006804: 4a10 ldr r2, [pc, #64] @ (8006848 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8006806: 4293 cmp r3, r2
8006808: d10c bne.n 8006824 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800680a: 68bb ldr r3, [r7, #8]
800680c: f023 0380 bic.w r3, r3, #128 @ 0x80
8006810: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8006812: 683b ldr r3, [r7, #0]
8006814: 685b ldr r3, [r3, #4]
8006816: 68ba ldr r2, [r7, #8]
8006818: 4313 orrs r3, r2
800681a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800681c: 687b ldr r3, [r7, #4]
800681e: 681b ldr r3, [r3, #0]
8006820: 68ba ldr r2, [r7, #8]
8006822: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8006824: 687b ldr r3, [r7, #4]
8006826: 2201 movs r2, #1
8006828: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
800682c: 687b ldr r3, [r7, #4]
800682e: 2200 movs r2, #0
8006830: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8006834: 2300 movs r3, #0
}
8006836: 4618 mov r0, r3
8006838: 3714 adds r7, #20
800683a: 46bd mov sp, r7
800683c: bc80 pop {r7}
800683e: 4770 bx lr
8006840: 40012c00 .word 0x40012c00
8006844: 40000400 .word 0x40000400
8006848: 40000800 .word 0x40000800
0800684c <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800684c: b580 push {r7, lr}
800684e: b082 sub sp, #8
8006850: af00 add r7, sp, #0
8006852: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8006854: 687b ldr r3, [r7, #4]
8006856: 2b00 cmp r3, #0
8006858: d101 bne.n 800685e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800685a: 2301 movs r3, #1
800685c: e042 b.n 80068e4 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
800685e: 687b ldr r3, [r7, #4]
8006860: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006864: b2db uxtb r3, r3
8006866: 2b00 cmp r3, #0
8006868: d106 bne.n 8006878 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800686a: 687b ldr r3, [r7, #4]
800686c: 2200 movs r2, #0
800686e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8006872: 6878 ldr r0, [r7, #4]
8006874: f7fb fb6a bl 8001f4c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8006878: 687b ldr r3, [r7, #4]
800687a: 2224 movs r2, #36 @ 0x24
800687c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8006880: 687b ldr r3, [r7, #4]
8006882: 681b ldr r3, [r3, #0]
8006884: 68da ldr r2, [r3, #12]
8006886: 687b ldr r3, [r7, #4]
8006888: 681b ldr r3, [r3, #0]
800688a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800688e: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8006890: 6878 ldr r0, [r7, #4]
8006892: f000 f82b bl 80068ec <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8006896: 687b ldr r3, [r7, #4]
8006898: 681b ldr r3, [r3, #0]
800689a: 691a ldr r2, [r3, #16]
800689c: 687b ldr r3, [r7, #4]
800689e: 681b ldr r3, [r3, #0]
80068a0: f422 4290 bic.w r2, r2, #18432 @ 0x4800
80068a4: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80068a6: 687b ldr r3, [r7, #4]
80068a8: 681b ldr r3, [r3, #0]
80068aa: 695a ldr r2, [r3, #20]
80068ac: 687b ldr r3, [r7, #4]
80068ae: 681b ldr r3, [r3, #0]
80068b0: f022 022a bic.w r2, r2, #42 @ 0x2a
80068b4: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
80068b6: 687b ldr r3, [r7, #4]
80068b8: 681b ldr r3, [r3, #0]
80068ba: 68da ldr r2, [r3, #12]
80068bc: 687b ldr r3, [r7, #4]
80068be: 681b ldr r3, [r3, #0]
80068c0: f442 5200 orr.w r2, r2, #8192 @ 0x2000
80068c4: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80068c6: 687b ldr r3, [r7, #4]
80068c8: 2200 movs r2, #0
80068ca: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
80068cc: 687b ldr r3, [r7, #4]
80068ce: 2220 movs r2, #32
80068d0: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
80068d4: 687b ldr r3, [r7, #4]
80068d6: 2220 movs r2, #32
80068d8: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
80068dc: 687b ldr r3, [r7, #4]
80068de: 2200 movs r2, #0
80068e0: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
80068e2: 2300 movs r3, #0
}
80068e4: 4618 mov r0, r3
80068e6: 3708 adds r7, #8
80068e8: 46bd mov sp, r7
80068ea: bd80 pop {r7, pc}
080068ec <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
80068ec: b580 push {r7, lr}
80068ee: b084 sub sp, #16
80068f0: af00 add r7, sp, #0
80068f2: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80068f4: 687b ldr r3, [r7, #4]
80068f6: 681b ldr r3, [r3, #0]
80068f8: 691b ldr r3, [r3, #16]
80068fa: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80068fe: 687b ldr r3, [r7, #4]
8006900: 68da ldr r2, [r3, #12]
8006902: 687b ldr r3, [r7, #4]
8006904: 681b ldr r3, [r3, #0]
8006906: 430a orrs r2, r1
8006908: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
800690a: 687b ldr r3, [r7, #4]
800690c: 689a ldr r2, [r3, #8]
800690e: 687b ldr r3, [r7, #4]
8006910: 691b ldr r3, [r3, #16]
8006912: 431a orrs r2, r3
8006914: 687b ldr r3, [r7, #4]
8006916: 695b ldr r3, [r3, #20]
8006918: 4313 orrs r3, r2
800691a: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
800691c: 687b ldr r3, [r7, #4]
800691e: 681b ldr r3, [r3, #0]
8006920: 68db ldr r3, [r3, #12]
8006922: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
8006926: f023 030c bic.w r3, r3, #12
800692a: 687a ldr r2, [r7, #4]
800692c: 6812 ldr r2, [r2, #0]
800692e: 68b9 ldr r1, [r7, #8]
8006930: 430b orrs r3, r1
8006932: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8006934: 687b ldr r3, [r7, #4]
8006936: 681b ldr r3, [r3, #0]
8006938: 695b ldr r3, [r3, #20]
800693a: f423 7140 bic.w r1, r3, #768 @ 0x300
800693e: 687b ldr r3, [r7, #4]
8006940: 699a ldr r2, [r3, #24]
8006942: 687b ldr r3, [r7, #4]
8006944: 681b ldr r3, [r3, #0]
8006946: 430a orrs r2, r1
8006948: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
800694a: 687b ldr r3, [r7, #4]
800694c: 681b ldr r3, [r3, #0]
800694e: 4a2c ldr r2, [pc, #176] @ (8006a00 <UART_SetConfig+0x114>)
8006950: 4293 cmp r3, r2
8006952: d103 bne.n 800695c <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8006954: f7ff f824 bl 80059a0 <HAL_RCC_GetPCLK2Freq>
8006958: 60f8 str r0, [r7, #12]
800695a: e002 b.n 8006962 <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800695c: f7ff f80c bl 8005978 <HAL_RCC_GetPCLK1Freq>
8006960: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8006962: 68fa ldr r2, [r7, #12]
8006964: 4613 mov r3, r2
8006966: 009b lsls r3, r3, #2
8006968: 4413 add r3, r2
800696a: 009a lsls r2, r3, #2
800696c: 441a add r2, r3
800696e: 687b ldr r3, [r7, #4]
8006970: 685b ldr r3, [r3, #4]
8006972: 009b lsls r3, r3, #2
8006974: fbb2 f3f3 udiv r3, r2, r3
8006978: 4a22 ldr r2, [pc, #136] @ (8006a04 <UART_SetConfig+0x118>)
800697a: fba2 2303 umull r2, r3, r2, r3
800697e: 095b lsrs r3, r3, #5
8006980: 0119 lsls r1, r3, #4
8006982: 68fa ldr r2, [r7, #12]
8006984: 4613 mov r3, r2
8006986: 009b lsls r3, r3, #2
8006988: 4413 add r3, r2
800698a: 009a lsls r2, r3, #2
800698c: 441a add r2, r3
800698e: 687b ldr r3, [r7, #4]
8006990: 685b ldr r3, [r3, #4]
8006992: 009b lsls r3, r3, #2
8006994: fbb2 f2f3 udiv r2, r2, r3
8006998: 4b1a ldr r3, [pc, #104] @ (8006a04 <UART_SetConfig+0x118>)
800699a: fba3 0302 umull r0, r3, r3, r2
800699e: 095b lsrs r3, r3, #5
80069a0: 2064 movs r0, #100 @ 0x64
80069a2: fb00 f303 mul.w r3, r0, r3
80069a6: 1ad3 subs r3, r2, r3
80069a8: 011b lsls r3, r3, #4
80069aa: 3332 adds r3, #50 @ 0x32
80069ac: 4a15 ldr r2, [pc, #84] @ (8006a04 <UART_SetConfig+0x118>)
80069ae: fba2 2303 umull r2, r3, r2, r3
80069b2: 095b lsrs r3, r3, #5
80069b4: f003 03f0 and.w r3, r3, #240 @ 0xf0
80069b8: 4419 add r1, r3
80069ba: 68fa ldr r2, [r7, #12]
80069bc: 4613 mov r3, r2
80069be: 009b lsls r3, r3, #2
80069c0: 4413 add r3, r2
80069c2: 009a lsls r2, r3, #2
80069c4: 441a add r2, r3
80069c6: 687b ldr r3, [r7, #4]
80069c8: 685b ldr r3, [r3, #4]
80069ca: 009b lsls r3, r3, #2
80069cc: fbb2 f2f3 udiv r2, r2, r3
80069d0: 4b0c ldr r3, [pc, #48] @ (8006a04 <UART_SetConfig+0x118>)
80069d2: fba3 0302 umull r0, r3, r3, r2
80069d6: 095b lsrs r3, r3, #5
80069d8: 2064 movs r0, #100 @ 0x64
80069da: fb00 f303 mul.w r3, r0, r3
80069de: 1ad3 subs r3, r2, r3
80069e0: 011b lsls r3, r3, #4
80069e2: 3332 adds r3, #50 @ 0x32
80069e4: 4a07 ldr r2, [pc, #28] @ (8006a04 <UART_SetConfig+0x118>)
80069e6: fba2 2303 umull r2, r3, r2, r3
80069ea: 095b lsrs r3, r3, #5
80069ec: f003 020f and.w r2, r3, #15
80069f0: 687b ldr r3, [r7, #4]
80069f2: 681b ldr r3, [r3, #0]
80069f4: 440a add r2, r1
80069f6: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
80069f8: bf00 nop
80069fa: 3710 adds r7, #16
80069fc: 46bd mov sp, r7
80069fe: bd80 pop {r7, pc}
8006a00: 40013800 .word 0x40013800
8006a04: 51eb851f .word 0x51eb851f
08006a08 <USB_CoreInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8006a08: b480 push {r7}
8006a0a: b085 sub sp, #20
8006a0c: af00 add r7, sp, #0
8006a0e: 60f8 str r0, [r7, #12]
8006a10: 4638 mov r0, r7
8006a12: e880 000e stmia.w r0, {r1, r2, r3}
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8006a16: 2300 movs r3, #0
}
8006a18: 4618 mov r0, r3
8006a1a: 3714 adds r7, #20
8006a1c: 46bd mov sp, r7
8006a1e: bc80 pop {r7}
8006a20: 4770 bx lr
08006a22 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
8006a22: b480 push {r7}
8006a24: b085 sub sp, #20
8006a26: af00 add r7, sp, #0
8006a28: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
8006a2a: 687b ldr r3, [r7, #4]
8006a2c: 2200 movs r2, #0
8006a2e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8006a32: f44f 433f mov.w r3, #48896 @ 0xbf00
8006a36: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR = (uint16_t)winterruptmask;
8006a38: 68fb ldr r3, [r7, #12]
8006a3a: b29a uxth r2, r3
8006a3c: 687b ldr r3, [r7, #4]
8006a3e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8006a42: 2300 movs r3, #0
}
8006a44: 4618 mov r0, r3
8006a46: 3714 adds r7, #20
8006a48: 46bd mov sp, r7
8006a4a: bc80 pop {r7}
8006a4c: 4770 bx lr
08006a4e <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
8006a4e: b480 push {r7}
8006a50: b085 sub sp, #20
8006a52: af00 add r7, sp, #0
8006a54: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8006a56: f44f 433f mov.w r3, #48896 @ 0xbf00
8006a5a: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= (uint16_t)(~winterruptmask);
8006a5c: 687b ldr r3, [r7, #4]
8006a5e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8006a62: b29a uxth r2, r3
8006a64: 68fb ldr r3, [r7, #12]
8006a66: b29b uxth r3, r3
8006a68: 43db mvns r3, r3
8006a6a: b29b uxth r3, r3
8006a6c: 4013 ands r3, r2
8006a6e: b29a uxth r2, r3
8006a70: 687b ldr r3, [r7, #4]
8006a72: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8006a76: 2300 movs r3, #0
}
8006a78: 4618 mov r0, r3
8006a7a: 3714 adds r7, #20
8006a7c: 46bd mov sp, r7
8006a7e: bc80 pop {r7}
8006a80: 4770 bx lr
08006a82 <USB_SetCurrentMode>:
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
8006a82: b480 push {r7}
8006a84: b083 sub sp, #12
8006a86: af00 add r7, sp, #0
8006a88: 6078 str r0, [r7, #4]
8006a8a: 460b mov r3, r1
8006a8c: 70fb strb r3, [r7, #3]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8006a8e: 2300 movs r3, #0
}
8006a90: 4618 mov r0, r3
8006a92: 370c adds r7, #12
8006a94: 46bd mov sp, r7
8006a96: bc80 pop {r7}
8006a98: 4770 bx lr
08006a9a <USB_DevInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8006a9a: b480 push {r7}
8006a9c: b085 sub sp, #20
8006a9e: af00 add r7, sp, #0
8006aa0: 60f8 str r0, [r7, #12]
8006aa2: 4638 mov r0, r7
8006aa4: e880 000e stmia.w r0, {r1, r2, r3}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
8006aa8: 68fb ldr r3, [r7, #12]
8006aaa: 2201 movs r2, #1
8006aac: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
8006ab0: 68fb ldr r3, [r7, #12]
8006ab2: 2200 movs r2, #0
8006ab4: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* Clear pending interrupts */
USBx->ISTR = 0U;
8006ab8: 68fb ldr r3, [r7, #12]
8006aba: 2200 movs r2, #0
8006abc: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
8006ac0: 68fb ldr r3, [r7, #12]
8006ac2: 2200 movs r2, #0
8006ac4: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
return HAL_OK;
8006ac8: 2300 movs r3, #0
}
8006aca: 4618 mov r0, r3
8006acc: 3714 adds r7, #20
8006ace: 46bd mov sp, r7
8006ad0: bc80 pop {r7}
8006ad2: 4770 bx lr
08006ad4 <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8006ad4: b480 push {r7}
8006ad6: b09d sub sp, #116 @ 0x74
8006ad8: af00 add r7, sp, #0
8006ada: 6078 str r0, [r7, #4]
8006adc: 6039 str r1, [r7, #0]
HAL_StatusTypeDef ret = HAL_OK;
8006ade: 2300 movs r3, #0
8006ae0: f887 306f strb.w r3, [r7, #111] @ 0x6f
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
8006ae4: 687a ldr r2, [r7, #4]
8006ae6: 683b ldr r3, [r7, #0]
8006ae8: 781b ldrb r3, [r3, #0]
8006aea: 009b lsls r3, r3, #2
8006aec: 4413 add r3, r2
8006aee: 881b ldrh r3, [r3, #0]
8006af0: b29b uxth r3, r3
8006af2: f423 43ec bic.w r3, r3, #30208 @ 0x7600
8006af6: f023 0370 bic.w r3, r3, #112 @ 0x70
8006afa: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
/* initialize Endpoint */
switch (ep->type)
8006afe: 683b ldr r3, [r7, #0]
8006b00: 78db ldrb r3, [r3, #3]
8006b02: 2b03 cmp r3, #3
8006b04: d81f bhi.n 8006b46 <USB_ActivateEndpoint+0x72>
8006b06: a201 add r2, pc, #4 @ (adr r2, 8006b0c <USB_ActivateEndpoint+0x38>)
8006b08: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006b0c: 08006b1d .word 0x08006b1d
8006b10: 08006b39 .word 0x08006b39
8006b14: 08006b4f .word 0x08006b4f
8006b18: 08006b2b .word 0x08006b2b
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
8006b1c: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006b20: f443 7300 orr.w r3, r3, #512 @ 0x200
8006b24: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8006b28: e012 b.n 8006b50 <USB_ActivateEndpoint+0x7c>
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
8006b2a: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006b2e: f443 63c0 orr.w r3, r3, #1536 @ 0x600
8006b32: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8006b36: e00b b.n 8006b50 <USB_ActivateEndpoint+0x7c>
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
8006b38: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006b3c: f443 6380 orr.w r3, r3, #1024 @ 0x400
8006b40: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8006b44: e004 b.n 8006b50 <USB_ActivateEndpoint+0x7c>
default:
ret = HAL_ERROR;
8006b46: 2301 movs r3, #1
8006b48: f887 306f strb.w r3, [r7, #111] @ 0x6f
break;
8006b4c: e000 b.n 8006b50 <USB_ActivateEndpoint+0x7c>
break;
8006b4e: bf00 nop
}
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
8006b50: 687a ldr r2, [r7, #4]
8006b52: 683b ldr r3, [r7, #0]
8006b54: 781b ldrb r3, [r3, #0]
8006b56: 009b lsls r3, r3, #2
8006b58: 441a add r2, r3
8006b5a: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006b5e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006b62: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006b66: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006b6a: f043 0380 orr.w r3, r3, #128 @ 0x80
8006b6e: b29b uxth r3, r3
8006b70: 8013 strh r3, [r2, #0]
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
8006b72: 687a ldr r2, [r7, #4]
8006b74: 683b ldr r3, [r7, #0]
8006b76: 781b ldrb r3, [r3, #0]
8006b78: 009b lsls r3, r3, #2
8006b7a: 4413 add r3, r2
8006b7c: 881b ldrh r3, [r3, #0]
8006b7e: b29b uxth r3, r3
8006b80: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006b84: f023 0370 bic.w r3, r3, #112 @ 0x70
8006b88: b29b uxth r3, r3
8006b8a: 683a ldr r2, [r7, #0]
8006b8c: 7812 ldrb r2, [r2, #0]
8006b8e: 4313 orrs r3, r2
8006b90: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
8006b94: 687a ldr r2, [r7, #4]
8006b96: 683b ldr r3, [r7, #0]
8006b98: 781b ldrb r3, [r3, #0]
8006b9a: 009b lsls r3, r3, #2
8006b9c: 441a add r2, r3
8006b9e: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
8006ba2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006ba6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006baa: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006bae: f043 0380 orr.w r3, r3, #128 @ 0x80
8006bb2: b29b uxth r3, r3
8006bb4: 8013 strh r3, [r2, #0]
if (ep->doublebuffer == 0U)
8006bb6: 683b ldr r3, [r7, #0]
8006bb8: 7b1b ldrb r3, [r3, #12]
8006bba: 2b00 cmp r3, #0
8006bbc: f040 8178 bne.w 8006eb0 <USB_ActivateEndpoint+0x3dc>
{
if (ep->is_in != 0U)
8006bc0: 683b ldr r3, [r7, #0]
8006bc2: 785b ldrb r3, [r3, #1]
8006bc4: 2b00 cmp r3, #0
8006bc6: f000 8084 beq.w 8006cd2 <USB_ActivateEndpoint+0x1fe>
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
8006bca: 687b ldr r3, [r7, #4]
8006bcc: 61bb str r3, [r7, #24]
8006bce: 687b ldr r3, [r7, #4]
8006bd0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006bd4: b29b uxth r3, r3
8006bd6: 461a mov r2, r3
8006bd8: 69bb ldr r3, [r7, #24]
8006bda: 4413 add r3, r2
8006bdc: 61bb str r3, [r7, #24]
8006bde: 683b ldr r3, [r7, #0]
8006be0: 781b ldrb r3, [r3, #0]
8006be2: 011a lsls r2, r3, #4
8006be4: 69bb ldr r3, [r7, #24]
8006be6: 4413 add r3, r2
8006be8: f503 6380 add.w r3, r3, #1024 @ 0x400
8006bec: 617b str r3, [r7, #20]
8006bee: 683b ldr r3, [r7, #0]
8006bf0: 88db ldrh r3, [r3, #6]
8006bf2: 085b lsrs r3, r3, #1
8006bf4: b29b uxth r3, r3
8006bf6: 005b lsls r3, r3, #1
8006bf8: b29a uxth r2, r3
8006bfa: 697b ldr r3, [r7, #20]
8006bfc: 801a strh r2, [r3, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8006bfe: 687a ldr r2, [r7, #4]
8006c00: 683b ldr r3, [r7, #0]
8006c02: 781b ldrb r3, [r3, #0]
8006c04: 009b lsls r3, r3, #2
8006c06: 4413 add r3, r2
8006c08: 881b ldrh r3, [r3, #0]
8006c0a: 827b strh r3, [r7, #18]
8006c0c: 8a7b ldrh r3, [r7, #18]
8006c0e: f003 0340 and.w r3, r3, #64 @ 0x40
8006c12: 2b00 cmp r3, #0
8006c14: d01b beq.n 8006c4e <USB_ActivateEndpoint+0x17a>
8006c16: 687a ldr r2, [r7, #4]
8006c18: 683b ldr r3, [r7, #0]
8006c1a: 781b ldrb r3, [r3, #0]
8006c1c: 009b lsls r3, r3, #2
8006c1e: 4413 add r3, r2
8006c20: 881b ldrh r3, [r3, #0]
8006c22: b29b uxth r3, r3
8006c24: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006c28: f023 0370 bic.w r3, r3, #112 @ 0x70
8006c2c: 823b strh r3, [r7, #16]
8006c2e: 687a ldr r2, [r7, #4]
8006c30: 683b ldr r3, [r7, #0]
8006c32: 781b ldrb r3, [r3, #0]
8006c34: 009b lsls r3, r3, #2
8006c36: 441a add r2, r3
8006c38: 8a3b ldrh r3, [r7, #16]
8006c3a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006c3e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006c42: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006c46: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8006c4a: b29b uxth r3, r3
8006c4c: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8006c4e: 683b ldr r3, [r7, #0]
8006c50: 78db ldrb r3, [r3, #3]
8006c52: 2b01 cmp r3, #1
8006c54: d020 beq.n 8006c98 <USB_ActivateEndpoint+0x1c4>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8006c56: 687a ldr r2, [r7, #4]
8006c58: 683b ldr r3, [r7, #0]
8006c5a: 781b ldrb r3, [r3, #0]
8006c5c: 009b lsls r3, r3, #2
8006c5e: 4413 add r3, r2
8006c60: 881b ldrh r3, [r3, #0]
8006c62: b29b uxth r3, r3
8006c64: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006c68: f023 0340 bic.w r3, r3, #64 @ 0x40
8006c6c: 81bb strh r3, [r7, #12]
8006c6e: 89bb ldrh r3, [r7, #12]
8006c70: f083 0320 eor.w r3, r3, #32
8006c74: 81bb strh r3, [r7, #12]
8006c76: 687a ldr r2, [r7, #4]
8006c78: 683b ldr r3, [r7, #0]
8006c7a: 781b ldrb r3, [r3, #0]
8006c7c: 009b lsls r3, r3, #2
8006c7e: 441a add r2, r3
8006c80: 89bb ldrh r3, [r7, #12]
8006c82: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006c86: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006c8a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006c8e: f043 0380 orr.w r3, r3, #128 @ 0x80
8006c92: b29b uxth r3, r3
8006c94: 8013 strh r3, [r2, #0]
8006c96: e2d5 b.n 8007244 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8006c98: 687a ldr r2, [r7, #4]
8006c9a: 683b ldr r3, [r7, #0]
8006c9c: 781b ldrb r3, [r3, #0]
8006c9e: 009b lsls r3, r3, #2
8006ca0: 4413 add r3, r2
8006ca2: 881b ldrh r3, [r3, #0]
8006ca4: b29b uxth r3, r3
8006ca6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006caa: f023 0340 bic.w r3, r3, #64 @ 0x40
8006cae: 81fb strh r3, [r7, #14]
8006cb0: 687a ldr r2, [r7, #4]
8006cb2: 683b ldr r3, [r7, #0]
8006cb4: 781b ldrb r3, [r3, #0]
8006cb6: 009b lsls r3, r3, #2
8006cb8: 441a add r2, r3
8006cba: 89fb ldrh r3, [r7, #14]
8006cbc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006cc0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006cc4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006cc8: f043 0380 orr.w r3, r3, #128 @ 0x80
8006ccc: b29b uxth r3, r3
8006cce: 8013 strh r3, [r2, #0]
8006cd0: e2b8 b.n 8007244 <USB_ActivateEndpoint+0x770>
}
}
else
{
/* Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
8006cd2: 687b ldr r3, [r7, #4]
8006cd4: 633b str r3, [r7, #48] @ 0x30
8006cd6: 687b ldr r3, [r7, #4]
8006cd8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006cdc: b29b uxth r3, r3
8006cde: 461a mov r2, r3
8006ce0: 6b3b ldr r3, [r7, #48] @ 0x30
8006ce2: 4413 add r3, r2
8006ce4: 633b str r3, [r7, #48] @ 0x30
8006ce6: 683b ldr r3, [r7, #0]
8006ce8: 781b ldrb r3, [r3, #0]
8006cea: 011a lsls r2, r3, #4
8006cec: 6b3b ldr r3, [r7, #48] @ 0x30
8006cee: 4413 add r3, r2
8006cf0: f503 6381 add.w r3, r3, #1032 @ 0x408
8006cf4: 62fb str r3, [r7, #44] @ 0x2c
8006cf6: 683b ldr r3, [r7, #0]
8006cf8: 88db ldrh r3, [r3, #6]
8006cfa: 085b lsrs r3, r3, #1
8006cfc: b29b uxth r3, r3
8006cfe: 005b lsls r3, r3, #1
8006d00: b29a uxth r2, r3
8006d02: 6afb ldr r3, [r7, #44] @ 0x2c
8006d04: 801a strh r2, [r3, #0]
/* Set the endpoint Receive buffer counter */
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
8006d06: 687b ldr r3, [r7, #4]
8006d08: 62bb str r3, [r7, #40] @ 0x28
8006d0a: 687b ldr r3, [r7, #4]
8006d0c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006d10: b29b uxth r3, r3
8006d12: 461a mov r2, r3
8006d14: 6abb ldr r3, [r7, #40] @ 0x28
8006d16: 4413 add r3, r2
8006d18: 62bb str r3, [r7, #40] @ 0x28
8006d1a: 683b ldr r3, [r7, #0]
8006d1c: 781b ldrb r3, [r3, #0]
8006d1e: 011a lsls r2, r3, #4
8006d20: 6abb ldr r3, [r7, #40] @ 0x28
8006d22: 4413 add r3, r2
8006d24: f203 430c addw r3, r3, #1036 @ 0x40c
8006d28: 627b str r3, [r7, #36] @ 0x24
8006d2a: 6a7b ldr r3, [r7, #36] @ 0x24
8006d2c: 881b ldrh r3, [r3, #0]
8006d2e: b29b uxth r3, r3
8006d30: f3c3 0309 ubfx r3, r3, #0, #10
8006d34: b29a uxth r2, r3
8006d36: 6a7b ldr r3, [r7, #36] @ 0x24
8006d38: 801a strh r2, [r3, #0]
8006d3a: 683b ldr r3, [r7, #0]
8006d3c: 691b ldr r3, [r3, #16]
8006d3e: 2b3e cmp r3, #62 @ 0x3e
8006d40: d91d bls.n 8006d7e <USB_ActivateEndpoint+0x2aa>
8006d42: 683b ldr r3, [r7, #0]
8006d44: 691b ldr r3, [r3, #16]
8006d46: 095b lsrs r3, r3, #5
8006d48: 66bb str r3, [r7, #104] @ 0x68
8006d4a: 683b ldr r3, [r7, #0]
8006d4c: 691b ldr r3, [r3, #16]
8006d4e: f003 031f and.w r3, r3, #31
8006d52: 2b00 cmp r3, #0
8006d54: d102 bne.n 8006d5c <USB_ActivateEndpoint+0x288>
8006d56: 6ebb ldr r3, [r7, #104] @ 0x68
8006d58: 3b01 subs r3, #1
8006d5a: 66bb str r3, [r7, #104] @ 0x68
8006d5c: 6a7b ldr r3, [r7, #36] @ 0x24
8006d5e: 881b ldrh r3, [r3, #0]
8006d60: b29a uxth r2, r3
8006d62: 6ebb ldr r3, [r7, #104] @ 0x68
8006d64: b29b uxth r3, r3
8006d66: 029b lsls r3, r3, #10
8006d68: b29b uxth r3, r3
8006d6a: 4313 orrs r3, r2
8006d6c: b29b uxth r3, r3
8006d6e: ea6f 4343 mvn.w r3, r3, lsl #17
8006d72: ea6f 4353 mvn.w r3, r3, lsr #17
8006d76: b29a uxth r2, r3
8006d78: 6a7b ldr r3, [r7, #36] @ 0x24
8006d7a: 801a strh r2, [r3, #0]
8006d7c: e026 b.n 8006dcc <USB_ActivateEndpoint+0x2f8>
8006d7e: 683b ldr r3, [r7, #0]
8006d80: 691b ldr r3, [r3, #16]
8006d82: 2b00 cmp r3, #0
8006d84: d10a bne.n 8006d9c <USB_ActivateEndpoint+0x2c8>
8006d86: 6a7b ldr r3, [r7, #36] @ 0x24
8006d88: 881b ldrh r3, [r3, #0]
8006d8a: b29b uxth r3, r3
8006d8c: ea6f 4343 mvn.w r3, r3, lsl #17
8006d90: ea6f 4353 mvn.w r3, r3, lsr #17
8006d94: b29a uxth r2, r3
8006d96: 6a7b ldr r3, [r7, #36] @ 0x24
8006d98: 801a strh r2, [r3, #0]
8006d9a: e017 b.n 8006dcc <USB_ActivateEndpoint+0x2f8>
8006d9c: 683b ldr r3, [r7, #0]
8006d9e: 691b ldr r3, [r3, #16]
8006da0: 085b lsrs r3, r3, #1
8006da2: 66bb str r3, [r7, #104] @ 0x68
8006da4: 683b ldr r3, [r7, #0]
8006da6: 691b ldr r3, [r3, #16]
8006da8: f003 0301 and.w r3, r3, #1
8006dac: 2b00 cmp r3, #0
8006dae: d002 beq.n 8006db6 <USB_ActivateEndpoint+0x2e2>
8006db0: 6ebb ldr r3, [r7, #104] @ 0x68
8006db2: 3301 adds r3, #1
8006db4: 66bb str r3, [r7, #104] @ 0x68
8006db6: 6a7b ldr r3, [r7, #36] @ 0x24
8006db8: 881b ldrh r3, [r3, #0]
8006dba: b29a uxth r2, r3
8006dbc: 6ebb ldr r3, [r7, #104] @ 0x68
8006dbe: b29b uxth r3, r3
8006dc0: 029b lsls r3, r3, #10
8006dc2: b29b uxth r3, r3
8006dc4: 4313 orrs r3, r2
8006dc6: b29a uxth r2, r3
8006dc8: 6a7b ldr r3, [r7, #36] @ 0x24
8006dca: 801a strh r2, [r3, #0]
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8006dcc: 687a ldr r2, [r7, #4]
8006dce: 683b ldr r3, [r7, #0]
8006dd0: 781b ldrb r3, [r3, #0]
8006dd2: 009b lsls r3, r3, #2
8006dd4: 4413 add r3, r2
8006dd6: 881b ldrh r3, [r3, #0]
8006dd8: 847b strh r3, [r7, #34] @ 0x22
8006dda: 8c7b ldrh r3, [r7, #34] @ 0x22
8006ddc: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006de0: 2b00 cmp r3, #0
8006de2: d01b beq.n 8006e1c <USB_ActivateEndpoint+0x348>
8006de4: 687a ldr r2, [r7, #4]
8006de6: 683b ldr r3, [r7, #0]
8006de8: 781b ldrb r3, [r3, #0]
8006dea: 009b lsls r3, r3, #2
8006dec: 4413 add r3, r2
8006dee: 881b ldrh r3, [r3, #0]
8006df0: b29b uxth r3, r3
8006df2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006df6: f023 0370 bic.w r3, r3, #112 @ 0x70
8006dfa: 843b strh r3, [r7, #32]
8006dfc: 687a ldr r2, [r7, #4]
8006dfe: 683b ldr r3, [r7, #0]
8006e00: 781b ldrb r3, [r3, #0]
8006e02: 009b lsls r3, r3, #2
8006e04: 441a add r2, r3
8006e06: 8c3b ldrh r3, [r7, #32]
8006e08: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006e0c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006e10: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006e14: f043 0380 orr.w r3, r3, #128 @ 0x80
8006e18: b29b uxth r3, r3
8006e1a: 8013 strh r3, [r2, #0]
if (ep->num == 0U)
8006e1c: 683b ldr r3, [r7, #0]
8006e1e: 781b ldrb r3, [r3, #0]
8006e20: 2b00 cmp r3, #0
8006e22: d124 bne.n 8006e6e <USB_ActivateEndpoint+0x39a>
{
/* Configure VALID status for EP0 */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8006e24: 687a ldr r2, [r7, #4]
8006e26: 683b ldr r3, [r7, #0]
8006e28: 781b ldrb r3, [r3, #0]
8006e2a: 009b lsls r3, r3, #2
8006e2c: 4413 add r3, r2
8006e2e: 881b ldrh r3, [r3, #0]
8006e30: b29b uxth r3, r3
8006e32: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006e36: f023 0370 bic.w r3, r3, #112 @ 0x70
8006e3a: 83bb strh r3, [r7, #28]
8006e3c: 8bbb ldrh r3, [r7, #28]
8006e3e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8006e42: 83bb strh r3, [r7, #28]
8006e44: 8bbb ldrh r3, [r7, #28]
8006e46: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8006e4a: 83bb strh r3, [r7, #28]
8006e4c: 687a ldr r2, [r7, #4]
8006e4e: 683b ldr r3, [r7, #0]
8006e50: 781b ldrb r3, [r3, #0]
8006e52: 009b lsls r3, r3, #2
8006e54: 441a add r2, r3
8006e56: 8bbb ldrh r3, [r7, #28]
8006e58: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006e5c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006e60: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006e64: f043 0380 orr.w r3, r3, #128 @ 0x80
8006e68: b29b uxth r3, r3
8006e6a: 8013 strh r3, [r2, #0]
8006e6c: e1ea b.n 8007244 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure NAK status for OUT Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
8006e6e: 687a ldr r2, [r7, #4]
8006e70: 683b ldr r3, [r7, #0]
8006e72: 781b ldrb r3, [r3, #0]
8006e74: 009b lsls r3, r3, #2
8006e76: 4413 add r3, r2
8006e78: 881b ldrh r3, [r3, #0]
8006e7a: b29b uxth r3, r3
8006e7c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006e80: f023 0370 bic.w r3, r3, #112 @ 0x70
8006e84: 83fb strh r3, [r7, #30]
8006e86: 8bfb ldrh r3, [r7, #30]
8006e88: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8006e8c: 83fb strh r3, [r7, #30]
8006e8e: 687a ldr r2, [r7, #4]
8006e90: 683b ldr r3, [r7, #0]
8006e92: 781b ldrb r3, [r3, #0]
8006e94: 009b lsls r3, r3, #2
8006e96: 441a add r2, r3
8006e98: 8bfb ldrh r3, [r7, #30]
8006e9a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006e9e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006ea2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006ea6: f043 0380 orr.w r3, r3, #128 @ 0x80
8006eaa: b29b uxth r3, r3
8006eac: 8013 strh r3, [r2, #0]
8006eae: e1c9 b.n 8007244 <USB_ActivateEndpoint+0x770>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->type == EP_TYPE_BULK)
8006eb0: 683b ldr r3, [r7, #0]
8006eb2: 78db ldrb r3, [r3, #3]
8006eb4: 2b02 cmp r3, #2
8006eb6: d11e bne.n 8006ef6 <USB_ActivateEndpoint+0x422>
{
/* Set bulk endpoint as double buffered */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
8006eb8: 687a ldr r2, [r7, #4]
8006eba: 683b ldr r3, [r7, #0]
8006ebc: 781b ldrb r3, [r3, #0]
8006ebe: 009b lsls r3, r3, #2
8006ec0: 4413 add r3, r2
8006ec2: 881b ldrh r3, [r3, #0]
8006ec4: b29b uxth r3, r3
8006ec6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006eca: f023 0370 bic.w r3, r3, #112 @ 0x70
8006ece: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8006ed2: 687a ldr r2, [r7, #4]
8006ed4: 683b ldr r3, [r7, #0]
8006ed6: 781b ldrb r3, [r3, #0]
8006ed8: 009b lsls r3, r3, #2
8006eda: 441a add r2, r3
8006edc: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
8006ee0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006ee4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006ee8: f443 4301 orr.w r3, r3, #33024 @ 0x8100
8006eec: f043 0380 orr.w r3, r3, #128 @ 0x80
8006ef0: b29b uxth r3, r3
8006ef2: 8013 strh r3, [r2, #0]
8006ef4: e01d b.n 8006f32 <USB_ActivateEndpoint+0x45e>
}
else
{
/* Set the ISOC endpoint in double buffer mode */
PCD_CLEAR_EP_KIND(USBx, ep->num);
8006ef6: 687a ldr r2, [r7, #4]
8006ef8: 683b ldr r3, [r7, #0]
8006efa: 781b ldrb r3, [r3, #0]
8006efc: 009b lsls r3, r3, #2
8006efe: 4413 add r3, r2
8006f00: 881b ldrh r3, [r3, #0]
8006f02: b29b uxth r3, r3
8006f04: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8006f08: f023 0370 bic.w r3, r3, #112 @ 0x70
8006f0c: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
8006f10: 687a ldr r2, [r7, #4]
8006f12: 683b ldr r3, [r7, #0]
8006f14: 781b ldrb r3, [r3, #0]
8006f16: 009b lsls r3, r3, #2
8006f18: 441a add r2, r3
8006f1a: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
8006f1e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006f22: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006f26: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006f2a: f043 0380 orr.w r3, r3, #128 @ 0x80
8006f2e: b29b uxth r3, r3
8006f30: 8013 strh r3, [r2, #0]
}
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
8006f32: 687b ldr r3, [r7, #4]
8006f34: 65fb str r3, [r7, #92] @ 0x5c
8006f36: 687b ldr r3, [r7, #4]
8006f38: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006f3c: b29b uxth r3, r3
8006f3e: 461a mov r2, r3
8006f40: 6dfb ldr r3, [r7, #92] @ 0x5c
8006f42: 4413 add r3, r2
8006f44: 65fb str r3, [r7, #92] @ 0x5c
8006f46: 683b ldr r3, [r7, #0]
8006f48: 781b ldrb r3, [r3, #0]
8006f4a: 011a lsls r2, r3, #4
8006f4c: 6dfb ldr r3, [r7, #92] @ 0x5c
8006f4e: 4413 add r3, r2
8006f50: f503 6380 add.w r3, r3, #1024 @ 0x400
8006f54: 65bb str r3, [r7, #88] @ 0x58
8006f56: 683b ldr r3, [r7, #0]
8006f58: 891b ldrh r3, [r3, #8]
8006f5a: 085b lsrs r3, r3, #1
8006f5c: b29b uxth r3, r3
8006f5e: 005b lsls r3, r3, #1
8006f60: b29a uxth r2, r3
8006f62: 6dbb ldr r3, [r7, #88] @ 0x58
8006f64: 801a strh r2, [r3, #0]
8006f66: 687b ldr r3, [r7, #4]
8006f68: 657b str r3, [r7, #84] @ 0x54
8006f6a: 687b ldr r3, [r7, #4]
8006f6c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006f70: b29b uxth r3, r3
8006f72: 461a mov r2, r3
8006f74: 6d7b ldr r3, [r7, #84] @ 0x54
8006f76: 4413 add r3, r2
8006f78: 657b str r3, [r7, #84] @ 0x54
8006f7a: 683b ldr r3, [r7, #0]
8006f7c: 781b ldrb r3, [r3, #0]
8006f7e: 011a lsls r2, r3, #4
8006f80: 6d7b ldr r3, [r7, #84] @ 0x54
8006f82: 4413 add r3, r2
8006f84: f503 6381 add.w r3, r3, #1032 @ 0x408
8006f88: 653b str r3, [r7, #80] @ 0x50
8006f8a: 683b ldr r3, [r7, #0]
8006f8c: 895b ldrh r3, [r3, #10]
8006f8e: 085b lsrs r3, r3, #1
8006f90: b29b uxth r3, r3
8006f92: 005b lsls r3, r3, #1
8006f94: b29a uxth r2, r3
8006f96: 6d3b ldr r3, [r7, #80] @ 0x50
8006f98: 801a strh r2, [r3, #0]
if (ep->is_in == 0U)
8006f9a: 683b ldr r3, [r7, #0]
8006f9c: 785b ldrb r3, [r3, #1]
8006f9e: 2b00 cmp r3, #0
8006fa0: f040 8093 bne.w 80070ca <USB_ActivateEndpoint+0x5f6>
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8006fa4: 687a ldr r2, [r7, #4]
8006fa6: 683b ldr r3, [r7, #0]
8006fa8: 781b ldrb r3, [r3, #0]
8006faa: 009b lsls r3, r3, #2
8006fac: 4413 add r3, r2
8006fae: 881b ldrh r3, [r3, #0]
8006fb0: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
8006fb4: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8006fb8: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006fbc: 2b00 cmp r3, #0
8006fbe: d01b beq.n 8006ff8 <USB_ActivateEndpoint+0x524>
8006fc0: 687a ldr r2, [r7, #4]
8006fc2: 683b ldr r3, [r7, #0]
8006fc4: 781b ldrb r3, [r3, #0]
8006fc6: 009b lsls r3, r3, #2
8006fc8: 4413 add r3, r2
8006fca: 881b ldrh r3, [r3, #0]
8006fcc: b29b uxth r3, r3
8006fce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006fd2: f023 0370 bic.w r3, r3, #112 @ 0x70
8006fd6: 87fb strh r3, [r7, #62] @ 0x3e
8006fd8: 687a ldr r2, [r7, #4]
8006fda: 683b ldr r3, [r7, #0]
8006fdc: 781b ldrb r3, [r3, #0]
8006fde: 009b lsls r3, r3, #2
8006fe0: 441a add r2, r3
8006fe2: 8ffb ldrh r3, [r7, #62] @ 0x3e
8006fe4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006fe8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006fec: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006ff0: f043 0380 orr.w r3, r3, #128 @ 0x80
8006ff4: b29b uxth r3, r3
8006ff6: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8006ff8: 687a ldr r2, [r7, #4]
8006ffa: 683b ldr r3, [r7, #0]
8006ffc: 781b ldrb r3, [r3, #0]
8006ffe: 009b lsls r3, r3, #2
8007000: 4413 add r3, r2
8007002: 881b ldrh r3, [r3, #0]
8007004: 87bb strh r3, [r7, #60] @ 0x3c
8007006: 8fbb ldrh r3, [r7, #60] @ 0x3c
8007008: f003 0340 and.w r3, r3, #64 @ 0x40
800700c: 2b00 cmp r3, #0
800700e: d01b beq.n 8007048 <USB_ActivateEndpoint+0x574>
8007010: 687a ldr r2, [r7, #4]
8007012: 683b ldr r3, [r7, #0]
8007014: 781b ldrb r3, [r3, #0]
8007016: 009b lsls r3, r3, #2
8007018: 4413 add r3, r2
800701a: 881b ldrh r3, [r3, #0]
800701c: b29b uxth r3, r3
800701e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007022: f023 0370 bic.w r3, r3, #112 @ 0x70
8007026: 877b strh r3, [r7, #58] @ 0x3a
8007028: 687a ldr r2, [r7, #4]
800702a: 683b ldr r3, [r7, #0]
800702c: 781b ldrb r3, [r3, #0]
800702e: 009b lsls r3, r3, #2
8007030: 441a add r2, r3
8007032: 8f7b ldrh r3, [r7, #58] @ 0x3a
8007034: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007038: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800703c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007040: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007044: b29b uxth r3, r3
8007046: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8007048: 687a ldr r2, [r7, #4]
800704a: 683b ldr r3, [r7, #0]
800704c: 781b ldrb r3, [r3, #0]
800704e: 009b lsls r3, r3, #2
8007050: 4413 add r3, r2
8007052: 881b ldrh r3, [r3, #0]
8007054: b29b uxth r3, r3
8007056: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800705a: f023 0370 bic.w r3, r3, #112 @ 0x70
800705e: 873b strh r3, [r7, #56] @ 0x38
8007060: 8f3b ldrh r3, [r7, #56] @ 0x38
8007062: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8007066: 873b strh r3, [r7, #56] @ 0x38
8007068: 8f3b ldrh r3, [r7, #56] @ 0x38
800706a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800706e: 873b strh r3, [r7, #56] @ 0x38
8007070: 687a ldr r2, [r7, #4]
8007072: 683b ldr r3, [r7, #0]
8007074: 781b ldrb r3, [r3, #0]
8007076: 009b lsls r3, r3, #2
8007078: 441a add r2, r3
800707a: 8f3b ldrh r3, [r7, #56] @ 0x38
800707c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007080: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007084: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007088: f043 0380 orr.w r3, r3, #128 @ 0x80
800708c: b29b uxth r3, r3
800708e: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8007090: 687a ldr r2, [r7, #4]
8007092: 683b ldr r3, [r7, #0]
8007094: 781b ldrb r3, [r3, #0]
8007096: 009b lsls r3, r3, #2
8007098: 4413 add r3, r2
800709a: 881b ldrh r3, [r3, #0]
800709c: b29b uxth r3, r3
800709e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80070a2: f023 0340 bic.w r3, r3, #64 @ 0x40
80070a6: 86fb strh r3, [r7, #54] @ 0x36
80070a8: 687a ldr r2, [r7, #4]
80070aa: 683b ldr r3, [r7, #0]
80070ac: 781b ldrb r3, [r3, #0]
80070ae: 009b lsls r3, r3, #2
80070b0: 441a add r2, r3
80070b2: 8efb ldrh r3, [r7, #54] @ 0x36
80070b4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80070b8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80070bc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80070c0: f043 0380 orr.w r3, r3, #128 @ 0x80
80070c4: b29b uxth r3, r3
80070c6: 8013 strh r3, [r2, #0]
80070c8: e0bc b.n 8007244 <USB_ActivateEndpoint+0x770>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80070ca: 687a ldr r2, [r7, #4]
80070cc: 683b ldr r3, [r7, #0]
80070ce: 781b ldrb r3, [r3, #0]
80070d0: 009b lsls r3, r3, #2
80070d2: 4413 add r3, r2
80070d4: 881b ldrh r3, [r3, #0]
80070d6: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
80070da: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80070de: f403 4380 and.w r3, r3, #16384 @ 0x4000
80070e2: 2b00 cmp r3, #0
80070e4: d01d beq.n 8007122 <USB_ActivateEndpoint+0x64e>
80070e6: 687a ldr r2, [r7, #4]
80070e8: 683b ldr r3, [r7, #0]
80070ea: 781b ldrb r3, [r3, #0]
80070ec: 009b lsls r3, r3, #2
80070ee: 4413 add r3, r2
80070f0: 881b ldrh r3, [r3, #0]
80070f2: b29b uxth r3, r3
80070f4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80070f8: f023 0370 bic.w r3, r3, #112 @ 0x70
80070fc: f8a7 304c strh.w r3, [r7, #76] @ 0x4c
8007100: 687a ldr r2, [r7, #4]
8007102: 683b ldr r3, [r7, #0]
8007104: 781b ldrb r3, [r3, #0]
8007106: 009b lsls r3, r3, #2
8007108: 441a add r2, r3
800710a: f8b7 304c ldrh.w r3, [r7, #76] @ 0x4c
800710e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007112: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007116: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800711a: f043 0380 orr.w r3, r3, #128 @ 0x80
800711e: b29b uxth r3, r3
8007120: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8007122: 687a ldr r2, [r7, #4]
8007124: 683b ldr r3, [r7, #0]
8007126: 781b ldrb r3, [r3, #0]
8007128: 009b lsls r3, r3, #2
800712a: 4413 add r3, r2
800712c: 881b ldrh r3, [r3, #0]
800712e: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
8007132: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8007136: f003 0340 and.w r3, r3, #64 @ 0x40
800713a: 2b00 cmp r3, #0
800713c: d01d beq.n 800717a <USB_ActivateEndpoint+0x6a6>
800713e: 687a ldr r2, [r7, #4]
8007140: 683b ldr r3, [r7, #0]
8007142: 781b ldrb r3, [r3, #0]
8007144: 009b lsls r3, r3, #2
8007146: 4413 add r3, r2
8007148: 881b ldrh r3, [r3, #0]
800714a: b29b uxth r3, r3
800714c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007150: f023 0370 bic.w r3, r3, #112 @ 0x70
8007154: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
8007158: 687a ldr r2, [r7, #4]
800715a: 683b ldr r3, [r7, #0]
800715c: 781b ldrb r3, [r3, #0]
800715e: 009b lsls r3, r3, #2
8007160: 441a add r2, r3
8007162: f8b7 3048 ldrh.w r3, [r7, #72] @ 0x48
8007166: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800716a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800716e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007172: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007176: b29b uxth r3, r3
8007178: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800717a: 683b ldr r3, [r7, #0]
800717c: 78db ldrb r3, [r3, #3]
800717e: 2b01 cmp r3, #1
8007180: d024 beq.n 80071cc <USB_ActivateEndpoint+0x6f8>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8007182: 687a ldr r2, [r7, #4]
8007184: 683b ldr r3, [r7, #0]
8007186: 781b ldrb r3, [r3, #0]
8007188: 009b lsls r3, r3, #2
800718a: 4413 add r3, r2
800718c: 881b ldrh r3, [r3, #0]
800718e: b29b uxth r3, r3
8007190: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007194: f023 0340 bic.w r3, r3, #64 @ 0x40
8007198: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
800719c: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
80071a0: f083 0320 eor.w r3, r3, #32
80071a4: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
80071a8: 687a ldr r2, [r7, #4]
80071aa: 683b ldr r3, [r7, #0]
80071ac: 781b ldrb r3, [r3, #0]
80071ae: 009b lsls r3, r3, #2
80071b0: 441a add r2, r3
80071b2: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
80071b6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80071ba: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80071be: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80071c2: f043 0380 orr.w r3, r3, #128 @ 0x80
80071c6: b29b uxth r3, r3
80071c8: 8013 strh r3, [r2, #0]
80071ca: e01d b.n 8007208 <USB_ActivateEndpoint+0x734>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80071cc: 687a ldr r2, [r7, #4]
80071ce: 683b ldr r3, [r7, #0]
80071d0: 781b ldrb r3, [r3, #0]
80071d2: 009b lsls r3, r3, #2
80071d4: 4413 add r3, r2
80071d6: 881b ldrh r3, [r3, #0]
80071d8: b29b uxth r3, r3
80071da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80071de: f023 0340 bic.w r3, r3, #64 @ 0x40
80071e2: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
80071e6: 687a ldr r2, [r7, #4]
80071e8: 683b ldr r3, [r7, #0]
80071ea: 781b ldrb r3, [r3, #0]
80071ec: 009b lsls r3, r3, #2
80071ee: 441a add r2, r3
80071f0: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46
80071f4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80071f8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80071fc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007200: f043 0380 orr.w r3, r3, #128 @ 0x80
8007204: b29b uxth r3, r3
8007206: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8007208: 687a ldr r2, [r7, #4]
800720a: 683b ldr r3, [r7, #0]
800720c: 781b ldrb r3, [r3, #0]
800720e: 009b lsls r3, r3, #2
8007210: 4413 add r3, r2
8007212: 881b ldrh r3, [r3, #0]
8007214: b29b uxth r3, r3
8007216: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800721a: f023 0370 bic.w r3, r3, #112 @ 0x70
800721e: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
8007222: 687a ldr r2, [r7, #4]
8007224: 683b ldr r3, [r7, #0]
8007226: 781b ldrb r3, [r3, #0]
8007228: 009b lsls r3, r3, #2
800722a: 441a add r2, r3
800722c: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
8007230: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007234: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007238: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800723c: f043 0380 orr.w r3, r3, #128 @ 0x80
8007240: b29b uxth r3, r3
8007242: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
8007244: f897 306f ldrb.w r3, [r7, #111] @ 0x6f
}
8007248: 4618 mov r0, r3
800724a: 3774 adds r7, #116 @ 0x74
800724c: 46bd mov sp, r7
800724e: bc80 pop {r7}
8007250: 4770 bx lr
8007252: bf00 nop
08007254 <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8007254: b480 push {r7}
8007256: b08d sub sp, #52 @ 0x34
8007258: af00 add r7, sp, #0
800725a: 6078 str r0, [r7, #4]
800725c: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
800725e: 683b ldr r3, [r7, #0]
8007260: 7b1b ldrb r3, [r3, #12]
8007262: 2b00 cmp r3, #0
8007264: f040 808e bne.w 8007384 <USB_DeactivateEndpoint+0x130>
{
if (ep->is_in != 0U)
8007268: 683b ldr r3, [r7, #0]
800726a: 785b ldrb r3, [r3, #1]
800726c: 2b00 cmp r3, #0
800726e: d044 beq.n 80072fa <USB_DeactivateEndpoint+0xa6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8007270: 687a ldr r2, [r7, #4]
8007272: 683b ldr r3, [r7, #0]
8007274: 781b ldrb r3, [r3, #0]
8007276: 009b lsls r3, r3, #2
8007278: 4413 add r3, r2
800727a: 881b ldrh r3, [r3, #0]
800727c: 81bb strh r3, [r7, #12]
800727e: 89bb ldrh r3, [r7, #12]
8007280: f003 0340 and.w r3, r3, #64 @ 0x40
8007284: 2b00 cmp r3, #0
8007286: d01b beq.n 80072c0 <USB_DeactivateEndpoint+0x6c>
8007288: 687a ldr r2, [r7, #4]
800728a: 683b ldr r3, [r7, #0]
800728c: 781b ldrb r3, [r3, #0]
800728e: 009b lsls r3, r3, #2
8007290: 4413 add r3, r2
8007292: 881b ldrh r3, [r3, #0]
8007294: b29b uxth r3, r3
8007296: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800729a: f023 0370 bic.w r3, r3, #112 @ 0x70
800729e: 817b strh r3, [r7, #10]
80072a0: 687a ldr r2, [r7, #4]
80072a2: 683b ldr r3, [r7, #0]
80072a4: 781b ldrb r3, [r3, #0]
80072a6: 009b lsls r3, r3, #2
80072a8: 441a add r2, r3
80072aa: 897b ldrh r3, [r7, #10]
80072ac: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80072b0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80072b4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80072b8: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80072bc: b29b uxth r3, r3
80072be: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80072c0: 687a ldr r2, [r7, #4]
80072c2: 683b ldr r3, [r7, #0]
80072c4: 781b ldrb r3, [r3, #0]
80072c6: 009b lsls r3, r3, #2
80072c8: 4413 add r3, r2
80072ca: 881b ldrh r3, [r3, #0]
80072cc: b29b uxth r3, r3
80072ce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80072d2: f023 0340 bic.w r3, r3, #64 @ 0x40
80072d6: 813b strh r3, [r7, #8]
80072d8: 687a ldr r2, [r7, #4]
80072da: 683b ldr r3, [r7, #0]
80072dc: 781b ldrb r3, [r3, #0]
80072de: 009b lsls r3, r3, #2
80072e0: 441a add r2, r3
80072e2: 893b ldrh r3, [r7, #8]
80072e4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80072e8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80072ec: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80072f0: f043 0380 orr.w r3, r3, #128 @ 0x80
80072f4: b29b uxth r3, r3
80072f6: 8013 strh r3, [r2, #0]
80072f8: e192 b.n 8007620 <USB_DeactivateEndpoint+0x3cc>
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80072fa: 687a ldr r2, [r7, #4]
80072fc: 683b ldr r3, [r7, #0]
80072fe: 781b ldrb r3, [r3, #0]
8007300: 009b lsls r3, r3, #2
8007302: 4413 add r3, r2
8007304: 881b ldrh r3, [r3, #0]
8007306: 827b strh r3, [r7, #18]
8007308: 8a7b ldrh r3, [r7, #18]
800730a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800730e: 2b00 cmp r3, #0
8007310: d01b beq.n 800734a <USB_DeactivateEndpoint+0xf6>
8007312: 687a ldr r2, [r7, #4]
8007314: 683b ldr r3, [r7, #0]
8007316: 781b ldrb r3, [r3, #0]
8007318: 009b lsls r3, r3, #2
800731a: 4413 add r3, r2
800731c: 881b ldrh r3, [r3, #0]
800731e: b29b uxth r3, r3
8007320: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007324: f023 0370 bic.w r3, r3, #112 @ 0x70
8007328: 823b strh r3, [r7, #16]
800732a: 687a ldr r2, [r7, #4]
800732c: 683b ldr r3, [r7, #0]
800732e: 781b ldrb r3, [r3, #0]
8007330: 009b lsls r3, r3, #2
8007332: 441a add r2, r3
8007334: 8a3b ldrh r3, [r7, #16]
8007336: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800733a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800733e: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8007342: f043 0380 orr.w r3, r3, #128 @ 0x80
8007346: b29b uxth r3, r3
8007348: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800734a: 687a ldr r2, [r7, #4]
800734c: 683b ldr r3, [r7, #0]
800734e: 781b ldrb r3, [r3, #0]
8007350: 009b lsls r3, r3, #2
8007352: 4413 add r3, r2
8007354: 881b ldrh r3, [r3, #0]
8007356: b29b uxth r3, r3
8007358: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800735c: f023 0370 bic.w r3, r3, #112 @ 0x70
8007360: 81fb strh r3, [r7, #14]
8007362: 687a ldr r2, [r7, #4]
8007364: 683b ldr r3, [r7, #0]
8007366: 781b ldrb r3, [r3, #0]
8007368: 009b lsls r3, r3, #2
800736a: 441a add r2, r3
800736c: 89fb ldrh r3, [r7, #14]
800736e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007372: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007376: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800737a: f043 0380 orr.w r3, r3, #128 @ 0x80
800737e: b29b uxth r3, r3
8007380: 8013 strh r3, [r2, #0]
8007382: e14d b.n 8007620 <USB_DeactivateEndpoint+0x3cc>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->is_in == 0U)
8007384: 683b ldr r3, [r7, #0]
8007386: 785b ldrb r3, [r3, #1]
8007388: 2b00 cmp r3, #0
800738a: f040 80a5 bne.w 80074d8 <USB_DeactivateEndpoint+0x284>
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800738e: 687a ldr r2, [r7, #4]
8007390: 683b ldr r3, [r7, #0]
8007392: 781b ldrb r3, [r3, #0]
8007394: 009b lsls r3, r3, #2
8007396: 4413 add r3, r2
8007398: 881b ldrh r3, [r3, #0]
800739a: 843b strh r3, [r7, #32]
800739c: 8c3b ldrh r3, [r7, #32]
800739e: f403 4380 and.w r3, r3, #16384 @ 0x4000
80073a2: 2b00 cmp r3, #0
80073a4: d01b beq.n 80073de <USB_DeactivateEndpoint+0x18a>
80073a6: 687a ldr r2, [r7, #4]
80073a8: 683b ldr r3, [r7, #0]
80073aa: 781b ldrb r3, [r3, #0]
80073ac: 009b lsls r3, r3, #2
80073ae: 4413 add r3, r2
80073b0: 881b ldrh r3, [r3, #0]
80073b2: b29b uxth r3, r3
80073b4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80073b8: f023 0370 bic.w r3, r3, #112 @ 0x70
80073bc: 83fb strh r3, [r7, #30]
80073be: 687a ldr r2, [r7, #4]
80073c0: 683b ldr r3, [r7, #0]
80073c2: 781b ldrb r3, [r3, #0]
80073c4: 009b lsls r3, r3, #2
80073c6: 441a add r2, r3
80073c8: 8bfb ldrh r3, [r7, #30]
80073ca: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80073ce: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80073d2: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80073d6: f043 0380 orr.w r3, r3, #128 @ 0x80
80073da: b29b uxth r3, r3
80073dc: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80073de: 687a ldr r2, [r7, #4]
80073e0: 683b ldr r3, [r7, #0]
80073e2: 781b ldrb r3, [r3, #0]
80073e4: 009b lsls r3, r3, #2
80073e6: 4413 add r3, r2
80073e8: 881b ldrh r3, [r3, #0]
80073ea: 83bb strh r3, [r7, #28]
80073ec: 8bbb ldrh r3, [r7, #28]
80073ee: f003 0340 and.w r3, r3, #64 @ 0x40
80073f2: 2b00 cmp r3, #0
80073f4: d01b beq.n 800742e <USB_DeactivateEndpoint+0x1da>
80073f6: 687a ldr r2, [r7, #4]
80073f8: 683b ldr r3, [r7, #0]
80073fa: 781b ldrb r3, [r3, #0]
80073fc: 009b lsls r3, r3, #2
80073fe: 4413 add r3, r2
8007400: 881b ldrh r3, [r3, #0]
8007402: b29b uxth r3, r3
8007404: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007408: f023 0370 bic.w r3, r3, #112 @ 0x70
800740c: 837b strh r3, [r7, #26]
800740e: 687a ldr r2, [r7, #4]
8007410: 683b ldr r3, [r7, #0]
8007412: 781b ldrb r3, [r3, #0]
8007414: 009b lsls r3, r3, #2
8007416: 441a add r2, r3
8007418: 8b7b ldrh r3, [r7, #26]
800741a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800741e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007422: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007426: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800742a: b29b uxth r3, r3
800742c: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
800742e: 687a ldr r2, [r7, #4]
8007430: 683b ldr r3, [r7, #0]
8007432: 781b ldrb r3, [r3, #0]
8007434: 009b lsls r3, r3, #2
8007436: 4413 add r3, r2
8007438: 881b ldrh r3, [r3, #0]
800743a: b29b uxth r3, r3
800743c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007440: f023 0370 bic.w r3, r3, #112 @ 0x70
8007444: 833b strh r3, [r7, #24]
8007446: 687a ldr r2, [r7, #4]
8007448: 683b ldr r3, [r7, #0]
800744a: 781b ldrb r3, [r3, #0]
800744c: 009b lsls r3, r3, #2
800744e: 441a add r2, r3
8007450: 8b3b ldrh r3, [r7, #24]
8007452: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007456: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800745a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800745e: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007462: b29b uxth r3, r3
8007464: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8007466: 687a ldr r2, [r7, #4]
8007468: 683b ldr r3, [r7, #0]
800746a: 781b ldrb r3, [r3, #0]
800746c: 009b lsls r3, r3, #2
800746e: 4413 add r3, r2
8007470: 881b ldrh r3, [r3, #0]
8007472: b29b uxth r3, r3
8007474: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8007478: f023 0370 bic.w r3, r3, #112 @ 0x70
800747c: 82fb strh r3, [r7, #22]
800747e: 687a ldr r2, [r7, #4]
8007480: 683b ldr r3, [r7, #0]
8007482: 781b ldrb r3, [r3, #0]
8007484: 009b lsls r3, r3, #2
8007486: 441a add r2, r3
8007488: 8afb ldrh r3, [r7, #22]
800748a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800748e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007492: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007496: f043 0380 orr.w r3, r3, #128 @ 0x80
800749a: b29b uxth r3, r3
800749c: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800749e: 687a ldr r2, [r7, #4]
80074a0: 683b ldr r3, [r7, #0]
80074a2: 781b ldrb r3, [r3, #0]
80074a4: 009b lsls r3, r3, #2
80074a6: 4413 add r3, r2
80074a8: 881b ldrh r3, [r3, #0]
80074aa: b29b uxth r3, r3
80074ac: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80074b0: f023 0340 bic.w r3, r3, #64 @ 0x40
80074b4: 82bb strh r3, [r7, #20]
80074b6: 687a ldr r2, [r7, #4]
80074b8: 683b ldr r3, [r7, #0]
80074ba: 781b ldrb r3, [r3, #0]
80074bc: 009b lsls r3, r3, #2
80074be: 441a add r2, r3
80074c0: 8abb ldrh r3, [r7, #20]
80074c2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80074c6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80074ca: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80074ce: f043 0380 orr.w r3, r3, #128 @ 0x80
80074d2: b29b uxth r3, r3
80074d4: 8013 strh r3, [r2, #0]
80074d6: e0a3 b.n 8007620 <USB_DeactivateEndpoint+0x3cc>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80074d8: 687a ldr r2, [r7, #4]
80074da: 683b ldr r3, [r7, #0]
80074dc: 781b ldrb r3, [r3, #0]
80074de: 009b lsls r3, r3, #2
80074e0: 4413 add r3, r2
80074e2: 881b ldrh r3, [r3, #0]
80074e4: 85fb strh r3, [r7, #46] @ 0x2e
80074e6: 8dfb ldrh r3, [r7, #46] @ 0x2e
80074e8: f403 4380 and.w r3, r3, #16384 @ 0x4000
80074ec: 2b00 cmp r3, #0
80074ee: d01b beq.n 8007528 <USB_DeactivateEndpoint+0x2d4>
80074f0: 687a ldr r2, [r7, #4]
80074f2: 683b ldr r3, [r7, #0]
80074f4: 781b ldrb r3, [r3, #0]
80074f6: 009b lsls r3, r3, #2
80074f8: 4413 add r3, r2
80074fa: 881b ldrh r3, [r3, #0]
80074fc: b29b uxth r3, r3
80074fe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007502: f023 0370 bic.w r3, r3, #112 @ 0x70
8007506: 85bb strh r3, [r7, #44] @ 0x2c
8007508: 687a ldr r2, [r7, #4]
800750a: 683b ldr r3, [r7, #0]
800750c: 781b ldrb r3, [r3, #0]
800750e: 009b lsls r3, r3, #2
8007510: 441a add r2, r3
8007512: 8dbb ldrh r3, [r7, #44] @ 0x2c
8007514: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007518: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800751c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8007520: f043 0380 orr.w r3, r3, #128 @ 0x80
8007524: b29b uxth r3, r3
8007526: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8007528: 687a ldr r2, [r7, #4]
800752a: 683b ldr r3, [r7, #0]
800752c: 781b ldrb r3, [r3, #0]
800752e: 009b lsls r3, r3, #2
8007530: 4413 add r3, r2
8007532: 881b ldrh r3, [r3, #0]
8007534: 857b strh r3, [r7, #42] @ 0x2a
8007536: 8d7b ldrh r3, [r7, #42] @ 0x2a
8007538: f003 0340 and.w r3, r3, #64 @ 0x40
800753c: 2b00 cmp r3, #0
800753e: d01b beq.n 8007578 <USB_DeactivateEndpoint+0x324>
8007540: 687a ldr r2, [r7, #4]
8007542: 683b ldr r3, [r7, #0]
8007544: 781b ldrb r3, [r3, #0]
8007546: 009b lsls r3, r3, #2
8007548: 4413 add r3, r2
800754a: 881b ldrh r3, [r3, #0]
800754c: b29b uxth r3, r3
800754e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007552: f023 0370 bic.w r3, r3, #112 @ 0x70
8007556: 853b strh r3, [r7, #40] @ 0x28
8007558: 687a ldr r2, [r7, #4]
800755a: 683b ldr r3, [r7, #0]
800755c: 781b ldrb r3, [r3, #0]
800755e: 009b lsls r3, r3, #2
8007560: 441a add r2, r3
8007562: 8d3b ldrh r3, [r7, #40] @ 0x28
8007564: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007568: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800756c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007570: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007574: b29b uxth r3, r3
8007576: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
8007578: 687a ldr r2, [r7, #4]
800757a: 683b ldr r3, [r7, #0]
800757c: 781b ldrb r3, [r3, #0]
800757e: 009b lsls r3, r3, #2
8007580: 4413 add r3, r2
8007582: 881b ldrh r3, [r3, #0]
8007584: b29b uxth r3, r3
8007586: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800758a: f023 0370 bic.w r3, r3, #112 @ 0x70
800758e: 84fb strh r3, [r7, #38] @ 0x26
8007590: 687a ldr r2, [r7, #4]
8007592: 683b ldr r3, [r7, #0]
8007594: 781b ldrb r3, [r3, #0]
8007596: 009b lsls r3, r3, #2
8007598: 441a add r2, r3
800759a: 8cfb ldrh r3, [r7, #38] @ 0x26
800759c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80075a0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80075a4: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80075a8: f043 0380 orr.w r3, r3, #128 @ 0x80
80075ac: b29b uxth r3, r3
80075ae: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80075b0: 687a ldr r2, [r7, #4]
80075b2: 683b ldr r3, [r7, #0]
80075b4: 781b ldrb r3, [r3, #0]
80075b6: 009b lsls r3, r3, #2
80075b8: 4413 add r3, r2
80075ba: 881b ldrh r3, [r3, #0]
80075bc: b29b uxth r3, r3
80075be: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80075c2: f023 0340 bic.w r3, r3, #64 @ 0x40
80075c6: 84bb strh r3, [r7, #36] @ 0x24
80075c8: 687a ldr r2, [r7, #4]
80075ca: 683b ldr r3, [r7, #0]
80075cc: 781b ldrb r3, [r3, #0]
80075ce: 009b lsls r3, r3, #2
80075d0: 441a add r2, r3
80075d2: 8cbb ldrh r3, [r7, #36] @ 0x24
80075d4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80075d8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80075dc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80075e0: f043 0380 orr.w r3, r3, #128 @ 0x80
80075e4: b29b uxth r3, r3
80075e6: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80075e8: 687a ldr r2, [r7, #4]
80075ea: 683b ldr r3, [r7, #0]
80075ec: 781b ldrb r3, [r3, #0]
80075ee: 009b lsls r3, r3, #2
80075f0: 4413 add r3, r2
80075f2: 881b ldrh r3, [r3, #0]
80075f4: b29b uxth r3, r3
80075f6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80075fa: f023 0370 bic.w r3, r3, #112 @ 0x70
80075fe: 847b strh r3, [r7, #34] @ 0x22
8007600: 687a ldr r2, [r7, #4]
8007602: 683b ldr r3, [r7, #0]
8007604: 781b ldrb r3, [r3, #0]
8007606: 009b lsls r3, r3, #2
8007608: 441a add r2, r3
800760a: 8c7b ldrh r3, [r7, #34] @ 0x22
800760c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007610: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007614: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007618: f043 0380 orr.w r3, r3, #128 @ 0x80
800761c: b29b uxth r3, r3
800761e: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
8007620: 2300 movs r3, #0
}
8007622: 4618 mov r0, r3
8007624: 3734 adds r7, #52 @ 0x34
8007626: 46bd mov sp, r7
8007628: bc80 pop {r7}
800762a: 4770 bx lr
0800762c <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800762c: b580 push {r7, lr}
800762e: b0c2 sub sp, #264 @ 0x108
8007630: af00 add r7, sp, #0
8007632: f507 7384 add.w r3, r7, #264 @ 0x108
8007636: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800763a: 6018 str r0, [r3, #0]
800763c: f507 7384 add.w r3, r7, #264 @ 0x108
8007640: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007644: 6019 str r1, [r3, #0]
uint16_t pmabuffer;
uint16_t wEPVal;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
8007646: f507 7384 add.w r3, r7, #264 @ 0x108
800764a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800764e: 681b ldr r3, [r3, #0]
8007650: 785b ldrb r3, [r3, #1]
8007652: 2b01 cmp r3, #1
8007654: f040 86b7 bne.w 80083c6 <USB_EPStartXfer+0xd9a>
{
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
8007658: f507 7384 add.w r3, r7, #264 @ 0x108
800765c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007660: 681b ldr r3, [r3, #0]
8007662: 699a ldr r2, [r3, #24]
8007664: f507 7384 add.w r3, r7, #264 @ 0x108
8007668: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800766c: 681b ldr r3, [r3, #0]
800766e: 691b ldr r3, [r3, #16]
8007670: 429a cmp r2, r3
8007672: d908 bls.n 8007686 <USB_EPStartXfer+0x5a>
{
len = ep->maxpacket;
8007674: f507 7384 add.w r3, r7, #264 @ 0x108
8007678: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800767c: 681b ldr r3, [r3, #0]
800767e: 691b ldr r3, [r3, #16]
8007680: f8c7 3104 str.w r3, [r7, #260] @ 0x104
8007684: e007 b.n 8007696 <USB_EPStartXfer+0x6a>
}
else
{
len = ep->xfer_len;
8007686: f507 7384 add.w r3, r7, #264 @ 0x108
800768a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800768e: 681b ldr r3, [r3, #0]
8007690: 699b ldr r3, [r3, #24]
8007692: f8c7 3104 str.w r3, [r7, #260] @ 0x104
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
8007696: f507 7384 add.w r3, r7, #264 @ 0x108
800769a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800769e: 681b ldr r3, [r3, #0]
80076a0: 7b1b ldrb r3, [r3, #12]
80076a2: 2b00 cmp r3, #0
80076a4: d13a bne.n 800771c <USB_EPStartXfer+0xf0>
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
80076a6: f507 7384 add.w r3, r7, #264 @ 0x108
80076aa: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80076ae: 681b ldr r3, [r3, #0]
80076b0: 6959 ldr r1, [r3, #20]
80076b2: f507 7384 add.w r3, r7, #264 @ 0x108
80076b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80076ba: 681b ldr r3, [r3, #0]
80076bc: 88da ldrh r2, [r3, #6]
80076be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80076c2: b29b uxth r3, r3
80076c4: f507 7084 add.w r0, r7, #264 @ 0x108
80076c8: f5a0 7082 sub.w r0, r0, #260 @ 0x104
80076cc: 6800 ldr r0, [r0, #0]
80076ce: f001 fc9c bl 800900a <USB_WritePMA>
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
80076d2: f507 7384 add.w r3, r7, #264 @ 0x108
80076d6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80076da: 681b ldr r3, [r3, #0]
80076dc: 613b str r3, [r7, #16]
80076de: f507 7384 add.w r3, r7, #264 @ 0x108
80076e2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80076e6: 681b ldr r3, [r3, #0]
80076e8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80076ec: b29b uxth r3, r3
80076ee: 461a mov r2, r3
80076f0: 693b ldr r3, [r7, #16]
80076f2: 4413 add r3, r2
80076f4: 613b str r3, [r7, #16]
80076f6: f507 7384 add.w r3, r7, #264 @ 0x108
80076fa: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80076fe: 681b ldr r3, [r3, #0]
8007700: 781b ldrb r3, [r3, #0]
8007702: 011a lsls r2, r3, #4
8007704: 693b ldr r3, [r7, #16]
8007706: 4413 add r3, r2
8007708: f203 4304 addw r3, r3, #1028 @ 0x404
800770c: 60fb str r3, [r7, #12]
800770e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007712: b29a uxth r2, r3
8007714: 68fb ldr r3, [r7, #12]
8007716: 801a strh r2, [r3, #0]
8007718: f000 be1f b.w 800835a <USB_EPStartXfer+0xd2e>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
800771c: f507 7384 add.w r3, r7, #264 @ 0x108
8007720: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007724: 681b ldr r3, [r3, #0]
8007726: 78db ldrb r3, [r3, #3]
8007728: 2b02 cmp r3, #2
800772a: f040 8462 bne.w 8007ff2 <USB_EPStartXfer+0x9c6>
{
if (ep->xfer_len_db > ep->maxpacket)
800772e: f507 7384 add.w r3, r7, #264 @ 0x108
8007732: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007736: 681b ldr r3, [r3, #0]
8007738: 6a1a ldr r2, [r3, #32]
800773a: f507 7384 add.w r3, r7, #264 @ 0x108
800773e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007742: 681b ldr r3, [r3, #0]
8007744: 691b ldr r3, [r3, #16]
8007746: 429a cmp r2, r3
8007748: f240 83df bls.w 8007f0a <USB_EPStartXfer+0x8de>
{
/* enable double buffer */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
800774c: f507 7384 add.w r3, r7, #264 @ 0x108
8007750: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007754: 681a ldr r2, [r3, #0]
8007756: f507 7384 add.w r3, r7, #264 @ 0x108
800775a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800775e: 681b ldr r3, [r3, #0]
8007760: 781b ldrb r3, [r3, #0]
8007762: 009b lsls r3, r3, #2
8007764: 4413 add r3, r2
8007766: 881b ldrh r3, [r3, #0]
8007768: b29b uxth r3, r3
800776a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800776e: f023 0370 bic.w r3, r3, #112 @ 0x70
8007772: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
8007776: f507 7384 add.w r3, r7, #264 @ 0x108
800777a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800777e: 681a ldr r2, [r3, #0]
8007780: f507 7384 add.w r3, r7, #264 @ 0x108
8007784: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007788: 681b ldr r3, [r3, #0]
800778a: 781b ldrb r3, [r3, #0]
800778c: 009b lsls r3, r3, #2
800778e: 441a add r2, r3
8007790: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
8007794: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007798: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800779c: f443 4301 orr.w r3, r3, #33024 @ 0x8100
80077a0: f043 0380 orr.w r3, r3, #128 @ 0x80
80077a4: b29b uxth r3, r3
80077a6: 8013 strh r3, [r2, #0]
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
80077a8: f507 7384 add.w r3, r7, #264 @ 0x108
80077ac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80077b0: 681b ldr r3, [r3, #0]
80077b2: 6a1a ldr r2, [r3, #32]
80077b4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80077b8: 1ad2 subs r2, r2, r3
80077ba: f507 7384 add.w r3, r7, #264 @ 0x108
80077be: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80077c2: 681b ldr r3, [r3, #0]
80077c4: 621a str r2, [r3, #32]
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
80077c6: f507 7384 add.w r3, r7, #264 @ 0x108
80077ca: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80077ce: 681a ldr r2, [r3, #0]
80077d0: f507 7384 add.w r3, r7, #264 @ 0x108
80077d4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80077d8: 681b ldr r3, [r3, #0]
80077da: 781b ldrb r3, [r3, #0]
80077dc: 009b lsls r3, r3, #2
80077de: 4413 add r3, r2
80077e0: 881b ldrh r3, [r3, #0]
80077e2: b29b uxth r3, r3
80077e4: f003 0340 and.w r3, r3, #64 @ 0x40
80077e8: 2b00 cmp r3, #0
80077ea: f000 81c7 beq.w 8007b7c <USB_EPStartXfer+0x550>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
80077ee: f507 7384 add.w r3, r7, #264 @ 0x108
80077f2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80077f6: 681b ldr r3, [r3, #0]
80077f8: 633b str r3, [r7, #48] @ 0x30
80077fa: f507 7384 add.w r3, r7, #264 @ 0x108
80077fe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007802: 681b ldr r3, [r3, #0]
8007804: 785b ldrb r3, [r3, #1]
8007806: 2b00 cmp r3, #0
8007808: d177 bne.n 80078fa <USB_EPStartXfer+0x2ce>
800780a: f507 7384 add.w r3, r7, #264 @ 0x108
800780e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007812: 681b ldr r3, [r3, #0]
8007814: 62bb str r3, [r7, #40] @ 0x28
8007816: f507 7384 add.w r3, r7, #264 @ 0x108
800781a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800781e: 681b ldr r3, [r3, #0]
8007820: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007824: b29b uxth r3, r3
8007826: 461a mov r2, r3
8007828: 6abb ldr r3, [r7, #40] @ 0x28
800782a: 4413 add r3, r2
800782c: 62bb str r3, [r7, #40] @ 0x28
800782e: f507 7384 add.w r3, r7, #264 @ 0x108
8007832: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007836: 681b ldr r3, [r3, #0]
8007838: 781b ldrb r3, [r3, #0]
800783a: 011a lsls r2, r3, #4
800783c: 6abb ldr r3, [r7, #40] @ 0x28
800783e: 4413 add r3, r2
8007840: f203 430c addw r3, r3, #1036 @ 0x40c
8007844: 627b str r3, [r7, #36] @ 0x24
8007846: 6a7b ldr r3, [r7, #36] @ 0x24
8007848: 881b ldrh r3, [r3, #0]
800784a: b29b uxth r3, r3
800784c: f3c3 0309 ubfx r3, r3, #0, #10
8007850: b29a uxth r2, r3
8007852: 6a7b ldr r3, [r7, #36] @ 0x24
8007854: 801a strh r2, [r3, #0]
8007856: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800785a: 2b3e cmp r3, #62 @ 0x3e
800785c: d921 bls.n 80078a2 <USB_EPStartXfer+0x276>
800785e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007862: 095b lsrs r3, r3, #5
8007864: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8007868: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800786c: f003 031f and.w r3, r3, #31
8007870: 2b00 cmp r3, #0
8007872: d104 bne.n 800787e <USB_EPStartXfer+0x252>
8007874: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8007878: 3b01 subs r3, #1
800787a: f8c7 3100 str.w r3, [r7, #256] @ 0x100
800787e: 6a7b ldr r3, [r7, #36] @ 0x24
8007880: 881b ldrh r3, [r3, #0]
8007882: b29a uxth r2, r3
8007884: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8007888: b29b uxth r3, r3
800788a: 029b lsls r3, r3, #10
800788c: b29b uxth r3, r3
800788e: 4313 orrs r3, r2
8007890: b29b uxth r3, r3
8007892: ea6f 4343 mvn.w r3, r3, lsl #17
8007896: ea6f 4353 mvn.w r3, r3, lsr #17
800789a: b29a uxth r2, r3
800789c: 6a7b ldr r3, [r7, #36] @ 0x24
800789e: 801a strh r2, [r3, #0]
80078a0: e050 b.n 8007944 <USB_EPStartXfer+0x318>
80078a2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80078a6: 2b00 cmp r3, #0
80078a8: d10a bne.n 80078c0 <USB_EPStartXfer+0x294>
80078aa: 6a7b ldr r3, [r7, #36] @ 0x24
80078ac: 881b ldrh r3, [r3, #0]
80078ae: b29b uxth r3, r3
80078b0: ea6f 4343 mvn.w r3, r3, lsl #17
80078b4: ea6f 4353 mvn.w r3, r3, lsr #17
80078b8: b29a uxth r2, r3
80078ba: 6a7b ldr r3, [r7, #36] @ 0x24
80078bc: 801a strh r2, [r3, #0]
80078be: e041 b.n 8007944 <USB_EPStartXfer+0x318>
80078c0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80078c4: 085b lsrs r3, r3, #1
80078c6: f8c7 3100 str.w r3, [r7, #256] @ 0x100
80078ca: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80078ce: f003 0301 and.w r3, r3, #1
80078d2: 2b00 cmp r3, #0
80078d4: d004 beq.n 80078e0 <USB_EPStartXfer+0x2b4>
80078d6: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
80078da: 3301 adds r3, #1
80078dc: f8c7 3100 str.w r3, [r7, #256] @ 0x100
80078e0: 6a7b ldr r3, [r7, #36] @ 0x24
80078e2: 881b ldrh r3, [r3, #0]
80078e4: b29a uxth r2, r3
80078e6: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
80078ea: b29b uxth r3, r3
80078ec: 029b lsls r3, r3, #10
80078ee: b29b uxth r3, r3
80078f0: 4313 orrs r3, r2
80078f2: b29a uxth r2, r3
80078f4: 6a7b ldr r3, [r7, #36] @ 0x24
80078f6: 801a strh r2, [r3, #0]
80078f8: e024 b.n 8007944 <USB_EPStartXfer+0x318>
80078fa: f507 7384 add.w r3, r7, #264 @ 0x108
80078fe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007902: 681b ldr r3, [r3, #0]
8007904: 785b ldrb r3, [r3, #1]
8007906: 2b01 cmp r3, #1
8007908: d11c bne.n 8007944 <USB_EPStartXfer+0x318>
800790a: f507 7384 add.w r3, r7, #264 @ 0x108
800790e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007912: 681b ldr r3, [r3, #0]
8007914: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007918: b29b uxth r3, r3
800791a: 461a mov r2, r3
800791c: 6b3b ldr r3, [r7, #48] @ 0x30
800791e: 4413 add r3, r2
8007920: 633b str r3, [r7, #48] @ 0x30
8007922: f507 7384 add.w r3, r7, #264 @ 0x108
8007926: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800792a: 681b ldr r3, [r3, #0]
800792c: 781b ldrb r3, [r3, #0]
800792e: 011a lsls r2, r3, #4
8007930: 6b3b ldr r3, [r7, #48] @ 0x30
8007932: 4413 add r3, r2
8007934: f203 430c addw r3, r3, #1036 @ 0x40c
8007938: 62fb str r3, [r7, #44] @ 0x2c
800793a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800793e: b29a uxth r2, r3
8007940: 6afb ldr r3, [r7, #44] @ 0x2c
8007942: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8007944: f507 7384 add.w r3, r7, #264 @ 0x108
8007948: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800794c: 681b ldr r3, [r3, #0]
800794e: 895b ldrh r3, [r3, #10]
8007950: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007954: f507 7384 add.w r3, r7, #264 @ 0x108
8007958: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800795c: 681b ldr r3, [r3, #0]
800795e: 6959 ldr r1, [r3, #20]
8007960: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007964: b29b uxth r3, r3
8007966: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800796a: f507 7084 add.w r0, r7, #264 @ 0x108
800796e: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007972: 6800 ldr r0, [r0, #0]
8007974: f001 fb49 bl 800900a <USB_WritePMA>
ep->xfer_buff += len;
8007978: f507 7384 add.w r3, r7, #264 @ 0x108
800797c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007980: 681b ldr r3, [r3, #0]
8007982: 695a ldr r2, [r3, #20]
8007984: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007988: 441a add r2, r3
800798a: f507 7384 add.w r3, r7, #264 @ 0x108
800798e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007992: 681b ldr r3, [r3, #0]
8007994: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8007996: f507 7384 add.w r3, r7, #264 @ 0x108
800799a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800799e: 681b ldr r3, [r3, #0]
80079a0: 6a1a ldr r2, [r3, #32]
80079a2: f507 7384 add.w r3, r7, #264 @ 0x108
80079a6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079aa: 681b ldr r3, [r3, #0]
80079ac: 691b ldr r3, [r3, #16]
80079ae: 429a cmp r2, r3
80079b0: d90f bls.n 80079d2 <USB_EPStartXfer+0x3a6>
{
ep->xfer_len_db -= len;
80079b2: f507 7384 add.w r3, r7, #264 @ 0x108
80079b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079ba: 681b ldr r3, [r3, #0]
80079bc: 6a1a ldr r2, [r3, #32]
80079be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80079c2: 1ad2 subs r2, r2, r3
80079c4: f507 7384 add.w r3, r7, #264 @ 0x108
80079c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079cc: 681b ldr r3, [r3, #0]
80079ce: 621a str r2, [r3, #32]
80079d0: e00e b.n 80079f0 <USB_EPStartXfer+0x3c4>
}
else
{
len = ep->xfer_len_db;
80079d2: f507 7384 add.w r3, r7, #264 @ 0x108
80079d6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079da: 681b ldr r3, [r3, #0]
80079dc: 6a1b ldr r3, [r3, #32]
80079de: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
80079e2: f507 7384 add.w r3, r7, #264 @ 0x108
80079e6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079ea: 681b ldr r3, [r3, #0]
80079ec: 2200 movs r2, #0
80079ee: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
80079f0: f507 7384 add.w r3, r7, #264 @ 0x108
80079f4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079f8: 681b ldr r3, [r3, #0]
80079fa: 785b ldrb r3, [r3, #1]
80079fc: 2b00 cmp r3, #0
80079fe: d177 bne.n 8007af0 <USB_EPStartXfer+0x4c4>
8007a00: f507 7384 add.w r3, r7, #264 @ 0x108
8007a04: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007a08: 681b ldr r3, [r3, #0]
8007a0a: 61bb str r3, [r7, #24]
8007a0c: f507 7384 add.w r3, r7, #264 @ 0x108
8007a10: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007a14: 681b ldr r3, [r3, #0]
8007a16: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007a1a: b29b uxth r3, r3
8007a1c: 461a mov r2, r3
8007a1e: 69bb ldr r3, [r7, #24]
8007a20: 4413 add r3, r2
8007a22: 61bb str r3, [r7, #24]
8007a24: f507 7384 add.w r3, r7, #264 @ 0x108
8007a28: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007a2c: 681b ldr r3, [r3, #0]
8007a2e: 781b ldrb r3, [r3, #0]
8007a30: 011a lsls r2, r3, #4
8007a32: 69bb ldr r3, [r7, #24]
8007a34: 4413 add r3, r2
8007a36: f203 4304 addw r3, r3, #1028 @ 0x404
8007a3a: 617b str r3, [r7, #20]
8007a3c: 697b ldr r3, [r7, #20]
8007a3e: 881b ldrh r3, [r3, #0]
8007a40: b29b uxth r3, r3
8007a42: f3c3 0309 ubfx r3, r3, #0, #10
8007a46: b29a uxth r2, r3
8007a48: 697b ldr r3, [r7, #20]
8007a4a: 801a strh r2, [r3, #0]
8007a4c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a50: 2b3e cmp r3, #62 @ 0x3e
8007a52: d921 bls.n 8007a98 <USB_EPStartXfer+0x46c>
8007a54: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a58: 095b lsrs r3, r3, #5
8007a5a: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007a5e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a62: f003 031f and.w r3, r3, #31
8007a66: 2b00 cmp r3, #0
8007a68: d104 bne.n 8007a74 <USB_EPStartXfer+0x448>
8007a6a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007a6e: 3b01 subs r3, #1
8007a70: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007a74: 697b ldr r3, [r7, #20]
8007a76: 881b ldrh r3, [r3, #0]
8007a78: b29a uxth r2, r3
8007a7a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007a7e: b29b uxth r3, r3
8007a80: 029b lsls r3, r3, #10
8007a82: b29b uxth r3, r3
8007a84: 4313 orrs r3, r2
8007a86: b29b uxth r3, r3
8007a88: ea6f 4343 mvn.w r3, r3, lsl #17
8007a8c: ea6f 4353 mvn.w r3, r3, lsr #17
8007a90: b29a uxth r2, r3
8007a92: 697b ldr r3, [r7, #20]
8007a94: 801a strh r2, [r3, #0]
8007a96: e056 b.n 8007b46 <USB_EPStartXfer+0x51a>
8007a98: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a9c: 2b00 cmp r3, #0
8007a9e: d10a bne.n 8007ab6 <USB_EPStartXfer+0x48a>
8007aa0: 697b ldr r3, [r7, #20]
8007aa2: 881b ldrh r3, [r3, #0]
8007aa4: b29b uxth r3, r3
8007aa6: ea6f 4343 mvn.w r3, r3, lsl #17
8007aaa: ea6f 4353 mvn.w r3, r3, lsr #17
8007aae: b29a uxth r2, r3
8007ab0: 697b ldr r3, [r7, #20]
8007ab2: 801a strh r2, [r3, #0]
8007ab4: e047 b.n 8007b46 <USB_EPStartXfer+0x51a>
8007ab6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007aba: 085b lsrs r3, r3, #1
8007abc: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007ac0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007ac4: f003 0301 and.w r3, r3, #1
8007ac8: 2b00 cmp r3, #0
8007aca: d004 beq.n 8007ad6 <USB_EPStartXfer+0x4aa>
8007acc: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007ad0: 3301 adds r3, #1
8007ad2: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007ad6: 697b ldr r3, [r7, #20]
8007ad8: 881b ldrh r3, [r3, #0]
8007ada: b29a uxth r2, r3
8007adc: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007ae0: b29b uxth r3, r3
8007ae2: 029b lsls r3, r3, #10
8007ae4: b29b uxth r3, r3
8007ae6: 4313 orrs r3, r2
8007ae8: b29a uxth r2, r3
8007aea: 697b ldr r3, [r7, #20]
8007aec: 801a strh r2, [r3, #0]
8007aee: e02a b.n 8007b46 <USB_EPStartXfer+0x51a>
8007af0: f507 7384 add.w r3, r7, #264 @ 0x108
8007af4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007af8: 681b ldr r3, [r3, #0]
8007afa: 785b ldrb r3, [r3, #1]
8007afc: 2b01 cmp r3, #1
8007afe: d122 bne.n 8007b46 <USB_EPStartXfer+0x51a>
8007b00: f507 7384 add.w r3, r7, #264 @ 0x108
8007b04: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007b08: 681b ldr r3, [r3, #0]
8007b0a: 623b str r3, [r7, #32]
8007b0c: f507 7384 add.w r3, r7, #264 @ 0x108
8007b10: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007b14: 681b ldr r3, [r3, #0]
8007b16: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007b1a: b29b uxth r3, r3
8007b1c: 461a mov r2, r3
8007b1e: 6a3b ldr r3, [r7, #32]
8007b20: 4413 add r3, r2
8007b22: 623b str r3, [r7, #32]
8007b24: f507 7384 add.w r3, r7, #264 @ 0x108
8007b28: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b2c: 681b ldr r3, [r3, #0]
8007b2e: 781b ldrb r3, [r3, #0]
8007b30: 011a lsls r2, r3, #4
8007b32: 6a3b ldr r3, [r7, #32]
8007b34: 4413 add r3, r2
8007b36: f203 4304 addw r3, r3, #1028 @ 0x404
8007b3a: 61fb str r3, [r7, #28]
8007b3c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007b40: b29a uxth r2, r3
8007b42: 69fb ldr r3, [r7, #28]
8007b44: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8007b46: f507 7384 add.w r3, r7, #264 @ 0x108
8007b4a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b4e: 681b ldr r3, [r3, #0]
8007b50: 891b ldrh r3, [r3, #8]
8007b52: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007b56: f507 7384 add.w r3, r7, #264 @ 0x108
8007b5a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b5e: 681b ldr r3, [r3, #0]
8007b60: 6959 ldr r1, [r3, #20]
8007b62: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007b66: b29b uxth r3, r3
8007b68: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007b6c: f507 7084 add.w r0, r7, #264 @ 0x108
8007b70: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007b74: 6800 ldr r0, [r0, #0]
8007b76: f001 fa48 bl 800900a <USB_WritePMA>
8007b7a: e3ee b.n 800835a <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8007b7c: f507 7384 add.w r3, r7, #264 @ 0x108
8007b80: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b84: 681b ldr r3, [r3, #0]
8007b86: 785b ldrb r3, [r3, #1]
8007b88: 2b00 cmp r3, #0
8007b8a: d177 bne.n 8007c7c <USB_EPStartXfer+0x650>
8007b8c: f507 7384 add.w r3, r7, #264 @ 0x108
8007b90: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007b94: 681b ldr r3, [r3, #0]
8007b96: 64bb str r3, [r7, #72] @ 0x48
8007b98: f507 7384 add.w r3, r7, #264 @ 0x108
8007b9c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007ba0: 681b ldr r3, [r3, #0]
8007ba2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007ba6: b29b uxth r3, r3
8007ba8: 461a mov r2, r3
8007baa: 6cbb ldr r3, [r7, #72] @ 0x48
8007bac: 4413 add r3, r2
8007bae: 64bb str r3, [r7, #72] @ 0x48
8007bb0: f507 7384 add.w r3, r7, #264 @ 0x108
8007bb4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007bb8: 681b ldr r3, [r3, #0]
8007bba: 781b ldrb r3, [r3, #0]
8007bbc: 011a lsls r2, r3, #4
8007bbe: 6cbb ldr r3, [r7, #72] @ 0x48
8007bc0: 4413 add r3, r2
8007bc2: f203 4304 addw r3, r3, #1028 @ 0x404
8007bc6: 647b str r3, [r7, #68] @ 0x44
8007bc8: 6c7b ldr r3, [r7, #68] @ 0x44
8007bca: 881b ldrh r3, [r3, #0]
8007bcc: b29b uxth r3, r3
8007bce: f3c3 0309 ubfx r3, r3, #0, #10
8007bd2: b29a uxth r2, r3
8007bd4: 6c7b ldr r3, [r7, #68] @ 0x44
8007bd6: 801a strh r2, [r3, #0]
8007bd8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007bdc: 2b3e cmp r3, #62 @ 0x3e
8007bde: d921 bls.n 8007c24 <USB_EPStartXfer+0x5f8>
8007be0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007be4: 095b lsrs r3, r3, #5
8007be6: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007bea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007bee: f003 031f and.w r3, r3, #31
8007bf2: 2b00 cmp r3, #0
8007bf4: d104 bne.n 8007c00 <USB_EPStartXfer+0x5d4>
8007bf6: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007bfa: 3b01 subs r3, #1
8007bfc: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007c00: 6c7b ldr r3, [r7, #68] @ 0x44
8007c02: 881b ldrh r3, [r3, #0]
8007c04: b29a uxth r2, r3
8007c06: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007c0a: b29b uxth r3, r3
8007c0c: 029b lsls r3, r3, #10
8007c0e: b29b uxth r3, r3
8007c10: 4313 orrs r3, r2
8007c12: b29b uxth r3, r3
8007c14: ea6f 4343 mvn.w r3, r3, lsl #17
8007c18: ea6f 4353 mvn.w r3, r3, lsr #17
8007c1c: b29a uxth r2, r3
8007c1e: 6c7b ldr r3, [r7, #68] @ 0x44
8007c20: 801a strh r2, [r3, #0]
8007c22: e056 b.n 8007cd2 <USB_EPStartXfer+0x6a6>
8007c24: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007c28: 2b00 cmp r3, #0
8007c2a: d10a bne.n 8007c42 <USB_EPStartXfer+0x616>
8007c2c: 6c7b ldr r3, [r7, #68] @ 0x44
8007c2e: 881b ldrh r3, [r3, #0]
8007c30: b29b uxth r3, r3
8007c32: ea6f 4343 mvn.w r3, r3, lsl #17
8007c36: ea6f 4353 mvn.w r3, r3, lsr #17
8007c3a: b29a uxth r2, r3
8007c3c: 6c7b ldr r3, [r7, #68] @ 0x44
8007c3e: 801a strh r2, [r3, #0]
8007c40: e047 b.n 8007cd2 <USB_EPStartXfer+0x6a6>
8007c42: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007c46: 085b lsrs r3, r3, #1
8007c48: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007c4c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007c50: f003 0301 and.w r3, r3, #1
8007c54: 2b00 cmp r3, #0
8007c56: d004 beq.n 8007c62 <USB_EPStartXfer+0x636>
8007c58: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007c5c: 3301 adds r3, #1
8007c5e: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007c62: 6c7b ldr r3, [r7, #68] @ 0x44
8007c64: 881b ldrh r3, [r3, #0]
8007c66: b29a uxth r2, r3
8007c68: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007c6c: b29b uxth r3, r3
8007c6e: 029b lsls r3, r3, #10
8007c70: b29b uxth r3, r3
8007c72: 4313 orrs r3, r2
8007c74: b29a uxth r2, r3
8007c76: 6c7b ldr r3, [r7, #68] @ 0x44
8007c78: 801a strh r2, [r3, #0]
8007c7a: e02a b.n 8007cd2 <USB_EPStartXfer+0x6a6>
8007c7c: f507 7384 add.w r3, r7, #264 @ 0x108
8007c80: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007c84: 681b ldr r3, [r3, #0]
8007c86: 785b ldrb r3, [r3, #1]
8007c88: 2b01 cmp r3, #1
8007c8a: d122 bne.n 8007cd2 <USB_EPStartXfer+0x6a6>
8007c8c: f507 7384 add.w r3, r7, #264 @ 0x108
8007c90: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007c94: 681b ldr r3, [r3, #0]
8007c96: 653b str r3, [r7, #80] @ 0x50
8007c98: f507 7384 add.w r3, r7, #264 @ 0x108
8007c9c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007ca0: 681b ldr r3, [r3, #0]
8007ca2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007ca6: b29b uxth r3, r3
8007ca8: 461a mov r2, r3
8007caa: 6d3b ldr r3, [r7, #80] @ 0x50
8007cac: 4413 add r3, r2
8007cae: 653b str r3, [r7, #80] @ 0x50
8007cb0: f507 7384 add.w r3, r7, #264 @ 0x108
8007cb4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cb8: 681b ldr r3, [r3, #0]
8007cba: 781b ldrb r3, [r3, #0]
8007cbc: 011a lsls r2, r3, #4
8007cbe: 6d3b ldr r3, [r7, #80] @ 0x50
8007cc0: 4413 add r3, r2
8007cc2: f203 4304 addw r3, r3, #1028 @ 0x404
8007cc6: 64fb str r3, [r7, #76] @ 0x4c
8007cc8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007ccc: b29a uxth r2, r3
8007cce: 6cfb ldr r3, [r7, #76] @ 0x4c
8007cd0: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8007cd2: f507 7384 add.w r3, r7, #264 @ 0x108
8007cd6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cda: 681b ldr r3, [r3, #0]
8007cdc: 891b ldrh r3, [r3, #8]
8007cde: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007ce2: f507 7384 add.w r3, r7, #264 @ 0x108
8007ce6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cea: 681b ldr r3, [r3, #0]
8007cec: 6959 ldr r1, [r3, #20]
8007cee: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007cf2: b29b uxth r3, r3
8007cf4: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007cf8: f507 7084 add.w r0, r7, #264 @ 0x108
8007cfc: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007d00: 6800 ldr r0, [r0, #0]
8007d02: f001 f982 bl 800900a <USB_WritePMA>
ep->xfer_buff += len;
8007d06: f507 7384 add.w r3, r7, #264 @ 0x108
8007d0a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d0e: 681b ldr r3, [r3, #0]
8007d10: 695a ldr r2, [r3, #20]
8007d12: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007d16: 441a add r2, r3
8007d18: f507 7384 add.w r3, r7, #264 @ 0x108
8007d1c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d20: 681b ldr r3, [r3, #0]
8007d22: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8007d24: f507 7384 add.w r3, r7, #264 @ 0x108
8007d28: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d2c: 681b ldr r3, [r3, #0]
8007d2e: 6a1a ldr r2, [r3, #32]
8007d30: f507 7384 add.w r3, r7, #264 @ 0x108
8007d34: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d38: 681b ldr r3, [r3, #0]
8007d3a: 691b ldr r3, [r3, #16]
8007d3c: 429a cmp r2, r3
8007d3e: d90f bls.n 8007d60 <USB_EPStartXfer+0x734>
{
ep->xfer_len_db -= len;
8007d40: f507 7384 add.w r3, r7, #264 @ 0x108
8007d44: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d48: 681b ldr r3, [r3, #0]
8007d4a: 6a1a ldr r2, [r3, #32]
8007d4c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007d50: 1ad2 subs r2, r2, r3
8007d52: f507 7384 add.w r3, r7, #264 @ 0x108
8007d56: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d5a: 681b ldr r3, [r3, #0]
8007d5c: 621a str r2, [r3, #32]
8007d5e: e00e b.n 8007d7e <USB_EPStartXfer+0x752>
}
else
{
len = ep->xfer_len_db;
8007d60: f507 7384 add.w r3, r7, #264 @ 0x108
8007d64: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d68: 681b ldr r3, [r3, #0]
8007d6a: 6a1b ldr r3, [r3, #32]
8007d6c: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
8007d70: f507 7384 add.w r3, r7, #264 @ 0x108
8007d74: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d78: 681b ldr r3, [r3, #0]
8007d7a: 2200 movs r2, #0
8007d7c: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8007d7e: f507 7384 add.w r3, r7, #264 @ 0x108
8007d82: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007d86: 681b ldr r3, [r3, #0]
8007d88: 643b str r3, [r7, #64] @ 0x40
8007d8a: f507 7384 add.w r3, r7, #264 @ 0x108
8007d8e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d92: 681b ldr r3, [r3, #0]
8007d94: 785b ldrb r3, [r3, #1]
8007d96: 2b00 cmp r3, #0
8007d98: d177 bne.n 8007e8a <USB_EPStartXfer+0x85e>
8007d9a: f507 7384 add.w r3, r7, #264 @ 0x108
8007d9e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007da2: 681b ldr r3, [r3, #0]
8007da4: 63bb str r3, [r7, #56] @ 0x38
8007da6: f507 7384 add.w r3, r7, #264 @ 0x108
8007daa: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007dae: 681b ldr r3, [r3, #0]
8007db0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007db4: b29b uxth r3, r3
8007db6: 461a mov r2, r3
8007db8: 6bbb ldr r3, [r7, #56] @ 0x38
8007dba: 4413 add r3, r2
8007dbc: 63bb str r3, [r7, #56] @ 0x38
8007dbe: f507 7384 add.w r3, r7, #264 @ 0x108
8007dc2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007dc6: 681b ldr r3, [r3, #0]
8007dc8: 781b ldrb r3, [r3, #0]
8007dca: 011a lsls r2, r3, #4
8007dcc: 6bbb ldr r3, [r7, #56] @ 0x38
8007dce: 4413 add r3, r2
8007dd0: f203 430c addw r3, r3, #1036 @ 0x40c
8007dd4: 637b str r3, [r7, #52] @ 0x34
8007dd6: 6b7b ldr r3, [r7, #52] @ 0x34
8007dd8: 881b ldrh r3, [r3, #0]
8007dda: b29b uxth r3, r3
8007ddc: f3c3 0309 ubfx r3, r3, #0, #10
8007de0: b29a uxth r2, r3
8007de2: 6b7b ldr r3, [r7, #52] @ 0x34
8007de4: 801a strh r2, [r3, #0]
8007de6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007dea: 2b3e cmp r3, #62 @ 0x3e
8007dec: d921 bls.n 8007e32 <USB_EPStartXfer+0x806>
8007dee: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007df2: 095b lsrs r3, r3, #5
8007df4: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007df8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007dfc: f003 031f and.w r3, r3, #31
8007e00: 2b00 cmp r3, #0
8007e02: d104 bne.n 8007e0e <USB_EPStartXfer+0x7e2>
8007e04: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007e08: 3b01 subs r3, #1
8007e0a: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007e0e: 6b7b ldr r3, [r7, #52] @ 0x34
8007e10: 881b ldrh r3, [r3, #0]
8007e12: b29a uxth r2, r3
8007e14: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007e18: b29b uxth r3, r3
8007e1a: 029b lsls r3, r3, #10
8007e1c: b29b uxth r3, r3
8007e1e: 4313 orrs r3, r2
8007e20: b29b uxth r3, r3
8007e22: ea6f 4343 mvn.w r3, r3, lsl #17
8007e26: ea6f 4353 mvn.w r3, r3, lsr #17
8007e2a: b29a uxth r2, r3
8007e2c: 6b7b ldr r3, [r7, #52] @ 0x34
8007e2e: 801a strh r2, [r3, #0]
8007e30: e050 b.n 8007ed4 <USB_EPStartXfer+0x8a8>
8007e32: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e36: 2b00 cmp r3, #0
8007e38: d10a bne.n 8007e50 <USB_EPStartXfer+0x824>
8007e3a: 6b7b ldr r3, [r7, #52] @ 0x34
8007e3c: 881b ldrh r3, [r3, #0]
8007e3e: b29b uxth r3, r3
8007e40: ea6f 4343 mvn.w r3, r3, lsl #17
8007e44: ea6f 4353 mvn.w r3, r3, lsr #17
8007e48: b29a uxth r2, r3
8007e4a: 6b7b ldr r3, [r7, #52] @ 0x34
8007e4c: 801a strh r2, [r3, #0]
8007e4e: e041 b.n 8007ed4 <USB_EPStartXfer+0x8a8>
8007e50: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e54: 085b lsrs r3, r3, #1
8007e56: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007e5a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e5e: f003 0301 and.w r3, r3, #1
8007e62: 2b00 cmp r3, #0
8007e64: d004 beq.n 8007e70 <USB_EPStartXfer+0x844>
8007e66: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007e6a: 3301 adds r3, #1
8007e6c: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007e70: 6b7b ldr r3, [r7, #52] @ 0x34
8007e72: 881b ldrh r3, [r3, #0]
8007e74: b29a uxth r2, r3
8007e76: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007e7a: b29b uxth r3, r3
8007e7c: 029b lsls r3, r3, #10
8007e7e: b29b uxth r3, r3
8007e80: 4313 orrs r3, r2
8007e82: b29a uxth r2, r3
8007e84: 6b7b ldr r3, [r7, #52] @ 0x34
8007e86: 801a strh r2, [r3, #0]
8007e88: e024 b.n 8007ed4 <USB_EPStartXfer+0x8a8>
8007e8a: f507 7384 add.w r3, r7, #264 @ 0x108
8007e8e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007e92: 681b ldr r3, [r3, #0]
8007e94: 785b ldrb r3, [r3, #1]
8007e96: 2b01 cmp r3, #1
8007e98: d11c bne.n 8007ed4 <USB_EPStartXfer+0x8a8>
8007e9a: f507 7384 add.w r3, r7, #264 @ 0x108
8007e9e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007ea2: 681b ldr r3, [r3, #0]
8007ea4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007ea8: b29b uxth r3, r3
8007eaa: 461a mov r2, r3
8007eac: 6c3b ldr r3, [r7, #64] @ 0x40
8007eae: 4413 add r3, r2
8007eb0: 643b str r3, [r7, #64] @ 0x40
8007eb2: f507 7384 add.w r3, r7, #264 @ 0x108
8007eb6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007eba: 681b ldr r3, [r3, #0]
8007ebc: 781b ldrb r3, [r3, #0]
8007ebe: 011a lsls r2, r3, #4
8007ec0: 6c3b ldr r3, [r7, #64] @ 0x40
8007ec2: 4413 add r3, r2
8007ec4: f203 430c addw r3, r3, #1036 @ 0x40c
8007ec8: 63fb str r3, [r7, #60] @ 0x3c
8007eca: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007ece: b29a uxth r2, r3
8007ed0: 6bfb ldr r3, [r7, #60] @ 0x3c
8007ed2: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8007ed4: f507 7384 add.w r3, r7, #264 @ 0x108
8007ed8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007edc: 681b ldr r3, [r3, #0]
8007ede: 895b ldrh r3, [r3, #10]
8007ee0: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007ee4: f507 7384 add.w r3, r7, #264 @ 0x108
8007ee8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007eec: 681b ldr r3, [r3, #0]
8007eee: 6959 ldr r1, [r3, #20]
8007ef0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007ef4: b29b uxth r3, r3
8007ef6: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007efa: f507 7084 add.w r0, r7, #264 @ 0x108
8007efe: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007f02: 6800 ldr r0, [r0, #0]
8007f04: f001 f881 bl 800900a <USB_WritePMA>
8007f08: e227 b.n 800835a <USB_EPStartXfer+0xd2e>
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
8007f0a: f507 7384 add.w r3, r7, #264 @ 0x108
8007f0e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007f12: 681b ldr r3, [r3, #0]
8007f14: 6a1b ldr r3, [r3, #32]
8007f16: f8c7 3104 str.w r3, [r7, #260] @ 0x104
/* disable double buffer mode for Bulk endpoint */
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
8007f1a: f507 7384 add.w r3, r7, #264 @ 0x108
8007f1e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f22: 681a ldr r2, [r3, #0]
8007f24: f507 7384 add.w r3, r7, #264 @ 0x108
8007f28: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007f2c: 681b ldr r3, [r3, #0]
8007f2e: 781b ldrb r3, [r3, #0]
8007f30: 009b lsls r3, r3, #2
8007f32: 4413 add r3, r2
8007f34: 881b ldrh r3, [r3, #0]
8007f36: b29b uxth r3, r3
8007f38: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8007f3c: f023 0370 bic.w r3, r3, #112 @ 0x70
8007f40: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8007f44: f507 7384 add.w r3, r7, #264 @ 0x108
8007f48: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f4c: 681a ldr r2, [r3, #0]
8007f4e: f507 7384 add.w r3, r7, #264 @ 0x108
8007f52: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007f56: 681b ldr r3, [r3, #0]
8007f58: 781b ldrb r3, [r3, #0]
8007f5a: 009b lsls r3, r3, #2
8007f5c: 441a add r2, r3
8007f5e: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
8007f62: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007f66: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007f6a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007f6e: f043 0380 orr.w r3, r3, #128 @ 0x80
8007f72: b29b uxth r3, r3
8007f74: 8013 strh r3, [r2, #0]
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
8007f76: f507 7384 add.w r3, r7, #264 @ 0x108
8007f7a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f7e: 681b ldr r3, [r3, #0]
8007f80: 65fb str r3, [r7, #92] @ 0x5c
8007f82: f507 7384 add.w r3, r7, #264 @ 0x108
8007f86: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f8a: 681b ldr r3, [r3, #0]
8007f8c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007f90: b29b uxth r3, r3
8007f92: 461a mov r2, r3
8007f94: 6dfb ldr r3, [r7, #92] @ 0x5c
8007f96: 4413 add r3, r2
8007f98: 65fb str r3, [r7, #92] @ 0x5c
8007f9a: f507 7384 add.w r3, r7, #264 @ 0x108
8007f9e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007fa2: 681b ldr r3, [r3, #0]
8007fa4: 781b ldrb r3, [r3, #0]
8007fa6: 011a lsls r2, r3, #4
8007fa8: 6dfb ldr r3, [r7, #92] @ 0x5c
8007faa: 4413 add r3, r2
8007fac: f203 4304 addw r3, r3, #1028 @ 0x404
8007fb0: 65bb str r3, [r7, #88] @ 0x58
8007fb2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007fb6: b29a uxth r2, r3
8007fb8: 6dbb ldr r3, [r7, #88] @ 0x58
8007fba: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8007fbc: f507 7384 add.w r3, r7, #264 @ 0x108
8007fc0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007fc4: 681b ldr r3, [r3, #0]
8007fc6: 891b ldrh r3, [r3, #8]
8007fc8: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007fcc: f507 7384 add.w r3, r7, #264 @ 0x108
8007fd0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007fd4: 681b ldr r3, [r3, #0]
8007fd6: 6959 ldr r1, [r3, #20]
8007fd8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007fdc: b29b uxth r3, r3
8007fde: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007fe2: f507 7084 add.w r0, r7, #264 @ 0x108
8007fe6: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007fea: 6800 ldr r0, [r0, #0]
8007fec: f001 f80d bl 800900a <USB_WritePMA>
8007ff0: e1b3 b.n 800835a <USB_EPStartXfer+0xd2e>
}
}
else /* manage isochronous double buffer IN mode */
{
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
8007ff2: f507 7384 add.w r3, r7, #264 @ 0x108
8007ff6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007ffa: 681b ldr r3, [r3, #0]
8007ffc: 6a1a ldr r2, [r3, #32]
8007ffe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008002: 1ad2 subs r2, r2, r3
8008004: f507 7384 add.w r3, r7, #264 @ 0x108
8008008: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800800c: 681b ldr r3, [r3, #0]
800800e: 621a str r2, [r3, #32]
/* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8008010: f507 7384 add.w r3, r7, #264 @ 0x108
8008014: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008018: 681a ldr r2, [r3, #0]
800801a: f507 7384 add.w r3, r7, #264 @ 0x108
800801e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008022: 681b ldr r3, [r3, #0]
8008024: 781b ldrb r3, [r3, #0]
8008026: 009b lsls r3, r3, #2
8008028: 4413 add r3, r2
800802a: 881b ldrh r3, [r3, #0]
800802c: b29b uxth r3, r3
800802e: f003 0340 and.w r3, r3, #64 @ 0x40
8008032: 2b00 cmp r3, #0
8008034: f000 80c6 beq.w 80081c4 <USB_EPStartXfer+0xb98>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8008038: f507 7384 add.w r3, r7, #264 @ 0x108
800803c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008040: 681b ldr r3, [r3, #0]
8008042: 673b str r3, [r7, #112] @ 0x70
8008044: f507 7384 add.w r3, r7, #264 @ 0x108
8008048: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800804c: 681b ldr r3, [r3, #0]
800804e: 785b ldrb r3, [r3, #1]
8008050: 2b00 cmp r3, #0
8008052: d177 bne.n 8008144 <USB_EPStartXfer+0xb18>
8008054: f507 7384 add.w r3, r7, #264 @ 0x108
8008058: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800805c: 681b ldr r3, [r3, #0]
800805e: 66bb str r3, [r7, #104] @ 0x68
8008060: f507 7384 add.w r3, r7, #264 @ 0x108
8008064: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008068: 681b ldr r3, [r3, #0]
800806a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800806e: b29b uxth r3, r3
8008070: 461a mov r2, r3
8008072: 6ebb ldr r3, [r7, #104] @ 0x68
8008074: 4413 add r3, r2
8008076: 66bb str r3, [r7, #104] @ 0x68
8008078: f507 7384 add.w r3, r7, #264 @ 0x108
800807c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008080: 681b ldr r3, [r3, #0]
8008082: 781b ldrb r3, [r3, #0]
8008084: 011a lsls r2, r3, #4
8008086: 6ebb ldr r3, [r7, #104] @ 0x68
8008088: 4413 add r3, r2
800808a: f203 430c addw r3, r3, #1036 @ 0x40c
800808e: 667b str r3, [r7, #100] @ 0x64
8008090: 6e7b ldr r3, [r7, #100] @ 0x64
8008092: 881b ldrh r3, [r3, #0]
8008094: b29b uxth r3, r3
8008096: f3c3 0309 ubfx r3, r3, #0, #10
800809a: b29a uxth r2, r3
800809c: 6e7b ldr r3, [r7, #100] @ 0x64
800809e: 801a strh r2, [r3, #0]
80080a0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080a4: 2b3e cmp r3, #62 @ 0x3e
80080a6: d921 bls.n 80080ec <USB_EPStartXfer+0xac0>
80080a8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080ac: 095b lsrs r3, r3, #5
80080ae: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
80080b2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080b6: f003 031f and.w r3, r3, #31
80080ba: 2b00 cmp r3, #0
80080bc: d104 bne.n 80080c8 <USB_EPStartXfer+0xa9c>
80080be: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
80080c2: 3b01 subs r3, #1
80080c4: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
80080c8: 6e7b ldr r3, [r7, #100] @ 0x64
80080ca: 881b ldrh r3, [r3, #0]
80080cc: b29a uxth r2, r3
80080ce: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
80080d2: b29b uxth r3, r3
80080d4: 029b lsls r3, r3, #10
80080d6: b29b uxth r3, r3
80080d8: 4313 orrs r3, r2
80080da: b29b uxth r3, r3
80080dc: ea6f 4343 mvn.w r3, r3, lsl #17
80080e0: ea6f 4353 mvn.w r3, r3, lsr #17
80080e4: b29a uxth r2, r3
80080e6: 6e7b ldr r3, [r7, #100] @ 0x64
80080e8: 801a strh r2, [r3, #0]
80080ea: e050 b.n 800818e <USB_EPStartXfer+0xb62>
80080ec: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080f0: 2b00 cmp r3, #0
80080f2: d10a bne.n 800810a <USB_EPStartXfer+0xade>
80080f4: 6e7b ldr r3, [r7, #100] @ 0x64
80080f6: 881b ldrh r3, [r3, #0]
80080f8: b29b uxth r3, r3
80080fa: ea6f 4343 mvn.w r3, r3, lsl #17
80080fe: ea6f 4353 mvn.w r3, r3, lsr #17
8008102: b29a uxth r2, r3
8008104: 6e7b ldr r3, [r7, #100] @ 0x64
8008106: 801a strh r2, [r3, #0]
8008108: e041 b.n 800818e <USB_EPStartXfer+0xb62>
800810a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800810e: 085b lsrs r3, r3, #1
8008110: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8008114: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008118: f003 0301 and.w r3, r3, #1
800811c: 2b00 cmp r3, #0
800811e: d004 beq.n 800812a <USB_EPStartXfer+0xafe>
8008120: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8008124: 3301 adds r3, #1
8008126: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
800812a: 6e7b ldr r3, [r7, #100] @ 0x64
800812c: 881b ldrh r3, [r3, #0]
800812e: b29a uxth r2, r3
8008130: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8008134: b29b uxth r3, r3
8008136: 029b lsls r3, r3, #10
8008138: b29b uxth r3, r3
800813a: 4313 orrs r3, r2
800813c: b29a uxth r2, r3
800813e: 6e7b ldr r3, [r7, #100] @ 0x64
8008140: 801a strh r2, [r3, #0]
8008142: e024 b.n 800818e <USB_EPStartXfer+0xb62>
8008144: f507 7384 add.w r3, r7, #264 @ 0x108
8008148: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800814c: 681b ldr r3, [r3, #0]
800814e: 785b ldrb r3, [r3, #1]
8008150: 2b01 cmp r3, #1
8008152: d11c bne.n 800818e <USB_EPStartXfer+0xb62>
8008154: f507 7384 add.w r3, r7, #264 @ 0x108
8008158: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800815c: 681b ldr r3, [r3, #0]
800815e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008162: b29b uxth r3, r3
8008164: 461a mov r2, r3
8008166: 6f3b ldr r3, [r7, #112] @ 0x70
8008168: 4413 add r3, r2
800816a: 673b str r3, [r7, #112] @ 0x70
800816c: f507 7384 add.w r3, r7, #264 @ 0x108
8008170: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008174: 681b ldr r3, [r3, #0]
8008176: 781b ldrb r3, [r3, #0]
8008178: 011a lsls r2, r3, #4
800817a: 6f3b ldr r3, [r7, #112] @ 0x70
800817c: 4413 add r3, r2
800817e: f203 430c addw r3, r3, #1036 @ 0x40c
8008182: 66fb str r3, [r7, #108] @ 0x6c
8008184: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008188: b29a uxth r2, r3
800818a: 6efb ldr r3, [r7, #108] @ 0x6c
800818c: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800818e: f507 7384 add.w r3, r7, #264 @ 0x108
8008192: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008196: 681b ldr r3, [r3, #0]
8008198: 895b ldrh r3, [r3, #10]
800819a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800819e: f507 7384 add.w r3, r7, #264 @ 0x108
80081a2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80081a6: 681b ldr r3, [r3, #0]
80081a8: 6959 ldr r1, [r3, #20]
80081aa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80081ae: b29b uxth r3, r3
80081b0: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
80081b4: f507 7084 add.w r0, r7, #264 @ 0x108
80081b8: f5a0 7082 sub.w r0, r0, #260 @ 0x104
80081bc: 6800 ldr r0, [r0, #0]
80081be: f000 ff24 bl 800900a <USB_WritePMA>
80081c2: e0ca b.n 800835a <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
80081c4: f507 7384 add.w r3, r7, #264 @ 0x108
80081c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80081cc: 681b ldr r3, [r3, #0]
80081ce: 785b ldrb r3, [r3, #1]
80081d0: 2b00 cmp r3, #0
80081d2: d177 bne.n 80082c4 <USB_EPStartXfer+0xc98>
80081d4: f507 7384 add.w r3, r7, #264 @ 0x108
80081d8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80081dc: 681b ldr r3, [r3, #0]
80081de: 67fb str r3, [r7, #124] @ 0x7c
80081e0: f507 7384 add.w r3, r7, #264 @ 0x108
80081e4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80081e8: 681b ldr r3, [r3, #0]
80081ea: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80081ee: b29b uxth r3, r3
80081f0: 461a mov r2, r3
80081f2: 6ffb ldr r3, [r7, #124] @ 0x7c
80081f4: 4413 add r3, r2
80081f6: 67fb str r3, [r7, #124] @ 0x7c
80081f8: f507 7384 add.w r3, r7, #264 @ 0x108
80081fc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008200: 681b ldr r3, [r3, #0]
8008202: 781b ldrb r3, [r3, #0]
8008204: 011a lsls r2, r3, #4
8008206: 6ffb ldr r3, [r7, #124] @ 0x7c
8008208: 4413 add r3, r2
800820a: f203 4304 addw r3, r3, #1028 @ 0x404
800820e: 67bb str r3, [r7, #120] @ 0x78
8008210: 6fbb ldr r3, [r7, #120] @ 0x78
8008212: 881b ldrh r3, [r3, #0]
8008214: b29b uxth r3, r3
8008216: f3c3 0309 ubfx r3, r3, #0, #10
800821a: b29a uxth r2, r3
800821c: 6fbb ldr r3, [r7, #120] @ 0x78
800821e: 801a strh r2, [r3, #0]
8008220: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008224: 2b3e cmp r3, #62 @ 0x3e
8008226: d921 bls.n 800826c <USB_EPStartXfer+0xc40>
8008228: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800822c: 095b lsrs r3, r3, #5
800822e: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8008232: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008236: f003 031f and.w r3, r3, #31
800823a: 2b00 cmp r3, #0
800823c: d104 bne.n 8008248 <USB_EPStartXfer+0xc1c>
800823e: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8008242: 3b01 subs r3, #1
8008244: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8008248: 6fbb ldr r3, [r7, #120] @ 0x78
800824a: 881b ldrh r3, [r3, #0]
800824c: b29a uxth r2, r3
800824e: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8008252: b29b uxth r3, r3
8008254: 029b lsls r3, r3, #10
8008256: b29b uxth r3, r3
8008258: 4313 orrs r3, r2
800825a: b29b uxth r3, r3
800825c: ea6f 4343 mvn.w r3, r3, lsl #17
8008260: ea6f 4353 mvn.w r3, r3, lsr #17
8008264: b29a uxth r2, r3
8008266: 6fbb ldr r3, [r7, #120] @ 0x78
8008268: 801a strh r2, [r3, #0]
800826a: e05c b.n 8008326 <USB_EPStartXfer+0xcfa>
800826c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008270: 2b00 cmp r3, #0
8008272: d10a bne.n 800828a <USB_EPStartXfer+0xc5e>
8008274: 6fbb ldr r3, [r7, #120] @ 0x78
8008276: 881b ldrh r3, [r3, #0]
8008278: b29b uxth r3, r3
800827a: ea6f 4343 mvn.w r3, r3, lsl #17
800827e: ea6f 4353 mvn.w r3, r3, lsr #17
8008282: b29a uxth r2, r3
8008284: 6fbb ldr r3, [r7, #120] @ 0x78
8008286: 801a strh r2, [r3, #0]
8008288: e04d b.n 8008326 <USB_EPStartXfer+0xcfa>
800828a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800828e: 085b lsrs r3, r3, #1
8008290: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8008294: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008298: f003 0301 and.w r3, r3, #1
800829c: 2b00 cmp r3, #0
800829e: d004 beq.n 80082aa <USB_EPStartXfer+0xc7e>
80082a0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
80082a4: 3301 adds r3, #1
80082a6: f8c7 30ec str.w r3, [r7, #236] @ 0xec
80082aa: 6fbb ldr r3, [r7, #120] @ 0x78
80082ac: 881b ldrh r3, [r3, #0]
80082ae: b29a uxth r2, r3
80082b0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
80082b4: b29b uxth r3, r3
80082b6: 029b lsls r3, r3, #10
80082b8: b29b uxth r3, r3
80082ba: 4313 orrs r3, r2
80082bc: b29a uxth r2, r3
80082be: 6fbb ldr r3, [r7, #120] @ 0x78
80082c0: 801a strh r2, [r3, #0]
80082c2: e030 b.n 8008326 <USB_EPStartXfer+0xcfa>
80082c4: f507 7384 add.w r3, r7, #264 @ 0x108
80082c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80082cc: 681b ldr r3, [r3, #0]
80082ce: 785b ldrb r3, [r3, #1]
80082d0: 2b01 cmp r3, #1
80082d2: d128 bne.n 8008326 <USB_EPStartXfer+0xcfa>
80082d4: f507 7384 add.w r3, r7, #264 @ 0x108
80082d8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80082dc: 681b ldr r3, [r3, #0]
80082de: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80082e2: f507 7384 add.w r3, r7, #264 @ 0x108
80082e6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80082ea: 681b ldr r3, [r3, #0]
80082ec: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80082f0: b29b uxth r3, r3
80082f2: 461a mov r2, r3
80082f4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
80082f8: 4413 add r3, r2
80082fa: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80082fe: f507 7384 add.w r3, r7, #264 @ 0x108
8008302: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008306: 681b ldr r3, [r3, #0]
8008308: 781b ldrb r3, [r3, #0]
800830a: 011a lsls r2, r3, #4
800830c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8008310: 4413 add r3, r2
8008312: f203 4304 addw r3, r3, #1028 @ 0x404
8008316: f8c7 3080 str.w r3, [r7, #128] @ 0x80
800831a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800831e: b29a uxth r2, r3
8008320: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8008324: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8008326: f507 7384 add.w r3, r7, #264 @ 0x108
800832a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800832e: 681b ldr r3, [r3, #0]
8008330: 891b ldrh r3, [r3, #8]
8008332: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8008336: f507 7384 add.w r3, r7, #264 @ 0x108
800833a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800833e: 681b ldr r3, [r3, #0]
8008340: 6959 ldr r1, [r3, #20]
8008342: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008346: b29b uxth r3, r3
8008348: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800834c: f507 7084 add.w r0, r7, #264 @ 0x108
8008350: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8008354: 6800 ldr r0, [r0, #0]
8008356: f000 fe58 bl 800900a <USB_WritePMA>
}
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
800835a: f507 7384 add.w r3, r7, #264 @ 0x108
800835e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008362: 681a ldr r2, [r3, #0]
8008364: f507 7384 add.w r3, r7, #264 @ 0x108
8008368: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800836c: 681b ldr r3, [r3, #0]
800836e: 781b ldrb r3, [r3, #0]
8008370: 009b lsls r3, r3, #2
8008372: 4413 add r3, r2
8008374: 881b ldrh r3, [r3, #0]
8008376: b29b uxth r3, r3
8008378: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800837c: f023 0340 bic.w r3, r3, #64 @ 0x40
8008380: 817b strh r3, [r7, #10]
8008382: 897b ldrh r3, [r7, #10]
8008384: f083 0310 eor.w r3, r3, #16
8008388: 817b strh r3, [r7, #10]
800838a: 897b ldrh r3, [r7, #10]
800838c: f083 0320 eor.w r3, r3, #32
8008390: 817b strh r3, [r7, #10]
8008392: f507 7384 add.w r3, r7, #264 @ 0x108
8008396: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800839a: 681a ldr r2, [r3, #0]
800839c: f507 7384 add.w r3, r7, #264 @ 0x108
80083a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083a4: 681b ldr r3, [r3, #0]
80083a6: 781b ldrb r3, [r3, #0]
80083a8: 009b lsls r3, r3, #2
80083aa: 441a add r2, r3
80083ac: 897b ldrh r3, [r7, #10]
80083ae: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80083b2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80083b6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80083ba: f043 0380 orr.w r3, r3, #128 @ 0x80
80083be: b29b uxth r3, r3
80083c0: 8013 strh r3, [r2, #0]
80083c2: f000 bcde b.w 8008d82 <USB_EPStartXfer+0x1756>
}
else /* OUT endpoint */
{
if (ep->doublebuffer == 0U)
80083c6: f507 7384 add.w r3, r7, #264 @ 0x108
80083ca: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083ce: 681b ldr r3, [r3, #0]
80083d0: 7b1b ldrb r3, [r3, #12]
80083d2: 2b00 cmp r3, #0
80083d4: f040 80bb bne.w 800854e <USB_EPStartXfer+0xf22>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
80083d8: f507 7384 add.w r3, r7, #264 @ 0x108
80083dc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083e0: 681b ldr r3, [r3, #0]
80083e2: 699a ldr r2, [r3, #24]
80083e4: f507 7384 add.w r3, r7, #264 @ 0x108
80083e8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083ec: 681b ldr r3, [r3, #0]
80083ee: 691b ldr r3, [r3, #16]
80083f0: 429a cmp r2, r3
80083f2: d917 bls.n 8008424 <USB_EPStartXfer+0xdf8>
{
len = ep->maxpacket;
80083f4: f507 7384 add.w r3, r7, #264 @ 0x108
80083f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083fc: 681b ldr r3, [r3, #0]
80083fe: 691b ldr r3, [r3, #16]
8008400: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
8008404: f507 7384 add.w r3, r7, #264 @ 0x108
8008408: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800840c: 681b ldr r3, [r3, #0]
800840e: 699a ldr r2, [r3, #24]
8008410: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008414: 1ad2 subs r2, r2, r3
8008416: f507 7384 add.w r3, r7, #264 @ 0x108
800841a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800841e: 681b ldr r3, [r3, #0]
8008420: 619a str r2, [r3, #24]
8008422: e00e b.n 8008442 <USB_EPStartXfer+0xe16>
}
else
{
len = ep->xfer_len;
8008424: f507 7384 add.w r3, r7, #264 @ 0x108
8008428: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800842c: 681b ldr r3, [r3, #0]
800842e: 699b ldr r3, [r3, #24]
8008430: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
8008434: f507 7384 add.w r3, r7, #264 @ 0x108
8008438: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800843c: 681b ldr r3, [r3, #0]
800843e: 2200 movs r2, #0
8008440: 619a str r2, [r3, #24]
}
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
8008442: f507 7384 add.w r3, r7, #264 @ 0x108
8008446: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800844a: 681b ldr r3, [r3, #0]
800844c: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8008450: f507 7384 add.w r3, r7, #264 @ 0x108
8008454: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008458: 681b ldr r3, [r3, #0]
800845a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800845e: b29b uxth r3, r3
8008460: 461a mov r2, r3
8008462: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8008466: 4413 add r3, r2
8008468: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800846c: f507 7384 add.w r3, r7, #264 @ 0x108
8008470: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008474: 681b ldr r3, [r3, #0]
8008476: 781b ldrb r3, [r3, #0]
8008478: 011a lsls r2, r3, #4
800847a: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800847e: 4413 add r3, r2
8008480: f203 430c addw r3, r3, #1036 @ 0x40c
8008484: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8008488: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800848c: 881b ldrh r3, [r3, #0]
800848e: b29b uxth r3, r3
8008490: f3c3 0309 ubfx r3, r3, #0, #10
8008494: b29a uxth r2, r3
8008496: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800849a: 801a strh r2, [r3, #0]
800849c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084a0: 2b3e cmp r3, #62 @ 0x3e
80084a2: d924 bls.n 80084ee <USB_EPStartXfer+0xec2>
80084a4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084a8: 095b lsrs r3, r3, #5
80084aa: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
80084ae: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084b2: f003 031f and.w r3, r3, #31
80084b6: 2b00 cmp r3, #0
80084b8: d104 bne.n 80084c4 <USB_EPStartXfer+0xe98>
80084ba: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80084be: 3b01 subs r3, #1
80084c0: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
80084c4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80084c8: 881b ldrh r3, [r3, #0]
80084ca: b29a uxth r2, r3
80084cc: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80084d0: b29b uxth r3, r3
80084d2: 029b lsls r3, r3, #10
80084d4: b29b uxth r3, r3
80084d6: 4313 orrs r3, r2
80084d8: b29b uxth r3, r3
80084da: ea6f 4343 mvn.w r3, r3, lsl #17
80084de: ea6f 4353 mvn.w r3, r3, lsr #17
80084e2: b29a uxth r2, r3
80084e4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80084e8: 801a strh r2, [r3, #0]
80084ea: f000 bc10 b.w 8008d0e <USB_EPStartXfer+0x16e2>
80084ee: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084f2: 2b00 cmp r3, #0
80084f4: d10c bne.n 8008510 <USB_EPStartXfer+0xee4>
80084f6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80084fa: 881b ldrh r3, [r3, #0]
80084fc: b29b uxth r3, r3
80084fe: ea6f 4343 mvn.w r3, r3, lsl #17
8008502: ea6f 4353 mvn.w r3, r3, lsr #17
8008506: b29a uxth r2, r3
8008508: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800850c: 801a strh r2, [r3, #0]
800850e: e3fe b.n 8008d0e <USB_EPStartXfer+0x16e2>
8008510: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008514: 085b lsrs r3, r3, #1
8008516: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
800851a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800851e: f003 0301 and.w r3, r3, #1
8008522: 2b00 cmp r3, #0
8008524: d004 beq.n 8008530 <USB_EPStartXfer+0xf04>
8008526: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
800852a: 3301 adds r3, #1
800852c: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8008530: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8008534: 881b ldrh r3, [r3, #0]
8008536: b29a uxth r2, r3
8008538: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
800853c: b29b uxth r3, r3
800853e: 029b lsls r3, r3, #10
8008540: b29b uxth r3, r3
8008542: 4313 orrs r3, r2
8008544: b29a uxth r2, r3
8008546: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800854a: 801a strh r2, [r3, #0]
800854c: e3df b.n 8008d0e <USB_EPStartXfer+0x16e2>
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
800854e: f507 7384 add.w r3, r7, #264 @ 0x108
8008552: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008556: 681b ldr r3, [r3, #0]
8008558: 78db ldrb r3, [r3, #3]
800855a: 2b02 cmp r3, #2
800855c: f040 8218 bne.w 8008990 <USB_EPStartXfer+0x1364>
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
8008560: f507 7384 add.w r3, r7, #264 @ 0x108
8008564: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008568: 681b ldr r3, [r3, #0]
800856a: 785b ldrb r3, [r3, #1]
800856c: 2b00 cmp r3, #0
800856e: f040 809d bne.w 80086ac <USB_EPStartXfer+0x1080>
8008572: f507 7384 add.w r3, r7, #264 @ 0x108
8008576: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800857a: 681b ldr r3, [r3, #0]
800857c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8008580: f507 7384 add.w r3, r7, #264 @ 0x108
8008584: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008588: 681b ldr r3, [r3, #0]
800858a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800858e: b29b uxth r3, r3
8008590: 461a mov r2, r3
8008592: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8008596: 4413 add r3, r2
8008598: f8c7 30ac str.w r3, [r7, #172] @ 0xac
800859c: f507 7384 add.w r3, r7, #264 @ 0x108
80085a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085a4: 681b ldr r3, [r3, #0]
80085a6: 781b ldrb r3, [r3, #0]
80085a8: 011a lsls r2, r3, #4
80085aa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80085ae: 4413 add r3, r2
80085b0: f203 4304 addw r3, r3, #1028 @ 0x404
80085b4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
80085b8: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80085bc: 881b ldrh r3, [r3, #0]
80085be: b29b uxth r3, r3
80085c0: f3c3 0309 ubfx r3, r3, #0, #10
80085c4: b29a uxth r2, r3
80085c6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80085ca: 801a strh r2, [r3, #0]
80085cc: f507 7384 add.w r3, r7, #264 @ 0x108
80085d0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085d4: 681b ldr r3, [r3, #0]
80085d6: 691b ldr r3, [r3, #16]
80085d8: 2b3e cmp r3, #62 @ 0x3e
80085da: d92b bls.n 8008634 <USB_EPStartXfer+0x1008>
80085dc: f507 7384 add.w r3, r7, #264 @ 0x108
80085e0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085e4: 681b ldr r3, [r3, #0]
80085e6: 691b ldr r3, [r3, #16]
80085e8: 095b lsrs r3, r3, #5
80085ea: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80085ee: f507 7384 add.w r3, r7, #264 @ 0x108
80085f2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085f6: 681b ldr r3, [r3, #0]
80085f8: 691b ldr r3, [r3, #16]
80085fa: f003 031f and.w r3, r3, #31
80085fe: 2b00 cmp r3, #0
8008600: d104 bne.n 800860c <USB_EPStartXfer+0xfe0>
8008602: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8008606: 3b01 subs r3, #1
8008608: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
800860c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008610: 881b ldrh r3, [r3, #0]
8008612: b29a uxth r2, r3
8008614: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8008618: b29b uxth r3, r3
800861a: 029b lsls r3, r3, #10
800861c: b29b uxth r3, r3
800861e: 4313 orrs r3, r2
8008620: b29b uxth r3, r3
8008622: ea6f 4343 mvn.w r3, r3, lsl #17
8008626: ea6f 4353 mvn.w r3, r3, lsr #17
800862a: b29a uxth r2, r3
800862c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008630: 801a strh r2, [r3, #0]
8008632: e070 b.n 8008716 <USB_EPStartXfer+0x10ea>
8008634: f507 7384 add.w r3, r7, #264 @ 0x108
8008638: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800863c: 681b ldr r3, [r3, #0]
800863e: 691b ldr r3, [r3, #16]
8008640: 2b00 cmp r3, #0
8008642: d10c bne.n 800865e <USB_EPStartXfer+0x1032>
8008644: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008648: 881b ldrh r3, [r3, #0]
800864a: b29b uxth r3, r3
800864c: ea6f 4343 mvn.w r3, r3, lsl #17
8008650: ea6f 4353 mvn.w r3, r3, lsr #17
8008654: b29a uxth r2, r3
8008656: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800865a: 801a strh r2, [r3, #0]
800865c: e05b b.n 8008716 <USB_EPStartXfer+0x10ea>
800865e: f507 7384 add.w r3, r7, #264 @ 0x108
8008662: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008666: 681b ldr r3, [r3, #0]
8008668: 691b ldr r3, [r3, #16]
800866a: 085b lsrs r3, r3, #1
800866c: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
8008670: f507 7384 add.w r3, r7, #264 @ 0x108
8008674: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008678: 681b ldr r3, [r3, #0]
800867a: 691b ldr r3, [r3, #16]
800867c: f003 0301 and.w r3, r3, #1
8008680: 2b00 cmp r3, #0
8008682: d004 beq.n 800868e <USB_EPStartXfer+0x1062>
8008684: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8008688: 3301 adds r3, #1
800868a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
800868e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008692: 881b ldrh r3, [r3, #0]
8008694: b29a uxth r2, r3
8008696: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800869a: b29b uxth r3, r3
800869c: 029b lsls r3, r3, #10
800869e: b29b uxth r3, r3
80086a0: 4313 orrs r3, r2
80086a2: b29a uxth r2, r3
80086a4: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80086a8: 801a strh r2, [r3, #0]
80086aa: e034 b.n 8008716 <USB_EPStartXfer+0x10ea>
80086ac: f507 7384 add.w r3, r7, #264 @ 0x108
80086b0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80086b4: 681b ldr r3, [r3, #0]
80086b6: 785b ldrb r3, [r3, #1]
80086b8: 2b01 cmp r3, #1
80086ba: d12c bne.n 8008716 <USB_EPStartXfer+0x10ea>
80086bc: f507 7384 add.w r3, r7, #264 @ 0x108
80086c0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80086c4: 681b ldr r3, [r3, #0]
80086c6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80086ca: f507 7384 add.w r3, r7, #264 @ 0x108
80086ce: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80086d2: 681b ldr r3, [r3, #0]
80086d4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80086d8: b29b uxth r3, r3
80086da: 461a mov r2, r3
80086dc: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80086e0: 4413 add r3, r2
80086e2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80086e6: f507 7384 add.w r3, r7, #264 @ 0x108
80086ea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80086ee: 681b ldr r3, [r3, #0]
80086f0: 781b ldrb r3, [r3, #0]
80086f2: 011a lsls r2, r3, #4
80086f4: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80086f8: 4413 add r3, r2
80086fa: f203 4304 addw r3, r3, #1028 @ 0x404
80086fe: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8008702: f507 7384 add.w r3, r7, #264 @ 0x108
8008706: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800870a: 681b ldr r3, [r3, #0]
800870c: 691b ldr r3, [r3, #16]
800870e: b29a uxth r2, r3
8008710: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
8008714: 801a strh r2, [r3, #0]
8008716: f507 7384 add.w r3, r7, #264 @ 0x108
800871a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800871e: 681b ldr r3, [r3, #0]
8008720: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
8008724: f507 7384 add.w r3, r7, #264 @ 0x108
8008728: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800872c: 681b ldr r3, [r3, #0]
800872e: 785b ldrb r3, [r3, #1]
8008730: 2b00 cmp r3, #0
8008732: f040 809d bne.w 8008870 <USB_EPStartXfer+0x1244>
8008736: f507 7384 add.w r3, r7, #264 @ 0x108
800873a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800873e: 681b ldr r3, [r3, #0]
8008740: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8008744: f507 7384 add.w r3, r7, #264 @ 0x108
8008748: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800874c: 681b ldr r3, [r3, #0]
800874e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008752: b29b uxth r3, r3
8008754: 461a mov r2, r3
8008756: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800875a: 4413 add r3, r2
800875c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8008760: f507 7384 add.w r3, r7, #264 @ 0x108
8008764: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008768: 681b ldr r3, [r3, #0]
800876a: 781b ldrb r3, [r3, #0]
800876c: 011a lsls r2, r3, #4
800876e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8008772: 4413 add r3, r2
8008774: f203 430c addw r3, r3, #1036 @ 0x40c
8008778: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800877c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8008780: 881b ldrh r3, [r3, #0]
8008782: b29b uxth r3, r3
8008784: f3c3 0309 ubfx r3, r3, #0, #10
8008788: b29a uxth r2, r3
800878a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800878e: 801a strh r2, [r3, #0]
8008790: f507 7384 add.w r3, r7, #264 @ 0x108
8008794: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008798: 681b ldr r3, [r3, #0]
800879a: 691b ldr r3, [r3, #16]
800879c: 2b3e cmp r3, #62 @ 0x3e
800879e: d92b bls.n 80087f8 <USB_EPStartXfer+0x11cc>
80087a0: f507 7384 add.w r3, r7, #264 @ 0x108
80087a4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80087a8: 681b ldr r3, [r3, #0]
80087aa: 691b ldr r3, [r3, #16]
80087ac: 095b lsrs r3, r3, #5
80087ae: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
80087b2: f507 7384 add.w r3, r7, #264 @ 0x108
80087b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80087ba: 681b ldr r3, [r3, #0]
80087bc: 691b ldr r3, [r3, #16]
80087be: f003 031f and.w r3, r3, #31
80087c2: 2b00 cmp r3, #0
80087c4: d104 bne.n 80087d0 <USB_EPStartXfer+0x11a4>
80087c6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80087ca: 3b01 subs r3, #1
80087cc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
80087d0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80087d4: 881b ldrh r3, [r3, #0]
80087d6: b29a uxth r2, r3
80087d8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80087dc: b29b uxth r3, r3
80087de: 029b lsls r3, r3, #10
80087e0: b29b uxth r3, r3
80087e2: 4313 orrs r3, r2
80087e4: b29b uxth r3, r3
80087e6: ea6f 4343 mvn.w r3, r3, lsl #17
80087ea: ea6f 4353 mvn.w r3, r3, lsr #17
80087ee: b29a uxth r2, r3
80087f0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80087f4: 801a strh r2, [r3, #0]
80087f6: e069 b.n 80088cc <USB_EPStartXfer+0x12a0>
80087f8: f507 7384 add.w r3, r7, #264 @ 0x108
80087fc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008800: 681b ldr r3, [r3, #0]
8008802: 691b ldr r3, [r3, #16]
8008804: 2b00 cmp r3, #0
8008806: d10c bne.n 8008822 <USB_EPStartXfer+0x11f6>
8008808: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800880c: 881b ldrh r3, [r3, #0]
800880e: b29b uxth r3, r3
8008810: ea6f 4343 mvn.w r3, r3, lsl #17
8008814: ea6f 4353 mvn.w r3, r3, lsr #17
8008818: b29a uxth r2, r3
800881a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800881e: 801a strh r2, [r3, #0]
8008820: e054 b.n 80088cc <USB_EPStartXfer+0x12a0>
8008822: f507 7384 add.w r3, r7, #264 @ 0x108
8008826: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800882a: 681b ldr r3, [r3, #0]
800882c: 691b ldr r3, [r3, #16]
800882e: 085b lsrs r3, r3, #1
8008830: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8008834: f507 7384 add.w r3, r7, #264 @ 0x108
8008838: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800883c: 681b ldr r3, [r3, #0]
800883e: 691b ldr r3, [r3, #16]
8008840: f003 0301 and.w r3, r3, #1
8008844: 2b00 cmp r3, #0
8008846: d004 beq.n 8008852 <USB_EPStartXfer+0x1226>
8008848: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800884c: 3301 adds r3, #1
800884e: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8008852: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8008856: 881b ldrh r3, [r3, #0]
8008858: b29a uxth r2, r3
800885a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800885e: b29b uxth r3, r3
8008860: 029b lsls r3, r3, #10
8008862: b29b uxth r3, r3
8008864: 4313 orrs r3, r2
8008866: b29a uxth r2, r3
8008868: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800886c: 801a strh r2, [r3, #0]
800886e: e02d b.n 80088cc <USB_EPStartXfer+0x12a0>
8008870: f507 7384 add.w r3, r7, #264 @ 0x108
8008874: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008878: 681b ldr r3, [r3, #0]
800887a: 785b ldrb r3, [r3, #1]
800887c: 2b01 cmp r3, #1
800887e: d125 bne.n 80088cc <USB_EPStartXfer+0x12a0>
8008880: f507 7384 add.w r3, r7, #264 @ 0x108
8008884: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008888: 681b ldr r3, [r3, #0]
800888a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800888e: b29b uxth r3, r3
8008890: 461a mov r2, r3
8008892: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8008896: 4413 add r3, r2
8008898: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800889c: f507 7384 add.w r3, r7, #264 @ 0x108
80088a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80088a4: 681b ldr r3, [r3, #0]
80088a6: 781b ldrb r3, [r3, #0]
80088a8: 011a lsls r2, r3, #4
80088aa: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
80088ae: 4413 add r3, r2
80088b0: f203 430c addw r3, r3, #1036 @ 0x40c
80088b4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
80088b8: f507 7384 add.w r3, r7, #264 @ 0x108
80088bc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80088c0: 681b ldr r3, [r3, #0]
80088c2: 691b ldr r3, [r3, #16]
80088c4: b29a uxth r2, r3
80088c6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
80088ca: 801a strh r2, [r3, #0]
/* Coming from ISR */
if (ep->xfer_count != 0U)
80088cc: f507 7384 add.w r3, r7, #264 @ 0x108
80088d0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80088d4: 681b ldr r3, [r3, #0]
80088d6: 69db ldr r3, [r3, #28]
80088d8: 2b00 cmp r3, #0
80088da: f000 8218 beq.w 8008d0e <USB_EPStartXfer+0x16e2>
{
/* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
80088de: f507 7384 add.w r3, r7, #264 @ 0x108
80088e2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80088e6: 681a ldr r2, [r3, #0]
80088e8: f507 7384 add.w r3, r7, #264 @ 0x108
80088ec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80088f0: 681b ldr r3, [r3, #0]
80088f2: 781b ldrb r3, [r3, #0]
80088f4: 009b lsls r3, r3, #2
80088f6: 4413 add r3, r2
80088f8: 881b ldrh r3, [r3, #0]
80088fa: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
80088fe: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8008902: f403 4380 and.w r3, r3, #16384 @ 0x4000
8008906: 2b00 cmp r3, #0
8008908: d005 beq.n 8008916 <USB_EPStartXfer+0x12ea>
800890a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
800890e: f003 0340 and.w r3, r3, #64 @ 0x40
8008912: 2b00 cmp r3, #0
8008914: d10d bne.n 8008932 <USB_EPStartXfer+0x1306>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
8008916: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
800891a: f403 4380 and.w r3, r3, #16384 @ 0x4000
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
800891e: 2b00 cmp r3, #0
8008920: f040 81f5 bne.w 8008d0e <USB_EPStartXfer+0x16e2>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
8008924: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8008928: f003 0340 and.w r3, r3, #64 @ 0x40
800892c: 2b00 cmp r3, #0
800892e: f040 81ee bne.w 8008d0e <USB_EPStartXfer+0x16e2>
{
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
8008932: f507 7384 add.w r3, r7, #264 @ 0x108
8008936: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800893a: 681a ldr r2, [r3, #0]
800893c: f507 7384 add.w r3, r7, #264 @ 0x108
8008940: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008944: 681b ldr r3, [r3, #0]
8008946: 781b ldrb r3, [r3, #0]
8008948: 009b lsls r3, r3, #2
800894a: 4413 add r3, r2
800894c: 881b ldrh r3, [r3, #0]
800894e: b29b uxth r3, r3
8008950: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008954: f023 0370 bic.w r3, r3, #112 @ 0x70
8008958: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
800895c: f507 7384 add.w r3, r7, #264 @ 0x108
8008960: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008964: 681a ldr r2, [r3, #0]
8008966: f507 7384 add.w r3, r7, #264 @ 0x108
800896a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800896e: 681b ldr r3, [r3, #0]
8008970: 781b ldrb r3, [r3, #0]
8008972: 009b lsls r3, r3, #2
8008974: 441a add r2, r3
8008976: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800897a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800897e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008982: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008986: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800898a: b29b uxth r3, r3
800898c: 8013 strh r3, [r2, #0]
800898e: e1be b.n 8008d0e <USB_EPStartXfer+0x16e2>
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
8008990: f507 7384 add.w r3, r7, #264 @ 0x108
8008994: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008998: 681b ldr r3, [r3, #0]
800899a: 78db ldrb r3, [r3, #3]
800899c: 2b01 cmp r3, #1
800899e: f040 81b4 bne.w 8008d0a <USB_EPStartXfer+0x16de>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
80089a2: f507 7384 add.w r3, r7, #264 @ 0x108
80089a6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089aa: 681b ldr r3, [r3, #0]
80089ac: 699a ldr r2, [r3, #24]
80089ae: f507 7384 add.w r3, r7, #264 @ 0x108
80089b2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089b6: 681b ldr r3, [r3, #0]
80089b8: 691b ldr r3, [r3, #16]
80089ba: 429a cmp r2, r3
80089bc: d917 bls.n 80089ee <USB_EPStartXfer+0x13c2>
{
len = ep->maxpacket;
80089be: f507 7384 add.w r3, r7, #264 @ 0x108
80089c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089c6: 681b ldr r3, [r3, #0]
80089c8: 691b ldr r3, [r3, #16]
80089ca: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
80089ce: f507 7384 add.w r3, r7, #264 @ 0x108
80089d2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089d6: 681b ldr r3, [r3, #0]
80089d8: 699a ldr r2, [r3, #24]
80089da: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80089de: 1ad2 subs r2, r2, r3
80089e0: f507 7384 add.w r3, r7, #264 @ 0x108
80089e4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089e8: 681b ldr r3, [r3, #0]
80089ea: 619a str r2, [r3, #24]
80089ec: e00e b.n 8008a0c <USB_EPStartXfer+0x13e0>
}
else
{
len = ep->xfer_len;
80089ee: f507 7384 add.w r3, r7, #264 @ 0x108
80089f2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089f6: 681b ldr r3, [r3, #0]
80089f8: 699b ldr r3, [r3, #24]
80089fa: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
80089fe: f507 7384 add.w r3, r7, #264 @ 0x108
8008a02: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a06: 681b ldr r3, [r3, #0]
8008a08: 2200 movs r2, #0
8008a0a: 619a str r2, [r3, #24]
}
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
8008a0c: f507 7384 add.w r3, r7, #264 @ 0x108
8008a10: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a14: 681b ldr r3, [r3, #0]
8008a16: 785b ldrb r3, [r3, #1]
8008a18: 2b00 cmp r3, #0
8008a1a: f040 8085 bne.w 8008b28 <USB_EPStartXfer+0x14fc>
8008a1e: f507 7384 add.w r3, r7, #264 @ 0x108
8008a22: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008a26: 681b ldr r3, [r3, #0]
8008a28: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8008a2c: f507 7384 add.w r3, r7, #264 @ 0x108
8008a30: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008a34: 681b ldr r3, [r3, #0]
8008a36: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008a3a: b29b uxth r3, r3
8008a3c: 461a mov r2, r3
8008a3e: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8008a42: 4413 add r3, r2
8008a44: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8008a48: f507 7384 add.w r3, r7, #264 @ 0x108
8008a4c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a50: 681b ldr r3, [r3, #0]
8008a52: 781b ldrb r3, [r3, #0]
8008a54: 011a lsls r2, r3, #4
8008a56: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8008a5a: 4413 add r3, r2
8008a5c: f203 4304 addw r3, r3, #1028 @ 0x404
8008a60: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8008a64: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008a68: 881b ldrh r3, [r3, #0]
8008a6a: b29b uxth r3, r3
8008a6c: f3c3 0309 ubfx r3, r3, #0, #10
8008a70: b29a uxth r2, r3
8008a72: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008a76: 801a strh r2, [r3, #0]
8008a78: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a7c: 2b3e cmp r3, #62 @ 0x3e
8008a7e: d923 bls.n 8008ac8 <USB_EPStartXfer+0x149c>
8008a80: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a84: 095b lsrs r3, r3, #5
8008a86: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008a8a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a8e: f003 031f and.w r3, r3, #31
8008a92: 2b00 cmp r3, #0
8008a94: d104 bne.n 8008aa0 <USB_EPStartXfer+0x1474>
8008a96: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008a9a: 3b01 subs r3, #1
8008a9c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008aa0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008aa4: 881b ldrh r3, [r3, #0]
8008aa6: b29a uxth r2, r3
8008aa8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008aac: b29b uxth r3, r3
8008aae: 029b lsls r3, r3, #10
8008ab0: b29b uxth r3, r3
8008ab2: 4313 orrs r3, r2
8008ab4: b29b uxth r3, r3
8008ab6: ea6f 4343 mvn.w r3, r3, lsl #17
8008aba: ea6f 4353 mvn.w r3, r3, lsr #17
8008abe: b29a uxth r2, r3
8008ac0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008ac4: 801a strh r2, [r3, #0]
8008ac6: e060 b.n 8008b8a <USB_EPStartXfer+0x155e>
8008ac8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008acc: 2b00 cmp r3, #0
8008ace: d10c bne.n 8008aea <USB_EPStartXfer+0x14be>
8008ad0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008ad4: 881b ldrh r3, [r3, #0]
8008ad6: b29b uxth r3, r3
8008ad8: ea6f 4343 mvn.w r3, r3, lsl #17
8008adc: ea6f 4353 mvn.w r3, r3, lsr #17
8008ae0: b29a uxth r2, r3
8008ae2: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008ae6: 801a strh r2, [r3, #0]
8008ae8: e04f b.n 8008b8a <USB_EPStartXfer+0x155e>
8008aea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008aee: 085b lsrs r3, r3, #1
8008af0: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008af4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008af8: f003 0301 and.w r3, r3, #1
8008afc: 2b00 cmp r3, #0
8008afe: d004 beq.n 8008b0a <USB_EPStartXfer+0x14de>
8008b00: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008b04: 3301 adds r3, #1
8008b06: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008b0a: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008b0e: 881b ldrh r3, [r3, #0]
8008b10: b29a uxth r2, r3
8008b12: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008b16: b29b uxth r3, r3
8008b18: 029b lsls r3, r3, #10
8008b1a: b29b uxth r3, r3
8008b1c: 4313 orrs r3, r2
8008b1e: b29a uxth r2, r3
8008b20: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008b24: 801a strh r2, [r3, #0]
8008b26: e030 b.n 8008b8a <USB_EPStartXfer+0x155e>
8008b28: f507 7384 add.w r3, r7, #264 @ 0x108
8008b2c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b30: 681b ldr r3, [r3, #0]
8008b32: 785b ldrb r3, [r3, #1]
8008b34: 2b01 cmp r3, #1
8008b36: d128 bne.n 8008b8a <USB_EPStartXfer+0x155e>
8008b38: f507 7384 add.w r3, r7, #264 @ 0x108
8008b3c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b40: 681b ldr r3, [r3, #0]
8008b42: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8008b46: f507 7384 add.w r3, r7, #264 @ 0x108
8008b4a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b4e: 681b ldr r3, [r3, #0]
8008b50: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008b54: b29b uxth r3, r3
8008b56: 461a mov r2, r3
8008b58: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8008b5c: 4413 add r3, r2
8008b5e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8008b62: f507 7384 add.w r3, r7, #264 @ 0x108
8008b66: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b6a: 681b ldr r3, [r3, #0]
8008b6c: 781b ldrb r3, [r3, #0]
8008b6e: 011a lsls r2, r3, #4
8008b70: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8008b74: 4413 add r3, r2
8008b76: f203 4304 addw r3, r3, #1028 @ 0x404
8008b7a: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8008b7e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008b82: b29a uxth r2, r3
8008b84: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
8008b88: 801a strh r2, [r3, #0]
8008b8a: f507 7384 add.w r3, r7, #264 @ 0x108
8008b8e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b92: 681b ldr r3, [r3, #0]
8008b94: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8008b98: f507 7384 add.w r3, r7, #264 @ 0x108
8008b9c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ba0: 681b ldr r3, [r3, #0]
8008ba2: 785b ldrb r3, [r3, #1]
8008ba4: 2b00 cmp r3, #0
8008ba6: f040 8085 bne.w 8008cb4 <USB_EPStartXfer+0x1688>
8008baa: f507 7384 add.w r3, r7, #264 @ 0x108
8008bae: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008bb2: 681b ldr r3, [r3, #0]
8008bb4: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8008bb8: f507 7384 add.w r3, r7, #264 @ 0x108
8008bbc: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008bc0: 681b ldr r3, [r3, #0]
8008bc2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008bc6: b29b uxth r3, r3
8008bc8: 461a mov r2, r3
8008bca: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8008bce: 4413 add r3, r2
8008bd0: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8008bd4: f507 7384 add.w r3, r7, #264 @ 0x108
8008bd8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008bdc: 681b ldr r3, [r3, #0]
8008bde: 781b ldrb r3, [r3, #0]
8008be0: 011a lsls r2, r3, #4
8008be2: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8008be6: 4413 add r3, r2
8008be8: f203 430c addw r3, r3, #1036 @ 0x40c
8008bec: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8008bf0: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008bf4: 881b ldrh r3, [r3, #0]
8008bf6: b29b uxth r3, r3
8008bf8: f3c3 0309 ubfx r3, r3, #0, #10
8008bfc: b29a uxth r2, r3
8008bfe: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c02: 801a strh r2, [r3, #0]
8008c04: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c08: 2b3e cmp r3, #62 @ 0x3e
8008c0a: d923 bls.n 8008c54 <USB_EPStartXfer+0x1628>
8008c0c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c10: 095b lsrs r3, r3, #5
8008c12: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008c16: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c1a: f003 031f and.w r3, r3, #31
8008c1e: 2b00 cmp r3, #0
8008c20: d104 bne.n 8008c2c <USB_EPStartXfer+0x1600>
8008c22: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008c26: 3b01 subs r3, #1
8008c28: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008c2c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c30: 881b ldrh r3, [r3, #0]
8008c32: b29a uxth r2, r3
8008c34: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008c38: b29b uxth r3, r3
8008c3a: 029b lsls r3, r3, #10
8008c3c: b29b uxth r3, r3
8008c3e: 4313 orrs r3, r2
8008c40: b29b uxth r3, r3
8008c42: ea6f 4343 mvn.w r3, r3, lsl #17
8008c46: ea6f 4353 mvn.w r3, r3, lsr #17
8008c4a: b29a uxth r2, r3
8008c4c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c50: 801a strh r2, [r3, #0]
8008c52: e05c b.n 8008d0e <USB_EPStartXfer+0x16e2>
8008c54: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c58: 2b00 cmp r3, #0
8008c5a: d10c bne.n 8008c76 <USB_EPStartXfer+0x164a>
8008c5c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c60: 881b ldrh r3, [r3, #0]
8008c62: b29b uxth r3, r3
8008c64: ea6f 4343 mvn.w r3, r3, lsl #17
8008c68: ea6f 4353 mvn.w r3, r3, lsr #17
8008c6c: b29a uxth r2, r3
8008c6e: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c72: 801a strh r2, [r3, #0]
8008c74: e04b b.n 8008d0e <USB_EPStartXfer+0x16e2>
8008c76: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c7a: 085b lsrs r3, r3, #1
8008c7c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008c80: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c84: f003 0301 and.w r3, r3, #1
8008c88: 2b00 cmp r3, #0
8008c8a: d004 beq.n 8008c96 <USB_EPStartXfer+0x166a>
8008c8c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008c90: 3301 adds r3, #1
8008c92: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008c96: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c9a: 881b ldrh r3, [r3, #0]
8008c9c: b29a uxth r2, r3
8008c9e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008ca2: b29b uxth r3, r3
8008ca4: 029b lsls r3, r3, #10
8008ca6: b29b uxth r3, r3
8008ca8: 4313 orrs r3, r2
8008caa: b29a uxth r2, r3
8008cac: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008cb0: 801a strh r2, [r3, #0]
8008cb2: e02c b.n 8008d0e <USB_EPStartXfer+0x16e2>
8008cb4: f507 7384 add.w r3, r7, #264 @ 0x108
8008cb8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cbc: 681b ldr r3, [r3, #0]
8008cbe: 785b ldrb r3, [r3, #1]
8008cc0: 2b01 cmp r3, #1
8008cc2: d124 bne.n 8008d0e <USB_EPStartXfer+0x16e2>
8008cc4: f507 7384 add.w r3, r7, #264 @ 0x108
8008cc8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008ccc: 681b ldr r3, [r3, #0]
8008cce: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008cd2: b29b uxth r3, r3
8008cd4: 461a mov r2, r3
8008cd6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8008cda: 4413 add r3, r2
8008cdc: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8008ce0: f507 7384 add.w r3, r7, #264 @ 0x108
8008ce4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ce8: 681b ldr r3, [r3, #0]
8008cea: 781b ldrb r3, [r3, #0]
8008cec: 011a lsls r2, r3, #4
8008cee: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8008cf2: 4413 add r3, r2
8008cf4: f203 430c addw r3, r3, #1036 @ 0x40c
8008cf8: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8008cfc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008d00: b29a uxth r2, r3
8008d02: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8008d06: 801a strh r2, [r3, #0]
8008d08: e001 b.n 8008d0e <USB_EPStartXfer+0x16e2>
}
else
{
return HAL_ERROR;
8008d0a: 2301 movs r3, #1
8008d0c: e03a b.n 8008d84 <USB_EPStartXfer+0x1758>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8008d0e: f507 7384 add.w r3, r7, #264 @ 0x108
8008d12: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008d16: 681a ldr r2, [r3, #0]
8008d18: f507 7384 add.w r3, r7, #264 @ 0x108
8008d1c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008d20: 681b ldr r3, [r3, #0]
8008d22: 781b ldrb r3, [r3, #0]
8008d24: 009b lsls r3, r3, #2
8008d26: 4413 add r3, r2
8008d28: 881b ldrh r3, [r3, #0]
8008d2a: b29b uxth r3, r3
8008d2c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008d30: f023 0370 bic.w r3, r3, #112 @ 0x70
8008d34: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8008d38: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008d3c: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008d40: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8008d44: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008d48: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008d4c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8008d50: f507 7384 add.w r3, r7, #264 @ 0x108
8008d54: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008d58: 681a ldr r2, [r3, #0]
8008d5a: f507 7384 add.w r3, r7, #264 @ 0x108
8008d5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008d62: 681b ldr r3, [r3, #0]
8008d64: 781b ldrb r3, [r3, #0]
8008d66: 009b lsls r3, r3, #2
8008d68: 441a add r2, r3
8008d6a: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008d6e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008d72: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008d76: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008d7a: f043 0380 orr.w r3, r3, #128 @ 0x80
8008d7e: b29b uxth r3, r3
8008d80: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8008d82: 2300 movs r3, #0
}
8008d84: 4618 mov r0, r3
8008d86: f507 7784 add.w r7, r7, #264 @ 0x108
8008d8a: 46bd mov sp, r7
8008d8c: bd80 pop {r7, pc}
08008d8e <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8008d8e: b480 push {r7}
8008d90: b085 sub sp, #20
8008d92: af00 add r7, sp, #0
8008d94: 6078 str r0, [r7, #4]
8008d96: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
8008d98: 683b ldr r3, [r7, #0]
8008d9a: 785b ldrb r3, [r3, #1]
8008d9c: 2b00 cmp r3, #0
8008d9e: d020 beq.n 8008de2 <USB_EPSetStall+0x54>
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
8008da0: 687a ldr r2, [r7, #4]
8008da2: 683b ldr r3, [r7, #0]
8008da4: 781b ldrb r3, [r3, #0]
8008da6: 009b lsls r3, r3, #2
8008da8: 4413 add r3, r2
8008daa: 881b ldrh r3, [r3, #0]
8008dac: b29b uxth r3, r3
8008dae: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008db2: f023 0340 bic.w r3, r3, #64 @ 0x40
8008db6: 81bb strh r3, [r7, #12]
8008db8: 89bb ldrh r3, [r7, #12]
8008dba: f083 0310 eor.w r3, r3, #16
8008dbe: 81bb strh r3, [r7, #12]
8008dc0: 687a ldr r2, [r7, #4]
8008dc2: 683b ldr r3, [r7, #0]
8008dc4: 781b ldrb r3, [r3, #0]
8008dc6: 009b lsls r3, r3, #2
8008dc8: 441a add r2, r3
8008dca: 89bb ldrh r3, [r7, #12]
8008dcc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008dd0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008dd4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008dd8: f043 0380 orr.w r3, r3, #128 @ 0x80
8008ddc: b29b uxth r3, r3
8008dde: 8013 strh r3, [r2, #0]
8008de0: e01f b.n 8008e22 <USB_EPSetStall+0x94>
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
8008de2: 687a ldr r2, [r7, #4]
8008de4: 683b ldr r3, [r7, #0]
8008de6: 781b ldrb r3, [r3, #0]
8008de8: 009b lsls r3, r3, #2
8008dea: 4413 add r3, r2
8008dec: 881b ldrh r3, [r3, #0]
8008dee: b29b uxth r3, r3
8008df0: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008df4: f023 0370 bic.w r3, r3, #112 @ 0x70
8008df8: 81fb strh r3, [r7, #14]
8008dfa: 89fb ldrh r3, [r7, #14]
8008dfc: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008e00: 81fb strh r3, [r7, #14]
8008e02: 687a ldr r2, [r7, #4]
8008e04: 683b ldr r3, [r7, #0]
8008e06: 781b ldrb r3, [r3, #0]
8008e08: 009b lsls r3, r3, #2
8008e0a: 441a add r2, r3
8008e0c: 89fb ldrh r3, [r7, #14]
8008e0e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008e12: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008e16: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008e1a: f043 0380 orr.w r3, r3, #128 @ 0x80
8008e1e: b29b uxth r3, r3
8008e20: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8008e22: 2300 movs r3, #0
}
8008e24: 4618 mov r0, r3
8008e26: 3714 adds r7, #20
8008e28: 46bd mov sp, r7
8008e2a: bc80 pop {r7}
8008e2c: 4770 bx lr
08008e2e <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8008e2e: b480 push {r7}
8008e30: b087 sub sp, #28
8008e32: af00 add r7, sp, #0
8008e34: 6078 str r0, [r7, #4]
8008e36: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
8008e38: 683b ldr r3, [r7, #0]
8008e3a: 7b1b ldrb r3, [r3, #12]
8008e3c: 2b00 cmp r3, #0
8008e3e: f040 809d bne.w 8008f7c <USB_EPClearStall+0x14e>
{
if (ep->is_in != 0U)
8008e42: 683b ldr r3, [r7, #0]
8008e44: 785b ldrb r3, [r3, #1]
8008e46: 2b00 cmp r3, #0
8008e48: d04c beq.n 8008ee4 <USB_EPClearStall+0xb6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8008e4a: 687a ldr r2, [r7, #4]
8008e4c: 683b ldr r3, [r7, #0]
8008e4e: 781b ldrb r3, [r3, #0]
8008e50: 009b lsls r3, r3, #2
8008e52: 4413 add r3, r2
8008e54: 881b ldrh r3, [r3, #0]
8008e56: 823b strh r3, [r7, #16]
8008e58: 8a3b ldrh r3, [r7, #16]
8008e5a: f003 0340 and.w r3, r3, #64 @ 0x40
8008e5e: 2b00 cmp r3, #0
8008e60: d01b beq.n 8008e9a <USB_EPClearStall+0x6c>
8008e62: 687a ldr r2, [r7, #4]
8008e64: 683b ldr r3, [r7, #0]
8008e66: 781b ldrb r3, [r3, #0]
8008e68: 009b lsls r3, r3, #2
8008e6a: 4413 add r3, r2
8008e6c: 881b ldrh r3, [r3, #0]
8008e6e: b29b uxth r3, r3
8008e70: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008e74: f023 0370 bic.w r3, r3, #112 @ 0x70
8008e78: 81fb strh r3, [r7, #14]
8008e7a: 687a ldr r2, [r7, #4]
8008e7c: 683b ldr r3, [r7, #0]
8008e7e: 781b ldrb r3, [r3, #0]
8008e80: 009b lsls r3, r3, #2
8008e82: 441a add r2, r3
8008e84: 89fb ldrh r3, [r7, #14]
8008e86: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008e8a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008e8e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008e92: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008e96: b29b uxth r3, r3
8008e98: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8008e9a: 683b ldr r3, [r7, #0]
8008e9c: 78db ldrb r3, [r3, #3]
8008e9e: 2b01 cmp r3, #1
8008ea0: d06c beq.n 8008f7c <USB_EPClearStall+0x14e>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8008ea2: 687a ldr r2, [r7, #4]
8008ea4: 683b ldr r3, [r7, #0]
8008ea6: 781b ldrb r3, [r3, #0]
8008ea8: 009b lsls r3, r3, #2
8008eaa: 4413 add r3, r2
8008eac: 881b ldrh r3, [r3, #0]
8008eae: b29b uxth r3, r3
8008eb0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008eb4: f023 0340 bic.w r3, r3, #64 @ 0x40
8008eb8: 81bb strh r3, [r7, #12]
8008eba: 89bb ldrh r3, [r7, #12]
8008ebc: f083 0320 eor.w r3, r3, #32
8008ec0: 81bb strh r3, [r7, #12]
8008ec2: 687a ldr r2, [r7, #4]
8008ec4: 683b ldr r3, [r7, #0]
8008ec6: 781b ldrb r3, [r3, #0]
8008ec8: 009b lsls r3, r3, #2
8008eca: 441a add r2, r3
8008ecc: 89bb ldrh r3, [r7, #12]
8008ece: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008ed2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008ed6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008eda: f043 0380 orr.w r3, r3, #128 @ 0x80
8008ede: b29b uxth r3, r3
8008ee0: 8013 strh r3, [r2, #0]
8008ee2: e04b b.n 8008f7c <USB_EPClearStall+0x14e>
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8008ee4: 687a ldr r2, [r7, #4]
8008ee6: 683b ldr r3, [r7, #0]
8008ee8: 781b ldrb r3, [r3, #0]
8008eea: 009b lsls r3, r3, #2
8008eec: 4413 add r3, r2
8008eee: 881b ldrh r3, [r3, #0]
8008ef0: 82fb strh r3, [r7, #22]
8008ef2: 8afb ldrh r3, [r7, #22]
8008ef4: f403 4380 and.w r3, r3, #16384 @ 0x4000
8008ef8: 2b00 cmp r3, #0
8008efa: d01b beq.n 8008f34 <USB_EPClearStall+0x106>
8008efc: 687a ldr r2, [r7, #4]
8008efe: 683b ldr r3, [r7, #0]
8008f00: 781b ldrb r3, [r3, #0]
8008f02: 009b lsls r3, r3, #2
8008f04: 4413 add r3, r2
8008f06: 881b ldrh r3, [r3, #0]
8008f08: b29b uxth r3, r3
8008f0a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008f0e: f023 0370 bic.w r3, r3, #112 @ 0x70
8008f12: 82bb strh r3, [r7, #20]
8008f14: 687a ldr r2, [r7, #4]
8008f16: 683b ldr r3, [r7, #0]
8008f18: 781b ldrb r3, [r3, #0]
8008f1a: 009b lsls r3, r3, #2
8008f1c: 441a add r2, r3
8008f1e: 8abb ldrh r3, [r7, #20]
8008f20: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008f24: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008f28: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8008f2c: f043 0380 orr.w r3, r3, #128 @ 0x80
8008f30: b29b uxth r3, r3
8008f32: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8008f34: 687a ldr r2, [r7, #4]
8008f36: 683b ldr r3, [r7, #0]
8008f38: 781b ldrb r3, [r3, #0]
8008f3a: 009b lsls r3, r3, #2
8008f3c: 4413 add r3, r2
8008f3e: 881b ldrh r3, [r3, #0]
8008f40: b29b uxth r3, r3
8008f42: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008f46: f023 0370 bic.w r3, r3, #112 @ 0x70
8008f4a: 827b strh r3, [r7, #18]
8008f4c: 8a7b ldrh r3, [r7, #18]
8008f4e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008f52: 827b strh r3, [r7, #18]
8008f54: 8a7b ldrh r3, [r7, #18]
8008f56: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008f5a: 827b strh r3, [r7, #18]
8008f5c: 687a ldr r2, [r7, #4]
8008f5e: 683b ldr r3, [r7, #0]
8008f60: 781b ldrb r3, [r3, #0]
8008f62: 009b lsls r3, r3, #2
8008f64: 441a add r2, r3
8008f66: 8a7b ldrh r3, [r7, #18]
8008f68: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008f6c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008f70: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008f74: f043 0380 orr.w r3, r3, #128 @ 0x80
8008f78: b29b uxth r3, r3
8008f7a: 8013 strh r3, [r2, #0]
}
}
return HAL_OK;
8008f7c: 2300 movs r3, #0
}
8008f7e: 4618 mov r0, r3
8008f80: 371c adds r7, #28
8008f82: 46bd mov sp, r7
8008f84: bc80 pop {r7}
8008f86: 4770 bx lr
08008f88 <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
8008f88: b480 push {r7}
8008f8a: b083 sub sp, #12
8008f8c: af00 add r7, sp, #0
8008f8e: 6078 str r0, [r7, #4]
8008f90: 460b mov r3, r1
8008f92: 70fb strb r3, [r7, #3]
if (address == 0U)
8008f94: 78fb ldrb r3, [r7, #3]
8008f96: 2b00 cmp r3, #0
8008f98: d103 bne.n 8008fa2 <USB_SetDevAddress+0x1a>
{
/* set device address and enable function */
USBx->DADDR = (uint16_t)USB_DADDR_EF;
8008f9a: 687b ldr r3, [r7, #4]
8008f9c: 2280 movs r2, #128 @ 0x80
8008f9e: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
}
return HAL_OK;
8008fa2: 2300 movs r3, #0
}
8008fa4: 4618 mov r0, r3
8008fa6: 370c adds r7, #12
8008fa8: 46bd mov sp, r7
8008faa: bc80 pop {r7}
8008fac: 4770 bx lr
08008fae <USB_DevConnect>:
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
8008fae: b480 push {r7}
8008fb0: b083 sub sp, #12
8008fb2: af00 add r7, sp, #0
8008fb4: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8008fb6: 2300 movs r3, #0
}
8008fb8: 4618 mov r0, r3
8008fba: 370c adds r7, #12
8008fbc: 46bd mov sp, r7
8008fbe: bc80 pop {r7}
8008fc0: 4770 bx lr
08008fc2 <USB_DevDisconnect>:
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
8008fc2: b480 push {r7}
8008fc4: b083 sub sp, #12
8008fc6: af00 add r7, sp, #0
8008fc8: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8008fca: 2300 movs r3, #0
}
8008fcc: 4618 mov r0, r3
8008fce: 370c adds r7, #12
8008fd0: 46bd mov sp, r7
8008fd2: bc80 pop {r7}
8008fd4: 4770 bx lr
08008fd6 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
8008fd6: b480 push {r7}
8008fd8: b085 sub sp, #20
8008fda: af00 add r7, sp, #0
8008fdc: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->ISTR;
8008fde: 687b ldr r3, [r7, #4]
8008fe0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8008fe4: b29b uxth r3, r3
8008fe6: 60fb str r3, [r7, #12]
return tmpreg;
8008fe8: 68fb ldr r3, [r7, #12]
}
8008fea: 4618 mov r0, r3
8008fec: 3714 adds r7, #20
8008fee: 46bd mov sp, r7
8008ff0: bc80 pop {r7}
8008ff2: 4770 bx lr
08008ff4 <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
8008ff4: b480 push {r7}
8008ff6: b083 sub sp, #12
8008ff8: af00 add r7, sp, #0
8008ffa: 6078 str r0, [r7, #4]
8008ffc: 6039 str r1, [r7, #0]
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8008ffe: 2300 movs r3, #0
}
8009000: 4618 mov r0, r3
8009002: 370c adds r7, #12
8009004: 46bd mov sp, r7
8009006: bc80 pop {r7}
8009008: 4770 bx lr
0800900a <USB_WritePMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
800900a: b480 push {r7}
800900c: b08b sub sp, #44 @ 0x2c
800900e: af00 add r7, sp, #0
8009010: 60f8 str r0, [r7, #12]
8009012: 60b9 str r1, [r7, #8]
8009014: 4611 mov r1, r2
8009016: 461a mov r2, r3
8009018: 460b mov r3, r1
800901a: 80fb strh r3, [r7, #6]
800901c: 4613 mov r3, r2
800901e: 80bb strh r3, [r7, #4]
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
8009020: 88bb ldrh r3, [r7, #4]
8009022: 3301 adds r3, #1
8009024: 085b lsrs r3, r3, #1
8009026: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
8009028: 68fb ldr r3, [r7, #12]
800902a: 617b str r3, [r7, #20]
uint32_t count;
uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
800902c: 68bb ldr r3, [r7, #8]
800902e: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
8009030: 88fb ldrh r3, [r7, #6]
8009032: 005a lsls r2, r3, #1
8009034: 697b ldr r3, [r7, #20]
8009036: 4413 add r3, r2
8009038: f503 6380 add.w r3, r3, #1024 @ 0x400
800903c: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800903e: 69bb ldr r3, [r7, #24]
8009040: 627b str r3, [r7, #36] @ 0x24
8009042: e01f b.n 8009084 <USB_WritePMA+0x7a>
{
WrVal = pBuf[0];
8009044: 69fb ldr r3, [r7, #28]
8009046: 781b ldrb r3, [r3, #0]
8009048: 827b strh r3, [r7, #18]
WrVal |= (uint16_t)pBuf[1] << 8;
800904a: 69fb ldr r3, [r7, #28]
800904c: 3301 adds r3, #1
800904e: 781b ldrb r3, [r3, #0]
8009050: b21b sxth r3, r3
8009052: 021b lsls r3, r3, #8
8009054: b21a sxth r2, r3
8009056: f9b7 3012 ldrsh.w r3, [r7, #18]
800905a: 4313 orrs r3, r2
800905c: b21b sxth r3, r3
800905e: 827b strh r3, [r7, #18]
*pdwVal = (WrVal & 0xFFFFU);
8009060: 6a3b ldr r3, [r7, #32]
8009062: 8a7a ldrh r2, [r7, #18]
8009064: 801a strh r2, [r3, #0]
pdwVal++;
8009066: 6a3b ldr r3, [r7, #32]
8009068: 3302 adds r3, #2
800906a: 623b str r3, [r7, #32]
#if PMA_ACCESS > 1U
pdwVal++;
800906c: 6a3b ldr r3, [r7, #32]
800906e: 3302 adds r3, #2
8009070: 623b str r3, [r7, #32]
#endif /* PMA_ACCESS */
pBuf++;
8009072: 69fb ldr r3, [r7, #28]
8009074: 3301 adds r3, #1
8009076: 61fb str r3, [r7, #28]
pBuf++;
8009078: 69fb ldr r3, [r7, #28]
800907a: 3301 adds r3, #1
800907c: 61fb str r3, [r7, #28]
for (count = n; count != 0U; count--)
800907e: 6a7b ldr r3, [r7, #36] @ 0x24
8009080: 3b01 subs r3, #1
8009082: 627b str r3, [r7, #36] @ 0x24
8009084: 6a7b ldr r3, [r7, #36] @ 0x24
8009086: 2b00 cmp r3, #0
8009088: d1dc bne.n 8009044 <USB_WritePMA+0x3a>
}
}
800908a: bf00 nop
800908c: bf00 nop
800908e: 372c adds r7, #44 @ 0x2c
8009090: 46bd mov sp, r7
8009092: bc80 pop {r7}
8009094: 4770 bx lr
08009096 <USB_ReadPMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
8009096: b480 push {r7}
8009098: b08b sub sp, #44 @ 0x2c
800909a: af00 add r7, sp, #0
800909c: 60f8 str r0, [r7, #12]
800909e: 60b9 str r1, [r7, #8]
80090a0: 4611 mov r1, r2
80090a2: 461a mov r2, r3
80090a4: 460b mov r3, r1
80090a6: 80fb strh r3, [r7, #6]
80090a8: 4613 mov r3, r2
80090aa: 80bb strh r3, [r7, #4]
uint32_t n = (uint32_t)wNBytes >> 1;
80090ac: 88bb ldrh r3, [r7, #4]
80090ae: 085b lsrs r3, r3, #1
80090b0: b29b uxth r3, r3
80090b2: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
80090b4: 68fb ldr r3, [r7, #12]
80090b6: 617b str r3, [r7, #20]
uint32_t count;
uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
80090b8: 68bb ldr r3, [r7, #8]
80090ba: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
80090bc: 88fb ldrh r3, [r7, #6]
80090be: 005a lsls r2, r3, #1
80090c0: 697b ldr r3, [r7, #20]
80090c2: 4413 add r3, r2
80090c4: f503 6380 add.w r3, r3, #1024 @ 0x400
80090c8: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
80090ca: 69bb ldr r3, [r7, #24]
80090cc: 627b str r3, [r7, #36] @ 0x24
80090ce: e01b b.n 8009108 <USB_ReadPMA+0x72>
{
RdVal = *(__IO uint16_t *)pdwVal;
80090d0: 6a3b ldr r3, [r7, #32]
80090d2: 881b ldrh r3, [r3, #0]
80090d4: b29b uxth r3, r3
80090d6: 613b str r3, [r7, #16]
pdwVal++;
80090d8: 6a3b ldr r3, [r7, #32]
80090da: 3302 adds r3, #2
80090dc: 623b str r3, [r7, #32]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
80090de: 693b ldr r3, [r7, #16]
80090e0: b2da uxtb r2, r3
80090e2: 69fb ldr r3, [r7, #28]
80090e4: 701a strb r2, [r3, #0]
pBuf++;
80090e6: 69fb ldr r3, [r7, #28]
80090e8: 3301 adds r3, #1
80090ea: 61fb str r3, [r7, #28]
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
80090ec: 693b ldr r3, [r7, #16]
80090ee: 0a1b lsrs r3, r3, #8
80090f0: b2da uxtb r2, r3
80090f2: 69fb ldr r3, [r7, #28]
80090f4: 701a strb r2, [r3, #0]
pBuf++;
80090f6: 69fb ldr r3, [r7, #28]
80090f8: 3301 adds r3, #1
80090fa: 61fb str r3, [r7, #28]
#if PMA_ACCESS > 1U
pdwVal++;
80090fc: 6a3b ldr r3, [r7, #32]
80090fe: 3302 adds r3, #2
8009100: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
8009102: 6a7b ldr r3, [r7, #36] @ 0x24
8009104: 3b01 subs r3, #1
8009106: 627b str r3, [r7, #36] @ 0x24
8009108: 6a7b ldr r3, [r7, #36] @ 0x24
800910a: 2b00 cmp r3, #0
800910c: d1e0 bne.n 80090d0 <USB_ReadPMA+0x3a>
#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
800910e: 88bb ldrh r3, [r7, #4]
8009110: f003 0301 and.w r3, r3, #1
8009114: b29b uxth r3, r3
8009116: 2b00 cmp r3, #0
8009118: d007 beq.n 800912a <USB_ReadPMA+0x94>
{
RdVal = *pdwVal;
800911a: 6a3b ldr r3, [r7, #32]
800911c: 881b ldrh r3, [r3, #0]
800911e: b29b uxth r3, r3
8009120: 613b str r3, [r7, #16]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
8009122: 693b ldr r3, [r7, #16]
8009124: b2da uxtb r2, r3
8009126: 69fb ldr r3, [r7, #28]
8009128: 701a strb r2, [r3, #0]
}
}
800912a: bf00 nop
800912c: 372c adds r7, #44 @ 0x2c
800912e: 46bd mov sp, r7
8009130: bc80 pop {r7}
8009132: 4770 bx lr
08009134 <USBD_CDC_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8009134: b580 push {r7, lr}
8009136: b084 sub sp, #16
8009138: af00 add r7, sp, #0
800913a: 6078 str r0, [r7, #4]
800913c: 460b mov r3, r1
800913e: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
8009140: 2300 movs r3, #0
8009142: 73fb strb r3, [r7, #15]
USBD_CDC_HandleTypeDef *hcdc;
if (pdev->dev_speed == USBD_SPEED_HIGH)
8009144: 687b ldr r3, [r7, #4]
8009146: 7c1b ldrb r3, [r3, #16]
8009148: 2b00 cmp r3, #0
800914a: d115 bne.n 8009178 <USBD_CDC_Init+0x44>
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
800914c: f44f 7300 mov.w r3, #512 @ 0x200
8009150: 2202 movs r2, #2
8009152: 2181 movs r1, #129 @ 0x81
8009154: 6878 ldr r0, [r7, #4]
8009156: f001 ff00 bl 800af5a <USBD_LL_OpenEP>
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
800915a: 687b ldr r3, [r7, #4]
800915c: 2201 movs r2, #1
800915e: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
8009160: f44f 7300 mov.w r3, #512 @ 0x200
8009164: 2202 movs r2, #2
8009166: 2101 movs r1, #1
8009168: 6878 ldr r0, [r7, #4]
800916a: f001 fef6 bl 800af5a <USBD_LL_OpenEP>
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
800916e: 687b ldr r3, [r7, #4]
8009170: 2201 movs r2, #1
8009172: f8c3 216c str.w r2, [r3, #364] @ 0x16c
8009176: e012 b.n 800919e <USBD_CDC_Init+0x6a>
}
else
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
8009178: 2340 movs r3, #64 @ 0x40
800917a: 2202 movs r2, #2
800917c: 2181 movs r1, #129 @ 0x81
800917e: 6878 ldr r0, [r7, #4]
8009180: f001 feeb bl 800af5a <USBD_LL_OpenEP>
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
8009184: 687b ldr r3, [r7, #4]
8009186: 2201 movs r2, #1
8009188: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
800918a: 2340 movs r3, #64 @ 0x40
800918c: 2202 movs r2, #2
800918e: 2101 movs r1, #1
8009190: 6878 ldr r0, [r7, #4]
8009192: f001 fee2 bl 800af5a <USBD_LL_OpenEP>
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
8009196: 687b ldr r3, [r7, #4]
8009198: 2201 movs r2, #1
800919a: f8c3 216c str.w r2, [r3, #364] @ 0x16c
}
/* Open Command IN EP */
USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
800919e: 2308 movs r3, #8
80091a0: 2203 movs r2, #3
80091a2: 2182 movs r1, #130 @ 0x82
80091a4: 6878 ldr r0, [r7, #4]
80091a6: f001 fed8 bl 800af5a <USBD_LL_OpenEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
80091aa: 687b ldr r3, [r7, #4]
80091ac: 2201 movs r2, #1
80091ae: 641a str r2, [r3, #64] @ 0x40
pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
80091b0: f44f 7007 mov.w r0, #540 @ 0x21c
80091b4: f001 fff8 bl 800b1a8 <USBD_static_malloc>
80091b8: 4602 mov r2, r0
80091ba: 687b ldr r3, [r7, #4]
80091bc: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClassData == NULL)
80091c0: 687b ldr r3, [r7, #4]
80091c2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80091c6: 2b00 cmp r3, #0
80091c8: d102 bne.n 80091d0 <USBD_CDC_Init+0x9c>
{
ret = 1U;
80091ca: 2301 movs r3, #1
80091cc: 73fb strb r3, [r7, #15]
80091ce: e026 b.n 800921e <USBD_CDC_Init+0xea>
}
else
{
hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80091d0: 687b ldr r3, [r7, #4]
80091d2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80091d6: 60bb str r3, [r7, #8]
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
80091d8: 687b ldr r3, [r7, #4]
80091da: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80091de: 681b ldr r3, [r3, #0]
80091e0: 4798 blx r3
/* Init Xfer states */
hcdc->TxState = 0U;
80091e2: 68bb ldr r3, [r7, #8]
80091e4: 2200 movs r2, #0
80091e6: f8c3 2214 str.w r2, [r3, #532] @ 0x214
hcdc->RxState = 0U;
80091ea: 68bb ldr r3, [r7, #8]
80091ec: 2200 movs r2, #0
80091ee: f8c3 2218 str.w r2, [r3, #536] @ 0x218
if (pdev->dev_speed == USBD_SPEED_HIGH)
80091f2: 687b ldr r3, [r7, #4]
80091f4: 7c1b ldrb r3, [r3, #16]
80091f6: 2b00 cmp r3, #0
80091f8: d109 bne.n 800920e <USBD_CDC_Init+0xda>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
80091fa: 68bb ldr r3, [r7, #8]
80091fc: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8009200: f44f 7300 mov.w r3, #512 @ 0x200
8009204: 2101 movs r1, #1
8009206: 6878 ldr r0, [r7, #4]
8009208: f001 ff97 bl 800b13a <USBD_LL_PrepareReceive>
800920c: e007 b.n 800921e <USBD_CDC_Init+0xea>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
800920e: 68bb ldr r3, [r7, #8]
8009210: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8009214: 2340 movs r3, #64 @ 0x40
8009216: 2101 movs r1, #1
8009218: 6878 ldr r0, [r7, #4]
800921a: f001 ff8e bl 800b13a <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
}
return ret;
800921e: 7bfb ldrb r3, [r7, #15]
}
8009220: 4618 mov r0, r3
8009222: 3710 adds r7, #16
8009224: 46bd mov sp, r7
8009226: bd80 pop {r7, pc}
08009228 <USBD_CDC_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8009228: b580 push {r7, lr}
800922a: b084 sub sp, #16
800922c: af00 add r7, sp, #0
800922e: 6078 str r0, [r7, #4]
8009230: 460b mov r3, r1
8009232: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
8009234: 2300 movs r3, #0
8009236: 73fb strb r3, [r7, #15]
/* Close EP IN */
USBD_LL_CloseEP(pdev, CDC_IN_EP);
8009238: 2181 movs r1, #129 @ 0x81
800923a: 6878 ldr r0, [r7, #4]
800923c: f001 feb3 bl 800afa6 <USBD_LL_CloseEP>
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
8009240: 687b ldr r3, [r7, #4]
8009242: 2200 movs r2, #0
8009244: 62da str r2, [r3, #44] @ 0x2c
/* Close EP OUT */
USBD_LL_CloseEP(pdev, CDC_OUT_EP);
8009246: 2101 movs r1, #1
8009248: 6878 ldr r0, [r7, #4]
800924a: f001 feac bl 800afa6 <USBD_LL_CloseEP>
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
800924e: 687b ldr r3, [r7, #4]
8009250: 2200 movs r2, #0
8009252: f8c3 216c str.w r2, [r3, #364] @ 0x16c
/* Close Command IN EP */
USBD_LL_CloseEP(pdev, CDC_CMD_EP);
8009256: 2182 movs r1, #130 @ 0x82
8009258: 6878 ldr r0, [r7, #4]
800925a: f001 fea4 bl 800afa6 <USBD_LL_CloseEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
800925e: 687b ldr r3, [r7, #4]
8009260: 2200 movs r2, #0
8009262: 641a str r2, [r3, #64] @ 0x40
/* DeInit physical Interface components */
if (pdev->pClassData != NULL)
8009264: 687b ldr r3, [r7, #4]
8009266: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800926a: 2b00 cmp r3, #0
800926c: d00e beq.n 800928c <USBD_CDC_DeInit+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
800926e: 687b ldr r3, [r7, #4]
8009270: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009274: 685b ldr r3, [r3, #4]
8009276: 4798 blx r3
USBD_free(pdev->pClassData);
8009278: 687b ldr r3, [r7, #4]
800927a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800927e: 4618 mov r0, r3
8009280: f001 ff9e bl 800b1c0 <USBD_static_free>
pdev->pClassData = NULL;
8009284: 687b ldr r3, [r7, #4]
8009286: 2200 movs r2, #0
8009288: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
}
return ret;
800928c: 7bfb ldrb r3, [r7, #15]
}
800928e: 4618 mov r0, r3
8009290: 3710 adds r7, #16
8009292: 46bd mov sp, r7
8009294: bd80 pop {r7, pc}
08009296 <USBD_CDC_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009296: b580 push {r7, lr}
8009298: b086 sub sp, #24
800929a: af00 add r7, sp, #0
800929c: 6078 str r0, [r7, #4]
800929e: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80092a0: 687b ldr r3, [r7, #4]
80092a2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80092a6: 613b str r3, [r7, #16]
uint8_t ifalt = 0U;
80092a8: 2300 movs r3, #0
80092aa: 73fb strb r3, [r7, #15]
uint16_t status_info = 0U;
80092ac: 2300 movs r3, #0
80092ae: 81bb strh r3, [r7, #12]
uint8_t ret = USBD_OK;
80092b0: 2300 movs r3, #0
80092b2: 75fb strb r3, [r7, #23]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
80092b4: 683b ldr r3, [r7, #0]
80092b6: 781b ldrb r3, [r3, #0]
80092b8: f003 0360 and.w r3, r3, #96 @ 0x60
80092bc: 2b00 cmp r3, #0
80092be: d039 beq.n 8009334 <USBD_CDC_Setup+0x9e>
80092c0: 2b20 cmp r3, #32
80092c2: d17f bne.n 80093c4 <USBD_CDC_Setup+0x12e>
{
case USB_REQ_TYPE_CLASS :
if (req->wLength)
80092c4: 683b ldr r3, [r7, #0]
80092c6: 88db ldrh r3, [r3, #6]
80092c8: 2b00 cmp r3, #0
80092ca: d029 beq.n 8009320 <USBD_CDC_Setup+0x8a>
{
if (req->bmRequest & 0x80U)
80092cc: 683b ldr r3, [r7, #0]
80092ce: 781b ldrb r3, [r3, #0]
80092d0: b25b sxtb r3, r3
80092d2: 2b00 cmp r3, #0
80092d4: da11 bge.n 80092fa <USBD_CDC_Setup+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80092d6: 687b ldr r3, [r7, #4]
80092d8: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80092dc: 689b ldr r3, [r3, #8]
80092de: 683a ldr r2, [r7, #0]
80092e0: 7850 ldrb r0, [r2, #1]
(uint8_t *)(void *)hcdc->data,
80092e2: 6939 ldr r1, [r7, #16]
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80092e4: 683a ldr r2, [r7, #0]
80092e6: 88d2 ldrh r2, [r2, #6]
80092e8: 4798 blx r3
req->wLength);
USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
80092ea: 6939 ldr r1, [r7, #16]
80092ec: 683b ldr r3, [r7, #0]
80092ee: 88db ldrh r3, [r3, #6]
80092f0: 461a mov r2, r3
80092f2: 6878 ldr r0, [r7, #4]
80092f4: f001 fa06 bl 800a704 <USBD_CtlSendData>
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
(uint8_t *)(void *)req, 0U);
}
break;
80092f8: e06b b.n 80093d2 <USBD_CDC_Setup+0x13c>
hcdc->CmdOpCode = req->bRequest;
80092fa: 683b ldr r3, [r7, #0]
80092fc: 785a ldrb r2, [r3, #1]
80092fe: 693b ldr r3, [r7, #16]
8009300: f883 2200 strb.w r2, [r3, #512] @ 0x200
hcdc->CmdLength = (uint8_t)req->wLength;
8009304: 683b ldr r3, [r7, #0]
8009306: 88db ldrh r3, [r3, #6]
8009308: b2da uxtb r2, r3
800930a: 693b ldr r3, [r7, #16]
800930c: f883 2201 strb.w r2, [r3, #513] @ 0x201
USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
8009310: 6939 ldr r1, [r7, #16]
8009312: 683b ldr r3, [r7, #0]
8009314: 88db ldrh r3, [r3, #6]
8009316: 461a mov r2, r3
8009318: 6878 ldr r0, [r7, #4]
800931a: f001 fa21 bl 800a760 <USBD_CtlPrepareRx>
break;
800931e: e058 b.n 80093d2 <USBD_CDC_Setup+0x13c>
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
8009320: 687b ldr r3, [r7, #4]
8009322: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009326: 689b ldr r3, [r3, #8]
8009328: 683a ldr r2, [r7, #0]
800932a: 7850 ldrb r0, [r2, #1]
800932c: 2200 movs r2, #0
800932e: 6839 ldr r1, [r7, #0]
8009330: 4798 blx r3
break;
8009332: e04e b.n 80093d2 <USBD_CDC_Setup+0x13c>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8009334: 683b ldr r3, [r7, #0]
8009336: 785b ldrb r3, [r3, #1]
8009338: 2b0b cmp r3, #11
800933a: d02e beq.n 800939a <USBD_CDC_Setup+0x104>
800933c: 2b0b cmp r3, #11
800933e: dc38 bgt.n 80093b2 <USBD_CDC_Setup+0x11c>
8009340: 2b00 cmp r3, #0
8009342: d002 beq.n 800934a <USBD_CDC_Setup+0xb4>
8009344: 2b0a cmp r3, #10
8009346: d014 beq.n 8009372 <USBD_CDC_Setup+0xdc>
8009348: e033 b.n 80093b2 <USBD_CDC_Setup+0x11c>
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800934a: 687b ldr r3, [r7, #4]
800934c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009350: 2b03 cmp r3, #3
8009352: d107 bne.n 8009364 <USBD_CDC_Setup+0xce>
{
USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
8009354: f107 030c add.w r3, r7, #12
8009358: 2202 movs r2, #2
800935a: 4619 mov r1, r3
800935c: 6878 ldr r0, [r7, #4]
800935e: f001 f9d1 bl 800a704 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8009362: e02e b.n 80093c2 <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
8009364: 6839 ldr r1, [r7, #0]
8009366: 6878 ldr r0, [r7, #4]
8009368: f001 f962 bl 800a630 <USBD_CtlError>
ret = USBD_FAIL;
800936c: 2302 movs r3, #2
800936e: 75fb strb r3, [r7, #23]
break;
8009370: e027 b.n 80093c2 <USBD_CDC_Setup+0x12c>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009372: 687b ldr r3, [r7, #4]
8009374: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009378: 2b03 cmp r3, #3
800937a: d107 bne.n 800938c <USBD_CDC_Setup+0xf6>
{
USBD_CtlSendData(pdev, &ifalt, 1U);
800937c: f107 030f add.w r3, r7, #15
8009380: 2201 movs r2, #1
8009382: 4619 mov r1, r3
8009384: 6878 ldr r0, [r7, #4]
8009386: f001 f9bd bl 800a704 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800938a: e01a b.n 80093c2 <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
800938c: 6839 ldr r1, [r7, #0]
800938e: 6878 ldr r0, [r7, #4]
8009390: f001 f94e bl 800a630 <USBD_CtlError>
ret = USBD_FAIL;
8009394: 2302 movs r3, #2
8009396: 75fb strb r3, [r7, #23]
break;
8009398: e013 b.n 80093c2 <USBD_CDC_Setup+0x12c>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
800939a: 687b ldr r3, [r7, #4]
800939c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80093a0: 2b03 cmp r3, #3
80093a2: d00d beq.n 80093c0 <USBD_CDC_Setup+0x12a>
{
USBD_CtlError(pdev, req);
80093a4: 6839 ldr r1, [r7, #0]
80093a6: 6878 ldr r0, [r7, #4]
80093a8: f001 f942 bl 800a630 <USBD_CtlError>
ret = USBD_FAIL;
80093ac: 2302 movs r3, #2
80093ae: 75fb strb r3, [r7, #23]
}
break;
80093b0: e006 b.n 80093c0 <USBD_CDC_Setup+0x12a>
default:
USBD_CtlError(pdev, req);
80093b2: 6839 ldr r1, [r7, #0]
80093b4: 6878 ldr r0, [r7, #4]
80093b6: f001 f93b bl 800a630 <USBD_CtlError>
ret = USBD_FAIL;
80093ba: 2302 movs r3, #2
80093bc: 75fb strb r3, [r7, #23]
break;
80093be: e000 b.n 80093c2 <USBD_CDC_Setup+0x12c>
break;
80093c0: bf00 nop
}
break;
80093c2: e006 b.n 80093d2 <USBD_CDC_Setup+0x13c>
default:
USBD_CtlError(pdev, req);
80093c4: 6839 ldr r1, [r7, #0]
80093c6: 6878 ldr r0, [r7, #4]
80093c8: f001 f932 bl 800a630 <USBD_CtlError>
ret = USBD_FAIL;
80093cc: 2302 movs r3, #2
80093ce: 75fb strb r3, [r7, #23]
break;
80093d0: bf00 nop
}
return ret;
80093d2: 7dfb ldrb r3, [r7, #23]
}
80093d4: 4618 mov r0, r3
80093d6: 3718 adds r7, #24
80093d8: 46bd mov sp, r7
80093da: bd80 pop {r7, pc}
080093dc <USBD_CDC_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
80093dc: b580 push {r7, lr}
80093de: b084 sub sp, #16
80093e0: af00 add r7, sp, #0
80093e2: 6078 str r0, [r7, #4]
80093e4: 460b mov r3, r1
80093e6: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
80093e8: 687b ldr r3, [r7, #4]
80093ea: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80093ee: 60fb str r3, [r7, #12]
PCD_HandleTypeDef *hpcd = pdev->pData;
80093f0: 687b ldr r3, [r7, #4]
80093f2: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
80093f6: 60bb str r3, [r7, #8]
if (pdev->pClassData != NULL)
80093f8: 687b ldr r3, [r7, #4]
80093fa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80093fe: 2b00 cmp r3, #0
8009400: d03a beq.n 8009478 <USBD_CDC_DataIn+0x9c>
{
if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
8009402: 78fa ldrb r2, [r7, #3]
8009404: 6879 ldr r1, [r7, #4]
8009406: 4613 mov r3, r2
8009408: 009b lsls r3, r3, #2
800940a: 4413 add r3, r2
800940c: 009b lsls r3, r3, #2
800940e: 440b add r3, r1
8009410: 331c adds r3, #28
8009412: 681b ldr r3, [r3, #0]
8009414: 2b00 cmp r3, #0
8009416: d029 beq.n 800946c <USBD_CDC_DataIn+0x90>
8009418: 78fa ldrb r2, [r7, #3]
800941a: 6879 ldr r1, [r7, #4]
800941c: 4613 mov r3, r2
800941e: 009b lsls r3, r3, #2
8009420: 4413 add r3, r2
8009422: 009b lsls r3, r3, #2
8009424: 440b add r3, r1
8009426: 331c adds r3, #28
8009428: 681a ldr r2, [r3, #0]
800942a: 78f9 ldrb r1, [r7, #3]
800942c: 68b8 ldr r0, [r7, #8]
800942e: 460b mov r3, r1
8009430: 009b lsls r3, r3, #2
8009432: 440b add r3, r1
8009434: 00db lsls r3, r3, #3
8009436: 4403 add r3, r0
8009438: 3320 adds r3, #32
800943a: 681b ldr r3, [r3, #0]
800943c: fbb2 f1f3 udiv r1, r2, r3
8009440: fb01 f303 mul.w r3, r1, r3
8009444: 1ad3 subs r3, r2, r3
8009446: 2b00 cmp r3, #0
8009448: d110 bne.n 800946c <USBD_CDC_DataIn+0x90>
{
/* Update the packet total length */
pdev->ep_in[epnum].total_length = 0U;
800944a: 78fa ldrb r2, [r7, #3]
800944c: 6879 ldr r1, [r7, #4]
800944e: 4613 mov r3, r2
8009450: 009b lsls r3, r3, #2
8009452: 4413 add r3, r2
8009454: 009b lsls r3, r3, #2
8009456: 440b add r3, r1
8009458: 331c adds r3, #28
800945a: 2200 movs r2, #0
800945c: 601a str r2, [r3, #0]
/* Send ZLP */
USBD_LL_Transmit(pdev, epnum, NULL, 0U);
800945e: 78f9 ldrb r1, [r7, #3]
8009460: 2300 movs r3, #0
8009462: 2200 movs r2, #0
8009464: 6878 ldr r0, [r7, #4]
8009466: f001 fe45 bl 800b0f4 <USBD_LL_Transmit>
800946a: e003 b.n 8009474 <USBD_CDC_DataIn+0x98>
}
else
{
hcdc->TxState = 0U;
800946c: 68fb ldr r3, [r7, #12]
800946e: 2200 movs r2, #0
8009470: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
return USBD_OK;
8009474: 2300 movs r3, #0
8009476: e000 b.n 800947a <USBD_CDC_DataIn+0x9e>
}
else
{
return USBD_FAIL;
8009478: 2302 movs r3, #2
}
}
800947a: 4618 mov r0, r3
800947c: 3710 adds r7, #16
800947e: 46bd mov sp, r7
8009480: bd80 pop {r7, pc}
08009482 <USBD_CDC_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
8009482: b580 push {r7, lr}
8009484: b084 sub sp, #16
8009486: af00 add r7, sp, #0
8009488: 6078 str r0, [r7, #4]
800948a: 460b mov r3, r1
800948c: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800948e: 687b ldr r3, [r7, #4]
8009490: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009494: 60fb str r3, [r7, #12]
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
8009496: 78fb ldrb r3, [r7, #3]
8009498: 4619 mov r1, r3
800949a: 6878 ldr r0, [r7, #4]
800949c: f001 fe70 bl 800b180 <USBD_LL_GetRxDataSize>
80094a0: 4602 mov r2, r0
80094a2: 68fb ldr r3, [r7, #12]
80094a4: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
if (pdev->pClassData != NULL)
80094a8: 687b ldr r3, [r7, #4]
80094aa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80094ae: 2b00 cmp r3, #0
80094b0: d00d beq.n 80094ce <USBD_CDC_DataOut+0x4c>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
80094b2: 687b ldr r3, [r7, #4]
80094b4: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80094b8: 68db ldr r3, [r3, #12]
80094ba: 68fa ldr r2, [r7, #12]
80094bc: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
80094c0: 68fa ldr r2, [r7, #12]
80094c2: f502 7203 add.w r2, r2, #524 @ 0x20c
80094c6: 4611 mov r1, r2
80094c8: 4798 blx r3
return USBD_OK;
80094ca: 2300 movs r3, #0
80094cc: e000 b.n 80094d0 <USBD_CDC_DataOut+0x4e>
}
else
{
return USBD_FAIL;
80094ce: 2302 movs r3, #2
}
}
80094d0: 4618 mov r0, r3
80094d2: 3710 adds r7, #16
80094d4: 46bd mov sp, r7
80094d6: bd80 pop {r7, pc}
080094d8 <USBD_CDC_EP0_RxReady>:
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
80094d8: b580 push {r7, lr}
80094da: b084 sub sp, #16
80094dc: af00 add r7, sp, #0
80094de: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80094e0: 687b ldr r3, [r7, #4]
80094e2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80094e6: 60fb str r3, [r7, #12]
if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
80094e8: 687b ldr r3, [r7, #4]
80094ea: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80094ee: 2b00 cmp r3, #0
80094f0: d014 beq.n 800951c <USBD_CDC_EP0_RxReady+0x44>
80094f2: 68fb ldr r3, [r7, #12]
80094f4: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
80094f8: 2bff cmp r3, #255 @ 0xff
80094fa: d00f beq.n 800951c <USBD_CDC_EP0_RxReady+0x44>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
80094fc: 687b ldr r3, [r7, #4]
80094fe: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009502: 689b ldr r3, [r3, #8]
8009504: 68fa ldr r2, [r7, #12]
8009506: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
(uint8_t *)(void *)hcdc->data,
800950a: 68f9 ldr r1, [r7, #12]
(uint16_t)hcdc->CmdLength);
800950c: 68fa ldr r2, [r7, #12]
800950e: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
8009512: 4798 blx r3
hcdc->CmdOpCode = 0xFFU;
8009514: 68fb ldr r3, [r7, #12]
8009516: 22ff movs r2, #255 @ 0xff
8009518: f883 2200 strb.w r2, [r3, #512] @ 0x200
}
return USBD_OK;
800951c: 2300 movs r3, #0
}
800951e: 4618 mov r0, r3
8009520: 3710 adds r7, #16
8009522: 46bd mov sp, r7
8009524: bd80 pop {r7, pc}
...
08009528 <USBD_CDC_GetFSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
8009528: b480 push {r7}
800952a: b083 sub sp, #12
800952c: af00 add r7, sp, #0
800952e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgFSDesc);
8009530: 687b ldr r3, [r7, #4]
8009532: 2243 movs r2, #67 @ 0x43
8009534: 801a strh r2, [r3, #0]
return USBD_CDC_CfgFSDesc;
8009536: 4b03 ldr r3, [pc, #12] @ (8009544 <USBD_CDC_GetFSCfgDesc+0x1c>)
}
8009538: 4618 mov r0, r3
800953a: 370c adds r7, #12
800953c: 46bd mov sp, r7
800953e: bc80 pop {r7}
8009540: 4770 bx lr
8009542: bf00 nop
8009544: 20000098 .word 0x20000098
08009548 <USBD_CDC_GetHSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
8009548: b480 push {r7}
800954a: b083 sub sp, #12
800954c: af00 add r7, sp, #0
800954e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgHSDesc);
8009550: 687b ldr r3, [r7, #4]
8009552: 2243 movs r2, #67 @ 0x43
8009554: 801a strh r2, [r3, #0]
return USBD_CDC_CfgHSDesc;
8009556: 4b03 ldr r3, [pc, #12] @ (8009564 <USBD_CDC_GetHSCfgDesc+0x1c>)
}
8009558: 4618 mov r0, r3
800955a: 370c adds r7, #12
800955c: 46bd mov sp, r7
800955e: bc80 pop {r7}
8009560: 4770 bx lr
8009562: bf00 nop
8009564: 20000054 .word 0x20000054
08009568 <USBD_CDC_GetOtherSpeedCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
8009568: b480 push {r7}
800956a: b083 sub sp, #12
800956c: af00 add r7, sp, #0
800956e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_OtherSpeedCfgDesc);
8009570: 687b ldr r3, [r7, #4]
8009572: 2243 movs r2, #67 @ 0x43
8009574: 801a strh r2, [r3, #0]
return USBD_CDC_OtherSpeedCfgDesc;
8009576: 4b03 ldr r3, [pc, #12] @ (8009584 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
}
8009578: 4618 mov r0, r3
800957a: 370c adds r7, #12
800957c: 46bd mov sp, r7
800957e: bc80 pop {r7}
8009580: 4770 bx lr
8009582: bf00 nop
8009584: 200000dc .word 0x200000dc
08009588 <USBD_CDC_GetDeviceQualifierDescriptor>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
8009588: b480 push {r7}
800958a: b083 sub sp, #12
800958c: af00 add r7, sp, #0
800958e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_DeviceQualifierDesc);
8009590: 687b ldr r3, [r7, #4]
8009592: 220a movs r2, #10
8009594: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceQualifierDesc;
8009596: 4b03 ldr r3, [pc, #12] @ (80095a4 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
}
8009598: 4618 mov r0, r3
800959a: 370c adds r7, #12
800959c: 46bd mov sp, r7
800959e: bc80 pop {r7}
80095a0: 4770 bx lr
80095a2: bf00 nop
80095a4: 20000010 .word 0x20000010
080095a8 <USBD_CDC_RegisterInterface>:
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
80095a8: b480 push {r7}
80095aa: b085 sub sp, #20
80095ac: af00 add r7, sp, #0
80095ae: 6078 str r0, [r7, #4]
80095b0: 6039 str r1, [r7, #0]
uint8_t ret = USBD_FAIL;
80095b2: 2302 movs r3, #2
80095b4: 73fb strb r3, [r7, #15]
if (fops != NULL)
80095b6: 683b ldr r3, [r7, #0]
80095b8: 2b00 cmp r3, #0
80095ba: d005 beq.n 80095c8 <USBD_CDC_RegisterInterface+0x20>
{
pdev->pUserData = fops;
80095bc: 687b ldr r3, [r7, #4]
80095be: 683a ldr r2, [r7, #0]
80095c0: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
ret = USBD_OK;
80095c4: 2300 movs r3, #0
80095c6: 73fb strb r3, [r7, #15]
}
return ret;
80095c8: 7bfb ldrb r3, [r7, #15]
}
80095ca: 4618 mov r0, r3
80095cc: 3714 adds r7, #20
80095ce: 46bd mov sp, r7
80095d0: bc80 pop {r7}
80095d2: 4770 bx lr
080095d4 <USBD_CDC_SetTxBuffer>:
* @retval status
*/
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff,
uint16_t length)
{
80095d4: b480 push {r7}
80095d6: b087 sub sp, #28
80095d8: af00 add r7, sp, #0
80095da: 60f8 str r0, [r7, #12]
80095dc: 60b9 str r1, [r7, #8]
80095de: 4613 mov r3, r2
80095e0: 80fb strh r3, [r7, #6]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80095e2: 68fb ldr r3, [r7, #12]
80095e4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80095e8: 617b str r3, [r7, #20]
hcdc->TxBuffer = pbuff;
80095ea: 697b ldr r3, [r7, #20]
80095ec: 68ba ldr r2, [r7, #8]
80095ee: f8c3 2208 str.w r2, [r3, #520] @ 0x208
hcdc->TxLength = length;
80095f2: 88fa ldrh r2, [r7, #6]
80095f4: 697b ldr r3, [r7, #20]
80095f6: f8c3 2210 str.w r2, [r3, #528] @ 0x210
return USBD_OK;
80095fa: 2300 movs r3, #0
}
80095fc: 4618 mov r0, r3
80095fe: 371c adds r7, #28
8009600: 46bd mov sp, r7
8009602: bc80 pop {r7}
8009604: 4770 bx lr
08009606 <USBD_CDC_SetRxBuffer>:
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff)
{
8009606: b480 push {r7}
8009608: b085 sub sp, #20
800960a: af00 add r7, sp, #0
800960c: 6078 str r0, [r7, #4]
800960e: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8009610: 687b ldr r3, [r7, #4]
8009612: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009616: 60fb str r3, [r7, #12]
hcdc->RxBuffer = pbuff;
8009618: 68fb ldr r3, [r7, #12]
800961a: 683a ldr r2, [r7, #0]
800961c: f8c3 2204 str.w r2, [r3, #516] @ 0x204
return USBD_OK;
8009620: 2300 movs r3, #0
}
8009622: 4618 mov r0, r3
8009624: 3714 adds r7, #20
8009626: 46bd mov sp, r7
8009628: bc80 pop {r7}
800962a: 4770 bx lr
0800962c <USBD_CDC_TransmitPacket>:
* Transmit packet on IN endpoint
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
800962c: b580 push {r7, lr}
800962e: b084 sub sp, #16
8009630: af00 add r7, sp, #0
8009632: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8009634: 687b ldr r3, [r7, #4]
8009636: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800963a: 60fb str r3, [r7, #12]
if (pdev->pClassData != NULL)
800963c: 687b ldr r3, [r7, #4]
800963e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009642: 2b00 cmp r3, #0
8009644: d01c beq.n 8009680 <USBD_CDC_TransmitPacket+0x54>
{
if (hcdc->TxState == 0U)
8009646: 68fb ldr r3, [r7, #12]
8009648: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800964c: 2b00 cmp r3, #0
800964e: d115 bne.n 800967c <USBD_CDC_TransmitPacket+0x50>
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
8009650: 68fb ldr r3, [r7, #12]
8009652: 2201 movs r2, #1
8009654: f8c3 2214 str.w r2, [r3, #532] @ 0x214
/* Update the packet total length */
pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
8009658: 68fb ldr r3, [r7, #12]
800965a: f8d3 2210 ldr.w r2, [r3, #528] @ 0x210
800965e: 687b ldr r3, [r7, #4]
8009660: 631a str r2, [r3, #48] @ 0x30
/* Transmit next packet */
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
8009662: 68fb ldr r3, [r7, #12]
8009664: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
(uint16_t)hcdc->TxLength);
8009668: 68fb ldr r3, [r7, #12]
800966a: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
800966e: b29b uxth r3, r3
8009670: 2181 movs r1, #129 @ 0x81
8009672: 6878 ldr r0, [r7, #4]
8009674: f001 fd3e bl 800b0f4 <USBD_LL_Transmit>
return USBD_OK;
8009678: 2300 movs r3, #0
800967a: e002 b.n 8009682 <USBD_CDC_TransmitPacket+0x56>
}
else
{
return USBD_BUSY;
800967c: 2301 movs r3, #1
800967e: e000 b.n 8009682 <USBD_CDC_TransmitPacket+0x56>
}
}
else
{
return USBD_FAIL;
8009680: 2302 movs r3, #2
}
}
8009682: 4618 mov r0, r3
8009684: 3710 adds r7, #16
8009686: 46bd mov sp, r7
8009688: bd80 pop {r7, pc}
0800968a <USBD_CDC_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
800968a: b580 push {r7, lr}
800968c: b084 sub sp, #16
800968e: af00 add r7, sp, #0
8009690: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8009692: 687b ldr r3, [r7, #4]
8009694: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009698: 60fb str r3, [r7, #12]
/* Suspend or Resume USB Out process */
if (pdev->pClassData != NULL)
800969a: 687b ldr r3, [r7, #4]
800969c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80096a0: 2b00 cmp r3, #0
80096a2: d017 beq.n 80096d4 <USBD_CDC_ReceivePacket+0x4a>
{
if (pdev->dev_speed == USBD_SPEED_HIGH)
80096a4: 687b ldr r3, [r7, #4]
80096a6: 7c1b ldrb r3, [r3, #16]
80096a8: 2b00 cmp r3, #0
80096aa: d109 bne.n 80096c0 <USBD_CDC_ReceivePacket+0x36>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
80096ac: 68fb ldr r3, [r7, #12]
80096ae: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80096b2: f44f 7300 mov.w r3, #512 @ 0x200
80096b6: 2101 movs r1, #1
80096b8: 6878 ldr r0, [r7, #4]
80096ba: f001 fd3e bl 800b13a <USBD_LL_PrepareReceive>
80096be: e007 b.n 80096d0 <USBD_CDC_ReceivePacket+0x46>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
80096c0: 68fb ldr r3, [r7, #12]
80096c2: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80096c6: 2340 movs r3, #64 @ 0x40
80096c8: 2101 movs r1, #1
80096ca: 6878 ldr r0, [r7, #4]
80096cc: f001 fd35 bl 800b13a <USBD_LL_PrepareReceive>
CDC_OUT_EP,
hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return USBD_OK;
80096d0: 2300 movs r3, #0
80096d2: e000 b.n 80096d6 <USBD_CDC_ReceivePacket+0x4c>
}
else
{
return USBD_FAIL;
80096d4: 2302 movs r3, #2
}
}
80096d6: 4618 mov r0, r3
80096d8: 3710 adds r7, #16
80096da: 46bd mov sp, r7
80096dc: bd80 pop {r7, pc}
080096de <USBD_Init>:
* @param id: Low level core index
* @retval None
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
80096de: b580 push {r7, lr}
80096e0: b084 sub sp, #16
80096e2: af00 add r7, sp, #0
80096e4: 60f8 str r0, [r7, #12]
80096e6: 60b9 str r1, [r7, #8]
80096e8: 4613 mov r3, r2
80096ea: 71fb strb r3, [r7, #7]
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
80096ec: 68fb ldr r3, [r7, #12]
80096ee: 2b00 cmp r3, #0
80096f0: d101 bne.n 80096f6 <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif
return USBD_FAIL;
80096f2: 2302 movs r3, #2
80096f4: e01a b.n 800972c <USBD_Init+0x4e>
}
/* Unlink previous class*/
if (pdev->pClass != NULL)
80096f6: 68fb ldr r3, [r7, #12]
80096f8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80096fc: 2b00 cmp r3, #0
80096fe: d003 beq.n 8009708 <USBD_Init+0x2a>
{
pdev->pClass = NULL;
8009700: 68fb ldr r3, [r7, #12]
8009702: 2200 movs r2, #0
8009704: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Assign USBD Descriptors */
if (pdesc != NULL)
8009708: 68bb ldr r3, [r7, #8]
800970a: 2b00 cmp r3, #0
800970c: d003 beq.n 8009716 <USBD_Init+0x38>
{
pdev->pDesc = pdesc;
800970e: 68fb ldr r3, [r7, #12]
8009710: 68ba ldr r2, [r7, #8]
8009712: f8c3 22b0 str.w r2, [r3, #688] @ 0x2b0
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
8009716: 68fb ldr r3, [r7, #12]
8009718: 2201 movs r2, #1
800971a: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
800971e: 68fb ldr r3, [r7, #12]
8009720: 79fa ldrb r2, [r7, #7]
8009722: 701a strb r2, [r3, #0]
/* Initialize low level driver */
USBD_LL_Init(pdev);
8009724: 68f8 ldr r0, [r7, #12]
8009726: f001 fba3 bl 800ae70 <USBD_LL_Init>
return USBD_OK;
800972a: 2300 movs r3, #0
}
800972c: 4618 mov r0, r3
800972e: 3710 adds r7, #16
8009730: 46bd mov sp, r7
8009732: bd80 pop {r7, pc}
08009734 <USBD_RegisterClass>:
* @param pDevice : Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
8009734: b480 push {r7}
8009736: b085 sub sp, #20
8009738: af00 add r7, sp, #0
800973a: 6078 str r0, [r7, #4]
800973c: 6039 str r1, [r7, #0]
USBD_StatusTypeDef status = USBD_OK;
800973e: 2300 movs r3, #0
8009740: 73fb strb r3, [r7, #15]
if (pclass != NULL)
8009742: 683b ldr r3, [r7, #0]
8009744: 2b00 cmp r3, #0
8009746: d006 beq.n 8009756 <USBD_RegisterClass+0x22>
{
/* link the class to the USB Device handle */
pdev->pClass = pclass;
8009748: 687b ldr r3, [r7, #4]
800974a: 683a ldr r2, [r7, #0]
800974c: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
status = USBD_OK;
8009750: 2300 movs r3, #0
8009752: 73fb strb r3, [r7, #15]
8009754: e001 b.n 800975a <USBD_RegisterClass+0x26>
else
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif
status = USBD_FAIL;
8009756: 2302 movs r3, #2
8009758: 73fb strb r3, [r7, #15]
}
return status;
800975a: 7bfb ldrb r3, [r7, #15]
}
800975c: 4618 mov r0, r3
800975e: 3714 adds r7, #20
8009760: 46bd mov sp, r7
8009762: bc80 pop {r7}
8009764: 4770 bx lr
08009766 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
8009766: b580 push {r7, lr}
8009768: b082 sub sp, #8
800976a: af00 add r7, sp, #0
800976c: 6078 str r0, [r7, #4]
/* Start the low level driver */
USBD_LL_Start(pdev);
800976e: 6878 ldr r0, [r7, #4]
8009770: f001 fbd8 bl 800af24 <USBD_LL_Start>
return USBD_OK;
8009774: 2300 movs r3, #0
}
8009776: 4618 mov r0, r3
8009778: 3708 adds r7, #8
800977a: 46bd mov sp, r7
800977c: bd80 pop {r7, pc}
0800977e <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
800977e: b480 push {r7}
8009780: b083 sub sp, #12
8009782: af00 add r7, sp, #0
8009784: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
8009786: 2300 movs r3, #0
}
8009788: 4618 mov r0, r3
800978a: 370c adds r7, #12
800978c: 46bd mov sp, r7
800978e: bc80 pop {r7}
8009790: 4770 bx lr
08009792 <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8009792: b580 push {r7, lr}
8009794: b084 sub sp, #16
8009796: af00 add r7, sp, #0
8009798: 6078 str r0, [r7, #4]
800979a: 460b mov r3, r1
800979c: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_FAIL;
800979e: 2302 movs r3, #2
80097a0: 73fb strb r3, [r7, #15]
if (pdev->pClass != NULL)
80097a2: 687b ldr r3, [r7, #4]
80097a4: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80097a8: 2b00 cmp r3, #0
80097aa: d00c beq.n 80097c6 <USBD_SetClassConfig+0x34>
{
/* Set configuration and Start the Class*/
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
80097ac: 687b ldr r3, [r7, #4]
80097ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80097b2: 681b ldr r3, [r3, #0]
80097b4: 78fa ldrb r2, [r7, #3]
80097b6: 4611 mov r1, r2
80097b8: 6878 ldr r0, [r7, #4]
80097ba: 4798 blx r3
80097bc: 4603 mov r3, r0
80097be: 2b00 cmp r3, #0
80097c0: d101 bne.n 80097c6 <USBD_SetClassConfig+0x34>
{
ret = USBD_OK;
80097c2: 2300 movs r3, #0
80097c4: 73fb strb r3, [r7, #15]
}
}
return ret;
80097c6: 7bfb ldrb r3, [r7, #15]
}
80097c8: 4618 mov r0, r3
80097ca: 3710 adds r7, #16
80097cc: 46bd mov sp, r7
80097ce: bd80 pop {r7, pc}
080097d0 <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status: USBD_StatusTypeDef
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80097d0: b580 push {r7, lr}
80097d2: b082 sub sp, #8
80097d4: af00 add r7, sp, #0
80097d6: 6078 str r0, [r7, #4]
80097d8: 460b mov r3, r1
80097da: 70fb strb r3, [r7, #3]
/* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx);
80097dc: 687b ldr r3, [r7, #4]
80097de: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80097e2: 685b ldr r3, [r3, #4]
80097e4: 78fa ldrb r2, [r7, #3]
80097e6: 4611 mov r1, r2
80097e8: 6878 ldr r0, [r7, #4]
80097ea: 4798 blx r3
return USBD_OK;
80097ec: 2300 movs r3, #0
}
80097ee: 4618 mov r0, r3
80097f0: 3708 adds r7, #8
80097f2: 46bd mov sp, r7
80097f4: bd80 pop {r7, pc}
080097f6 <USBD_LL_SetupStage>:
* Handle the setup stage
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
80097f6: b580 push {r7, lr}
80097f8: b082 sub sp, #8
80097fa: af00 add r7, sp, #0
80097fc: 6078 str r0, [r7, #4]
80097fe: 6039 str r1, [r7, #0]
USBD_ParseSetupRequest(&pdev->request, psetup);
8009800: 687b ldr r3, [r7, #4]
8009802: f503 732a add.w r3, r3, #680 @ 0x2a8
8009806: 6839 ldr r1, [r7, #0]
8009808: 4618 mov r0, r3
800980a: f000 fed8 bl 800a5be <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
800980e: 687b ldr r3, [r7, #4]
8009810: 2201 movs r2, #1
8009812: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
8009816: 687b ldr r3, [r7, #4]
8009818: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
800981c: 461a mov r2, r3
800981e: 687b ldr r3, [r7, #4]
8009820: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
8009824: 687b ldr r3, [r7, #4]
8009826: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
800982a: f003 031f and.w r3, r3, #31
800982e: 2b02 cmp r3, #2
8009830: d016 beq.n 8009860 <USBD_LL_SetupStage+0x6a>
8009832: 2b02 cmp r3, #2
8009834: d81c bhi.n 8009870 <USBD_LL_SetupStage+0x7a>
8009836: 2b00 cmp r3, #0
8009838: d002 beq.n 8009840 <USBD_LL_SetupStage+0x4a>
800983a: 2b01 cmp r3, #1
800983c: d008 beq.n 8009850 <USBD_LL_SetupStage+0x5a>
800983e: e017 b.n 8009870 <USBD_LL_SetupStage+0x7a>
{
case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq(pdev, &pdev->request);
8009840: 687b ldr r3, [r7, #4]
8009842: f503 732a add.w r3, r3, #680 @ 0x2a8
8009846: 4619 mov r1, r3
8009848: 6878 ldr r0, [r7, #4]
800984a: f000 f9cb bl 8009be4 <USBD_StdDevReq>
break;
800984e: e01a b.n 8009886 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request);
8009850: 687b ldr r3, [r7, #4]
8009852: f503 732a add.w r3, r3, #680 @ 0x2a8
8009856: 4619 mov r1, r3
8009858: 6878 ldr r0, [r7, #4]
800985a: f000 fa2d bl 8009cb8 <USBD_StdItfReq>
break;
800985e: e012 b.n 8009886 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request);
8009860: 687b ldr r3, [r7, #4]
8009862: f503 732a add.w r3, r3, #680 @ 0x2a8
8009866: 4619 mov r1, r3
8009868: 6878 ldr r0, [r7, #4]
800986a: f000 fa6d bl 8009d48 <USBD_StdEPReq>
break;
800986e: e00a b.n 8009886 <USBD_LL_SetupStage+0x90>
default:
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
8009870: 687b ldr r3, [r7, #4]
8009872: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
8009876: f023 037f bic.w r3, r3, #127 @ 0x7f
800987a: b2db uxtb r3, r3
800987c: 4619 mov r1, r3
800987e: 6878 ldr r0, [r7, #4]
8009880: f001 fbb0 bl 800afe4 <USBD_LL_StallEP>
break;
8009884: bf00 nop
}
return USBD_OK;
8009886: 2300 movs r3, #0
}
8009888: 4618 mov r0, r3
800988a: 3708 adds r7, #8
800988c: 46bd mov sp, r7
800988e: bd80 pop {r7, pc}
08009890 <USBD_LL_DataOutStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8009890: b580 push {r7, lr}
8009892: b086 sub sp, #24
8009894: af00 add r7, sp, #0
8009896: 60f8 str r0, [r7, #12]
8009898: 460b mov r3, r1
800989a: 607a str r2, [r7, #4]
800989c: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
800989e: 7afb ldrb r3, [r7, #11]
80098a0: 2b00 cmp r3, #0
80098a2: d14b bne.n 800993c <USBD_LL_DataOutStage+0xac>
{
pep = &pdev->ep_out[0];
80098a4: 68fb ldr r3, [r7, #12]
80098a6: f503 73aa add.w r3, r3, #340 @ 0x154
80098aa: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
80098ac: 68fb ldr r3, [r7, #12]
80098ae: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
80098b2: 2b03 cmp r3, #3
80098b4: d134 bne.n 8009920 <USBD_LL_DataOutStage+0x90>
{
if (pep->rem_length > pep->maxpacket)
80098b6: 697b ldr r3, [r7, #20]
80098b8: 68da ldr r2, [r3, #12]
80098ba: 697b ldr r3, [r7, #20]
80098bc: 691b ldr r3, [r3, #16]
80098be: 429a cmp r2, r3
80098c0: d919 bls.n 80098f6 <USBD_LL_DataOutStage+0x66>
{
pep->rem_length -= pep->maxpacket;
80098c2: 697b ldr r3, [r7, #20]
80098c4: 68da ldr r2, [r3, #12]
80098c6: 697b ldr r3, [r7, #20]
80098c8: 691b ldr r3, [r3, #16]
80098ca: 1ad2 subs r2, r2, r3
80098cc: 697b ldr r3, [r7, #20]
80098ce: 60da str r2, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80098d0: 697b ldr r3, [r7, #20]
80098d2: 68da ldr r2, [r3, #12]
80098d4: 697b ldr r3, [r7, #20]
80098d6: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
80098d8: 429a cmp r2, r3
80098da: d203 bcs.n 80098e4 <USBD_LL_DataOutStage+0x54>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80098dc: 697b ldr r3, [r7, #20]
80098de: 68db ldr r3, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
80098e0: b29b uxth r3, r3
80098e2: e002 b.n 80098ea <USBD_LL_DataOutStage+0x5a>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80098e4: 697b ldr r3, [r7, #20]
80098e6: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
80098e8: b29b uxth r3, r3
80098ea: 461a mov r2, r3
80098ec: 6879 ldr r1, [r7, #4]
80098ee: 68f8 ldr r0, [r7, #12]
80098f0: f000 ff54 bl 800a79c <USBD_CtlContinueRx>
80098f4: e038 b.n 8009968 <USBD_LL_DataOutStage+0xd8>
}
else
{
if ((pdev->pClass->EP0_RxReady != NULL) &&
80098f6: 68fb ldr r3, [r7, #12]
80098f8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80098fc: 691b ldr r3, [r3, #16]
80098fe: 2b00 cmp r3, #0
8009900: d00a beq.n 8009918 <USBD_LL_DataOutStage+0x88>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8009902: 68fb ldr r3, [r7, #12]
8009904: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_RxReady != NULL) &&
8009908: 2b03 cmp r3, #3
800990a: d105 bne.n 8009918 <USBD_LL_DataOutStage+0x88>
{
pdev->pClass->EP0_RxReady(pdev);
800990c: 68fb ldr r3, [r7, #12]
800990e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009912: 691b ldr r3, [r3, #16]
8009914: 68f8 ldr r0, [r7, #12]
8009916: 4798 blx r3
}
USBD_CtlSendStatus(pdev);
8009918: 68f8 ldr r0, [r7, #12]
800991a: f000 ff51 bl 800a7c0 <USBD_CtlSendStatus>
800991e: e023 b.n 8009968 <USBD_LL_DataOutStage+0xd8>
}
}
else
{
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
8009920: 68fb ldr r3, [r7, #12]
8009922: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009926: 2b05 cmp r3, #5
8009928: d11e bne.n 8009968 <USBD_LL_DataOutStage+0xd8>
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
800992a: 68fb ldr r3, [r7, #12]
800992c: 2200 movs r2, #0
800992e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
USBD_LL_StallEP(pdev, 0U);
8009932: 2100 movs r1, #0
8009934: 68f8 ldr r0, [r7, #12]
8009936: f001 fb55 bl 800afe4 <USBD_LL_StallEP>
800993a: e015 b.n 8009968 <USBD_LL_DataOutStage+0xd8>
}
}
}
else if ((pdev->pClass->DataOut != NULL) &&
800993c: 68fb ldr r3, [r7, #12]
800993e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009942: 699b ldr r3, [r3, #24]
8009944: 2b00 cmp r3, #0
8009946: d00d beq.n 8009964 <USBD_LL_DataOutStage+0xd4>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8009948: 68fb ldr r3, [r7, #12]
800994a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataOut != NULL) &&
800994e: 2b03 cmp r3, #3
8009950: d108 bne.n 8009964 <USBD_LL_DataOutStage+0xd4>
{
pdev->pClass->DataOut(pdev, epnum);
8009952: 68fb ldr r3, [r7, #12]
8009954: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009958: 699b ldr r3, [r3, #24]
800995a: 7afa ldrb r2, [r7, #11]
800995c: 4611 mov r1, r2
800995e: 68f8 ldr r0, [r7, #12]
8009960: 4798 blx r3
8009962: e001 b.n 8009968 <USBD_LL_DataOutStage+0xd8>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
8009964: 2302 movs r3, #2
8009966: e000 b.n 800996a <USBD_LL_DataOutStage+0xda>
}
return USBD_OK;
8009968: 2300 movs r3, #0
}
800996a: 4618 mov r0, r3
800996c: 3718 adds r7, #24
800996e: 46bd mov sp, r7
8009970: bd80 pop {r7, pc}
08009972 <USBD_LL_DataInStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8009972: b580 push {r7, lr}
8009974: b086 sub sp, #24
8009976: af00 add r7, sp, #0
8009978: 60f8 str r0, [r7, #12]
800997a: 460b mov r3, r1
800997c: 607a str r2, [r7, #4]
800997e: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
8009980: 7afb ldrb r3, [r7, #11]
8009982: 2b00 cmp r3, #0
8009984: d17f bne.n 8009a86 <USBD_LL_DataInStage+0x114>
{
pep = &pdev->ep_in[0];
8009986: 68fb ldr r3, [r7, #12]
8009988: 3314 adds r3, #20
800998a: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
800998c: 68fb ldr r3, [r7, #12]
800998e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009992: 2b02 cmp r3, #2
8009994: d15c bne.n 8009a50 <USBD_LL_DataInStage+0xde>
{
if (pep->rem_length > pep->maxpacket)
8009996: 697b ldr r3, [r7, #20]
8009998: 68da ldr r2, [r3, #12]
800999a: 697b ldr r3, [r7, #20]
800999c: 691b ldr r3, [r3, #16]
800999e: 429a cmp r2, r3
80099a0: d915 bls.n 80099ce <USBD_LL_DataInStage+0x5c>
{
pep->rem_length -= pep->maxpacket;
80099a2: 697b ldr r3, [r7, #20]
80099a4: 68da ldr r2, [r3, #12]
80099a6: 697b ldr r3, [r7, #20]
80099a8: 691b ldr r3, [r3, #16]
80099aa: 1ad2 subs r2, r2, r3
80099ac: 697b ldr r3, [r7, #20]
80099ae: 60da str r2, [r3, #12]
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
80099b0: 697b ldr r3, [r7, #20]
80099b2: 68db ldr r3, [r3, #12]
80099b4: b29b uxth r3, r3
80099b6: 461a mov r2, r3
80099b8: 6879 ldr r1, [r7, #4]
80099ba: 68f8 ldr r0, [r7, #12]
80099bc: f000 febe bl 800a73c <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80099c0: 2300 movs r3, #0
80099c2: 2200 movs r2, #0
80099c4: 2100 movs r1, #0
80099c6: 68f8 ldr r0, [r7, #12]
80099c8: f001 fbb7 bl 800b13a <USBD_LL_PrepareReceive>
80099cc: e04e b.n 8009a6c <USBD_LL_DataInStage+0xfa>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->total_length % pep->maxpacket == 0U) &&
80099ce: 697b ldr r3, [r7, #20]
80099d0: 689b ldr r3, [r3, #8]
80099d2: 697a ldr r2, [r7, #20]
80099d4: 6912 ldr r2, [r2, #16]
80099d6: fbb3 f1f2 udiv r1, r3, r2
80099da: fb01 f202 mul.w r2, r1, r2
80099de: 1a9b subs r3, r3, r2
80099e0: 2b00 cmp r3, #0
80099e2: d11c bne.n 8009a1e <USBD_LL_DataInStage+0xac>
(pep->total_length >= pep->maxpacket) &&
80099e4: 697b ldr r3, [r7, #20]
80099e6: 689a ldr r2, [r3, #8]
80099e8: 697b ldr r3, [r7, #20]
80099ea: 691b ldr r3, [r3, #16]
if ((pep->total_length % pep->maxpacket == 0U) &&
80099ec: 429a cmp r2, r3
80099ee: d316 bcc.n 8009a1e <USBD_LL_DataInStage+0xac>
(pep->total_length < pdev->ep0_data_len))
80099f0: 697b ldr r3, [r7, #20]
80099f2: 689a ldr r2, [r3, #8]
80099f4: 68fb ldr r3, [r7, #12]
80099f6: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
80099fa: 429a cmp r2, r3
80099fc: d20f bcs.n 8009a1e <USBD_LL_DataInStage+0xac>
{
USBD_CtlContinueSendData(pdev, NULL, 0U);
80099fe: 2200 movs r2, #0
8009a00: 2100 movs r1, #0
8009a02: 68f8 ldr r0, [r7, #12]
8009a04: f000 fe9a bl 800a73c <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
8009a08: 68fb ldr r3, [r7, #12]
8009a0a: 2200 movs r2, #0
8009a0c: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8009a10: 2300 movs r3, #0
8009a12: 2200 movs r2, #0
8009a14: 2100 movs r1, #0
8009a16: 68f8 ldr r0, [r7, #12]
8009a18: f001 fb8f bl 800b13a <USBD_LL_PrepareReceive>
8009a1c: e026 b.n 8009a6c <USBD_LL_DataInStage+0xfa>
}
else
{
if ((pdev->pClass->EP0_TxSent != NULL) &&
8009a1e: 68fb ldr r3, [r7, #12]
8009a20: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009a24: 68db ldr r3, [r3, #12]
8009a26: 2b00 cmp r3, #0
8009a28: d00a beq.n 8009a40 <USBD_LL_DataInStage+0xce>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8009a2a: 68fb ldr r3, [r7, #12]
8009a2c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_TxSent != NULL) &&
8009a30: 2b03 cmp r3, #3
8009a32: d105 bne.n 8009a40 <USBD_LL_DataInStage+0xce>
{
pdev->pClass->EP0_TxSent(pdev);
8009a34: 68fb ldr r3, [r7, #12]
8009a36: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009a3a: 68db ldr r3, [r3, #12]
8009a3c: 68f8 ldr r0, [r7, #12]
8009a3e: 4798 blx r3
}
USBD_LL_StallEP(pdev, 0x80U);
8009a40: 2180 movs r1, #128 @ 0x80
8009a42: 68f8 ldr r0, [r7, #12]
8009a44: f001 face bl 800afe4 <USBD_LL_StallEP>
USBD_CtlReceiveStatus(pdev);
8009a48: 68f8 ldr r0, [r7, #12]
8009a4a: f000 fecc bl 800a7e6 <USBD_CtlReceiveStatus>
8009a4e: e00d b.n 8009a6c <USBD_LL_DataInStage+0xfa>
}
}
}
else
{
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
8009a50: 68fb ldr r3, [r7, #12]
8009a52: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009a56: 2b04 cmp r3, #4
8009a58: d004 beq.n 8009a64 <USBD_LL_DataInStage+0xf2>
(pdev->ep0_state == USBD_EP0_IDLE))
8009a5a: 68fb ldr r3, [r7, #12]
8009a5c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
8009a60: 2b00 cmp r3, #0
8009a62: d103 bne.n 8009a6c <USBD_LL_DataInStage+0xfa>
{
USBD_LL_StallEP(pdev, 0x80U);
8009a64: 2180 movs r1, #128 @ 0x80
8009a66: 68f8 ldr r0, [r7, #12]
8009a68: f001 fabc bl 800afe4 <USBD_LL_StallEP>
}
}
if (pdev->dev_test_mode == 1U)
8009a6c: 68fb ldr r3, [r7, #12]
8009a6e: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
8009a72: 2b01 cmp r3, #1
8009a74: d11d bne.n 8009ab2 <USBD_LL_DataInStage+0x140>
{
USBD_RunTestMode(pdev);
8009a76: 68f8 ldr r0, [r7, #12]
8009a78: f7ff fe81 bl 800977e <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
8009a7c: 68fb ldr r3, [r7, #12]
8009a7e: 2200 movs r2, #0
8009a80: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
8009a84: e015 b.n 8009ab2 <USBD_LL_DataInStage+0x140>
}
}
else if ((pdev->pClass->DataIn != NULL) &&
8009a86: 68fb ldr r3, [r7, #12]
8009a88: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009a8c: 695b ldr r3, [r3, #20]
8009a8e: 2b00 cmp r3, #0
8009a90: d00d beq.n 8009aae <USBD_LL_DataInStage+0x13c>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8009a92: 68fb ldr r3, [r7, #12]
8009a94: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataIn != NULL) &&
8009a98: 2b03 cmp r3, #3
8009a9a: d108 bne.n 8009aae <USBD_LL_DataInStage+0x13c>
{
pdev->pClass->DataIn(pdev, epnum);
8009a9c: 68fb ldr r3, [r7, #12]
8009a9e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009aa2: 695b ldr r3, [r3, #20]
8009aa4: 7afa ldrb r2, [r7, #11]
8009aa6: 4611 mov r1, r2
8009aa8: 68f8 ldr r0, [r7, #12]
8009aaa: 4798 blx r3
8009aac: e001 b.n 8009ab2 <USBD_LL_DataInStage+0x140>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
8009aae: 2302 movs r3, #2
8009ab0: e000 b.n 8009ab4 <USBD_LL_DataInStage+0x142>
}
return USBD_OK;
8009ab2: 2300 movs r3, #0
}
8009ab4: 4618 mov r0, r3
8009ab6: 3718 adds r7, #24
8009ab8: 46bd mov sp, r7
8009aba: bd80 pop {r7, pc}
08009abc <USBD_LL_Reset>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
8009abc: b580 push {r7, lr}
8009abe: b082 sub sp, #8
8009ac0: af00 add r7, sp, #0
8009ac2: 6078 str r0, [r7, #4]
/* Open EP0 OUT */
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8009ac4: 2340 movs r3, #64 @ 0x40
8009ac6: 2200 movs r2, #0
8009ac8: 2100 movs r1, #0
8009aca: 6878 ldr r0, [r7, #4]
8009acc: f001 fa45 bl 800af5a <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
8009ad0: 687b ldr r3, [r7, #4]
8009ad2: 2201 movs r2, #1
8009ad4: f8c3 2158 str.w r2, [r3, #344] @ 0x158
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
8009ad8: 687b ldr r3, [r7, #4]
8009ada: 2240 movs r2, #64 @ 0x40
8009adc: f8c3 2164 str.w r2, [r3, #356] @ 0x164
/* Open EP0 IN */
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8009ae0: 2340 movs r3, #64 @ 0x40
8009ae2: 2200 movs r2, #0
8009ae4: 2180 movs r1, #128 @ 0x80
8009ae6: 6878 ldr r0, [r7, #4]
8009ae8: f001 fa37 bl 800af5a <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
8009aec: 687b ldr r3, [r7, #4]
8009aee: 2201 movs r2, #1
8009af0: 619a str r2, [r3, #24]
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
8009af2: 687b ldr r3, [r7, #4]
8009af4: 2240 movs r2, #64 @ 0x40
8009af6: 625a str r2, [r3, #36] @ 0x24
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
8009af8: 687b ldr r3, [r7, #4]
8009afa: 2201 movs r2, #1
8009afc: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
8009b00: 687b ldr r3, [r7, #4]
8009b02: 2200 movs r2, #0
8009b04: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
8009b08: 687b ldr r3, [r7, #4]
8009b0a: 2200 movs r2, #0
8009b0c: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
8009b0e: 687b ldr r3, [r7, #4]
8009b10: 2200 movs r2, #0
8009b12: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
if (pdev->pClassData)
8009b16: 687b ldr r3, [r7, #4]
8009b18: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009b1c: 2b00 cmp r3, #0
8009b1e: d009 beq.n 8009b34 <USBD_LL_Reset+0x78>
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
8009b20: 687b ldr r3, [r7, #4]
8009b22: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009b26: 685b ldr r3, [r3, #4]
8009b28: 687a ldr r2, [r7, #4]
8009b2a: 6852 ldr r2, [r2, #4]
8009b2c: b2d2 uxtb r2, r2
8009b2e: 4611 mov r1, r2
8009b30: 6878 ldr r0, [r7, #4]
8009b32: 4798 blx r3
}
return USBD_OK;
8009b34: 2300 movs r3, #0
}
8009b36: 4618 mov r0, r3
8009b38: 3708 adds r7, #8
8009b3a: 46bd mov sp, r7
8009b3c: bd80 pop {r7, pc}
08009b3e <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8009b3e: b480 push {r7}
8009b40: b083 sub sp, #12
8009b42: af00 add r7, sp, #0
8009b44: 6078 str r0, [r7, #4]
8009b46: 460b mov r3, r1
8009b48: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
8009b4a: 687b ldr r3, [r7, #4]
8009b4c: 78fa ldrb r2, [r7, #3]
8009b4e: 741a strb r2, [r3, #16]
return USBD_OK;
8009b50: 2300 movs r3, #0
}
8009b52: 4618 mov r0, r3
8009b54: 370c adds r7, #12
8009b56: 46bd mov sp, r7
8009b58: bc80 pop {r7}
8009b5a: 4770 bx lr
08009b5c <USBD_LL_Suspend>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8009b5c: b480 push {r7}
8009b5e: b083 sub sp, #12
8009b60: af00 add r7, sp, #0
8009b62: 6078 str r0, [r7, #4]
pdev->dev_old_state = pdev->dev_state;
8009b64: 687b ldr r3, [r7, #4]
8009b66: f893 229c ldrb.w r2, [r3, #668] @ 0x29c
8009b6a: 687b ldr r3, [r7, #4]
8009b6c: f883 229d strb.w r2, [r3, #669] @ 0x29d
pdev->dev_state = USBD_STATE_SUSPENDED;
8009b70: 687b ldr r3, [r7, #4]
8009b72: 2204 movs r2, #4
8009b74: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
8009b78: 2300 movs r3, #0
}
8009b7a: 4618 mov r0, r3
8009b7c: 370c adds r7, #12
8009b7e: 46bd mov sp, r7
8009b80: bc80 pop {r7}
8009b82: 4770 bx lr
08009b84 <USBD_LL_Resume>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
8009b84: b480 push {r7}
8009b86: b083 sub sp, #12
8009b88: af00 add r7, sp, #0
8009b8a: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8009b8c: 687b ldr r3, [r7, #4]
8009b8e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009b92: 2b04 cmp r3, #4
8009b94: d105 bne.n 8009ba2 <USBD_LL_Resume+0x1e>
{
pdev->dev_state = pdev->dev_old_state;
8009b96: 687b ldr r3, [r7, #4]
8009b98: f893 229d ldrb.w r2, [r3, #669] @ 0x29d
8009b9c: 687b ldr r3, [r7, #4]
8009b9e: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
8009ba2: 2300 movs r3, #0
}
8009ba4: 4618 mov r0, r3
8009ba6: 370c adds r7, #12
8009ba8: 46bd mov sp, r7
8009baa: bc80 pop {r7}
8009bac: 4770 bx lr
08009bae <USBD_LL_SOF>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
8009bae: b580 push {r7, lr}
8009bb0: b082 sub sp, #8
8009bb2: af00 add r7, sp, #0
8009bb4: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009bb6: 687b ldr r3, [r7, #4]
8009bb8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009bbc: 2b03 cmp r3, #3
8009bbe: d10b bne.n 8009bd8 <USBD_LL_SOF+0x2a>
{
if (pdev->pClass->SOF != NULL)
8009bc0: 687b ldr r3, [r7, #4]
8009bc2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009bc6: 69db ldr r3, [r3, #28]
8009bc8: 2b00 cmp r3, #0
8009bca: d005 beq.n 8009bd8 <USBD_LL_SOF+0x2a>
{
pdev->pClass->SOF(pdev);
8009bcc: 687b ldr r3, [r7, #4]
8009bce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009bd2: 69db ldr r3, [r3, #28]
8009bd4: 6878 ldr r0, [r7, #4]
8009bd6: 4798 blx r3
}
}
return USBD_OK;
8009bd8: 2300 movs r3, #0
}
8009bda: 4618 mov r0, r3
8009bdc: 3708 adds r7, #8
8009bde: 46bd mov sp, r7
8009be0: bd80 pop {r7, pc}
...
08009be4 <USBD_StdDevReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009be4: b580 push {r7, lr}
8009be6: b084 sub sp, #16
8009be8: af00 add r7, sp, #0
8009bea: 6078 str r0, [r7, #4]
8009bec: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8009bee: 2300 movs r3, #0
8009bf0: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009bf2: 683b ldr r3, [r7, #0]
8009bf4: 781b ldrb r3, [r3, #0]
8009bf6: f003 0360 and.w r3, r3, #96 @ 0x60
8009bfa: 2b40 cmp r3, #64 @ 0x40
8009bfc: d005 beq.n 8009c0a <USBD_StdDevReq+0x26>
8009bfe: 2b40 cmp r3, #64 @ 0x40
8009c00: d84f bhi.n 8009ca2 <USBD_StdDevReq+0xbe>
8009c02: 2b00 cmp r3, #0
8009c04: d009 beq.n 8009c1a <USBD_StdDevReq+0x36>
8009c06: 2b20 cmp r3, #32
8009c08: d14b bne.n 8009ca2 <USBD_StdDevReq+0xbe>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8009c0a: 687b ldr r3, [r7, #4]
8009c0c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009c10: 689b ldr r3, [r3, #8]
8009c12: 6839 ldr r1, [r7, #0]
8009c14: 6878 ldr r0, [r7, #4]
8009c16: 4798 blx r3
break;
8009c18: e048 b.n 8009cac <USBD_StdDevReq+0xc8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8009c1a: 683b ldr r3, [r7, #0]
8009c1c: 785b ldrb r3, [r3, #1]
8009c1e: 2b09 cmp r3, #9
8009c20: d839 bhi.n 8009c96 <USBD_StdDevReq+0xb2>
8009c22: a201 add r2, pc, #4 @ (adr r2, 8009c28 <USBD_StdDevReq+0x44>)
8009c24: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009c28: 08009c79 .word 0x08009c79
8009c2c: 08009c8d .word 0x08009c8d
8009c30: 08009c97 .word 0x08009c97
8009c34: 08009c83 .word 0x08009c83
8009c38: 08009c97 .word 0x08009c97
8009c3c: 08009c5b .word 0x08009c5b
8009c40: 08009c51 .word 0x08009c51
8009c44: 08009c97 .word 0x08009c97
8009c48: 08009c6f .word 0x08009c6f
8009c4c: 08009c65 .word 0x08009c65
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
8009c50: 6839 ldr r1, [r7, #0]
8009c52: 6878 ldr r0, [r7, #4]
8009c54: f000 f9dc bl 800a010 <USBD_GetDescriptor>
break;
8009c58: e022 b.n 8009ca0 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
8009c5a: 6839 ldr r1, [r7, #0]
8009c5c: 6878 ldr r0, [r7, #4]
8009c5e: f000 fb3f bl 800a2e0 <USBD_SetAddress>
break;
8009c62: e01d b.n 8009ca0 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_CONFIGURATION:
USBD_SetConfig(pdev, req);
8009c64: 6839 ldr r1, [r7, #0]
8009c66: 6878 ldr r0, [r7, #4]
8009c68: f000 fb7e bl 800a368 <USBD_SetConfig>
break;
8009c6c: e018 b.n 8009ca0 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
8009c6e: 6839 ldr r1, [r7, #0]
8009c70: 6878 ldr r0, [r7, #4]
8009c72: f000 fc07 bl 800a484 <USBD_GetConfig>
break;
8009c76: e013 b.n 8009ca0 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
8009c78: 6839 ldr r1, [r7, #0]
8009c7a: 6878 ldr r0, [r7, #4]
8009c7c: f000 fc37 bl 800a4ee <USBD_GetStatus>
break;
8009c80: e00e b.n 8009ca0 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
8009c82: 6839 ldr r1, [r7, #0]
8009c84: 6878 ldr r0, [r7, #4]
8009c86: f000 fc65 bl 800a554 <USBD_SetFeature>
break;
8009c8a: e009 b.n 8009ca0 <USBD_StdDevReq+0xbc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
8009c8c: 6839 ldr r1, [r7, #0]
8009c8e: 6878 ldr r0, [r7, #4]
8009c90: f000 fc74 bl 800a57c <USBD_ClrFeature>
break;
8009c94: e004 b.n 8009ca0 <USBD_StdDevReq+0xbc>
default:
USBD_CtlError(pdev, req);
8009c96: 6839 ldr r1, [r7, #0]
8009c98: 6878 ldr r0, [r7, #4]
8009c9a: f000 fcc9 bl 800a630 <USBD_CtlError>
break;
8009c9e: bf00 nop
}
break;
8009ca0: e004 b.n 8009cac <USBD_StdDevReq+0xc8>
default:
USBD_CtlError(pdev, req);
8009ca2: 6839 ldr r1, [r7, #0]
8009ca4: 6878 ldr r0, [r7, #4]
8009ca6: f000 fcc3 bl 800a630 <USBD_CtlError>
break;
8009caa: bf00 nop
}
return ret;
8009cac: 7bfb ldrb r3, [r7, #15]
}
8009cae: 4618 mov r0, r3
8009cb0: 3710 adds r7, #16
8009cb2: 46bd mov sp, r7
8009cb4: bd80 pop {r7, pc}
8009cb6: bf00 nop
08009cb8 <USBD_StdItfReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009cb8: b580 push {r7, lr}
8009cba: b084 sub sp, #16
8009cbc: af00 add r7, sp, #0
8009cbe: 6078 str r0, [r7, #4]
8009cc0: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8009cc2: 2300 movs r3, #0
8009cc4: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009cc6: 683b ldr r3, [r7, #0]
8009cc8: 781b ldrb r3, [r3, #0]
8009cca: f003 0360 and.w r3, r3, #96 @ 0x60
8009cce: 2b40 cmp r3, #64 @ 0x40
8009cd0: d005 beq.n 8009cde <USBD_StdItfReq+0x26>
8009cd2: 2b40 cmp r3, #64 @ 0x40
8009cd4: d82e bhi.n 8009d34 <USBD_StdItfReq+0x7c>
8009cd6: 2b00 cmp r3, #0
8009cd8: d001 beq.n 8009cde <USBD_StdItfReq+0x26>
8009cda: 2b20 cmp r3, #32
8009cdc: d12a bne.n 8009d34 <USBD_StdItfReq+0x7c>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
8009cde: 687b ldr r3, [r7, #4]
8009ce0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009ce4: 3b01 subs r3, #1
8009ce6: 2b02 cmp r3, #2
8009ce8: d81d bhi.n 8009d26 <USBD_StdItfReq+0x6e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
8009cea: 683b ldr r3, [r7, #0]
8009cec: 889b ldrh r3, [r3, #4]
8009cee: b2db uxtb r3, r3
8009cf0: 2b01 cmp r3, #1
8009cf2: d813 bhi.n 8009d1c <USBD_StdItfReq+0x64>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8009cf4: 687b ldr r3, [r7, #4]
8009cf6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009cfa: 689b ldr r3, [r3, #8]
8009cfc: 6839 ldr r1, [r7, #0]
8009cfe: 6878 ldr r0, [r7, #4]
8009d00: 4798 blx r3
8009d02: 4603 mov r3, r0
8009d04: 73fb strb r3, [r7, #15]
if ((req->wLength == 0U) && (ret == USBD_OK))
8009d06: 683b ldr r3, [r7, #0]
8009d08: 88db ldrh r3, [r3, #6]
8009d0a: 2b00 cmp r3, #0
8009d0c: d110 bne.n 8009d30 <USBD_StdItfReq+0x78>
8009d0e: 7bfb ldrb r3, [r7, #15]
8009d10: 2b00 cmp r3, #0
8009d12: d10d bne.n 8009d30 <USBD_StdItfReq+0x78>
{
USBD_CtlSendStatus(pdev);
8009d14: 6878 ldr r0, [r7, #4]
8009d16: f000 fd53 bl 800a7c0 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8009d1a: e009 b.n 8009d30 <USBD_StdItfReq+0x78>
USBD_CtlError(pdev, req);
8009d1c: 6839 ldr r1, [r7, #0]
8009d1e: 6878 ldr r0, [r7, #4]
8009d20: f000 fc86 bl 800a630 <USBD_CtlError>
break;
8009d24: e004 b.n 8009d30 <USBD_StdItfReq+0x78>
default:
USBD_CtlError(pdev, req);
8009d26: 6839 ldr r1, [r7, #0]
8009d28: 6878 ldr r0, [r7, #4]
8009d2a: f000 fc81 bl 800a630 <USBD_CtlError>
break;
8009d2e: e000 b.n 8009d32 <USBD_StdItfReq+0x7a>
break;
8009d30: bf00 nop
}
break;
8009d32: e004 b.n 8009d3e <USBD_StdItfReq+0x86>
default:
USBD_CtlError(pdev, req);
8009d34: 6839 ldr r1, [r7, #0]
8009d36: 6878 ldr r0, [r7, #4]
8009d38: f000 fc7a bl 800a630 <USBD_CtlError>
break;
8009d3c: bf00 nop
}
return USBD_OK;
8009d3e: 2300 movs r3, #0
}
8009d40: 4618 mov r0, r3
8009d42: 3710 adds r7, #16
8009d44: 46bd mov sp, r7
8009d46: bd80 pop {r7, pc}
08009d48 <USBD_StdEPReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009d48: b580 push {r7, lr}
8009d4a: b084 sub sp, #16
8009d4c: af00 add r7, sp, #0
8009d4e: 6078 str r0, [r7, #4]
8009d50: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
USBD_StatusTypeDef ret = USBD_OK;
8009d52: 2300 movs r3, #0
8009d54: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
8009d56: 683b ldr r3, [r7, #0]
8009d58: 889b ldrh r3, [r3, #4]
8009d5a: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009d5c: 683b ldr r3, [r7, #0]
8009d5e: 781b ldrb r3, [r3, #0]
8009d60: f003 0360 and.w r3, r3, #96 @ 0x60
8009d64: 2b40 cmp r3, #64 @ 0x40
8009d66: d007 beq.n 8009d78 <USBD_StdEPReq+0x30>
8009d68: 2b40 cmp r3, #64 @ 0x40
8009d6a: f200 8146 bhi.w 8009ffa <USBD_StdEPReq+0x2b2>
8009d6e: 2b00 cmp r3, #0
8009d70: d00a beq.n 8009d88 <USBD_StdEPReq+0x40>
8009d72: 2b20 cmp r3, #32
8009d74: f040 8141 bne.w 8009ffa <USBD_StdEPReq+0x2b2>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8009d78: 687b ldr r3, [r7, #4]
8009d7a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009d7e: 689b ldr r3, [r3, #8]
8009d80: 6839 ldr r1, [r7, #0]
8009d82: 6878 ldr r0, [r7, #4]
8009d84: 4798 blx r3
break;
8009d86: e13d b.n 800a004 <USBD_StdEPReq+0x2bc>
case USB_REQ_TYPE_STANDARD:
/* Check if it is a class request */
if ((req->bmRequest & 0x60U) == 0x20U)
8009d88: 683b ldr r3, [r7, #0]
8009d8a: 781b ldrb r3, [r3, #0]
8009d8c: f003 0360 and.w r3, r3, #96 @ 0x60
8009d90: 2b20 cmp r3, #32
8009d92: d10a bne.n 8009daa <USBD_StdEPReq+0x62>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8009d94: 687b ldr r3, [r7, #4]
8009d96: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009d9a: 689b ldr r3, [r3, #8]
8009d9c: 6839 ldr r1, [r7, #0]
8009d9e: 6878 ldr r0, [r7, #4]
8009da0: 4798 blx r3
8009da2: 4603 mov r3, r0
8009da4: 73fb strb r3, [r7, #15]
return ret;
8009da6: 7bfb ldrb r3, [r7, #15]
8009da8: e12d b.n 800a006 <USBD_StdEPReq+0x2be>
}
switch (req->bRequest)
8009daa: 683b ldr r3, [r7, #0]
8009dac: 785b ldrb r3, [r3, #1]
8009dae: 2b03 cmp r3, #3
8009db0: d007 beq.n 8009dc2 <USBD_StdEPReq+0x7a>
8009db2: 2b03 cmp r3, #3
8009db4: f300 811b bgt.w 8009fee <USBD_StdEPReq+0x2a6>
8009db8: 2b00 cmp r3, #0
8009dba: d072 beq.n 8009ea2 <USBD_StdEPReq+0x15a>
8009dbc: 2b01 cmp r3, #1
8009dbe: d03a beq.n 8009e36 <USBD_StdEPReq+0xee>
8009dc0: e115 b.n 8009fee <USBD_StdEPReq+0x2a6>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
8009dc2: 687b ldr r3, [r7, #4]
8009dc4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009dc8: 2b02 cmp r3, #2
8009dca: d002 beq.n 8009dd2 <USBD_StdEPReq+0x8a>
8009dcc: 2b03 cmp r3, #3
8009dce: d015 beq.n 8009dfc <USBD_StdEPReq+0xb4>
8009dd0: e02b b.n 8009e2a <USBD_StdEPReq+0xe2>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8009dd2: 7bbb ldrb r3, [r7, #14]
8009dd4: 2b00 cmp r3, #0
8009dd6: d00c beq.n 8009df2 <USBD_StdEPReq+0xaa>
8009dd8: 7bbb ldrb r3, [r7, #14]
8009dda: 2b80 cmp r3, #128 @ 0x80
8009ddc: d009 beq.n 8009df2 <USBD_StdEPReq+0xaa>
{
USBD_LL_StallEP(pdev, ep_addr);
8009dde: 7bbb ldrb r3, [r7, #14]
8009de0: 4619 mov r1, r3
8009de2: 6878 ldr r0, [r7, #4]
8009de4: f001 f8fe bl 800afe4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8009de8: 2180 movs r1, #128 @ 0x80
8009dea: 6878 ldr r0, [r7, #4]
8009dec: f001 f8fa bl 800afe4 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8009df0: e020 b.n 8009e34 <USBD_StdEPReq+0xec>
USBD_CtlError(pdev, req);
8009df2: 6839 ldr r1, [r7, #0]
8009df4: 6878 ldr r0, [r7, #4]
8009df6: f000 fc1b bl 800a630 <USBD_CtlError>
break;
8009dfa: e01b b.n 8009e34 <USBD_StdEPReq+0xec>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8009dfc: 683b ldr r3, [r7, #0]
8009dfe: 885b ldrh r3, [r3, #2]
8009e00: 2b00 cmp r3, #0
8009e02: d10e bne.n 8009e22 <USBD_StdEPReq+0xda>
{
if ((ep_addr != 0x00U) &&
8009e04: 7bbb ldrb r3, [r7, #14]
8009e06: 2b00 cmp r3, #0
8009e08: d00b beq.n 8009e22 <USBD_StdEPReq+0xda>
8009e0a: 7bbb ldrb r3, [r7, #14]
8009e0c: 2b80 cmp r3, #128 @ 0x80
8009e0e: d008 beq.n 8009e22 <USBD_StdEPReq+0xda>
(ep_addr != 0x80U) && (req->wLength == 0x00U))
8009e10: 683b ldr r3, [r7, #0]
8009e12: 88db ldrh r3, [r3, #6]
8009e14: 2b00 cmp r3, #0
8009e16: d104 bne.n 8009e22 <USBD_StdEPReq+0xda>
{
USBD_LL_StallEP(pdev, ep_addr);
8009e18: 7bbb ldrb r3, [r7, #14]
8009e1a: 4619 mov r1, r3
8009e1c: 6878 ldr r0, [r7, #4]
8009e1e: f001 f8e1 bl 800afe4 <USBD_LL_StallEP>
}
}
USBD_CtlSendStatus(pdev);
8009e22: 6878 ldr r0, [r7, #4]
8009e24: f000 fccc bl 800a7c0 <USBD_CtlSendStatus>
break;
8009e28: e004 b.n 8009e34 <USBD_StdEPReq+0xec>
default:
USBD_CtlError(pdev, req);
8009e2a: 6839 ldr r1, [r7, #0]
8009e2c: 6878 ldr r0, [r7, #4]
8009e2e: f000 fbff bl 800a630 <USBD_CtlError>
break;
8009e32: bf00 nop
}
break;
8009e34: e0e0 b.n 8009ff8 <USBD_StdEPReq+0x2b0>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
8009e36: 687b ldr r3, [r7, #4]
8009e38: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009e3c: 2b02 cmp r3, #2
8009e3e: d002 beq.n 8009e46 <USBD_StdEPReq+0xfe>
8009e40: 2b03 cmp r3, #3
8009e42: d015 beq.n 8009e70 <USBD_StdEPReq+0x128>
8009e44: e026 b.n 8009e94 <USBD_StdEPReq+0x14c>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8009e46: 7bbb ldrb r3, [r7, #14]
8009e48: 2b00 cmp r3, #0
8009e4a: d00c beq.n 8009e66 <USBD_StdEPReq+0x11e>
8009e4c: 7bbb ldrb r3, [r7, #14]
8009e4e: 2b80 cmp r3, #128 @ 0x80
8009e50: d009 beq.n 8009e66 <USBD_StdEPReq+0x11e>
{
USBD_LL_StallEP(pdev, ep_addr);
8009e52: 7bbb ldrb r3, [r7, #14]
8009e54: 4619 mov r1, r3
8009e56: 6878 ldr r0, [r7, #4]
8009e58: f001 f8c4 bl 800afe4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8009e5c: 2180 movs r1, #128 @ 0x80
8009e5e: 6878 ldr r0, [r7, #4]
8009e60: f001 f8c0 bl 800afe4 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8009e64: e01c b.n 8009ea0 <USBD_StdEPReq+0x158>
USBD_CtlError(pdev, req);
8009e66: 6839 ldr r1, [r7, #0]
8009e68: 6878 ldr r0, [r7, #4]
8009e6a: f000 fbe1 bl 800a630 <USBD_CtlError>
break;
8009e6e: e017 b.n 8009ea0 <USBD_StdEPReq+0x158>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8009e70: 683b ldr r3, [r7, #0]
8009e72: 885b ldrh r3, [r3, #2]
8009e74: 2b00 cmp r3, #0
8009e76: d112 bne.n 8009e9e <USBD_StdEPReq+0x156>
{
if ((ep_addr & 0x7FU) != 0x00U)
8009e78: 7bbb ldrb r3, [r7, #14]
8009e7a: f003 037f and.w r3, r3, #127 @ 0x7f
8009e7e: 2b00 cmp r3, #0
8009e80: d004 beq.n 8009e8c <USBD_StdEPReq+0x144>
{
USBD_LL_ClearStallEP(pdev, ep_addr);
8009e82: 7bbb ldrb r3, [r7, #14]
8009e84: 4619 mov r1, r3
8009e86: 6878 ldr r0, [r7, #4]
8009e88: f001 f8cb bl 800b022 <USBD_LL_ClearStallEP>
}
USBD_CtlSendStatus(pdev);
8009e8c: 6878 ldr r0, [r7, #4]
8009e8e: f000 fc97 bl 800a7c0 <USBD_CtlSendStatus>
}
break;
8009e92: e004 b.n 8009e9e <USBD_StdEPReq+0x156>
default:
USBD_CtlError(pdev, req);
8009e94: 6839 ldr r1, [r7, #0]
8009e96: 6878 ldr r0, [r7, #4]
8009e98: f000 fbca bl 800a630 <USBD_CtlError>
break;
8009e9c: e000 b.n 8009ea0 <USBD_StdEPReq+0x158>
break;
8009e9e: bf00 nop
}
break;
8009ea0: e0aa b.n 8009ff8 <USBD_StdEPReq+0x2b0>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
8009ea2: 687b ldr r3, [r7, #4]
8009ea4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009ea8: 2b02 cmp r3, #2
8009eaa: d002 beq.n 8009eb2 <USBD_StdEPReq+0x16a>
8009eac: 2b03 cmp r3, #3
8009eae: d032 beq.n 8009f16 <USBD_StdEPReq+0x1ce>
8009eb0: e097 b.n 8009fe2 <USBD_StdEPReq+0x29a>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8009eb2: 7bbb ldrb r3, [r7, #14]
8009eb4: 2b00 cmp r3, #0
8009eb6: d007 beq.n 8009ec8 <USBD_StdEPReq+0x180>
8009eb8: 7bbb ldrb r3, [r7, #14]
8009eba: 2b80 cmp r3, #128 @ 0x80
8009ebc: d004 beq.n 8009ec8 <USBD_StdEPReq+0x180>
{
USBD_CtlError(pdev, req);
8009ebe: 6839 ldr r1, [r7, #0]
8009ec0: 6878 ldr r0, [r7, #4]
8009ec2: f000 fbb5 bl 800a630 <USBD_CtlError>
break;
8009ec6: e091 b.n 8009fec <USBD_StdEPReq+0x2a4>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009ec8: f997 300e ldrsb.w r3, [r7, #14]
8009ecc: 2b00 cmp r3, #0
8009ece: da0b bge.n 8009ee8 <USBD_StdEPReq+0x1a0>
8009ed0: 7bbb ldrb r3, [r7, #14]
8009ed2: f003 027f and.w r2, r3, #127 @ 0x7f
8009ed6: 4613 mov r3, r2
8009ed8: 009b lsls r3, r3, #2
8009eda: 4413 add r3, r2
8009edc: 009b lsls r3, r3, #2
8009ede: 3310 adds r3, #16
8009ee0: 687a ldr r2, [r7, #4]
8009ee2: 4413 add r3, r2
8009ee4: 3304 adds r3, #4
8009ee6: e00b b.n 8009f00 <USBD_StdEPReq+0x1b8>
&pdev->ep_out[ep_addr & 0x7FU];
8009ee8: 7bbb ldrb r3, [r7, #14]
8009eea: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009eee: 4613 mov r3, r2
8009ef0: 009b lsls r3, r3, #2
8009ef2: 4413 add r3, r2
8009ef4: 009b lsls r3, r3, #2
8009ef6: f503 73a8 add.w r3, r3, #336 @ 0x150
8009efa: 687a ldr r2, [r7, #4]
8009efc: 4413 add r3, r2
8009efe: 3304 adds r3, #4
8009f00: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
8009f02: 68bb ldr r3, [r7, #8]
8009f04: 2200 movs r2, #0
8009f06: 601a str r2, [r3, #0]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8009f08: 68bb ldr r3, [r7, #8]
8009f0a: 2202 movs r2, #2
8009f0c: 4619 mov r1, r3
8009f0e: 6878 ldr r0, [r7, #4]
8009f10: f000 fbf8 bl 800a704 <USBD_CtlSendData>
break;
8009f14: e06a b.n 8009fec <USBD_StdEPReq+0x2a4>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
8009f16: f997 300e ldrsb.w r3, [r7, #14]
8009f1a: 2b00 cmp r3, #0
8009f1c: da11 bge.n 8009f42 <USBD_StdEPReq+0x1fa>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
8009f1e: 7bbb ldrb r3, [r7, #14]
8009f20: f003 020f and.w r2, r3, #15
8009f24: 6879 ldr r1, [r7, #4]
8009f26: 4613 mov r3, r2
8009f28: 009b lsls r3, r3, #2
8009f2a: 4413 add r3, r2
8009f2c: 009b lsls r3, r3, #2
8009f2e: 440b add r3, r1
8009f30: 3318 adds r3, #24
8009f32: 681b ldr r3, [r3, #0]
8009f34: 2b00 cmp r3, #0
8009f36: d117 bne.n 8009f68 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
8009f38: 6839 ldr r1, [r7, #0]
8009f3a: 6878 ldr r0, [r7, #4]
8009f3c: f000 fb78 bl 800a630 <USBD_CtlError>
break;
8009f40: e054 b.n 8009fec <USBD_StdEPReq+0x2a4>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
8009f42: 7bbb ldrb r3, [r7, #14]
8009f44: f003 020f and.w r2, r3, #15
8009f48: 6879 ldr r1, [r7, #4]
8009f4a: 4613 mov r3, r2
8009f4c: 009b lsls r3, r3, #2
8009f4e: 4413 add r3, r2
8009f50: 009b lsls r3, r3, #2
8009f52: 440b add r3, r1
8009f54: f503 73ac add.w r3, r3, #344 @ 0x158
8009f58: 681b ldr r3, [r3, #0]
8009f5a: 2b00 cmp r3, #0
8009f5c: d104 bne.n 8009f68 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
8009f5e: 6839 ldr r1, [r7, #0]
8009f60: 6878 ldr r0, [r7, #4]
8009f62: f000 fb65 bl 800a630 <USBD_CtlError>
break;
8009f66: e041 b.n 8009fec <USBD_StdEPReq+0x2a4>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009f68: f997 300e ldrsb.w r3, [r7, #14]
8009f6c: 2b00 cmp r3, #0
8009f6e: da0b bge.n 8009f88 <USBD_StdEPReq+0x240>
8009f70: 7bbb ldrb r3, [r7, #14]
8009f72: f003 027f and.w r2, r3, #127 @ 0x7f
8009f76: 4613 mov r3, r2
8009f78: 009b lsls r3, r3, #2
8009f7a: 4413 add r3, r2
8009f7c: 009b lsls r3, r3, #2
8009f7e: 3310 adds r3, #16
8009f80: 687a ldr r2, [r7, #4]
8009f82: 4413 add r3, r2
8009f84: 3304 adds r3, #4
8009f86: e00b b.n 8009fa0 <USBD_StdEPReq+0x258>
&pdev->ep_out[ep_addr & 0x7FU];
8009f88: 7bbb ldrb r3, [r7, #14]
8009f8a: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009f8e: 4613 mov r3, r2
8009f90: 009b lsls r3, r3, #2
8009f92: 4413 add r3, r2
8009f94: 009b lsls r3, r3, #2
8009f96: f503 73a8 add.w r3, r3, #336 @ 0x150
8009f9a: 687a ldr r2, [r7, #4]
8009f9c: 4413 add r3, r2
8009f9e: 3304 adds r3, #4
8009fa0: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
8009fa2: 7bbb ldrb r3, [r7, #14]
8009fa4: 2b00 cmp r3, #0
8009fa6: d002 beq.n 8009fae <USBD_StdEPReq+0x266>
8009fa8: 7bbb ldrb r3, [r7, #14]
8009faa: 2b80 cmp r3, #128 @ 0x80
8009fac: d103 bne.n 8009fb6 <USBD_StdEPReq+0x26e>
{
pep->status = 0x0000U;
8009fae: 68bb ldr r3, [r7, #8]
8009fb0: 2200 movs r2, #0
8009fb2: 601a str r2, [r3, #0]
8009fb4: e00e b.n 8009fd4 <USBD_StdEPReq+0x28c>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr))
8009fb6: 7bbb ldrb r3, [r7, #14]
8009fb8: 4619 mov r1, r3
8009fba: 6878 ldr r0, [r7, #4]
8009fbc: f001 f850 bl 800b060 <USBD_LL_IsStallEP>
8009fc0: 4603 mov r3, r0
8009fc2: 2b00 cmp r3, #0
8009fc4: d003 beq.n 8009fce <USBD_StdEPReq+0x286>
{
pep->status = 0x0001U;
8009fc6: 68bb ldr r3, [r7, #8]
8009fc8: 2201 movs r2, #1
8009fca: 601a str r2, [r3, #0]
8009fcc: e002 b.n 8009fd4 <USBD_StdEPReq+0x28c>
}
else
{
pep->status = 0x0000U;
8009fce: 68bb ldr r3, [r7, #8]
8009fd0: 2200 movs r2, #0
8009fd2: 601a str r2, [r3, #0]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8009fd4: 68bb ldr r3, [r7, #8]
8009fd6: 2202 movs r2, #2
8009fd8: 4619 mov r1, r3
8009fda: 6878 ldr r0, [r7, #4]
8009fdc: f000 fb92 bl 800a704 <USBD_CtlSendData>
break;
8009fe0: e004 b.n 8009fec <USBD_StdEPReq+0x2a4>
default:
USBD_CtlError(pdev, req);
8009fe2: 6839 ldr r1, [r7, #0]
8009fe4: 6878 ldr r0, [r7, #4]
8009fe6: f000 fb23 bl 800a630 <USBD_CtlError>
break;
8009fea: bf00 nop
}
break;
8009fec: e004 b.n 8009ff8 <USBD_StdEPReq+0x2b0>
default:
USBD_CtlError(pdev, req);
8009fee: 6839 ldr r1, [r7, #0]
8009ff0: 6878 ldr r0, [r7, #4]
8009ff2: f000 fb1d bl 800a630 <USBD_CtlError>
break;
8009ff6: bf00 nop
}
break;
8009ff8: e004 b.n 800a004 <USBD_StdEPReq+0x2bc>
default:
USBD_CtlError(pdev, req);
8009ffa: 6839 ldr r1, [r7, #0]
8009ffc: 6878 ldr r0, [r7, #4]
8009ffe: f000 fb17 bl 800a630 <USBD_CtlError>
break;
800a002: bf00 nop
}
return ret;
800a004: 7bfb ldrb r3, [r7, #15]
}
800a006: 4618 mov r0, r3
800a008: 3710 adds r7, #16
800a00a: 46bd mov sp, r7
800a00c: bd80 pop {r7, pc}
...
0800a010 <USBD_GetDescriptor>:
* @param req: usb request
* @retval status
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a010: b580 push {r7, lr}
800a012: b084 sub sp, #16
800a014: af00 add r7, sp, #0
800a016: 6078 str r0, [r7, #4]
800a018: 6039 str r1, [r7, #0]
uint16_t len = 0U;
800a01a: 2300 movs r3, #0
800a01c: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
800a01e: 2300 movs r3, #0
800a020: 60fb str r3, [r7, #12]
uint8_t err = 0U;
800a022: 2300 movs r3, #0
800a024: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
800a026: 683b ldr r3, [r7, #0]
800a028: 885b ldrh r3, [r3, #2]
800a02a: 0a1b lsrs r3, r3, #8
800a02c: b29b uxth r3, r3
800a02e: 3b01 subs r3, #1
800a030: 2b06 cmp r3, #6
800a032: f200 8128 bhi.w 800a286 <USBD_GetDescriptor+0x276>
800a036: a201 add r2, pc, #4 @ (adr r2, 800a03c <USBD_GetDescriptor+0x2c>)
800a038: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a03c: 0800a059 .word 0x0800a059
800a040: 0800a071 .word 0x0800a071
800a044: 0800a0b1 .word 0x0800a0b1
800a048: 0800a287 .word 0x0800a287
800a04c: 0800a287 .word 0x0800a287
800a050: 0800a227 .word 0x0800a227
800a054: 0800a253 .word 0x0800a253
err++;
}
break;
#endif
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
800a058: 687b ldr r3, [r7, #4]
800a05a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a05e: 681b ldr r3, [r3, #0]
800a060: 687a ldr r2, [r7, #4]
800a062: 7c12 ldrb r2, [r2, #16]
800a064: f107 0108 add.w r1, r7, #8
800a068: 4610 mov r0, r2
800a06a: 4798 blx r3
800a06c: 60f8 str r0, [r7, #12]
break;
800a06e: e112 b.n 800a296 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a070: 687b ldr r3, [r7, #4]
800a072: 7c1b ldrb r3, [r3, #16]
800a074: 2b00 cmp r3, #0
800a076: d10d bne.n 800a094 <USBD_GetDescriptor+0x84>
{
pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
800a078: 687b ldr r3, [r7, #4]
800a07a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a07e: 6a9b ldr r3, [r3, #40] @ 0x28
800a080: f107 0208 add.w r2, r7, #8
800a084: 4610 mov r0, r2
800a086: 4798 blx r3
800a088: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800a08a: 68fb ldr r3, [r7, #12]
800a08c: 3301 adds r3, #1
800a08e: 2202 movs r2, #2
800a090: 701a strb r2, [r3, #0]
else
{
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
800a092: e100 b.n 800a296 <USBD_GetDescriptor+0x286>
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
800a094: 687b ldr r3, [r7, #4]
800a096: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a09a: 6adb ldr r3, [r3, #44] @ 0x2c
800a09c: f107 0208 add.w r2, r7, #8
800a0a0: 4610 mov r0, r2
800a0a2: 4798 blx r3
800a0a4: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800a0a6: 68fb ldr r3, [r7, #12]
800a0a8: 3301 adds r3, #1
800a0aa: 2202 movs r2, #2
800a0ac: 701a strb r2, [r3, #0]
break;
800a0ae: e0f2 b.n 800a296 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
800a0b0: 683b ldr r3, [r7, #0]
800a0b2: 885b ldrh r3, [r3, #2]
800a0b4: b2db uxtb r3, r3
800a0b6: 2b05 cmp r3, #5
800a0b8: f200 80ac bhi.w 800a214 <USBD_GetDescriptor+0x204>
800a0bc: a201 add r2, pc, #4 @ (adr r2, 800a0c4 <USBD_GetDescriptor+0xb4>)
800a0be: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a0c2: bf00 nop
800a0c4: 0800a0dd .word 0x0800a0dd
800a0c8: 0800a111 .word 0x0800a111
800a0cc: 0800a145 .word 0x0800a145
800a0d0: 0800a179 .word 0x0800a179
800a0d4: 0800a1ad .word 0x0800a1ad
800a0d8: 0800a1e1 .word 0x0800a1e1
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
800a0dc: 687b ldr r3, [r7, #4]
800a0de: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a0e2: 685b ldr r3, [r3, #4]
800a0e4: 2b00 cmp r3, #0
800a0e6: d00b beq.n 800a100 <USBD_GetDescriptor+0xf0>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
800a0e8: 687b ldr r3, [r7, #4]
800a0ea: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a0ee: 685b ldr r3, [r3, #4]
800a0f0: 687a ldr r2, [r7, #4]
800a0f2: 7c12 ldrb r2, [r2, #16]
800a0f4: f107 0108 add.w r1, r7, #8
800a0f8: 4610 mov r0, r2
800a0fa: 4798 blx r3
800a0fc: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a0fe: e091 b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a100: 6839 ldr r1, [r7, #0]
800a102: 6878 ldr r0, [r7, #4]
800a104: f000 fa94 bl 800a630 <USBD_CtlError>
err++;
800a108: 7afb ldrb r3, [r7, #11]
800a10a: 3301 adds r3, #1
800a10c: 72fb strb r3, [r7, #11]
break;
800a10e: e089 b.n 800a224 <USBD_GetDescriptor+0x214>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
800a110: 687b ldr r3, [r7, #4]
800a112: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a116: 689b ldr r3, [r3, #8]
800a118: 2b00 cmp r3, #0
800a11a: d00b beq.n 800a134 <USBD_GetDescriptor+0x124>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
800a11c: 687b ldr r3, [r7, #4]
800a11e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a122: 689b ldr r3, [r3, #8]
800a124: 687a ldr r2, [r7, #4]
800a126: 7c12 ldrb r2, [r2, #16]
800a128: f107 0108 add.w r1, r7, #8
800a12c: 4610 mov r0, r2
800a12e: 4798 blx r3
800a130: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a132: e077 b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a134: 6839 ldr r1, [r7, #0]
800a136: 6878 ldr r0, [r7, #4]
800a138: f000 fa7a bl 800a630 <USBD_CtlError>
err++;
800a13c: 7afb ldrb r3, [r7, #11]
800a13e: 3301 adds r3, #1
800a140: 72fb strb r3, [r7, #11]
break;
800a142: e06f b.n 800a224 <USBD_GetDescriptor+0x214>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
800a144: 687b ldr r3, [r7, #4]
800a146: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a14a: 68db ldr r3, [r3, #12]
800a14c: 2b00 cmp r3, #0
800a14e: d00b beq.n 800a168 <USBD_GetDescriptor+0x158>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
800a150: 687b ldr r3, [r7, #4]
800a152: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a156: 68db ldr r3, [r3, #12]
800a158: 687a ldr r2, [r7, #4]
800a15a: 7c12 ldrb r2, [r2, #16]
800a15c: f107 0108 add.w r1, r7, #8
800a160: 4610 mov r0, r2
800a162: 4798 blx r3
800a164: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a166: e05d b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a168: 6839 ldr r1, [r7, #0]
800a16a: 6878 ldr r0, [r7, #4]
800a16c: f000 fa60 bl 800a630 <USBD_CtlError>
err++;
800a170: 7afb ldrb r3, [r7, #11]
800a172: 3301 adds r3, #1
800a174: 72fb strb r3, [r7, #11]
break;
800a176: e055 b.n 800a224 <USBD_GetDescriptor+0x214>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
800a178: 687b ldr r3, [r7, #4]
800a17a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a17e: 691b ldr r3, [r3, #16]
800a180: 2b00 cmp r3, #0
800a182: d00b beq.n 800a19c <USBD_GetDescriptor+0x18c>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
800a184: 687b ldr r3, [r7, #4]
800a186: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a18a: 691b ldr r3, [r3, #16]
800a18c: 687a ldr r2, [r7, #4]
800a18e: 7c12 ldrb r2, [r2, #16]
800a190: f107 0108 add.w r1, r7, #8
800a194: 4610 mov r0, r2
800a196: 4798 blx r3
800a198: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a19a: e043 b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a19c: 6839 ldr r1, [r7, #0]
800a19e: 6878 ldr r0, [r7, #4]
800a1a0: f000 fa46 bl 800a630 <USBD_CtlError>
err++;
800a1a4: 7afb ldrb r3, [r7, #11]
800a1a6: 3301 adds r3, #1
800a1a8: 72fb strb r3, [r7, #11]
break;
800a1aa: e03b b.n 800a224 <USBD_GetDescriptor+0x214>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
800a1ac: 687b ldr r3, [r7, #4]
800a1ae: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a1b2: 695b ldr r3, [r3, #20]
800a1b4: 2b00 cmp r3, #0
800a1b6: d00b beq.n 800a1d0 <USBD_GetDescriptor+0x1c0>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
800a1b8: 687b ldr r3, [r7, #4]
800a1ba: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a1be: 695b ldr r3, [r3, #20]
800a1c0: 687a ldr r2, [r7, #4]
800a1c2: 7c12 ldrb r2, [r2, #16]
800a1c4: f107 0108 add.w r1, r7, #8
800a1c8: 4610 mov r0, r2
800a1ca: 4798 blx r3
800a1cc: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a1ce: e029 b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a1d0: 6839 ldr r1, [r7, #0]
800a1d2: 6878 ldr r0, [r7, #4]
800a1d4: f000 fa2c bl 800a630 <USBD_CtlError>
err++;
800a1d8: 7afb ldrb r3, [r7, #11]
800a1da: 3301 adds r3, #1
800a1dc: 72fb strb r3, [r7, #11]
break;
800a1de: e021 b.n 800a224 <USBD_GetDescriptor+0x214>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
800a1e0: 687b ldr r3, [r7, #4]
800a1e2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a1e6: 699b ldr r3, [r3, #24]
800a1e8: 2b00 cmp r3, #0
800a1ea: d00b beq.n 800a204 <USBD_GetDescriptor+0x1f4>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
800a1ec: 687b ldr r3, [r7, #4]
800a1ee: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a1f2: 699b ldr r3, [r3, #24]
800a1f4: 687a ldr r2, [r7, #4]
800a1f6: 7c12 ldrb r2, [r2, #16]
800a1f8: f107 0108 add.w r1, r7, #8
800a1fc: 4610 mov r0, r2
800a1fe: 4798 blx r3
800a200: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a202: e00f b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a204: 6839 ldr r1, [r7, #0]
800a206: 6878 ldr r0, [r7, #4]
800a208: f000 fa12 bl 800a630 <USBD_CtlError>
err++;
800a20c: 7afb ldrb r3, [r7, #11]
800a20e: 3301 adds r3, #1
800a210: 72fb strb r3, [r7, #11]
break;
800a212: e007 b.n 800a224 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
err++;
}
break;
#else
USBD_CtlError(pdev, req);
800a214: 6839 ldr r1, [r7, #0]
800a216: 6878 ldr r0, [r7, #4]
800a218: f000 fa0a bl 800a630 <USBD_CtlError>
err++;
800a21c: 7afb ldrb r3, [r7, #11]
800a21e: 3301 adds r3, #1
800a220: 72fb strb r3, [r7, #11]
#endif
}
break;
800a222: e038 b.n 800a296 <USBD_GetDescriptor+0x286>
800a224: e037 b.n 800a296 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a226: 687b ldr r3, [r7, #4]
800a228: 7c1b ldrb r3, [r3, #16]
800a22a: 2b00 cmp r3, #0
800a22c: d109 bne.n 800a242 <USBD_GetDescriptor+0x232>
{
pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
800a22e: 687b ldr r3, [r7, #4]
800a230: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a234: 6b5b ldr r3, [r3, #52] @ 0x34
800a236: f107 0208 add.w r2, r7, #8
800a23a: 4610 mov r0, r2
800a23c: 4798 blx r3
800a23e: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a240: e029 b.n 800a296 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
800a242: 6839 ldr r1, [r7, #0]
800a244: 6878 ldr r0, [r7, #4]
800a246: f000 f9f3 bl 800a630 <USBD_CtlError>
err++;
800a24a: 7afb ldrb r3, [r7, #11]
800a24c: 3301 adds r3, #1
800a24e: 72fb strb r3, [r7, #11]
break;
800a250: e021 b.n 800a296 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a252: 687b ldr r3, [r7, #4]
800a254: 7c1b ldrb r3, [r3, #16]
800a256: 2b00 cmp r3, #0
800a258: d10d bne.n 800a276 <USBD_GetDescriptor+0x266>
{
pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
800a25a: 687b ldr r3, [r7, #4]
800a25c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a260: 6b1b ldr r3, [r3, #48] @ 0x30
800a262: f107 0208 add.w r2, r7, #8
800a266: 4610 mov r0, r2
800a268: 4798 blx r3
800a26a: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
800a26c: 68fb ldr r3, [r7, #12]
800a26e: 3301 adds r3, #1
800a270: 2207 movs r2, #7
800a272: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a274: e00f b.n 800a296 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
800a276: 6839 ldr r1, [r7, #0]
800a278: 6878 ldr r0, [r7, #4]
800a27a: f000 f9d9 bl 800a630 <USBD_CtlError>
err++;
800a27e: 7afb ldrb r3, [r7, #11]
800a280: 3301 adds r3, #1
800a282: 72fb strb r3, [r7, #11]
break;
800a284: e007 b.n 800a296 <USBD_GetDescriptor+0x286>
default:
USBD_CtlError(pdev, req);
800a286: 6839 ldr r1, [r7, #0]
800a288: 6878 ldr r0, [r7, #4]
800a28a: f000 f9d1 bl 800a630 <USBD_CtlError>
err++;
800a28e: 7afb ldrb r3, [r7, #11]
800a290: 3301 adds r3, #1
800a292: 72fb strb r3, [r7, #11]
break;
800a294: bf00 nop
}
if (err != 0U)
800a296: 7afb ldrb r3, [r7, #11]
800a298: 2b00 cmp r3, #0
800a29a: d11c bne.n 800a2d6 <USBD_GetDescriptor+0x2c6>
{
return;
}
else
{
if ((len != 0U) && (req->wLength != 0U))
800a29c: 893b ldrh r3, [r7, #8]
800a29e: 2b00 cmp r3, #0
800a2a0: d011 beq.n 800a2c6 <USBD_GetDescriptor+0x2b6>
800a2a2: 683b ldr r3, [r7, #0]
800a2a4: 88db ldrh r3, [r3, #6]
800a2a6: 2b00 cmp r3, #0
800a2a8: d00d beq.n 800a2c6 <USBD_GetDescriptor+0x2b6>
{
len = MIN(len, req->wLength);
800a2aa: 683b ldr r3, [r7, #0]
800a2ac: 88da ldrh r2, [r3, #6]
800a2ae: 893b ldrh r3, [r7, #8]
800a2b0: 4293 cmp r3, r2
800a2b2: bf28 it cs
800a2b4: 4613 movcs r3, r2
800a2b6: b29b uxth r3, r3
800a2b8: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
800a2ba: 893b ldrh r3, [r7, #8]
800a2bc: 461a mov r2, r3
800a2be: 68f9 ldr r1, [r7, #12]
800a2c0: 6878 ldr r0, [r7, #4]
800a2c2: f000 fa1f bl 800a704 <USBD_CtlSendData>
}
if (req->wLength == 0U)
800a2c6: 683b ldr r3, [r7, #0]
800a2c8: 88db ldrh r3, [r3, #6]
800a2ca: 2b00 cmp r3, #0
800a2cc: d104 bne.n 800a2d8 <USBD_GetDescriptor+0x2c8>
{
(void)USBD_CtlSendStatus(pdev);
800a2ce: 6878 ldr r0, [r7, #4]
800a2d0: f000 fa76 bl 800a7c0 <USBD_CtlSendStatus>
800a2d4: e000 b.n 800a2d8 <USBD_GetDescriptor+0x2c8>
return;
800a2d6: bf00 nop
}
}
}
800a2d8: 3710 adds r7, #16
800a2da: 46bd mov sp, r7
800a2dc: bd80 pop {r7, pc}
800a2de: bf00 nop
0800a2e0 <USBD_SetAddress>:
* @param req: usb request
* @retval status
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a2e0: b580 push {r7, lr}
800a2e2: b084 sub sp, #16
800a2e4: af00 add r7, sp, #0
800a2e6: 6078 str r0, [r7, #4]
800a2e8: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
800a2ea: 683b ldr r3, [r7, #0]
800a2ec: 889b ldrh r3, [r3, #4]
800a2ee: 2b00 cmp r3, #0
800a2f0: d130 bne.n 800a354 <USBD_SetAddress+0x74>
800a2f2: 683b ldr r3, [r7, #0]
800a2f4: 88db ldrh r3, [r3, #6]
800a2f6: 2b00 cmp r3, #0
800a2f8: d12c bne.n 800a354 <USBD_SetAddress+0x74>
800a2fa: 683b ldr r3, [r7, #0]
800a2fc: 885b ldrh r3, [r3, #2]
800a2fe: 2b7f cmp r3, #127 @ 0x7f
800a300: d828 bhi.n 800a354 <USBD_SetAddress+0x74>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
800a302: 683b ldr r3, [r7, #0]
800a304: 885b ldrh r3, [r3, #2]
800a306: b2db uxtb r3, r3
800a308: f003 037f and.w r3, r3, #127 @ 0x7f
800a30c: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a30e: 687b ldr r3, [r7, #4]
800a310: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a314: 2b03 cmp r3, #3
800a316: d104 bne.n 800a322 <USBD_SetAddress+0x42>
{
USBD_CtlError(pdev, req);
800a318: 6839 ldr r1, [r7, #0]
800a31a: 6878 ldr r0, [r7, #4]
800a31c: f000 f988 bl 800a630 <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a320: e01d b.n 800a35e <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_address = dev_addr;
800a322: 687b ldr r3, [r7, #4]
800a324: 7bfa ldrb r2, [r7, #15]
800a326: f883 229e strb.w r2, [r3, #670] @ 0x29e
USBD_LL_SetUSBAddress(pdev, dev_addr);
800a32a: 7bfb ldrb r3, [r7, #15]
800a32c: 4619 mov r1, r3
800a32e: 6878 ldr r0, [r7, #4]
800a330: f000 fec1 bl 800b0b6 <USBD_LL_SetUSBAddress>
USBD_CtlSendStatus(pdev);
800a334: 6878 ldr r0, [r7, #4]
800a336: f000 fa43 bl 800a7c0 <USBD_CtlSendStatus>
if (dev_addr != 0U)
800a33a: 7bfb ldrb r3, [r7, #15]
800a33c: 2b00 cmp r3, #0
800a33e: d004 beq.n 800a34a <USBD_SetAddress+0x6a>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800a340: 687b ldr r3, [r7, #4]
800a342: 2202 movs r2, #2
800a344: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a348: e009 b.n 800a35e <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
800a34a: 687b ldr r3, [r7, #4]
800a34c: 2201 movs r2, #1
800a34e: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a352: e004 b.n 800a35e <USBD_SetAddress+0x7e>
}
}
}
else
{
USBD_CtlError(pdev, req);
800a354: 6839 ldr r1, [r7, #0]
800a356: 6878 ldr r0, [r7, #4]
800a358: f000 f96a bl 800a630 <USBD_CtlError>
}
}
800a35c: bf00 nop
800a35e: bf00 nop
800a360: 3710 adds r7, #16
800a362: 46bd mov sp, r7
800a364: bd80 pop {r7, pc}
...
0800a368 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a368: b580 push {r7, lr}
800a36a: b082 sub sp, #8
800a36c: af00 add r7, sp, #0
800a36e: 6078 str r0, [r7, #4]
800a370: 6039 str r1, [r7, #0]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
800a372: 683b ldr r3, [r7, #0]
800a374: 885b ldrh r3, [r3, #2]
800a376: b2da uxtb r2, r3
800a378: 4b41 ldr r3, [pc, #260] @ (800a480 <USBD_SetConfig+0x118>)
800a37a: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
800a37c: 4b40 ldr r3, [pc, #256] @ (800a480 <USBD_SetConfig+0x118>)
800a37e: 781b ldrb r3, [r3, #0]
800a380: 2b01 cmp r3, #1
800a382: d904 bls.n 800a38e <USBD_SetConfig+0x26>
{
USBD_CtlError(pdev, req);
800a384: 6839 ldr r1, [r7, #0]
800a386: 6878 ldr r0, [r7, #4]
800a388: f000 f952 bl 800a630 <USBD_CtlError>
800a38c: e075 b.n 800a47a <USBD_SetConfig+0x112>
}
else
{
switch (pdev->dev_state)
800a38e: 687b ldr r3, [r7, #4]
800a390: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a394: 2b02 cmp r3, #2
800a396: d002 beq.n 800a39e <USBD_SetConfig+0x36>
800a398: 2b03 cmp r3, #3
800a39a: d023 beq.n 800a3e4 <USBD_SetConfig+0x7c>
800a39c: e062 b.n 800a464 <USBD_SetConfig+0xfc>
{
case USBD_STATE_ADDRESSED:
if (cfgidx)
800a39e: 4b38 ldr r3, [pc, #224] @ (800a480 <USBD_SetConfig+0x118>)
800a3a0: 781b ldrb r3, [r3, #0]
800a3a2: 2b00 cmp r3, #0
800a3a4: d01a beq.n 800a3dc <USBD_SetConfig+0x74>
{
pdev->dev_config = cfgidx;
800a3a6: 4b36 ldr r3, [pc, #216] @ (800a480 <USBD_SetConfig+0x118>)
800a3a8: 781b ldrb r3, [r3, #0]
800a3aa: 461a mov r2, r3
800a3ac: 687b ldr r3, [r7, #4]
800a3ae: 605a str r2, [r3, #4]
pdev->dev_state = USBD_STATE_CONFIGURED;
800a3b0: 687b ldr r3, [r7, #4]
800a3b2: 2203 movs r2, #3
800a3b4: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800a3b8: 4b31 ldr r3, [pc, #196] @ (800a480 <USBD_SetConfig+0x118>)
800a3ba: 781b ldrb r3, [r3, #0]
800a3bc: 4619 mov r1, r3
800a3be: 6878 ldr r0, [r7, #4]
800a3c0: f7ff f9e7 bl 8009792 <USBD_SetClassConfig>
800a3c4: 4603 mov r3, r0
800a3c6: 2b02 cmp r3, #2
800a3c8: d104 bne.n 800a3d4 <USBD_SetConfig+0x6c>
{
USBD_CtlError(pdev, req);
800a3ca: 6839 ldr r1, [r7, #0]
800a3cc: 6878 ldr r0, [r7, #4]
800a3ce: f000 f92f bl 800a630 <USBD_CtlError>
return;
800a3d2: e052 b.n 800a47a <USBD_SetConfig+0x112>
}
USBD_CtlSendStatus(pdev);
800a3d4: 6878 ldr r0, [r7, #4]
800a3d6: f000 f9f3 bl 800a7c0 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800a3da: e04e b.n 800a47a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800a3dc: 6878 ldr r0, [r7, #4]
800a3de: f000 f9ef bl 800a7c0 <USBD_CtlSendStatus>
break;
800a3e2: e04a b.n 800a47a <USBD_SetConfig+0x112>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
800a3e4: 4b26 ldr r3, [pc, #152] @ (800a480 <USBD_SetConfig+0x118>)
800a3e6: 781b ldrb r3, [r3, #0]
800a3e8: 2b00 cmp r3, #0
800a3ea: d112 bne.n 800a412 <USBD_SetConfig+0xaa>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800a3ec: 687b ldr r3, [r7, #4]
800a3ee: 2202 movs r2, #2
800a3f0: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
800a3f4: 4b22 ldr r3, [pc, #136] @ (800a480 <USBD_SetConfig+0x118>)
800a3f6: 781b ldrb r3, [r3, #0]
800a3f8: 461a mov r2, r3
800a3fa: 687b ldr r3, [r7, #4]
800a3fc: 605a str r2, [r3, #4]
USBD_ClrClassConfig(pdev, cfgidx);
800a3fe: 4b20 ldr r3, [pc, #128] @ (800a480 <USBD_SetConfig+0x118>)
800a400: 781b ldrb r3, [r3, #0]
800a402: 4619 mov r1, r3
800a404: 6878 ldr r0, [r7, #4]
800a406: f7ff f9e3 bl 80097d0 <USBD_ClrClassConfig>
USBD_CtlSendStatus(pdev);
800a40a: 6878 ldr r0, [r7, #4]
800a40c: f000 f9d8 bl 800a7c0 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800a410: e033 b.n 800a47a <USBD_SetConfig+0x112>
else if (cfgidx != pdev->dev_config)
800a412: 4b1b ldr r3, [pc, #108] @ (800a480 <USBD_SetConfig+0x118>)
800a414: 781b ldrb r3, [r3, #0]
800a416: 461a mov r2, r3
800a418: 687b ldr r3, [r7, #4]
800a41a: 685b ldr r3, [r3, #4]
800a41c: 429a cmp r2, r3
800a41e: d01d beq.n 800a45c <USBD_SetConfig+0xf4>
USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
800a420: 687b ldr r3, [r7, #4]
800a422: 685b ldr r3, [r3, #4]
800a424: b2db uxtb r3, r3
800a426: 4619 mov r1, r3
800a428: 6878 ldr r0, [r7, #4]
800a42a: f7ff f9d1 bl 80097d0 <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
800a42e: 4b14 ldr r3, [pc, #80] @ (800a480 <USBD_SetConfig+0x118>)
800a430: 781b ldrb r3, [r3, #0]
800a432: 461a mov r2, r3
800a434: 687b ldr r3, [r7, #4]
800a436: 605a str r2, [r3, #4]
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800a438: 4b11 ldr r3, [pc, #68] @ (800a480 <USBD_SetConfig+0x118>)
800a43a: 781b ldrb r3, [r3, #0]
800a43c: 4619 mov r1, r3
800a43e: 6878 ldr r0, [r7, #4]
800a440: f7ff f9a7 bl 8009792 <USBD_SetClassConfig>
800a444: 4603 mov r3, r0
800a446: 2b02 cmp r3, #2
800a448: d104 bne.n 800a454 <USBD_SetConfig+0xec>
USBD_CtlError(pdev, req);
800a44a: 6839 ldr r1, [r7, #0]
800a44c: 6878 ldr r0, [r7, #4]
800a44e: f000 f8ef bl 800a630 <USBD_CtlError>
return;
800a452: e012 b.n 800a47a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800a454: 6878 ldr r0, [r7, #4]
800a456: f000 f9b3 bl 800a7c0 <USBD_CtlSendStatus>
break;
800a45a: e00e b.n 800a47a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800a45c: 6878 ldr r0, [r7, #4]
800a45e: f000 f9af bl 800a7c0 <USBD_CtlSendStatus>
break;
800a462: e00a b.n 800a47a <USBD_SetConfig+0x112>
default:
USBD_CtlError(pdev, req);
800a464: 6839 ldr r1, [r7, #0]
800a466: 6878 ldr r0, [r7, #4]
800a468: f000 f8e2 bl 800a630 <USBD_CtlError>
USBD_ClrClassConfig(pdev, cfgidx);
800a46c: 4b04 ldr r3, [pc, #16] @ (800a480 <USBD_SetConfig+0x118>)
800a46e: 781b ldrb r3, [r3, #0]
800a470: 4619 mov r1, r3
800a472: 6878 ldr r0, [r7, #4]
800a474: f7ff f9ac bl 80097d0 <USBD_ClrClassConfig>
break;
800a478: bf00 nop
}
}
}
800a47a: 3708 adds r7, #8
800a47c: 46bd mov sp, r7
800a47e: bd80 pop {r7, pc}
800a480: 20000410 .word 0x20000410
0800a484 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a484: b580 push {r7, lr}
800a486: b082 sub sp, #8
800a488: af00 add r7, sp, #0
800a48a: 6078 str r0, [r7, #4]
800a48c: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
800a48e: 683b ldr r3, [r7, #0]
800a490: 88db ldrh r3, [r3, #6]
800a492: 2b01 cmp r3, #1
800a494: d004 beq.n 800a4a0 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
800a496: 6839 ldr r1, [r7, #0]
800a498: 6878 ldr r0, [r7, #4]
800a49a: f000 f8c9 bl 800a630 <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
800a49e: e022 b.n 800a4e6 <USBD_GetConfig+0x62>
switch (pdev->dev_state)
800a4a0: 687b ldr r3, [r7, #4]
800a4a2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a4a6: 2b02 cmp r3, #2
800a4a8: dc02 bgt.n 800a4b0 <USBD_GetConfig+0x2c>
800a4aa: 2b00 cmp r3, #0
800a4ac: dc03 bgt.n 800a4b6 <USBD_GetConfig+0x32>
800a4ae: e015 b.n 800a4dc <USBD_GetConfig+0x58>
800a4b0: 2b03 cmp r3, #3
800a4b2: d00b beq.n 800a4cc <USBD_GetConfig+0x48>
800a4b4: e012 b.n 800a4dc <USBD_GetConfig+0x58>
pdev->dev_default_config = 0U;
800a4b6: 687b ldr r3, [r7, #4]
800a4b8: 2200 movs r2, #0
800a4ba: 609a str r2, [r3, #8]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
800a4bc: 687b ldr r3, [r7, #4]
800a4be: 3308 adds r3, #8
800a4c0: 2201 movs r2, #1
800a4c2: 4619 mov r1, r3
800a4c4: 6878 ldr r0, [r7, #4]
800a4c6: f000 f91d bl 800a704 <USBD_CtlSendData>
break;
800a4ca: e00c b.n 800a4e6 <USBD_GetConfig+0x62>
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
800a4cc: 687b ldr r3, [r7, #4]
800a4ce: 3304 adds r3, #4
800a4d0: 2201 movs r2, #1
800a4d2: 4619 mov r1, r3
800a4d4: 6878 ldr r0, [r7, #4]
800a4d6: f000 f915 bl 800a704 <USBD_CtlSendData>
break;
800a4da: e004 b.n 800a4e6 <USBD_GetConfig+0x62>
USBD_CtlError(pdev, req);
800a4dc: 6839 ldr r1, [r7, #0]
800a4de: 6878 ldr r0, [r7, #4]
800a4e0: f000 f8a6 bl 800a630 <USBD_CtlError>
break;
800a4e4: bf00 nop
}
800a4e6: bf00 nop
800a4e8: 3708 adds r7, #8
800a4ea: 46bd mov sp, r7
800a4ec: bd80 pop {r7, pc}
0800a4ee <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a4ee: b580 push {r7, lr}
800a4f0: b082 sub sp, #8
800a4f2: af00 add r7, sp, #0
800a4f4: 6078 str r0, [r7, #4]
800a4f6: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800a4f8: 687b ldr r3, [r7, #4]
800a4fa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a4fe: 3b01 subs r3, #1
800a500: 2b02 cmp r3, #2
800a502: d81e bhi.n 800a542 <USBD_GetStatus+0x54>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
800a504: 683b ldr r3, [r7, #0]
800a506: 88db ldrh r3, [r3, #6]
800a508: 2b02 cmp r3, #2
800a50a: d004 beq.n 800a516 <USBD_GetStatus+0x28>
{
USBD_CtlError(pdev, req);
800a50c: 6839 ldr r1, [r7, #0]
800a50e: 6878 ldr r0, [r7, #4]
800a510: f000 f88e bl 800a630 <USBD_CtlError>
break;
800a514: e01a b.n 800a54c <USBD_GetStatus+0x5e>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
800a516: 687b ldr r3, [r7, #4]
800a518: 2201 movs r2, #1
800a51a: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif
if (pdev->dev_remote_wakeup)
800a51c: 687b ldr r3, [r7, #4]
800a51e: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
800a522: 2b00 cmp r3, #0
800a524: d005 beq.n 800a532 <USBD_GetStatus+0x44>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
800a526: 687b ldr r3, [r7, #4]
800a528: 68db ldr r3, [r3, #12]
800a52a: f043 0202 orr.w r2, r3, #2
800a52e: 687b ldr r3, [r7, #4]
800a530: 60da str r2, [r3, #12]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
800a532: 687b ldr r3, [r7, #4]
800a534: 330c adds r3, #12
800a536: 2202 movs r2, #2
800a538: 4619 mov r1, r3
800a53a: 6878 ldr r0, [r7, #4]
800a53c: f000 f8e2 bl 800a704 <USBD_CtlSendData>
break;
800a540: e004 b.n 800a54c <USBD_GetStatus+0x5e>
default:
USBD_CtlError(pdev, req);
800a542: 6839 ldr r1, [r7, #0]
800a544: 6878 ldr r0, [r7, #4]
800a546: f000 f873 bl 800a630 <USBD_CtlError>
break;
800a54a: bf00 nop
}
}
800a54c: bf00 nop
800a54e: 3708 adds r7, #8
800a550: 46bd mov sp, r7
800a552: bd80 pop {r7, pc}
0800a554 <USBD_SetFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a554: b580 push {r7, lr}
800a556: b082 sub sp, #8
800a558: af00 add r7, sp, #0
800a55a: 6078 str r0, [r7, #4]
800a55c: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800a55e: 683b ldr r3, [r7, #0]
800a560: 885b ldrh r3, [r3, #2]
800a562: 2b01 cmp r3, #1
800a564: d106 bne.n 800a574 <USBD_SetFeature+0x20>
{
pdev->dev_remote_wakeup = 1U;
800a566: 687b ldr r3, [r7, #4]
800a568: 2201 movs r2, #1
800a56a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800a56e: 6878 ldr r0, [r7, #4]
800a570: f000 f926 bl 800a7c0 <USBD_CtlSendStatus>
}
}
800a574: bf00 nop
800a576: 3708 adds r7, #8
800a578: 46bd mov sp, r7
800a57a: bd80 pop {r7, pc}
0800a57c <USBD_ClrFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a57c: b580 push {r7, lr}
800a57e: b082 sub sp, #8
800a580: af00 add r7, sp, #0
800a582: 6078 str r0, [r7, #4]
800a584: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800a586: 687b ldr r3, [r7, #4]
800a588: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a58c: 3b01 subs r3, #1
800a58e: 2b02 cmp r3, #2
800a590: d80b bhi.n 800a5aa <USBD_ClrFeature+0x2e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800a592: 683b ldr r3, [r7, #0]
800a594: 885b ldrh r3, [r3, #2]
800a596: 2b01 cmp r3, #1
800a598: d10c bne.n 800a5b4 <USBD_ClrFeature+0x38>
{
pdev->dev_remote_wakeup = 0U;
800a59a: 687b ldr r3, [r7, #4]
800a59c: 2200 movs r2, #0
800a59e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800a5a2: 6878 ldr r0, [r7, #4]
800a5a4: f000 f90c bl 800a7c0 <USBD_CtlSendStatus>
}
break;
800a5a8: e004 b.n 800a5b4 <USBD_ClrFeature+0x38>
default:
USBD_CtlError(pdev, req);
800a5aa: 6839 ldr r1, [r7, #0]
800a5ac: 6878 ldr r0, [r7, #4]
800a5ae: f000 f83f bl 800a630 <USBD_CtlError>
break;
800a5b2: e000 b.n 800a5b6 <USBD_ClrFeature+0x3a>
break;
800a5b4: bf00 nop
}
}
800a5b6: bf00 nop
800a5b8: 3708 adds r7, #8
800a5ba: 46bd mov sp, r7
800a5bc: bd80 pop {r7, pc}
0800a5be <USBD_ParseSetupRequest>:
* @param req: usb request
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
800a5be: b480 push {r7}
800a5c0: b083 sub sp, #12
800a5c2: af00 add r7, sp, #0
800a5c4: 6078 str r0, [r7, #4]
800a5c6: 6039 str r1, [r7, #0]
req->bmRequest = *(uint8_t *)(pdata);
800a5c8: 683b ldr r3, [r7, #0]
800a5ca: 781a ldrb r2, [r3, #0]
800a5cc: 687b ldr r3, [r7, #4]
800a5ce: 701a strb r2, [r3, #0]
req->bRequest = *(uint8_t *)(pdata + 1U);
800a5d0: 683b ldr r3, [r7, #0]
800a5d2: 785a ldrb r2, [r3, #1]
800a5d4: 687b ldr r3, [r7, #4]
800a5d6: 705a strb r2, [r3, #1]
req->wValue = SWAPBYTE(pdata + 2U);
800a5d8: 683b ldr r3, [r7, #0]
800a5da: 3302 adds r3, #2
800a5dc: 781b ldrb r3, [r3, #0]
800a5de: 461a mov r2, r3
800a5e0: 683b ldr r3, [r7, #0]
800a5e2: 3303 adds r3, #3
800a5e4: 781b ldrb r3, [r3, #0]
800a5e6: 021b lsls r3, r3, #8
800a5e8: b29b uxth r3, r3
800a5ea: 4413 add r3, r2
800a5ec: b29a uxth r2, r3
800a5ee: 687b ldr r3, [r7, #4]
800a5f0: 805a strh r2, [r3, #2]
req->wIndex = SWAPBYTE(pdata + 4U);
800a5f2: 683b ldr r3, [r7, #0]
800a5f4: 3304 adds r3, #4
800a5f6: 781b ldrb r3, [r3, #0]
800a5f8: 461a mov r2, r3
800a5fa: 683b ldr r3, [r7, #0]
800a5fc: 3305 adds r3, #5
800a5fe: 781b ldrb r3, [r3, #0]
800a600: 021b lsls r3, r3, #8
800a602: b29b uxth r3, r3
800a604: 4413 add r3, r2
800a606: b29a uxth r2, r3
800a608: 687b ldr r3, [r7, #4]
800a60a: 809a strh r2, [r3, #4]
req->wLength = SWAPBYTE(pdata + 6U);
800a60c: 683b ldr r3, [r7, #0]
800a60e: 3306 adds r3, #6
800a610: 781b ldrb r3, [r3, #0]
800a612: 461a mov r2, r3
800a614: 683b ldr r3, [r7, #0]
800a616: 3307 adds r3, #7
800a618: 781b ldrb r3, [r3, #0]
800a61a: 021b lsls r3, r3, #8
800a61c: b29b uxth r3, r3
800a61e: 4413 add r3, r2
800a620: b29a uxth r2, r3
800a622: 687b ldr r3, [r7, #4]
800a624: 80da strh r2, [r3, #6]
}
800a626: bf00 nop
800a628: 370c adds r7, #12
800a62a: 46bd mov sp, r7
800a62c: bc80 pop {r7}
800a62e: 4770 bx lr
0800a630 <USBD_CtlError>:
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a630: b580 push {r7, lr}
800a632: b082 sub sp, #8
800a634: af00 add r7, sp, #0
800a636: 6078 str r0, [r7, #4]
800a638: 6039 str r1, [r7, #0]
USBD_LL_StallEP(pdev, 0x80U);
800a63a: 2180 movs r1, #128 @ 0x80
800a63c: 6878 ldr r0, [r7, #4]
800a63e: f000 fcd1 bl 800afe4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0U);
800a642: 2100 movs r1, #0
800a644: 6878 ldr r0, [r7, #4]
800a646: f000 fccd bl 800afe4 <USBD_LL_StallEP>
}
800a64a: bf00 nop
800a64c: 3708 adds r7, #8
800a64e: 46bd mov sp, r7
800a650: bd80 pop {r7, pc}
0800a652 <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
800a652: b580 push {r7, lr}
800a654: b086 sub sp, #24
800a656: af00 add r7, sp, #0
800a658: 60f8 str r0, [r7, #12]
800a65a: 60b9 str r1, [r7, #8]
800a65c: 607a str r2, [r7, #4]
uint8_t idx = 0U;
800a65e: 2300 movs r3, #0
800a660: 75fb strb r3, [r7, #23]
if (desc != NULL)
800a662: 68fb ldr r3, [r7, #12]
800a664: 2b00 cmp r3, #0
800a666: d032 beq.n 800a6ce <USBD_GetString+0x7c>
{
*len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
800a668: 68f8 ldr r0, [r7, #12]
800a66a: f000 f834 bl 800a6d6 <USBD_GetLen>
800a66e: 4603 mov r3, r0
800a670: 3301 adds r3, #1
800a672: b29b uxth r3, r3
800a674: 005b lsls r3, r3, #1
800a676: b29a uxth r2, r3
800a678: 687b ldr r3, [r7, #4]
800a67a: 801a strh r2, [r3, #0]
unicode[idx++] = *(uint8_t *)(void *)len;
800a67c: 7dfb ldrb r3, [r7, #23]
800a67e: 1c5a adds r2, r3, #1
800a680: 75fa strb r2, [r7, #23]
800a682: 461a mov r2, r3
800a684: 68bb ldr r3, [r7, #8]
800a686: 4413 add r3, r2
800a688: 687a ldr r2, [r7, #4]
800a68a: 7812 ldrb r2, [r2, #0]
800a68c: 701a strb r2, [r3, #0]
unicode[idx++] = USB_DESC_TYPE_STRING;
800a68e: 7dfb ldrb r3, [r7, #23]
800a690: 1c5a adds r2, r3, #1
800a692: 75fa strb r2, [r7, #23]
800a694: 461a mov r2, r3
800a696: 68bb ldr r3, [r7, #8]
800a698: 4413 add r3, r2
800a69a: 2203 movs r2, #3
800a69c: 701a strb r2, [r3, #0]
while (*desc != '\0')
800a69e: e012 b.n 800a6c6 <USBD_GetString+0x74>
{
unicode[idx++] = *desc++;
800a6a0: 68fb ldr r3, [r7, #12]
800a6a2: 1c5a adds r2, r3, #1
800a6a4: 60fa str r2, [r7, #12]
800a6a6: 7dfa ldrb r2, [r7, #23]
800a6a8: 1c51 adds r1, r2, #1
800a6aa: 75f9 strb r1, [r7, #23]
800a6ac: 4611 mov r1, r2
800a6ae: 68ba ldr r2, [r7, #8]
800a6b0: 440a add r2, r1
800a6b2: 781b ldrb r3, [r3, #0]
800a6b4: 7013 strb r3, [r2, #0]
unicode[idx++] = 0U;
800a6b6: 7dfb ldrb r3, [r7, #23]
800a6b8: 1c5a adds r2, r3, #1
800a6ba: 75fa strb r2, [r7, #23]
800a6bc: 461a mov r2, r3
800a6be: 68bb ldr r3, [r7, #8]
800a6c0: 4413 add r3, r2
800a6c2: 2200 movs r2, #0
800a6c4: 701a strb r2, [r3, #0]
while (*desc != '\0')
800a6c6: 68fb ldr r3, [r7, #12]
800a6c8: 781b ldrb r3, [r3, #0]
800a6ca: 2b00 cmp r3, #0
800a6cc: d1e8 bne.n 800a6a0 <USBD_GetString+0x4e>
}
}
}
800a6ce: bf00 nop
800a6d0: 3718 adds r7, #24
800a6d2: 46bd mov sp, r7
800a6d4: bd80 pop {r7, pc}
0800a6d6 <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
800a6d6: b480 push {r7}
800a6d8: b085 sub sp, #20
800a6da: af00 add r7, sp, #0
800a6dc: 6078 str r0, [r7, #4]
uint8_t len = 0U;
800a6de: 2300 movs r3, #0
800a6e0: 73fb strb r3, [r7, #15]
while (*buf != '\0')
800a6e2: e005 b.n 800a6f0 <USBD_GetLen+0x1a>
{
len++;
800a6e4: 7bfb ldrb r3, [r7, #15]
800a6e6: 3301 adds r3, #1
800a6e8: 73fb strb r3, [r7, #15]
buf++;
800a6ea: 687b ldr r3, [r7, #4]
800a6ec: 3301 adds r3, #1
800a6ee: 607b str r3, [r7, #4]
while (*buf != '\0')
800a6f0: 687b ldr r3, [r7, #4]
800a6f2: 781b ldrb r3, [r3, #0]
800a6f4: 2b00 cmp r3, #0
800a6f6: d1f5 bne.n 800a6e4 <USBD_GetLen+0xe>
}
return len;
800a6f8: 7bfb ldrb r3, [r7, #15]
}
800a6fa: 4618 mov r0, r3
800a6fc: 3714 adds r7, #20
800a6fe: 46bd mov sp, r7
800a700: bc80 pop {r7}
800a702: 4770 bx lr
0800a704 <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a704: b580 push {r7, lr}
800a706: b084 sub sp, #16
800a708: af00 add r7, sp, #0
800a70a: 60f8 str r0, [r7, #12]
800a70c: 60b9 str r1, [r7, #8]
800a70e: 4613 mov r3, r2
800a710: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
800a712: 68fb ldr r3, [r7, #12]
800a714: 2202 movs r2, #2
800a716: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
800a71a: 88fa ldrh r2, [r7, #6]
800a71c: 68fb ldr r3, [r7, #12]
800a71e: 61da str r2, [r3, #28]
pdev->ep_in[0].rem_length = len;
800a720: 88fa ldrh r2, [r7, #6]
800a722: 68fb ldr r3, [r7, #12]
800a724: 621a str r2, [r3, #32]
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800a726: 88fb ldrh r3, [r7, #6]
800a728: 68ba ldr r2, [r7, #8]
800a72a: 2100 movs r1, #0
800a72c: 68f8 ldr r0, [r7, #12]
800a72e: f000 fce1 bl 800b0f4 <USBD_LL_Transmit>
return USBD_OK;
800a732: 2300 movs r3, #0
}
800a734: 4618 mov r0, r3
800a736: 3710 adds r7, #16
800a738: 46bd mov sp, r7
800a73a: bd80 pop {r7, pc}
0800a73c <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a73c: b580 push {r7, lr}
800a73e: b084 sub sp, #16
800a740: af00 add r7, sp, #0
800a742: 60f8 str r0, [r7, #12]
800a744: 60b9 str r1, [r7, #8]
800a746: 4613 mov r3, r2
800a748: 80fb strh r3, [r7, #6]
/* Start the next transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800a74a: 88fb ldrh r3, [r7, #6]
800a74c: 68ba ldr r2, [r7, #8]
800a74e: 2100 movs r1, #0
800a750: 68f8 ldr r0, [r7, #12]
800a752: f000 fccf bl 800b0f4 <USBD_LL_Transmit>
return USBD_OK;
800a756: 2300 movs r3, #0
}
800a758: 4618 mov r0, r3
800a75a: 3710 adds r7, #16
800a75c: 46bd mov sp, r7
800a75e: bd80 pop {r7, pc}
0800a760 <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a760: b580 push {r7, lr}
800a762: b084 sub sp, #16
800a764: af00 add r7, sp, #0
800a766: 60f8 str r0, [r7, #12]
800a768: 60b9 str r1, [r7, #8]
800a76a: 4613 mov r3, r2
800a76c: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
800a76e: 68fb ldr r3, [r7, #12]
800a770: 2203 movs r2, #3
800a772: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_out[0].total_length = len;
800a776: 88fa ldrh r2, [r7, #6]
800a778: 68fb ldr r3, [r7, #12]
800a77a: f8c3 215c str.w r2, [r3, #348] @ 0x15c
pdev->ep_out[0].rem_length = len;
800a77e: 88fa ldrh r2, [r7, #6]
800a780: 68fb ldr r3, [r7, #12]
800a782: f8c3 2160 str.w r2, [r3, #352] @ 0x160
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800a786: 88fb ldrh r3, [r7, #6]
800a788: 68ba ldr r2, [r7, #8]
800a78a: 2100 movs r1, #0
800a78c: 68f8 ldr r0, [r7, #12]
800a78e: f000 fcd4 bl 800b13a <USBD_LL_PrepareReceive>
return USBD_OK;
800a792: 2300 movs r3, #0
}
800a794: 4618 mov r0, r3
800a796: 3710 adds r7, #16
800a798: 46bd mov sp, r7
800a79a: bd80 pop {r7, pc}
0800a79c <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a79c: b580 push {r7, lr}
800a79e: b084 sub sp, #16
800a7a0: af00 add r7, sp, #0
800a7a2: 60f8 str r0, [r7, #12]
800a7a4: 60b9 str r1, [r7, #8]
800a7a6: 4613 mov r3, r2
800a7a8: 80fb strh r3, [r7, #6]
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800a7aa: 88fb ldrh r3, [r7, #6]
800a7ac: 68ba ldr r2, [r7, #8]
800a7ae: 2100 movs r1, #0
800a7b0: 68f8 ldr r0, [r7, #12]
800a7b2: f000 fcc2 bl 800b13a <USBD_LL_PrepareReceive>
return USBD_OK;
800a7b6: 2300 movs r3, #0
}
800a7b8: 4618 mov r0, r3
800a7ba: 3710 adds r7, #16
800a7bc: 46bd mov sp, r7
800a7be: bd80 pop {r7, pc}
0800a7c0 <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
800a7c0: b580 push {r7, lr}
800a7c2: b082 sub sp, #8
800a7c4: af00 add r7, sp, #0
800a7c6: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
800a7c8: 687b ldr r3, [r7, #4]
800a7ca: 2204 movs r2, #4
800a7cc: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
800a7d0: 2300 movs r3, #0
800a7d2: 2200 movs r2, #0
800a7d4: 2100 movs r1, #0
800a7d6: 6878 ldr r0, [r7, #4]
800a7d8: f000 fc8c bl 800b0f4 <USBD_LL_Transmit>
return USBD_OK;
800a7dc: 2300 movs r3, #0
}
800a7de: 4618 mov r0, r3
800a7e0: 3708 adds r7, #8
800a7e2: 46bd mov sp, r7
800a7e4: bd80 pop {r7, pc}
0800a7e6 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
800a7e6: b580 push {r7, lr}
800a7e8: b082 sub sp, #8
800a7ea: af00 add r7, sp, #0
800a7ec: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
800a7ee: 687b ldr r3, [r7, #4]
800a7f0: 2205 movs r2, #5
800a7f2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800a7f6: 2300 movs r3, #0
800a7f8: 2200 movs r2, #0
800a7fa: 2100 movs r1, #0
800a7fc: 6878 ldr r0, [r7, #4]
800a7fe: f000 fc9c bl 800b13a <USBD_LL_PrepareReceive>
return USBD_OK;
800a802: 2300 movs r3, #0
}
800a804: 4618 mov r0, r3
800a806: 3708 adds r7, #8
800a808: 46bd mov sp, r7
800a80a: bd80 pop {r7, pc}
0800a80c <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
800a80c: b580 push {r7, lr}
800a80e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
800a810: 2200 movs r2, #0
800a812: 4912 ldr r1, [pc, #72] @ (800a85c <MX_USB_DEVICE_Init+0x50>)
800a814: 4812 ldr r0, [pc, #72] @ (800a860 <MX_USB_DEVICE_Init+0x54>)
800a816: f7fe ff62 bl 80096de <USBD_Init>
800a81a: 4603 mov r3, r0
800a81c: 2b00 cmp r3, #0
800a81e: d001 beq.n 800a824 <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
800a820: f7f7 f870 bl 8001904 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
800a824: 490f ldr r1, [pc, #60] @ (800a864 <MX_USB_DEVICE_Init+0x58>)
800a826: 480e ldr r0, [pc, #56] @ (800a860 <MX_USB_DEVICE_Init+0x54>)
800a828: f7fe ff84 bl 8009734 <USBD_RegisterClass>
800a82c: 4603 mov r3, r0
800a82e: 2b00 cmp r3, #0
800a830: d001 beq.n 800a836 <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
800a832: f7f7 f867 bl 8001904 <Error_Handler>
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
800a836: 490c ldr r1, [pc, #48] @ (800a868 <MX_USB_DEVICE_Init+0x5c>)
800a838: 4809 ldr r0, [pc, #36] @ (800a860 <MX_USB_DEVICE_Init+0x54>)
800a83a: f7fe feb5 bl 80095a8 <USBD_CDC_RegisterInterface>
800a83e: 4603 mov r3, r0
800a840: 2b00 cmp r3, #0
800a842: d001 beq.n 800a848 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
800a844: f7f7 f85e bl 8001904 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
800a848: 4805 ldr r0, [pc, #20] @ (800a860 <MX_USB_DEVICE_Init+0x54>)
800a84a: f7fe ff8c bl 8009766 <USBD_Start>
800a84e: 4603 mov r3, r0
800a850: 2b00 cmp r3, #0
800a852: d001 beq.n 800a858 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
800a854: f7f7 f856 bl 8001904 <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
800a858: bf00 nop
800a85a: bd80 pop {r7, pc}
800a85c: 20000130 .word 0x20000130
800a860: 20000414 .word 0x20000414
800a864: 2000001c .word 0x2000001c
800a868: 20000120 .word 0x20000120
0800a86c <fifo_push>:
/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
#define RX_FIFO_SZ 256
static uint8_t rx_fifo[RX_FIFO_SZ];
static volatile uint16_t rx_head = 0, rx_tail = 0;
static void fifo_push(const uint8_t* data, uint32_t len) {
800a86c: b480 push {r7}
800a86e: b085 sub sp, #20
800a870: af00 add r7, sp, #0
800a872: 6078 str r0, [r7, #4]
800a874: 6039 str r1, [r7, #0]
while (len--) {
800a876: e01e b.n 800a8b6 <fifo_push+0x4a>
uint16_t next = (rx_head + 1u) & (RX_FIFO_SZ - 1u);
800a878: 4b14 ldr r3, [pc, #80] @ (800a8cc <fifo_push+0x60>)
800a87a: 881b ldrh r3, [r3, #0]
800a87c: b29b uxth r3, r3
800a87e: 3301 adds r3, #1
800a880: b29b uxth r3, r3
800a882: b2db uxtb r3, r3
800a884: 81fb strh r3, [r7, #14]
if (next == (rx_tail & (RX_FIFO_SZ - 1u))) {
800a886: 89fa ldrh r2, [r7, #14]
800a888: 4b11 ldr r3, [pc, #68] @ (800a8d0 <fifo_push+0x64>)
800a88a: 881b ldrh r3, [r3, #0]
800a88c: b29b uxth r3, r3
800a88e: b2db uxtb r3, r3
800a890: 429a cmp r2, r3
800a892: d103 bne.n 800a89c <fifo_push+0x30>
/* overflow — drop byte (or set a flag) */
data++;
800a894: 687b ldr r3, [r7, #4]
800a896: 3301 adds r3, #1
800a898: 607b str r3, [r7, #4]
continue;
800a89a: e00c b.n 800a8b6 <fifo_push+0x4a>
}
rx_fifo[rx_head & (RX_FIFO_SZ - 1u)] = *data++;
800a89c: 687b ldr r3, [r7, #4]
800a89e: 1c5a adds r2, r3, #1
800a8a0: 607a str r2, [r7, #4]
800a8a2: 4a0a ldr r2, [pc, #40] @ (800a8cc <fifo_push+0x60>)
800a8a4: 8812 ldrh r2, [r2, #0]
800a8a6: b292 uxth r2, r2
800a8a8: b2d2 uxtb r2, r2
800a8aa: 7819 ldrb r1, [r3, #0]
800a8ac: 4b09 ldr r3, [pc, #36] @ (800a8d4 <fifo_push+0x68>)
800a8ae: 5499 strb r1, [r3, r2]
rx_head = next;
800a8b0: 4a06 ldr r2, [pc, #24] @ (800a8cc <fifo_push+0x60>)
800a8b2: 89fb ldrh r3, [r7, #14]
800a8b4: 8013 strh r3, [r2, #0]
while (len--) {
800a8b6: 683b ldr r3, [r7, #0]
800a8b8: 1e5a subs r2, r3, #1
800a8ba: 603a str r2, [r7, #0]
800a8bc: 2b00 cmp r3, #0
800a8be: d1db bne.n 800a878 <fifo_push+0xc>
}
}
800a8c0: bf00 nop
800a8c2: bf00 nop
800a8c4: 3714 adds r7, #20
800a8c6: 46bd mov sp, r7
800a8c8: bc80 pop {r7}
800a8ca: 4770 bx lr
800a8cc: 20000fd8 .word 0x20000fd8
800a8d0: 20000fda .word 0x20000fda
800a8d4: 20000ed8 .word 0x20000ed8
0800a8d8 <CDC_Available>:
uint32_t CDC_Available(void) {
800a8d8: b480 push {r7}
800a8da: af00 add r7, sp, #0
return (uint16_t)((rx_head - rx_tail) & (RX_FIFO_SZ - 1u));
800a8dc: 4b06 ldr r3, [pc, #24] @ (800a8f8 <CDC_Available+0x20>)
800a8de: 881b ldrh r3, [r3, #0]
800a8e0: b29a uxth r2, r3
800a8e2: 4b06 ldr r3, [pc, #24] @ (800a8fc <CDC_Available+0x24>)
800a8e4: 881b ldrh r3, [r3, #0]
800a8e6: b29b uxth r3, r3
800a8e8: 1ad3 subs r3, r2, r3
800a8ea: b29b uxth r3, r3
800a8ec: b2db uxtb r3, r3
}
800a8ee: 4618 mov r0, r3
800a8f0: 46bd mov sp, r7
800a8f2: bc80 pop {r7}
800a8f4: 4770 bx lr
800a8f6: bf00 nop
800a8f8: 20000fd8 .word 0x20000fd8
800a8fc: 20000fda .word 0x20000fda
0800a900 <CDC_ReadByte>:
int CDC_ReadByte(void) {
800a900: b480 push {r7}
800a902: b083 sub sp, #12
800a904: af00 add r7, sp, #0
if (rx_tail == rx_head) return -1;
800a906: 4b10 ldr r3, [pc, #64] @ (800a948 <CDC_ReadByte+0x48>)
800a908: 881b ldrh r3, [r3, #0]
800a90a: b29a uxth r2, r3
800a90c: 4b0f ldr r3, [pc, #60] @ (800a94c <CDC_ReadByte+0x4c>)
800a90e: 881b ldrh r3, [r3, #0]
800a910: b29b uxth r3, r3
800a912: 429a cmp r2, r3
800a914: d102 bne.n 800a91c <CDC_ReadByte+0x1c>
800a916: f04f 33ff mov.w r3, #4294967295
800a91a: e010 b.n 800a93e <CDC_ReadByte+0x3e>
int b = rx_fifo[rx_tail & (RX_FIFO_SZ - 1u)];
800a91c: 4b0a ldr r3, [pc, #40] @ (800a948 <CDC_ReadByte+0x48>)
800a91e: 881b ldrh r3, [r3, #0]
800a920: b29b uxth r3, r3
800a922: b2db uxtb r3, r3
800a924: 4a0a ldr r2, [pc, #40] @ (800a950 <CDC_ReadByte+0x50>)
800a926: 5cd3 ldrb r3, [r2, r3]
800a928: 607b str r3, [r7, #4]
rx_tail = (rx_tail + 1u) & (RX_FIFO_SZ - 1u);
800a92a: 4b07 ldr r3, [pc, #28] @ (800a948 <CDC_ReadByte+0x48>)
800a92c: 881b ldrh r3, [r3, #0]
800a92e: b29b uxth r3, r3
800a930: 3301 adds r3, #1
800a932: b29b uxth r3, r3
800a934: b2db uxtb r3, r3
800a936: b29a uxth r2, r3
800a938: 4b03 ldr r3, [pc, #12] @ (800a948 <CDC_ReadByte+0x48>)
800a93a: 801a strh r2, [r3, #0]
return b;
800a93c: 687b ldr r3, [r7, #4]
}
800a93e: 4618 mov r0, r3
800a940: 370c adds r7, #12
800a942: 46bd mov sp, r7
800a944: bc80 pop {r7}
800a946: 4770 bx lr
800a948: 20000fda .word 0x20000fda
800a94c: 20000fd8 .word 0x20000fd8
800a950: 20000ed8 .word 0x20000ed8
0800a954 <CDC_Init_FS>:
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
800a954: b580 push {r7, lr}
800a956: af00 add r7, sp, #0
/* USER CODE BEGIN 3 */
/* Set Application Buffers */
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
800a958: 2200 movs r2, #0
800a95a: 4905 ldr r1, [pc, #20] @ (800a970 <CDC_Init_FS+0x1c>)
800a95c: 4805 ldr r0, [pc, #20] @ (800a974 <CDC_Init_FS+0x20>)
800a95e: f7fe fe39 bl 80095d4 <USBD_CDC_SetTxBuffer>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
800a962: 4905 ldr r1, [pc, #20] @ (800a978 <CDC_Init_FS+0x24>)
800a964: 4803 ldr r0, [pc, #12] @ (800a974 <CDC_Init_FS+0x20>)
800a966: f7fe fe4e bl 8009606 <USBD_CDC_SetRxBuffer>
return (USBD_OK);
800a96a: 2300 movs r3, #0
/* USER CODE END 3 */
}
800a96c: 4618 mov r0, r3
800a96e: bd80 pop {r7, pc}
800a970: 20000ad8 .word 0x20000ad8
800a974: 20000414 .word 0x20000414
800a978: 200006d8 .word 0x200006d8
0800a97c <CDC_DeInit_FS>:
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
800a97c: b480 push {r7}
800a97e: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
800a980: 2300 movs r3, #0
/* USER CODE END 4 */
}
800a982: 4618 mov r0, r3
800a984: 46bd mov sp, r7
800a986: bc80 pop {r7}
800a988: 4770 bx lr
...
0800a98c <CDC_Control_FS>:
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
800a98c: b480 push {r7}
800a98e: b083 sub sp, #12
800a990: af00 add r7, sp, #0
800a992: 4603 mov r3, r0
800a994: 6039 str r1, [r7, #0]
800a996: 71fb strb r3, [r7, #7]
800a998: 4613 mov r3, r2
800a99a: 80bb strh r3, [r7, #4]
/* USER CODE BEGIN 5 */
switch(cmd)
800a99c: 79fb ldrb r3, [r7, #7]
800a99e: 2b23 cmp r3, #35 @ 0x23
800a9a0: d84a bhi.n 800aa38 <CDC_Control_FS+0xac>
800a9a2: a201 add r2, pc, #4 @ (adr r2, 800a9a8 <CDC_Control_FS+0x1c>)
800a9a4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a9a8: 0800aa39 .word 0x0800aa39
800a9ac: 0800aa39 .word 0x0800aa39
800a9b0: 0800aa39 .word 0x0800aa39
800a9b4: 0800aa39 .word 0x0800aa39
800a9b8: 0800aa39 .word 0x0800aa39
800a9bc: 0800aa39 .word 0x0800aa39
800a9c0: 0800aa39 .word 0x0800aa39
800a9c4: 0800aa39 .word 0x0800aa39
800a9c8: 0800aa39 .word 0x0800aa39
800a9cc: 0800aa39 .word 0x0800aa39
800a9d0: 0800aa39 .word 0x0800aa39
800a9d4: 0800aa39 .word 0x0800aa39
800a9d8: 0800aa39 .word 0x0800aa39
800a9dc: 0800aa39 .word 0x0800aa39
800a9e0: 0800aa39 .word 0x0800aa39
800a9e4: 0800aa39 .word 0x0800aa39
800a9e8: 0800aa39 .word 0x0800aa39
800a9ec: 0800aa39 .word 0x0800aa39
800a9f0: 0800aa39 .word 0x0800aa39
800a9f4: 0800aa39 .word 0x0800aa39
800a9f8: 0800aa39 .word 0x0800aa39
800a9fc: 0800aa39 .word 0x0800aa39
800aa00: 0800aa39 .word 0x0800aa39
800aa04: 0800aa39 .word 0x0800aa39
800aa08: 0800aa39 .word 0x0800aa39
800aa0c: 0800aa39 .word 0x0800aa39
800aa10: 0800aa39 .word 0x0800aa39
800aa14: 0800aa39 .word 0x0800aa39
800aa18: 0800aa39 .word 0x0800aa39
800aa1c: 0800aa39 .word 0x0800aa39
800aa20: 0800aa39 .word 0x0800aa39
800aa24: 0800aa39 .word 0x0800aa39
800aa28: 0800aa39 .word 0x0800aa39
800aa2c: 0800aa39 .word 0x0800aa39
800aa30: 0800aa39 .word 0x0800aa39
800aa34: 0800aa39 .word 0x0800aa39
case CDC_SEND_BREAK:
break;
default:
break;
800aa38: bf00 nop
}
return (USBD_OK);
800aa3a: 2300 movs r3, #0
/* USER CODE END 5 */
}
800aa3c: 4618 mov r0, r3
800aa3e: 370c adds r7, #12
800aa40: 46bd mov sp, r7
800aa42: bc80 pop {r7}
800aa44: 4770 bx lr
800aa46: bf00 nop
0800aa48 <CDC_Receive_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
800aa48: b580 push {r7, lr}
800aa4a: b082 sub sp, #8
800aa4c: af00 add r7, sp, #0
800aa4e: 6078 str r0, [r7, #4]
800aa50: 6039 str r1, [r7, #0]
/* USER CODE BEGIN 6 */
if (*Len) fifo_push(Buf, *Len);
800aa52: 683b ldr r3, [r7, #0]
800aa54: 681b ldr r3, [r3, #0]
800aa56: 2b00 cmp r3, #0
800aa58: d005 beq.n 800aa66 <CDC_Receive_FS+0x1e>
800aa5a: 683b ldr r3, [r7, #0]
800aa5c: 681b ldr r3, [r3, #0]
800aa5e: 4619 mov r1, r3
800aa60: 6878 ldr r0, [r7, #4]
800aa62: f7ff ff03 bl 800a86c <fifo_push>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
800aa66: 6879 ldr r1, [r7, #4]
800aa68: 4805 ldr r0, [pc, #20] @ (800aa80 <CDC_Receive_FS+0x38>)
800aa6a: f7fe fdcc bl 8009606 <USBD_CDC_SetRxBuffer>
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
800aa6e: 4804 ldr r0, [pc, #16] @ (800aa80 <CDC_Receive_FS+0x38>)
800aa70: f7fe fe0b bl 800968a <USBD_CDC_ReceivePacket>
return (USBD_OK);
800aa74: 2300 movs r3, #0
/* USER CODE END 6 */
}
800aa76: 4618 mov r0, r3
800aa78: 3708 adds r7, #8
800aa7a: 46bd mov sp, r7
800aa7c: bd80 pop {r7, pc}
800aa7e: bf00 nop
800aa80: 20000414 .word 0x20000414
0800aa84 <CDC_Transmit_FS>:
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
800aa84: b580 push {r7, lr}
800aa86: b084 sub sp, #16
800aa88: af00 add r7, sp, #0
800aa8a: 6078 str r0, [r7, #4]
800aa8c: 460b mov r3, r1
800aa8e: 807b strh r3, [r7, #2]
uint8_t result = USBD_OK;
800aa90: 2300 movs r3, #0
800aa92: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
800aa94: 4b0d ldr r3, [pc, #52] @ (800aacc <CDC_Transmit_FS+0x48>)
800aa96: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800aa9a: 60bb str r3, [r7, #8]
if (hcdc->TxState != 0){
800aa9c: 68bb ldr r3, [r7, #8]
800aa9e: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800aaa2: 2b00 cmp r3, #0
800aaa4: d001 beq.n 800aaaa <CDC_Transmit_FS+0x26>
return USBD_BUSY;
800aaa6: 2301 movs r3, #1
800aaa8: e00b b.n 800aac2 <CDC_Transmit_FS+0x3e>
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
800aaaa: 887b ldrh r3, [r7, #2]
800aaac: 461a mov r2, r3
800aaae: 6879 ldr r1, [r7, #4]
800aab0: 4806 ldr r0, [pc, #24] @ (800aacc <CDC_Transmit_FS+0x48>)
800aab2: f7fe fd8f bl 80095d4 <USBD_CDC_SetTxBuffer>
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
800aab6: 4805 ldr r0, [pc, #20] @ (800aacc <CDC_Transmit_FS+0x48>)
800aab8: f7fe fdb8 bl 800962c <USBD_CDC_TransmitPacket>
800aabc: 4603 mov r3, r0
800aabe: 73fb strb r3, [r7, #15]
/* USER CODE END 7 */
return result;
800aac0: 7bfb ldrb r3, [r7, #15]
}
800aac2: 4618 mov r0, r3
800aac4: 3710 adds r7, #16
800aac6: 46bd mov sp, r7
800aac8: bd80 pop {r7, pc}
800aaca: bf00 nop
800aacc: 20000414 .word 0x20000414
0800aad0 <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aad0: b480 push {r7}
800aad2: b083 sub sp, #12
800aad4: af00 add r7, sp, #0
800aad6: 4603 mov r3, r0
800aad8: 6039 str r1, [r7, #0]
800aada: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
800aadc: 683b ldr r3, [r7, #0]
800aade: 2212 movs r2, #18
800aae0: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
800aae2: 4b03 ldr r3, [pc, #12] @ (800aaf0 <USBD_FS_DeviceDescriptor+0x20>)
}
800aae4: 4618 mov r0, r3
800aae6: 370c adds r7, #12
800aae8: 46bd mov sp, r7
800aaea: bc80 pop {r7}
800aaec: 4770 bx lr
800aaee: bf00 nop
800aaf0: 2000014c .word 0x2000014c
0800aaf4 <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aaf4: b480 push {r7}
800aaf6: b083 sub sp, #12
800aaf8: af00 add r7, sp, #0
800aafa: 4603 mov r3, r0
800aafc: 6039 str r1, [r7, #0]
800aafe: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
800ab00: 683b ldr r3, [r7, #0]
800ab02: 2204 movs r2, #4
800ab04: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
800ab06: 4b03 ldr r3, [pc, #12] @ (800ab14 <USBD_FS_LangIDStrDescriptor+0x20>)
}
800ab08: 4618 mov r0, r3
800ab0a: 370c adds r7, #12
800ab0c: 46bd mov sp, r7
800ab0e: bc80 pop {r7}
800ab10: 4770 bx lr
800ab12: bf00 nop
800ab14: 20000160 .word 0x20000160
0800ab18 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ab18: b580 push {r7, lr}
800ab1a: b082 sub sp, #8
800ab1c: af00 add r7, sp, #0
800ab1e: 4603 mov r3, r0
800ab20: 6039 str r1, [r7, #0]
800ab22: 71fb strb r3, [r7, #7]
if(speed == 0)
800ab24: 79fb ldrb r3, [r7, #7]
800ab26: 2b00 cmp r3, #0
800ab28: d105 bne.n 800ab36 <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800ab2a: 683a ldr r2, [r7, #0]
800ab2c: 4907 ldr r1, [pc, #28] @ (800ab4c <USBD_FS_ProductStrDescriptor+0x34>)
800ab2e: 4808 ldr r0, [pc, #32] @ (800ab50 <USBD_FS_ProductStrDescriptor+0x38>)
800ab30: f7ff fd8f bl 800a652 <USBD_GetString>
800ab34: e004 b.n 800ab40 <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800ab36: 683a ldr r2, [r7, #0]
800ab38: 4904 ldr r1, [pc, #16] @ (800ab4c <USBD_FS_ProductStrDescriptor+0x34>)
800ab3a: 4805 ldr r0, [pc, #20] @ (800ab50 <USBD_FS_ProductStrDescriptor+0x38>)
800ab3c: f7ff fd89 bl 800a652 <USBD_GetString>
}
return USBD_StrDesc;
800ab40: 4b02 ldr r3, [pc, #8] @ (800ab4c <USBD_FS_ProductStrDescriptor+0x34>)
}
800ab42: 4618 mov r0, r3
800ab44: 3708 adds r7, #8
800ab46: 46bd mov sp, r7
800ab48: bd80 pop {r7, pc}
800ab4a: bf00 nop
800ab4c: 20000fdc .word 0x20000fdc
800ab50: 0800bd9c .word 0x0800bd9c
0800ab54 <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ab54: b580 push {r7, lr}
800ab56: b082 sub sp, #8
800ab58: af00 add r7, sp, #0
800ab5a: 4603 mov r3, r0
800ab5c: 6039 str r1, [r7, #0]
800ab5e: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
800ab60: 683a ldr r2, [r7, #0]
800ab62: 4904 ldr r1, [pc, #16] @ (800ab74 <USBD_FS_ManufacturerStrDescriptor+0x20>)
800ab64: 4804 ldr r0, [pc, #16] @ (800ab78 <USBD_FS_ManufacturerStrDescriptor+0x24>)
800ab66: f7ff fd74 bl 800a652 <USBD_GetString>
return USBD_StrDesc;
800ab6a: 4b02 ldr r3, [pc, #8] @ (800ab74 <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
800ab6c: 4618 mov r0, r3
800ab6e: 3708 adds r7, #8
800ab70: 46bd mov sp, r7
800ab72: bd80 pop {r7, pc}
800ab74: 20000fdc .word 0x20000fdc
800ab78: 0800bdb4 .word 0x0800bdb4
0800ab7c <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ab7c: b580 push {r7, lr}
800ab7e: b082 sub sp, #8
800ab80: af00 add r7, sp, #0
800ab82: 4603 mov r3, r0
800ab84: 6039 str r1, [r7, #0]
800ab86: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
800ab88: 683b ldr r3, [r7, #0]
800ab8a: 221a movs r2, #26
800ab8c: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
800ab8e: f000 f843 bl 800ac18 <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
800ab92: 4b02 ldr r3, [pc, #8] @ (800ab9c <USBD_FS_SerialStrDescriptor+0x20>)
}
800ab94: 4618 mov r0, r3
800ab96: 3708 adds r7, #8
800ab98: 46bd mov sp, r7
800ab9a: bd80 pop {r7, pc}
800ab9c: 20000164 .word 0x20000164
0800aba0 <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aba0: b580 push {r7, lr}
800aba2: b082 sub sp, #8
800aba4: af00 add r7, sp, #0
800aba6: 4603 mov r3, r0
800aba8: 6039 str r1, [r7, #0]
800abaa: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
800abac: 79fb ldrb r3, [r7, #7]
800abae: 2b00 cmp r3, #0
800abb0: d105 bne.n 800abbe <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800abb2: 683a ldr r2, [r7, #0]
800abb4: 4907 ldr r1, [pc, #28] @ (800abd4 <USBD_FS_ConfigStrDescriptor+0x34>)
800abb6: 4808 ldr r0, [pc, #32] @ (800abd8 <USBD_FS_ConfigStrDescriptor+0x38>)
800abb8: f7ff fd4b bl 800a652 <USBD_GetString>
800abbc: e004 b.n 800abc8 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800abbe: 683a ldr r2, [r7, #0]
800abc0: 4904 ldr r1, [pc, #16] @ (800abd4 <USBD_FS_ConfigStrDescriptor+0x34>)
800abc2: 4805 ldr r0, [pc, #20] @ (800abd8 <USBD_FS_ConfigStrDescriptor+0x38>)
800abc4: f7ff fd45 bl 800a652 <USBD_GetString>
}
return USBD_StrDesc;
800abc8: 4b02 ldr r3, [pc, #8] @ (800abd4 <USBD_FS_ConfigStrDescriptor+0x34>)
}
800abca: 4618 mov r0, r3
800abcc: 3708 adds r7, #8
800abce: 46bd mov sp, r7
800abd0: bd80 pop {r7, pc}
800abd2: bf00 nop
800abd4: 20000fdc .word 0x20000fdc
800abd8: 0800bdc8 .word 0x0800bdc8
0800abdc <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800abdc: b580 push {r7, lr}
800abde: b082 sub sp, #8
800abe0: af00 add r7, sp, #0
800abe2: 4603 mov r3, r0
800abe4: 6039 str r1, [r7, #0]
800abe6: 71fb strb r3, [r7, #7]
if(speed == 0)
800abe8: 79fb ldrb r3, [r7, #7]
800abea: 2b00 cmp r3, #0
800abec: d105 bne.n 800abfa <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800abee: 683a ldr r2, [r7, #0]
800abf0: 4907 ldr r1, [pc, #28] @ (800ac10 <USBD_FS_InterfaceStrDescriptor+0x34>)
800abf2: 4808 ldr r0, [pc, #32] @ (800ac14 <USBD_FS_InterfaceStrDescriptor+0x38>)
800abf4: f7ff fd2d bl 800a652 <USBD_GetString>
800abf8: e004 b.n 800ac04 <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800abfa: 683a ldr r2, [r7, #0]
800abfc: 4904 ldr r1, [pc, #16] @ (800ac10 <USBD_FS_InterfaceStrDescriptor+0x34>)
800abfe: 4805 ldr r0, [pc, #20] @ (800ac14 <USBD_FS_InterfaceStrDescriptor+0x38>)
800ac00: f7ff fd27 bl 800a652 <USBD_GetString>
}
return USBD_StrDesc;
800ac04: 4b02 ldr r3, [pc, #8] @ (800ac10 <USBD_FS_InterfaceStrDescriptor+0x34>)
}
800ac06: 4618 mov r0, r3
800ac08: 3708 adds r7, #8
800ac0a: 46bd mov sp, r7
800ac0c: bd80 pop {r7, pc}
800ac0e: bf00 nop
800ac10: 20000fdc .word 0x20000fdc
800ac14: 0800bdd4 .word 0x0800bdd4
0800ac18 <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
800ac18: b580 push {r7, lr}
800ac1a: b084 sub sp, #16
800ac1c: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
800ac1e: 4b0f ldr r3, [pc, #60] @ (800ac5c <Get_SerialNum+0x44>)
800ac20: 681b ldr r3, [r3, #0]
800ac22: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
800ac24: 4b0e ldr r3, [pc, #56] @ (800ac60 <Get_SerialNum+0x48>)
800ac26: 681b ldr r3, [r3, #0]
800ac28: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
800ac2a: 4b0e ldr r3, [pc, #56] @ (800ac64 <Get_SerialNum+0x4c>)
800ac2c: 681b ldr r3, [r3, #0]
800ac2e: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
800ac30: 68fa ldr r2, [r7, #12]
800ac32: 687b ldr r3, [r7, #4]
800ac34: 4413 add r3, r2
800ac36: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
800ac38: 68fb ldr r3, [r7, #12]
800ac3a: 2b00 cmp r3, #0
800ac3c: d009 beq.n 800ac52 <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
800ac3e: 2208 movs r2, #8
800ac40: 4909 ldr r1, [pc, #36] @ (800ac68 <Get_SerialNum+0x50>)
800ac42: 68f8 ldr r0, [r7, #12]
800ac44: f000 f814 bl 800ac70 <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
800ac48: 2204 movs r2, #4
800ac4a: 4908 ldr r1, [pc, #32] @ (800ac6c <Get_SerialNum+0x54>)
800ac4c: 68b8 ldr r0, [r7, #8]
800ac4e: f000 f80f bl 800ac70 <IntToUnicode>
}
}
800ac52: bf00 nop
800ac54: 3710 adds r7, #16
800ac56: 46bd mov sp, r7
800ac58: bd80 pop {r7, pc}
800ac5a: bf00 nop
800ac5c: 1ffff7e8 .word 0x1ffff7e8
800ac60: 1ffff7ec .word 0x1ffff7ec
800ac64: 1ffff7f0 .word 0x1ffff7f0
800ac68: 20000166 .word 0x20000166
800ac6c: 20000176 .word 0x20000176
0800ac70 <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
800ac70: b480 push {r7}
800ac72: b087 sub sp, #28
800ac74: af00 add r7, sp, #0
800ac76: 60f8 str r0, [r7, #12]
800ac78: 60b9 str r1, [r7, #8]
800ac7a: 4613 mov r3, r2
800ac7c: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
800ac7e: 2300 movs r3, #0
800ac80: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
800ac82: 2300 movs r3, #0
800ac84: 75fb strb r3, [r7, #23]
800ac86: e027 b.n 800acd8 <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
800ac88: 68fb ldr r3, [r7, #12]
800ac8a: 0f1b lsrs r3, r3, #28
800ac8c: 2b09 cmp r3, #9
800ac8e: d80b bhi.n 800aca8 <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
800ac90: 68fb ldr r3, [r7, #12]
800ac92: 0f1b lsrs r3, r3, #28
800ac94: b2da uxtb r2, r3
800ac96: 7dfb ldrb r3, [r7, #23]
800ac98: 005b lsls r3, r3, #1
800ac9a: 4619 mov r1, r3
800ac9c: 68bb ldr r3, [r7, #8]
800ac9e: 440b add r3, r1
800aca0: 3230 adds r2, #48 @ 0x30
800aca2: b2d2 uxtb r2, r2
800aca4: 701a strb r2, [r3, #0]
800aca6: e00a b.n 800acbe <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
800aca8: 68fb ldr r3, [r7, #12]
800acaa: 0f1b lsrs r3, r3, #28
800acac: b2da uxtb r2, r3
800acae: 7dfb ldrb r3, [r7, #23]
800acb0: 005b lsls r3, r3, #1
800acb2: 4619 mov r1, r3
800acb4: 68bb ldr r3, [r7, #8]
800acb6: 440b add r3, r1
800acb8: 3237 adds r2, #55 @ 0x37
800acba: b2d2 uxtb r2, r2
800acbc: 701a strb r2, [r3, #0]
}
value = value << 4;
800acbe: 68fb ldr r3, [r7, #12]
800acc0: 011b lsls r3, r3, #4
800acc2: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
800acc4: 7dfb ldrb r3, [r7, #23]
800acc6: 005b lsls r3, r3, #1
800acc8: 3301 adds r3, #1
800acca: 68ba ldr r2, [r7, #8]
800accc: 4413 add r3, r2
800acce: 2200 movs r2, #0
800acd0: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
800acd2: 7dfb ldrb r3, [r7, #23]
800acd4: 3301 adds r3, #1
800acd6: 75fb strb r3, [r7, #23]
800acd8: 7dfa ldrb r2, [r7, #23]
800acda: 79fb ldrb r3, [r7, #7]
800acdc: 429a cmp r2, r3
800acde: d3d3 bcc.n 800ac88 <IntToUnicode+0x18>
}
}
800ace0: bf00 nop
800ace2: bf00 nop
800ace4: 371c adds r7, #28
800ace6: 46bd mov sp, r7
800ace8: bc80 pop {r7}
800acea: 4770 bx lr
0800acec <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
800acec: b580 push {r7, lr}
800acee: b084 sub sp, #16
800acf0: af00 add r7, sp, #0
800acf2: 6078 str r0, [r7, #4]
if(pcdHandle->Instance==USB)
800acf4: 687b ldr r3, [r7, #4]
800acf6: 681b ldr r3, [r3, #0]
800acf8: 4a0d ldr r2, [pc, #52] @ (800ad30 <HAL_PCD_MspInit+0x44>)
800acfa: 4293 cmp r3, r2
800acfc: d113 bne.n 800ad26 <HAL_PCD_MspInit+0x3a>
{
/* USER CODE BEGIN USB_MspInit 0 */
/* USER CODE END USB_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
800acfe: 4b0d ldr r3, [pc, #52] @ (800ad34 <HAL_PCD_MspInit+0x48>)
800ad00: 69db ldr r3, [r3, #28]
800ad02: 4a0c ldr r2, [pc, #48] @ (800ad34 <HAL_PCD_MspInit+0x48>)
800ad04: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
800ad08: 61d3 str r3, [r2, #28]
800ad0a: 4b0a ldr r3, [pc, #40] @ (800ad34 <HAL_PCD_MspInit+0x48>)
800ad0c: 69db ldr r3, [r3, #28]
800ad0e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800ad12: 60fb str r3, [r7, #12]
800ad14: 68fb ldr r3, [r7, #12]
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
800ad16: 2200 movs r2, #0
800ad18: 2100 movs r1, #0
800ad1a: 2014 movs r0, #20
800ad1c: f7f7 ff0b bl 8002b36 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
800ad20: 2014 movs r0, #20
800ad22: f7f7 ff24 bl 8002b6e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
800ad26: bf00 nop
800ad28: 3710 adds r7, #16
800ad2a: 46bd mov sp, r7
800ad2c: bd80 pop {r7, pc}
800ad2e: bf00 nop
800ad30: 40005c00 .word 0x40005c00
800ad34: 40021000 .word 0x40021000
0800ad38 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad38: b580 push {r7, lr}
800ad3a: b082 sub sp, #8
800ad3c: af00 add r7, sp, #0
800ad3e: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
800ad40: 687b ldr r3, [r7, #4]
800ad42: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800ad46: 687b ldr r3, [r7, #4]
800ad48: f503 7326 add.w r3, r3, #664 @ 0x298
800ad4c: 4619 mov r1, r3
800ad4e: 4610 mov r0, r2
800ad50: f7fe fd51 bl 80097f6 <USBD_LL_SetupStage>
}
800ad54: bf00 nop
800ad56: 3708 adds r7, #8
800ad58: 46bd mov sp, r7
800ad5a: bd80 pop {r7, pc}
0800ad5c <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad5c: b580 push {r7, lr}
800ad5e: b082 sub sp, #8
800ad60: af00 add r7, sp, #0
800ad62: 6078 str r0, [r7, #4]
800ad64: 460b mov r3, r1
800ad66: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
800ad68: 687b ldr r3, [r7, #4]
800ad6a: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
800ad6e: 78fa ldrb r2, [r7, #3]
800ad70: 6879 ldr r1, [r7, #4]
800ad72: 4613 mov r3, r2
800ad74: 009b lsls r3, r3, #2
800ad76: 4413 add r3, r2
800ad78: 00db lsls r3, r3, #3
800ad7a: 440b add r3, r1
800ad7c: f503 73b2 add.w r3, r3, #356 @ 0x164
800ad80: 681a ldr r2, [r3, #0]
800ad82: 78fb ldrb r3, [r7, #3]
800ad84: 4619 mov r1, r3
800ad86: f7fe fd83 bl 8009890 <USBD_LL_DataOutStage>
}
800ad8a: bf00 nop
800ad8c: 3708 adds r7, #8
800ad8e: 46bd mov sp, r7
800ad90: bd80 pop {r7, pc}
0800ad92 <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad92: b580 push {r7, lr}
800ad94: b082 sub sp, #8
800ad96: af00 add r7, sp, #0
800ad98: 6078 str r0, [r7, #4]
800ad9a: 460b mov r3, r1
800ad9c: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
800ad9e: 687b ldr r3, [r7, #4]
800ada0: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
800ada4: 78fa ldrb r2, [r7, #3]
800ada6: 6879 ldr r1, [r7, #4]
800ada8: 4613 mov r3, r2
800adaa: 009b lsls r3, r3, #2
800adac: 4413 add r3, r2
800adae: 00db lsls r3, r3, #3
800adb0: 440b add r3, r1
800adb2: 3324 adds r3, #36 @ 0x24
800adb4: 681a ldr r2, [r3, #0]
800adb6: 78fb ldrb r3, [r7, #3]
800adb8: 4619 mov r1, r3
800adba: f7fe fdda bl 8009972 <USBD_LL_DataInStage>
}
800adbe: bf00 nop
800adc0: 3708 adds r7, #8
800adc2: 46bd mov sp, r7
800adc4: bd80 pop {r7, pc}
0800adc6 <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800adc6: b580 push {r7, lr}
800adc8: b082 sub sp, #8
800adca: af00 add r7, sp, #0
800adcc: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
800adce: 687b ldr r3, [r7, #4]
800add0: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800add4: 4618 mov r0, r3
800add6: f7fe feea bl 8009bae <USBD_LL_SOF>
}
800adda: bf00 nop
800addc: 3708 adds r7, #8
800adde: 46bd mov sp, r7
800ade0: bd80 pop {r7, pc}
0800ade2 <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ade2: b580 push {r7, lr}
800ade4: b084 sub sp, #16
800ade6: af00 add r7, sp, #0
800ade8: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
800adea: 2301 movs r3, #1
800adec: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
800adee: 687b ldr r3, [r7, #4]
800adf0: 799b ldrb r3, [r3, #6]
800adf2: 2b02 cmp r3, #2
800adf4: d001 beq.n 800adfa <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
800adf6: f7f6 fd85 bl 8001904 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
800adfa: 687b ldr r3, [r7, #4]
800adfc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ae00: 7bfa ldrb r2, [r7, #15]
800ae02: 4611 mov r1, r2
800ae04: 4618 mov r0, r3
800ae06: f7fe fe9a bl 8009b3e <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
800ae0a: 687b ldr r3, [r7, #4]
800ae0c: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ae10: 4618 mov r0, r3
800ae12: f7fe fe53 bl 8009abc <USBD_LL_Reset>
}
800ae16: bf00 nop
800ae18: 3710 adds r7, #16
800ae1a: 46bd mov sp, r7
800ae1c: bd80 pop {r7, pc}
...
0800ae20 <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ae20: b580 push {r7, lr}
800ae22: b082 sub sp, #8
800ae24: af00 add r7, sp, #0
800ae26: 6078 str r0, [r7, #4]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
800ae28: 687b ldr r3, [r7, #4]
800ae2a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ae2e: 4618 mov r0, r3
800ae30: f7fe fe94 bl 8009b5c <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
800ae34: 687b ldr r3, [r7, #4]
800ae36: 7a9b ldrb r3, [r3, #10]
800ae38: 2b00 cmp r3, #0
800ae3a: d005 beq.n 800ae48 <HAL_PCD_SuspendCallback+0x28>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800ae3c: 4b04 ldr r3, [pc, #16] @ (800ae50 <HAL_PCD_SuspendCallback+0x30>)
800ae3e: 691b ldr r3, [r3, #16]
800ae40: 4a03 ldr r2, [pc, #12] @ (800ae50 <HAL_PCD_SuspendCallback+0x30>)
800ae42: f043 0306 orr.w r3, r3, #6
800ae46: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
800ae48: bf00 nop
800ae4a: 3708 adds r7, #8
800ae4c: 46bd mov sp, r7
800ae4e: bd80 pop {r7, pc}
800ae50: e000ed00 .word 0xe000ed00
0800ae54 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ae54: b580 push {r7, lr}
800ae56: b082 sub sp, #8
800ae58: af00 add r7, sp, #0
800ae5a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
800ae5c: 687b ldr r3, [r7, #4]
800ae5e: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ae62: 4618 mov r0, r3
800ae64: f7fe fe8e bl 8009b84 <USBD_LL_Resume>
}
800ae68: bf00 nop
800ae6a: 3708 adds r7, #8
800ae6c: 46bd mov sp, r7
800ae6e: bd80 pop {r7, pc}
0800ae70 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
800ae70: b580 push {r7, lr}
800ae72: b082 sub sp, #8
800ae74: af00 add r7, sp, #0
800ae76: 6078 str r0, [r7, #4]
/* Init USB Ip. */
/* Link the driver to the stack. */
hpcd_USB_FS.pData = pdev;
800ae78: 4a28 ldr r2, [pc, #160] @ (800af1c <USBD_LL_Init+0xac>)
800ae7a: 687b ldr r3, [r7, #4]
800ae7c: f8c2 32d4 str.w r3, [r2, #724] @ 0x2d4
pdev->pData = &hpcd_USB_FS;
800ae80: 687b ldr r3, [r7, #4]
800ae82: 4a26 ldr r2, [pc, #152] @ (800af1c <USBD_LL_Init+0xac>)
800ae84: f8c3 22c0 str.w r2, [r3, #704] @ 0x2c0
hpcd_USB_FS.Instance = USB;
800ae88: 4b24 ldr r3, [pc, #144] @ (800af1c <USBD_LL_Init+0xac>)
800ae8a: 4a25 ldr r2, [pc, #148] @ (800af20 <USBD_LL_Init+0xb0>)
800ae8c: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
800ae8e: 4b23 ldr r3, [pc, #140] @ (800af1c <USBD_LL_Init+0xac>)
800ae90: 2208 movs r2, #8
800ae92: 711a strb r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
800ae94: 4b21 ldr r3, [pc, #132] @ (800af1c <USBD_LL_Init+0xac>)
800ae96: 2202 movs r2, #2
800ae98: 719a strb r2, [r3, #6]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
800ae9a: 4b20 ldr r3, [pc, #128] @ (800af1c <USBD_LL_Init+0xac>)
800ae9c: 2200 movs r2, #0
800ae9e: 729a strb r2, [r3, #10]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
800aea0: 4b1e ldr r3, [pc, #120] @ (800af1c <USBD_LL_Init+0xac>)
800aea2: 2200 movs r2, #0
800aea4: 72da strb r2, [r3, #11]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
800aea6: 4b1d ldr r3, [pc, #116] @ (800af1c <USBD_LL_Init+0xac>)
800aea8: 2200 movs r2, #0
800aeaa: 731a strb r2, [r3, #12]
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
800aeac: 481b ldr r0, [pc, #108] @ (800af1c <USBD_LL_Init+0xac>)
800aeae: f7f8 fc39 bl 8003724 <HAL_PCD_Init>
800aeb2: 4603 mov r3, r0
800aeb4: 2b00 cmp r3, #0
800aeb6: d001 beq.n 800aebc <USBD_LL_Init+0x4c>
{
Error_Handler( );
800aeb8: f7f6 fd24 bl 8001904 <Error_Handler>
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
800aebc: 687b ldr r3, [r7, #4]
800aebe: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aec2: 2318 movs r3, #24
800aec4: 2200 movs r2, #0
800aec6: 2100 movs r1, #0
800aec8: f7fa f94a bl 8005160 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
800aecc: 687b ldr r3, [r7, #4]
800aece: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aed2: 2358 movs r3, #88 @ 0x58
800aed4: 2200 movs r2, #0
800aed6: 2180 movs r1, #128 @ 0x80
800aed8: f7fa f942 bl 8005160 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
800aedc: 687b ldr r3, [r7, #4]
800aede: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aee2: 23c0 movs r3, #192 @ 0xc0
800aee4: 2200 movs r2, #0
800aee6: 2181 movs r1, #129 @ 0x81
800aee8: f7fa f93a bl 8005160 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
800aeec: 687b ldr r3, [r7, #4]
800aeee: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aef2: f44f 7388 mov.w r3, #272 @ 0x110
800aef6: 2200 movs r2, #0
800aef8: 2101 movs r1, #1
800aefa: f7fa f931 bl 8005160 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
800aefe: 687b ldr r3, [r7, #4]
800af00: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800af04: f44f 7380 mov.w r3, #256 @ 0x100
800af08: 2200 movs r2, #0
800af0a: 2182 movs r1, #130 @ 0x82
800af0c: f7fa f928 bl 8005160 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK;
800af10: 2300 movs r3, #0
}
800af12: 4618 mov r0, r3
800af14: 3708 adds r7, #8
800af16: 46bd mov sp, r7
800af18: bd80 pop {r7, pc}
800af1a: bf00 nop
800af1c: 200011dc .word 0x200011dc
800af20: 40005c00 .word 0x40005c00
0800af24 <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
800af24: b580 push {r7, lr}
800af26: b084 sub sp, #16
800af28: af00 add r7, sp, #0
800af2a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
800af2c: 2300 movs r3, #0
800af2e: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800af30: 2300 movs r3, #0
800af32: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_Start(pdev->pData);
800af34: 687b ldr r3, [r7, #4]
800af36: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800af3a: 4618 mov r0, r3
800af3c: f7f8 fce8 bl 8003910 <HAL_PCD_Start>
800af40: 4603 mov r3, r0
800af42: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800af44: 7bfb ldrb r3, [r7, #15]
800af46: 4618 mov r0, r3
800af48: f000 f94e bl 800b1e8 <USBD_Get_USB_Status>
800af4c: 4603 mov r3, r0
800af4e: 73bb strb r3, [r7, #14]
return usb_status;
800af50: 7bbb ldrb r3, [r7, #14]
}
800af52: 4618 mov r0, r3
800af54: 3710 adds r7, #16
800af56: 46bd mov sp, r7
800af58: bd80 pop {r7, pc}
0800af5a <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
800af5a: b580 push {r7, lr}
800af5c: b084 sub sp, #16
800af5e: af00 add r7, sp, #0
800af60: 6078 str r0, [r7, #4]
800af62: 4608 mov r0, r1
800af64: 4611 mov r1, r2
800af66: 461a mov r2, r3
800af68: 4603 mov r3, r0
800af6a: 70fb strb r3, [r7, #3]
800af6c: 460b mov r3, r1
800af6e: 70bb strb r3, [r7, #2]
800af70: 4613 mov r3, r2
800af72: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
800af74: 2300 movs r3, #0
800af76: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800af78: 2300 movs r3, #0
800af7a: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
800af7c: 687b ldr r3, [r7, #4]
800af7e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800af82: 78bb ldrb r3, [r7, #2]
800af84: 883a ldrh r2, [r7, #0]
800af86: 78f9 ldrb r1, [r7, #3]
800af88: f7f8 fe3c bl 8003c04 <HAL_PCD_EP_Open>
800af8c: 4603 mov r3, r0
800af8e: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800af90: 7bfb ldrb r3, [r7, #15]
800af92: 4618 mov r0, r3
800af94: f000 f928 bl 800b1e8 <USBD_Get_USB_Status>
800af98: 4603 mov r3, r0
800af9a: 73bb strb r3, [r7, #14]
return usb_status;
800af9c: 7bbb ldrb r3, [r7, #14]
}
800af9e: 4618 mov r0, r3
800afa0: 3710 adds r7, #16
800afa2: 46bd mov sp, r7
800afa4: bd80 pop {r7, pc}
0800afa6 <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800afa6: b580 push {r7, lr}
800afa8: b084 sub sp, #16
800afaa: af00 add r7, sp, #0
800afac: 6078 str r0, [r7, #4]
800afae: 460b mov r3, r1
800afb0: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800afb2: 2300 movs r3, #0
800afb4: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800afb6: 2300 movs r3, #0
800afb8: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
800afba: 687b ldr r3, [r7, #4]
800afbc: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800afc0: 78fa ldrb r2, [r7, #3]
800afc2: 4611 mov r1, r2
800afc4: 4618 mov r0, r3
800afc6: f7f8 fe7a bl 8003cbe <HAL_PCD_EP_Close>
800afca: 4603 mov r3, r0
800afcc: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800afce: 7bfb ldrb r3, [r7, #15]
800afd0: 4618 mov r0, r3
800afd2: f000 f909 bl 800b1e8 <USBD_Get_USB_Status>
800afd6: 4603 mov r3, r0
800afd8: 73bb strb r3, [r7, #14]
return usb_status;
800afda: 7bbb ldrb r3, [r7, #14]
}
800afdc: 4618 mov r0, r3
800afde: 3710 adds r7, #16
800afe0: 46bd mov sp, r7
800afe2: bd80 pop {r7, pc}
0800afe4 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800afe4: b580 push {r7, lr}
800afe6: b084 sub sp, #16
800afe8: af00 add r7, sp, #0
800afea: 6078 str r0, [r7, #4]
800afec: 460b mov r3, r1
800afee: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800aff0: 2300 movs r3, #0
800aff2: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800aff4: 2300 movs r3, #0
800aff6: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
800aff8: 687b ldr r3, [r7, #4]
800affa: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800affe: 78fa ldrb r2, [r7, #3]
800b000: 4611 mov r1, r2
800b002: 4618 mov r0, r3
800b004: f7f8 ff22 bl 8003e4c <HAL_PCD_EP_SetStall>
800b008: 4603 mov r3, r0
800b00a: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800b00c: 7bfb ldrb r3, [r7, #15]
800b00e: 4618 mov r0, r3
800b010: f000 f8ea bl 800b1e8 <USBD_Get_USB_Status>
800b014: 4603 mov r3, r0
800b016: 73bb strb r3, [r7, #14]
return usb_status;
800b018: 7bbb ldrb r3, [r7, #14]
}
800b01a: 4618 mov r0, r3
800b01c: 3710 adds r7, #16
800b01e: 46bd mov sp, r7
800b020: bd80 pop {r7, pc}
0800b022 <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b022: b580 push {r7, lr}
800b024: b084 sub sp, #16
800b026: af00 add r7, sp, #0
800b028: 6078 str r0, [r7, #4]
800b02a: 460b mov r3, r1
800b02c: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b02e: 2300 movs r3, #0
800b030: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800b032: 2300 movs r3, #0
800b034: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
800b036: 687b ldr r3, [r7, #4]
800b038: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b03c: 78fa ldrb r2, [r7, #3]
800b03e: 4611 mov r1, r2
800b040: 4618 mov r0, r3
800b042: f7f8 ff63 bl 8003f0c <HAL_PCD_EP_ClrStall>
800b046: 4603 mov r3, r0
800b048: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800b04a: 7bfb ldrb r3, [r7, #15]
800b04c: 4618 mov r0, r3
800b04e: f000 f8cb bl 800b1e8 <USBD_Get_USB_Status>
800b052: 4603 mov r3, r0
800b054: 73bb strb r3, [r7, #14]
return usb_status;
800b056: 7bbb ldrb r3, [r7, #14]
}
800b058: 4618 mov r0, r3
800b05a: 3710 adds r7, #16
800b05c: 46bd mov sp, r7
800b05e: bd80 pop {r7, pc}
0800b060 <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b060: b480 push {r7}
800b062: b085 sub sp, #20
800b064: af00 add r7, sp, #0
800b066: 6078 str r0, [r7, #4]
800b068: 460b mov r3, r1
800b06a: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
800b06c: 687b ldr r3, [r7, #4]
800b06e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b072: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
800b074: f997 3003 ldrsb.w r3, [r7, #3]
800b078: 2b00 cmp r3, #0
800b07a: da0b bge.n 800b094 <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
800b07c: 78fb ldrb r3, [r7, #3]
800b07e: f003 027f and.w r2, r3, #127 @ 0x7f
800b082: 68f9 ldr r1, [r7, #12]
800b084: 4613 mov r3, r2
800b086: 009b lsls r3, r3, #2
800b088: 4413 add r3, r2
800b08a: 00db lsls r3, r3, #3
800b08c: 440b add r3, r1
800b08e: 3312 adds r3, #18
800b090: 781b ldrb r3, [r3, #0]
800b092: e00b b.n 800b0ac <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
800b094: 78fb ldrb r3, [r7, #3]
800b096: f003 027f and.w r2, r3, #127 @ 0x7f
800b09a: 68f9 ldr r1, [r7, #12]
800b09c: 4613 mov r3, r2
800b09e: 009b lsls r3, r3, #2
800b0a0: 4413 add r3, r2
800b0a2: 00db lsls r3, r3, #3
800b0a4: 440b add r3, r1
800b0a6: f503 73a9 add.w r3, r3, #338 @ 0x152
800b0aa: 781b ldrb r3, [r3, #0]
}
}
800b0ac: 4618 mov r0, r3
800b0ae: 3714 adds r7, #20
800b0b0: 46bd mov sp, r7
800b0b2: bc80 pop {r7}
800b0b4: 4770 bx lr
0800b0b6 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
800b0b6: b580 push {r7, lr}
800b0b8: b084 sub sp, #16
800b0ba: af00 add r7, sp, #0
800b0bc: 6078 str r0, [r7, #4]
800b0be: 460b mov r3, r1
800b0c0: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b0c2: 2300 movs r3, #0
800b0c4: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800b0c6: 2300 movs r3, #0
800b0c8: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
800b0ca: 687b ldr r3, [r7, #4]
800b0cc: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b0d0: 78fa ldrb r2, [r7, #3]
800b0d2: 4611 mov r1, r2
800b0d4: 4618 mov r0, r3
800b0d6: f7f8 fd71 bl 8003bbc <HAL_PCD_SetAddress>
800b0da: 4603 mov r3, r0
800b0dc: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800b0de: 7bfb ldrb r3, [r7, #15]
800b0e0: 4618 mov r0, r3
800b0e2: f000 f881 bl 800b1e8 <USBD_Get_USB_Status>
800b0e6: 4603 mov r3, r0
800b0e8: 73bb strb r3, [r7, #14]
return usb_status;
800b0ea: 7bbb ldrb r3, [r7, #14]
}
800b0ec: 4618 mov r0, r3
800b0ee: 3710 adds r7, #16
800b0f0: 46bd mov sp, r7
800b0f2: bd80 pop {r7, pc}
0800b0f4 <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800b0f4: b580 push {r7, lr}
800b0f6: b086 sub sp, #24
800b0f8: af00 add r7, sp, #0
800b0fa: 60f8 str r0, [r7, #12]
800b0fc: 607a str r2, [r7, #4]
800b0fe: 461a mov r2, r3
800b100: 460b mov r3, r1
800b102: 72fb strb r3, [r7, #11]
800b104: 4613 mov r3, r2
800b106: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800b108: 2300 movs r3, #0
800b10a: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
800b10c: 2300 movs r3, #0
800b10e: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
800b110: 68fb ldr r3, [r7, #12]
800b112: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800b116: 893b ldrh r3, [r7, #8]
800b118: 7af9 ldrb r1, [r7, #11]
800b11a: 687a ldr r2, [r7, #4]
800b11c: f7f8 fe5f bl 8003dde <HAL_PCD_EP_Transmit>
800b120: 4603 mov r3, r0
800b122: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800b124: 7dfb ldrb r3, [r7, #23]
800b126: 4618 mov r0, r3
800b128: f000 f85e bl 800b1e8 <USBD_Get_USB_Status>
800b12c: 4603 mov r3, r0
800b12e: 75bb strb r3, [r7, #22]
return usb_status;
800b130: 7dbb ldrb r3, [r7, #22]
}
800b132: 4618 mov r0, r3
800b134: 3718 adds r7, #24
800b136: 46bd mov sp, r7
800b138: bd80 pop {r7, pc}
0800b13a <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800b13a: b580 push {r7, lr}
800b13c: b086 sub sp, #24
800b13e: af00 add r7, sp, #0
800b140: 60f8 str r0, [r7, #12]
800b142: 607a str r2, [r7, #4]
800b144: 461a mov r2, r3
800b146: 460b mov r3, r1
800b148: 72fb strb r3, [r7, #11]
800b14a: 4613 mov r3, r2
800b14c: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800b14e: 2300 movs r3, #0
800b150: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
800b152: 2300 movs r3, #0
800b154: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
800b156: 68fb ldr r3, [r7, #12]
800b158: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800b15c: 893b ldrh r3, [r7, #8]
800b15e: 7af9 ldrb r1, [r7, #11]
800b160: 687a ldr r2, [r7, #4]
800b162: f7f8 fdf4 bl 8003d4e <HAL_PCD_EP_Receive>
800b166: 4603 mov r3, r0
800b168: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800b16a: 7dfb ldrb r3, [r7, #23]
800b16c: 4618 mov r0, r3
800b16e: f000 f83b bl 800b1e8 <USBD_Get_USB_Status>
800b172: 4603 mov r3, r0
800b174: 75bb strb r3, [r7, #22]
return usb_status;
800b176: 7dbb ldrb r3, [r7, #22]
}
800b178: 4618 mov r0, r3
800b17a: 3718 adds r7, #24
800b17c: 46bd mov sp, r7
800b17e: bd80 pop {r7, pc}
0800b180 <USBD_LL_GetRxDataSize>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Received Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b180: b580 push {r7, lr}
800b182: b082 sub sp, #8
800b184: af00 add r7, sp, #0
800b186: 6078 str r0, [r7, #4]
800b188: 460b mov r3, r1
800b18a: 70fb strb r3, [r7, #3]
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
800b18c: 687b ldr r3, [r7, #4]
800b18e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b192: 78fa ldrb r2, [r7, #3]
800b194: 4611 mov r1, r2
800b196: 4618 mov r0, r3
800b198: f7f8 fe0a bl 8003db0 <HAL_PCD_EP_GetRxCount>
800b19c: 4603 mov r3, r0
}
800b19e: 4618 mov r0, r3
800b1a0: 3708 adds r7, #8
800b1a2: 46bd mov sp, r7
800b1a4: bd80 pop {r7, pc}
...
0800b1a8 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
800b1a8: b480 push {r7}
800b1aa: b083 sub sp, #12
800b1ac: af00 add r7, sp, #0
800b1ae: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
return mem;
800b1b0: 4b02 ldr r3, [pc, #8] @ (800b1bc <USBD_static_malloc+0x14>)
}
800b1b2: 4618 mov r0, r3
800b1b4: 370c adds r7, #12
800b1b6: 46bd mov sp, r7
800b1b8: bc80 pop {r7}
800b1ba: 4770 bx lr
800b1bc: 200014b4 .word 0x200014b4
0800b1c0 <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
800b1c0: b480 push {r7}
800b1c2: b083 sub sp, #12
800b1c4: af00 add r7, sp, #0
800b1c6: 6078 str r0, [r7, #4]
}
800b1c8: bf00 nop
800b1ca: 370c adds r7, #12
800b1cc: 46bd mov sp, r7
800b1ce: bc80 pop {r7}
800b1d0: 4770 bx lr
0800b1d2 <HAL_PCDEx_SetConnectionState>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b1d2: b480 push {r7}
800b1d4: b083 sub sp, #12
800b1d6: af00 add r7, sp, #0
800b1d8: 6078 str r0, [r7, #4]
800b1da: 460b mov r3, r1
800b1dc: 70fb strb r3, [r7, #3]
{
/* Configure High connection state. */
}
/* USER CODE END 6 */
}
800b1de: bf00 nop
800b1e0: 370c adds r7, #12
800b1e2: 46bd mov sp, r7
800b1e4: bc80 pop {r7}
800b1e6: 4770 bx lr
0800b1e8 <USBD_Get_USB_Status>:
* @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
800b1e8: b480 push {r7}
800b1ea: b085 sub sp, #20
800b1ec: af00 add r7, sp, #0
800b1ee: 4603 mov r3, r0
800b1f0: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef usb_status = USBD_OK;
800b1f2: 2300 movs r3, #0
800b1f4: 73fb strb r3, [r7, #15]
switch (hal_status)
800b1f6: 79fb ldrb r3, [r7, #7]
800b1f8: 2b03 cmp r3, #3
800b1fa: d817 bhi.n 800b22c <USBD_Get_USB_Status+0x44>
800b1fc: a201 add r2, pc, #4 @ (adr r2, 800b204 <USBD_Get_USB_Status+0x1c>)
800b1fe: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b202: bf00 nop
800b204: 0800b215 .word 0x0800b215
800b208: 0800b21b .word 0x0800b21b
800b20c: 0800b221 .word 0x0800b221
800b210: 0800b227 .word 0x0800b227
{
case HAL_OK :
usb_status = USBD_OK;
800b214: 2300 movs r3, #0
800b216: 73fb strb r3, [r7, #15]
break;
800b218: e00b b.n 800b232 <USBD_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b21a: 2302 movs r3, #2
800b21c: 73fb strb r3, [r7, #15]
break;
800b21e: e008 b.n 800b232 <USBD_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b220: 2301 movs r3, #1
800b222: 73fb strb r3, [r7, #15]
break;
800b224: e005 b.n 800b232 <USBD_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b226: 2302 movs r3, #2
800b228: 73fb strb r3, [r7, #15]
break;
800b22a: e002 b.n 800b232 <USBD_Get_USB_Status+0x4a>
default :
usb_status = USBD_FAIL;
800b22c: 2302 movs r3, #2
800b22e: 73fb strb r3, [r7, #15]
break;
800b230: bf00 nop
}
return usb_status;
800b232: 7bfb ldrb r3, [r7, #15]
}
800b234: 4618 mov r0, r3
800b236: 3714 adds r7, #20
800b238: 46bd mov sp, r7
800b23a: bc80 pop {r7}
800b23c: 4770 bx lr
800b23e: bf00 nop
0800b240 <siprintf>:
800b240: b40e push {r1, r2, r3}
800b242: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
800b246: b510 push {r4, lr}
800b248: 2400 movs r4, #0
800b24a: b09d sub sp, #116 @ 0x74
800b24c: ab1f add r3, sp, #124 @ 0x7c
800b24e: 9002 str r0, [sp, #8]
800b250: 9006 str r0, [sp, #24]
800b252: 9107 str r1, [sp, #28]
800b254: 9104 str r1, [sp, #16]
800b256: 4809 ldr r0, [pc, #36] @ (800b27c <siprintf+0x3c>)
800b258: 4909 ldr r1, [pc, #36] @ (800b280 <siprintf+0x40>)
800b25a: f853 2b04 ldr.w r2, [r3], #4
800b25e: 9105 str r1, [sp, #20]
800b260: 6800 ldr r0, [r0, #0]
800b262: a902 add r1, sp, #8
800b264: 9301 str r3, [sp, #4]
800b266: 941b str r4, [sp, #108] @ 0x6c
800b268: f000 f992 bl 800b590 <_svfiprintf_r>
800b26c: 9b02 ldr r3, [sp, #8]
800b26e: 701c strb r4, [r3, #0]
800b270: b01d add sp, #116 @ 0x74
800b272: e8bd 4010 ldmia.w sp!, {r4, lr}
800b276: b003 add sp, #12
800b278: 4770 bx lr
800b27a: bf00 nop
800b27c: 20000180 .word 0x20000180
800b280: ffff0208 .word 0xffff0208
0800b284 <memset>:
800b284: 4603 mov r3, r0
800b286: 4402 add r2, r0
800b288: 4293 cmp r3, r2
800b28a: d100 bne.n 800b28e <memset+0xa>
800b28c: 4770 bx lr
800b28e: f803 1b01 strb.w r1, [r3], #1
800b292: e7f9 b.n 800b288 <memset+0x4>
0800b294 <__errno>:
800b294: 4b01 ldr r3, [pc, #4] @ (800b29c <__errno+0x8>)
800b296: 6818 ldr r0, [r3, #0]
800b298: 4770 bx lr
800b29a: bf00 nop
800b29c: 20000180 .word 0x20000180
0800b2a0 <__libc_init_array>:
800b2a0: b570 push {r4, r5, r6, lr}
800b2a2: 2600 movs r6, #0
800b2a4: 4d0c ldr r5, [pc, #48] @ (800b2d8 <__libc_init_array+0x38>)
800b2a6: 4c0d ldr r4, [pc, #52] @ (800b2dc <__libc_init_array+0x3c>)
800b2a8: 1b64 subs r4, r4, r5
800b2aa: 10a4 asrs r4, r4, #2
800b2ac: 42a6 cmp r6, r4
800b2ae: d109 bne.n 800b2c4 <__libc_init_array+0x24>
800b2b0: f000 fc76 bl 800bba0 <_init>
800b2b4: 2600 movs r6, #0
800b2b6: 4d0a ldr r5, [pc, #40] @ (800b2e0 <__libc_init_array+0x40>)
800b2b8: 4c0a ldr r4, [pc, #40] @ (800b2e4 <__libc_init_array+0x44>)
800b2ba: 1b64 subs r4, r4, r5
800b2bc: 10a4 asrs r4, r4, #2
800b2be: 42a6 cmp r6, r4
800b2c0: d105 bne.n 800b2ce <__libc_init_array+0x2e>
800b2c2: bd70 pop {r4, r5, r6, pc}
800b2c4: f855 3b04 ldr.w r3, [r5], #4
800b2c8: 4798 blx r3
800b2ca: 3601 adds r6, #1
800b2cc: e7ee b.n 800b2ac <__libc_init_array+0xc>
800b2ce: f855 3b04 ldr.w r3, [r5], #4
800b2d2: 4798 blx r3
800b2d4: 3601 adds r6, #1
800b2d6: e7f2 b.n 800b2be <__libc_init_array+0x1e>
800b2d8: 0800be8c .word 0x0800be8c
800b2dc: 0800be8c .word 0x0800be8c
800b2e0: 0800be8c .word 0x0800be8c
800b2e4: 0800be90 .word 0x0800be90
0800b2e8 <__retarget_lock_acquire_recursive>:
800b2e8: 4770 bx lr
0800b2ea <__retarget_lock_release_recursive>:
800b2ea: 4770 bx lr
0800b2ec <_free_r>:
800b2ec: b538 push {r3, r4, r5, lr}
800b2ee: 4605 mov r5, r0
800b2f0: 2900 cmp r1, #0
800b2f2: d040 beq.n 800b376 <_free_r+0x8a>
800b2f4: f851 3c04 ldr.w r3, [r1, #-4]
800b2f8: 1f0c subs r4, r1, #4
800b2fa: 2b00 cmp r3, #0
800b2fc: bfb8 it lt
800b2fe: 18e4 addlt r4, r4, r3
800b300: f000 f8de bl 800b4c0 <__malloc_lock>
800b304: 4a1c ldr r2, [pc, #112] @ (800b378 <_free_r+0x8c>)
800b306: 6813 ldr r3, [r2, #0]
800b308: b933 cbnz r3, 800b318 <_free_r+0x2c>
800b30a: 6063 str r3, [r4, #4]
800b30c: 6014 str r4, [r2, #0]
800b30e: 4628 mov r0, r5
800b310: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
800b314: f000 b8da b.w 800b4cc <__malloc_unlock>
800b318: 42a3 cmp r3, r4
800b31a: d908 bls.n 800b32e <_free_r+0x42>
800b31c: 6820 ldr r0, [r4, #0]
800b31e: 1821 adds r1, r4, r0
800b320: 428b cmp r3, r1
800b322: bf01 itttt eq
800b324: 6819 ldreq r1, [r3, #0]
800b326: 685b ldreq r3, [r3, #4]
800b328: 1809 addeq r1, r1, r0
800b32a: 6021 streq r1, [r4, #0]
800b32c: e7ed b.n 800b30a <_free_r+0x1e>
800b32e: 461a mov r2, r3
800b330: 685b ldr r3, [r3, #4]
800b332: b10b cbz r3, 800b338 <_free_r+0x4c>
800b334: 42a3 cmp r3, r4
800b336: d9fa bls.n 800b32e <_free_r+0x42>
800b338: 6811 ldr r1, [r2, #0]
800b33a: 1850 adds r0, r2, r1
800b33c: 42a0 cmp r0, r4
800b33e: d10b bne.n 800b358 <_free_r+0x6c>
800b340: 6820 ldr r0, [r4, #0]
800b342: 4401 add r1, r0
800b344: 1850 adds r0, r2, r1
800b346: 4283 cmp r3, r0
800b348: 6011 str r1, [r2, #0]
800b34a: d1e0 bne.n 800b30e <_free_r+0x22>
800b34c: 6818 ldr r0, [r3, #0]
800b34e: 685b ldr r3, [r3, #4]
800b350: 4408 add r0, r1
800b352: 6010 str r0, [r2, #0]
800b354: 6053 str r3, [r2, #4]
800b356: e7da b.n 800b30e <_free_r+0x22>
800b358: d902 bls.n 800b360 <_free_r+0x74>
800b35a: 230c movs r3, #12
800b35c: 602b str r3, [r5, #0]
800b35e: e7d6 b.n 800b30e <_free_r+0x22>
800b360: 6820 ldr r0, [r4, #0]
800b362: 1821 adds r1, r4, r0
800b364: 428b cmp r3, r1
800b366: bf01 itttt eq
800b368: 6819 ldreq r1, [r3, #0]
800b36a: 685b ldreq r3, [r3, #4]
800b36c: 1809 addeq r1, r1, r0
800b36e: 6021 streq r1, [r4, #0]
800b370: 6063 str r3, [r4, #4]
800b372: 6054 str r4, [r2, #4]
800b374: e7cb b.n 800b30e <_free_r+0x22>
800b376: bd38 pop {r3, r4, r5, pc}
800b378: 20001818 .word 0x20001818
0800b37c <sbrk_aligned>:
800b37c: b570 push {r4, r5, r6, lr}
800b37e: 4e0f ldr r6, [pc, #60] @ (800b3bc <sbrk_aligned+0x40>)
800b380: 460c mov r4, r1
800b382: 6831 ldr r1, [r6, #0]
800b384: 4605 mov r5, r0
800b386: b911 cbnz r1, 800b38e <sbrk_aligned+0x12>
800b388: f000 fba8 bl 800badc <_sbrk_r>
800b38c: 6030 str r0, [r6, #0]
800b38e: 4621 mov r1, r4
800b390: 4628 mov r0, r5
800b392: f000 fba3 bl 800badc <_sbrk_r>
800b396: 1c43 adds r3, r0, #1
800b398: d103 bne.n 800b3a2 <sbrk_aligned+0x26>
800b39a: f04f 34ff mov.w r4, #4294967295
800b39e: 4620 mov r0, r4
800b3a0: bd70 pop {r4, r5, r6, pc}
800b3a2: 1cc4 adds r4, r0, #3
800b3a4: f024 0403 bic.w r4, r4, #3
800b3a8: 42a0 cmp r0, r4
800b3aa: d0f8 beq.n 800b39e <sbrk_aligned+0x22>
800b3ac: 1a21 subs r1, r4, r0
800b3ae: 4628 mov r0, r5
800b3b0: f000 fb94 bl 800badc <_sbrk_r>
800b3b4: 3001 adds r0, #1
800b3b6: d1f2 bne.n 800b39e <sbrk_aligned+0x22>
800b3b8: e7ef b.n 800b39a <sbrk_aligned+0x1e>
800b3ba: bf00 nop
800b3bc: 20001814 .word 0x20001814
0800b3c0 <_malloc_r>:
800b3c0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800b3c4: 1ccd adds r5, r1, #3
800b3c6: f025 0503 bic.w r5, r5, #3
800b3ca: 3508 adds r5, #8
800b3cc: 2d0c cmp r5, #12
800b3ce: bf38 it cc
800b3d0: 250c movcc r5, #12
800b3d2: 2d00 cmp r5, #0
800b3d4: 4606 mov r6, r0
800b3d6: db01 blt.n 800b3dc <_malloc_r+0x1c>
800b3d8: 42a9 cmp r1, r5
800b3da: d904 bls.n 800b3e6 <_malloc_r+0x26>
800b3dc: 230c movs r3, #12
800b3de: 6033 str r3, [r6, #0]
800b3e0: 2000 movs r0, #0
800b3e2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800b3e6: f8df 80d4 ldr.w r8, [pc, #212] @ 800b4bc <_malloc_r+0xfc>
800b3ea: f000 f869 bl 800b4c0 <__malloc_lock>
800b3ee: f8d8 3000 ldr.w r3, [r8]
800b3f2: 461c mov r4, r3
800b3f4: bb44 cbnz r4, 800b448 <_malloc_r+0x88>
800b3f6: 4629 mov r1, r5
800b3f8: 4630 mov r0, r6
800b3fa: f7ff ffbf bl 800b37c <sbrk_aligned>
800b3fe: 1c43 adds r3, r0, #1
800b400: 4604 mov r4, r0
800b402: d158 bne.n 800b4b6 <_malloc_r+0xf6>
800b404: f8d8 4000 ldr.w r4, [r8]
800b408: 4627 mov r7, r4
800b40a: 2f00 cmp r7, #0
800b40c: d143 bne.n 800b496 <_malloc_r+0xd6>
800b40e: 2c00 cmp r4, #0
800b410: d04b beq.n 800b4aa <_malloc_r+0xea>
800b412: 6823 ldr r3, [r4, #0]
800b414: 4639 mov r1, r7
800b416: 4630 mov r0, r6
800b418: eb04 0903 add.w r9, r4, r3
800b41c: f000 fb5e bl 800badc <_sbrk_r>
800b420: 4581 cmp r9, r0
800b422: d142 bne.n 800b4aa <_malloc_r+0xea>
800b424: 6821 ldr r1, [r4, #0]
800b426: 4630 mov r0, r6
800b428: 1a6d subs r5, r5, r1
800b42a: 4629 mov r1, r5
800b42c: f7ff ffa6 bl 800b37c <sbrk_aligned>
800b430: 3001 adds r0, #1
800b432: d03a beq.n 800b4aa <_malloc_r+0xea>
800b434: 6823 ldr r3, [r4, #0]
800b436: 442b add r3, r5
800b438: 6023 str r3, [r4, #0]
800b43a: f8d8 3000 ldr.w r3, [r8]
800b43e: 685a ldr r2, [r3, #4]
800b440: bb62 cbnz r2, 800b49c <_malloc_r+0xdc>
800b442: f8c8 7000 str.w r7, [r8]
800b446: e00f b.n 800b468 <_malloc_r+0xa8>
800b448: 6822 ldr r2, [r4, #0]
800b44a: 1b52 subs r2, r2, r5
800b44c: d420 bmi.n 800b490 <_malloc_r+0xd0>
800b44e: 2a0b cmp r2, #11
800b450: d917 bls.n 800b482 <_malloc_r+0xc2>
800b452: 1961 adds r1, r4, r5
800b454: 42a3 cmp r3, r4
800b456: 6025 str r5, [r4, #0]
800b458: bf18 it ne
800b45a: 6059 strne r1, [r3, #4]
800b45c: 6863 ldr r3, [r4, #4]
800b45e: bf08 it eq
800b460: f8c8 1000 streq.w r1, [r8]
800b464: 5162 str r2, [r4, r5]
800b466: 604b str r3, [r1, #4]
800b468: 4630 mov r0, r6
800b46a: f000 f82f bl 800b4cc <__malloc_unlock>
800b46e: f104 000b add.w r0, r4, #11
800b472: 1d23 adds r3, r4, #4
800b474: f020 0007 bic.w r0, r0, #7
800b478: 1ac2 subs r2, r0, r3
800b47a: bf1c itt ne
800b47c: 1a1b subne r3, r3, r0
800b47e: 50a3 strne r3, [r4, r2]
800b480: e7af b.n 800b3e2 <_malloc_r+0x22>
800b482: 6862 ldr r2, [r4, #4]
800b484: 42a3 cmp r3, r4
800b486: bf0c ite eq
800b488: f8c8 2000 streq.w r2, [r8]
800b48c: 605a strne r2, [r3, #4]
800b48e: e7eb b.n 800b468 <_malloc_r+0xa8>
800b490: 4623 mov r3, r4
800b492: 6864 ldr r4, [r4, #4]
800b494: e7ae b.n 800b3f4 <_malloc_r+0x34>
800b496: 463c mov r4, r7
800b498: 687f ldr r7, [r7, #4]
800b49a: e7b6 b.n 800b40a <_malloc_r+0x4a>
800b49c: 461a mov r2, r3
800b49e: 685b ldr r3, [r3, #4]
800b4a0: 42a3 cmp r3, r4
800b4a2: d1fb bne.n 800b49c <_malloc_r+0xdc>
800b4a4: 2300 movs r3, #0
800b4a6: 6053 str r3, [r2, #4]
800b4a8: e7de b.n 800b468 <_malloc_r+0xa8>
800b4aa: 230c movs r3, #12
800b4ac: 4630 mov r0, r6
800b4ae: 6033 str r3, [r6, #0]
800b4b0: f000 f80c bl 800b4cc <__malloc_unlock>
800b4b4: e794 b.n 800b3e0 <_malloc_r+0x20>
800b4b6: 6005 str r5, [r0, #0]
800b4b8: e7d6 b.n 800b468 <_malloc_r+0xa8>
800b4ba: bf00 nop
800b4bc: 20001818 .word 0x20001818
0800b4c0 <__malloc_lock>:
800b4c0: 4801 ldr r0, [pc, #4] @ (800b4c8 <__malloc_lock+0x8>)
800b4c2: f7ff bf11 b.w 800b2e8 <__retarget_lock_acquire_recursive>
800b4c6: bf00 nop
800b4c8: 20001810 .word 0x20001810
0800b4cc <__malloc_unlock>:
800b4cc: 4801 ldr r0, [pc, #4] @ (800b4d4 <__malloc_unlock+0x8>)
800b4ce: f7ff bf0c b.w 800b2ea <__retarget_lock_release_recursive>
800b4d2: bf00 nop
800b4d4: 20001810 .word 0x20001810
0800b4d8 <__ssputs_r>:
800b4d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800b4dc: 461f mov r7, r3
800b4de: 688e ldr r6, [r1, #8]
800b4e0: 4682 mov sl, r0
800b4e2: 42be cmp r6, r7
800b4e4: 460c mov r4, r1
800b4e6: 4690 mov r8, r2
800b4e8: 680b ldr r3, [r1, #0]
800b4ea: d82d bhi.n 800b548 <__ssputs_r+0x70>
800b4ec: f9b1 200c ldrsh.w r2, [r1, #12]
800b4f0: f412 6f90 tst.w r2, #1152 @ 0x480
800b4f4: d026 beq.n 800b544 <__ssputs_r+0x6c>
800b4f6: 6965 ldr r5, [r4, #20]
800b4f8: 6909 ldr r1, [r1, #16]
800b4fa: eb05 0545 add.w r5, r5, r5, lsl #1
800b4fe: eba3 0901 sub.w r9, r3, r1
800b502: eb05 75d5 add.w r5, r5, r5, lsr #31
800b506: 1c7b adds r3, r7, #1
800b508: 444b add r3, r9
800b50a: 106d asrs r5, r5, #1
800b50c: 429d cmp r5, r3
800b50e: bf38 it cc
800b510: 461d movcc r5, r3
800b512: 0553 lsls r3, r2, #21
800b514: d527 bpl.n 800b566 <__ssputs_r+0x8e>
800b516: 4629 mov r1, r5
800b518: f7ff ff52 bl 800b3c0 <_malloc_r>
800b51c: 4606 mov r6, r0
800b51e: b360 cbz r0, 800b57a <__ssputs_r+0xa2>
800b520: 464a mov r2, r9
800b522: 6921 ldr r1, [r4, #16]
800b524: f000 faf8 bl 800bb18 <memcpy>
800b528: 89a3 ldrh r3, [r4, #12]
800b52a: f423 6390 bic.w r3, r3, #1152 @ 0x480
800b52e: f043 0380 orr.w r3, r3, #128 @ 0x80
800b532: 81a3 strh r3, [r4, #12]
800b534: 6126 str r6, [r4, #16]
800b536: 444e add r6, r9
800b538: 6026 str r6, [r4, #0]
800b53a: 463e mov r6, r7
800b53c: 6165 str r5, [r4, #20]
800b53e: eba5 0509 sub.w r5, r5, r9
800b542: 60a5 str r5, [r4, #8]
800b544: 42be cmp r6, r7
800b546: d900 bls.n 800b54a <__ssputs_r+0x72>
800b548: 463e mov r6, r7
800b54a: 4632 mov r2, r6
800b54c: 4641 mov r1, r8
800b54e: 6820 ldr r0, [r4, #0]
800b550: f000 faaa bl 800baa8 <memmove>
800b554: 2000 movs r0, #0
800b556: 68a3 ldr r3, [r4, #8]
800b558: 1b9b subs r3, r3, r6
800b55a: 60a3 str r3, [r4, #8]
800b55c: 6823 ldr r3, [r4, #0]
800b55e: 4433 add r3, r6
800b560: 6023 str r3, [r4, #0]
800b562: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b566: 462a mov r2, r5
800b568: f000 fae4 bl 800bb34 <_realloc_r>
800b56c: 4606 mov r6, r0
800b56e: 2800 cmp r0, #0
800b570: d1e0 bne.n 800b534 <__ssputs_r+0x5c>
800b572: 4650 mov r0, sl
800b574: 6921 ldr r1, [r4, #16]
800b576: f7ff feb9 bl 800b2ec <_free_r>
800b57a: 230c movs r3, #12
800b57c: f8ca 3000 str.w r3, [sl]
800b580: 89a3 ldrh r3, [r4, #12]
800b582: f04f 30ff mov.w r0, #4294967295
800b586: f043 0340 orr.w r3, r3, #64 @ 0x40
800b58a: 81a3 strh r3, [r4, #12]
800b58c: e7e9 b.n 800b562 <__ssputs_r+0x8a>
...
0800b590 <_svfiprintf_r>:
800b590: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800b594: 4698 mov r8, r3
800b596: 898b ldrh r3, [r1, #12]
800b598: 4607 mov r7, r0
800b59a: 061b lsls r3, r3, #24
800b59c: 460d mov r5, r1
800b59e: 4614 mov r4, r2
800b5a0: b09d sub sp, #116 @ 0x74
800b5a2: d510 bpl.n 800b5c6 <_svfiprintf_r+0x36>
800b5a4: 690b ldr r3, [r1, #16]
800b5a6: b973 cbnz r3, 800b5c6 <_svfiprintf_r+0x36>
800b5a8: 2140 movs r1, #64 @ 0x40
800b5aa: f7ff ff09 bl 800b3c0 <_malloc_r>
800b5ae: 6028 str r0, [r5, #0]
800b5b0: 6128 str r0, [r5, #16]
800b5b2: b930 cbnz r0, 800b5c2 <_svfiprintf_r+0x32>
800b5b4: 230c movs r3, #12
800b5b6: 603b str r3, [r7, #0]
800b5b8: f04f 30ff mov.w r0, #4294967295
800b5bc: b01d add sp, #116 @ 0x74
800b5be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800b5c2: 2340 movs r3, #64 @ 0x40
800b5c4: 616b str r3, [r5, #20]
800b5c6: 2300 movs r3, #0
800b5c8: 9309 str r3, [sp, #36] @ 0x24
800b5ca: 2320 movs r3, #32
800b5cc: f88d 3029 strb.w r3, [sp, #41] @ 0x29
800b5d0: 2330 movs r3, #48 @ 0x30
800b5d2: f04f 0901 mov.w r9, #1
800b5d6: f8cd 800c str.w r8, [sp, #12]
800b5da: f8df 8198 ldr.w r8, [pc, #408] @ 800b774 <_svfiprintf_r+0x1e4>
800b5de: f88d 302a strb.w r3, [sp, #42] @ 0x2a
800b5e2: 4623 mov r3, r4
800b5e4: 469a mov sl, r3
800b5e6: f813 2b01 ldrb.w r2, [r3], #1
800b5ea: b10a cbz r2, 800b5f0 <_svfiprintf_r+0x60>
800b5ec: 2a25 cmp r2, #37 @ 0x25
800b5ee: d1f9 bne.n 800b5e4 <_svfiprintf_r+0x54>
800b5f0: ebba 0b04 subs.w fp, sl, r4
800b5f4: d00b beq.n 800b60e <_svfiprintf_r+0x7e>
800b5f6: 465b mov r3, fp
800b5f8: 4622 mov r2, r4
800b5fa: 4629 mov r1, r5
800b5fc: 4638 mov r0, r7
800b5fe: f7ff ff6b bl 800b4d8 <__ssputs_r>
800b602: 3001 adds r0, #1
800b604: f000 80a7 beq.w 800b756 <_svfiprintf_r+0x1c6>
800b608: 9a09 ldr r2, [sp, #36] @ 0x24
800b60a: 445a add r2, fp
800b60c: 9209 str r2, [sp, #36] @ 0x24
800b60e: f89a 3000 ldrb.w r3, [sl]
800b612: 2b00 cmp r3, #0
800b614: f000 809f beq.w 800b756 <_svfiprintf_r+0x1c6>
800b618: 2300 movs r3, #0
800b61a: f04f 32ff mov.w r2, #4294967295
800b61e: e9cd 2305 strd r2, r3, [sp, #20]
800b622: f10a 0a01 add.w sl, sl, #1
800b626: 9304 str r3, [sp, #16]
800b628: 9307 str r3, [sp, #28]
800b62a: f88d 3053 strb.w r3, [sp, #83] @ 0x53
800b62e: 931a str r3, [sp, #104] @ 0x68
800b630: 4654 mov r4, sl
800b632: 2205 movs r2, #5
800b634: f814 1b01 ldrb.w r1, [r4], #1
800b638: 484e ldr r0, [pc, #312] @ (800b774 <_svfiprintf_r+0x1e4>)
800b63a: f000 fa5f bl 800bafc <memchr>
800b63e: 9a04 ldr r2, [sp, #16]
800b640: b9d8 cbnz r0, 800b67a <_svfiprintf_r+0xea>
800b642: 06d0 lsls r0, r2, #27
800b644: bf44 itt mi
800b646: 2320 movmi r3, #32
800b648: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800b64c: 0711 lsls r1, r2, #28
800b64e: bf44 itt mi
800b650: 232b movmi r3, #43 @ 0x2b
800b652: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800b656: f89a 3000 ldrb.w r3, [sl]
800b65a: 2b2a cmp r3, #42 @ 0x2a
800b65c: d015 beq.n 800b68a <_svfiprintf_r+0xfa>
800b65e: 4654 mov r4, sl
800b660: 2000 movs r0, #0
800b662: f04f 0c0a mov.w ip, #10
800b666: 9a07 ldr r2, [sp, #28]
800b668: 4621 mov r1, r4
800b66a: f811 3b01 ldrb.w r3, [r1], #1
800b66e: 3b30 subs r3, #48 @ 0x30
800b670: 2b09 cmp r3, #9
800b672: d94b bls.n 800b70c <_svfiprintf_r+0x17c>
800b674: b1b0 cbz r0, 800b6a4 <_svfiprintf_r+0x114>
800b676: 9207 str r2, [sp, #28]
800b678: e014 b.n 800b6a4 <_svfiprintf_r+0x114>
800b67a: eba0 0308 sub.w r3, r0, r8
800b67e: fa09 f303 lsl.w r3, r9, r3
800b682: 4313 orrs r3, r2
800b684: 46a2 mov sl, r4
800b686: 9304 str r3, [sp, #16]
800b688: e7d2 b.n 800b630 <_svfiprintf_r+0xa0>
800b68a: 9b03 ldr r3, [sp, #12]
800b68c: 1d19 adds r1, r3, #4
800b68e: 681b ldr r3, [r3, #0]
800b690: 9103 str r1, [sp, #12]
800b692: 2b00 cmp r3, #0
800b694: bfbb ittet lt
800b696: 425b neglt r3, r3
800b698: f042 0202 orrlt.w r2, r2, #2
800b69c: 9307 strge r3, [sp, #28]
800b69e: 9307 strlt r3, [sp, #28]
800b6a0: bfb8 it lt
800b6a2: 9204 strlt r2, [sp, #16]
800b6a4: 7823 ldrb r3, [r4, #0]
800b6a6: 2b2e cmp r3, #46 @ 0x2e
800b6a8: d10a bne.n 800b6c0 <_svfiprintf_r+0x130>
800b6aa: 7863 ldrb r3, [r4, #1]
800b6ac: 2b2a cmp r3, #42 @ 0x2a
800b6ae: d132 bne.n 800b716 <_svfiprintf_r+0x186>
800b6b0: 9b03 ldr r3, [sp, #12]
800b6b2: 3402 adds r4, #2
800b6b4: 1d1a adds r2, r3, #4
800b6b6: 681b ldr r3, [r3, #0]
800b6b8: 9203 str r2, [sp, #12]
800b6ba: ea43 73e3 orr.w r3, r3, r3, asr #31
800b6be: 9305 str r3, [sp, #20]
800b6c0: f8df a0b4 ldr.w sl, [pc, #180] @ 800b778 <_svfiprintf_r+0x1e8>
800b6c4: 2203 movs r2, #3
800b6c6: 4650 mov r0, sl
800b6c8: 7821 ldrb r1, [r4, #0]
800b6ca: f000 fa17 bl 800bafc <memchr>
800b6ce: b138 cbz r0, 800b6e0 <_svfiprintf_r+0x150>
800b6d0: 2240 movs r2, #64 @ 0x40
800b6d2: 9b04 ldr r3, [sp, #16]
800b6d4: eba0 000a sub.w r0, r0, sl
800b6d8: 4082 lsls r2, r0
800b6da: 4313 orrs r3, r2
800b6dc: 3401 adds r4, #1
800b6de: 9304 str r3, [sp, #16]
800b6e0: f814 1b01 ldrb.w r1, [r4], #1
800b6e4: 2206 movs r2, #6
800b6e6: 4825 ldr r0, [pc, #148] @ (800b77c <_svfiprintf_r+0x1ec>)
800b6e8: f88d 1028 strb.w r1, [sp, #40] @ 0x28
800b6ec: f000 fa06 bl 800bafc <memchr>
800b6f0: 2800 cmp r0, #0
800b6f2: d036 beq.n 800b762 <_svfiprintf_r+0x1d2>
800b6f4: 4b22 ldr r3, [pc, #136] @ (800b780 <_svfiprintf_r+0x1f0>)
800b6f6: bb1b cbnz r3, 800b740 <_svfiprintf_r+0x1b0>
800b6f8: 9b03 ldr r3, [sp, #12]
800b6fa: 3307 adds r3, #7
800b6fc: f023 0307 bic.w r3, r3, #7
800b700: 3308 adds r3, #8
800b702: 9303 str r3, [sp, #12]
800b704: 9b09 ldr r3, [sp, #36] @ 0x24
800b706: 4433 add r3, r6
800b708: 9309 str r3, [sp, #36] @ 0x24
800b70a: e76a b.n 800b5e2 <_svfiprintf_r+0x52>
800b70c: 460c mov r4, r1
800b70e: 2001 movs r0, #1
800b710: fb0c 3202 mla r2, ip, r2, r3
800b714: e7a8 b.n 800b668 <_svfiprintf_r+0xd8>
800b716: 2300 movs r3, #0
800b718: f04f 0c0a mov.w ip, #10
800b71c: 4619 mov r1, r3
800b71e: 3401 adds r4, #1
800b720: 9305 str r3, [sp, #20]
800b722: 4620 mov r0, r4
800b724: f810 2b01 ldrb.w r2, [r0], #1
800b728: 3a30 subs r2, #48 @ 0x30
800b72a: 2a09 cmp r2, #9
800b72c: d903 bls.n 800b736 <_svfiprintf_r+0x1a6>
800b72e: 2b00 cmp r3, #0
800b730: d0c6 beq.n 800b6c0 <_svfiprintf_r+0x130>
800b732: 9105 str r1, [sp, #20]
800b734: e7c4 b.n 800b6c0 <_svfiprintf_r+0x130>
800b736: 4604 mov r4, r0
800b738: 2301 movs r3, #1
800b73a: fb0c 2101 mla r1, ip, r1, r2
800b73e: e7f0 b.n 800b722 <_svfiprintf_r+0x192>
800b740: ab03 add r3, sp, #12
800b742: 9300 str r3, [sp, #0]
800b744: 462a mov r2, r5
800b746: 4638 mov r0, r7
800b748: 4b0e ldr r3, [pc, #56] @ (800b784 <_svfiprintf_r+0x1f4>)
800b74a: a904 add r1, sp, #16
800b74c: f3af 8000 nop.w
800b750: 1c42 adds r2, r0, #1
800b752: 4606 mov r6, r0
800b754: d1d6 bne.n 800b704 <_svfiprintf_r+0x174>
800b756: 89ab ldrh r3, [r5, #12]
800b758: 065b lsls r3, r3, #25
800b75a: f53f af2d bmi.w 800b5b8 <_svfiprintf_r+0x28>
800b75e: 9809 ldr r0, [sp, #36] @ 0x24
800b760: e72c b.n 800b5bc <_svfiprintf_r+0x2c>
800b762: ab03 add r3, sp, #12
800b764: 9300 str r3, [sp, #0]
800b766: 462a mov r2, r5
800b768: 4638 mov r0, r7
800b76a: 4b06 ldr r3, [pc, #24] @ (800b784 <_svfiprintf_r+0x1f4>)
800b76c: a904 add r1, sp, #16
800b76e: f000 f87d bl 800b86c <_printf_i>
800b772: e7ed b.n 800b750 <_svfiprintf_r+0x1c0>
800b774: 0800be4e .word 0x0800be4e
800b778: 0800be54 .word 0x0800be54
800b77c: 0800be58 .word 0x0800be58
800b780: 00000000 .word 0x00000000
800b784: 0800b4d9 .word 0x0800b4d9
0800b788 <_printf_common>:
800b788: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800b78c: 4616 mov r6, r2
800b78e: 4698 mov r8, r3
800b790: 688a ldr r2, [r1, #8]
800b792: 690b ldr r3, [r1, #16]
800b794: 4607 mov r7, r0
800b796: 4293 cmp r3, r2
800b798: bfb8 it lt
800b79a: 4613 movlt r3, r2
800b79c: 6033 str r3, [r6, #0]
800b79e: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
800b7a2: 460c mov r4, r1
800b7a4: f8dd 9020 ldr.w r9, [sp, #32]
800b7a8: b10a cbz r2, 800b7ae <_printf_common+0x26>
800b7aa: 3301 adds r3, #1
800b7ac: 6033 str r3, [r6, #0]
800b7ae: 6823 ldr r3, [r4, #0]
800b7b0: 0699 lsls r1, r3, #26
800b7b2: bf42 ittt mi
800b7b4: 6833 ldrmi r3, [r6, #0]
800b7b6: 3302 addmi r3, #2
800b7b8: 6033 strmi r3, [r6, #0]
800b7ba: 6825 ldr r5, [r4, #0]
800b7bc: f015 0506 ands.w r5, r5, #6
800b7c0: d106 bne.n 800b7d0 <_printf_common+0x48>
800b7c2: f104 0a19 add.w sl, r4, #25
800b7c6: 68e3 ldr r3, [r4, #12]
800b7c8: 6832 ldr r2, [r6, #0]
800b7ca: 1a9b subs r3, r3, r2
800b7cc: 42ab cmp r3, r5
800b7ce: dc2b bgt.n 800b828 <_printf_common+0xa0>
800b7d0: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
800b7d4: 6822 ldr r2, [r4, #0]
800b7d6: 3b00 subs r3, #0
800b7d8: bf18 it ne
800b7da: 2301 movne r3, #1
800b7dc: 0692 lsls r2, r2, #26
800b7de: d430 bmi.n 800b842 <_printf_common+0xba>
800b7e0: 4641 mov r1, r8
800b7e2: 4638 mov r0, r7
800b7e4: f104 0243 add.w r2, r4, #67 @ 0x43
800b7e8: 47c8 blx r9
800b7ea: 3001 adds r0, #1
800b7ec: d023 beq.n 800b836 <_printf_common+0xae>
800b7ee: 6823 ldr r3, [r4, #0]
800b7f0: 6922 ldr r2, [r4, #16]
800b7f2: f003 0306 and.w r3, r3, #6
800b7f6: 2b04 cmp r3, #4
800b7f8: bf14 ite ne
800b7fa: 2500 movne r5, #0
800b7fc: 6833 ldreq r3, [r6, #0]
800b7fe: f04f 0600 mov.w r6, #0
800b802: bf08 it eq
800b804: 68e5 ldreq r5, [r4, #12]
800b806: f104 041a add.w r4, r4, #26
800b80a: bf08 it eq
800b80c: 1aed subeq r5, r5, r3
800b80e: f854 3c12 ldr.w r3, [r4, #-18]
800b812: bf08 it eq
800b814: ea25 75e5 biceq.w r5, r5, r5, asr #31
800b818: 4293 cmp r3, r2
800b81a: bfc4 itt gt
800b81c: 1a9b subgt r3, r3, r2
800b81e: 18ed addgt r5, r5, r3
800b820: 42b5 cmp r5, r6
800b822: d11a bne.n 800b85a <_printf_common+0xd2>
800b824: 2000 movs r0, #0
800b826: e008 b.n 800b83a <_printf_common+0xb2>
800b828: 2301 movs r3, #1
800b82a: 4652 mov r2, sl
800b82c: 4641 mov r1, r8
800b82e: 4638 mov r0, r7
800b830: 47c8 blx r9
800b832: 3001 adds r0, #1
800b834: d103 bne.n 800b83e <_printf_common+0xb6>
800b836: f04f 30ff mov.w r0, #4294967295
800b83a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b83e: 3501 adds r5, #1
800b840: e7c1 b.n 800b7c6 <_printf_common+0x3e>
800b842: 2030 movs r0, #48 @ 0x30
800b844: 18e1 adds r1, r4, r3
800b846: f881 0043 strb.w r0, [r1, #67] @ 0x43
800b84a: 1c5a adds r2, r3, #1
800b84c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
800b850: 4422 add r2, r4
800b852: 3302 adds r3, #2
800b854: f882 1043 strb.w r1, [r2, #67] @ 0x43
800b858: e7c2 b.n 800b7e0 <_printf_common+0x58>
800b85a: 2301 movs r3, #1
800b85c: 4622 mov r2, r4
800b85e: 4641 mov r1, r8
800b860: 4638 mov r0, r7
800b862: 47c8 blx r9
800b864: 3001 adds r0, #1
800b866: d0e6 beq.n 800b836 <_printf_common+0xae>
800b868: 3601 adds r6, #1
800b86a: e7d9 b.n 800b820 <_printf_common+0x98>
0800b86c <_printf_i>:
800b86c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
800b870: 7e0f ldrb r7, [r1, #24]
800b872: 4691 mov r9, r2
800b874: 2f78 cmp r7, #120 @ 0x78
800b876: 4680 mov r8, r0
800b878: 460c mov r4, r1
800b87a: 469a mov sl, r3
800b87c: 9e0c ldr r6, [sp, #48] @ 0x30
800b87e: f101 0243 add.w r2, r1, #67 @ 0x43
800b882: d807 bhi.n 800b894 <_printf_i+0x28>
800b884: 2f62 cmp r7, #98 @ 0x62
800b886: d80a bhi.n 800b89e <_printf_i+0x32>
800b888: 2f00 cmp r7, #0
800b88a: f000 80d1 beq.w 800ba30 <_printf_i+0x1c4>
800b88e: 2f58 cmp r7, #88 @ 0x58
800b890: f000 80b8 beq.w 800ba04 <_printf_i+0x198>
800b894: f104 0642 add.w r6, r4, #66 @ 0x42
800b898: f884 7042 strb.w r7, [r4, #66] @ 0x42
800b89c: e03a b.n 800b914 <_printf_i+0xa8>
800b89e: f1a7 0363 sub.w r3, r7, #99 @ 0x63
800b8a2: 2b15 cmp r3, #21
800b8a4: d8f6 bhi.n 800b894 <_printf_i+0x28>
800b8a6: a101 add r1, pc, #4 @ (adr r1, 800b8ac <_printf_i+0x40>)
800b8a8: f851 f023 ldr.w pc, [r1, r3, lsl #2]
800b8ac: 0800b905 .word 0x0800b905
800b8b0: 0800b919 .word 0x0800b919
800b8b4: 0800b895 .word 0x0800b895
800b8b8: 0800b895 .word 0x0800b895
800b8bc: 0800b895 .word 0x0800b895
800b8c0: 0800b895 .word 0x0800b895
800b8c4: 0800b919 .word 0x0800b919
800b8c8: 0800b895 .word 0x0800b895
800b8cc: 0800b895 .word 0x0800b895
800b8d0: 0800b895 .word 0x0800b895
800b8d4: 0800b895 .word 0x0800b895
800b8d8: 0800ba17 .word 0x0800ba17
800b8dc: 0800b943 .word 0x0800b943
800b8e0: 0800b9d1 .word 0x0800b9d1
800b8e4: 0800b895 .word 0x0800b895
800b8e8: 0800b895 .word 0x0800b895
800b8ec: 0800ba39 .word 0x0800ba39
800b8f0: 0800b895 .word 0x0800b895
800b8f4: 0800b943 .word 0x0800b943
800b8f8: 0800b895 .word 0x0800b895
800b8fc: 0800b895 .word 0x0800b895
800b900: 0800b9d9 .word 0x0800b9d9
800b904: 6833 ldr r3, [r6, #0]
800b906: 1d1a adds r2, r3, #4
800b908: 681b ldr r3, [r3, #0]
800b90a: 6032 str r2, [r6, #0]
800b90c: f104 0642 add.w r6, r4, #66 @ 0x42
800b910: f884 3042 strb.w r3, [r4, #66] @ 0x42
800b914: 2301 movs r3, #1
800b916: e09c b.n 800ba52 <_printf_i+0x1e6>
800b918: 6833 ldr r3, [r6, #0]
800b91a: 6820 ldr r0, [r4, #0]
800b91c: 1d19 adds r1, r3, #4
800b91e: 6031 str r1, [r6, #0]
800b920: 0606 lsls r6, r0, #24
800b922: d501 bpl.n 800b928 <_printf_i+0xbc>
800b924: 681d ldr r5, [r3, #0]
800b926: e003 b.n 800b930 <_printf_i+0xc4>
800b928: 0645 lsls r5, r0, #25
800b92a: d5fb bpl.n 800b924 <_printf_i+0xb8>
800b92c: f9b3 5000 ldrsh.w r5, [r3]
800b930: 2d00 cmp r5, #0
800b932: da03 bge.n 800b93c <_printf_i+0xd0>
800b934: 232d movs r3, #45 @ 0x2d
800b936: 426d negs r5, r5
800b938: f884 3043 strb.w r3, [r4, #67] @ 0x43
800b93c: 230a movs r3, #10
800b93e: 4858 ldr r0, [pc, #352] @ (800baa0 <_printf_i+0x234>)
800b940: e011 b.n 800b966 <_printf_i+0xfa>
800b942: 6821 ldr r1, [r4, #0]
800b944: 6833 ldr r3, [r6, #0]
800b946: 0608 lsls r0, r1, #24
800b948: f853 5b04 ldr.w r5, [r3], #4
800b94c: d402 bmi.n 800b954 <_printf_i+0xe8>
800b94e: 0649 lsls r1, r1, #25
800b950: bf48 it mi
800b952: b2ad uxthmi r5, r5
800b954: 2f6f cmp r7, #111 @ 0x6f
800b956: 6033 str r3, [r6, #0]
800b958: bf14 ite ne
800b95a: 230a movne r3, #10
800b95c: 2308 moveq r3, #8
800b95e: 4850 ldr r0, [pc, #320] @ (800baa0 <_printf_i+0x234>)
800b960: 2100 movs r1, #0
800b962: f884 1043 strb.w r1, [r4, #67] @ 0x43
800b966: 6866 ldr r6, [r4, #4]
800b968: 2e00 cmp r6, #0
800b96a: 60a6 str r6, [r4, #8]
800b96c: db05 blt.n 800b97a <_printf_i+0x10e>
800b96e: 6821 ldr r1, [r4, #0]
800b970: 432e orrs r6, r5
800b972: f021 0104 bic.w r1, r1, #4
800b976: 6021 str r1, [r4, #0]
800b978: d04b beq.n 800ba12 <_printf_i+0x1a6>
800b97a: 4616 mov r6, r2
800b97c: fbb5 f1f3 udiv r1, r5, r3
800b980: fb03 5711 mls r7, r3, r1, r5
800b984: 5dc7 ldrb r7, [r0, r7]
800b986: f806 7d01 strb.w r7, [r6, #-1]!
800b98a: 462f mov r7, r5
800b98c: 42bb cmp r3, r7
800b98e: 460d mov r5, r1
800b990: d9f4 bls.n 800b97c <_printf_i+0x110>
800b992: 2b08 cmp r3, #8
800b994: d10b bne.n 800b9ae <_printf_i+0x142>
800b996: 6823 ldr r3, [r4, #0]
800b998: 07df lsls r7, r3, #31
800b99a: d508 bpl.n 800b9ae <_printf_i+0x142>
800b99c: 6923 ldr r3, [r4, #16]
800b99e: 6861 ldr r1, [r4, #4]
800b9a0: 4299 cmp r1, r3
800b9a2: bfde ittt le
800b9a4: 2330 movle r3, #48 @ 0x30
800b9a6: f806 3c01 strble.w r3, [r6, #-1]
800b9aa: f106 36ff addle.w r6, r6, #4294967295
800b9ae: 1b92 subs r2, r2, r6
800b9b0: 6122 str r2, [r4, #16]
800b9b2: 464b mov r3, r9
800b9b4: 4621 mov r1, r4
800b9b6: 4640 mov r0, r8
800b9b8: f8cd a000 str.w sl, [sp]
800b9bc: aa03 add r2, sp, #12
800b9be: f7ff fee3 bl 800b788 <_printf_common>
800b9c2: 3001 adds r0, #1
800b9c4: d14a bne.n 800ba5c <_printf_i+0x1f0>
800b9c6: f04f 30ff mov.w r0, #4294967295
800b9ca: b004 add sp, #16
800b9cc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b9d0: 6823 ldr r3, [r4, #0]
800b9d2: f043 0320 orr.w r3, r3, #32
800b9d6: 6023 str r3, [r4, #0]
800b9d8: 2778 movs r7, #120 @ 0x78
800b9da: 4832 ldr r0, [pc, #200] @ (800baa4 <_printf_i+0x238>)
800b9dc: f884 7045 strb.w r7, [r4, #69] @ 0x45
800b9e0: 6823 ldr r3, [r4, #0]
800b9e2: 6831 ldr r1, [r6, #0]
800b9e4: 061f lsls r7, r3, #24
800b9e6: f851 5b04 ldr.w r5, [r1], #4
800b9ea: d402 bmi.n 800b9f2 <_printf_i+0x186>
800b9ec: 065f lsls r7, r3, #25
800b9ee: bf48 it mi
800b9f0: b2ad uxthmi r5, r5
800b9f2: 6031 str r1, [r6, #0]
800b9f4: 07d9 lsls r1, r3, #31
800b9f6: bf44 itt mi
800b9f8: f043 0320 orrmi.w r3, r3, #32
800b9fc: 6023 strmi r3, [r4, #0]
800b9fe: b11d cbz r5, 800ba08 <_printf_i+0x19c>
800ba00: 2310 movs r3, #16
800ba02: e7ad b.n 800b960 <_printf_i+0xf4>
800ba04: 4826 ldr r0, [pc, #152] @ (800baa0 <_printf_i+0x234>)
800ba06: e7e9 b.n 800b9dc <_printf_i+0x170>
800ba08: 6823 ldr r3, [r4, #0]
800ba0a: f023 0320 bic.w r3, r3, #32
800ba0e: 6023 str r3, [r4, #0]
800ba10: e7f6 b.n 800ba00 <_printf_i+0x194>
800ba12: 4616 mov r6, r2
800ba14: e7bd b.n 800b992 <_printf_i+0x126>
800ba16: 6833 ldr r3, [r6, #0]
800ba18: 6825 ldr r5, [r4, #0]
800ba1a: 1d18 adds r0, r3, #4
800ba1c: 6961 ldr r1, [r4, #20]
800ba1e: 6030 str r0, [r6, #0]
800ba20: 062e lsls r6, r5, #24
800ba22: 681b ldr r3, [r3, #0]
800ba24: d501 bpl.n 800ba2a <_printf_i+0x1be>
800ba26: 6019 str r1, [r3, #0]
800ba28: e002 b.n 800ba30 <_printf_i+0x1c4>
800ba2a: 0668 lsls r0, r5, #25
800ba2c: d5fb bpl.n 800ba26 <_printf_i+0x1ba>
800ba2e: 8019 strh r1, [r3, #0]
800ba30: 2300 movs r3, #0
800ba32: 4616 mov r6, r2
800ba34: 6123 str r3, [r4, #16]
800ba36: e7bc b.n 800b9b2 <_printf_i+0x146>
800ba38: 6833 ldr r3, [r6, #0]
800ba3a: 2100 movs r1, #0
800ba3c: 1d1a adds r2, r3, #4
800ba3e: 6032 str r2, [r6, #0]
800ba40: 681e ldr r6, [r3, #0]
800ba42: 6862 ldr r2, [r4, #4]
800ba44: 4630 mov r0, r6
800ba46: f000 f859 bl 800bafc <memchr>
800ba4a: b108 cbz r0, 800ba50 <_printf_i+0x1e4>
800ba4c: 1b80 subs r0, r0, r6
800ba4e: 6060 str r0, [r4, #4]
800ba50: 6863 ldr r3, [r4, #4]
800ba52: 6123 str r3, [r4, #16]
800ba54: 2300 movs r3, #0
800ba56: f884 3043 strb.w r3, [r4, #67] @ 0x43
800ba5a: e7aa b.n 800b9b2 <_printf_i+0x146>
800ba5c: 4632 mov r2, r6
800ba5e: 4649 mov r1, r9
800ba60: 4640 mov r0, r8
800ba62: 6923 ldr r3, [r4, #16]
800ba64: 47d0 blx sl
800ba66: 3001 adds r0, #1
800ba68: d0ad beq.n 800b9c6 <_printf_i+0x15a>
800ba6a: 6823 ldr r3, [r4, #0]
800ba6c: 079b lsls r3, r3, #30
800ba6e: d413 bmi.n 800ba98 <_printf_i+0x22c>
800ba70: 68e0 ldr r0, [r4, #12]
800ba72: 9b03 ldr r3, [sp, #12]
800ba74: 4298 cmp r0, r3
800ba76: bfb8 it lt
800ba78: 4618 movlt r0, r3
800ba7a: e7a6 b.n 800b9ca <_printf_i+0x15e>
800ba7c: 2301 movs r3, #1
800ba7e: 4632 mov r2, r6
800ba80: 4649 mov r1, r9
800ba82: 4640 mov r0, r8
800ba84: 47d0 blx sl
800ba86: 3001 adds r0, #1
800ba88: d09d beq.n 800b9c6 <_printf_i+0x15a>
800ba8a: 3501 adds r5, #1
800ba8c: 68e3 ldr r3, [r4, #12]
800ba8e: 9903 ldr r1, [sp, #12]
800ba90: 1a5b subs r3, r3, r1
800ba92: 42ab cmp r3, r5
800ba94: dcf2 bgt.n 800ba7c <_printf_i+0x210>
800ba96: e7eb b.n 800ba70 <_printf_i+0x204>
800ba98: 2500 movs r5, #0
800ba9a: f104 0619 add.w r6, r4, #25
800ba9e: e7f5 b.n 800ba8c <_printf_i+0x220>
800baa0: 0800be5f .word 0x0800be5f
800baa4: 0800be70 .word 0x0800be70
0800baa8 <memmove>:
800baa8: 4288 cmp r0, r1
800baaa: b510 push {r4, lr}
800baac: eb01 0402 add.w r4, r1, r2
800bab0: d902 bls.n 800bab8 <memmove+0x10>
800bab2: 4284 cmp r4, r0
800bab4: 4623 mov r3, r4
800bab6: d807 bhi.n 800bac8 <memmove+0x20>
800bab8: 1e43 subs r3, r0, #1
800baba: 42a1 cmp r1, r4
800babc: d008 beq.n 800bad0 <memmove+0x28>
800babe: f811 2b01 ldrb.w r2, [r1], #1
800bac2: f803 2f01 strb.w r2, [r3, #1]!
800bac6: e7f8 b.n 800baba <memmove+0x12>
800bac8: 4601 mov r1, r0
800baca: 4402 add r2, r0
800bacc: 428a cmp r2, r1
800bace: d100 bne.n 800bad2 <memmove+0x2a>
800bad0: bd10 pop {r4, pc}
800bad2: f813 4d01 ldrb.w r4, [r3, #-1]!
800bad6: f802 4d01 strb.w r4, [r2, #-1]!
800bada: e7f7 b.n 800bacc <memmove+0x24>
0800badc <_sbrk_r>:
800badc: b538 push {r3, r4, r5, lr}
800bade: 2300 movs r3, #0
800bae0: 4d05 ldr r5, [pc, #20] @ (800baf8 <_sbrk_r+0x1c>)
800bae2: 4604 mov r4, r0
800bae4: 4608 mov r0, r1
800bae6: 602b str r3, [r5, #0]
800bae8: f7f6 fabe bl 8002068 <_sbrk>
800baec: 1c43 adds r3, r0, #1
800baee: d102 bne.n 800baf6 <_sbrk_r+0x1a>
800baf0: 682b ldr r3, [r5, #0]
800baf2: b103 cbz r3, 800baf6 <_sbrk_r+0x1a>
800baf4: 6023 str r3, [r4, #0]
800baf6: bd38 pop {r3, r4, r5, pc}
800baf8: 2000180c .word 0x2000180c
0800bafc <memchr>:
800bafc: 4603 mov r3, r0
800bafe: b510 push {r4, lr}
800bb00: b2c9 uxtb r1, r1
800bb02: 4402 add r2, r0
800bb04: 4293 cmp r3, r2
800bb06: 4618 mov r0, r3
800bb08: d101 bne.n 800bb0e <memchr+0x12>
800bb0a: 2000 movs r0, #0
800bb0c: e003 b.n 800bb16 <memchr+0x1a>
800bb0e: 7804 ldrb r4, [r0, #0]
800bb10: 3301 adds r3, #1
800bb12: 428c cmp r4, r1
800bb14: d1f6 bne.n 800bb04 <memchr+0x8>
800bb16: bd10 pop {r4, pc}
0800bb18 <memcpy>:
800bb18: 440a add r2, r1
800bb1a: 4291 cmp r1, r2
800bb1c: f100 33ff add.w r3, r0, #4294967295
800bb20: d100 bne.n 800bb24 <memcpy+0xc>
800bb22: 4770 bx lr
800bb24: b510 push {r4, lr}
800bb26: f811 4b01 ldrb.w r4, [r1], #1
800bb2a: 4291 cmp r1, r2
800bb2c: f803 4f01 strb.w r4, [r3, #1]!
800bb30: d1f9 bne.n 800bb26 <memcpy+0xe>
800bb32: bd10 pop {r4, pc}
0800bb34 <_realloc_r>:
800bb34: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800bb38: 4607 mov r7, r0
800bb3a: 4614 mov r4, r2
800bb3c: 460d mov r5, r1
800bb3e: b921 cbnz r1, 800bb4a <_realloc_r+0x16>
800bb40: 4611 mov r1, r2
800bb42: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
800bb46: f7ff bc3b b.w 800b3c0 <_malloc_r>
800bb4a: b92a cbnz r2, 800bb58 <_realloc_r+0x24>
800bb4c: f7ff fbce bl 800b2ec <_free_r>
800bb50: 4625 mov r5, r4
800bb52: 4628 mov r0, r5
800bb54: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
800bb58: f000 f81a bl 800bb90 <_malloc_usable_size_r>
800bb5c: 4284 cmp r4, r0
800bb5e: 4606 mov r6, r0
800bb60: d802 bhi.n 800bb68 <_realloc_r+0x34>
800bb62: ebb4 0f50 cmp.w r4, r0, lsr #1
800bb66: d8f4 bhi.n 800bb52 <_realloc_r+0x1e>
800bb68: 4621 mov r1, r4
800bb6a: 4638 mov r0, r7
800bb6c: f7ff fc28 bl 800b3c0 <_malloc_r>
800bb70: 4680 mov r8, r0
800bb72: b908 cbnz r0, 800bb78 <_realloc_r+0x44>
800bb74: 4645 mov r5, r8
800bb76: e7ec b.n 800bb52 <_realloc_r+0x1e>
800bb78: 42b4 cmp r4, r6
800bb7a: 4622 mov r2, r4
800bb7c: 4629 mov r1, r5
800bb7e: bf28 it cs
800bb80: 4632 movcs r2, r6
800bb82: f7ff ffc9 bl 800bb18 <memcpy>
800bb86: 4629 mov r1, r5
800bb88: 4638 mov r0, r7
800bb8a: f7ff fbaf bl 800b2ec <_free_r>
800bb8e: e7f1 b.n 800bb74 <_realloc_r+0x40>
0800bb90 <_malloc_usable_size_r>:
800bb90: f851 3c04 ldr.w r3, [r1, #-4]
800bb94: 1f18 subs r0, r3, #4
800bb96: 2b00 cmp r3, #0
800bb98: bfbc itt lt
800bb9a: 580b ldrlt r3, [r1, r0]
800bb9c: 18c0 addlt r0, r0, r3
800bb9e: 4770 bx lr
0800bba0 <_init>:
800bba0: b5f8 push {r3, r4, r5, r6, r7, lr}
800bba2: bf00 nop
800bba4: bcf8 pop {r3, r4, r5, r6, r7}
800bba6: bc08 pop {r3}
800bba8: 469e mov lr, r3
800bbaa: 4770 bx lr
0800bbac <_fini>:
800bbac: b5f8 push {r3, r4, r5, r6, r7, lr}
800bbae: bf00 nop
800bbb0: bcf8 pop {r3, r4, r5, r6, r7}
800bbb2: bc08 pop {r3}
800bbb4: 469e mov lr, r3
800bbb6: 4770 bx lr
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