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43a9a9d480996d7faa1ea6d1fee47bdb6eb179c1
AUTOM/workspace/AUTOM10/Debug/AUTOM10.list
andrea 43a9a9d480 wip
2025-12-08 16:43:26 +01:00

29155 lines
1.1 MiB
Raw Blame History

AUTOM10.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000ba7c 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000002c0 0800bb88 0800bb88 0000cb88 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800be48 0800be48 0000d1d0 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800be48 0800be48 0000ce48 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800be50 0800be50 0000d1d0 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800be50 0800be50 0000ce50 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800be54 0800be54 0000ce54 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 000001d0 20000000 0800be58 0000d000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000164c 200001d0 0800c028 0000d1d0 2**3
ALLOC
10 ._user_heap_stack 00000604 2000181c 0800c028 0000d81c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000d1d0 2**0
CONTENTS, READONLY
12 .debug_info 000184fb 00000000 00000000 0000d1f9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000452e 00000000 00000000 000256f4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000015f8 00000000 00000000 00029c28 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000010d9 00000000 00000000 0002b220 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001c730 00000000 00000000 0002c2f9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001cc76 00000000 00000000 00048a29 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00095753 00000000 00000000 0006569f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000fadf2 2**0
CONTENTS, READONLY
20 .debug_frame 00005ef8 00000000 00000000 000fae38 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 00100d30 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 200001d0 .word 0x200001d0
8000128: 00000000 .word 0x00000000
800012c: 0800bb70 .word 0x0800bb70
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 200001d4 .word 0x200001d4
8000148: 0800bb70 .word 0x0800bb70
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <manageAdc>:
uint16_t ch5 ;
uint16_t ch6 ;
uint16_t ch7 ;
uint16_t ch8 ;
void manageAdc(void){
800015c: b480 push {r7}
800015e: af00 add r7, sp, #0
if (adc_avg_ready)
8000160: 4b12 ldr r3, [pc, #72] @ (80001ac <manageAdc+0x50>)
8000162: 781b ldrb r3, [r3, #0]
8000164: b2db uxtb r3, r3
8000166: 2b00 cmp r3, #0
8000168: d01b beq.n 80001a2 <manageAdc+0x46>
{
adc_avg_ready = 0;
800016a: 4b10 ldr r3, [pc, #64] @ (80001ac <manageAdc+0x50>)
800016c: 2200 movs r2, #0
800016e: 701a strb r2, [r3, #0]
// Read averaged channels (example mapping)
ch4 = adc_avg[0];
8000170: 4b0f ldr r3, [pc, #60] @ (80001b0 <manageAdc+0x54>)
8000172: 881b ldrh r3, [r3, #0]
8000174: b29a uxth r2, r3
8000176: 4b0f ldr r3, [pc, #60] @ (80001b4 <manageAdc+0x58>)
8000178: 801a strh r2, [r3, #0]
ch5 = adc_avg[1];
800017a: 4b0d ldr r3, [pc, #52] @ (80001b0 <manageAdc+0x54>)
800017c: 885b ldrh r3, [r3, #2]
800017e: b29a uxth r2, r3
8000180: 4b0d ldr r3, [pc, #52] @ (80001b8 <manageAdc+0x5c>)
8000182: 801a strh r2, [r3, #0]
ch6 = adc_avg[2];
8000184: 4b0a ldr r3, [pc, #40] @ (80001b0 <manageAdc+0x54>)
8000186: 889b ldrh r3, [r3, #4]
8000188: b29a uxth r2, r3
800018a: 4b0c ldr r3, [pc, #48] @ (80001bc <manageAdc+0x60>)
800018c: 801a strh r2, [r3, #0]
ch7 = adc_avg[3];
800018e: 4b08 ldr r3, [pc, #32] @ (80001b0 <manageAdc+0x54>)
8000190: 88db ldrh r3, [r3, #6]
8000192: b29a uxth r2, r3
8000194: 4b0a ldr r3, [pc, #40] @ (80001c0 <manageAdc+0x64>)
8000196: 801a strh r2, [r3, #0]
ch8 = adc_avg[4];
8000198: 4b05 ldr r3, [pc, #20] @ (80001b0 <manageAdc+0x54>)
800019a: 891b ldrh r3, [r3, #8]
800019c: b29a uxth r2, r3
800019e: 4b09 ldr r3, [pc, #36] @ (80001c4 <manageAdc+0x68>)
80001a0: 801a strh r2, [r3, #0]
// Use them (convert to volts, control, etc.)
// float v4 = (3.3f * ch4) / 4095.0f;
}
}
80001a2: bf00 nop
80001a4: 46bd mov sp, r7
80001a6: bc80 pop {r7}
80001a8: 4770 bx lr
80001aa: bf00 nop
80001ac: 20000219 .word 0x20000219
80001b0: 200001f8 .word 0x200001f8
80001b4: 2000021a .word 0x2000021a
80001b8: 2000021c .word 0x2000021c
80001bc: 2000021e .word 0x2000021e
80001c0: 20000220 .word 0x20000220
80001c4: 20000222 .word 0x20000222
080001c8 <readAdc>:
void readAdc(void){
80001c8: b480 push {r7}
80001ca: b083 sub sp, #12
80001cc: af00 add r7, sp, #0
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
80001ce: 2300 movs r3, #0
80001d0: 71fb strb r3, [r7, #7]
80001d2: e010 b.n 80001f6 <readAdc+0x2e>
{
adc_sum[i] += adc_dma_buf[i];
80001d4: 79fb ldrb r3, [r7, #7]
80001d6: 4a21 ldr r2, [pc, #132] @ (800025c <readAdc+0x94>)
80001d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80001dc: b299 uxth r1, r3
80001de: 79fb ldrb r3, [r7, #7]
80001e0: 4a1f ldr r2, [pc, #124] @ (8000260 <readAdc+0x98>)
80001e2: f852 2023 ldr.w r2, [r2, r3, lsl #2]
80001e6: 79fb ldrb r3, [r7, #7]
80001e8: 440a add r2, r1
80001ea: 491d ldr r1, [pc, #116] @ (8000260 <readAdc+0x98>)
80001ec: f841 2023 str.w r2, [r1, r3, lsl #2]
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
80001f0: 79fb ldrb r3, [r7, #7]
80001f2: 3301 adds r3, #1
80001f4: 71fb strb r3, [r7, #7]
80001f6: 79fb ldrb r3, [r7, #7]
80001f8: 2b04 cmp r3, #4
80001fa: d9eb bls.n 80001d4 <readAdc+0xc>
}
adc_sum_count++;
80001fc: 4b19 ldr r3, [pc, #100] @ (8000264 <readAdc+0x9c>)
80001fe: 781b ldrb r3, [r3, #0]
8000200: 3301 adds r3, #1
8000202: b2da uxtb r2, r3
8000204: 4b17 ldr r3, [pc, #92] @ (8000264 <readAdc+0x9c>)
8000206: 701a strb r2, [r3, #0]
/* When we collected ADC_AVG_WINDOW samples → compute average */
if (adc_sum_count >= ADC_AVG_WINDOW)
8000208: 4b16 ldr r3, [pc, #88] @ (8000264 <readAdc+0x9c>)
800020a: 781b ldrb r3, [r3, #0]
800020c: 2b04 cmp r3, #4
800020e: d920 bls.n 8000252 <readAdc+0x8a>
{
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
8000210: 2300 movs r3, #0
8000212: 71bb strb r3, [r7, #6]
8000214: e014 b.n 8000240 <readAdc+0x78>
{
adc_avg[i] = (uint16_t)(adc_sum[i] / ADC_AVG_WINDOW);
8000216: 79bb ldrb r3, [r7, #6]
8000218: 4a11 ldr r2, [pc, #68] @ (8000260 <readAdc+0x98>)
800021a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800021e: 4a12 ldr r2, [pc, #72] @ (8000268 <readAdc+0xa0>)
8000220: fba2 2303 umull r2, r3, r2, r3
8000224: 089a lsrs r2, r3, #2
8000226: 79bb ldrb r3, [r7, #6]
8000228: b291 uxth r1, r2
800022a: 4a10 ldr r2, [pc, #64] @ (800026c <readAdc+0xa4>)
800022c: f822 1013 strh.w r1, [r2, r3, lsl #1]
adc_sum[i] = 0;
8000230: 79bb ldrb r3, [r7, #6]
8000232: 4a0b ldr r2, [pc, #44] @ (8000260 <readAdc+0x98>)
8000234: 2100 movs r1, #0
8000236: f842 1023 str.w r1, [r2, r3, lsl #2]
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
800023a: 79bb ldrb r3, [r7, #6]
800023c: 3301 adds r3, #1
800023e: 71bb strb r3, [r7, #6]
8000240: 79bb ldrb r3, [r7, #6]
8000242: 2b04 cmp r3, #4
8000244: d9e7 bls.n 8000216 <readAdc+0x4e>
}
adc_sum_count = 0;
8000246: 4b07 ldr r3, [pc, #28] @ (8000264 <readAdc+0x9c>)
8000248: 2200 movs r2, #0
800024a: 701a strb r2, [r3, #0]
adc_avg_ready = 1; // tell main loop new data is ready
800024c: 4b08 ldr r3, [pc, #32] @ (8000270 <readAdc+0xa8>)
800024e: 2201 movs r2, #1
8000250: 701a strb r2, [r3, #0]
}
}
8000252: bf00 nop
8000254: 370c adds r7, #12
8000256: 46bd mov sp, r7
8000258: bc80 pop {r7}
800025a: 4770 bx lr
800025c: 200001ec .word 0x200001ec
8000260: 20000204 .word 0x20000204
8000264: 20000218 .word 0x20000218
8000268: cccccccd .word 0xcccccccd
800026c: 200001f8 .word 0x200001f8
8000270: 20000219 .word 0x20000219
08000274 <EEW_Read>:
uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data);
uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data);
/* Pseudo-array accessor EEW[idx] */
static inline uint16_t EEW_Read(uint8_t idx, uint16_t *value)
{
8000274: b580 push {r7, lr}
8000276: b082 sub sp, #8
8000278: af00 add r7, sp, #0
800027a: 4603 mov r3, r0
800027c: 6039 str r1, [r7, #0]
800027e: 71fb strb r3, [r7, #7]
return EE_ReadVariable(EEW_ADDR(idx), value);
8000280: 79fb ldrb r3, [r7, #7]
8000282: b29b uxth r3, r3
8000284: 3301 adds r3, #1
8000286: b29b uxth r3, r3
8000288: 6839 ldr r1, [r7, #0]
800028a: 4618 mov r0, r3
800028c: f000 feae bl 8000fec <EE_ReadVariable>
8000290: 4603 mov r3, r0
}
8000292: 4618 mov r0, r3
8000294: 3708 adds r7, #8
8000296: 46bd mov sp, r7
8000298: bd80 pop {r7, pc}
0800029a <EEW_Write>:
static inline uint16_t EEW_Write(uint8_t idx, uint16_t value)
{
800029a: b580 push {r7, lr}
800029c: b082 sub sp, #8
800029e: af00 add r7, sp, #0
80002a0: 4603 mov r3, r0
80002a2: 460a mov r2, r1
80002a4: 71fb strb r3, [r7, #7]
80002a6: 4613 mov r3, r2
80002a8: 80bb strh r3, [r7, #4]
return EE_WriteVariable(EEW_ADDR(idx), value);
80002aa: 79fb ldrb r3, [r7, #7]
80002ac: b29b uxth r3, r3
80002ae: 3301 adds r3, #1
80002b0: b29b uxth r3, r3
80002b2: 88ba ldrh r2, [r7, #4]
80002b4: 4611 mov r1, r2
80002b6: 4618 mov r0, r3
80002b8: f000 feb4 bl 8001024 <EE_WriteVariable>
80002bc: 4603 mov r3, r0
}
80002be: 4618 mov r0, r3
80002c0: 3708 adds r7, #8
80002c2: 46bd mov sp, r7
80002c4: bd80 pop {r7, pc}
080002c6 <toHex>:
extern uint16_t ch5 ;
extern uint16_t ch6 ;
extern uint16_t ch7 ;
extern uint16_t ch8 ;
bool toHex(char c1,char c2,char c3,char c4,uint16_t* retval){
80002c6: b490 push {r4, r7}
80002c8: b082 sub sp, #8
80002ca: af00 add r7, sp, #0
80002cc: 4604 mov r4, r0
80002ce: 4608 mov r0, r1
80002d0: 4611 mov r1, r2
80002d2: 461a mov r2, r3
80002d4: 4623 mov r3, r4
80002d6: 71fb strb r3, [r7, #7]
80002d8: 4603 mov r3, r0
80002da: 71bb strb r3, [r7, #6]
80002dc: 460b mov r3, r1
80002de: 717b strb r3, [r7, #5]
80002e0: 4613 mov r3, r2
80002e2: 713b strb r3, [r7, #4]
if((c1>='0')&&(c1<='9')){
80002e4: 79fb ldrb r3, [r7, #7]
80002e6: 2b2f cmp r3, #47 @ 0x2f
80002e8: d906 bls.n 80002f8 <toHex+0x32>
80002ea: 79fb ldrb r3, [r7, #7]
80002ec: 2b39 cmp r3, #57 @ 0x39
80002ee: d803 bhi.n 80002f8 <toHex+0x32>
c1-='0';
80002f0: 79fb ldrb r3, [r7, #7]
80002f2: 3b30 subs r3, #48 @ 0x30
80002f4: 71fb strb r3, [r7, #7]
80002f6: e00b b.n 8000310 <toHex+0x4a>
}else if((c1>='a')&&(c1<='f')){
80002f8: 79fb ldrb r3, [r7, #7]
80002fa: 2b60 cmp r3, #96 @ 0x60
80002fc: d906 bls.n 800030c <toHex+0x46>
80002fe: 79fb ldrb r3, [r7, #7]
8000300: 2b66 cmp r3, #102 @ 0x66
8000302: d803 bhi.n 800030c <toHex+0x46>
c1=(c1-'a')+10;
8000304: 79fb ldrb r3, [r7, #7]
8000306: 3b57 subs r3, #87 @ 0x57
8000308: 71fb strb r3, [r7, #7]
800030a: e001 b.n 8000310 <toHex+0x4a>
}else return false;
800030c: 2300 movs r3, #0
800030e: e070 b.n 80003f2 <toHex+0x12c>
if((c2>='0')&&(c2<='9')){
8000310: 79bb ldrb r3, [r7, #6]
8000312: 2b2f cmp r3, #47 @ 0x2f
8000314: d906 bls.n 8000324 <toHex+0x5e>
8000316: 79bb ldrb r3, [r7, #6]
8000318: 2b39 cmp r3, #57 @ 0x39
800031a: d803 bhi.n 8000324 <toHex+0x5e>
c2-='0';
800031c: 79bb ldrb r3, [r7, #6]
800031e: 3b30 subs r3, #48 @ 0x30
8000320: 71bb strb r3, [r7, #6]
8000322: e00b b.n 800033c <toHex+0x76>
}else if((c2>='a')&&(c2<='f')){
8000324: 79bb ldrb r3, [r7, #6]
8000326: 2b60 cmp r3, #96 @ 0x60
8000328: d906 bls.n 8000338 <toHex+0x72>
800032a: 79bb ldrb r3, [r7, #6]
800032c: 2b66 cmp r3, #102 @ 0x66
800032e: d803 bhi.n 8000338 <toHex+0x72>
c2=(c2-'a')+10;
8000330: 79bb ldrb r3, [r7, #6]
8000332: 3b57 subs r3, #87 @ 0x57
8000334: 71bb strb r3, [r7, #6]
8000336: e001 b.n 800033c <toHex+0x76>
}else return false;
8000338: 2300 movs r3, #0
800033a: e05a b.n 80003f2 <toHex+0x12c>
if((c3>='0')&&(c3<='9')){
800033c: 797b ldrb r3, [r7, #5]
800033e: 2b2f cmp r3, #47 @ 0x2f
8000340: d906 bls.n 8000350 <toHex+0x8a>
8000342: 797b ldrb r3, [r7, #5]
8000344: 2b39 cmp r3, #57 @ 0x39
8000346: d803 bhi.n 8000350 <toHex+0x8a>
c3-='0';
8000348: 797b ldrb r3, [r7, #5]
800034a: 3b30 subs r3, #48 @ 0x30
800034c: 717b strb r3, [r7, #5]
800034e: e00b b.n 8000368 <toHex+0xa2>
}else if((c3>='a')&&(c3<='f')){
8000350: 797b ldrb r3, [r7, #5]
8000352: 2b60 cmp r3, #96 @ 0x60
8000354: d906 bls.n 8000364 <toHex+0x9e>
8000356: 797b ldrb r3, [r7, #5]
8000358: 2b66 cmp r3, #102 @ 0x66
800035a: d803 bhi.n 8000364 <toHex+0x9e>
c3=(c3-'a')+10;
800035c: 797b ldrb r3, [r7, #5]
800035e: 3b57 subs r3, #87 @ 0x57
8000360: 717b strb r3, [r7, #5]
8000362: e001 b.n 8000368 <toHex+0xa2>
}else return false;
8000364: 2300 movs r3, #0
8000366: e044 b.n 80003f2 <toHex+0x12c>
if((c4>='0')&&(c4<='9')){
8000368: 793b ldrb r3, [r7, #4]
800036a: 2b2f cmp r3, #47 @ 0x2f
800036c: d906 bls.n 800037c <toHex+0xb6>
800036e: 793b ldrb r3, [r7, #4]
8000370: 2b39 cmp r3, #57 @ 0x39
8000372: d803 bhi.n 800037c <toHex+0xb6>
c4-='0';
8000374: 793b ldrb r3, [r7, #4]
8000376: 3b30 subs r3, #48 @ 0x30
8000378: 713b strb r3, [r7, #4]
800037a: e00b b.n 8000394 <toHex+0xce>
}else if((c4>='a')&&(c4<='f')){
800037c: 793b ldrb r3, [r7, #4]
800037e: 2b60 cmp r3, #96 @ 0x60
8000380: d906 bls.n 8000390 <toHex+0xca>
8000382: 793b ldrb r3, [r7, #4]
8000384: 2b66 cmp r3, #102 @ 0x66
8000386: d803 bhi.n 8000390 <toHex+0xca>
c4=(c4-'a')+10;
8000388: 793b ldrb r3, [r7, #4]
800038a: 3b57 subs r3, #87 @ 0x57
800038c: 713b strb r3, [r7, #4]
800038e: e001 b.n 8000394 <toHex+0xce>
}else return false;
8000390: 2300 movs r3, #0
8000392: e02e b.n 80003f2 <toHex+0x12c>
*retval=c1;
8000394: 79fb ldrb r3, [r7, #7]
8000396: b29a uxth r2, r3
8000398: 693b ldr r3, [r7, #16]
800039a: 801a strh r2, [r3, #0]
*retval*=16;
800039c: 693b ldr r3, [r7, #16]
800039e: 881b ldrh r3, [r3, #0]
80003a0: 011b lsls r3, r3, #4
80003a2: b29a uxth r2, r3
80003a4: 693b ldr r3, [r7, #16]
80003a6: 801a strh r2, [r3, #0]
*retval+=c2;
80003a8: 693b ldr r3, [r7, #16]
80003aa: 881a ldrh r2, [r3, #0]
80003ac: 79bb ldrb r3, [r7, #6]
80003ae: b29b uxth r3, r3
80003b0: 4413 add r3, r2
80003b2: b29a uxth r2, r3
80003b4: 693b ldr r3, [r7, #16]
80003b6: 801a strh r2, [r3, #0]
*retval*=16;
80003b8: 693b ldr r3, [r7, #16]
80003ba: 881b ldrh r3, [r3, #0]
80003bc: 011b lsls r3, r3, #4
80003be: b29a uxth r2, r3
80003c0: 693b ldr r3, [r7, #16]
80003c2: 801a strh r2, [r3, #0]
*retval+=c3;
80003c4: 693b ldr r3, [r7, #16]
80003c6: 881a ldrh r2, [r3, #0]
80003c8: 797b ldrb r3, [r7, #5]
80003ca: b29b uxth r3, r3
80003cc: 4413 add r3, r2
80003ce: b29a uxth r2, r3
80003d0: 693b ldr r3, [r7, #16]
80003d2: 801a strh r2, [r3, #0]
*retval*=16;
80003d4: 693b ldr r3, [r7, #16]
80003d6: 881b ldrh r3, [r3, #0]
80003d8: 011b lsls r3, r3, #4
80003da: b29a uxth r2, r3
80003dc: 693b ldr r3, [r7, #16]
80003de: 801a strh r2, [r3, #0]
*retval+=c4;
80003e0: 693b ldr r3, [r7, #16]
80003e2: 881a ldrh r2, [r3, #0]
80003e4: 793b ldrb r3, [r7, #4]
80003e6: b29b uxth r3, r3
80003e8: 4413 add r3, r2
80003ea: b29a uxth r2, r3
80003ec: 693b ldr r3, [r7, #16]
80003ee: 801a strh r2, [r3, #0]
return true;
80003f0: 2301 movs r3, #1
}
80003f2: 4618 mov r0, r3
80003f4: 3708 adds r7, #8
80003f6: 46bd mov sp, r7
80003f8: bc90 pop {r4, r7}
80003fa: 4770 bx lr
080003fc <manageCDC>:
void manageCDC(void){
80003fc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
8000400: b0a7 sub sp, #156 @ 0x9c
8000402: af06 add r7, sp, #24
uint16_t val;
uint16_t st;
uint16_t eeadd;
uint8_t i;
if (CDC_Available()) {
8000404: f00a fa50 bl 800a8a8 <CDC_Available>
8000408: 4603 mov r3, r0
800040a: 2b00 cmp r3, #0
800040c: f000 841a beq.w 8000c44 <manageCDC+0x848>
int rx = CDC_ReadByte();
8000410: f00a fa5e bl 800a8d0 <CDC_ReadByte>
8000414: 67b8 str r0, [r7, #120] @ 0x78
if (rx < 0) return;
8000416: 6fbb ldr r3, [r7, #120] @ 0x78
8000418: 2b00 cmp r3, #0
800041a: f2c0 8412 blt.w 8000c42 <manageCDC+0x846>
//uint8_t out = (uint8_t)c;
//if (out >= 'a' && out <= 'z') out -= 32; // to upper
rxbuf[rxidx]=rx;
800041e: 4b97 ldr r3, [pc, #604] @ (800067c <manageCDC+0x280>)
8000420: 781b ldrb r3, [r3, #0]
8000422: 461a mov r2, r3
8000424: 6fbb ldr r3, [r7, #120] @ 0x78
8000426: b2d9 uxtb r1, r3
8000428: 4b95 ldr r3, [pc, #596] @ (8000680 <manageCDC+0x284>)
800042a: 5499 strb r1, [r3, r2]
while (CDC_Transmit_FS(&rxbuf[rxidx], 1) == USBD_BUSY);//echo
800042c: bf00 nop
800042e: 4b93 ldr r3, [pc, #588] @ (800067c <manageCDC+0x280>)
8000430: 781b ldrb r3, [r3, #0]
8000432: 461a mov r2, r3
8000434: 4b92 ldr r3, [pc, #584] @ (8000680 <manageCDC+0x284>)
8000436: 4413 add r3, r2
8000438: 2101 movs r1, #1
800043a: 4618 mov r0, r3
800043c: f00a fb0a bl 800aa54 <CDC_Transmit_FS>
8000440: 4603 mov r3, r0
8000442: 2b01 cmp r3, #1
8000444: d0f3 beq.n 800042e <manageCDC+0x32>
if((rx==0x0d)||(rx==0x0a)){
8000446: 6fbb ldr r3, [r7, #120] @ 0x78
8000448: 2b0d cmp r3, #13
800044a: d003 beq.n 8000454 <manageCDC+0x58>
800044c: 6fbb ldr r3, [r7, #120] @ 0x78
800044e: 2b0a cmp r3, #10
8000450: f040 83f0 bne.w 8000c34 <manageCDC+0x838>
if(rxidx){
8000454: 4b89 ldr r3, [pc, #548] @ (800067c <manageCDC+0x280>)
8000456: 781b ldrb r3, [r3, #0]
8000458: 2b00 cmp r3, #0
800045a: f000 83e7 beq.w 8000c2c <manageCDC+0x830>
switch(rxbuf[0]){
800045e: 4b88 ldr r3, [pc, #544] @ (8000680 <manageCDC+0x284>)
8000460: 781b ldrb r3, [r3, #0]
8000462: 2b6d cmp r3, #109 @ 0x6d
8000464: f000 80cf beq.w 8000606 <manageCDC+0x20a>
8000468: 2b6d cmp r3, #109 @ 0x6d
800046a: f300 83ce bgt.w 8000c0a <manageCDC+0x80e>
800046e: 2b65 cmp r3, #101 @ 0x65
8000470: f000 81fc beq.w 800086c <manageCDC+0x470>
8000474: 2b69 cmp r3, #105 @ 0x69
8000476: f040 83c8 bne.w 8000c0a <manageCDC+0x80e>
case 'i':
sprintf((char*)s,"\ninfo");
800047a: f107 030c add.w r3, r7, #12
800047e: 4981 ldr r1, [pc, #516] @ (8000684 <manageCDC+0x288>)
8000480: 4618 mov r0, r3
8000482: f00a fec5 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, 5) == USBD_BUSY);
8000486: bf00 nop
8000488: f107 030c add.w r3, r7, #12
800048c: 2105 movs r1, #5
800048e: 4618 mov r0, r3
8000490: f00a fae0 bl 800aa54 <CDC_Transmit_FS>
8000494: 4603 mov r3, r0
8000496: 2b01 cmp r3, #1
8000498: d0f6 beq.n 8000488 <manageCDC+0x8c>
sprintf((char*)s,"\npwm %d%d%d%d%d%d%d%d",IsPwmRunning(timMot1,FWMot1),IsPwmRunning(timMot1,BWMot1),IsPwmRunning(timMot2,FWMot2),IsPwmRunning(timMot2,BWMot2),IsPwmRunning(timMot3,FWMot3),IsPwmRunning(timMot3,BWMot3),IsPwmRunning(timMot4,FWMot4),IsPwmRunning(timMot4,BWMot4));
800049a: 2100 movs r1, #0
800049c: 487a ldr r0, [pc, #488] @ (8000688 <manageCDC+0x28c>)
800049e: f001 fa1f bl 80018e0 <IsPwmRunning>
80004a2: 4603 mov r3, r0
80004a4: 4698 mov r8, r3
80004a6: 2104 movs r1, #4
80004a8: 4877 ldr r0, [pc, #476] @ (8000688 <manageCDC+0x28c>)
80004aa: f001 fa19 bl 80018e0 <IsPwmRunning>
80004ae: 4603 mov r3, r0
80004b0: 4699 mov r9, r3
80004b2: 2108 movs r1, #8
80004b4: 4874 ldr r0, [pc, #464] @ (8000688 <manageCDC+0x28c>)
80004b6: f001 fa13 bl 80018e0 <IsPwmRunning>
80004ba: 4603 mov r3, r0
80004bc: 461c mov r4, r3
80004be: 210c movs r1, #12
80004c0: 4871 ldr r0, [pc, #452] @ (8000688 <manageCDC+0x28c>)
80004c2: f001 fa0d bl 80018e0 <IsPwmRunning>
80004c6: 4603 mov r3, r0
80004c8: 461d mov r5, r3
80004ca: 2100 movs r1, #0
80004cc: 486f ldr r0, [pc, #444] @ (800068c <manageCDC+0x290>)
80004ce: f001 fa07 bl 80018e0 <IsPwmRunning>
80004d2: 4603 mov r3, r0
80004d4: 461e mov r6, r3
80004d6: 2104 movs r1, #4
80004d8: 486c ldr r0, [pc, #432] @ (800068c <manageCDC+0x290>)
80004da: f001 fa01 bl 80018e0 <IsPwmRunning>
80004de: 4603 mov r3, r0
80004e0: 607b str r3, [r7, #4]
80004e2: 2108 movs r1, #8
80004e4: 4869 ldr r0, [pc, #420] @ (800068c <manageCDC+0x290>)
80004e6: f001 f9fb bl 80018e0 <IsPwmRunning>
80004ea: 4603 mov r3, r0
80004ec: 603b str r3, [r7, #0]
80004ee: 210c movs r1, #12
80004f0: 4866 ldr r0, [pc, #408] @ (800068c <manageCDC+0x290>)
80004f2: f001 f9f5 bl 80018e0 <IsPwmRunning>
80004f6: 4603 mov r3, r0
80004f8: f107 000c add.w r0, r7, #12
80004fc: 9305 str r3, [sp, #20]
80004fe: 683a ldr r2, [r7, #0]
8000500: 9204 str r2, [sp, #16]
8000502: 687b ldr r3, [r7, #4]
8000504: 9303 str r3, [sp, #12]
8000506: 9602 str r6, [sp, #8]
8000508: 9501 str r5, [sp, #4]
800050a: 9400 str r4, [sp, #0]
800050c: 464b mov r3, r9
800050e: 4642 mov r2, r8
8000510: 495f ldr r1, [pc, #380] @ (8000690 <manageCDC+0x294>)
8000512: f00a fe7d bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000516: bf00 nop
8000518: f107 030c add.w r3, r7, #12
800051c: 4618 mov r0, r3
800051e: f7ff fe15 bl 800014c <strlen>
8000522: 4603 mov r3, r0
8000524: b29a uxth r2, r3
8000526: f107 030c add.w r3, r7, #12
800052a: 4611 mov r1, r2
800052c: 4618 mov r0, r3
800052e: f00a fa91 bl 800aa54 <CDC_Transmit_FS>
8000532: 4603 mov r3, r0
8000534: 2b01 cmp r3, #1
8000536: d0ef beq.n 8000518 <manageCDC+0x11c>
sprintf((char*)s,"\n0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx",(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,FWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,BWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,FWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,BWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,FWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,BWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,FWMot4),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,BWMot4));
8000538: 4b53 ldr r3, [pc, #332] @ (8000688 <manageCDC+0x28c>)
800053a: 681b ldr r3, [r3, #0]
800053c: 6b5b ldr r3, [r3, #52] @ 0x34
800053e: 607b str r3, [r7, #4]
8000540: 4b51 ldr r3, [pc, #324] @ (8000688 <manageCDC+0x28c>)
8000542: 681b ldr r3, [r3, #0]
8000544: 6b99 ldr r1, [r3, #56] @ 0x38
8000546: 6039 str r1, [r7, #0]
8000548: 4b4f ldr r3, [pc, #316] @ (8000688 <manageCDC+0x28c>)
800054a: 681b ldr r3, [r3, #0]
800054c: 6bdb ldr r3, [r3, #60] @ 0x3c
800054e: 4a4e ldr r2, [pc, #312] @ (8000688 <manageCDC+0x28c>)
8000550: 6812 ldr r2, [r2, #0]
8000552: 6c12 ldr r2, [r2, #64] @ 0x40
8000554: 494d ldr r1, [pc, #308] @ (800068c <manageCDC+0x290>)
8000556: 6809 ldr r1, [r1, #0]
8000558: 6b49 ldr r1, [r1, #52] @ 0x34
800055a: 484c ldr r0, [pc, #304] @ (800068c <manageCDC+0x290>)
800055c: 6800 ldr r0, [r0, #0]
800055e: 6b80 ldr r0, [r0, #56] @ 0x38
8000560: 4c4a ldr r4, [pc, #296] @ (800068c <manageCDC+0x290>)
8000562: 6824 ldr r4, [r4, #0]
8000564: 6be4 ldr r4, [r4, #60] @ 0x3c
8000566: 4d49 ldr r5, [pc, #292] @ (800068c <manageCDC+0x290>)
8000568: 682d ldr r5, [r5, #0]
800056a: 6c2d ldr r5, [r5, #64] @ 0x40
800056c: f107 060c add.w r6, r7, #12
8000570: 9505 str r5, [sp, #20]
8000572: 9404 str r4, [sp, #16]
8000574: 9003 str r0, [sp, #12]
8000576: 9102 str r1, [sp, #8]
8000578: 9201 str r2, [sp, #4]
800057a: 9300 str r3, [sp, #0]
800057c: 683b ldr r3, [r7, #0]
800057e: 687a ldr r2, [r7, #4]
8000580: 4944 ldr r1, [pc, #272] @ (8000694 <manageCDC+0x298>)
8000582: 4630 mov r0, r6
8000584: f00a fe44 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000588: bf00 nop
800058a: f107 030c add.w r3, r7, #12
800058e: 4618 mov r0, r3
8000590: f7ff fddc bl 800014c <strlen>
8000594: 4603 mov r3, r0
8000596: b29a uxth r2, r3
8000598: f107 030c add.w r3, r7, #12
800059c: 4611 mov r1, r2
800059e: 4618 mov r0, r3
80005a0: f00a fa58 bl 800aa54 <CDC_Transmit_FS>
80005a4: 4603 mov r3, r0
80005a6: 2b01 cmp r3, #1
80005a8: d0ef beq.n 800058a <manageCDC+0x18e>
sprintf((char*)s,"\nP=0x%x ch4=%05d ch5=%05d ch6=%05d ch7=%05d ch8=%05d",pulsanti,ch4,ch5,ch6,ch7,ch8);
80005aa: 4b3b ldr r3, [pc, #236] @ (8000698 <manageCDC+0x29c>)
80005ac: 781b ldrb r3, [r3, #0]
80005ae: 461d mov r5, r3
80005b0: 4b3a ldr r3, [pc, #232] @ (800069c <manageCDC+0x2a0>)
80005b2: 881b ldrh r3, [r3, #0]
80005b4: 461e mov r6, r3
80005b6: 4b3a ldr r3, [pc, #232] @ (80006a0 <manageCDC+0x2a4>)
80005b8: 881b ldrh r3, [r3, #0]
80005ba: 461a mov r2, r3
80005bc: 4b39 ldr r3, [pc, #228] @ (80006a4 <manageCDC+0x2a8>)
80005be: 881b ldrh r3, [r3, #0]
80005c0: 4619 mov r1, r3
80005c2: 4b39 ldr r3, [pc, #228] @ (80006a8 <manageCDC+0x2ac>)
80005c4: 881b ldrh r3, [r3, #0]
80005c6: 461c mov r4, r3
80005c8: 4b38 ldr r3, [pc, #224] @ (80006ac <manageCDC+0x2b0>)
80005ca: 881b ldrh r3, [r3, #0]
80005cc: f107 000c add.w r0, r7, #12
80005d0: 9303 str r3, [sp, #12]
80005d2: 9402 str r4, [sp, #8]
80005d4: 9101 str r1, [sp, #4]
80005d6: 9200 str r2, [sp, #0]
80005d8: 4633 mov r3, r6
80005da: 462a mov r2, r5
80005dc: 4934 ldr r1, [pc, #208] @ (80006b0 <manageCDC+0x2b4>)
80005de: f00a fe17 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
80005e2: bf00 nop
80005e4: f107 030c add.w r3, r7, #12
80005e8: 4618 mov r0, r3
80005ea: f7ff fdaf bl 800014c <strlen>
80005ee: 4603 mov r3, r0
80005f0: b29a uxth r2, r3
80005f2: f107 030c add.w r3, r7, #12
80005f6: 4611 mov r1, r2
80005f8: 4618 mov r0, r3
80005fa: f00a fa2b bl 800aa54 <CDC_Transmit_FS>
80005fe: 4603 mov r3, r0
8000600: 2b01 cmp r3, #1
8000602: d0ef beq.n 80005e4 <manageCDC+0x1e8>
break;
8000604: e312 b.n 8000c2c <manageCDC+0x830>
case 'm':
if(rxidx==8){
8000606: 4b1d ldr r3, [pc, #116] @ (800067c <manageCDC+0x280>)
8000608: 781b ldrb r3, [r3, #0]
800060a: 2b08 cmp r3, #8
800060c: f040 811c bne.w 8000848 <manageCDC+0x44c>
if((rxbuf[1]>='1')&&(rxbuf[1]<='4')){
8000610: 4b1b ldr r3, [pc, #108] @ (8000680 <manageCDC+0x284>)
8000612: 785b ldrb r3, [r3, #1]
8000614: 2b30 cmp r3, #48 @ 0x30
8000616: f240 8106 bls.w 8000826 <manageCDC+0x42a>
800061a: 4b19 ldr r3, [pc, #100] @ (8000680 <manageCDC+0x284>)
800061c: 785b ldrb r3, [r3, #1]
800061e: 2b34 cmp r3, #52 @ 0x34
8000620: f200 8101 bhi.w 8000826 <manageCDC+0x42a>
mot=rxbuf[1]-='0';
8000624: 4b16 ldr r3, [pc, #88] @ (8000680 <manageCDC+0x284>)
8000626: 785b ldrb r3, [r3, #1]
8000628: 3b30 subs r3, #48 @ 0x30
800062a: b2da uxtb r2, r3
800062c: 4b14 ldr r3, [pc, #80] @ (8000680 <manageCDC+0x284>)
800062e: 705a strb r2, [r3, #1]
8000630: 4b13 ldr r3, [pc, #76] @ (8000680 <manageCDC+0x284>)
8000632: 785b ldrb r3, [r3, #1]
8000634: f887 3077 strb.w r3, [r7, #119] @ 0x77
if(rxbuf[2]=='f'){
8000638: 4b11 ldr r3, [pc, #68] @ (8000680 <manageCDC+0x284>)
800063a: 789b ldrb r3, [r3, #2]
800063c: 2b66 cmp r3, #102 @ 0x66
800063e: d103 bne.n 8000648 <manageCDC+0x24c>
dir=FW;
8000640: 2300 movs r3, #0
8000642: f887 307f strb.w r3, [r7, #127] @ 0x7f
8000646: e037 b.n 80006b8 <manageCDC+0x2bc>
}else if(rxbuf[2]=='b'){
8000648: 4b0d ldr r3, [pc, #52] @ (8000680 <manageCDC+0x284>)
800064a: 789b ldrb r3, [r3, #2]
800064c: 2b62 cmp r3, #98 @ 0x62
800064e: d103 bne.n 8000658 <manageCDC+0x25c>
dir=BW;
8000650: 2301 movs r3, #1
8000652: f887 307f strb.w r3, [r7, #127] @ 0x7f
8000656: e02f b.n 80006b8 <manageCDC+0x2bc>
}else{
sprintf((char*)s,"\n?mnsvvvvv s=f|b");//m nmotore senso valore
8000658: f107 030c add.w r3, r7, #12
800065c: 4915 ldr r1, [pc, #84] @ (80006b4 <manageCDC+0x2b8>)
800065e: 4618 mov r0, r3
8000660: f00a fdd6 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, 16) == USBD_BUSY);
8000664: bf00 nop
8000666: f107 030c add.w r3, r7, #12
800066a: 2110 movs r1, #16
800066c: 4618 mov r0, r3
800066e: f00a f9f1 bl 800aa54 <CDC_Transmit_FS>
8000672: 4603 mov r3, r0
8000674: 2b01 cmp r3, #1
8000676: d0f6 beq.n 8000666 <manageCDC+0x26a>
break;
8000678: e2d8 b.n 8000c2c <manageCDC+0x830>
800067a: bf00 nop
800067c: 20000224 .word 0x20000224
8000680: 20000228 .word 0x20000228
8000684: 0800bb88 .word 0x0800bb88
8000688: 20000300 .word 0x20000300
800068c: 20000348 .word 0x20000348
8000690: 0800bb90 .word 0x0800bb90
8000694: 0800bba8 .word 0x0800bba8
8000698: 200003d8 .word 0x200003d8
800069c: 2000021a .word 0x2000021a
80006a0: 2000021c .word 0x2000021c
80006a4: 2000021e .word 0x2000021e
80006a8: 20000220 .word 0x20000220
80006ac: 20000222 .word 0x20000222
80006b0: 0800bbdc .word 0x0800bbdc
80006b4: 0800bc14 .word 0x0800bc14
}
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
80006b8: 4bb4 ldr r3, [pc, #720] @ (800098c <manageCDC+0x590>)
80006ba: 78db ldrb r3, [r3, #3]
80006bc: 2b2f cmp r3, #47 @ 0x2f
80006be: f240 80a1 bls.w 8000804 <manageCDC+0x408>
80006c2: 4bb2 ldr r3, [pc, #712] @ (800098c <manageCDC+0x590>)
80006c4: 78db ldrb r3, [r3, #3]
80006c6: 2b39 cmp r3, #57 @ 0x39
80006c8: f200 809c bhi.w 8000804 <manageCDC+0x408>
80006cc: 4baf ldr r3, [pc, #700] @ (800098c <manageCDC+0x590>)
80006ce: 791b ldrb r3, [r3, #4]
80006d0: 2b2f cmp r3, #47 @ 0x2f
80006d2: f240 8097 bls.w 8000804 <manageCDC+0x408>
80006d6: 4bad ldr r3, [pc, #692] @ (800098c <manageCDC+0x590>)
80006d8: 791b ldrb r3, [r3, #4]
80006da: 2b39 cmp r3, #57 @ 0x39
80006dc: f200 8092 bhi.w 8000804 <manageCDC+0x408>
80006e0: 4baa ldr r3, [pc, #680] @ (800098c <manageCDC+0x590>)
80006e2: 795b ldrb r3, [r3, #5]
80006e4: 2b2f cmp r3, #47 @ 0x2f
80006e6: f240 808d bls.w 8000804 <manageCDC+0x408>
80006ea: 4ba8 ldr r3, [pc, #672] @ (800098c <manageCDC+0x590>)
80006ec: 795b ldrb r3, [r3, #5]
80006ee: 2b39 cmp r3, #57 @ 0x39
80006f0: f200 8088 bhi.w 8000804 <manageCDC+0x408>
80006f4: 4ba5 ldr r3, [pc, #660] @ (800098c <manageCDC+0x590>)
80006f6: 799b ldrb r3, [r3, #6]
80006f8: 2b2f cmp r3, #47 @ 0x2f
80006fa: f240 8083 bls.w 8000804 <manageCDC+0x408>
80006fe: 4ba3 ldr r3, [pc, #652] @ (800098c <manageCDC+0x590>)
8000700: 799b ldrb r3, [r3, #6]
8000702: 2b39 cmp r3, #57 @ 0x39
8000704: d87e bhi.n 8000804 <manageCDC+0x408>
8000706: 4ba1 ldr r3, [pc, #644] @ (800098c <manageCDC+0x590>)
8000708: 79db ldrb r3, [r3, #7]
800070a: 2b2f cmp r3, #47 @ 0x2f
800070c: d97a bls.n 8000804 <manageCDC+0x408>
800070e: 4b9f ldr r3, [pc, #636] @ (800098c <manageCDC+0x590>)
8000710: 79db ldrb r3, [r3, #7]
8000712: 2b39 cmp r3, #57 @ 0x39
8000714: d876 bhi.n 8000804 <manageCDC+0x408>
dm=rxbuf[3]-='0';
8000716: 4b9d ldr r3, [pc, #628] @ (800098c <manageCDC+0x590>)
8000718: 78db ldrb r3, [r3, #3]
800071a: 3b30 subs r3, #48 @ 0x30
800071c: b2da uxtb r2, r3
800071e: 4b9b ldr r3, [pc, #620] @ (800098c <manageCDC+0x590>)
8000720: 70da strb r2, [r3, #3]
8000722: 4b9a ldr r3, [pc, #616] @ (800098c <manageCDC+0x590>)
8000724: 78db ldrb r3, [r3, #3]
8000726: f887 3076 strb.w r3, [r7, #118] @ 0x76
m=rxbuf[4]-='0';
800072a: 4b98 ldr r3, [pc, #608] @ (800098c <manageCDC+0x590>)
800072c: 791b ldrb r3, [r3, #4]
800072e: 3b30 subs r3, #48 @ 0x30
8000730: b2da uxtb r2, r3
8000732: 4b96 ldr r3, [pc, #600] @ (800098c <manageCDC+0x590>)
8000734: 711a strb r2, [r3, #4]
8000736: 4b95 ldr r3, [pc, #596] @ (800098c <manageCDC+0x590>)
8000738: 791b ldrb r3, [r3, #4]
800073a: f887 3075 strb.w r3, [r7, #117] @ 0x75
c=rxbuf[5]-='0';
800073e: 4b93 ldr r3, [pc, #588] @ (800098c <manageCDC+0x590>)
8000740: 795b ldrb r3, [r3, #5]
8000742: 3b30 subs r3, #48 @ 0x30
8000744: b2da uxtb r2, r3
8000746: 4b91 ldr r3, [pc, #580] @ (800098c <manageCDC+0x590>)
8000748: 715a strb r2, [r3, #5]
800074a: 4b90 ldr r3, [pc, #576] @ (800098c <manageCDC+0x590>)
800074c: 795b ldrb r3, [r3, #5]
800074e: f887 3074 strb.w r3, [r7, #116] @ 0x74
d=rxbuf[6]-='0';
8000752: 4b8e ldr r3, [pc, #568] @ (800098c <manageCDC+0x590>)
8000754: 799b ldrb r3, [r3, #6]
8000756: 3b30 subs r3, #48 @ 0x30
8000758: b2da uxtb r2, r3
800075a: 4b8c ldr r3, [pc, #560] @ (800098c <manageCDC+0x590>)
800075c: 719a strb r2, [r3, #6]
800075e: 4b8b ldr r3, [pc, #556] @ (800098c <manageCDC+0x590>)
8000760: 799b ldrb r3, [r3, #6]
8000762: f887 3073 strb.w r3, [r7, #115] @ 0x73
u=rxbuf[7]-='0';
8000766: 4b89 ldr r3, [pc, #548] @ (800098c <manageCDC+0x590>)
8000768: 79db ldrb r3, [r3, #7]
800076a: 3b30 subs r3, #48 @ 0x30
800076c: b2da uxtb r2, r3
800076e: 4b87 ldr r3, [pc, #540] @ (800098c <manageCDC+0x590>)
8000770: 71da strb r2, [r3, #7]
8000772: 4b86 ldr r3, [pc, #536] @ (800098c <manageCDC+0x590>)
8000774: 79db ldrb r3, [r3, #7]
8000776: f887 3072 strb.w r3, [r7, #114] @ 0x72
val=dm;
800077a: f897 3076 ldrb.w r3, [r7, #118] @ 0x76
800077e: b29b uxth r3, r3
8000780: 817b strh r3, [r7, #10]
val*=10;
8000782: 897b ldrh r3, [r7, #10]
8000784: 461a mov r2, r3
8000786: 0092 lsls r2, r2, #2
8000788: 4413 add r3, r2
800078a: 005b lsls r3, r3, #1
800078c: b29b uxth r3, r3
800078e: 817b strh r3, [r7, #10]
val+=m;
8000790: f897 3075 ldrb.w r3, [r7, #117] @ 0x75
8000794: b29a uxth r2, r3
8000796: 897b ldrh r3, [r7, #10]
8000798: 4413 add r3, r2
800079a: b29b uxth r3, r3
800079c: 817b strh r3, [r7, #10]
val*=10;
800079e: 897b ldrh r3, [r7, #10]
80007a0: 461a mov r2, r3
80007a2: 0092 lsls r2, r2, #2
80007a4: 4413 add r3, r2
80007a6: 005b lsls r3, r3, #1
80007a8: b29b uxth r3, r3
80007aa: 817b strh r3, [r7, #10]
val+=c;
80007ac: f897 3074 ldrb.w r3, [r7, #116] @ 0x74
80007b0: b29a uxth r2, r3
80007b2: 897b ldrh r3, [r7, #10]
80007b4: 4413 add r3, r2
80007b6: b29b uxth r3, r3
80007b8: 817b strh r3, [r7, #10]
val*=10;
80007ba: 897b ldrh r3, [r7, #10]
80007bc: 461a mov r2, r3
80007be: 0092 lsls r2, r2, #2
80007c0: 4413 add r3, r2
80007c2: 005b lsls r3, r3, #1
80007c4: b29b uxth r3, r3
80007c6: 817b strh r3, [r7, #10]
val+=d;
80007c8: f897 3073 ldrb.w r3, [r7, #115] @ 0x73
80007cc: b29a uxth r2, r3
80007ce: 897b ldrh r3, [r7, #10]
80007d0: 4413 add r3, r2
80007d2: b29b uxth r3, r3
80007d4: 817b strh r3, [r7, #10]
val*=10;
80007d6: 897b ldrh r3, [r7, #10]
80007d8: 461a mov r2, r3
80007da: 0092 lsls r2, r2, #2
80007dc: 4413 add r3, r2
80007de: 005b lsls r3, r3, #1
80007e0: b29b uxth r3, r3
80007e2: 817b strh r3, [r7, #10]
val+=u;
80007e4: f897 3072 ldrb.w r3, [r7, #114] @ 0x72
80007e8: b29a uxth r2, r3
80007ea: 897b ldrh r3, [r7, #10]
80007ec: 4413 add r3, r2
80007ee: b29b uxth r3, r3
80007f0: 817b strh r3, [r7, #10]
SetMot(mot,dir,val);
80007f2: 897a ldrh r2, [r7, #10]
80007f4: f897 107f ldrb.w r1, [r7, #127] @ 0x7f
80007f8: f897 3077 ldrb.w r3, [r7, #119] @ 0x77
80007fc: 4618 mov r0, r3
80007fe: f001 f8e5 bl 80019cc <SetMot>
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
8000802: e032 b.n 800086a <manageCDC+0x46e>
}else{
sprintf((char*)s,"\n?mnsvvvvv 00000>=vvvvv<=99999");//m nmotore senso valore
8000804: f107 030c add.w r3, r7, #12
8000808: 4961 ldr r1, [pc, #388] @ (8000990 <manageCDC+0x594>)
800080a: 4618 mov r0, r3
800080c: f00a fd00 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
8000810: bf00 nop
8000812: f107 030c add.w r3, r7, #12
8000816: 2113 movs r1, #19
8000818: 4618 mov r0, r3
800081a: f00a f91b bl 800aa54 <CDC_Transmit_FS>
800081e: 4603 mov r3, r0
8000820: 2b01 cmp r3, #1
8000822: d0f6 beq.n 8000812 <manageCDC+0x416>
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
8000824: e021 b.n 800086a <manageCDC+0x46e>
}
}else{
sprintf((char*)s,"\n?mnsvvvvv 1>=m<=4");//m nmotore senso valore
8000826: f107 030c add.w r3, r7, #12
800082a: 495a ldr r1, [pc, #360] @ (8000994 <manageCDC+0x598>)
800082c: 4618 mov r0, r3
800082e: f00a fcef bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
8000832: bf00 nop
8000834: f107 030c add.w r3, r7, #12
8000838: 2113 movs r1, #19
800083a: 4618 mov r0, r3
800083c: f00a f90a bl 800aa54 <CDC_Transmit_FS>
8000840: 4603 mov r3, r0
8000842: 2b01 cmp r3, #1
8000844: d0f6 beq.n 8000834 <manageCDC+0x438>
}
}else{
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
}
break;
8000846: e1f1 b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
8000848: f107 030c add.w r3, r7, #12
800084c: 4952 ldr r1, [pc, #328] @ (8000998 <manageCDC+0x59c>)
800084e: 4618 mov r0, r3
8000850: f00a fcde bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
8000854: bf00 nop
8000856: f107 030c add.w r3, r7, #12
800085a: 210a movs r1, #10
800085c: 4618 mov r0, r3
800085e: f00a f8f9 bl 800aa54 <CDC_Transmit_FS>
8000862: 4603 mov r3, r0
8000864: 2b01 cmp r3, #1
8000866: d0f6 beq.n 8000856 <manageCDC+0x45a>
break;
8000868: e1e0 b.n 8000c2c <manageCDC+0x830>
800086a: e1df b.n 8000c2c <manageCDC+0x830>
case 'e':
if(rxidx>1){
800086c: 4b4b ldr r3, [pc, #300] @ (800099c <manageCDC+0x5a0>)
800086e: 781b ldrb r3, [r3, #0]
8000870: 2b01 cmp r3, #1
8000872: f240 81b2 bls.w 8000bda <manageCDC+0x7de>
if(rxbuf[1]=='r'){
8000876: 4b45 ldr r3, [pc, #276] @ (800098c <manageCDC+0x590>)
8000878: 785b ldrb r3, [r3, #1]
800087a: 2b72 cmp r3, #114 @ 0x72
800087c: f040 8098 bne.w 80009b0 <manageCDC+0x5b4>
if(rxidx==4){
8000880: 4b46 ldr r3, [pc, #280] @ (800099c <manageCDC+0x5a0>)
8000882: 781b ldrb r3, [r3, #0]
8000884: 2b04 cmp r3, #4
8000886: d169 bne.n 800095c <manageCDC+0x560>
if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){
8000888: 4b40 ldr r3, [pc, #256] @ (800098c <manageCDC+0x590>)
800088a: 789a ldrb r2, [r3, #2]
800088c: 4b3f ldr r3, [pc, #252] @ (800098c <manageCDC+0x590>)
800088e: 78d9 ldrb r1, [r3, #3]
8000890: f107 0308 add.w r3, r7, #8
8000894: 9300 str r3, [sp, #0]
8000896: 460b mov r3, r1
8000898: 2130 movs r1, #48 @ 0x30
800089a: 2030 movs r0, #48 @ 0x30
800089c: f7ff fd13 bl 80002c6 <toHex>
80008a0: 4603 mov r3, r0
80008a2: 2b00 cmp r3, #0
80008a4: d042 beq.n 800092c <manageCDC+0x530>
st=EEW_Read(eeadd, &val);
80008a6: 893b ldrh r3, [r7, #8]
80008a8: b2db uxtb r3, r3
80008aa: f107 020a add.w r2, r7, #10
80008ae: 4611 mov r1, r2
80008b0: 4618 mov r0, r3
80008b2: f7ff fcdf bl 8000274 <EEW_Read>
80008b6: 4603 mov r3, r0
80008b8: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK){
80008bc: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
80008c0: 2b00 cmp r3, #0
80008c2: d119 bne.n 80008f8 <manageCDC+0x4fc>
sprintf((char*)s,"\nee 0x%02x=0x%04x",eeadd,val);
80008c4: 893b ldrh r3, [r7, #8]
80008c6: 461a mov r2, r3
80008c8: 897b ldrh r3, [r7, #10]
80008ca: f107 000c add.w r0, r7, #12
80008ce: 4934 ldr r1, [pc, #208] @ (80009a0 <manageCDC+0x5a4>)
80008d0: f00a fc9e bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
80008d4: bf00 nop
80008d6: f107 030c add.w r3, r7, #12
80008da: 4618 mov r0, r3
80008dc: f7ff fc36 bl 800014c <strlen>
80008e0: 4603 mov r3, r0
80008e2: b29a uxth r2, r3
80008e4: f107 030c add.w r3, r7, #12
80008e8: 4611 mov r1, r2
80008ea: 4618 mov r0, r3
80008ec: f00a f8b2 bl 800aa54 <CDC_Transmit_FS>
80008f0: 4603 mov r3, r0
80008f2: 2b01 cmp r3, #1
80008f4: d0ef beq.n 80008d6 <manageCDC+0x4da>
}
}else{
sprintf((char*)s,"\n?eraa | ewaavvvv");
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
}
break;
80008f6: e199 b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\nee read error %d",st);
80008f8: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
80008fc: f107 030c add.w r3, r7, #12
8000900: 4928 ldr r1, [pc, #160] @ (80009a4 <manageCDC+0x5a8>)
8000902: 4618 mov r0, r3
8000904: f00a fc84 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000908: bf00 nop
800090a: f107 030c add.w r3, r7, #12
800090e: 4618 mov r0, r3
8000910: f7ff fc1c bl 800014c <strlen>
8000914: 4603 mov r3, r0
8000916: b29a uxth r2, r3
8000918: f107 030c add.w r3, r7, #12
800091c: 4611 mov r1, r2
800091e: 4618 mov r0, r3
8000920: f00a f898 bl 800aa54 <CDC_Transmit_FS>
8000924: 4603 mov r3, r0
8000926: 2b01 cmp r3, #1
8000928: d0ef beq.n 800090a <manageCDC+0x50e>
break;
800092a: e17f b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\n?eraa hex values");
800092c: f107 030c add.w r3, r7, #12
8000930: 491d ldr r1, [pc, #116] @ (80009a8 <manageCDC+0x5ac>)
8000932: 4618 mov r0, r3
8000934: f00a fc6c bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000938: bf00 nop
800093a: f107 030c add.w r3, r7, #12
800093e: 4618 mov r0, r3
8000940: f7ff fc04 bl 800014c <strlen>
8000944: 4603 mov r3, r0
8000946: b29a uxth r2, r3
8000948: f107 030c add.w r3, r7, #12
800094c: 4611 mov r1, r2
800094e: 4618 mov r0, r3
8000950: f00a f880 bl 800aa54 <CDC_Transmit_FS>
8000954: 4603 mov r3, r0
8000956: 2b01 cmp r3, #1
8000958: d0ef beq.n 800093a <manageCDC+0x53e>
break;
800095a: e167 b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\n?eraa");
800095c: f107 030c add.w r3, r7, #12
8000960: 4912 ldr r1, [pc, #72] @ (80009ac <manageCDC+0x5b0>)
8000962: 4618 mov r0, r3
8000964: f00a fc54 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000968: bf00 nop
800096a: f107 030c add.w r3, r7, #12
800096e: 4618 mov r0, r3
8000970: f7ff fbec bl 800014c <strlen>
8000974: 4603 mov r3, r0
8000976: b29a uxth r2, r3
8000978: f107 030c add.w r3, r7, #12
800097c: 4611 mov r1, r2
800097e: 4618 mov r0, r3
8000980: f00a f868 bl 800aa54 <CDC_Transmit_FS>
8000984: 4603 mov r3, r0
8000986: 2b01 cmp r3, #1
8000988: d0ef beq.n 800096a <manageCDC+0x56e>
break;
800098a: e14f b.n 8000c2c <manageCDC+0x830>
800098c: 20000228 .word 0x20000228
8000990: 0800bc28 .word 0x0800bc28
8000994: 0800bc48 .word 0x0800bc48
8000998: 0800bc5c .word 0x0800bc5c
800099c: 20000224 .word 0x20000224
80009a0: 0800bc68 .word 0x0800bc68
80009a4: 0800bc7c .word 0x0800bc7c
80009a8: 0800bc90 .word 0x0800bc90
80009ac: 0800bca4 .word 0x0800bca4
}else if(rxbuf[1]=='w'){
80009b0: 4ba6 ldr r3, [pc, #664] @ (8000c4c <manageCDC+0x850>)
80009b2: 785b ldrb r3, [r3, #1]
80009b4: 2b77 cmp r3, #119 @ 0x77
80009b6: d169 bne.n 8000a8c <manageCDC+0x690>
if(rxidx==8){
80009b8: 4ba5 ldr r3, [pc, #660] @ (8000c50 <manageCDC+0x854>)
80009ba: 781b ldrb r3, [r3, #0]
80009bc: 2b08 cmp r3, #8
80009be: d14d bne.n 8000a5c <manageCDC+0x660>
if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){
80009c0: 4ba2 ldr r3, [pc, #648] @ (8000c4c <manageCDC+0x850>)
80009c2: 789a ldrb r2, [r3, #2]
80009c4: 4ba1 ldr r3, [pc, #644] @ (8000c4c <manageCDC+0x850>)
80009c6: 78d9 ldrb r1, [r3, #3]
80009c8: f107 0308 add.w r3, r7, #8
80009cc: 9300 str r3, [sp, #0]
80009ce: 460b mov r3, r1
80009d0: 2130 movs r1, #48 @ 0x30
80009d2: 2030 movs r0, #48 @ 0x30
80009d4: f7ff fc77 bl 80002c6 <toHex>
80009d8: 4603 mov r3, r0
80009da: 2b00 cmp r3, #0
80009dc: d037 beq.n 8000a4e <manageCDC+0x652>
if(toHex(rxbuf[4],rxbuf[5],rxbuf[6],rxbuf[7],&val)){
80009de: 4b9b ldr r3, [pc, #620] @ (8000c4c <manageCDC+0x850>)
80009e0: 7918 ldrb r0, [r3, #4]
80009e2: 4b9a ldr r3, [pc, #616] @ (8000c4c <manageCDC+0x850>)
80009e4: 7959 ldrb r1, [r3, #5]
80009e6: 4b99 ldr r3, [pc, #612] @ (8000c4c <manageCDC+0x850>)
80009e8: 799a ldrb r2, [r3, #6]
80009ea: 4b98 ldr r3, [pc, #608] @ (8000c4c <manageCDC+0x850>)
80009ec: 79dc ldrb r4, [r3, #7]
80009ee: f107 030a add.w r3, r7, #10
80009f2: 9300 str r3, [sp, #0]
80009f4: 4623 mov r3, r4
80009f6: f7ff fc66 bl 80002c6 <toHex>
80009fa: 4603 mov r3, r0
80009fc: 2b00 cmp r3, #0
80009fe: d01f beq.n 8000a40 <manageCDC+0x644>
st=EEW_Write(eeadd, val);
8000a00: 893b ldrh r3, [r7, #8]
8000a02: b2db uxtb r3, r3
8000a04: 897a ldrh r2, [r7, #10]
8000a06: 4611 mov r1, r2
8000a08: 4618 mov r0, r3
8000a0a: f7ff fc46 bl 800029a <EEW_Write>
8000a0e: 4603 mov r3, r0
8000a10: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK)sprintf((char*)s,"\ndone 0x%02x=0x%04x",eeadd,val);
8000a14: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000a18: 2b00 cmp r3, #0
8000a1a: d108 bne.n 8000a2e <manageCDC+0x632>
8000a1c: 893b ldrh r3, [r7, #8]
8000a1e: 461a mov r2, r3
8000a20: 897b ldrh r3, [r7, #10]
8000a22: f107 000c add.w r0, r7, #12
8000a26: 498b ldr r1, [pc, #556] @ (8000c54 <manageCDC+0x858>)
8000a28: f00a fbf2 bl 800b210 <siprintf>
8000a2c: e01c b.n 8000a68 <manageCDC+0x66c>
else sprintf((char*)s,"\nee write error %d", st);
8000a2e: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000a32: f107 030c add.w r3, r7, #12
8000a36: 4988 ldr r1, [pc, #544] @ (8000c58 <manageCDC+0x85c>)
8000a38: 4618 mov r0, r3
8000a3a: f00a fbe9 bl 800b210 <siprintf>
8000a3e: e013 b.n 8000a68 <manageCDC+0x66c>
}else sprintf((char*)s,"\n?ewaavvvv hex values");
8000a40: f107 030c add.w r3, r7, #12
8000a44: 4985 ldr r1, [pc, #532] @ (8000c5c <manageCDC+0x860>)
8000a46: 4618 mov r0, r3
8000a48: f00a fbe2 bl 800b210 <siprintf>
8000a4c: e00c b.n 8000a68 <manageCDC+0x66c>
}else sprintf((char*)s,"\n?ewaa hex values");
8000a4e: f107 030c add.w r3, r7, #12
8000a52: 4983 ldr r1, [pc, #524] @ (8000c60 <manageCDC+0x864>)
8000a54: 4618 mov r0, r3
8000a56: f00a fbdb bl 800b210 <siprintf>
8000a5a: e005 b.n 8000a68 <manageCDC+0x66c>
}else sprintf((char*)s,"\n?ewaavvvv");
8000a5c: f107 030c add.w r3, r7, #12
8000a60: 4980 ldr r1, [pc, #512] @ (8000c64 <manageCDC+0x868>)
8000a62: 4618 mov r0, r3
8000a64: f00a fbd4 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000a68: bf00 nop
8000a6a: f107 030c add.w r3, r7, #12
8000a6e: 4618 mov r0, r3
8000a70: f7ff fb6c bl 800014c <strlen>
8000a74: 4603 mov r3, r0
8000a76: b29a uxth r2, r3
8000a78: f107 030c add.w r3, r7, #12
8000a7c: 4611 mov r1, r2
8000a7e: 4618 mov r0, r3
8000a80: f009 ffe8 bl 800aa54 <CDC_Transmit_FS>
8000a84: 4603 mov r3, r0
8000a86: 2b01 cmp r3, #1
8000a88: d0ef beq.n 8000a6a <manageCDC+0x66e>
break;
8000a8a: e0cf b.n 8000c2c <manageCDC+0x830>
}else if(rxbuf[1]=='d'){
8000a8c: 4b6f ldr r3, [pc, #444] @ (8000c4c <manageCDC+0x850>)
8000a8e: 785b ldrb r3, [r3, #1]
8000a90: 2b64 cmp r3, #100 @ 0x64
8000a92: f040 808a bne.w 8000baa <manageCDC+0x7ae>
if(rxidx==2){
8000a96: 4b6e ldr r3, [pc, #440] @ (8000c50 <manageCDC+0x854>)
8000a98: 781b ldrb r3, [r3, #0]
8000a9a: 2b02 cmp r3, #2
8000a9c: d16d bne.n 8000b7a <manageCDC+0x77e>
for(i=0;i<32;i++){
8000a9e: 2300 movs r3, #0
8000aa0: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000aa4: e064 b.n 8000b70 <manageCDC+0x774>
if((i%4)==0){
8000aa6: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000aaa: f003 0303 and.w r3, r3, #3
8000aae: b2db uxtb r3, r3
8000ab0: 2b00 cmp r3, #0
8000ab2: d116 bne.n 8000ae2 <manageCDC+0x6e6>
sprintf((char*)s,"\n");
8000ab4: f107 030c add.w r3, r7, #12
8000ab8: 496b ldr r1, [pc, #428] @ (8000c68 <manageCDC+0x86c>)
8000aba: 4618 mov r0, r3
8000abc: f00a fba8 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000ac0: bf00 nop
8000ac2: f107 030c add.w r3, r7, #12
8000ac6: 4618 mov r0, r3
8000ac8: f7ff fb40 bl 800014c <strlen>
8000acc: 4603 mov r3, r0
8000ace: b29a uxth r2, r3
8000ad0: f107 030c add.w r3, r7, #12
8000ad4: 4611 mov r1, r2
8000ad6: 4618 mov r0, r3
8000ad8: f009 ffbc bl 800aa54 <CDC_Transmit_FS>
8000adc: 4603 mov r3, r0
8000ade: 2b01 cmp r3, #1
8000ae0: d0ef beq.n 8000ac2 <manageCDC+0x6c6>
st=EEW_Read(i, &val);
8000ae2: f107 020a add.w r2, r7, #10
8000ae6: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000aea: 4611 mov r1, r2
8000aec: 4618 mov r0, r3
8000aee: f7ff fbc1 bl 8000274 <EEW_Read>
8000af2: 4603 mov r3, r0
8000af4: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK){
8000af8: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000afc: 2b00 cmp r3, #0
8000afe: d119 bne.n 8000b34 <manageCDC+0x738>
sprintf((char*)s,"0x%02x=0x%04x ",i,val);
8000b00: f897 207e ldrb.w r2, [r7, #126] @ 0x7e
8000b04: 897b ldrh r3, [r7, #10]
8000b06: f107 000c add.w r0, r7, #12
8000b0a: 4958 ldr r1, [pc, #352] @ (8000c6c <manageCDC+0x870>)
8000b0c: f00a fb80 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b10: bf00 nop
8000b12: f107 030c add.w r3, r7, #12
8000b16: 4618 mov r0, r3
8000b18: f7ff fb18 bl 800014c <strlen>
8000b1c: 4603 mov r3, r0
8000b1e: b29a uxth r2, r3
8000b20: f107 030c add.w r3, r7, #12
8000b24: 4611 mov r1, r2
8000b26: 4618 mov r0, r3
8000b28: f009 ff94 bl 800aa54 <CDC_Transmit_FS>
8000b2c: 4603 mov r3, r0
8000b2e: 2b01 cmp r3, #1
8000b30: d0ef beq.n 8000b12 <manageCDC+0x716>
8000b32: e018 b.n 8000b66 <manageCDC+0x76a>
sprintf((char*)s,"rderr %d ",st);
8000b34: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000b38: f107 030c add.w r3, r7, #12
8000b3c: 494c ldr r1, [pc, #304] @ (8000c70 <manageCDC+0x874>)
8000b3e: 4618 mov r0, r3
8000b40: f00a fb66 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b44: bf00 nop
8000b46: f107 030c add.w r3, r7, #12
8000b4a: 4618 mov r0, r3
8000b4c: f7ff fafe bl 800014c <strlen>
8000b50: 4603 mov r3, r0
8000b52: b29a uxth r2, r3
8000b54: f107 030c add.w r3, r7, #12
8000b58: 4611 mov r1, r2
8000b5a: 4618 mov r0, r3
8000b5c: f009 ff7a bl 800aa54 <CDC_Transmit_FS>
8000b60: 4603 mov r3, r0
8000b62: 2b01 cmp r3, #1
8000b64: d0ef beq.n 8000b46 <manageCDC+0x74a>
for(i=0;i<32;i++){
8000b66: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000b6a: 3301 adds r3, #1
8000b6c: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000b70: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000b74: 2b1f cmp r3, #31
8000b76: d996 bls.n 8000aa6 <manageCDC+0x6aa>
break;
8000b78: e058 b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\n?ed");
8000b7a: f107 030c add.w r3, r7, #12
8000b7e: 493d ldr r1, [pc, #244] @ (8000c74 <manageCDC+0x878>)
8000b80: 4618 mov r0, r3
8000b82: f00a fb45 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b86: bf00 nop
8000b88: f107 030c add.w r3, r7, #12
8000b8c: 4618 mov r0, r3
8000b8e: f7ff fadd bl 800014c <strlen>
8000b92: 4603 mov r3, r0
8000b94: b29a uxth r2, r3
8000b96: f107 030c add.w r3, r7, #12
8000b9a: 4611 mov r1, r2
8000b9c: 4618 mov r0, r3
8000b9e: f009 ff59 bl 800aa54 <CDC_Transmit_FS>
8000ba2: 4603 mov r3, r0
8000ba4: 2b01 cmp r3, #1
8000ba6: d0ef beq.n 8000b88 <manageCDC+0x78c>
break;
8000ba8: e040 b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\n?er|w|d");
8000baa: f107 030c add.w r3, r7, #12
8000bae: 4932 ldr r1, [pc, #200] @ (8000c78 <manageCDC+0x87c>)
8000bb0: 4618 mov r0, r3
8000bb2: f00a fb2d bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000bb6: bf00 nop
8000bb8: f107 030c add.w r3, r7, #12
8000bbc: 4618 mov r0, r3
8000bbe: f7ff fac5 bl 800014c <strlen>
8000bc2: 4603 mov r3, r0
8000bc4: b29a uxth r2, r3
8000bc6: f107 030c add.w r3, r7, #12
8000bca: 4611 mov r1, r2
8000bcc: 4618 mov r0, r3
8000bce: f009 ff41 bl 800aa54 <CDC_Transmit_FS>
8000bd2: 4603 mov r3, r0
8000bd4: 2b01 cmp r3, #1
8000bd6: d0ef beq.n 8000bb8 <manageCDC+0x7bc>
break;
8000bd8: e028 b.n 8000c2c <manageCDC+0x830>
sprintf((char*)s,"\n?eraa | ewaavvvv");
8000bda: f107 030c add.w r3, r7, #12
8000bde: 4927 ldr r1, [pc, #156] @ (8000c7c <manageCDC+0x880>)
8000be0: 4618 mov r0, r3
8000be2: f00a fb15 bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000be6: bf00 nop
8000be8: f107 030c add.w r3, r7, #12
8000bec: 4618 mov r0, r3
8000bee: f7ff faad bl 800014c <strlen>
8000bf2: 4603 mov r3, r0
8000bf4: b29a uxth r2, r3
8000bf6: f107 030c add.w r3, r7, #12
8000bfa: 4611 mov r1, r2
8000bfc: 4618 mov r0, r3
8000bfe: f009 ff29 bl 800aa54 <CDC_Transmit_FS>
8000c02: 4603 mov r3, r0
8000c04: 2b01 cmp r3, #1
8000c06: d0ef beq.n 8000be8 <manageCDC+0x7ec>
break;
8000c08: e010 b.n 8000c2c <manageCDC+0x830>
default:
sprintf((char*)s,"\n?");
8000c0a: f107 030c add.w r3, r7, #12
8000c0e: 491c ldr r1, [pc, #112] @ (8000c80 <manageCDC+0x884>)
8000c10: 4618 mov r0, r3
8000c12: f00a fafd bl 800b210 <siprintf>
while (CDC_Transmit_FS(s, 2) == USBD_BUSY);
8000c16: bf00 nop
8000c18: f107 030c add.w r3, r7, #12
8000c1c: 2102 movs r1, #2
8000c1e: 4618 mov r0, r3
8000c20: f009 ff18 bl 800aa54 <CDC_Transmit_FS>
8000c24: 4603 mov r3, r0
8000c26: 2b01 cmp r3, #1
8000c28: d0f6 beq.n 8000c18 <manageCDC+0x81c>
break;
8000c2a: bf00 nop
}
}
rxidx=0;
8000c2c: 4b08 ldr r3, [pc, #32] @ (8000c50 <manageCDC+0x854>)
8000c2e: 2200 movs r2, #0
8000c30: 701a strb r2, [r3, #0]
8000c32: e007 b.n 8000c44 <manageCDC+0x848>
}else rxidx++;
8000c34: 4b06 ldr r3, [pc, #24] @ (8000c50 <manageCDC+0x854>)
8000c36: 781b ldrb r3, [r3, #0]
8000c38: 3301 adds r3, #1
8000c3a: b2da uxtb r2, r3
8000c3c: 4b04 ldr r3, [pc, #16] @ (8000c50 <manageCDC+0x854>)
8000c3e: 701a strb r2, [r3, #0]
8000c40: e000 b.n 8000c44 <manageCDC+0x848>
if (rx < 0) return;
8000c42: bf00 nop
// tiny spin or yield
}
}
8000c44: 3784 adds r7, #132 @ 0x84
8000c46: 46bd mov sp, r7
8000c48: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8000c4c: 20000228 .word 0x20000228
8000c50: 20000224 .word 0x20000224
8000c54: 0800bcac .word 0x0800bcac
8000c58: 0800bcc0 .word 0x0800bcc0
8000c5c: 0800bcd4 .word 0x0800bcd4
8000c60: 0800bcec .word 0x0800bcec
8000c64: 0800bd00 .word 0x0800bd00
8000c68: 0800bd0c .word 0x0800bd0c
8000c6c: 0800bd10 .word 0x0800bd10
8000c70: 0800bd20 .word 0x0800bd20
8000c74: 0800bd2c .word 0x0800bd2c
8000c78: 0800bd34 .word 0x0800bd34
8000c7c: 0800bd40 .word 0x0800bd40
8000c80: 0800bd54 .word 0x0800bd54
08000c84 <EE_GetPageStatus>:
/* ========================================================================= */
/* --- Internal helpers ---------------------------------------------------- */
static uint16_t EE_GetPageStatus(uint32_t pageBase)
{
8000c84: b480 push {r7}
8000c86: b083 sub sp, #12
8000c88: af00 add r7, sp, #0
8000c8a: 6078 str r0, [r7, #4]
return *(__IO uint16_t *)pageBase;
8000c8c: 687b ldr r3, [r7, #4]
8000c8e: 881b ldrh r3, [r3, #0]
8000c90: b29b uxth r3, r3
}
8000c92: 4618 mov r0, r3
8000c94: 370c adds r7, #12
8000c96: 46bd mov sp, r7
8000c98: bc80 pop {r7}
8000c9a: 4770 bx lr
08000c9c <EE_FlashProgramHalfWord>:
static HAL_StatusTypeDef EE_FlashProgramHalfWord(uint32_t Address, uint16_t Data)
{
8000c9c: b5b0 push {r4, r5, r7, lr}
8000c9e: b084 sub sp, #16
8000ca0: af00 add r7, sp, #0
8000ca2: 6078 str r0, [r7, #4]
8000ca4: 460b mov r3, r1
8000ca6: 807b strh r3, [r7, #2]
HAL_StatusTypeDef status;
HAL_FLASH_Unlock();
8000ca8: f002 f9c8 bl 800303c <HAL_FLASH_Unlock>
status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, Address, Data);
8000cac: 887b ldrh r3, [r7, #2]
8000cae: 2200 movs r2, #0
8000cb0: 461c mov r4, r3
8000cb2: 4615 mov r5, r2
8000cb4: 4622 mov r2, r4
8000cb6: 462b mov r3, r5
8000cb8: 6879 ldr r1, [r7, #4]
8000cba: 2001 movs r0, #1
8000cbc: f002 f94e bl 8002f5c <HAL_FLASH_Program>
8000cc0: 4603 mov r3, r0
8000cc2: 73fb strb r3, [r7, #15]
HAL_FLASH_Lock();
8000cc4: f002 f9e0 bl 8003088 <HAL_FLASH_Lock>
return status;
8000cc8: 7bfb ldrb r3, [r7, #15]
}
8000cca: 4618 mov r0, r3
8000ccc: 3710 adds r7, #16
8000cce: 46bd mov sp, r7
8000cd0: bdb0 pop {r4, r5, r7, pc}
08000cd2 <EE_FlashErasePage>:
static HAL_StatusTypeDef EE_FlashErasePage(uint32_t PageAddress)
{
8000cd2: b580 push {r7, lr}
8000cd4: b088 sub sp, #32
8000cd6: af00 add r7, sp, #0
8000cd8: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
FLASH_EraseInitTypeDef EraseInit;
uint32_t PageError = 0;
8000cda: 2300 movs r3, #0
8000cdc: 60bb str r3, [r7, #8]
HAL_FLASH_Unlock();
8000cde: f002 f9ad bl 800303c <HAL_FLASH_Unlock>
EraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
8000ce2: 2300 movs r3, #0
8000ce4: 60fb str r3, [r7, #12]
EraseInit.PageAddress = PageAddress;
8000ce6: 687b ldr r3, [r7, #4]
8000ce8: 617b str r3, [r7, #20]
EraseInit.NbPages = 1;
8000cea: 2301 movs r3, #1
8000cec: 61bb str r3, [r7, #24]
status = HAL_FLASHEx_Erase(&EraseInit, &PageError);
8000cee: f107 0208 add.w r2, r7, #8
8000cf2: f107 030c add.w r3, r7, #12
8000cf6: 4611 mov r1, r2
8000cf8: 4618 mov r0, r3
8000cfa: f002 fa87 bl 800320c <HAL_FLASHEx_Erase>
8000cfe: 4603 mov r3, r0
8000d00: 77fb strb r3, [r7, #31]
HAL_FLASH_Lock();
8000d02: f002 f9c1 bl 8003088 <HAL_FLASH_Lock>
return status;
8000d06: 7ffb ldrb r3, [r7, #31]
}
8000d08: 4618 mov r0, r3
8000d0a: 3720 adds r7, #32
8000d0c: 46bd mov sp, r7
8000d0e: bd80 pop {r7, pc}
08000d10 <EE_FindFreeAddress>:
/* Find first free record address in given page (returns 0 if full) */
static uint32_t EE_FindFreeAddress(uint32_t pageBase)
{
8000d10: b480 push {r7}
8000d12: b087 sub sp, #28
8000d14: af00 add r7, sp, #0
8000d16: 6078 str r0, [r7, #4]
uint32_t addr = pageBase + 2U; /* Skip status word */
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 3302 adds r3, #2
8000d1c: 617b str r3, [r7, #20]
uint32_t pageEnd = pageBase + EE_PAGE_SIZE;
8000d1e: 687b ldr r3, [r7, #4]
8000d20: f503 6380 add.w r3, r3, #1024 @ 0x400
8000d24: 613b str r3, [r7, #16]
while (addr < (pageEnd - sizeof(EE_Record_t) + 1U))
8000d26: e00c b.n 8000d42 <EE_FindFreeAddress+0x32>
{
uint16_t vaddr = *(__IO uint16_t *)addr;
8000d28: 697b ldr r3, [r7, #20]
8000d2a: 881b ldrh r3, [r3, #0]
8000d2c: 81fb strh r3, [r7, #14]
if (vaddr == 0xFFFFU)
8000d2e: 89fb ldrh r3, [r7, #14]
8000d30: f64f 72ff movw r2, #65535 @ 0xffff
8000d34: 4293 cmp r3, r2
8000d36: d101 bne.n 8000d3c <EE_FindFreeAddress+0x2c>
{
/* Empty slot */
return addr;
8000d38: 697b ldr r3, [r7, #20]
8000d3a: e008 b.n 8000d4e <EE_FindFreeAddress+0x3e>
}
addr += sizeof(EE_Record_t);
8000d3c: 697b ldr r3, [r7, #20]
8000d3e: 3304 adds r3, #4
8000d40: 617b str r3, [r7, #20]
while (addr < (pageEnd - sizeof(EE_Record_t) + 1U))
8000d42: 693b ldr r3, [r7, #16]
8000d44: 3b03 subs r3, #3
8000d46: 697a ldr r2, [r7, #20]
8000d48: 429a cmp r2, r3
8000d4a: d3ed bcc.n 8000d28 <EE_FindFreeAddress+0x18>
}
return 0U; /* No space */
8000d4c: 2300 movs r3, #0
}
8000d4e: 4618 mov r0, r3
8000d50: 371c adds r7, #28
8000d52: 46bd mov sp, r7
8000d54: bc80 pop {r7}
8000d56: 4770 bx lr
08000d58 <EE_FindInPage>:
/* Find latest value of VirtAddress in a specific page (internal, uses EE_Status) */
/* Find latest value of VirtAddress in a specific page (scan forward) */
static EE_Status EE_FindInPage(uint32_t pageBase, uint16_t VirtAddress, uint16_t *Data)
{
8000d58: b480 push {r7}
8000d5a: b089 sub sp, #36 @ 0x24
8000d5c: af00 add r7, sp, #0
8000d5e: 60f8 str r0, [r7, #12]
8000d60: 460b mov r3, r1
8000d62: 607a str r2, [r7, #4]
8000d64: 817b strh r3, [r7, #10]
uint32_t addr = pageBase + 2U; // skip status halfword
8000d66: 68fb ldr r3, [r7, #12]
8000d68: 3302 adds r3, #2
8000d6a: 61fb str r3, [r7, #28]
uint32_t pageEnd = pageBase + EE_PAGE_SIZE;
8000d6c: 68fb ldr r3, [r7, #12]
8000d6e: f503 6380 add.w r3, r3, #1024 @ 0x400
8000d72: 617b str r3, [r7, #20]
EE_Status result = EE_NOT_FOUND;
8000d74: 2302 movs r3, #2
8000d76: 76fb strb r3, [r7, #27]
uint16_t lastVal = 0;
8000d78: 2300 movs r3, #0
8000d7a: 833b strh r3, [r7, #24]
if (Data == NULL)
8000d7c: 687b ldr r3, [r7, #4]
8000d7e: 2b00 cmp r3, #0
8000d80: d118 bne.n 8000db4 <EE_FindInPage+0x5c>
return EE_ERROR;
8000d82: 2301 movs r3, #1
8000d84: e024 b.n 8000dd0 <EE_FindInPage+0x78>
while (addr <= (pageEnd - sizeof(EE_Record_t)))
{
uint16_t vaddr = *(__IO uint16_t *)addr;
8000d86: 69fb ldr r3, [r7, #28]
8000d88: 881b ldrh r3, [r3, #0]
8000d8a: 827b strh r3, [r7, #18]
if (vaddr == 0xFFFFU)
8000d8c: 8a7b ldrh r3, [r7, #18]
8000d8e: f64f 72ff movw r2, #65535 @ 0xffff
8000d92: 4293 cmp r3, r2
8000d94: d014 beq.n 8000dc0 <EE_FindInPage+0x68>
{
// First empty slot => no more records in this page
break;
}
uint16_t value = *(__IO uint16_t *)(addr + 2U);
8000d96: 69fb ldr r3, [r7, #28]
8000d98: 3302 adds r3, #2
8000d9a: 881b ldrh r3, [r3, #0]
8000d9c: 823b strh r3, [r7, #16]
if (vaddr == VirtAddress)
8000d9e: 8a7a ldrh r2, [r7, #18]
8000da0: 897b ldrh r3, [r7, #10]
8000da2: 429a cmp r2, r3
8000da4: d103 bne.n 8000dae <EE_FindInPage+0x56>
{
lastVal = value; // keep most recent
8000da6: 8a3b ldrh r3, [r7, #16]
8000da8: 833b strh r3, [r7, #24]
result = EE_OK;
8000daa: 2300 movs r3, #0
8000dac: 76fb strb r3, [r7, #27]
}
addr += sizeof(EE_Record_t); // move 4 bytes forward
8000dae: 69fb ldr r3, [r7, #28]
8000db0: 3304 adds r3, #4
8000db2: 61fb str r3, [r7, #28]
while (addr <= (pageEnd - sizeof(EE_Record_t)))
8000db4: 697b ldr r3, [r7, #20]
8000db6: 3b04 subs r3, #4
8000db8: 69fa ldr r2, [r7, #28]
8000dba: 429a cmp r2, r3
8000dbc: d9e3 bls.n 8000d86 <EE_FindInPage+0x2e>
8000dbe: e000 b.n 8000dc2 <EE_FindInPage+0x6a>
break;
8000dc0: bf00 nop
}
if (result == EE_OK)
8000dc2: 7efb ldrb r3, [r7, #27]
8000dc4: 2b00 cmp r3, #0
8000dc6: d102 bne.n 8000dce <EE_FindInPage+0x76>
*Data = lastVal;
8000dc8: 687b ldr r3, [r7, #4]
8000dca: 8b3a ldrh r2, [r7, #24]
8000dcc: 801a strh r2, [r3, #0]
return result;
8000dce: 7efb ldrb r3, [r7, #27]
}
8000dd0: 4618 mov r0, r3
8000dd2: 3724 adds r7, #36 @ 0x24
8000dd4: 46bd mov sp, r7
8000dd6: bc80 pop {r7}
8000dd8: 4770 bx lr
...
08000ddc <EE_Format>:
/* Format both pages: erase and set PAGE0 as VALID */
static EE_Status EE_Format(void)
{
8000ddc: b580 push {r7, lr}
8000dde: af00 add r7, sp, #0
if (EE_FlashErasePage(EE_PAGE0_BASE) != HAL_OK)
8000de0: 480f ldr r0, [pc, #60] @ (8000e20 <EE_Format+0x44>)
8000de2: f7ff ff76 bl 8000cd2 <EE_FlashErasePage>
8000de6: 4603 mov r3, r0
8000de8: 2b00 cmp r3, #0
8000dea: d001 beq.n 8000df0 <EE_Format+0x14>
return EE_STATUS_ERROR;
8000dec: 2301 movs r3, #1
8000dee: e015 b.n 8000e1c <EE_Format+0x40>
if (EE_FlashErasePage(EE_PAGE1_BASE) != HAL_OK)
8000df0: 480c ldr r0, [pc, #48] @ (8000e24 <EE_Format+0x48>)
8000df2: f7ff ff6e bl 8000cd2 <EE_FlashErasePage>
8000df6: 4603 mov r3, r0
8000df8: 2b00 cmp r3, #0
8000dfa: d001 beq.n 8000e00 <EE_Format+0x24>
return EE_STATUS_ERROR;
8000dfc: 2301 movs r3, #1
8000dfe: e00d b.n 8000e1c <EE_Format+0x40>
if (EE_FlashProgramHalfWord(EE_PAGE0_BASE, EE_PAGE_STATUS_VALID) != HAL_OK)
8000e00: f64a 21aa movw r1, #43690 @ 0xaaaa
8000e04: 4806 ldr r0, [pc, #24] @ (8000e20 <EE_Format+0x44>)
8000e06: f7ff ff49 bl 8000c9c <EE_FlashProgramHalfWord>
8000e0a: 4603 mov r3, r0
8000e0c: 2b00 cmp r3, #0
8000e0e: d001 beq.n 8000e14 <EE_Format+0x38>
return EE_STATUS_ERROR;
8000e10: 2301 movs r3, #1
8000e12: e003 b.n 8000e1c <EE_Format+0x40>
/* PAGE1 will remain erased (status = 0xFFFF) */
EE_ActivePageBase = EE_PAGE0_BASE;
8000e14: 4b04 ldr r3, [pc, #16] @ (8000e28 <EE_Format+0x4c>)
8000e16: 4a02 ldr r2, [pc, #8] @ (8000e20 <EE_Format+0x44>)
8000e18: 601a str r2, [r3, #0]
return EE_STATUS_OK;
8000e1a: 2300 movs r3, #0
}
8000e1c: 4618 mov r0, r3
8000e1e: bd80 pop {r7, pc}
8000e20: 0800f800 .word 0x0800f800
8000e24: 0800fc00 .word 0x0800fc00
8000e28: 20000000 .word 0x20000000
08000e2c <EE_GetOtherPageBase>:
/* Get the base of the other page */
static uint32_t EE_GetOtherPageBase(uint32_t pageBase)
{
8000e2c: b480 push {r7}
8000e2e: b083 sub sp, #12
8000e30: af00 add r7, sp, #0
8000e32: 6078 str r0, [r7, #4]
return (pageBase == EE_PAGE0_BASE) ? EE_PAGE1_BASE : EE_PAGE0_BASE;
8000e34: 687b ldr r3, [r7, #4]
8000e36: 4a05 ldr r2, [pc, #20] @ (8000e4c <EE_GetOtherPageBase+0x20>)
8000e38: 4293 cmp r3, r2
8000e3a: d101 bne.n 8000e40 <EE_GetOtherPageBase+0x14>
8000e3c: 4b04 ldr r3, [pc, #16] @ (8000e50 <EE_GetOtherPageBase+0x24>)
8000e3e: e000 b.n 8000e42 <EE_GetOtherPageBase+0x16>
8000e40: 4b02 ldr r3, [pc, #8] @ (8000e4c <EE_GetOtherPageBase+0x20>)
}
8000e42: 4618 mov r0, r3
8000e44: 370c adds r7, #12
8000e46: 46bd mov sp, r7
8000e48: bc80 pop {r7}
8000e4a: 4770 bx lr
8000e4c: 0800f800 .word 0x0800f800
8000e50: 0800fc00 .word 0x0800fc00
08000e54 <EE_PageTransfer>:
/* Page transfer (garbage collection + new write) */
static EE_Status EE_PageTransfer(uint16_t VirtAddress, uint16_t Data)
{
8000e54: b580 push {r7, lr}
8000e56: b088 sub sp, #32
8000e58: af00 add r7, sp, #0
8000e5a: 4603 mov r3, r0
8000e5c: 460a mov r2, r1
8000e5e: 80fb strh r3, [r7, #6]
8000e60: 4613 mov r3, r2
8000e62: 80bb strh r3, [r7, #4]
uint32_t oldBase = EE_ActivePageBase;
8000e64: 4b3c ldr r3, [pc, #240] @ (8000f58 <EE_PageTransfer+0x104>)
8000e66: 681b ldr r3, [r3, #0]
8000e68: 617b str r3, [r7, #20]
uint32_t newBase = EE_GetOtherPageBase(oldBase);
8000e6a: 6978 ldr r0, [r7, #20]
8000e6c: f7ff ffde bl 8000e2c <EE_GetOtherPageBase>
8000e70: 6138 str r0, [r7, #16]
uint32_t addr;
uint16_t value;
EE_Status st;
/* Erase new page */
if (EE_FlashErasePage(newBase) != HAL_OK)
8000e72: 6938 ldr r0, [r7, #16]
8000e74: f7ff ff2d bl 8000cd2 <EE_FlashErasePage>
8000e78: 4603 mov r3, r0
8000e7a: 2b00 cmp r3, #0
8000e7c: d001 beq.n 8000e82 <EE_PageTransfer+0x2e>
return EE_STATUS_ERROR;
8000e7e: 2301 movs r3, #1
8000e80: e065 b.n 8000f4e <EE_PageTransfer+0xfa>
/* Mark new page as RECEIVE */
if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_RECEIVE) != HAL_OK)
8000e82: f245 5155 movw r1, #21845 @ 0x5555
8000e86: 6938 ldr r0, [r7, #16]
8000e88: f7ff ff08 bl 8000c9c <EE_FlashProgramHalfWord>
8000e8c: 4603 mov r3, r0
8000e8e: 2b00 cmp r3, #0
8000e90: d001 beq.n 8000e96 <EE_PageTransfer+0x42>
return EE_STATUS_ERROR;
8000e92: 2301 movs r3, #1
8000e94: e05b b.n 8000f4e <EE_PageTransfer+0xfa>
/* Start writing records just after status */
addr = newBase + 2U;
8000e96: 693b ldr r3, [r7, #16]
8000e98: 3302 adds r3, #2
8000e9a: 61fb str r3, [r7, #28]
/* For each known virtual variable */
for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++)
8000e9c: 2300 movs r3, #0
8000e9e: 837b strh r3, [r7, #26]
8000ea0: e03c b.n 8000f1c <EE_PageTransfer+0xc8>
{
uint16_t vaddr = EE_VirtAddrs[i];
8000ea2: 8b7b ldrh r3, [r7, #26]
8000ea4: 4a2d ldr r2, [pc, #180] @ (8000f5c <EE_PageTransfer+0x108>)
8000ea6: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8000eaa: 81fb strh r3, [r7, #14]
if (vaddr == VirtAddress)
8000eac: 89fa ldrh r2, [r7, #14]
8000eae: 88fb ldrh r3, [r7, #6]
8000eb0: 429a cmp r2, r3
8000eb2: d102 bne.n 8000eba <EE_PageTransfer+0x66>
{
/* Use the new data passed into PageTransfer */
value = Data;
8000eb4: 88bb ldrh r3, [r7, #4]
8000eb6: 817b strh r3, [r7, #10]
8000eb8: e00b b.n 8000ed2 <EE_PageTransfer+0x7e>
}
else
{
/* Read latest value from old active page */
st = EE_FindInPage(oldBase, vaddr, &value);
8000eba: f107 020a add.w r2, r7, #10
8000ebe: 89fb ldrh r3, [r7, #14]
8000ec0: 4619 mov r1, r3
8000ec2: 6978 ldr r0, [r7, #20]
8000ec4: f7ff ff48 bl 8000d58 <EE_FindInPage>
8000ec8: 4603 mov r3, r0
8000eca: 737b strb r3, [r7, #13]
if (st != EE_STATUS_OK)
8000ecc: 7b7b ldrb r3, [r7, #13]
8000ece: 2b00 cmp r3, #0
8000ed0: d120 bne.n 8000f14 <EE_PageTransfer+0xc0>
continue;
}
}
/* Write record to new page */
if (EE_FlashProgramHalfWord(addr, vaddr) != HAL_OK)
8000ed2: 89fb ldrh r3, [r7, #14]
8000ed4: 4619 mov r1, r3
8000ed6: 69f8 ldr r0, [r7, #28]
8000ed8: f7ff fee0 bl 8000c9c <EE_FlashProgramHalfWord>
8000edc: 4603 mov r3, r0
8000ede: 2b00 cmp r3, #0
8000ee0: d001 beq.n 8000ee6 <EE_PageTransfer+0x92>
return EE_STATUS_ERROR;
8000ee2: 2301 movs r3, #1
8000ee4: e033 b.n 8000f4e <EE_PageTransfer+0xfa>
if (EE_FlashProgramHalfWord(addr + 2U, value) != HAL_OK)
8000ee6: 69fb ldr r3, [r7, #28]
8000ee8: 3302 adds r3, #2
8000eea: 897a ldrh r2, [r7, #10]
8000eec: 4611 mov r1, r2
8000eee: 4618 mov r0, r3
8000ef0: f7ff fed4 bl 8000c9c <EE_FlashProgramHalfWord>
8000ef4: 4603 mov r3, r0
8000ef6: 2b00 cmp r3, #0
8000ef8: d001 beq.n 8000efe <EE_PageTransfer+0xaa>
return EE_STATUS_ERROR;
8000efa: 2301 movs r3, #1
8000efc: e027 b.n 8000f4e <EE_PageTransfer+0xfa>
addr += sizeof(EE_Record_t);
8000efe: 69fb ldr r3, [r7, #28]
8000f00: 3304 adds r3, #4
8000f02: 61fb str r3, [r7, #28]
if (addr >= (newBase + EE_PAGE_SIZE))
8000f04: 693b ldr r3, [r7, #16]
8000f06: f503 6380 add.w r3, r3, #1024 @ 0x400
8000f0a: 69fa ldr r2, [r7, #28]
8000f0c: 429a cmp r2, r3
8000f0e: d302 bcc.n 8000f16 <EE_PageTransfer+0xc2>
return EE_STATUS_NO_SPACE;
8000f10: 2303 movs r3, #3
8000f12: e01c b.n 8000f4e <EE_PageTransfer+0xfa>
continue;
8000f14: bf00 nop
for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++)
8000f16: 8b7b ldrh r3, [r7, #26]
8000f18: 3301 adds r3, #1
8000f1a: 837b strh r3, [r7, #26]
8000f1c: 8b7b ldrh r3, [r7, #26]
8000f1e: 2b1f cmp r3, #31
8000f20: d9bf bls.n 8000ea2 <EE_PageTransfer+0x4e>
}
/* Erase old page */
if (EE_FlashErasePage(oldBase) != HAL_OK)
8000f22: 6978 ldr r0, [r7, #20]
8000f24: f7ff fed5 bl 8000cd2 <EE_FlashErasePage>
8000f28: 4603 mov r3, r0
8000f2a: 2b00 cmp r3, #0
8000f2c: d001 beq.n 8000f32 <EE_PageTransfer+0xde>
return EE_STATUS_ERROR;
8000f2e: 2301 movs r3, #1
8000f30: e00d b.n 8000f4e <EE_PageTransfer+0xfa>
/* Mark new page as VALID */
if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_VALID) != HAL_OK)
8000f32: f64a 21aa movw r1, #43690 @ 0xaaaa
8000f36: 6938 ldr r0, [r7, #16]
8000f38: f7ff feb0 bl 8000c9c <EE_FlashProgramHalfWord>
8000f3c: 4603 mov r3, r0
8000f3e: 2b00 cmp r3, #0
8000f40: d001 beq.n 8000f46 <EE_PageTransfer+0xf2>
return EE_STATUS_ERROR;
8000f42: 2301 movs r3, #1
8000f44: e003 b.n 8000f4e <EE_PageTransfer+0xfa>
/* Update active page */
EE_ActivePageBase = newBase;
8000f46: 4a04 ldr r2, [pc, #16] @ (8000f58 <EE_PageTransfer+0x104>)
8000f48: 693b ldr r3, [r7, #16]
8000f4a: 6013 str r3, [r2, #0]
return EE_STATUS_OK;
8000f4c: 2300 movs r3, #0
}
8000f4e: 4618 mov r0, r3
8000f50: 3720 adds r7, #32
8000f52: 46bd mov sp, r7
8000f54: bd80 pop {r7, pc}
8000f56: bf00 nop
8000f58: 20000000 .word 0x20000000
8000f5c: 0800bda8 .word 0x0800bda8
08000f60 <EE_Init>:
* - Checks page statuses and chooses the active page.
* - If inconsistent or blank, formats pages.
* PUBLIC RETURN TYPE: uint16_t (EE_OK / EE_ERROR / ...)
*/
uint16_t EE_Init(void)
{
8000f60: b580 push {r7, lr}
8000f62: b082 sub sp, #8
8000f64: af00 add r7, sp, #0
uint16_t status0 = EE_GetPageStatus(EE_PAGE0_BASE);
8000f66: 481e ldr r0, [pc, #120] @ (8000fe0 <EE_Init+0x80>)
8000f68: f7ff fe8c bl 8000c84 <EE_GetPageStatus>
8000f6c: 4603 mov r3, r0
8000f6e: 80fb strh r3, [r7, #6]
uint16_t status1 = EE_GetPageStatus(EE_PAGE1_BASE);
8000f70: 481c ldr r0, [pc, #112] @ (8000fe4 <EE_Init+0x84>)
8000f72: f7ff fe87 bl 8000c84 <EE_GetPageStatus>
8000f76: 4603 mov r3, r0
8000f78: 80bb strh r3, [r7, #4]
if ((status0 == EE_PAGE_STATUS_ERASED) && (status1 == EE_PAGE_STATUS_ERASED))
8000f7a: 88fb ldrh r3, [r7, #6]
8000f7c: f64f 72ff movw r2, #65535 @ 0xffff
8000f80: 4293 cmp r3, r2
8000f82: d108 bne.n 8000f96 <EE_Init+0x36>
8000f84: 88bb ldrh r3, [r7, #4]
8000f86: f64f 72ff movw r2, #65535 @ 0xffff
8000f8a: 4293 cmp r3, r2
8000f8c: d103 bne.n 8000f96 <EE_Init+0x36>
{
/* Fresh device -> format */
return (uint16_t)EE_Format();
8000f8e: f7ff ff25 bl 8000ddc <EE_Format>
8000f92: 4603 mov r3, r0
8000f94: e020 b.n 8000fd8 <EE_Init+0x78>
}
else if ((status0 == EE_PAGE_STATUS_VALID) && (status1 == EE_PAGE_STATUS_ERASED))
8000f96: 88fb ldrh r3, [r7, #6]
8000f98: f64a 22aa movw r2, #43690 @ 0xaaaa
8000f9c: 4293 cmp r3, r2
8000f9e: d109 bne.n 8000fb4 <EE_Init+0x54>
8000fa0: 88bb ldrh r3, [r7, #4]
8000fa2: f64f 72ff movw r2, #65535 @ 0xffff
8000fa6: 4293 cmp r3, r2
8000fa8: d104 bne.n 8000fb4 <EE_Init+0x54>
{
EE_ActivePageBase = EE_PAGE0_BASE;
8000faa: 4b0f ldr r3, [pc, #60] @ (8000fe8 <EE_Init+0x88>)
8000fac: 4a0c ldr r2, [pc, #48] @ (8000fe0 <EE_Init+0x80>)
8000fae: 601a str r2, [r3, #0]
return EE_OK;
8000fb0: 2300 movs r3, #0
8000fb2: e011 b.n 8000fd8 <EE_Init+0x78>
}
else if ((status1 == EE_PAGE_STATUS_VALID) && (status0 == EE_PAGE_STATUS_ERASED))
8000fb4: 88bb ldrh r3, [r7, #4]
8000fb6: f64a 22aa movw r2, #43690 @ 0xaaaa
8000fba: 4293 cmp r3, r2
8000fbc: d109 bne.n 8000fd2 <EE_Init+0x72>
8000fbe: 88fb ldrh r3, [r7, #6]
8000fc0: f64f 72ff movw r2, #65535 @ 0xffff
8000fc4: 4293 cmp r3, r2
8000fc6: d104 bne.n 8000fd2 <EE_Init+0x72>
{
EE_ActivePageBase = EE_PAGE1_BASE;
8000fc8: 4b07 ldr r3, [pc, #28] @ (8000fe8 <EE_Init+0x88>)
8000fca: 4a06 ldr r2, [pc, #24] @ (8000fe4 <EE_Init+0x84>)
8000fcc: 601a str r2, [r3, #0]
return EE_OK;
8000fce: 2300 movs r3, #0
8000fd0: e002 b.n 8000fd8 <EE_Init+0x78>
}
else
{
/* Any weird or inconsistent state -> reformat */
return (uint16_t)EE_Format();
8000fd2: f7ff ff03 bl 8000ddc <EE_Format>
8000fd6: 4603 mov r3, r0
}
}
8000fd8: 4618 mov r0, r3
8000fda: 3708 adds r7, #8
8000fdc: 46bd mov sp, r7
8000fde: bd80 pop {r7, pc}
8000fe0: 0800f800 .word 0x0800f800
8000fe4: 0800fc00 .word 0x0800fc00
8000fe8: 20000000 .word 0x20000000
08000fec <EE_ReadVariable>:
/*
* Read a 16-bit variable by its virtual address.
* PUBLIC RETURN: EE_OK / EE_NOT_FOUND / EE_ERROR (as uint16_t)
*/
uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data)
{
8000fec: b580 push {r7, lr}
8000fee: b084 sub sp, #16
8000ff0: af00 add r7, sp, #0
8000ff2: 4603 mov r3, r0
8000ff4: 6039 str r1, [r7, #0]
8000ff6: 80fb strh r3, [r7, #6]
EE_Status st;
if (Data == NULL)
8000ff8: 683b ldr r3, [r7, #0]
8000ffa: 2b00 cmp r3, #0
8000ffc: d101 bne.n 8001002 <EE_ReadVariable+0x16>
return EE_ERROR;
8000ffe: 2301 movs r3, #1
8001000: e00a b.n 8001018 <EE_ReadVariable+0x2c>
st = EE_FindInPage(EE_ActivePageBase, VirtAddress, Data);
8001002: 4b07 ldr r3, [pc, #28] @ (8001020 <EE_ReadVariable+0x34>)
8001004: 681b ldr r3, [r3, #0]
8001006: 88f9 ldrh r1, [r7, #6]
8001008: 683a ldr r2, [r7, #0]
800100a: 4618 mov r0, r3
800100c: f7ff fea4 bl 8000d58 <EE_FindInPage>
8001010: 4603 mov r3, r0
8001012: 73fb strb r3, [r7, #15]
return (uint16_t)st;
8001014: 7bfb ldrb r3, [r7, #15]
8001016: b29b uxth r3, r3
}
8001018: 4618 mov r0, r3
800101a: 3710 adds r7, #16
800101c: 46bd mov sp, r7
800101e: bd80 pop {r7, pc}
8001020: 20000000 .word 0x20000000
08001024 <EE_WriteVariable>:
* - Writes a new record in the active page.
* - If the page is full, triggers a page transfer (GC).
* PUBLIC RETURN: EE_OK / EE_ERROR / EE_NO_SPACE (as uint16_t)
*/
uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data)
{
8001024: b580 push {r7, lr}
8001026: b084 sub sp, #16
8001028: af00 add r7, sp, #0
800102a: 4603 mov r3, r0
800102c: 460a mov r2, r1
800102e: 80fb strh r3, [r7, #6]
8001030: 4613 mov r3, r2
8001032: 80bb strh r3, [r7, #4]
uint32_t freeAddr;
EE_Status st;
/* Find free space in active page */
freeAddr = EE_FindFreeAddress(EE_ActivePageBase);
8001034: 4b17 ldr r3, [pc, #92] @ (8001094 <EE_WriteVariable+0x70>)
8001036: 681b ldr r3, [r3, #0]
8001038: 4618 mov r0, r3
800103a: f7ff fe69 bl 8000d10 <EE_FindFreeAddress>
800103e: 60f8 str r0, [r7, #12]
if (freeAddr != 0U)
8001040: 68fb ldr r3, [r7, #12]
8001042: 2b00 cmp r3, #0
8001044: d017 beq.n 8001076 <EE_WriteVariable+0x52>
{
/* Write new record */
if (EE_FlashProgramHalfWord(freeAddr, VirtAddress) != HAL_OK)
8001046: 88fb ldrh r3, [r7, #6]
8001048: 4619 mov r1, r3
800104a: 68f8 ldr r0, [r7, #12]
800104c: f7ff fe26 bl 8000c9c <EE_FlashProgramHalfWord>
8001050: 4603 mov r3, r0
8001052: 2b00 cmp r3, #0
8001054: d001 beq.n 800105a <EE_WriteVariable+0x36>
return EE_ERROR;
8001056: 2301 movs r3, #1
8001058: e017 b.n 800108a <EE_WriteVariable+0x66>
if (EE_FlashProgramHalfWord(freeAddr + 2U, Data) != HAL_OK)
800105a: 68fb ldr r3, [r7, #12]
800105c: 3302 adds r3, #2
800105e: 88ba ldrh r2, [r7, #4]
8001060: 4611 mov r1, r2
8001062: 4618 mov r0, r3
8001064: f7ff fe1a bl 8000c9c <EE_FlashProgramHalfWord>
8001068: 4603 mov r3, r0
800106a: 2b00 cmp r3, #0
800106c: d001 beq.n 8001072 <EE_WriteVariable+0x4e>
return EE_ERROR;
800106e: 2301 movs r3, #1
8001070: e00b b.n 800108a <EE_WriteVariable+0x66>
return EE_OK;
8001072: 2300 movs r3, #0
8001074: e009 b.n 800108a <EE_WriteVariable+0x66>
}
/* No space -> page transfer */
st = EE_PageTransfer(VirtAddress, Data);
8001076: 88ba ldrh r2, [r7, #4]
8001078: 88fb ldrh r3, [r7, #6]
800107a: 4611 mov r1, r2
800107c: 4618 mov r0, r3
800107e: f7ff fee9 bl 8000e54 <EE_PageTransfer>
8001082: 4603 mov r3, r0
8001084: 72fb strb r3, [r7, #11]
return (uint16_t)st;
8001086: 7afb ldrb r3, [r7, #11]
8001088: b29b uxth r3, r3
}
800108a: 4618 mov r0, r3
800108c: 3710 adds r7, #16
800108e: 46bd mov sp, r7
8001090: bd80 pop {r7, pc}
8001092: bf00 nop
8001094: 20000000 .word 0x20000000
08001098 <HAL_SYSTICK_Callback>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_SYSTICK_Callback(void){
8001098: b580 push {r7, lr}
800109a: af00 add r7, sp, #0
static uint8_t c100ms = 0;
static uint8_t c1s = 0;
static uint8_t inidx=0;
static uint8_t inbuf[4];
if (++c10ms >= 10) { // 10 ms
800109c: 4b53 ldr r3, [pc, #332] @ (80011ec <HAL_SYSTICK_Callback+0x154>)
800109e: 781b ldrb r3, [r3, #0]
80010a0: 3301 adds r3, #1
80010a2: b2da uxtb r2, r3
80010a4: 4b51 ldr r3, [pc, #324] @ (80011ec <HAL_SYSTICK_Callback+0x154>)
80010a6: 701a strb r2, [r3, #0]
80010a8: 4b50 ldr r3, [pc, #320] @ (80011ec <HAL_SYSTICK_Callback+0x154>)
80010aa: 781b ldrb r3, [r3, #0]
80010ac: 2b09 cmp r3, #9
80010ae: f240 809b bls.w 80011e8 <HAL_SYSTICK_Callback+0x150>
c10ms = 0;
80010b2: 4b4e ldr r3, [pc, #312] @ (80011ec <HAL_SYSTICK_Callback+0x154>)
80010b4: 2200 movs r2, #0
80010b6: 701a strb r2, [r3, #0]
//**** legge i tasti********************************************************************************
inidx++;
80010b8: 4b4d ldr r3, [pc, #308] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010ba: 781b ldrb r3, [r3, #0]
80010bc: 3301 adds r3, #1
80010be: b2da uxtb r2, r3
80010c0: 4b4b ldr r3, [pc, #300] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010c2: 701a strb r2, [r3, #0]
inidx&=0x03;
80010c4: 4b4a ldr r3, [pc, #296] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010c6: 781b ldrb r3, [r3, #0]
80010c8: f003 0303 and.w r3, r3, #3
80010cc: b2da uxtb r2, r3
80010ce: 4b48 ldr r3, [pc, #288] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010d0: 701a strb r2, [r3, #0]
if(HAL_GPIO_ReadPin(P1_GPIO_Port, P1_Pin)==GPIO_PIN_SET)inbuf[inidx]|=INP1;else inbuf[inidx]&=(~INP1);
80010d2: f44f 4180 mov.w r1, #16384 @ 0x4000
80010d6: 4847 ldr r0, [pc, #284] @ (80011f4 <HAL_SYSTICK_Callback+0x15c>)
80010d8: f002 fac4 bl 8003664 <HAL_GPIO_ReadPin>
80010dc: 4603 mov r3, r0
80010de: 2b01 cmp r3, #1
80010e0: d10c bne.n 80010fc <HAL_SYSTICK_Callback+0x64>
80010e2: 4b43 ldr r3, [pc, #268] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010e4: 781b ldrb r3, [r3, #0]
80010e6: 461a mov r2, r3
80010e8: 4b43 ldr r3, [pc, #268] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
80010ea: 5c9b ldrb r3, [r3, r2]
80010ec: 4a40 ldr r2, [pc, #256] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010ee: 7812 ldrb r2, [r2, #0]
80010f0: f043 0301 orr.w r3, r3, #1
80010f4: b2d9 uxtb r1, r3
80010f6: 4b40 ldr r3, [pc, #256] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
80010f8: 5499 strb r1, [r3, r2]
80010fa: e00b b.n 8001114 <HAL_SYSTICK_Callback+0x7c>
80010fc: 4b3c ldr r3, [pc, #240] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
80010fe: 781b ldrb r3, [r3, #0]
8001100: 461a mov r2, r3
8001102: 4b3d ldr r3, [pc, #244] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001104: 5c9b ldrb r3, [r3, r2]
8001106: 4a3a ldr r2, [pc, #232] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
8001108: 7812 ldrb r2, [r2, #0]
800110a: f023 0301 bic.w r3, r3, #1
800110e: b2d9 uxtb r1, r3
8001110: 4b39 ldr r3, [pc, #228] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001112: 5499 strb r1, [r3, r2]
if(HAL_GPIO_ReadPin(P2_GPIO_Port, P2_Pin)==GPIO_PIN_SET)inbuf[inidx]|=INP2;else inbuf[inidx]&=(~INP2);
8001114: f44f 4100 mov.w r1, #32768 @ 0x8000
8001118: 4836 ldr r0, [pc, #216] @ (80011f4 <HAL_SYSTICK_Callback+0x15c>)
800111a: f002 faa3 bl 8003664 <HAL_GPIO_ReadPin>
800111e: 4603 mov r3, r0
8001120: 2b01 cmp r3, #1
8001122: d10c bne.n 800113e <HAL_SYSTICK_Callback+0xa6>
8001124: 4b32 ldr r3, [pc, #200] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
8001126: 781b ldrb r3, [r3, #0]
8001128: 461a mov r2, r3
800112a: 4b33 ldr r3, [pc, #204] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
800112c: 5c9b ldrb r3, [r3, r2]
800112e: 4a30 ldr r2, [pc, #192] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
8001130: 7812 ldrb r2, [r2, #0]
8001132: f043 0302 orr.w r3, r3, #2
8001136: b2d9 uxtb r1, r3
8001138: 4b2f ldr r3, [pc, #188] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
800113a: 5499 strb r1, [r3, r2]
800113c: e00b b.n 8001156 <HAL_SYSTICK_Callback+0xbe>
800113e: 4b2c ldr r3, [pc, #176] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
8001140: 781b ldrb r3, [r3, #0]
8001142: 461a mov r2, r3
8001144: 4b2c ldr r3, [pc, #176] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001146: 5c9b ldrb r3, [r3, r2]
8001148: 4a29 ldr r2, [pc, #164] @ (80011f0 <HAL_SYSTICK_Callback+0x158>)
800114a: 7812 ldrb r2, [r2, #0]
800114c: f023 0302 bic.w r3, r3, #2
8001150: b2d9 uxtb r1, r3
8001152: 4b29 ldr r3, [pc, #164] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001154: 5499 strb r1, [r3, r2]
pulsanti|=(inbuf[0]&inbuf[1]&inbuf[2]&inbuf[3]);
8001156: 4b28 ldr r3, [pc, #160] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001158: 781a ldrb r2, [r3, #0]
800115a: 4b27 ldr r3, [pc, #156] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
800115c: 785b ldrb r3, [r3, #1]
800115e: 4013 ands r3, r2
8001160: b2da uxtb r2, r3
8001162: 4b25 ldr r3, [pc, #148] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001164: 789b ldrb r3, [r3, #2]
8001166: 4013 ands r3, r2
8001168: b2da uxtb r2, r3
800116a: 4b23 ldr r3, [pc, #140] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
800116c: 78db ldrb r3, [r3, #3]
800116e: 4013 ands r3, r2
8001170: b2da uxtb r2, r3
8001172: 4b22 ldr r3, [pc, #136] @ (80011fc <HAL_SYSTICK_Callback+0x164>)
8001174: 781b ldrb r3, [r3, #0]
8001176: 4313 orrs r3, r2
8001178: b2da uxtb r2, r3
800117a: 4b20 ldr r3, [pc, #128] @ (80011fc <HAL_SYSTICK_Callback+0x164>)
800117c: 701a strb r2, [r3, #0]
pulsanti&=(inbuf[0]|inbuf[1]|inbuf[2]|inbuf[3]);
800117e: 4b1e ldr r3, [pc, #120] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001180: 781a ldrb r2, [r3, #0]
8001182: 4b1d ldr r3, [pc, #116] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001184: 785b ldrb r3, [r3, #1]
8001186: 4313 orrs r3, r2
8001188: b2da uxtb r2, r3
800118a: 4b1b ldr r3, [pc, #108] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
800118c: 789b ldrb r3, [r3, #2]
800118e: 4313 orrs r3, r2
8001190: b2da uxtb r2, r3
8001192: 4b19 ldr r3, [pc, #100] @ (80011f8 <HAL_SYSTICK_Callback+0x160>)
8001194: 78db ldrb r3, [r3, #3]
8001196: 4313 orrs r3, r2
8001198: b2da uxtb r2, r3
800119a: 4b18 ldr r3, [pc, #96] @ (80011fc <HAL_SYSTICK_Callback+0x164>)
800119c: 781b ldrb r3, [r3, #0]
800119e: 4013 ands r3, r2
80011a0: b2da uxtb r2, r3
80011a2: 4b16 ldr r3, [pc, #88] @ (80011fc <HAL_SYSTICK_Callback+0x164>)
80011a4: 701a strb r2, [r3, #0]
//**** legge adc ***********************************************************************************
readAdc();
80011a6: f7ff f80f bl 80001c8 <readAdc>
if (++c100ms >= 10) { // 10 ms
80011aa: 4b15 ldr r3, [pc, #84] @ (8001200 <HAL_SYSTICK_Callback+0x168>)
80011ac: 781b ldrb r3, [r3, #0]
80011ae: 3301 adds r3, #1
80011b0: b2da uxtb r2, r3
80011b2: 4b13 ldr r3, [pc, #76] @ (8001200 <HAL_SYSTICK_Callback+0x168>)
80011b4: 701a strb r2, [r3, #0]
80011b6: 4b12 ldr r3, [pc, #72] @ (8001200 <HAL_SYSTICK_Callback+0x168>)
80011b8: 781b ldrb r3, [r3, #0]
80011ba: 2b09 cmp r3, #9
80011bc: d914 bls.n 80011e8 <HAL_SYSTICK_Callback+0x150>
c100ms = 0; //flag_10ms = 1; // set a flag; do real work in main loop
80011be: 4b10 ldr r3, [pc, #64] @ (8001200 <HAL_SYSTICK_Callback+0x168>)
80011c0: 2200 movs r2, #0
80011c2: 701a strb r2, [r3, #0]
if (++c1s >= 10) { // 10 ms
80011c4: 4b0f ldr r3, [pc, #60] @ (8001204 <HAL_SYSTICK_Callback+0x16c>)
80011c6: 781b ldrb r3, [r3, #0]
80011c8: 3301 adds r3, #1
80011ca: b2da uxtb r2, r3
80011cc: 4b0d ldr r3, [pc, #52] @ (8001204 <HAL_SYSTICK_Callback+0x16c>)
80011ce: 701a strb r2, [r3, #0]
80011d0: 4b0c ldr r3, [pc, #48] @ (8001204 <HAL_SYSTICK_Callback+0x16c>)
80011d2: 781b ldrb r3, [r3, #0]
80011d4: 2b09 cmp r3, #9
80011d6: d907 bls.n 80011e8 <HAL_SYSTICK_Callback+0x150>
c1s = 0;
80011d8: 4b0a ldr r3, [pc, #40] @ (8001204 <HAL_SYSTICK_Callback+0x16c>)
80011da: 2200 movs r2, #0
80011dc: 701a strb r2, [r3, #0]
HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
80011de: f44f 5100 mov.w r1, #8192 @ 0x2000
80011e2: 4804 ldr r0, [pc, #16] @ (80011f4 <HAL_SYSTICK_Callback+0x15c>)
80011e4: f002 fa6d bl 80036c2 <HAL_GPIO_TogglePin>
}
}
}
}
80011e8: bf00 nop
80011ea: bd80 pop {r7, pc}
80011ec: 200003d9 .word 0x200003d9
80011f0: 200003da .word 0x200003da
80011f4: 40011000 .word 0x40011000
80011f8: 200003dc .word 0x200003dc
80011fc: 200003d8 .word 0x200003d8
8001200: 200003e0 .word 0x200003e0
8001204: 200003e1 .word 0x200003e1
08001208 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8001208: b580 push {r7, lr}
800120a: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800120c: f000 ff76 bl 80020fc <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8001210: f000 f852 bl 80012b8 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8001214: f000 fab4 bl 8001780 <MX_GPIO_Init>
MX_DMA_Init();
8001218: f000 fa94 bl 8001744 <MX_DMA_Init>
MX_USB_DEVICE_Init();
800121c: f009 fade bl 800a7dc <MX_USB_DEVICE_Init>
MX_TIM2_Init();
8001220: f000 f920 bl 8001464 <MX_TIM2_Init>
MX_TIM4_Init();
8001224: f000 f9c2 bl 80015ac <MX_TIM4_Init>
MX_ADC1_Init();
8001228: f000 f8a4 bl 8001374 <MX_ADC1_Init>
MX_USART1_UART_Init();
800122c: f000 fa60 bl 80016f0 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_buf, ADC_NUM_CHANNELS);
8001230: 2205 movs r2, #5
8001232: 491c ldr r1, [pc, #112] @ (80012a4 <main+0x9c>)
8001234: 481c ldr r0, [pc, #112] @ (80012a8 <main+0xa0>)
8001236: f001 f89b bl 8002370 <HAL_ADC_Start_DMA>
StopMot(timMot1,FWMot1);
800123a: 2100 movs r1, #0
800123c: 481b ldr r0, [pc, #108] @ (80012ac <main+0xa4>)
800123e: f000 fb64 bl 800190a <StopMot>
StopMot(timMot1,BWMot1);
8001242: 2104 movs r1, #4
8001244: 4819 ldr r0, [pc, #100] @ (80012ac <main+0xa4>)
8001246: f000 fb60 bl 800190a <StopMot>
StopMot(timMot2,FWMot2);
800124a: 2108 movs r1, #8
800124c: 4817 ldr r0, [pc, #92] @ (80012ac <main+0xa4>)
800124e: f000 fb5c bl 800190a <StopMot>
StopMot(timMot2,BWMot2);
8001252: 210c movs r1, #12
8001254: 4815 ldr r0, [pc, #84] @ (80012ac <main+0xa4>)
8001256: f000 fb58 bl 800190a <StopMot>
StopMot(timMot3,FWMot3);
800125a: 2100 movs r1, #0
800125c: 4814 ldr r0, [pc, #80] @ (80012b0 <main+0xa8>)
800125e: f000 fb54 bl 800190a <StopMot>
StopMot(timMot3,BWMot3);
8001262: 2104 movs r1, #4
8001264: 4812 ldr r0, [pc, #72] @ (80012b0 <main+0xa8>)
8001266: f000 fb50 bl 800190a <StopMot>
StopMot(timMot4,FWMot4);
800126a: 2108 movs r1, #8
800126c: 4810 ldr r0, [pc, #64] @ (80012b0 <main+0xa8>)
800126e: f000 fb4c bl 800190a <StopMot>
StopMot(timMot4,BWMot4);
8001272: 210c movs r1, #12
8001274: 480e ldr r0, [pc, #56] @ (80012b0 <main+0xa8>)
8001276: f000 fb48 bl 800190a <StopMot>
//CDC_Transmit_FS((uint8_t*)"Start\r\n", 7);
while (CDC_Transmit_FS((uint8_t*)"Start\r\n", 7) == USBD_BUSY);
800127a: bf00 nop
800127c: 2107 movs r1, #7
800127e: 480d ldr r0, [pc, #52] @ (80012b4 <main+0xac>)
8001280: f009 fbe8 bl 800aa54 <CDC_Transmit_FS>
8001284: 4603 mov r3, r0
8001286: 2b01 cmp r3, #1
8001288: d0f8 beq.n 800127c <main+0x74>
if (EE_Init() != EE_OK){
800128a: f7ff fe69 bl 8000f60 <EE_Init>
800128e: 4603 mov r3, r0
8001290: 2b00 cmp r3, #0
8001292: d001 beq.n 8001298 <main+0x90>
for(;;);//errore eeprom
8001294: bf00 nop
8001296: e7fd b.n 8001294 <main+0x8c>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1){
manageCDC();
8001298: f7ff f8b0 bl 80003fc <manageCDC>
manageAdc();
800129c: f7fe ff5e bl 800015c <manageAdc>
manageCDC();
80012a0: e7fa b.n 8001298 <main+0x90>
80012a2: bf00 nop
80012a4: 200001ec .word 0x200001ec
80012a8: 2000028c .word 0x2000028c
80012ac: 20000300 .word 0x20000300
80012b0: 20000348 .word 0x20000348
80012b4: 0800bd58 .word 0x0800bd58
080012b8 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80012b8: b580 push {r7, lr}
80012ba: b094 sub sp, #80 @ 0x50
80012bc: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80012be: f107 0328 add.w r3, r7, #40 @ 0x28
80012c2: 2228 movs r2, #40 @ 0x28
80012c4: 2100 movs r1, #0
80012c6: 4618 mov r0, r3
80012c8: f009 ffc4 bl 800b254 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80012cc: f107 0314 add.w r3, r7, #20
80012d0: 2200 movs r2, #0
80012d2: 601a str r2, [r3, #0]
80012d4: 605a str r2, [r3, #4]
80012d6: 609a str r2, [r3, #8]
80012d8: 60da str r2, [r3, #12]
80012da: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80012dc: 1d3b adds r3, r7, #4
80012de: 2200 movs r2, #0
80012e0: 601a str r2, [r3, #0]
80012e2: 605a str r2, [r3, #4]
80012e4: 609a str r2, [r3, #8]
80012e6: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80012e8: 2301 movs r3, #1
80012ea: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80012ec: f44f 3380 mov.w r3, #65536 @ 0x10000
80012f0: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
80012f2: 2300 movs r3, #0
80012f4: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80012f6: 2301 movs r3, #1
80012f8: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80012fa: 2302 movs r3, #2
80012fc: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80012fe: f44f 3380 mov.w r3, #65536 @ 0x10000
8001302: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
8001304: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000
8001308: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800130a: f107 0328 add.w r3, r7, #40 @ 0x28
800130e: 4618 mov r0, r3
8001310: f003 ff50 bl 80051b4 <HAL_RCC_OscConfig>
8001314: 4603 mov r3, r0
8001316: 2b00 cmp r3, #0
8001318: d001 beq.n 800131e <SystemClock_Config+0x66>
{
Error_Handler();
800131a: f000 fadb bl 80018d4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800131e: 230f movs r3, #15
8001320: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8001322: 2302 movs r3, #2
8001324: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8001326: 2300 movs r3, #0
8001328: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
800132a: f44f 6380 mov.w r3, #1024 @ 0x400
800132e: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8001330: 2300 movs r3, #0
8001332: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
8001334: f107 0314 add.w r3, r7, #20
8001338: 2102 movs r1, #2
800133a: 4618 mov r0, r3
800133c: f004 f9bc bl 80056b8 <HAL_RCC_ClockConfig>
8001340: 4603 mov r3, r0
8001342: 2b00 cmp r3, #0
8001344: d001 beq.n 800134a <SystemClock_Config+0x92>
{
Error_Handler();
8001346: f000 fac5 bl 80018d4 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
800134a: 2312 movs r3, #18
800134c: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
800134e: f44f 4300 mov.w r3, #32768 @ 0x8000
8001352: 60fb str r3, [r7, #12]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
8001354: 2300 movs r3, #0
8001356: 613b str r3, [r7, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001358: 1d3b adds r3, r7, #4
800135a: 4618 mov r0, r3
800135c: f004 fb3a bl 80059d4 <HAL_RCCEx_PeriphCLKConfig>
8001360: 4603 mov r3, r0
8001362: 2b00 cmp r3, #0
8001364: d001 beq.n 800136a <SystemClock_Config+0xb2>
{
Error_Handler();
8001366: f000 fab5 bl 80018d4 <Error_Handler>
}
}
800136a: bf00 nop
800136c: 3750 adds r7, #80 @ 0x50
800136e: 46bd mov sp, r7
8001370: bd80 pop {r7, pc}
...
08001374 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8001374: b580 push {r7, lr}
8001376: b084 sub sp, #16
8001378: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800137a: 1d3b adds r3, r7, #4
800137c: 2200 movs r2, #0
800137e: 601a str r2, [r3, #0]
8001380: 605a str r2, [r3, #4]
8001382: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8001384: 4b35 ldr r3, [pc, #212] @ (800145c <MX_ADC1_Init+0xe8>)
8001386: 4a36 ldr r2, [pc, #216] @ (8001460 <MX_ADC1_Init+0xec>)
8001388: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
800138a: 4b34 ldr r3, [pc, #208] @ (800145c <MX_ADC1_Init+0xe8>)
800138c: f44f 7280 mov.w r2, #256 @ 0x100
8001390: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
8001392: 4b32 ldr r3, [pc, #200] @ (800145c <MX_ADC1_Init+0xe8>)
8001394: 2201 movs r2, #1
8001396: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8001398: 4b30 ldr r3, [pc, #192] @ (800145c <MX_ADC1_Init+0xe8>)
800139a: 2200 movs r2, #0
800139c: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
800139e: 4b2f ldr r3, [pc, #188] @ (800145c <MX_ADC1_Init+0xe8>)
80013a0: f44f 2260 mov.w r2, #917504 @ 0xe0000
80013a4: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80013a6: 4b2d ldr r3, [pc, #180] @ (800145c <MX_ADC1_Init+0xe8>)
80013a8: 2200 movs r2, #0
80013aa: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 5;
80013ac: 4b2b ldr r3, [pc, #172] @ (800145c <MX_ADC1_Init+0xe8>)
80013ae: 2205 movs r2, #5
80013b0: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80013b2: 482a ldr r0, [pc, #168] @ (800145c <MX_ADC1_Init+0xe8>)
80013b4: f000 ff04 bl 80021c0 <HAL_ADC_Init>
80013b8: 4603 mov r3, r0
80013ba: 2b00 cmp r3, #0
80013bc: d001 beq.n 80013c2 <MX_ADC1_Init+0x4e>
{
Error_Handler();
80013be: f000 fa89 bl 80018d4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
80013c2: 2304 movs r3, #4
80013c4: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80013c6: 2301 movs r3, #1
80013c8: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_28CYCLES_5;
80013ca: 2303 movs r3, #3
80013cc: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80013ce: 1d3b adds r3, r7, #4
80013d0: 4619 mov r1, r3
80013d2: 4822 ldr r0, [pc, #136] @ (800145c <MX_ADC1_Init+0xe8>)
80013d4: f001 f8c6 bl 8002564 <HAL_ADC_ConfigChannel>
80013d8: 4603 mov r3, r0
80013da: 2b00 cmp r3, #0
80013dc: d001 beq.n 80013e2 <MX_ADC1_Init+0x6e>
{
Error_Handler();
80013de: f000 fa79 bl 80018d4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
80013e2: 2305 movs r3, #5
80013e4: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_2;
80013e6: 2302 movs r3, #2
80013e8: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80013ea: 1d3b adds r3, r7, #4
80013ec: 4619 mov r1, r3
80013ee: 481b ldr r0, [pc, #108] @ (800145c <MX_ADC1_Init+0xe8>)
80013f0: f001 f8b8 bl 8002564 <HAL_ADC_ConfigChannel>
80013f4: 4603 mov r3, r0
80013f6: 2b00 cmp r3, #0
80013f8: d001 beq.n 80013fe <MX_ADC1_Init+0x8a>
{
Error_Handler();
80013fa: f000 fa6b bl 80018d4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_6;
80013fe: 2306 movs r3, #6
8001400: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_3;
8001402: 2303 movs r3, #3
8001404: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001406: 1d3b adds r3, r7, #4
8001408: 4619 mov r1, r3
800140a: 4814 ldr r0, [pc, #80] @ (800145c <MX_ADC1_Init+0xe8>)
800140c: f001 f8aa bl 8002564 <HAL_ADC_ConfigChannel>
8001410: 4603 mov r3, r0
8001412: 2b00 cmp r3, #0
8001414: d001 beq.n 800141a <MX_ADC1_Init+0xa6>
{
Error_Handler();
8001416: f000 fa5d bl 80018d4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_7;
800141a: 2307 movs r3, #7
800141c: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_4;
800141e: 2304 movs r3, #4
8001420: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001422: 1d3b adds r3, r7, #4
8001424: 4619 mov r1, r3
8001426: 480d ldr r0, [pc, #52] @ (800145c <MX_ADC1_Init+0xe8>)
8001428: f001 f89c bl 8002564 <HAL_ADC_ConfigChannel>
800142c: 4603 mov r3, r0
800142e: 2b00 cmp r3, #0
8001430: d001 beq.n 8001436 <MX_ADC1_Init+0xc2>
{
Error_Handler();
8001432: f000 fa4f bl 80018d4 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_8;
8001436: 2308 movs r3, #8
8001438: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_5;
800143a: 2305 movs r3, #5
800143c: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
800143e: 1d3b adds r3, r7, #4
8001440: 4619 mov r1, r3
8001442: 4806 ldr r0, [pc, #24] @ (800145c <MX_ADC1_Init+0xe8>)
8001444: f001 f88e bl 8002564 <HAL_ADC_ConfigChannel>
8001448: 4603 mov r3, r0
800144a: 2b00 cmp r3, #0
800144c: d001 beq.n 8001452 <MX_ADC1_Init+0xde>
{
Error_Handler();
800144e: f000 fa41 bl 80018d4 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8001452: bf00 nop
8001454: 3710 adds r7, #16
8001456: 46bd mov sp, r7
8001458: bd80 pop {r7, pc}
800145a: bf00 nop
800145c: 2000028c .word 0x2000028c
8001460: 40012400 .word 0x40012400
08001464 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8001464: b580 push {r7, lr}
8001466: b08e sub sp, #56 @ 0x38
8001468: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800146a: f107 0328 add.w r3, r7, #40 @ 0x28
800146e: 2200 movs r2, #0
8001470: 601a str r2, [r3, #0]
8001472: 605a str r2, [r3, #4]
8001474: 609a str r2, [r3, #8]
8001476: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001478: f107 0320 add.w r3, r7, #32
800147c: 2200 movs r2, #0
800147e: 601a str r2, [r3, #0]
8001480: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8001482: 1d3b adds r3, r7, #4
8001484: 2200 movs r2, #0
8001486: 601a str r2, [r3, #0]
8001488: 605a str r2, [r3, #4]
800148a: 609a str r2, [r3, #8]
800148c: 60da str r2, [r3, #12]
800148e: 611a str r2, [r3, #16]
8001490: 615a str r2, [r3, #20]
8001492: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8001494: 4b44 ldr r3, [pc, #272] @ (80015a8 <MX_TIM2_Init+0x144>)
8001496: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
800149a: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
800149c: 4b42 ldr r3, [pc, #264] @ (80015a8 <MX_TIM2_Init+0x144>)
800149e: 2200 movs r2, #0
80014a0: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
80014a2: 4b41 ldr r3, [pc, #260] @ (80015a8 <MX_TIM2_Init+0x144>)
80014a4: 2200 movs r2, #0
80014a6: 609a str r2, [r3, #8]
htim2.Init.Period = 17999;
80014a8: 4b3f ldr r3, [pc, #252] @ (80015a8 <MX_TIM2_Init+0x144>)
80014aa: f244 624f movw r2, #17999 @ 0x464f
80014ae: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80014b0: 4b3d ldr r3, [pc, #244] @ (80015a8 <MX_TIM2_Init+0x144>)
80014b2: 2200 movs r2, #0
80014b4: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80014b6: 4b3c ldr r3, [pc, #240] @ (80015a8 <MX_TIM2_Init+0x144>)
80014b8: 2200 movs r2, #0
80014ba: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
80014bc: 483a ldr r0, [pc, #232] @ (80015a8 <MX_TIM2_Init+0x144>)
80014be: f004 fb3f bl 8005b40 <HAL_TIM_Base_Init>
80014c2: 4603 mov r3, r0
80014c4: 2b00 cmp r3, #0
80014c6: d001 beq.n 80014cc <MX_TIM2_Init+0x68>
{
Error_Handler();
80014c8: f000 fa04 bl 80018d4 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80014cc: f44f 5380 mov.w r3, #4096 @ 0x1000
80014d0: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
80014d2: f107 0328 add.w r3, r7, #40 @ 0x28
80014d6: 4619 mov r1, r3
80014d8: 4833 ldr r0, [pc, #204] @ (80015a8 <MX_TIM2_Init+0x144>)
80014da: f004 fda1 bl 8006020 <HAL_TIM_ConfigClockSource>
80014de: 4603 mov r3, r0
80014e0: 2b00 cmp r3, #0
80014e2: d001 beq.n 80014e8 <MX_TIM2_Init+0x84>
{
Error_Handler();
80014e4: f000 f9f6 bl 80018d4 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
80014e8: 482f ldr r0, [pc, #188] @ (80015a8 <MX_TIM2_Init+0x144>)
80014ea: f004 fb78 bl 8005bde <HAL_TIM_PWM_Init>
80014ee: 4603 mov r3, r0
80014f0: 2b00 cmp r3, #0
80014f2: d001 beq.n 80014f8 <MX_TIM2_Init+0x94>
{
Error_Handler();
80014f4: f000 f9ee bl 80018d4 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80014f8: 2300 movs r3, #0
80014fa: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80014fc: 2300 movs r3, #0
80014fe: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8001500: f107 0320 add.w r3, r7, #32
8001504: 4619 mov r1, r3
8001506: 4828 ldr r0, [pc, #160] @ (80015a8 <MX_TIM2_Init+0x144>)
8001508: f005 f92a bl 8006760 <HAL_TIMEx_MasterConfigSynchronization>
800150c: 4603 mov r3, r0
800150e: 2b00 cmp r3, #0
8001510: d001 beq.n 8001516 <MX_TIM2_Init+0xb2>
{
Error_Handler();
8001512: f000 f9df bl 80018d4 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001516: 2360 movs r3, #96 @ 0x60
8001518: 607b str r3, [r7, #4]
sConfigOC.Pulse = 1000;
800151a: f44f 737a mov.w r3, #1000 @ 0x3e8
800151e: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001520: 2300 movs r3, #0
8001522: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8001524: 2304 movs r3, #4
8001526: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001528: 1d3b adds r3, r7, #4
800152a: 2200 movs r2, #0
800152c: 4619 mov r1, r3
800152e: 481e ldr r0, [pc, #120] @ (80015a8 <MX_TIM2_Init+0x144>)
8001530: f004 fcb4 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
8001534: 4603 mov r3, r0
8001536: 2b00 cmp r3, #0
8001538: d001 beq.n 800153e <MX_TIM2_Init+0xda>
{
Error_Handler();
800153a: f000 f9cb bl 80018d4 <Error_Handler>
}
sConfigOC.Pulse = 2000;
800153e: f44f 63fa mov.w r3, #2000 @ 0x7d0
8001542: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8001544: 1d3b adds r3, r7, #4
8001546: 2204 movs r2, #4
8001548: 4619 mov r1, r3
800154a: 4817 ldr r0, [pc, #92] @ (80015a8 <MX_TIM2_Init+0x144>)
800154c: f004 fca6 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
8001550: 4603 mov r3, r0
8001552: 2b00 cmp r3, #0
8001554: d001 beq.n 800155a <MX_TIM2_Init+0xf6>
{
Error_Handler();
8001556: f000 f9bd bl 80018d4 <Error_Handler>
}
sConfigOC.Pulse = 3000;
800155a: f640 33b8 movw r3, #3000 @ 0xbb8
800155e: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001560: 2300 movs r3, #0
8001562: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8001564: 1d3b adds r3, r7, #4
8001566: 2208 movs r2, #8
8001568: 4619 mov r1, r3
800156a: 480f ldr r0, [pc, #60] @ (80015a8 <MX_TIM2_Init+0x144>)
800156c: f004 fc96 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
8001570: 4603 mov r3, r0
8001572: 2b00 cmp r3, #0
8001574: d001 beq.n 800157a <MX_TIM2_Init+0x116>
{
Error_Handler();
8001576: f000 f9ad bl 80018d4 <Error_Handler>
}
sConfigOC.Pulse = 4000;
800157a: f44f 637a mov.w r3, #4000 @ 0xfa0
800157e: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8001580: 2304 movs r3, #4
8001582: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8001584: 1d3b adds r3, r7, #4
8001586: 220c movs r2, #12
8001588: 4619 mov r1, r3
800158a: 4807 ldr r0, [pc, #28] @ (80015a8 <MX_TIM2_Init+0x144>)
800158c: f004 fc86 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
8001590: 4603 mov r3, r0
8001592: 2b00 cmp r3, #0
8001594: d001 beq.n 800159a <MX_TIM2_Init+0x136>
{
Error_Handler();
8001596: f000 f99d bl 80018d4 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
800159a: 4803 ldr r0, [pc, #12] @ (80015a8 <MX_TIM2_Init+0x144>)
800159c: f000 fc6a bl 8001e74 <HAL_TIM_MspPostInit>
}
80015a0: bf00 nop
80015a2: 3738 adds r7, #56 @ 0x38
80015a4: 46bd mov sp, r7
80015a6: bd80 pop {r7, pc}
80015a8: 20000300 .word 0x20000300
080015ac <MX_TIM4_Init>:
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
80015ac: b580 push {r7, lr}
80015ae: b08e sub sp, #56 @ 0x38
80015b0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80015b2: f107 0328 add.w r3, r7, #40 @ 0x28
80015b6: 2200 movs r2, #0
80015b8: 601a str r2, [r3, #0]
80015ba: 605a str r2, [r3, #4]
80015bc: 609a str r2, [r3, #8]
80015be: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80015c0: f107 0320 add.w r3, r7, #32
80015c4: 2200 movs r2, #0
80015c6: 601a str r2, [r3, #0]
80015c8: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80015ca: 1d3b adds r3, r7, #4
80015cc: 2200 movs r2, #0
80015ce: 601a str r2, [r3, #0]
80015d0: 605a str r2, [r3, #4]
80015d2: 609a str r2, [r3, #8]
80015d4: 60da str r2, [r3, #12]
80015d6: 611a str r2, [r3, #16]
80015d8: 615a str r2, [r3, #20]
80015da: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
80015dc: 4b42 ldr r3, [pc, #264] @ (80016e8 <MX_TIM4_Init+0x13c>)
80015de: 4a43 ldr r2, [pc, #268] @ (80016ec <MX_TIM4_Init+0x140>)
80015e0: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 0;
80015e2: 4b41 ldr r3, [pc, #260] @ (80016e8 <MX_TIM4_Init+0x13c>)
80015e4: 2200 movs r2, #0
80015e6: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
80015e8: 4b3f ldr r3, [pc, #252] @ (80016e8 <MX_TIM4_Init+0x13c>)
80015ea: 2200 movs r2, #0
80015ec: 609a str r2, [r3, #8]
htim4.Init.Period = 17999;
80015ee: 4b3e ldr r3, [pc, #248] @ (80016e8 <MX_TIM4_Init+0x13c>)
80015f0: f244 624f movw r2, #17999 @ 0x464f
80015f4: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80015f6: 4b3c ldr r3, [pc, #240] @ (80016e8 <MX_TIM4_Init+0x13c>)
80015f8: 2200 movs r2, #0
80015fa: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80015fc: 4b3a ldr r3, [pc, #232] @ (80016e8 <MX_TIM4_Init+0x13c>)
80015fe: 2200 movs r2, #0
8001600: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
8001602: 4839 ldr r0, [pc, #228] @ (80016e8 <MX_TIM4_Init+0x13c>)
8001604: f004 fa9c bl 8005b40 <HAL_TIM_Base_Init>
8001608: 4603 mov r3, r0
800160a: 2b00 cmp r3, #0
800160c: d001 beq.n 8001612 <MX_TIM4_Init+0x66>
{
Error_Handler();
800160e: f000 f961 bl 80018d4 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001612: f44f 5380 mov.w r3, #4096 @ 0x1000
8001616: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
8001618: f107 0328 add.w r3, r7, #40 @ 0x28
800161c: 4619 mov r1, r3
800161e: 4832 ldr r0, [pc, #200] @ (80016e8 <MX_TIM4_Init+0x13c>)
8001620: f004 fcfe bl 8006020 <HAL_TIM_ConfigClockSource>
8001624: 4603 mov r3, r0
8001626: 2b00 cmp r3, #0
8001628: d001 beq.n 800162e <MX_TIM4_Init+0x82>
{
Error_Handler();
800162a: f000 f953 bl 80018d4 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
800162e: 482e ldr r0, [pc, #184] @ (80016e8 <MX_TIM4_Init+0x13c>)
8001630: f004 fad5 bl 8005bde <HAL_TIM_PWM_Init>
8001634: 4603 mov r3, r0
8001636: 2b00 cmp r3, #0
8001638: d001 beq.n 800163e <MX_TIM4_Init+0x92>
{
Error_Handler();
800163a: f000 f94b bl 80018d4 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800163e: 2300 movs r3, #0
8001640: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001642: 2300 movs r3, #0
8001644: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
8001646: f107 0320 add.w r3, r7, #32
800164a: 4619 mov r1, r3
800164c: 4826 ldr r0, [pc, #152] @ (80016e8 <MX_TIM4_Init+0x13c>)
800164e: f005 f887 bl 8006760 <HAL_TIMEx_MasterConfigSynchronization>
8001652: 4603 mov r3, r0
8001654: 2b00 cmp r3, #0
8001656: d001 beq.n 800165c <MX_TIM4_Init+0xb0>
{
Error_Handler();
8001658: f000 f93c bl 80018d4 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800165c: 2360 movs r3, #96 @ 0x60
800165e: 607b str r3, [r7, #4]
sConfigOC.Pulse = 5000;
8001660: f241 3388 movw r3, #5000 @ 0x1388
8001664: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001666: 2300 movs r3, #0
8001668: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
800166a: 2304 movs r3, #4
800166c: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800166e: 1d3b adds r3, r7, #4
8001670: 2200 movs r2, #0
8001672: 4619 mov r1, r3
8001674: 481c ldr r0, [pc, #112] @ (80016e8 <MX_TIM4_Init+0x13c>)
8001676: f004 fc11 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
800167a: 4603 mov r3, r0
800167c: 2b00 cmp r3, #0
800167e: d001 beq.n 8001684 <MX_TIM4_Init+0xd8>
{
Error_Handler();
8001680: f000 f928 bl 80018d4 <Error_Handler>
}
sConfigOC.Pulse = 6000;
8001684: f241 7370 movw r3, #6000 @ 0x1770
8001688: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
800168a: 1d3b adds r3, r7, #4
800168c: 2204 movs r2, #4
800168e: 4619 mov r1, r3
8001690: 4815 ldr r0, [pc, #84] @ (80016e8 <MX_TIM4_Init+0x13c>)
8001692: f004 fc03 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
8001696: 4603 mov r3, r0
8001698: 2b00 cmp r3, #0
800169a: d001 beq.n 80016a0 <MX_TIM4_Init+0xf4>
{
Error_Handler();
800169c: f000 f91a bl 80018d4 <Error_Handler>
}
sConfigOC.Pulse = 7000;
80016a0: f641 3358 movw r3, #7000 @ 0x1b58
80016a4: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80016a6: 1d3b adds r3, r7, #4
80016a8: 2208 movs r2, #8
80016aa: 4619 mov r1, r3
80016ac: 480e ldr r0, [pc, #56] @ (80016e8 <MX_TIM4_Init+0x13c>)
80016ae: f004 fbf5 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
80016b2: 4603 mov r3, r0
80016b4: 2b00 cmp r3, #0
80016b6: d001 beq.n 80016bc <MX_TIM4_Init+0x110>
{
Error_Handler();
80016b8: f000 f90c bl 80018d4 <Error_Handler>
}
sConfigOC.Pulse = 8000;
80016bc: f44f 53fa mov.w r3, #8000 @ 0x1f40
80016c0: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
80016c2: 1d3b adds r3, r7, #4
80016c4: 220c movs r2, #12
80016c6: 4619 mov r1, r3
80016c8: 4807 ldr r0, [pc, #28] @ (80016e8 <MX_TIM4_Init+0x13c>)
80016ca: f004 fbe7 bl 8005e9c <HAL_TIM_PWM_ConfigChannel>
80016ce: 4603 mov r3, r0
80016d0: 2b00 cmp r3, #0
80016d2: d001 beq.n 80016d8 <MX_TIM4_Init+0x12c>
{
Error_Handler();
80016d4: f000 f8fe bl 80018d4 <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
80016d8: 4803 ldr r0, [pc, #12] @ (80016e8 <MX_TIM4_Init+0x13c>)
80016da: f000 fbcb bl 8001e74 <HAL_TIM_MspPostInit>
}
80016de: bf00 nop
80016e0: 3738 adds r7, #56 @ 0x38
80016e2: 46bd mov sp, r7
80016e4: bd80 pop {r7, pc}
80016e6: bf00 nop
80016e8: 20000348 .word 0x20000348
80016ec: 40000800 .word 0x40000800
080016f0 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
80016f0: b580 push {r7, lr}
80016f2: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
80016f4: 4b11 ldr r3, [pc, #68] @ (800173c <MX_USART1_UART_Init+0x4c>)
80016f6: 4a12 ldr r2, [pc, #72] @ (8001740 <MX_USART1_UART_Init+0x50>)
80016f8: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
80016fa: 4b10 ldr r3, [pc, #64] @ (800173c <MX_USART1_UART_Init+0x4c>)
80016fc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8001700: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8001702: 4b0e ldr r3, [pc, #56] @ (800173c <MX_USART1_UART_Init+0x4c>)
8001704: 2200 movs r2, #0
8001706: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8001708: 4b0c ldr r3, [pc, #48] @ (800173c <MX_USART1_UART_Init+0x4c>)
800170a: 2200 movs r2, #0
800170c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800170e: 4b0b ldr r3, [pc, #44] @ (800173c <MX_USART1_UART_Init+0x4c>)
8001710: 2200 movs r2, #0
8001712: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8001714: 4b09 ldr r3, [pc, #36] @ (800173c <MX_USART1_UART_Init+0x4c>)
8001716: 220c movs r2, #12
8001718: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800171a: 4b08 ldr r3, [pc, #32] @ (800173c <MX_USART1_UART_Init+0x4c>)
800171c: 2200 movs r2, #0
800171e: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8001720: 4b06 ldr r3, [pc, #24] @ (800173c <MX_USART1_UART_Init+0x4c>)
8001722: 2200 movs r2, #0
8001724: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8001726: 4805 ldr r0, [pc, #20] @ (800173c <MX_USART1_UART_Init+0x4c>)
8001728: f005 f878 bl 800681c <HAL_UART_Init>
800172c: 4603 mov r3, r0
800172e: 2b00 cmp r3, #0
8001730: d001 beq.n 8001736 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8001732: f000 f8cf bl 80018d4 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8001736: bf00 nop
8001738: bd80 pop {r7, pc}
800173a: bf00 nop
800173c: 20000390 .word 0x20000390
8001740: 40013800 .word 0x40013800
08001744 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8001744: b580 push {r7, lr}
8001746: b082 sub sp, #8
8001748: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
800174a: 4b0c ldr r3, [pc, #48] @ (800177c <MX_DMA_Init+0x38>)
800174c: 695b ldr r3, [r3, #20]
800174e: 4a0b ldr r2, [pc, #44] @ (800177c <MX_DMA_Init+0x38>)
8001750: f043 0301 orr.w r3, r3, #1
8001754: 6153 str r3, [r2, #20]
8001756: 4b09 ldr r3, [pc, #36] @ (800177c <MX_DMA_Init+0x38>)
8001758: 695b ldr r3, [r3, #20]
800175a: f003 0301 and.w r3, r3, #1
800175e: 607b str r3, [r7, #4]
8001760: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8001762: 2200 movs r2, #0
8001764: 2100 movs r1, #0
8001766: 200b movs r0, #11
8001768: f001 f9cd bl 8002b06 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
800176c: 200b movs r0, #11
800176e: f001 f9e6 bl 8002b3e <HAL_NVIC_EnableIRQ>
}
8001772: bf00 nop
8001774: 3708 adds r7, #8
8001776: 46bd mov sp, r7
8001778: bd80 pop {r7, pc}
800177a: bf00 nop
800177c: 40021000 .word 0x40021000
08001780 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001780: b580 push {r7, lr}
8001782: b088 sub sp, #32
8001784: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001786: f107 0310 add.w r3, r7, #16
800178a: 2200 movs r2, #0
800178c: 601a str r2, [r3, #0]
800178e: 605a str r2, [r3, #4]
8001790: 609a str r2, [r3, #8]
8001792: 60da str r2, [r3, #12]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8001794: 4b4b ldr r3, [pc, #300] @ (80018c4 <MX_GPIO_Init+0x144>)
8001796: 699b ldr r3, [r3, #24]
8001798: 4a4a ldr r2, [pc, #296] @ (80018c4 <MX_GPIO_Init+0x144>)
800179a: f043 0310 orr.w r3, r3, #16
800179e: 6193 str r3, [r2, #24]
80017a0: 4b48 ldr r3, [pc, #288] @ (80018c4 <MX_GPIO_Init+0x144>)
80017a2: 699b ldr r3, [r3, #24]
80017a4: f003 0310 and.w r3, r3, #16
80017a8: 60fb str r3, [r7, #12]
80017aa: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
80017ac: 4b45 ldr r3, [pc, #276] @ (80018c4 <MX_GPIO_Init+0x144>)
80017ae: 699b ldr r3, [r3, #24]
80017b0: 4a44 ldr r2, [pc, #272] @ (80018c4 <MX_GPIO_Init+0x144>)
80017b2: f043 0320 orr.w r3, r3, #32
80017b6: 6193 str r3, [r2, #24]
80017b8: 4b42 ldr r3, [pc, #264] @ (80018c4 <MX_GPIO_Init+0x144>)
80017ba: 699b ldr r3, [r3, #24]
80017bc: f003 0320 and.w r3, r3, #32
80017c0: 60bb str r3, [r7, #8]
80017c2: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80017c4: 4b3f ldr r3, [pc, #252] @ (80018c4 <MX_GPIO_Init+0x144>)
80017c6: 699b ldr r3, [r3, #24]
80017c8: 4a3e ldr r2, [pc, #248] @ (80018c4 <MX_GPIO_Init+0x144>)
80017ca: f043 0304 orr.w r3, r3, #4
80017ce: 6193 str r3, [r2, #24]
80017d0: 4b3c ldr r3, [pc, #240] @ (80018c4 <MX_GPIO_Init+0x144>)
80017d2: 699b ldr r3, [r3, #24]
80017d4: f003 0304 and.w r3, r3, #4
80017d8: 607b str r3, [r7, #4]
80017da: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80017dc: 4b39 ldr r3, [pc, #228] @ (80018c4 <MX_GPIO_Init+0x144>)
80017de: 699b ldr r3, [r3, #24]
80017e0: 4a38 ldr r2, [pc, #224] @ (80018c4 <MX_GPIO_Init+0x144>)
80017e2: f043 0308 orr.w r3, r3, #8
80017e6: 6193 str r3, [r2, #24]
80017e8: 4b36 ldr r3, [pc, #216] @ (80018c4 <MX_GPIO_Init+0x144>)
80017ea: 699b ldr r3, [r3, #24]
80017ec: f003 0308 and.w r3, r3, #8
80017f0: 603b str r3, [r7, #0]
80017f2: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
80017f4: 2200 movs r2, #0
80017f6: f44f 5100 mov.w r1, #8192 @ 0x2000
80017fa: 4833 ldr r0, [pc, #204] @ (80018c8 <MX_GPIO_Init+0x148>)
80017fc: f001 ff49 bl 8003692 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
8001800: 2200 movs r2, #0
8001802: f640 413e movw r1, #3134 @ 0xc3e
8001806: 4831 ldr r0, [pc, #196] @ (80018cc <MX_GPIO_Init+0x14c>)
8001808: f001 ff43 bl 8003692 <HAL_GPIO_WritePin>
|EXP1_Pin|EXP2_Pin|EXP3_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, BUZ_Pin|LED1_Pin, GPIO_PIN_RESET);
800180c: 2200 movs r2, #0
800180e: f44f 4101 mov.w r1, #33024 @ 0x8100
8001812: 482f ldr r0, [pc, #188] @ (80018d0 <MX_GPIO_Init+0x150>)
8001814: f001 ff3d bl 8003692 <HAL_GPIO_WritePin>
/*Configure GPIO pin : LED2_Pin */
GPIO_InitStruct.Pin = LED2_Pin;
8001818: f44f 5300 mov.w r3, #8192 @ 0x2000
800181c: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800181e: 2301 movs r3, #1
8001820: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001822: 2300 movs r3, #0
8001824: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001826: 2302 movs r3, #2
8001828: 61fb str r3, [r7, #28]
HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
800182a: f107 0310 add.w r3, r7, #16
800182e: 4619 mov r1, r3
8001830: 4825 ldr r0, [pc, #148] @ (80018c8 <MX_GPIO_Init+0x148>)
8001832: f001 fd93 bl 800335c <HAL_GPIO_Init>
/*Configure GPIO pins : P1_Pin P2_Pin */
GPIO_InitStruct.Pin = P1_Pin|P2_Pin;
8001836: f44f 4340 mov.w r3, #49152 @ 0xc000
800183a: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800183c: 2300 movs r3, #0
800183e: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001840: 2300 movs r3, #0
8001842: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001844: f107 0310 add.w r3, r7, #16
8001848: 4619 mov r1, r3
800184a: 481f ldr r0, [pc, #124] @ (80018c8 <MX_GPIO_Init+0x148>)
800184c: f001 fd86 bl 800335c <HAL_GPIO_Init>
/*Configure GPIO pin : AIN1_Pin */
GPIO_InitStruct.Pin = AIN1_Pin;
8001850: 2310 movs r3, #16
8001852: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001854: 2303 movs r3, #3
8001856: 617b str r3, [r7, #20]
HAL_GPIO_Init(AIN1_GPIO_Port, &GPIO_InitStruct);
8001858: f107 0310 add.w r3, r7, #16
800185c: 4619 mov r1, r3
800185e: 481c ldr r0, [pc, #112] @ (80018d0 <MX_GPIO_Init+0x150>)
8001860: f001 fd7c bl 800335c <HAL_GPIO_Init>
/*Configure GPIO pins : INH1_Pin INH2_Pin INH3_Pin INH4_Pin
EXP1_Pin EXP2_Pin EXP3_Pin */
GPIO_InitStruct.Pin = INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
8001864: f640 433e movw r3, #3134 @ 0xc3e
8001868: 613b str r3, [r7, #16]
|EXP1_Pin|EXP2_Pin|EXP3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800186a: 2301 movs r3, #1
800186c: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800186e: 2300 movs r3, #0
8001870: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001872: 2302 movs r3, #2
8001874: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001876: f107 0310 add.w r3, r7, #16
800187a: 4619 mov r1, r3
800187c: 4813 ldr r0, [pc, #76] @ (80018cc <MX_GPIO_Init+0x14c>)
800187e: f001 fd6d bl 800335c <HAL_GPIO_Init>
/*Configure GPIO pins : CH1_Pin CH2_Pin CH3_Pin CH4_Pin */
GPIO_InitStruct.Pin = CH1_Pin|CH2_Pin|CH3_Pin|CH4_Pin;
8001882: f44f 4370 mov.w r3, #61440 @ 0xf000
8001886: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001888: 2300 movs r3, #0
800188a: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800188c: 2300 movs r3, #0
800188e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001890: f107 0310 add.w r3, r7, #16
8001894: 4619 mov r1, r3
8001896: 480d ldr r0, [pc, #52] @ (80018cc <MX_GPIO_Init+0x14c>)
8001898: f001 fd60 bl 800335c <HAL_GPIO_Init>
/*Configure GPIO pins : BUZ_Pin LED1_Pin */
GPIO_InitStruct.Pin = BUZ_Pin|LED1_Pin;
800189c: f44f 4301 mov.w r3, #33024 @ 0x8100
80018a0: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80018a2: 2301 movs r3, #1
80018a4: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80018a6: 2300 movs r3, #0
80018a8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80018aa: 2302 movs r3, #2
80018ac: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80018ae: f107 0310 add.w r3, r7, #16
80018b2: 4619 mov r1, r3
80018b4: 4806 ldr r0, [pc, #24] @ (80018d0 <MX_GPIO_Init+0x150>)
80018b6: f001 fd51 bl 800335c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80018ba: bf00 nop
80018bc: 3720 adds r7, #32
80018be: 46bd mov sp, r7
80018c0: bd80 pop {r7, pc}
80018c2: bf00 nop
80018c4: 40021000 .word 0x40021000
80018c8: 40011000 .word 0x40011000
80018cc: 40010c00 .word 0x40010c00
80018d0: 40010800 .word 0x40010800
080018d4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80018d4: b480 push {r7}
80018d6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80018d8: b672 cpsid i
}
80018da: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80018dc: bf00 nop
80018de: e7fd b.n 80018dc <Error_Handler+0x8>
080018e0 <IsPwmRunning>:
extern TIM_HandleTypeDef htim2;
extern TIM_HandleTypeDef htim3;
extern TIM_HandleTypeDef htim4;
bool IsPwmRunning(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80018e0: b580 push {r7, lr}
80018e2: b084 sub sp, #16
80018e4: af00 add r7, sp, #0
80018e6: 6078 str r0, [r7, #4]
80018e8: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef chState = HAL_TIM_GetChannelState(htim, Channel);
80018ea: 6839 ldr r1, [r7, #0]
80018ec: 6878 ldr r0, [r7, #4]
80018ee: f004 fc5e bl 80061ae <HAL_TIM_GetChannelState>
80018f2: 4603 mov r3, r0
80018f4: 73fb strb r3, [r7, #15]
return (chState == HAL_TIM_CHANNEL_STATE_BUSY);
80018f6: 7bfb ldrb r3, [r7, #15]
80018f8: 2b02 cmp r3, #2
80018fa: bf0c ite eq
80018fc: 2301 moveq r3, #1
80018fe: 2300 movne r3, #0
8001900: b2db uxtb r3, r3
}
8001902: 4618 mov r0, r3
8001904: 3710 adds r7, #16
8001906: 46bd mov sp, r7
8001908: bd80 pop {r7, pc}
0800190a <StopMot>:
void StopMot(TIM_HandleTypeDef *htim,uint32_t Channel){
800190a: b580 push {r7, lr}
800190c: b082 sub sp, #8
800190e: af00 add r7, sp, #0
8001910: 6078 str r0, [r7, #4]
8001912: 6039 str r1, [r7, #0]
HAL_TIM_PWM_Stop(htim, Channel);
8001914: 6839 ldr r1, [r7, #0]
8001916: 6878 ldr r0, [r7, #4]
8001918: f004 fa5c bl 8005dd4 <HAL_TIM_PWM_Stop>
}
800191c: bf00 nop
800191e: 3708 adds r7, #8
8001920: 46bd mov sp, r7
8001922: bd80 pop {r7, pc}
08001924 <StartMot>:
void StartMot(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
8001924: b580 push {r7, lr}
8001926: b084 sub sp, #16
8001928: af00 add r7, sp, #0
800192a: 60f8 str r0, [r7, #12]
800192c: 60b9 str r1, [r7, #8]
800192e: 4613 mov r3, r2
8001930: 80fb strh r3, [r7, #6]
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8001932: 68bb ldr r3, [r7, #8]
8001934: 2b00 cmp r3, #0
8001936: d104 bne.n 8001942 <StartMot+0x1e>
8001938: 68fb ldr r3, [r7, #12]
800193a: 681b ldr r3, [r3, #0]
800193c: 88fa ldrh r2, [r7, #6]
800193e: 635a str r2, [r3, #52] @ 0x34
8001940: e013 b.n 800196a <StartMot+0x46>
8001942: 68bb ldr r3, [r7, #8]
8001944: 2b04 cmp r3, #4
8001946: d104 bne.n 8001952 <StartMot+0x2e>
8001948: 68fb ldr r3, [r7, #12]
800194a: 681a ldr r2, [r3, #0]
800194c: 88fb ldrh r3, [r7, #6]
800194e: 6393 str r3, [r2, #56] @ 0x38
8001950: e00b b.n 800196a <StartMot+0x46>
8001952: 68bb ldr r3, [r7, #8]
8001954: 2b08 cmp r3, #8
8001956: d104 bne.n 8001962 <StartMot+0x3e>
8001958: 68fb ldr r3, [r7, #12]
800195a: 681a ldr r2, [r3, #0]
800195c: 88fb ldrh r3, [r7, #6]
800195e: 63d3 str r3, [r2, #60] @ 0x3c
8001960: e003 b.n 800196a <StartMot+0x46>
8001962: 68fb ldr r3, [r7, #12]
8001964: 681a ldr r2, [r3, #0]
8001966: 88fb ldrh r3, [r7, #6]
8001968: 6413 str r3, [r2, #64] @ 0x40
HAL_TIM_PWM_Start(htim, Channel);
800196a: 68b9 ldr r1, [r7, #8]
800196c: 68f8 ldr r0, [r7, #12]
800196e: f004 f98f bl 8005c90 <HAL_TIM_PWM_Start>
}
8001972: bf00 nop
8001974: 3710 adds r7, #16
8001976: 46bd mov sp, r7
8001978: bd80 pop {r7, pc}
0800197a <SetMotPwm>:
void SetMotPwm(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
800197a: b480 push {r7}
800197c: b085 sub sp, #20
800197e: af00 add r7, sp, #0
8001980: 60f8 str r0, [r7, #12]
8001982: 60b9 str r1, [r7, #8]
8001984: 4613 mov r3, r2
8001986: 80fb strh r3, [r7, #6]
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8001988: 68bb ldr r3, [r7, #8]
800198a: 2b00 cmp r3, #0
800198c: d104 bne.n 8001998 <SetMotPwm+0x1e>
800198e: 68fb ldr r3, [r7, #12]
8001990: 681b ldr r3, [r3, #0]
8001992: 88fa ldrh r2, [r7, #6]
8001994: 635a str r2, [r3, #52] @ 0x34
}
8001996: e013 b.n 80019c0 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8001998: 68bb ldr r3, [r7, #8]
800199a: 2b04 cmp r3, #4
800199c: d104 bne.n 80019a8 <SetMotPwm+0x2e>
800199e: 68fb ldr r3, [r7, #12]
80019a0: 681a ldr r2, [r3, #0]
80019a2: 88fb ldrh r3, [r7, #6]
80019a4: 6393 str r3, [r2, #56] @ 0x38
}
80019a6: e00b b.n 80019c0 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80019a8: 68bb ldr r3, [r7, #8]
80019aa: 2b08 cmp r3, #8
80019ac: d104 bne.n 80019b8 <SetMotPwm+0x3e>
80019ae: 68fb ldr r3, [r7, #12]
80019b0: 681a ldr r2, [r3, #0]
80019b2: 88fb ldrh r3, [r7, #6]
80019b4: 63d3 str r3, [r2, #60] @ 0x3c
}
80019b6: e003 b.n 80019c0 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80019b8: 68fb ldr r3, [r7, #12]
80019ba: 681a ldr r2, [r3, #0]
80019bc: 88fb ldrh r3, [r7, #6]
80019be: 6413 str r3, [r2, #64] @ 0x40
}
80019c0: bf00 nop
80019c2: 3714 adds r7, #20
80019c4: 46bd mov sp, r7
80019c6: bc80 pop {r7}
80019c8: 4770 bx lr
...
080019cc <SetMot>:
void SetMot(uint8_t mot,uint8_t dir,uint16_t pwmval){
80019cc: b580 push {r7, lr}
80019ce: b082 sub sp, #8
80019d0: af00 add r7, sp, #0
80019d2: 4603 mov r3, r0
80019d4: 71fb strb r3, [r7, #7]
80019d6: 460b mov r3, r1
80019d8: 71bb strb r3, [r7, #6]
80019da: 4613 mov r3, r2
80019dc: 80bb strh r3, [r7, #4]
switch(mot){
80019de: 79fb ldrb r3, [r7, #7]
80019e0: 3b01 subs r3, #1
80019e2: 2b03 cmp r3, #3
80019e4: f200 8158 bhi.w 8001c98 <SetMot+0x2cc>
80019e8: a201 add r2, pc, #4 @ (adr r2, 80019f0 <SetMot+0x24>)
80019ea: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80019ee: bf00 nop
80019f0: 08001a01 .word 0x08001a01
80019f4: 08001aa3 .word 0x08001aa3
80019f8: 08001b45 .word 0x08001b45
80019fc: 08001bef .word 0x08001bef
case 1:
if(dir==FW){
8001a00: 79bb ldrb r3, [r7, #6]
8001a02: 2b00 cmp r3, #0
8001a04: d126 bne.n 8001a54 <SetMot+0x88>
if(pwmval==0){
8001a06: 88bb ldrh r3, [r7, #4]
8001a08: 2b00 cmp r3, #0
8001a0a: d109 bne.n 8001a20 <SetMot+0x54>
StopMot(timMot1,FWMot1);
8001a0c: 2100 movs r1, #0
8001a0e: 48a5 ldr r0, [pc, #660] @ (8001ca4 <SetMot+0x2d8>)
8001a10: f7ff ff7b bl 800190a <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
8001a14: 2200 movs r2, #0
8001a16: 2102 movs r1, #2
8001a18: 48a3 ldr r0, [pc, #652] @ (8001ca8 <SetMot+0x2dc>)
8001a1a: f001 fe3a bl 8003692 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
StartMot(timMot1,BWMot1,pwmval);
}
}
break;
8001a1e: e13c b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot1, FWMot1)){
8001a20: 2100 movs r1, #0
8001a22: 48a0 ldr r0, [pc, #640] @ (8001ca4 <SetMot+0x2d8>)
8001a24: f7ff ff5c bl 80018e0 <IsPwmRunning>
8001a28: 4603 mov r3, r0
8001a2a: 2b00 cmp r3, #0
8001a2c: d006 beq.n 8001a3c <SetMot+0x70>
SetMotPwm(timMot1,FWMot1,pwmval);
8001a2e: 88bb ldrh r3, [r7, #4]
8001a30: 461a mov r2, r3
8001a32: 2100 movs r1, #0
8001a34: 489b ldr r0, [pc, #620] @ (8001ca4 <SetMot+0x2d8>)
8001a36: f7ff ffa0 bl 800197a <SetMotPwm>
break;
8001a3a: e12e b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8001a3c: 2201 movs r2, #1
8001a3e: 2102 movs r1, #2
8001a40: 4899 ldr r0, [pc, #612] @ (8001ca8 <SetMot+0x2dc>)
8001a42: f001 fe26 bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot1,FWMot1,pwmval);
8001a46: 88bb ldrh r3, [r7, #4]
8001a48: 461a mov r2, r3
8001a4a: 2100 movs r1, #0
8001a4c: 4895 ldr r0, [pc, #596] @ (8001ca4 <SetMot+0x2d8>)
8001a4e: f7ff ff69 bl 8001924 <StartMot>
break;
8001a52: e122 b.n 8001c9a <SetMot+0x2ce>
if(pwmval==0){
8001a54: 88bb ldrh r3, [r7, #4]
8001a56: 2b00 cmp r3, #0
8001a58: d109 bne.n 8001a6e <SetMot+0xa2>
StopMot(timMot1,BWMot1);
8001a5a: 2104 movs r1, #4
8001a5c: 4891 ldr r0, [pc, #580] @ (8001ca4 <SetMot+0x2d8>)
8001a5e: f7ff ff54 bl 800190a <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
8001a62: 2200 movs r2, #0
8001a64: 2102 movs r1, #2
8001a66: 4890 ldr r0, [pc, #576] @ (8001ca8 <SetMot+0x2dc>)
8001a68: f001 fe13 bl 8003692 <HAL_GPIO_WritePin>
break;
8001a6c: e115 b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot1, BWMot1)){
8001a6e: 2104 movs r1, #4
8001a70: 488c ldr r0, [pc, #560] @ (8001ca4 <SetMot+0x2d8>)
8001a72: f7ff ff35 bl 80018e0 <IsPwmRunning>
8001a76: 4603 mov r3, r0
8001a78: 2b00 cmp r3, #0
8001a7a: d006 beq.n 8001a8a <SetMot+0xbe>
SetMotPwm(timMot1,BWMot1,pwmval);
8001a7c: 88bb ldrh r3, [r7, #4]
8001a7e: 461a mov r2, r3
8001a80: 2104 movs r1, #4
8001a82: 4888 ldr r0, [pc, #544] @ (8001ca4 <SetMot+0x2d8>)
8001a84: f7ff ff79 bl 800197a <SetMotPwm>
break;
8001a88: e107 b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8001a8a: 2201 movs r2, #1
8001a8c: 2102 movs r1, #2
8001a8e: 4886 ldr r0, [pc, #536] @ (8001ca8 <SetMot+0x2dc>)
8001a90: f001 fdff bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot1,BWMot1,pwmval);
8001a94: 88bb ldrh r3, [r7, #4]
8001a96: 461a mov r2, r3
8001a98: 2104 movs r1, #4
8001a9a: 4882 ldr r0, [pc, #520] @ (8001ca4 <SetMot+0x2d8>)
8001a9c: f7ff ff42 bl 8001924 <StartMot>
break;
8001aa0: e0fb b.n 8001c9a <SetMot+0x2ce>
case 2:
if(dir==FW){
8001aa2: 79bb ldrb r3, [r7, #6]
8001aa4: 2b00 cmp r3, #0
8001aa6: d126 bne.n 8001af6 <SetMot+0x12a>
if(pwmval==0){
8001aa8: 88bb ldrh r3, [r7, #4]
8001aaa: 2b00 cmp r3, #0
8001aac: d109 bne.n 8001ac2 <SetMot+0xf6>
StopMot(timMot2,FWMot2);
8001aae: 2108 movs r1, #8
8001ab0: 487c ldr r0, [pc, #496] @ (8001ca4 <SetMot+0x2d8>)
8001ab2: f7ff ff2a bl 800190a <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
8001ab6: 2200 movs r2, #0
8001ab8: 2104 movs r1, #4
8001aba: 487b ldr r0, [pc, #492] @ (8001ca8 <SetMot+0x2dc>)
8001abc: f001 fde9 bl 8003692 <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
StartMot(timMot2,BWMot2,pwmval);
}
}
break;
8001ac0: e0eb b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot2, FWMot2)){
8001ac2: 2108 movs r1, #8
8001ac4: 4877 ldr r0, [pc, #476] @ (8001ca4 <SetMot+0x2d8>)
8001ac6: f7ff ff0b bl 80018e0 <IsPwmRunning>
8001aca: 4603 mov r3, r0
8001acc: 2b00 cmp r3, #0
8001ace: d006 beq.n 8001ade <SetMot+0x112>
SetMotPwm(timMot2,FWMot2,pwmval);
8001ad0: 88bb ldrh r3, [r7, #4]
8001ad2: 461a mov r2, r3
8001ad4: 2108 movs r1, #8
8001ad6: 4873 ldr r0, [pc, #460] @ (8001ca4 <SetMot+0x2d8>)
8001ad8: f7ff ff4f bl 800197a <SetMotPwm>
break;
8001adc: e0dd b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8001ade: 2201 movs r2, #1
8001ae0: 2104 movs r1, #4
8001ae2: 4871 ldr r0, [pc, #452] @ (8001ca8 <SetMot+0x2dc>)
8001ae4: f001 fdd5 bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot2,FWMot2,pwmval);
8001ae8: 88bb ldrh r3, [r7, #4]
8001aea: 461a mov r2, r3
8001aec: 2108 movs r1, #8
8001aee: 486d ldr r0, [pc, #436] @ (8001ca4 <SetMot+0x2d8>)
8001af0: f7ff ff18 bl 8001924 <StartMot>
break;
8001af4: e0d1 b.n 8001c9a <SetMot+0x2ce>
if(pwmval==0){
8001af6: 88bb ldrh r3, [r7, #4]
8001af8: 2b00 cmp r3, #0
8001afa: d109 bne.n 8001b10 <SetMot+0x144>
StopMot(timMot2,BWMot2);
8001afc: 210c movs r1, #12
8001afe: 4869 ldr r0, [pc, #420] @ (8001ca4 <SetMot+0x2d8>)
8001b00: f7ff ff03 bl 800190a <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
8001b04: 2200 movs r2, #0
8001b06: 2104 movs r1, #4
8001b08: 4867 ldr r0, [pc, #412] @ (8001ca8 <SetMot+0x2dc>)
8001b0a: f001 fdc2 bl 8003692 <HAL_GPIO_WritePin>
break;
8001b0e: e0c4 b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot2, BWMot2)){
8001b10: 210c movs r1, #12
8001b12: 4864 ldr r0, [pc, #400] @ (8001ca4 <SetMot+0x2d8>)
8001b14: f7ff fee4 bl 80018e0 <IsPwmRunning>
8001b18: 4603 mov r3, r0
8001b1a: 2b00 cmp r3, #0
8001b1c: d006 beq.n 8001b2c <SetMot+0x160>
SetMotPwm(timMot2,BWMot2,pwmval);
8001b1e: 88bb ldrh r3, [r7, #4]
8001b20: 461a mov r2, r3
8001b22: 210c movs r1, #12
8001b24: 485f ldr r0, [pc, #380] @ (8001ca4 <SetMot+0x2d8>)
8001b26: f7ff ff28 bl 800197a <SetMotPwm>
break;
8001b2a: e0b6 b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8001b2c: 2201 movs r2, #1
8001b2e: 2104 movs r1, #4
8001b30: 485d ldr r0, [pc, #372] @ (8001ca8 <SetMot+0x2dc>)
8001b32: f001 fdae bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot2,BWMot2,pwmval);
8001b36: 88bb ldrh r3, [r7, #4]
8001b38: 461a mov r2, r3
8001b3a: 210c movs r1, #12
8001b3c: 4859 ldr r0, [pc, #356] @ (8001ca4 <SetMot+0x2d8>)
8001b3e: f7ff fef1 bl 8001924 <StartMot>
break;
8001b42: e0aa b.n 8001c9a <SetMot+0x2ce>
case 3:
if(dir==FW){
8001b44: 79bb ldrb r3, [r7, #6]
8001b46: 2b00 cmp r3, #0
8001b48: d128 bne.n 8001b9c <SetMot+0x1d0>
if(pwmval==0){
8001b4a: 88bb ldrh r3, [r7, #4]
8001b4c: 2b00 cmp r3, #0
8001b4e: d10a bne.n 8001b66 <SetMot+0x19a>
StopMot(timMot3,FWMot3);
8001b50: 2100 movs r1, #0
8001b52: 4856 ldr r0, [pc, #344] @ (8001cac <SetMot+0x2e0>)
8001b54: f7ff fed9 bl 800190a <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8001b58: 2200 movs r2, #0
8001b5a: f44f 6180 mov.w r1, #1024 @ 0x400
8001b5e: 4852 ldr r0, [pc, #328] @ (8001ca8 <SetMot+0x2dc>)
8001b60: f001 fd97 bl 8003692 <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
StartMot(timMot3,BWMot3,pwmval);
}
}
break;
8001b64: e099 b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot3, FWMot3)){
8001b66: 2100 movs r1, #0
8001b68: 4850 ldr r0, [pc, #320] @ (8001cac <SetMot+0x2e0>)
8001b6a: f7ff feb9 bl 80018e0 <IsPwmRunning>
8001b6e: 4603 mov r3, r0
8001b70: 2b00 cmp r3, #0
8001b72: d006 beq.n 8001b82 <SetMot+0x1b6>
SetMotPwm(timMot3,FWMot3,pwmval);
8001b74: 88bb ldrh r3, [r7, #4]
8001b76: 461a mov r2, r3
8001b78: 2100 movs r1, #0
8001b7a: 484c ldr r0, [pc, #304] @ (8001cac <SetMot+0x2e0>)
8001b7c: f7ff fefd bl 800197a <SetMotPwm>
break;
8001b80: e08b b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8001b82: 2201 movs r2, #1
8001b84: f44f 6180 mov.w r1, #1024 @ 0x400
8001b88: 4847 ldr r0, [pc, #284] @ (8001ca8 <SetMot+0x2dc>)
8001b8a: f001 fd82 bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot3,FWMot3,pwmval);
8001b8e: 88bb ldrh r3, [r7, #4]
8001b90: 461a mov r2, r3
8001b92: 2100 movs r1, #0
8001b94: 4845 ldr r0, [pc, #276] @ (8001cac <SetMot+0x2e0>)
8001b96: f7ff fec5 bl 8001924 <StartMot>
break;
8001b9a: e07e b.n 8001c9a <SetMot+0x2ce>
if(pwmval==0){
8001b9c: 88bb ldrh r3, [r7, #4]
8001b9e: 2b00 cmp r3, #0
8001ba0: d10a bne.n 8001bb8 <SetMot+0x1ec>
StopMot(timMot3,BWMot3);
8001ba2: 2104 movs r1, #4
8001ba4: 4841 ldr r0, [pc, #260] @ (8001cac <SetMot+0x2e0>)
8001ba6: f7ff feb0 bl 800190a <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8001baa: 2200 movs r2, #0
8001bac: f44f 6180 mov.w r1, #1024 @ 0x400
8001bb0: 483d ldr r0, [pc, #244] @ (8001ca8 <SetMot+0x2dc>)
8001bb2: f001 fd6e bl 8003692 <HAL_GPIO_WritePin>
break;
8001bb6: e070 b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot3, BWMot3)){
8001bb8: 2104 movs r1, #4
8001bba: 483c ldr r0, [pc, #240] @ (8001cac <SetMot+0x2e0>)
8001bbc: f7ff fe90 bl 80018e0 <IsPwmRunning>
8001bc0: 4603 mov r3, r0
8001bc2: 2b00 cmp r3, #0
8001bc4: d006 beq.n 8001bd4 <SetMot+0x208>
SetMotPwm(timMot3,BWMot3,pwmval);
8001bc6: 88bb ldrh r3, [r7, #4]
8001bc8: 461a mov r2, r3
8001bca: 2104 movs r1, #4
8001bcc: 4837 ldr r0, [pc, #220] @ (8001cac <SetMot+0x2e0>)
8001bce: f7ff fed4 bl 800197a <SetMotPwm>
break;
8001bd2: e062 b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8001bd4: 2201 movs r2, #1
8001bd6: f44f 6180 mov.w r1, #1024 @ 0x400
8001bda: 4833 ldr r0, [pc, #204] @ (8001ca8 <SetMot+0x2dc>)
8001bdc: f001 fd59 bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot3,BWMot3,pwmval);
8001be0: 88bb ldrh r3, [r7, #4]
8001be2: 461a mov r2, r3
8001be4: 2104 movs r1, #4
8001be6: 4831 ldr r0, [pc, #196] @ (8001cac <SetMot+0x2e0>)
8001be8: f7ff fe9c bl 8001924 <StartMot>
break;
8001bec: e055 b.n 8001c9a <SetMot+0x2ce>
case 4:
if(dir==FW){
8001bee: 79bb ldrb r3, [r7, #6]
8001bf0: 2b00 cmp r3, #0
8001bf2: d128 bne.n 8001c46 <SetMot+0x27a>
if(pwmval==0){
8001bf4: 88bb ldrh r3, [r7, #4]
8001bf6: 2b00 cmp r3, #0
8001bf8: d10a bne.n 8001c10 <SetMot+0x244>
StopMot(timMot4,FWMot4);
8001bfa: 2108 movs r1, #8
8001bfc: 482b ldr r0, [pc, #172] @ (8001cac <SetMot+0x2e0>)
8001bfe: f7ff fe84 bl 800190a <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8001c02: 2200 movs r2, #0
8001c04: f44f 6100 mov.w r1, #2048 @ 0x800
8001c08: 4827 ldr r0, [pc, #156] @ (8001ca8 <SetMot+0x2dc>)
8001c0a: f001 fd42 bl 8003692 <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
StartMot(timMot4,BWMot4,pwmval);
}
}
break;
8001c0e: e044 b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot4, FWMot4)){
8001c10: 2108 movs r1, #8
8001c12: 4826 ldr r0, [pc, #152] @ (8001cac <SetMot+0x2e0>)
8001c14: f7ff fe64 bl 80018e0 <IsPwmRunning>
8001c18: 4603 mov r3, r0
8001c1a: 2b00 cmp r3, #0
8001c1c: d006 beq.n 8001c2c <SetMot+0x260>
SetMotPwm(timMot4,FWMot4,pwmval);
8001c1e: 88bb ldrh r3, [r7, #4]
8001c20: 461a mov r2, r3
8001c22: 2108 movs r1, #8
8001c24: 4821 ldr r0, [pc, #132] @ (8001cac <SetMot+0x2e0>)
8001c26: f7ff fea8 bl 800197a <SetMotPwm>
break;
8001c2a: e036 b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8001c2c: 2201 movs r2, #1
8001c2e: f44f 6100 mov.w r1, #2048 @ 0x800
8001c32: 481d ldr r0, [pc, #116] @ (8001ca8 <SetMot+0x2dc>)
8001c34: f001 fd2d bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot4,FWMot4,pwmval);
8001c38: 88bb ldrh r3, [r7, #4]
8001c3a: 461a mov r2, r3
8001c3c: 2108 movs r1, #8
8001c3e: 481b ldr r0, [pc, #108] @ (8001cac <SetMot+0x2e0>)
8001c40: f7ff fe70 bl 8001924 <StartMot>
break;
8001c44: e029 b.n 8001c9a <SetMot+0x2ce>
if(pwmval==0){
8001c46: 88bb ldrh r3, [r7, #4]
8001c48: 2b00 cmp r3, #0
8001c4a: d10a bne.n 8001c62 <SetMot+0x296>
StopMot(timMot4,BWMot4);
8001c4c: 210c movs r1, #12
8001c4e: 4817 ldr r0, [pc, #92] @ (8001cac <SetMot+0x2e0>)
8001c50: f7ff fe5b bl 800190a <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8001c54: 2200 movs r2, #0
8001c56: f44f 6100 mov.w r1, #2048 @ 0x800
8001c5a: 4813 ldr r0, [pc, #76] @ (8001ca8 <SetMot+0x2dc>)
8001c5c: f001 fd19 bl 8003692 <HAL_GPIO_WritePin>
break;
8001c60: e01b b.n 8001c9a <SetMot+0x2ce>
}else if(IsPwmRunning(timMot4, BWMot4)){
8001c62: 210c movs r1, #12
8001c64: 4811 ldr r0, [pc, #68] @ (8001cac <SetMot+0x2e0>)
8001c66: f7ff fe3b bl 80018e0 <IsPwmRunning>
8001c6a: 4603 mov r3, r0
8001c6c: 2b00 cmp r3, #0
8001c6e: d006 beq.n 8001c7e <SetMot+0x2b2>
SetMotPwm(timMot4,BWMot4,pwmval);
8001c70: 88bb ldrh r3, [r7, #4]
8001c72: 461a mov r2, r3
8001c74: 210c movs r1, #12
8001c76: 480d ldr r0, [pc, #52] @ (8001cac <SetMot+0x2e0>)
8001c78: f7ff fe7f bl 800197a <SetMotPwm>
break;
8001c7c: e00d b.n 8001c9a <SetMot+0x2ce>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8001c7e: 2201 movs r2, #1
8001c80: f44f 6100 mov.w r1, #2048 @ 0x800
8001c84: 4808 ldr r0, [pc, #32] @ (8001ca8 <SetMot+0x2dc>)
8001c86: f001 fd04 bl 8003692 <HAL_GPIO_WritePin>
StartMot(timMot4,BWMot4,pwmval);
8001c8a: 88bb ldrh r3, [r7, #4]
8001c8c: 461a mov r2, r3
8001c8e: 210c movs r1, #12
8001c90: 4806 ldr r0, [pc, #24] @ (8001cac <SetMot+0x2e0>)
8001c92: f7ff fe47 bl 8001924 <StartMot>
break;
8001c96: e000 b.n 8001c9a <SetMot+0x2ce>
default:
break;
8001c98: bf00 nop
}
}
8001c9a: bf00 nop
8001c9c: 3708 adds r7, #8
8001c9e: 46bd mov sp, r7
8001ca0: bd80 pop {r7, pc}
8001ca2: bf00 nop
8001ca4: 20000300 .word 0x20000300
8001ca8: 40010c00 .word 0x40010c00
8001cac: 20000348 .word 0x20000348
08001cb0 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001cb0: b480 push {r7}
8001cb2: b085 sub sp, #20
8001cb4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8001cb6: 4b15 ldr r3, [pc, #84] @ (8001d0c <HAL_MspInit+0x5c>)
8001cb8: 699b ldr r3, [r3, #24]
8001cba: 4a14 ldr r2, [pc, #80] @ (8001d0c <HAL_MspInit+0x5c>)
8001cbc: f043 0301 orr.w r3, r3, #1
8001cc0: 6193 str r3, [r2, #24]
8001cc2: 4b12 ldr r3, [pc, #72] @ (8001d0c <HAL_MspInit+0x5c>)
8001cc4: 699b ldr r3, [r3, #24]
8001cc6: f003 0301 and.w r3, r3, #1
8001cca: 60bb str r3, [r7, #8]
8001ccc: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8001cce: 4b0f ldr r3, [pc, #60] @ (8001d0c <HAL_MspInit+0x5c>)
8001cd0: 69db ldr r3, [r3, #28]
8001cd2: 4a0e ldr r2, [pc, #56] @ (8001d0c <HAL_MspInit+0x5c>)
8001cd4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001cd8: 61d3 str r3, [r2, #28]
8001cda: 4b0c ldr r3, [pc, #48] @ (8001d0c <HAL_MspInit+0x5c>)
8001cdc: 69db ldr r3, [r3, #28]
8001cde: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001ce2: 607b str r3, [r7, #4]
8001ce4: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8001ce6: 4b0a ldr r3, [pc, #40] @ (8001d10 <HAL_MspInit+0x60>)
8001ce8: 685b ldr r3, [r3, #4]
8001cea: 60fb str r3, [r7, #12]
8001cec: 68fb ldr r3, [r7, #12]
8001cee: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
8001cf2: 60fb str r3, [r7, #12]
8001cf4: 68fb ldr r3, [r7, #12]
8001cf6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8001cfa: 60fb str r3, [r7, #12]
8001cfc: 4a04 ldr r2, [pc, #16] @ (8001d10 <HAL_MspInit+0x60>)
8001cfe: 68fb ldr r3, [r7, #12]
8001d00: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001d02: bf00 nop
8001d04: 3714 adds r7, #20
8001d06: 46bd mov sp, r7
8001d08: bc80 pop {r7}
8001d0a: 4770 bx lr
8001d0c: 40021000 .word 0x40021000
8001d10: 40010000 .word 0x40010000
08001d14 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001d14: b580 push {r7, lr}
8001d16: b08a sub sp, #40 @ 0x28
8001d18: af00 add r7, sp, #0
8001d1a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001d1c: f107 0318 add.w r3, r7, #24
8001d20: 2200 movs r2, #0
8001d22: 601a str r2, [r3, #0]
8001d24: 605a str r2, [r3, #4]
8001d26: 609a str r2, [r3, #8]
8001d28: 60da str r2, [r3, #12]
if(hadc->Instance==ADC1)
8001d2a: 687b ldr r3, [r7, #4]
8001d2c: 681b ldr r3, [r3, #0]
8001d2e: 4a33 ldr r2, [pc, #204] @ (8001dfc <HAL_ADC_MspInit+0xe8>)
8001d30: 4293 cmp r3, r2
8001d32: d15f bne.n 8001df4 <HAL_ADC_MspInit+0xe0>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8001d34: 4b32 ldr r3, [pc, #200] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d36: 699b ldr r3, [r3, #24]
8001d38: 4a31 ldr r2, [pc, #196] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d3a: f443 7300 orr.w r3, r3, #512 @ 0x200
8001d3e: 6193 str r3, [r2, #24]
8001d40: 4b2f ldr r3, [pc, #188] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d42: 699b ldr r3, [r3, #24]
8001d44: f403 7300 and.w r3, r3, #512 @ 0x200
8001d48: 617b str r3, [r7, #20]
8001d4a: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001d4c: 4b2c ldr r3, [pc, #176] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d4e: 699b ldr r3, [r3, #24]
8001d50: 4a2b ldr r2, [pc, #172] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d52: f043 0304 orr.w r3, r3, #4
8001d56: 6193 str r3, [r2, #24]
8001d58: 4b29 ldr r3, [pc, #164] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d5a: 699b ldr r3, [r3, #24]
8001d5c: f003 0304 and.w r3, r3, #4
8001d60: 613b str r3, [r7, #16]
8001d62: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001d64: 4b26 ldr r3, [pc, #152] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d66: 699b ldr r3, [r3, #24]
8001d68: 4a25 ldr r2, [pc, #148] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d6a: f043 0308 orr.w r3, r3, #8
8001d6e: 6193 str r3, [r2, #24]
8001d70: 4b23 ldr r3, [pc, #140] @ (8001e00 <HAL_ADC_MspInit+0xec>)
8001d72: 699b ldr r3, [r3, #24]
8001d74: f003 0308 and.w r3, r3, #8
8001d78: 60fb str r3, [r7, #12]
8001d7a: 68fb ldr r3, [r7, #12]
PA5 ------> ADC1_IN5
PA6 ------> ADC1_IN6
PA7 ------> ADC1_IN7
PB0 ------> ADC1_IN8
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin|AIN3_Pin|AIN4_Pin;
8001d7c: 23f0 movs r3, #240 @ 0xf0
8001d7e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001d80: 2303 movs r3, #3
8001d82: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001d84: f107 0318 add.w r3, r7, #24
8001d88: 4619 mov r1, r3
8001d8a: 481e ldr r0, [pc, #120] @ (8001e04 <HAL_ADC_MspInit+0xf0>)
8001d8c: f001 fae6 bl 800335c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ANEM_Pin;
8001d90: 2301 movs r3, #1
8001d92: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001d94: 2303 movs r3, #3
8001d96: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ANEM_GPIO_Port, &GPIO_InitStruct);
8001d98: f107 0318 add.w r3, r7, #24
8001d9c: 4619 mov r1, r3
8001d9e: 481a ldr r0, [pc, #104] @ (8001e08 <HAL_ADC_MspInit+0xf4>)
8001da0: f001 fadc bl 800335c <HAL_GPIO_Init>
/* ADC1 DMA Init */
/* ADC1 Init */
hdma_adc1.Instance = DMA1_Channel1;
8001da4: 4b19 ldr r3, [pc, #100] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001da6: 4a1a ldr r2, [pc, #104] @ (8001e10 <HAL_ADC_MspInit+0xfc>)
8001da8: 601a str r2, [r3, #0]
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
8001daa: 4b18 ldr r3, [pc, #96] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dac: 2200 movs r2, #0
8001dae: 605a str r2, [r3, #4]
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
8001db0: 4b16 ldr r3, [pc, #88] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001db2: 2200 movs r2, #0
8001db4: 609a str r2, [r3, #8]
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
8001db6: 4b15 ldr r3, [pc, #84] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001db8: 2280 movs r2, #128 @ 0x80
8001dba: 60da str r2, [r3, #12]
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
8001dbc: 4b13 ldr r3, [pc, #76] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dbe: f44f 7280 mov.w r2, #256 @ 0x100
8001dc2: 611a str r2, [r3, #16]
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
8001dc4: 4b11 ldr r3, [pc, #68] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dc6: f44f 6280 mov.w r2, #1024 @ 0x400
8001dca: 615a str r2, [r3, #20]
hdma_adc1.Init.Mode = DMA_CIRCULAR;
8001dcc: 4b0f ldr r3, [pc, #60] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dce: 2220 movs r2, #32
8001dd0: 619a str r2, [r3, #24]
hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
8001dd2: 4b0e ldr r3, [pc, #56] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dd4: 2200 movs r2, #0
8001dd6: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
8001dd8: 480c ldr r0, [pc, #48] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dda: f000 fed1 bl 8002b80 <HAL_DMA_Init>
8001dde: 4603 mov r3, r0
8001de0: 2b00 cmp r3, #0
8001de2: d001 beq.n 8001de8 <HAL_ADC_MspInit+0xd4>
{
Error_Handler();
8001de4: f7ff fd76 bl 80018d4 <Error_Handler>
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
8001de8: 687b ldr r3, [r7, #4]
8001dea: 4a08 ldr r2, [pc, #32] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001dec: 621a str r2, [r3, #32]
8001dee: 4a07 ldr r2, [pc, #28] @ (8001e0c <HAL_ADC_MspInit+0xf8>)
8001df0: 687b ldr r3, [r7, #4]
8001df2: 6253 str r3, [r2, #36] @ 0x24
/* USER CODE END ADC1_MspInit 1 */
}
}
8001df4: bf00 nop
8001df6: 3728 adds r7, #40 @ 0x28
8001df8: 46bd mov sp, r7
8001dfa: bd80 pop {r7, pc}
8001dfc: 40012400 .word 0x40012400
8001e00: 40021000 .word 0x40021000
8001e04: 40010800 .word 0x40010800
8001e08: 40010c00 .word 0x40010c00
8001e0c: 200002bc .word 0x200002bc
8001e10: 40020008 .word 0x40020008
08001e14 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001e14: b480 push {r7}
8001e16: b085 sub sp, #20
8001e18: af00 add r7, sp, #0
8001e1a: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 681b ldr r3, [r3, #0]
8001e20: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001e24: d10c bne.n 8001e40 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001e26: 4b11 ldr r3, [pc, #68] @ (8001e6c <HAL_TIM_Base_MspInit+0x58>)
8001e28: 69db ldr r3, [r3, #28]
8001e2a: 4a10 ldr r2, [pc, #64] @ (8001e6c <HAL_TIM_Base_MspInit+0x58>)
8001e2c: f043 0301 orr.w r3, r3, #1
8001e30: 61d3 str r3, [r2, #28]
8001e32: 4b0e ldr r3, [pc, #56] @ (8001e6c <HAL_TIM_Base_MspInit+0x58>)
8001e34: 69db ldr r3, [r3, #28]
8001e36: f003 0301 and.w r3, r3, #1
8001e3a: 60fb str r3, [r7, #12]
8001e3c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
8001e3e: e010 b.n 8001e62 <HAL_TIM_Base_MspInit+0x4e>
else if(htim_base->Instance==TIM4)
8001e40: 687b ldr r3, [r7, #4]
8001e42: 681b ldr r3, [r3, #0]
8001e44: 4a0a ldr r2, [pc, #40] @ (8001e70 <HAL_TIM_Base_MspInit+0x5c>)
8001e46: 4293 cmp r3, r2
8001e48: d10b bne.n 8001e62 <HAL_TIM_Base_MspInit+0x4e>
__HAL_RCC_TIM4_CLK_ENABLE();
8001e4a: 4b08 ldr r3, [pc, #32] @ (8001e6c <HAL_TIM_Base_MspInit+0x58>)
8001e4c: 69db ldr r3, [r3, #28]
8001e4e: 4a07 ldr r2, [pc, #28] @ (8001e6c <HAL_TIM_Base_MspInit+0x58>)
8001e50: f043 0304 orr.w r3, r3, #4
8001e54: 61d3 str r3, [r2, #28]
8001e56: 4b05 ldr r3, [pc, #20] @ (8001e6c <HAL_TIM_Base_MspInit+0x58>)
8001e58: 69db ldr r3, [r3, #28]
8001e5a: f003 0304 and.w r3, r3, #4
8001e5e: 60bb str r3, [r7, #8]
8001e60: 68bb ldr r3, [r7, #8]
}
8001e62: bf00 nop
8001e64: 3714 adds r7, #20
8001e66: 46bd mov sp, r7
8001e68: bc80 pop {r7}
8001e6a: 4770 bx lr
8001e6c: 40021000 .word 0x40021000
8001e70: 40000800 .word 0x40000800
08001e74 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001e74: b580 push {r7, lr}
8001e76: b088 sub sp, #32
8001e78: af00 add r7, sp, #0
8001e7a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001e7c: f107 0310 add.w r3, r7, #16
8001e80: 2200 movs r2, #0
8001e82: 601a str r2, [r3, #0]
8001e84: 605a str r2, [r3, #4]
8001e86: 609a str r2, [r3, #8]
8001e88: 60da str r2, [r3, #12]
if(htim->Instance==TIM2)
8001e8a: 687b ldr r3, [r7, #4]
8001e8c: 681b ldr r3, [r3, #0]
8001e8e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001e92: d118 bne.n 8001ec6 <HAL_TIM_MspPostInit+0x52>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001e94: 4b1d ldr r3, [pc, #116] @ (8001f0c <HAL_TIM_MspPostInit+0x98>)
8001e96: 699b ldr r3, [r3, #24]
8001e98: 4a1c ldr r2, [pc, #112] @ (8001f0c <HAL_TIM_MspPostInit+0x98>)
8001e9a: f043 0304 orr.w r3, r3, #4
8001e9e: 6193 str r3, [r2, #24]
8001ea0: 4b1a ldr r3, [pc, #104] @ (8001f0c <HAL_TIM_MspPostInit+0x98>)
8001ea2: 699b ldr r3, [r3, #24]
8001ea4: f003 0304 and.w r3, r3, #4
8001ea8: 60fb str r3, [r7, #12]
8001eaa: 68fb ldr r3, [r7, #12]
PA0-WKUP ------> TIM2_CH1
PA1 ------> TIM2_CH2
PA2 ------> TIM2_CH3
PA3 ------> TIM2_CH4
*/
GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|IN3_Pin|IN4_Pin;
8001eac: 230f movs r3, #15
8001eae: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001eb0: 2302 movs r3, #2
8001eb2: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001eb4: 2302 movs r3, #2
8001eb6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001eb8: f107 0310 add.w r3, r7, #16
8001ebc: 4619 mov r1, r3
8001ebe: 4814 ldr r0, [pc, #80] @ (8001f10 <HAL_TIM_MspPostInit+0x9c>)
8001ec0: f001 fa4c bl 800335c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
8001ec4: e01d b.n 8001f02 <HAL_TIM_MspPostInit+0x8e>
else if(htim->Instance==TIM4)
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: 681b ldr r3, [r3, #0]
8001eca: 4a12 ldr r2, [pc, #72] @ (8001f14 <HAL_TIM_MspPostInit+0xa0>)
8001ecc: 4293 cmp r3, r2
8001ece: d118 bne.n 8001f02 <HAL_TIM_MspPostInit+0x8e>
__HAL_RCC_GPIOB_CLK_ENABLE();
8001ed0: 4b0e ldr r3, [pc, #56] @ (8001f0c <HAL_TIM_MspPostInit+0x98>)
8001ed2: 699b ldr r3, [r3, #24]
8001ed4: 4a0d ldr r2, [pc, #52] @ (8001f0c <HAL_TIM_MspPostInit+0x98>)
8001ed6: f043 0308 orr.w r3, r3, #8
8001eda: 6193 str r3, [r2, #24]
8001edc: 4b0b ldr r3, [pc, #44] @ (8001f0c <HAL_TIM_MspPostInit+0x98>)
8001ede: 699b ldr r3, [r3, #24]
8001ee0: f003 0308 and.w r3, r3, #8
8001ee4: 60bb str r3, [r7, #8]
8001ee6: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = IN5_Pin|IN6_Pin|IN7_Pin|IN8_Pin;
8001ee8: f44f 7370 mov.w r3, #960 @ 0x3c0
8001eec: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001eee: 2302 movs r3, #2
8001ef0: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001ef2: 2302 movs r3, #2
8001ef4: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001ef6: f107 0310 add.w r3, r7, #16
8001efa: 4619 mov r1, r3
8001efc: 4806 ldr r0, [pc, #24] @ (8001f18 <HAL_TIM_MspPostInit+0xa4>)
8001efe: f001 fa2d bl 800335c <HAL_GPIO_Init>
}
8001f02: bf00 nop
8001f04: 3720 adds r7, #32
8001f06: 46bd mov sp, r7
8001f08: bd80 pop {r7, pc}
8001f0a: bf00 nop
8001f0c: 40021000 .word 0x40021000
8001f10: 40010800 .word 0x40010800
8001f14: 40000800 .word 0x40000800
8001f18: 40010c00 .word 0x40010c00
08001f1c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001f1c: b580 push {r7, lr}
8001f1e: b088 sub sp, #32
8001f20: af00 add r7, sp, #0
8001f22: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001f24: f107 0310 add.w r3, r7, #16
8001f28: 2200 movs r2, #0
8001f2a: 601a str r2, [r3, #0]
8001f2c: 605a str r2, [r3, #4]
8001f2e: 609a str r2, [r3, #8]
8001f30: 60da str r2, [r3, #12]
if(huart->Instance==USART1)
8001f32: 687b ldr r3, [r7, #4]
8001f34: 681b ldr r3, [r3, #0]
8001f36: 4a1c ldr r2, [pc, #112] @ (8001fa8 <HAL_UART_MspInit+0x8c>)
8001f38: 4293 cmp r3, r2
8001f3a: d131 bne.n 8001fa0 <HAL_UART_MspInit+0x84>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8001f3c: 4b1b ldr r3, [pc, #108] @ (8001fac <HAL_UART_MspInit+0x90>)
8001f3e: 699b ldr r3, [r3, #24]
8001f40: 4a1a ldr r2, [pc, #104] @ (8001fac <HAL_UART_MspInit+0x90>)
8001f42: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001f46: 6193 str r3, [r2, #24]
8001f48: 4b18 ldr r3, [pc, #96] @ (8001fac <HAL_UART_MspInit+0x90>)
8001f4a: 699b ldr r3, [r3, #24]
8001f4c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001f50: 60fb str r3, [r7, #12]
8001f52: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001f54: 4b15 ldr r3, [pc, #84] @ (8001fac <HAL_UART_MspInit+0x90>)
8001f56: 699b ldr r3, [r3, #24]
8001f58: 4a14 ldr r2, [pc, #80] @ (8001fac <HAL_UART_MspInit+0x90>)
8001f5a: f043 0304 orr.w r3, r3, #4
8001f5e: 6193 str r3, [r2, #24]
8001f60: 4b12 ldr r3, [pc, #72] @ (8001fac <HAL_UART_MspInit+0x90>)
8001f62: 699b ldr r3, [r3, #24]
8001f64: f003 0304 and.w r3, r3, #4
8001f68: 60bb str r3, [r7, #8]
8001f6a: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
8001f6c: f44f 7300 mov.w r3, #512 @ 0x200
8001f70: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001f72: 2302 movs r3, #2
8001f74: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8001f76: 2303 movs r3, #3
8001f78: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001f7a: f107 0310 add.w r3, r7, #16
8001f7e: 4619 mov r1, r3
8001f80: 480b ldr r0, [pc, #44] @ (8001fb0 <HAL_UART_MspInit+0x94>)
8001f82: f001 f9eb bl 800335c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_10;
8001f86: f44f 6380 mov.w r3, #1024 @ 0x400
8001f8a: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001f8c: 2300 movs r3, #0
8001f8e: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f90: 2300 movs r3, #0
8001f92: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001f94: f107 0310 add.w r3, r7, #16
8001f98: 4619 mov r1, r3
8001f9a: 4805 ldr r0, [pc, #20] @ (8001fb0 <HAL_UART_MspInit+0x94>)
8001f9c: f001 f9de bl 800335c <HAL_GPIO_Init>
/* USER CODE END USART1_MspInit 1 */
}
}
8001fa0: bf00 nop
8001fa2: 3720 adds r7, #32
8001fa4: 46bd mov sp, r7
8001fa6: bd80 pop {r7, pc}
8001fa8: 40013800 .word 0x40013800
8001fac: 40021000 .word 0x40021000
8001fb0: 40010800 .word 0x40010800
08001fb4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001fb4: b480 push {r7}
8001fb6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001fb8: bf00 nop
8001fba: e7fd b.n 8001fb8 <NMI_Handler+0x4>
08001fbc <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001fbc: b480 push {r7}
8001fbe: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001fc0: bf00 nop
8001fc2: e7fd b.n 8001fc0 <HardFault_Handler+0x4>
08001fc4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001fc4: b480 push {r7}
8001fc6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001fc8: bf00 nop
8001fca: e7fd b.n 8001fc8 <MemManage_Handler+0x4>
08001fcc <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001fcc: b480 push {r7}
8001fce: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001fd0: bf00 nop
8001fd2: e7fd b.n 8001fd0 <BusFault_Handler+0x4>
08001fd4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001fd4: b480 push {r7}
8001fd6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001fd8: bf00 nop
8001fda: e7fd b.n 8001fd8 <UsageFault_Handler+0x4>
08001fdc <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001fdc: b480 push {r7}
8001fde: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001fe0: bf00 nop
8001fe2: 46bd mov sp, r7
8001fe4: bc80 pop {r7}
8001fe6: 4770 bx lr
08001fe8 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001fe8: b480 push {r7}
8001fea: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001fec: bf00 nop
8001fee: 46bd mov sp, r7
8001ff0: bc80 pop {r7}
8001ff2: 4770 bx lr
08001ff4 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001ff4: b480 push {r7}
8001ff6: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001ff8: bf00 nop
8001ffa: 46bd mov sp, r7
8001ffc: bc80 pop {r7}
8001ffe: 4770 bx lr
08002000 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002000: b580 push {r7, lr}
8002002: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8002004: f000 f8c0 bl 8002188 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
HAL_SYSTICK_IRQHandler();
8002008: f000 fdb3 bl 8002b72 <HAL_SYSTICK_IRQHandler>
/* USER CODE END SysTick_IRQn 1 */
}
800200c: bf00 nop
800200e: bd80 pop {r7, pc}
08002010 <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
8002010: b580 push {r7, lr}
8002012: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc1);
8002014: 4802 ldr r0, [pc, #8] @ (8002020 <DMA1_Channel1_IRQHandler+0x10>)
8002016: f000 fe6d bl 8002cf4 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
800201a: bf00 nop
800201c: bd80 pop {r7, pc}
800201e: bf00 nop
8002020: 200002bc .word 0x200002bc
08002024 <USB_LP_CAN1_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN RX0 interrupts.
*/
void USB_LP_CAN1_RX0_IRQHandler(void)
{
8002024: b580 push {r7, lr}
8002026: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_FS);
8002028: 4802 ldr r0, [pc, #8] @ (8002034 <USB_LP_CAN1_RX0_IRQHandler+0x10>)
800202a: f001 fc7f bl 800392c <HAL_PCD_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
}
800202e: bf00 nop
8002030: bd80 pop {r7, pc}
8002032: bf00 nop
8002034: 200011dc .word 0x200011dc
08002038 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8002038: b580 push {r7, lr}
800203a: b086 sub sp, #24
800203c: af00 add r7, sp, #0
800203e: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8002040: 4a14 ldr r2, [pc, #80] @ (8002094 <_sbrk+0x5c>)
8002042: 4b15 ldr r3, [pc, #84] @ (8002098 <_sbrk+0x60>)
8002044: 1ad3 subs r3, r2, r3
8002046: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8002048: 697b ldr r3, [r7, #20]
800204a: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
800204c: 4b13 ldr r3, [pc, #76] @ (800209c <_sbrk+0x64>)
800204e: 681b ldr r3, [r3, #0]
8002050: 2b00 cmp r3, #0
8002052: d102 bne.n 800205a <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8002054: 4b11 ldr r3, [pc, #68] @ (800209c <_sbrk+0x64>)
8002056: 4a12 ldr r2, [pc, #72] @ (80020a0 <_sbrk+0x68>)
8002058: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
800205a: 4b10 ldr r3, [pc, #64] @ (800209c <_sbrk+0x64>)
800205c: 681a ldr r2, [r3, #0]
800205e: 687b ldr r3, [r7, #4]
8002060: 4413 add r3, r2
8002062: 693a ldr r2, [r7, #16]
8002064: 429a cmp r2, r3
8002066: d207 bcs.n 8002078 <_sbrk+0x40>
{
errno = ENOMEM;
8002068: f009 f8fc bl 800b264 <__errno>
800206c: 4603 mov r3, r0
800206e: 220c movs r2, #12
8002070: 601a str r2, [r3, #0]
return (void *)-1;
8002072: f04f 33ff mov.w r3, #4294967295
8002076: e009 b.n 800208c <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8002078: 4b08 ldr r3, [pc, #32] @ (800209c <_sbrk+0x64>)
800207a: 681b ldr r3, [r3, #0]
800207c: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
800207e: 4b07 ldr r3, [pc, #28] @ (800209c <_sbrk+0x64>)
8002080: 681a ldr r2, [r3, #0]
8002082: 687b ldr r3, [r7, #4]
8002084: 4413 add r3, r2
8002086: 4a05 ldr r2, [pc, #20] @ (800209c <_sbrk+0x64>)
8002088: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
800208a: 68fb ldr r3, [r7, #12]
}
800208c: 4618 mov r0, r3
800208e: 3718 adds r7, #24
8002090: 46bd mov sp, r7
8002092: bd80 pop {r7, pc}
8002094: 20005000 .word 0x20005000
8002098: 00000400 .word 0x00000400
800209c: 200003e4 .word 0x200003e4
80020a0: 20001820 .word 0x20001820
080020a4 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80020a4: b480 push {r7}
80020a6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80020a8: bf00 nop
80020aa: 46bd mov sp, r7
80020ac: bc80 pop {r7}
80020ae: 4770 bx lr
080020b0 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80020b0: f7ff fff8 bl 80020a4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80020b4: 480b ldr r0, [pc, #44] @ (80020e4 <LoopFillZerobss+0xe>)
ldr r1, =_edata
80020b6: 490c ldr r1, [pc, #48] @ (80020e8 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
80020b8: 4a0c ldr r2, [pc, #48] @ (80020ec <LoopFillZerobss+0x16>)
movs r3, #0
80020ba: 2300 movs r3, #0
b LoopCopyDataInit
80020bc: e002 b.n 80020c4 <LoopCopyDataInit>
080020be <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80020be: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80020c0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80020c2: 3304 adds r3, #4
080020c4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80020c4: 18c4 adds r4, r0, r3
cmp r4, r1
80020c6: 428c cmp r4, r1
bcc CopyDataInit
80020c8: d3f9 bcc.n 80020be <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80020ca: 4a09 ldr r2, [pc, #36] @ (80020f0 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
80020cc: 4c09 ldr r4, [pc, #36] @ (80020f4 <LoopFillZerobss+0x1e>)
movs r3, #0
80020ce: 2300 movs r3, #0
b LoopFillZerobss
80020d0: e001 b.n 80020d6 <LoopFillZerobss>
080020d2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80020d2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80020d4: 3204 adds r2, #4
080020d6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80020d6: 42a2 cmp r2, r4
bcc FillZerobss
80020d8: d3fb bcc.n 80020d2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80020da: f009 f8c9 bl 800b270 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80020de: f7ff f893 bl 8001208 <main>
bx lr
80020e2: 4770 bx lr
ldr r0, =_sdata
80020e4: 20000000 .word 0x20000000
ldr r1, =_edata
80020e8: 200001d0 .word 0x200001d0
ldr r2, =_sidata
80020ec: 0800be58 .word 0x0800be58
ldr r2, =_sbss
80020f0: 200001d0 .word 0x200001d0
ldr r4, =_ebss
80020f4: 2000181c .word 0x2000181c
080020f8 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80020f8: e7fe b.n 80020f8 <ADC1_2_IRQHandler>
...
080020fc <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80020fc: b580 push {r7, lr}
80020fe: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8002100: 4b08 ldr r3, [pc, #32] @ (8002124 <HAL_Init+0x28>)
8002102: 681b ldr r3, [r3, #0]
8002104: 4a07 ldr r2, [pc, #28] @ (8002124 <HAL_Init+0x28>)
8002106: f043 0310 orr.w r3, r3, #16
800210a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800210c: 2003 movs r0, #3
800210e: f000 fcef bl 8002af0 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8002112: 200f movs r0, #15
8002114: f000 f808 bl 8002128 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8002118: f7ff fdca bl 8001cb0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800211c: 2300 movs r3, #0
}
800211e: 4618 mov r0, r3
8002120: bd80 pop {r7, pc}
8002122: bf00 nop
8002124: 40022000 .word 0x40022000
08002128 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002128: b580 push {r7, lr}
800212a: b082 sub sp, #8
800212c: af00 add r7, sp, #0
800212e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8002130: 4b12 ldr r3, [pc, #72] @ (800217c <HAL_InitTick+0x54>)
8002132: 681a ldr r2, [r3, #0]
8002134: 4b12 ldr r3, [pc, #72] @ (8002180 <HAL_InitTick+0x58>)
8002136: 781b ldrb r3, [r3, #0]
8002138: 4619 mov r1, r3
800213a: f44f 737a mov.w r3, #1000 @ 0x3e8
800213e: fbb3 f3f1 udiv r3, r3, r1
8002142: fbb2 f3f3 udiv r3, r2, r3
8002146: 4618 mov r0, r3
8002148: f000 fd07 bl 8002b5a <HAL_SYSTICK_Config>
800214c: 4603 mov r3, r0
800214e: 2b00 cmp r3, #0
8002150: d001 beq.n 8002156 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8002152: 2301 movs r3, #1
8002154: e00e b.n 8002174 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8002156: 687b ldr r3, [r7, #4]
8002158: 2b0f cmp r3, #15
800215a: d80a bhi.n 8002172 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800215c: 2200 movs r2, #0
800215e: 6879 ldr r1, [r7, #4]
8002160: f04f 30ff mov.w r0, #4294967295
8002164: f000 fccf bl 8002b06 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8002168: 4a06 ldr r2, [pc, #24] @ (8002184 <HAL_InitTick+0x5c>)
800216a: 687b ldr r3, [r7, #4]
800216c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800216e: 2300 movs r3, #0
8002170: e000 b.n 8002174 <HAL_InitTick+0x4c>
return HAL_ERROR;
8002172: 2301 movs r3, #1
}
8002174: 4618 mov r0, r3
8002176: 3708 adds r7, #8
8002178: 46bd mov sp, r7
800217a: bd80 pop {r7, pc}
800217c: 20000004 .word 0x20000004
8002180: 2000000c .word 0x2000000c
8002184: 20000008 .word 0x20000008
08002188 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8002188: b480 push {r7}
800218a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800218c: 4b05 ldr r3, [pc, #20] @ (80021a4 <HAL_IncTick+0x1c>)
800218e: 781b ldrb r3, [r3, #0]
8002190: 461a mov r2, r3
8002192: 4b05 ldr r3, [pc, #20] @ (80021a8 <HAL_IncTick+0x20>)
8002194: 681b ldr r3, [r3, #0]
8002196: 4413 add r3, r2
8002198: 4a03 ldr r2, [pc, #12] @ (80021a8 <HAL_IncTick+0x20>)
800219a: 6013 str r3, [r2, #0]
}
800219c: bf00 nop
800219e: 46bd mov sp, r7
80021a0: bc80 pop {r7}
80021a2: 4770 bx lr
80021a4: 2000000c .word 0x2000000c
80021a8: 200003e8 .word 0x200003e8
080021ac <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80021ac: b480 push {r7}
80021ae: af00 add r7, sp, #0
return uwTick;
80021b0: 4b02 ldr r3, [pc, #8] @ (80021bc <HAL_GetTick+0x10>)
80021b2: 681b ldr r3, [r3, #0]
}
80021b4: 4618 mov r0, r3
80021b6: 46bd mov sp, r7
80021b8: bc80 pop {r7}
80021ba: 4770 bx lr
80021bc: 200003e8 .word 0x200003e8
080021c0 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80021c0: b580 push {r7, lr}
80021c2: b086 sub sp, #24
80021c4: af00 add r7, sp, #0
80021c6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80021c8: 2300 movs r3, #0
80021ca: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
80021cc: 2300 movs r3, #0
80021ce: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
80021d0: 2300 movs r3, #0
80021d2: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
80021d4: 2300 movs r3, #0
80021d6: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
80021d8: 687b ldr r3, [r7, #4]
80021da: 2b00 cmp r3, #0
80021dc: d101 bne.n 80021e2 <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
80021de: 2301 movs r3, #1
80021e0: e0be b.n 8002360 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
80021e2: 687b ldr r3, [r7, #4]
80021e4: 689b ldr r3, [r3, #8]
80021e6: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
80021e8: 687b ldr r3, [r7, #4]
80021ea: 6a9b ldr r3, [r3, #40] @ 0x28
80021ec: 2b00 cmp r3, #0
80021ee: d109 bne.n 8002204 <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
80021f0: 687b ldr r3, [r7, #4]
80021f2: 2200 movs r2, #0
80021f4: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
80021f6: 687b ldr r3, [r7, #4]
80021f8: 2200 movs r2, #0
80021fa: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80021fe: 6878 ldr r0, [r7, #4]
8002200: f7ff fd88 bl 8001d14 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8002204: 6878 ldr r0, [r7, #4]
8002206: f000 faff bl 8002808 <ADC_ConversionStop_Disable>
800220a: 4603 mov r3, r0
800220c: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
800220e: 687b ldr r3, [r7, #4]
8002210: 6a9b ldr r3, [r3, #40] @ 0x28
8002212: f003 0310 and.w r3, r3, #16
8002216: 2b00 cmp r3, #0
8002218: f040 8099 bne.w 800234e <HAL_ADC_Init+0x18e>
800221c: 7dfb ldrb r3, [r7, #23]
800221e: 2b00 cmp r3, #0
8002220: f040 8095 bne.w 800234e <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002224: 687b ldr r3, [r7, #4]
8002226: 6a9b ldr r3, [r3, #40] @ 0x28
8002228: f423 5388 bic.w r3, r3, #4352 @ 0x1100
800222c: f023 0302 bic.w r3, r3, #2
8002230: f043 0202 orr.w r2, r3, #2
8002234: 687b ldr r3, [r7, #4]
8002236: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8002238: 687b ldr r3, [r7, #4]
800223a: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
800223c: 687b ldr r3, [r7, #4]
800223e: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8002240: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8002242: 687b ldr r3, [r7, #4]
8002244: 7b1b ldrb r3, [r3, #12]
8002246: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8002248: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
800224a: 68ba ldr r2, [r7, #8]
800224c: 4313 orrs r3, r2
800224e: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8002250: 687b ldr r3, [r7, #4]
8002252: 689b ldr r3, [r3, #8]
8002254: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002258: d003 beq.n 8002262 <HAL_ADC_Init+0xa2>
800225a: 687b ldr r3, [r7, #4]
800225c: 689b ldr r3, [r3, #8]
800225e: 2b01 cmp r3, #1
8002260: d102 bne.n 8002268 <HAL_ADC_Init+0xa8>
8002262: f44f 7380 mov.w r3, #256 @ 0x100
8002266: e000 b.n 800226a <HAL_ADC_Init+0xaa>
8002268: 2300 movs r3, #0
800226a: 693a ldr r2, [r7, #16]
800226c: 4313 orrs r3, r2
800226e: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8002270: 687b ldr r3, [r7, #4]
8002272: 7d1b ldrb r3, [r3, #20]
8002274: 2b01 cmp r3, #1
8002276: d119 bne.n 80022ac <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8002278: 687b ldr r3, [r7, #4]
800227a: 7b1b ldrb r3, [r3, #12]
800227c: 2b00 cmp r3, #0
800227e: d109 bne.n 8002294 <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8002280: 687b ldr r3, [r7, #4]
8002282: 699b ldr r3, [r3, #24]
8002284: 3b01 subs r3, #1
8002286: 035a lsls r2, r3, #13
8002288: 693b ldr r3, [r7, #16]
800228a: 4313 orrs r3, r2
800228c: f443 6300 orr.w r3, r3, #2048 @ 0x800
8002290: 613b str r3, [r7, #16]
8002292: e00b b.n 80022ac <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002294: 687b ldr r3, [r7, #4]
8002296: 6a9b ldr r3, [r3, #40] @ 0x28
8002298: f043 0220 orr.w r2, r3, #32
800229c: 687b ldr r3, [r7, #4]
800229e: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80022a0: 687b ldr r3, [r7, #4]
80022a2: 6adb ldr r3, [r3, #44] @ 0x2c
80022a4: f043 0201 orr.w r2, r3, #1
80022a8: 687b ldr r3, [r7, #4]
80022aa: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
80022ac: 687b ldr r3, [r7, #4]
80022ae: 681b ldr r3, [r3, #0]
80022b0: 685b ldr r3, [r3, #4]
80022b2: f423 4169 bic.w r1, r3, #59648 @ 0xe900
80022b6: 687b ldr r3, [r7, #4]
80022b8: 681b ldr r3, [r3, #0]
80022ba: 693a ldr r2, [r7, #16]
80022bc: 430a orrs r2, r1
80022be: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
80022c0: 687b ldr r3, [r7, #4]
80022c2: 681b ldr r3, [r3, #0]
80022c4: 689a ldr r2, [r3, #8]
80022c6: 4b28 ldr r3, [pc, #160] @ (8002368 <HAL_ADC_Init+0x1a8>)
80022c8: 4013 ands r3, r2
80022ca: 687a ldr r2, [r7, #4]
80022cc: 6812 ldr r2, [r2, #0]
80022ce: 68b9 ldr r1, [r7, #8]
80022d0: 430b orrs r3, r1
80022d2: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
80022d4: 687b ldr r3, [r7, #4]
80022d6: 689b ldr r3, [r3, #8]
80022d8: f5b3 7f80 cmp.w r3, #256 @ 0x100
80022dc: d003 beq.n 80022e6 <HAL_ADC_Init+0x126>
80022de: 687b ldr r3, [r7, #4]
80022e0: 689b ldr r3, [r3, #8]
80022e2: 2b01 cmp r3, #1
80022e4: d104 bne.n 80022f0 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
80022e6: 687b ldr r3, [r7, #4]
80022e8: 691b ldr r3, [r3, #16]
80022ea: 3b01 subs r3, #1
80022ec: 051b lsls r3, r3, #20
80022ee: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
80022f0: 687b ldr r3, [r7, #4]
80022f2: 681b ldr r3, [r3, #0]
80022f4: 6adb ldr r3, [r3, #44] @ 0x2c
80022f6: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
80022fa: 687b ldr r3, [r7, #4]
80022fc: 681b ldr r3, [r3, #0]
80022fe: 68fa ldr r2, [r7, #12]
8002300: 430a orrs r2, r1
8002302: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8002304: 687b ldr r3, [r7, #4]
8002306: 681b ldr r3, [r3, #0]
8002308: 689a ldr r2, [r3, #8]
800230a: 4b18 ldr r3, [pc, #96] @ (800236c <HAL_ADC_Init+0x1ac>)
800230c: 4013 ands r3, r2
800230e: 68ba ldr r2, [r7, #8]
8002310: 429a cmp r2, r3
8002312: d10b bne.n 800232c <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002314: 687b ldr r3, [r7, #4]
8002316: 2200 movs r2, #0
8002318: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800231a: 687b ldr r3, [r7, #4]
800231c: 6a9b ldr r3, [r3, #40] @ 0x28
800231e: f023 0303 bic.w r3, r3, #3
8002322: f043 0201 orr.w r2, r3, #1
8002326: 687b ldr r3, [r7, #4]
8002328: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800232a: e018 b.n 800235e <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
800232c: 687b ldr r3, [r7, #4]
800232e: 6a9b ldr r3, [r3, #40] @ 0x28
8002330: f023 0312 bic.w r3, r3, #18
8002334: f043 0210 orr.w r2, r3, #16
8002338: 687b ldr r3, [r7, #4]
800233a: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800233c: 687b ldr r3, [r7, #4]
800233e: 6adb ldr r3, [r3, #44] @ 0x2c
8002340: f043 0201 orr.w r2, r3, #1
8002344: 687b ldr r3, [r7, #4]
8002346: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8002348: 2301 movs r3, #1
800234a: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800234c: e007 b.n 800235e <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800234e: 687b ldr r3, [r7, #4]
8002350: 6a9b ldr r3, [r3, #40] @ 0x28
8002352: f043 0210 orr.w r2, r3, #16
8002356: 687b ldr r3, [r7, #4]
8002358: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
800235a: 2301 movs r3, #1
800235c: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800235e: 7dfb ldrb r3, [r7, #23]
}
8002360: 4618 mov r0, r3
8002362: 3718 adds r7, #24
8002364: 46bd mov sp, r7
8002366: bd80 pop {r7, pc}
8002368: ffe1f7fd .word 0xffe1f7fd
800236c: ff1f0efe .word 0xff1f0efe
08002370 <HAL_ADC_Start_DMA>:
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
8002370: b580 push {r7, lr}
8002372: b086 sub sp, #24
8002374: af00 add r7, sp, #0
8002376: 60f8 str r0, [r7, #12]
8002378: 60b9 str r1, [r7, #8]
800237a: 607a str r2, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800237c: 2300 movs r3, #0
800237e: 75fb strb r3, [r7, #23]
assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
/* Verification if multimode is disabled (for devices with several ADC) */
/* If multimode is enabled, dedicated function multimode conversion */
/* start DMA must be used. */
if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
8002380: 68fb ldr r3, [r7, #12]
8002382: 681b ldr r3, [r3, #0]
8002384: 4a64 ldr r2, [pc, #400] @ (8002518 <HAL_ADC_Start_DMA+0x1a8>)
8002386: 4293 cmp r3, r2
8002388: d004 beq.n 8002394 <HAL_ADC_Start_DMA+0x24>
800238a: 68fb ldr r3, [r7, #12]
800238c: 681b ldr r3, [r3, #0]
800238e: 4a63 ldr r2, [pc, #396] @ (800251c <HAL_ADC_Start_DMA+0x1ac>)
8002390: 4293 cmp r3, r2
8002392: d106 bne.n 80023a2 <HAL_ADC_Start_DMA+0x32>
8002394: 4b60 ldr r3, [pc, #384] @ (8002518 <HAL_ADC_Start_DMA+0x1a8>)
8002396: 685b ldr r3, [r3, #4]
8002398: f403 2370 and.w r3, r3, #983040 @ 0xf0000
800239c: 2b00 cmp r3, #0
800239e: f040 80b3 bne.w 8002508 <HAL_ADC_Start_DMA+0x198>
{
/* Process locked */
__HAL_LOCK(hadc);
80023a2: 68fb ldr r3, [r7, #12]
80023a4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80023a8: 2b01 cmp r3, #1
80023aa: d101 bne.n 80023b0 <HAL_ADC_Start_DMA+0x40>
80023ac: 2302 movs r3, #2
80023ae: e0ae b.n 800250e <HAL_ADC_Start_DMA+0x19e>
80023b0: 68fb ldr r3, [r7, #12]
80023b2: 2201 movs r2, #1
80023b4: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
80023b8: 68f8 ldr r0, [r7, #12]
80023ba: f000 f9cb bl 8002754 <ADC_Enable>
80023be: 4603 mov r3, r0
80023c0: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
80023c2: 7dfb ldrb r3, [r7, #23]
80023c4: 2b00 cmp r3, #0
80023c6: f040 809a bne.w 80024fe <HAL_ADC_Start_DMA+0x18e>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
80023ca: 68fb ldr r3, [r7, #12]
80023cc: 6a9b ldr r3, [r3, #40] @ 0x28
80023ce: f423 6370 bic.w r3, r3, #3840 @ 0xf00
80023d2: f023 0301 bic.w r3, r3, #1
80023d6: f443 7280 orr.w r2, r3, #256 @ 0x100
80023da: 68fb ldr r3, [r7, #12]
80023dc: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_REG_BUSY);
/* Set group injected state (from auto-injection) and multimode state */
/* for all cases of multimode: independent mode, multimode ADC master */
/* or multimode ADC slave (for devices with several ADCs): */
if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
80023de: 68fb ldr r3, [r7, #12]
80023e0: 681b ldr r3, [r3, #0]
80023e2: 4a4e ldr r2, [pc, #312] @ (800251c <HAL_ADC_Start_DMA+0x1ac>)
80023e4: 4293 cmp r3, r2
80023e6: d105 bne.n 80023f4 <HAL_ADC_Start_DMA+0x84>
80023e8: 4b4b ldr r3, [pc, #300] @ (8002518 <HAL_ADC_Start_DMA+0x1a8>)
80023ea: 685b ldr r3, [r3, #4]
80023ec: f403 2370 and.w r3, r3, #983040 @ 0xf0000
80023f0: 2b00 cmp r3, #0
80023f2: d115 bne.n 8002420 <HAL_ADC_Start_DMA+0xb0>
{
/* Set ADC state (ADC independent or master) */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
80023f4: 68fb ldr r3, [r7, #12]
80023f6: 6a9b ldr r3, [r3, #40] @ 0x28
80023f8: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
80023fc: 68fb ldr r3, [r7, #12]
80023fe: 629a str r2, [r3, #40] @ 0x28
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8002400: 68fb ldr r3, [r7, #12]
8002402: 681b ldr r3, [r3, #0]
8002404: 685b ldr r3, [r3, #4]
8002406: f403 6380 and.w r3, r3, #1024 @ 0x400
800240a: 2b00 cmp r3, #0
800240c: d026 beq.n 800245c <HAL_ADC_Start_DMA+0xec>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800240e: 68fb ldr r3, [r7, #12]
8002410: 6a9b ldr r3, [r3, #40] @ 0x28
8002412: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002416: f443 5280 orr.w r2, r3, #4096 @ 0x1000
800241a: 68fb ldr r3, [r7, #12]
800241c: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
800241e: e01d b.n 800245c <HAL_ADC_Start_DMA+0xec>
}
}
else
{
/* Set ADC state (ADC slave) */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002420: 68fb ldr r3, [r7, #12]
8002422: 6a9b ldr r3, [r3, #40] @ 0x28
8002424: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
8002428: 68fb ldr r3, [r7, #12]
800242a: 629a str r2, [r3, #40] @ 0x28
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
800242c: 68fb ldr r3, [r7, #12]
800242e: 681b ldr r3, [r3, #0]
8002430: 4a39 ldr r2, [pc, #228] @ (8002518 <HAL_ADC_Start_DMA+0x1a8>)
8002432: 4293 cmp r3, r2
8002434: d004 beq.n 8002440 <HAL_ADC_Start_DMA+0xd0>
8002436: 68fb ldr r3, [r7, #12]
8002438: 681b ldr r3, [r3, #0]
800243a: 4a38 ldr r2, [pc, #224] @ (800251c <HAL_ADC_Start_DMA+0x1ac>)
800243c: 4293 cmp r3, r2
800243e: d10d bne.n 800245c <HAL_ADC_Start_DMA+0xec>
8002440: 4b35 ldr r3, [pc, #212] @ (8002518 <HAL_ADC_Start_DMA+0x1a8>)
8002442: 685b ldr r3, [r3, #4]
8002444: f403 6380 and.w r3, r3, #1024 @ 0x400
8002448: 2b00 cmp r3, #0
800244a: d007 beq.n 800245c <HAL_ADC_Start_DMA+0xec>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800244c: 68fb ldr r3, [r7, #12]
800244e: 6a9b ldr r3, [r3, #40] @ 0x28
8002450: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002454: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8002458: 68fb ldr r3, [r7, #12]
800245a: 629a str r2, [r3, #40] @ 0x28
}
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
800245c: 68fb ldr r3, [r7, #12]
800245e: 6a9b ldr r3, [r3, #40] @ 0x28
8002460: f403 5380 and.w r3, r3, #4096 @ 0x1000
8002464: 2b00 cmp r3, #0
8002466: d006 beq.n 8002476 <HAL_ADC_Start_DMA+0x106>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8002468: 68fb ldr r3, [r7, #12]
800246a: 6adb ldr r3, [r3, #44] @ 0x2c
800246c: f023 0206 bic.w r2, r3, #6
8002470: 68fb ldr r3, [r7, #12]
8002472: 62da str r2, [r3, #44] @ 0x2c
8002474: e002 b.n 800247c <HAL_ADC_Start_DMA+0x10c>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8002476: 68fb ldr r3, [r7, #12]
8002478: 2200 movs r2, #0
800247a: 62da str r2, [r3, #44] @ 0x2c
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
800247c: 68fb ldr r3, [r7, #12]
800247e: 2200 movs r2, #0
8002480: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
8002484: 68fb ldr r3, [r7, #12]
8002486: 6a1b ldr r3, [r3, #32]
8002488: 4a25 ldr r2, [pc, #148] @ (8002520 <HAL_ADC_Start_DMA+0x1b0>)
800248a: 629a str r2, [r3, #40] @ 0x28
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
800248c: 68fb ldr r3, [r7, #12]
800248e: 6a1b ldr r3, [r3, #32]
8002490: 4a24 ldr r2, [pc, #144] @ (8002524 <HAL_ADC_Start_DMA+0x1b4>)
8002492: 62da str r2, [r3, #44] @ 0x2c
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
8002494: 68fb ldr r3, [r7, #12]
8002496: 6a1b ldr r3, [r3, #32]
8002498: 4a23 ldr r2, [pc, #140] @ (8002528 <HAL_ADC_Start_DMA+0x1b8>)
800249a: 631a str r2, [r3, #48] @ 0x30
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
800249c: 68fb ldr r3, [r7, #12]
800249e: 681b ldr r3, [r3, #0]
80024a0: f06f 0202 mvn.w r2, #2
80024a4: 601a str r2, [r3, #0]
/* Enable ADC DMA mode */
SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
80024a6: 68fb ldr r3, [r7, #12]
80024a8: 681b ldr r3, [r3, #0]
80024aa: 689a ldr r2, [r3, #8]
80024ac: 68fb ldr r3, [r7, #12]
80024ae: 681b ldr r3, [r3, #0]
80024b0: f442 7280 orr.w r2, r2, #256 @ 0x100
80024b4: 609a str r2, [r3, #8]
/* Start the DMA channel */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
80024b6: 68fb ldr r3, [r7, #12]
80024b8: 6a18 ldr r0, [r3, #32]
80024ba: 68fb ldr r3, [r7, #12]
80024bc: 681b ldr r3, [r3, #0]
80024be: 334c adds r3, #76 @ 0x4c
80024c0: 4619 mov r1, r3
80024c2: 68ba ldr r2, [r7, #8]
80024c4: 687b ldr r3, [r7, #4]
80024c6: f000 fbb5 bl 8002c34 <HAL_DMA_Start_IT>
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
80024ca: 68fb ldr r3, [r7, #12]
80024cc: 681b ldr r3, [r3, #0]
80024ce: 689b ldr r3, [r3, #8]
80024d0: f403 2360 and.w r3, r3, #917504 @ 0xe0000
80024d4: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000
80024d8: d108 bne.n 80024ec <HAL_ADC_Start_DMA+0x17c>
{
/* Start ADC conversion on regular group with SW start */
SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
80024da: 68fb ldr r3, [r7, #12]
80024dc: 681b ldr r3, [r3, #0]
80024de: 689a ldr r2, [r3, #8]
80024e0: 68fb ldr r3, [r7, #12]
80024e2: 681b ldr r3, [r3, #0]
80024e4: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000
80024e8: 609a str r2, [r3, #8]
if (tmp_hal_status == HAL_OK)
80024ea: e00f b.n 800250c <HAL_ADC_Start_DMA+0x19c>
}
else
{
/* Start ADC conversion on regular group with external trigger */
SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
80024ec: 68fb ldr r3, [r7, #12]
80024ee: 681b ldr r3, [r3, #0]
80024f0: 689a ldr r2, [r3, #8]
80024f2: 68fb ldr r3, [r7, #12]
80024f4: 681b ldr r3, [r3, #0]
80024f6: f442 1280 orr.w r2, r2, #1048576 @ 0x100000
80024fa: 609a str r2, [r3, #8]
if (tmp_hal_status == HAL_OK)
80024fc: e006 b.n 800250c <HAL_ADC_Start_DMA+0x19c>
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
80024fe: 68fb ldr r3, [r7, #12]
8002500: 2200 movs r2, #0
8002502: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (tmp_hal_status == HAL_OK)
8002506: e001 b.n 800250c <HAL_ADC_Start_DMA+0x19c>
}
}
else
{
tmp_hal_status = HAL_ERROR;
8002508: 2301 movs r3, #1
800250a: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800250c: 7dfb ldrb r3, [r7, #23]
}
800250e: 4618 mov r0, r3
8002510: 3718 adds r7, #24
8002512: 46bd mov sp, r7
8002514: bd80 pop {r7, pc}
8002516: bf00 nop
8002518: 40012400 .word 0x40012400
800251c: 40012800 .word 0x40012800
8002520: 0800288b .word 0x0800288b
8002524: 08002907 .word 0x08002907
8002528: 08002923 .word 0x08002923
0800252c <HAL_ADC_ConvCpltCallback>:
* @brief Conversion complete callback in non blocking mode
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
800252c: b480 push {r7}
800252e: b083 sub sp, #12
8002530: af00 add r7, sp, #0
8002532: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
8002534: bf00 nop
8002536: 370c adds r7, #12
8002538: 46bd mov sp, r7
800253a: bc80 pop {r7}
800253c: 4770 bx lr
0800253e <HAL_ADC_ConvHalfCpltCallback>:
* @brief Conversion DMA half-transfer callback in non blocking mode
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
800253e: b480 push {r7}
8002540: b083 sub sp, #12
8002542: af00 add r7, sp, #0
8002544: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
8002546: bf00 nop
8002548: 370c adds r7, #12
800254a: 46bd mov sp, r7
800254c: bc80 pop {r7}
800254e: 4770 bx lr
08002550 <HAL_ADC_ErrorCallback>:
* (ADC conversion with interruption or transfer by DMA)
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
8002550: b480 push {r7}
8002552: b083 sub sp, #12
8002554: af00 add r7, sp, #0
8002556: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
8002558: bf00 nop
800255a: 370c adds r7, #12
800255c: 46bd mov sp, r7
800255e: bc80 pop {r7}
8002560: 4770 bx lr
...
08002564 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8002564: b480 push {r7}
8002566: b085 sub sp, #20
8002568: af00 add r7, sp, #0
800256a: 6078 str r0, [r7, #4]
800256c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800256e: 2300 movs r3, #0
8002570: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
8002572: 2300 movs r3, #0
8002574: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8002576: 687b ldr r3, [r7, #4]
8002578: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
800257c: 2b01 cmp r3, #1
800257e: d101 bne.n 8002584 <HAL_ADC_ConfigChannel+0x20>
8002580: 2302 movs r3, #2
8002582: e0dc b.n 800273e <HAL_ADC_ConfigChannel+0x1da>
8002584: 687b ldr r3, [r7, #4]
8002586: 2201 movs r2, #1
8002588: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
800258c: 683b ldr r3, [r7, #0]
800258e: 685b ldr r3, [r3, #4]
8002590: 2b06 cmp r3, #6
8002592: d81c bhi.n 80025ce <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
8002594: 687b ldr r3, [r7, #4]
8002596: 681b ldr r3, [r3, #0]
8002598: 6b59 ldr r1, [r3, #52] @ 0x34
800259a: 683b ldr r3, [r7, #0]
800259c: 685a ldr r2, [r3, #4]
800259e: 4613 mov r3, r2
80025a0: 009b lsls r3, r3, #2
80025a2: 4413 add r3, r2
80025a4: 3b05 subs r3, #5
80025a6: 221f movs r2, #31
80025a8: fa02 f303 lsl.w r3, r2, r3
80025ac: 43db mvns r3, r3
80025ae: 4019 ands r1, r3
80025b0: 683b ldr r3, [r7, #0]
80025b2: 6818 ldr r0, [r3, #0]
80025b4: 683b ldr r3, [r7, #0]
80025b6: 685a ldr r2, [r3, #4]
80025b8: 4613 mov r3, r2
80025ba: 009b lsls r3, r3, #2
80025bc: 4413 add r3, r2
80025be: 3b05 subs r3, #5
80025c0: fa00 f203 lsl.w r2, r0, r3
80025c4: 687b ldr r3, [r7, #4]
80025c6: 681b ldr r3, [r3, #0]
80025c8: 430a orrs r2, r1
80025ca: 635a str r2, [r3, #52] @ 0x34
80025cc: e03c b.n 8002648 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
80025ce: 683b ldr r3, [r7, #0]
80025d0: 685b ldr r3, [r3, #4]
80025d2: 2b0c cmp r3, #12
80025d4: d81c bhi.n 8002610 <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
80025d6: 687b ldr r3, [r7, #4]
80025d8: 681b ldr r3, [r3, #0]
80025da: 6b19 ldr r1, [r3, #48] @ 0x30
80025dc: 683b ldr r3, [r7, #0]
80025de: 685a ldr r2, [r3, #4]
80025e0: 4613 mov r3, r2
80025e2: 009b lsls r3, r3, #2
80025e4: 4413 add r3, r2
80025e6: 3b23 subs r3, #35 @ 0x23
80025e8: 221f movs r2, #31
80025ea: fa02 f303 lsl.w r3, r2, r3
80025ee: 43db mvns r3, r3
80025f0: 4019 ands r1, r3
80025f2: 683b ldr r3, [r7, #0]
80025f4: 6818 ldr r0, [r3, #0]
80025f6: 683b ldr r3, [r7, #0]
80025f8: 685a ldr r2, [r3, #4]
80025fa: 4613 mov r3, r2
80025fc: 009b lsls r3, r3, #2
80025fe: 4413 add r3, r2
8002600: 3b23 subs r3, #35 @ 0x23
8002602: fa00 f203 lsl.w r2, r0, r3
8002606: 687b ldr r3, [r7, #4]
8002608: 681b ldr r3, [r3, #0]
800260a: 430a orrs r2, r1
800260c: 631a str r2, [r3, #48] @ 0x30
800260e: e01b b.n 8002648 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
8002610: 687b ldr r3, [r7, #4]
8002612: 681b ldr r3, [r3, #0]
8002614: 6ad9 ldr r1, [r3, #44] @ 0x2c
8002616: 683b ldr r3, [r7, #0]
8002618: 685a ldr r2, [r3, #4]
800261a: 4613 mov r3, r2
800261c: 009b lsls r3, r3, #2
800261e: 4413 add r3, r2
8002620: 3b41 subs r3, #65 @ 0x41
8002622: 221f movs r2, #31
8002624: fa02 f303 lsl.w r3, r2, r3
8002628: 43db mvns r3, r3
800262a: 4019 ands r1, r3
800262c: 683b ldr r3, [r7, #0]
800262e: 6818 ldr r0, [r3, #0]
8002630: 683b ldr r3, [r7, #0]
8002632: 685a ldr r2, [r3, #4]
8002634: 4613 mov r3, r2
8002636: 009b lsls r3, r3, #2
8002638: 4413 add r3, r2
800263a: 3b41 subs r3, #65 @ 0x41
800263c: fa00 f203 lsl.w r2, r0, r3
8002640: 687b ldr r3, [r7, #4]
8002642: 681b ldr r3, [r3, #0]
8002644: 430a orrs r2, r1
8002646: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8002648: 683b ldr r3, [r7, #0]
800264a: 681b ldr r3, [r3, #0]
800264c: 2b09 cmp r3, #9
800264e: d91c bls.n 800268a <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
8002650: 687b ldr r3, [r7, #4]
8002652: 681b ldr r3, [r3, #0]
8002654: 68d9 ldr r1, [r3, #12]
8002656: 683b ldr r3, [r7, #0]
8002658: 681a ldr r2, [r3, #0]
800265a: 4613 mov r3, r2
800265c: 005b lsls r3, r3, #1
800265e: 4413 add r3, r2
8002660: 3b1e subs r3, #30
8002662: 2207 movs r2, #7
8002664: fa02 f303 lsl.w r3, r2, r3
8002668: 43db mvns r3, r3
800266a: 4019 ands r1, r3
800266c: 683b ldr r3, [r7, #0]
800266e: 6898 ldr r0, [r3, #8]
8002670: 683b ldr r3, [r7, #0]
8002672: 681a ldr r2, [r3, #0]
8002674: 4613 mov r3, r2
8002676: 005b lsls r3, r3, #1
8002678: 4413 add r3, r2
800267a: 3b1e subs r3, #30
800267c: fa00 f203 lsl.w r2, r0, r3
8002680: 687b ldr r3, [r7, #4]
8002682: 681b ldr r3, [r3, #0]
8002684: 430a orrs r2, r1
8002686: 60da str r2, [r3, #12]
8002688: e019 b.n 80026be <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
800268a: 687b ldr r3, [r7, #4]
800268c: 681b ldr r3, [r3, #0]
800268e: 6919 ldr r1, [r3, #16]
8002690: 683b ldr r3, [r7, #0]
8002692: 681a ldr r2, [r3, #0]
8002694: 4613 mov r3, r2
8002696: 005b lsls r3, r3, #1
8002698: 4413 add r3, r2
800269a: 2207 movs r2, #7
800269c: fa02 f303 lsl.w r3, r2, r3
80026a0: 43db mvns r3, r3
80026a2: 4019 ands r1, r3
80026a4: 683b ldr r3, [r7, #0]
80026a6: 6898 ldr r0, [r3, #8]
80026a8: 683b ldr r3, [r7, #0]
80026aa: 681a ldr r2, [r3, #0]
80026ac: 4613 mov r3, r2
80026ae: 005b lsls r3, r3, #1
80026b0: 4413 add r3, r2
80026b2: fa00 f203 lsl.w r2, r0, r3
80026b6: 687b ldr r3, [r7, #4]
80026b8: 681b ldr r3, [r3, #0]
80026ba: 430a orrs r2, r1
80026bc: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80026be: 683b ldr r3, [r7, #0]
80026c0: 681b ldr r3, [r3, #0]
80026c2: 2b10 cmp r3, #16
80026c4: d003 beq.n 80026ce <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
80026c6: 683b ldr r3, [r7, #0]
80026c8: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80026ca: 2b11 cmp r3, #17
80026cc: d132 bne.n 8002734 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
80026ce: 687b ldr r3, [r7, #4]
80026d0: 681b ldr r3, [r3, #0]
80026d2: 4a1d ldr r2, [pc, #116] @ (8002748 <HAL_ADC_ConfigChannel+0x1e4>)
80026d4: 4293 cmp r3, r2
80026d6: d125 bne.n 8002724 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
80026d8: 687b ldr r3, [r7, #4]
80026da: 681b ldr r3, [r3, #0]
80026dc: 689b ldr r3, [r3, #8]
80026de: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80026e2: 2b00 cmp r3, #0
80026e4: d126 bne.n 8002734 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
80026e6: 687b ldr r3, [r7, #4]
80026e8: 681b ldr r3, [r3, #0]
80026ea: 689a ldr r2, [r3, #8]
80026ec: 687b ldr r3, [r7, #4]
80026ee: 681b ldr r3, [r3, #0]
80026f0: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
80026f4: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
80026f6: 683b ldr r3, [r7, #0]
80026f8: 681b ldr r3, [r3, #0]
80026fa: 2b10 cmp r3, #16
80026fc: d11a bne.n 8002734 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
80026fe: 4b13 ldr r3, [pc, #76] @ (800274c <HAL_ADC_ConfigChannel+0x1e8>)
8002700: 681b ldr r3, [r3, #0]
8002702: 4a13 ldr r2, [pc, #76] @ (8002750 <HAL_ADC_ConfigChannel+0x1ec>)
8002704: fba2 2303 umull r2, r3, r2, r3
8002708: 0c9a lsrs r2, r3, #18
800270a: 4613 mov r3, r2
800270c: 009b lsls r3, r3, #2
800270e: 4413 add r3, r2
8002710: 005b lsls r3, r3, #1
8002712: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8002714: e002 b.n 800271c <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
8002716: 68bb ldr r3, [r7, #8]
8002718: 3b01 subs r3, #1
800271a: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
800271c: 68bb ldr r3, [r7, #8]
800271e: 2b00 cmp r3, #0
8002720: d1f9 bne.n 8002716 <HAL_ADC_ConfigChannel+0x1b2>
8002722: e007 b.n 8002734 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002724: 687b ldr r3, [r7, #4]
8002726: 6a9b ldr r3, [r3, #40] @ 0x28
8002728: f043 0220 orr.w r2, r3, #32
800272c: 687b ldr r3, [r7, #4]
800272e: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8002730: 2301 movs r3, #1
8002732: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002734: 687b ldr r3, [r7, #4]
8002736: 2200 movs r2, #0
8002738: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
800273c: 7bfb ldrb r3, [r7, #15]
}
800273e: 4618 mov r0, r3
8002740: 3714 adds r7, #20
8002742: 46bd mov sp, r7
8002744: bc80 pop {r7}
8002746: 4770 bx lr
8002748: 40012400 .word 0x40012400
800274c: 20000004 .word 0x20000004
8002750: 431bde83 .word 0x431bde83
08002754 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
8002754: b580 push {r7, lr}
8002756: b084 sub sp, #16
8002758: af00 add r7, sp, #0
800275a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800275c: 2300 movs r3, #0
800275e: 60fb str r3, [r7, #12]
__IO uint32_t wait_loop_index = 0U;
8002760: 2300 movs r3, #0
8002762: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (ADC_IS_ENABLE(hadc) == RESET)
8002764: 687b ldr r3, [r7, #4]
8002766: 681b ldr r3, [r3, #0]
8002768: 689b ldr r3, [r3, #8]
800276a: f003 0301 and.w r3, r3, #1
800276e: 2b01 cmp r3, #1
8002770: d040 beq.n 80027f4 <ADC_Enable+0xa0>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8002772: 687b ldr r3, [r7, #4]
8002774: 681b ldr r3, [r3, #0]
8002776: 689a ldr r2, [r3, #8]
8002778: 687b ldr r3, [r7, #4]
800277a: 681b ldr r3, [r3, #0]
800277c: f042 0201 orr.w r2, r2, #1
8002780: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
8002782: 4b1f ldr r3, [pc, #124] @ (8002800 <ADC_Enable+0xac>)
8002784: 681b ldr r3, [r3, #0]
8002786: 4a1f ldr r2, [pc, #124] @ (8002804 <ADC_Enable+0xb0>)
8002788: fba2 2303 umull r2, r3, r2, r3
800278c: 0c9b lsrs r3, r3, #18
800278e: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8002790: e002 b.n 8002798 <ADC_Enable+0x44>
{
wait_loop_index--;
8002792: 68bb ldr r3, [r7, #8]
8002794: 3b01 subs r3, #1
8002796: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8002798: 68bb ldr r3, [r7, #8]
800279a: 2b00 cmp r3, #0
800279c: d1f9 bne.n 8002792 <ADC_Enable+0x3e>
}
/* Get tick count */
tickstart = HAL_GetTick();
800279e: f7ff fd05 bl 80021ac <HAL_GetTick>
80027a2: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively enabled */
while(ADC_IS_ENABLE(hadc) == RESET)
80027a4: e01f b.n 80027e6 <ADC_Enable+0x92>
{
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
80027a6: f7ff fd01 bl 80021ac <HAL_GetTick>
80027aa: 4602 mov r2, r0
80027ac: 68fb ldr r3, [r7, #12]
80027ae: 1ad3 subs r3, r2, r3
80027b0: 2b02 cmp r3, #2
80027b2: d918 bls.n 80027e6 <ADC_Enable+0x92>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) == RESET)
80027b4: 687b ldr r3, [r7, #4]
80027b6: 681b ldr r3, [r3, #0]
80027b8: 689b ldr r3, [r3, #8]
80027ba: f003 0301 and.w r3, r3, #1
80027be: 2b01 cmp r3, #1
80027c0: d011 beq.n 80027e6 <ADC_Enable+0x92>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80027c2: 687b ldr r3, [r7, #4]
80027c4: 6a9b ldr r3, [r3, #40] @ 0x28
80027c6: f043 0210 orr.w r2, r3, #16
80027ca: 687b ldr r3, [r7, #4]
80027cc: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80027ce: 687b ldr r3, [r7, #4]
80027d0: 6adb ldr r3, [r3, #44] @ 0x2c
80027d2: f043 0201 orr.w r2, r3, #1
80027d6: 687b ldr r3, [r7, #4]
80027d8: 62da str r2, [r3, #44] @ 0x2c
/* Process unlocked */
__HAL_UNLOCK(hadc);
80027da: 687b ldr r3, [r7, #4]
80027dc: 2200 movs r2, #0
80027de: f883 2024 strb.w r2, [r3, #36] @ 0x24
return HAL_ERROR;
80027e2: 2301 movs r3, #1
80027e4: e007 b.n 80027f6 <ADC_Enable+0xa2>
while(ADC_IS_ENABLE(hadc) == RESET)
80027e6: 687b ldr r3, [r7, #4]
80027e8: 681b ldr r3, [r3, #0]
80027ea: 689b ldr r3, [r3, #8]
80027ec: f003 0301 and.w r3, r3, #1
80027f0: 2b01 cmp r3, #1
80027f2: d1d8 bne.n 80027a6 <ADC_Enable+0x52>
}
}
}
/* Return HAL status */
return HAL_OK;
80027f4: 2300 movs r3, #0
}
80027f6: 4618 mov r0, r3
80027f8: 3710 adds r7, #16
80027fa: 46bd mov sp, r7
80027fc: bd80 pop {r7, pc}
80027fe: bf00 nop
8002800: 20000004 .word 0x20000004
8002804: 431bde83 .word 0x431bde83
08002808 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8002808: b580 push {r7, lr}
800280a: b084 sub sp, #16
800280c: af00 add r7, sp, #0
800280e: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8002810: 2300 movs r3, #0
8002812: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
8002814: 687b ldr r3, [r7, #4]
8002816: 681b ldr r3, [r3, #0]
8002818: 689b ldr r3, [r3, #8]
800281a: f003 0301 and.w r3, r3, #1
800281e: 2b01 cmp r3, #1
8002820: d12e bne.n 8002880 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8002822: 687b ldr r3, [r7, #4]
8002824: 681b ldr r3, [r3, #0]
8002826: 689a ldr r2, [r3, #8]
8002828: 687b ldr r3, [r7, #4]
800282a: 681b ldr r3, [r3, #0]
800282c: f022 0201 bic.w r2, r2, #1
8002830: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
8002832: f7ff fcbb bl 80021ac <HAL_GetTick>
8002836: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8002838: e01b b.n 8002872 <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
800283a: f7ff fcb7 bl 80021ac <HAL_GetTick>
800283e: 4602 mov r2, r0
8002840: 68fb ldr r3, [r7, #12]
8002842: 1ad3 subs r3, r2, r3
8002844: 2b02 cmp r3, #2
8002846: d914 bls.n 8002872 <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
8002848: 687b ldr r3, [r7, #4]
800284a: 681b ldr r3, [r3, #0]
800284c: 689b ldr r3, [r3, #8]
800284e: f003 0301 and.w r3, r3, #1
8002852: 2b01 cmp r3, #1
8002854: d10d bne.n 8002872 <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002856: 687b ldr r3, [r7, #4]
8002858: 6a9b ldr r3, [r3, #40] @ 0x28
800285a: f043 0210 orr.w r2, r3, #16
800285e: 687b ldr r3, [r7, #4]
8002860: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002862: 687b ldr r3, [r7, #4]
8002864: 6adb ldr r3, [r3, #44] @ 0x2c
8002866: f043 0201 orr.w r2, r3, #1
800286a: 687b ldr r3, [r7, #4]
800286c: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
800286e: 2301 movs r3, #1
8002870: e007 b.n 8002882 <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
8002872: 687b ldr r3, [r7, #4]
8002874: 681b ldr r3, [r3, #0]
8002876: 689b ldr r3, [r3, #8]
8002878: f003 0301 and.w r3, r3, #1
800287c: 2b01 cmp r3, #1
800287e: d0dc beq.n 800283a <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
8002880: 2300 movs r3, #0
}
8002882: 4618 mov r0, r3
8002884: 3710 adds r7, #16
8002886: 46bd mov sp, r7
8002888: bd80 pop {r7, pc}
0800288a <ADC_DMAConvCplt>:
* @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
800288a: b580 push {r7, lr}
800288c: b084 sub sp, #16
800288e: af00 add r7, sp, #0
8002890: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
8002892: 687b ldr r3, [r7, #4]
8002894: 6a5b ldr r3, [r3, #36] @ 0x24
8002896: 60fb str r3, [r7, #12]
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
8002898: 68fb ldr r3, [r7, #12]
800289a: 6a9b ldr r3, [r3, #40] @ 0x28
800289c: f003 0350 and.w r3, r3, #80 @ 0x50
80028a0: 2b00 cmp r3, #0
80028a2: d127 bne.n 80028f4 <ADC_DMAConvCplt+0x6a>
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
80028a4: 68fb ldr r3, [r7, #12]
80028a6: 6a9b ldr r3, [r3, #40] @ 0x28
80028a8: f443 7200 orr.w r2, r3, #512 @ 0x200
80028ac: 68fb ldr r3, [r7, #12]
80028ae: 629a str r2, [r3, #40] @ 0x28
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F1 devices, in case of sequencer enabled */
/* (several ranks selected), end of conversion flag is raised */
/* at the end of the sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
80028b0: 68fb ldr r3, [r7, #12]
80028b2: 681b ldr r3, [r3, #0]
80028b4: 689b ldr r3, [r3, #8]
80028b6: f403 2360 and.w r3, r3, #917504 @ 0xe0000
80028ba: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000
80028be: d115 bne.n 80028ec <ADC_DMAConvCplt+0x62>
(hadc->Init.ContinuousConvMode == DISABLE) )
80028c0: 68fb ldr r3, [r7, #12]
80028c2: 7b1b ldrb r3, [r3, #12]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
80028c4: 2b00 cmp r3, #0
80028c6: d111 bne.n 80028ec <ADC_DMAConvCplt+0x62>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80028c8: 68fb ldr r3, [r7, #12]
80028ca: 6a9b ldr r3, [r3, #40] @ 0x28
80028cc: f423 7280 bic.w r2, r3, #256 @ 0x100
80028d0: 68fb ldr r3, [r7, #12]
80028d2: 629a str r2, [r3, #40] @ 0x28
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
80028d4: 68fb ldr r3, [r7, #12]
80028d6: 6a9b ldr r3, [r3, #40] @ 0x28
80028d8: f403 5380 and.w r3, r3, #4096 @ 0x1000
80028dc: 2b00 cmp r3, #0
80028de: d105 bne.n 80028ec <ADC_DMAConvCplt+0x62>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80028e0: 68fb ldr r3, [r7, #12]
80028e2: 6a9b ldr r3, [r3, #40] @ 0x28
80028e4: f043 0201 orr.w r2, r3, #1
80028e8: 68fb ldr r3, [r7, #12]
80028ea: 629a str r2, [r3, #40] @ 0x28
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
80028ec: 68f8 ldr r0, [r7, #12]
80028ee: f7ff fe1d bl 800252c <HAL_ADC_ConvCpltCallback>
else
{
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
80028f2: e004 b.n 80028fe <ADC_DMAConvCplt+0x74>
hadc->DMA_Handle->XferErrorCallback(hdma);
80028f4: 68fb ldr r3, [r7, #12]
80028f6: 6a1b ldr r3, [r3, #32]
80028f8: 6b1b ldr r3, [r3, #48] @ 0x30
80028fa: 6878 ldr r0, [r7, #4]
80028fc: 4798 blx r3
}
80028fe: bf00 nop
8002900: 3710 adds r7, #16
8002902: 46bd mov sp, r7
8002904: bd80 pop {r7, pc}
08002906 <ADC_DMAHalfConvCplt>:
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
8002906: b580 push {r7, lr}
8002908: b084 sub sp, #16
800290a: af00 add r7, sp, #0
800290c: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
800290e: 687b ldr r3, [r7, #4]
8002910: 6a5b ldr r3, [r3, #36] @ 0x24
8002912: 60fb str r3, [r7, #12]
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc);
8002914: 68f8 ldr r0, [r7, #12]
8002916: f7ff fe12 bl 800253e <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
800291a: bf00 nop
800291c: 3710 adds r7, #16
800291e: 46bd mov sp, r7
8002920: bd80 pop {r7, pc}
08002922 <ADC_DMAError>:
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
8002922: b580 push {r7, lr}
8002924: b084 sub sp, #16
8002926: af00 add r7, sp, #0
8002928: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
800292a: 687b ldr r3, [r7, #4]
800292c: 6a5b ldr r3, [r3, #36] @ 0x24
800292e: 60fb str r3, [r7, #12]
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
8002930: 68fb ldr r3, [r7, #12]
8002932: 6a9b ldr r3, [r3, #40] @ 0x28
8002934: f043 0240 orr.w r2, r3, #64 @ 0x40
8002938: 68fb ldr r3, [r7, #12]
800293a: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to DMA error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
800293c: 68fb ldr r3, [r7, #12]
800293e: 6adb ldr r3, [r3, #44] @ 0x2c
8002940: f043 0204 orr.w r2, r3, #4
8002944: 68fb ldr r3, [r7, #12]
8002946: 62da str r2, [r3, #44] @ 0x2c
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8002948: 68f8 ldr r0, [r7, #12]
800294a: f7ff fe01 bl 8002550 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
800294e: bf00 nop
8002950: 3710 adds r7, #16
8002952: 46bd mov sp, r7
8002954: bd80 pop {r7, pc}
...
08002958 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002958: b480 push {r7}
800295a: b085 sub sp, #20
800295c: af00 add r7, sp, #0
800295e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002960: 687b ldr r3, [r7, #4]
8002962: f003 0307 and.w r3, r3, #7
8002966: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002968: 4b0c ldr r3, [pc, #48] @ (800299c <__NVIC_SetPriorityGrouping+0x44>)
800296a: 68db ldr r3, [r3, #12]
800296c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800296e: 68ba ldr r2, [r7, #8]
8002970: f64f 03ff movw r3, #63743 @ 0xf8ff
8002974: 4013 ands r3, r2
8002976: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8002978: 68fb ldr r3, [r7, #12]
800297a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800297c: 68bb ldr r3, [r7, #8]
800297e: 4313 orrs r3, r2
reg_value = (reg_value |
8002980: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8002984: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002988: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800298a: 4a04 ldr r2, [pc, #16] @ (800299c <__NVIC_SetPriorityGrouping+0x44>)
800298c: 68bb ldr r3, [r7, #8]
800298e: 60d3 str r3, [r2, #12]
}
8002990: bf00 nop
8002992: 3714 adds r7, #20
8002994: 46bd mov sp, r7
8002996: bc80 pop {r7}
8002998: 4770 bx lr
800299a: bf00 nop
800299c: e000ed00 .word 0xe000ed00
080029a0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80029a0: b480 push {r7}
80029a2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80029a4: 4b04 ldr r3, [pc, #16] @ (80029b8 <__NVIC_GetPriorityGrouping+0x18>)
80029a6: 68db ldr r3, [r3, #12]
80029a8: 0a1b lsrs r3, r3, #8
80029aa: f003 0307 and.w r3, r3, #7
}
80029ae: 4618 mov r0, r3
80029b0: 46bd mov sp, r7
80029b2: bc80 pop {r7}
80029b4: 4770 bx lr
80029b6: bf00 nop
80029b8: e000ed00 .word 0xe000ed00
080029bc <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80029bc: b480 push {r7}
80029be: b083 sub sp, #12
80029c0: af00 add r7, sp, #0
80029c2: 4603 mov r3, r0
80029c4: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80029c6: f997 3007 ldrsb.w r3, [r7, #7]
80029ca: 2b00 cmp r3, #0
80029cc: db0b blt.n 80029e6 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80029ce: 79fb ldrb r3, [r7, #7]
80029d0: f003 021f and.w r2, r3, #31
80029d4: 4906 ldr r1, [pc, #24] @ (80029f0 <__NVIC_EnableIRQ+0x34>)
80029d6: f997 3007 ldrsb.w r3, [r7, #7]
80029da: 095b lsrs r3, r3, #5
80029dc: 2001 movs r0, #1
80029de: fa00 f202 lsl.w r2, r0, r2
80029e2: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80029e6: bf00 nop
80029e8: 370c adds r7, #12
80029ea: 46bd mov sp, r7
80029ec: bc80 pop {r7}
80029ee: 4770 bx lr
80029f0: e000e100 .word 0xe000e100
080029f4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80029f4: b480 push {r7}
80029f6: b083 sub sp, #12
80029f8: af00 add r7, sp, #0
80029fa: 4603 mov r3, r0
80029fc: 6039 str r1, [r7, #0]
80029fe: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002a00: f997 3007 ldrsb.w r3, [r7, #7]
8002a04: 2b00 cmp r3, #0
8002a06: db0a blt.n 8002a1e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002a08: 683b ldr r3, [r7, #0]
8002a0a: b2da uxtb r2, r3
8002a0c: 490c ldr r1, [pc, #48] @ (8002a40 <__NVIC_SetPriority+0x4c>)
8002a0e: f997 3007 ldrsb.w r3, [r7, #7]
8002a12: 0112 lsls r2, r2, #4
8002a14: b2d2 uxtb r2, r2
8002a16: 440b add r3, r1
8002a18: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8002a1c: e00a b.n 8002a34 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002a1e: 683b ldr r3, [r7, #0]
8002a20: b2da uxtb r2, r3
8002a22: 4908 ldr r1, [pc, #32] @ (8002a44 <__NVIC_SetPriority+0x50>)
8002a24: 79fb ldrb r3, [r7, #7]
8002a26: f003 030f and.w r3, r3, #15
8002a2a: 3b04 subs r3, #4
8002a2c: 0112 lsls r2, r2, #4
8002a2e: b2d2 uxtb r2, r2
8002a30: 440b add r3, r1
8002a32: 761a strb r2, [r3, #24]
}
8002a34: bf00 nop
8002a36: 370c adds r7, #12
8002a38: 46bd mov sp, r7
8002a3a: bc80 pop {r7}
8002a3c: 4770 bx lr
8002a3e: bf00 nop
8002a40: e000e100 .word 0xe000e100
8002a44: e000ed00 .word 0xe000ed00
08002a48 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002a48: b480 push {r7}
8002a4a: b089 sub sp, #36 @ 0x24
8002a4c: af00 add r7, sp, #0
8002a4e: 60f8 str r0, [r7, #12]
8002a50: 60b9 str r1, [r7, #8]
8002a52: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002a54: 68fb ldr r3, [r7, #12]
8002a56: f003 0307 and.w r3, r3, #7
8002a5a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8002a5c: 69fb ldr r3, [r7, #28]
8002a5e: f1c3 0307 rsb r3, r3, #7
8002a62: 2b04 cmp r3, #4
8002a64: bf28 it cs
8002a66: 2304 movcs r3, #4
8002a68: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8002a6a: 69fb ldr r3, [r7, #28]
8002a6c: 3304 adds r3, #4
8002a6e: 2b06 cmp r3, #6
8002a70: d902 bls.n 8002a78 <NVIC_EncodePriority+0x30>
8002a72: 69fb ldr r3, [r7, #28]
8002a74: 3b03 subs r3, #3
8002a76: e000 b.n 8002a7a <NVIC_EncodePriority+0x32>
8002a78: 2300 movs r3, #0
8002a7a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002a7c: f04f 32ff mov.w r2, #4294967295
8002a80: 69bb ldr r3, [r7, #24]
8002a82: fa02 f303 lsl.w r3, r2, r3
8002a86: 43da mvns r2, r3
8002a88: 68bb ldr r3, [r7, #8]
8002a8a: 401a ands r2, r3
8002a8c: 697b ldr r3, [r7, #20]
8002a8e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002a90: f04f 31ff mov.w r1, #4294967295
8002a94: 697b ldr r3, [r7, #20]
8002a96: fa01 f303 lsl.w r3, r1, r3
8002a9a: 43d9 mvns r1, r3
8002a9c: 687b ldr r3, [r7, #4]
8002a9e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002aa0: 4313 orrs r3, r2
);
}
8002aa2: 4618 mov r0, r3
8002aa4: 3724 adds r7, #36 @ 0x24
8002aa6: 46bd mov sp, r7
8002aa8: bc80 pop {r7}
8002aaa: 4770 bx lr
08002aac <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002aac: b580 push {r7, lr}
8002aae: b082 sub sp, #8
8002ab0: af00 add r7, sp, #0
8002ab2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002ab4: 687b ldr r3, [r7, #4]
8002ab6: 3b01 subs r3, #1
8002ab8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8002abc: d301 bcc.n 8002ac2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8002abe: 2301 movs r3, #1
8002ac0: e00f b.n 8002ae2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002ac2: 4a0a ldr r2, [pc, #40] @ (8002aec <SysTick_Config+0x40>)
8002ac4: 687b ldr r3, [r7, #4]
8002ac6: 3b01 subs r3, #1
8002ac8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8002aca: 210f movs r1, #15
8002acc: f04f 30ff mov.w r0, #4294967295
8002ad0: f7ff ff90 bl 80029f4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002ad4: 4b05 ldr r3, [pc, #20] @ (8002aec <SysTick_Config+0x40>)
8002ad6: 2200 movs r2, #0
8002ad8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002ada: 4b04 ldr r3, [pc, #16] @ (8002aec <SysTick_Config+0x40>)
8002adc: 2207 movs r2, #7
8002ade: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002ae0: 2300 movs r3, #0
}
8002ae2: 4618 mov r0, r3
8002ae4: 3708 adds r7, #8
8002ae6: 46bd mov sp, r7
8002ae8: bd80 pop {r7, pc}
8002aea: bf00 nop
8002aec: e000e010 .word 0xe000e010
08002af0 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002af0: b580 push {r7, lr}
8002af2: b082 sub sp, #8
8002af4: af00 add r7, sp, #0
8002af6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8002af8: 6878 ldr r0, [r7, #4]
8002afa: f7ff ff2d bl 8002958 <__NVIC_SetPriorityGrouping>
}
8002afe: bf00 nop
8002b00: 3708 adds r7, #8
8002b02: 46bd mov sp, r7
8002b04: bd80 pop {r7, pc}
08002b06 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002b06: b580 push {r7, lr}
8002b08: b086 sub sp, #24
8002b0a: af00 add r7, sp, #0
8002b0c: 4603 mov r3, r0
8002b0e: 60b9 str r1, [r7, #8]
8002b10: 607a str r2, [r7, #4]
8002b12: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8002b14: 2300 movs r3, #0
8002b16: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8002b18: f7ff ff42 bl 80029a0 <__NVIC_GetPriorityGrouping>
8002b1c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8002b1e: 687a ldr r2, [r7, #4]
8002b20: 68b9 ldr r1, [r7, #8]
8002b22: 6978 ldr r0, [r7, #20]
8002b24: f7ff ff90 bl 8002a48 <NVIC_EncodePriority>
8002b28: 4602 mov r2, r0
8002b2a: f997 300f ldrsb.w r3, [r7, #15]
8002b2e: 4611 mov r1, r2
8002b30: 4618 mov r0, r3
8002b32: f7ff ff5f bl 80029f4 <__NVIC_SetPriority>
}
8002b36: bf00 nop
8002b38: 3718 adds r7, #24
8002b3a: 46bd mov sp, r7
8002b3c: bd80 pop {r7, pc}
08002b3e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002b3e: b580 push {r7, lr}
8002b40: b082 sub sp, #8
8002b42: af00 add r7, sp, #0
8002b44: 4603 mov r3, r0
8002b46: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002b48: f997 3007 ldrsb.w r3, [r7, #7]
8002b4c: 4618 mov r0, r3
8002b4e: f7ff ff35 bl 80029bc <__NVIC_EnableIRQ>
}
8002b52: bf00 nop
8002b54: 3708 adds r7, #8
8002b56: 46bd mov sp, r7
8002b58: bd80 pop {r7, pc}
08002b5a <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8002b5a: b580 push {r7, lr}
8002b5c: b082 sub sp, #8
8002b5e: af00 add r7, sp, #0
8002b60: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002b62: 6878 ldr r0, [r7, #4]
8002b64: f7ff ffa2 bl 8002aac <SysTick_Config>
8002b68: 4603 mov r3, r0
}
8002b6a: 4618 mov r0, r3
8002b6c: 3708 adds r7, #8
8002b6e: 46bd mov sp, r7
8002b70: bd80 pop {r7, pc}
08002b72 <HAL_SYSTICK_IRQHandler>:
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
8002b72: b580 push {r7, lr}
8002b74: af00 add r7, sp, #0
HAL_SYSTICK_Callback();
8002b76: f7fe fa8f bl 8001098 <HAL_SYSTICK_Callback>
}
8002b7a: bf00 nop
8002b7c: bd80 pop {r7, pc}
...
08002b80 <HAL_DMA_Init>:
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8002b80: b480 push {r7}
8002b82: b085 sub sp, #20
8002b84: af00 add r7, sp, #0
8002b86: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
8002b88: 2300 movs r3, #0
8002b8a: 60fb str r3, [r7, #12]
/* Check the DMA handle allocation */
if(hdma == NULL)
8002b8c: 687b ldr r3, [r7, #4]
8002b8e: 2b00 cmp r3, #0
8002b90: d101 bne.n 8002b96 <HAL_DMA_Init+0x16>
{
return HAL_ERROR;
8002b92: 2301 movs r3, #1
8002b94: e043 b.n 8002c1e <HAL_DMA_Init+0x9e>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
8002b96: 687b ldr r3, [r7, #4]
8002b98: 681b ldr r3, [r3, #0]
8002b9a: 461a mov r2, r3
8002b9c: 4b22 ldr r3, [pc, #136] @ (8002c28 <HAL_DMA_Init+0xa8>)
8002b9e: 4413 add r3, r2
8002ba0: 4a22 ldr r2, [pc, #136] @ (8002c2c <HAL_DMA_Init+0xac>)
8002ba2: fba2 2303 umull r2, r3, r2, r3
8002ba6: 091b lsrs r3, r3, #4
8002ba8: 009a lsls r2, r3, #2
8002baa: 687b ldr r3, [r7, #4]
8002bac: 641a str r2, [r3, #64] @ 0x40
hdma->DmaBaseAddress = DMA1;
8002bae: 687b ldr r3, [r7, #4]
8002bb0: 4a1f ldr r2, [pc, #124] @ (8002c30 <HAL_DMA_Init+0xb0>)
8002bb2: 63da str r2, [r3, #60] @ 0x3c
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8002bb4: 687b ldr r3, [r7, #4]
8002bb6: 2202 movs r2, #2
8002bb8: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Get the CR register value */
tmp = hdma->Instance->CCR;
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 681b ldr r3, [r3, #0]
8002bc0: 681b ldr r3, [r3, #0]
8002bc2: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8002bc4: 68fb ldr r3, [r7, #12]
8002bc6: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8002bca: f023 0330 bic.w r3, r3, #48 @ 0x30
8002bce: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
8002bd0: 687b ldr r3, [r7, #4]
8002bd2: 685a ldr r2, [r3, #4]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8002bd4: 687b ldr r3, [r7, #4]
8002bd6: 689b ldr r3, [r3, #8]
tmp |= hdma->Init.Direction |
8002bd8: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8002bda: 687b ldr r3, [r7, #4]
8002bdc: 68db ldr r3, [r3, #12]
8002bde: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8002be0: 687b ldr r3, [r7, #4]
8002be2: 691b ldr r3, [r3, #16]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8002be4: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8002be6: 687b ldr r3, [r7, #4]
8002be8: 695b ldr r3, [r3, #20]
8002bea: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8002bec: 687b ldr r3, [r7, #4]
8002bee: 699b ldr r3, [r3, #24]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8002bf0: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8002bf2: 687b ldr r3, [r7, #4]
8002bf4: 69db ldr r3, [r3, #28]
8002bf6: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8002bf8: 68fa ldr r2, [r7, #12]
8002bfa: 4313 orrs r3, r2
8002bfc: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
8002bfe: 687b ldr r3, [r7, #4]
8002c00: 681b ldr r3, [r3, #0]
8002c02: 68fa ldr r2, [r7, #12]
8002c04: 601a str r2, [r3, #0]
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002c06: 687b ldr r3, [r7, #4]
8002c08: 2200 movs r2, #0
8002c0a: 639a str r2, [r3, #56] @ 0x38
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8002c0c: 687b ldr r3, [r7, #4]
8002c0e: 2201 movs r2, #1
8002c10: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
8002c14: 687b ldr r3, [r7, #4]
8002c16: 2200 movs r2, #0
8002c18: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
8002c1c: 2300 movs r3, #0
}
8002c1e: 4618 mov r0, r3
8002c20: 3714 adds r7, #20
8002c22: 46bd mov sp, r7
8002c24: bc80 pop {r7}
8002c26: 4770 bx lr
8002c28: bffdfff8 .word 0xbffdfff8
8002c2c: cccccccd .word 0xcccccccd
8002c30: 40020000 .word 0x40020000
08002c34 <HAL_DMA_Start_IT>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8002c34: b580 push {r7, lr}
8002c36: b086 sub sp, #24
8002c38: af00 add r7, sp, #0
8002c3a: 60f8 str r0, [r7, #12]
8002c3c: 60b9 str r1, [r7, #8]
8002c3e: 607a str r2, [r7, #4]
8002c40: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8002c42: 2300 movs r3, #0
8002c44: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8002c46: 68fb ldr r3, [r7, #12]
8002c48: f893 3020 ldrb.w r3, [r3, #32]
8002c4c: 2b01 cmp r3, #1
8002c4e: d101 bne.n 8002c54 <HAL_DMA_Start_IT+0x20>
8002c50: 2302 movs r3, #2
8002c52: e04b b.n 8002cec <HAL_DMA_Start_IT+0xb8>
8002c54: 68fb ldr r3, [r7, #12]
8002c56: 2201 movs r2, #1
8002c58: f883 2020 strb.w r2, [r3, #32]
if(HAL_DMA_STATE_READY == hdma->State)
8002c5c: 68fb ldr r3, [r7, #12]
8002c5e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8002c62: b2db uxtb r3, r3
8002c64: 2b01 cmp r3, #1
8002c66: d13a bne.n 8002cde <HAL_DMA_Start_IT+0xaa>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8002c68: 68fb ldr r3, [r7, #12]
8002c6a: 2202 movs r2, #2
8002c6c: f883 2021 strb.w r2, [r3, #33] @ 0x21
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002c70: 68fb ldr r3, [r7, #12]
8002c72: 2200 movs r2, #0
8002c74: 639a str r2, [r3, #56] @ 0x38
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8002c76: 68fb ldr r3, [r7, #12]
8002c78: 681b ldr r3, [r3, #0]
8002c7a: 681a ldr r2, [r3, #0]
8002c7c: 68fb ldr r3, [r7, #12]
8002c7e: 681b ldr r3, [r3, #0]
8002c80: f022 0201 bic.w r2, r2, #1
8002c84: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8002c86: 683b ldr r3, [r7, #0]
8002c88: 687a ldr r2, [r7, #4]
8002c8a: 68b9 ldr r1, [r7, #8]
8002c8c: 68f8 ldr r0, [r7, #12]
8002c8e: f000 f937 bl 8002f00 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback)
8002c92: 68fb ldr r3, [r7, #12]
8002c94: 6adb ldr r3, [r3, #44] @ 0x2c
8002c96: 2b00 cmp r3, #0
8002c98: d008 beq.n 8002cac <HAL_DMA_Start_IT+0x78>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8002c9a: 68fb ldr r3, [r7, #12]
8002c9c: 681b ldr r3, [r3, #0]
8002c9e: 681a ldr r2, [r3, #0]
8002ca0: 68fb ldr r3, [r7, #12]
8002ca2: 681b ldr r3, [r3, #0]
8002ca4: f042 020e orr.w r2, r2, #14
8002ca8: 601a str r2, [r3, #0]
8002caa: e00f b.n 8002ccc <HAL_DMA_Start_IT+0x98>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8002cac: 68fb ldr r3, [r7, #12]
8002cae: 681b ldr r3, [r3, #0]
8002cb0: 681a ldr r2, [r3, #0]
8002cb2: 68fb ldr r3, [r7, #12]
8002cb4: 681b ldr r3, [r3, #0]
8002cb6: f022 0204 bic.w r2, r2, #4
8002cba: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8002cbc: 68fb ldr r3, [r7, #12]
8002cbe: 681b ldr r3, [r3, #0]
8002cc0: 681a ldr r2, [r3, #0]
8002cc2: 68fb ldr r3, [r7, #12]
8002cc4: 681b ldr r3, [r3, #0]
8002cc6: f042 020a orr.w r2, r2, #10
8002cca: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8002ccc: 68fb ldr r3, [r7, #12]
8002cce: 681b ldr r3, [r3, #0]
8002cd0: 681a ldr r2, [r3, #0]
8002cd2: 68fb ldr r3, [r7, #12]
8002cd4: 681b ldr r3, [r3, #0]
8002cd6: f042 0201 orr.w r2, r2, #1
8002cda: 601a str r2, [r3, #0]
8002cdc: e005 b.n 8002cea <HAL_DMA_Start_IT+0xb6>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002cde: 68fb ldr r3, [r7, #12]
8002ce0: 2200 movs r2, #0
8002ce2: f883 2020 strb.w r2, [r3, #32]
/* Remain BUSY */
status = HAL_BUSY;
8002ce6: 2302 movs r3, #2
8002ce8: 75fb strb r3, [r7, #23]
}
return status;
8002cea: 7dfb ldrb r3, [r7, #23]
}
8002cec: 4618 mov r0, r3
8002cee: 3718 adds r7, #24
8002cf0: 46bd mov sp, r7
8002cf2: bd80 pop {r7, pc}
08002cf4 <HAL_DMA_IRQHandler>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
8002cf4: b580 push {r7, lr}
8002cf6: b084 sub sp, #16
8002cf8: af00 add r7, sp, #0
8002cfa: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8002cfc: 687b ldr r3, [r7, #4]
8002cfe: 6bdb ldr r3, [r3, #60] @ 0x3c
8002d00: 681b ldr r3, [r3, #0]
8002d02: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
8002d04: 687b ldr r3, [r7, #4]
8002d06: 681b ldr r3, [r3, #0]
8002d08: 681b ldr r3, [r3, #0]
8002d0a: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
8002d0c: 687b ldr r3, [r7, #4]
8002d0e: 6c1b ldr r3, [r3, #64] @ 0x40
8002d10: 2204 movs r2, #4
8002d12: 409a lsls r2, r3
8002d14: 68fb ldr r3, [r7, #12]
8002d16: 4013 ands r3, r2
8002d18: 2b00 cmp r3, #0
8002d1a: d04f beq.n 8002dbc <HAL_DMA_IRQHandler+0xc8>
8002d1c: 68bb ldr r3, [r7, #8]
8002d1e: f003 0304 and.w r3, r3, #4
8002d22: 2b00 cmp r3, #0
8002d24: d04a beq.n 8002dbc <HAL_DMA_IRQHandler+0xc8>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8002d26: 687b ldr r3, [r7, #4]
8002d28: 681b ldr r3, [r3, #0]
8002d2a: 681b ldr r3, [r3, #0]
8002d2c: f003 0320 and.w r3, r3, #32
8002d30: 2b00 cmp r3, #0
8002d32: d107 bne.n 8002d44 <HAL_DMA_IRQHandler+0x50>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8002d34: 687b ldr r3, [r7, #4]
8002d36: 681b ldr r3, [r3, #0]
8002d38: 681a ldr r2, [r3, #0]
8002d3a: 687b ldr r3, [r7, #4]
8002d3c: 681b ldr r3, [r3, #0]
8002d3e: f022 0204 bic.w r2, r2, #4
8002d42: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
8002d44: 687b ldr r3, [r7, #4]
8002d46: 681b ldr r3, [r3, #0]
8002d48: 4a66 ldr r2, [pc, #408] @ (8002ee4 <HAL_DMA_IRQHandler+0x1f0>)
8002d4a: 4293 cmp r3, r2
8002d4c: d029 beq.n 8002da2 <HAL_DMA_IRQHandler+0xae>
8002d4e: 687b ldr r3, [r7, #4]
8002d50: 681b ldr r3, [r3, #0]
8002d52: 4a65 ldr r2, [pc, #404] @ (8002ee8 <HAL_DMA_IRQHandler+0x1f4>)
8002d54: 4293 cmp r3, r2
8002d56: d022 beq.n 8002d9e <HAL_DMA_IRQHandler+0xaa>
8002d58: 687b ldr r3, [r7, #4]
8002d5a: 681b ldr r3, [r3, #0]
8002d5c: 4a63 ldr r2, [pc, #396] @ (8002eec <HAL_DMA_IRQHandler+0x1f8>)
8002d5e: 4293 cmp r3, r2
8002d60: d01a beq.n 8002d98 <HAL_DMA_IRQHandler+0xa4>
8002d62: 687b ldr r3, [r7, #4]
8002d64: 681b ldr r3, [r3, #0]
8002d66: 4a62 ldr r2, [pc, #392] @ (8002ef0 <HAL_DMA_IRQHandler+0x1fc>)
8002d68: 4293 cmp r3, r2
8002d6a: d012 beq.n 8002d92 <HAL_DMA_IRQHandler+0x9e>
8002d6c: 687b ldr r3, [r7, #4]
8002d6e: 681b ldr r3, [r3, #0]
8002d70: 4a60 ldr r2, [pc, #384] @ (8002ef4 <HAL_DMA_IRQHandler+0x200>)
8002d72: 4293 cmp r3, r2
8002d74: d00a beq.n 8002d8c <HAL_DMA_IRQHandler+0x98>
8002d76: 687b ldr r3, [r7, #4]
8002d78: 681b ldr r3, [r3, #0]
8002d7a: 4a5f ldr r2, [pc, #380] @ (8002ef8 <HAL_DMA_IRQHandler+0x204>)
8002d7c: 4293 cmp r3, r2
8002d7e: d102 bne.n 8002d86 <HAL_DMA_IRQHandler+0x92>
8002d80: f44f 0380 mov.w r3, #4194304 @ 0x400000
8002d84: e00e b.n 8002da4 <HAL_DMA_IRQHandler+0xb0>
8002d86: f04f 6380 mov.w r3, #67108864 @ 0x4000000
8002d8a: e00b b.n 8002da4 <HAL_DMA_IRQHandler+0xb0>
8002d8c: f44f 2380 mov.w r3, #262144 @ 0x40000
8002d90: e008 b.n 8002da4 <HAL_DMA_IRQHandler+0xb0>
8002d92: f44f 4380 mov.w r3, #16384 @ 0x4000
8002d96: e005 b.n 8002da4 <HAL_DMA_IRQHandler+0xb0>
8002d98: f44f 6380 mov.w r3, #1024 @ 0x400
8002d9c: e002 b.n 8002da4 <HAL_DMA_IRQHandler+0xb0>
8002d9e: 2340 movs r3, #64 @ 0x40
8002da0: e000 b.n 8002da4 <HAL_DMA_IRQHandler+0xb0>
8002da2: 2304 movs r3, #4
8002da4: 4a55 ldr r2, [pc, #340] @ (8002efc <HAL_DMA_IRQHandler+0x208>)
8002da6: 6053 str r3, [r2, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
8002da8: 687b ldr r3, [r7, #4]
8002daa: 6adb ldr r3, [r3, #44] @ 0x2c
8002dac: 2b00 cmp r3, #0
8002dae: f000 8094 beq.w 8002eda <HAL_DMA_IRQHandler+0x1e6>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8002db2: 687b ldr r3, [r7, #4]
8002db4: 6adb ldr r3, [r3, #44] @ 0x2c
8002db6: 6878 ldr r0, [r7, #4]
8002db8: 4798 blx r3
if(hdma->XferHalfCpltCallback != NULL)
8002dba: e08e b.n 8002eda <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
8002dbc: 687b ldr r3, [r7, #4]
8002dbe: 6c1b ldr r3, [r3, #64] @ 0x40
8002dc0: 2202 movs r2, #2
8002dc2: 409a lsls r2, r3
8002dc4: 68fb ldr r3, [r7, #12]
8002dc6: 4013 ands r3, r2
8002dc8: 2b00 cmp r3, #0
8002dca: d056 beq.n 8002e7a <HAL_DMA_IRQHandler+0x186>
8002dcc: 68bb ldr r3, [r7, #8]
8002dce: f003 0302 and.w r3, r3, #2
8002dd2: 2b00 cmp r3, #0
8002dd4: d051 beq.n 8002e7a <HAL_DMA_IRQHandler+0x186>
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8002dd6: 687b ldr r3, [r7, #4]
8002dd8: 681b ldr r3, [r3, #0]
8002dda: 681b ldr r3, [r3, #0]
8002ddc: f003 0320 and.w r3, r3, #32
8002de0: 2b00 cmp r3, #0
8002de2: d10b bne.n 8002dfc <HAL_DMA_IRQHandler+0x108>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8002de4: 687b ldr r3, [r7, #4]
8002de6: 681b ldr r3, [r3, #0]
8002de8: 681a ldr r2, [r3, #0]
8002dea: 687b ldr r3, [r7, #4]
8002dec: 681b ldr r3, [r3, #0]
8002dee: f022 020a bic.w r2, r2, #10
8002df2: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8002df4: 687b ldr r3, [r7, #4]
8002df6: 2201 movs r2, #1
8002df8: f883 2021 strb.w r2, [r3, #33] @ 0x21
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
8002dfc: 687b ldr r3, [r7, #4]
8002dfe: 681b ldr r3, [r3, #0]
8002e00: 4a38 ldr r2, [pc, #224] @ (8002ee4 <HAL_DMA_IRQHandler+0x1f0>)
8002e02: 4293 cmp r3, r2
8002e04: d029 beq.n 8002e5a <HAL_DMA_IRQHandler+0x166>
8002e06: 687b ldr r3, [r7, #4]
8002e08: 681b ldr r3, [r3, #0]
8002e0a: 4a37 ldr r2, [pc, #220] @ (8002ee8 <HAL_DMA_IRQHandler+0x1f4>)
8002e0c: 4293 cmp r3, r2
8002e0e: d022 beq.n 8002e56 <HAL_DMA_IRQHandler+0x162>
8002e10: 687b ldr r3, [r7, #4]
8002e12: 681b ldr r3, [r3, #0]
8002e14: 4a35 ldr r2, [pc, #212] @ (8002eec <HAL_DMA_IRQHandler+0x1f8>)
8002e16: 4293 cmp r3, r2
8002e18: d01a beq.n 8002e50 <HAL_DMA_IRQHandler+0x15c>
8002e1a: 687b ldr r3, [r7, #4]
8002e1c: 681b ldr r3, [r3, #0]
8002e1e: 4a34 ldr r2, [pc, #208] @ (8002ef0 <HAL_DMA_IRQHandler+0x1fc>)
8002e20: 4293 cmp r3, r2
8002e22: d012 beq.n 8002e4a <HAL_DMA_IRQHandler+0x156>
8002e24: 687b ldr r3, [r7, #4]
8002e26: 681b ldr r3, [r3, #0]
8002e28: 4a32 ldr r2, [pc, #200] @ (8002ef4 <HAL_DMA_IRQHandler+0x200>)
8002e2a: 4293 cmp r3, r2
8002e2c: d00a beq.n 8002e44 <HAL_DMA_IRQHandler+0x150>
8002e2e: 687b ldr r3, [r7, #4]
8002e30: 681b ldr r3, [r3, #0]
8002e32: 4a31 ldr r2, [pc, #196] @ (8002ef8 <HAL_DMA_IRQHandler+0x204>)
8002e34: 4293 cmp r3, r2
8002e36: d102 bne.n 8002e3e <HAL_DMA_IRQHandler+0x14a>
8002e38: f44f 1300 mov.w r3, #2097152 @ 0x200000
8002e3c: e00e b.n 8002e5c <HAL_DMA_IRQHandler+0x168>
8002e3e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002e42: e00b b.n 8002e5c <HAL_DMA_IRQHandler+0x168>
8002e44: f44f 3300 mov.w r3, #131072 @ 0x20000
8002e48: e008 b.n 8002e5c <HAL_DMA_IRQHandler+0x168>
8002e4a: f44f 5300 mov.w r3, #8192 @ 0x2000
8002e4e: e005 b.n 8002e5c <HAL_DMA_IRQHandler+0x168>
8002e50: f44f 7300 mov.w r3, #512 @ 0x200
8002e54: e002 b.n 8002e5c <HAL_DMA_IRQHandler+0x168>
8002e56: 2320 movs r3, #32
8002e58: e000 b.n 8002e5c <HAL_DMA_IRQHandler+0x168>
8002e5a: 2302 movs r3, #2
8002e5c: 4a27 ldr r2, [pc, #156] @ (8002efc <HAL_DMA_IRQHandler+0x208>)
8002e5e: 6053 str r3, [r2, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002e60: 687b ldr r3, [r7, #4]
8002e62: 2200 movs r2, #0
8002e64: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferCpltCallback != NULL)
8002e68: 687b ldr r3, [r7, #4]
8002e6a: 6a9b ldr r3, [r3, #40] @ 0x28
8002e6c: 2b00 cmp r3, #0
8002e6e: d034 beq.n 8002eda <HAL_DMA_IRQHandler+0x1e6>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8002e70: 687b ldr r3, [r7, #4]
8002e72: 6a9b ldr r3, [r3, #40] @ 0x28
8002e74: 6878 ldr r0, [r7, #4]
8002e76: 4798 blx r3
if(hdma->XferCpltCallback != NULL)
8002e78: e02f b.n 8002eda <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
8002e7a: 687b ldr r3, [r7, #4]
8002e7c: 6c1b ldr r3, [r3, #64] @ 0x40
8002e7e: 2208 movs r2, #8
8002e80: 409a lsls r2, r3
8002e82: 68fb ldr r3, [r7, #12]
8002e84: 4013 ands r3, r2
8002e86: 2b00 cmp r3, #0
8002e88: d028 beq.n 8002edc <HAL_DMA_IRQHandler+0x1e8>
8002e8a: 68bb ldr r3, [r7, #8]
8002e8c: f003 0308 and.w r3, r3, #8
8002e90: 2b00 cmp r3, #0
8002e92: d023 beq.n 8002edc <HAL_DMA_IRQHandler+0x1e8>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8002e94: 687b ldr r3, [r7, #4]
8002e96: 681b ldr r3, [r3, #0]
8002e98: 681a ldr r2, [r3, #0]
8002e9a: 687b ldr r3, [r7, #4]
8002e9c: 681b ldr r3, [r3, #0]
8002e9e: f022 020e bic.w r2, r2, #14
8002ea2: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8002ea4: 687b ldr r3, [r7, #4]
8002ea6: 6c1a ldr r2, [r3, #64] @ 0x40
8002ea8: 687b ldr r3, [r7, #4]
8002eaa: 6bdb ldr r3, [r3, #60] @ 0x3c
8002eac: 2101 movs r1, #1
8002eae: fa01 f202 lsl.w r2, r1, r2
8002eb2: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8002eb4: 687b ldr r3, [r7, #4]
8002eb6: 2201 movs r2, #1
8002eb8: 639a str r2, [r3, #56] @ 0x38
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8002eba: 687b ldr r3, [r7, #4]
8002ebc: 2201 movs r2, #1
8002ebe: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002ec2: 687b ldr r3, [r7, #4]
8002ec4: 2200 movs r2, #0
8002ec6: f883 2020 strb.w r2, [r3, #32]
if (hdma->XferErrorCallback != NULL)
8002eca: 687b ldr r3, [r7, #4]
8002ecc: 6b1b ldr r3, [r3, #48] @ 0x30
8002ece: 2b00 cmp r3, #0
8002ed0: d004 beq.n 8002edc <HAL_DMA_IRQHandler+0x1e8>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8002ed2: 687b ldr r3, [r7, #4]
8002ed4: 6b1b ldr r3, [r3, #48] @ 0x30
8002ed6: 6878 ldr r0, [r7, #4]
8002ed8: 4798 blx r3
}
}
return;
8002eda: bf00 nop
8002edc: bf00 nop
}
8002ede: 3710 adds r7, #16
8002ee0: 46bd mov sp, r7
8002ee2: bd80 pop {r7, pc}
8002ee4: 40020008 .word 0x40020008
8002ee8: 4002001c .word 0x4002001c
8002eec: 40020030 .word 0x40020030
8002ef0: 40020044 .word 0x40020044
8002ef4: 40020058 .word 0x40020058
8002ef8: 4002006c .word 0x4002006c
8002efc: 40020000 .word 0x40020000
08002f00 <DMA_SetConfig>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8002f00: b480 push {r7}
8002f02: b085 sub sp, #20
8002f04: af00 add r7, sp, #0
8002f06: 60f8 str r0, [r7, #12]
8002f08: 60b9 str r1, [r7, #8]
8002f0a: 607a str r2, [r7, #4]
8002f0c: 603b str r3, [r7, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8002f0e: 68fb ldr r3, [r7, #12]
8002f10: 6c1a ldr r2, [r3, #64] @ 0x40
8002f12: 68fb ldr r3, [r7, #12]
8002f14: 6bdb ldr r3, [r3, #60] @ 0x3c
8002f16: 2101 movs r1, #1
8002f18: fa01 f202 lsl.w r2, r1, r2
8002f1c: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8002f1e: 68fb ldr r3, [r7, #12]
8002f20: 681b ldr r3, [r3, #0]
8002f22: 683a ldr r2, [r7, #0]
8002f24: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8002f26: 68fb ldr r3, [r7, #12]
8002f28: 685b ldr r3, [r3, #4]
8002f2a: 2b10 cmp r3, #16
8002f2c: d108 bne.n 8002f40 <DMA_SetConfig+0x40>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8002f2e: 68fb ldr r3, [r7, #12]
8002f30: 681b ldr r3, [r3, #0]
8002f32: 687a ldr r2, [r7, #4]
8002f34: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8002f36: 68fb ldr r3, [r7, #12]
8002f38: 681b ldr r3, [r3, #0]
8002f3a: 68ba ldr r2, [r7, #8]
8002f3c: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8002f3e: e007 b.n 8002f50 <DMA_SetConfig+0x50>
hdma->Instance->CPAR = SrcAddress;
8002f40: 68fb ldr r3, [r7, #12]
8002f42: 681b ldr r3, [r3, #0]
8002f44: 68ba ldr r2, [r7, #8]
8002f46: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8002f48: 68fb ldr r3, [r7, #12]
8002f4a: 681b ldr r3, [r3, #0]
8002f4c: 687a ldr r2, [r7, #4]
8002f4e: 60da str r2, [r3, #12]
}
8002f50: bf00 nop
8002f52: 3714 adds r7, #20
8002f54: 46bd mov sp, r7
8002f56: bc80 pop {r7}
8002f58: 4770 bx lr
...
08002f5c <HAL_FLASH_Program>:
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
8002f5c: b5f0 push {r4, r5, r6, r7, lr}
8002f5e: b087 sub sp, #28
8002f60: af00 add r7, sp, #0
8002f62: 60f8 str r0, [r7, #12]
8002f64: 60b9 str r1, [r7, #8]
8002f66: e9c7 2300 strd r2, r3, [r7]
HAL_StatusTypeDef status = HAL_ERROR;
8002f6a: 2301 movs r3, #1
8002f6c: 75fb strb r3, [r7, #23]
uint8_t index = 0;
8002f6e: 2300 movs r3, #0
8002f70: 75bb strb r3, [r7, #22]
uint8_t nbiterations = 0;
8002f72: 2300 movs r3, #0
8002f74: 757b strb r3, [r7, #21]
/* Process Locked */
__HAL_LOCK(&pFlash);
8002f76: 4b2f ldr r3, [pc, #188] @ (8003034 <HAL_FLASH_Program+0xd8>)
8002f78: 7e1b ldrb r3, [r3, #24]
8002f7a: 2b01 cmp r3, #1
8002f7c: d101 bne.n 8002f82 <HAL_FLASH_Program+0x26>
8002f7e: 2302 movs r3, #2
8002f80: e054 b.n 800302c <HAL_FLASH_Program+0xd0>
8002f82: 4b2c ldr r3, [pc, #176] @ (8003034 <HAL_FLASH_Program+0xd8>)
8002f84: 2201 movs r2, #1
8002f86: 761a strb r2, [r3, #24]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8002f88: f24c 3050 movw r0, #50000 @ 0xc350
8002f8c: f000 f8a8 bl 80030e0 <FLASH_WaitForLastOperation>
8002f90: 4603 mov r3, r0
8002f92: 75fb strb r3, [r7, #23]
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
if(status == HAL_OK)
8002f94: 7dfb ldrb r3, [r7, #23]
8002f96: 2b00 cmp r3, #0
8002f98: d144 bne.n 8003024 <HAL_FLASH_Program+0xc8>
{
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
8002f9a: 68fb ldr r3, [r7, #12]
8002f9c: 2b01 cmp r3, #1
8002f9e: d102 bne.n 8002fa6 <HAL_FLASH_Program+0x4a>
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1U;
8002fa0: 2301 movs r3, #1
8002fa2: 757b strb r3, [r7, #21]
8002fa4: e007 b.n 8002fb6 <HAL_FLASH_Program+0x5a>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
8002fa6: 68fb ldr r3, [r7, #12]
8002fa8: 2b02 cmp r3, #2
8002faa: d102 bne.n 8002fb2 <HAL_FLASH_Program+0x56>
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2U;
8002fac: 2302 movs r3, #2
8002fae: 757b strb r3, [r7, #21]
8002fb0: e001 b.n 8002fb6 <HAL_FLASH_Program+0x5a>
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
nbiterations = 4U;
8002fb2: 2304 movs r3, #4
8002fb4: 757b strb r3, [r7, #21]
}
for (index = 0U; index < nbiterations; index++)
8002fb6: 2300 movs r3, #0
8002fb8: 75bb strb r3, [r7, #22]
8002fba: e02d b.n 8003018 <HAL_FLASH_Program+0xbc>
{
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
8002fbc: 7dbb ldrb r3, [r7, #22]
8002fbe: 005a lsls r2, r3, #1
8002fc0: 68bb ldr r3, [r7, #8]
8002fc2: eb02 0c03 add.w ip, r2, r3
8002fc6: 7dbb ldrb r3, [r7, #22]
8002fc8: 0119 lsls r1, r3, #4
8002fca: e9d7 2300 ldrd r2, r3, [r7]
8002fce: f1c1 0620 rsb r6, r1, #32
8002fd2: f1a1 0020 sub.w r0, r1, #32
8002fd6: fa22 f401 lsr.w r4, r2, r1
8002fda: fa03 f606 lsl.w r6, r3, r6
8002fde: 4334 orrs r4, r6
8002fe0: fa23 f000 lsr.w r0, r3, r0
8002fe4: 4304 orrs r4, r0
8002fe6: fa23 f501 lsr.w r5, r3, r1
8002fea: b2a3 uxth r3, r4
8002fec: 4619 mov r1, r3
8002fee: 4660 mov r0, ip
8002ff0: f000 f85a bl 80030a8 <FLASH_Program_HalfWord>
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
8002ff4: f24c 3050 movw r0, #50000 @ 0xc350
8002ff8: f000 f872 bl 80030e0 <FLASH_WaitForLastOperation>
8002ffc: 4603 mov r3, r0
8002ffe: 75fb strb r3, [r7, #23]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
8003000: 4b0d ldr r3, [pc, #52] @ (8003038 <HAL_FLASH_Program+0xdc>)
8003002: 691b ldr r3, [r3, #16]
8003004: 4a0c ldr r2, [pc, #48] @ (8003038 <HAL_FLASH_Program+0xdc>)
8003006: f023 0301 bic.w r3, r3, #1
800300a: 6113 str r3, [r2, #16]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* In case of error, stop programation procedure */
if (status != HAL_OK)
800300c: 7dfb ldrb r3, [r7, #23]
800300e: 2b00 cmp r3, #0
8003010: d107 bne.n 8003022 <HAL_FLASH_Program+0xc6>
for (index = 0U; index < nbiterations; index++)
8003012: 7dbb ldrb r3, [r7, #22]
8003014: 3301 adds r3, #1
8003016: 75bb strb r3, [r7, #22]
8003018: 7dba ldrb r2, [r7, #22]
800301a: 7d7b ldrb r3, [r7, #21]
800301c: 429a cmp r2, r3
800301e: d3cd bcc.n 8002fbc <HAL_FLASH_Program+0x60>
8003020: e000 b.n 8003024 <HAL_FLASH_Program+0xc8>
{
break;
8003022: bf00 nop
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8003024: 4b03 ldr r3, [pc, #12] @ (8003034 <HAL_FLASH_Program+0xd8>)
8003026: 2200 movs r2, #0
8003028: 761a strb r2, [r3, #24]
return status;
800302a: 7dfb ldrb r3, [r7, #23]
}
800302c: 4618 mov r0, r3
800302e: 371c adds r7, #28
8003030: 46bd mov sp, r7
8003032: bdf0 pop {r4, r5, r6, r7, pc}
8003034: 200003f0 .word 0x200003f0
8003038: 40022000 .word 0x40022000
0800303c <HAL_FLASH_Unlock>:
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
800303c: b480 push {r7}
800303e: b083 sub sp, #12
8003040: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8003042: 2300 movs r3, #0
8003044: 71fb strb r3, [r7, #7]
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
8003046: 4b0d ldr r3, [pc, #52] @ (800307c <HAL_FLASH_Unlock+0x40>)
8003048: 691b ldr r3, [r3, #16]
800304a: f003 0380 and.w r3, r3, #128 @ 0x80
800304e: 2b00 cmp r3, #0
8003050: d00d beq.n 800306e <HAL_FLASH_Unlock+0x32>
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
8003052: 4b0a ldr r3, [pc, #40] @ (800307c <HAL_FLASH_Unlock+0x40>)
8003054: 4a0a ldr r2, [pc, #40] @ (8003080 <HAL_FLASH_Unlock+0x44>)
8003056: 605a str r2, [r3, #4]
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
8003058: 4b08 ldr r3, [pc, #32] @ (800307c <HAL_FLASH_Unlock+0x40>)
800305a: 4a0a ldr r2, [pc, #40] @ (8003084 <HAL_FLASH_Unlock+0x48>)
800305c: 605a str r2, [r3, #4]
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
800305e: 4b07 ldr r3, [pc, #28] @ (800307c <HAL_FLASH_Unlock+0x40>)
8003060: 691b ldr r3, [r3, #16]
8003062: f003 0380 and.w r3, r3, #128 @ 0x80
8003066: 2b00 cmp r3, #0
8003068: d001 beq.n 800306e <HAL_FLASH_Unlock+0x32>
{
status = HAL_ERROR;
800306a: 2301 movs r3, #1
800306c: 71fb strb r3, [r7, #7]
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return status;
800306e: 79fb ldrb r3, [r7, #7]
}
8003070: 4618 mov r0, r3
8003072: 370c adds r7, #12
8003074: 46bd mov sp, r7
8003076: bc80 pop {r7}
8003078: 4770 bx lr
800307a: bf00 nop
800307c: 40022000 .word 0x40022000
8003080: 45670123 .word 0x45670123
8003084: cdef89ab .word 0xcdef89ab
08003088 <HAL_FLASH_Lock>:
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
8003088: b480 push {r7}
800308a: af00 add r7, sp, #0
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
800308c: 4b05 ldr r3, [pc, #20] @ (80030a4 <HAL_FLASH_Lock+0x1c>)
800308e: 691b ldr r3, [r3, #16]
8003090: 4a04 ldr r2, [pc, #16] @ (80030a4 <HAL_FLASH_Lock+0x1c>)
8003092: f043 0380 orr.w r3, r3, #128 @ 0x80
8003096: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
#endif /* FLASH_BANK2_END */
return HAL_OK;
8003098: 2300 movs r3, #0
}
800309a: 4618 mov r0, r3
800309c: 46bd mov sp, r7
800309e: bc80 pop {r7}
80030a0: 4770 bx lr
80030a2: bf00 nop
80030a4: 40022000 .word 0x40022000
080030a8 <FLASH_Program_HalfWord>:
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
80030a8: b480 push {r7}
80030aa: b083 sub sp, #12
80030ac: af00 add r7, sp, #0
80030ae: 6078 str r0, [r7, #4]
80030b0: 460b mov r3, r1
80030b2: 807b strh r3, [r7, #2]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
80030b4: 4b08 ldr r3, [pc, #32] @ (80030d8 <FLASH_Program_HalfWord+0x30>)
80030b6: 2200 movs r2, #0
80030b8: 61da str r2, [r3, #28]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Proceed to program the new data */
SET_BIT(FLASH->CR, FLASH_CR_PG);
80030ba: 4b08 ldr r3, [pc, #32] @ (80030dc <FLASH_Program_HalfWord+0x34>)
80030bc: 691b ldr r3, [r3, #16]
80030be: 4a07 ldr r2, [pc, #28] @ (80030dc <FLASH_Program_HalfWord+0x34>)
80030c0: f043 0301 orr.w r3, r3, #1
80030c4: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* Write data in the address */
*(__IO uint16_t*)Address = Data;
80030c6: 687b ldr r3, [r7, #4]
80030c8: 887a ldrh r2, [r7, #2]
80030ca: 801a strh r2, [r3, #0]
}
80030cc: bf00 nop
80030ce: 370c adds r7, #12
80030d0: 46bd mov sp, r7
80030d2: bc80 pop {r7}
80030d4: 4770 bx lr
80030d6: bf00 nop
80030d8: 200003f0 .word 0x200003f0
80030dc: 40022000 .word 0x40022000
080030e0 <FLASH_WaitForLastOperation>:
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
80030e0: b580 push {r7, lr}
80030e2: b084 sub sp, #16
80030e4: af00 add r7, sp, #0
80030e6: 6078 str r0, [r7, #4]
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
80030e8: f7ff f860 bl 80021ac <HAL_GetTick>
80030ec: 60f8 str r0, [r7, #12]
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
80030ee: e010 b.n 8003112 <FLASH_WaitForLastOperation+0x32>
{
if (Timeout != HAL_MAX_DELAY)
80030f0: 687b ldr r3, [r7, #4]
80030f2: f1b3 3fff cmp.w r3, #4294967295
80030f6: d00c beq.n 8003112 <FLASH_WaitForLastOperation+0x32>
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
80030f8: 687b ldr r3, [r7, #4]
80030fa: 2b00 cmp r3, #0
80030fc: d007 beq.n 800310e <FLASH_WaitForLastOperation+0x2e>
80030fe: f7ff f855 bl 80021ac <HAL_GetTick>
8003102: 4602 mov r2, r0
8003104: 68fb ldr r3, [r7, #12]
8003106: 1ad3 subs r3, r2, r3
8003108: 687a ldr r2, [r7, #4]
800310a: 429a cmp r2, r3
800310c: d201 bcs.n 8003112 <FLASH_WaitForLastOperation+0x32>
{
return HAL_TIMEOUT;
800310e: 2303 movs r3, #3
8003110: e025 b.n 800315e <FLASH_WaitForLastOperation+0x7e>
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
8003112: 4b15 ldr r3, [pc, #84] @ (8003168 <FLASH_WaitForLastOperation+0x88>)
8003114: 68db ldr r3, [r3, #12]
8003116: f003 0301 and.w r3, r3, #1
800311a: 2b00 cmp r3, #0
800311c: d1e8 bne.n 80030f0 <FLASH_WaitForLastOperation+0x10>
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
800311e: 4b12 ldr r3, [pc, #72] @ (8003168 <FLASH_WaitForLastOperation+0x88>)
8003120: 68db ldr r3, [r3, #12]
8003122: f003 0320 and.w r3, r3, #32
8003126: 2b00 cmp r3, #0
8003128: d002 beq.n 8003130 <FLASH_WaitForLastOperation+0x50>
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
800312a: 4b0f ldr r3, [pc, #60] @ (8003168 <FLASH_WaitForLastOperation+0x88>)
800312c: 2220 movs r2, #32
800312e: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8003130: 4b0d ldr r3, [pc, #52] @ (8003168 <FLASH_WaitForLastOperation+0x88>)
8003132: 68db ldr r3, [r3, #12]
8003134: f003 0310 and.w r3, r3, #16
8003138: 2b00 cmp r3, #0
800313a: d10b bne.n 8003154 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
800313c: 4b0a ldr r3, [pc, #40] @ (8003168 <FLASH_WaitForLastOperation+0x88>)
800313e: 69db ldr r3, [r3, #28]
8003140: f003 0301 and.w r3, r3, #1
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8003144: 2b00 cmp r3, #0
8003146: d105 bne.n 8003154 <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
8003148: 4b07 ldr r3, [pc, #28] @ (8003168 <FLASH_WaitForLastOperation+0x88>)
800314a: 68db ldr r3, [r3, #12]
800314c: f003 0304 and.w r3, r3, #4
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
8003150: 2b00 cmp r3, #0
8003152: d003 beq.n 800315c <FLASH_WaitForLastOperation+0x7c>
{
/*Save the error code*/
FLASH_SetErrorCode();
8003154: f000 f80a bl 800316c <FLASH_SetErrorCode>
return HAL_ERROR;
8003158: 2301 movs r3, #1
800315a: e000 b.n 800315e <FLASH_WaitForLastOperation+0x7e>
}
/* There is no error flag set */
return HAL_OK;
800315c: 2300 movs r3, #0
}
800315e: 4618 mov r0, r3
8003160: 3710 adds r7, #16
8003162: 46bd mov sp, r7
8003164: bd80 pop {r7, pc}
8003166: bf00 nop
8003168: 40022000 .word 0x40022000
0800316c <FLASH_SetErrorCode>:
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
800316c: b480 push {r7}
800316e: b083 sub sp, #12
8003170: af00 add r7, sp, #0
uint32_t flags = 0U;
8003172: 2300 movs r3, #0
8003174: 607b str r3, [r7, #4]
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
8003176: 4b23 ldr r3, [pc, #140] @ (8003204 <FLASH_SetErrorCode+0x98>)
8003178: 68db ldr r3, [r3, #12]
800317a: f003 0310 and.w r3, r3, #16
800317e: 2b00 cmp r3, #0
8003180: d009 beq.n 8003196 <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
8003182: 4b21 ldr r3, [pc, #132] @ (8003208 <FLASH_SetErrorCode+0x9c>)
8003184: 69db ldr r3, [r3, #28]
8003186: f043 0302 orr.w r3, r3, #2
800318a: 4a1f ldr r2, [pc, #124] @ (8003208 <FLASH_SetErrorCode+0x9c>)
800318c: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
flags |= FLASH_FLAG_WRPERR;
800318e: 687b ldr r3, [r7, #4]
8003190: f043 0310 orr.w r3, r3, #16
8003194: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
8003196: 4b1b ldr r3, [pc, #108] @ (8003204 <FLASH_SetErrorCode+0x98>)
8003198: 68db ldr r3, [r3, #12]
800319a: f003 0304 and.w r3, r3, #4
800319e: 2b00 cmp r3, #0
80031a0: d009 beq.n 80031b6 <FLASH_SetErrorCode+0x4a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
80031a2: 4b19 ldr r3, [pc, #100] @ (8003208 <FLASH_SetErrorCode+0x9c>)
80031a4: 69db ldr r3, [r3, #28]
80031a6: f043 0301 orr.w r3, r3, #1
80031aa: 4a17 ldr r2, [pc, #92] @ (8003208 <FLASH_SetErrorCode+0x9c>)
80031ac: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
flags |= FLASH_FLAG_PGERR;
80031ae: 687b ldr r3, [r7, #4]
80031b0: f043 0304 orr.w r3, r3, #4
80031b4: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
80031b6: 4b13 ldr r3, [pc, #76] @ (8003204 <FLASH_SetErrorCode+0x98>)
80031b8: 69db ldr r3, [r3, #28]
80031ba: f003 0301 and.w r3, r3, #1
80031be: 2b00 cmp r3, #0
80031c0: d00b beq.n 80031da <FLASH_SetErrorCode+0x6e>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
80031c2: 4b11 ldr r3, [pc, #68] @ (8003208 <FLASH_SetErrorCode+0x9c>)
80031c4: 69db ldr r3, [r3, #28]
80031c6: f043 0304 orr.w r3, r3, #4
80031ca: 4a0f ldr r2, [pc, #60] @ (8003208 <FLASH_SetErrorCode+0x9c>)
80031cc: 61d3 str r3, [r2, #28]
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
80031ce: 4b0d ldr r3, [pc, #52] @ (8003204 <FLASH_SetErrorCode+0x98>)
80031d0: 69db ldr r3, [r3, #28]
80031d2: 4a0c ldr r2, [pc, #48] @ (8003204 <FLASH_SetErrorCode+0x98>)
80031d4: f023 0301 bic.w r3, r3, #1
80031d8: 61d3 str r3, [r2, #28]
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
80031da: 687b ldr r3, [r7, #4]
80031dc: f240 1201 movw r2, #257 @ 0x101
80031e0: 4293 cmp r3, r2
80031e2: d106 bne.n 80031f2 <FLASH_SetErrorCode+0x86>
80031e4: 4b07 ldr r3, [pc, #28] @ (8003204 <FLASH_SetErrorCode+0x98>)
80031e6: 69db ldr r3, [r3, #28]
80031e8: 4a06 ldr r2, [pc, #24] @ (8003204 <FLASH_SetErrorCode+0x98>)
80031ea: f023 0301 bic.w r3, r3, #1
80031ee: 61d3 str r3, [r2, #28]
}
80031f0: e002 b.n 80031f8 <FLASH_SetErrorCode+0x8c>
__HAL_FLASH_CLEAR_FLAG(flags);
80031f2: 4a04 ldr r2, [pc, #16] @ (8003204 <FLASH_SetErrorCode+0x98>)
80031f4: 687b ldr r3, [r7, #4]
80031f6: 60d3 str r3, [r2, #12]
}
80031f8: bf00 nop
80031fa: 370c adds r7, #12
80031fc: 46bd mov sp, r7
80031fe: bc80 pop {r7}
8003200: 4770 bx lr
8003202: bf00 nop
8003204: 40022000 .word 0x40022000
8003208: 200003f0 .word 0x200003f0
0800320c <HAL_FLASHEx_Erase>:
* (0xFFFFFFFF means that all the pages have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
800320c: b580 push {r7, lr}
800320e: b084 sub sp, #16
8003210: af00 add r7, sp, #0
8003212: 6078 str r0, [r7, #4]
8003214: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_ERROR;
8003216: 2301 movs r3, #1
8003218: 73fb strb r3, [r7, #15]
uint32_t address = 0U;
800321a: 2300 movs r3, #0
800321c: 60bb str r3, [r7, #8]
/* Process Locked */
__HAL_LOCK(&pFlash);
800321e: 4b2f ldr r3, [pc, #188] @ (80032dc <HAL_FLASHEx_Erase+0xd0>)
8003220: 7e1b ldrb r3, [r3, #24]
8003222: 2b01 cmp r3, #1
8003224: d101 bne.n 800322a <HAL_FLASHEx_Erase+0x1e>
8003226: 2302 movs r3, #2
8003228: e053 b.n 80032d2 <HAL_FLASHEx_Erase+0xc6>
800322a: 4b2c ldr r3, [pc, #176] @ (80032dc <HAL_FLASHEx_Erase+0xd0>)
800322c: 2201 movs r2, #1
800322e: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
8003230: 687b ldr r3, [r7, #4]
8003232: 681b ldr r3, [r3, #0]
8003234: 2b02 cmp r3, #2
8003236: d116 bne.n 8003266 <HAL_FLASHEx_Erase+0x5a>
else
#endif /* FLASH_BANK2_END */
{
/* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8003238: f24c 3050 movw r0, #50000 @ 0xc350
800323c: f7ff ff50 bl 80030e0 <FLASH_WaitForLastOperation>
8003240: 4603 mov r3, r0
8003242: 2b00 cmp r3, #0
8003244: d141 bne.n 80032ca <HAL_FLASHEx_Erase+0xbe>
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_1);
8003246: 2001 movs r0, #1
8003248: f000 f84c bl 80032e4 <FLASH_MassErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
800324c: f24c 3050 movw r0, #50000 @ 0xc350
8003250: f7ff ff46 bl 80030e0 <FLASH_WaitForLastOperation>
8003254: 4603 mov r3, r0
8003256: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
8003258: 4b21 ldr r3, [pc, #132] @ (80032e0 <HAL_FLASHEx_Erase+0xd4>)
800325a: 691b ldr r3, [r3, #16]
800325c: 4a20 ldr r2, [pc, #128] @ (80032e0 <HAL_FLASHEx_Erase+0xd4>)
800325e: f023 0304 bic.w r3, r3, #4
8003262: 6113 str r3, [r2, #16]
8003264: e031 b.n 80032ca <HAL_FLASHEx_Erase+0xbe>
else
#endif /* FLASH_BANK2_END */
{
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8003266: f24c 3050 movw r0, #50000 @ 0xc350
800326a: f7ff ff39 bl 80030e0 <FLASH_WaitForLastOperation>
800326e: 4603 mov r3, r0
8003270: 2b00 cmp r3, #0
8003272: d12a bne.n 80032ca <HAL_FLASHEx_Erase+0xbe>
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
8003274: 683b ldr r3, [r7, #0]
8003276: f04f 32ff mov.w r2, #4294967295
800327a: 601a str r2, [r3, #0]
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
800327c: 687b ldr r3, [r7, #4]
800327e: 689b ldr r3, [r3, #8]
8003280: 60bb str r3, [r7, #8]
8003282: e019 b.n 80032b8 <HAL_FLASHEx_Erase+0xac>
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
8003284: 68b8 ldr r0, [r7, #8]
8003286: f000 f849 bl 800331c <FLASH_PageErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
800328a: f24c 3050 movw r0, #50000 @ 0xc350
800328e: f7ff ff27 bl 80030e0 <FLASH_WaitForLastOperation>
8003292: 4603 mov r3, r0
8003294: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
8003296: 4b12 ldr r3, [pc, #72] @ (80032e0 <HAL_FLASHEx_Erase+0xd4>)
8003298: 691b ldr r3, [r3, #16]
800329a: 4a11 ldr r2, [pc, #68] @ (80032e0 <HAL_FLASHEx_Erase+0xd4>)
800329c: f023 0302 bic.w r3, r3, #2
80032a0: 6113 str r3, [r2, #16]
if (status != HAL_OK)
80032a2: 7bfb ldrb r3, [r7, #15]
80032a4: 2b00 cmp r3, #0
80032a6: d003 beq.n 80032b0 <HAL_FLASHEx_Erase+0xa4>
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
80032a8: 683b ldr r3, [r7, #0]
80032aa: 68ba ldr r2, [r7, #8]
80032ac: 601a str r2, [r3, #0]
break;
80032ae: e00c b.n 80032ca <HAL_FLASHEx_Erase+0xbe>
address += FLASH_PAGE_SIZE)
80032b0: 68bb ldr r3, [r7, #8]
80032b2: f503 6380 add.w r3, r3, #1024 @ 0x400
80032b6: 60bb str r3, [r7, #8]
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
80032b8: 687b ldr r3, [r7, #4]
80032ba: 68db ldr r3, [r3, #12]
80032bc: 029a lsls r2, r3, #10
80032be: 687b ldr r3, [r7, #4]
80032c0: 689b ldr r3, [r3, #8]
80032c2: 4413 add r3, r2
80032c4: 68ba ldr r2, [r7, #8]
80032c6: 429a cmp r2, r3
80032c8: d3dc bcc.n 8003284 <HAL_FLASHEx_Erase+0x78>
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
80032ca: 4b04 ldr r3, [pc, #16] @ (80032dc <HAL_FLASHEx_Erase+0xd0>)
80032cc: 2200 movs r2, #0
80032ce: 761a strb r2, [r3, #24]
return status;
80032d0: 7bfb ldrb r3, [r7, #15]
}
80032d2: 4618 mov r0, r3
80032d4: 3710 adds r7, #16
80032d6: 46bd mov sp, r7
80032d8: bd80 pop {r7, pc}
80032da: bf00 nop
80032dc: 200003f0 .word 0x200003f0
80032e0: 40022000 .word 0x40022000
080032e4 <FLASH_MassErase>:
@endif
*
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
80032e4: b480 push {r7}
80032e6: b083 sub sp, #12
80032e8: af00 add r7, sp, #0
80032ea: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
80032ec: 4b09 ldr r3, [pc, #36] @ (8003314 <FLASH_MassErase+0x30>)
80032ee: 2200 movs r2, #0
80032f0: 61da str r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH->CR, FLASH_CR_MER);
80032f2: 4b09 ldr r3, [pc, #36] @ (8003318 <FLASH_MassErase+0x34>)
80032f4: 691b ldr r3, [r3, #16]
80032f6: 4a08 ldr r2, [pc, #32] @ (8003318 <FLASH_MassErase+0x34>)
80032f8: f043 0304 orr.w r3, r3, #4
80032fc: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
80032fe: 4b06 ldr r3, [pc, #24] @ (8003318 <FLASH_MassErase+0x34>)
8003300: 691b ldr r3, [r3, #16]
8003302: 4a05 ldr r2, [pc, #20] @ (8003318 <FLASH_MassErase+0x34>)
8003304: f043 0340 orr.w r3, r3, #64 @ 0x40
8003308: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
800330a: bf00 nop
800330c: 370c adds r7, #12
800330e: 46bd mov sp, r7
8003310: bc80 pop {r7}
8003312: 4770 bx lr
8003314: 200003f0 .word 0x200003f0
8003318: 40022000 .word 0x40022000
0800331c <FLASH_PageErase>:
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)
{
800331c: b480 push {r7}
800331e: b083 sub sp, #12
8003320: af00 add r7, sp, #0
8003322: 6078 str r0, [r7, #4]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8003324: 4b0b ldr r3, [pc, #44] @ (8003354 <FLASH_PageErase+0x38>)
8003326: 2200 movs r2, #0
8003328: 61da str r2, [r3, #28]
}
else
{
#endif /* FLASH_BANK2_END */
/* Proceed to erase the page */
SET_BIT(FLASH->CR, FLASH_CR_PER);
800332a: 4b0b ldr r3, [pc, #44] @ (8003358 <FLASH_PageErase+0x3c>)
800332c: 691b ldr r3, [r3, #16]
800332e: 4a0a ldr r2, [pc, #40] @ (8003358 <FLASH_PageErase+0x3c>)
8003330: f043 0302 orr.w r3, r3, #2
8003334: 6113 str r3, [r2, #16]
WRITE_REG(FLASH->AR, PageAddress);
8003336: 4a08 ldr r2, [pc, #32] @ (8003358 <FLASH_PageErase+0x3c>)
8003338: 687b ldr r3, [r7, #4]
800333a: 6153 str r3, [r2, #20]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
800333c: 4b06 ldr r3, [pc, #24] @ (8003358 <FLASH_PageErase+0x3c>)
800333e: 691b ldr r3, [r3, #16]
8003340: 4a05 ldr r2, [pc, #20] @ (8003358 <FLASH_PageErase+0x3c>)
8003342: f043 0340 orr.w r3, r3, #64 @ 0x40
8003346: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8003348: bf00 nop
800334a: 370c adds r7, #12
800334c: 46bd mov sp, r7
800334e: bc80 pop {r7}
8003350: 4770 bx lr
8003352: bf00 nop
8003354: 200003f0 .word 0x200003f0
8003358: 40022000 .word 0x40022000
0800335c <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800335c: b480 push {r7}
800335e: b08b sub sp, #44 @ 0x2c
8003360: af00 add r7, sp, #0
8003362: 6078 str r0, [r7, #4]
8003364: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003366: 2300 movs r3, #0
8003368: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
800336a: 2300 movs r3, #0
800336c: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800336e: e169 b.n 8003644 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8003370: 2201 movs r2, #1
8003372: 6a7b ldr r3, [r7, #36] @ 0x24
8003374: fa02 f303 lsl.w r3, r2, r3
8003378: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800337a: 683b ldr r3, [r7, #0]
800337c: 681b ldr r3, [r3, #0]
800337e: 69fa ldr r2, [r7, #28]
8003380: 4013 ands r3, r2
8003382: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8003384: 69ba ldr r2, [r7, #24]
8003386: 69fb ldr r3, [r7, #28]
8003388: 429a cmp r2, r3
800338a: f040 8158 bne.w 800363e <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
800338e: 683b ldr r3, [r7, #0]
8003390: 685b ldr r3, [r3, #4]
8003392: 4a9a ldr r2, [pc, #616] @ (80035fc <HAL_GPIO_Init+0x2a0>)
8003394: 4293 cmp r3, r2
8003396: d05e beq.n 8003456 <HAL_GPIO_Init+0xfa>
8003398: 4a98 ldr r2, [pc, #608] @ (80035fc <HAL_GPIO_Init+0x2a0>)
800339a: 4293 cmp r3, r2
800339c: d875 bhi.n 800348a <HAL_GPIO_Init+0x12e>
800339e: 4a98 ldr r2, [pc, #608] @ (8003600 <HAL_GPIO_Init+0x2a4>)
80033a0: 4293 cmp r3, r2
80033a2: d058 beq.n 8003456 <HAL_GPIO_Init+0xfa>
80033a4: 4a96 ldr r2, [pc, #600] @ (8003600 <HAL_GPIO_Init+0x2a4>)
80033a6: 4293 cmp r3, r2
80033a8: d86f bhi.n 800348a <HAL_GPIO_Init+0x12e>
80033aa: 4a96 ldr r2, [pc, #600] @ (8003604 <HAL_GPIO_Init+0x2a8>)
80033ac: 4293 cmp r3, r2
80033ae: d052 beq.n 8003456 <HAL_GPIO_Init+0xfa>
80033b0: 4a94 ldr r2, [pc, #592] @ (8003604 <HAL_GPIO_Init+0x2a8>)
80033b2: 4293 cmp r3, r2
80033b4: d869 bhi.n 800348a <HAL_GPIO_Init+0x12e>
80033b6: 4a94 ldr r2, [pc, #592] @ (8003608 <HAL_GPIO_Init+0x2ac>)
80033b8: 4293 cmp r3, r2
80033ba: d04c beq.n 8003456 <HAL_GPIO_Init+0xfa>
80033bc: 4a92 ldr r2, [pc, #584] @ (8003608 <HAL_GPIO_Init+0x2ac>)
80033be: 4293 cmp r3, r2
80033c0: d863 bhi.n 800348a <HAL_GPIO_Init+0x12e>
80033c2: 4a92 ldr r2, [pc, #584] @ (800360c <HAL_GPIO_Init+0x2b0>)
80033c4: 4293 cmp r3, r2
80033c6: d046 beq.n 8003456 <HAL_GPIO_Init+0xfa>
80033c8: 4a90 ldr r2, [pc, #576] @ (800360c <HAL_GPIO_Init+0x2b0>)
80033ca: 4293 cmp r3, r2
80033cc: d85d bhi.n 800348a <HAL_GPIO_Init+0x12e>
80033ce: 2b12 cmp r3, #18
80033d0: d82a bhi.n 8003428 <HAL_GPIO_Init+0xcc>
80033d2: 2b12 cmp r3, #18
80033d4: d859 bhi.n 800348a <HAL_GPIO_Init+0x12e>
80033d6: a201 add r2, pc, #4 @ (adr r2, 80033dc <HAL_GPIO_Init+0x80>)
80033d8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80033dc: 08003457 .word 0x08003457
80033e0: 08003431 .word 0x08003431
80033e4: 08003443 .word 0x08003443
80033e8: 08003485 .word 0x08003485
80033ec: 0800348b .word 0x0800348b
80033f0: 0800348b .word 0x0800348b
80033f4: 0800348b .word 0x0800348b
80033f8: 0800348b .word 0x0800348b
80033fc: 0800348b .word 0x0800348b
8003400: 0800348b .word 0x0800348b
8003404: 0800348b .word 0x0800348b
8003408: 0800348b .word 0x0800348b
800340c: 0800348b .word 0x0800348b
8003410: 0800348b .word 0x0800348b
8003414: 0800348b .word 0x0800348b
8003418: 0800348b .word 0x0800348b
800341c: 0800348b .word 0x0800348b
8003420: 08003439 .word 0x08003439
8003424: 0800344d .word 0x0800344d
8003428: 4a79 ldr r2, [pc, #484] @ (8003610 <HAL_GPIO_Init+0x2b4>)
800342a: 4293 cmp r3, r2
800342c: d013 beq.n 8003456 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
800342e: e02c b.n 800348a <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8003430: 683b ldr r3, [r7, #0]
8003432: 68db ldr r3, [r3, #12]
8003434: 623b str r3, [r7, #32]
break;
8003436: e029 b.n 800348c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8003438: 683b ldr r3, [r7, #0]
800343a: 68db ldr r3, [r3, #12]
800343c: 3304 adds r3, #4
800343e: 623b str r3, [r7, #32]
break;
8003440: e024 b.n 800348c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8003442: 683b ldr r3, [r7, #0]
8003444: 68db ldr r3, [r3, #12]
8003446: 3308 adds r3, #8
8003448: 623b str r3, [r7, #32]
break;
800344a: e01f b.n 800348c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
800344c: 683b ldr r3, [r7, #0]
800344e: 68db ldr r3, [r3, #12]
8003450: 330c adds r3, #12
8003452: 623b str r3, [r7, #32]
break;
8003454: e01a b.n 800348c <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8003456: 683b ldr r3, [r7, #0]
8003458: 689b ldr r3, [r3, #8]
800345a: 2b00 cmp r3, #0
800345c: d102 bne.n 8003464 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800345e: 2304 movs r3, #4
8003460: 623b str r3, [r7, #32]
break;
8003462: e013 b.n 800348c <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8003464: 683b ldr r3, [r7, #0]
8003466: 689b ldr r3, [r3, #8]
8003468: 2b01 cmp r3, #1
800346a: d105 bne.n 8003478 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
800346c: 2308 movs r3, #8
800346e: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8003470: 687b ldr r3, [r7, #4]
8003472: 69fa ldr r2, [r7, #28]
8003474: 611a str r2, [r3, #16]
break;
8003476: e009 b.n 800348c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8003478: 2308 movs r3, #8
800347a: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
800347c: 687b ldr r3, [r7, #4]
800347e: 69fa ldr r2, [r7, #28]
8003480: 615a str r2, [r3, #20]
break;
8003482: e003 b.n 800348c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8003484: 2300 movs r3, #0
8003486: 623b str r3, [r7, #32]
break;
8003488: e000 b.n 800348c <HAL_GPIO_Init+0x130>
break;
800348a: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
800348c: 69bb ldr r3, [r7, #24]
800348e: 2bff cmp r3, #255 @ 0xff
8003490: d801 bhi.n 8003496 <HAL_GPIO_Init+0x13a>
8003492: 687b ldr r3, [r7, #4]
8003494: e001 b.n 800349a <HAL_GPIO_Init+0x13e>
8003496: 687b ldr r3, [r7, #4]
8003498: 3304 adds r3, #4
800349a: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
800349c: 69bb ldr r3, [r7, #24]
800349e: 2bff cmp r3, #255 @ 0xff
80034a0: d802 bhi.n 80034a8 <HAL_GPIO_Init+0x14c>
80034a2: 6a7b ldr r3, [r7, #36] @ 0x24
80034a4: 009b lsls r3, r3, #2
80034a6: e002 b.n 80034ae <HAL_GPIO_Init+0x152>
80034a8: 6a7b ldr r3, [r7, #36] @ 0x24
80034aa: 3b08 subs r3, #8
80034ac: 009b lsls r3, r3, #2
80034ae: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80034b0: 697b ldr r3, [r7, #20]
80034b2: 681a ldr r2, [r3, #0]
80034b4: 210f movs r1, #15
80034b6: 693b ldr r3, [r7, #16]
80034b8: fa01 f303 lsl.w r3, r1, r3
80034bc: 43db mvns r3, r3
80034be: 401a ands r2, r3
80034c0: 6a39 ldr r1, [r7, #32]
80034c2: 693b ldr r3, [r7, #16]
80034c4: fa01 f303 lsl.w r3, r1, r3
80034c8: 431a orrs r2, r3
80034ca: 697b ldr r3, [r7, #20]
80034cc: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80034ce: 683b ldr r3, [r7, #0]
80034d0: 685b ldr r3, [r3, #4]
80034d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80034d6: 2b00 cmp r3, #0
80034d8: f000 80b1 beq.w 800363e <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
80034dc: 4b4d ldr r3, [pc, #308] @ (8003614 <HAL_GPIO_Init+0x2b8>)
80034de: 699b ldr r3, [r3, #24]
80034e0: 4a4c ldr r2, [pc, #304] @ (8003614 <HAL_GPIO_Init+0x2b8>)
80034e2: f043 0301 orr.w r3, r3, #1
80034e6: 6193 str r3, [r2, #24]
80034e8: 4b4a ldr r3, [pc, #296] @ (8003614 <HAL_GPIO_Init+0x2b8>)
80034ea: 699b ldr r3, [r3, #24]
80034ec: f003 0301 and.w r3, r3, #1
80034f0: 60bb str r3, [r7, #8]
80034f2: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
80034f4: 4a48 ldr r2, [pc, #288] @ (8003618 <HAL_GPIO_Init+0x2bc>)
80034f6: 6a7b ldr r3, [r7, #36] @ 0x24
80034f8: 089b lsrs r3, r3, #2
80034fa: 3302 adds r3, #2
80034fc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003500: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8003502: 6a7b ldr r3, [r7, #36] @ 0x24
8003504: f003 0303 and.w r3, r3, #3
8003508: 009b lsls r3, r3, #2
800350a: 220f movs r2, #15
800350c: fa02 f303 lsl.w r3, r2, r3
8003510: 43db mvns r3, r3
8003512: 68fa ldr r2, [r7, #12]
8003514: 4013 ands r3, r2
8003516: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8003518: 687b ldr r3, [r7, #4]
800351a: 4a40 ldr r2, [pc, #256] @ (800361c <HAL_GPIO_Init+0x2c0>)
800351c: 4293 cmp r3, r2
800351e: d013 beq.n 8003548 <HAL_GPIO_Init+0x1ec>
8003520: 687b ldr r3, [r7, #4]
8003522: 4a3f ldr r2, [pc, #252] @ (8003620 <HAL_GPIO_Init+0x2c4>)
8003524: 4293 cmp r3, r2
8003526: d00d beq.n 8003544 <HAL_GPIO_Init+0x1e8>
8003528: 687b ldr r3, [r7, #4]
800352a: 4a3e ldr r2, [pc, #248] @ (8003624 <HAL_GPIO_Init+0x2c8>)
800352c: 4293 cmp r3, r2
800352e: d007 beq.n 8003540 <HAL_GPIO_Init+0x1e4>
8003530: 687b ldr r3, [r7, #4]
8003532: 4a3d ldr r2, [pc, #244] @ (8003628 <HAL_GPIO_Init+0x2cc>)
8003534: 4293 cmp r3, r2
8003536: d101 bne.n 800353c <HAL_GPIO_Init+0x1e0>
8003538: 2303 movs r3, #3
800353a: e006 b.n 800354a <HAL_GPIO_Init+0x1ee>
800353c: 2304 movs r3, #4
800353e: e004 b.n 800354a <HAL_GPIO_Init+0x1ee>
8003540: 2302 movs r3, #2
8003542: e002 b.n 800354a <HAL_GPIO_Init+0x1ee>
8003544: 2301 movs r3, #1
8003546: e000 b.n 800354a <HAL_GPIO_Init+0x1ee>
8003548: 2300 movs r3, #0
800354a: 6a7a ldr r2, [r7, #36] @ 0x24
800354c: f002 0203 and.w r2, r2, #3
8003550: 0092 lsls r2, r2, #2
8003552: 4093 lsls r3, r2
8003554: 68fa ldr r2, [r7, #12]
8003556: 4313 orrs r3, r2
8003558: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
800355a: 492f ldr r1, [pc, #188] @ (8003618 <HAL_GPIO_Init+0x2bc>)
800355c: 6a7b ldr r3, [r7, #36] @ 0x24
800355e: 089b lsrs r3, r3, #2
8003560: 3302 adds r3, #2
8003562: 68fa ldr r2, [r7, #12]
8003564: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8003568: 683b ldr r3, [r7, #0]
800356a: 685b ldr r3, [r3, #4]
800356c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003570: 2b00 cmp r3, #0
8003572: d006 beq.n 8003582 <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8003574: 4b2d ldr r3, [pc, #180] @ (800362c <HAL_GPIO_Init+0x2d0>)
8003576: 689a ldr r2, [r3, #8]
8003578: 492c ldr r1, [pc, #176] @ (800362c <HAL_GPIO_Init+0x2d0>)
800357a: 69bb ldr r3, [r7, #24]
800357c: 4313 orrs r3, r2
800357e: 608b str r3, [r1, #8]
8003580: e006 b.n 8003590 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8003582: 4b2a ldr r3, [pc, #168] @ (800362c <HAL_GPIO_Init+0x2d0>)
8003584: 689a ldr r2, [r3, #8]
8003586: 69bb ldr r3, [r7, #24]
8003588: 43db mvns r3, r3
800358a: 4928 ldr r1, [pc, #160] @ (800362c <HAL_GPIO_Init+0x2d0>)
800358c: 4013 ands r3, r2
800358e: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8003590: 683b ldr r3, [r7, #0]
8003592: 685b ldr r3, [r3, #4]
8003594: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003598: 2b00 cmp r3, #0
800359a: d006 beq.n 80035aa <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
800359c: 4b23 ldr r3, [pc, #140] @ (800362c <HAL_GPIO_Init+0x2d0>)
800359e: 68da ldr r2, [r3, #12]
80035a0: 4922 ldr r1, [pc, #136] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035a2: 69bb ldr r3, [r7, #24]
80035a4: 4313 orrs r3, r2
80035a6: 60cb str r3, [r1, #12]
80035a8: e006 b.n 80035b8 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
80035aa: 4b20 ldr r3, [pc, #128] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035ac: 68da ldr r2, [r3, #12]
80035ae: 69bb ldr r3, [r7, #24]
80035b0: 43db mvns r3, r3
80035b2: 491e ldr r1, [pc, #120] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035b4: 4013 ands r3, r2
80035b6: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
80035b8: 683b ldr r3, [r7, #0]
80035ba: 685b ldr r3, [r3, #4]
80035bc: f403 3300 and.w r3, r3, #131072 @ 0x20000
80035c0: 2b00 cmp r3, #0
80035c2: d006 beq.n 80035d2 <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
80035c4: 4b19 ldr r3, [pc, #100] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035c6: 685a ldr r2, [r3, #4]
80035c8: 4918 ldr r1, [pc, #96] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035ca: 69bb ldr r3, [r7, #24]
80035cc: 4313 orrs r3, r2
80035ce: 604b str r3, [r1, #4]
80035d0: e006 b.n 80035e0 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
80035d2: 4b16 ldr r3, [pc, #88] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035d4: 685a ldr r2, [r3, #4]
80035d6: 69bb ldr r3, [r7, #24]
80035d8: 43db mvns r3, r3
80035da: 4914 ldr r1, [pc, #80] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035dc: 4013 ands r3, r2
80035de: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80035e0: 683b ldr r3, [r7, #0]
80035e2: 685b ldr r3, [r3, #4]
80035e4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80035e8: 2b00 cmp r3, #0
80035ea: d021 beq.n 8003630 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
80035ec: 4b0f ldr r3, [pc, #60] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035ee: 681a ldr r2, [r3, #0]
80035f0: 490e ldr r1, [pc, #56] @ (800362c <HAL_GPIO_Init+0x2d0>)
80035f2: 69bb ldr r3, [r7, #24]
80035f4: 4313 orrs r3, r2
80035f6: 600b str r3, [r1, #0]
80035f8: e021 b.n 800363e <HAL_GPIO_Init+0x2e2>
80035fa: bf00 nop
80035fc: 10320000 .word 0x10320000
8003600: 10310000 .word 0x10310000
8003604: 10220000 .word 0x10220000
8003608: 10210000 .word 0x10210000
800360c: 10120000 .word 0x10120000
8003610: 10110000 .word 0x10110000
8003614: 40021000 .word 0x40021000
8003618: 40010000 .word 0x40010000
800361c: 40010800 .word 0x40010800
8003620: 40010c00 .word 0x40010c00
8003624: 40011000 .word 0x40011000
8003628: 40011400 .word 0x40011400
800362c: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8003630: 4b0b ldr r3, [pc, #44] @ (8003660 <HAL_GPIO_Init+0x304>)
8003632: 681a ldr r2, [r3, #0]
8003634: 69bb ldr r3, [r7, #24]
8003636: 43db mvns r3, r3
8003638: 4909 ldr r1, [pc, #36] @ (8003660 <HAL_GPIO_Init+0x304>)
800363a: 4013 ands r3, r2
800363c: 600b str r3, [r1, #0]
}
}
}
position++;
800363e: 6a7b ldr r3, [r7, #36] @ 0x24
8003640: 3301 adds r3, #1
8003642: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003644: 683b ldr r3, [r7, #0]
8003646: 681a ldr r2, [r3, #0]
8003648: 6a7b ldr r3, [r7, #36] @ 0x24
800364a: fa22 f303 lsr.w r3, r2, r3
800364e: 2b00 cmp r3, #0
8003650: f47f ae8e bne.w 8003370 <HAL_GPIO_Init+0x14>
}
}
8003654: bf00 nop
8003656: bf00 nop
8003658: 372c adds r7, #44 @ 0x2c
800365a: 46bd mov sp, r7
800365c: bc80 pop {r7}
800365e: 4770 bx lr
8003660: 40010400 .word 0x40010400
08003664 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8003664: b480 push {r7}
8003666: b085 sub sp, #20
8003668: af00 add r7, sp, #0
800366a: 6078 str r0, [r7, #4]
800366c: 460b mov r3, r1
800366e: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8003670: 687b ldr r3, [r7, #4]
8003672: 689a ldr r2, [r3, #8]
8003674: 887b ldrh r3, [r7, #2]
8003676: 4013 ands r3, r2
8003678: 2b00 cmp r3, #0
800367a: d002 beq.n 8003682 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
800367c: 2301 movs r3, #1
800367e: 73fb strb r3, [r7, #15]
8003680: e001 b.n 8003686 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8003682: 2300 movs r3, #0
8003684: 73fb strb r3, [r7, #15]
}
return bitstatus;
8003686: 7bfb ldrb r3, [r7, #15]
}
8003688: 4618 mov r0, r3
800368a: 3714 adds r7, #20
800368c: 46bd mov sp, r7
800368e: bc80 pop {r7}
8003690: 4770 bx lr
08003692 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003692: b480 push {r7}
8003694: b083 sub sp, #12
8003696: af00 add r7, sp, #0
8003698: 6078 str r0, [r7, #4]
800369a: 460b mov r3, r1
800369c: 807b strh r3, [r7, #2]
800369e: 4613 mov r3, r2
80036a0: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80036a2: 787b ldrb r3, [r7, #1]
80036a4: 2b00 cmp r3, #0
80036a6: d003 beq.n 80036b0 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80036a8: 887a ldrh r2, [r7, #2]
80036aa: 687b ldr r3, [r7, #4]
80036ac: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
80036ae: e003 b.n 80036b8 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
80036b0: 887b ldrh r3, [r7, #2]
80036b2: 041a lsls r2, r3, #16
80036b4: 687b ldr r3, [r7, #4]
80036b6: 611a str r2, [r3, #16]
}
80036b8: bf00 nop
80036ba: 370c adds r7, #12
80036bc: 46bd mov sp, r7
80036be: bc80 pop {r7}
80036c0: 4770 bx lr
080036c2 <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80036c2: b480 push {r7}
80036c4: b085 sub sp, #20
80036c6: af00 add r7, sp, #0
80036c8: 6078 str r0, [r7, #4]
80036ca: 460b mov r3, r1
80036cc: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
80036ce: 687b ldr r3, [r7, #4]
80036d0: 68db ldr r3, [r3, #12]
80036d2: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
80036d4: 887a ldrh r2, [r7, #2]
80036d6: 68fb ldr r3, [r7, #12]
80036d8: 4013 ands r3, r2
80036da: 041a lsls r2, r3, #16
80036dc: 68fb ldr r3, [r7, #12]
80036de: 43d9 mvns r1, r3
80036e0: 887b ldrh r3, [r7, #2]
80036e2: 400b ands r3, r1
80036e4: 431a orrs r2, r3
80036e6: 687b ldr r3, [r7, #4]
80036e8: 611a str r2, [r3, #16]
}
80036ea: bf00 nop
80036ec: 3714 adds r7, #20
80036ee: 46bd mov sp, r7
80036f0: bc80 pop {r7}
80036f2: 4770 bx lr
080036f4 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
80036f4: b580 push {r7, lr}
80036f6: b084 sub sp, #16
80036f8: af00 add r7, sp, #0
80036fa: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
80036fc: 687b ldr r3, [r7, #4]
80036fe: 2b00 cmp r3, #0
8003700: d101 bne.n 8003706 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8003702: 2301 movs r3, #1
8003704: e0e8 b.n 80038d8 <HAL_PCD_Init+0x1e4>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8003706: 687b ldr r3, [r7, #4]
8003708: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
800370c: b2db uxtb r3, r3
800370e: 2b00 cmp r3, #0
8003710: d106 bne.n 8003720 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8003712: 687b ldr r3, [r7, #4]
8003714: 2200 movs r2, #0
8003716: f883 2290 strb.w r2, [r3, #656] @ 0x290
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
800371a: 6878 ldr r0, [r7, #4]
800371c: f007 face bl 800acbc <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8003720: 687b ldr r3, [r7, #4]
8003722: 2203 movs r2, #3
8003724: f883 2291 strb.w r2, [r3, #657] @ 0x291
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
8003728: 687b ldr r3, [r7, #4]
800372a: 2200 movs r2, #0
800372c: 715a strb r2, [r3, #5]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
800372e: 687b ldr r3, [r7, #4]
8003730: 681b ldr r3, [r3, #0]
8003732: 4618 mov r0, r3
8003734: f003 f973 bl 8006a1e <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8003738: 687b ldr r3, [r7, #4]
800373a: 6818 ldr r0, [r3, #0]
800373c: 687b ldr r3, [r7, #4]
800373e: 3304 adds r3, #4
8003740: cb0e ldmia r3, {r1, r2, r3}
8003742: f003 f949 bl 80069d8 <USB_CoreInit>
8003746: 4603 mov r3, r0
8003748: 2b00 cmp r3, #0
800374a: d005 beq.n 8003758 <HAL_PCD_Init+0x64>
{
hpcd->State = HAL_PCD_STATE_ERROR;
800374c: 687b ldr r3, [r7, #4]
800374e: 2202 movs r2, #2
8003750: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8003754: 2301 movs r3, #1
8003756: e0bf b.n 80038d8 <HAL_PCD_Init+0x1e4>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
8003758: 687b ldr r3, [r7, #4]
800375a: 681b ldr r3, [r3, #0]
800375c: 2100 movs r1, #0
800375e: 4618 mov r0, r3
8003760: f003 f977 bl 8006a52 <USB_SetCurrentMode>
8003764: 4603 mov r3, r0
8003766: 2b00 cmp r3, #0
8003768: d005 beq.n 8003776 <HAL_PCD_Init+0x82>
{
hpcd->State = HAL_PCD_STATE_ERROR;
800376a: 687b ldr r3, [r7, #4]
800376c: 2202 movs r2, #2
800376e: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8003772: 2301 movs r3, #1
8003774: e0b0 b.n 80038d8 <HAL_PCD_Init+0x1e4>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003776: 2300 movs r3, #0
8003778: 73fb strb r3, [r7, #15]
800377a: e03e b.n 80037fa <HAL_PCD_Init+0x106>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
800377c: 7bfa ldrb r2, [r7, #15]
800377e: 6879 ldr r1, [r7, #4]
8003780: 4613 mov r3, r2
8003782: 009b lsls r3, r3, #2
8003784: 4413 add r3, r2
8003786: 00db lsls r3, r3, #3
8003788: 440b add r3, r1
800378a: 3311 adds r3, #17
800378c: 2201 movs r2, #1
800378e: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8003790: 7bfa ldrb r2, [r7, #15]
8003792: 6879 ldr r1, [r7, #4]
8003794: 4613 mov r3, r2
8003796: 009b lsls r3, r3, #2
8003798: 4413 add r3, r2
800379a: 00db lsls r3, r3, #3
800379c: 440b add r3, r1
800379e: 3310 adds r3, #16
80037a0: 7bfa ldrb r2, [r7, #15]
80037a2: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
80037a4: 7bfa ldrb r2, [r7, #15]
80037a6: 6879 ldr r1, [r7, #4]
80037a8: 4613 mov r3, r2
80037aa: 009b lsls r3, r3, #2
80037ac: 4413 add r3, r2
80037ae: 00db lsls r3, r3, #3
80037b0: 440b add r3, r1
80037b2: 3313 adds r3, #19
80037b4: 2200 movs r2, #0
80037b6: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
80037b8: 7bfa ldrb r2, [r7, #15]
80037ba: 6879 ldr r1, [r7, #4]
80037bc: 4613 mov r3, r2
80037be: 009b lsls r3, r3, #2
80037c0: 4413 add r3, r2
80037c2: 00db lsls r3, r3, #3
80037c4: 440b add r3, r1
80037c6: 3320 adds r3, #32
80037c8: 2200 movs r2, #0
80037ca: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
80037cc: 7bfa ldrb r2, [r7, #15]
80037ce: 6879 ldr r1, [r7, #4]
80037d0: 4613 mov r3, r2
80037d2: 009b lsls r3, r3, #2
80037d4: 4413 add r3, r2
80037d6: 00db lsls r3, r3, #3
80037d8: 440b add r3, r1
80037da: 3324 adds r3, #36 @ 0x24
80037dc: 2200 movs r2, #0
80037de: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
80037e0: 7bfb ldrb r3, [r7, #15]
80037e2: 6879 ldr r1, [r7, #4]
80037e4: 1c5a adds r2, r3, #1
80037e6: 4613 mov r3, r2
80037e8: 009b lsls r3, r3, #2
80037ea: 4413 add r3, r2
80037ec: 00db lsls r3, r3, #3
80037ee: 440b add r3, r1
80037f0: 2200 movs r2, #0
80037f2: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80037f4: 7bfb ldrb r3, [r7, #15]
80037f6: 3301 adds r3, #1
80037f8: 73fb strb r3, [r7, #15]
80037fa: 687b ldr r3, [r7, #4]
80037fc: 791b ldrb r3, [r3, #4]
80037fe: 7bfa ldrb r2, [r7, #15]
8003800: 429a cmp r2, r3
8003802: d3bb bcc.n 800377c <HAL_PCD_Init+0x88>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8003804: 2300 movs r3, #0
8003806: 73fb strb r3, [r7, #15]
8003808: e044 b.n 8003894 <HAL_PCD_Init+0x1a0>
{
hpcd->OUT_ep[i].is_in = 0U;
800380a: 7bfa ldrb r2, [r7, #15]
800380c: 6879 ldr r1, [r7, #4]
800380e: 4613 mov r3, r2
8003810: 009b lsls r3, r3, #2
8003812: 4413 add r3, r2
8003814: 00db lsls r3, r3, #3
8003816: 440b add r3, r1
8003818: f203 1351 addw r3, r3, #337 @ 0x151
800381c: 2200 movs r2, #0
800381e: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8003820: 7bfa ldrb r2, [r7, #15]
8003822: 6879 ldr r1, [r7, #4]
8003824: 4613 mov r3, r2
8003826: 009b lsls r3, r3, #2
8003828: 4413 add r3, r2
800382a: 00db lsls r3, r3, #3
800382c: 440b add r3, r1
800382e: f503 73a8 add.w r3, r3, #336 @ 0x150
8003832: 7bfa ldrb r2, [r7, #15]
8003834: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8003836: 7bfa ldrb r2, [r7, #15]
8003838: 6879 ldr r1, [r7, #4]
800383a: 4613 mov r3, r2
800383c: 009b lsls r3, r3, #2
800383e: 4413 add r3, r2
8003840: 00db lsls r3, r3, #3
8003842: 440b add r3, r1
8003844: f203 1353 addw r3, r3, #339 @ 0x153
8003848: 2200 movs r2, #0
800384a: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
800384c: 7bfa ldrb r2, [r7, #15]
800384e: 6879 ldr r1, [r7, #4]
8003850: 4613 mov r3, r2
8003852: 009b lsls r3, r3, #2
8003854: 4413 add r3, r2
8003856: 00db lsls r3, r3, #3
8003858: 440b add r3, r1
800385a: f503 73b0 add.w r3, r3, #352 @ 0x160
800385e: 2200 movs r2, #0
8003860: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8003862: 7bfa ldrb r2, [r7, #15]
8003864: 6879 ldr r1, [r7, #4]
8003866: 4613 mov r3, r2
8003868: 009b lsls r3, r3, #2
800386a: 4413 add r3, r2
800386c: 00db lsls r3, r3, #3
800386e: 440b add r3, r1
8003870: f503 73b2 add.w r3, r3, #356 @ 0x164
8003874: 2200 movs r2, #0
8003876: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8003878: 7bfa ldrb r2, [r7, #15]
800387a: 6879 ldr r1, [r7, #4]
800387c: 4613 mov r3, r2
800387e: 009b lsls r3, r3, #2
8003880: 4413 add r3, r2
8003882: 00db lsls r3, r3, #3
8003884: 440b add r3, r1
8003886: f503 73b4 add.w r3, r3, #360 @ 0x168
800388a: 2200 movs r2, #0
800388c: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
800388e: 7bfb ldrb r3, [r7, #15]
8003890: 3301 adds r3, #1
8003892: 73fb strb r3, [r7, #15]
8003894: 687b ldr r3, [r7, #4]
8003896: 791b ldrb r3, [r3, #4]
8003898: 7bfa ldrb r2, [r7, #15]
800389a: 429a cmp r2, r3
800389c: d3b5 bcc.n 800380a <HAL_PCD_Init+0x116>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
800389e: 687b ldr r3, [r7, #4]
80038a0: 6818 ldr r0, [r3, #0]
80038a2: 687b ldr r3, [r7, #4]
80038a4: 3304 adds r3, #4
80038a6: cb0e ldmia r3, {r1, r2, r3}
80038a8: f003 f8df bl 8006a6a <USB_DevInit>
80038ac: 4603 mov r3, r0
80038ae: 2b00 cmp r3, #0
80038b0: d005 beq.n 80038be <HAL_PCD_Init+0x1ca>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80038b2: 687b ldr r3, [r7, #4]
80038b4: 2202 movs r2, #2
80038b6: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
80038ba: 2301 movs r3, #1
80038bc: e00c b.n 80038d8 <HAL_PCD_Init+0x1e4>
}
hpcd->USB_Address = 0U;
80038be: 687b ldr r3, [r7, #4]
80038c0: 2200 movs r2, #0
80038c2: 735a strb r2, [r3, #13]
hpcd->State = HAL_PCD_STATE_READY;
80038c4: 687b ldr r3, [r7, #4]
80038c6: 2201 movs r2, #1
80038c8: f883 2291 strb.w r2, [r3, #657] @ 0x291
(void)USB_DevDisconnect(hpcd->Instance);
80038cc: 687b ldr r3, [r7, #4]
80038ce: 681b ldr r3, [r3, #0]
80038d0: 4618 mov r0, r3
80038d2: f005 fb5e bl 8008f92 <USB_DevDisconnect>
return HAL_OK;
80038d6: 2300 movs r3, #0
}
80038d8: 4618 mov r0, r3
80038da: 3710 adds r7, #16
80038dc: 46bd mov sp, r7
80038de: bd80 pop {r7, pc}
080038e0 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
80038e0: b580 push {r7, lr}
80038e2: b082 sub sp, #8
80038e4: af00 add r7, sp, #0
80038e6: 6078 str r0, [r7, #4]
__HAL_LOCK(hpcd);
80038e8: 687b ldr r3, [r7, #4]
80038ea: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
80038ee: 2b01 cmp r3, #1
80038f0: d101 bne.n 80038f6 <HAL_PCD_Start+0x16>
80038f2: 2302 movs r3, #2
80038f4: e016 b.n 8003924 <HAL_PCD_Start+0x44>
80038f6: 687b ldr r3, [r7, #4]
80038f8: 2201 movs r2, #1
80038fa: f883 2290 strb.w r2, [r3, #656] @ 0x290
__HAL_PCD_ENABLE(hpcd);
80038fe: 687b ldr r3, [r7, #4]
8003900: 681b ldr r3, [r3, #0]
8003902: 4618 mov r0, r3
8003904: f003 f875 bl 80069f2 <USB_EnableGlobalInt>
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
8003908: 2101 movs r1, #1
800390a: 6878 ldr r0, [r7, #4]
800390c: f007 fc49 bl 800b1a2 <HAL_PCDEx_SetConnectionState>
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
8003910: 687b ldr r3, [r7, #4]
8003912: 681b ldr r3, [r3, #0]
8003914: 4618 mov r0, r3
8003916: f005 fb32 bl 8008f7e <USB_DevConnect>
__HAL_UNLOCK(hpcd);
800391a: 687b ldr r3, [r7, #4]
800391c: 2200 movs r2, #0
800391e: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003922: 2300 movs r3, #0
}
8003924: 4618 mov r0, r3
8003926: 3708 adds r7, #8
8003928: 46bd mov sp, r7
800392a: bd80 pop {r7, pc}
0800392c <HAL_PCD_IRQHandler>:
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
800392c: b580 push {r7, lr}
800392e: b088 sub sp, #32
8003930: af00 add r7, sp, #0
8003932: 6078 str r0, [r7, #4]
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
8003934: 687b ldr r3, [r7, #4]
8003936: 681b ldr r3, [r3, #0]
8003938: 4618 mov r0, r3
800393a: f005 fb34 bl 8008fa6 <USB_ReadInterrupts>
800393e: 61b8 str r0, [r7, #24]
uint16_t store_ep[8];
uint8_t i;
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
8003940: 69bb ldr r3, [r7, #24]
8003942: f403 4300 and.w r3, r3, #32768 @ 0x8000
8003946: 2b00 cmp r3, #0
8003948: d003 beq.n 8003952 <HAL_PCD_IRQHandler+0x26>
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
800394a: 6878 ldr r0, [r7, #4]
800394c: f000 fb1a bl 8003f84 <PCD_EP_ISR_Handler>
return;
8003950: e119 b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
8003952: 69bb ldr r3, [r7, #24]
8003954: f403 6380 and.w r3, r3, #1024 @ 0x400
8003958: 2b00 cmp r3, #0
800395a: d013 beq.n 8003984 <HAL_PCD_IRQHandler+0x58>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
800395c: 687b ldr r3, [r7, #4]
800395e: 681b ldr r3, [r3, #0]
8003960: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003964: b29a uxth r2, r3
8003966: 687b ldr r3, [r7, #4]
8003968: 681b ldr r3, [r3, #0]
800396a: f422 6280 bic.w r2, r2, #1024 @ 0x400
800396e: b292 uxth r2, r2
8003970: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
8003974: 6878 ldr r0, [r7, #4]
8003976: f007 fa1c bl 800adb2 <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
800397a: 2100 movs r1, #0
800397c: 6878 ldr r0, [r7, #4]
800397e: f000 f905 bl 8003b8c <HAL_PCD_SetAddress>
return;
8003982: e100 b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
8003984: 69bb ldr r3, [r7, #24]
8003986: f403 4380 and.w r3, r3, #16384 @ 0x4000
800398a: 2b00 cmp r3, #0
800398c: d00c beq.n 80039a8 <HAL_PCD_IRQHandler+0x7c>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
800398e: 687b ldr r3, [r7, #4]
8003990: 681b ldr r3, [r3, #0]
8003992: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003996: b29a uxth r2, r3
8003998: 687b ldr r3, [r7, #4]
800399a: 681b ldr r3, [r3, #0]
800399c: f422 4280 bic.w r2, r2, #16384 @ 0x4000
80039a0: b292 uxth r2, r2
80039a2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
80039a6: e0ee b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
80039a8: 69bb ldr r3, [r7, #24]
80039aa: f403 5300 and.w r3, r3, #8192 @ 0x2000
80039ae: 2b00 cmp r3, #0
80039b0: d00c beq.n 80039cc <HAL_PCD_IRQHandler+0xa0>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
80039b2: 687b ldr r3, [r7, #4]
80039b4: 681b ldr r3, [r3, #0]
80039b6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80039ba: b29a uxth r2, r3
80039bc: 687b ldr r3, [r7, #4]
80039be: 681b ldr r3, [r3, #0]
80039c0: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80039c4: b292 uxth r2, r2
80039c6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
80039ca: e0dc b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
80039cc: 69bb ldr r3, [r7, #24]
80039ce: f403 5380 and.w r3, r3, #4096 @ 0x1000
80039d2: 2b00 cmp r3, #0
80039d4: d027 beq.n 8003a26 <HAL_PCD_IRQHandler+0xfa>
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
80039d6: 687b ldr r3, [r7, #4]
80039d8: 681b ldr r3, [r3, #0]
80039da: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
80039de: b29a uxth r2, r3
80039e0: 687b ldr r3, [r7, #4]
80039e2: 681b ldr r3, [r3, #0]
80039e4: f022 0204 bic.w r2, r2, #4
80039e8: b292 uxth r2, r2
80039ea: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
80039ee: 687b ldr r3, [r7, #4]
80039f0: 681b ldr r3, [r3, #0]
80039f2: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
80039f6: b29a uxth r2, r3
80039f8: 687b ldr r3, [r7, #4]
80039fa: 681b ldr r3, [r3, #0]
80039fc: f022 0208 bic.w r2, r2, #8
8003a00: b292 uxth r2, r2
8003a02: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
8003a06: 6878 ldr r0, [r7, #4]
8003a08: f007 fa0c bl 800ae24 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
8003a0c: 687b ldr r3, [r7, #4]
8003a0e: 681b ldr r3, [r3, #0]
8003a10: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003a14: b29a uxth r2, r3
8003a16: 687b ldr r3, [r7, #4]
8003a18: 681b ldr r3, [r3, #0]
8003a1a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8003a1e: b292 uxth r2, r2
8003a20: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8003a24: e0af b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
8003a26: 69bb ldr r3, [r7, #24]
8003a28: f403 6300 and.w r3, r3, #2048 @ 0x800
8003a2c: 2b00 cmp r3, #0
8003a2e: f000 8083 beq.w 8003b38 <HAL_PCD_IRQHandler+0x20c>
{
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint registers */
for (i = 0U; i < 8U; i++)
8003a32: 2300 movs r3, #0
8003a34: 77fb strb r3, [r7, #31]
8003a36: e010 b.n 8003a5a <HAL_PCD_IRQHandler+0x12e>
{
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
8003a38: 687b ldr r3, [r7, #4]
8003a3a: 681b ldr r3, [r3, #0]
8003a3c: 461a mov r2, r3
8003a3e: 7ffb ldrb r3, [r7, #31]
8003a40: 009b lsls r3, r3, #2
8003a42: 441a add r2, r3
8003a44: 7ffb ldrb r3, [r7, #31]
8003a46: 8812 ldrh r2, [r2, #0]
8003a48: b292 uxth r2, r2
8003a4a: 005b lsls r3, r3, #1
8003a4c: 3320 adds r3, #32
8003a4e: 443b add r3, r7
8003a50: f823 2c18 strh.w r2, [r3, #-24]
for (i = 0U; i < 8U; i++)
8003a54: 7ffb ldrb r3, [r7, #31]
8003a56: 3301 adds r3, #1
8003a58: 77fb strb r3, [r7, #31]
8003a5a: 7ffb ldrb r3, [r7, #31]
8003a5c: 2b07 cmp r3, #7
8003a5e: d9eb bls.n 8003a38 <HAL_PCD_IRQHandler+0x10c>
}
/* FORCE RESET */
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
8003a60: 687b ldr r3, [r7, #4]
8003a62: 681b ldr r3, [r3, #0]
8003a64: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003a68: b29a uxth r2, r3
8003a6a: 687b ldr r3, [r7, #4]
8003a6c: 681b ldr r3, [r3, #0]
8003a6e: f042 0201 orr.w r2, r2, #1
8003a72: b292 uxth r2, r2
8003a74: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CLEAR RESET */
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
8003a78: 687b ldr r3, [r7, #4]
8003a7a: 681b ldr r3, [r3, #0]
8003a7c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003a80: b29a uxth r2, r3
8003a82: 687b ldr r3, [r7, #4]
8003a84: 681b ldr r3, [r3, #0]
8003a86: f022 0201 bic.w r2, r2, #1
8003a8a: b292 uxth r2, r2
8003a8c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* wait for reset flag in ISTR */
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
8003a90: bf00 nop
8003a92: 687b ldr r3, [r7, #4]
8003a94: 681b ldr r3, [r3, #0]
8003a96: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003a9a: b29b uxth r3, r3
8003a9c: f403 6380 and.w r3, r3, #1024 @ 0x400
8003aa0: 2b00 cmp r3, #0
8003aa2: d0f6 beq.n 8003a92 <HAL_PCD_IRQHandler+0x166>
{
}
/* Clear Reset Flag */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8003aa4: 687b ldr r3, [r7, #4]
8003aa6: 681b ldr r3, [r3, #0]
8003aa8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003aac: b29a uxth r2, r3
8003aae: 687b ldr r3, [r7, #4]
8003ab0: 681b ldr r3, [r3, #0]
8003ab2: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003ab6: b292 uxth r2, r2
8003ab8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Restore Registre */
for (i = 0U; i < 8U; i++)
8003abc: 2300 movs r3, #0
8003abe: 77fb strb r3, [r7, #31]
8003ac0: e00f b.n 8003ae2 <HAL_PCD_IRQHandler+0x1b6>
{
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
8003ac2: 7ffb ldrb r3, [r7, #31]
8003ac4: 687a ldr r2, [r7, #4]
8003ac6: 6812 ldr r2, [r2, #0]
8003ac8: 4611 mov r1, r2
8003aca: 7ffa ldrb r2, [r7, #31]
8003acc: 0092 lsls r2, r2, #2
8003ace: 440a add r2, r1
8003ad0: 005b lsls r3, r3, #1
8003ad2: 3320 adds r3, #32
8003ad4: 443b add r3, r7
8003ad6: f833 3c18 ldrh.w r3, [r3, #-24]
8003ada: 8013 strh r3, [r2, #0]
for (i = 0U; i < 8U; i++)
8003adc: 7ffb ldrb r3, [r7, #31]
8003ade: 3301 adds r3, #1
8003ae0: 77fb strb r3, [r7, #31]
8003ae2: 7ffb ldrb r3, [r7, #31]
8003ae4: 2b07 cmp r3, #7
8003ae6: d9ec bls.n 8003ac2 <HAL_PCD_IRQHandler+0x196>
}
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
8003ae8: 687b ldr r3, [r7, #4]
8003aea: 681b ldr r3, [r3, #0]
8003aec: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003af0: b29a uxth r2, r3
8003af2: 687b ldr r3, [r7, #4]
8003af4: 681b ldr r3, [r3, #0]
8003af6: f042 0208 orr.w r2, r2, #8
8003afa: b292 uxth r2, r2
8003afc: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
8003b00: 687b ldr r3, [r7, #4]
8003b02: 681b ldr r3, [r3, #0]
8003b04: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003b08: b29a uxth r2, r3
8003b0a: 687b ldr r3, [r7, #4]
8003b0c: 681b ldr r3, [r3, #0]
8003b0e: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003b12: b292 uxth r2, r2
8003b14: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
8003b18: 687b ldr r3, [r7, #4]
8003b1a: 681b ldr r3, [r3, #0]
8003b1c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8003b20: b29a uxth r2, r3
8003b22: 687b ldr r3, [r7, #4]
8003b24: 681b ldr r3, [r3, #0]
8003b26: f042 0204 orr.w r2, r2, #4
8003b2a: b292 uxth r2, r2
8003b2c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
8003b30: 6878 ldr r0, [r7, #4]
8003b32: f007 f95d bl 800adf0 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8003b36: e026 b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
8003b38: 69bb ldr r3, [r7, #24]
8003b3a: f403 7300 and.w r3, r3, #512 @ 0x200
8003b3e: 2b00 cmp r3, #0
8003b40: d00f beq.n 8003b62 <HAL_PCD_IRQHandler+0x236>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
8003b42: 687b ldr r3, [r7, #4]
8003b44: 681b ldr r3, [r3, #0]
8003b46: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003b4a: b29a uxth r2, r3
8003b4c: 687b ldr r3, [r7, #4]
8003b4e: 681b ldr r3, [r3, #0]
8003b50: f422 7200 bic.w r2, r2, #512 @ 0x200
8003b54: b292 uxth r2, r2
8003b56: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
8003b5a: 6878 ldr r0, [r7, #4]
8003b5c: f007 f91b bl 800ad96 <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8003b60: e011 b.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
8003b62: 69bb ldr r3, [r7, #24]
8003b64: f403 7380 and.w r3, r3, #256 @ 0x100
8003b68: 2b00 cmp r3, #0
8003b6a: d00c beq.n 8003b86 <HAL_PCD_IRQHandler+0x25a>
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
8003b6c: 687b ldr r3, [r7, #4]
8003b6e: 681b ldr r3, [r3, #0]
8003b70: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003b74: b29a uxth r2, r3
8003b76: 687b ldr r3, [r7, #4]
8003b78: 681b ldr r3, [r3, #0]
8003b7a: f422 7280 bic.w r2, r2, #256 @ 0x100
8003b7e: b292 uxth r2, r2
8003b80: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8003b84: bf00 nop
}
}
8003b86: 3720 adds r7, #32
8003b88: 46bd mov sp, r7
8003b8a: bd80 pop {r7, pc}
08003b8c <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
8003b8c: b580 push {r7, lr}
8003b8e: b082 sub sp, #8
8003b90: af00 add r7, sp, #0
8003b92: 6078 str r0, [r7, #4]
8003b94: 460b mov r3, r1
8003b96: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
8003b98: 687b ldr r3, [r7, #4]
8003b9a: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003b9e: 2b01 cmp r3, #1
8003ba0: d101 bne.n 8003ba6 <HAL_PCD_SetAddress+0x1a>
8003ba2: 2302 movs r3, #2
8003ba4: e012 b.n 8003bcc <HAL_PCD_SetAddress+0x40>
8003ba6: 687b ldr r3, [r7, #4]
8003ba8: 2201 movs r2, #1
8003baa: f883 2290 strb.w r2, [r3, #656] @ 0x290
hpcd->USB_Address = address;
8003bae: 687b ldr r3, [r7, #4]
8003bb0: 78fa ldrb r2, [r7, #3]
8003bb2: 735a strb r2, [r3, #13]
(void)USB_SetDevAddress(hpcd->Instance, address);
8003bb4: 687b ldr r3, [r7, #4]
8003bb6: 681b ldr r3, [r3, #0]
8003bb8: 78fa ldrb r2, [r7, #3]
8003bba: 4611 mov r1, r2
8003bbc: 4618 mov r0, r3
8003bbe: f005 f9cb bl 8008f58 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8003bc2: 687b ldr r3, [r7, #4]
8003bc4: 2200 movs r2, #0
8003bc6: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003bca: 2300 movs r3, #0
}
8003bcc: 4618 mov r0, r3
8003bce: 3708 adds r7, #8
8003bd0: 46bd mov sp, r7
8003bd2: bd80 pop {r7, pc}
08003bd4 <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
8003bd4: b580 push {r7, lr}
8003bd6: b084 sub sp, #16
8003bd8: af00 add r7, sp, #0
8003bda: 6078 str r0, [r7, #4]
8003bdc: 4608 mov r0, r1
8003bde: 4611 mov r1, r2
8003be0: 461a mov r2, r3
8003be2: 4603 mov r3, r0
8003be4: 70fb strb r3, [r7, #3]
8003be6: 460b mov r3, r1
8003be8: 803b strh r3, [r7, #0]
8003bea: 4613 mov r3, r2
8003bec: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8003bee: 2300 movs r3, #0
8003bf0: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8003bf2: f997 3003 ldrsb.w r3, [r7, #3]
8003bf6: 2b00 cmp r3, #0
8003bf8: da0e bge.n 8003c18 <HAL_PCD_EP_Open+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003bfa: 78fb ldrb r3, [r7, #3]
8003bfc: f003 0207 and.w r2, r3, #7
8003c00: 4613 mov r3, r2
8003c02: 009b lsls r3, r3, #2
8003c04: 4413 add r3, r2
8003c06: 00db lsls r3, r3, #3
8003c08: 3310 adds r3, #16
8003c0a: 687a ldr r2, [r7, #4]
8003c0c: 4413 add r3, r2
8003c0e: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003c10: 68fb ldr r3, [r7, #12]
8003c12: 2201 movs r2, #1
8003c14: 705a strb r2, [r3, #1]
8003c16: e00e b.n 8003c36 <HAL_PCD_EP_Open+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003c18: 78fb ldrb r3, [r7, #3]
8003c1a: f003 0207 and.w r2, r3, #7
8003c1e: 4613 mov r3, r2
8003c20: 009b lsls r3, r3, #2
8003c22: 4413 add r3, r2
8003c24: 00db lsls r3, r3, #3
8003c26: f503 73a8 add.w r3, r3, #336 @ 0x150
8003c2a: 687a ldr r2, [r7, #4]
8003c2c: 4413 add r3, r2
8003c2e: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003c30: 68fb ldr r3, [r7, #12]
8003c32: 2200 movs r2, #0
8003c34: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8003c36: 78fb ldrb r3, [r7, #3]
8003c38: f003 0307 and.w r3, r3, #7
8003c3c: b2da uxtb r2, r3
8003c3e: 68fb ldr r3, [r7, #12]
8003c40: 701a strb r2, [r3, #0]
ep->maxpacket = ep_mps;
8003c42: 883a ldrh r2, [r7, #0]
8003c44: 68fb ldr r3, [r7, #12]
8003c46: 611a str r2, [r3, #16]
ep->type = ep_type;
8003c48: 68fb ldr r3, [r7, #12]
8003c4a: 78ba ldrb r2, [r7, #2]
8003c4c: 70da strb r2, [r3, #3]
ep->tx_fifo_num = ep->num;
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
8003c4e: 78bb ldrb r3, [r7, #2]
8003c50: 2b02 cmp r3, #2
8003c52: d102 bne.n 8003c5a <HAL_PCD_EP_Open+0x86>
{
ep->data_pid_start = 0U;
8003c54: 68fb ldr r3, [r7, #12]
8003c56: 2200 movs r2, #0
8003c58: 711a strb r2, [r3, #4]
}
__HAL_LOCK(hpcd);
8003c5a: 687b ldr r3, [r7, #4]
8003c5c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003c60: 2b01 cmp r3, #1
8003c62: d101 bne.n 8003c68 <HAL_PCD_EP_Open+0x94>
8003c64: 2302 movs r3, #2
8003c66: e00e b.n 8003c86 <HAL_PCD_EP_Open+0xb2>
8003c68: 687b ldr r3, [r7, #4]
8003c6a: 2201 movs r2, #1
8003c6c: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
8003c70: 687b ldr r3, [r7, #4]
8003c72: 681b ldr r3, [r3, #0]
8003c74: 68f9 ldr r1, [r7, #12]
8003c76: 4618 mov r0, r3
8003c78: f002 ff14 bl 8006aa4 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
8003c7c: 687b ldr r3, [r7, #4]
8003c7e: 2200 movs r2, #0
8003c80: f883 2290 strb.w r2, [r3, #656] @ 0x290
return ret;
8003c84: 7afb ldrb r3, [r7, #11]
}
8003c86: 4618 mov r0, r3
8003c88: 3710 adds r7, #16
8003c8a: 46bd mov sp, r7
8003c8c: bd80 pop {r7, pc}
08003c8e <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8003c8e: b580 push {r7, lr}
8003c90: b084 sub sp, #16
8003c92: af00 add r7, sp, #0
8003c94: 6078 str r0, [r7, #4]
8003c96: 460b mov r3, r1
8003c98: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8003c9a: f997 3003 ldrsb.w r3, [r7, #3]
8003c9e: 2b00 cmp r3, #0
8003ca0: da0e bge.n 8003cc0 <HAL_PCD_EP_Close+0x32>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003ca2: 78fb ldrb r3, [r7, #3]
8003ca4: f003 0207 and.w r2, r3, #7
8003ca8: 4613 mov r3, r2
8003caa: 009b lsls r3, r3, #2
8003cac: 4413 add r3, r2
8003cae: 00db lsls r3, r3, #3
8003cb0: 3310 adds r3, #16
8003cb2: 687a ldr r2, [r7, #4]
8003cb4: 4413 add r3, r2
8003cb6: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003cb8: 68fb ldr r3, [r7, #12]
8003cba: 2201 movs r2, #1
8003cbc: 705a strb r2, [r3, #1]
8003cbe: e00e b.n 8003cde <HAL_PCD_EP_Close+0x50>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003cc0: 78fb ldrb r3, [r7, #3]
8003cc2: f003 0207 and.w r2, r3, #7
8003cc6: 4613 mov r3, r2
8003cc8: 009b lsls r3, r3, #2
8003cca: 4413 add r3, r2
8003ccc: 00db lsls r3, r3, #3
8003cce: f503 73a8 add.w r3, r3, #336 @ 0x150
8003cd2: 687a ldr r2, [r7, #4]
8003cd4: 4413 add r3, r2
8003cd6: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003cd8: 68fb ldr r3, [r7, #12]
8003cda: 2200 movs r2, #0
8003cdc: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8003cde: 78fb ldrb r3, [r7, #3]
8003ce0: f003 0307 and.w r3, r3, #7
8003ce4: b2da uxtb r2, r3
8003ce6: 68fb ldr r3, [r7, #12]
8003ce8: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8003cea: 687b ldr r3, [r7, #4]
8003cec: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003cf0: 2b01 cmp r3, #1
8003cf2: d101 bne.n 8003cf8 <HAL_PCD_EP_Close+0x6a>
8003cf4: 2302 movs r3, #2
8003cf6: e00e b.n 8003d16 <HAL_PCD_EP_Close+0x88>
8003cf8: 687b ldr r3, [r7, #4]
8003cfa: 2201 movs r2, #1
8003cfc: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
8003d00: 687b ldr r3, [r7, #4]
8003d02: 681b ldr r3, [r3, #0]
8003d04: 68f9 ldr r1, [r7, #12]
8003d06: 4618 mov r0, r3
8003d08: f003 fa8c bl 8007224 <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
8003d0c: 687b ldr r3, [r7, #4]
8003d0e: 2200 movs r2, #0
8003d10: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003d14: 2300 movs r3, #0
}
8003d16: 4618 mov r0, r3
8003d18: 3710 adds r7, #16
8003d1a: 46bd mov sp, r7
8003d1c: bd80 pop {r7, pc}
08003d1e <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8003d1e: b580 push {r7, lr}
8003d20: b086 sub sp, #24
8003d22: af00 add r7, sp, #0
8003d24: 60f8 str r0, [r7, #12]
8003d26: 607a str r2, [r7, #4]
8003d28: 603b str r3, [r7, #0]
8003d2a: 460b mov r3, r1
8003d2c: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003d2e: 7afb ldrb r3, [r7, #11]
8003d30: f003 0207 and.w r2, r3, #7
8003d34: 4613 mov r3, r2
8003d36: 009b lsls r3, r3, #2
8003d38: 4413 add r3, r2
8003d3a: 00db lsls r3, r3, #3
8003d3c: f503 73a8 add.w r3, r3, #336 @ 0x150
8003d40: 68fa ldr r2, [r7, #12]
8003d42: 4413 add r3, r2
8003d44: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8003d46: 697b ldr r3, [r7, #20]
8003d48: 687a ldr r2, [r7, #4]
8003d4a: 615a str r2, [r3, #20]
ep->xfer_len = len;
8003d4c: 697b ldr r3, [r7, #20]
8003d4e: 683a ldr r2, [r7, #0]
8003d50: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
8003d52: 697b ldr r3, [r7, #20]
8003d54: 2200 movs r2, #0
8003d56: 61da str r2, [r3, #28]
ep->is_in = 0U;
8003d58: 697b ldr r3, [r7, #20]
8003d5a: 2200 movs r2, #0
8003d5c: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8003d5e: 7afb ldrb r3, [r7, #11]
8003d60: f003 0307 and.w r3, r3, #7
8003d64: b2da uxtb r2, r3
8003d66: 697b ldr r3, [r7, #20]
8003d68: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8003d6a: 68fb ldr r3, [r7, #12]
8003d6c: 681b ldr r3, [r3, #0]
8003d6e: 6979 ldr r1, [r7, #20]
8003d70: 4618 mov r0, r3
8003d72: f003 fc43 bl 80075fc <USB_EPStartXfer>
return HAL_OK;
8003d76: 2300 movs r3, #0
}
8003d78: 4618 mov r0, r3
8003d7a: 3718 adds r7, #24
8003d7c: 46bd mov sp, r7
8003d7e: bd80 pop {r7, pc}
08003d80 <HAL_PCD_EP_GetRxCount>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
8003d80: b480 push {r7}
8003d82: b083 sub sp, #12
8003d84: af00 add r7, sp, #0
8003d86: 6078 str r0, [r7, #4]
8003d88: 460b mov r3, r1
8003d8a: 70fb strb r3, [r7, #3]
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
8003d8c: 78fb ldrb r3, [r7, #3]
8003d8e: f003 0207 and.w r2, r3, #7
8003d92: 6879 ldr r1, [r7, #4]
8003d94: 4613 mov r3, r2
8003d96: 009b lsls r3, r3, #2
8003d98: 4413 add r3, r2
8003d9a: 00db lsls r3, r3, #3
8003d9c: 440b add r3, r1
8003d9e: f503 73b6 add.w r3, r3, #364 @ 0x16c
8003da2: 681b ldr r3, [r3, #0]
}
8003da4: 4618 mov r0, r3
8003da6: 370c adds r7, #12
8003da8: 46bd mov sp, r7
8003daa: bc80 pop {r7}
8003dac: 4770 bx lr
08003dae <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8003dae: b580 push {r7, lr}
8003db0: b086 sub sp, #24
8003db2: af00 add r7, sp, #0
8003db4: 60f8 str r0, [r7, #12]
8003db6: 607a str r2, [r7, #4]
8003db8: 603b str r3, [r7, #0]
8003dba: 460b mov r3, r1
8003dbc: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003dbe: 7afb ldrb r3, [r7, #11]
8003dc0: f003 0207 and.w r2, r3, #7
8003dc4: 4613 mov r3, r2
8003dc6: 009b lsls r3, r3, #2
8003dc8: 4413 add r3, r2
8003dca: 00db lsls r3, r3, #3
8003dcc: 3310 adds r3, #16
8003dce: 68fa ldr r2, [r7, #12]
8003dd0: 4413 add r3, r2
8003dd2: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8003dd4: 697b ldr r3, [r7, #20]
8003dd6: 687a ldr r2, [r7, #4]
8003dd8: 615a str r2, [r3, #20]
ep->xfer_len = len;
8003dda: 697b ldr r3, [r7, #20]
8003ddc: 683a ldr r2, [r7, #0]
8003dde: 619a str r2, [r3, #24]
#if defined (USB)
ep->xfer_fill_db = 1U;
8003de0: 697b ldr r3, [r7, #20]
8003de2: 2201 movs r2, #1
8003de4: f883 2024 strb.w r2, [r3, #36] @ 0x24
ep->xfer_len_db = len;
8003de8: 697b ldr r3, [r7, #20]
8003dea: 683a ldr r2, [r7, #0]
8003dec: 621a str r2, [r3, #32]
#endif /* defined (USB) */
ep->xfer_count = 0U;
8003dee: 697b ldr r3, [r7, #20]
8003df0: 2200 movs r2, #0
8003df2: 61da str r2, [r3, #28]
ep->is_in = 1U;
8003df4: 697b ldr r3, [r7, #20]
8003df6: 2201 movs r2, #1
8003df8: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8003dfa: 7afb ldrb r3, [r7, #11]
8003dfc: f003 0307 and.w r3, r3, #7
8003e00: b2da uxtb r2, r3
8003e02: 697b ldr r3, [r7, #20]
8003e04: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8003e06: 68fb ldr r3, [r7, #12]
8003e08: 681b ldr r3, [r3, #0]
8003e0a: 6979 ldr r1, [r7, #20]
8003e0c: 4618 mov r0, r3
8003e0e: f003 fbf5 bl 80075fc <USB_EPStartXfer>
return HAL_OK;
8003e12: 2300 movs r3, #0
}
8003e14: 4618 mov r0, r3
8003e16: 3718 adds r7, #24
8003e18: 46bd mov sp, r7
8003e1a: bd80 pop {r7, pc}
08003e1c <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8003e1c: b580 push {r7, lr}
8003e1e: b084 sub sp, #16
8003e20: af00 add r7, sp, #0
8003e22: 6078 str r0, [r7, #4]
8003e24: 460b mov r3, r1
8003e26: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8003e28: 78fb ldrb r3, [r7, #3]
8003e2a: f003 0307 and.w r3, r3, #7
8003e2e: 687a ldr r2, [r7, #4]
8003e30: 7912 ldrb r2, [r2, #4]
8003e32: 4293 cmp r3, r2
8003e34: d901 bls.n 8003e3a <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
8003e36: 2301 movs r3, #1
8003e38: e04c b.n 8003ed4 <HAL_PCD_EP_SetStall+0xb8>
}
if ((0x80U & ep_addr) == 0x80U)
8003e3a: f997 3003 ldrsb.w r3, [r7, #3]
8003e3e: 2b00 cmp r3, #0
8003e40: da0e bge.n 8003e60 <HAL_PCD_EP_SetStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003e42: 78fb ldrb r3, [r7, #3]
8003e44: f003 0207 and.w r2, r3, #7
8003e48: 4613 mov r3, r2
8003e4a: 009b lsls r3, r3, #2
8003e4c: 4413 add r3, r2
8003e4e: 00db lsls r3, r3, #3
8003e50: 3310 adds r3, #16
8003e52: 687a ldr r2, [r7, #4]
8003e54: 4413 add r3, r2
8003e56: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003e58: 68fb ldr r3, [r7, #12]
8003e5a: 2201 movs r2, #1
8003e5c: 705a strb r2, [r3, #1]
8003e5e: e00c b.n 8003e7a <HAL_PCD_EP_SetStall+0x5e>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8003e60: 78fa ldrb r2, [r7, #3]
8003e62: 4613 mov r3, r2
8003e64: 009b lsls r3, r3, #2
8003e66: 4413 add r3, r2
8003e68: 00db lsls r3, r3, #3
8003e6a: f503 73a8 add.w r3, r3, #336 @ 0x150
8003e6e: 687a ldr r2, [r7, #4]
8003e70: 4413 add r3, r2
8003e72: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003e74: 68fb ldr r3, [r7, #12]
8003e76: 2200 movs r2, #0
8003e78: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
8003e7a: 68fb ldr r3, [r7, #12]
8003e7c: 2201 movs r2, #1
8003e7e: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8003e80: 78fb ldrb r3, [r7, #3]
8003e82: f003 0307 and.w r3, r3, #7
8003e86: b2da uxtb r2, r3
8003e88: 68fb ldr r3, [r7, #12]
8003e8a: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8003e8c: 687b ldr r3, [r7, #4]
8003e8e: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003e92: 2b01 cmp r3, #1
8003e94: d101 bne.n 8003e9a <HAL_PCD_EP_SetStall+0x7e>
8003e96: 2302 movs r3, #2
8003e98: e01c b.n 8003ed4 <HAL_PCD_EP_SetStall+0xb8>
8003e9a: 687b ldr r3, [r7, #4]
8003e9c: 2201 movs r2, #1
8003e9e: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPSetStall(hpcd->Instance, ep);
8003ea2: 687b ldr r3, [r7, #4]
8003ea4: 681b ldr r3, [r3, #0]
8003ea6: 68f9 ldr r1, [r7, #12]
8003ea8: 4618 mov r0, r3
8003eaa: f004 ff58 bl 8008d5e <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
8003eae: 78fb ldrb r3, [r7, #3]
8003eb0: f003 0307 and.w r3, r3, #7
8003eb4: 2b00 cmp r3, #0
8003eb6: d108 bne.n 8003eca <HAL_PCD_EP_SetStall+0xae>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
8003eb8: 687b ldr r3, [r7, #4]
8003eba: 681a ldr r2, [r3, #0]
8003ebc: 687b ldr r3, [r7, #4]
8003ebe: f503 7326 add.w r3, r3, #664 @ 0x298
8003ec2: 4619 mov r1, r3
8003ec4: 4610 mov r0, r2
8003ec6: f005 f87d bl 8008fc4 <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 2200 movs r2, #0
8003ece: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003ed2: 2300 movs r3, #0
}
8003ed4: 4618 mov r0, r3
8003ed6: 3710 adds r7, #16
8003ed8: 46bd mov sp, r7
8003eda: bd80 pop {r7, pc}
08003edc <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8003edc: b580 push {r7, lr}
8003ede: b084 sub sp, #16
8003ee0: af00 add r7, sp, #0
8003ee2: 6078 str r0, [r7, #4]
8003ee4: 460b mov r3, r1
8003ee6: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
8003ee8: 78fb ldrb r3, [r7, #3]
8003eea: f003 030f and.w r3, r3, #15
8003eee: 687a ldr r2, [r7, #4]
8003ef0: 7912 ldrb r2, [r2, #4]
8003ef2: 4293 cmp r3, r2
8003ef4: d901 bls.n 8003efa <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
8003ef6: 2301 movs r3, #1
8003ef8: e040 b.n 8003f7c <HAL_PCD_EP_ClrStall+0xa0>
}
if ((0x80U & ep_addr) == 0x80U)
8003efa: f997 3003 ldrsb.w r3, [r7, #3]
8003efe: 2b00 cmp r3, #0
8003f00: da0e bge.n 8003f20 <HAL_PCD_EP_ClrStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8003f02: 78fb ldrb r3, [r7, #3]
8003f04: f003 0207 and.w r2, r3, #7
8003f08: 4613 mov r3, r2
8003f0a: 009b lsls r3, r3, #2
8003f0c: 4413 add r3, r2
8003f0e: 00db lsls r3, r3, #3
8003f10: 3310 adds r3, #16
8003f12: 687a ldr r2, [r7, #4]
8003f14: 4413 add r3, r2
8003f16: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8003f18: 68fb ldr r3, [r7, #12]
8003f1a: 2201 movs r2, #1
8003f1c: 705a strb r2, [r3, #1]
8003f1e: e00e b.n 8003f3e <HAL_PCD_EP_ClrStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8003f20: 78fb ldrb r3, [r7, #3]
8003f22: f003 0207 and.w r2, r3, #7
8003f26: 4613 mov r3, r2
8003f28: 009b lsls r3, r3, #2
8003f2a: 4413 add r3, r2
8003f2c: 00db lsls r3, r3, #3
8003f2e: f503 73a8 add.w r3, r3, #336 @ 0x150
8003f32: 687a ldr r2, [r7, #4]
8003f34: 4413 add r3, r2
8003f36: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8003f38: 68fb ldr r3, [r7, #12]
8003f3a: 2200 movs r2, #0
8003f3c: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
8003f3e: 68fb ldr r3, [r7, #12]
8003f40: 2200 movs r2, #0
8003f42: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8003f44: 78fb ldrb r3, [r7, #3]
8003f46: f003 0307 and.w r3, r3, #7
8003f4a: b2da uxtb r2, r3
8003f4c: 68fb ldr r3, [r7, #12]
8003f4e: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8003f50: 687b ldr r3, [r7, #4]
8003f52: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8003f56: 2b01 cmp r3, #1
8003f58: d101 bne.n 8003f5e <HAL_PCD_EP_ClrStall+0x82>
8003f5a: 2302 movs r3, #2
8003f5c: e00e b.n 8003f7c <HAL_PCD_EP_ClrStall+0xa0>
8003f5e: 687b ldr r3, [r7, #4]
8003f60: 2201 movs r2, #1
8003f62: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPClearStall(hpcd->Instance, ep);
8003f66: 687b ldr r3, [r7, #4]
8003f68: 681b ldr r3, [r3, #0]
8003f6a: 68f9 ldr r1, [r7, #12]
8003f6c: 4618 mov r0, r3
8003f6e: f004 ff46 bl 8008dfe <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
8003f72: 687b ldr r3, [r7, #4]
8003f74: 2200 movs r2, #0
8003f76: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8003f7a: 2300 movs r3, #0
}
8003f7c: 4618 mov r0, r3
8003f7e: 3710 adds r7, #16
8003f80: 46bd mov sp, r7
8003f82: bd80 pop {r7, pc}
08003f84 <PCD_EP_ISR_Handler>:
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
8003f84: b580 push {r7, lr}
8003f86: b096 sub sp, #88 @ 0x58
8003f88: af00 add r7, sp, #0
8003f8a: 6078 str r0, [r7, #4]
#if (USE_USB_DOUBLE_BUFFER != 1U)
count = 0U;
#endif /* USE_USB_DOUBLE_BUFFER */
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8003f8c: e3bb b.n 8004706 <PCD_EP_ISR_Handler+0x782>
{
wIstr = hpcd->Instance->ISTR;
8003f8e: 687b ldr r3, [r7, #4]
8003f90: 681b ldr r3, [r3, #0]
8003f92: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8003f96: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
8003f9a: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8003f9e: b2db uxtb r3, r3
8003fa0: f003 030f and.w r3, r3, #15
8003fa4: f887 304d strb.w r3, [r7, #77] @ 0x4d
if (epindex == 0U)
8003fa8: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8003fac: 2b00 cmp r3, #0
8003fae: f040 8175 bne.w 800429c <PCD_EP_ISR_Handler+0x318>
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
8003fb2: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8003fb6: f003 0310 and.w r3, r3, #16
8003fba: 2b00 cmp r3, #0
8003fbc: d14e bne.n 800405c <PCD_EP_ISR_Handler+0xd8>
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8003fbe: 687b ldr r3, [r7, #4]
8003fc0: 681b ldr r3, [r3, #0]
8003fc2: 881b ldrh r3, [r3, #0]
8003fc4: b29b uxth r3, r3
8003fc6: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
8003fca: f023 0370 bic.w r3, r3, #112 @ 0x70
8003fce: 81fb strh r3, [r7, #14]
8003fd0: 687b ldr r3, [r7, #4]
8003fd2: 681a ldr r2, [r3, #0]
8003fd4: 89fb ldrh r3, [r7, #14]
8003fd6: ea6f 4343 mvn.w r3, r3, lsl #17
8003fda: ea6f 4353 mvn.w r3, r3, lsr #17
8003fde: b29b uxth r3, r3
8003fe0: 8013 strh r3, [r2, #0]
ep = &hpcd->IN_ep[0];
8003fe2: 687b ldr r3, [r7, #4]
8003fe4: 3310 adds r3, #16
8003fe6: 657b str r3, [r7, #84] @ 0x54
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
8003fe8: 687b ldr r3, [r7, #4]
8003fea: 681b ldr r3, [r3, #0]
8003fec: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8003ff0: b29b uxth r3, r3
8003ff2: 461a mov r2, r3
8003ff4: 6d7b ldr r3, [r7, #84] @ 0x54
8003ff6: 781b ldrb r3, [r3, #0]
8003ff8: 00db lsls r3, r3, #3
8003ffa: 4413 add r3, r2
8003ffc: 3302 adds r3, #2
8003ffe: 005b lsls r3, r3, #1
8004000: 687a ldr r2, [r7, #4]
8004002: 6812 ldr r2, [r2, #0]
8004004: 4413 add r3, r2
8004006: f503 6380 add.w r3, r3, #1024 @ 0x400
800400a: 881b ldrh r3, [r3, #0]
800400c: f3c3 0209 ubfx r2, r3, #0, #10
8004010: 6d7b ldr r3, [r7, #84] @ 0x54
8004012: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
8004014: 6d7b ldr r3, [r7, #84] @ 0x54
8004016: 695a ldr r2, [r3, #20]
8004018: 6d7b ldr r3, [r7, #84] @ 0x54
800401a: 69db ldr r3, [r3, #28]
800401c: 441a add r2, r3
800401e: 6d7b ldr r3, [r7, #84] @ 0x54
8004020: 615a str r2, [r3, #20]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
8004022: 2100 movs r1, #0
8004024: 6878 ldr r0, [r7, #4]
8004026: f006 fe9c bl 800ad62 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
800402a: 687b ldr r3, [r7, #4]
800402c: 7b5b ldrb r3, [r3, #13]
800402e: b2db uxtb r3, r3
8004030: 2b00 cmp r3, #0
8004032: f000 8368 beq.w 8004706 <PCD_EP_ISR_Handler+0x782>
8004036: 6d7b ldr r3, [r7, #84] @ 0x54
8004038: 699b ldr r3, [r3, #24]
800403a: 2b00 cmp r3, #0
800403c: f040 8363 bne.w 8004706 <PCD_EP_ISR_Handler+0x782>
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
8004040: 687b ldr r3, [r7, #4]
8004042: 7b5b ldrb r3, [r3, #13]
8004044: b2db uxtb r3, r3
8004046: f063 037f orn r3, r3, #127 @ 0x7f
800404a: b2da uxtb r2, r3
800404c: 687b ldr r3, [r7, #4]
800404e: 681b ldr r3, [r3, #0]
8004050: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
hpcd->USB_Address = 0U;
8004054: 687b ldr r3, [r7, #4]
8004056: 2200 movs r2, #0
8004058: 735a strb r2, [r3, #13]
800405a: e354 b.n 8004706 <PCD_EP_ISR_Handler+0x782>
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
800405c: 687b ldr r3, [r7, #4]
800405e: f503 73a8 add.w r3, r3, #336 @ 0x150
8004062: 657b str r3, [r7, #84] @ 0x54
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
8004064: 687b ldr r3, [r7, #4]
8004066: 681b ldr r3, [r3, #0]
8004068: 881b ldrh r3, [r3, #0]
800406a: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_SETUP) != 0U)
800406e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004072: f403 6300 and.w r3, r3, #2048 @ 0x800
8004076: 2b00 cmp r3, #0
8004078: d034 beq.n 80040e4 <PCD_EP_ISR_Handler+0x160>
{
/* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800407a: 687b ldr r3, [r7, #4]
800407c: 681b ldr r3, [r3, #0]
800407e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004082: b29b uxth r3, r3
8004084: 461a mov r2, r3
8004086: 6d7b ldr r3, [r7, #84] @ 0x54
8004088: 781b ldrb r3, [r3, #0]
800408a: 00db lsls r3, r3, #3
800408c: 4413 add r3, r2
800408e: 3306 adds r3, #6
8004090: 005b lsls r3, r3, #1
8004092: 687a ldr r2, [r7, #4]
8004094: 6812 ldr r2, [r2, #0]
8004096: 4413 add r3, r2
8004098: f503 6380 add.w r3, r3, #1024 @ 0x400
800409c: 881b ldrh r3, [r3, #0]
800409e: f3c3 0209 ubfx r2, r3, #0, #10
80040a2: 6d7b ldr r3, [r7, #84] @ 0x54
80040a4: 61da str r2, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
80040a6: 687b ldr r3, [r7, #4]
80040a8: 6818 ldr r0, [r3, #0]
80040aa: 687b ldr r3, [r7, #4]
80040ac: f503 7126 add.w r1, r3, #664 @ 0x298
80040b0: 6d7b ldr r3, [r7, #84] @ 0x54
80040b2: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
80040b4: 6d7b ldr r3, [r7, #84] @ 0x54
80040b6: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
80040b8: b29b uxth r3, r3
80040ba: f004 ffd4 bl 8009066 <USB_ReadPMA>
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
80040be: 687b ldr r3, [r7, #4]
80040c0: 681b ldr r3, [r3, #0]
80040c2: 881b ldrh r3, [r3, #0]
80040c4: b29a uxth r2, r3
80040c6: f640 738f movw r3, #3983 @ 0xf8f
80040ca: 4013 ands r3, r2
80040cc: 823b strh r3, [r7, #16]
80040ce: 687b ldr r3, [r7, #4]
80040d0: 681b ldr r3, [r3, #0]
80040d2: 8a3a ldrh r2, [r7, #16]
80040d4: f042 0280 orr.w r2, r2, #128 @ 0x80
80040d8: b292 uxth r2, r2
80040da: 801a strh r2, [r3, #0]
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
80040dc: 6878 ldr r0, [r7, #4]
80040de: f006 fe13 bl 800ad08 <HAL_PCD_SetupStageCallback>
80040e2: e310 b.n 8004706 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
80040e4: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
80040e8: 2b00 cmp r3, #0
80040ea: f280 830c bge.w 8004706 <PCD_EP_ISR_Handler+0x782>
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
80040ee: 687b ldr r3, [r7, #4]
80040f0: 681b ldr r3, [r3, #0]
80040f2: 881b ldrh r3, [r3, #0]
80040f4: b29a uxth r2, r3
80040f6: f640 738f movw r3, #3983 @ 0xf8f
80040fa: 4013 ands r3, r2
80040fc: 83fb strh r3, [r7, #30]
80040fe: 687b ldr r3, [r7, #4]
8004100: 681b ldr r3, [r3, #0]
8004102: 8bfa ldrh r2, [r7, #30]
8004104: f042 0280 orr.w r2, r2, #128 @ 0x80
8004108: b292 uxth r2, r2
800410a: 801a strh r2, [r3, #0]
/* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800410c: 687b ldr r3, [r7, #4]
800410e: 681b ldr r3, [r3, #0]
8004110: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004114: b29b uxth r3, r3
8004116: 461a mov r2, r3
8004118: 6d7b ldr r3, [r7, #84] @ 0x54
800411a: 781b ldrb r3, [r3, #0]
800411c: 00db lsls r3, r3, #3
800411e: 4413 add r3, r2
8004120: 3306 adds r3, #6
8004122: 005b lsls r3, r3, #1
8004124: 687a ldr r2, [r7, #4]
8004126: 6812 ldr r2, [r2, #0]
8004128: 4413 add r3, r2
800412a: f503 6380 add.w r3, r3, #1024 @ 0x400
800412e: 881b ldrh r3, [r3, #0]
8004130: f3c3 0209 ubfx r2, r3, #0, #10
8004134: 6d7b ldr r3, [r7, #84] @ 0x54
8004136: 61da str r2, [r3, #28]
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
8004138: 6d7b ldr r3, [r7, #84] @ 0x54
800413a: 69db ldr r3, [r3, #28]
800413c: 2b00 cmp r3, #0
800413e: d019 beq.n 8004174 <PCD_EP_ISR_Handler+0x1f0>
8004140: 6d7b ldr r3, [r7, #84] @ 0x54
8004142: 695b ldr r3, [r3, #20]
8004144: 2b00 cmp r3, #0
8004146: d015 beq.n 8004174 <PCD_EP_ISR_Handler+0x1f0>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8004148: 687b ldr r3, [r7, #4]
800414a: 6818 ldr r0, [r3, #0]
800414c: 6d7b ldr r3, [r7, #84] @ 0x54
800414e: 6959 ldr r1, [r3, #20]
8004150: 6d7b ldr r3, [r7, #84] @ 0x54
8004152: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
8004154: 6d7b ldr r3, [r7, #84] @ 0x54
8004156: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8004158: b29b uxth r3, r3
800415a: f004 ff84 bl 8009066 <USB_ReadPMA>
ep->xfer_buff += ep->xfer_count;
800415e: 6d7b ldr r3, [r7, #84] @ 0x54
8004160: 695a ldr r2, [r3, #20]
8004162: 6d7b ldr r3, [r7, #84] @ 0x54
8004164: 69db ldr r3, [r3, #28]
8004166: 441a add r2, r3
8004168: 6d7b ldr r3, [r7, #84] @ 0x54
800416a: 615a str r2, [r3, #20]
/* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
800416c: 2100 movs r1, #0
800416e: 6878 ldr r0, [r7, #4]
8004170: f006 fddc bl 800ad2c <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
8004174: 687b ldr r3, [r7, #4]
8004176: 681b ldr r3, [r3, #0]
8004178: 881b ldrh r3, [r3, #0]
800417a: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
800417e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004182: f403 6300 and.w r3, r3, #2048 @ 0x800
8004186: 2b00 cmp r3, #0
8004188: f040 82bd bne.w 8004706 <PCD_EP_ISR_Handler+0x782>
800418c: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004190: f403 5340 and.w r3, r3, #12288 @ 0x3000
8004194: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
8004198: f000 82b5 beq.w 8004706 <PCD_EP_ISR_Handler+0x782>
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
800419c: 687b ldr r3, [r7, #4]
800419e: 681b ldr r3, [r3, #0]
80041a0: 61bb str r3, [r7, #24]
80041a2: 687b ldr r3, [r7, #4]
80041a4: 681b ldr r3, [r3, #0]
80041a6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80041aa: b29b uxth r3, r3
80041ac: 461a mov r2, r3
80041ae: 69bb ldr r3, [r7, #24]
80041b0: 4413 add r3, r2
80041b2: 61bb str r3, [r7, #24]
80041b4: 69bb ldr r3, [r7, #24]
80041b6: f203 430c addw r3, r3, #1036 @ 0x40c
80041ba: 617b str r3, [r7, #20]
80041bc: 697b ldr r3, [r7, #20]
80041be: 881b ldrh r3, [r3, #0]
80041c0: b29b uxth r3, r3
80041c2: f3c3 0309 ubfx r3, r3, #0, #10
80041c6: b29a uxth r2, r3
80041c8: 697b ldr r3, [r7, #20]
80041ca: 801a strh r2, [r3, #0]
80041cc: 6d7b ldr r3, [r7, #84] @ 0x54
80041ce: 691b ldr r3, [r3, #16]
80041d0: 2b3e cmp r3, #62 @ 0x3e
80041d2: d91d bls.n 8004210 <PCD_EP_ISR_Handler+0x28c>
80041d4: 6d7b ldr r3, [r7, #84] @ 0x54
80041d6: 691b ldr r3, [r3, #16]
80041d8: 095b lsrs r3, r3, #5
80041da: 647b str r3, [r7, #68] @ 0x44
80041dc: 6d7b ldr r3, [r7, #84] @ 0x54
80041de: 691b ldr r3, [r3, #16]
80041e0: f003 031f and.w r3, r3, #31
80041e4: 2b00 cmp r3, #0
80041e6: d102 bne.n 80041ee <PCD_EP_ISR_Handler+0x26a>
80041e8: 6c7b ldr r3, [r7, #68] @ 0x44
80041ea: 3b01 subs r3, #1
80041ec: 647b str r3, [r7, #68] @ 0x44
80041ee: 697b ldr r3, [r7, #20]
80041f0: 881b ldrh r3, [r3, #0]
80041f2: b29a uxth r2, r3
80041f4: 6c7b ldr r3, [r7, #68] @ 0x44
80041f6: b29b uxth r3, r3
80041f8: 029b lsls r3, r3, #10
80041fa: b29b uxth r3, r3
80041fc: 4313 orrs r3, r2
80041fe: b29b uxth r3, r3
8004200: ea6f 4343 mvn.w r3, r3, lsl #17
8004204: ea6f 4353 mvn.w r3, r3, lsr #17
8004208: b29a uxth r2, r3
800420a: 697b ldr r3, [r7, #20]
800420c: 801a strh r2, [r3, #0]
800420e: e026 b.n 800425e <PCD_EP_ISR_Handler+0x2da>
8004210: 6d7b ldr r3, [r7, #84] @ 0x54
8004212: 691b ldr r3, [r3, #16]
8004214: 2b00 cmp r3, #0
8004216: d10a bne.n 800422e <PCD_EP_ISR_Handler+0x2aa>
8004218: 697b ldr r3, [r7, #20]
800421a: 881b ldrh r3, [r3, #0]
800421c: b29b uxth r3, r3
800421e: ea6f 4343 mvn.w r3, r3, lsl #17
8004222: ea6f 4353 mvn.w r3, r3, lsr #17
8004226: b29a uxth r2, r3
8004228: 697b ldr r3, [r7, #20]
800422a: 801a strh r2, [r3, #0]
800422c: e017 b.n 800425e <PCD_EP_ISR_Handler+0x2da>
800422e: 6d7b ldr r3, [r7, #84] @ 0x54
8004230: 691b ldr r3, [r3, #16]
8004232: 085b lsrs r3, r3, #1
8004234: 647b str r3, [r7, #68] @ 0x44
8004236: 6d7b ldr r3, [r7, #84] @ 0x54
8004238: 691b ldr r3, [r3, #16]
800423a: f003 0301 and.w r3, r3, #1
800423e: 2b00 cmp r3, #0
8004240: d002 beq.n 8004248 <PCD_EP_ISR_Handler+0x2c4>
8004242: 6c7b ldr r3, [r7, #68] @ 0x44
8004244: 3301 adds r3, #1
8004246: 647b str r3, [r7, #68] @ 0x44
8004248: 697b ldr r3, [r7, #20]
800424a: 881b ldrh r3, [r3, #0]
800424c: b29a uxth r2, r3
800424e: 6c7b ldr r3, [r7, #68] @ 0x44
8004250: b29b uxth r3, r3
8004252: 029b lsls r3, r3, #10
8004254: b29b uxth r3, r3
8004256: 4313 orrs r3, r2
8004258: b29a uxth r2, r3
800425a: 697b ldr r3, [r7, #20]
800425c: 801a strh r2, [r3, #0]
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
800425e: 687b ldr r3, [r7, #4]
8004260: 681b ldr r3, [r3, #0]
8004262: 881b ldrh r3, [r3, #0]
8004264: b29b uxth r3, r3
8004266: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800426a: f023 0370 bic.w r3, r3, #112 @ 0x70
800426e: 827b strh r3, [r7, #18]
8004270: 8a7b ldrh r3, [r7, #18]
8004272: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8004276: 827b strh r3, [r7, #18]
8004278: 8a7b ldrh r3, [r7, #18]
800427a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800427e: 827b strh r3, [r7, #18]
8004280: 687b ldr r3, [r7, #4]
8004282: 681a ldr r2, [r3, #0]
8004284: 8a7b ldrh r3, [r7, #18]
8004286: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800428a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800428e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004292: f043 0380 orr.w r3, r3, #128 @ 0x80
8004296: b29b uxth r3, r3
8004298: 8013 strh r3, [r2, #0]
800429a: e234 b.n 8004706 <PCD_EP_ISR_Handler+0x782>
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
800429c: 687b ldr r3, [r7, #4]
800429e: 681b ldr r3, [r3, #0]
80042a0: 461a mov r2, r3
80042a2: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80042a6: 009b lsls r3, r3, #2
80042a8: 4413 add r3, r2
80042aa: 881b ldrh r3, [r3, #0]
80042ac: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_CTR_RX) != 0U)
80042b0: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
80042b4: 2b00 cmp r3, #0
80042b6: f280 80fc bge.w 80044b2 <PCD_EP_ISR_Handler+0x52e>
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
80042ba: 687b ldr r3, [r7, #4]
80042bc: 681b ldr r3, [r3, #0]
80042be: 461a mov r2, r3
80042c0: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80042c4: 009b lsls r3, r3, #2
80042c6: 4413 add r3, r2
80042c8: 881b ldrh r3, [r3, #0]
80042ca: b29a uxth r2, r3
80042cc: f640 738f movw r3, #3983 @ 0xf8f
80042d0: 4013 ands r3, r2
80042d2: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
80042d6: 687b ldr r3, [r7, #4]
80042d8: 681b ldr r3, [r3, #0]
80042da: 461a mov r2, r3
80042dc: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80042e0: 009b lsls r3, r3, #2
80042e2: 4413 add r3, r2
80042e4: f8b7 2048 ldrh.w r2, [r7, #72] @ 0x48
80042e8: f042 0280 orr.w r2, r2, #128 @ 0x80
80042ec: b292 uxth r2, r2
80042ee: 801a strh r2, [r3, #0]
ep = &hpcd->OUT_ep[epindex];
80042f0: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
80042f4: 4613 mov r3, r2
80042f6: 009b lsls r3, r3, #2
80042f8: 4413 add r3, r2
80042fa: 00db lsls r3, r3, #3
80042fc: f503 73a8 add.w r3, r3, #336 @ 0x150
8004300: 687a ldr r2, [r7, #4]
8004302: 4413 add r3, r2
8004304: 657b str r3, [r7, #84] @ 0x54
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
8004306: 6d7b ldr r3, [r7, #84] @ 0x54
8004308: 7b1b ldrb r3, [r3, #12]
800430a: 2b00 cmp r3, #0
800430c: d125 bne.n 800435a <PCD_EP_ISR_Handler+0x3d6>
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800430e: 687b ldr r3, [r7, #4]
8004310: 681b ldr r3, [r3, #0]
8004312: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004316: b29b uxth r3, r3
8004318: 461a mov r2, r3
800431a: 6d7b ldr r3, [r7, #84] @ 0x54
800431c: 781b ldrb r3, [r3, #0]
800431e: 00db lsls r3, r3, #3
8004320: 4413 add r3, r2
8004322: 3306 adds r3, #6
8004324: 005b lsls r3, r3, #1
8004326: 687a ldr r2, [r7, #4]
8004328: 6812 ldr r2, [r2, #0]
800432a: 4413 add r3, r2
800432c: f503 6380 add.w r3, r3, #1024 @ 0x400
8004330: 881b ldrh r3, [r3, #0]
8004332: f3c3 0309 ubfx r3, r3, #0, #10
8004336: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
800433a: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800433e: 2b00 cmp r3, #0
8004340: f000 8092 beq.w 8004468 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
8004344: 687b ldr r3, [r7, #4]
8004346: 6818 ldr r0, [r3, #0]
8004348: 6d7b ldr r3, [r7, #84] @ 0x54
800434a: 6959 ldr r1, [r3, #20]
800434c: 6d7b ldr r3, [r7, #84] @ 0x54
800434e: 88da ldrh r2, [r3, #6]
8004350: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004354: f004 fe87 bl 8009066 <USB_ReadPMA>
8004358: e086 b.n 8004468 <PCD_EP_ISR_Handler+0x4e4>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
800435a: 6d7b ldr r3, [r7, #84] @ 0x54
800435c: 78db ldrb r3, [r3, #3]
800435e: 2b02 cmp r3, #2
8004360: d10a bne.n 8004378 <PCD_EP_ISR_Handler+0x3f4>
{
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
8004362: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004366: 461a mov r2, r3
8004368: 6d79 ldr r1, [r7, #84] @ 0x54
800436a: 6878 ldr r0, [r7, #4]
800436c: f000 f9d9 bl 8004722 <HAL_PCD_EP_DB_Receive>
8004370: 4603 mov r3, r0
8004372: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
8004376: e077 b.n 8004468 <PCD_EP_ISR_Handler+0x4e4>
}
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8004378: 687b ldr r3, [r7, #4]
800437a: 681b ldr r3, [r3, #0]
800437c: 461a mov r2, r3
800437e: 6d7b ldr r3, [r7, #84] @ 0x54
8004380: 781b ldrb r3, [r3, #0]
8004382: 009b lsls r3, r3, #2
8004384: 4413 add r3, r2
8004386: 881b ldrh r3, [r3, #0]
8004388: b29b uxth r3, r3
800438a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800438e: f023 0370 bic.w r3, r3, #112 @ 0x70
8004392: f8a7 3052 strh.w r3, [r7, #82] @ 0x52
8004396: 687b ldr r3, [r7, #4]
8004398: 681b ldr r3, [r3, #0]
800439a: 461a mov r2, r3
800439c: 6d7b ldr r3, [r7, #84] @ 0x54
800439e: 781b ldrb r3, [r3, #0]
80043a0: 009b lsls r3, r3, #2
80043a2: 441a add r2, r3
80043a4: f8b7 3052 ldrh.w r3, [r7, #82] @ 0x52
80043a8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80043ac: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80043b0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80043b4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80043b8: b29b uxth r3, r3
80043ba: 8013 strh r3, [r2, #0]
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
80043bc: 687b ldr r3, [r7, #4]
80043be: 681b ldr r3, [r3, #0]
80043c0: 461a mov r2, r3
80043c2: 6d7b ldr r3, [r7, #84] @ 0x54
80043c4: 781b ldrb r3, [r3, #0]
80043c6: 009b lsls r3, r3, #2
80043c8: 4413 add r3, r2
80043ca: 881b ldrh r3, [r3, #0]
80043cc: b29b uxth r3, r3
80043ce: f403 4380 and.w r3, r3, #16384 @ 0x4000
80043d2: 2b00 cmp r3, #0
80043d4: d024 beq.n 8004420 <PCD_EP_ISR_Handler+0x49c>
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
80043d6: 687b ldr r3, [r7, #4]
80043d8: 681b ldr r3, [r3, #0]
80043da: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80043de: b29b uxth r3, r3
80043e0: 461a mov r2, r3
80043e2: 6d7b ldr r3, [r7, #84] @ 0x54
80043e4: 781b ldrb r3, [r3, #0]
80043e6: 00db lsls r3, r3, #3
80043e8: 4413 add r3, r2
80043ea: 3302 adds r3, #2
80043ec: 005b lsls r3, r3, #1
80043ee: 687a ldr r2, [r7, #4]
80043f0: 6812 ldr r2, [r2, #0]
80043f2: 4413 add r3, r2
80043f4: f503 6380 add.w r3, r3, #1024 @ 0x400
80043f8: 881b ldrh r3, [r3, #0]
80043fa: f3c3 0309 ubfx r3, r3, #0, #10
80043fe: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
8004402: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004406: 2b00 cmp r3, #0
8004408: d02e beq.n 8004468 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
800440a: 687b ldr r3, [r7, #4]
800440c: 6818 ldr r0, [r3, #0]
800440e: 6d7b ldr r3, [r7, #84] @ 0x54
8004410: 6959 ldr r1, [r3, #20]
8004412: 6d7b ldr r3, [r7, #84] @ 0x54
8004414: 891a ldrh r2, [r3, #8]
8004416: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800441a: f004 fe24 bl 8009066 <USB_ReadPMA>
800441e: e023 b.n 8004468 <PCD_EP_ISR_Handler+0x4e4>
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8004420: 687b ldr r3, [r7, #4]
8004422: 681b ldr r3, [r3, #0]
8004424: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004428: b29b uxth r3, r3
800442a: 461a mov r2, r3
800442c: 6d7b ldr r3, [r7, #84] @ 0x54
800442e: 781b ldrb r3, [r3, #0]
8004430: 00db lsls r3, r3, #3
8004432: 4413 add r3, r2
8004434: 3306 adds r3, #6
8004436: 005b lsls r3, r3, #1
8004438: 687a ldr r2, [r7, #4]
800443a: 6812 ldr r2, [r2, #0]
800443c: 4413 add r3, r2
800443e: f503 6380 add.w r3, r3, #1024 @ 0x400
8004442: 881b ldrh r3, [r3, #0]
8004444: f3c3 0309 ubfx r3, r3, #0, #10
8004448: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
800444c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004450: 2b00 cmp r3, #0
8004452: d009 beq.n 8004468 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8004454: 687b ldr r3, [r7, #4]
8004456: 6818 ldr r0, [r3, #0]
8004458: 6d7b ldr r3, [r7, #84] @ 0x54
800445a: 6959 ldr r1, [r3, #20]
800445c: 6d7b ldr r3, [r7, #84] @ 0x54
800445e: 895a ldrh r2, [r3, #10]
8004460: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004464: f004 fdff bl 8009066 <USB_ReadPMA>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
8004468: 6d7b ldr r3, [r7, #84] @ 0x54
800446a: 69da ldr r2, [r3, #28]
800446c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8004470: 441a add r2, r3
8004472: 6d7b ldr r3, [r7, #84] @ 0x54
8004474: 61da str r2, [r3, #28]
ep->xfer_buff += count;
8004476: 6d7b ldr r3, [r7, #84] @ 0x54
8004478: 695a ldr r2, [r3, #20]
800447a: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800447e: 441a add r2, r3
8004480: 6d7b ldr r3, [r7, #84] @ 0x54
8004482: 615a str r2, [r3, #20]
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
8004484: 6d7b ldr r3, [r7, #84] @ 0x54
8004486: 699b ldr r3, [r3, #24]
8004488: 2b00 cmp r3, #0
800448a: d005 beq.n 8004498 <PCD_EP_ISR_Handler+0x514>
800448c: f8b7 2050 ldrh.w r2, [r7, #80] @ 0x50
8004490: 6d7b ldr r3, [r7, #84] @ 0x54
8004492: 691b ldr r3, [r3, #16]
8004494: 429a cmp r2, r3
8004496: d206 bcs.n 80044a6 <PCD_EP_ISR_Handler+0x522>
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
8004498: 6d7b ldr r3, [r7, #84] @ 0x54
800449a: 781b ldrb r3, [r3, #0]
800449c: 4619 mov r1, r3
800449e: 6878 ldr r0, [r7, #4]
80044a0: f006 fc44 bl 800ad2c <HAL_PCD_DataOutStageCallback>
80044a4: e005 b.n 80044b2 <PCD_EP_ISR_Handler+0x52e>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
80044a6: 687b ldr r3, [r7, #4]
80044a8: 681b ldr r3, [r3, #0]
80044aa: 6d79 ldr r1, [r7, #84] @ 0x54
80044ac: 4618 mov r0, r3
80044ae: f003 f8a5 bl 80075fc <USB_EPStartXfer>
}
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
80044b2: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80044b6: f003 0380 and.w r3, r3, #128 @ 0x80
80044ba: 2b00 cmp r3, #0
80044bc: f000 8123 beq.w 8004706 <PCD_EP_ISR_Handler+0x782>
{
ep = &hpcd->IN_ep[epindex];
80044c0: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
80044c4: 4613 mov r3, r2
80044c6: 009b lsls r3, r3, #2
80044c8: 4413 add r3, r2
80044ca: 00db lsls r3, r3, #3
80044cc: 3310 adds r3, #16
80044ce: 687a ldr r2, [r7, #4]
80044d0: 4413 add r3, r2
80044d2: 657b str r3, [r7, #84] @ 0x54
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
80044d4: 687b ldr r3, [r7, #4]
80044d6: 681b ldr r3, [r3, #0]
80044d8: 461a mov r2, r3
80044da: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80044de: 009b lsls r3, r3, #2
80044e0: 4413 add r3, r2
80044e2: 881b ldrh r3, [r3, #0]
80044e4: b29b uxth r3, r3
80044e6: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
80044ea: f023 0370 bic.w r3, r3, #112 @ 0x70
80044ee: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
80044f2: 687b ldr r3, [r7, #4]
80044f4: 681b ldr r3, [r3, #0]
80044f6: 461a mov r2, r3
80044f8: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80044fc: 009b lsls r3, r3, #2
80044fe: 441a add r2, r3
8004500: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
8004504: ea6f 4343 mvn.w r3, r3, lsl #17
8004508: ea6f 4353 mvn.w r3, r3, lsr #17
800450c: b29b uxth r3, r3
800450e: 8013 strh r3, [r2, #0]
if (ep->type == EP_TYPE_ISOC)
8004510: 6d7b ldr r3, [r7, #84] @ 0x54
8004512: 78db ldrb r3, [r3, #3]
8004514: 2b01 cmp r3, #1
8004516: f040 80a2 bne.w 800465e <PCD_EP_ISR_Handler+0x6da>
{
ep->xfer_len = 0U;
800451a: 6d7b ldr r3, [r7, #84] @ 0x54
800451c: 2200 movs r2, #0
800451e: 619a str r2, [r3, #24]
#if (USE_USB_DOUBLE_BUFFER == 1U)
if (ep->doublebuffer != 0U)
8004520: 6d7b ldr r3, [r7, #84] @ 0x54
8004522: 7b1b ldrb r3, [r3, #12]
8004524: 2b00 cmp r3, #0
8004526: f000 8093 beq.w 8004650 <PCD_EP_ISR_Handler+0x6cc>
{
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
800452a: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
800452e: f003 0340 and.w r3, r3, #64 @ 0x40
8004532: 2b00 cmp r3, #0
8004534: d046 beq.n 80045c4 <PCD_EP_ISR_Handler+0x640>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004536: 6d7b ldr r3, [r7, #84] @ 0x54
8004538: 785b ldrb r3, [r3, #1]
800453a: 2b00 cmp r3, #0
800453c: d126 bne.n 800458c <PCD_EP_ISR_Handler+0x608>
800453e: 687b ldr r3, [r7, #4]
8004540: 681b ldr r3, [r3, #0]
8004542: 627b str r3, [r7, #36] @ 0x24
8004544: 687b ldr r3, [r7, #4]
8004546: 681b ldr r3, [r3, #0]
8004548: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800454c: b29b uxth r3, r3
800454e: 461a mov r2, r3
8004550: 6a7b ldr r3, [r7, #36] @ 0x24
8004552: 4413 add r3, r2
8004554: 627b str r3, [r7, #36] @ 0x24
8004556: 6d7b ldr r3, [r7, #84] @ 0x54
8004558: 781b ldrb r3, [r3, #0]
800455a: 011a lsls r2, r3, #4
800455c: 6a7b ldr r3, [r7, #36] @ 0x24
800455e: 4413 add r3, r2
8004560: f203 4304 addw r3, r3, #1028 @ 0x404
8004564: 623b str r3, [r7, #32]
8004566: 6a3b ldr r3, [r7, #32]
8004568: 881b ldrh r3, [r3, #0]
800456a: b29b uxth r3, r3
800456c: f3c3 0309 ubfx r3, r3, #0, #10
8004570: b29a uxth r2, r3
8004572: 6a3b ldr r3, [r7, #32]
8004574: 801a strh r2, [r3, #0]
8004576: 6a3b ldr r3, [r7, #32]
8004578: 881b ldrh r3, [r3, #0]
800457a: b29b uxth r3, r3
800457c: ea6f 4343 mvn.w r3, r3, lsl #17
8004580: ea6f 4353 mvn.w r3, r3, lsr #17
8004584: b29a uxth r2, r3
8004586: 6a3b ldr r3, [r7, #32]
8004588: 801a strh r2, [r3, #0]
800458a: e061 b.n 8004650 <PCD_EP_ISR_Handler+0x6cc>
800458c: 6d7b ldr r3, [r7, #84] @ 0x54
800458e: 785b ldrb r3, [r3, #1]
8004590: 2b01 cmp r3, #1
8004592: d15d bne.n 8004650 <PCD_EP_ISR_Handler+0x6cc>
8004594: 687b ldr r3, [r7, #4]
8004596: 681b ldr r3, [r3, #0]
8004598: 62fb str r3, [r7, #44] @ 0x2c
800459a: 687b ldr r3, [r7, #4]
800459c: 681b ldr r3, [r3, #0]
800459e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80045a2: b29b uxth r3, r3
80045a4: 461a mov r2, r3
80045a6: 6afb ldr r3, [r7, #44] @ 0x2c
80045a8: 4413 add r3, r2
80045aa: 62fb str r3, [r7, #44] @ 0x2c
80045ac: 6d7b ldr r3, [r7, #84] @ 0x54
80045ae: 781b ldrb r3, [r3, #0]
80045b0: 011a lsls r2, r3, #4
80045b2: 6afb ldr r3, [r7, #44] @ 0x2c
80045b4: 4413 add r3, r2
80045b6: f203 4304 addw r3, r3, #1028 @ 0x404
80045ba: 62bb str r3, [r7, #40] @ 0x28
80045bc: 6abb ldr r3, [r7, #40] @ 0x28
80045be: 2200 movs r2, #0
80045c0: 801a strh r2, [r3, #0]
80045c2: e045 b.n 8004650 <PCD_EP_ISR_Handler+0x6cc>
}
else
{
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80045c4: 687b ldr r3, [r7, #4]
80045c6: 681b ldr r3, [r3, #0]
80045c8: 63fb str r3, [r7, #60] @ 0x3c
80045ca: 6d7b ldr r3, [r7, #84] @ 0x54
80045cc: 785b ldrb r3, [r3, #1]
80045ce: 2b00 cmp r3, #0
80045d0: d126 bne.n 8004620 <PCD_EP_ISR_Handler+0x69c>
80045d2: 687b ldr r3, [r7, #4]
80045d4: 681b ldr r3, [r3, #0]
80045d6: 637b str r3, [r7, #52] @ 0x34
80045d8: 687b ldr r3, [r7, #4]
80045da: 681b ldr r3, [r3, #0]
80045dc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80045e0: b29b uxth r3, r3
80045e2: 461a mov r2, r3
80045e4: 6b7b ldr r3, [r7, #52] @ 0x34
80045e6: 4413 add r3, r2
80045e8: 637b str r3, [r7, #52] @ 0x34
80045ea: 6d7b ldr r3, [r7, #84] @ 0x54
80045ec: 781b ldrb r3, [r3, #0]
80045ee: 011a lsls r2, r3, #4
80045f0: 6b7b ldr r3, [r7, #52] @ 0x34
80045f2: 4413 add r3, r2
80045f4: f203 430c addw r3, r3, #1036 @ 0x40c
80045f8: 633b str r3, [r7, #48] @ 0x30
80045fa: 6b3b ldr r3, [r7, #48] @ 0x30
80045fc: 881b ldrh r3, [r3, #0]
80045fe: b29b uxth r3, r3
8004600: f3c3 0309 ubfx r3, r3, #0, #10
8004604: b29a uxth r2, r3
8004606: 6b3b ldr r3, [r7, #48] @ 0x30
8004608: 801a strh r2, [r3, #0]
800460a: 6b3b ldr r3, [r7, #48] @ 0x30
800460c: 881b ldrh r3, [r3, #0]
800460e: b29b uxth r3, r3
8004610: ea6f 4343 mvn.w r3, r3, lsl #17
8004614: ea6f 4353 mvn.w r3, r3, lsr #17
8004618: b29a uxth r2, r3
800461a: 6b3b ldr r3, [r7, #48] @ 0x30
800461c: 801a strh r2, [r3, #0]
800461e: e017 b.n 8004650 <PCD_EP_ISR_Handler+0x6cc>
8004620: 6d7b ldr r3, [r7, #84] @ 0x54
8004622: 785b ldrb r3, [r3, #1]
8004624: 2b01 cmp r3, #1
8004626: d113 bne.n 8004650 <PCD_EP_ISR_Handler+0x6cc>
8004628: 687b ldr r3, [r7, #4]
800462a: 681b ldr r3, [r3, #0]
800462c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004630: b29b uxth r3, r3
8004632: 461a mov r2, r3
8004634: 6bfb ldr r3, [r7, #60] @ 0x3c
8004636: 4413 add r3, r2
8004638: 63fb str r3, [r7, #60] @ 0x3c
800463a: 6d7b ldr r3, [r7, #84] @ 0x54
800463c: 781b ldrb r3, [r3, #0]
800463e: 011a lsls r2, r3, #4
8004640: 6bfb ldr r3, [r7, #60] @ 0x3c
8004642: 4413 add r3, r2
8004644: f203 430c addw r3, r3, #1036 @ 0x40c
8004648: 63bb str r3, [r7, #56] @ 0x38
800464a: 6bbb ldr r3, [r7, #56] @ 0x38
800464c: 2200 movs r2, #0
800464e: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8004650: 6d7b ldr r3, [r7, #84] @ 0x54
8004652: 781b ldrb r3, [r3, #0]
8004654: 4619 mov r1, r3
8004656: 6878 ldr r0, [r7, #4]
8004658: f006 fb83 bl 800ad62 <HAL_PCD_DataInStageCallback>
800465c: e053 b.n 8004706 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
800465e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8004662: f403 7380 and.w r3, r3, #256 @ 0x100
8004666: 2b00 cmp r3, #0
8004668: d146 bne.n 80046f8 <PCD_EP_ISR_Handler+0x774>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
800466a: 687b ldr r3, [r7, #4]
800466c: 681b ldr r3, [r3, #0]
800466e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004672: b29b uxth r3, r3
8004674: 461a mov r2, r3
8004676: 6d7b ldr r3, [r7, #84] @ 0x54
8004678: 781b ldrb r3, [r3, #0]
800467a: 00db lsls r3, r3, #3
800467c: 4413 add r3, r2
800467e: 3302 adds r3, #2
8004680: 005b lsls r3, r3, #1
8004682: 687a ldr r2, [r7, #4]
8004684: 6812 ldr r2, [r2, #0]
8004686: 4413 add r3, r2
8004688: f503 6380 add.w r3, r3, #1024 @ 0x400
800468c: 881b ldrh r3, [r3, #0]
800468e: f3c3 0309 ubfx r3, r3, #0, #10
8004692: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
if (ep->xfer_len > TxPctSize)
8004696: 6d7b ldr r3, [r7, #84] @ 0x54
8004698: 699a ldr r2, [r3, #24]
800469a: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
800469e: 429a cmp r2, r3
80046a0: d907 bls.n 80046b2 <PCD_EP_ISR_Handler+0x72e>
{
ep->xfer_len -= TxPctSize;
80046a2: 6d7b ldr r3, [r7, #84] @ 0x54
80046a4: 699a ldr r2, [r3, #24]
80046a6: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80046aa: 1ad2 subs r2, r2, r3
80046ac: 6d7b ldr r3, [r7, #84] @ 0x54
80046ae: 619a str r2, [r3, #24]
80046b0: e002 b.n 80046b8 <PCD_EP_ISR_Handler+0x734>
}
else
{
ep->xfer_len = 0U;
80046b2: 6d7b ldr r3, [r7, #84] @ 0x54
80046b4: 2200 movs r2, #0
80046b6: 619a str r2, [r3, #24]
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
80046b8: 6d7b ldr r3, [r7, #84] @ 0x54
80046ba: 699b ldr r3, [r3, #24]
80046bc: 2b00 cmp r3, #0
80046be: d106 bne.n 80046ce <PCD_EP_ISR_Handler+0x74a>
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80046c0: 6d7b ldr r3, [r7, #84] @ 0x54
80046c2: 781b ldrb r3, [r3, #0]
80046c4: 4619 mov r1, r3
80046c6: 6878 ldr r0, [r7, #4]
80046c8: f006 fb4b bl 800ad62 <HAL_PCD_DataInStageCallback>
80046cc: e01b b.n 8004706 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxPctSize;
80046ce: 6d7b ldr r3, [r7, #84] @ 0x54
80046d0: 695a ldr r2, [r3, #20]
80046d2: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80046d6: 441a add r2, r3
80046d8: 6d7b ldr r3, [r7, #84] @ 0x54
80046da: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
80046dc: 6d7b ldr r3, [r7, #84] @ 0x54
80046de: 69da ldr r2, [r3, #28]
80046e0: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80046e4: 441a add r2, r3
80046e6: 6d7b ldr r3, [r7, #84] @ 0x54
80046e8: 61da str r2, [r3, #28]
(void)USB_EPStartXfer(hpcd->Instance, ep);
80046ea: 687b ldr r3, [r7, #4]
80046ec: 681b ldr r3, [r3, #0]
80046ee: 6d79 ldr r1, [r7, #84] @ 0x54
80046f0: 4618 mov r0, r3
80046f2: f002 ff83 bl 80075fc <USB_EPStartXfer>
80046f6: e006 b.n 8004706 <PCD_EP_ISR_Handler+0x782>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
80046f8: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80046fc: 461a mov r2, r3
80046fe: 6d79 ldr r1, [r7, #84] @ 0x54
8004700: 6878 ldr r0, [r7, #4]
8004702: f000 f91b bl 800493c <HAL_PCD_EP_DB_Transmit>
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8004706: 687b ldr r3, [r7, #4]
8004708: 681b ldr r3, [r3, #0]
800470a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
800470e: b29b uxth r3, r3
8004710: b21b sxth r3, r3
8004712: 2b00 cmp r3, #0
8004714: f6ff ac3b blt.w 8003f8e <PCD_EP_ISR_Handler+0xa>
}
}
}
}
return HAL_OK;
8004718: 2300 movs r3, #0
}
800471a: 4618 mov r0, r3
800471c: 3758 adds r7, #88 @ 0x58
800471e: 46bd mov sp, r7
8004720: bd80 pop {r7, pc}
08004722 <HAL_PCD_EP_DB_Receive>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8004722: b580 push {r7, lr}
8004724: b088 sub sp, #32
8004726: af00 add r7, sp, #0
8004728: 60f8 str r0, [r7, #12]
800472a: 60b9 str r1, [r7, #8]
800472c: 4613 mov r3, r2
800472e: 80fb strh r3, [r7, #6]
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8004730: 88fb ldrh r3, [r7, #6]
8004732: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004736: 2b00 cmp r3, #0
8004738: d07e beq.n 8004838 <HAL_PCD_EP_DB_Receive+0x116>
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
800473a: 68fb ldr r3, [r7, #12]
800473c: 681b ldr r3, [r3, #0]
800473e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004742: b29b uxth r3, r3
8004744: 461a mov r2, r3
8004746: 68bb ldr r3, [r7, #8]
8004748: 781b ldrb r3, [r3, #0]
800474a: 00db lsls r3, r3, #3
800474c: 4413 add r3, r2
800474e: 3302 adds r3, #2
8004750: 005b lsls r3, r3, #1
8004752: 68fa ldr r2, [r7, #12]
8004754: 6812 ldr r2, [r2, #0]
8004756: 4413 add r3, r2
8004758: f503 6380 add.w r3, r3, #1024 @ 0x400
800475c: 881b ldrh r3, [r3, #0]
800475e: f3c3 0309 ubfx r3, r3, #0, #10
8004762: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8004764: 68bb ldr r3, [r7, #8]
8004766: 699a ldr r2, [r3, #24]
8004768: 8b7b ldrh r3, [r7, #26]
800476a: 429a cmp r2, r3
800476c: d306 bcc.n 800477c <HAL_PCD_EP_DB_Receive+0x5a>
{
ep->xfer_len -= count;
800476e: 68bb ldr r3, [r7, #8]
8004770: 699a ldr r2, [r3, #24]
8004772: 8b7b ldrh r3, [r7, #26]
8004774: 1ad2 subs r2, r2, r3
8004776: 68bb ldr r3, [r7, #8]
8004778: 619a str r2, [r3, #24]
800477a: e002 b.n 8004782 <HAL_PCD_EP_DB_Receive+0x60>
}
else
{
ep->xfer_len = 0U;
800477c: 68bb ldr r3, [r7, #8]
800477e: 2200 movs r2, #0
8004780: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8004782: 68bb ldr r3, [r7, #8]
8004784: 699b ldr r3, [r3, #24]
8004786: 2b00 cmp r3, #0
8004788: d123 bne.n 80047d2 <HAL_PCD_EP_DB_Receive+0xb0>
{
/* set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
800478a: 68fb ldr r3, [r7, #12]
800478c: 681b ldr r3, [r3, #0]
800478e: 461a mov r2, r3
8004790: 68bb ldr r3, [r7, #8]
8004792: 781b ldrb r3, [r3, #0]
8004794: 009b lsls r3, r3, #2
8004796: 4413 add r3, r2
8004798: 881b ldrh r3, [r3, #0]
800479a: b29b uxth r3, r3
800479c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80047a0: f023 0370 bic.w r3, r3, #112 @ 0x70
80047a4: 833b strh r3, [r7, #24]
80047a6: 8b3b ldrh r3, [r7, #24]
80047a8: f483 5300 eor.w r3, r3, #8192 @ 0x2000
80047ac: 833b strh r3, [r7, #24]
80047ae: 68fb ldr r3, [r7, #12]
80047b0: 681b ldr r3, [r3, #0]
80047b2: 461a mov r2, r3
80047b4: 68bb ldr r3, [r7, #8]
80047b6: 781b ldrb r3, [r3, #0]
80047b8: 009b lsls r3, r3, #2
80047ba: 441a add r2, r3
80047bc: 8b3b ldrh r3, [r7, #24]
80047be: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80047c2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80047c6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80047ca: f043 0380 orr.w r3, r3, #128 @ 0x80
80047ce: b29b uxth r3, r3
80047d0: 8013 strh r3, [r2, #0]
}
/* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
80047d2: 88fb ldrh r3, [r7, #6]
80047d4: f003 0340 and.w r3, r3, #64 @ 0x40
80047d8: 2b00 cmp r3, #0
80047da: d01f beq.n 800481c <HAL_PCD_EP_DB_Receive+0xfa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
80047dc: 68fb ldr r3, [r7, #12]
80047de: 681b ldr r3, [r3, #0]
80047e0: 461a mov r2, r3
80047e2: 68bb ldr r3, [r7, #8]
80047e4: 781b ldrb r3, [r3, #0]
80047e6: 009b lsls r3, r3, #2
80047e8: 4413 add r3, r2
80047ea: 881b ldrh r3, [r3, #0]
80047ec: b29b uxth r3, r3
80047ee: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80047f2: f023 0370 bic.w r3, r3, #112 @ 0x70
80047f6: 82fb strh r3, [r7, #22]
80047f8: 68fb ldr r3, [r7, #12]
80047fa: 681b ldr r3, [r3, #0]
80047fc: 461a mov r2, r3
80047fe: 68bb ldr r3, [r7, #8]
8004800: 781b ldrb r3, [r3, #0]
8004802: 009b lsls r3, r3, #2
8004804: 441a add r2, r3
8004806: 8afb ldrh r3, [r7, #22]
8004808: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800480c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004810: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004814: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8004818: b29b uxth r3, r3
800481a: 8013 strh r3, [r2, #0]
}
if (count != 0U)
800481c: 8b7b ldrh r3, [r7, #26]
800481e: 2b00 cmp r3, #0
8004820: f000 8087 beq.w 8004932 <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
8004824: 68fb ldr r3, [r7, #12]
8004826: 6818 ldr r0, [r3, #0]
8004828: 68bb ldr r3, [r7, #8]
800482a: 6959 ldr r1, [r3, #20]
800482c: 68bb ldr r3, [r7, #8]
800482e: 891a ldrh r2, [r3, #8]
8004830: 8b7b ldrh r3, [r7, #26]
8004832: f004 fc18 bl 8009066 <USB_ReadPMA>
8004836: e07c b.n 8004932 <HAL_PCD_EP_DB_Receive+0x210>
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8004838: 68fb ldr r3, [r7, #12]
800483a: 681b ldr r3, [r3, #0]
800483c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004840: b29b uxth r3, r3
8004842: 461a mov r2, r3
8004844: 68bb ldr r3, [r7, #8]
8004846: 781b ldrb r3, [r3, #0]
8004848: 00db lsls r3, r3, #3
800484a: 4413 add r3, r2
800484c: 3306 adds r3, #6
800484e: 005b lsls r3, r3, #1
8004850: 68fa ldr r2, [r7, #12]
8004852: 6812 ldr r2, [r2, #0]
8004854: 4413 add r3, r2
8004856: f503 6380 add.w r3, r3, #1024 @ 0x400
800485a: 881b ldrh r3, [r3, #0]
800485c: f3c3 0309 ubfx r3, r3, #0, #10
8004860: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8004862: 68bb ldr r3, [r7, #8]
8004864: 699a ldr r2, [r3, #24]
8004866: 8b7b ldrh r3, [r7, #26]
8004868: 429a cmp r2, r3
800486a: d306 bcc.n 800487a <HAL_PCD_EP_DB_Receive+0x158>
{
ep->xfer_len -= count;
800486c: 68bb ldr r3, [r7, #8]
800486e: 699a ldr r2, [r3, #24]
8004870: 8b7b ldrh r3, [r7, #26]
8004872: 1ad2 subs r2, r2, r3
8004874: 68bb ldr r3, [r7, #8]
8004876: 619a str r2, [r3, #24]
8004878: e002 b.n 8004880 <HAL_PCD_EP_DB_Receive+0x15e>
}
else
{
ep->xfer_len = 0U;
800487a: 68bb ldr r3, [r7, #8]
800487c: 2200 movs r2, #0
800487e: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8004880: 68bb ldr r3, [r7, #8]
8004882: 699b ldr r3, [r3, #24]
8004884: 2b00 cmp r3, #0
8004886: d123 bne.n 80048d0 <HAL_PCD_EP_DB_Receive+0x1ae>
{
/* set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
8004888: 68fb ldr r3, [r7, #12]
800488a: 681b ldr r3, [r3, #0]
800488c: 461a mov r2, r3
800488e: 68bb ldr r3, [r7, #8]
8004890: 781b ldrb r3, [r3, #0]
8004892: 009b lsls r3, r3, #2
8004894: 4413 add r3, r2
8004896: 881b ldrh r3, [r3, #0]
8004898: b29b uxth r3, r3
800489a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800489e: f023 0370 bic.w r3, r3, #112 @ 0x70
80048a2: 83fb strh r3, [r7, #30]
80048a4: 8bfb ldrh r3, [r7, #30]
80048a6: f483 5300 eor.w r3, r3, #8192 @ 0x2000
80048aa: 83fb strh r3, [r7, #30]
80048ac: 68fb ldr r3, [r7, #12]
80048ae: 681b ldr r3, [r3, #0]
80048b0: 461a mov r2, r3
80048b2: 68bb ldr r3, [r7, #8]
80048b4: 781b ldrb r3, [r3, #0]
80048b6: 009b lsls r3, r3, #2
80048b8: 441a add r2, r3
80048ba: 8bfb ldrh r3, [r7, #30]
80048bc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80048c0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80048c4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80048c8: f043 0380 orr.w r3, r3, #128 @ 0x80
80048cc: b29b uxth r3, r3
80048ce: 8013 strh r3, [r2, #0]
}
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
80048d0: 88fb ldrh r3, [r7, #6]
80048d2: f003 0340 and.w r3, r3, #64 @ 0x40
80048d6: 2b00 cmp r3, #0
80048d8: d11f bne.n 800491a <HAL_PCD_EP_DB_Receive+0x1f8>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
80048da: 68fb ldr r3, [r7, #12]
80048dc: 681b ldr r3, [r3, #0]
80048de: 461a mov r2, r3
80048e0: 68bb ldr r3, [r7, #8]
80048e2: 781b ldrb r3, [r3, #0]
80048e4: 009b lsls r3, r3, #2
80048e6: 4413 add r3, r2
80048e8: 881b ldrh r3, [r3, #0]
80048ea: b29b uxth r3, r3
80048ec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80048f0: f023 0370 bic.w r3, r3, #112 @ 0x70
80048f4: 83bb strh r3, [r7, #28]
80048f6: 68fb ldr r3, [r7, #12]
80048f8: 681b ldr r3, [r3, #0]
80048fa: 461a mov r2, r3
80048fc: 68bb ldr r3, [r7, #8]
80048fe: 781b ldrb r3, [r3, #0]
8004900: 009b lsls r3, r3, #2
8004902: 441a add r2, r3
8004904: 8bbb ldrh r3, [r7, #28]
8004906: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800490a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800490e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004912: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8004916: b29b uxth r3, r3
8004918: 8013 strh r3, [r2, #0]
}
if (count != 0U)
800491a: 8b7b ldrh r3, [r7, #26]
800491c: 2b00 cmp r3, #0
800491e: d008 beq.n 8004932 <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8004920: 68fb ldr r3, [r7, #12]
8004922: 6818 ldr r0, [r3, #0]
8004924: 68bb ldr r3, [r7, #8]
8004926: 6959 ldr r1, [r3, #20]
8004928: 68bb ldr r3, [r7, #8]
800492a: 895a ldrh r2, [r3, #10]
800492c: 8b7b ldrh r3, [r7, #26]
800492e: f004 fb9a bl 8009066 <USB_ReadPMA>
}
}
return count;
8004932: 8b7b ldrh r3, [r7, #26]
}
8004934: 4618 mov r0, r3
8004936: 3720 adds r7, #32
8004938: 46bd mov sp, r7
800493a: bd80 pop {r7, pc}
0800493c <HAL_PCD_EP_DB_Transmit>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
800493c: b580 push {r7, lr}
800493e: b0a4 sub sp, #144 @ 0x90
8004940: af00 add r7, sp, #0
8004942: 60f8 str r0, [r7, #12]
8004944: 60b9 str r1, [r7, #8]
8004946: 4613 mov r3, r2
8004948: 80fb strh r3, [r7, #6]
uint32_t len;
uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
800494a: 88fb ldrh r3, [r7, #6]
800494c: f003 0340 and.w r3, r3, #64 @ 0x40
8004950: 2b00 cmp r3, #0
8004952: f000 81dd beq.w 8004d10 <HAL_PCD_EP_DB_Transmit+0x3d4>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8004956: 68fb ldr r3, [r7, #12]
8004958: 681b ldr r3, [r3, #0]
800495a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800495e: b29b uxth r3, r3
8004960: 461a mov r2, r3
8004962: 68bb ldr r3, [r7, #8]
8004964: 781b ldrb r3, [r3, #0]
8004966: 00db lsls r3, r3, #3
8004968: 4413 add r3, r2
800496a: 3302 adds r3, #2
800496c: 005b lsls r3, r3, #1
800496e: 68fa ldr r2, [r7, #12]
8004970: 6812 ldr r2, [r2, #0]
8004972: 4413 add r3, r2
8004974: f503 6380 add.w r3, r3, #1024 @ 0x400
8004978: 881b ldrh r3, [r3, #0]
800497a: f3c3 0309 ubfx r3, r3, #0, #10
800497e: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len > TxPctSize)
8004982: 68bb ldr r3, [r7, #8]
8004984: 699a ldr r2, [r3, #24]
8004986: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
800498a: 429a cmp r2, r3
800498c: d907 bls.n 800499e <HAL_PCD_EP_DB_Transmit+0x62>
{
ep->xfer_len -= TxPctSize;
800498e: 68bb ldr r3, [r7, #8]
8004990: 699a ldr r2, [r3, #24]
8004992: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004996: 1ad2 subs r2, r2, r3
8004998: 68bb ldr r3, [r7, #8]
800499a: 619a str r2, [r3, #24]
800499c: e002 b.n 80049a4 <HAL_PCD_EP_DB_Transmit+0x68>
}
else
{
ep->xfer_len = 0U;
800499e: 68bb ldr r3, [r7, #8]
80049a0: 2200 movs r2, #0
80049a2: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
80049a4: 68bb ldr r3, [r7, #8]
80049a6: 699b ldr r3, [r3, #24]
80049a8: 2b00 cmp r3, #0
80049aa: f040 80b9 bne.w 8004b20 <HAL_PCD_EP_DB_Transmit+0x1e4>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80049ae: 68bb ldr r3, [r7, #8]
80049b0: 785b ldrb r3, [r3, #1]
80049b2: 2b00 cmp r3, #0
80049b4: d126 bne.n 8004a04 <HAL_PCD_EP_DB_Transmit+0xc8>
80049b6: 68fb ldr r3, [r7, #12]
80049b8: 681b ldr r3, [r3, #0]
80049ba: 62fb str r3, [r7, #44] @ 0x2c
80049bc: 68fb ldr r3, [r7, #12]
80049be: 681b ldr r3, [r3, #0]
80049c0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80049c4: b29b uxth r3, r3
80049c6: 461a mov r2, r3
80049c8: 6afb ldr r3, [r7, #44] @ 0x2c
80049ca: 4413 add r3, r2
80049cc: 62fb str r3, [r7, #44] @ 0x2c
80049ce: 68bb ldr r3, [r7, #8]
80049d0: 781b ldrb r3, [r3, #0]
80049d2: 011a lsls r2, r3, #4
80049d4: 6afb ldr r3, [r7, #44] @ 0x2c
80049d6: 4413 add r3, r2
80049d8: f203 4304 addw r3, r3, #1028 @ 0x404
80049dc: 62bb str r3, [r7, #40] @ 0x28
80049de: 6abb ldr r3, [r7, #40] @ 0x28
80049e0: 881b ldrh r3, [r3, #0]
80049e2: b29b uxth r3, r3
80049e4: f3c3 0309 ubfx r3, r3, #0, #10
80049e8: b29a uxth r2, r3
80049ea: 6abb ldr r3, [r7, #40] @ 0x28
80049ec: 801a strh r2, [r3, #0]
80049ee: 6abb ldr r3, [r7, #40] @ 0x28
80049f0: 881b ldrh r3, [r3, #0]
80049f2: b29b uxth r3, r3
80049f4: ea6f 4343 mvn.w r3, r3, lsl #17
80049f8: ea6f 4353 mvn.w r3, r3, lsr #17
80049fc: b29a uxth r2, r3
80049fe: 6abb ldr r3, [r7, #40] @ 0x28
8004a00: 801a strh r2, [r3, #0]
8004a02: e01a b.n 8004a3a <HAL_PCD_EP_DB_Transmit+0xfe>
8004a04: 68bb ldr r3, [r7, #8]
8004a06: 785b ldrb r3, [r3, #1]
8004a08: 2b01 cmp r3, #1
8004a0a: d116 bne.n 8004a3a <HAL_PCD_EP_DB_Transmit+0xfe>
8004a0c: 68fb ldr r3, [r7, #12]
8004a0e: 681b ldr r3, [r3, #0]
8004a10: 637b str r3, [r7, #52] @ 0x34
8004a12: 68fb ldr r3, [r7, #12]
8004a14: 681b ldr r3, [r3, #0]
8004a16: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004a1a: b29b uxth r3, r3
8004a1c: 461a mov r2, r3
8004a1e: 6b7b ldr r3, [r7, #52] @ 0x34
8004a20: 4413 add r3, r2
8004a22: 637b str r3, [r7, #52] @ 0x34
8004a24: 68bb ldr r3, [r7, #8]
8004a26: 781b ldrb r3, [r3, #0]
8004a28: 011a lsls r2, r3, #4
8004a2a: 6b7b ldr r3, [r7, #52] @ 0x34
8004a2c: 4413 add r3, r2
8004a2e: f203 4304 addw r3, r3, #1028 @ 0x404
8004a32: 633b str r3, [r7, #48] @ 0x30
8004a34: 6b3b ldr r3, [r7, #48] @ 0x30
8004a36: 2200 movs r2, #0
8004a38: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004a3a: 68fb ldr r3, [r7, #12]
8004a3c: 681b ldr r3, [r3, #0]
8004a3e: 627b str r3, [r7, #36] @ 0x24
8004a40: 68bb ldr r3, [r7, #8]
8004a42: 785b ldrb r3, [r3, #1]
8004a44: 2b00 cmp r3, #0
8004a46: d126 bne.n 8004a96 <HAL_PCD_EP_DB_Transmit+0x15a>
8004a48: 68fb ldr r3, [r7, #12]
8004a4a: 681b ldr r3, [r3, #0]
8004a4c: 61fb str r3, [r7, #28]
8004a4e: 68fb ldr r3, [r7, #12]
8004a50: 681b ldr r3, [r3, #0]
8004a52: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004a56: b29b uxth r3, r3
8004a58: 461a mov r2, r3
8004a5a: 69fb ldr r3, [r7, #28]
8004a5c: 4413 add r3, r2
8004a5e: 61fb str r3, [r7, #28]
8004a60: 68bb ldr r3, [r7, #8]
8004a62: 781b ldrb r3, [r3, #0]
8004a64: 011a lsls r2, r3, #4
8004a66: 69fb ldr r3, [r7, #28]
8004a68: 4413 add r3, r2
8004a6a: f203 430c addw r3, r3, #1036 @ 0x40c
8004a6e: 61bb str r3, [r7, #24]
8004a70: 69bb ldr r3, [r7, #24]
8004a72: 881b ldrh r3, [r3, #0]
8004a74: b29b uxth r3, r3
8004a76: f3c3 0309 ubfx r3, r3, #0, #10
8004a7a: b29a uxth r2, r3
8004a7c: 69bb ldr r3, [r7, #24]
8004a7e: 801a strh r2, [r3, #0]
8004a80: 69bb ldr r3, [r7, #24]
8004a82: 881b ldrh r3, [r3, #0]
8004a84: b29b uxth r3, r3
8004a86: ea6f 4343 mvn.w r3, r3, lsl #17
8004a8a: ea6f 4353 mvn.w r3, r3, lsr #17
8004a8e: b29a uxth r2, r3
8004a90: 69bb ldr r3, [r7, #24]
8004a92: 801a strh r2, [r3, #0]
8004a94: e017 b.n 8004ac6 <HAL_PCD_EP_DB_Transmit+0x18a>
8004a96: 68bb ldr r3, [r7, #8]
8004a98: 785b ldrb r3, [r3, #1]
8004a9a: 2b01 cmp r3, #1
8004a9c: d113 bne.n 8004ac6 <HAL_PCD_EP_DB_Transmit+0x18a>
8004a9e: 68fb ldr r3, [r7, #12]
8004aa0: 681b ldr r3, [r3, #0]
8004aa2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004aa6: b29b uxth r3, r3
8004aa8: 461a mov r2, r3
8004aaa: 6a7b ldr r3, [r7, #36] @ 0x24
8004aac: 4413 add r3, r2
8004aae: 627b str r3, [r7, #36] @ 0x24
8004ab0: 68bb ldr r3, [r7, #8]
8004ab2: 781b ldrb r3, [r3, #0]
8004ab4: 011a lsls r2, r3, #4
8004ab6: 6a7b ldr r3, [r7, #36] @ 0x24
8004ab8: 4413 add r3, r2
8004aba: f203 430c addw r3, r3, #1036 @ 0x40c
8004abe: 623b str r3, [r7, #32]
8004ac0: 6a3b ldr r3, [r7, #32]
8004ac2: 2200 movs r2, #0
8004ac4: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8004ac6: 68bb ldr r3, [r7, #8]
8004ac8: 781b ldrb r3, [r3, #0]
8004aca: 4619 mov r1, r3
8004acc: 68f8 ldr r0, [r7, #12]
8004ace: f006 f948 bl 800ad62 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8004ad2: 88fb ldrh r3, [r7, #6]
8004ad4: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004ad8: 2b00 cmp r3, #0
8004ada: f000 82fc beq.w 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004ade: 68fb ldr r3, [r7, #12]
8004ae0: 681b ldr r3, [r3, #0]
8004ae2: 461a mov r2, r3
8004ae4: 68bb ldr r3, [r7, #8]
8004ae6: 781b ldrb r3, [r3, #0]
8004ae8: 009b lsls r3, r3, #2
8004aea: 4413 add r3, r2
8004aec: 881b ldrh r3, [r3, #0]
8004aee: b29b uxth r3, r3
8004af0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004af4: f023 0370 bic.w r3, r3, #112 @ 0x70
8004af8: 82fb strh r3, [r7, #22]
8004afa: 68fb ldr r3, [r7, #12]
8004afc: 681b ldr r3, [r3, #0]
8004afe: 461a mov r2, r3
8004b00: 68bb ldr r3, [r7, #8]
8004b02: 781b ldrb r3, [r3, #0]
8004b04: 009b lsls r3, r3, #2
8004b06: 441a add r2, r3
8004b08: 8afb ldrh r3, [r7, #22]
8004b0a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b0e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b12: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004b16: f043 0380 orr.w r3, r3, #128 @ 0x80
8004b1a: b29b uxth r3, r3
8004b1c: 8013 strh r3, [r2, #0]
8004b1e: e2da b.n 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8004b20: 88fb ldrh r3, [r7, #6]
8004b22: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004b26: 2b00 cmp r3, #0
8004b28: d021 beq.n 8004b6e <HAL_PCD_EP_DB_Transmit+0x232>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004b2a: 68fb ldr r3, [r7, #12]
8004b2c: 681b ldr r3, [r3, #0]
8004b2e: 461a mov r2, r3
8004b30: 68bb ldr r3, [r7, #8]
8004b32: 781b ldrb r3, [r3, #0]
8004b34: 009b lsls r3, r3, #2
8004b36: 4413 add r3, r2
8004b38: 881b ldrh r3, [r3, #0]
8004b3a: b29b uxth r3, r3
8004b3c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004b40: f023 0370 bic.w r3, r3, #112 @ 0x70
8004b44: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8004b48: 68fb ldr r3, [r7, #12]
8004b4a: 681b ldr r3, [r3, #0]
8004b4c: 461a mov r2, r3
8004b4e: 68bb ldr r3, [r7, #8]
8004b50: 781b ldrb r3, [r3, #0]
8004b52: 009b lsls r3, r3, #2
8004b54: 441a add r2, r3
8004b56: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8004b5a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b5e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b62: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004b66: f043 0380 orr.w r3, r3, #128 @ 0x80
8004b6a: b29b uxth r3, r3
8004b6c: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8004b6e: 68bb ldr r3, [r7, #8]
8004b70: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8004b74: 2b01 cmp r3, #1
8004b76: f040 82ae bne.w 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
8004b7a: 68bb ldr r3, [r7, #8]
8004b7c: 695a ldr r2, [r3, #20]
8004b7e: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004b82: 441a add r2, r3
8004b84: 68bb ldr r3, [r7, #8]
8004b86: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8004b88: 68bb ldr r3, [r7, #8]
8004b8a: 69da ldr r2, [r3, #28]
8004b8c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004b90: 441a add r2, r3
8004b92: 68bb ldr r3, [r7, #8]
8004b94: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8004b96: 68bb ldr r3, [r7, #8]
8004b98: 6a1a ldr r2, [r3, #32]
8004b9a: 68bb ldr r3, [r7, #8]
8004b9c: 691b ldr r3, [r3, #16]
8004b9e: 429a cmp r2, r3
8004ba0: d30b bcc.n 8004bba <HAL_PCD_EP_DB_Transmit+0x27e>
{
len = ep->maxpacket;
8004ba2: 68bb ldr r3, [r7, #8]
8004ba4: 691b ldr r3, [r3, #16]
8004ba6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8004baa: 68bb ldr r3, [r7, #8]
8004bac: 6a1a ldr r2, [r3, #32]
8004bae: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004bb2: 1ad2 subs r2, r2, r3
8004bb4: 68bb ldr r3, [r7, #8]
8004bb6: 621a str r2, [r3, #32]
8004bb8: e017 b.n 8004bea <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else if (ep->xfer_len_db == 0U)
8004bba: 68bb ldr r3, [r7, #8]
8004bbc: 6a1b ldr r3, [r3, #32]
8004bbe: 2b00 cmp r3, #0
8004bc0: d108 bne.n 8004bd4 <HAL_PCD_EP_DB_Transmit+0x298>
{
len = TxPctSize;
8004bc2: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004bc6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8004bca: 68bb ldr r3, [r7, #8]
8004bcc: 2200 movs r2, #0
8004bce: f883 2024 strb.w r2, [r3, #36] @ 0x24
8004bd2: e00a b.n 8004bea <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else
{
ep->xfer_fill_db = 0U;
8004bd4: 68bb ldr r3, [r7, #8]
8004bd6: 2200 movs r2, #0
8004bd8: f883 2024 strb.w r2, [r3, #36] @ 0x24
len = ep->xfer_len_db;
8004bdc: 68bb ldr r3, [r7, #8]
8004bde: 6a1b ldr r3, [r3, #32]
8004be0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8004be4: 68bb ldr r3, [r7, #8]
8004be6: 2200 movs r2, #0
8004be8: 621a str r2, [r3, #32]
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8004bea: 68bb ldr r3, [r7, #8]
8004bec: 785b ldrb r3, [r3, #1]
8004bee: 2b00 cmp r3, #0
8004bf0: d165 bne.n 8004cbe <HAL_PCD_EP_DB_Transmit+0x382>
8004bf2: 68fb ldr r3, [r7, #12]
8004bf4: 681b ldr r3, [r3, #0]
8004bf6: 63fb str r3, [r7, #60] @ 0x3c
8004bf8: 68fb ldr r3, [r7, #12]
8004bfa: 681b ldr r3, [r3, #0]
8004bfc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004c00: b29b uxth r3, r3
8004c02: 461a mov r2, r3
8004c04: 6bfb ldr r3, [r7, #60] @ 0x3c
8004c06: 4413 add r3, r2
8004c08: 63fb str r3, [r7, #60] @ 0x3c
8004c0a: 68bb ldr r3, [r7, #8]
8004c0c: 781b ldrb r3, [r3, #0]
8004c0e: 011a lsls r2, r3, #4
8004c10: 6bfb ldr r3, [r7, #60] @ 0x3c
8004c12: 4413 add r3, r2
8004c14: f203 4304 addw r3, r3, #1028 @ 0x404
8004c18: 63bb str r3, [r7, #56] @ 0x38
8004c1a: 6bbb ldr r3, [r7, #56] @ 0x38
8004c1c: 881b ldrh r3, [r3, #0]
8004c1e: b29b uxth r3, r3
8004c20: f3c3 0309 ubfx r3, r3, #0, #10
8004c24: b29a uxth r2, r3
8004c26: 6bbb ldr r3, [r7, #56] @ 0x38
8004c28: 801a strh r2, [r3, #0]
8004c2a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c2e: 2b3e cmp r3, #62 @ 0x3e
8004c30: d91d bls.n 8004c6e <HAL_PCD_EP_DB_Transmit+0x332>
8004c32: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c36: 095b lsrs r3, r3, #5
8004c38: 64bb str r3, [r7, #72] @ 0x48
8004c3a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c3e: f003 031f and.w r3, r3, #31
8004c42: 2b00 cmp r3, #0
8004c44: d102 bne.n 8004c4c <HAL_PCD_EP_DB_Transmit+0x310>
8004c46: 6cbb ldr r3, [r7, #72] @ 0x48
8004c48: 3b01 subs r3, #1
8004c4a: 64bb str r3, [r7, #72] @ 0x48
8004c4c: 6bbb ldr r3, [r7, #56] @ 0x38
8004c4e: 881b ldrh r3, [r3, #0]
8004c50: b29a uxth r2, r3
8004c52: 6cbb ldr r3, [r7, #72] @ 0x48
8004c54: b29b uxth r3, r3
8004c56: 029b lsls r3, r3, #10
8004c58: b29b uxth r3, r3
8004c5a: 4313 orrs r3, r2
8004c5c: b29b uxth r3, r3
8004c5e: ea6f 4343 mvn.w r3, r3, lsl #17
8004c62: ea6f 4353 mvn.w r3, r3, lsr #17
8004c66: b29a uxth r2, r3
8004c68: 6bbb ldr r3, [r7, #56] @ 0x38
8004c6a: 801a strh r2, [r3, #0]
8004c6c: e044 b.n 8004cf8 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004c6e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c72: 2b00 cmp r3, #0
8004c74: d10a bne.n 8004c8c <HAL_PCD_EP_DB_Transmit+0x350>
8004c76: 6bbb ldr r3, [r7, #56] @ 0x38
8004c78: 881b ldrh r3, [r3, #0]
8004c7a: b29b uxth r3, r3
8004c7c: ea6f 4343 mvn.w r3, r3, lsl #17
8004c80: ea6f 4353 mvn.w r3, r3, lsr #17
8004c84: b29a uxth r2, r3
8004c86: 6bbb ldr r3, [r7, #56] @ 0x38
8004c88: 801a strh r2, [r3, #0]
8004c8a: e035 b.n 8004cf8 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004c8c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c90: 085b lsrs r3, r3, #1
8004c92: 64bb str r3, [r7, #72] @ 0x48
8004c94: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004c98: f003 0301 and.w r3, r3, #1
8004c9c: 2b00 cmp r3, #0
8004c9e: d002 beq.n 8004ca6 <HAL_PCD_EP_DB_Transmit+0x36a>
8004ca0: 6cbb ldr r3, [r7, #72] @ 0x48
8004ca2: 3301 adds r3, #1
8004ca4: 64bb str r3, [r7, #72] @ 0x48
8004ca6: 6bbb ldr r3, [r7, #56] @ 0x38
8004ca8: 881b ldrh r3, [r3, #0]
8004caa: b29a uxth r2, r3
8004cac: 6cbb ldr r3, [r7, #72] @ 0x48
8004cae: b29b uxth r3, r3
8004cb0: 029b lsls r3, r3, #10
8004cb2: b29b uxth r3, r3
8004cb4: 4313 orrs r3, r2
8004cb6: b29a uxth r2, r3
8004cb8: 6bbb ldr r3, [r7, #56] @ 0x38
8004cba: 801a strh r2, [r3, #0]
8004cbc: e01c b.n 8004cf8 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004cbe: 68bb ldr r3, [r7, #8]
8004cc0: 785b ldrb r3, [r3, #1]
8004cc2: 2b01 cmp r3, #1
8004cc4: d118 bne.n 8004cf8 <HAL_PCD_EP_DB_Transmit+0x3bc>
8004cc6: 68fb ldr r3, [r7, #12]
8004cc8: 681b ldr r3, [r3, #0]
8004cca: 647b str r3, [r7, #68] @ 0x44
8004ccc: 68fb ldr r3, [r7, #12]
8004cce: 681b ldr r3, [r3, #0]
8004cd0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004cd4: b29b uxth r3, r3
8004cd6: 461a mov r2, r3
8004cd8: 6c7b ldr r3, [r7, #68] @ 0x44
8004cda: 4413 add r3, r2
8004cdc: 647b str r3, [r7, #68] @ 0x44
8004cde: 68bb ldr r3, [r7, #8]
8004ce0: 781b ldrb r3, [r3, #0]
8004ce2: 011a lsls r2, r3, #4
8004ce4: 6c7b ldr r3, [r7, #68] @ 0x44
8004ce6: 4413 add r3, r2
8004ce8: f203 4304 addw r3, r3, #1028 @ 0x404
8004cec: 643b str r3, [r7, #64] @ 0x40
8004cee: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004cf2: b29a uxth r2, r3
8004cf4: 6c3b ldr r3, [r7, #64] @ 0x40
8004cf6: 801a strh r2, [r3, #0]
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
8004cf8: 68fb ldr r3, [r7, #12]
8004cfa: 6818 ldr r0, [r3, #0]
8004cfc: 68bb ldr r3, [r7, #8]
8004cfe: 6959 ldr r1, [r3, #20]
8004d00: 68bb ldr r3, [r7, #8]
8004d02: 891a ldrh r2, [r3, #8]
8004d04: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004d08: b29b uxth r3, r3
8004d0a: f004 f966 bl 8008fda <USB_WritePMA>
8004d0e: e1e2 b.n 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8004d10: 68fb ldr r3, [r7, #12]
8004d12: 681b ldr r3, [r3, #0]
8004d14: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004d18: b29b uxth r3, r3
8004d1a: 461a mov r2, r3
8004d1c: 68bb ldr r3, [r7, #8]
8004d1e: 781b ldrb r3, [r3, #0]
8004d20: 00db lsls r3, r3, #3
8004d22: 4413 add r3, r2
8004d24: 3306 adds r3, #6
8004d26: 005b lsls r3, r3, #1
8004d28: 68fa ldr r2, [r7, #12]
8004d2a: 6812 ldr r2, [r2, #0]
8004d2c: 4413 add r3, r2
8004d2e: f503 6380 add.w r3, r3, #1024 @ 0x400
8004d32: 881b ldrh r3, [r3, #0]
8004d34: f3c3 0309 ubfx r3, r3, #0, #10
8004d38: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len >= TxPctSize)
8004d3c: 68bb ldr r3, [r7, #8]
8004d3e: 699a ldr r2, [r3, #24]
8004d40: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004d44: 429a cmp r2, r3
8004d46: d307 bcc.n 8004d58 <HAL_PCD_EP_DB_Transmit+0x41c>
{
ep->xfer_len -= TxPctSize;
8004d48: 68bb ldr r3, [r7, #8]
8004d4a: 699a ldr r2, [r3, #24]
8004d4c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004d50: 1ad2 subs r2, r2, r3
8004d52: 68bb ldr r3, [r7, #8]
8004d54: 619a str r2, [r3, #24]
8004d56: e002 b.n 8004d5e <HAL_PCD_EP_DB_Transmit+0x422>
}
else
{
ep->xfer_len = 0U;
8004d58: 68bb ldr r3, [r7, #8]
8004d5a: 2200 movs r2, #0
8004d5c: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8004d5e: 68bb ldr r3, [r7, #8]
8004d60: 699b ldr r3, [r3, #24]
8004d62: 2b00 cmp r3, #0
8004d64: f040 80c0 bne.w 8004ee8 <HAL_PCD_EP_DB_Transmit+0x5ac>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004d68: 68bb ldr r3, [r7, #8]
8004d6a: 785b ldrb r3, [r3, #1]
8004d6c: 2b00 cmp r3, #0
8004d6e: d126 bne.n 8004dbe <HAL_PCD_EP_DB_Transmit+0x482>
8004d70: 68fb ldr r3, [r7, #12]
8004d72: 681b ldr r3, [r3, #0]
8004d74: 67fb str r3, [r7, #124] @ 0x7c
8004d76: 68fb ldr r3, [r7, #12]
8004d78: 681b ldr r3, [r3, #0]
8004d7a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004d7e: b29b uxth r3, r3
8004d80: 461a mov r2, r3
8004d82: 6ffb ldr r3, [r7, #124] @ 0x7c
8004d84: 4413 add r3, r2
8004d86: 67fb str r3, [r7, #124] @ 0x7c
8004d88: 68bb ldr r3, [r7, #8]
8004d8a: 781b ldrb r3, [r3, #0]
8004d8c: 011a lsls r2, r3, #4
8004d8e: 6ffb ldr r3, [r7, #124] @ 0x7c
8004d90: 4413 add r3, r2
8004d92: f203 4304 addw r3, r3, #1028 @ 0x404
8004d96: 67bb str r3, [r7, #120] @ 0x78
8004d98: 6fbb ldr r3, [r7, #120] @ 0x78
8004d9a: 881b ldrh r3, [r3, #0]
8004d9c: b29b uxth r3, r3
8004d9e: f3c3 0309 ubfx r3, r3, #0, #10
8004da2: b29a uxth r2, r3
8004da4: 6fbb ldr r3, [r7, #120] @ 0x78
8004da6: 801a strh r2, [r3, #0]
8004da8: 6fbb ldr r3, [r7, #120] @ 0x78
8004daa: 881b ldrh r3, [r3, #0]
8004dac: b29b uxth r3, r3
8004dae: ea6f 4343 mvn.w r3, r3, lsl #17
8004db2: ea6f 4353 mvn.w r3, r3, lsr #17
8004db6: b29a uxth r2, r3
8004db8: 6fbb ldr r3, [r7, #120] @ 0x78
8004dba: 801a strh r2, [r3, #0]
8004dbc: e01a b.n 8004df4 <HAL_PCD_EP_DB_Transmit+0x4b8>
8004dbe: 68bb ldr r3, [r7, #8]
8004dc0: 785b ldrb r3, [r3, #1]
8004dc2: 2b01 cmp r3, #1
8004dc4: d116 bne.n 8004df4 <HAL_PCD_EP_DB_Transmit+0x4b8>
8004dc6: 68fb ldr r3, [r7, #12]
8004dc8: 681b ldr r3, [r3, #0]
8004dca: 667b str r3, [r7, #100] @ 0x64
8004dcc: 68fb ldr r3, [r7, #12]
8004dce: 681b ldr r3, [r3, #0]
8004dd0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004dd4: b29b uxth r3, r3
8004dd6: 461a mov r2, r3
8004dd8: 6e7b ldr r3, [r7, #100] @ 0x64
8004dda: 4413 add r3, r2
8004ddc: 667b str r3, [r7, #100] @ 0x64
8004dde: 68bb ldr r3, [r7, #8]
8004de0: 781b ldrb r3, [r3, #0]
8004de2: 011a lsls r2, r3, #4
8004de4: 6e7b ldr r3, [r7, #100] @ 0x64
8004de6: 4413 add r3, r2
8004de8: f203 4304 addw r3, r3, #1028 @ 0x404
8004dec: 663b str r3, [r7, #96] @ 0x60
8004dee: 6e3b ldr r3, [r7, #96] @ 0x60
8004df0: 2200 movs r2, #0
8004df2: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8004df4: 68fb ldr r3, [r7, #12]
8004df6: 681b ldr r3, [r3, #0]
8004df8: 677b str r3, [r7, #116] @ 0x74
8004dfa: 68bb ldr r3, [r7, #8]
8004dfc: 785b ldrb r3, [r3, #1]
8004dfe: 2b00 cmp r3, #0
8004e00: d12b bne.n 8004e5a <HAL_PCD_EP_DB_Transmit+0x51e>
8004e02: 68fb ldr r3, [r7, #12]
8004e04: 681b ldr r3, [r3, #0]
8004e06: 66fb str r3, [r7, #108] @ 0x6c
8004e08: 68fb ldr r3, [r7, #12]
8004e0a: 681b ldr r3, [r3, #0]
8004e0c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e10: b29b uxth r3, r3
8004e12: 461a mov r2, r3
8004e14: 6efb ldr r3, [r7, #108] @ 0x6c
8004e16: 4413 add r3, r2
8004e18: 66fb str r3, [r7, #108] @ 0x6c
8004e1a: 68bb ldr r3, [r7, #8]
8004e1c: 781b ldrb r3, [r3, #0]
8004e1e: 011a lsls r2, r3, #4
8004e20: 6efb ldr r3, [r7, #108] @ 0x6c
8004e22: 4413 add r3, r2
8004e24: f203 430c addw r3, r3, #1036 @ 0x40c
8004e28: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8004e2c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e30: 881b ldrh r3, [r3, #0]
8004e32: b29b uxth r3, r3
8004e34: f3c3 0309 ubfx r3, r3, #0, #10
8004e38: b29a uxth r2, r3
8004e3a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e3e: 801a strh r2, [r3, #0]
8004e40: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e44: 881b ldrh r3, [r3, #0]
8004e46: b29b uxth r3, r3
8004e48: ea6f 4343 mvn.w r3, r3, lsl #17
8004e4c: ea6f 4353 mvn.w r3, r3, lsr #17
8004e50: b29a uxth r2, r3
8004e52: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8004e56: 801a strh r2, [r3, #0]
8004e58: e017 b.n 8004e8a <HAL_PCD_EP_DB_Transmit+0x54e>
8004e5a: 68bb ldr r3, [r7, #8]
8004e5c: 785b ldrb r3, [r3, #1]
8004e5e: 2b01 cmp r3, #1
8004e60: d113 bne.n 8004e8a <HAL_PCD_EP_DB_Transmit+0x54e>
8004e62: 68fb ldr r3, [r7, #12]
8004e64: 681b ldr r3, [r3, #0]
8004e66: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e6a: b29b uxth r3, r3
8004e6c: 461a mov r2, r3
8004e6e: 6f7b ldr r3, [r7, #116] @ 0x74
8004e70: 4413 add r3, r2
8004e72: 677b str r3, [r7, #116] @ 0x74
8004e74: 68bb ldr r3, [r7, #8]
8004e76: 781b ldrb r3, [r3, #0]
8004e78: 011a lsls r2, r3, #4
8004e7a: 6f7b ldr r3, [r7, #116] @ 0x74
8004e7c: 4413 add r3, r2
8004e7e: f203 430c addw r3, r3, #1036 @ 0x40c
8004e82: 673b str r3, [r7, #112] @ 0x70
8004e84: 6f3b ldr r3, [r7, #112] @ 0x70
8004e86: 2200 movs r2, #0
8004e88: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8004e8a: 68bb ldr r3, [r7, #8]
8004e8c: 781b ldrb r3, [r3, #0]
8004e8e: 4619 mov r1, r3
8004e90: 68f8 ldr r0, [r7, #12]
8004e92: f005 ff66 bl 800ad62 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8004e96: 88fb ldrh r3, [r7, #6]
8004e98: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004e9c: 2b00 cmp r3, #0
8004e9e: f040 811a bne.w 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004ea2: 68fb ldr r3, [r7, #12]
8004ea4: 681b ldr r3, [r3, #0]
8004ea6: 461a mov r2, r3
8004ea8: 68bb ldr r3, [r7, #8]
8004eaa: 781b ldrb r3, [r3, #0]
8004eac: 009b lsls r3, r3, #2
8004eae: 4413 add r3, r2
8004eb0: 881b ldrh r3, [r3, #0]
8004eb2: b29b uxth r3, r3
8004eb4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004eb8: f023 0370 bic.w r3, r3, #112 @ 0x70
8004ebc: f8a7 3088 strh.w r3, [r7, #136] @ 0x88
8004ec0: 68fb ldr r3, [r7, #12]
8004ec2: 681b ldr r3, [r3, #0]
8004ec4: 461a mov r2, r3
8004ec6: 68bb ldr r3, [r7, #8]
8004ec8: 781b ldrb r3, [r3, #0]
8004eca: 009b lsls r3, r3, #2
8004ecc: 441a add r2, r3
8004ece: f8b7 3088 ldrh.w r3, [r7, #136] @ 0x88
8004ed2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004ed6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004eda: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004ede: f043 0380 orr.w r3, r3, #128 @ 0x80
8004ee2: b29b uxth r3, r3
8004ee4: 8013 strh r3, [r2, #0]
8004ee6: e0f6 b.n 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8004ee8: 88fb ldrh r3, [r7, #6]
8004eea: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004eee: 2b00 cmp r3, #0
8004ef0: d121 bne.n 8004f36 <HAL_PCD_EP_DB_Transmit+0x5fa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8004ef2: 68fb ldr r3, [r7, #12]
8004ef4: 681b ldr r3, [r3, #0]
8004ef6: 461a mov r2, r3
8004ef8: 68bb ldr r3, [r7, #8]
8004efa: 781b ldrb r3, [r3, #0]
8004efc: 009b lsls r3, r3, #2
8004efe: 4413 add r3, r2
8004f00: 881b ldrh r3, [r3, #0]
8004f02: b29b uxth r3, r3
8004f04: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004f08: f023 0370 bic.w r3, r3, #112 @ 0x70
8004f0c: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
8004f10: 68fb ldr r3, [r7, #12]
8004f12: 681b ldr r3, [r3, #0]
8004f14: 461a mov r2, r3
8004f16: 68bb ldr r3, [r7, #8]
8004f18: 781b ldrb r3, [r3, #0]
8004f1a: 009b lsls r3, r3, #2
8004f1c: 441a add r2, r3
8004f1e: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8004f22: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004f26: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004f2a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004f2e: f043 0380 orr.w r3, r3, #128 @ 0x80
8004f32: b29b uxth r3, r3
8004f34: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8004f36: 68bb ldr r3, [r7, #8]
8004f38: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8004f3c: 2b01 cmp r3, #1
8004f3e: f040 80ca bne.w 80050d6 <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
8004f42: 68bb ldr r3, [r7, #8]
8004f44: 695a ldr r2, [r3, #20]
8004f46: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004f4a: 441a add r2, r3
8004f4c: 68bb ldr r3, [r7, #8]
8004f4e: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8004f50: 68bb ldr r3, [r7, #8]
8004f52: 69da ldr r2, [r3, #28]
8004f54: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004f58: 441a add r2, r3
8004f5a: 68bb ldr r3, [r7, #8]
8004f5c: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8004f5e: 68bb ldr r3, [r7, #8]
8004f60: 6a1a ldr r2, [r3, #32]
8004f62: 68bb ldr r3, [r7, #8]
8004f64: 691b ldr r3, [r3, #16]
8004f66: 429a cmp r2, r3
8004f68: d30b bcc.n 8004f82 <HAL_PCD_EP_DB_Transmit+0x646>
{
len = ep->maxpacket;
8004f6a: 68bb ldr r3, [r7, #8]
8004f6c: 691b ldr r3, [r3, #16]
8004f6e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8004f72: 68bb ldr r3, [r7, #8]
8004f74: 6a1a ldr r2, [r3, #32]
8004f76: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004f7a: 1ad2 subs r2, r2, r3
8004f7c: 68bb ldr r3, [r7, #8]
8004f7e: 621a str r2, [r3, #32]
8004f80: e017 b.n 8004fb2 <HAL_PCD_EP_DB_Transmit+0x676>
}
else if (ep->xfer_len_db == 0U)
8004f82: 68bb ldr r3, [r7, #8]
8004f84: 6a1b ldr r3, [r3, #32]
8004f86: 2b00 cmp r3, #0
8004f88: d108 bne.n 8004f9c <HAL_PCD_EP_DB_Transmit+0x660>
{
len = TxPctSize;
8004f8a: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8004f8e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8004f92: 68bb ldr r3, [r7, #8]
8004f94: 2200 movs r2, #0
8004f96: f883 2024 strb.w r2, [r3, #36] @ 0x24
8004f9a: e00a b.n 8004fb2 <HAL_PCD_EP_DB_Transmit+0x676>
}
else
{
len = ep->xfer_len_db;
8004f9c: 68bb ldr r3, [r7, #8]
8004f9e: 6a1b ldr r3, [r3, #32]
8004fa0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8004fa4: 68bb ldr r3, [r7, #8]
8004fa6: 2200 movs r2, #0
8004fa8: 621a str r2, [r3, #32]
ep->xfer_fill_db = 0;
8004faa: 68bb ldr r3, [r7, #8]
8004fac: 2200 movs r2, #0
8004fae: f883 2024 strb.w r2, [r3, #36] @ 0x24
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8004fb2: 68fb ldr r3, [r7, #12]
8004fb4: 681b ldr r3, [r3, #0]
8004fb6: 657b str r3, [r7, #84] @ 0x54
8004fb8: 68bb ldr r3, [r7, #8]
8004fba: 785b ldrb r3, [r3, #1]
8004fbc: 2b00 cmp r3, #0
8004fbe: d165 bne.n 800508c <HAL_PCD_EP_DB_Transmit+0x750>
8004fc0: 68fb ldr r3, [r7, #12]
8004fc2: 681b ldr r3, [r3, #0]
8004fc4: 65fb str r3, [r7, #92] @ 0x5c
8004fc6: 68fb ldr r3, [r7, #12]
8004fc8: 681b ldr r3, [r3, #0]
8004fca: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004fce: b29b uxth r3, r3
8004fd0: 461a mov r2, r3
8004fd2: 6dfb ldr r3, [r7, #92] @ 0x5c
8004fd4: 4413 add r3, r2
8004fd6: 65fb str r3, [r7, #92] @ 0x5c
8004fd8: 68bb ldr r3, [r7, #8]
8004fda: 781b ldrb r3, [r3, #0]
8004fdc: 011a lsls r2, r3, #4
8004fde: 6dfb ldr r3, [r7, #92] @ 0x5c
8004fe0: 4413 add r3, r2
8004fe2: f203 430c addw r3, r3, #1036 @ 0x40c
8004fe6: 65bb str r3, [r7, #88] @ 0x58
8004fe8: 6dbb ldr r3, [r7, #88] @ 0x58
8004fea: 881b ldrh r3, [r3, #0]
8004fec: b29b uxth r3, r3
8004fee: f3c3 0309 ubfx r3, r3, #0, #10
8004ff2: b29a uxth r2, r3
8004ff4: 6dbb ldr r3, [r7, #88] @ 0x58
8004ff6: 801a strh r2, [r3, #0]
8004ff8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8004ffc: 2b3e cmp r3, #62 @ 0x3e
8004ffe: d91d bls.n 800503c <HAL_PCD_EP_DB_Transmit+0x700>
8005000: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005004: 095b lsrs r3, r3, #5
8005006: 66bb str r3, [r7, #104] @ 0x68
8005008: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800500c: f003 031f and.w r3, r3, #31
8005010: 2b00 cmp r3, #0
8005012: d102 bne.n 800501a <HAL_PCD_EP_DB_Transmit+0x6de>
8005014: 6ebb ldr r3, [r7, #104] @ 0x68
8005016: 3b01 subs r3, #1
8005018: 66bb str r3, [r7, #104] @ 0x68
800501a: 6dbb ldr r3, [r7, #88] @ 0x58
800501c: 881b ldrh r3, [r3, #0]
800501e: b29a uxth r2, r3
8005020: 6ebb ldr r3, [r7, #104] @ 0x68
8005022: b29b uxth r3, r3
8005024: 029b lsls r3, r3, #10
8005026: b29b uxth r3, r3
8005028: 4313 orrs r3, r2
800502a: b29b uxth r3, r3
800502c: ea6f 4343 mvn.w r3, r3, lsl #17
8005030: ea6f 4353 mvn.w r3, r3, lsr #17
8005034: b29a uxth r2, r3
8005036: 6dbb ldr r3, [r7, #88] @ 0x58
8005038: 801a strh r2, [r3, #0]
800503a: e041 b.n 80050c0 <HAL_PCD_EP_DB_Transmit+0x784>
800503c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005040: 2b00 cmp r3, #0
8005042: d10a bne.n 800505a <HAL_PCD_EP_DB_Transmit+0x71e>
8005044: 6dbb ldr r3, [r7, #88] @ 0x58
8005046: 881b ldrh r3, [r3, #0]
8005048: b29b uxth r3, r3
800504a: ea6f 4343 mvn.w r3, r3, lsl #17
800504e: ea6f 4353 mvn.w r3, r3, lsr #17
8005052: b29a uxth r2, r3
8005054: 6dbb ldr r3, [r7, #88] @ 0x58
8005056: 801a strh r2, [r3, #0]
8005058: e032 b.n 80050c0 <HAL_PCD_EP_DB_Transmit+0x784>
800505a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800505e: 085b lsrs r3, r3, #1
8005060: 66bb str r3, [r7, #104] @ 0x68
8005062: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005066: f003 0301 and.w r3, r3, #1
800506a: 2b00 cmp r3, #0
800506c: d002 beq.n 8005074 <HAL_PCD_EP_DB_Transmit+0x738>
800506e: 6ebb ldr r3, [r7, #104] @ 0x68
8005070: 3301 adds r3, #1
8005072: 66bb str r3, [r7, #104] @ 0x68
8005074: 6dbb ldr r3, [r7, #88] @ 0x58
8005076: 881b ldrh r3, [r3, #0]
8005078: b29a uxth r2, r3
800507a: 6ebb ldr r3, [r7, #104] @ 0x68
800507c: b29b uxth r3, r3
800507e: 029b lsls r3, r3, #10
8005080: b29b uxth r3, r3
8005082: 4313 orrs r3, r2
8005084: b29a uxth r2, r3
8005086: 6dbb ldr r3, [r7, #88] @ 0x58
8005088: 801a strh r2, [r3, #0]
800508a: e019 b.n 80050c0 <HAL_PCD_EP_DB_Transmit+0x784>
800508c: 68bb ldr r3, [r7, #8]
800508e: 785b ldrb r3, [r3, #1]
8005090: 2b01 cmp r3, #1
8005092: d115 bne.n 80050c0 <HAL_PCD_EP_DB_Transmit+0x784>
8005094: 68fb ldr r3, [r7, #12]
8005096: 681b ldr r3, [r3, #0]
8005098: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800509c: b29b uxth r3, r3
800509e: 461a mov r2, r3
80050a0: 6d7b ldr r3, [r7, #84] @ 0x54
80050a2: 4413 add r3, r2
80050a4: 657b str r3, [r7, #84] @ 0x54
80050a6: 68bb ldr r3, [r7, #8]
80050a8: 781b ldrb r3, [r3, #0]
80050aa: 011a lsls r2, r3, #4
80050ac: 6d7b ldr r3, [r7, #84] @ 0x54
80050ae: 4413 add r3, r2
80050b0: f203 430c addw r3, r3, #1036 @ 0x40c
80050b4: 653b str r3, [r7, #80] @ 0x50
80050b6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80050ba: b29a uxth r2, r3
80050bc: 6d3b ldr r3, [r7, #80] @ 0x50
80050be: 801a strh r2, [r3, #0]
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
80050c0: 68fb ldr r3, [r7, #12]
80050c2: 6818 ldr r0, [r3, #0]
80050c4: 68bb ldr r3, [r7, #8]
80050c6: 6959 ldr r1, [r3, #20]
80050c8: 68bb ldr r3, [r7, #8]
80050ca: 895a ldrh r2, [r3, #10]
80050cc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80050d0: b29b uxth r3, r3
80050d2: f003 ff82 bl 8008fda <USB_WritePMA>
}
}
}
/*enable endpoint IN*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
80050d6: 68fb ldr r3, [r7, #12]
80050d8: 681b ldr r3, [r3, #0]
80050da: 461a mov r2, r3
80050dc: 68bb ldr r3, [r7, #8]
80050de: 781b ldrb r3, [r3, #0]
80050e0: 009b lsls r3, r3, #2
80050e2: 4413 add r3, r2
80050e4: 881b ldrh r3, [r3, #0]
80050e6: b29b uxth r3, r3
80050e8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80050ec: f023 0340 bic.w r3, r3, #64 @ 0x40
80050f0: 82bb strh r3, [r7, #20]
80050f2: 8abb ldrh r3, [r7, #20]
80050f4: f083 0310 eor.w r3, r3, #16
80050f8: 82bb strh r3, [r7, #20]
80050fa: 8abb ldrh r3, [r7, #20]
80050fc: f083 0320 eor.w r3, r3, #32
8005100: 82bb strh r3, [r7, #20]
8005102: 68fb ldr r3, [r7, #12]
8005104: 681b ldr r3, [r3, #0]
8005106: 461a mov r2, r3
8005108: 68bb ldr r3, [r7, #8]
800510a: 781b ldrb r3, [r3, #0]
800510c: 009b lsls r3, r3, #2
800510e: 441a add r2, r3
8005110: 8abb ldrh r3, [r7, #20]
8005112: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005116: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800511a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800511e: f043 0380 orr.w r3, r3, #128 @ 0x80
8005122: b29b uxth r3, r3
8005124: 8013 strh r3, [r2, #0]
return HAL_OK;
8005126: 2300 movs r3, #0
}
8005128: 4618 mov r0, r3
800512a: 3790 adds r7, #144 @ 0x90
800512c: 46bd mov sp, r7
800512e: bd80 pop {r7, pc}
08005130 <HAL_PCDEx_PMAConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
8005130: b480 push {r7}
8005132: b087 sub sp, #28
8005134: af00 add r7, sp, #0
8005136: 60f8 str r0, [r7, #12]
8005138: 607b str r3, [r7, #4]
800513a: 460b mov r3, r1
800513c: 817b strh r3, [r7, #10]
800513e: 4613 mov r3, r2
8005140: 813b strh r3, [r7, #8]
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
8005142: 897b ldrh r3, [r7, #10]
8005144: f003 0380 and.w r3, r3, #128 @ 0x80
8005148: b29b uxth r3, r3
800514a: 2b00 cmp r3, #0
800514c: d00b beq.n 8005166 <HAL_PCDEx_PMAConfig+0x36>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800514e: 897b ldrh r3, [r7, #10]
8005150: f003 0207 and.w r2, r3, #7
8005154: 4613 mov r3, r2
8005156: 009b lsls r3, r3, #2
8005158: 4413 add r3, r2
800515a: 00db lsls r3, r3, #3
800515c: 3310 adds r3, #16
800515e: 68fa ldr r2, [r7, #12]
8005160: 4413 add r3, r2
8005162: 617b str r3, [r7, #20]
8005164: e009 b.n 800517a <HAL_PCDEx_PMAConfig+0x4a>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8005166: 897a ldrh r2, [r7, #10]
8005168: 4613 mov r3, r2
800516a: 009b lsls r3, r3, #2
800516c: 4413 add r3, r2
800516e: 00db lsls r3, r3, #3
8005170: f503 73a8 add.w r3, r3, #336 @ 0x150
8005174: 68fa ldr r2, [r7, #12]
8005176: 4413 add r3, r2
8005178: 617b str r3, [r7, #20]
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
800517a: 893b ldrh r3, [r7, #8]
800517c: 2b00 cmp r3, #0
800517e: d107 bne.n 8005190 <HAL_PCDEx_PMAConfig+0x60>
{
/* Single Buffer */
ep->doublebuffer = 0U;
8005180: 697b ldr r3, [r7, #20]
8005182: 2200 movs r2, #0
8005184: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
8005186: 687b ldr r3, [r7, #4]
8005188: b29a uxth r2, r3
800518a: 697b ldr r3, [r7, #20]
800518c: 80da strh r2, [r3, #6]
800518e: e00b b.n 80051a8 <HAL_PCDEx_PMAConfig+0x78>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
8005190: 697b ldr r3, [r7, #20]
8005192: 2201 movs r2, #1
8005194: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
8005196: 687b ldr r3, [r7, #4]
8005198: b29a uxth r2, r3
800519a: 697b ldr r3, [r7, #20]
800519c: 811a strh r2, [r3, #8]
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
800519e: 687b ldr r3, [r7, #4]
80051a0: 0c1b lsrs r3, r3, #16
80051a2: b29a uxth r2, r3
80051a4: 697b ldr r3, [r7, #20]
80051a6: 815a strh r2, [r3, #10]
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
80051a8: 2300 movs r3, #0
}
80051aa: 4618 mov r0, r3
80051ac: 371c adds r7, #28
80051ae: 46bd mov sp, r7
80051b0: bc80 pop {r7}
80051b2: 4770 bx lr
080051b4 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80051b4: b580 push {r7, lr}
80051b6: b086 sub sp, #24
80051b8: af00 add r7, sp, #0
80051ba: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80051bc: 687b ldr r3, [r7, #4]
80051be: 2b00 cmp r3, #0
80051c0: d101 bne.n 80051c6 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80051c2: 2301 movs r3, #1
80051c4: e272 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80051c6: 687b ldr r3, [r7, #4]
80051c8: 681b ldr r3, [r3, #0]
80051ca: f003 0301 and.w r3, r3, #1
80051ce: 2b00 cmp r3, #0
80051d0: f000 8087 beq.w 80052e2 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80051d4: 4b92 ldr r3, [pc, #584] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80051d6: 685b ldr r3, [r3, #4]
80051d8: f003 030c and.w r3, r3, #12
80051dc: 2b04 cmp r3, #4
80051de: d00c beq.n 80051fa <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
80051e0: 4b8f ldr r3, [pc, #572] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80051e2: 685b ldr r3, [r3, #4]
80051e4: f003 030c and.w r3, r3, #12
80051e8: 2b08 cmp r3, #8
80051ea: d112 bne.n 8005212 <HAL_RCC_OscConfig+0x5e>
80051ec: 4b8c ldr r3, [pc, #560] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80051ee: 685b ldr r3, [r3, #4]
80051f0: f403 3380 and.w r3, r3, #65536 @ 0x10000
80051f4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80051f8: d10b bne.n 8005212 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80051fa: 4b89 ldr r3, [pc, #548] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80051fc: 681b ldr r3, [r3, #0]
80051fe: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005202: 2b00 cmp r3, #0
8005204: d06c beq.n 80052e0 <HAL_RCC_OscConfig+0x12c>
8005206: 687b ldr r3, [r7, #4]
8005208: 685b ldr r3, [r3, #4]
800520a: 2b00 cmp r3, #0
800520c: d168 bne.n 80052e0 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
800520e: 2301 movs r3, #1
8005210: e24c b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8005212: 687b ldr r3, [r7, #4]
8005214: 685b ldr r3, [r3, #4]
8005216: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800521a: d106 bne.n 800522a <HAL_RCC_OscConfig+0x76>
800521c: 4b80 ldr r3, [pc, #512] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
800521e: 681b ldr r3, [r3, #0]
8005220: 4a7f ldr r2, [pc, #508] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005222: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8005226: 6013 str r3, [r2, #0]
8005228: e02e b.n 8005288 <HAL_RCC_OscConfig+0xd4>
800522a: 687b ldr r3, [r7, #4]
800522c: 685b ldr r3, [r3, #4]
800522e: 2b00 cmp r3, #0
8005230: d10c bne.n 800524c <HAL_RCC_OscConfig+0x98>
8005232: 4b7b ldr r3, [pc, #492] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005234: 681b ldr r3, [r3, #0]
8005236: 4a7a ldr r2, [pc, #488] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005238: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800523c: 6013 str r3, [r2, #0]
800523e: 4b78 ldr r3, [pc, #480] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005240: 681b ldr r3, [r3, #0]
8005242: 4a77 ldr r2, [pc, #476] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005244: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005248: 6013 str r3, [r2, #0]
800524a: e01d b.n 8005288 <HAL_RCC_OscConfig+0xd4>
800524c: 687b ldr r3, [r7, #4]
800524e: 685b ldr r3, [r3, #4]
8005250: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8005254: d10c bne.n 8005270 <HAL_RCC_OscConfig+0xbc>
8005256: 4b72 ldr r3, [pc, #456] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005258: 681b ldr r3, [r3, #0]
800525a: 4a71 ldr r2, [pc, #452] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
800525c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8005260: 6013 str r3, [r2, #0]
8005262: 4b6f ldr r3, [pc, #444] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005264: 681b ldr r3, [r3, #0]
8005266: 4a6e ldr r2, [pc, #440] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005268: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800526c: 6013 str r3, [r2, #0]
800526e: e00b b.n 8005288 <HAL_RCC_OscConfig+0xd4>
8005270: 4b6b ldr r3, [pc, #428] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005272: 681b ldr r3, [r3, #0]
8005274: 4a6a ldr r2, [pc, #424] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005276: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800527a: 6013 str r3, [r2, #0]
800527c: 4b68 ldr r3, [pc, #416] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
800527e: 681b ldr r3, [r3, #0]
8005280: 4a67 ldr r2, [pc, #412] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005282: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005286: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8005288: 687b ldr r3, [r7, #4]
800528a: 685b ldr r3, [r3, #4]
800528c: 2b00 cmp r3, #0
800528e: d013 beq.n 80052b8 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005290: f7fc ff8c bl 80021ac <HAL_GetTick>
8005294: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8005296: e008 b.n 80052aa <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8005298: f7fc ff88 bl 80021ac <HAL_GetTick>
800529c: 4602 mov r2, r0
800529e: 693b ldr r3, [r7, #16]
80052a0: 1ad3 subs r3, r2, r3
80052a2: 2b64 cmp r3, #100 @ 0x64
80052a4: d901 bls.n 80052aa <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
80052a6: 2303 movs r3, #3
80052a8: e200 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80052aa: 4b5d ldr r3, [pc, #372] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80052ac: 681b ldr r3, [r3, #0]
80052ae: f403 3300 and.w r3, r3, #131072 @ 0x20000
80052b2: 2b00 cmp r3, #0
80052b4: d0f0 beq.n 8005298 <HAL_RCC_OscConfig+0xe4>
80052b6: e014 b.n 80052e2 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80052b8: f7fc ff78 bl 80021ac <HAL_GetTick>
80052bc: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80052be: e008 b.n 80052d2 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80052c0: f7fc ff74 bl 80021ac <HAL_GetTick>
80052c4: 4602 mov r2, r0
80052c6: 693b ldr r3, [r7, #16]
80052c8: 1ad3 subs r3, r2, r3
80052ca: 2b64 cmp r3, #100 @ 0x64
80052cc: d901 bls.n 80052d2 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
80052ce: 2303 movs r3, #3
80052d0: e1ec b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80052d2: 4b53 ldr r3, [pc, #332] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80052d4: 681b ldr r3, [r3, #0]
80052d6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80052da: 2b00 cmp r3, #0
80052dc: d1f0 bne.n 80052c0 <HAL_RCC_OscConfig+0x10c>
80052de: e000 b.n 80052e2 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80052e0: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80052e2: 687b ldr r3, [r7, #4]
80052e4: 681b ldr r3, [r3, #0]
80052e6: f003 0302 and.w r3, r3, #2
80052ea: 2b00 cmp r3, #0
80052ec: d063 beq.n 80053b6 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80052ee: 4b4c ldr r3, [pc, #304] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80052f0: 685b ldr r3, [r3, #4]
80052f2: f003 030c and.w r3, r3, #12
80052f6: 2b00 cmp r3, #0
80052f8: d00b beq.n 8005312 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
80052fa: 4b49 ldr r3, [pc, #292] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80052fc: 685b ldr r3, [r3, #4]
80052fe: f003 030c and.w r3, r3, #12
8005302: 2b08 cmp r3, #8
8005304: d11c bne.n 8005340 <HAL_RCC_OscConfig+0x18c>
8005306: 4b46 ldr r3, [pc, #280] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005308: 685b ldr r3, [r3, #4]
800530a: f403 3380 and.w r3, r3, #65536 @ 0x10000
800530e: 2b00 cmp r3, #0
8005310: d116 bne.n 8005340 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8005312: 4b43 ldr r3, [pc, #268] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005314: 681b ldr r3, [r3, #0]
8005316: f003 0302 and.w r3, r3, #2
800531a: 2b00 cmp r3, #0
800531c: d005 beq.n 800532a <HAL_RCC_OscConfig+0x176>
800531e: 687b ldr r3, [r7, #4]
8005320: 691b ldr r3, [r3, #16]
8005322: 2b01 cmp r3, #1
8005324: d001 beq.n 800532a <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8005326: 2301 movs r3, #1
8005328: e1c0 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800532a: 4b3d ldr r3, [pc, #244] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
800532c: 681b ldr r3, [r3, #0]
800532e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8005332: 687b ldr r3, [r7, #4]
8005334: 695b ldr r3, [r3, #20]
8005336: 00db lsls r3, r3, #3
8005338: 4939 ldr r1, [pc, #228] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
800533a: 4313 orrs r3, r2
800533c: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800533e: e03a b.n 80053b6 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8005340: 687b ldr r3, [r7, #4]
8005342: 691b ldr r3, [r3, #16]
8005344: 2b00 cmp r3, #0
8005346: d020 beq.n 800538a <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8005348: 4b36 ldr r3, [pc, #216] @ (8005424 <HAL_RCC_OscConfig+0x270>)
800534a: 2201 movs r2, #1
800534c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800534e: f7fc ff2d bl 80021ac <HAL_GetTick>
8005352: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005354: e008 b.n 8005368 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8005356: f7fc ff29 bl 80021ac <HAL_GetTick>
800535a: 4602 mov r2, r0
800535c: 693b ldr r3, [r7, #16]
800535e: 1ad3 subs r3, r2, r3
8005360: 2b02 cmp r3, #2
8005362: d901 bls.n 8005368 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8005364: 2303 movs r3, #3
8005366: e1a1 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005368: 4b2d ldr r3, [pc, #180] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
800536a: 681b ldr r3, [r3, #0]
800536c: f003 0302 and.w r3, r3, #2
8005370: 2b00 cmp r3, #0
8005372: d0f0 beq.n 8005356 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8005374: 4b2a ldr r3, [pc, #168] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005376: 681b ldr r3, [r3, #0]
8005378: f023 02f8 bic.w r2, r3, #248 @ 0xf8
800537c: 687b ldr r3, [r7, #4]
800537e: 695b ldr r3, [r3, #20]
8005380: 00db lsls r3, r3, #3
8005382: 4927 ldr r1, [pc, #156] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
8005384: 4313 orrs r3, r2
8005386: 600b str r3, [r1, #0]
8005388: e015 b.n 80053b6 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800538a: 4b26 ldr r3, [pc, #152] @ (8005424 <HAL_RCC_OscConfig+0x270>)
800538c: 2200 movs r2, #0
800538e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005390: f7fc ff0c bl 80021ac <HAL_GetTick>
8005394: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8005396: e008 b.n 80053aa <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8005398: f7fc ff08 bl 80021ac <HAL_GetTick>
800539c: 4602 mov r2, r0
800539e: 693b ldr r3, [r7, #16]
80053a0: 1ad3 subs r3, r2, r3
80053a2: 2b02 cmp r3, #2
80053a4: d901 bls.n 80053aa <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
80053a6: 2303 movs r3, #3
80053a8: e180 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80053aa: 4b1d ldr r3, [pc, #116] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80053ac: 681b ldr r3, [r3, #0]
80053ae: f003 0302 and.w r3, r3, #2
80053b2: 2b00 cmp r3, #0
80053b4: d1f0 bne.n 8005398 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80053b6: 687b ldr r3, [r7, #4]
80053b8: 681b ldr r3, [r3, #0]
80053ba: f003 0308 and.w r3, r3, #8
80053be: 2b00 cmp r3, #0
80053c0: d03a beq.n 8005438 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80053c2: 687b ldr r3, [r7, #4]
80053c4: 699b ldr r3, [r3, #24]
80053c6: 2b00 cmp r3, #0
80053c8: d019 beq.n 80053fe <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80053ca: 4b17 ldr r3, [pc, #92] @ (8005428 <HAL_RCC_OscConfig+0x274>)
80053cc: 2201 movs r2, #1
80053ce: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80053d0: f7fc feec bl 80021ac <HAL_GetTick>
80053d4: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80053d6: e008 b.n 80053ea <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80053d8: f7fc fee8 bl 80021ac <HAL_GetTick>
80053dc: 4602 mov r2, r0
80053de: 693b ldr r3, [r7, #16]
80053e0: 1ad3 subs r3, r2, r3
80053e2: 2b02 cmp r3, #2
80053e4: d901 bls.n 80053ea <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
80053e6: 2303 movs r3, #3
80053e8: e160 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80053ea: 4b0d ldr r3, [pc, #52] @ (8005420 <HAL_RCC_OscConfig+0x26c>)
80053ec: 6a5b ldr r3, [r3, #36] @ 0x24
80053ee: f003 0302 and.w r3, r3, #2
80053f2: 2b00 cmp r3, #0
80053f4: d0f0 beq.n 80053d8 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
80053f6: 2001 movs r0, #1
80053f8: f000 face bl 8005998 <RCC_Delay>
80053fc: e01c b.n 8005438 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80053fe: 4b0a ldr r3, [pc, #40] @ (8005428 <HAL_RCC_OscConfig+0x274>)
8005400: 2200 movs r2, #0
8005402: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005404: f7fc fed2 bl 80021ac <HAL_GetTick>
8005408: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800540a: e00f b.n 800542c <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800540c: f7fc fece bl 80021ac <HAL_GetTick>
8005410: 4602 mov r2, r0
8005412: 693b ldr r3, [r7, #16]
8005414: 1ad3 subs r3, r2, r3
8005416: 2b02 cmp r3, #2
8005418: d908 bls.n 800542c <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
800541a: 2303 movs r3, #3
800541c: e146 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
800541e: bf00 nop
8005420: 40021000 .word 0x40021000
8005424: 42420000 .word 0x42420000
8005428: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800542c: 4b92 ldr r3, [pc, #584] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800542e: 6a5b ldr r3, [r3, #36] @ 0x24
8005430: f003 0302 and.w r3, r3, #2
8005434: 2b00 cmp r3, #0
8005436: d1e9 bne.n 800540c <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8005438: 687b ldr r3, [r7, #4]
800543a: 681b ldr r3, [r3, #0]
800543c: f003 0304 and.w r3, r3, #4
8005440: 2b00 cmp r3, #0
8005442: f000 80a6 beq.w 8005592 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8005446: 2300 movs r3, #0
8005448: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800544a: 4b8b ldr r3, [pc, #556] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800544c: 69db ldr r3, [r3, #28]
800544e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005452: 2b00 cmp r3, #0
8005454: d10d bne.n 8005472 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005456: 4b88 ldr r3, [pc, #544] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005458: 69db ldr r3, [r3, #28]
800545a: 4a87 ldr r2, [pc, #540] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800545c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005460: 61d3 str r3, [r2, #28]
8005462: 4b85 ldr r3, [pc, #532] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005464: 69db ldr r3, [r3, #28]
8005466: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800546a: 60bb str r3, [r7, #8]
800546c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800546e: 2301 movs r3, #1
8005470: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005472: 4b82 ldr r3, [pc, #520] @ (800567c <HAL_RCC_OscConfig+0x4c8>)
8005474: 681b ldr r3, [r3, #0]
8005476: f403 7380 and.w r3, r3, #256 @ 0x100
800547a: 2b00 cmp r3, #0
800547c: d118 bne.n 80054b0 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800547e: 4b7f ldr r3, [pc, #508] @ (800567c <HAL_RCC_OscConfig+0x4c8>)
8005480: 681b ldr r3, [r3, #0]
8005482: 4a7e ldr r2, [pc, #504] @ (800567c <HAL_RCC_OscConfig+0x4c8>)
8005484: f443 7380 orr.w r3, r3, #256 @ 0x100
8005488: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800548a: f7fc fe8f bl 80021ac <HAL_GetTick>
800548e: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005490: e008 b.n 80054a4 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005492: f7fc fe8b bl 80021ac <HAL_GetTick>
8005496: 4602 mov r2, r0
8005498: 693b ldr r3, [r7, #16]
800549a: 1ad3 subs r3, r2, r3
800549c: 2b64 cmp r3, #100 @ 0x64
800549e: d901 bls.n 80054a4 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
80054a0: 2303 movs r3, #3
80054a2: e103 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80054a4: 4b75 ldr r3, [pc, #468] @ (800567c <HAL_RCC_OscConfig+0x4c8>)
80054a6: 681b ldr r3, [r3, #0]
80054a8: f403 7380 and.w r3, r3, #256 @ 0x100
80054ac: 2b00 cmp r3, #0
80054ae: d0f0 beq.n 8005492 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80054b0: 687b ldr r3, [r7, #4]
80054b2: 68db ldr r3, [r3, #12]
80054b4: 2b01 cmp r3, #1
80054b6: d106 bne.n 80054c6 <HAL_RCC_OscConfig+0x312>
80054b8: 4b6f ldr r3, [pc, #444] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054ba: 6a1b ldr r3, [r3, #32]
80054bc: 4a6e ldr r2, [pc, #440] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054be: f043 0301 orr.w r3, r3, #1
80054c2: 6213 str r3, [r2, #32]
80054c4: e02d b.n 8005522 <HAL_RCC_OscConfig+0x36e>
80054c6: 687b ldr r3, [r7, #4]
80054c8: 68db ldr r3, [r3, #12]
80054ca: 2b00 cmp r3, #0
80054cc: d10c bne.n 80054e8 <HAL_RCC_OscConfig+0x334>
80054ce: 4b6a ldr r3, [pc, #424] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054d0: 6a1b ldr r3, [r3, #32]
80054d2: 4a69 ldr r2, [pc, #420] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054d4: f023 0301 bic.w r3, r3, #1
80054d8: 6213 str r3, [r2, #32]
80054da: 4b67 ldr r3, [pc, #412] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054dc: 6a1b ldr r3, [r3, #32]
80054de: 4a66 ldr r2, [pc, #408] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054e0: f023 0304 bic.w r3, r3, #4
80054e4: 6213 str r3, [r2, #32]
80054e6: e01c b.n 8005522 <HAL_RCC_OscConfig+0x36e>
80054e8: 687b ldr r3, [r7, #4]
80054ea: 68db ldr r3, [r3, #12]
80054ec: 2b05 cmp r3, #5
80054ee: d10c bne.n 800550a <HAL_RCC_OscConfig+0x356>
80054f0: 4b61 ldr r3, [pc, #388] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054f2: 6a1b ldr r3, [r3, #32]
80054f4: 4a60 ldr r2, [pc, #384] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054f6: f043 0304 orr.w r3, r3, #4
80054fa: 6213 str r3, [r2, #32]
80054fc: 4b5e ldr r3, [pc, #376] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80054fe: 6a1b ldr r3, [r3, #32]
8005500: 4a5d ldr r2, [pc, #372] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005502: f043 0301 orr.w r3, r3, #1
8005506: 6213 str r3, [r2, #32]
8005508: e00b b.n 8005522 <HAL_RCC_OscConfig+0x36e>
800550a: 4b5b ldr r3, [pc, #364] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800550c: 6a1b ldr r3, [r3, #32]
800550e: 4a5a ldr r2, [pc, #360] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005510: f023 0301 bic.w r3, r3, #1
8005514: 6213 str r3, [r2, #32]
8005516: 4b58 ldr r3, [pc, #352] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005518: 6a1b ldr r3, [r3, #32]
800551a: 4a57 ldr r2, [pc, #348] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800551c: f023 0304 bic.w r3, r3, #4
8005520: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8005522: 687b ldr r3, [r7, #4]
8005524: 68db ldr r3, [r3, #12]
8005526: 2b00 cmp r3, #0
8005528: d015 beq.n 8005556 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800552a: f7fc fe3f bl 80021ac <HAL_GetTick>
800552e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005530: e00a b.n 8005548 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005532: f7fc fe3b bl 80021ac <HAL_GetTick>
8005536: 4602 mov r2, r0
8005538: 693b ldr r3, [r7, #16]
800553a: 1ad3 subs r3, r2, r3
800553c: f241 3288 movw r2, #5000 @ 0x1388
8005540: 4293 cmp r3, r2
8005542: d901 bls.n 8005548 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8005544: 2303 movs r3, #3
8005546: e0b1 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005548: 4b4b ldr r3, [pc, #300] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800554a: 6a1b ldr r3, [r3, #32]
800554c: f003 0302 and.w r3, r3, #2
8005550: 2b00 cmp r3, #0
8005552: d0ee beq.n 8005532 <HAL_RCC_OscConfig+0x37e>
8005554: e014 b.n 8005580 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005556: f7fc fe29 bl 80021ac <HAL_GetTick>
800555a: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800555c: e00a b.n 8005574 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800555e: f7fc fe25 bl 80021ac <HAL_GetTick>
8005562: 4602 mov r2, r0
8005564: 693b ldr r3, [r7, #16]
8005566: 1ad3 subs r3, r2, r3
8005568: f241 3288 movw r2, #5000 @ 0x1388
800556c: 4293 cmp r3, r2
800556e: d901 bls.n 8005574 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8005570: 2303 movs r3, #3
8005572: e09b b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8005574: 4b40 ldr r3, [pc, #256] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005576: 6a1b ldr r3, [r3, #32]
8005578: f003 0302 and.w r3, r3, #2
800557c: 2b00 cmp r3, #0
800557e: d1ee bne.n 800555e <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005580: 7dfb ldrb r3, [r7, #23]
8005582: 2b01 cmp r3, #1
8005584: d105 bne.n 8005592 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005586: 4b3c ldr r3, [pc, #240] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005588: 69db ldr r3, [r3, #28]
800558a: 4a3b ldr r2, [pc, #236] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800558c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005590: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8005592: 687b ldr r3, [r7, #4]
8005594: 69db ldr r3, [r3, #28]
8005596: 2b00 cmp r3, #0
8005598: f000 8087 beq.w 80056aa <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800559c: 4b36 ldr r3, [pc, #216] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800559e: 685b ldr r3, [r3, #4]
80055a0: f003 030c and.w r3, r3, #12
80055a4: 2b08 cmp r3, #8
80055a6: d061 beq.n 800566c <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80055a8: 687b ldr r3, [r7, #4]
80055aa: 69db ldr r3, [r3, #28]
80055ac: 2b02 cmp r3, #2
80055ae: d146 bne.n 800563e <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80055b0: 4b33 ldr r3, [pc, #204] @ (8005680 <HAL_RCC_OscConfig+0x4cc>)
80055b2: 2200 movs r2, #0
80055b4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80055b6: f7fc fdf9 bl 80021ac <HAL_GetTick>
80055ba: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80055bc: e008 b.n 80055d0 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80055be: f7fc fdf5 bl 80021ac <HAL_GetTick>
80055c2: 4602 mov r2, r0
80055c4: 693b ldr r3, [r7, #16]
80055c6: 1ad3 subs r3, r2, r3
80055c8: 2b02 cmp r3, #2
80055ca: d901 bls.n 80055d0 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
80055cc: 2303 movs r3, #3
80055ce: e06d b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80055d0: 4b29 ldr r3, [pc, #164] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80055d2: 681b ldr r3, [r3, #0]
80055d4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80055d8: 2b00 cmp r3, #0
80055da: d1f0 bne.n 80055be <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
80055dc: 687b ldr r3, [r7, #4]
80055de: 6a1b ldr r3, [r3, #32]
80055e0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80055e4: d108 bne.n 80055f8 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80055e6: 4b24 ldr r3, [pc, #144] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80055e8: 685b ldr r3, [r3, #4]
80055ea: f423 3200 bic.w r2, r3, #131072 @ 0x20000
80055ee: 687b ldr r3, [r7, #4]
80055f0: 689b ldr r3, [r3, #8]
80055f2: 4921 ldr r1, [pc, #132] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80055f4: 4313 orrs r3, r2
80055f6: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80055f8: 4b1f ldr r3, [pc, #124] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
80055fa: 685b ldr r3, [r3, #4]
80055fc: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8005600: 687b ldr r3, [r7, #4]
8005602: 6a19 ldr r1, [r3, #32]
8005604: 687b ldr r3, [r7, #4]
8005606: 6a5b ldr r3, [r3, #36] @ 0x24
8005608: 430b orrs r3, r1
800560a: 491b ldr r1, [pc, #108] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
800560c: 4313 orrs r3, r2
800560e: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8005610: 4b1b ldr r3, [pc, #108] @ (8005680 <HAL_RCC_OscConfig+0x4cc>)
8005612: 2201 movs r2, #1
8005614: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005616: f7fc fdc9 bl 80021ac <HAL_GetTick>
800561a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800561c: e008 b.n 8005630 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800561e: f7fc fdc5 bl 80021ac <HAL_GetTick>
8005622: 4602 mov r2, r0
8005624: 693b ldr r3, [r7, #16]
8005626: 1ad3 subs r3, r2, r3
8005628: 2b02 cmp r3, #2
800562a: d901 bls.n 8005630 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
800562c: 2303 movs r3, #3
800562e: e03d b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8005630: 4b11 ldr r3, [pc, #68] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005632: 681b ldr r3, [r3, #0]
8005634: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005638: 2b00 cmp r3, #0
800563a: d0f0 beq.n 800561e <HAL_RCC_OscConfig+0x46a>
800563c: e035 b.n 80056aa <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800563e: 4b10 ldr r3, [pc, #64] @ (8005680 <HAL_RCC_OscConfig+0x4cc>)
8005640: 2200 movs r2, #0
8005642: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8005644: f7fc fdb2 bl 80021ac <HAL_GetTick>
8005648: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800564a: e008 b.n 800565e <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800564c: f7fc fdae bl 80021ac <HAL_GetTick>
8005650: 4602 mov r2, r0
8005652: 693b ldr r3, [r7, #16]
8005654: 1ad3 subs r3, r2, r3
8005656: 2b02 cmp r3, #2
8005658: d901 bls.n 800565e <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
800565a: 2303 movs r3, #3
800565c: e026 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800565e: 4b06 ldr r3, [pc, #24] @ (8005678 <HAL_RCC_OscConfig+0x4c4>)
8005660: 681b ldr r3, [r3, #0]
8005662: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8005666: 2b00 cmp r3, #0
8005668: d1f0 bne.n 800564c <HAL_RCC_OscConfig+0x498>
800566a: e01e b.n 80056aa <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800566c: 687b ldr r3, [r7, #4]
800566e: 69db ldr r3, [r3, #28]
8005670: 2b01 cmp r3, #1
8005672: d107 bne.n 8005684 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8005674: 2301 movs r3, #1
8005676: e019 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
8005678: 40021000 .word 0x40021000
800567c: 40007000 .word 0x40007000
8005680: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8005684: 4b0b ldr r3, [pc, #44] @ (80056b4 <HAL_RCC_OscConfig+0x500>)
8005686: 685b ldr r3, [r3, #4]
8005688: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800568a: 68fb ldr r3, [r7, #12]
800568c: f403 3280 and.w r2, r3, #65536 @ 0x10000
8005690: 687b ldr r3, [r7, #4]
8005692: 6a1b ldr r3, [r3, #32]
8005694: 429a cmp r2, r3
8005696: d106 bne.n 80056a6 <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8005698: 68fb ldr r3, [r7, #12]
800569a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
800569e: 687b ldr r3, [r7, #4]
80056a0: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80056a2: 429a cmp r2, r3
80056a4: d001 beq.n 80056aa <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80056a6: 2301 movs r3, #1
80056a8: e000 b.n 80056ac <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80056aa: 2300 movs r3, #0
}
80056ac: 4618 mov r0, r3
80056ae: 3718 adds r7, #24
80056b0: 46bd mov sp, r7
80056b2: bd80 pop {r7, pc}
80056b4: 40021000 .word 0x40021000
080056b8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80056b8: b580 push {r7, lr}
80056ba: b084 sub sp, #16
80056bc: af00 add r7, sp, #0
80056be: 6078 str r0, [r7, #4]
80056c0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80056c2: 687b ldr r3, [r7, #4]
80056c4: 2b00 cmp r3, #0
80056c6: d101 bne.n 80056cc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80056c8: 2301 movs r3, #1
80056ca: e0d0 b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80056cc: 4b6a ldr r3, [pc, #424] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80056ce: 681b ldr r3, [r3, #0]
80056d0: f003 0307 and.w r3, r3, #7
80056d4: 683a ldr r2, [r7, #0]
80056d6: 429a cmp r2, r3
80056d8: d910 bls.n 80056fc <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80056da: 4b67 ldr r3, [pc, #412] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80056dc: 681b ldr r3, [r3, #0]
80056de: f023 0207 bic.w r2, r3, #7
80056e2: 4965 ldr r1, [pc, #404] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80056e4: 683b ldr r3, [r7, #0]
80056e6: 4313 orrs r3, r2
80056e8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80056ea: 4b63 ldr r3, [pc, #396] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80056ec: 681b ldr r3, [r3, #0]
80056ee: f003 0307 and.w r3, r3, #7
80056f2: 683a ldr r2, [r7, #0]
80056f4: 429a cmp r2, r3
80056f6: d001 beq.n 80056fc <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
80056f8: 2301 movs r3, #1
80056fa: e0b8 b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80056fc: 687b ldr r3, [r7, #4]
80056fe: 681b ldr r3, [r3, #0]
8005700: f003 0302 and.w r3, r3, #2
8005704: 2b00 cmp r3, #0
8005706: d020 beq.n 800574a <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8005708: 687b ldr r3, [r7, #4]
800570a: 681b ldr r3, [r3, #0]
800570c: f003 0304 and.w r3, r3, #4
8005710: 2b00 cmp r3, #0
8005712: d005 beq.n 8005720 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8005714: 4b59 ldr r3, [pc, #356] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005716: 685b ldr r3, [r3, #4]
8005718: 4a58 ldr r2, [pc, #352] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
800571a: f443 63e0 orr.w r3, r3, #1792 @ 0x700
800571e: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005720: 687b ldr r3, [r7, #4]
8005722: 681b ldr r3, [r3, #0]
8005724: f003 0308 and.w r3, r3, #8
8005728: 2b00 cmp r3, #0
800572a: d005 beq.n 8005738 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800572c: 4b53 ldr r3, [pc, #332] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
800572e: 685b ldr r3, [r3, #4]
8005730: 4a52 ldr r2, [pc, #328] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005732: f443 5360 orr.w r3, r3, #14336 @ 0x3800
8005736: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8005738: 4b50 ldr r3, [pc, #320] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
800573a: 685b ldr r3, [r3, #4]
800573c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8005740: 687b ldr r3, [r7, #4]
8005742: 689b ldr r3, [r3, #8]
8005744: 494d ldr r1, [pc, #308] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005746: 4313 orrs r3, r2
8005748: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800574a: 687b ldr r3, [r7, #4]
800574c: 681b ldr r3, [r3, #0]
800574e: f003 0301 and.w r3, r3, #1
8005752: 2b00 cmp r3, #0
8005754: d040 beq.n 80057d8 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8005756: 687b ldr r3, [r7, #4]
8005758: 685b ldr r3, [r3, #4]
800575a: 2b01 cmp r3, #1
800575c: d107 bne.n 800576e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800575e: 4b47 ldr r3, [pc, #284] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005760: 681b ldr r3, [r3, #0]
8005762: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005766: 2b00 cmp r3, #0
8005768: d115 bne.n 8005796 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800576a: 2301 movs r3, #1
800576c: e07f b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800576e: 687b ldr r3, [r7, #4]
8005770: 685b ldr r3, [r3, #4]
8005772: 2b02 cmp r3, #2
8005774: d107 bne.n 8005786 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8005776: 4b41 ldr r3, [pc, #260] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005778: 681b ldr r3, [r3, #0]
800577a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800577e: 2b00 cmp r3, #0
8005780: d109 bne.n 8005796 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8005782: 2301 movs r3, #1
8005784: e073 b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8005786: 4b3d ldr r3, [pc, #244] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005788: 681b ldr r3, [r3, #0]
800578a: f003 0302 and.w r3, r3, #2
800578e: 2b00 cmp r3, #0
8005790: d101 bne.n 8005796 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8005792: 2301 movs r3, #1
8005794: e06b b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8005796: 4b39 ldr r3, [pc, #228] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005798: 685b ldr r3, [r3, #4]
800579a: f023 0203 bic.w r2, r3, #3
800579e: 687b ldr r3, [r7, #4]
80057a0: 685b ldr r3, [r3, #4]
80057a2: 4936 ldr r1, [pc, #216] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
80057a4: 4313 orrs r3, r2
80057a6: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80057a8: f7fc fd00 bl 80021ac <HAL_GetTick>
80057ac: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80057ae: e00a b.n 80057c6 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80057b0: f7fc fcfc bl 80021ac <HAL_GetTick>
80057b4: 4602 mov r2, r0
80057b6: 68fb ldr r3, [r7, #12]
80057b8: 1ad3 subs r3, r2, r3
80057ba: f241 3288 movw r2, #5000 @ 0x1388
80057be: 4293 cmp r3, r2
80057c0: d901 bls.n 80057c6 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80057c2: 2303 movs r3, #3
80057c4: e053 b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80057c6: 4b2d ldr r3, [pc, #180] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
80057c8: 685b ldr r3, [r3, #4]
80057ca: f003 020c and.w r2, r3, #12
80057ce: 687b ldr r3, [r7, #4]
80057d0: 685b ldr r3, [r3, #4]
80057d2: 009b lsls r3, r3, #2
80057d4: 429a cmp r2, r3
80057d6: d1eb bne.n 80057b0 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80057d8: 4b27 ldr r3, [pc, #156] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80057da: 681b ldr r3, [r3, #0]
80057dc: f003 0307 and.w r3, r3, #7
80057e0: 683a ldr r2, [r7, #0]
80057e2: 429a cmp r2, r3
80057e4: d210 bcs.n 8005808 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80057e6: 4b24 ldr r3, [pc, #144] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80057e8: 681b ldr r3, [r3, #0]
80057ea: f023 0207 bic.w r2, r3, #7
80057ee: 4922 ldr r1, [pc, #136] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80057f0: 683b ldr r3, [r7, #0]
80057f2: 4313 orrs r3, r2
80057f4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80057f6: 4b20 ldr r3, [pc, #128] @ (8005878 <HAL_RCC_ClockConfig+0x1c0>)
80057f8: 681b ldr r3, [r3, #0]
80057fa: f003 0307 and.w r3, r3, #7
80057fe: 683a ldr r2, [r7, #0]
8005800: 429a cmp r2, r3
8005802: d001 beq.n 8005808 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8005804: 2301 movs r3, #1
8005806: e032 b.n 800586e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8005808: 687b ldr r3, [r7, #4]
800580a: 681b ldr r3, [r3, #0]
800580c: f003 0304 and.w r3, r3, #4
8005810: 2b00 cmp r3, #0
8005812: d008 beq.n 8005826 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8005814: 4b19 ldr r3, [pc, #100] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005816: 685b ldr r3, [r3, #4]
8005818: f423 62e0 bic.w r2, r3, #1792 @ 0x700
800581c: 687b ldr r3, [r7, #4]
800581e: 68db ldr r3, [r3, #12]
8005820: 4916 ldr r1, [pc, #88] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005822: 4313 orrs r3, r2
8005824: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8005826: 687b ldr r3, [r7, #4]
8005828: 681b ldr r3, [r3, #0]
800582a: f003 0308 and.w r3, r3, #8
800582e: 2b00 cmp r3, #0
8005830: d009 beq.n 8005846 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8005832: 4b12 ldr r3, [pc, #72] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005834: 685b ldr r3, [r3, #4]
8005836: f423 5260 bic.w r2, r3, #14336 @ 0x3800
800583a: 687b ldr r3, [r7, #4]
800583c: 691b ldr r3, [r3, #16]
800583e: 00db lsls r3, r3, #3
8005840: 490e ldr r1, [pc, #56] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
8005842: 4313 orrs r3, r2
8005844: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8005846: f000 f821 bl 800588c <HAL_RCC_GetSysClockFreq>
800584a: 4602 mov r2, r0
800584c: 4b0b ldr r3, [pc, #44] @ (800587c <HAL_RCC_ClockConfig+0x1c4>)
800584e: 685b ldr r3, [r3, #4]
8005850: 091b lsrs r3, r3, #4
8005852: f003 030f and.w r3, r3, #15
8005856: 490a ldr r1, [pc, #40] @ (8005880 <HAL_RCC_ClockConfig+0x1c8>)
8005858: 5ccb ldrb r3, [r1, r3]
800585a: fa22 f303 lsr.w r3, r2, r3
800585e: 4a09 ldr r2, [pc, #36] @ (8005884 <HAL_RCC_ClockConfig+0x1cc>)
8005860: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8005862: 4b09 ldr r3, [pc, #36] @ (8005888 <HAL_RCC_ClockConfig+0x1d0>)
8005864: 681b ldr r3, [r3, #0]
8005866: 4618 mov r0, r3
8005868: f7fc fc5e bl 8002128 <HAL_InitTick>
return HAL_OK;
800586c: 2300 movs r3, #0
}
800586e: 4618 mov r0, r3
8005870: 3710 adds r7, #16
8005872: 46bd mov sp, r7
8005874: bd80 pop {r7, pc}
8005876: bf00 nop
8005878: 40022000 .word 0x40022000
800587c: 40021000 .word 0x40021000
8005880: 0800bde8 .word 0x0800bde8
8005884: 20000004 .word 0x20000004
8005888: 20000008 .word 0x20000008
0800588c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800588c: b480 push {r7}
800588e: b087 sub sp, #28
8005890: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8005892: 2300 movs r3, #0
8005894: 60fb str r3, [r7, #12]
8005896: 2300 movs r3, #0
8005898: 60bb str r3, [r7, #8]
800589a: 2300 movs r3, #0
800589c: 617b str r3, [r7, #20]
800589e: 2300 movs r3, #0
80058a0: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80058a2: 2300 movs r3, #0
80058a4: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80058a6: 4b1e ldr r3, [pc, #120] @ (8005920 <HAL_RCC_GetSysClockFreq+0x94>)
80058a8: 685b ldr r3, [r3, #4]
80058aa: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80058ac: 68fb ldr r3, [r7, #12]
80058ae: f003 030c and.w r3, r3, #12
80058b2: 2b04 cmp r3, #4
80058b4: d002 beq.n 80058bc <HAL_RCC_GetSysClockFreq+0x30>
80058b6: 2b08 cmp r3, #8
80058b8: d003 beq.n 80058c2 <HAL_RCC_GetSysClockFreq+0x36>
80058ba: e027 b.n 800590c <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80058bc: 4b19 ldr r3, [pc, #100] @ (8005924 <HAL_RCC_GetSysClockFreq+0x98>)
80058be: 613b str r3, [r7, #16]
break;
80058c0: e027 b.n 8005912 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80058c2: 68fb ldr r3, [r7, #12]
80058c4: 0c9b lsrs r3, r3, #18
80058c6: f003 030f and.w r3, r3, #15
80058ca: 4a17 ldr r2, [pc, #92] @ (8005928 <HAL_RCC_GetSysClockFreq+0x9c>)
80058cc: 5cd3 ldrb r3, [r2, r3]
80058ce: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80058d0: 68fb ldr r3, [r7, #12]
80058d2: f403 3380 and.w r3, r3, #65536 @ 0x10000
80058d6: 2b00 cmp r3, #0
80058d8: d010 beq.n 80058fc <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80058da: 4b11 ldr r3, [pc, #68] @ (8005920 <HAL_RCC_GetSysClockFreq+0x94>)
80058dc: 685b ldr r3, [r3, #4]
80058de: 0c5b lsrs r3, r3, #17
80058e0: f003 0301 and.w r3, r3, #1
80058e4: 4a11 ldr r2, [pc, #68] @ (800592c <HAL_RCC_GetSysClockFreq+0xa0>)
80058e6: 5cd3 ldrb r3, [r2, r3]
80058e8: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
80058ea: 687b ldr r3, [r7, #4]
80058ec: 4a0d ldr r2, [pc, #52] @ (8005924 <HAL_RCC_GetSysClockFreq+0x98>)
80058ee: fb03 f202 mul.w r2, r3, r2
80058f2: 68bb ldr r3, [r7, #8]
80058f4: fbb2 f3f3 udiv r3, r2, r3
80058f8: 617b str r3, [r7, #20]
80058fa: e004 b.n 8005906 <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
80058fc: 687b ldr r3, [r7, #4]
80058fe: 4a0c ldr r2, [pc, #48] @ (8005930 <HAL_RCC_GetSysClockFreq+0xa4>)
8005900: fb02 f303 mul.w r3, r2, r3
8005904: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
8005906: 697b ldr r3, [r7, #20]
8005908: 613b str r3, [r7, #16]
break;
800590a: e002 b.n 8005912 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800590c: 4b05 ldr r3, [pc, #20] @ (8005924 <HAL_RCC_GetSysClockFreq+0x98>)
800590e: 613b str r3, [r7, #16]
break;
8005910: bf00 nop
}
}
return sysclockfreq;
8005912: 693b ldr r3, [r7, #16]
}
8005914: 4618 mov r0, r3
8005916: 371c adds r7, #28
8005918: 46bd mov sp, r7
800591a: bc80 pop {r7}
800591c: 4770 bx lr
800591e: bf00 nop
8005920: 40021000 .word 0x40021000
8005924: 007a1200 .word 0x007a1200
8005928: 0800be00 .word 0x0800be00
800592c: 0800be10 .word 0x0800be10
8005930: 003d0900 .word 0x003d0900
08005934 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8005934: b480 push {r7}
8005936: af00 add r7, sp, #0
return SystemCoreClock;
8005938: 4b02 ldr r3, [pc, #8] @ (8005944 <HAL_RCC_GetHCLKFreq+0x10>)
800593a: 681b ldr r3, [r3, #0]
}
800593c: 4618 mov r0, r3
800593e: 46bd mov sp, r7
8005940: bc80 pop {r7}
8005942: 4770 bx lr
8005944: 20000004 .word 0x20000004
08005948 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8005948: b580 push {r7, lr}
800594a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
800594c: f7ff fff2 bl 8005934 <HAL_RCC_GetHCLKFreq>
8005950: 4602 mov r2, r0
8005952: 4b05 ldr r3, [pc, #20] @ (8005968 <HAL_RCC_GetPCLK1Freq+0x20>)
8005954: 685b ldr r3, [r3, #4]
8005956: 0a1b lsrs r3, r3, #8
8005958: f003 0307 and.w r3, r3, #7
800595c: 4903 ldr r1, [pc, #12] @ (800596c <HAL_RCC_GetPCLK1Freq+0x24>)
800595e: 5ccb ldrb r3, [r1, r3]
8005960: fa22 f303 lsr.w r3, r2, r3
}
8005964: 4618 mov r0, r3
8005966: bd80 pop {r7, pc}
8005968: 40021000 .word 0x40021000
800596c: 0800bdf8 .word 0x0800bdf8
08005970 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8005970: b580 push {r7, lr}
8005972: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8005974: f7ff ffde bl 8005934 <HAL_RCC_GetHCLKFreq>
8005978: 4602 mov r2, r0
800597a: 4b05 ldr r3, [pc, #20] @ (8005990 <HAL_RCC_GetPCLK2Freq+0x20>)
800597c: 685b ldr r3, [r3, #4]
800597e: 0adb lsrs r3, r3, #11
8005980: f003 0307 and.w r3, r3, #7
8005984: 4903 ldr r1, [pc, #12] @ (8005994 <HAL_RCC_GetPCLK2Freq+0x24>)
8005986: 5ccb ldrb r3, [r1, r3]
8005988: fa22 f303 lsr.w r3, r2, r3
}
800598c: 4618 mov r0, r3
800598e: bd80 pop {r7, pc}
8005990: 40021000 .word 0x40021000
8005994: 0800bdf8 .word 0x0800bdf8
08005998 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8005998: b480 push {r7}
800599a: b085 sub sp, #20
800599c: af00 add r7, sp, #0
800599e: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
80059a0: 4b0a ldr r3, [pc, #40] @ (80059cc <RCC_Delay+0x34>)
80059a2: 681b ldr r3, [r3, #0]
80059a4: 4a0a ldr r2, [pc, #40] @ (80059d0 <RCC_Delay+0x38>)
80059a6: fba2 2303 umull r2, r3, r2, r3
80059aa: 0a5b lsrs r3, r3, #9
80059ac: 687a ldr r2, [r7, #4]
80059ae: fb02 f303 mul.w r3, r2, r3
80059b2: 60fb str r3, [r7, #12]
do
{
__NOP();
80059b4: bf00 nop
}
while (Delay --);
80059b6: 68fb ldr r3, [r7, #12]
80059b8: 1e5a subs r2, r3, #1
80059ba: 60fa str r2, [r7, #12]
80059bc: 2b00 cmp r3, #0
80059be: d1f9 bne.n 80059b4 <RCC_Delay+0x1c>
}
80059c0: bf00 nop
80059c2: bf00 nop
80059c4: 3714 adds r7, #20
80059c6: 46bd mov sp, r7
80059c8: bc80 pop {r7}
80059ca: 4770 bx lr
80059cc: 20000004 .word 0x20000004
80059d0: 10624dd3 .word 0x10624dd3
080059d4 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
80059d4: b580 push {r7, lr}
80059d6: b086 sub sp, #24
80059d8: af00 add r7, sp, #0
80059da: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
80059dc: 2300 movs r3, #0
80059de: 613b str r3, [r7, #16]
80059e0: 2300 movs r3, #0
80059e2: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
80059e4: 687b ldr r3, [r7, #4]
80059e6: 681b ldr r3, [r3, #0]
80059e8: f003 0301 and.w r3, r3, #1
80059ec: 2b00 cmp r3, #0
80059ee: d07d beq.n 8005aec <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
80059f0: 2300 movs r3, #0
80059f2: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80059f4: 4b4f ldr r3, [pc, #316] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80059f6: 69db ldr r3, [r3, #28]
80059f8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80059fc: 2b00 cmp r3, #0
80059fe: d10d bne.n 8005a1c <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8005a00: 4b4c ldr r3, [pc, #304] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a02: 69db ldr r3, [r3, #28]
8005a04: 4a4b ldr r2, [pc, #300] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a06: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8005a0a: 61d3 str r3, [r2, #28]
8005a0c: 4b49 ldr r3, [pc, #292] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a0e: 69db ldr r3, [r3, #28]
8005a10: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005a14: 60bb str r3, [r7, #8]
8005a16: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8005a18: 2301 movs r3, #1
8005a1a: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005a1c: 4b46 ldr r3, [pc, #280] @ (8005b38 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a1e: 681b ldr r3, [r3, #0]
8005a20: f403 7380 and.w r3, r3, #256 @ 0x100
8005a24: 2b00 cmp r3, #0
8005a26: d118 bne.n 8005a5a <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8005a28: 4b43 ldr r3, [pc, #268] @ (8005b38 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a2a: 681b ldr r3, [r3, #0]
8005a2c: 4a42 ldr r2, [pc, #264] @ (8005b38 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a2e: f443 7380 orr.w r3, r3, #256 @ 0x100
8005a32: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8005a34: f7fc fbba bl 80021ac <HAL_GetTick>
8005a38: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005a3a: e008 b.n 8005a4e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8005a3c: f7fc fbb6 bl 80021ac <HAL_GetTick>
8005a40: 4602 mov r2, r0
8005a42: 693b ldr r3, [r7, #16]
8005a44: 1ad3 subs r3, r2, r3
8005a46: 2b64 cmp r3, #100 @ 0x64
8005a48: d901 bls.n 8005a4e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8005a4a: 2303 movs r3, #3
8005a4c: e06d b.n 8005b2a <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8005a4e: 4b3a ldr r3, [pc, #232] @ (8005b38 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8005a50: 681b ldr r3, [r3, #0]
8005a52: f403 7380 and.w r3, r3, #256 @ 0x100
8005a56: 2b00 cmp r3, #0
8005a58: d0f0 beq.n 8005a3c <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8005a5a: 4b36 ldr r3, [pc, #216] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a5c: 6a1b ldr r3, [r3, #32]
8005a5e: f403 7340 and.w r3, r3, #768 @ 0x300
8005a62: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8005a64: 68fb ldr r3, [r7, #12]
8005a66: 2b00 cmp r3, #0
8005a68: d02e beq.n 8005ac8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8005a6a: 687b ldr r3, [r7, #4]
8005a6c: 685b ldr r3, [r3, #4]
8005a6e: f403 7340 and.w r3, r3, #768 @ 0x300
8005a72: 68fa ldr r2, [r7, #12]
8005a74: 429a cmp r2, r3
8005a76: d027 beq.n 8005ac8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8005a78: 4b2e ldr r3, [pc, #184] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a7a: 6a1b ldr r3, [r3, #32]
8005a7c: f423 7340 bic.w r3, r3, #768 @ 0x300
8005a80: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8005a82: 4b2e ldr r3, [pc, #184] @ (8005b3c <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005a84: 2201 movs r2, #1
8005a86: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8005a88: 4b2c ldr r3, [pc, #176] @ (8005b3c <HAL_RCCEx_PeriphCLKConfig+0x168>)
8005a8a: 2200 movs r2, #0
8005a8c: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8005a8e: 4a29 ldr r2, [pc, #164] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005a90: 68fb ldr r3, [r7, #12]
8005a92: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8005a94: 68fb ldr r3, [r7, #12]
8005a96: f003 0301 and.w r3, r3, #1
8005a9a: 2b00 cmp r3, #0
8005a9c: d014 beq.n 8005ac8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8005a9e: f7fc fb85 bl 80021ac <HAL_GetTick>
8005aa2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005aa4: e00a b.n 8005abc <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8005aa6: f7fc fb81 bl 80021ac <HAL_GetTick>
8005aaa: 4602 mov r2, r0
8005aac: 693b ldr r3, [r7, #16]
8005aae: 1ad3 subs r3, r2, r3
8005ab0: f241 3288 movw r2, #5000 @ 0x1388
8005ab4: 4293 cmp r3, r2
8005ab6: d901 bls.n 8005abc <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8005ab8: 2303 movs r3, #3
8005aba: e036 b.n 8005b2a <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005abc: 4b1d ldr r3, [pc, #116] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005abe: 6a1b ldr r3, [r3, #32]
8005ac0: f003 0302 and.w r3, r3, #2
8005ac4: 2b00 cmp r3, #0
8005ac6: d0ee beq.n 8005aa6 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8005ac8: 4b1a ldr r3, [pc, #104] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005aca: 6a1b ldr r3, [r3, #32]
8005acc: f423 7240 bic.w r2, r3, #768 @ 0x300
8005ad0: 687b ldr r3, [r7, #4]
8005ad2: 685b ldr r3, [r3, #4]
8005ad4: 4917 ldr r1, [pc, #92] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005ad6: 4313 orrs r3, r2
8005ad8: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8005ada: 7dfb ldrb r3, [r7, #23]
8005adc: 2b01 cmp r3, #1
8005ade: d105 bne.n 8005aec <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8005ae0: 4b14 ldr r3, [pc, #80] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005ae2: 69db ldr r3, [r3, #28]
8005ae4: 4a13 ldr r2, [pc, #76] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005ae6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8005aea: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8005aec: 687b ldr r3, [r7, #4]
8005aee: 681b ldr r3, [r3, #0]
8005af0: f003 0302 and.w r3, r3, #2
8005af4: 2b00 cmp r3, #0
8005af6: d008 beq.n 8005b0a <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8005af8: 4b0e ldr r3, [pc, #56] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005afa: 685b ldr r3, [r3, #4]
8005afc: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8005b00: 687b ldr r3, [r7, #4]
8005b02: 689b ldr r3, [r3, #8]
8005b04: 490b ldr r1, [pc, #44] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b06: 4313 orrs r3, r2
8005b08: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8005b0a: 687b ldr r3, [r7, #4]
8005b0c: 681b ldr r3, [r3, #0]
8005b0e: f003 0310 and.w r3, r3, #16
8005b12: 2b00 cmp r3, #0
8005b14: d008 beq.n 8005b28 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8005b16: 4b07 ldr r3, [pc, #28] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b18: 685b ldr r3, [r3, #4]
8005b1a: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
8005b1e: 687b ldr r3, [r7, #4]
8005b20: 68db ldr r3, [r3, #12]
8005b22: 4904 ldr r1, [pc, #16] @ (8005b34 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8005b24: 4313 orrs r3, r2
8005b26: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8005b28: 2300 movs r3, #0
}
8005b2a: 4618 mov r0, r3
8005b2c: 3718 adds r7, #24
8005b2e: 46bd mov sp, r7
8005b30: bd80 pop {r7, pc}
8005b32: bf00 nop
8005b34: 40021000 .word 0x40021000
8005b38: 40007000 .word 0x40007000
8005b3c: 42420440 .word 0x42420440
08005b40 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8005b40: b580 push {r7, lr}
8005b42: b082 sub sp, #8
8005b44: af00 add r7, sp, #0
8005b46: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8005b48: 687b ldr r3, [r7, #4]
8005b4a: 2b00 cmp r3, #0
8005b4c: d101 bne.n 8005b52 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8005b4e: 2301 movs r3, #1
8005b50: e041 b.n 8005bd6 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8005b52: 687b ldr r3, [r7, #4]
8005b54: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8005b58: b2db uxtb r3, r3
8005b5a: 2b00 cmp r3, #0
8005b5c: d106 bne.n 8005b6c <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005b5e: 687b ldr r3, [r7, #4]
8005b60: 2200 movs r2, #0
8005b62: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8005b66: 6878 ldr r0, [r7, #4]
8005b68: f7fc f954 bl 8001e14 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005b6c: 687b ldr r3, [r7, #4]
8005b6e: 2202 movs r2, #2
8005b70: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8005b74: 687b ldr r3, [r7, #4]
8005b76: 681a ldr r2, [r3, #0]
8005b78: 687b ldr r3, [r7, #4]
8005b7a: 3304 adds r3, #4
8005b7c: 4619 mov r1, r3
8005b7e: 4610 mov r0, r2
8005b80: f000 fb3e bl 8006200 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8005b84: 687b ldr r3, [r7, #4]
8005b86: 2201 movs r2, #1
8005b88: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005b8c: 687b ldr r3, [r7, #4]
8005b8e: 2201 movs r2, #1
8005b90: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005b94: 687b ldr r3, [r7, #4]
8005b96: 2201 movs r2, #1
8005b98: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005b9c: 687b ldr r3, [r7, #4]
8005b9e: 2201 movs r2, #1
8005ba0: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005ba4: 687b ldr r3, [r7, #4]
8005ba6: 2201 movs r2, #1
8005ba8: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005bac: 687b ldr r3, [r7, #4]
8005bae: 2201 movs r2, #1
8005bb0: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005bb4: 687b ldr r3, [r7, #4]
8005bb6: 2201 movs r2, #1
8005bb8: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005bbc: 687b ldr r3, [r7, #4]
8005bbe: 2201 movs r2, #1
8005bc0: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005bc4: 687b ldr r3, [r7, #4]
8005bc6: 2201 movs r2, #1
8005bc8: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8005bcc: 687b ldr r3, [r7, #4]
8005bce: 2201 movs r2, #1
8005bd0: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8005bd4: 2300 movs r3, #0
}
8005bd6: 4618 mov r0, r3
8005bd8: 3708 adds r7, #8
8005bda: 46bd mov sp, r7
8005bdc: bd80 pop {r7, pc}
08005bde <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8005bde: b580 push {r7, lr}
8005be0: b082 sub sp, #8
8005be2: af00 add r7, sp, #0
8005be4: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8005be6: 687b ldr r3, [r7, #4]
8005be8: 2b00 cmp r3, #0
8005bea: d101 bne.n 8005bf0 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8005bec: 2301 movs r3, #1
8005bee: e041 b.n 8005c74 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8005bf0: 687b ldr r3, [r7, #4]
8005bf2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8005bf6: b2db uxtb r3, r3
8005bf8: 2b00 cmp r3, #0
8005bfa: d106 bne.n 8005c0a <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005bfc: 687b ldr r3, [r7, #4]
8005bfe: 2200 movs r2, #0
8005c00: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8005c04: 6878 ldr r0, [r7, #4]
8005c06: f000 f839 bl 8005c7c <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005c0a: 687b ldr r3, [r7, #4]
8005c0c: 2202 movs r2, #2
8005c0e: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8005c12: 687b ldr r3, [r7, #4]
8005c14: 681a ldr r2, [r3, #0]
8005c16: 687b ldr r3, [r7, #4]
8005c18: 3304 adds r3, #4
8005c1a: 4619 mov r1, r3
8005c1c: 4610 mov r0, r2
8005c1e: f000 faef bl 8006200 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8005c22: 687b ldr r3, [r7, #4]
8005c24: 2201 movs r2, #1
8005c26: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005c2a: 687b ldr r3, [r7, #4]
8005c2c: 2201 movs r2, #1
8005c2e: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005c32: 687b ldr r3, [r7, #4]
8005c34: 2201 movs r2, #1
8005c36: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005c3a: 687b ldr r3, [r7, #4]
8005c3c: 2201 movs r2, #1
8005c3e: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005c42: 687b ldr r3, [r7, #4]
8005c44: 2201 movs r2, #1
8005c46: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005c4a: 687b ldr r3, [r7, #4]
8005c4c: 2201 movs r2, #1
8005c4e: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005c52: 687b ldr r3, [r7, #4]
8005c54: 2201 movs r2, #1
8005c56: f883 2043 strb.w r2, [r3, #67] @ 0x43
8005c5a: 687b ldr r3, [r7, #4]
8005c5c: 2201 movs r2, #1
8005c5e: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005c62: 687b ldr r3, [r7, #4]
8005c64: 2201 movs r2, #1
8005c66: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8005c6a: 687b ldr r3, [r7, #4]
8005c6c: 2201 movs r2, #1
8005c6e: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8005c72: 2300 movs r3, #0
}
8005c74: 4618 mov r0, r3
8005c76: 3708 adds r7, #8
8005c78: 46bd mov sp, r7
8005c7a: bd80 pop {r7, pc}
08005c7c <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8005c7c: b480 push {r7}
8005c7e: b083 sub sp, #12
8005c80: af00 add r7, sp, #0
8005c82: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8005c84: bf00 nop
8005c86: 370c adds r7, #12
8005c88: 46bd mov sp, r7
8005c8a: bc80 pop {r7}
8005c8c: 4770 bx lr
...
08005c90 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8005c90: b580 push {r7, lr}
8005c92: b084 sub sp, #16
8005c94: af00 add r7, sp, #0
8005c96: 6078 str r0, [r7, #4]
8005c98: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8005c9a: 683b ldr r3, [r7, #0]
8005c9c: 2b00 cmp r3, #0
8005c9e: d109 bne.n 8005cb4 <HAL_TIM_PWM_Start+0x24>
8005ca0: 687b ldr r3, [r7, #4]
8005ca2: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8005ca6: b2db uxtb r3, r3
8005ca8: 2b01 cmp r3, #1
8005caa: bf14 ite ne
8005cac: 2301 movne r3, #1
8005cae: 2300 moveq r3, #0
8005cb0: b2db uxtb r3, r3
8005cb2: e022 b.n 8005cfa <HAL_TIM_PWM_Start+0x6a>
8005cb4: 683b ldr r3, [r7, #0]
8005cb6: 2b04 cmp r3, #4
8005cb8: d109 bne.n 8005cce <HAL_TIM_PWM_Start+0x3e>
8005cba: 687b ldr r3, [r7, #4]
8005cbc: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8005cc0: b2db uxtb r3, r3
8005cc2: 2b01 cmp r3, #1
8005cc4: bf14 ite ne
8005cc6: 2301 movne r3, #1
8005cc8: 2300 moveq r3, #0
8005cca: b2db uxtb r3, r3
8005ccc: e015 b.n 8005cfa <HAL_TIM_PWM_Start+0x6a>
8005cce: 683b ldr r3, [r7, #0]
8005cd0: 2b08 cmp r3, #8
8005cd2: d109 bne.n 8005ce8 <HAL_TIM_PWM_Start+0x58>
8005cd4: 687b ldr r3, [r7, #4]
8005cd6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8005cda: b2db uxtb r3, r3
8005cdc: 2b01 cmp r3, #1
8005cde: bf14 ite ne
8005ce0: 2301 movne r3, #1
8005ce2: 2300 moveq r3, #0
8005ce4: b2db uxtb r3, r3
8005ce6: e008 b.n 8005cfa <HAL_TIM_PWM_Start+0x6a>
8005ce8: 687b ldr r3, [r7, #4]
8005cea: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005cee: b2db uxtb r3, r3
8005cf0: 2b01 cmp r3, #1
8005cf2: bf14 ite ne
8005cf4: 2301 movne r3, #1
8005cf6: 2300 moveq r3, #0
8005cf8: b2db uxtb r3, r3
8005cfa: 2b00 cmp r3, #0
8005cfc: d001 beq.n 8005d02 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8005cfe: 2301 movs r3, #1
8005d00: e05e b.n 8005dc0 <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8005d02: 683b ldr r3, [r7, #0]
8005d04: 2b00 cmp r3, #0
8005d06: d104 bne.n 8005d12 <HAL_TIM_PWM_Start+0x82>
8005d08: 687b ldr r3, [r7, #4]
8005d0a: 2202 movs r2, #2
8005d0c: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005d10: e013 b.n 8005d3a <HAL_TIM_PWM_Start+0xaa>
8005d12: 683b ldr r3, [r7, #0]
8005d14: 2b04 cmp r3, #4
8005d16: d104 bne.n 8005d22 <HAL_TIM_PWM_Start+0x92>
8005d18: 687b ldr r3, [r7, #4]
8005d1a: 2202 movs r2, #2
8005d1c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005d20: e00b b.n 8005d3a <HAL_TIM_PWM_Start+0xaa>
8005d22: 683b ldr r3, [r7, #0]
8005d24: 2b08 cmp r3, #8
8005d26: d104 bne.n 8005d32 <HAL_TIM_PWM_Start+0xa2>
8005d28: 687b ldr r3, [r7, #4]
8005d2a: 2202 movs r2, #2
8005d2c: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005d30: e003 b.n 8005d3a <HAL_TIM_PWM_Start+0xaa>
8005d32: 687b ldr r3, [r7, #4]
8005d34: 2202 movs r2, #2
8005d36: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8005d3a: 687b ldr r3, [r7, #4]
8005d3c: 681b ldr r3, [r3, #0]
8005d3e: 2201 movs r2, #1
8005d40: 6839 ldr r1, [r7, #0]
8005d42: 4618 mov r0, r3
8005d44: f000 fce8 bl 8006718 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8005d48: 687b ldr r3, [r7, #4]
8005d4a: 681b ldr r3, [r3, #0]
8005d4c: 4a1e ldr r2, [pc, #120] @ (8005dc8 <HAL_TIM_PWM_Start+0x138>)
8005d4e: 4293 cmp r3, r2
8005d50: d107 bne.n 8005d62 <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8005d52: 687b ldr r3, [r7, #4]
8005d54: 681b ldr r3, [r3, #0]
8005d56: 6c5a ldr r2, [r3, #68] @ 0x44
8005d58: 687b ldr r3, [r7, #4]
8005d5a: 681b ldr r3, [r3, #0]
8005d5c: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8005d60: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005d62: 687b ldr r3, [r7, #4]
8005d64: 681b ldr r3, [r3, #0]
8005d66: 4a18 ldr r2, [pc, #96] @ (8005dc8 <HAL_TIM_PWM_Start+0x138>)
8005d68: 4293 cmp r3, r2
8005d6a: d00e beq.n 8005d8a <HAL_TIM_PWM_Start+0xfa>
8005d6c: 687b ldr r3, [r7, #4]
8005d6e: 681b ldr r3, [r3, #0]
8005d70: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005d74: d009 beq.n 8005d8a <HAL_TIM_PWM_Start+0xfa>
8005d76: 687b ldr r3, [r7, #4]
8005d78: 681b ldr r3, [r3, #0]
8005d7a: 4a14 ldr r2, [pc, #80] @ (8005dcc <HAL_TIM_PWM_Start+0x13c>)
8005d7c: 4293 cmp r3, r2
8005d7e: d004 beq.n 8005d8a <HAL_TIM_PWM_Start+0xfa>
8005d80: 687b ldr r3, [r7, #4]
8005d82: 681b ldr r3, [r3, #0]
8005d84: 4a12 ldr r2, [pc, #72] @ (8005dd0 <HAL_TIM_PWM_Start+0x140>)
8005d86: 4293 cmp r3, r2
8005d88: d111 bne.n 8005dae <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8005d8a: 687b ldr r3, [r7, #4]
8005d8c: 681b ldr r3, [r3, #0]
8005d8e: 689b ldr r3, [r3, #8]
8005d90: f003 0307 and.w r3, r3, #7
8005d94: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8005d96: 68fb ldr r3, [r7, #12]
8005d98: 2b06 cmp r3, #6
8005d9a: d010 beq.n 8005dbe <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
8005d9c: 687b ldr r3, [r7, #4]
8005d9e: 681b ldr r3, [r3, #0]
8005da0: 681a ldr r2, [r3, #0]
8005da2: 687b ldr r3, [r7, #4]
8005da4: 681b ldr r3, [r3, #0]
8005da6: f042 0201 orr.w r2, r2, #1
8005daa: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8005dac: e007 b.n 8005dbe <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8005dae: 687b ldr r3, [r7, #4]
8005db0: 681b ldr r3, [r3, #0]
8005db2: 681a ldr r2, [r3, #0]
8005db4: 687b ldr r3, [r7, #4]
8005db6: 681b ldr r3, [r3, #0]
8005db8: f042 0201 orr.w r2, r2, #1
8005dbc: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8005dbe: 2300 movs r3, #0
}
8005dc0: 4618 mov r0, r3
8005dc2: 3710 adds r7, #16
8005dc4: 46bd mov sp, r7
8005dc6: bd80 pop {r7, pc}
8005dc8: 40012c00 .word 0x40012c00
8005dcc: 40000400 .word 0x40000400
8005dd0: 40000800 .word 0x40000800
08005dd4 <HAL_TIM_PWM_Stop>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8005dd4: b580 push {r7, lr}
8005dd6: b082 sub sp, #8
8005dd8: af00 add r7, sp, #0
8005dda: 6078 str r0, [r7, #4]
8005ddc: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
8005dde: 687b ldr r3, [r7, #4]
8005de0: 681b ldr r3, [r3, #0]
8005de2: 2200 movs r2, #0
8005de4: 6839 ldr r1, [r7, #0]
8005de6: 4618 mov r0, r3
8005de8: f000 fc96 bl 8006718 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8005dec: 687b ldr r3, [r7, #4]
8005dee: 681b ldr r3, [r3, #0]
8005df0: 4a29 ldr r2, [pc, #164] @ (8005e98 <HAL_TIM_PWM_Stop+0xc4>)
8005df2: 4293 cmp r3, r2
8005df4: d117 bne.n 8005e26 <HAL_TIM_PWM_Stop+0x52>
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
8005df6: 687b ldr r3, [r7, #4]
8005df8: 681b ldr r3, [r3, #0]
8005dfa: 6a1a ldr r2, [r3, #32]
8005dfc: f241 1311 movw r3, #4369 @ 0x1111
8005e00: 4013 ands r3, r2
8005e02: 2b00 cmp r3, #0
8005e04: d10f bne.n 8005e26 <HAL_TIM_PWM_Stop+0x52>
8005e06: 687b ldr r3, [r7, #4]
8005e08: 681b ldr r3, [r3, #0]
8005e0a: 6a1a ldr r2, [r3, #32]
8005e0c: f240 4344 movw r3, #1092 @ 0x444
8005e10: 4013 ands r3, r2
8005e12: 2b00 cmp r3, #0
8005e14: d107 bne.n 8005e26 <HAL_TIM_PWM_Stop+0x52>
8005e16: 687b ldr r3, [r7, #4]
8005e18: 681b ldr r3, [r3, #0]
8005e1a: 6c5a ldr r2, [r3, #68] @ 0x44
8005e1c: 687b ldr r3, [r7, #4]
8005e1e: 681b ldr r3, [r3, #0]
8005e20: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8005e24: 645a str r2, [r3, #68] @ 0x44
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
8005e26: 687b ldr r3, [r7, #4]
8005e28: 681b ldr r3, [r3, #0]
8005e2a: 6a1a ldr r2, [r3, #32]
8005e2c: f241 1311 movw r3, #4369 @ 0x1111
8005e30: 4013 ands r3, r2
8005e32: 2b00 cmp r3, #0
8005e34: d10f bne.n 8005e56 <HAL_TIM_PWM_Stop+0x82>
8005e36: 687b ldr r3, [r7, #4]
8005e38: 681b ldr r3, [r3, #0]
8005e3a: 6a1a ldr r2, [r3, #32]
8005e3c: f240 4344 movw r3, #1092 @ 0x444
8005e40: 4013 ands r3, r2
8005e42: 2b00 cmp r3, #0
8005e44: d107 bne.n 8005e56 <HAL_TIM_PWM_Stop+0x82>
8005e46: 687b ldr r3, [r7, #4]
8005e48: 681b ldr r3, [r3, #0]
8005e4a: 681a ldr r2, [r3, #0]
8005e4c: 687b ldr r3, [r7, #4]
8005e4e: 681b ldr r3, [r3, #0]
8005e50: f022 0201 bic.w r2, r2, #1
8005e54: 601a str r2, [r3, #0]
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
8005e56: 683b ldr r3, [r7, #0]
8005e58: 2b00 cmp r3, #0
8005e5a: d104 bne.n 8005e66 <HAL_TIM_PWM_Stop+0x92>
8005e5c: 687b ldr r3, [r7, #4]
8005e5e: 2201 movs r2, #1
8005e60: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005e64: e013 b.n 8005e8e <HAL_TIM_PWM_Stop+0xba>
8005e66: 683b ldr r3, [r7, #0]
8005e68: 2b04 cmp r3, #4
8005e6a: d104 bne.n 8005e76 <HAL_TIM_PWM_Stop+0xa2>
8005e6c: 687b ldr r3, [r7, #4]
8005e6e: 2201 movs r2, #1
8005e70: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005e74: e00b b.n 8005e8e <HAL_TIM_PWM_Stop+0xba>
8005e76: 683b ldr r3, [r7, #0]
8005e78: 2b08 cmp r3, #8
8005e7a: d104 bne.n 8005e86 <HAL_TIM_PWM_Stop+0xb2>
8005e7c: 687b ldr r3, [r7, #4]
8005e7e: 2201 movs r2, #1
8005e80: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005e84: e003 b.n 8005e8e <HAL_TIM_PWM_Stop+0xba>
8005e86: 687b ldr r3, [r7, #4]
8005e88: 2201 movs r2, #1
8005e8a: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Return function status */
return HAL_OK;
8005e8e: 2300 movs r3, #0
}
8005e90: 4618 mov r0, r3
8005e92: 3708 adds r7, #8
8005e94: 46bd mov sp, r7
8005e96: bd80 pop {r7, pc}
8005e98: 40012c00 .word 0x40012c00
08005e9c <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8005e9c: b580 push {r7, lr}
8005e9e: b086 sub sp, #24
8005ea0: af00 add r7, sp, #0
8005ea2: 60f8 str r0, [r7, #12]
8005ea4: 60b9 str r1, [r7, #8]
8005ea6: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8005ea8: 2300 movs r3, #0
8005eaa: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8005eac: 68fb ldr r3, [r7, #12]
8005eae: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005eb2: 2b01 cmp r3, #1
8005eb4: d101 bne.n 8005eba <HAL_TIM_PWM_ConfigChannel+0x1e>
8005eb6: 2302 movs r3, #2
8005eb8: e0ae b.n 8006018 <HAL_TIM_PWM_ConfigChannel+0x17c>
8005eba: 68fb ldr r3, [r7, #12]
8005ebc: 2201 movs r2, #1
8005ebe: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8005ec2: 687b ldr r3, [r7, #4]
8005ec4: 2b0c cmp r3, #12
8005ec6: f200 809f bhi.w 8006008 <HAL_TIM_PWM_ConfigChannel+0x16c>
8005eca: a201 add r2, pc, #4 @ (adr r2, 8005ed0 <HAL_TIM_PWM_ConfigChannel+0x34>)
8005ecc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005ed0: 08005f05 .word 0x08005f05
8005ed4: 08006009 .word 0x08006009
8005ed8: 08006009 .word 0x08006009
8005edc: 08006009 .word 0x08006009
8005ee0: 08005f45 .word 0x08005f45
8005ee4: 08006009 .word 0x08006009
8005ee8: 08006009 .word 0x08006009
8005eec: 08006009 .word 0x08006009
8005ef0: 08005f87 .word 0x08005f87
8005ef4: 08006009 .word 0x08006009
8005ef8: 08006009 .word 0x08006009
8005efc: 08006009 .word 0x08006009
8005f00: 08005fc7 .word 0x08005fc7
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8005f04: 68fb ldr r3, [r7, #12]
8005f06: 681b ldr r3, [r3, #0]
8005f08: 68b9 ldr r1, [r7, #8]
8005f0a: 4618 mov r0, r3
8005f0c: f000 f9e6 bl 80062dc <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8005f10: 68fb ldr r3, [r7, #12]
8005f12: 681b ldr r3, [r3, #0]
8005f14: 699a ldr r2, [r3, #24]
8005f16: 68fb ldr r3, [r7, #12]
8005f18: 681b ldr r3, [r3, #0]
8005f1a: f042 0208 orr.w r2, r2, #8
8005f1e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8005f20: 68fb ldr r3, [r7, #12]
8005f22: 681b ldr r3, [r3, #0]
8005f24: 699a ldr r2, [r3, #24]
8005f26: 68fb ldr r3, [r7, #12]
8005f28: 681b ldr r3, [r3, #0]
8005f2a: f022 0204 bic.w r2, r2, #4
8005f2e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8005f30: 68fb ldr r3, [r7, #12]
8005f32: 681b ldr r3, [r3, #0]
8005f34: 6999 ldr r1, [r3, #24]
8005f36: 68bb ldr r3, [r7, #8]
8005f38: 691a ldr r2, [r3, #16]
8005f3a: 68fb ldr r3, [r7, #12]
8005f3c: 681b ldr r3, [r3, #0]
8005f3e: 430a orrs r2, r1
8005f40: 619a str r2, [r3, #24]
break;
8005f42: e064 b.n 800600e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8005f44: 68fb ldr r3, [r7, #12]
8005f46: 681b ldr r3, [r3, #0]
8005f48: 68b9 ldr r1, [r7, #8]
8005f4a: 4618 mov r0, r3
8005f4c: f000 fa2c bl 80063a8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8005f50: 68fb ldr r3, [r7, #12]
8005f52: 681b ldr r3, [r3, #0]
8005f54: 699a ldr r2, [r3, #24]
8005f56: 68fb ldr r3, [r7, #12]
8005f58: 681b ldr r3, [r3, #0]
8005f5a: f442 6200 orr.w r2, r2, #2048 @ 0x800
8005f5e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8005f60: 68fb ldr r3, [r7, #12]
8005f62: 681b ldr r3, [r3, #0]
8005f64: 699a ldr r2, [r3, #24]
8005f66: 68fb ldr r3, [r7, #12]
8005f68: 681b ldr r3, [r3, #0]
8005f6a: f422 6280 bic.w r2, r2, #1024 @ 0x400
8005f6e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8005f70: 68fb ldr r3, [r7, #12]
8005f72: 681b ldr r3, [r3, #0]
8005f74: 6999 ldr r1, [r3, #24]
8005f76: 68bb ldr r3, [r7, #8]
8005f78: 691b ldr r3, [r3, #16]
8005f7a: 021a lsls r2, r3, #8
8005f7c: 68fb ldr r3, [r7, #12]
8005f7e: 681b ldr r3, [r3, #0]
8005f80: 430a orrs r2, r1
8005f82: 619a str r2, [r3, #24]
break;
8005f84: e043 b.n 800600e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8005f86: 68fb ldr r3, [r7, #12]
8005f88: 681b ldr r3, [r3, #0]
8005f8a: 68b9 ldr r1, [r7, #8]
8005f8c: 4618 mov r0, r3
8005f8e: f000 fa75 bl 800647c <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8005f92: 68fb ldr r3, [r7, #12]
8005f94: 681b ldr r3, [r3, #0]
8005f96: 69da ldr r2, [r3, #28]
8005f98: 68fb ldr r3, [r7, #12]
8005f9a: 681b ldr r3, [r3, #0]
8005f9c: f042 0208 orr.w r2, r2, #8
8005fa0: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8005fa2: 68fb ldr r3, [r7, #12]
8005fa4: 681b ldr r3, [r3, #0]
8005fa6: 69da ldr r2, [r3, #28]
8005fa8: 68fb ldr r3, [r7, #12]
8005faa: 681b ldr r3, [r3, #0]
8005fac: f022 0204 bic.w r2, r2, #4
8005fb0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8005fb2: 68fb ldr r3, [r7, #12]
8005fb4: 681b ldr r3, [r3, #0]
8005fb6: 69d9 ldr r1, [r3, #28]
8005fb8: 68bb ldr r3, [r7, #8]
8005fba: 691a ldr r2, [r3, #16]
8005fbc: 68fb ldr r3, [r7, #12]
8005fbe: 681b ldr r3, [r3, #0]
8005fc0: 430a orrs r2, r1
8005fc2: 61da str r2, [r3, #28]
break;
8005fc4: e023 b.n 800600e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8005fc6: 68fb ldr r3, [r7, #12]
8005fc8: 681b ldr r3, [r3, #0]
8005fca: 68b9 ldr r1, [r7, #8]
8005fcc: 4618 mov r0, r3
8005fce: f000 fabf bl 8006550 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8005fd2: 68fb ldr r3, [r7, #12]
8005fd4: 681b ldr r3, [r3, #0]
8005fd6: 69da ldr r2, [r3, #28]
8005fd8: 68fb ldr r3, [r7, #12]
8005fda: 681b ldr r3, [r3, #0]
8005fdc: f442 6200 orr.w r2, r2, #2048 @ 0x800
8005fe0: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8005fe2: 68fb ldr r3, [r7, #12]
8005fe4: 681b ldr r3, [r3, #0]
8005fe6: 69da ldr r2, [r3, #28]
8005fe8: 68fb ldr r3, [r7, #12]
8005fea: 681b ldr r3, [r3, #0]
8005fec: f422 6280 bic.w r2, r2, #1024 @ 0x400
8005ff0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8005ff2: 68fb ldr r3, [r7, #12]
8005ff4: 681b ldr r3, [r3, #0]
8005ff6: 69d9 ldr r1, [r3, #28]
8005ff8: 68bb ldr r3, [r7, #8]
8005ffa: 691b ldr r3, [r3, #16]
8005ffc: 021a lsls r2, r3, #8
8005ffe: 68fb ldr r3, [r7, #12]
8006000: 681b ldr r3, [r3, #0]
8006002: 430a orrs r2, r1
8006004: 61da str r2, [r3, #28]
break;
8006006: e002 b.n 800600e <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8006008: 2301 movs r3, #1
800600a: 75fb strb r3, [r7, #23]
break;
800600c: bf00 nop
}
__HAL_UNLOCK(htim);
800600e: 68fb ldr r3, [r7, #12]
8006010: 2200 movs r2, #0
8006012: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8006016: 7dfb ldrb r3, [r7, #23]
}
8006018: 4618 mov r0, r3
800601a: 3718 adds r7, #24
800601c: 46bd mov sp, r7
800601e: bd80 pop {r7, pc}
08006020 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8006020: b580 push {r7, lr}
8006022: b084 sub sp, #16
8006024: af00 add r7, sp, #0
8006026: 6078 str r0, [r7, #4]
8006028: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
800602a: 2300 movs r3, #0
800602c: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800602e: 687b ldr r3, [r7, #4]
8006030: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8006034: 2b01 cmp r3, #1
8006036: d101 bne.n 800603c <HAL_TIM_ConfigClockSource+0x1c>
8006038: 2302 movs r3, #2
800603a: e0b4 b.n 80061a6 <HAL_TIM_ConfigClockSource+0x186>
800603c: 687b ldr r3, [r7, #4]
800603e: 2201 movs r2, #1
8006040: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8006044: 687b ldr r3, [r7, #4]
8006046: 2202 movs r2, #2
8006048: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800604c: 687b ldr r3, [r7, #4]
800604e: 681b ldr r3, [r3, #0]
8006050: 689b ldr r3, [r3, #8]
8006052: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8006054: 68bb ldr r3, [r7, #8]
8006056: f023 0377 bic.w r3, r3, #119 @ 0x77
800605a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800605c: 68bb ldr r3, [r7, #8]
800605e: f423 437f bic.w r3, r3, #65280 @ 0xff00
8006062: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8006064: 687b ldr r3, [r7, #4]
8006066: 681b ldr r3, [r3, #0]
8006068: 68ba ldr r2, [r7, #8]
800606a: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800606c: 683b ldr r3, [r7, #0]
800606e: 681b ldr r3, [r3, #0]
8006070: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8006074: d03e beq.n 80060f4 <HAL_TIM_ConfigClockSource+0xd4>
8006076: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800607a: f200 8087 bhi.w 800618c <HAL_TIM_ConfigClockSource+0x16c>
800607e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8006082: f000 8086 beq.w 8006192 <HAL_TIM_ConfigClockSource+0x172>
8006086: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800608a: d87f bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
800608c: 2b70 cmp r3, #112 @ 0x70
800608e: d01a beq.n 80060c6 <HAL_TIM_ConfigClockSource+0xa6>
8006090: 2b70 cmp r3, #112 @ 0x70
8006092: d87b bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
8006094: 2b60 cmp r3, #96 @ 0x60
8006096: d050 beq.n 800613a <HAL_TIM_ConfigClockSource+0x11a>
8006098: 2b60 cmp r3, #96 @ 0x60
800609a: d877 bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
800609c: 2b50 cmp r3, #80 @ 0x50
800609e: d03c beq.n 800611a <HAL_TIM_ConfigClockSource+0xfa>
80060a0: 2b50 cmp r3, #80 @ 0x50
80060a2: d873 bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
80060a4: 2b40 cmp r3, #64 @ 0x40
80060a6: d058 beq.n 800615a <HAL_TIM_ConfigClockSource+0x13a>
80060a8: 2b40 cmp r3, #64 @ 0x40
80060aa: d86f bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
80060ac: 2b30 cmp r3, #48 @ 0x30
80060ae: d064 beq.n 800617a <HAL_TIM_ConfigClockSource+0x15a>
80060b0: 2b30 cmp r3, #48 @ 0x30
80060b2: d86b bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
80060b4: 2b20 cmp r3, #32
80060b6: d060 beq.n 800617a <HAL_TIM_ConfigClockSource+0x15a>
80060b8: 2b20 cmp r3, #32
80060ba: d867 bhi.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
80060bc: 2b00 cmp r3, #0
80060be: d05c beq.n 800617a <HAL_TIM_ConfigClockSource+0x15a>
80060c0: 2b10 cmp r3, #16
80060c2: d05a beq.n 800617a <HAL_TIM_ConfigClockSource+0x15a>
80060c4: e062 b.n 800618c <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80060c6: 687b ldr r3, [r7, #4]
80060c8: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80060ca: 683b ldr r3, [r7, #0]
80060cc: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80060ce: 683b ldr r3, [r7, #0]
80060d0: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80060d2: 683b ldr r3, [r7, #0]
80060d4: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80060d6: f000 fb00 bl 80066da <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
80060da: 687b ldr r3, [r7, #4]
80060dc: 681b ldr r3, [r3, #0]
80060de: 689b ldr r3, [r3, #8]
80060e0: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80060e2: 68bb ldr r3, [r7, #8]
80060e4: f043 0377 orr.w r3, r3, #119 @ 0x77
80060e8: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80060ea: 687b ldr r3, [r7, #4]
80060ec: 681b ldr r3, [r3, #0]
80060ee: 68ba ldr r2, [r7, #8]
80060f0: 609a str r2, [r3, #8]
break;
80060f2: e04f b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80060f4: 687b ldr r3, [r7, #4]
80060f6: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80060f8: 683b ldr r3, [r7, #0]
80060fa: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80060fc: 683b ldr r3, [r7, #0]
80060fe: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8006100: 683b ldr r3, [r7, #0]
8006102: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8006104: f000 fae9 bl 80066da <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8006108: 687b ldr r3, [r7, #4]
800610a: 681b ldr r3, [r3, #0]
800610c: 689a ldr r2, [r3, #8]
800610e: 687b ldr r3, [r7, #4]
8006110: 681b ldr r3, [r3, #0]
8006112: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8006116: 609a str r2, [r3, #8]
break;
8006118: e03c b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800611a: 687b ldr r3, [r7, #4]
800611c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800611e: 683b ldr r3, [r7, #0]
8006120: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8006122: 683b ldr r3, [r7, #0]
8006124: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8006126: 461a mov r2, r3
8006128: f000 fa60 bl 80065ec <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
800612c: 687b ldr r3, [r7, #4]
800612e: 681b ldr r3, [r3, #0]
8006130: 2150 movs r1, #80 @ 0x50
8006132: 4618 mov r0, r3
8006134: f000 fab7 bl 80066a6 <TIM_ITRx_SetConfig>
break;
8006138: e02c b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
800613a: 687b ldr r3, [r7, #4]
800613c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800613e: 683b ldr r3, [r7, #0]
8006140: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8006142: 683b ldr r3, [r7, #0]
8006144: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8006146: 461a mov r2, r3
8006148: f000 fa7e bl 8006648 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800614c: 687b ldr r3, [r7, #4]
800614e: 681b ldr r3, [r3, #0]
8006150: 2160 movs r1, #96 @ 0x60
8006152: 4618 mov r0, r3
8006154: f000 faa7 bl 80066a6 <TIM_ITRx_SetConfig>
break;
8006158: e01c b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800615a: 687b ldr r3, [r7, #4]
800615c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800615e: 683b ldr r3, [r7, #0]
8006160: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8006162: 683b ldr r3, [r7, #0]
8006164: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8006166: 461a mov r2, r3
8006168: f000 fa40 bl 80065ec <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800616c: 687b ldr r3, [r7, #4]
800616e: 681b ldr r3, [r3, #0]
8006170: 2140 movs r1, #64 @ 0x40
8006172: 4618 mov r0, r3
8006174: f000 fa97 bl 80066a6 <TIM_ITRx_SetConfig>
break;
8006178: e00c b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800617a: 687b ldr r3, [r7, #4]
800617c: 681a ldr r2, [r3, #0]
800617e: 683b ldr r3, [r7, #0]
8006180: 681b ldr r3, [r3, #0]
8006182: 4619 mov r1, r3
8006184: 4610 mov r0, r2
8006186: f000 fa8e bl 80066a6 <TIM_ITRx_SetConfig>
break;
800618a: e003 b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
800618c: 2301 movs r3, #1
800618e: 73fb strb r3, [r7, #15]
break;
8006190: e000 b.n 8006194 <HAL_TIM_ConfigClockSource+0x174>
break;
8006192: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8006194: 687b ldr r3, [r7, #4]
8006196: 2201 movs r2, #1
8006198: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
800619c: 687b ldr r3, [r7, #4]
800619e: 2200 movs r2, #0
80061a0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80061a4: 7bfb ldrb r3, [r7, #15]
}
80061a6: 4618 mov r0, r3
80061a8: 3710 adds r7, #16
80061aa: 46bd mov sp, r7
80061ac: bd80 pop {r7, pc}
080061ae <HAL_TIM_GetChannelState>:
* @arg TIM_CHANNEL_5: TIM Channel 5
* @arg TIM_CHANNEL_6: TIM Channel 6
* @retval TIM Channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
80061ae: b480 push {r7}
80061b0: b085 sub sp, #20
80061b2: af00 add r7, sp, #0
80061b4: 6078 str r0, [r7, #4]
80061b6: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
80061b8: 683b ldr r3, [r7, #0]
80061ba: 2b00 cmp r3, #0
80061bc: d104 bne.n 80061c8 <HAL_TIM_GetChannelState+0x1a>
80061be: 687b ldr r3, [r7, #4]
80061c0: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
80061c4: b2db uxtb r3, r3
80061c6: e013 b.n 80061f0 <HAL_TIM_GetChannelState+0x42>
80061c8: 683b ldr r3, [r7, #0]
80061ca: 2b04 cmp r3, #4
80061cc: d104 bne.n 80061d8 <HAL_TIM_GetChannelState+0x2a>
80061ce: 687b ldr r3, [r7, #4]
80061d0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
80061d4: b2db uxtb r3, r3
80061d6: e00b b.n 80061f0 <HAL_TIM_GetChannelState+0x42>
80061d8: 683b ldr r3, [r7, #0]
80061da: 2b08 cmp r3, #8
80061dc: d104 bne.n 80061e8 <HAL_TIM_GetChannelState+0x3a>
80061de: 687b ldr r3, [r7, #4]
80061e0: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80061e4: b2db uxtb r3, r3
80061e6: e003 b.n 80061f0 <HAL_TIM_GetChannelState+0x42>
80061e8: 687b ldr r3, [r7, #4]
80061ea: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80061ee: b2db uxtb r3, r3
80061f0: 73fb strb r3, [r7, #15]
return channel_state;
80061f2: 7bfb ldrb r3, [r7, #15]
}
80061f4: 4618 mov r0, r3
80061f6: 3714 adds r7, #20
80061f8: 46bd mov sp, r7
80061fa: bc80 pop {r7}
80061fc: 4770 bx lr
...
08006200 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8006200: b480 push {r7}
8006202: b085 sub sp, #20
8006204: af00 add r7, sp, #0
8006206: 6078 str r0, [r7, #4]
8006208: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800620a: 687b ldr r3, [r7, #4]
800620c: 681b ldr r3, [r3, #0]
800620e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8006210: 687b ldr r3, [r7, #4]
8006212: 4a2f ldr r2, [pc, #188] @ (80062d0 <TIM_Base_SetConfig+0xd0>)
8006214: 4293 cmp r3, r2
8006216: d00b beq.n 8006230 <TIM_Base_SetConfig+0x30>
8006218: 687b ldr r3, [r7, #4]
800621a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800621e: d007 beq.n 8006230 <TIM_Base_SetConfig+0x30>
8006220: 687b ldr r3, [r7, #4]
8006222: 4a2c ldr r2, [pc, #176] @ (80062d4 <TIM_Base_SetConfig+0xd4>)
8006224: 4293 cmp r3, r2
8006226: d003 beq.n 8006230 <TIM_Base_SetConfig+0x30>
8006228: 687b ldr r3, [r7, #4]
800622a: 4a2b ldr r2, [pc, #172] @ (80062d8 <TIM_Base_SetConfig+0xd8>)
800622c: 4293 cmp r3, r2
800622e: d108 bne.n 8006242 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8006230: 68fb ldr r3, [r7, #12]
8006232: f023 0370 bic.w r3, r3, #112 @ 0x70
8006236: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8006238: 683b ldr r3, [r7, #0]
800623a: 685b ldr r3, [r3, #4]
800623c: 68fa ldr r2, [r7, #12]
800623e: 4313 orrs r3, r2
8006240: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8006242: 687b ldr r3, [r7, #4]
8006244: 4a22 ldr r2, [pc, #136] @ (80062d0 <TIM_Base_SetConfig+0xd0>)
8006246: 4293 cmp r3, r2
8006248: d00b beq.n 8006262 <TIM_Base_SetConfig+0x62>
800624a: 687b ldr r3, [r7, #4]
800624c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8006250: d007 beq.n 8006262 <TIM_Base_SetConfig+0x62>
8006252: 687b ldr r3, [r7, #4]
8006254: 4a1f ldr r2, [pc, #124] @ (80062d4 <TIM_Base_SetConfig+0xd4>)
8006256: 4293 cmp r3, r2
8006258: d003 beq.n 8006262 <TIM_Base_SetConfig+0x62>
800625a: 687b ldr r3, [r7, #4]
800625c: 4a1e ldr r2, [pc, #120] @ (80062d8 <TIM_Base_SetConfig+0xd8>)
800625e: 4293 cmp r3, r2
8006260: d108 bne.n 8006274 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8006262: 68fb ldr r3, [r7, #12]
8006264: f423 7340 bic.w r3, r3, #768 @ 0x300
8006268: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800626a: 683b ldr r3, [r7, #0]
800626c: 68db ldr r3, [r3, #12]
800626e: 68fa ldr r2, [r7, #12]
8006270: 4313 orrs r3, r2
8006272: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8006274: 68fb ldr r3, [r7, #12]
8006276: f023 0280 bic.w r2, r3, #128 @ 0x80
800627a: 683b ldr r3, [r7, #0]
800627c: 695b ldr r3, [r3, #20]
800627e: 4313 orrs r3, r2
8006280: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8006282: 687b ldr r3, [r7, #4]
8006284: 68fa ldr r2, [r7, #12]
8006286: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8006288: 683b ldr r3, [r7, #0]
800628a: 689a ldr r2, [r3, #8]
800628c: 687b ldr r3, [r7, #4]
800628e: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8006290: 683b ldr r3, [r7, #0]
8006292: 681a ldr r2, [r3, #0]
8006294: 687b ldr r3, [r7, #4]
8006296: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8006298: 687b ldr r3, [r7, #4]
800629a: 4a0d ldr r2, [pc, #52] @ (80062d0 <TIM_Base_SetConfig+0xd0>)
800629c: 4293 cmp r3, r2
800629e: d103 bne.n 80062a8 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80062a0: 683b ldr r3, [r7, #0]
80062a2: 691a ldr r2, [r3, #16]
80062a4: 687b ldr r3, [r7, #4]
80062a6: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80062a8: 687b ldr r3, [r7, #4]
80062aa: 2201 movs r2, #1
80062ac: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
80062ae: 687b ldr r3, [r7, #4]
80062b0: 691b ldr r3, [r3, #16]
80062b2: f003 0301 and.w r3, r3, #1
80062b6: 2b00 cmp r3, #0
80062b8: d005 beq.n 80062c6 <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
80062ba: 687b ldr r3, [r7, #4]
80062bc: 691b ldr r3, [r3, #16]
80062be: f023 0201 bic.w r2, r3, #1
80062c2: 687b ldr r3, [r7, #4]
80062c4: 611a str r2, [r3, #16]
}
}
80062c6: bf00 nop
80062c8: 3714 adds r7, #20
80062ca: 46bd mov sp, r7
80062cc: bc80 pop {r7}
80062ce: 4770 bx lr
80062d0: 40012c00 .word 0x40012c00
80062d4: 40000400 .word 0x40000400
80062d8: 40000800 .word 0x40000800
080062dc <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80062dc: b480 push {r7}
80062de: b087 sub sp, #28
80062e0: af00 add r7, sp, #0
80062e2: 6078 str r0, [r7, #4]
80062e4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80062e6: 687b ldr r3, [r7, #4]
80062e8: 6a1b ldr r3, [r3, #32]
80062ea: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80062ec: 687b ldr r3, [r7, #4]
80062ee: 6a1b ldr r3, [r3, #32]
80062f0: f023 0201 bic.w r2, r3, #1
80062f4: 687b ldr r3, [r7, #4]
80062f6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80062f8: 687b ldr r3, [r7, #4]
80062fa: 685b ldr r3, [r3, #4]
80062fc: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80062fe: 687b ldr r3, [r7, #4]
8006300: 699b ldr r3, [r3, #24]
8006302: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8006304: 68fb ldr r3, [r7, #12]
8006306: f023 0370 bic.w r3, r3, #112 @ 0x70
800630a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800630c: 68fb ldr r3, [r7, #12]
800630e: f023 0303 bic.w r3, r3, #3
8006312: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8006314: 683b ldr r3, [r7, #0]
8006316: 681b ldr r3, [r3, #0]
8006318: 68fa ldr r2, [r7, #12]
800631a: 4313 orrs r3, r2
800631c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800631e: 697b ldr r3, [r7, #20]
8006320: f023 0302 bic.w r3, r3, #2
8006324: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8006326: 683b ldr r3, [r7, #0]
8006328: 689b ldr r3, [r3, #8]
800632a: 697a ldr r2, [r7, #20]
800632c: 4313 orrs r3, r2
800632e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8006330: 687b ldr r3, [r7, #4]
8006332: 4a1c ldr r2, [pc, #112] @ (80063a4 <TIM_OC1_SetConfig+0xc8>)
8006334: 4293 cmp r3, r2
8006336: d10c bne.n 8006352 <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8006338: 697b ldr r3, [r7, #20]
800633a: f023 0308 bic.w r3, r3, #8
800633e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8006340: 683b ldr r3, [r7, #0]
8006342: 68db ldr r3, [r3, #12]
8006344: 697a ldr r2, [r7, #20]
8006346: 4313 orrs r3, r2
8006348: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800634a: 697b ldr r3, [r7, #20]
800634c: f023 0304 bic.w r3, r3, #4
8006350: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8006352: 687b ldr r3, [r7, #4]
8006354: 4a13 ldr r2, [pc, #76] @ (80063a4 <TIM_OC1_SetConfig+0xc8>)
8006356: 4293 cmp r3, r2
8006358: d111 bne.n 800637e <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800635a: 693b ldr r3, [r7, #16]
800635c: f423 7380 bic.w r3, r3, #256 @ 0x100
8006360: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8006362: 693b ldr r3, [r7, #16]
8006364: f423 7300 bic.w r3, r3, #512 @ 0x200
8006368: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800636a: 683b ldr r3, [r7, #0]
800636c: 695b ldr r3, [r3, #20]
800636e: 693a ldr r2, [r7, #16]
8006370: 4313 orrs r3, r2
8006372: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8006374: 683b ldr r3, [r7, #0]
8006376: 699b ldr r3, [r3, #24]
8006378: 693a ldr r2, [r7, #16]
800637a: 4313 orrs r3, r2
800637c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800637e: 687b ldr r3, [r7, #4]
8006380: 693a ldr r2, [r7, #16]
8006382: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8006384: 687b ldr r3, [r7, #4]
8006386: 68fa ldr r2, [r7, #12]
8006388: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800638a: 683b ldr r3, [r7, #0]
800638c: 685a ldr r2, [r3, #4]
800638e: 687b ldr r3, [r7, #4]
8006390: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8006392: 687b ldr r3, [r7, #4]
8006394: 697a ldr r2, [r7, #20]
8006396: 621a str r2, [r3, #32]
}
8006398: bf00 nop
800639a: 371c adds r7, #28
800639c: 46bd mov sp, r7
800639e: bc80 pop {r7}
80063a0: 4770 bx lr
80063a2: bf00 nop
80063a4: 40012c00 .word 0x40012c00
080063a8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80063a8: b480 push {r7}
80063aa: b087 sub sp, #28
80063ac: af00 add r7, sp, #0
80063ae: 6078 str r0, [r7, #4]
80063b0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80063b2: 687b ldr r3, [r7, #4]
80063b4: 6a1b ldr r3, [r3, #32]
80063b6: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80063b8: 687b ldr r3, [r7, #4]
80063ba: 6a1b ldr r3, [r3, #32]
80063bc: f023 0210 bic.w r2, r3, #16
80063c0: 687b ldr r3, [r7, #4]
80063c2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80063c4: 687b ldr r3, [r7, #4]
80063c6: 685b ldr r3, [r3, #4]
80063c8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80063ca: 687b ldr r3, [r7, #4]
80063cc: 699b ldr r3, [r3, #24]
80063ce: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
80063d0: 68fb ldr r3, [r7, #12]
80063d2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80063d6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
80063d8: 68fb ldr r3, [r7, #12]
80063da: f423 7340 bic.w r3, r3, #768 @ 0x300
80063de: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80063e0: 683b ldr r3, [r7, #0]
80063e2: 681b ldr r3, [r3, #0]
80063e4: 021b lsls r3, r3, #8
80063e6: 68fa ldr r2, [r7, #12]
80063e8: 4313 orrs r3, r2
80063ea: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
80063ec: 697b ldr r3, [r7, #20]
80063ee: f023 0320 bic.w r3, r3, #32
80063f2: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
80063f4: 683b ldr r3, [r7, #0]
80063f6: 689b ldr r3, [r3, #8]
80063f8: 011b lsls r3, r3, #4
80063fa: 697a ldr r2, [r7, #20]
80063fc: 4313 orrs r3, r2
80063fe: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8006400: 687b ldr r3, [r7, #4]
8006402: 4a1d ldr r2, [pc, #116] @ (8006478 <TIM_OC2_SetConfig+0xd0>)
8006404: 4293 cmp r3, r2
8006406: d10d bne.n 8006424 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8006408: 697b ldr r3, [r7, #20]
800640a: f023 0380 bic.w r3, r3, #128 @ 0x80
800640e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8006410: 683b ldr r3, [r7, #0]
8006412: 68db ldr r3, [r3, #12]
8006414: 011b lsls r3, r3, #4
8006416: 697a ldr r2, [r7, #20]
8006418: 4313 orrs r3, r2
800641a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
800641c: 697b ldr r3, [r7, #20]
800641e: f023 0340 bic.w r3, r3, #64 @ 0x40
8006422: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8006424: 687b ldr r3, [r7, #4]
8006426: 4a14 ldr r2, [pc, #80] @ (8006478 <TIM_OC2_SetConfig+0xd0>)
8006428: 4293 cmp r3, r2
800642a: d113 bne.n 8006454 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
800642c: 693b ldr r3, [r7, #16]
800642e: f423 6380 bic.w r3, r3, #1024 @ 0x400
8006432: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8006434: 693b ldr r3, [r7, #16]
8006436: f423 6300 bic.w r3, r3, #2048 @ 0x800
800643a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
800643c: 683b ldr r3, [r7, #0]
800643e: 695b ldr r3, [r3, #20]
8006440: 009b lsls r3, r3, #2
8006442: 693a ldr r2, [r7, #16]
8006444: 4313 orrs r3, r2
8006446: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8006448: 683b ldr r3, [r7, #0]
800644a: 699b ldr r3, [r3, #24]
800644c: 009b lsls r3, r3, #2
800644e: 693a ldr r2, [r7, #16]
8006450: 4313 orrs r3, r2
8006452: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8006454: 687b ldr r3, [r7, #4]
8006456: 693a ldr r2, [r7, #16]
8006458: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800645a: 687b ldr r3, [r7, #4]
800645c: 68fa ldr r2, [r7, #12]
800645e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8006460: 683b ldr r3, [r7, #0]
8006462: 685a ldr r2, [r3, #4]
8006464: 687b ldr r3, [r7, #4]
8006466: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8006468: 687b ldr r3, [r7, #4]
800646a: 697a ldr r2, [r7, #20]
800646c: 621a str r2, [r3, #32]
}
800646e: bf00 nop
8006470: 371c adds r7, #28
8006472: 46bd mov sp, r7
8006474: bc80 pop {r7}
8006476: 4770 bx lr
8006478: 40012c00 .word 0x40012c00
0800647c <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800647c: b480 push {r7}
800647e: b087 sub sp, #28
8006480: af00 add r7, sp, #0
8006482: 6078 str r0, [r7, #4]
8006484: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8006486: 687b ldr r3, [r7, #4]
8006488: 6a1b ldr r3, [r3, #32]
800648a: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800648c: 687b ldr r3, [r7, #4]
800648e: 6a1b ldr r3, [r3, #32]
8006490: f423 7280 bic.w r2, r3, #256 @ 0x100
8006494: 687b ldr r3, [r7, #4]
8006496: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8006498: 687b ldr r3, [r7, #4]
800649a: 685b ldr r3, [r3, #4]
800649c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800649e: 687b ldr r3, [r7, #4]
80064a0: 69db ldr r3, [r3, #28]
80064a2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
80064a4: 68fb ldr r3, [r7, #12]
80064a6: f023 0370 bic.w r3, r3, #112 @ 0x70
80064aa: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80064ac: 68fb ldr r3, [r7, #12]
80064ae: f023 0303 bic.w r3, r3, #3
80064b2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80064b4: 683b ldr r3, [r7, #0]
80064b6: 681b ldr r3, [r3, #0]
80064b8: 68fa ldr r2, [r7, #12]
80064ba: 4313 orrs r3, r2
80064bc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80064be: 697b ldr r3, [r7, #20]
80064c0: f423 7300 bic.w r3, r3, #512 @ 0x200
80064c4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80064c6: 683b ldr r3, [r7, #0]
80064c8: 689b ldr r3, [r3, #8]
80064ca: 021b lsls r3, r3, #8
80064cc: 697a ldr r2, [r7, #20]
80064ce: 4313 orrs r3, r2
80064d0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
80064d2: 687b ldr r3, [r7, #4]
80064d4: 4a1d ldr r2, [pc, #116] @ (800654c <TIM_OC3_SetConfig+0xd0>)
80064d6: 4293 cmp r3, r2
80064d8: d10d bne.n 80064f6 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
80064da: 697b ldr r3, [r7, #20]
80064dc: f423 6300 bic.w r3, r3, #2048 @ 0x800
80064e0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80064e2: 683b ldr r3, [r7, #0]
80064e4: 68db ldr r3, [r3, #12]
80064e6: 021b lsls r3, r3, #8
80064e8: 697a ldr r2, [r7, #20]
80064ea: 4313 orrs r3, r2
80064ec: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
80064ee: 697b ldr r3, [r7, #20]
80064f0: f423 6380 bic.w r3, r3, #1024 @ 0x400
80064f4: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80064f6: 687b ldr r3, [r7, #4]
80064f8: 4a14 ldr r2, [pc, #80] @ (800654c <TIM_OC3_SetConfig+0xd0>)
80064fa: 4293 cmp r3, r2
80064fc: d113 bne.n 8006526 <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
80064fe: 693b ldr r3, [r7, #16]
8006500: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8006504: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8006506: 693b ldr r3, [r7, #16]
8006508: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800650c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800650e: 683b ldr r3, [r7, #0]
8006510: 695b ldr r3, [r3, #20]
8006512: 011b lsls r3, r3, #4
8006514: 693a ldr r2, [r7, #16]
8006516: 4313 orrs r3, r2
8006518: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800651a: 683b ldr r3, [r7, #0]
800651c: 699b ldr r3, [r3, #24]
800651e: 011b lsls r3, r3, #4
8006520: 693a ldr r2, [r7, #16]
8006522: 4313 orrs r3, r2
8006524: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8006526: 687b ldr r3, [r7, #4]
8006528: 693a ldr r2, [r7, #16]
800652a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800652c: 687b ldr r3, [r7, #4]
800652e: 68fa ldr r2, [r7, #12]
8006530: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8006532: 683b ldr r3, [r7, #0]
8006534: 685a ldr r2, [r3, #4]
8006536: 687b ldr r3, [r7, #4]
8006538: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800653a: 687b ldr r3, [r7, #4]
800653c: 697a ldr r2, [r7, #20]
800653e: 621a str r2, [r3, #32]
}
8006540: bf00 nop
8006542: 371c adds r7, #28
8006544: 46bd mov sp, r7
8006546: bc80 pop {r7}
8006548: 4770 bx lr
800654a: bf00 nop
800654c: 40012c00 .word 0x40012c00
08006550 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8006550: b480 push {r7}
8006552: b087 sub sp, #28
8006554: af00 add r7, sp, #0
8006556: 6078 str r0, [r7, #4]
8006558: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800655a: 687b ldr r3, [r7, #4]
800655c: 6a1b ldr r3, [r3, #32]
800655e: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8006560: 687b ldr r3, [r7, #4]
8006562: 6a1b ldr r3, [r3, #32]
8006564: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8006568: 687b ldr r3, [r7, #4]
800656a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800656c: 687b ldr r3, [r7, #4]
800656e: 685b ldr r3, [r3, #4]
8006570: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8006572: 687b ldr r3, [r7, #4]
8006574: 69db ldr r3, [r3, #28]
8006576: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8006578: 68fb ldr r3, [r7, #12]
800657a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800657e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8006580: 68fb ldr r3, [r7, #12]
8006582: f423 7340 bic.w r3, r3, #768 @ 0x300
8006586: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8006588: 683b ldr r3, [r7, #0]
800658a: 681b ldr r3, [r3, #0]
800658c: 021b lsls r3, r3, #8
800658e: 68fa ldr r2, [r7, #12]
8006590: 4313 orrs r3, r2
8006592: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8006594: 693b ldr r3, [r7, #16]
8006596: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800659a: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
800659c: 683b ldr r3, [r7, #0]
800659e: 689b ldr r3, [r3, #8]
80065a0: 031b lsls r3, r3, #12
80065a2: 693a ldr r2, [r7, #16]
80065a4: 4313 orrs r3, r2
80065a6: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80065a8: 687b ldr r3, [r7, #4]
80065aa: 4a0f ldr r2, [pc, #60] @ (80065e8 <TIM_OC4_SetConfig+0x98>)
80065ac: 4293 cmp r3, r2
80065ae: d109 bne.n 80065c4 <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80065b0: 697b ldr r3, [r7, #20]
80065b2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80065b6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80065b8: 683b ldr r3, [r7, #0]
80065ba: 695b ldr r3, [r3, #20]
80065bc: 019b lsls r3, r3, #6
80065be: 697a ldr r2, [r7, #20]
80065c0: 4313 orrs r3, r2
80065c2: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80065c4: 687b ldr r3, [r7, #4]
80065c6: 697a ldr r2, [r7, #20]
80065c8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80065ca: 687b ldr r3, [r7, #4]
80065cc: 68fa ldr r2, [r7, #12]
80065ce: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80065d0: 683b ldr r3, [r7, #0]
80065d2: 685a ldr r2, [r3, #4]
80065d4: 687b ldr r3, [r7, #4]
80065d6: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80065d8: 687b ldr r3, [r7, #4]
80065da: 693a ldr r2, [r7, #16]
80065dc: 621a str r2, [r3, #32]
}
80065de: bf00 nop
80065e0: 371c adds r7, #28
80065e2: 46bd mov sp, r7
80065e4: bc80 pop {r7}
80065e6: 4770 bx lr
80065e8: 40012c00 .word 0x40012c00
080065ec <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80065ec: b480 push {r7}
80065ee: b087 sub sp, #28
80065f0: af00 add r7, sp, #0
80065f2: 60f8 str r0, [r7, #12]
80065f4: 60b9 str r1, [r7, #8]
80065f6: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
80065f8: 68fb ldr r3, [r7, #12]
80065fa: 6a1b ldr r3, [r3, #32]
80065fc: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
80065fe: 68fb ldr r3, [r7, #12]
8006600: 6a1b ldr r3, [r3, #32]
8006602: f023 0201 bic.w r2, r3, #1
8006606: 68fb ldr r3, [r7, #12]
8006608: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800660a: 68fb ldr r3, [r7, #12]
800660c: 699b ldr r3, [r3, #24]
800660e: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8006610: 693b ldr r3, [r7, #16]
8006612: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8006616: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8006618: 687b ldr r3, [r7, #4]
800661a: 011b lsls r3, r3, #4
800661c: 693a ldr r2, [r7, #16]
800661e: 4313 orrs r3, r2
8006620: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8006622: 697b ldr r3, [r7, #20]
8006624: f023 030a bic.w r3, r3, #10
8006628: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800662a: 697a ldr r2, [r7, #20]
800662c: 68bb ldr r3, [r7, #8]
800662e: 4313 orrs r3, r2
8006630: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8006632: 68fb ldr r3, [r7, #12]
8006634: 693a ldr r2, [r7, #16]
8006636: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8006638: 68fb ldr r3, [r7, #12]
800663a: 697a ldr r2, [r7, #20]
800663c: 621a str r2, [r3, #32]
}
800663e: bf00 nop
8006640: 371c adds r7, #28
8006642: 46bd mov sp, r7
8006644: bc80 pop {r7}
8006646: 4770 bx lr
08006648 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8006648: b480 push {r7}
800664a: b087 sub sp, #28
800664c: af00 add r7, sp, #0
800664e: 60f8 str r0, [r7, #12]
8006650: 60b9 str r1, [r7, #8]
8006652: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8006654: 68fb ldr r3, [r7, #12]
8006656: 6a1b ldr r3, [r3, #32]
8006658: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
800665a: 68fb ldr r3, [r7, #12]
800665c: 6a1b ldr r3, [r3, #32]
800665e: f023 0210 bic.w r2, r3, #16
8006662: 68fb ldr r3, [r7, #12]
8006664: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8006666: 68fb ldr r3, [r7, #12]
8006668: 699b ldr r3, [r3, #24]
800666a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800666c: 693b ldr r3, [r7, #16]
800666e: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8006672: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8006674: 687b ldr r3, [r7, #4]
8006676: 031b lsls r3, r3, #12
8006678: 693a ldr r2, [r7, #16]
800667a: 4313 orrs r3, r2
800667c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800667e: 697b ldr r3, [r7, #20]
8006680: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8006684: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8006686: 68bb ldr r3, [r7, #8]
8006688: 011b lsls r3, r3, #4
800668a: 697a ldr r2, [r7, #20]
800668c: 4313 orrs r3, r2
800668e: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8006690: 68fb ldr r3, [r7, #12]
8006692: 693a ldr r2, [r7, #16]
8006694: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8006696: 68fb ldr r3, [r7, #12]
8006698: 697a ldr r2, [r7, #20]
800669a: 621a str r2, [r3, #32]
}
800669c: bf00 nop
800669e: 371c adds r7, #28
80066a0: 46bd mov sp, r7
80066a2: bc80 pop {r7}
80066a4: 4770 bx lr
080066a6 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80066a6: b480 push {r7}
80066a8: b085 sub sp, #20
80066aa: af00 add r7, sp, #0
80066ac: 6078 str r0, [r7, #4]
80066ae: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80066b0: 687b ldr r3, [r7, #4]
80066b2: 689b ldr r3, [r3, #8]
80066b4: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80066b6: 68fb ldr r3, [r7, #12]
80066b8: f023 0370 bic.w r3, r3, #112 @ 0x70
80066bc: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80066be: 683a ldr r2, [r7, #0]
80066c0: 68fb ldr r3, [r7, #12]
80066c2: 4313 orrs r3, r2
80066c4: f043 0307 orr.w r3, r3, #7
80066c8: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80066ca: 687b ldr r3, [r7, #4]
80066cc: 68fa ldr r2, [r7, #12]
80066ce: 609a str r2, [r3, #8]
}
80066d0: bf00 nop
80066d2: 3714 adds r7, #20
80066d4: 46bd mov sp, r7
80066d6: bc80 pop {r7}
80066d8: 4770 bx lr
080066da <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
80066da: b480 push {r7}
80066dc: b087 sub sp, #28
80066de: af00 add r7, sp, #0
80066e0: 60f8 str r0, [r7, #12]
80066e2: 60b9 str r1, [r7, #8]
80066e4: 607a str r2, [r7, #4]
80066e6: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
80066e8: 68fb ldr r3, [r7, #12]
80066ea: 689b ldr r3, [r3, #8]
80066ec: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80066ee: 697b ldr r3, [r7, #20]
80066f0: f423 437f bic.w r3, r3, #65280 @ 0xff00
80066f4: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
80066f6: 683b ldr r3, [r7, #0]
80066f8: 021a lsls r2, r3, #8
80066fa: 687b ldr r3, [r7, #4]
80066fc: 431a orrs r2, r3
80066fe: 68bb ldr r3, [r7, #8]
8006700: 4313 orrs r3, r2
8006702: 697a ldr r2, [r7, #20]
8006704: 4313 orrs r3, r2
8006706: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8006708: 68fb ldr r3, [r7, #12]
800670a: 697a ldr r2, [r7, #20]
800670c: 609a str r2, [r3, #8]
}
800670e: bf00 nop
8006710: 371c adds r7, #28
8006712: 46bd mov sp, r7
8006714: bc80 pop {r7}
8006716: 4770 bx lr
08006718 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8006718: b480 push {r7}
800671a: b087 sub sp, #28
800671c: af00 add r7, sp, #0
800671e: 60f8 str r0, [r7, #12]
8006720: 60b9 str r1, [r7, #8]
8006722: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8006724: 68bb ldr r3, [r7, #8]
8006726: f003 031f and.w r3, r3, #31
800672a: 2201 movs r2, #1
800672c: fa02 f303 lsl.w r3, r2, r3
8006730: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8006732: 68fb ldr r3, [r7, #12]
8006734: 6a1a ldr r2, [r3, #32]
8006736: 697b ldr r3, [r7, #20]
8006738: 43db mvns r3, r3
800673a: 401a ands r2, r3
800673c: 68fb ldr r3, [r7, #12]
800673e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8006740: 68fb ldr r3, [r7, #12]
8006742: 6a1a ldr r2, [r3, #32]
8006744: 68bb ldr r3, [r7, #8]
8006746: f003 031f and.w r3, r3, #31
800674a: 6879 ldr r1, [r7, #4]
800674c: fa01 f303 lsl.w r3, r1, r3
8006750: 431a orrs r2, r3
8006752: 68fb ldr r3, [r7, #12]
8006754: 621a str r2, [r3, #32]
}
8006756: bf00 nop
8006758: 371c adds r7, #28
800675a: 46bd mov sp, r7
800675c: bc80 pop {r7}
800675e: 4770 bx lr
08006760 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8006760: b480 push {r7}
8006762: b085 sub sp, #20
8006764: af00 add r7, sp, #0
8006766: 6078 str r0, [r7, #4]
8006768: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800676a: 687b ldr r3, [r7, #4]
800676c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8006770: 2b01 cmp r3, #1
8006772: d101 bne.n 8006778 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8006774: 2302 movs r3, #2
8006776: e046 b.n 8006806 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8006778: 687b ldr r3, [r7, #4]
800677a: 2201 movs r2, #1
800677c: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8006780: 687b ldr r3, [r7, #4]
8006782: 2202 movs r2, #2
8006784: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8006788: 687b ldr r3, [r7, #4]
800678a: 681b ldr r3, [r3, #0]
800678c: 685b ldr r3, [r3, #4]
800678e: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8006790: 687b ldr r3, [r7, #4]
8006792: 681b ldr r3, [r3, #0]
8006794: 689b ldr r3, [r3, #8]
8006796: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8006798: 68fb ldr r3, [r7, #12]
800679a: f023 0370 bic.w r3, r3, #112 @ 0x70
800679e: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80067a0: 683b ldr r3, [r7, #0]
80067a2: 681b ldr r3, [r3, #0]
80067a4: 68fa ldr r2, [r7, #12]
80067a6: 4313 orrs r3, r2
80067a8: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80067aa: 687b ldr r3, [r7, #4]
80067ac: 681b ldr r3, [r3, #0]
80067ae: 68fa ldr r2, [r7, #12]
80067b0: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80067b2: 687b ldr r3, [r7, #4]
80067b4: 681b ldr r3, [r3, #0]
80067b6: 4a16 ldr r2, [pc, #88] @ (8006810 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
80067b8: 4293 cmp r3, r2
80067ba: d00e beq.n 80067da <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80067bc: 687b ldr r3, [r7, #4]
80067be: 681b ldr r3, [r3, #0]
80067c0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80067c4: d009 beq.n 80067da <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80067c6: 687b ldr r3, [r7, #4]
80067c8: 681b ldr r3, [r3, #0]
80067ca: 4a12 ldr r2, [pc, #72] @ (8006814 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
80067cc: 4293 cmp r3, r2
80067ce: d004 beq.n 80067da <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80067d0: 687b ldr r3, [r7, #4]
80067d2: 681b ldr r3, [r3, #0]
80067d4: 4a10 ldr r2, [pc, #64] @ (8006818 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
80067d6: 4293 cmp r3, r2
80067d8: d10c bne.n 80067f4 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
80067da: 68bb ldr r3, [r7, #8]
80067dc: f023 0380 bic.w r3, r3, #128 @ 0x80
80067e0: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
80067e2: 683b ldr r3, [r7, #0]
80067e4: 685b ldr r3, [r3, #4]
80067e6: 68ba ldr r2, [r7, #8]
80067e8: 4313 orrs r3, r2
80067ea: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80067ec: 687b ldr r3, [r7, #4]
80067ee: 681b ldr r3, [r3, #0]
80067f0: 68ba ldr r2, [r7, #8]
80067f2: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
80067f4: 687b ldr r3, [r7, #4]
80067f6: 2201 movs r2, #1
80067f8: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80067fc: 687b ldr r3, [r7, #4]
80067fe: 2200 movs r2, #0
8006800: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8006804: 2300 movs r3, #0
}
8006806: 4618 mov r0, r3
8006808: 3714 adds r7, #20
800680a: 46bd mov sp, r7
800680c: bc80 pop {r7}
800680e: 4770 bx lr
8006810: 40012c00 .word 0x40012c00
8006814: 40000400 .word 0x40000400
8006818: 40000800 .word 0x40000800
0800681c <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800681c: b580 push {r7, lr}
800681e: b082 sub sp, #8
8006820: af00 add r7, sp, #0
8006822: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8006824: 687b ldr r3, [r7, #4]
8006826: 2b00 cmp r3, #0
8006828: d101 bne.n 800682e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800682a: 2301 movs r3, #1
800682c: e042 b.n 80068b4 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
800682e: 687b ldr r3, [r7, #4]
8006830: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006834: b2db uxtb r3, r3
8006836: 2b00 cmp r3, #0
8006838: d106 bne.n 8006848 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800683a: 687b ldr r3, [r7, #4]
800683c: 2200 movs r2, #0
800683e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8006842: 6878 ldr r0, [r7, #4]
8006844: f7fb fb6a bl 8001f1c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8006848: 687b ldr r3, [r7, #4]
800684a: 2224 movs r2, #36 @ 0x24
800684c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8006850: 687b ldr r3, [r7, #4]
8006852: 681b ldr r3, [r3, #0]
8006854: 68da ldr r2, [r3, #12]
8006856: 687b ldr r3, [r7, #4]
8006858: 681b ldr r3, [r3, #0]
800685a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800685e: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8006860: 6878 ldr r0, [r7, #4]
8006862: f000 f82b bl 80068bc <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8006866: 687b ldr r3, [r7, #4]
8006868: 681b ldr r3, [r3, #0]
800686a: 691a ldr r2, [r3, #16]
800686c: 687b ldr r3, [r7, #4]
800686e: 681b ldr r3, [r3, #0]
8006870: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8006874: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8006876: 687b ldr r3, [r7, #4]
8006878: 681b ldr r3, [r3, #0]
800687a: 695a ldr r2, [r3, #20]
800687c: 687b ldr r3, [r7, #4]
800687e: 681b ldr r3, [r3, #0]
8006880: f022 022a bic.w r2, r2, #42 @ 0x2a
8006884: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8006886: 687b ldr r3, [r7, #4]
8006888: 681b ldr r3, [r3, #0]
800688a: 68da ldr r2, [r3, #12]
800688c: 687b ldr r3, [r7, #4]
800688e: 681b ldr r3, [r3, #0]
8006890: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8006894: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8006896: 687b ldr r3, [r7, #4]
8006898: 2200 movs r2, #0
800689a: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
800689c: 687b ldr r3, [r7, #4]
800689e: 2220 movs r2, #32
80068a0: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
80068a4: 687b ldr r3, [r7, #4]
80068a6: 2220 movs r2, #32
80068a8: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
80068ac: 687b ldr r3, [r7, #4]
80068ae: 2200 movs r2, #0
80068b0: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
80068b2: 2300 movs r3, #0
}
80068b4: 4618 mov r0, r3
80068b6: 3708 adds r7, #8
80068b8: 46bd mov sp, r7
80068ba: bd80 pop {r7, pc}
080068bc <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
80068bc: b580 push {r7, lr}
80068be: b084 sub sp, #16
80068c0: af00 add r7, sp, #0
80068c2: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80068c4: 687b ldr r3, [r7, #4]
80068c6: 681b ldr r3, [r3, #0]
80068c8: 691b ldr r3, [r3, #16]
80068ca: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80068ce: 687b ldr r3, [r7, #4]
80068d0: 68da ldr r2, [r3, #12]
80068d2: 687b ldr r3, [r7, #4]
80068d4: 681b ldr r3, [r3, #0]
80068d6: 430a orrs r2, r1
80068d8: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
80068da: 687b ldr r3, [r7, #4]
80068dc: 689a ldr r2, [r3, #8]
80068de: 687b ldr r3, [r7, #4]
80068e0: 691b ldr r3, [r3, #16]
80068e2: 431a orrs r2, r3
80068e4: 687b ldr r3, [r7, #4]
80068e6: 695b ldr r3, [r3, #20]
80068e8: 4313 orrs r3, r2
80068ea: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
80068ec: 687b ldr r3, [r7, #4]
80068ee: 681b ldr r3, [r3, #0]
80068f0: 68db ldr r3, [r3, #12]
80068f2: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
80068f6: f023 030c bic.w r3, r3, #12
80068fa: 687a ldr r2, [r7, #4]
80068fc: 6812 ldr r2, [r2, #0]
80068fe: 68b9 ldr r1, [r7, #8]
8006900: 430b orrs r3, r1
8006902: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8006904: 687b ldr r3, [r7, #4]
8006906: 681b ldr r3, [r3, #0]
8006908: 695b ldr r3, [r3, #20]
800690a: f423 7140 bic.w r1, r3, #768 @ 0x300
800690e: 687b ldr r3, [r7, #4]
8006910: 699a ldr r2, [r3, #24]
8006912: 687b ldr r3, [r7, #4]
8006914: 681b ldr r3, [r3, #0]
8006916: 430a orrs r2, r1
8006918: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
800691a: 687b ldr r3, [r7, #4]
800691c: 681b ldr r3, [r3, #0]
800691e: 4a2c ldr r2, [pc, #176] @ (80069d0 <UART_SetConfig+0x114>)
8006920: 4293 cmp r3, r2
8006922: d103 bne.n 800692c <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8006924: f7ff f824 bl 8005970 <HAL_RCC_GetPCLK2Freq>
8006928: 60f8 str r0, [r7, #12]
800692a: e002 b.n 8006932 <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800692c: f7ff f80c bl 8005948 <HAL_RCC_GetPCLK1Freq>
8006930: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8006932: 68fa ldr r2, [r7, #12]
8006934: 4613 mov r3, r2
8006936: 009b lsls r3, r3, #2
8006938: 4413 add r3, r2
800693a: 009a lsls r2, r3, #2
800693c: 441a add r2, r3
800693e: 687b ldr r3, [r7, #4]
8006940: 685b ldr r3, [r3, #4]
8006942: 009b lsls r3, r3, #2
8006944: fbb2 f3f3 udiv r3, r2, r3
8006948: 4a22 ldr r2, [pc, #136] @ (80069d4 <UART_SetConfig+0x118>)
800694a: fba2 2303 umull r2, r3, r2, r3
800694e: 095b lsrs r3, r3, #5
8006950: 0119 lsls r1, r3, #4
8006952: 68fa ldr r2, [r7, #12]
8006954: 4613 mov r3, r2
8006956: 009b lsls r3, r3, #2
8006958: 4413 add r3, r2
800695a: 009a lsls r2, r3, #2
800695c: 441a add r2, r3
800695e: 687b ldr r3, [r7, #4]
8006960: 685b ldr r3, [r3, #4]
8006962: 009b lsls r3, r3, #2
8006964: fbb2 f2f3 udiv r2, r2, r3
8006968: 4b1a ldr r3, [pc, #104] @ (80069d4 <UART_SetConfig+0x118>)
800696a: fba3 0302 umull r0, r3, r3, r2
800696e: 095b lsrs r3, r3, #5
8006970: 2064 movs r0, #100 @ 0x64
8006972: fb00 f303 mul.w r3, r0, r3
8006976: 1ad3 subs r3, r2, r3
8006978: 011b lsls r3, r3, #4
800697a: 3332 adds r3, #50 @ 0x32
800697c: 4a15 ldr r2, [pc, #84] @ (80069d4 <UART_SetConfig+0x118>)
800697e: fba2 2303 umull r2, r3, r2, r3
8006982: 095b lsrs r3, r3, #5
8006984: f003 03f0 and.w r3, r3, #240 @ 0xf0
8006988: 4419 add r1, r3
800698a: 68fa ldr r2, [r7, #12]
800698c: 4613 mov r3, r2
800698e: 009b lsls r3, r3, #2
8006990: 4413 add r3, r2
8006992: 009a lsls r2, r3, #2
8006994: 441a add r2, r3
8006996: 687b ldr r3, [r7, #4]
8006998: 685b ldr r3, [r3, #4]
800699a: 009b lsls r3, r3, #2
800699c: fbb2 f2f3 udiv r2, r2, r3
80069a0: 4b0c ldr r3, [pc, #48] @ (80069d4 <UART_SetConfig+0x118>)
80069a2: fba3 0302 umull r0, r3, r3, r2
80069a6: 095b lsrs r3, r3, #5
80069a8: 2064 movs r0, #100 @ 0x64
80069aa: fb00 f303 mul.w r3, r0, r3
80069ae: 1ad3 subs r3, r2, r3
80069b0: 011b lsls r3, r3, #4
80069b2: 3332 adds r3, #50 @ 0x32
80069b4: 4a07 ldr r2, [pc, #28] @ (80069d4 <UART_SetConfig+0x118>)
80069b6: fba2 2303 umull r2, r3, r2, r3
80069ba: 095b lsrs r3, r3, #5
80069bc: f003 020f and.w r2, r3, #15
80069c0: 687b ldr r3, [r7, #4]
80069c2: 681b ldr r3, [r3, #0]
80069c4: 440a add r2, r1
80069c6: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
80069c8: bf00 nop
80069ca: 3710 adds r7, #16
80069cc: 46bd mov sp, r7
80069ce: bd80 pop {r7, pc}
80069d0: 40013800 .word 0x40013800
80069d4: 51eb851f .word 0x51eb851f
080069d8 <USB_CoreInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
80069d8: b480 push {r7}
80069da: b085 sub sp, #20
80069dc: af00 add r7, sp, #0
80069de: 60f8 str r0, [r7, #12]
80069e0: 4638 mov r0, r7
80069e2: e880 000e stmia.w r0, {r1, r2, r3}
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
80069e6: 2300 movs r3, #0
}
80069e8: 4618 mov r0, r3
80069ea: 3714 adds r7, #20
80069ec: 46bd mov sp, r7
80069ee: bc80 pop {r7}
80069f0: 4770 bx lr
080069f2 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
80069f2: b480 push {r7}
80069f4: b085 sub sp, #20
80069f6: af00 add r7, sp, #0
80069f8: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
80069fa: 687b ldr r3, [r7, #4]
80069fc: 2200 movs r2, #0
80069fe: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8006a02: f44f 433f mov.w r3, #48896 @ 0xbf00
8006a06: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR = (uint16_t)winterruptmask;
8006a08: 68fb ldr r3, [r7, #12]
8006a0a: b29a uxth r2, r3
8006a0c: 687b ldr r3, [r7, #4]
8006a0e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8006a12: 2300 movs r3, #0
}
8006a14: 4618 mov r0, r3
8006a16: 3714 adds r7, #20
8006a18: 46bd mov sp, r7
8006a1a: bc80 pop {r7}
8006a1c: 4770 bx lr
08006a1e <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
8006a1e: b480 push {r7}
8006a20: b085 sub sp, #20
8006a22: af00 add r7, sp, #0
8006a24: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8006a26: f44f 433f mov.w r3, #48896 @ 0xbf00
8006a2a: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= (uint16_t)(~winterruptmask);
8006a2c: 687b ldr r3, [r7, #4]
8006a2e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8006a32: b29a uxth r2, r3
8006a34: 68fb ldr r3, [r7, #12]
8006a36: b29b uxth r3, r3
8006a38: 43db mvns r3, r3
8006a3a: b29b uxth r3, r3
8006a3c: 4013 ands r3, r2
8006a3e: b29a uxth r2, r3
8006a40: 687b ldr r3, [r7, #4]
8006a42: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8006a46: 2300 movs r3, #0
}
8006a48: 4618 mov r0, r3
8006a4a: 3714 adds r7, #20
8006a4c: 46bd mov sp, r7
8006a4e: bc80 pop {r7}
8006a50: 4770 bx lr
08006a52 <USB_SetCurrentMode>:
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
8006a52: b480 push {r7}
8006a54: b083 sub sp, #12
8006a56: af00 add r7, sp, #0
8006a58: 6078 str r0, [r7, #4]
8006a5a: 460b mov r3, r1
8006a5c: 70fb strb r3, [r7, #3]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8006a5e: 2300 movs r3, #0
}
8006a60: 4618 mov r0, r3
8006a62: 370c adds r7, #12
8006a64: 46bd mov sp, r7
8006a66: bc80 pop {r7}
8006a68: 4770 bx lr
08006a6a <USB_DevInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8006a6a: b480 push {r7}
8006a6c: b085 sub sp, #20
8006a6e: af00 add r7, sp, #0
8006a70: 60f8 str r0, [r7, #12]
8006a72: 4638 mov r0, r7
8006a74: e880 000e stmia.w r0, {r1, r2, r3}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
8006a78: 68fb ldr r3, [r7, #12]
8006a7a: 2201 movs r2, #1
8006a7c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
8006a80: 68fb ldr r3, [r7, #12]
8006a82: 2200 movs r2, #0
8006a84: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* Clear pending interrupts */
USBx->ISTR = 0U;
8006a88: 68fb ldr r3, [r7, #12]
8006a8a: 2200 movs r2, #0
8006a8c: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
8006a90: 68fb ldr r3, [r7, #12]
8006a92: 2200 movs r2, #0
8006a94: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
return HAL_OK;
8006a98: 2300 movs r3, #0
}
8006a9a: 4618 mov r0, r3
8006a9c: 3714 adds r7, #20
8006a9e: 46bd mov sp, r7
8006aa0: bc80 pop {r7}
8006aa2: 4770 bx lr
08006aa4 <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8006aa4: b480 push {r7}
8006aa6: b09d sub sp, #116 @ 0x74
8006aa8: af00 add r7, sp, #0
8006aaa: 6078 str r0, [r7, #4]
8006aac: 6039 str r1, [r7, #0]
HAL_StatusTypeDef ret = HAL_OK;
8006aae: 2300 movs r3, #0
8006ab0: f887 306f strb.w r3, [r7, #111] @ 0x6f
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
8006ab4: 687a ldr r2, [r7, #4]
8006ab6: 683b ldr r3, [r7, #0]
8006ab8: 781b ldrb r3, [r3, #0]
8006aba: 009b lsls r3, r3, #2
8006abc: 4413 add r3, r2
8006abe: 881b ldrh r3, [r3, #0]
8006ac0: b29b uxth r3, r3
8006ac2: f423 43ec bic.w r3, r3, #30208 @ 0x7600
8006ac6: f023 0370 bic.w r3, r3, #112 @ 0x70
8006aca: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
/* initialize Endpoint */
switch (ep->type)
8006ace: 683b ldr r3, [r7, #0]
8006ad0: 78db ldrb r3, [r3, #3]
8006ad2: 2b03 cmp r3, #3
8006ad4: d81f bhi.n 8006b16 <USB_ActivateEndpoint+0x72>
8006ad6: a201 add r2, pc, #4 @ (adr r2, 8006adc <USB_ActivateEndpoint+0x38>)
8006ad8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006adc: 08006aed .word 0x08006aed
8006ae0: 08006b09 .word 0x08006b09
8006ae4: 08006b1f .word 0x08006b1f
8006ae8: 08006afb .word 0x08006afb
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
8006aec: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006af0: f443 7300 orr.w r3, r3, #512 @ 0x200
8006af4: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8006af8: e012 b.n 8006b20 <USB_ActivateEndpoint+0x7c>
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
8006afa: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006afe: f443 63c0 orr.w r3, r3, #1536 @ 0x600
8006b02: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8006b06: e00b b.n 8006b20 <USB_ActivateEndpoint+0x7c>
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
8006b08: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006b0c: f443 6380 orr.w r3, r3, #1024 @ 0x400
8006b10: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8006b14: e004 b.n 8006b20 <USB_ActivateEndpoint+0x7c>
default:
ret = HAL_ERROR;
8006b16: 2301 movs r3, #1
8006b18: f887 306f strb.w r3, [r7, #111] @ 0x6f
break;
8006b1c: e000 b.n 8006b20 <USB_ActivateEndpoint+0x7c>
break;
8006b1e: bf00 nop
}
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
8006b20: 687a ldr r2, [r7, #4]
8006b22: 683b ldr r3, [r7, #0]
8006b24: 781b ldrb r3, [r3, #0]
8006b26: 009b lsls r3, r3, #2
8006b28: 441a add r2, r3
8006b2a: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8006b2e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006b32: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006b36: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006b3a: f043 0380 orr.w r3, r3, #128 @ 0x80
8006b3e: b29b uxth r3, r3
8006b40: 8013 strh r3, [r2, #0]
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
8006b42: 687a ldr r2, [r7, #4]
8006b44: 683b ldr r3, [r7, #0]
8006b46: 781b ldrb r3, [r3, #0]
8006b48: 009b lsls r3, r3, #2
8006b4a: 4413 add r3, r2
8006b4c: 881b ldrh r3, [r3, #0]
8006b4e: b29b uxth r3, r3
8006b50: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006b54: f023 0370 bic.w r3, r3, #112 @ 0x70
8006b58: b29b uxth r3, r3
8006b5a: 683a ldr r2, [r7, #0]
8006b5c: 7812 ldrb r2, [r2, #0]
8006b5e: 4313 orrs r3, r2
8006b60: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
8006b64: 687a ldr r2, [r7, #4]
8006b66: 683b ldr r3, [r7, #0]
8006b68: 781b ldrb r3, [r3, #0]
8006b6a: 009b lsls r3, r3, #2
8006b6c: 441a add r2, r3
8006b6e: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
8006b72: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006b76: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006b7a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006b7e: f043 0380 orr.w r3, r3, #128 @ 0x80
8006b82: b29b uxth r3, r3
8006b84: 8013 strh r3, [r2, #0]
if (ep->doublebuffer == 0U)
8006b86: 683b ldr r3, [r7, #0]
8006b88: 7b1b ldrb r3, [r3, #12]
8006b8a: 2b00 cmp r3, #0
8006b8c: f040 8178 bne.w 8006e80 <USB_ActivateEndpoint+0x3dc>
{
if (ep->is_in != 0U)
8006b90: 683b ldr r3, [r7, #0]
8006b92: 785b ldrb r3, [r3, #1]
8006b94: 2b00 cmp r3, #0
8006b96: f000 8084 beq.w 8006ca2 <USB_ActivateEndpoint+0x1fe>
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
8006b9a: 687b ldr r3, [r7, #4]
8006b9c: 61bb str r3, [r7, #24]
8006b9e: 687b ldr r3, [r7, #4]
8006ba0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006ba4: b29b uxth r3, r3
8006ba6: 461a mov r2, r3
8006ba8: 69bb ldr r3, [r7, #24]
8006baa: 4413 add r3, r2
8006bac: 61bb str r3, [r7, #24]
8006bae: 683b ldr r3, [r7, #0]
8006bb0: 781b ldrb r3, [r3, #0]
8006bb2: 011a lsls r2, r3, #4
8006bb4: 69bb ldr r3, [r7, #24]
8006bb6: 4413 add r3, r2
8006bb8: f503 6380 add.w r3, r3, #1024 @ 0x400
8006bbc: 617b str r3, [r7, #20]
8006bbe: 683b ldr r3, [r7, #0]
8006bc0: 88db ldrh r3, [r3, #6]
8006bc2: 085b lsrs r3, r3, #1
8006bc4: b29b uxth r3, r3
8006bc6: 005b lsls r3, r3, #1
8006bc8: b29a uxth r2, r3
8006bca: 697b ldr r3, [r7, #20]
8006bcc: 801a strh r2, [r3, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8006bce: 687a ldr r2, [r7, #4]
8006bd0: 683b ldr r3, [r7, #0]
8006bd2: 781b ldrb r3, [r3, #0]
8006bd4: 009b lsls r3, r3, #2
8006bd6: 4413 add r3, r2
8006bd8: 881b ldrh r3, [r3, #0]
8006bda: 827b strh r3, [r7, #18]
8006bdc: 8a7b ldrh r3, [r7, #18]
8006bde: f003 0340 and.w r3, r3, #64 @ 0x40
8006be2: 2b00 cmp r3, #0
8006be4: d01b beq.n 8006c1e <USB_ActivateEndpoint+0x17a>
8006be6: 687a ldr r2, [r7, #4]
8006be8: 683b ldr r3, [r7, #0]
8006bea: 781b ldrb r3, [r3, #0]
8006bec: 009b lsls r3, r3, #2
8006bee: 4413 add r3, r2
8006bf0: 881b ldrh r3, [r3, #0]
8006bf2: b29b uxth r3, r3
8006bf4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006bf8: f023 0370 bic.w r3, r3, #112 @ 0x70
8006bfc: 823b strh r3, [r7, #16]
8006bfe: 687a ldr r2, [r7, #4]
8006c00: 683b ldr r3, [r7, #0]
8006c02: 781b ldrb r3, [r3, #0]
8006c04: 009b lsls r3, r3, #2
8006c06: 441a add r2, r3
8006c08: 8a3b ldrh r3, [r7, #16]
8006c0a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006c0e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006c12: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006c16: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8006c1a: b29b uxth r3, r3
8006c1c: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8006c1e: 683b ldr r3, [r7, #0]
8006c20: 78db ldrb r3, [r3, #3]
8006c22: 2b01 cmp r3, #1
8006c24: d020 beq.n 8006c68 <USB_ActivateEndpoint+0x1c4>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8006c26: 687a ldr r2, [r7, #4]
8006c28: 683b ldr r3, [r7, #0]
8006c2a: 781b ldrb r3, [r3, #0]
8006c2c: 009b lsls r3, r3, #2
8006c2e: 4413 add r3, r2
8006c30: 881b ldrh r3, [r3, #0]
8006c32: b29b uxth r3, r3
8006c34: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006c38: f023 0340 bic.w r3, r3, #64 @ 0x40
8006c3c: 81bb strh r3, [r7, #12]
8006c3e: 89bb ldrh r3, [r7, #12]
8006c40: f083 0320 eor.w r3, r3, #32
8006c44: 81bb strh r3, [r7, #12]
8006c46: 687a ldr r2, [r7, #4]
8006c48: 683b ldr r3, [r7, #0]
8006c4a: 781b ldrb r3, [r3, #0]
8006c4c: 009b lsls r3, r3, #2
8006c4e: 441a add r2, r3
8006c50: 89bb ldrh r3, [r7, #12]
8006c52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006c56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006c5a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006c5e: f043 0380 orr.w r3, r3, #128 @ 0x80
8006c62: b29b uxth r3, r3
8006c64: 8013 strh r3, [r2, #0]
8006c66: e2d5 b.n 8007214 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8006c68: 687a ldr r2, [r7, #4]
8006c6a: 683b ldr r3, [r7, #0]
8006c6c: 781b ldrb r3, [r3, #0]
8006c6e: 009b lsls r3, r3, #2
8006c70: 4413 add r3, r2
8006c72: 881b ldrh r3, [r3, #0]
8006c74: b29b uxth r3, r3
8006c76: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006c7a: f023 0340 bic.w r3, r3, #64 @ 0x40
8006c7e: 81fb strh r3, [r7, #14]
8006c80: 687a ldr r2, [r7, #4]
8006c82: 683b ldr r3, [r7, #0]
8006c84: 781b ldrb r3, [r3, #0]
8006c86: 009b lsls r3, r3, #2
8006c88: 441a add r2, r3
8006c8a: 89fb ldrh r3, [r7, #14]
8006c8c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006c90: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006c94: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006c98: f043 0380 orr.w r3, r3, #128 @ 0x80
8006c9c: b29b uxth r3, r3
8006c9e: 8013 strh r3, [r2, #0]
8006ca0: e2b8 b.n 8007214 <USB_ActivateEndpoint+0x770>
}
}
else
{
/* Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
8006ca2: 687b ldr r3, [r7, #4]
8006ca4: 633b str r3, [r7, #48] @ 0x30
8006ca6: 687b ldr r3, [r7, #4]
8006ca8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006cac: b29b uxth r3, r3
8006cae: 461a mov r2, r3
8006cb0: 6b3b ldr r3, [r7, #48] @ 0x30
8006cb2: 4413 add r3, r2
8006cb4: 633b str r3, [r7, #48] @ 0x30
8006cb6: 683b ldr r3, [r7, #0]
8006cb8: 781b ldrb r3, [r3, #0]
8006cba: 011a lsls r2, r3, #4
8006cbc: 6b3b ldr r3, [r7, #48] @ 0x30
8006cbe: 4413 add r3, r2
8006cc0: f503 6381 add.w r3, r3, #1032 @ 0x408
8006cc4: 62fb str r3, [r7, #44] @ 0x2c
8006cc6: 683b ldr r3, [r7, #0]
8006cc8: 88db ldrh r3, [r3, #6]
8006cca: 085b lsrs r3, r3, #1
8006ccc: b29b uxth r3, r3
8006cce: 005b lsls r3, r3, #1
8006cd0: b29a uxth r2, r3
8006cd2: 6afb ldr r3, [r7, #44] @ 0x2c
8006cd4: 801a strh r2, [r3, #0]
/* Set the endpoint Receive buffer counter */
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
8006cd6: 687b ldr r3, [r7, #4]
8006cd8: 62bb str r3, [r7, #40] @ 0x28
8006cda: 687b ldr r3, [r7, #4]
8006cdc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006ce0: b29b uxth r3, r3
8006ce2: 461a mov r2, r3
8006ce4: 6abb ldr r3, [r7, #40] @ 0x28
8006ce6: 4413 add r3, r2
8006ce8: 62bb str r3, [r7, #40] @ 0x28
8006cea: 683b ldr r3, [r7, #0]
8006cec: 781b ldrb r3, [r3, #0]
8006cee: 011a lsls r2, r3, #4
8006cf0: 6abb ldr r3, [r7, #40] @ 0x28
8006cf2: 4413 add r3, r2
8006cf4: f203 430c addw r3, r3, #1036 @ 0x40c
8006cf8: 627b str r3, [r7, #36] @ 0x24
8006cfa: 6a7b ldr r3, [r7, #36] @ 0x24
8006cfc: 881b ldrh r3, [r3, #0]
8006cfe: b29b uxth r3, r3
8006d00: f3c3 0309 ubfx r3, r3, #0, #10
8006d04: b29a uxth r2, r3
8006d06: 6a7b ldr r3, [r7, #36] @ 0x24
8006d08: 801a strh r2, [r3, #0]
8006d0a: 683b ldr r3, [r7, #0]
8006d0c: 691b ldr r3, [r3, #16]
8006d0e: 2b3e cmp r3, #62 @ 0x3e
8006d10: d91d bls.n 8006d4e <USB_ActivateEndpoint+0x2aa>
8006d12: 683b ldr r3, [r7, #0]
8006d14: 691b ldr r3, [r3, #16]
8006d16: 095b lsrs r3, r3, #5
8006d18: 66bb str r3, [r7, #104] @ 0x68
8006d1a: 683b ldr r3, [r7, #0]
8006d1c: 691b ldr r3, [r3, #16]
8006d1e: f003 031f and.w r3, r3, #31
8006d22: 2b00 cmp r3, #0
8006d24: d102 bne.n 8006d2c <USB_ActivateEndpoint+0x288>
8006d26: 6ebb ldr r3, [r7, #104] @ 0x68
8006d28: 3b01 subs r3, #1
8006d2a: 66bb str r3, [r7, #104] @ 0x68
8006d2c: 6a7b ldr r3, [r7, #36] @ 0x24
8006d2e: 881b ldrh r3, [r3, #0]
8006d30: b29a uxth r2, r3
8006d32: 6ebb ldr r3, [r7, #104] @ 0x68
8006d34: b29b uxth r3, r3
8006d36: 029b lsls r3, r3, #10
8006d38: b29b uxth r3, r3
8006d3a: 4313 orrs r3, r2
8006d3c: b29b uxth r3, r3
8006d3e: ea6f 4343 mvn.w r3, r3, lsl #17
8006d42: ea6f 4353 mvn.w r3, r3, lsr #17
8006d46: b29a uxth r2, r3
8006d48: 6a7b ldr r3, [r7, #36] @ 0x24
8006d4a: 801a strh r2, [r3, #0]
8006d4c: e026 b.n 8006d9c <USB_ActivateEndpoint+0x2f8>
8006d4e: 683b ldr r3, [r7, #0]
8006d50: 691b ldr r3, [r3, #16]
8006d52: 2b00 cmp r3, #0
8006d54: d10a bne.n 8006d6c <USB_ActivateEndpoint+0x2c8>
8006d56: 6a7b ldr r3, [r7, #36] @ 0x24
8006d58: 881b ldrh r3, [r3, #0]
8006d5a: b29b uxth r3, r3
8006d5c: ea6f 4343 mvn.w r3, r3, lsl #17
8006d60: ea6f 4353 mvn.w r3, r3, lsr #17
8006d64: b29a uxth r2, r3
8006d66: 6a7b ldr r3, [r7, #36] @ 0x24
8006d68: 801a strh r2, [r3, #0]
8006d6a: e017 b.n 8006d9c <USB_ActivateEndpoint+0x2f8>
8006d6c: 683b ldr r3, [r7, #0]
8006d6e: 691b ldr r3, [r3, #16]
8006d70: 085b lsrs r3, r3, #1
8006d72: 66bb str r3, [r7, #104] @ 0x68
8006d74: 683b ldr r3, [r7, #0]
8006d76: 691b ldr r3, [r3, #16]
8006d78: f003 0301 and.w r3, r3, #1
8006d7c: 2b00 cmp r3, #0
8006d7e: d002 beq.n 8006d86 <USB_ActivateEndpoint+0x2e2>
8006d80: 6ebb ldr r3, [r7, #104] @ 0x68
8006d82: 3301 adds r3, #1
8006d84: 66bb str r3, [r7, #104] @ 0x68
8006d86: 6a7b ldr r3, [r7, #36] @ 0x24
8006d88: 881b ldrh r3, [r3, #0]
8006d8a: b29a uxth r2, r3
8006d8c: 6ebb ldr r3, [r7, #104] @ 0x68
8006d8e: b29b uxth r3, r3
8006d90: 029b lsls r3, r3, #10
8006d92: b29b uxth r3, r3
8006d94: 4313 orrs r3, r2
8006d96: b29a uxth r2, r3
8006d98: 6a7b ldr r3, [r7, #36] @ 0x24
8006d9a: 801a strh r2, [r3, #0]
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8006d9c: 687a ldr r2, [r7, #4]
8006d9e: 683b ldr r3, [r7, #0]
8006da0: 781b ldrb r3, [r3, #0]
8006da2: 009b lsls r3, r3, #2
8006da4: 4413 add r3, r2
8006da6: 881b ldrh r3, [r3, #0]
8006da8: 847b strh r3, [r7, #34] @ 0x22
8006daa: 8c7b ldrh r3, [r7, #34] @ 0x22
8006dac: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006db0: 2b00 cmp r3, #0
8006db2: d01b beq.n 8006dec <USB_ActivateEndpoint+0x348>
8006db4: 687a ldr r2, [r7, #4]
8006db6: 683b ldr r3, [r7, #0]
8006db8: 781b ldrb r3, [r3, #0]
8006dba: 009b lsls r3, r3, #2
8006dbc: 4413 add r3, r2
8006dbe: 881b ldrh r3, [r3, #0]
8006dc0: b29b uxth r3, r3
8006dc2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006dc6: f023 0370 bic.w r3, r3, #112 @ 0x70
8006dca: 843b strh r3, [r7, #32]
8006dcc: 687a ldr r2, [r7, #4]
8006dce: 683b ldr r3, [r7, #0]
8006dd0: 781b ldrb r3, [r3, #0]
8006dd2: 009b lsls r3, r3, #2
8006dd4: 441a add r2, r3
8006dd6: 8c3b ldrh r3, [r7, #32]
8006dd8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006ddc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006de0: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006de4: f043 0380 orr.w r3, r3, #128 @ 0x80
8006de8: b29b uxth r3, r3
8006dea: 8013 strh r3, [r2, #0]
if (ep->num == 0U)
8006dec: 683b ldr r3, [r7, #0]
8006dee: 781b ldrb r3, [r3, #0]
8006df0: 2b00 cmp r3, #0
8006df2: d124 bne.n 8006e3e <USB_ActivateEndpoint+0x39a>
{
/* Configure VALID status for EP0 */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8006df4: 687a ldr r2, [r7, #4]
8006df6: 683b ldr r3, [r7, #0]
8006df8: 781b ldrb r3, [r3, #0]
8006dfa: 009b lsls r3, r3, #2
8006dfc: 4413 add r3, r2
8006dfe: 881b ldrh r3, [r3, #0]
8006e00: b29b uxth r3, r3
8006e02: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006e06: f023 0370 bic.w r3, r3, #112 @ 0x70
8006e0a: 83bb strh r3, [r7, #28]
8006e0c: 8bbb ldrh r3, [r7, #28]
8006e0e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8006e12: 83bb strh r3, [r7, #28]
8006e14: 8bbb ldrh r3, [r7, #28]
8006e16: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8006e1a: 83bb strh r3, [r7, #28]
8006e1c: 687a ldr r2, [r7, #4]
8006e1e: 683b ldr r3, [r7, #0]
8006e20: 781b ldrb r3, [r3, #0]
8006e22: 009b lsls r3, r3, #2
8006e24: 441a add r2, r3
8006e26: 8bbb ldrh r3, [r7, #28]
8006e28: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006e2c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006e30: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006e34: f043 0380 orr.w r3, r3, #128 @ 0x80
8006e38: b29b uxth r3, r3
8006e3a: 8013 strh r3, [r2, #0]
8006e3c: e1ea b.n 8007214 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure NAK status for OUT Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
8006e3e: 687a ldr r2, [r7, #4]
8006e40: 683b ldr r3, [r7, #0]
8006e42: 781b ldrb r3, [r3, #0]
8006e44: 009b lsls r3, r3, #2
8006e46: 4413 add r3, r2
8006e48: 881b ldrh r3, [r3, #0]
8006e4a: b29b uxth r3, r3
8006e4c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006e50: f023 0370 bic.w r3, r3, #112 @ 0x70
8006e54: 83fb strh r3, [r7, #30]
8006e56: 8bfb ldrh r3, [r7, #30]
8006e58: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8006e5c: 83fb strh r3, [r7, #30]
8006e5e: 687a ldr r2, [r7, #4]
8006e60: 683b ldr r3, [r7, #0]
8006e62: 781b ldrb r3, [r3, #0]
8006e64: 009b lsls r3, r3, #2
8006e66: 441a add r2, r3
8006e68: 8bfb ldrh r3, [r7, #30]
8006e6a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006e6e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006e72: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006e76: f043 0380 orr.w r3, r3, #128 @ 0x80
8006e7a: b29b uxth r3, r3
8006e7c: 8013 strh r3, [r2, #0]
8006e7e: e1c9 b.n 8007214 <USB_ActivateEndpoint+0x770>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->type == EP_TYPE_BULK)
8006e80: 683b ldr r3, [r7, #0]
8006e82: 78db ldrb r3, [r3, #3]
8006e84: 2b02 cmp r3, #2
8006e86: d11e bne.n 8006ec6 <USB_ActivateEndpoint+0x422>
{
/* Set bulk endpoint as double buffered */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
8006e88: 687a ldr r2, [r7, #4]
8006e8a: 683b ldr r3, [r7, #0]
8006e8c: 781b ldrb r3, [r3, #0]
8006e8e: 009b lsls r3, r3, #2
8006e90: 4413 add r3, r2
8006e92: 881b ldrh r3, [r3, #0]
8006e94: b29b uxth r3, r3
8006e96: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006e9a: f023 0370 bic.w r3, r3, #112 @ 0x70
8006e9e: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8006ea2: 687a ldr r2, [r7, #4]
8006ea4: 683b ldr r3, [r7, #0]
8006ea6: 781b ldrb r3, [r3, #0]
8006ea8: 009b lsls r3, r3, #2
8006eaa: 441a add r2, r3
8006eac: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
8006eb0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006eb4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006eb8: f443 4301 orr.w r3, r3, #33024 @ 0x8100
8006ebc: f043 0380 orr.w r3, r3, #128 @ 0x80
8006ec0: b29b uxth r3, r3
8006ec2: 8013 strh r3, [r2, #0]
8006ec4: e01d b.n 8006f02 <USB_ActivateEndpoint+0x45e>
}
else
{
/* Set the ISOC endpoint in double buffer mode */
PCD_CLEAR_EP_KIND(USBx, ep->num);
8006ec6: 687a ldr r2, [r7, #4]
8006ec8: 683b ldr r3, [r7, #0]
8006eca: 781b ldrb r3, [r3, #0]
8006ecc: 009b lsls r3, r3, #2
8006ece: 4413 add r3, r2
8006ed0: 881b ldrh r3, [r3, #0]
8006ed2: b29b uxth r3, r3
8006ed4: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8006ed8: f023 0370 bic.w r3, r3, #112 @ 0x70
8006edc: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
8006ee0: 687a ldr r2, [r7, #4]
8006ee2: 683b ldr r3, [r7, #0]
8006ee4: 781b ldrb r3, [r3, #0]
8006ee6: 009b lsls r3, r3, #2
8006ee8: 441a add r2, r3
8006eea: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
8006eee: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006ef2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006ef6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006efa: f043 0380 orr.w r3, r3, #128 @ 0x80
8006efe: b29b uxth r3, r3
8006f00: 8013 strh r3, [r2, #0]
}
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
8006f02: 687b ldr r3, [r7, #4]
8006f04: 65fb str r3, [r7, #92] @ 0x5c
8006f06: 687b ldr r3, [r7, #4]
8006f08: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006f0c: b29b uxth r3, r3
8006f0e: 461a mov r2, r3
8006f10: 6dfb ldr r3, [r7, #92] @ 0x5c
8006f12: 4413 add r3, r2
8006f14: 65fb str r3, [r7, #92] @ 0x5c
8006f16: 683b ldr r3, [r7, #0]
8006f18: 781b ldrb r3, [r3, #0]
8006f1a: 011a lsls r2, r3, #4
8006f1c: 6dfb ldr r3, [r7, #92] @ 0x5c
8006f1e: 4413 add r3, r2
8006f20: f503 6380 add.w r3, r3, #1024 @ 0x400
8006f24: 65bb str r3, [r7, #88] @ 0x58
8006f26: 683b ldr r3, [r7, #0]
8006f28: 891b ldrh r3, [r3, #8]
8006f2a: 085b lsrs r3, r3, #1
8006f2c: b29b uxth r3, r3
8006f2e: 005b lsls r3, r3, #1
8006f30: b29a uxth r2, r3
8006f32: 6dbb ldr r3, [r7, #88] @ 0x58
8006f34: 801a strh r2, [r3, #0]
8006f36: 687b ldr r3, [r7, #4]
8006f38: 657b str r3, [r7, #84] @ 0x54
8006f3a: 687b ldr r3, [r7, #4]
8006f3c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006f40: b29b uxth r3, r3
8006f42: 461a mov r2, r3
8006f44: 6d7b ldr r3, [r7, #84] @ 0x54
8006f46: 4413 add r3, r2
8006f48: 657b str r3, [r7, #84] @ 0x54
8006f4a: 683b ldr r3, [r7, #0]
8006f4c: 781b ldrb r3, [r3, #0]
8006f4e: 011a lsls r2, r3, #4
8006f50: 6d7b ldr r3, [r7, #84] @ 0x54
8006f52: 4413 add r3, r2
8006f54: f503 6381 add.w r3, r3, #1032 @ 0x408
8006f58: 653b str r3, [r7, #80] @ 0x50
8006f5a: 683b ldr r3, [r7, #0]
8006f5c: 895b ldrh r3, [r3, #10]
8006f5e: 085b lsrs r3, r3, #1
8006f60: b29b uxth r3, r3
8006f62: 005b lsls r3, r3, #1
8006f64: b29a uxth r2, r3
8006f66: 6d3b ldr r3, [r7, #80] @ 0x50
8006f68: 801a strh r2, [r3, #0]
if (ep->is_in == 0U)
8006f6a: 683b ldr r3, [r7, #0]
8006f6c: 785b ldrb r3, [r3, #1]
8006f6e: 2b00 cmp r3, #0
8006f70: f040 8093 bne.w 800709a <USB_ActivateEndpoint+0x5f6>
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8006f74: 687a ldr r2, [r7, #4]
8006f76: 683b ldr r3, [r7, #0]
8006f78: 781b ldrb r3, [r3, #0]
8006f7a: 009b lsls r3, r3, #2
8006f7c: 4413 add r3, r2
8006f7e: 881b ldrh r3, [r3, #0]
8006f80: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
8006f84: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8006f88: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006f8c: 2b00 cmp r3, #0
8006f8e: d01b beq.n 8006fc8 <USB_ActivateEndpoint+0x524>
8006f90: 687a ldr r2, [r7, #4]
8006f92: 683b ldr r3, [r7, #0]
8006f94: 781b ldrb r3, [r3, #0]
8006f96: 009b lsls r3, r3, #2
8006f98: 4413 add r3, r2
8006f9a: 881b ldrh r3, [r3, #0]
8006f9c: b29b uxth r3, r3
8006f9e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006fa2: f023 0370 bic.w r3, r3, #112 @ 0x70
8006fa6: 87fb strh r3, [r7, #62] @ 0x3e
8006fa8: 687a ldr r2, [r7, #4]
8006faa: 683b ldr r3, [r7, #0]
8006fac: 781b ldrb r3, [r3, #0]
8006fae: 009b lsls r3, r3, #2
8006fb0: 441a add r2, r3
8006fb2: 8ffb ldrh r3, [r7, #62] @ 0x3e
8006fb4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006fb8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006fbc: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006fc0: f043 0380 orr.w r3, r3, #128 @ 0x80
8006fc4: b29b uxth r3, r3
8006fc6: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8006fc8: 687a ldr r2, [r7, #4]
8006fca: 683b ldr r3, [r7, #0]
8006fcc: 781b ldrb r3, [r3, #0]
8006fce: 009b lsls r3, r3, #2
8006fd0: 4413 add r3, r2
8006fd2: 881b ldrh r3, [r3, #0]
8006fd4: 87bb strh r3, [r7, #60] @ 0x3c
8006fd6: 8fbb ldrh r3, [r7, #60] @ 0x3c
8006fd8: f003 0340 and.w r3, r3, #64 @ 0x40
8006fdc: 2b00 cmp r3, #0
8006fde: d01b beq.n 8007018 <USB_ActivateEndpoint+0x574>
8006fe0: 687a ldr r2, [r7, #4]
8006fe2: 683b ldr r3, [r7, #0]
8006fe4: 781b ldrb r3, [r3, #0]
8006fe6: 009b lsls r3, r3, #2
8006fe8: 4413 add r3, r2
8006fea: 881b ldrh r3, [r3, #0]
8006fec: b29b uxth r3, r3
8006fee: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006ff2: f023 0370 bic.w r3, r3, #112 @ 0x70
8006ff6: 877b strh r3, [r7, #58] @ 0x3a
8006ff8: 687a ldr r2, [r7, #4]
8006ffa: 683b ldr r3, [r7, #0]
8006ffc: 781b ldrb r3, [r3, #0]
8006ffe: 009b lsls r3, r3, #2
8007000: 441a add r2, r3
8007002: 8f7b ldrh r3, [r7, #58] @ 0x3a
8007004: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007008: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800700c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007010: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007014: b29b uxth r3, r3
8007016: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8007018: 687a ldr r2, [r7, #4]
800701a: 683b ldr r3, [r7, #0]
800701c: 781b ldrb r3, [r3, #0]
800701e: 009b lsls r3, r3, #2
8007020: 4413 add r3, r2
8007022: 881b ldrh r3, [r3, #0]
8007024: b29b uxth r3, r3
8007026: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800702a: f023 0370 bic.w r3, r3, #112 @ 0x70
800702e: 873b strh r3, [r7, #56] @ 0x38
8007030: 8f3b ldrh r3, [r7, #56] @ 0x38
8007032: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8007036: 873b strh r3, [r7, #56] @ 0x38
8007038: 8f3b ldrh r3, [r7, #56] @ 0x38
800703a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800703e: 873b strh r3, [r7, #56] @ 0x38
8007040: 687a ldr r2, [r7, #4]
8007042: 683b ldr r3, [r7, #0]
8007044: 781b ldrb r3, [r3, #0]
8007046: 009b lsls r3, r3, #2
8007048: 441a add r2, r3
800704a: 8f3b ldrh r3, [r7, #56] @ 0x38
800704c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007050: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007054: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007058: f043 0380 orr.w r3, r3, #128 @ 0x80
800705c: b29b uxth r3, r3
800705e: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8007060: 687a ldr r2, [r7, #4]
8007062: 683b ldr r3, [r7, #0]
8007064: 781b ldrb r3, [r3, #0]
8007066: 009b lsls r3, r3, #2
8007068: 4413 add r3, r2
800706a: 881b ldrh r3, [r3, #0]
800706c: b29b uxth r3, r3
800706e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007072: f023 0340 bic.w r3, r3, #64 @ 0x40
8007076: 86fb strh r3, [r7, #54] @ 0x36
8007078: 687a ldr r2, [r7, #4]
800707a: 683b ldr r3, [r7, #0]
800707c: 781b ldrb r3, [r3, #0]
800707e: 009b lsls r3, r3, #2
8007080: 441a add r2, r3
8007082: 8efb ldrh r3, [r7, #54] @ 0x36
8007084: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007088: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800708c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007090: f043 0380 orr.w r3, r3, #128 @ 0x80
8007094: b29b uxth r3, r3
8007096: 8013 strh r3, [r2, #0]
8007098: e0bc b.n 8007214 <USB_ActivateEndpoint+0x770>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800709a: 687a ldr r2, [r7, #4]
800709c: 683b ldr r3, [r7, #0]
800709e: 781b ldrb r3, [r3, #0]
80070a0: 009b lsls r3, r3, #2
80070a2: 4413 add r3, r2
80070a4: 881b ldrh r3, [r3, #0]
80070a6: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
80070aa: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80070ae: f403 4380 and.w r3, r3, #16384 @ 0x4000
80070b2: 2b00 cmp r3, #0
80070b4: d01d beq.n 80070f2 <USB_ActivateEndpoint+0x64e>
80070b6: 687a ldr r2, [r7, #4]
80070b8: 683b ldr r3, [r7, #0]
80070ba: 781b ldrb r3, [r3, #0]
80070bc: 009b lsls r3, r3, #2
80070be: 4413 add r3, r2
80070c0: 881b ldrh r3, [r3, #0]
80070c2: b29b uxth r3, r3
80070c4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80070c8: f023 0370 bic.w r3, r3, #112 @ 0x70
80070cc: f8a7 304c strh.w r3, [r7, #76] @ 0x4c
80070d0: 687a ldr r2, [r7, #4]
80070d2: 683b ldr r3, [r7, #0]
80070d4: 781b ldrb r3, [r3, #0]
80070d6: 009b lsls r3, r3, #2
80070d8: 441a add r2, r3
80070da: f8b7 304c ldrh.w r3, [r7, #76] @ 0x4c
80070de: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80070e2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80070e6: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80070ea: f043 0380 orr.w r3, r3, #128 @ 0x80
80070ee: b29b uxth r3, r3
80070f0: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80070f2: 687a ldr r2, [r7, #4]
80070f4: 683b ldr r3, [r7, #0]
80070f6: 781b ldrb r3, [r3, #0]
80070f8: 009b lsls r3, r3, #2
80070fa: 4413 add r3, r2
80070fc: 881b ldrh r3, [r3, #0]
80070fe: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
8007102: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8007106: f003 0340 and.w r3, r3, #64 @ 0x40
800710a: 2b00 cmp r3, #0
800710c: d01d beq.n 800714a <USB_ActivateEndpoint+0x6a6>
800710e: 687a ldr r2, [r7, #4]
8007110: 683b ldr r3, [r7, #0]
8007112: 781b ldrb r3, [r3, #0]
8007114: 009b lsls r3, r3, #2
8007116: 4413 add r3, r2
8007118: 881b ldrh r3, [r3, #0]
800711a: b29b uxth r3, r3
800711c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007120: f023 0370 bic.w r3, r3, #112 @ 0x70
8007124: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
8007128: 687a ldr r2, [r7, #4]
800712a: 683b ldr r3, [r7, #0]
800712c: 781b ldrb r3, [r3, #0]
800712e: 009b lsls r3, r3, #2
8007130: 441a add r2, r3
8007132: f8b7 3048 ldrh.w r3, [r7, #72] @ 0x48
8007136: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800713a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800713e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007142: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007146: b29b uxth r3, r3
8007148: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800714a: 683b ldr r3, [r7, #0]
800714c: 78db ldrb r3, [r3, #3]
800714e: 2b01 cmp r3, #1
8007150: d024 beq.n 800719c <USB_ActivateEndpoint+0x6f8>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8007152: 687a ldr r2, [r7, #4]
8007154: 683b ldr r3, [r7, #0]
8007156: 781b ldrb r3, [r3, #0]
8007158: 009b lsls r3, r3, #2
800715a: 4413 add r3, r2
800715c: 881b ldrh r3, [r3, #0]
800715e: b29b uxth r3, r3
8007160: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007164: f023 0340 bic.w r3, r3, #64 @ 0x40
8007168: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
800716c: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
8007170: f083 0320 eor.w r3, r3, #32
8007174: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
8007178: 687a ldr r2, [r7, #4]
800717a: 683b ldr r3, [r7, #0]
800717c: 781b ldrb r3, [r3, #0]
800717e: 009b lsls r3, r3, #2
8007180: 441a add r2, r3
8007182: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
8007186: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800718a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800718e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007192: f043 0380 orr.w r3, r3, #128 @ 0x80
8007196: b29b uxth r3, r3
8007198: 8013 strh r3, [r2, #0]
800719a: e01d b.n 80071d8 <USB_ActivateEndpoint+0x734>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800719c: 687a ldr r2, [r7, #4]
800719e: 683b ldr r3, [r7, #0]
80071a0: 781b ldrb r3, [r3, #0]
80071a2: 009b lsls r3, r3, #2
80071a4: 4413 add r3, r2
80071a6: 881b ldrh r3, [r3, #0]
80071a8: b29b uxth r3, r3
80071aa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80071ae: f023 0340 bic.w r3, r3, #64 @ 0x40
80071b2: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
80071b6: 687a ldr r2, [r7, #4]
80071b8: 683b ldr r3, [r7, #0]
80071ba: 781b ldrb r3, [r3, #0]
80071bc: 009b lsls r3, r3, #2
80071be: 441a add r2, r3
80071c0: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46
80071c4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80071c8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80071cc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80071d0: f043 0380 orr.w r3, r3, #128 @ 0x80
80071d4: b29b uxth r3, r3
80071d6: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80071d8: 687a ldr r2, [r7, #4]
80071da: 683b ldr r3, [r7, #0]
80071dc: 781b ldrb r3, [r3, #0]
80071de: 009b lsls r3, r3, #2
80071e0: 4413 add r3, r2
80071e2: 881b ldrh r3, [r3, #0]
80071e4: b29b uxth r3, r3
80071e6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80071ea: f023 0370 bic.w r3, r3, #112 @ 0x70
80071ee: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
80071f2: 687a ldr r2, [r7, #4]
80071f4: 683b ldr r3, [r7, #0]
80071f6: 781b ldrb r3, [r3, #0]
80071f8: 009b lsls r3, r3, #2
80071fa: 441a add r2, r3
80071fc: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
8007200: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007204: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007208: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800720c: f043 0380 orr.w r3, r3, #128 @ 0x80
8007210: b29b uxth r3, r3
8007212: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
8007214: f897 306f ldrb.w r3, [r7, #111] @ 0x6f
}
8007218: 4618 mov r0, r3
800721a: 3774 adds r7, #116 @ 0x74
800721c: 46bd mov sp, r7
800721e: bc80 pop {r7}
8007220: 4770 bx lr
8007222: bf00 nop
08007224 <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8007224: b480 push {r7}
8007226: b08d sub sp, #52 @ 0x34
8007228: af00 add r7, sp, #0
800722a: 6078 str r0, [r7, #4]
800722c: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
800722e: 683b ldr r3, [r7, #0]
8007230: 7b1b ldrb r3, [r3, #12]
8007232: 2b00 cmp r3, #0
8007234: f040 808e bne.w 8007354 <USB_DeactivateEndpoint+0x130>
{
if (ep->is_in != 0U)
8007238: 683b ldr r3, [r7, #0]
800723a: 785b ldrb r3, [r3, #1]
800723c: 2b00 cmp r3, #0
800723e: d044 beq.n 80072ca <USB_DeactivateEndpoint+0xa6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8007240: 687a ldr r2, [r7, #4]
8007242: 683b ldr r3, [r7, #0]
8007244: 781b ldrb r3, [r3, #0]
8007246: 009b lsls r3, r3, #2
8007248: 4413 add r3, r2
800724a: 881b ldrh r3, [r3, #0]
800724c: 81bb strh r3, [r7, #12]
800724e: 89bb ldrh r3, [r7, #12]
8007250: f003 0340 and.w r3, r3, #64 @ 0x40
8007254: 2b00 cmp r3, #0
8007256: d01b beq.n 8007290 <USB_DeactivateEndpoint+0x6c>
8007258: 687a ldr r2, [r7, #4]
800725a: 683b ldr r3, [r7, #0]
800725c: 781b ldrb r3, [r3, #0]
800725e: 009b lsls r3, r3, #2
8007260: 4413 add r3, r2
8007262: 881b ldrh r3, [r3, #0]
8007264: b29b uxth r3, r3
8007266: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800726a: f023 0370 bic.w r3, r3, #112 @ 0x70
800726e: 817b strh r3, [r7, #10]
8007270: 687a ldr r2, [r7, #4]
8007272: 683b ldr r3, [r7, #0]
8007274: 781b ldrb r3, [r3, #0]
8007276: 009b lsls r3, r3, #2
8007278: 441a add r2, r3
800727a: 897b ldrh r3, [r7, #10]
800727c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007280: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007284: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007288: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800728c: b29b uxth r3, r3
800728e: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8007290: 687a ldr r2, [r7, #4]
8007292: 683b ldr r3, [r7, #0]
8007294: 781b ldrb r3, [r3, #0]
8007296: 009b lsls r3, r3, #2
8007298: 4413 add r3, r2
800729a: 881b ldrh r3, [r3, #0]
800729c: b29b uxth r3, r3
800729e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80072a2: f023 0340 bic.w r3, r3, #64 @ 0x40
80072a6: 813b strh r3, [r7, #8]
80072a8: 687a ldr r2, [r7, #4]
80072aa: 683b ldr r3, [r7, #0]
80072ac: 781b ldrb r3, [r3, #0]
80072ae: 009b lsls r3, r3, #2
80072b0: 441a add r2, r3
80072b2: 893b ldrh r3, [r7, #8]
80072b4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80072b8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80072bc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80072c0: f043 0380 orr.w r3, r3, #128 @ 0x80
80072c4: b29b uxth r3, r3
80072c6: 8013 strh r3, [r2, #0]
80072c8: e192 b.n 80075f0 <USB_DeactivateEndpoint+0x3cc>
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80072ca: 687a ldr r2, [r7, #4]
80072cc: 683b ldr r3, [r7, #0]
80072ce: 781b ldrb r3, [r3, #0]
80072d0: 009b lsls r3, r3, #2
80072d2: 4413 add r3, r2
80072d4: 881b ldrh r3, [r3, #0]
80072d6: 827b strh r3, [r7, #18]
80072d8: 8a7b ldrh r3, [r7, #18]
80072da: f403 4380 and.w r3, r3, #16384 @ 0x4000
80072de: 2b00 cmp r3, #0
80072e0: d01b beq.n 800731a <USB_DeactivateEndpoint+0xf6>
80072e2: 687a ldr r2, [r7, #4]
80072e4: 683b ldr r3, [r7, #0]
80072e6: 781b ldrb r3, [r3, #0]
80072e8: 009b lsls r3, r3, #2
80072ea: 4413 add r3, r2
80072ec: 881b ldrh r3, [r3, #0]
80072ee: b29b uxth r3, r3
80072f0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80072f4: f023 0370 bic.w r3, r3, #112 @ 0x70
80072f8: 823b strh r3, [r7, #16]
80072fa: 687a ldr r2, [r7, #4]
80072fc: 683b ldr r3, [r7, #0]
80072fe: 781b ldrb r3, [r3, #0]
8007300: 009b lsls r3, r3, #2
8007302: 441a add r2, r3
8007304: 8a3b ldrh r3, [r7, #16]
8007306: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800730a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800730e: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8007312: f043 0380 orr.w r3, r3, #128 @ 0x80
8007316: b29b uxth r3, r3
8007318: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800731a: 687a ldr r2, [r7, #4]
800731c: 683b ldr r3, [r7, #0]
800731e: 781b ldrb r3, [r3, #0]
8007320: 009b lsls r3, r3, #2
8007322: 4413 add r3, r2
8007324: 881b ldrh r3, [r3, #0]
8007326: b29b uxth r3, r3
8007328: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800732c: f023 0370 bic.w r3, r3, #112 @ 0x70
8007330: 81fb strh r3, [r7, #14]
8007332: 687a ldr r2, [r7, #4]
8007334: 683b ldr r3, [r7, #0]
8007336: 781b ldrb r3, [r3, #0]
8007338: 009b lsls r3, r3, #2
800733a: 441a add r2, r3
800733c: 89fb ldrh r3, [r7, #14]
800733e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007342: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007346: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800734a: f043 0380 orr.w r3, r3, #128 @ 0x80
800734e: b29b uxth r3, r3
8007350: 8013 strh r3, [r2, #0]
8007352: e14d b.n 80075f0 <USB_DeactivateEndpoint+0x3cc>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->is_in == 0U)
8007354: 683b ldr r3, [r7, #0]
8007356: 785b ldrb r3, [r3, #1]
8007358: 2b00 cmp r3, #0
800735a: f040 80a5 bne.w 80074a8 <USB_DeactivateEndpoint+0x284>
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800735e: 687a ldr r2, [r7, #4]
8007360: 683b ldr r3, [r7, #0]
8007362: 781b ldrb r3, [r3, #0]
8007364: 009b lsls r3, r3, #2
8007366: 4413 add r3, r2
8007368: 881b ldrh r3, [r3, #0]
800736a: 843b strh r3, [r7, #32]
800736c: 8c3b ldrh r3, [r7, #32]
800736e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8007372: 2b00 cmp r3, #0
8007374: d01b beq.n 80073ae <USB_DeactivateEndpoint+0x18a>
8007376: 687a ldr r2, [r7, #4]
8007378: 683b ldr r3, [r7, #0]
800737a: 781b ldrb r3, [r3, #0]
800737c: 009b lsls r3, r3, #2
800737e: 4413 add r3, r2
8007380: 881b ldrh r3, [r3, #0]
8007382: b29b uxth r3, r3
8007384: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007388: f023 0370 bic.w r3, r3, #112 @ 0x70
800738c: 83fb strh r3, [r7, #30]
800738e: 687a ldr r2, [r7, #4]
8007390: 683b ldr r3, [r7, #0]
8007392: 781b ldrb r3, [r3, #0]
8007394: 009b lsls r3, r3, #2
8007396: 441a add r2, r3
8007398: 8bfb ldrh r3, [r7, #30]
800739a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800739e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80073a2: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80073a6: f043 0380 orr.w r3, r3, #128 @ 0x80
80073aa: b29b uxth r3, r3
80073ac: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80073ae: 687a ldr r2, [r7, #4]
80073b0: 683b ldr r3, [r7, #0]
80073b2: 781b ldrb r3, [r3, #0]
80073b4: 009b lsls r3, r3, #2
80073b6: 4413 add r3, r2
80073b8: 881b ldrh r3, [r3, #0]
80073ba: 83bb strh r3, [r7, #28]
80073bc: 8bbb ldrh r3, [r7, #28]
80073be: f003 0340 and.w r3, r3, #64 @ 0x40
80073c2: 2b00 cmp r3, #0
80073c4: d01b beq.n 80073fe <USB_DeactivateEndpoint+0x1da>
80073c6: 687a ldr r2, [r7, #4]
80073c8: 683b ldr r3, [r7, #0]
80073ca: 781b ldrb r3, [r3, #0]
80073cc: 009b lsls r3, r3, #2
80073ce: 4413 add r3, r2
80073d0: 881b ldrh r3, [r3, #0]
80073d2: b29b uxth r3, r3
80073d4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80073d8: f023 0370 bic.w r3, r3, #112 @ 0x70
80073dc: 837b strh r3, [r7, #26]
80073de: 687a ldr r2, [r7, #4]
80073e0: 683b ldr r3, [r7, #0]
80073e2: 781b ldrb r3, [r3, #0]
80073e4: 009b lsls r3, r3, #2
80073e6: 441a add r2, r3
80073e8: 8b7b ldrh r3, [r7, #26]
80073ea: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80073ee: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80073f2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80073f6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80073fa: b29b uxth r3, r3
80073fc: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
80073fe: 687a ldr r2, [r7, #4]
8007400: 683b ldr r3, [r7, #0]
8007402: 781b ldrb r3, [r3, #0]
8007404: 009b lsls r3, r3, #2
8007406: 4413 add r3, r2
8007408: 881b ldrh r3, [r3, #0]
800740a: b29b uxth r3, r3
800740c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007410: f023 0370 bic.w r3, r3, #112 @ 0x70
8007414: 833b strh r3, [r7, #24]
8007416: 687a ldr r2, [r7, #4]
8007418: 683b ldr r3, [r7, #0]
800741a: 781b ldrb r3, [r3, #0]
800741c: 009b lsls r3, r3, #2
800741e: 441a add r2, r3
8007420: 8b3b ldrh r3, [r7, #24]
8007422: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007426: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800742a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800742e: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007432: b29b uxth r3, r3
8007434: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8007436: 687a ldr r2, [r7, #4]
8007438: 683b ldr r3, [r7, #0]
800743a: 781b ldrb r3, [r3, #0]
800743c: 009b lsls r3, r3, #2
800743e: 4413 add r3, r2
8007440: 881b ldrh r3, [r3, #0]
8007442: b29b uxth r3, r3
8007444: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8007448: f023 0370 bic.w r3, r3, #112 @ 0x70
800744c: 82fb strh r3, [r7, #22]
800744e: 687a ldr r2, [r7, #4]
8007450: 683b ldr r3, [r7, #0]
8007452: 781b ldrb r3, [r3, #0]
8007454: 009b lsls r3, r3, #2
8007456: 441a add r2, r3
8007458: 8afb ldrh r3, [r7, #22]
800745a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800745e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007462: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007466: f043 0380 orr.w r3, r3, #128 @ 0x80
800746a: b29b uxth r3, r3
800746c: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800746e: 687a ldr r2, [r7, #4]
8007470: 683b ldr r3, [r7, #0]
8007472: 781b ldrb r3, [r3, #0]
8007474: 009b lsls r3, r3, #2
8007476: 4413 add r3, r2
8007478: 881b ldrh r3, [r3, #0]
800747a: b29b uxth r3, r3
800747c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007480: f023 0340 bic.w r3, r3, #64 @ 0x40
8007484: 82bb strh r3, [r7, #20]
8007486: 687a ldr r2, [r7, #4]
8007488: 683b ldr r3, [r7, #0]
800748a: 781b ldrb r3, [r3, #0]
800748c: 009b lsls r3, r3, #2
800748e: 441a add r2, r3
8007490: 8abb ldrh r3, [r7, #20]
8007492: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007496: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800749a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800749e: f043 0380 orr.w r3, r3, #128 @ 0x80
80074a2: b29b uxth r3, r3
80074a4: 8013 strh r3, [r2, #0]
80074a6: e0a3 b.n 80075f0 <USB_DeactivateEndpoint+0x3cc>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80074a8: 687a ldr r2, [r7, #4]
80074aa: 683b ldr r3, [r7, #0]
80074ac: 781b ldrb r3, [r3, #0]
80074ae: 009b lsls r3, r3, #2
80074b0: 4413 add r3, r2
80074b2: 881b ldrh r3, [r3, #0]
80074b4: 85fb strh r3, [r7, #46] @ 0x2e
80074b6: 8dfb ldrh r3, [r7, #46] @ 0x2e
80074b8: f403 4380 and.w r3, r3, #16384 @ 0x4000
80074bc: 2b00 cmp r3, #0
80074be: d01b beq.n 80074f8 <USB_DeactivateEndpoint+0x2d4>
80074c0: 687a ldr r2, [r7, #4]
80074c2: 683b ldr r3, [r7, #0]
80074c4: 781b ldrb r3, [r3, #0]
80074c6: 009b lsls r3, r3, #2
80074c8: 4413 add r3, r2
80074ca: 881b ldrh r3, [r3, #0]
80074cc: b29b uxth r3, r3
80074ce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80074d2: f023 0370 bic.w r3, r3, #112 @ 0x70
80074d6: 85bb strh r3, [r7, #44] @ 0x2c
80074d8: 687a ldr r2, [r7, #4]
80074da: 683b ldr r3, [r7, #0]
80074dc: 781b ldrb r3, [r3, #0]
80074de: 009b lsls r3, r3, #2
80074e0: 441a add r2, r3
80074e2: 8dbb ldrh r3, [r7, #44] @ 0x2c
80074e4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80074e8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80074ec: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80074f0: f043 0380 orr.w r3, r3, #128 @ 0x80
80074f4: b29b uxth r3, r3
80074f6: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80074f8: 687a ldr r2, [r7, #4]
80074fa: 683b ldr r3, [r7, #0]
80074fc: 781b ldrb r3, [r3, #0]
80074fe: 009b lsls r3, r3, #2
8007500: 4413 add r3, r2
8007502: 881b ldrh r3, [r3, #0]
8007504: 857b strh r3, [r7, #42] @ 0x2a
8007506: 8d7b ldrh r3, [r7, #42] @ 0x2a
8007508: f003 0340 and.w r3, r3, #64 @ 0x40
800750c: 2b00 cmp r3, #0
800750e: d01b beq.n 8007548 <USB_DeactivateEndpoint+0x324>
8007510: 687a ldr r2, [r7, #4]
8007512: 683b ldr r3, [r7, #0]
8007514: 781b ldrb r3, [r3, #0]
8007516: 009b lsls r3, r3, #2
8007518: 4413 add r3, r2
800751a: 881b ldrh r3, [r3, #0]
800751c: b29b uxth r3, r3
800751e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007522: f023 0370 bic.w r3, r3, #112 @ 0x70
8007526: 853b strh r3, [r7, #40] @ 0x28
8007528: 687a ldr r2, [r7, #4]
800752a: 683b ldr r3, [r7, #0]
800752c: 781b ldrb r3, [r3, #0]
800752e: 009b lsls r3, r3, #2
8007530: 441a add r2, r3
8007532: 8d3b ldrh r3, [r7, #40] @ 0x28
8007534: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007538: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800753c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007540: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007544: b29b uxth r3, r3
8007546: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
8007548: 687a ldr r2, [r7, #4]
800754a: 683b ldr r3, [r7, #0]
800754c: 781b ldrb r3, [r3, #0]
800754e: 009b lsls r3, r3, #2
8007550: 4413 add r3, r2
8007552: 881b ldrh r3, [r3, #0]
8007554: b29b uxth r3, r3
8007556: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800755a: f023 0370 bic.w r3, r3, #112 @ 0x70
800755e: 84fb strh r3, [r7, #38] @ 0x26
8007560: 687a ldr r2, [r7, #4]
8007562: 683b ldr r3, [r7, #0]
8007564: 781b ldrb r3, [r3, #0]
8007566: 009b lsls r3, r3, #2
8007568: 441a add r2, r3
800756a: 8cfb ldrh r3, [r7, #38] @ 0x26
800756c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007570: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007574: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8007578: f043 0380 orr.w r3, r3, #128 @ 0x80
800757c: b29b uxth r3, r3
800757e: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8007580: 687a ldr r2, [r7, #4]
8007582: 683b ldr r3, [r7, #0]
8007584: 781b ldrb r3, [r3, #0]
8007586: 009b lsls r3, r3, #2
8007588: 4413 add r3, r2
800758a: 881b ldrh r3, [r3, #0]
800758c: b29b uxth r3, r3
800758e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007592: f023 0340 bic.w r3, r3, #64 @ 0x40
8007596: 84bb strh r3, [r7, #36] @ 0x24
8007598: 687a ldr r2, [r7, #4]
800759a: 683b ldr r3, [r7, #0]
800759c: 781b ldrb r3, [r3, #0]
800759e: 009b lsls r3, r3, #2
80075a0: 441a add r2, r3
80075a2: 8cbb ldrh r3, [r7, #36] @ 0x24
80075a4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80075a8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80075ac: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80075b0: f043 0380 orr.w r3, r3, #128 @ 0x80
80075b4: b29b uxth r3, r3
80075b6: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80075b8: 687a ldr r2, [r7, #4]
80075ba: 683b ldr r3, [r7, #0]
80075bc: 781b ldrb r3, [r3, #0]
80075be: 009b lsls r3, r3, #2
80075c0: 4413 add r3, r2
80075c2: 881b ldrh r3, [r3, #0]
80075c4: b29b uxth r3, r3
80075c6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80075ca: f023 0370 bic.w r3, r3, #112 @ 0x70
80075ce: 847b strh r3, [r7, #34] @ 0x22
80075d0: 687a ldr r2, [r7, #4]
80075d2: 683b ldr r3, [r7, #0]
80075d4: 781b ldrb r3, [r3, #0]
80075d6: 009b lsls r3, r3, #2
80075d8: 441a add r2, r3
80075da: 8c7b ldrh r3, [r7, #34] @ 0x22
80075dc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80075e0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80075e4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80075e8: f043 0380 orr.w r3, r3, #128 @ 0x80
80075ec: b29b uxth r3, r3
80075ee: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
80075f0: 2300 movs r3, #0
}
80075f2: 4618 mov r0, r3
80075f4: 3734 adds r7, #52 @ 0x34
80075f6: 46bd mov sp, r7
80075f8: bc80 pop {r7}
80075fa: 4770 bx lr
080075fc <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
80075fc: b580 push {r7, lr}
80075fe: b0c2 sub sp, #264 @ 0x108
8007600: af00 add r7, sp, #0
8007602: f507 7384 add.w r3, r7, #264 @ 0x108
8007606: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800760a: 6018 str r0, [r3, #0]
800760c: f507 7384 add.w r3, r7, #264 @ 0x108
8007610: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007614: 6019 str r1, [r3, #0]
uint16_t pmabuffer;
uint16_t wEPVal;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
8007616: f507 7384 add.w r3, r7, #264 @ 0x108
800761a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800761e: 681b ldr r3, [r3, #0]
8007620: 785b ldrb r3, [r3, #1]
8007622: 2b01 cmp r3, #1
8007624: f040 86b7 bne.w 8008396 <USB_EPStartXfer+0xd9a>
{
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
8007628: f507 7384 add.w r3, r7, #264 @ 0x108
800762c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007630: 681b ldr r3, [r3, #0]
8007632: 699a ldr r2, [r3, #24]
8007634: f507 7384 add.w r3, r7, #264 @ 0x108
8007638: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800763c: 681b ldr r3, [r3, #0]
800763e: 691b ldr r3, [r3, #16]
8007640: 429a cmp r2, r3
8007642: d908 bls.n 8007656 <USB_EPStartXfer+0x5a>
{
len = ep->maxpacket;
8007644: f507 7384 add.w r3, r7, #264 @ 0x108
8007648: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800764c: 681b ldr r3, [r3, #0]
800764e: 691b ldr r3, [r3, #16]
8007650: f8c7 3104 str.w r3, [r7, #260] @ 0x104
8007654: e007 b.n 8007666 <USB_EPStartXfer+0x6a>
}
else
{
len = ep->xfer_len;
8007656: f507 7384 add.w r3, r7, #264 @ 0x108
800765a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800765e: 681b ldr r3, [r3, #0]
8007660: 699b ldr r3, [r3, #24]
8007662: f8c7 3104 str.w r3, [r7, #260] @ 0x104
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
8007666: f507 7384 add.w r3, r7, #264 @ 0x108
800766a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800766e: 681b ldr r3, [r3, #0]
8007670: 7b1b ldrb r3, [r3, #12]
8007672: 2b00 cmp r3, #0
8007674: d13a bne.n 80076ec <USB_EPStartXfer+0xf0>
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
8007676: f507 7384 add.w r3, r7, #264 @ 0x108
800767a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800767e: 681b ldr r3, [r3, #0]
8007680: 6959 ldr r1, [r3, #20]
8007682: f507 7384 add.w r3, r7, #264 @ 0x108
8007686: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800768a: 681b ldr r3, [r3, #0]
800768c: 88da ldrh r2, [r3, #6]
800768e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007692: b29b uxth r3, r3
8007694: f507 7084 add.w r0, r7, #264 @ 0x108
8007698: f5a0 7082 sub.w r0, r0, #260 @ 0x104
800769c: 6800 ldr r0, [r0, #0]
800769e: f001 fc9c bl 8008fda <USB_WritePMA>
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
80076a2: f507 7384 add.w r3, r7, #264 @ 0x108
80076a6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80076aa: 681b ldr r3, [r3, #0]
80076ac: 613b str r3, [r7, #16]
80076ae: f507 7384 add.w r3, r7, #264 @ 0x108
80076b2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80076b6: 681b ldr r3, [r3, #0]
80076b8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80076bc: b29b uxth r3, r3
80076be: 461a mov r2, r3
80076c0: 693b ldr r3, [r7, #16]
80076c2: 4413 add r3, r2
80076c4: 613b str r3, [r7, #16]
80076c6: f507 7384 add.w r3, r7, #264 @ 0x108
80076ca: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80076ce: 681b ldr r3, [r3, #0]
80076d0: 781b ldrb r3, [r3, #0]
80076d2: 011a lsls r2, r3, #4
80076d4: 693b ldr r3, [r7, #16]
80076d6: 4413 add r3, r2
80076d8: f203 4304 addw r3, r3, #1028 @ 0x404
80076dc: 60fb str r3, [r7, #12]
80076de: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80076e2: b29a uxth r2, r3
80076e4: 68fb ldr r3, [r7, #12]
80076e6: 801a strh r2, [r3, #0]
80076e8: f000 be1f b.w 800832a <USB_EPStartXfer+0xd2e>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
80076ec: f507 7384 add.w r3, r7, #264 @ 0x108
80076f0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80076f4: 681b ldr r3, [r3, #0]
80076f6: 78db ldrb r3, [r3, #3]
80076f8: 2b02 cmp r3, #2
80076fa: f040 8462 bne.w 8007fc2 <USB_EPStartXfer+0x9c6>
{
if (ep->xfer_len_db > ep->maxpacket)
80076fe: f507 7384 add.w r3, r7, #264 @ 0x108
8007702: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007706: 681b ldr r3, [r3, #0]
8007708: 6a1a ldr r2, [r3, #32]
800770a: f507 7384 add.w r3, r7, #264 @ 0x108
800770e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007712: 681b ldr r3, [r3, #0]
8007714: 691b ldr r3, [r3, #16]
8007716: 429a cmp r2, r3
8007718: f240 83df bls.w 8007eda <USB_EPStartXfer+0x8de>
{
/* enable double buffer */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
800771c: f507 7384 add.w r3, r7, #264 @ 0x108
8007720: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007724: 681a ldr r2, [r3, #0]
8007726: f507 7384 add.w r3, r7, #264 @ 0x108
800772a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800772e: 681b ldr r3, [r3, #0]
8007730: 781b ldrb r3, [r3, #0]
8007732: 009b lsls r3, r3, #2
8007734: 4413 add r3, r2
8007736: 881b ldrh r3, [r3, #0]
8007738: b29b uxth r3, r3
800773a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800773e: f023 0370 bic.w r3, r3, #112 @ 0x70
8007742: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
8007746: f507 7384 add.w r3, r7, #264 @ 0x108
800774a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800774e: 681a ldr r2, [r3, #0]
8007750: f507 7384 add.w r3, r7, #264 @ 0x108
8007754: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007758: 681b ldr r3, [r3, #0]
800775a: 781b ldrb r3, [r3, #0]
800775c: 009b lsls r3, r3, #2
800775e: 441a add r2, r3
8007760: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
8007764: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007768: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800776c: f443 4301 orr.w r3, r3, #33024 @ 0x8100
8007770: f043 0380 orr.w r3, r3, #128 @ 0x80
8007774: b29b uxth r3, r3
8007776: 8013 strh r3, [r2, #0]
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
8007778: f507 7384 add.w r3, r7, #264 @ 0x108
800777c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007780: 681b ldr r3, [r3, #0]
8007782: 6a1a ldr r2, [r3, #32]
8007784: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007788: 1ad2 subs r2, r2, r3
800778a: f507 7384 add.w r3, r7, #264 @ 0x108
800778e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007792: 681b ldr r3, [r3, #0]
8007794: 621a str r2, [r3, #32]
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8007796: f507 7384 add.w r3, r7, #264 @ 0x108
800779a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800779e: 681a ldr r2, [r3, #0]
80077a0: f507 7384 add.w r3, r7, #264 @ 0x108
80077a4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80077a8: 681b ldr r3, [r3, #0]
80077aa: 781b ldrb r3, [r3, #0]
80077ac: 009b lsls r3, r3, #2
80077ae: 4413 add r3, r2
80077b0: 881b ldrh r3, [r3, #0]
80077b2: b29b uxth r3, r3
80077b4: f003 0340 and.w r3, r3, #64 @ 0x40
80077b8: 2b00 cmp r3, #0
80077ba: f000 81c7 beq.w 8007b4c <USB_EPStartXfer+0x550>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
80077be: f507 7384 add.w r3, r7, #264 @ 0x108
80077c2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80077c6: 681b ldr r3, [r3, #0]
80077c8: 633b str r3, [r7, #48] @ 0x30
80077ca: f507 7384 add.w r3, r7, #264 @ 0x108
80077ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80077d2: 681b ldr r3, [r3, #0]
80077d4: 785b ldrb r3, [r3, #1]
80077d6: 2b00 cmp r3, #0
80077d8: d177 bne.n 80078ca <USB_EPStartXfer+0x2ce>
80077da: f507 7384 add.w r3, r7, #264 @ 0x108
80077de: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80077e2: 681b ldr r3, [r3, #0]
80077e4: 62bb str r3, [r7, #40] @ 0x28
80077e6: f507 7384 add.w r3, r7, #264 @ 0x108
80077ea: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80077ee: 681b ldr r3, [r3, #0]
80077f0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80077f4: b29b uxth r3, r3
80077f6: 461a mov r2, r3
80077f8: 6abb ldr r3, [r7, #40] @ 0x28
80077fa: 4413 add r3, r2
80077fc: 62bb str r3, [r7, #40] @ 0x28
80077fe: f507 7384 add.w r3, r7, #264 @ 0x108
8007802: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007806: 681b ldr r3, [r3, #0]
8007808: 781b ldrb r3, [r3, #0]
800780a: 011a lsls r2, r3, #4
800780c: 6abb ldr r3, [r7, #40] @ 0x28
800780e: 4413 add r3, r2
8007810: f203 430c addw r3, r3, #1036 @ 0x40c
8007814: 627b str r3, [r7, #36] @ 0x24
8007816: 6a7b ldr r3, [r7, #36] @ 0x24
8007818: 881b ldrh r3, [r3, #0]
800781a: b29b uxth r3, r3
800781c: f3c3 0309 ubfx r3, r3, #0, #10
8007820: b29a uxth r2, r3
8007822: 6a7b ldr r3, [r7, #36] @ 0x24
8007824: 801a strh r2, [r3, #0]
8007826: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800782a: 2b3e cmp r3, #62 @ 0x3e
800782c: d921 bls.n 8007872 <USB_EPStartXfer+0x276>
800782e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007832: 095b lsrs r3, r3, #5
8007834: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8007838: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800783c: f003 031f and.w r3, r3, #31
8007840: 2b00 cmp r3, #0
8007842: d104 bne.n 800784e <USB_EPStartXfer+0x252>
8007844: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8007848: 3b01 subs r3, #1
800784a: f8c7 3100 str.w r3, [r7, #256] @ 0x100
800784e: 6a7b ldr r3, [r7, #36] @ 0x24
8007850: 881b ldrh r3, [r3, #0]
8007852: b29a uxth r2, r3
8007854: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8007858: b29b uxth r3, r3
800785a: 029b lsls r3, r3, #10
800785c: b29b uxth r3, r3
800785e: 4313 orrs r3, r2
8007860: b29b uxth r3, r3
8007862: ea6f 4343 mvn.w r3, r3, lsl #17
8007866: ea6f 4353 mvn.w r3, r3, lsr #17
800786a: b29a uxth r2, r3
800786c: 6a7b ldr r3, [r7, #36] @ 0x24
800786e: 801a strh r2, [r3, #0]
8007870: e050 b.n 8007914 <USB_EPStartXfer+0x318>
8007872: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007876: 2b00 cmp r3, #0
8007878: d10a bne.n 8007890 <USB_EPStartXfer+0x294>
800787a: 6a7b ldr r3, [r7, #36] @ 0x24
800787c: 881b ldrh r3, [r3, #0]
800787e: b29b uxth r3, r3
8007880: ea6f 4343 mvn.w r3, r3, lsl #17
8007884: ea6f 4353 mvn.w r3, r3, lsr #17
8007888: b29a uxth r2, r3
800788a: 6a7b ldr r3, [r7, #36] @ 0x24
800788c: 801a strh r2, [r3, #0]
800788e: e041 b.n 8007914 <USB_EPStartXfer+0x318>
8007890: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007894: 085b lsrs r3, r3, #1
8007896: f8c7 3100 str.w r3, [r7, #256] @ 0x100
800789a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800789e: f003 0301 and.w r3, r3, #1
80078a2: 2b00 cmp r3, #0
80078a4: d004 beq.n 80078b0 <USB_EPStartXfer+0x2b4>
80078a6: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
80078aa: 3301 adds r3, #1
80078ac: f8c7 3100 str.w r3, [r7, #256] @ 0x100
80078b0: 6a7b ldr r3, [r7, #36] @ 0x24
80078b2: 881b ldrh r3, [r3, #0]
80078b4: b29a uxth r2, r3
80078b6: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
80078ba: b29b uxth r3, r3
80078bc: 029b lsls r3, r3, #10
80078be: b29b uxth r3, r3
80078c0: 4313 orrs r3, r2
80078c2: b29a uxth r2, r3
80078c4: 6a7b ldr r3, [r7, #36] @ 0x24
80078c6: 801a strh r2, [r3, #0]
80078c8: e024 b.n 8007914 <USB_EPStartXfer+0x318>
80078ca: f507 7384 add.w r3, r7, #264 @ 0x108
80078ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80078d2: 681b ldr r3, [r3, #0]
80078d4: 785b ldrb r3, [r3, #1]
80078d6: 2b01 cmp r3, #1
80078d8: d11c bne.n 8007914 <USB_EPStartXfer+0x318>
80078da: f507 7384 add.w r3, r7, #264 @ 0x108
80078de: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80078e2: 681b ldr r3, [r3, #0]
80078e4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80078e8: b29b uxth r3, r3
80078ea: 461a mov r2, r3
80078ec: 6b3b ldr r3, [r7, #48] @ 0x30
80078ee: 4413 add r3, r2
80078f0: 633b str r3, [r7, #48] @ 0x30
80078f2: f507 7384 add.w r3, r7, #264 @ 0x108
80078f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80078fa: 681b ldr r3, [r3, #0]
80078fc: 781b ldrb r3, [r3, #0]
80078fe: 011a lsls r2, r3, #4
8007900: 6b3b ldr r3, [r7, #48] @ 0x30
8007902: 4413 add r3, r2
8007904: f203 430c addw r3, r3, #1036 @ 0x40c
8007908: 62fb str r3, [r7, #44] @ 0x2c
800790a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800790e: b29a uxth r2, r3
8007910: 6afb ldr r3, [r7, #44] @ 0x2c
8007912: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8007914: f507 7384 add.w r3, r7, #264 @ 0x108
8007918: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800791c: 681b ldr r3, [r3, #0]
800791e: 895b ldrh r3, [r3, #10]
8007920: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007924: f507 7384 add.w r3, r7, #264 @ 0x108
8007928: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800792c: 681b ldr r3, [r3, #0]
800792e: 6959 ldr r1, [r3, #20]
8007930: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007934: b29b uxth r3, r3
8007936: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800793a: f507 7084 add.w r0, r7, #264 @ 0x108
800793e: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007942: 6800 ldr r0, [r0, #0]
8007944: f001 fb49 bl 8008fda <USB_WritePMA>
ep->xfer_buff += len;
8007948: f507 7384 add.w r3, r7, #264 @ 0x108
800794c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007950: 681b ldr r3, [r3, #0]
8007952: 695a ldr r2, [r3, #20]
8007954: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007958: 441a add r2, r3
800795a: f507 7384 add.w r3, r7, #264 @ 0x108
800795e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007962: 681b ldr r3, [r3, #0]
8007964: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8007966: f507 7384 add.w r3, r7, #264 @ 0x108
800796a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800796e: 681b ldr r3, [r3, #0]
8007970: 6a1a ldr r2, [r3, #32]
8007972: f507 7384 add.w r3, r7, #264 @ 0x108
8007976: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800797a: 681b ldr r3, [r3, #0]
800797c: 691b ldr r3, [r3, #16]
800797e: 429a cmp r2, r3
8007980: d90f bls.n 80079a2 <USB_EPStartXfer+0x3a6>
{
ep->xfer_len_db -= len;
8007982: f507 7384 add.w r3, r7, #264 @ 0x108
8007986: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800798a: 681b ldr r3, [r3, #0]
800798c: 6a1a ldr r2, [r3, #32]
800798e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007992: 1ad2 subs r2, r2, r3
8007994: f507 7384 add.w r3, r7, #264 @ 0x108
8007998: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800799c: 681b ldr r3, [r3, #0]
800799e: 621a str r2, [r3, #32]
80079a0: e00e b.n 80079c0 <USB_EPStartXfer+0x3c4>
}
else
{
len = ep->xfer_len_db;
80079a2: f507 7384 add.w r3, r7, #264 @ 0x108
80079a6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079aa: 681b ldr r3, [r3, #0]
80079ac: 6a1b ldr r3, [r3, #32]
80079ae: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
80079b2: f507 7384 add.w r3, r7, #264 @ 0x108
80079b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079ba: 681b ldr r3, [r3, #0]
80079bc: 2200 movs r2, #0
80079be: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
80079c0: f507 7384 add.w r3, r7, #264 @ 0x108
80079c4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079c8: 681b ldr r3, [r3, #0]
80079ca: 785b ldrb r3, [r3, #1]
80079cc: 2b00 cmp r3, #0
80079ce: d177 bne.n 8007ac0 <USB_EPStartXfer+0x4c4>
80079d0: f507 7384 add.w r3, r7, #264 @ 0x108
80079d4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80079d8: 681b ldr r3, [r3, #0]
80079da: 61bb str r3, [r7, #24]
80079dc: f507 7384 add.w r3, r7, #264 @ 0x108
80079e0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80079e4: 681b ldr r3, [r3, #0]
80079e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80079ea: b29b uxth r3, r3
80079ec: 461a mov r2, r3
80079ee: 69bb ldr r3, [r7, #24]
80079f0: 4413 add r3, r2
80079f2: 61bb str r3, [r7, #24]
80079f4: f507 7384 add.w r3, r7, #264 @ 0x108
80079f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80079fc: 681b ldr r3, [r3, #0]
80079fe: 781b ldrb r3, [r3, #0]
8007a00: 011a lsls r2, r3, #4
8007a02: 69bb ldr r3, [r7, #24]
8007a04: 4413 add r3, r2
8007a06: f203 4304 addw r3, r3, #1028 @ 0x404
8007a0a: 617b str r3, [r7, #20]
8007a0c: 697b ldr r3, [r7, #20]
8007a0e: 881b ldrh r3, [r3, #0]
8007a10: b29b uxth r3, r3
8007a12: f3c3 0309 ubfx r3, r3, #0, #10
8007a16: b29a uxth r2, r3
8007a18: 697b ldr r3, [r7, #20]
8007a1a: 801a strh r2, [r3, #0]
8007a1c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a20: 2b3e cmp r3, #62 @ 0x3e
8007a22: d921 bls.n 8007a68 <USB_EPStartXfer+0x46c>
8007a24: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a28: 095b lsrs r3, r3, #5
8007a2a: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007a2e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a32: f003 031f and.w r3, r3, #31
8007a36: 2b00 cmp r3, #0
8007a38: d104 bne.n 8007a44 <USB_EPStartXfer+0x448>
8007a3a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007a3e: 3b01 subs r3, #1
8007a40: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007a44: 697b ldr r3, [r7, #20]
8007a46: 881b ldrh r3, [r3, #0]
8007a48: b29a uxth r2, r3
8007a4a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007a4e: b29b uxth r3, r3
8007a50: 029b lsls r3, r3, #10
8007a52: b29b uxth r3, r3
8007a54: 4313 orrs r3, r2
8007a56: b29b uxth r3, r3
8007a58: ea6f 4343 mvn.w r3, r3, lsl #17
8007a5c: ea6f 4353 mvn.w r3, r3, lsr #17
8007a60: b29a uxth r2, r3
8007a62: 697b ldr r3, [r7, #20]
8007a64: 801a strh r2, [r3, #0]
8007a66: e056 b.n 8007b16 <USB_EPStartXfer+0x51a>
8007a68: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a6c: 2b00 cmp r3, #0
8007a6e: d10a bne.n 8007a86 <USB_EPStartXfer+0x48a>
8007a70: 697b ldr r3, [r7, #20]
8007a72: 881b ldrh r3, [r3, #0]
8007a74: b29b uxth r3, r3
8007a76: ea6f 4343 mvn.w r3, r3, lsl #17
8007a7a: ea6f 4353 mvn.w r3, r3, lsr #17
8007a7e: b29a uxth r2, r3
8007a80: 697b ldr r3, [r7, #20]
8007a82: 801a strh r2, [r3, #0]
8007a84: e047 b.n 8007b16 <USB_EPStartXfer+0x51a>
8007a86: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a8a: 085b lsrs r3, r3, #1
8007a8c: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007a90: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007a94: f003 0301 and.w r3, r3, #1
8007a98: 2b00 cmp r3, #0
8007a9a: d004 beq.n 8007aa6 <USB_EPStartXfer+0x4aa>
8007a9c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007aa0: 3301 adds r3, #1
8007aa2: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8007aa6: 697b ldr r3, [r7, #20]
8007aa8: 881b ldrh r3, [r3, #0]
8007aaa: b29a uxth r2, r3
8007aac: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8007ab0: b29b uxth r3, r3
8007ab2: 029b lsls r3, r3, #10
8007ab4: b29b uxth r3, r3
8007ab6: 4313 orrs r3, r2
8007ab8: b29a uxth r2, r3
8007aba: 697b ldr r3, [r7, #20]
8007abc: 801a strh r2, [r3, #0]
8007abe: e02a b.n 8007b16 <USB_EPStartXfer+0x51a>
8007ac0: f507 7384 add.w r3, r7, #264 @ 0x108
8007ac4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007ac8: 681b ldr r3, [r3, #0]
8007aca: 785b ldrb r3, [r3, #1]
8007acc: 2b01 cmp r3, #1
8007ace: d122 bne.n 8007b16 <USB_EPStartXfer+0x51a>
8007ad0: f507 7384 add.w r3, r7, #264 @ 0x108
8007ad4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007ad8: 681b ldr r3, [r3, #0]
8007ada: 623b str r3, [r7, #32]
8007adc: f507 7384 add.w r3, r7, #264 @ 0x108
8007ae0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007ae4: 681b ldr r3, [r3, #0]
8007ae6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007aea: b29b uxth r3, r3
8007aec: 461a mov r2, r3
8007aee: 6a3b ldr r3, [r7, #32]
8007af0: 4413 add r3, r2
8007af2: 623b str r3, [r7, #32]
8007af4: f507 7384 add.w r3, r7, #264 @ 0x108
8007af8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007afc: 681b ldr r3, [r3, #0]
8007afe: 781b ldrb r3, [r3, #0]
8007b00: 011a lsls r2, r3, #4
8007b02: 6a3b ldr r3, [r7, #32]
8007b04: 4413 add r3, r2
8007b06: f203 4304 addw r3, r3, #1028 @ 0x404
8007b0a: 61fb str r3, [r7, #28]
8007b0c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007b10: b29a uxth r2, r3
8007b12: 69fb ldr r3, [r7, #28]
8007b14: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8007b16: f507 7384 add.w r3, r7, #264 @ 0x108
8007b1a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b1e: 681b ldr r3, [r3, #0]
8007b20: 891b ldrh r3, [r3, #8]
8007b22: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007b26: f507 7384 add.w r3, r7, #264 @ 0x108
8007b2a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b2e: 681b ldr r3, [r3, #0]
8007b30: 6959 ldr r1, [r3, #20]
8007b32: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007b36: b29b uxth r3, r3
8007b38: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007b3c: f507 7084 add.w r0, r7, #264 @ 0x108
8007b40: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007b44: 6800 ldr r0, [r0, #0]
8007b46: f001 fa48 bl 8008fda <USB_WritePMA>
8007b4a: e3ee b.n 800832a <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8007b4c: f507 7384 add.w r3, r7, #264 @ 0x108
8007b50: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b54: 681b ldr r3, [r3, #0]
8007b56: 785b ldrb r3, [r3, #1]
8007b58: 2b00 cmp r3, #0
8007b5a: d177 bne.n 8007c4c <USB_EPStartXfer+0x650>
8007b5c: f507 7384 add.w r3, r7, #264 @ 0x108
8007b60: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007b64: 681b ldr r3, [r3, #0]
8007b66: 64bb str r3, [r7, #72] @ 0x48
8007b68: f507 7384 add.w r3, r7, #264 @ 0x108
8007b6c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007b70: 681b ldr r3, [r3, #0]
8007b72: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007b76: b29b uxth r3, r3
8007b78: 461a mov r2, r3
8007b7a: 6cbb ldr r3, [r7, #72] @ 0x48
8007b7c: 4413 add r3, r2
8007b7e: 64bb str r3, [r7, #72] @ 0x48
8007b80: f507 7384 add.w r3, r7, #264 @ 0x108
8007b84: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007b88: 681b ldr r3, [r3, #0]
8007b8a: 781b ldrb r3, [r3, #0]
8007b8c: 011a lsls r2, r3, #4
8007b8e: 6cbb ldr r3, [r7, #72] @ 0x48
8007b90: 4413 add r3, r2
8007b92: f203 4304 addw r3, r3, #1028 @ 0x404
8007b96: 647b str r3, [r7, #68] @ 0x44
8007b98: 6c7b ldr r3, [r7, #68] @ 0x44
8007b9a: 881b ldrh r3, [r3, #0]
8007b9c: b29b uxth r3, r3
8007b9e: f3c3 0309 ubfx r3, r3, #0, #10
8007ba2: b29a uxth r2, r3
8007ba4: 6c7b ldr r3, [r7, #68] @ 0x44
8007ba6: 801a strh r2, [r3, #0]
8007ba8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007bac: 2b3e cmp r3, #62 @ 0x3e
8007bae: d921 bls.n 8007bf4 <USB_EPStartXfer+0x5f8>
8007bb0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007bb4: 095b lsrs r3, r3, #5
8007bb6: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007bba: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007bbe: f003 031f and.w r3, r3, #31
8007bc2: 2b00 cmp r3, #0
8007bc4: d104 bne.n 8007bd0 <USB_EPStartXfer+0x5d4>
8007bc6: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007bca: 3b01 subs r3, #1
8007bcc: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007bd0: 6c7b ldr r3, [r7, #68] @ 0x44
8007bd2: 881b ldrh r3, [r3, #0]
8007bd4: b29a uxth r2, r3
8007bd6: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007bda: b29b uxth r3, r3
8007bdc: 029b lsls r3, r3, #10
8007bde: b29b uxth r3, r3
8007be0: 4313 orrs r3, r2
8007be2: b29b uxth r3, r3
8007be4: ea6f 4343 mvn.w r3, r3, lsl #17
8007be8: ea6f 4353 mvn.w r3, r3, lsr #17
8007bec: b29a uxth r2, r3
8007bee: 6c7b ldr r3, [r7, #68] @ 0x44
8007bf0: 801a strh r2, [r3, #0]
8007bf2: e056 b.n 8007ca2 <USB_EPStartXfer+0x6a6>
8007bf4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007bf8: 2b00 cmp r3, #0
8007bfa: d10a bne.n 8007c12 <USB_EPStartXfer+0x616>
8007bfc: 6c7b ldr r3, [r7, #68] @ 0x44
8007bfe: 881b ldrh r3, [r3, #0]
8007c00: b29b uxth r3, r3
8007c02: ea6f 4343 mvn.w r3, r3, lsl #17
8007c06: ea6f 4353 mvn.w r3, r3, lsr #17
8007c0a: b29a uxth r2, r3
8007c0c: 6c7b ldr r3, [r7, #68] @ 0x44
8007c0e: 801a strh r2, [r3, #0]
8007c10: e047 b.n 8007ca2 <USB_EPStartXfer+0x6a6>
8007c12: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007c16: 085b lsrs r3, r3, #1
8007c18: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007c1c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007c20: f003 0301 and.w r3, r3, #1
8007c24: 2b00 cmp r3, #0
8007c26: d004 beq.n 8007c32 <USB_EPStartXfer+0x636>
8007c28: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007c2c: 3301 adds r3, #1
8007c2e: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8007c32: 6c7b ldr r3, [r7, #68] @ 0x44
8007c34: 881b ldrh r3, [r3, #0]
8007c36: b29a uxth r2, r3
8007c38: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8007c3c: b29b uxth r3, r3
8007c3e: 029b lsls r3, r3, #10
8007c40: b29b uxth r3, r3
8007c42: 4313 orrs r3, r2
8007c44: b29a uxth r2, r3
8007c46: 6c7b ldr r3, [r7, #68] @ 0x44
8007c48: 801a strh r2, [r3, #0]
8007c4a: e02a b.n 8007ca2 <USB_EPStartXfer+0x6a6>
8007c4c: f507 7384 add.w r3, r7, #264 @ 0x108
8007c50: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007c54: 681b ldr r3, [r3, #0]
8007c56: 785b ldrb r3, [r3, #1]
8007c58: 2b01 cmp r3, #1
8007c5a: d122 bne.n 8007ca2 <USB_EPStartXfer+0x6a6>
8007c5c: f507 7384 add.w r3, r7, #264 @ 0x108
8007c60: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007c64: 681b ldr r3, [r3, #0]
8007c66: 653b str r3, [r7, #80] @ 0x50
8007c68: f507 7384 add.w r3, r7, #264 @ 0x108
8007c6c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007c70: 681b ldr r3, [r3, #0]
8007c72: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007c76: b29b uxth r3, r3
8007c78: 461a mov r2, r3
8007c7a: 6d3b ldr r3, [r7, #80] @ 0x50
8007c7c: 4413 add r3, r2
8007c7e: 653b str r3, [r7, #80] @ 0x50
8007c80: f507 7384 add.w r3, r7, #264 @ 0x108
8007c84: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007c88: 681b ldr r3, [r3, #0]
8007c8a: 781b ldrb r3, [r3, #0]
8007c8c: 011a lsls r2, r3, #4
8007c8e: 6d3b ldr r3, [r7, #80] @ 0x50
8007c90: 4413 add r3, r2
8007c92: f203 4304 addw r3, r3, #1028 @ 0x404
8007c96: 64fb str r3, [r7, #76] @ 0x4c
8007c98: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007c9c: b29a uxth r2, r3
8007c9e: 6cfb ldr r3, [r7, #76] @ 0x4c
8007ca0: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8007ca2: f507 7384 add.w r3, r7, #264 @ 0x108
8007ca6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007caa: 681b ldr r3, [r3, #0]
8007cac: 891b ldrh r3, [r3, #8]
8007cae: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007cb2: f507 7384 add.w r3, r7, #264 @ 0x108
8007cb6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cba: 681b ldr r3, [r3, #0]
8007cbc: 6959 ldr r1, [r3, #20]
8007cbe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007cc2: b29b uxth r3, r3
8007cc4: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007cc8: f507 7084 add.w r0, r7, #264 @ 0x108
8007ccc: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007cd0: 6800 ldr r0, [r0, #0]
8007cd2: f001 f982 bl 8008fda <USB_WritePMA>
ep->xfer_buff += len;
8007cd6: f507 7384 add.w r3, r7, #264 @ 0x108
8007cda: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cde: 681b ldr r3, [r3, #0]
8007ce0: 695a ldr r2, [r3, #20]
8007ce2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007ce6: 441a add r2, r3
8007ce8: f507 7384 add.w r3, r7, #264 @ 0x108
8007cec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cf0: 681b ldr r3, [r3, #0]
8007cf2: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8007cf4: f507 7384 add.w r3, r7, #264 @ 0x108
8007cf8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007cfc: 681b ldr r3, [r3, #0]
8007cfe: 6a1a ldr r2, [r3, #32]
8007d00: f507 7384 add.w r3, r7, #264 @ 0x108
8007d04: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d08: 681b ldr r3, [r3, #0]
8007d0a: 691b ldr r3, [r3, #16]
8007d0c: 429a cmp r2, r3
8007d0e: d90f bls.n 8007d30 <USB_EPStartXfer+0x734>
{
ep->xfer_len_db -= len;
8007d10: f507 7384 add.w r3, r7, #264 @ 0x108
8007d14: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d18: 681b ldr r3, [r3, #0]
8007d1a: 6a1a ldr r2, [r3, #32]
8007d1c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007d20: 1ad2 subs r2, r2, r3
8007d22: f507 7384 add.w r3, r7, #264 @ 0x108
8007d26: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d2a: 681b ldr r3, [r3, #0]
8007d2c: 621a str r2, [r3, #32]
8007d2e: e00e b.n 8007d4e <USB_EPStartXfer+0x752>
}
else
{
len = ep->xfer_len_db;
8007d30: f507 7384 add.w r3, r7, #264 @ 0x108
8007d34: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d38: 681b ldr r3, [r3, #0]
8007d3a: 6a1b ldr r3, [r3, #32]
8007d3c: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
8007d40: f507 7384 add.w r3, r7, #264 @ 0x108
8007d44: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d48: 681b ldr r3, [r3, #0]
8007d4a: 2200 movs r2, #0
8007d4c: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8007d4e: f507 7384 add.w r3, r7, #264 @ 0x108
8007d52: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007d56: 681b ldr r3, [r3, #0]
8007d58: 643b str r3, [r7, #64] @ 0x40
8007d5a: f507 7384 add.w r3, r7, #264 @ 0x108
8007d5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d62: 681b ldr r3, [r3, #0]
8007d64: 785b ldrb r3, [r3, #1]
8007d66: 2b00 cmp r3, #0
8007d68: d177 bne.n 8007e5a <USB_EPStartXfer+0x85e>
8007d6a: f507 7384 add.w r3, r7, #264 @ 0x108
8007d6e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007d72: 681b ldr r3, [r3, #0]
8007d74: 63bb str r3, [r7, #56] @ 0x38
8007d76: f507 7384 add.w r3, r7, #264 @ 0x108
8007d7a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007d7e: 681b ldr r3, [r3, #0]
8007d80: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007d84: b29b uxth r3, r3
8007d86: 461a mov r2, r3
8007d88: 6bbb ldr r3, [r7, #56] @ 0x38
8007d8a: 4413 add r3, r2
8007d8c: 63bb str r3, [r7, #56] @ 0x38
8007d8e: f507 7384 add.w r3, r7, #264 @ 0x108
8007d92: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007d96: 681b ldr r3, [r3, #0]
8007d98: 781b ldrb r3, [r3, #0]
8007d9a: 011a lsls r2, r3, #4
8007d9c: 6bbb ldr r3, [r7, #56] @ 0x38
8007d9e: 4413 add r3, r2
8007da0: f203 430c addw r3, r3, #1036 @ 0x40c
8007da4: 637b str r3, [r7, #52] @ 0x34
8007da6: 6b7b ldr r3, [r7, #52] @ 0x34
8007da8: 881b ldrh r3, [r3, #0]
8007daa: b29b uxth r3, r3
8007dac: f3c3 0309 ubfx r3, r3, #0, #10
8007db0: b29a uxth r2, r3
8007db2: 6b7b ldr r3, [r7, #52] @ 0x34
8007db4: 801a strh r2, [r3, #0]
8007db6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007dba: 2b3e cmp r3, #62 @ 0x3e
8007dbc: d921 bls.n 8007e02 <USB_EPStartXfer+0x806>
8007dbe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007dc2: 095b lsrs r3, r3, #5
8007dc4: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007dc8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007dcc: f003 031f and.w r3, r3, #31
8007dd0: 2b00 cmp r3, #0
8007dd2: d104 bne.n 8007dde <USB_EPStartXfer+0x7e2>
8007dd4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007dd8: 3b01 subs r3, #1
8007dda: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007dde: 6b7b ldr r3, [r7, #52] @ 0x34
8007de0: 881b ldrh r3, [r3, #0]
8007de2: b29a uxth r2, r3
8007de4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007de8: b29b uxth r3, r3
8007dea: 029b lsls r3, r3, #10
8007dec: b29b uxth r3, r3
8007dee: 4313 orrs r3, r2
8007df0: b29b uxth r3, r3
8007df2: ea6f 4343 mvn.w r3, r3, lsl #17
8007df6: ea6f 4353 mvn.w r3, r3, lsr #17
8007dfa: b29a uxth r2, r3
8007dfc: 6b7b ldr r3, [r7, #52] @ 0x34
8007dfe: 801a strh r2, [r3, #0]
8007e00: e050 b.n 8007ea4 <USB_EPStartXfer+0x8a8>
8007e02: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e06: 2b00 cmp r3, #0
8007e08: d10a bne.n 8007e20 <USB_EPStartXfer+0x824>
8007e0a: 6b7b ldr r3, [r7, #52] @ 0x34
8007e0c: 881b ldrh r3, [r3, #0]
8007e0e: b29b uxth r3, r3
8007e10: ea6f 4343 mvn.w r3, r3, lsl #17
8007e14: ea6f 4353 mvn.w r3, r3, lsr #17
8007e18: b29a uxth r2, r3
8007e1a: 6b7b ldr r3, [r7, #52] @ 0x34
8007e1c: 801a strh r2, [r3, #0]
8007e1e: e041 b.n 8007ea4 <USB_EPStartXfer+0x8a8>
8007e20: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e24: 085b lsrs r3, r3, #1
8007e26: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007e2a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e2e: f003 0301 and.w r3, r3, #1
8007e32: 2b00 cmp r3, #0
8007e34: d004 beq.n 8007e40 <USB_EPStartXfer+0x844>
8007e36: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007e3a: 3301 adds r3, #1
8007e3c: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8007e40: 6b7b ldr r3, [r7, #52] @ 0x34
8007e42: 881b ldrh r3, [r3, #0]
8007e44: b29a uxth r2, r3
8007e46: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8007e4a: b29b uxth r3, r3
8007e4c: 029b lsls r3, r3, #10
8007e4e: b29b uxth r3, r3
8007e50: 4313 orrs r3, r2
8007e52: b29a uxth r2, r3
8007e54: 6b7b ldr r3, [r7, #52] @ 0x34
8007e56: 801a strh r2, [r3, #0]
8007e58: e024 b.n 8007ea4 <USB_EPStartXfer+0x8a8>
8007e5a: f507 7384 add.w r3, r7, #264 @ 0x108
8007e5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007e62: 681b ldr r3, [r3, #0]
8007e64: 785b ldrb r3, [r3, #1]
8007e66: 2b01 cmp r3, #1
8007e68: d11c bne.n 8007ea4 <USB_EPStartXfer+0x8a8>
8007e6a: f507 7384 add.w r3, r7, #264 @ 0x108
8007e6e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007e72: 681b ldr r3, [r3, #0]
8007e74: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007e78: b29b uxth r3, r3
8007e7a: 461a mov r2, r3
8007e7c: 6c3b ldr r3, [r7, #64] @ 0x40
8007e7e: 4413 add r3, r2
8007e80: 643b str r3, [r7, #64] @ 0x40
8007e82: f507 7384 add.w r3, r7, #264 @ 0x108
8007e86: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007e8a: 681b ldr r3, [r3, #0]
8007e8c: 781b ldrb r3, [r3, #0]
8007e8e: 011a lsls r2, r3, #4
8007e90: 6c3b ldr r3, [r7, #64] @ 0x40
8007e92: 4413 add r3, r2
8007e94: f203 430c addw r3, r3, #1036 @ 0x40c
8007e98: 63fb str r3, [r7, #60] @ 0x3c
8007e9a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007e9e: b29a uxth r2, r3
8007ea0: 6bfb ldr r3, [r7, #60] @ 0x3c
8007ea2: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8007ea4: f507 7384 add.w r3, r7, #264 @ 0x108
8007ea8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007eac: 681b ldr r3, [r3, #0]
8007eae: 895b ldrh r3, [r3, #10]
8007eb0: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007eb4: f507 7384 add.w r3, r7, #264 @ 0x108
8007eb8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007ebc: 681b ldr r3, [r3, #0]
8007ebe: 6959 ldr r1, [r3, #20]
8007ec0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007ec4: b29b uxth r3, r3
8007ec6: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007eca: f507 7084 add.w r0, r7, #264 @ 0x108
8007ece: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007ed2: 6800 ldr r0, [r0, #0]
8007ed4: f001 f881 bl 8008fda <USB_WritePMA>
8007ed8: e227 b.n 800832a <USB_EPStartXfer+0xd2e>
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
8007eda: f507 7384 add.w r3, r7, #264 @ 0x108
8007ede: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007ee2: 681b ldr r3, [r3, #0]
8007ee4: 6a1b ldr r3, [r3, #32]
8007ee6: f8c7 3104 str.w r3, [r7, #260] @ 0x104
/* disable double buffer mode for Bulk endpoint */
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
8007eea: f507 7384 add.w r3, r7, #264 @ 0x108
8007eee: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007ef2: 681a ldr r2, [r3, #0]
8007ef4: f507 7384 add.w r3, r7, #264 @ 0x108
8007ef8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007efc: 681b ldr r3, [r3, #0]
8007efe: 781b ldrb r3, [r3, #0]
8007f00: 009b lsls r3, r3, #2
8007f02: 4413 add r3, r2
8007f04: 881b ldrh r3, [r3, #0]
8007f06: b29b uxth r3, r3
8007f08: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8007f0c: f023 0370 bic.w r3, r3, #112 @ 0x70
8007f10: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8007f14: f507 7384 add.w r3, r7, #264 @ 0x108
8007f18: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f1c: 681a ldr r2, [r3, #0]
8007f1e: f507 7384 add.w r3, r7, #264 @ 0x108
8007f22: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007f26: 681b ldr r3, [r3, #0]
8007f28: 781b ldrb r3, [r3, #0]
8007f2a: 009b lsls r3, r3, #2
8007f2c: 441a add r2, r3
8007f2e: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
8007f32: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007f36: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007f3a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007f3e: f043 0380 orr.w r3, r3, #128 @ 0x80
8007f42: b29b uxth r3, r3
8007f44: 8013 strh r3, [r2, #0]
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
8007f46: f507 7384 add.w r3, r7, #264 @ 0x108
8007f4a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f4e: 681b ldr r3, [r3, #0]
8007f50: 65fb str r3, [r7, #92] @ 0x5c
8007f52: f507 7384 add.w r3, r7, #264 @ 0x108
8007f56: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007f5a: 681b ldr r3, [r3, #0]
8007f5c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007f60: b29b uxth r3, r3
8007f62: 461a mov r2, r3
8007f64: 6dfb ldr r3, [r7, #92] @ 0x5c
8007f66: 4413 add r3, r2
8007f68: 65fb str r3, [r7, #92] @ 0x5c
8007f6a: f507 7384 add.w r3, r7, #264 @ 0x108
8007f6e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007f72: 681b ldr r3, [r3, #0]
8007f74: 781b ldrb r3, [r3, #0]
8007f76: 011a lsls r2, r3, #4
8007f78: 6dfb ldr r3, [r7, #92] @ 0x5c
8007f7a: 4413 add r3, r2
8007f7c: f203 4304 addw r3, r3, #1028 @ 0x404
8007f80: 65bb str r3, [r7, #88] @ 0x58
8007f82: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007f86: b29a uxth r2, r3
8007f88: 6dbb ldr r3, [r7, #88] @ 0x58
8007f8a: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8007f8c: f507 7384 add.w r3, r7, #264 @ 0x108
8007f90: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007f94: 681b ldr r3, [r3, #0]
8007f96: 891b ldrh r3, [r3, #8]
8007f98: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8007f9c: f507 7384 add.w r3, r7, #264 @ 0x108
8007fa0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007fa4: 681b ldr r3, [r3, #0]
8007fa6: 6959 ldr r1, [r3, #20]
8007fa8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007fac: b29b uxth r3, r3
8007fae: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8007fb2: f507 7084 add.w r0, r7, #264 @ 0x108
8007fb6: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8007fba: 6800 ldr r0, [r0, #0]
8007fbc: f001 f80d bl 8008fda <USB_WritePMA>
8007fc0: e1b3 b.n 800832a <USB_EPStartXfer+0xd2e>
}
}
else /* manage isochronous double buffer IN mode */
{
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
8007fc2: f507 7384 add.w r3, r7, #264 @ 0x108
8007fc6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007fca: 681b ldr r3, [r3, #0]
8007fcc: 6a1a ldr r2, [r3, #32]
8007fce: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8007fd2: 1ad2 subs r2, r2, r3
8007fd4: f507 7384 add.w r3, r7, #264 @ 0x108
8007fd8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007fdc: 681b ldr r3, [r3, #0]
8007fde: 621a str r2, [r3, #32]
/* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8007fe0: f507 7384 add.w r3, r7, #264 @ 0x108
8007fe4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8007fe8: 681a ldr r2, [r3, #0]
8007fea: f507 7384 add.w r3, r7, #264 @ 0x108
8007fee: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8007ff2: 681b ldr r3, [r3, #0]
8007ff4: 781b ldrb r3, [r3, #0]
8007ff6: 009b lsls r3, r3, #2
8007ff8: 4413 add r3, r2
8007ffa: 881b ldrh r3, [r3, #0]
8007ffc: b29b uxth r3, r3
8007ffe: f003 0340 and.w r3, r3, #64 @ 0x40
8008002: 2b00 cmp r3, #0
8008004: f000 80c6 beq.w 8008194 <USB_EPStartXfer+0xb98>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8008008: f507 7384 add.w r3, r7, #264 @ 0x108
800800c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008010: 681b ldr r3, [r3, #0]
8008012: 673b str r3, [r7, #112] @ 0x70
8008014: f507 7384 add.w r3, r7, #264 @ 0x108
8008018: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800801c: 681b ldr r3, [r3, #0]
800801e: 785b ldrb r3, [r3, #1]
8008020: 2b00 cmp r3, #0
8008022: d177 bne.n 8008114 <USB_EPStartXfer+0xb18>
8008024: f507 7384 add.w r3, r7, #264 @ 0x108
8008028: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800802c: 681b ldr r3, [r3, #0]
800802e: 66bb str r3, [r7, #104] @ 0x68
8008030: f507 7384 add.w r3, r7, #264 @ 0x108
8008034: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008038: 681b ldr r3, [r3, #0]
800803a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800803e: b29b uxth r3, r3
8008040: 461a mov r2, r3
8008042: 6ebb ldr r3, [r7, #104] @ 0x68
8008044: 4413 add r3, r2
8008046: 66bb str r3, [r7, #104] @ 0x68
8008048: f507 7384 add.w r3, r7, #264 @ 0x108
800804c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008050: 681b ldr r3, [r3, #0]
8008052: 781b ldrb r3, [r3, #0]
8008054: 011a lsls r2, r3, #4
8008056: 6ebb ldr r3, [r7, #104] @ 0x68
8008058: 4413 add r3, r2
800805a: f203 430c addw r3, r3, #1036 @ 0x40c
800805e: 667b str r3, [r7, #100] @ 0x64
8008060: 6e7b ldr r3, [r7, #100] @ 0x64
8008062: 881b ldrh r3, [r3, #0]
8008064: b29b uxth r3, r3
8008066: f3c3 0309 ubfx r3, r3, #0, #10
800806a: b29a uxth r2, r3
800806c: 6e7b ldr r3, [r7, #100] @ 0x64
800806e: 801a strh r2, [r3, #0]
8008070: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008074: 2b3e cmp r3, #62 @ 0x3e
8008076: d921 bls.n 80080bc <USB_EPStartXfer+0xac0>
8008078: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800807c: 095b lsrs r3, r3, #5
800807e: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8008082: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008086: f003 031f and.w r3, r3, #31
800808a: 2b00 cmp r3, #0
800808c: d104 bne.n 8008098 <USB_EPStartXfer+0xa9c>
800808e: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8008092: 3b01 subs r3, #1
8008094: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8008098: 6e7b ldr r3, [r7, #100] @ 0x64
800809a: 881b ldrh r3, [r3, #0]
800809c: b29a uxth r2, r3
800809e: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
80080a2: b29b uxth r3, r3
80080a4: 029b lsls r3, r3, #10
80080a6: b29b uxth r3, r3
80080a8: 4313 orrs r3, r2
80080aa: b29b uxth r3, r3
80080ac: ea6f 4343 mvn.w r3, r3, lsl #17
80080b0: ea6f 4353 mvn.w r3, r3, lsr #17
80080b4: b29a uxth r2, r3
80080b6: 6e7b ldr r3, [r7, #100] @ 0x64
80080b8: 801a strh r2, [r3, #0]
80080ba: e050 b.n 800815e <USB_EPStartXfer+0xb62>
80080bc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080c0: 2b00 cmp r3, #0
80080c2: d10a bne.n 80080da <USB_EPStartXfer+0xade>
80080c4: 6e7b ldr r3, [r7, #100] @ 0x64
80080c6: 881b ldrh r3, [r3, #0]
80080c8: b29b uxth r3, r3
80080ca: ea6f 4343 mvn.w r3, r3, lsl #17
80080ce: ea6f 4353 mvn.w r3, r3, lsr #17
80080d2: b29a uxth r2, r3
80080d4: 6e7b ldr r3, [r7, #100] @ 0x64
80080d6: 801a strh r2, [r3, #0]
80080d8: e041 b.n 800815e <USB_EPStartXfer+0xb62>
80080da: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080de: 085b lsrs r3, r3, #1
80080e0: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
80080e4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80080e8: f003 0301 and.w r3, r3, #1
80080ec: 2b00 cmp r3, #0
80080ee: d004 beq.n 80080fa <USB_EPStartXfer+0xafe>
80080f0: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
80080f4: 3301 adds r3, #1
80080f6: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
80080fa: 6e7b ldr r3, [r7, #100] @ 0x64
80080fc: 881b ldrh r3, [r3, #0]
80080fe: b29a uxth r2, r3
8008100: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8008104: b29b uxth r3, r3
8008106: 029b lsls r3, r3, #10
8008108: b29b uxth r3, r3
800810a: 4313 orrs r3, r2
800810c: b29a uxth r2, r3
800810e: 6e7b ldr r3, [r7, #100] @ 0x64
8008110: 801a strh r2, [r3, #0]
8008112: e024 b.n 800815e <USB_EPStartXfer+0xb62>
8008114: f507 7384 add.w r3, r7, #264 @ 0x108
8008118: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800811c: 681b ldr r3, [r3, #0]
800811e: 785b ldrb r3, [r3, #1]
8008120: 2b01 cmp r3, #1
8008122: d11c bne.n 800815e <USB_EPStartXfer+0xb62>
8008124: f507 7384 add.w r3, r7, #264 @ 0x108
8008128: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800812c: 681b ldr r3, [r3, #0]
800812e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008132: b29b uxth r3, r3
8008134: 461a mov r2, r3
8008136: 6f3b ldr r3, [r7, #112] @ 0x70
8008138: 4413 add r3, r2
800813a: 673b str r3, [r7, #112] @ 0x70
800813c: f507 7384 add.w r3, r7, #264 @ 0x108
8008140: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008144: 681b ldr r3, [r3, #0]
8008146: 781b ldrb r3, [r3, #0]
8008148: 011a lsls r2, r3, #4
800814a: 6f3b ldr r3, [r7, #112] @ 0x70
800814c: 4413 add r3, r2
800814e: f203 430c addw r3, r3, #1036 @ 0x40c
8008152: 66fb str r3, [r7, #108] @ 0x6c
8008154: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008158: b29a uxth r2, r3
800815a: 6efb ldr r3, [r7, #108] @ 0x6c
800815c: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800815e: f507 7384 add.w r3, r7, #264 @ 0x108
8008162: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008166: 681b ldr r3, [r3, #0]
8008168: 895b ldrh r3, [r3, #10]
800816a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800816e: f507 7384 add.w r3, r7, #264 @ 0x108
8008172: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008176: 681b ldr r3, [r3, #0]
8008178: 6959 ldr r1, [r3, #20]
800817a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800817e: b29b uxth r3, r3
8008180: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8008184: f507 7084 add.w r0, r7, #264 @ 0x108
8008188: f5a0 7082 sub.w r0, r0, #260 @ 0x104
800818c: 6800 ldr r0, [r0, #0]
800818e: f000 ff24 bl 8008fda <USB_WritePMA>
8008192: e0ca b.n 800832a <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8008194: f507 7384 add.w r3, r7, #264 @ 0x108
8008198: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800819c: 681b ldr r3, [r3, #0]
800819e: 785b ldrb r3, [r3, #1]
80081a0: 2b00 cmp r3, #0
80081a2: d177 bne.n 8008294 <USB_EPStartXfer+0xc98>
80081a4: f507 7384 add.w r3, r7, #264 @ 0x108
80081a8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80081ac: 681b ldr r3, [r3, #0]
80081ae: 67fb str r3, [r7, #124] @ 0x7c
80081b0: f507 7384 add.w r3, r7, #264 @ 0x108
80081b4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80081b8: 681b ldr r3, [r3, #0]
80081ba: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80081be: b29b uxth r3, r3
80081c0: 461a mov r2, r3
80081c2: 6ffb ldr r3, [r7, #124] @ 0x7c
80081c4: 4413 add r3, r2
80081c6: 67fb str r3, [r7, #124] @ 0x7c
80081c8: f507 7384 add.w r3, r7, #264 @ 0x108
80081cc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80081d0: 681b ldr r3, [r3, #0]
80081d2: 781b ldrb r3, [r3, #0]
80081d4: 011a lsls r2, r3, #4
80081d6: 6ffb ldr r3, [r7, #124] @ 0x7c
80081d8: 4413 add r3, r2
80081da: f203 4304 addw r3, r3, #1028 @ 0x404
80081de: 67bb str r3, [r7, #120] @ 0x78
80081e0: 6fbb ldr r3, [r7, #120] @ 0x78
80081e2: 881b ldrh r3, [r3, #0]
80081e4: b29b uxth r3, r3
80081e6: f3c3 0309 ubfx r3, r3, #0, #10
80081ea: b29a uxth r2, r3
80081ec: 6fbb ldr r3, [r7, #120] @ 0x78
80081ee: 801a strh r2, [r3, #0]
80081f0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80081f4: 2b3e cmp r3, #62 @ 0x3e
80081f6: d921 bls.n 800823c <USB_EPStartXfer+0xc40>
80081f8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80081fc: 095b lsrs r3, r3, #5
80081fe: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8008202: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008206: f003 031f and.w r3, r3, #31
800820a: 2b00 cmp r3, #0
800820c: d104 bne.n 8008218 <USB_EPStartXfer+0xc1c>
800820e: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8008212: 3b01 subs r3, #1
8008214: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8008218: 6fbb ldr r3, [r7, #120] @ 0x78
800821a: 881b ldrh r3, [r3, #0]
800821c: b29a uxth r2, r3
800821e: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8008222: b29b uxth r3, r3
8008224: 029b lsls r3, r3, #10
8008226: b29b uxth r3, r3
8008228: 4313 orrs r3, r2
800822a: b29b uxth r3, r3
800822c: ea6f 4343 mvn.w r3, r3, lsl #17
8008230: ea6f 4353 mvn.w r3, r3, lsr #17
8008234: b29a uxth r2, r3
8008236: 6fbb ldr r3, [r7, #120] @ 0x78
8008238: 801a strh r2, [r3, #0]
800823a: e05c b.n 80082f6 <USB_EPStartXfer+0xcfa>
800823c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008240: 2b00 cmp r3, #0
8008242: d10a bne.n 800825a <USB_EPStartXfer+0xc5e>
8008244: 6fbb ldr r3, [r7, #120] @ 0x78
8008246: 881b ldrh r3, [r3, #0]
8008248: b29b uxth r3, r3
800824a: ea6f 4343 mvn.w r3, r3, lsl #17
800824e: ea6f 4353 mvn.w r3, r3, lsr #17
8008252: b29a uxth r2, r3
8008254: 6fbb ldr r3, [r7, #120] @ 0x78
8008256: 801a strh r2, [r3, #0]
8008258: e04d b.n 80082f6 <USB_EPStartXfer+0xcfa>
800825a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800825e: 085b lsrs r3, r3, #1
8008260: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8008264: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008268: f003 0301 and.w r3, r3, #1
800826c: 2b00 cmp r3, #0
800826e: d004 beq.n 800827a <USB_EPStartXfer+0xc7e>
8008270: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8008274: 3301 adds r3, #1
8008276: f8c7 30ec str.w r3, [r7, #236] @ 0xec
800827a: 6fbb ldr r3, [r7, #120] @ 0x78
800827c: 881b ldrh r3, [r3, #0]
800827e: b29a uxth r2, r3
8008280: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8008284: b29b uxth r3, r3
8008286: 029b lsls r3, r3, #10
8008288: b29b uxth r3, r3
800828a: 4313 orrs r3, r2
800828c: b29a uxth r2, r3
800828e: 6fbb ldr r3, [r7, #120] @ 0x78
8008290: 801a strh r2, [r3, #0]
8008292: e030 b.n 80082f6 <USB_EPStartXfer+0xcfa>
8008294: f507 7384 add.w r3, r7, #264 @ 0x108
8008298: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800829c: 681b ldr r3, [r3, #0]
800829e: 785b ldrb r3, [r3, #1]
80082a0: 2b01 cmp r3, #1
80082a2: d128 bne.n 80082f6 <USB_EPStartXfer+0xcfa>
80082a4: f507 7384 add.w r3, r7, #264 @ 0x108
80082a8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80082ac: 681b ldr r3, [r3, #0]
80082ae: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80082b2: f507 7384 add.w r3, r7, #264 @ 0x108
80082b6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80082ba: 681b ldr r3, [r3, #0]
80082bc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80082c0: b29b uxth r3, r3
80082c2: 461a mov r2, r3
80082c4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
80082c8: 4413 add r3, r2
80082ca: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80082ce: f507 7384 add.w r3, r7, #264 @ 0x108
80082d2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80082d6: 681b ldr r3, [r3, #0]
80082d8: 781b ldrb r3, [r3, #0]
80082da: 011a lsls r2, r3, #4
80082dc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
80082e0: 4413 add r3, r2
80082e2: f203 4304 addw r3, r3, #1028 @ 0x404
80082e6: f8c7 3080 str.w r3, [r7, #128] @ 0x80
80082ea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80082ee: b29a uxth r2, r3
80082f0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80082f4: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
80082f6: f507 7384 add.w r3, r7, #264 @ 0x108
80082fa: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80082fe: 681b ldr r3, [r3, #0]
8008300: 891b ldrh r3, [r3, #8]
8008302: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8008306: f507 7384 add.w r3, r7, #264 @ 0x108
800830a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800830e: 681b ldr r3, [r3, #0]
8008310: 6959 ldr r1, [r3, #20]
8008312: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008316: b29b uxth r3, r3
8008318: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800831c: f507 7084 add.w r0, r7, #264 @ 0x108
8008320: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8008324: 6800 ldr r0, [r0, #0]
8008326: f000 fe58 bl 8008fda <USB_WritePMA>
}
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
800832a: f507 7384 add.w r3, r7, #264 @ 0x108
800832e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008332: 681a ldr r2, [r3, #0]
8008334: f507 7384 add.w r3, r7, #264 @ 0x108
8008338: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800833c: 681b ldr r3, [r3, #0]
800833e: 781b ldrb r3, [r3, #0]
8008340: 009b lsls r3, r3, #2
8008342: 4413 add r3, r2
8008344: 881b ldrh r3, [r3, #0]
8008346: b29b uxth r3, r3
8008348: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800834c: f023 0340 bic.w r3, r3, #64 @ 0x40
8008350: 817b strh r3, [r7, #10]
8008352: 897b ldrh r3, [r7, #10]
8008354: f083 0310 eor.w r3, r3, #16
8008358: 817b strh r3, [r7, #10]
800835a: 897b ldrh r3, [r7, #10]
800835c: f083 0320 eor.w r3, r3, #32
8008360: 817b strh r3, [r7, #10]
8008362: f507 7384 add.w r3, r7, #264 @ 0x108
8008366: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800836a: 681a ldr r2, [r3, #0]
800836c: f507 7384 add.w r3, r7, #264 @ 0x108
8008370: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008374: 681b ldr r3, [r3, #0]
8008376: 781b ldrb r3, [r3, #0]
8008378: 009b lsls r3, r3, #2
800837a: 441a add r2, r3
800837c: 897b ldrh r3, [r7, #10]
800837e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008382: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008386: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800838a: f043 0380 orr.w r3, r3, #128 @ 0x80
800838e: b29b uxth r3, r3
8008390: 8013 strh r3, [r2, #0]
8008392: f000 bcde b.w 8008d52 <USB_EPStartXfer+0x1756>
}
else /* OUT endpoint */
{
if (ep->doublebuffer == 0U)
8008396: f507 7384 add.w r3, r7, #264 @ 0x108
800839a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800839e: 681b ldr r3, [r3, #0]
80083a0: 7b1b ldrb r3, [r3, #12]
80083a2: 2b00 cmp r3, #0
80083a4: f040 80bb bne.w 800851e <USB_EPStartXfer+0xf22>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
80083a8: f507 7384 add.w r3, r7, #264 @ 0x108
80083ac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083b0: 681b ldr r3, [r3, #0]
80083b2: 699a ldr r2, [r3, #24]
80083b4: f507 7384 add.w r3, r7, #264 @ 0x108
80083b8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083bc: 681b ldr r3, [r3, #0]
80083be: 691b ldr r3, [r3, #16]
80083c0: 429a cmp r2, r3
80083c2: d917 bls.n 80083f4 <USB_EPStartXfer+0xdf8>
{
len = ep->maxpacket;
80083c4: f507 7384 add.w r3, r7, #264 @ 0x108
80083c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083cc: 681b ldr r3, [r3, #0]
80083ce: 691b ldr r3, [r3, #16]
80083d0: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
80083d4: f507 7384 add.w r3, r7, #264 @ 0x108
80083d8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083dc: 681b ldr r3, [r3, #0]
80083de: 699a ldr r2, [r3, #24]
80083e0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80083e4: 1ad2 subs r2, r2, r3
80083e6: f507 7384 add.w r3, r7, #264 @ 0x108
80083ea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083ee: 681b ldr r3, [r3, #0]
80083f0: 619a str r2, [r3, #24]
80083f2: e00e b.n 8008412 <USB_EPStartXfer+0xe16>
}
else
{
len = ep->xfer_len;
80083f4: f507 7384 add.w r3, r7, #264 @ 0x108
80083f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80083fc: 681b ldr r3, [r3, #0]
80083fe: 699b ldr r3, [r3, #24]
8008400: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
8008404: f507 7384 add.w r3, r7, #264 @ 0x108
8008408: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800840c: 681b ldr r3, [r3, #0]
800840e: 2200 movs r2, #0
8008410: 619a str r2, [r3, #24]
}
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
8008412: f507 7384 add.w r3, r7, #264 @ 0x108
8008416: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800841a: 681b ldr r3, [r3, #0]
800841c: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8008420: f507 7384 add.w r3, r7, #264 @ 0x108
8008424: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008428: 681b ldr r3, [r3, #0]
800842a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800842e: b29b uxth r3, r3
8008430: 461a mov r2, r3
8008432: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8008436: 4413 add r3, r2
8008438: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800843c: f507 7384 add.w r3, r7, #264 @ 0x108
8008440: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008444: 681b ldr r3, [r3, #0]
8008446: 781b ldrb r3, [r3, #0]
8008448: 011a lsls r2, r3, #4
800844a: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800844e: 4413 add r3, r2
8008450: f203 430c addw r3, r3, #1036 @ 0x40c
8008454: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8008458: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800845c: 881b ldrh r3, [r3, #0]
800845e: b29b uxth r3, r3
8008460: f3c3 0309 ubfx r3, r3, #0, #10
8008464: b29a uxth r2, r3
8008466: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800846a: 801a strh r2, [r3, #0]
800846c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008470: 2b3e cmp r3, #62 @ 0x3e
8008472: d924 bls.n 80084be <USB_EPStartXfer+0xec2>
8008474: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008478: 095b lsrs r3, r3, #5
800847a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
800847e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008482: f003 031f and.w r3, r3, #31
8008486: 2b00 cmp r3, #0
8008488: d104 bne.n 8008494 <USB_EPStartXfer+0xe98>
800848a: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
800848e: 3b01 subs r3, #1
8008490: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8008494: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8008498: 881b ldrh r3, [r3, #0]
800849a: b29a uxth r2, r3
800849c: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80084a0: b29b uxth r3, r3
80084a2: 029b lsls r3, r3, #10
80084a4: b29b uxth r3, r3
80084a6: 4313 orrs r3, r2
80084a8: b29b uxth r3, r3
80084aa: ea6f 4343 mvn.w r3, r3, lsl #17
80084ae: ea6f 4353 mvn.w r3, r3, lsr #17
80084b2: b29a uxth r2, r3
80084b4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80084b8: 801a strh r2, [r3, #0]
80084ba: f000 bc10 b.w 8008cde <USB_EPStartXfer+0x16e2>
80084be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084c2: 2b00 cmp r3, #0
80084c4: d10c bne.n 80084e0 <USB_EPStartXfer+0xee4>
80084c6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80084ca: 881b ldrh r3, [r3, #0]
80084cc: b29b uxth r3, r3
80084ce: ea6f 4343 mvn.w r3, r3, lsl #17
80084d2: ea6f 4353 mvn.w r3, r3, lsr #17
80084d6: b29a uxth r2, r3
80084d8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80084dc: 801a strh r2, [r3, #0]
80084de: e3fe b.n 8008cde <USB_EPStartXfer+0x16e2>
80084e0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084e4: 085b lsrs r3, r3, #1
80084e6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
80084ea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80084ee: f003 0301 and.w r3, r3, #1
80084f2: 2b00 cmp r3, #0
80084f4: d004 beq.n 8008500 <USB_EPStartXfer+0xf04>
80084f6: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80084fa: 3301 adds r3, #1
80084fc: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8008500: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8008504: 881b ldrh r3, [r3, #0]
8008506: b29a uxth r2, r3
8008508: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
800850c: b29b uxth r3, r3
800850e: 029b lsls r3, r3, #10
8008510: b29b uxth r3, r3
8008512: 4313 orrs r3, r2
8008514: b29a uxth r2, r3
8008516: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800851a: 801a strh r2, [r3, #0]
800851c: e3df b.n 8008cde <USB_EPStartXfer+0x16e2>
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
800851e: f507 7384 add.w r3, r7, #264 @ 0x108
8008522: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008526: 681b ldr r3, [r3, #0]
8008528: 78db ldrb r3, [r3, #3]
800852a: 2b02 cmp r3, #2
800852c: f040 8218 bne.w 8008960 <USB_EPStartXfer+0x1364>
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
8008530: f507 7384 add.w r3, r7, #264 @ 0x108
8008534: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008538: 681b ldr r3, [r3, #0]
800853a: 785b ldrb r3, [r3, #1]
800853c: 2b00 cmp r3, #0
800853e: f040 809d bne.w 800867c <USB_EPStartXfer+0x1080>
8008542: f507 7384 add.w r3, r7, #264 @ 0x108
8008546: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800854a: 681b ldr r3, [r3, #0]
800854c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8008550: f507 7384 add.w r3, r7, #264 @ 0x108
8008554: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008558: 681b ldr r3, [r3, #0]
800855a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800855e: b29b uxth r3, r3
8008560: 461a mov r2, r3
8008562: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8008566: 4413 add r3, r2
8008568: f8c7 30ac str.w r3, [r7, #172] @ 0xac
800856c: f507 7384 add.w r3, r7, #264 @ 0x108
8008570: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008574: 681b ldr r3, [r3, #0]
8008576: 781b ldrb r3, [r3, #0]
8008578: 011a lsls r2, r3, #4
800857a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800857e: 4413 add r3, r2
8008580: f203 4304 addw r3, r3, #1028 @ 0x404
8008584: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
8008588: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800858c: 881b ldrh r3, [r3, #0]
800858e: b29b uxth r3, r3
8008590: f3c3 0309 ubfx r3, r3, #0, #10
8008594: b29a uxth r2, r3
8008596: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800859a: 801a strh r2, [r3, #0]
800859c: f507 7384 add.w r3, r7, #264 @ 0x108
80085a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085a4: 681b ldr r3, [r3, #0]
80085a6: 691b ldr r3, [r3, #16]
80085a8: 2b3e cmp r3, #62 @ 0x3e
80085aa: d92b bls.n 8008604 <USB_EPStartXfer+0x1008>
80085ac: f507 7384 add.w r3, r7, #264 @ 0x108
80085b0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085b4: 681b ldr r3, [r3, #0]
80085b6: 691b ldr r3, [r3, #16]
80085b8: 095b lsrs r3, r3, #5
80085ba: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80085be: f507 7384 add.w r3, r7, #264 @ 0x108
80085c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80085c6: 681b ldr r3, [r3, #0]
80085c8: 691b ldr r3, [r3, #16]
80085ca: f003 031f and.w r3, r3, #31
80085ce: 2b00 cmp r3, #0
80085d0: d104 bne.n 80085dc <USB_EPStartXfer+0xfe0>
80085d2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80085d6: 3b01 subs r3, #1
80085d8: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80085dc: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80085e0: 881b ldrh r3, [r3, #0]
80085e2: b29a uxth r2, r3
80085e4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80085e8: b29b uxth r3, r3
80085ea: 029b lsls r3, r3, #10
80085ec: b29b uxth r3, r3
80085ee: 4313 orrs r3, r2
80085f0: b29b uxth r3, r3
80085f2: ea6f 4343 mvn.w r3, r3, lsl #17
80085f6: ea6f 4353 mvn.w r3, r3, lsr #17
80085fa: b29a uxth r2, r3
80085fc: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008600: 801a strh r2, [r3, #0]
8008602: e070 b.n 80086e6 <USB_EPStartXfer+0x10ea>
8008604: f507 7384 add.w r3, r7, #264 @ 0x108
8008608: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800860c: 681b ldr r3, [r3, #0]
800860e: 691b ldr r3, [r3, #16]
8008610: 2b00 cmp r3, #0
8008612: d10c bne.n 800862e <USB_EPStartXfer+0x1032>
8008614: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008618: 881b ldrh r3, [r3, #0]
800861a: b29b uxth r3, r3
800861c: ea6f 4343 mvn.w r3, r3, lsl #17
8008620: ea6f 4353 mvn.w r3, r3, lsr #17
8008624: b29a uxth r2, r3
8008626: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800862a: 801a strh r2, [r3, #0]
800862c: e05b b.n 80086e6 <USB_EPStartXfer+0x10ea>
800862e: f507 7384 add.w r3, r7, #264 @ 0x108
8008632: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008636: 681b ldr r3, [r3, #0]
8008638: 691b ldr r3, [r3, #16]
800863a: 085b lsrs r3, r3, #1
800863c: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
8008640: f507 7384 add.w r3, r7, #264 @ 0x108
8008644: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008648: 681b ldr r3, [r3, #0]
800864a: 691b ldr r3, [r3, #16]
800864c: f003 0301 and.w r3, r3, #1
8008650: 2b00 cmp r3, #0
8008652: d004 beq.n 800865e <USB_EPStartXfer+0x1062>
8008654: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8008658: 3301 adds r3, #1
800865a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
800865e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008662: 881b ldrh r3, [r3, #0]
8008664: b29a uxth r2, r3
8008666: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800866a: b29b uxth r3, r3
800866c: 029b lsls r3, r3, #10
800866e: b29b uxth r3, r3
8008670: 4313 orrs r3, r2
8008672: b29a uxth r2, r3
8008674: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8008678: 801a strh r2, [r3, #0]
800867a: e034 b.n 80086e6 <USB_EPStartXfer+0x10ea>
800867c: f507 7384 add.w r3, r7, #264 @ 0x108
8008680: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008684: 681b ldr r3, [r3, #0]
8008686: 785b ldrb r3, [r3, #1]
8008688: 2b01 cmp r3, #1
800868a: d12c bne.n 80086e6 <USB_EPStartXfer+0x10ea>
800868c: f507 7384 add.w r3, r7, #264 @ 0x108
8008690: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008694: 681b ldr r3, [r3, #0]
8008696: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
800869a: f507 7384 add.w r3, r7, #264 @ 0x108
800869e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80086a2: 681b ldr r3, [r3, #0]
80086a4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80086a8: b29b uxth r3, r3
80086aa: 461a mov r2, r3
80086ac: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80086b0: 4413 add r3, r2
80086b2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80086b6: f507 7384 add.w r3, r7, #264 @ 0x108
80086ba: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80086be: 681b ldr r3, [r3, #0]
80086c0: 781b ldrb r3, [r3, #0]
80086c2: 011a lsls r2, r3, #4
80086c4: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80086c8: 4413 add r3, r2
80086ca: f203 4304 addw r3, r3, #1028 @ 0x404
80086ce: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
80086d2: f507 7384 add.w r3, r7, #264 @ 0x108
80086d6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80086da: 681b ldr r3, [r3, #0]
80086dc: 691b ldr r3, [r3, #16]
80086de: b29a uxth r2, r3
80086e0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
80086e4: 801a strh r2, [r3, #0]
80086e6: f507 7384 add.w r3, r7, #264 @ 0x108
80086ea: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80086ee: 681b ldr r3, [r3, #0]
80086f0: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
80086f4: f507 7384 add.w r3, r7, #264 @ 0x108
80086f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80086fc: 681b ldr r3, [r3, #0]
80086fe: 785b ldrb r3, [r3, #1]
8008700: 2b00 cmp r3, #0
8008702: f040 809d bne.w 8008840 <USB_EPStartXfer+0x1244>
8008706: f507 7384 add.w r3, r7, #264 @ 0x108
800870a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800870e: 681b ldr r3, [r3, #0]
8008710: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8008714: f507 7384 add.w r3, r7, #264 @ 0x108
8008718: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800871c: 681b ldr r3, [r3, #0]
800871e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008722: b29b uxth r3, r3
8008724: 461a mov r2, r3
8008726: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800872a: 4413 add r3, r2
800872c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8008730: f507 7384 add.w r3, r7, #264 @ 0x108
8008734: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008738: 681b ldr r3, [r3, #0]
800873a: 781b ldrb r3, [r3, #0]
800873c: 011a lsls r2, r3, #4
800873e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8008742: 4413 add r3, r2
8008744: f203 430c addw r3, r3, #1036 @ 0x40c
8008748: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800874c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8008750: 881b ldrh r3, [r3, #0]
8008752: b29b uxth r3, r3
8008754: f3c3 0309 ubfx r3, r3, #0, #10
8008758: b29a uxth r2, r3
800875a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800875e: 801a strh r2, [r3, #0]
8008760: f507 7384 add.w r3, r7, #264 @ 0x108
8008764: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008768: 681b ldr r3, [r3, #0]
800876a: 691b ldr r3, [r3, #16]
800876c: 2b3e cmp r3, #62 @ 0x3e
800876e: d92b bls.n 80087c8 <USB_EPStartXfer+0x11cc>
8008770: f507 7384 add.w r3, r7, #264 @ 0x108
8008774: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008778: 681b ldr r3, [r3, #0]
800877a: 691b ldr r3, [r3, #16]
800877c: 095b lsrs r3, r3, #5
800877e: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8008782: f507 7384 add.w r3, r7, #264 @ 0x108
8008786: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800878a: 681b ldr r3, [r3, #0]
800878c: 691b ldr r3, [r3, #16]
800878e: f003 031f and.w r3, r3, #31
8008792: 2b00 cmp r3, #0
8008794: d104 bne.n 80087a0 <USB_EPStartXfer+0x11a4>
8008796: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800879a: 3b01 subs r3, #1
800879c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
80087a0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80087a4: 881b ldrh r3, [r3, #0]
80087a6: b29a uxth r2, r3
80087a8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80087ac: b29b uxth r3, r3
80087ae: 029b lsls r3, r3, #10
80087b0: b29b uxth r3, r3
80087b2: 4313 orrs r3, r2
80087b4: b29b uxth r3, r3
80087b6: ea6f 4343 mvn.w r3, r3, lsl #17
80087ba: ea6f 4353 mvn.w r3, r3, lsr #17
80087be: b29a uxth r2, r3
80087c0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80087c4: 801a strh r2, [r3, #0]
80087c6: e069 b.n 800889c <USB_EPStartXfer+0x12a0>
80087c8: f507 7384 add.w r3, r7, #264 @ 0x108
80087cc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80087d0: 681b ldr r3, [r3, #0]
80087d2: 691b ldr r3, [r3, #16]
80087d4: 2b00 cmp r3, #0
80087d6: d10c bne.n 80087f2 <USB_EPStartXfer+0x11f6>
80087d8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80087dc: 881b ldrh r3, [r3, #0]
80087de: b29b uxth r3, r3
80087e0: ea6f 4343 mvn.w r3, r3, lsl #17
80087e4: ea6f 4353 mvn.w r3, r3, lsr #17
80087e8: b29a uxth r2, r3
80087ea: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80087ee: 801a strh r2, [r3, #0]
80087f0: e054 b.n 800889c <USB_EPStartXfer+0x12a0>
80087f2: f507 7384 add.w r3, r7, #264 @ 0x108
80087f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80087fa: 681b ldr r3, [r3, #0]
80087fc: 691b ldr r3, [r3, #16]
80087fe: 085b lsrs r3, r3, #1
8008800: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8008804: f507 7384 add.w r3, r7, #264 @ 0x108
8008808: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800880c: 681b ldr r3, [r3, #0]
800880e: 691b ldr r3, [r3, #16]
8008810: f003 0301 and.w r3, r3, #1
8008814: 2b00 cmp r3, #0
8008816: d004 beq.n 8008822 <USB_EPStartXfer+0x1226>
8008818: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800881c: 3301 adds r3, #1
800881e: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8008822: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8008826: 881b ldrh r3, [r3, #0]
8008828: b29a uxth r2, r3
800882a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800882e: b29b uxth r3, r3
8008830: 029b lsls r3, r3, #10
8008832: b29b uxth r3, r3
8008834: 4313 orrs r3, r2
8008836: b29a uxth r2, r3
8008838: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800883c: 801a strh r2, [r3, #0]
800883e: e02d b.n 800889c <USB_EPStartXfer+0x12a0>
8008840: f507 7384 add.w r3, r7, #264 @ 0x108
8008844: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008848: 681b ldr r3, [r3, #0]
800884a: 785b ldrb r3, [r3, #1]
800884c: 2b01 cmp r3, #1
800884e: d125 bne.n 800889c <USB_EPStartXfer+0x12a0>
8008850: f507 7384 add.w r3, r7, #264 @ 0x108
8008854: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008858: 681b ldr r3, [r3, #0]
800885a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800885e: b29b uxth r3, r3
8008860: 461a mov r2, r3
8008862: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8008866: 4413 add r3, r2
8008868: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800886c: f507 7384 add.w r3, r7, #264 @ 0x108
8008870: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008874: 681b ldr r3, [r3, #0]
8008876: 781b ldrb r3, [r3, #0]
8008878: 011a lsls r2, r3, #4
800887a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800887e: 4413 add r3, r2
8008880: f203 430c addw r3, r3, #1036 @ 0x40c
8008884: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
8008888: f507 7384 add.w r3, r7, #264 @ 0x108
800888c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008890: 681b ldr r3, [r3, #0]
8008892: 691b ldr r3, [r3, #16]
8008894: b29a uxth r2, r3
8008896: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800889a: 801a strh r2, [r3, #0]
/* Coming from ISR */
if (ep->xfer_count != 0U)
800889c: f507 7384 add.w r3, r7, #264 @ 0x108
80088a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80088a4: 681b ldr r3, [r3, #0]
80088a6: 69db ldr r3, [r3, #28]
80088a8: 2b00 cmp r3, #0
80088aa: f000 8218 beq.w 8008cde <USB_EPStartXfer+0x16e2>
{
/* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
80088ae: f507 7384 add.w r3, r7, #264 @ 0x108
80088b2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80088b6: 681a ldr r2, [r3, #0]
80088b8: f507 7384 add.w r3, r7, #264 @ 0x108
80088bc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80088c0: 681b ldr r3, [r3, #0]
80088c2: 781b ldrb r3, [r3, #0]
80088c4: 009b lsls r3, r3, #2
80088c6: 4413 add r3, r2
80088c8: 881b ldrh r3, [r3, #0]
80088ca: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
80088ce: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80088d2: f403 4380 and.w r3, r3, #16384 @ 0x4000
80088d6: 2b00 cmp r3, #0
80088d8: d005 beq.n 80088e6 <USB_EPStartXfer+0x12ea>
80088da: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80088de: f003 0340 and.w r3, r3, #64 @ 0x40
80088e2: 2b00 cmp r3, #0
80088e4: d10d bne.n 8008902 <USB_EPStartXfer+0x1306>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
80088e6: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80088ea: f403 4380 and.w r3, r3, #16384 @ 0x4000
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
80088ee: 2b00 cmp r3, #0
80088f0: f040 81f5 bne.w 8008cde <USB_EPStartXfer+0x16e2>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
80088f4: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80088f8: f003 0340 and.w r3, r3, #64 @ 0x40
80088fc: 2b00 cmp r3, #0
80088fe: f040 81ee bne.w 8008cde <USB_EPStartXfer+0x16e2>
{
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
8008902: f507 7384 add.w r3, r7, #264 @ 0x108
8008906: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800890a: 681a ldr r2, [r3, #0]
800890c: f507 7384 add.w r3, r7, #264 @ 0x108
8008910: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008914: 681b ldr r3, [r3, #0]
8008916: 781b ldrb r3, [r3, #0]
8008918: 009b lsls r3, r3, #2
800891a: 4413 add r3, r2
800891c: 881b ldrh r3, [r3, #0]
800891e: b29b uxth r3, r3
8008920: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008924: f023 0370 bic.w r3, r3, #112 @ 0x70
8008928: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
800892c: f507 7384 add.w r3, r7, #264 @ 0x108
8008930: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008934: 681a ldr r2, [r3, #0]
8008936: f507 7384 add.w r3, r7, #264 @ 0x108
800893a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800893e: 681b ldr r3, [r3, #0]
8008940: 781b ldrb r3, [r3, #0]
8008942: 009b lsls r3, r3, #2
8008944: 441a add r2, r3
8008946: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800894a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800894e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008952: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008956: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800895a: b29b uxth r3, r3
800895c: 8013 strh r3, [r2, #0]
800895e: e1be b.n 8008cde <USB_EPStartXfer+0x16e2>
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
8008960: f507 7384 add.w r3, r7, #264 @ 0x108
8008964: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008968: 681b ldr r3, [r3, #0]
800896a: 78db ldrb r3, [r3, #3]
800896c: 2b01 cmp r3, #1
800896e: f040 81b4 bne.w 8008cda <USB_EPStartXfer+0x16de>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
8008972: f507 7384 add.w r3, r7, #264 @ 0x108
8008976: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800897a: 681b ldr r3, [r3, #0]
800897c: 699a ldr r2, [r3, #24]
800897e: f507 7384 add.w r3, r7, #264 @ 0x108
8008982: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008986: 681b ldr r3, [r3, #0]
8008988: 691b ldr r3, [r3, #16]
800898a: 429a cmp r2, r3
800898c: d917 bls.n 80089be <USB_EPStartXfer+0x13c2>
{
len = ep->maxpacket;
800898e: f507 7384 add.w r3, r7, #264 @ 0x108
8008992: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008996: 681b ldr r3, [r3, #0]
8008998: 691b ldr r3, [r3, #16]
800899a: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
800899e: f507 7384 add.w r3, r7, #264 @ 0x108
80089a2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089a6: 681b ldr r3, [r3, #0]
80089a8: 699a ldr r2, [r3, #24]
80089aa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80089ae: 1ad2 subs r2, r2, r3
80089b0: f507 7384 add.w r3, r7, #264 @ 0x108
80089b4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089b8: 681b ldr r3, [r3, #0]
80089ba: 619a str r2, [r3, #24]
80089bc: e00e b.n 80089dc <USB_EPStartXfer+0x13e0>
}
else
{
len = ep->xfer_len;
80089be: f507 7384 add.w r3, r7, #264 @ 0x108
80089c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089c6: 681b ldr r3, [r3, #0]
80089c8: 699b ldr r3, [r3, #24]
80089ca: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
80089ce: f507 7384 add.w r3, r7, #264 @ 0x108
80089d2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089d6: 681b ldr r3, [r3, #0]
80089d8: 2200 movs r2, #0
80089da: 619a str r2, [r3, #24]
}
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
80089dc: f507 7384 add.w r3, r7, #264 @ 0x108
80089e0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089e4: 681b ldr r3, [r3, #0]
80089e6: 785b ldrb r3, [r3, #1]
80089e8: 2b00 cmp r3, #0
80089ea: f040 8085 bne.w 8008af8 <USB_EPStartXfer+0x14fc>
80089ee: f507 7384 add.w r3, r7, #264 @ 0x108
80089f2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80089f6: 681b ldr r3, [r3, #0]
80089f8: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
80089fc: f507 7384 add.w r3, r7, #264 @ 0x108
8008a00: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008a04: 681b ldr r3, [r3, #0]
8008a06: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008a0a: b29b uxth r3, r3
8008a0c: 461a mov r2, r3
8008a0e: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8008a12: 4413 add r3, r2
8008a14: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8008a18: f507 7384 add.w r3, r7, #264 @ 0x108
8008a1c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a20: 681b ldr r3, [r3, #0]
8008a22: 781b ldrb r3, [r3, #0]
8008a24: 011a lsls r2, r3, #4
8008a26: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8008a2a: 4413 add r3, r2
8008a2c: f203 4304 addw r3, r3, #1028 @ 0x404
8008a30: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8008a34: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008a38: 881b ldrh r3, [r3, #0]
8008a3a: b29b uxth r3, r3
8008a3c: f3c3 0309 ubfx r3, r3, #0, #10
8008a40: b29a uxth r2, r3
8008a42: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008a46: 801a strh r2, [r3, #0]
8008a48: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a4c: 2b3e cmp r3, #62 @ 0x3e
8008a4e: d923 bls.n 8008a98 <USB_EPStartXfer+0x149c>
8008a50: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a54: 095b lsrs r3, r3, #5
8008a56: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008a5a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a5e: f003 031f and.w r3, r3, #31
8008a62: 2b00 cmp r3, #0
8008a64: d104 bne.n 8008a70 <USB_EPStartXfer+0x1474>
8008a66: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008a6a: 3b01 subs r3, #1
8008a6c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008a70: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008a74: 881b ldrh r3, [r3, #0]
8008a76: b29a uxth r2, r3
8008a78: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008a7c: b29b uxth r3, r3
8008a7e: 029b lsls r3, r3, #10
8008a80: b29b uxth r3, r3
8008a82: 4313 orrs r3, r2
8008a84: b29b uxth r3, r3
8008a86: ea6f 4343 mvn.w r3, r3, lsl #17
8008a8a: ea6f 4353 mvn.w r3, r3, lsr #17
8008a8e: b29a uxth r2, r3
8008a90: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008a94: 801a strh r2, [r3, #0]
8008a96: e060 b.n 8008b5a <USB_EPStartXfer+0x155e>
8008a98: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a9c: 2b00 cmp r3, #0
8008a9e: d10c bne.n 8008aba <USB_EPStartXfer+0x14be>
8008aa0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008aa4: 881b ldrh r3, [r3, #0]
8008aa6: b29b uxth r3, r3
8008aa8: ea6f 4343 mvn.w r3, r3, lsl #17
8008aac: ea6f 4353 mvn.w r3, r3, lsr #17
8008ab0: b29a uxth r2, r3
8008ab2: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008ab6: 801a strh r2, [r3, #0]
8008ab8: e04f b.n 8008b5a <USB_EPStartXfer+0x155e>
8008aba: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008abe: 085b lsrs r3, r3, #1
8008ac0: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008ac4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008ac8: f003 0301 and.w r3, r3, #1
8008acc: 2b00 cmp r3, #0
8008ace: d004 beq.n 8008ada <USB_EPStartXfer+0x14de>
8008ad0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008ad4: 3301 adds r3, #1
8008ad6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8008ada: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008ade: 881b ldrh r3, [r3, #0]
8008ae0: b29a uxth r2, r3
8008ae2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8008ae6: b29b uxth r3, r3
8008ae8: 029b lsls r3, r3, #10
8008aea: b29b uxth r3, r3
8008aec: 4313 orrs r3, r2
8008aee: b29a uxth r2, r3
8008af0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8008af4: 801a strh r2, [r3, #0]
8008af6: e030 b.n 8008b5a <USB_EPStartXfer+0x155e>
8008af8: f507 7384 add.w r3, r7, #264 @ 0x108
8008afc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b00: 681b ldr r3, [r3, #0]
8008b02: 785b ldrb r3, [r3, #1]
8008b04: 2b01 cmp r3, #1
8008b06: d128 bne.n 8008b5a <USB_EPStartXfer+0x155e>
8008b08: f507 7384 add.w r3, r7, #264 @ 0x108
8008b0c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b10: 681b ldr r3, [r3, #0]
8008b12: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8008b16: f507 7384 add.w r3, r7, #264 @ 0x108
8008b1a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b1e: 681b ldr r3, [r3, #0]
8008b20: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008b24: b29b uxth r3, r3
8008b26: 461a mov r2, r3
8008b28: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8008b2c: 4413 add r3, r2
8008b2e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8008b32: f507 7384 add.w r3, r7, #264 @ 0x108
8008b36: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b3a: 681b ldr r3, [r3, #0]
8008b3c: 781b ldrb r3, [r3, #0]
8008b3e: 011a lsls r2, r3, #4
8008b40: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8008b44: 4413 add r3, r2
8008b46: f203 4304 addw r3, r3, #1028 @ 0x404
8008b4a: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8008b4e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008b52: b29a uxth r2, r3
8008b54: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
8008b58: 801a strh r2, [r3, #0]
8008b5a: f507 7384 add.w r3, r7, #264 @ 0x108
8008b5e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b62: 681b ldr r3, [r3, #0]
8008b64: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8008b68: f507 7384 add.w r3, r7, #264 @ 0x108
8008b6c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b70: 681b ldr r3, [r3, #0]
8008b72: 785b ldrb r3, [r3, #1]
8008b74: 2b00 cmp r3, #0
8008b76: f040 8085 bne.w 8008c84 <USB_EPStartXfer+0x1688>
8008b7a: f507 7384 add.w r3, r7, #264 @ 0x108
8008b7e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b82: 681b ldr r3, [r3, #0]
8008b84: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8008b88: f507 7384 add.w r3, r7, #264 @ 0x108
8008b8c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b90: 681b ldr r3, [r3, #0]
8008b92: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008b96: b29b uxth r3, r3
8008b98: 461a mov r2, r3
8008b9a: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8008b9e: 4413 add r3, r2
8008ba0: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8008ba4: f507 7384 add.w r3, r7, #264 @ 0x108
8008ba8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008bac: 681b ldr r3, [r3, #0]
8008bae: 781b ldrb r3, [r3, #0]
8008bb0: 011a lsls r2, r3, #4
8008bb2: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8008bb6: 4413 add r3, r2
8008bb8: f203 430c addw r3, r3, #1036 @ 0x40c
8008bbc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8008bc0: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008bc4: 881b ldrh r3, [r3, #0]
8008bc6: b29b uxth r3, r3
8008bc8: f3c3 0309 ubfx r3, r3, #0, #10
8008bcc: b29a uxth r2, r3
8008bce: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008bd2: 801a strh r2, [r3, #0]
8008bd4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008bd8: 2b3e cmp r3, #62 @ 0x3e
8008bda: d923 bls.n 8008c24 <USB_EPStartXfer+0x1628>
8008bdc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008be0: 095b lsrs r3, r3, #5
8008be2: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008be6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008bea: f003 031f and.w r3, r3, #31
8008bee: 2b00 cmp r3, #0
8008bf0: d104 bne.n 8008bfc <USB_EPStartXfer+0x1600>
8008bf2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008bf6: 3b01 subs r3, #1
8008bf8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008bfc: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c00: 881b ldrh r3, [r3, #0]
8008c02: b29a uxth r2, r3
8008c04: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008c08: b29b uxth r3, r3
8008c0a: 029b lsls r3, r3, #10
8008c0c: b29b uxth r3, r3
8008c0e: 4313 orrs r3, r2
8008c10: b29b uxth r3, r3
8008c12: ea6f 4343 mvn.w r3, r3, lsl #17
8008c16: ea6f 4353 mvn.w r3, r3, lsr #17
8008c1a: b29a uxth r2, r3
8008c1c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c20: 801a strh r2, [r3, #0]
8008c22: e05c b.n 8008cde <USB_EPStartXfer+0x16e2>
8008c24: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c28: 2b00 cmp r3, #0
8008c2a: d10c bne.n 8008c46 <USB_EPStartXfer+0x164a>
8008c2c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c30: 881b ldrh r3, [r3, #0]
8008c32: b29b uxth r3, r3
8008c34: ea6f 4343 mvn.w r3, r3, lsl #17
8008c38: ea6f 4353 mvn.w r3, r3, lsr #17
8008c3c: b29a uxth r2, r3
8008c3e: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c42: 801a strh r2, [r3, #0]
8008c44: e04b b.n 8008cde <USB_EPStartXfer+0x16e2>
8008c46: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c4a: 085b lsrs r3, r3, #1
8008c4c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008c50: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c54: f003 0301 and.w r3, r3, #1
8008c58: 2b00 cmp r3, #0
8008c5a: d004 beq.n 8008c66 <USB_EPStartXfer+0x166a>
8008c5c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008c60: 3301 adds r3, #1
8008c62: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8008c66: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c6a: 881b ldrh r3, [r3, #0]
8008c6c: b29a uxth r2, r3
8008c6e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8008c72: b29b uxth r3, r3
8008c74: 029b lsls r3, r3, #10
8008c76: b29b uxth r3, r3
8008c78: 4313 orrs r3, r2
8008c7a: b29a uxth r2, r3
8008c7c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8008c80: 801a strh r2, [r3, #0]
8008c82: e02c b.n 8008cde <USB_EPStartXfer+0x16e2>
8008c84: f507 7384 add.w r3, r7, #264 @ 0x108
8008c88: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c8c: 681b ldr r3, [r3, #0]
8008c8e: 785b ldrb r3, [r3, #1]
8008c90: 2b01 cmp r3, #1
8008c92: d124 bne.n 8008cde <USB_EPStartXfer+0x16e2>
8008c94: f507 7384 add.w r3, r7, #264 @ 0x108
8008c98: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008c9c: 681b ldr r3, [r3, #0]
8008c9e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008ca2: b29b uxth r3, r3
8008ca4: 461a mov r2, r3
8008ca6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8008caa: 4413 add r3, r2
8008cac: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8008cb0: f507 7384 add.w r3, r7, #264 @ 0x108
8008cb4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cb8: 681b ldr r3, [r3, #0]
8008cba: 781b ldrb r3, [r3, #0]
8008cbc: 011a lsls r2, r3, #4
8008cbe: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8008cc2: 4413 add r3, r2
8008cc4: f203 430c addw r3, r3, #1036 @ 0x40c
8008cc8: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8008ccc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008cd0: b29a uxth r2, r3
8008cd2: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8008cd6: 801a strh r2, [r3, #0]
8008cd8: e001 b.n 8008cde <USB_EPStartXfer+0x16e2>
}
else
{
return HAL_ERROR;
8008cda: 2301 movs r3, #1
8008cdc: e03a b.n 8008d54 <USB_EPStartXfer+0x1758>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8008cde: f507 7384 add.w r3, r7, #264 @ 0x108
8008ce2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008ce6: 681a ldr r2, [r3, #0]
8008ce8: f507 7384 add.w r3, r7, #264 @ 0x108
8008cec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cf0: 681b ldr r3, [r3, #0]
8008cf2: 781b ldrb r3, [r3, #0]
8008cf4: 009b lsls r3, r3, #2
8008cf6: 4413 add r3, r2
8008cf8: 881b ldrh r3, [r3, #0]
8008cfa: b29b uxth r3, r3
8008cfc: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008d00: f023 0370 bic.w r3, r3, #112 @ 0x70
8008d04: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8008d08: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008d0c: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008d10: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8008d14: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008d18: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008d1c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8008d20: f507 7384 add.w r3, r7, #264 @ 0x108
8008d24: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008d28: 681a ldr r2, [r3, #0]
8008d2a: f507 7384 add.w r3, r7, #264 @ 0x108
8008d2e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008d32: 681b ldr r3, [r3, #0]
8008d34: 781b ldrb r3, [r3, #0]
8008d36: 009b lsls r3, r3, #2
8008d38: 441a add r2, r3
8008d3a: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008d3e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008d42: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008d46: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008d4a: f043 0380 orr.w r3, r3, #128 @ 0x80
8008d4e: b29b uxth r3, r3
8008d50: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8008d52: 2300 movs r3, #0
}
8008d54: 4618 mov r0, r3
8008d56: f507 7784 add.w r7, r7, #264 @ 0x108
8008d5a: 46bd mov sp, r7
8008d5c: bd80 pop {r7, pc}
08008d5e <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8008d5e: b480 push {r7}
8008d60: b085 sub sp, #20
8008d62: af00 add r7, sp, #0
8008d64: 6078 str r0, [r7, #4]
8008d66: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
8008d68: 683b ldr r3, [r7, #0]
8008d6a: 785b ldrb r3, [r3, #1]
8008d6c: 2b00 cmp r3, #0
8008d6e: d020 beq.n 8008db2 <USB_EPSetStall+0x54>
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
8008d70: 687a ldr r2, [r7, #4]
8008d72: 683b ldr r3, [r7, #0]
8008d74: 781b ldrb r3, [r3, #0]
8008d76: 009b lsls r3, r3, #2
8008d78: 4413 add r3, r2
8008d7a: 881b ldrh r3, [r3, #0]
8008d7c: b29b uxth r3, r3
8008d7e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008d82: f023 0340 bic.w r3, r3, #64 @ 0x40
8008d86: 81bb strh r3, [r7, #12]
8008d88: 89bb ldrh r3, [r7, #12]
8008d8a: f083 0310 eor.w r3, r3, #16
8008d8e: 81bb strh r3, [r7, #12]
8008d90: 687a ldr r2, [r7, #4]
8008d92: 683b ldr r3, [r7, #0]
8008d94: 781b ldrb r3, [r3, #0]
8008d96: 009b lsls r3, r3, #2
8008d98: 441a add r2, r3
8008d9a: 89bb ldrh r3, [r7, #12]
8008d9c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008da0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008da4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008da8: f043 0380 orr.w r3, r3, #128 @ 0x80
8008dac: b29b uxth r3, r3
8008dae: 8013 strh r3, [r2, #0]
8008db0: e01f b.n 8008df2 <USB_EPSetStall+0x94>
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
8008db2: 687a ldr r2, [r7, #4]
8008db4: 683b ldr r3, [r7, #0]
8008db6: 781b ldrb r3, [r3, #0]
8008db8: 009b lsls r3, r3, #2
8008dba: 4413 add r3, r2
8008dbc: 881b ldrh r3, [r3, #0]
8008dbe: b29b uxth r3, r3
8008dc0: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008dc4: f023 0370 bic.w r3, r3, #112 @ 0x70
8008dc8: 81fb strh r3, [r7, #14]
8008dca: 89fb ldrh r3, [r7, #14]
8008dcc: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008dd0: 81fb strh r3, [r7, #14]
8008dd2: 687a ldr r2, [r7, #4]
8008dd4: 683b ldr r3, [r7, #0]
8008dd6: 781b ldrb r3, [r3, #0]
8008dd8: 009b lsls r3, r3, #2
8008dda: 441a add r2, r3
8008ddc: 89fb ldrh r3, [r7, #14]
8008dde: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008de2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008de6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008dea: f043 0380 orr.w r3, r3, #128 @ 0x80
8008dee: b29b uxth r3, r3
8008df0: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8008df2: 2300 movs r3, #0
}
8008df4: 4618 mov r0, r3
8008df6: 3714 adds r7, #20
8008df8: 46bd mov sp, r7
8008dfa: bc80 pop {r7}
8008dfc: 4770 bx lr
08008dfe <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8008dfe: b480 push {r7}
8008e00: b087 sub sp, #28
8008e02: af00 add r7, sp, #0
8008e04: 6078 str r0, [r7, #4]
8008e06: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
8008e08: 683b ldr r3, [r7, #0]
8008e0a: 7b1b ldrb r3, [r3, #12]
8008e0c: 2b00 cmp r3, #0
8008e0e: f040 809d bne.w 8008f4c <USB_EPClearStall+0x14e>
{
if (ep->is_in != 0U)
8008e12: 683b ldr r3, [r7, #0]
8008e14: 785b ldrb r3, [r3, #1]
8008e16: 2b00 cmp r3, #0
8008e18: d04c beq.n 8008eb4 <USB_EPClearStall+0xb6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8008e1a: 687a ldr r2, [r7, #4]
8008e1c: 683b ldr r3, [r7, #0]
8008e1e: 781b ldrb r3, [r3, #0]
8008e20: 009b lsls r3, r3, #2
8008e22: 4413 add r3, r2
8008e24: 881b ldrh r3, [r3, #0]
8008e26: 823b strh r3, [r7, #16]
8008e28: 8a3b ldrh r3, [r7, #16]
8008e2a: f003 0340 and.w r3, r3, #64 @ 0x40
8008e2e: 2b00 cmp r3, #0
8008e30: d01b beq.n 8008e6a <USB_EPClearStall+0x6c>
8008e32: 687a ldr r2, [r7, #4]
8008e34: 683b ldr r3, [r7, #0]
8008e36: 781b ldrb r3, [r3, #0]
8008e38: 009b lsls r3, r3, #2
8008e3a: 4413 add r3, r2
8008e3c: 881b ldrh r3, [r3, #0]
8008e3e: b29b uxth r3, r3
8008e40: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008e44: f023 0370 bic.w r3, r3, #112 @ 0x70
8008e48: 81fb strh r3, [r7, #14]
8008e4a: 687a ldr r2, [r7, #4]
8008e4c: 683b ldr r3, [r7, #0]
8008e4e: 781b ldrb r3, [r3, #0]
8008e50: 009b lsls r3, r3, #2
8008e52: 441a add r2, r3
8008e54: 89fb ldrh r3, [r7, #14]
8008e56: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008e5a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008e5e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008e62: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008e66: b29b uxth r3, r3
8008e68: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8008e6a: 683b ldr r3, [r7, #0]
8008e6c: 78db ldrb r3, [r3, #3]
8008e6e: 2b01 cmp r3, #1
8008e70: d06c beq.n 8008f4c <USB_EPClearStall+0x14e>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8008e72: 687a ldr r2, [r7, #4]
8008e74: 683b ldr r3, [r7, #0]
8008e76: 781b ldrb r3, [r3, #0]
8008e78: 009b lsls r3, r3, #2
8008e7a: 4413 add r3, r2
8008e7c: 881b ldrh r3, [r3, #0]
8008e7e: b29b uxth r3, r3
8008e80: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008e84: f023 0340 bic.w r3, r3, #64 @ 0x40
8008e88: 81bb strh r3, [r7, #12]
8008e8a: 89bb ldrh r3, [r7, #12]
8008e8c: f083 0320 eor.w r3, r3, #32
8008e90: 81bb strh r3, [r7, #12]
8008e92: 687a ldr r2, [r7, #4]
8008e94: 683b ldr r3, [r7, #0]
8008e96: 781b ldrb r3, [r3, #0]
8008e98: 009b lsls r3, r3, #2
8008e9a: 441a add r2, r3
8008e9c: 89bb ldrh r3, [r7, #12]
8008e9e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008ea2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008ea6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008eaa: f043 0380 orr.w r3, r3, #128 @ 0x80
8008eae: b29b uxth r3, r3
8008eb0: 8013 strh r3, [r2, #0]
8008eb2: e04b b.n 8008f4c <USB_EPClearStall+0x14e>
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8008eb4: 687a ldr r2, [r7, #4]
8008eb6: 683b ldr r3, [r7, #0]
8008eb8: 781b ldrb r3, [r3, #0]
8008eba: 009b lsls r3, r3, #2
8008ebc: 4413 add r3, r2
8008ebe: 881b ldrh r3, [r3, #0]
8008ec0: 82fb strh r3, [r7, #22]
8008ec2: 8afb ldrh r3, [r7, #22]
8008ec4: f403 4380 and.w r3, r3, #16384 @ 0x4000
8008ec8: 2b00 cmp r3, #0
8008eca: d01b beq.n 8008f04 <USB_EPClearStall+0x106>
8008ecc: 687a ldr r2, [r7, #4]
8008ece: 683b ldr r3, [r7, #0]
8008ed0: 781b ldrb r3, [r3, #0]
8008ed2: 009b lsls r3, r3, #2
8008ed4: 4413 add r3, r2
8008ed6: 881b ldrh r3, [r3, #0]
8008ed8: b29b uxth r3, r3
8008eda: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008ede: f023 0370 bic.w r3, r3, #112 @ 0x70
8008ee2: 82bb strh r3, [r7, #20]
8008ee4: 687a ldr r2, [r7, #4]
8008ee6: 683b ldr r3, [r7, #0]
8008ee8: 781b ldrb r3, [r3, #0]
8008eea: 009b lsls r3, r3, #2
8008eec: 441a add r2, r3
8008eee: 8abb ldrh r3, [r7, #20]
8008ef0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008ef4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008ef8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8008efc: f043 0380 orr.w r3, r3, #128 @ 0x80
8008f00: b29b uxth r3, r3
8008f02: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8008f04: 687a ldr r2, [r7, #4]
8008f06: 683b ldr r3, [r7, #0]
8008f08: 781b ldrb r3, [r3, #0]
8008f0a: 009b lsls r3, r3, #2
8008f0c: 4413 add r3, r2
8008f0e: 881b ldrh r3, [r3, #0]
8008f10: b29b uxth r3, r3
8008f12: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008f16: f023 0370 bic.w r3, r3, #112 @ 0x70
8008f1a: 827b strh r3, [r7, #18]
8008f1c: 8a7b ldrh r3, [r7, #18]
8008f1e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008f22: 827b strh r3, [r7, #18]
8008f24: 8a7b ldrh r3, [r7, #18]
8008f26: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008f2a: 827b strh r3, [r7, #18]
8008f2c: 687a ldr r2, [r7, #4]
8008f2e: 683b ldr r3, [r7, #0]
8008f30: 781b ldrb r3, [r3, #0]
8008f32: 009b lsls r3, r3, #2
8008f34: 441a add r2, r3
8008f36: 8a7b ldrh r3, [r7, #18]
8008f38: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008f3c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008f40: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008f44: f043 0380 orr.w r3, r3, #128 @ 0x80
8008f48: b29b uxth r3, r3
8008f4a: 8013 strh r3, [r2, #0]
}
}
return HAL_OK;
8008f4c: 2300 movs r3, #0
}
8008f4e: 4618 mov r0, r3
8008f50: 371c adds r7, #28
8008f52: 46bd mov sp, r7
8008f54: bc80 pop {r7}
8008f56: 4770 bx lr
08008f58 <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
8008f58: b480 push {r7}
8008f5a: b083 sub sp, #12
8008f5c: af00 add r7, sp, #0
8008f5e: 6078 str r0, [r7, #4]
8008f60: 460b mov r3, r1
8008f62: 70fb strb r3, [r7, #3]
if (address == 0U)
8008f64: 78fb ldrb r3, [r7, #3]
8008f66: 2b00 cmp r3, #0
8008f68: d103 bne.n 8008f72 <USB_SetDevAddress+0x1a>
{
/* set device address and enable function */
USBx->DADDR = (uint16_t)USB_DADDR_EF;
8008f6a: 687b ldr r3, [r7, #4]
8008f6c: 2280 movs r2, #128 @ 0x80
8008f6e: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
}
return HAL_OK;
8008f72: 2300 movs r3, #0
}
8008f74: 4618 mov r0, r3
8008f76: 370c adds r7, #12
8008f78: 46bd mov sp, r7
8008f7a: bc80 pop {r7}
8008f7c: 4770 bx lr
08008f7e <USB_DevConnect>:
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
8008f7e: b480 push {r7}
8008f80: b083 sub sp, #12
8008f82: af00 add r7, sp, #0
8008f84: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8008f86: 2300 movs r3, #0
}
8008f88: 4618 mov r0, r3
8008f8a: 370c adds r7, #12
8008f8c: 46bd mov sp, r7
8008f8e: bc80 pop {r7}
8008f90: 4770 bx lr
08008f92 <USB_DevDisconnect>:
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
8008f92: b480 push {r7}
8008f94: b083 sub sp, #12
8008f96: af00 add r7, sp, #0
8008f98: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8008f9a: 2300 movs r3, #0
}
8008f9c: 4618 mov r0, r3
8008f9e: 370c adds r7, #12
8008fa0: 46bd mov sp, r7
8008fa2: bc80 pop {r7}
8008fa4: 4770 bx lr
08008fa6 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
8008fa6: b480 push {r7}
8008fa8: b085 sub sp, #20
8008faa: af00 add r7, sp, #0
8008fac: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->ISTR;
8008fae: 687b ldr r3, [r7, #4]
8008fb0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8008fb4: b29b uxth r3, r3
8008fb6: 60fb str r3, [r7, #12]
return tmpreg;
8008fb8: 68fb ldr r3, [r7, #12]
}
8008fba: 4618 mov r0, r3
8008fbc: 3714 adds r7, #20
8008fbe: 46bd mov sp, r7
8008fc0: bc80 pop {r7}
8008fc2: 4770 bx lr
08008fc4 <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
8008fc4: b480 push {r7}
8008fc6: b083 sub sp, #12
8008fc8: af00 add r7, sp, #0
8008fca: 6078 str r0, [r7, #4]
8008fcc: 6039 str r1, [r7, #0]
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8008fce: 2300 movs r3, #0
}
8008fd0: 4618 mov r0, r3
8008fd2: 370c adds r7, #12
8008fd4: 46bd mov sp, r7
8008fd6: bc80 pop {r7}
8008fd8: 4770 bx lr
08008fda <USB_WritePMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
8008fda: b480 push {r7}
8008fdc: b08b sub sp, #44 @ 0x2c
8008fde: af00 add r7, sp, #0
8008fe0: 60f8 str r0, [r7, #12]
8008fe2: 60b9 str r1, [r7, #8]
8008fe4: 4611 mov r1, r2
8008fe6: 461a mov r2, r3
8008fe8: 460b mov r3, r1
8008fea: 80fb strh r3, [r7, #6]
8008fec: 4613 mov r3, r2
8008fee: 80bb strh r3, [r7, #4]
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
8008ff0: 88bb ldrh r3, [r7, #4]
8008ff2: 3301 adds r3, #1
8008ff4: 085b lsrs r3, r3, #1
8008ff6: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
8008ff8: 68fb ldr r3, [r7, #12]
8008ffa: 617b str r3, [r7, #20]
uint32_t count;
uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
8008ffc: 68bb ldr r3, [r7, #8]
8008ffe: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
8009000: 88fb ldrh r3, [r7, #6]
8009002: 005a lsls r2, r3, #1
8009004: 697b ldr r3, [r7, #20]
8009006: 4413 add r3, r2
8009008: f503 6380 add.w r3, r3, #1024 @ 0x400
800900c: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800900e: 69bb ldr r3, [r7, #24]
8009010: 627b str r3, [r7, #36] @ 0x24
8009012: e01f b.n 8009054 <USB_WritePMA+0x7a>
{
WrVal = pBuf[0];
8009014: 69fb ldr r3, [r7, #28]
8009016: 781b ldrb r3, [r3, #0]
8009018: 827b strh r3, [r7, #18]
WrVal |= (uint16_t)pBuf[1] << 8;
800901a: 69fb ldr r3, [r7, #28]
800901c: 3301 adds r3, #1
800901e: 781b ldrb r3, [r3, #0]
8009020: b21b sxth r3, r3
8009022: 021b lsls r3, r3, #8
8009024: b21a sxth r2, r3
8009026: f9b7 3012 ldrsh.w r3, [r7, #18]
800902a: 4313 orrs r3, r2
800902c: b21b sxth r3, r3
800902e: 827b strh r3, [r7, #18]
*pdwVal = (WrVal & 0xFFFFU);
8009030: 6a3b ldr r3, [r7, #32]
8009032: 8a7a ldrh r2, [r7, #18]
8009034: 801a strh r2, [r3, #0]
pdwVal++;
8009036: 6a3b ldr r3, [r7, #32]
8009038: 3302 adds r3, #2
800903a: 623b str r3, [r7, #32]
#if PMA_ACCESS > 1U
pdwVal++;
800903c: 6a3b ldr r3, [r7, #32]
800903e: 3302 adds r3, #2
8009040: 623b str r3, [r7, #32]
#endif /* PMA_ACCESS */
pBuf++;
8009042: 69fb ldr r3, [r7, #28]
8009044: 3301 adds r3, #1
8009046: 61fb str r3, [r7, #28]
pBuf++;
8009048: 69fb ldr r3, [r7, #28]
800904a: 3301 adds r3, #1
800904c: 61fb str r3, [r7, #28]
for (count = n; count != 0U; count--)
800904e: 6a7b ldr r3, [r7, #36] @ 0x24
8009050: 3b01 subs r3, #1
8009052: 627b str r3, [r7, #36] @ 0x24
8009054: 6a7b ldr r3, [r7, #36] @ 0x24
8009056: 2b00 cmp r3, #0
8009058: d1dc bne.n 8009014 <USB_WritePMA+0x3a>
}
}
800905a: bf00 nop
800905c: bf00 nop
800905e: 372c adds r7, #44 @ 0x2c
8009060: 46bd mov sp, r7
8009062: bc80 pop {r7}
8009064: 4770 bx lr
08009066 <USB_ReadPMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
8009066: b480 push {r7}
8009068: b08b sub sp, #44 @ 0x2c
800906a: af00 add r7, sp, #0
800906c: 60f8 str r0, [r7, #12]
800906e: 60b9 str r1, [r7, #8]
8009070: 4611 mov r1, r2
8009072: 461a mov r2, r3
8009074: 460b mov r3, r1
8009076: 80fb strh r3, [r7, #6]
8009078: 4613 mov r3, r2
800907a: 80bb strh r3, [r7, #4]
uint32_t n = (uint32_t)wNBytes >> 1;
800907c: 88bb ldrh r3, [r7, #4]
800907e: 085b lsrs r3, r3, #1
8009080: b29b uxth r3, r3
8009082: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
8009084: 68fb ldr r3, [r7, #12]
8009086: 617b str r3, [r7, #20]
uint32_t count;
uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
8009088: 68bb ldr r3, [r7, #8]
800908a: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
800908c: 88fb ldrh r3, [r7, #6]
800908e: 005a lsls r2, r3, #1
8009090: 697b ldr r3, [r7, #20]
8009092: 4413 add r3, r2
8009094: f503 6380 add.w r3, r3, #1024 @ 0x400
8009098: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800909a: 69bb ldr r3, [r7, #24]
800909c: 627b str r3, [r7, #36] @ 0x24
800909e: e01b b.n 80090d8 <USB_ReadPMA+0x72>
{
RdVal = *(__IO uint16_t *)pdwVal;
80090a0: 6a3b ldr r3, [r7, #32]
80090a2: 881b ldrh r3, [r3, #0]
80090a4: b29b uxth r3, r3
80090a6: 613b str r3, [r7, #16]
pdwVal++;
80090a8: 6a3b ldr r3, [r7, #32]
80090aa: 3302 adds r3, #2
80090ac: 623b str r3, [r7, #32]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
80090ae: 693b ldr r3, [r7, #16]
80090b0: b2da uxtb r2, r3
80090b2: 69fb ldr r3, [r7, #28]
80090b4: 701a strb r2, [r3, #0]
pBuf++;
80090b6: 69fb ldr r3, [r7, #28]
80090b8: 3301 adds r3, #1
80090ba: 61fb str r3, [r7, #28]
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
80090bc: 693b ldr r3, [r7, #16]
80090be: 0a1b lsrs r3, r3, #8
80090c0: b2da uxtb r2, r3
80090c2: 69fb ldr r3, [r7, #28]
80090c4: 701a strb r2, [r3, #0]
pBuf++;
80090c6: 69fb ldr r3, [r7, #28]
80090c8: 3301 adds r3, #1
80090ca: 61fb str r3, [r7, #28]
#if PMA_ACCESS > 1U
pdwVal++;
80090cc: 6a3b ldr r3, [r7, #32]
80090ce: 3302 adds r3, #2
80090d0: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
80090d2: 6a7b ldr r3, [r7, #36] @ 0x24
80090d4: 3b01 subs r3, #1
80090d6: 627b str r3, [r7, #36] @ 0x24
80090d8: 6a7b ldr r3, [r7, #36] @ 0x24
80090da: 2b00 cmp r3, #0
80090dc: d1e0 bne.n 80090a0 <USB_ReadPMA+0x3a>
#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
80090de: 88bb ldrh r3, [r7, #4]
80090e0: f003 0301 and.w r3, r3, #1
80090e4: b29b uxth r3, r3
80090e6: 2b00 cmp r3, #0
80090e8: d007 beq.n 80090fa <USB_ReadPMA+0x94>
{
RdVal = *pdwVal;
80090ea: 6a3b ldr r3, [r7, #32]
80090ec: 881b ldrh r3, [r3, #0]
80090ee: b29b uxth r3, r3
80090f0: 613b str r3, [r7, #16]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
80090f2: 693b ldr r3, [r7, #16]
80090f4: b2da uxtb r2, r3
80090f6: 69fb ldr r3, [r7, #28]
80090f8: 701a strb r2, [r3, #0]
}
}
80090fa: bf00 nop
80090fc: 372c adds r7, #44 @ 0x2c
80090fe: 46bd mov sp, r7
8009100: bc80 pop {r7}
8009102: 4770 bx lr
08009104 <USBD_CDC_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8009104: b580 push {r7, lr}
8009106: b084 sub sp, #16
8009108: af00 add r7, sp, #0
800910a: 6078 str r0, [r7, #4]
800910c: 460b mov r3, r1
800910e: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
8009110: 2300 movs r3, #0
8009112: 73fb strb r3, [r7, #15]
USBD_CDC_HandleTypeDef *hcdc;
if (pdev->dev_speed == USBD_SPEED_HIGH)
8009114: 687b ldr r3, [r7, #4]
8009116: 7c1b ldrb r3, [r3, #16]
8009118: 2b00 cmp r3, #0
800911a: d115 bne.n 8009148 <USBD_CDC_Init+0x44>
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
800911c: f44f 7300 mov.w r3, #512 @ 0x200
8009120: 2202 movs r2, #2
8009122: 2181 movs r1, #129 @ 0x81
8009124: 6878 ldr r0, [r7, #4]
8009126: f001 ff00 bl 800af2a <USBD_LL_OpenEP>
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
800912a: 687b ldr r3, [r7, #4]
800912c: 2201 movs r2, #1
800912e: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
8009130: f44f 7300 mov.w r3, #512 @ 0x200
8009134: 2202 movs r2, #2
8009136: 2101 movs r1, #1
8009138: 6878 ldr r0, [r7, #4]
800913a: f001 fef6 bl 800af2a <USBD_LL_OpenEP>
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
800913e: 687b ldr r3, [r7, #4]
8009140: 2201 movs r2, #1
8009142: f8c3 216c str.w r2, [r3, #364] @ 0x16c
8009146: e012 b.n 800916e <USBD_CDC_Init+0x6a>
}
else
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
8009148: 2340 movs r3, #64 @ 0x40
800914a: 2202 movs r2, #2
800914c: 2181 movs r1, #129 @ 0x81
800914e: 6878 ldr r0, [r7, #4]
8009150: f001 feeb bl 800af2a <USBD_LL_OpenEP>
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
8009154: 687b ldr r3, [r7, #4]
8009156: 2201 movs r2, #1
8009158: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
800915a: 2340 movs r3, #64 @ 0x40
800915c: 2202 movs r2, #2
800915e: 2101 movs r1, #1
8009160: 6878 ldr r0, [r7, #4]
8009162: f001 fee2 bl 800af2a <USBD_LL_OpenEP>
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
8009166: 687b ldr r3, [r7, #4]
8009168: 2201 movs r2, #1
800916a: f8c3 216c str.w r2, [r3, #364] @ 0x16c
}
/* Open Command IN EP */
USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
800916e: 2308 movs r3, #8
8009170: 2203 movs r2, #3
8009172: 2182 movs r1, #130 @ 0x82
8009174: 6878 ldr r0, [r7, #4]
8009176: f001 fed8 bl 800af2a <USBD_LL_OpenEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
800917a: 687b ldr r3, [r7, #4]
800917c: 2201 movs r2, #1
800917e: 641a str r2, [r3, #64] @ 0x40
pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
8009180: f44f 7007 mov.w r0, #540 @ 0x21c
8009184: f001 fff8 bl 800b178 <USBD_static_malloc>
8009188: 4602 mov r2, r0
800918a: 687b ldr r3, [r7, #4]
800918c: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClassData == NULL)
8009190: 687b ldr r3, [r7, #4]
8009192: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009196: 2b00 cmp r3, #0
8009198: d102 bne.n 80091a0 <USBD_CDC_Init+0x9c>
{
ret = 1U;
800919a: 2301 movs r3, #1
800919c: 73fb strb r3, [r7, #15]
800919e: e026 b.n 80091ee <USBD_CDC_Init+0xea>
}
else
{
hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80091a0: 687b ldr r3, [r7, #4]
80091a2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80091a6: 60bb str r3, [r7, #8]
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
80091a8: 687b ldr r3, [r7, #4]
80091aa: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80091ae: 681b ldr r3, [r3, #0]
80091b0: 4798 blx r3
/* Init Xfer states */
hcdc->TxState = 0U;
80091b2: 68bb ldr r3, [r7, #8]
80091b4: 2200 movs r2, #0
80091b6: f8c3 2214 str.w r2, [r3, #532] @ 0x214
hcdc->RxState = 0U;
80091ba: 68bb ldr r3, [r7, #8]
80091bc: 2200 movs r2, #0
80091be: f8c3 2218 str.w r2, [r3, #536] @ 0x218
if (pdev->dev_speed == USBD_SPEED_HIGH)
80091c2: 687b ldr r3, [r7, #4]
80091c4: 7c1b ldrb r3, [r3, #16]
80091c6: 2b00 cmp r3, #0
80091c8: d109 bne.n 80091de <USBD_CDC_Init+0xda>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
80091ca: 68bb ldr r3, [r7, #8]
80091cc: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80091d0: f44f 7300 mov.w r3, #512 @ 0x200
80091d4: 2101 movs r1, #1
80091d6: 6878 ldr r0, [r7, #4]
80091d8: f001 ff97 bl 800b10a <USBD_LL_PrepareReceive>
80091dc: e007 b.n 80091ee <USBD_CDC_Init+0xea>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
80091de: 68bb ldr r3, [r7, #8]
80091e0: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80091e4: 2340 movs r3, #64 @ 0x40
80091e6: 2101 movs r1, #1
80091e8: 6878 ldr r0, [r7, #4]
80091ea: f001 ff8e bl 800b10a <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
}
return ret;
80091ee: 7bfb ldrb r3, [r7, #15]
}
80091f0: 4618 mov r0, r3
80091f2: 3710 adds r7, #16
80091f4: 46bd mov sp, r7
80091f6: bd80 pop {r7, pc}
080091f8 <USBD_CDC_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80091f8: b580 push {r7, lr}
80091fa: b084 sub sp, #16
80091fc: af00 add r7, sp, #0
80091fe: 6078 str r0, [r7, #4]
8009200: 460b mov r3, r1
8009202: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
8009204: 2300 movs r3, #0
8009206: 73fb strb r3, [r7, #15]
/* Close EP IN */
USBD_LL_CloseEP(pdev, CDC_IN_EP);
8009208: 2181 movs r1, #129 @ 0x81
800920a: 6878 ldr r0, [r7, #4]
800920c: f001 feb3 bl 800af76 <USBD_LL_CloseEP>
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
8009210: 687b ldr r3, [r7, #4]
8009212: 2200 movs r2, #0
8009214: 62da str r2, [r3, #44] @ 0x2c
/* Close EP OUT */
USBD_LL_CloseEP(pdev, CDC_OUT_EP);
8009216: 2101 movs r1, #1
8009218: 6878 ldr r0, [r7, #4]
800921a: f001 feac bl 800af76 <USBD_LL_CloseEP>
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
800921e: 687b ldr r3, [r7, #4]
8009220: 2200 movs r2, #0
8009222: f8c3 216c str.w r2, [r3, #364] @ 0x16c
/* Close Command IN EP */
USBD_LL_CloseEP(pdev, CDC_CMD_EP);
8009226: 2182 movs r1, #130 @ 0x82
8009228: 6878 ldr r0, [r7, #4]
800922a: f001 fea4 bl 800af76 <USBD_LL_CloseEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
800922e: 687b ldr r3, [r7, #4]
8009230: 2200 movs r2, #0
8009232: 641a str r2, [r3, #64] @ 0x40
/* DeInit physical Interface components */
if (pdev->pClassData != NULL)
8009234: 687b ldr r3, [r7, #4]
8009236: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800923a: 2b00 cmp r3, #0
800923c: d00e beq.n 800925c <USBD_CDC_DeInit+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
800923e: 687b ldr r3, [r7, #4]
8009240: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009244: 685b ldr r3, [r3, #4]
8009246: 4798 blx r3
USBD_free(pdev->pClassData);
8009248: 687b ldr r3, [r7, #4]
800924a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800924e: 4618 mov r0, r3
8009250: f001 ff9e bl 800b190 <USBD_static_free>
pdev->pClassData = NULL;
8009254: 687b ldr r3, [r7, #4]
8009256: 2200 movs r2, #0
8009258: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
}
return ret;
800925c: 7bfb ldrb r3, [r7, #15]
}
800925e: 4618 mov r0, r3
8009260: 3710 adds r7, #16
8009262: 46bd mov sp, r7
8009264: bd80 pop {r7, pc}
08009266 <USBD_CDC_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009266: b580 push {r7, lr}
8009268: b086 sub sp, #24
800926a: af00 add r7, sp, #0
800926c: 6078 str r0, [r7, #4]
800926e: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8009270: 687b ldr r3, [r7, #4]
8009272: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009276: 613b str r3, [r7, #16]
uint8_t ifalt = 0U;
8009278: 2300 movs r3, #0
800927a: 73fb strb r3, [r7, #15]
uint16_t status_info = 0U;
800927c: 2300 movs r3, #0
800927e: 81bb strh r3, [r7, #12]
uint8_t ret = USBD_OK;
8009280: 2300 movs r3, #0
8009282: 75fb strb r3, [r7, #23]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009284: 683b ldr r3, [r7, #0]
8009286: 781b ldrb r3, [r3, #0]
8009288: f003 0360 and.w r3, r3, #96 @ 0x60
800928c: 2b00 cmp r3, #0
800928e: d039 beq.n 8009304 <USBD_CDC_Setup+0x9e>
8009290: 2b20 cmp r3, #32
8009292: d17f bne.n 8009394 <USBD_CDC_Setup+0x12e>
{
case USB_REQ_TYPE_CLASS :
if (req->wLength)
8009294: 683b ldr r3, [r7, #0]
8009296: 88db ldrh r3, [r3, #6]
8009298: 2b00 cmp r3, #0
800929a: d029 beq.n 80092f0 <USBD_CDC_Setup+0x8a>
{
if (req->bmRequest & 0x80U)
800929c: 683b ldr r3, [r7, #0]
800929e: 781b ldrb r3, [r3, #0]
80092a0: b25b sxtb r3, r3
80092a2: 2b00 cmp r3, #0
80092a4: da11 bge.n 80092ca <USBD_CDC_Setup+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80092a6: 687b ldr r3, [r7, #4]
80092a8: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80092ac: 689b ldr r3, [r3, #8]
80092ae: 683a ldr r2, [r7, #0]
80092b0: 7850 ldrb r0, [r2, #1]
(uint8_t *)(void *)hcdc->data,
80092b2: 6939 ldr r1, [r7, #16]
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80092b4: 683a ldr r2, [r7, #0]
80092b6: 88d2 ldrh r2, [r2, #6]
80092b8: 4798 blx r3
req->wLength);
USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
80092ba: 6939 ldr r1, [r7, #16]
80092bc: 683b ldr r3, [r7, #0]
80092be: 88db ldrh r3, [r3, #6]
80092c0: 461a mov r2, r3
80092c2: 6878 ldr r0, [r7, #4]
80092c4: f001 fa06 bl 800a6d4 <USBD_CtlSendData>
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
(uint8_t *)(void *)req, 0U);
}
break;
80092c8: e06b b.n 80093a2 <USBD_CDC_Setup+0x13c>
hcdc->CmdOpCode = req->bRequest;
80092ca: 683b ldr r3, [r7, #0]
80092cc: 785a ldrb r2, [r3, #1]
80092ce: 693b ldr r3, [r7, #16]
80092d0: f883 2200 strb.w r2, [r3, #512] @ 0x200
hcdc->CmdLength = (uint8_t)req->wLength;
80092d4: 683b ldr r3, [r7, #0]
80092d6: 88db ldrh r3, [r3, #6]
80092d8: b2da uxtb r2, r3
80092da: 693b ldr r3, [r7, #16]
80092dc: f883 2201 strb.w r2, [r3, #513] @ 0x201
USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
80092e0: 6939 ldr r1, [r7, #16]
80092e2: 683b ldr r3, [r7, #0]
80092e4: 88db ldrh r3, [r3, #6]
80092e6: 461a mov r2, r3
80092e8: 6878 ldr r0, [r7, #4]
80092ea: f001 fa21 bl 800a730 <USBD_CtlPrepareRx>
break;
80092ee: e058 b.n 80093a2 <USBD_CDC_Setup+0x13c>
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80092f0: 687b ldr r3, [r7, #4]
80092f2: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80092f6: 689b ldr r3, [r3, #8]
80092f8: 683a ldr r2, [r7, #0]
80092fa: 7850 ldrb r0, [r2, #1]
80092fc: 2200 movs r2, #0
80092fe: 6839 ldr r1, [r7, #0]
8009300: 4798 blx r3
break;
8009302: e04e b.n 80093a2 <USBD_CDC_Setup+0x13c>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8009304: 683b ldr r3, [r7, #0]
8009306: 785b ldrb r3, [r3, #1]
8009308: 2b0b cmp r3, #11
800930a: d02e beq.n 800936a <USBD_CDC_Setup+0x104>
800930c: 2b0b cmp r3, #11
800930e: dc38 bgt.n 8009382 <USBD_CDC_Setup+0x11c>
8009310: 2b00 cmp r3, #0
8009312: d002 beq.n 800931a <USBD_CDC_Setup+0xb4>
8009314: 2b0a cmp r3, #10
8009316: d014 beq.n 8009342 <USBD_CDC_Setup+0xdc>
8009318: e033 b.n 8009382 <USBD_CDC_Setup+0x11c>
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800931a: 687b ldr r3, [r7, #4]
800931c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009320: 2b03 cmp r3, #3
8009322: d107 bne.n 8009334 <USBD_CDC_Setup+0xce>
{
USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
8009324: f107 030c add.w r3, r7, #12
8009328: 2202 movs r2, #2
800932a: 4619 mov r1, r3
800932c: 6878 ldr r0, [r7, #4]
800932e: f001 f9d1 bl 800a6d4 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8009332: e02e b.n 8009392 <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
8009334: 6839 ldr r1, [r7, #0]
8009336: 6878 ldr r0, [r7, #4]
8009338: f001 f962 bl 800a600 <USBD_CtlError>
ret = USBD_FAIL;
800933c: 2302 movs r3, #2
800933e: 75fb strb r3, [r7, #23]
break;
8009340: e027 b.n 8009392 <USBD_CDC_Setup+0x12c>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009342: 687b ldr r3, [r7, #4]
8009344: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009348: 2b03 cmp r3, #3
800934a: d107 bne.n 800935c <USBD_CDC_Setup+0xf6>
{
USBD_CtlSendData(pdev, &ifalt, 1U);
800934c: f107 030f add.w r3, r7, #15
8009350: 2201 movs r2, #1
8009352: 4619 mov r1, r3
8009354: 6878 ldr r0, [r7, #4]
8009356: f001 f9bd bl 800a6d4 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800935a: e01a b.n 8009392 <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
800935c: 6839 ldr r1, [r7, #0]
800935e: 6878 ldr r0, [r7, #4]
8009360: f001 f94e bl 800a600 <USBD_CtlError>
ret = USBD_FAIL;
8009364: 2302 movs r3, #2
8009366: 75fb strb r3, [r7, #23]
break;
8009368: e013 b.n 8009392 <USBD_CDC_Setup+0x12c>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
800936a: 687b ldr r3, [r7, #4]
800936c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009370: 2b03 cmp r3, #3
8009372: d00d beq.n 8009390 <USBD_CDC_Setup+0x12a>
{
USBD_CtlError(pdev, req);
8009374: 6839 ldr r1, [r7, #0]
8009376: 6878 ldr r0, [r7, #4]
8009378: f001 f942 bl 800a600 <USBD_CtlError>
ret = USBD_FAIL;
800937c: 2302 movs r3, #2
800937e: 75fb strb r3, [r7, #23]
}
break;
8009380: e006 b.n 8009390 <USBD_CDC_Setup+0x12a>
default:
USBD_CtlError(pdev, req);
8009382: 6839 ldr r1, [r7, #0]
8009384: 6878 ldr r0, [r7, #4]
8009386: f001 f93b bl 800a600 <USBD_CtlError>
ret = USBD_FAIL;
800938a: 2302 movs r3, #2
800938c: 75fb strb r3, [r7, #23]
break;
800938e: e000 b.n 8009392 <USBD_CDC_Setup+0x12c>
break;
8009390: bf00 nop
}
break;
8009392: e006 b.n 80093a2 <USBD_CDC_Setup+0x13c>
default:
USBD_CtlError(pdev, req);
8009394: 6839 ldr r1, [r7, #0]
8009396: 6878 ldr r0, [r7, #4]
8009398: f001 f932 bl 800a600 <USBD_CtlError>
ret = USBD_FAIL;
800939c: 2302 movs r3, #2
800939e: 75fb strb r3, [r7, #23]
break;
80093a0: bf00 nop
}
return ret;
80093a2: 7dfb ldrb r3, [r7, #23]
}
80093a4: 4618 mov r0, r3
80093a6: 3718 adds r7, #24
80093a8: 46bd mov sp, r7
80093aa: bd80 pop {r7, pc}
080093ac <USBD_CDC_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
80093ac: b580 push {r7, lr}
80093ae: b084 sub sp, #16
80093b0: af00 add r7, sp, #0
80093b2: 6078 str r0, [r7, #4]
80093b4: 460b mov r3, r1
80093b6: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
80093b8: 687b ldr r3, [r7, #4]
80093ba: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80093be: 60fb str r3, [r7, #12]
PCD_HandleTypeDef *hpcd = pdev->pData;
80093c0: 687b ldr r3, [r7, #4]
80093c2: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
80093c6: 60bb str r3, [r7, #8]
if (pdev->pClassData != NULL)
80093c8: 687b ldr r3, [r7, #4]
80093ca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80093ce: 2b00 cmp r3, #0
80093d0: d03a beq.n 8009448 <USBD_CDC_DataIn+0x9c>
{
if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
80093d2: 78fa ldrb r2, [r7, #3]
80093d4: 6879 ldr r1, [r7, #4]
80093d6: 4613 mov r3, r2
80093d8: 009b lsls r3, r3, #2
80093da: 4413 add r3, r2
80093dc: 009b lsls r3, r3, #2
80093de: 440b add r3, r1
80093e0: 331c adds r3, #28
80093e2: 681b ldr r3, [r3, #0]
80093e4: 2b00 cmp r3, #0
80093e6: d029 beq.n 800943c <USBD_CDC_DataIn+0x90>
80093e8: 78fa ldrb r2, [r7, #3]
80093ea: 6879 ldr r1, [r7, #4]
80093ec: 4613 mov r3, r2
80093ee: 009b lsls r3, r3, #2
80093f0: 4413 add r3, r2
80093f2: 009b lsls r3, r3, #2
80093f4: 440b add r3, r1
80093f6: 331c adds r3, #28
80093f8: 681a ldr r2, [r3, #0]
80093fa: 78f9 ldrb r1, [r7, #3]
80093fc: 68b8 ldr r0, [r7, #8]
80093fe: 460b mov r3, r1
8009400: 009b lsls r3, r3, #2
8009402: 440b add r3, r1
8009404: 00db lsls r3, r3, #3
8009406: 4403 add r3, r0
8009408: 3320 adds r3, #32
800940a: 681b ldr r3, [r3, #0]
800940c: fbb2 f1f3 udiv r1, r2, r3
8009410: fb01 f303 mul.w r3, r1, r3
8009414: 1ad3 subs r3, r2, r3
8009416: 2b00 cmp r3, #0
8009418: d110 bne.n 800943c <USBD_CDC_DataIn+0x90>
{
/* Update the packet total length */
pdev->ep_in[epnum].total_length = 0U;
800941a: 78fa ldrb r2, [r7, #3]
800941c: 6879 ldr r1, [r7, #4]
800941e: 4613 mov r3, r2
8009420: 009b lsls r3, r3, #2
8009422: 4413 add r3, r2
8009424: 009b lsls r3, r3, #2
8009426: 440b add r3, r1
8009428: 331c adds r3, #28
800942a: 2200 movs r2, #0
800942c: 601a str r2, [r3, #0]
/* Send ZLP */
USBD_LL_Transmit(pdev, epnum, NULL, 0U);
800942e: 78f9 ldrb r1, [r7, #3]
8009430: 2300 movs r3, #0
8009432: 2200 movs r2, #0
8009434: 6878 ldr r0, [r7, #4]
8009436: f001 fe45 bl 800b0c4 <USBD_LL_Transmit>
800943a: e003 b.n 8009444 <USBD_CDC_DataIn+0x98>
}
else
{
hcdc->TxState = 0U;
800943c: 68fb ldr r3, [r7, #12]
800943e: 2200 movs r2, #0
8009440: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
return USBD_OK;
8009444: 2300 movs r3, #0
8009446: e000 b.n 800944a <USBD_CDC_DataIn+0x9e>
}
else
{
return USBD_FAIL;
8009448: 2302 movs r3, #2
}
}
800944a: 4618 mov r0, r3
800944c: 3710 adds r7, #16
800944e: 46bd mov sp, r7
8009450: bd80 pop {r7, pc}
08009452 <USBD_CDC_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
8009452: b580 push {r7, lr}
8009454: b084 sub sp, #16
8009456: af00 add r7, sp, #0
8009458: 6078 str r0, [r7, #4]
800945a: 460b mov r3, r1
800945c: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800945e: 687b ldr r3, [r7, #4]
8009460: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009464: 60fb str r3, [r7, #12]
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
8009466: 78fb ldrb r3, [r7, #3]
8009468: 4619 mov r1, r3
800946a: 6878 ldr r0, [r7, #4]
800946c: f001 fe70 bl 800b150 <USBD_LL_GetRxDataSize>
8009470: 4602 mov r2, r0
8009472: 68fb ldr r3, [r7, #12]
8009474: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
if (pdev->pClassData != NULL)
8009478: 687b ldr r3, [r7, #4]
800947a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800947e: 2b00 cmp r3, #0
8009480: d00d beq.n 800949e <USBD_CDC_DataOut+0x4c>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
8009482: 687b ldr r3, [r7, #4]
8009484: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8009488: 68db ldr r3, [r3, #12]
800948a: 68fa ldr r2, [r7, #12]
800948c: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
8009490: 68fa ldr r2, [r7, #12]
8009492: f502 7203 add.w r2, r2, #524 @ 0x20c
8009496: 4611 mov r1, r2
8009498: 4798 blx r3
return USBD_OK;
800949a: 2300 movs r3, #0
800949c: e000 b.n 80094a0 <USBD_CDC_DataOut+0x4e>
}
else
{
return USBD_FAIL;
800949e: 2302 movs r3, #2
}
}
80094a0: 4618 mov r0, r3
80094a2: 3710 adds r7, #16
80094a4: 46bd mov sp, r7
80094a6: bd80 pop {r7, pc}
080094a8 <USBD_CDC_EP0_RxReady>:
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
80094a8: b580 push {r7, lr}
80094aa: b084 sub sp, #16
80094ac: af00 add r7, sp, #0
80094ae: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80094b0: 687b ldr r3, [r7, #4]
80094b2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80094b6: 60fb str r3, [r7, #12]
if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
80094b8: 687b ldr r3, [r7, #4]
80094ba: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80094be: 2b00 cmp r3, #0
80094c0: d014 beq.n 80094ec <USBD_CDC_EP0_RxReady+0x44>
80094c2: 68fb ldr r3, [r7, #12]
80094c4: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
80094c8: 2bff cmp r3, #255 @ 0xff
80094ca: d00f beq.n 80094ec <USBD_CDC_EP0_RxReady+0x44>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
80094cc: 687b ldr r3, [r7, #4]
80094ce: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80094d2: 689b ldr r3, [r3, #8]
80094d4: 68fa ldr r2, [r7, #12]
80094d6: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
(uint8_t *)(void *)hcdc->data,
80094da: 68f9 ldr r1, [r7, #12]
(uint16_t)hcdc->CmdLength);
80094dc: 68fa ldr r2, [r7, #12]
80094de: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
80094e2: 4798 blx r3
hcdc->CmdOpCode = 0xFFU;
80094e4: 68fb ldr r3, [r7, #12]
80094e6: 22ff movs r2, #255 @ 0xff
80094e8: f883 2200 strb.w r2, [r3, #512] @ 0x200
}
return USBD_OK;
80094ec: 2300 movs r3, #0
}
80094ee: 4618 mov r0, r3
80094f0: 3710 adds r7, #16
80094f2: 46bd mov sp, r7
80094f4: bd80 pop {r7, pc}
...
080094f8 <USBD_CDC_GetFSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
80094f8: b480 push {r7}
80094fa: b083 sub sp, #12
80094fc: af00 add r7, sp, #0
80094fe: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgFSDesc);
8009500: 687b ldr r3, [r7, #4]
8009502: 2243 movs r2, #67 @ 0x43
8009504: 801a strh r2, [r3, #0]
return USBD_CDC_CfgFSDesc;
8009506: 4b03 ldr r3, [pc, #12] @ (8009514 <USBD_CDC_GetFSCfgDesc+0x1c>)
}
8009508: 4618 mov r0, r3
800950a: 370c adds r7, #12
800950c: 46bd mov sp, r7
800950e: bc80 pop {r7}
8009510: 4770 bx lr
8009512: bf00 nop
8009514: 20000098 .word 0x20000098
08009518 <USBD_CDC_GetHSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
8009518: b480 push {r7}
800951a: b083 sub sp, #12
800951c: af00 add r7, sp, #0
800951e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgHSDesc);
8009520: 687b ldr r3, [r7, #4]
8009522: 2243 movs r2, #67 @ 0x43
8009524: 801a strh r2, [r3, #0]
return USBD_CDC_CfgHSDesc;
8009526: 4b03 ldr r3, [pc, #12] @ (8009534 <USBD_CDC_GetHSCfgDesc+0x1c>)
}
8009528: 4618 mov r0, r3
800952a: 370c adds r7, #12
800952c: 46bd mov sp, r7
800952e: bc80 pop {r7}
8009530: 4770 bx lr
8009532: bf00 nop
8009534: 20000054 .word 0x20000054
08009538 <USBD_CDC_GetOtherSpeedCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
8009538: b480 push {r7}
800953a: b083 sub sp, #12
800953c: af00 add r7, sp, #0
800953e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_OtherSpeedCfgDesc);
8009540: 687b ldr r3, [r7, #4]
8009542: 2243 movs r2, #67 @ 0x43
8009544: 801a strh r2, [r3, #0]
return USBD_CDC_OtherSpeedCfgDesc;
8009546: 4b03 ldr r3, [pc, #12] @ (8009554 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
}
8009548: 4618 mov r0, r3
800954a: 370c adds r7, #12
800954c: 46bd mov sp, r7
800954e: bc80 pop {r7}
8009550: 4770 bx lr
8009552: bf00 nop
8009554: 200000dc .word 0x200000dc
08009558 <USBD_CDC_GetDeviceQualifierDescriptor>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
8009558: b480 push {r7}
800955a: b083 sub sp, #12
800955c: af00 add r7, sp, #0
800955e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_DeviceQualifierDesc);
8009560: 687b ldr r3, [r7, #4]
8009562: 220a movs r2, #10
8009564: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceQualifierDesc;
8009566: 4b03 ldr r3, [pc, #12] @ (8009574 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
}
8009568: 4618 mov r0, r3
800956a: 370c adds r7, #12
800956c: 46bd mov sp, r7
800956e: bc80 pop {r7}
8009570: 4770 bx lr
8009572: bf00 nop
8009574: 20000010 .word 0x20000010
08009578 <USBD_CDC_RegisterInterface>:
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
8009578: b480 push {r7}
800957a: b085 sub sp, #20
800957c: af00 add r7, sp, #0
800957e: 6078 str r0, [r7, #4]
8009580: 6039 str r1, [r7, #0]
uint8_t ret = USBD_FAIL;
8009582: 2302 movs r3, #2
8009584: 73fb strb r3, [r7, #15]
if (fops != NULL)
8009586: 683b ldr r3, [r7, #0]
8009588: 2b00 cmp r3, #0
800958a: d005 beq.n 8009598 <USBD_CDC_RegisterInterface+0x20>
{
pdev->pUserData = fops;
800958c: 687b ldr r3, [r7, #4]
800958e: 683a ldr r2, [r7, #0]
8009590: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
ret = USBD_OK;
8009594: 2300 movs r3, #0
8009596: 73fb strb r3, [r7, #15]
}
return ret;
8009598: 7bfb ldrb r3, [r7, #15]
}
800959a: 4618 mov r0, r3
800959c: 3714 adds r7, #20
800959e: 46bd mov sp, r7
80095a0: bc80 pop {r7}
80095a2: 4770 bx lr
080095a4 <USBD_CDC_SetTxBuffer>:
* @retval status
*/
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff,
uint16_t length)
{
80095a4: b480 push {r7}
80095a6: b087 sub sp, #28
80095a8: af00 add r7, sp, #0
80095aa: 60f8 str r0, [r7, #12]
80095ac: 60b9 str r1, [r7, #8]
80095ae: 4613 mov r3, r2
80095b0: 80fb strh r3, [r7, #6]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80095b2: 68fb ldr r3, [r7, #12]
80095b4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80095b8: 617b str r3, [r7, #20]
hcdc->TxBuffer = pbuff;
80095ba: 697b ldr r3, [r7, #20]
80095bc: 68ba ldr r2, [r7, #8]
80095be: f8c3 2208 str.w r2, [r3, #520] @ 0x208
hcdc->TxLength = length;
80095c2: 88fa ldrh r2, [r7, #6]
80095c4: 697b ldr r3, [r7, #20]
80095c6: f8c3 2210 str.w r2, [r3, #528] @ 0x210
return USBD_OK;
80095ca: 2300 movs r3, #0
}
80095cc: 4618 mov r0, r3
80095ce: 371c adds r7, #28
80095d0: 46bd mov sp, r7
80095d2: bc80 pop {r7}
80095d4: 4770 bx lr
080095d6 <USBD_CDC_SetRxBuffer>:
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff)
{
80095d6: b480 push {r7}
80095d8: b085 sub sp, #20
80095da: af00 add r7, sp, #0
80095dc: 6078 str r0, [r7, #4]
80095de: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80095e0: 687b ldr r3, [r7, #4]
80095e2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80095e6: 60fb str r3, [r7, #12]
hcdc->RxBuffer = pbuff;
80095e8: 68fb ldr r3, [r7, #12]
80095ea: 683a ldr r2, [r7, #0]
80095ec: f8c3 2204 str.w r2, [r3, #516] @ 0x204
return USBD_OK;
80095f0: 2300 movs r3, #0
}
80095f2: 4618 mov r0, r3
80095f4: 3714 adds r7, #20
80095f6: 46bd mov sp, r7
80095f8: bc80 pop {r7}
80095fa: 4770 bx lr
080095fc <USBD_CDC_TransmitPacket>:
* Transmit packet on IN endpoint
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
80095fc: b580 push {r7, lr}
80095fe: b084 sub sp, #16
8009600: af00 add r7, sp, #0
8009602: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8009604: 687b ldr r3, [r7, #4]
8009606: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800960a: 60fb str r3, [r7, #12]
if (pdev->pClassData != NULL)
800960c: 687b ldr r3, [r7, #4]
800960e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009612: 2b00 cmp r3, #0
8009614: d01c beq.n 8009650 <USBD_CDC_TransmitPacket+0x54>
{
if (hcdc->TxState == 0U)
8009616: 68fb ldr r3, [r7, #12]
8009618: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800961c: 2b00 cmp r3, #0
800961e: d115 bne.n 800964c <USBD_CDC_TransmitPacket+0x50>
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
8009620: 68fb ldr r3, [r7, #12]
8009622: 2201 movs r2, #1
8009624: f8c3 2214 str.w r2, [r3, #532] @ 0x214
/* Update the packet total length */
pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
8009628: 68fb ldr r3, [r7, #12]
800962a: f8d3 2210 ldr.w r2, [r3, #528] @ 0x210
800962e: 687b ldr r3, [r7, #4]
8009630: 631a str r2, [r3, #48] @ 0x30
/* Transmit next packet */
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
8009632: 68fb ldr r3, [r7, #12]
8009634: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
(uint16_t)hcdc->TxLength);
8009638: 68fb ldr r3, [r7, #12]
800963a: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
800963e: b29b uxth r3, r3
8009640: 2181 movs r1, #129 @ 0x81
8009642: 6878 ldr r0, [r7, #4]
8009644: f001 fd3e bl 800b0c4 <USBD_LL_Transmit>
return USBD_OK;
8009648: 2300 movs r3, #0
800964a: e002 b.n 8009652 <USBD_CDC_TransmitPacket+0x56>
}
else
{
return USBD_BUSY;
800964c: 2301 movs r3, #1
800964e: e000 b.n 8009652 <USBD_CDC_TransmitPacket+0x56>
}
}
else
{
return USBD_FAIL;
8009650: 2302 movs r3, #2
}
}
8009652: 4618 mov r0, r3
8009654: 3710 adds r7, #16
8009656: 46bd mov sp, r7
8009658: bd80 pop {r7, pc}
0800965a <USBD_CDC_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
800965a: b580 push {r7, lr}
800965c: b084 sub sp, #16
800965e: af00 add r7, sp, #0
8009660: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8009662: 687b ldr r3, [r7, #4]
8009664: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009668: 60fb str r3, [r7, #12]
/* Suspend or Resume USB Out process */
if (pdev->pClassData != NULL)
800966a: 687b ldr r3, [r7, #4]
800966c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009670: 2b00 cmp r3, #0
8009672: d017 beq.n 80096a4 <USBD_CDC_ReceivePacket+0x4a>
{
if (pdev->dev_speed == USBD_SPEED_HIGH)
8009674: 687b ldr r3, [r7, #4]
8009676: 7c1b ldrb r3, [r3, #16]
8009678: 2b00 cmp r3, #0
800967a: d109 bne.n 8009690 <USBD_CDC_ReceivePacket+0x36>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
800967c: 68fb ldr r3, [r7, #12]
800967e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8009682: f44f 7300 mov.w r3, #512 @ 0x200
8009686: 2101 movs r1, #1
8009688: 6878 ldr r0, [r7, #4]
800968a: f001 fd3e bl 800b10a <USBD_LL_PrepareReceive>
800968e: e007 b.n 80096a0 <USBD_CDC_ReceivePacket+0x46>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
8009690: 68fb ldr r3, [r7, #12]
8009692: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8009696: 2340 movs r3, #64 @ 0x40
8009698: 2101 movs r1, #1
800969a: 6878 ldr r0, [r7, #4]
800969c: f001 fd35 bl 800b10a <USBD_LL_PrepareReceive>
CDC_OUT_EP,
hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return USBD_OK;
80096a0: 2300 movs r3, #0
80096a2: e000 b.n 80096a6 <USBD_CDC_ReceivePacket+0x4c>
}
else
{
return USBD_FAIL;
80096a4: 2302 movs r3, #2
}
}
80096a6: 4618 mov r0, r3
80096a8: 3710 adds r7, #16
80096aa: 46bd mov sp, r7
80096ac: bd80 pop {r7, pc}
080096ae <USBD_Init>:
* @param id: Low level core index
* @retval None
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
80096ae: b580 push {r7, lr}
80096b0: b084 sub sp, #16
80096b2: af00 add r7, sp, #0
80096b4: 60f8 str r0, [r7, #12]
80096b6: 60b9 str r1, [r7, #8]
80096b8: 4613 mov r3, r2
80096ba: 71fb strb r3, [r7, #7]
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
80096bc: 68fb ldr r3, [r7, #12]
80096be: 2b00 cmp r3, #0
80096c0: d101 bne.n 80096c6 <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif
return USBD_FAIL;
80096c2: 2302 movs r3, #2
80096c4: e01a b.n 80096fc <USBD_Init+0x4e>
}
/* Unlink previous class*/
if (pdev->pClass != NULL)
80096c6: 68fb ldr r3, [r7, #12]
80096c8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80096cc: 2b00 cmp r3, #0
80096ce: d003 beq.n 80096d8 <USBD_Init+0x2a>
{
pdev->pClass = NULL;
80096d0: 68fb ldr r3, [r7, #12]
80096d2: 2200 movs r2, #0
80096d4: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Assign USBD Descriptors */
if (pdesc != NULL)
80096d8: 68bb ldr r3, [r7, #8]
80096da: 2b00 cmp r3, #0
80096dc: d003 beq.n 80096e6 <USBD_Init+0x38>
{
pdev->pDesc = pdesc;
80096de: 68fb ldr r3, [r7, #12]
80096e0: 68ba ldr r2, [r7, #8]
80096e2: f8c3 22b0 str.w r2, [r3, #688] @ 0x2b0
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
80096e6: 68fb ldr r3, [r7, #12]
80096e8: 2201 movs r2, #1
80096ea: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
80096ee: 68fb ldr r3, [r7, #12]
80096f0: 79fa ldrb r2, [r7, #7]
80096f2: 701a strb r2, [r3, #0]
/* Initialize low level driver */
USBD_LL_Init(pdev);
80096f4: 68f8 ldr r0, [r7, #12]
80096f6: f001 fba3 bl 800ae40 <USBD_LL_Init>
return USBD_OK;
80096fa: 2300 movs r3, #0
}
80096fc: 4618 mov r0, r3
80096fe: 3710 adds r7, #16
8009700: 46bd mov sp, r7
8009702: bd80 pop {r7, pc}
08009704 <USBD_RegisterClass>:
* @param pDevice : Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
8009704: b480 push {r7}
8009706: b085 sub sp, #20
8009708: af00 add r7, sp, #0
800970a: 6078 str r0, [r7, #4]
800970c: 6039 str r1, [r7, #0]
USBD_StatusTypeDef status = USBD_OK;
800970e: 2300 movs r3, #0
8009710: 73fb strb r3, [r7, #15]
if (pclass != NULL)
8009712: 683b ldr r3, [r7, #0]
8009714: 2b00 cmp r3, #0
8009716: d006 beq.n 8009726 <USBD_RegisterClass+0x22>
{
/* link the class to the USB Device handle */
pdev->pClass = pclass;
8009718: 687b ldr r3, [r7, #4]
800971a: 683a ldr r2, [r7, #0]
800971c: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
status = USBD_OK;
8009720: 2300 movs r3, #0
8009722: 73fb strb r3, [r7, #15]
8009724: e001 b.n 800972a <USBD_RegisterClass+0x26>
else
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif
status = USBD_FAIL;
8009726: 2302 movs r3, #2
8009728: 73fb strb r3, [r7, #15]
}
return status;
800972a: 7bfb ldrb r3, [r7, #15]
}
800972c: 4618 mov r0, r3
800972e: 3714 adds r7, #20
8009730: 46bd mov sp, r7
8009732: bc80 pop {r7}
8009734: 4770 bx lr
08009736 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
8009736: b580 push {r7, lr}
8009738: b082 sub sp, #8
800973a: af00 add r7, sp, #0
800973c: 6078 str r0, [r7, #4]
/* Start the low level driver */
USBD_LL_Start(pdev);
800973e: 6878 ldr r0, [r7, #4]
8009740: f001 fbd8 bl 800aef4 <USBD_LL_Start>
return USBD_OK;
8009744: 2300 movs r3, #0
}
8009746: 4618 mov r0, r3
8009748: 3708 adds r7, #8
800974a: 46bd mov sp, r7
800974c: bd80 pop {r7, pc}
0800974e <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
800974e: b480 push {r7}
8009750: b083 sub sp, #12
8009752: af00 add r7, sp, #0
8009754: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
8009756: 2300 movs r3, #0
}
8009758: 4618 mov r0, r3
800975a: 370c adds r7, #12
800975c: 46bd mov sp, r7
800975e: bc80 pop {r7}
8009760: 4770 bx lr
08009762 <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8009762: b580 push {r7, lr}
8009764: b084 sub sp, #16
8009766: af00 add r7, sp, #0
8009768: 6078 str r0, [r7, #4]
800976a: 460b mov r3, r1
800976c: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_FAIL;
800976e: 2302 movs r3, #2
8009770: 73fb strb r3, [r7, #15]
if (pdev->pClass != NULL)
8009772: 687b ldr r3, [r7, #4]
8009774: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009778: 2b00 cmp r3, #0
800977a: d00c beq.n 8009796 <USBD_SetClassConfig+0x34>
{
/* Set configuration and Start the Class*/
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
800977c: 687b ldr r3, [r7, #4]
800977e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009782: 681b ldr r3, [r3, #0]
8009784: 78fa ldrb r2, [r7, #3]
8009786: 4611 mov r1, r2
8009788: 6878 ldr r0, [r7, #4]
800978a: 4798 blx r3
800978c: 4603 mov r3, r0
800978e: 2b00 cmp r3, #0
8009790: d101 bne.n 8009796 <USBD_SetClassConfig+0x34>
{
ret = USBD_OK;
8009792: 2300 movs r3, #0
8009794: 73fb strb r3, [r7, #15]
}
}
return ret;
8009796: 7bfb ldrb r3, [r7, #15]
}
8009798: 4618 mov r0, r3
800979a: 3710 adds r7, #16
800979c: 46bd mov sp, r7
800979e: bd80 pop {r7, pc}
080097a0 <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status: USBD_StatusTypeDef
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80097a0: b580 push {r7, lr}
80097a2: b082 sub sp, #8
80097a4: af00 add r7, sp, #0
80097a6: 6078 str r0, [r7, #4]
80097a8: 460b mov r3, r1
80097aa: 70fb strb r3, [r7, #3]
/* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx);
80097ac: 687b ldr r3, [r7, #4]
80097ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80097b2: 685b ldr r3, [r3, #4]
80097b4: 78fa ldrb r2, [r7, #3]
80097b6: 4611 mov r1, r2
80097b8: 6878 ldr r0, [r7, #4]
80097ba: 4798 blx r3
return USBD_OK;
80097bc: 2300 movs r3, #0
}
80097be: 4618 mov r0, r3
80097c0: 3708 adds r7, #8
80097c2: 46bd mov sp, r7
80097c4: bd80 pop {r7, pc}
080097c6 <USBD_LL_SetupStage>:
* Handle the setup stage
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
80097c6: b580 push {r7, lr}
80097c8: b082 sub sp, #8
80097ca: af00 add r7, sp, #0
80097cc: 6078 str r0, [r7, #4]
80097ce: 6039 str r1, [r7, #0]
USBD_ParseSetupRequest(&pdev->request, psetup);
80097d0: 687b ldr r3, [r7, #4]
80097d2: f503 732a add.w r3, r3, #680 @ 0x2a8
80097d6: 6839 ldr r1, [r7, #0]
80097d8: 4618 mov r0, r3
80097da: f000 fed8 bl 800a58e <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
80097de: 687b ldr r3, [r7, #4]
80097e0: 2201 movs r2, #1
80097e2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
80097e6: 687b ldr r3, [r7, #4]
80097e8: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
80097ec: 461a mov r2, r3
80097ee: 687b ldr r3, [r7, #4]
80097f0: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
80097f4: 687b ldr r3, [r7, #4]
80097f6: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
80097fa: f003 031f and.w r3, r3, #31
80097fe: 2b02 cmp r3, #2
8009800: d016 beq.n 8009830 <USBD_LL_SetupStage+0x6a>
8009802: 2b02 cmp r3, #2
8009804: d81c bhi.n 8009840 <USBD_LL_SetupStage+0x7a>
8009806: 2b00 cmp r3, #0
8009808: d002 beq.n 8009810 <USBD_LL_SetupStage+0x4a>
800980a: 2b01 cmp r3, #1
800980c: d008 beq.n 8009820 <USBD_LL_SetupStage+0x5a>
800980e: e017 b.n 8009840 <USBD_LL_SetupStage+0x7a>
{
case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq(pdev, &pdev->request);
8009810: 687b ldr r3, [r7, #4]
8009812: f503 732a add.w r3, r3, #680 @ 0x2a8
8009816: 4619 mov r1, r3
8009818: 6878 ldr r0, [r7, #4]
800981a: f000 f9cb bl 8009bb4 <USBD_StdDevReq>
break;
800981e: e01a b.n 8009856 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request);
8009820: 687b ldr r3, [r7, #4]
8009822: f503 732a add.w r3, r3, #680 @ 0x2a8
8009826: 4619 mov r1, r3
8009828: 6878 ldr r0, [r7, #4]
800982a: f000 fa2d bl 8009c88 <USBD_StdItfReq>
break;
800982e: e012 b.n 8009856 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request);
8009830: 687b ldr r3, [r7, #4]
8009832: f503 732a add.w r3, r3, #680 @ 0x2a8
8009836: 4619 mov r1, r3
8009838: 6878 ldr r0, [r7, #4]
800983a: f000 fa6d bl 8009d18 <USBD_StdEPReq>
break;
800983e: e00a b.n 8009856 <USBD_LL_SetupStage+0x90>
default:
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
8009840: 687b ldr r3, [r7, #4]
8009842: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
8009846: f023 037f bic.w r3, r3, #127 @ 0x7f
800984a: b2db uxtb r3, r3
800984c: 4619 mov r1, r3
800984e: 6878 ldr r0, [r7, #4]
8009850: f001 fbb0 bl 800afb4 <USBD_LL_StallEP>
break;
8009854: bf00 nop
}
return USBD_OK;
8009856: 2300 movs r3, #0
}
8009858: 4618 mov r0, r3
800985a: 3708 adds r7, #8
800985c: 46bd mov sp, r7
800985e: bd80 pop {r7, pc}
08009860 <USBD_LL_DataOutStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8009860: b580 push {r7, lr}
8009862: b086 sub sp, #24
8009864: af00 add r7, sp, #0
8009866: 60f8 str r0, [r7, #12]
8009868: 460b mov r3, r1
800986a: 607a str r2, [r7, #4]
800986c: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
800986e: 7afb ldrb r3, [r7, #11]
8009870: 2b00 cmp r3, #0
8009872: d14b bne.n 800990c <USBD_LL_DataOutStage+0xac>
{
pep = &pdev->ep_out[0];
8009874: 68fb ldr r3, [r7, #12]
8009876: f503 73aa add.w r3, r3, #340 @ 0x154
800987a: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
800987c: 68fb ldr r3, [r7, #12]
800987e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009882: 2b03 cmp r3, #3
8009884: d134 bne.n 80098f0 <USBD_LL_DataOutStage+0x90>
{
if (pep->rem_length > pep->maxpacket)
8009886: 697b ldr r3, [r7, #20]
8009888: 68da ldr r2, [r3, #12]
800988a: 697b ldr r3, [r7, #20]
800988c: 691b ldr r3, [r3, #16]
800988e: 429a cmp r2, r3
8009890: d919 bls.n 80098c6 <USBD_LL_DataOutStage+0x66>
{
pep->rem_length -= pep->maxpacket;
8009892: 697b ldr r3, [r7, #20]
8009894: 68da ldr r2, [r3, #12]
8009896: 697b ldr r3, [r7, #20]
8009898: 691b ldr r3, [r3, #16]
800989a: 1ad2 subs r2, r2, r3
800989c: 697b ldr r3, [r7, #20]
800989e: 60da str r2, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80098a0: 697b ldr r3, [r7, #20]
80098a2: 68da ldr r2, [r3, #12]
80098a4: 697b ldr r3, [r7, #20]
80098a6: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
80098a8: 429a cmp r2, r3
80098aa: d203 bcs.n 80098b4 <USBD_LL_DataOutStage+0x54>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80098ac: 697b ldr r3, [r7, #20]
80098ae: 68db ldr r3, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
80098b0: b29b uxth r3, r3
80098b2: e002 b.n 80098ba <USBD_LL_DataOutStage+0x5a>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80098b4: 697b ldr r3, [r7, #20]
80098b6: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
80098b8: b29b uxth r3, r3
80098ba: 461a mov r2, r3
80098bc: 6879 ldr r1, [r7, #4]
80098be: 68f8 ldr r0, [r7, #12]
80098c0: f000 ff54 bl 800a76c <USBD_CtlContinueRx>
80098c4: e038 b.n 8009938 <USBD_LL_DataOutStage+0xd8>
}
else
{
if ((pdev->pClass->EP0_RxReady != NULL) &&
80098c6: 68fb ldr r3, [r7, #12]
80098c8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80098cc: 691b ldr r3, [r3, #16]
80098ce: 2b00 cmp r3, #0
80098d0: d00a beq.n 80098e8 <USBD_LL_DataOutStage+0x88>
(pdev->dev_state == USBD_STATE_CONFIGURED))
80098d2: 68fb ldr r3, [r7, #12]
80098d4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_RxReady != NULL) &&
80098d8: 2b03 cmp r3, #3
80098da: d105 bne.n 80098e8 <USBD_LL_DataOutStage+0x88>
{
pdev->pClass->EP0_RxReady(pdev);
80098dc: 68fb ldr r3, [r7, #12]
80098de: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80098e2: 691b ldr r3, [r3, #16]
80098e4: 68f8 ldr r0, [r7, #12]
80098e6: 4798 blx r3
}
USBD_CtlSendStatus(pdev);
80098e8: 68f8 ldr r0, [r7, #12]
80098ea: f000 ff51 bl 800a790 <USBD_CtlSendStatus>
80098ee: e023 b.n 8009938 <USBD_LL_DataOutStage+0xd8>
}
}
else
{
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
80098f0: 68fb ldr r3, [r7, #12]
80098f2: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
80098f6: 2b05 cmp r3, #5
80098f8: d11e bne.n 8009938 <USBD_LL_DataOutStage+0xd8>
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
80098fa: 68fb ldr r3, [r7, #12]
80098fc: 2200 movs r2, #0
80098fe: f8c3 2294 str.w r2, [r3, #660] @ 0x294
USBD_LL_StallEP(pdev, 0U);
8009902: 2100 movs r1, #0
8009904: 68f8 ldr r0, [r7, #12]
8009906: f001 fb55 bl 800afb4 <USBD_LL_StallEP>
800990a: e015 b.n 8009938 <USBD_LL_DataOutStage+0xd8>
}
}
}
else if ((pdev->pClass->DataOut != NULL) &&
800990c: 68fb ldr r3, [r7, #12]
800990e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009912: 699b ldr r3, [r3, #24]
8009914: 2b00 cmp r3, #0
8009916: d00d beq.n 8009934 <USBD_LL_DataOutStage+0xd4>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8009918: 68fb ldr r3, [r7, #12]
800991a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataOut != NULL) &&
800991e: 2b03 cmp r3, #3
8009920: d108 bne.n 8009934 <USBD_LL_DataOutStage+0xd4>
{
pdev->pClass->DataOut(pdev, epnum);
8009922: 68fb ldr r3, [r7, #12]
8009924: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009928: 699b ldr r3, [r3, #24]
800992a: 7afa ldrb r2, [r7, #11]
800992c: 4611 mov r1, r2
800992e: 68f8 ldr r0, [r7, #12]
8009930: 4798 blx r3
8009932: e001 b.n 8009938 <USBD_LL_DataOutStage+0xd8>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
8009934: 2302 movs r3, #2
8009936: e000 b.n 800993a <USBD_LL_DataOutStage+0xda>
}
return USBD_OK;
8009938: 2300 movs r3, #0
}
800993a: 4618 mov r0, r3
800993c: 3718 adds r7, #24
800993e: 46bd mov sp, r7
8009940: bd80 pop {r7, pc}
08009942 <USBD_LL_DataInStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8009942: b580 push {r7, lr}
8009944: b086 sub sp, #24
8009946: af00 add r7, sp, #0
8009948: 60f8 str r0, [r7, #12]
800994a: 460b mov r3, r1
800994c: 607a str r2, [r7, #4]
800994e: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
8009950: 7afb ldrb r3, [r7, #11]
8009952: 2b00 cmp r3, #0
8009954: d17f bne.n 8009a56 <USBD_LL_DataInStage+0x114>
{
pep = &pdev->ep_in[0];
8009956: 68fb ldr r3, [r7, #12]
8009958: 3314 adds r3, #20
800995a: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
800995c: 68fb ldr r3, [r7, #12]
800995e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009962: 2b02 cmp r3, #2
8009964: d15c bne.n 8009a20 <USBD_LL_DataInStage+0xde>
{
if (pep->rem_length > pep->maxpacket)
8009966: 697b ldr r3, [r7, #20]
8009968: 68da ldr r2, [r3, #12]
800996a: 697b ldr r3, [r7, #20]
800996c: 691b ldr r3, [r3, #16]
800996e: 429a cmp r2, r3
8009970: d915 bls.n 800999e <USBD_LL_DataInStage+0x5c>
{
pep->rem_length -= pep->maxpacket;
8009972: 697b ldr r3, [r7, #20]
8009974: 68da ldr r2, [r3, #12]
8009976: 697b ldr r3, [r7, #20]
8009978: 691b ldr r3, [r3, #16]
800997a: 1ad2 subs r2, r2, r3
800997c: 697b ldr r3, [r7, #20]
800997e: 60da str r2, [r3, #12]
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
8009980: 697b ldr r3, [r7, #20]
8009982: 68db ldr r3, [r3, #12]
8009984: b29b uxth r3, r3
8009986: 461a mov r2, r3
8009988: 6879 ldr r1, [r7, #4]
800998a: 68f8 ldr r0, [r7, #12]
800998c: f000 febe bl 800a70c <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8009990: 2300 movs r3, #0
8009992: 2200 movs r2, #0
8009994: 2100 movs r1, #0
8009996: 68f8 ldr r0, [r7, #12]
8009998: f001 fbb7 bl 800b10a <USBD_LL_PrepareReceive>
800999c: e04e b.n 8009a3c <USBD_LL_DataInStage+0xfa>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->total_length % pep->maxpacket == 0U) &&
800999e: 697b ldr r3, [r7, #20]
80099a0: 689b ldr r3, [r3, #8]
80099a2: 697a ldr r2, [r7, #20]
80099a4: 6912 ldr r2, [r2, #16]
80099a6: fbb3 f1f2 udiv r1, r3, r2
80099aa: fb01 f202 mul.w r2, r1, r2
80099ae: 1a9b subs r3, r3, r2
80099b0: 2b00 cmp r3, #0
80099b2: d11c bne.n 80099ee <USBD_LL_DataInStage+0xac>
(pep->total_length >= pep->maxpacket) &&
80099b4: 697b ldr r3, [r7, #20]
80099b6: 689a ldr r2, [r3, #8]
80099b8: 697b ldr r3, [r7, #20]
80099ba: 691b ldr r3, [r3, #16]
if ((pep->total_length % pep->maxpacket == 0U) &&
80099bc: 429a cmp r2, r3
80099be: d316 bcc.n 80099ee <USBD_LL_DataInStage+0xac>
(pep->total_length < pdev->ep0_data_len))
80099c0: 697b ldr r3, [r7, #20]
80099c2: 689a ldr r2, [r3, #8]
80099c4: 68fb ldr r3, [r7, #12]
80099c6: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
80099ca: 429a cmp r2, r3
80099cc: d20f bcs.n 80099ee <USBD_LL_DataInStage+0xac>
{
USBD_CtlContinueSendData(pdev, NULL, 0U);
80099ce: 2200 movs r2, #0
80099d0: 2100 movs r1, #0
80099d2: 68f8 ldr r0, [r7, #12]
80099d4: f000 fe9a bl 800a70c <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
80099d8: 68fb ldr r3, [r7, #12]
80099da: 2200 movs r2, #0
80099dc: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80099e0: 2300 movs r3, #0
80099e2: 2200 movs r2, #0
80099e4: 2100 movs r1, #0
80099e6: 68f8 ldr r0, [r7, #12]
80099e8: f001 fb8f bl 800b10a <USBD_LL_PrepareReceive>
80099ec: e026 b.n 8009a3c <USBD_LL_DataInStage+0xfa>
}
else
{
if ((pdev->pClass->EP0_TxSent != NULL) &&
80099ee: 68fb ldr r3, [r7, #12]
80099f0: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80099f4: 68db ldr r3, [r3, #12]
80099f6: 2b00 cmp r3, #0
80099f8: d00a beq.n 8009a10 <USBD_LL_DataInStage+0xce>
(pdev->dev_state == USBD_STATE_CONFIGURED))
80099fa: 68fb ldr r3, [r7, #12]
80099fc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_TxSent != NULL) &&
8009a00: 2b03 cmp r3, #3
8009a02: d105 bne.n 8009a10 <USBD_LL_DataInStage+0xce>
{
pdev->pClass->EP0_TxSent(pdev);
8009a04: 68fb ldr r3, [r7, #12]
8009a06: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009a0a: 68db ldr r3, [r3, #12]
8009a0c: 68f8 ldr r0, [r7, #12]
8009a0e: 4798 blx r3
}
USBD_LL_StallEP(pdev, 0x80U);
8009a10: 2180 movs r1, #128 @ 0x80
8009a12: 68f8 ldr r0, [r7, #12]
8009a14: f001 face bl 800afb4 <USBD_LL_StallEP>
USBD_CtlReceiveStatus(pdev);
8009a18: 68f8 ldr r0, [r7, #12]
8009a1a: f000 fecc bl 800a7b6 <USBD_CtlReceiveStatus>
8009a1e: e00d b.n 8009a3c <USBD_LL_DataInStage+0xfa>
}
}
}
else
{
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
8009a20: 68fb ldr r3, [r7, #12]
8009a22: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8009a26: 2b04 cmp r3, #4
8009a28: d004 beq.n 8009a34 <USBD_LL_DataInStage+0xf2>
(pdev->ep0_state == USBD_EP0_IDLE))
8009a2a: 68fb ldr r3, [r7, #12]
8009a2c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
8009a30: 2b00 cmp r3, #0
8009a32: d103 bne.n 8009a3c <USBD_LL_DataInStage+0xfa>
{
USBD_LL_StallEP(pdev, 0x80U);
8009a34: 2180 movs r1, #128 @ 0x80
8009a36: 68f8 ldr r0, [r7, #12]
8009a38: f001 fabc bl 800afb4 <USBD_LL_StallEP>
}
}
if (pdev->dev_test_mode == 1U)
8009a3c: 68fb ldr r3, [r7, #12]
8009a3e: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
8009a42: 2b01 cmp r3, #1
8009a44: d11d bne.n 8009a82 <USBD_LL_DataInStage+0x140>
{
USBD_RunTestMode(pdev);
8009a46: 68f8 ldr r0, [r7, #12]
8009a48: f7ff fe81 bl 800974e <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
8009a4c: 68fb ldr r3, [r7, #12]
8009a4e: 2200 movs r2, #0
8009a50: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
8009a54: e015 b.n 8009a82 <USBD_LL_DataInStage+0x140>
}
}
else if ((pdev->pClass->DataIn != NULL) &&
8009a56: 68fb ldr r3, [r7, #12]
8009a58: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009a5c: 695b ldr r3, [r3, #20]
8009a5e: 2b00 cmp r3, #0
8009a60: d00d beq.n 8009a7e <USBD_LL_DataInStage+0x13c>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8009a62: 68fb ldr r3, [r7, #12]
8009a64: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataIn != NULL) &&
8009a68: 2b03 cmp r3, #3
8009a6a: d108 bne.n 8009a7e <USBD_LL_DataInStage+0x13c>
{
pdev->pClass->DataIn(pdev, epnum);
8009a6c: 68fb ldr r3, [r7, #12]
8009a6e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009a72: 695b ldr r3, [r3, #20]
8009a74: 7afa ldrb r2, [r7, #11]
8009a76: 4611 mov r1, r2
8009a78: 68f8 ldr r0, [r7, #12]
8009a7a: 4798 blx r3
8009a7c: e001 b.n 8009a82 <USBD_LL_DataInStage+0x140>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
8009a7e: 2302 movs r3, #2
8009a80: e000 b.n 8009a84 <USBD_LL_DataInStage+0x142>
}
return USBD_OK;
8009a82: 2300 movs r3, #0
}
8009a84: 4618 mov r0, r3
8009a86: 3718 adds r7, #24
8009a88: 46bd mov sp, r7
8009a8a: bd80 pop {r7, pc}
08009a8c <USBD_LL_Reset>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
8009a8c: b580 push {r7, lr}
8009a8e: b082 sub sp, #8
8009a90: af00 add r7, sp, #0
8009a92: 6078 str r0, [r7, #4]
/* Open EP0 OUT */
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8009a94: 2340 movs r3, #64 @ 0x40
8009a96: 2200 movs r2, #0
8009a98: 2100 movs r1, #0
8009a9a: 6878 ldr r0, [r7, #4]
8009a9c: f001 fa45 bl 800af2a <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
8009aa0: 687b ldr r3, [r7, #4]
8009aa2: 2201 movs r2, #1
8009aa4: f8c3 2158 str.w r2, [r3, #344] @ 0x158
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
8009aa8: 687b ldr r3, [r7, #4]
8009aaa: 2240 movs r2, #64 @ 0x40
8009aac: f8c3 2164 str.w r2, [r3, #356] @ 0x164
/* Open EP0 IN */
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8009ab0: 2340 movs r3, #64 @ 0x40
8009ab2: 2200 movs r2, #0
8009ab4: 2180 movs r1, #128 @ 0x80
8009ab6: 6878 ldr r0, [r7, #4]
8009ab8: f001 fa37 bl 800af2a <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
8009abc: 687b ldr r3, [r7, #4]
8009abe: 2201 movs r2, #1
8009ac0: 619a str r2, [r3, #24]
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
8009ac2: 687b ldr r3, [r7, #4]
8009ac4: 2240 movs r2, #64 @ 0x40
8009ac6: 625a str r2, [r3, #36] @ 0x24
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
8009ac8: 687b ldr r3, [r7, #4]
8009aca: 2201 movs r2, #1
8009acc: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
8009ad0: 687b ldr r3, [r7, #4]
8009ad2: 2200 movs r2, #0
8009ad4: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
8009ad8: 687b ldr r3, [r7, #4]
8009ada: 2200 movs r2, #0
8009adc: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
8009ade: 687b ldr r3, [r7, #4]
8009ae0: 2200 movs r2, #0
8009ae2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
if (pdev->pClassData)
8009ae6: 687b ldr r3, [r7, #4]
8009ae8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8009aec: 2b00 cmp r3, #0
8009aee: d009 beq.n 8009b04 <USBD_LL_Reset+0x78>
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
8009af0: 687b ldr r3, [r7, #4]
8009af2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009af6: 685b ldr r3, [r3, #4]
8009af8: 687a ldr r2, [r7, #4]
8009afa: 6852 ldr r2, [r2, #4]
8009afc: b2d2 uxtb r2, r2
8009afe: 4611 mov r1, r2
8009b00: 6878 ldr r0, [r7, #4]
8009b02: 4798 blx r3
}
return USBD_OK;
8009b04: 2300 movs r3, #0
}
8009b06: 4618 mov r0, r3
8009b08: 3708 adds r7, #8
8009b0a: 46bd mov sp, r7
8009b0c: bd80 pop {r7, pc}
08009b0e <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8009b0e: b480 push {r7}
8009b10: b083 sub sp, #12
8009b12: af00 add r7, sp, #0
8009b14: 6078 str r0, [r7, #4]
8009b16: 460b mov r3, r1
8009b18: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
8009b1a: 687b ldr r3, [r7, #4]
8009b1c: 78fa ldrb r2, [r7, #3]
8009b1e: 741a strb r2, [r3, #16]
return USBD_OK;
8009b20: 2300 movs r3, #0
}
8009b22: 4618 mov r0, r3
8009b24: 370c adds r7, #12
8009b26: 46bd mov sp, r7
8009b28: bc80 pop {r7}
8009b2a: 4770 bx lr
08009b2c <USBD_LL_Suspend>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8009b2c: b480 push {r7}
8009b2e: b083 sub sp, #12
8009b30: af00 add r7, sp, #0
8009b32: 6078 str r0, [r7, #4]
pdev->dev_old_state = pdev->dev_state;
8009b34: 687b ldr r3, [r7, #4]
8009b36: f893 229c ldrb.w r2, [r3, #668] @ 0x29c
8009b3a: 687b ldr r3, [r7, #4]
8009b3c: f883 229d strb.w r2, [r3, #669] @ 0x29d
pdev->dev_state = USBD_STATE_SUSPENDED;
8009b40: 687b ldr r3, [r7, #4]
8009b42: 2204 movs r2, #4
8009b44: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
8009b48: 2300 movs r3, #0
}
8009b4a: 4618 mov r0, r3
8009b4c: 370c adds r7, #12
8009b4e: 46bd mov sp, r7
8009b50: bc80 pop {r7}
8009b52: 4770 bx lr
08009b54 <USBD_LL_Resume>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
8009b54: b480 push {r7}
8009b56: b083 sub sp, #12
8009b58: af00 add r7, sp, #0
8009b5a: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8009b5c: 687b ldr r3, [r7, #4]
8009b5e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009b62: 2b04 cmp r3, #4
8009b64: d105 bne.n 8009b72 <USBD_LL_Resume+0x1e>
{
pdev->dev_state = pdev->dev_old_state;
8009b66: 687b ldr r3, [r7, #4]
8009b68: f893 229d ldrb.w r2, [r3, #669] @ 0x29d
8009b6c: 687b ldr r3, [r7, #4]
8009b6e: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
8009b72: 2300 movs r3, #0
}
8009b74: 4618 mov r0, r3
8009b76: 370c adds r7, #12
8009b78: 46bd mov sp, r7
8009b7a: bc80 pop {r7}
8009b7c: 4770 bx lr
08009b7e <USBD_LL_SOF>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
8009b7e: b580 push {r7, lr}
8009b80: b082 sub sp, #8
8009b82: af00 add r7, sp, #0
8009b84: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8009b86: 687b ldr r3, [r7, #4]
8009b88: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009b8c: 2b03 cmp r3, #3
8009b8e: d10b bne.n 8009ba8 <USBD_LL_SOF+0x2a>
{
if (pdev->pClass->SOF != NULL)
8009b90: 687b ldr r3, [r7, #4]
8009b92: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009b96: 69db ldr r3, [r3, #28]
8009b98: 2b00 cmp r3, #0
8009b9a: d005 beq.n 8009ba8 <USBD_LL_SOF+0x2a>
{
pdev->pClass->SOF(pdev);
8009b9c: 687b ldr r3, [r7, #4]
8009b9e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009ba2: 69db ldr r3, [r3, #28]
8009ba4: 6878 ldr r0, [r7, #4]
8009ba6: 4798 blx r3
}
}
return USBD_OK;
8009ba8: 2300 movs r3, #0
}
8009baa: 4618 mov r0, r3
8009bac: 3708 adds r7, #8
8009bae: 46bd mov sp, r7
8009bb0: bd80 pop {r7, pc}
...
08009bb4 <USBD_StdDevReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009bb4: b580 push {r7, lr}
8009bb6: b084 sub sp, #16
8009bb8: af00 add r7, sp, #0
8009bba: 6078 str r0, [r7, #4]
8009bbc: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8009bbe: 2300 movs r3, #0
8009bc0: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009bc2: 683b ldr r3, [r7, #0]
8009bc4: 781b ldrb r3, [r3, #0]
8009bc6: f003 0360 and.w r3, r3, #96 @ 0x60
8009bca: 2b40 cmp r3, #64 @ 0x40
8009bcc: d005 beq.n 8009bda <USBD_StdDevReq+0x26>
8009bce: 2b40 cmp r3, #64 @ 0x40
8009bd0: d84f bhi.n 8009c72 <USBD_StdDevReq+0xbe>
8009bd2: 2b00 cmp r3, #0
8009bd4: d009 beq.n 8009bea <USBD_StdDevReq+0x36>
8009bd6: 2b20 cmp r3, #32
8009bd8: d14b bne.n 8009c72 <USBD_StdDevReq+0xbe>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8009bda: 687b ldr r3, [r7, #4]
8009bdc: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009be0: 689b ldr r3, [r3, #8]
8009be2: 6839 ldr r1, [r7, #0]
8009be4: 6878 ldr r0, [r7, #4]
8009be6: 4798 blx r3
break;
8009be8: e048 b.n 8009c7c <USBD_StdDevReq+0xc8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8009bea: 683b ldr r3, [r7, #0]
8009bec: 785b ldrb r3, [r3, #1]
8009bee: 2b09 cmp r3, #9
8009bf0: d839 bhi.n 8009c66 <USBD_StdDevReq+0xb2>
8009bf2: a201 add r2, pc, #4 @ (adr r2, 8009bf8 <USBD_StdDevReq+0x44>)
8009bf4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009bf8: 08009c49 .word 0x08009c49
8009bfc: 08009c5d .word 0x08009c5d
8009c00: 08009c67 .word 0x08009c67
8009c04: 08009c53 .word 0x08009c53
8009c08: 08009c67 .word 0x08009c67
8009c0c: 08009c2b .word 0x08009c2b
8009c10: 08009c21 .word 0x08009c21
8009c14: 08009c67 .word 0x08009c67
8009c18: 08009c3f .word 0x08009c3f
8009c1c: 08009c35 .word 0x08009c35
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
8009c20: 6839 ldr r1, [r7, #0]
8009c22: 6878 ldr r0, [r7, #4]
8009c24: f000 f9dc bl 8009fe0 <USBD_GetDescriptor>
break;
8009c28: e022 b.n 8009c70 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
8009c2a: 6839 ldr r1, [r7, #0]
8009c2c: 6878 ldr r0, [r7, #4]
8009c2e: f000 fb3f bl 800a2b0 <USBD_SetAddress>
break;
8009c32: e01d b.n 8009c70 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_CONFIGURATION:
USBD_SetConfig(pdev, req);
8009c34: 6839 ldr r1, [r7, #0]
8009c36: 6878 ldr r0, [r7, #4]
8009c38: f000 fb7e bl 800a338 <USBD_SetConfig>
break;
8009c3c: e018 b.n 8009c70 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
8009c3e: 6839 ldr r1, [r7, #0]
8009c40: 6878 ldr r0, [r7, #4]
8009c42: f000 fc07 bl 800a454 <USBD_GetConfig>
break;
8009c46: e013 b.n 8009c70 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
8009c48: 6839 ldr r1, [r7, #0]
8009c4a: 6878 ldr r0, [r7, #4]
8009c4c: f000 fc37 bl 800a4be <USBD_GetStatus>
break;
8009c50: e00e b.n 8009c70 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
8009c52: 6839 ldr r1, [r7, #0]
8009c54: 6878 ldr r0, [r7, #4]
8009c56: f000 fc65 bl 800a524 <USBD_SetFeature>
break;
8009c5a: e009 b.n 8009c70 <USBD_StdDevReq+0xbc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
8009c5c: 6839 ldr r1, [r7, #0]
8009c5e: 6878 ldr r0, [r7, #4]
8009c60: f000 fc74 bl 800a54c <USBD_ClrFeature>
break;
8009c64: e004 b.n 8009c70 <USBD_StdDevReq+0xbc>
default:
USBD_CtlError(pdev, req);
8009c66: 6839 ldr r1, [r7, #0]
8009c68: 6878 ldr r0, [r7, #4]
8009c6a: f000 fcc9 bl 800a600 <USBD_CtlError>
break;
8009c6e: bf00 nop
}
break;
8009c70: e004 b.n 8009c7c <USBD_StdDevReq+0xc8>
default:
USBD_CtlError(pdev, req);
8009c72: 6839 ldr r1, [r7, #0]
8009c74: 6878 ldr r0, [r7, #4]
8009c76: f000 fcc3 bl 800a600 <USBD_CtlError>
break;
8009c7a: bf00 nop
}
return ret;
8009c7c: 7bfb ldrb r3, [r7, #15]
}
8009c7e: 4618 mov r0, r3
8009c80: 3710 adds r7, #16
8009c82: 46bd mov sp, r7
8009c84: bd80 pop {r7, pc}
8009c86: bf00 nop
08009c88 <USBD_StdItfReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009c88: b580 push {r7, lr}
8009c8a: b084 sub sp, #16
8009c8c: af00 add r7, sp, #0
8009c8e: 6078 str r0, [r7, #4]
8009c90: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8009c92: 2300 movs r3, #0
8009c94: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009c96: 683b ldr r3, [r7, #0]
8009c98: 781b ldrb r3, [r3, #0]
8009c9a: f003 0360 and.w r3, r3, #96 @ 0x60
8009c9e: 2b40 cmp r3, #64 @ 0x40
8009ca0: d005 beq.n 8009cae <USBD_StdItfReq+0x26>
8009ca2: 2b40 cmp r3, #64 @ 0x40
8009ca4: d82e bhi.n 8009d04 <USBD_StdItfReq+0x7c>
8009ca6: 2b00 cmp r3, #0
8009ca8: d001 beq.n 8009cae <USBD_StdItfReq+0x26>
8009caa: 2b20 cmp r3, #32
8009cac: d12a bne.n 8009d04 <USBD_StdItfReq+0x7c>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
8009cae: 687b ldr r3, [r7, #4]
8009cb0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009cb4: 3b01 subs r3, #1
8009cb6: 2b02 cmp r3, #2
8009cb8: d81d bhi.n 8009cf6 <USBD_StdItfReq+0x6e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
8009cba: 683b ldr r3, [r7, #0]
8009cbc: 889b ldrh r3, [r3, #4]
8009cbe: b2db uxtb r3, r3
8009cc0: 2b01 cmp r3, #1
8009cc2: d813 bhi.n 8009cec <USBD_StdItfReq+0x64>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8009cc4: 687b ldr r3, [r7, #4]
8009cc6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009cca: 689b ldr r3, [r3, #8]
8009ccc: 6839 ldr r1, [r7, #0]
8009cce: 6878 ldr r0, [r7, #4]
8009cd0: 4798 blx r3
8009cd2: 4603 mov r3, r0
8009cd4: 73fb strb r3, [r7, #15]
if ((req->wLength == 0U) && (ret == USBD_OK))
8009cd6: 683b ldr r3, [r7, #0]
8009cd8: 88db ldrh r3, [r3, #6]
8009cda: 2b00 cmp r3, #0
8009cdc: d110 bne.n 8009d00 <USBD_StdItfReq+0x78>
8009cde: 7bfb ldrb r3, [r7, #15]
8009ce0: 2b00 cmp r3, #0
8009ce2: d10d bne.n 8009d00 <USBD_StdItfReq+0x78>
{
USBD_CtlSendStatus(pdev);
8009ce4: 6878 ldr r0, [r7, #4]
8009ce6: f000 fd53 bl 800a790 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8009cea: e009 b.n 8009d00 <USBD_StdItfReq+0x78>
USBD_CtlError(pdev, req);
8009cec: 6839 ldr r1, [r7, #0]
8009cee: 6878 ldr r0, [r7, #4]
8009cf0: f000 fc86 bl 800a600 <USBD_CtlError>
break;
8009cf4: e004 b.n 8009d00 <USBD_StdItfReq+0x78>
default:
USBD_CtlError(pdev, req);
8009cf6: 6839 ldr r1, [r7, #0]
8009cf8: 6878 ldr r0, [r7, #4]
8009cfa: f000 fc81 bl 800a600 <USBD_CtlError>
break;
8009cfe: e000 b.n 8009d02 <USBD_StdItfReq+0x7a>
break;
8009d00: bf00 nop
}
break;
8009d02: e004 b.n 8009d0e <USBD_StdItfReq+0x86>
default:
USBD_CtlError(pdev, req);
8009d04: 6839 ldr r1, [r7, #0]
8009d06: 6878 ldr r0, [r7, #4]
8009d08: f000 fc7a bl 800a600 <USBD_CtlError>
break;
8009d0c: bf00 nop
}
return USBD_OK;
8009d0e: 2300 movs r3, #0
}
8009d10: 4618 mov r0, r3
8009d12: 3710 adds r7, #16
8009d14: 46bd mov sp, r7
8009d16: bd80 pop {r7, pc}
08009d18 <USBD_StdEPReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009d18: b580 push {r7, lr}
8009d1a: b084 sub sp, #16
8009d1c: af00 add r7, sp, #0
8009d1e: 6078 str r0, [r7, #4]
8009d20: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
USBD_StatusTypeDef ret = USBD_OK;
8009d22: 2300 movs r3, #0
8009d24: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
8009d26: 683b ldr r3, [r7, #0]
8009d28: 889b ldrh r3, [r3, #4]
8009d2a: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8009d2c: 683b ldr r3, [r7, #0]
8009d2e: 781b ldrb r3, [r3, #0]
8009d30: f003 0360 and.w r3, r3, #96 @ 0x60
8009d34: 2b40 cmp r3, #64 @ 0x40
8009d36: d007 beq.n 8009d48 <USBD_StdEPReq+0x30>
8009d38: 2b40 cmp r3, #64 @ 0x40
8009d3a: f200 8146 bhi.w 8009fca <USBD_StdEPReq+0x2b2>
8009d3e: 2b00 cmp r3, #0
8009d40: d00a beq.n 8009d58 <USBD_StdEPReq+0x40>
8009d42: 2b20 cmp r3, #32
8009d44: f040 8141 bne.w 8009fca <USBD_StdEPReq+0x2b2>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8009d48: 687b ldr r3, [r7, #4]
8009d4a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009d4e: 689b ldr r3, [r3, #8]
8009d50: 6839 ldr r1, [r7, #0]
8009d52: 6878 ldr r0, [r7, #4]
8009d54: 4798 blx r3
break;
8009d56: e13d b.n 8009fd4 <USBD_StdEPReq+0x2bc>
case USB_REQ_TYPE_STANDARD:
/* Check if it is a class request */
if ((req->bmRequest & 0x60U) == 0x20U)
8009d58: 683b ldr r3, [r7, #0]
8009d5a: 781b ldrb r3, [r3, #0]
8009d5c: f003 0360 and.w r3, r3, #96 @ 0x60
8009d60: 2b20 cmp r3, #32
8009d62: d10a bne.n 8009d7a <USBD_StdEPReq+0x62>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8009d64: 687b ldr r3, [r7, #4]
8009d66: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8009d6a: 689b ldr r3, [r3, #8]
8009d6c: 6839 ldr r1, [r7, #0]
8009d6e: 6878 ldr r0, [r7, #4]
8009d70: 4798 blx r3
8009d72: 4603 mov r3, r0
8009d74: 73fb strb r3, [r7, #15]
return ret;
8009d76: 7bfb ldrb r3, [r7, #15]
8009d78: e12d b.n 8009fd6 <USBD_StdEPReq+0x2be>
}
switch (req->bRequest)
8009d7a: 683b ldr r3, [r7, #0]
8009d7c: 785b ldrb r3, [r3, #1]
8009d7e: 2b03 cmp r3, #3
8009d80: d007 beq.n 8009d92 <USBD_StdEPReq+0x7a>
8009d82: 2b03 cmp r3, #3
8009d84: f300 811b bgt.w 8009fbe <USBD_StdEPReq+0x2a6>
8009d88: 2b00 cmp r3, #0
8009d8a: d072 beq.n 8009e72 <USBD_StdEPReq+0x15a>
8009d8c: 2b01 cmp r3, #1
8009d8e: d03a beq.n 8009e06 <USBD_StdEPReq+0xee>
8009d90: e115 b.n 8009fbe <USBD_StdEPReq+0x2a6>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
8009d92: 687b ldr r3, [r7, #4]
8009d94: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009d98: 2b02 cmp r3, #2
8009d9a: d002 beq.n 8009da2 <USBD_StdEPReq+0x8a>
8009d9c: 2b03 cmp r3, #3
8009d9e: d015 beq.n 8009dcc <USBD_StdEPReq+0xb4>
8009da0: e02b b.n 8009dfa <USBD_StdEPReq+0xe2>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8009da2: 7bbb ldrb r3, [r7, #14]
8009da4: 2b00 cmp r3, #0
8009da6: d00c beq.n 8009dc2 <USBD_StdEPReq+0xaa>
8009da8: 7bbb ldrb r3, [r7, #14]
8009daa: 2b80 cmp r3, #128 @ 0x80
8009dac: d009 beq.n 8009dc2 <USBD_StdEPReq+0xaa>
{
USBD_LL_StallEP(pdev, ep_addr);
8009dae: 7bbb ldrb r3, [r7, #14]
8009db0: 4619 mov r1, r3
8009db2: 6878 ldr r0, [r7, #4]
8009db4: f001 f8fe bl 800afb4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8009db8: 2180 movs r1, #128 @ 0x80
8009dba: 6878 ldr r0, [r7, #4]
8009dbc: f001 f8fa bl 800afb4 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8009dc0: e020 b.n 8009e04 <USBD_StdEPReq+0xec>
USBD_CtlError(pdev, req);
8009dc2: 6839 ldr r1, [r7, #0]
8009dc4: 6878 ldr r0, [r7, #4]
8009dc6: f000 fc1b bl 800a600 <USBD_CtlError>
break;
8009dca: e01b b.n 8009e04 <USBD_StdEPReq+0xec>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8009dcc: 683b ldr r3, [r7, #0]
8009dce: 885b ldrh r3, [r3, #2]
8009dd0: 2b00 cmp r3, #0
8009dd2: d10e bne.n 8009df2 <USBD_StdEPReq+0xda>
{
if ((ep_addr != 0x00U) &&
8009dd4: 7bbb ldrb r3, [r7, #14]
8009dd6: 2b00 cmp r3, #0
8009dd8: d00b beq.n 8009df2 <USBD_StdEPReq+0xda>
8009dda: 7bbb ldrb r3, [r7, #14]
8009ddc: 2b80 cmp r3, #128 @ 0x80
8009dde: d008 beq.n 8009df2 <USBD_StdEPReq+0xda>
(ep_addr != 0x80U) && (req->wLength == 0x00U))
8009de0: 683b ldr r3, [r7, #0]
8009de2: 88db ldrh r3, [r3, #6]
8009de4: 2b00 cmp r3, #0
8009de6: d104 bne.n 8009df2 <USBD_StdEPReq+0xda>
{
USBD_LL_StallEP(pdev, ep_addr);
8009de8: 7bbb ldrb r3, [r7, #14]
8009dea: 4619 mov r1, r3
8009dec: 6878 ldr r0, [r7, #4]
8009dee: f001 f8e1 bl 800afb4 <USBD_LL_StallEP>
}
}
USBD_CtlSendStatus(pdev);
8009df2: 6878 ldr r0, [r7, #4]
8009df4: f000 fccc bl 800a790 <USBD_CtlSendStatus>
break;
8009df8: e004 b.n 8009e04 <USBD_StdEPReq+0xec>
default:
USBD_CtlError(pdev, req);
8009dfa: 6839 ldr r1, [r7, #0]
8009dfc: 6878 ldr r0, [r7, #4]
8009dfe: f000 fbff bl 800a600 <USBD_CtlError>
break;
8009e02: bf00 nop
}
break;
8009e04: e0e0 b.n 8009fc8 <USBD_StdEPReq+0x2b0>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
8009e06: 687b ldr r3, [r7, #4]
8009e08: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009e0c: 2b02 cmp r3, #2
8009e0e: d002 beq.n 8009e16 <USBD_StdEPReq+0xfe>
8009e10: 2b03 cmp r3, #3
8009e12: d015 beq.n 8009e40 <USBD_StdEPReq+0x128>
8009e14: e026 b.n 8009e64 <USBD_StdEPReq+0x14c>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8009e16: 7bbb ldrb r3, [r7, #14]
8009e18: 2b00 cmp r3, #0
8009e1a: d00c beq.n 8009e36 <USBD_StdEPReq+0x11e>
8009e1c: 7bbb ldrb r3, [r7, #14]
8009e1e: 2b80 cmp r3, #128 @ 0x80
8009e20: d009 beq.n 8009e36 <USBD_StdEPReq+0x11e>
{
USBD_LL_StallEP(pdev, ep_addr);
8009e22: 7bbb ldrb r3, [r7, #14]
8009e24: 4619 mov r1, r3
8009e26: 6878 ldr r0, [r7, #4]
8009e28: f001 f8c4 bl 800afb4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8009e2c: 2180 movs r1, #128 @ 0x80
8009e2e: 6878 ldr r0, [r7, #4]
8009e30: f001 f8c0 bl 800afb4 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8009e34: e01c b.n 8009e70 <USBD_StdEPReq+0x158>
USBD_CtlError(pdev, req);
8009e36: 6839 ldr r1, [r7, #0]
8009e38: 6878 ldr r0, [r7, #4]
8009e3a: f000 fbe1 bl 800a600 <USBD_CtlError>
break;
8009e3e: e017 b.n 8009e70 <USBD_StdEPReq+0x158>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8009e40: 683b ldr r3, [r7, #0]
8009e42: 885b ldrh r3, [r3, #2]
8009e44: 2b00 cmp r3, #0
8009e46: d112 bne.n 8009e6e <USBD_StdEPReq+0x156>
{
if ((ep_addr & 0x7FU) != 0x00U)
8009e48: 7bbb ldrb r3, [r7, #14]
8009e4a: f003 037f and.w r3, r3, #127 @ 0x7f
8009e4e: 2b00 cmp r3, #0
8009e50: d004 beq.n 8009e5c <USBD_StdEPReq+0x144>
{
USBD_LL_ClearStallEP(pdev, ep_addr);
8009e52: 7bbb ldrb r3, [r7, #14]
8009e54: 4619 mov r1, r3
8009e56: 6878 ldr r0, [r7, #4]
8009e58: f001 f8cb bl 800aff2 <USBD_LL_ClearStallEP>
}
USBD_CtlSendStatus(pdev);
8009e5c: 6878 ldr r0, [r7, #4]
8009e5e: f000 fc97 bl 800a790 <USBD_CtlSendStatus>
}
break;
8009e62: e004 b.n 8009e6e <USBD_StdEPReq+0x156>
default:
USBD_CtlError(pdev, req);
8009e64: 6839 ldr r1, [r7, #0]
8009e66: 6878 ldr r0, [r7, #4]
8009e68: f000 fbca bl 800a600 <USBD_CtlError>
break;
8009e6c: e000 b.n 8009e70 <USBD_StdEPReq+0x158>
break;
8009e6e: bf00 nop
}
break;
8009e70: e0aa b.n 8009fc8 <USBD_StdEPReq+0x2b0>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
8009e72: 687b ldr r3, [r7, #4]
8009e74: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8009e78: 2b02 cmp r3, #2
8009e7a: d002 beq.n 8009e82 <USBD_StdEPReq+0x16a>
8009e7c: 2b03 cmp r3, #3
8009e7e: d032 beq.n 8009ee6 <USBD_StdEPReq+0x1ce>
8009e80: e097 b.n 8009fb2 <USBD_StdEPReq+0x29a>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8009e82: 7bbb ldrb r3, [r7, #14]
8009e84: 2b00 cmp r3, #0
8009e86: d007 beq.n 8009e98 <USBD_StdEPReq+0x180>
8009e88: 7bbb ldrb r3, [r7, #14]
8009e8a: 2b80 cmp r3, #128 @ 0x80
8009e8c: d004 beq.n 8009e98 <USBD_StdEPReq+0x180>
{
USBD_CtlError(pdev, req);
8009e8e: 6839 ldr r1, [r7, #0]
8009e90: 6878 ldr r0, [r7, #4]
8009e92: f000 fbb5 bl 800a600 <USBD_CtlError>
break;
8009e96: e091 b.n 8009fbc <USBD_StdEPReq+0x2a4>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009e98: f997 300e ldrsb.w r3, [r7, #14]
8009e9c: 2b00 cmp r3, #0
8009e9e: da0b bge.n 8009eb8 <USBD_StdEPReq+0x1a0>
8009ea0: 7bbb ldrb r3, [r7, #14]
8009ea2: f003 027f and.w r2, r3, #127 @ 0x7f
8009ea6: 4613 mov r3, r2
8009ea8: 009b lsls r3, r3, #2
8009eaa: 4413 add r3, r2
8009eac: 009b lsls r3, r3, #2
8009eae: 3310 adds r3, #16
8009eb0: 687a ldr r2, [r7, #4]
8009eb2: 4413 add r3, r2
8009eb4: 3304 adds r3, #4
8009eb6: e00b b.n 8009ed0 <USBD_StdEPReq+0x1b8>
&pdev->ep_out[ep_addr & 0x7FU];
8009eb8: 7bbb ldrb r3, [r7, #14]
8009eba: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009ebe: 4613 mov r3, r2
8009ec0: 009b lsls r3, r3, #2
8009ec2: 4413 add r3, r2
8009ec4: 009b lsls r3, r3, #2
8009ec6: f503 73a8 add.w r3, r3, #336 @ 0x150
8009eca: 687a ldr r2, [r7, #4]
8009ecc: 4413 add r3, r2
8009ece: 3304 adds r3, #4
8009ed0: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
8009ed2: 68bb ldr r3, [r7, #8]
8009ed4: 2200 movs r2, #0
8009ed6: 601a str r2, [r3, #0]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8009ed8: 68bb ldr r3, [r7, #8]
8009eda: 2202 movs r2, #2
8009edc: 4619 mov r1, r3
8009ede: 6878 ldr r0, [r7, #4]
8009ee0: f000 fbf8 bl 800a6d4 <USBD_CtlSendData>
break;
8009ee4: e06a b.n 8009fbc <USBD_StdEPReq+0x2a4>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
8009ee6: f997 300e ldrsb.w r3, [r7, #14]
8009eea: 2b00 cmp r3, #0
8009eec: da11 bge.n 8009f12 <USBD_StdEPReq+0x1fa>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
8009eee: 7bbb ldrb r3, [r7, #14]
8009ef0: f003 020f and.w r2, r3, #15
8009ef4: 6879 ldr r1, [r7, #4]
8009ef6: 4613 mov r3, r2
8009ef8: 009b lsls r3, r3, #2
8009efa: 4413 add r3, r2
8009efc: 009b lsls r3, r3, #2
8009efe: 440b add r3, r1
8009f00: 3318 adds r3, #24
8009f02: 681b ldr r3, [r3, #0]
8009f04: 2b00 cmp r3, #0
8009f06: d117 bne.n 8009f38 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
8009f08: 6839 ldr r1, [r7, #0]
8009f0a: 6878 ldr r0, [r7, #4]
8009f0c: f000 fb78 bl 800a600 <USBD_CtlError>
break;
8009f10: e054 b.n 8009fbc <USBD_StdEPReq+0x2a4>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
8009f12: 7bbb ldrb r3, [r7, #14]
8009f14: f003 020f and.w r2, r3, #15
8009f18: 6879 ldr r1, [r7, #4]
8009f1a: 4613 mov r3, r2
8009f1c: 009b lsls r3, r3, #2
8009f1e: 4413 add r3, r2
8009f20: 009b lsls r3, r3, #2
8009f22: 440b add r3, r1
8009f24: f503 73ac add.w r3, r3, #344 @ 0x158
8009f28: 681b ldr r3, [r3, #0]
8009f2a: 2b00 cmp r3, #0
8009f2c: d104 bne.n 8009f38 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
8009f2e: 6839 ldr r1, [r7, #0]
8009f30: 6878 ldr r0, [r7, #4]
8009f32: f000 fb65 bl 800a600 <USBD_CtlError>
break;
8009f36: e041 b.n 8009fbc <USBD_StdEPReq+0x2a4>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009f38: f997 300e ldrsb.w r3, [r7, #14]
8009f3c: 2b00 cmp r3, #0
8009f3e: da0b bge.n 8009f58 <USBD_StdEPReq+0x240>
8009f40: 7bbb ldrb r3, [r7, #14]
8009f42: f003 027f and.w r2, r3, #127 @ 0x7f
8009f46: 4613 mov r3, r2
8009f48: 009b lsls r3, r3, #2
8009f4a: 4413 add r3, r2
8009f4c: 009b lsls r3, r3, #2
8009f4e: 3310 adds r3, #16
8009f50: 687a ldr r2, [r7, #4]
8009f52: 4413 add r3, r2
8009f54: 3304 adds r3, #4
8009f56: e00b b.n 8009f70 <USBD_StdEPReq+0x258>
&pdev->ep_out[ep_addr & 0x7FU];
8009f58: 7bbb ldrb r3, [r7, #14]
8009f5a: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8009f5e: 4613 mov r3, r2
8009f60: 009b lsls r3, r3, #2
8009f62: 4413 add r3, r2
8009f64: 009b lsls r3, r3, #2
8009f66: f503 73a8 add.w r3, r3, #336 @ 0x150
8009f6a: 687a ldr r2, [r7, #4]
8009f6c: 4413 add r3, r2
8009f6e: 3304 adds r3, #4
8009f70: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
8009f72: 7bbb ldrb r3, [r7, #14]
8009f74: 2b00 cmp r3, #0
8009f76: d002 beq.n 8009f7e <USBD_StdEPReq+0x266>
8009f78: 7bbb ldrb r3, [r7, #14]
8009f7a: 2b80 cmp r3, #128 @ 0x80
8009f7c: d103 bne.n 8009f86 <USBD_StdEPReq+0x26e>
{
pep->status = 0x0000U;
8009f7e: 68bb ldr r3, [r7, #8]
8009f80: 2200 movs r2, #0
8009f82: 601a str r2, [r3, #0]
8009f84: e00e b.n 8009fa4 <USBD_StdEPReq+0x28c>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr))
8009f86: 7bbb ldrb r3, [r7, #14]
8009f88: 4619 mov r1, r3
8009f8a: 6878 ldr r0, [r7, #4]
8009f8c: f001 f850 bl 800b030 <USBD_LL_IsStallEP>
8009f90: 4603 mov r3, r0
8009f92: 2b00 cmp r3, #0
8009f94: d003 beq.n 8009f9e <USBD_StdEPReq+0x286>
{
pep->status = 0x0001U;
8009f96: 68bb ldr r3, [r7, #8]
8009f98: 2201 movs r2, #1
8009f9a: 601a str r2, [r3, #0]
8009f9c: e002 b.n 8009fa4 <USBD_StdEPReq+0x28c>
}
else
{
pep->status = 0x0000U;
8009f9e: 68bb ldr r3, [r7, #8]
8009fa0: 2200 movs r2, #0
8009fa2: 601a str r2, [r3, #0]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8009fa4: 68bb ldr r3, [r7, #8]
8009fa6: 2202 movs r2, #2
8009fa8: 4619 mov r1, r3
8009faa: 6878 ldr r0, [r7, #4]
8009fac: f000 fb92 bl 800a6d4 <USBD_CtlSendData>
break;
8009fb0: e004 b.n 8009fbc <USBD_StdEPReq+0x2a4>
default:
USBD_CtlError(pdev, req);
8009fb2: 6839 ldr r1, [r7, #0]
8009fb4: 6878 ldr r0, [r7, #4]
8009fb6: f000 fb23 bl 800a600 <USBD_CtlError>
break;
8009fba: bf00 nop
}
break;
8009fbc: e004 b.n 8009fc8 <USBD_StdEPReq+0x2b0>
default:
USBD_CtlError(pdev, req);
8009fbe: 6839 ldr r1, [r7, #0]
8009fc0: 6878 ldr r0, [r7, #4]
8009fc2: f000 fb1d bl 800a600 <USBD_CtlError>
break;
8009fc6: bf00 nop
}
break;
8009fc8: e004 b.n 8009fd4 <USBD_StdEPReq+0x2bc>
default:
USBD_CtlError(pdev, req);
8009fca: 6839 ldr r1, [r7, #0]
8009fcc: 6878 ldr r0, [r7, #4]
8009fce: f000 fb17 bl 800a600 <USBD_CtlError>
break;
8009fd2: bf00 nop
}
return ret;
8009fd4: 7bfb ldrb r3, [r7, #15]
}
8009fd6: 4618 mov r0, r3
8009fd8: 3710 adds r7, #16
8009fda: 46bd mov sp, r7
8009fdc: bd80 pop {r7, pc}
...
08009fe0 <USBD_GetDescriptor>:
* @param req: usb request
* @retval status
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8009fe0: b580 push {r7, lr}
8009fe2: b084 sub sp, #16
8009fe4: af00 add r7, sp, #0
8009fe6: 6078 str r0, [r7, #4]
8009fe8: 6039 str r1, [r7, #0]
uint16_t len = 0U;
8009fea: 2300 movs r3, #0
8009fec: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
8009fee: 2300 movs r3, #0
8009ff0: 60fb str r3, [r7, #12]
uint8_t err = 0U;
8009ff2: 2300 movs r3, #0
8009ff4: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
8009ff6: 683b ldr r3, [r7, #0]
8009ff8: 885b ldrh r3, [r3, #2]
8009ffa: 0a1b lsrs r3, r3, #8
8009ffc: b29b uxth r3, r3
8009ffe: 3b01 subs r3, #1
800a000: 2b06 cmp r3, #6
800a002: f200 8128 bhi.w 800a256 <USBD_GetDescriptor+0x276>
800a006: a201 add r2, pc, #4 @ (adr r2, 800a00c <USBD_GetDescriptor+0x2c>)
800a008: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a00c: 0800a029 .word 0x0800a029
800a010: 0800a041 .word 0x0800a041
800a014: 0800a081 .word 0x0800a081
800a018: 0800a257 .word 0x0800a257
800a01c: 0800a257 .word 0x0800a257
800a020: 0800a1f7 .word 0x0800a1f7
800a024: 0800a223 .word 0x0800a223
err++;
}
break;
#endif
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
800a028: 687b ldr r3, [r7, #4]
800a02a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a02e: 681b ldr r3, [r3, #0]
800a030: 687a ldr r2, [r7, #4]
800a032: 7c12 ldrb r2, [r2, #16]
800a034: f107 0108 add.w r1, r7, #8
800a038: 4610 mov r0, r2
800a03a: 4798 blx r3
800a03c: 60f8 str r0, [r7, #12]
break;
800a03e: e112 b.n 800a266 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a040: 687b ldr r3, [r7, #4]
800a042: 7c1b ldrb r3, [r3, #16]
800a044: 2b00 cmp r3, #0
800a046: d10d bne.n 800a064 <USBD_GetDescriptor+0x84>
{
pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
800a048: 687b ldr r3, [r7, #4]
800a04a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a04e: 6a9b ldr r3, [r3, #40] @ 0x28
800a050: f107 0208 add.w r2, r7, #8
800a054: 4610 mov r0, r2
800a056: 4798 blx r3
800a058: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800a05a: 68fb ldr r3, [r7, #12]
800a05c: 3301 adds r3, #1
800a05e: 2202 movs r2, #2
800a060: 701a strb r2, [r3, #0]
else
{
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
800a062: e100 b.n 800a266 <USBD_GetDescriptor+0x286>
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
800a064: 687b ldr r3, [r7, #4]
800a066: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a06a: 6adb ldr r3, [r3, #44] @ 0x2c
800a06c: f107 0208 add.w r2, r7, #8
800a070: 4610 mov r0, r2
800a072: 4798 blx r3
800a074: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800a076: 68fb ldr r3, [r7, #12]
800a078: 3301 adds r3, #1
800a07a: 2202 movs r2, #2
800a07c: 701a strb r2, [r3, #0]
break;
800a07e: e0f2 b.n 800a266 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
800a080: 683b ldr r3, [r7, #0]
800a082: 885b ldrh r3, [r3, #2]
800a084: b2db uxtb r3, r3
800a086: 2b05 cmp r3, #5
800a088: f200 80ac bhi.w 800a1e4 <USBD_GetDescriptor+0x204>
800a08c: a201 add r2, pc, #4 @ (adr r2, 800a094 <USBD_GetDescriptor+0xb4>)
800a08e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a092: bf00 nop
800a094: 0800a0ad .word 0x0800a0ad
800a098: 0800a0e1 .word 0x0800a0e1
800a09c: 0800a115 .word 0x0800a115
800a0a0: 0800a149 .word 0x0800a149
800a0a4: 0800a17d .word 0x0800a17d
800a0a8: 0800a1b1 .word 0x0800a1b1
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
800a0ac: 687b ldr r3, [r7, #4]
800a0ae: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a0b2: 685b ldr r3, [r3, #4]
800a0b4: 2b00 cmp r3, #0
800a0b6: d00b beq.n 800a0d0 <USBD_GetDescriptor+0xf0>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
800a0b8: 687b ldr r3, [r7, #4]
800a0ba: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a0be: 685b ldr r3, [r3, #4]
800a0c0: 687a ldr r2, [r7, #4]
800a0c2: 7c12 ldrb r2, [r2, #16]
800a0c4: f107 0108 add.w r1, r7, #8
800a0c8: 4610 mov r0, r2
800a0ca: 4798 blx r3
800a0cc: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a0ce: e091 b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a0d0: 6839 ldr r1, [r7, #0]
800a0d2: 6878 ldr r0, [r7, #4]
800a0d4: f000 fa94 bl 800a600 <USBD_CtlError>
err++;
800a0d8: 7afb ldrb r3, [r7, #11]
800a0da: 3301 adds r3, #1
800a0dc: 72fb strb r3, [r7, #11]
break;
800a0de: e089 b.n 800a1f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
800a0e0: 687b ldr r3, [r7, #4]
800a0e2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a0e6: 689b ldr r3, [r3, #8]
800a0e8: 2b00 cmp r3, #0
800a0ea: d00b beq.n 800a104 <USBD_GetDescriptor+0x124>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
800a0ec: 687b ldr r3, [r7, #4]
800a0ee: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a0f2: 689b ldr r3, [r3, #8]
800a0f4: 687a ldr r2, [r7, #4]
800a0f6: 7c12 ldrb r2, [r2, #16]
800a0f8: f107 0108 add.w r1, r7, #8
800a0fc: 4610 mov r0, r2
800a0fe: 4798 blx r3
800a100: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a102: e077 b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a104: 6839 ldr r1, [r7, #0]
800a106: 6878 ldr r0, [r7, #4]
800a108: f000 fa7a bl 800a600 <USBD_CtlError>
err++;
800a10c: 7afb ldrb r3, [r7, #11]
800a10e: 3301 adds r3, #1
800a110: 72fb strb r3, [r7, #11]
break;
800a112: e06f b.n 800a1f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
800a114: 687b ldr r3, [r7, #4]
800a116: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a11a: 68db ldr r3, [r3, #12]
800a11c: 2b00 cmp r3, #0
800a11e: d00b beq.n 800a138 <USBD_GetDescriptor+0x158>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
800a120: 687b ldr r3, [r7, #4]
800a122: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a126: 68db ldr r3, [r3, #12]
800a128: 687a ldr r2, [r7, #4]
800a12a: 7c12 ldrb r2, [r2, #16]
800a12c: f107 0108 add.w r1, r7, #8
800a130: 4610 mov r0, r2
800a132: 4798 blx r3
800a134: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a136: e05d b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a138: 6839 ldr r1, [r7, #0]
800a13a: 6878 ldr r0, [r7, #4]
800a13c: f000 fa60 bl 800a600 <USBD_CtlError>
err++;
800a140: 7afb ldrb r3, [r7, #11]
800a142: 3301 adds r3, #1
800a144: 72fb strb r3, [r7, #11]
break;
800a146: e055 b.n 800a1f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
800a148: 687b ldr r3, [r7, #4]
800a14a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a14e: 691b ldr r3, [r3, #16]
800a150: 2b00 cmp r3, #0
800a152: d00b beq.n 800a16c <USBD_GetDescriptor+0x18c>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
800a154: 687b ldr r3, [r7, #4]
800a156: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a15a: 691b ldr r3, [r3, #16]
800a15c: 687a ldr r2, [r7, #4]
800a15e: 7c12 ldrb r2, [r2, #16]
800a160: f107 0108 add.w r1, r7, #8
800a164: 4610 mov r0, r2
800a166: 4798 blx r3
800a168: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a16a: e043 b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a16c: 6839 ldr r1, [r7, #0]
800a16e: 6878 ldr r0, [r7, #4]
800a170: f000 fa46 bl 800a600 <USBD_CtlError>
err++;
800a174: 7afb ldrb r3, [r7, #11]
800a176: 3301 adds r3, #1
800a178: 72fb strb r3, [r7, #11]
break;
800a17a: e03b b.n 800a1f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
800a17c: 687b ldr r3, [r7, #4]
800a17e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a182: 695b ldr r3, [r3, #20]
800a184: 2b00 cmp r3, #0
800a186: d00b beq.n 800a1a0 <USBD_GetDescriptor+0x1c0>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
800a188: 687b ldr r3, [r7, #4]
800a18a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a18e: 695b ldr r3, [r3, #20]
800a190: 687a ldr r2, [r7, #4]
800a192: 7c12 ldrb r2, [r2, #16]
800a194: f107 0108 add.w r1, r7, #8
800a198: 4610 mov r0, r2
800a19a: 4798 blx r3
800a19c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a19e: e029 b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a1a0: 6839 ldr r1, [r7, #0]
800a1a2: 6878 ldr r0, [r7, #4]
800a1a4: f000 fa2c bl 800a600 <USBD_CtlError>
err++;
800a1a8: 7afb ldrb r3, [r7, #11]
800a1aa: 3301 adds r3, #1
800a1ac: 72fb strb r3, [r7, #11]
break;
800a1ae: e021 b.n 800a1f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
800a1b0: 687b ldr r3, [r7, #4]
800a1b2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a1b6: 699b ldr r3, [r3, #24]
800a1b8: 2b00 cmp r3, #0
800a1ba: d00b beq.n 800a1d4 <USBD_GetDescriptor+0x1f4>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
800a1bc: 687b ldr r3, [r7, #4]
800a1be: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800a1c2: 699b ldr r3, [r3, #24]
800a1c4: 687a ldr r2, [r7, #4]
800a1c6: 7c12 ldrb r2, [r2, #16]
800a1c8: f107 0108 add.w r1, r7, #8
800a1cc: 4610 mov r0, r2
800a1ce: 4798 blx r3
800a1d0: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a1d2: e00f b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800a1d4: 6839 ldr r1, [r7, #0]
800a1d6: 6878 ldr r0, [r7, #4]
800a1d8: f000 fa12 bl 800a600 <USBD_CtlError>
err++;
800a1dc: 7afb ldrb r3, [r7, #11]
800a1de: 3301 adds r3, #1
800a1e0: 72fb strb r3, [r7, #11]
break;
800a1e2: e007 b.n 800a1f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
err++;
}
break;
#else
USBD_CtlError(pdev, req);
800a1e4: 6839 ldr r1, [r7, #0]
800a1e6: 6878 ldr r0, [r7, #4]
800a1e8: f000 fa0a bl 800a600 <USBD_CtlError>
err++;
800a1ec: 7afb ldrb r3, [r7, #11]
800a1ee: 3301 adds r3, #1
800a1f0: 72fb strb r3, [r7, #11]
#endif
}
break;
800a1f2: e038 b.n 800a266 <USBD_GetDescriptor+0x286>
800a1f4: e037 b.n 800a266 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a1f6: 687b ldr r3, [r7, #4]
800a1f8: 7c1b ldrb r3, [r3, #16]
800a1fa: 2b00 cmp r3, #0
800a1fc: d109 bne.n 800a212 <USBD_GetDescriptor+0x232>
{
pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
800a1fe: 687b ldr r3, [r7, #4]
800a200: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a204: 6b5b ldr r3, [r3, #52] @ 0x34
800a206: f107 0208 add.w r2, r7, #8
800a20a: 4610 mov r0, r2
800a20c: 4798 blx r3
800a20e: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a210: e029 b.n 800a266 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
800a212: 6839 ldr r1, [r7, #0]
800a214: 6878 ldr r0, [r7, #4]
800a216: f000 f9f3 bl 800a600 <USBD_CtlError>
err++;
800a21a: 7afb ldrb r3, [r7, #11]
800a21c: 3301 adds r3, #1
800a21e: 72fb strb r3, [r7, #11]
break;
800a220: e021 b.n 800a266 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a222: 687b ldr r3, [r7, #4]
800a224: 7c1b ldrb r3, [r3, #16]
800a226: 2b00 cmp r3, #0
800a228: d10d bne.n 800a246 <USBD_GetDescriptor+0x266>
{
pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
800a22a: 687b ldr r3, [r7, #4]
800a22c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800a230: 6b1b ldr r3, [r3, #48] @ 0x30
800a232: f107 0208 add.w r2, r7, #8
800a236: 4610 mov r0, r2
800a238: 4798 blx r3
800a23a: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
800a23c: 68fb ldr r3, [r7, #12]
800a23e: 3301 adds r3, #1
800a240: 2207 movs r2, #7
800a242: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800a244: e00f b.n 800a266 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
800a246: 6839 ldr r1, [r7, #0]
800a248: 6878 ldr r0, [r7, #4]
800a24a: f000 f9d9 bl 800a600 <USBD_CtlError>
err++;
800a24e: 7afb ldrb r3, [r7, #11]
800a250: 3301 adds r3, #1
800a252: 72fb strb r3, [r7, #11]
break;
800a254: e007 b.n 800a266 <USBD_GetDescriptor+0x286>
default:
USBD_CtlError(pdev, req);
800a256: 6839 ldr r1, [r7, #0]
800a258: 6878 ldr r0, [r7, #4]
800a25a: f000 f9d1 bl 800a600 <USBD_CtlError>
err++;
800a25e: 7afb ldrb r3, [r7, #11]
800a260: 3301 adds r3, #1
800a262: 72fb strb r3, [r7, #11]
break;
800a264: bf00 nop
}
if (err != 0U)
800a266: 7afb ldrb r3, [r7, #11]
800a268: 2b00 cmp r3, #0
800a26a: d11c bne.n 800a2a6 <USBD_GetDescriptor+0x2c6>
{
return;
}
else
{
if ((len != 0U) && (req->wLength != 0U))
800a26c: 893b ldrh r3, [r7, #8]
800a26e: 2b00 cmp r3, #0
800a270: d011 beq.n 800a296 <USBD_GetDescriptor+0x2b6>
800a272: 683b ldr r3, [r7, #0]
800a274: 88db ldrh r3, [r3, #6]
800a276: 2b00 cmp r3, #0
800a278: d00d beq.n 800a296 <USBD_GetDescriptor+0x2b6>
{
len = MIN(len, req->wLength);
800a27a: 683b ldr r3, [r7, #0]
800a27c: 88da ldrh r2, [r3, #6]
800a27e: 893b ldrh r3, [r7, #8]
800a280: 4293 cmp r3, r2
800a282: bf28 it cs
800a284: 4613 movcs r3, r2
800a286: b29b uxth r3, r3
800a288: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
800a28a: 893b ldrh r3, [r7, #8]
800a28c: 461a mov r2, r3
800a28e: 68f9 ldr r1, [r7, #12]
800a290: 6878 ldr r0, [r7, #4]
800a292: f000 fa1f bl 800a6d4 <USBD_CtlSendData>
}
if (req->wLength == 0U)
800a296: 683b ldr r3, [r7, #0]
800a298: 88db ldrh r3, [r3, #6]
800a29a: 2b00 cmp r3, #0
800a29c: d104 bne.n 800a2a8 <USBD_GetDescriptor+0x2c8>
{
(void)USBD_CtlSendStatus(pdev);
800a29e: 6878 ldr r0, [r7, #4]
800a2a0: f000 fa76 bl 800a790 <USBD_CtlSendStatus>
800a2a4: e000 b.n 800a2a8 <USBD_GetDescriptor+0x2c8>
return;
800a2a6: bf00 nop
}
}
}
800a2a8: 3710 adds r7, #16
800a2aa: 46bd mov sp, r7
800a2ac: bd80 pop {r7, pc}
800a2ae: bf00 nop
0800a2b0 <USBD_SetAddress>:
* @param req: usb request
* @retval status
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a2b0: b580 push {r7, lr}
800a2b2: b084 sub sp, #16
800a2b4: af00 add r7, sp, #0
800a2b6: 6078 str r0, [r7, #4]
800a2b8: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
800a2ba: 683b ldr r3, [r7, #0]
800a2bc: 889b ldrh r3, [r3, #4]
800a2be: 2b00 cmp r3, #0
800a2c0: d130 bne.n 800a324 <USBD_SetAddress+0x74>
800a2c2: 683b ldr r3, [r7, #0]
800a2c4: 88db ldrh r3, [r3, #6]
800a2c6: 2b00 cmp r3, #0
800a2c8: d12c bne.n 800a324 <USBD_SetAddress+0x74>
800a2ca: 683b ldr r3, [r7, #0]
800a2cc: 885b ldrh r3, [r3, #2]
800a2ce: 2b7f cmp r3, #127 @ 0x7f
800a2d0: d828 bhi.n 800a324 <USBD_SetAddress+0x74>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
800a2d2: 683b ldr r3, [r7, #0]
800a2d4: 885b ldrh r3, [r3, #2]
800a2d6: b2db uxtb r3, r3
800a2d8: f003 037f and.w r3, r3, #127 @ 0x7f
800a2dc: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a2de: 687b ldr r3, [r7, #4]
800a2e0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a2e4: 2b03 cmp r3, #3
800a2e6: d104 bne.n 800a2f2 <USBD_SetAddress+0x42>
{
USBD_CtlError(pdev, req);
800a2e8: 6839 ldr r1, [r7, #0]
800a2ea: 6878 ldr r0, [r7, #4]
800a2ec: f000 f988 bl 800a600 <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a2f0: e01d b.n 800a32e <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_address = dev_addr;
800a2f2: 687b ldr r3, [r7, #4]
800a2f4: 7bfa ldrb r2, [r7, #15]
800a2f6: f883 229e strb.w r2, [r3, #670] @ 0x29e
USBD_LL_SetUSBAddress(pdev, dev_addr);
800a2fa: 7bfb ldrb r3, [r7, #15]
800a2fc: 4619 mov r1, r3
800a2fe: 6878 ldr r0, [r7, #4]
800a300: f000 fec1 bl 800b086 <USBD_LL_SetUSBAddress>
USBD_CtlSendStatus(pdev);
800a304: 6878 ldr r0, [r7, #4]
800a306: f000 fa43 bl 800a790 <USBD_CtlSendStatus>
if (dev_addr != 0U)
800a30a: 7bfb ldrb r3, [r7, #15]
800a30c: 2b00 cmp r3, #0
800a30e: d004 beq.n 800a31a <USBD_SetAddress+0x6a>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800a310: 687b ldr r3, [r7, #4]
800a312: 2202 movs r2, #2
800a314: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a318: e009 b.n 800a32e <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
800a31a: 687b ldr r3, [r7, #4]
800a31c: 2201 movs r2, #1
800a31e: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a322: e004 b.n 800a32e <USBD_SetAddress+0x7e>
}
}
}
else
{
USBD_CtlError(pdev, req);
800a324: 6839 ldr r1, [r7, #0]
800a326: 6878 ldr r0, [r7, #4]
800a328: f000 f96a bl 800a600 <USBD_CtlError>
}
}
800a32c: bf00 nop
800a32e: bf00 nop
800a330: 3710 adds r7, #16
800a332: 46bd mov sp, r7
800a334: bd80 pop {r7, pc}
...
0800a338 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a338: b580 push {r7, lr}
800a33a: b082 sub sp, #8
800a33c: af00 add r7, sp, #0
800a33e: 6078 str r0, [r7, #4]
800a340: 6039 str r1, [r7, #0]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
800a342: 683b ldr r3, [r7, #0]
800a344: 885b ldrh r3, [r3, #2]
800a346: b2da uxtb r2, r3
800a348: 4b41 ldr r3, [pc, #260] @ (800a450 <USBD_SetConfig+0x118>)
800a34a: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
800a34c: 4b40 ldr r3, [pc, #256] @ (800a450 <USBD_SetConfig+0x118>)
800a34e: 781b ldrb r3, [r3, #0]
800a350: 2b01 cmp r3, #1
800a352: d904 bls.n 800a35e <USBD_SetConfig+0x26>
{
USBD_CtlError(pdev, req);
800a354: 6839 ldr r1, [r7, #0]
800a356: 6878 ldr r0, [r7, #4]
800a358: f000 f952 bl 800a600 <USBD_CtlError>
800a35c: e075 b.n 800a44a <USBD_SetConfig+0x112>
}
else
{
switch (pdev->dev_state)
800a35e: 687b ldr r3, [r7, #4]
800a360: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a364: 2b02 cmp r3, #2
800a366: d002 beq.n 800a36e <USBD_SetConfig+0x36>
800a368: 2b03 cmp r3, #3
800a36a: d023 beq.n 800a3b4 <USBD_SetConfig+0x7c>
800a36c: e062 b.n 800a434 <USBD_SetConfig+0xfc>
{
case USBD_STATE_ADDRESSED:
if (cfgidx)
800a36e: 4b38 ldr r3, [pc, #224] @ (800a450 <USBD_SetConfig+0x118>)
800a370: 781b ldrb r3, [r3, #0]
800a372: 2b00 cmp r3, #0
800a374: d01a beq.n 800a3ac <USBD_SetConfig+0x74>
{
pdev->dev_config = cfgidx;
800a376: 4b36 ldr r3, [pc, #216] @ (800a450 <USBD_SetConfig+0x118>)
800a378: 781b ldrb r3, [r3, #0]
800a37a: 461a mov r2, r3
800a37c: 687b ldr r3, [r7, #4]
800a37e: 605a str r2, [r3, #4]
pdev->dev_state = USBD_STATE_CONFIGURED;
800a380: 687b ldr r3, [r7, #4]
800a382: 2203 movs r2, #3
800a384: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800a388: 4b31 ldr r3, [pc, #196] @ (800a450 <USBD_SetConfig+0x118>)
800a38a: 781b ldrb r3, [r3, #0]
800a38c: 4619 mov r1, r3
800a38e: 6878 ldr r0, [r7, #4]
800a390: f7ff f9e7 bl 8009762 <USBD_SetClassConfig>
800a394: 4603 mov r3, r0
800a396: 2b02 cmp r3, #2
800a398: d104 bne.n 800a3a4 <USBD_SetConfig+0x6c>
{
USBD_CtlError(pdev, req);
800a39a: 6839 ldr r1, [r7, #0]
800a39c: 6878 ldr r0, [r7, #4]
800a39e: f000 f92f bl 800a600 <USBD_CtlError>
return;
800a3a2: e052 b.n 800a44a <USBD_SetConfig+0x112>
}
USBD_CtlSendStatus(pdev);
800a3a4: 6878 ldr r0, [r7, #4]
800a3a6: f000 f9f3 bl 800a790 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800a3aa: e04e b.n 800a44a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800a3ac: 6878 ldr r0, [r7, #4]
800a3ae: f000 f9ef bl 800a790 <USBD_CtlSendStatus>
break;
800a3b2: e04a b.n 800a44a <USBD_SetConfig+0x112>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
800a3b4: 4b26 ldr r3, [pc, #152] @ (800a450 <USBD_SetConfig+0x118>)
800a3b6: 781b ldrb r3, [r3, #0]
800a3b8: 2b00 cmp r3, #0
800a3ba: d112 bne.n 800a3e2 <USBD_SetConfig+0xaa>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800a3bc: 687b ldr r3, [r7, #4]
800a3be: 2202 movs r2, #2
800a3c0: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
800a3c4: 4b22 ldr r3, [pc, #136] @ (800a450 <USBD_SetConfig+0x118>)
800a3c6: 781b ldrb r3, [r3, #0]
800a3c8: 461a mov r2, r3
800a3ca: 687b ldr r3, [r7, #4]
800a3cc: 605a str r2, [r3, #4]
USBD_ClrClassConfig(pdev, cfgidx);
800a3ce: 4b20 ldr r3, [pc, #128] @ (800a450 <USBD_SetConfig+0x118>)
800a3d0: 781b ldrb r3, [r3, #0]
800a3d2: 4619 mov r1, r3
800a3d4: 6878 ldr r0, [r7, #4]
800a3d6: f7ff f9e3 bl 80097a0 <USBD_ClrClassConfig>
USBD_CtlSendStatus(pdev);
800a3da: 6878 ldr r0, [r7, #4]
800a3dc: f000 f9d8 bl 800a790 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800a3e0: e033 b.n 800a44a <USBD_SetConfig+0x112>
else if (cfgidx != pdev->dev_config)
800a3e2: 4b1b ldr r3, [pc, #108] @ (800a450 <USBD_SetConfig+0x118>)
800a3e4: 781b ldrb r3, [r3, #0]
800a3e6: 461a mov r2, r3
800a3e8: 687b ldr r3, [r7, #4]
800a3ea: 685b ldr r3, [r3, #4]
800a3ec: 429a cmp r2, r3
800a3ee: d01d beq.n 800a42c <USBD_SetConfig+0xf4>
USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
800a3f0: 687b ldr r3, [r7, #4]
800a3f2: 685b ldr r3, [r3, #4]
800a3f4: b2db uxtb r3, r3
800a3f6: 4619 mov r1, r3
800a3f8: 6878 ldr r0, [r7, #4]
800a3fa: f7ff f9d1 bl 80097a0 <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
800a3fe: 4b14 ldr r3, [pc, #80] @ (800a450 <USBD_SetConfig+0x118>)
800a400: 781b ldrb r3, [r3, #0]
800a402: 461a mov r2, r3
800a404: 687b ldr r3, [r7, #4]
800a406: 605a str r2, [r3, #4]
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800a408: 4b11 ldr r3, [pc, #68] @ (800a450 <USBD_SetConfig+0x118>)
800a40a: 781b ldrb r3, [r3, #0]
800a40c: 4619 mov r1, r3
800a40e: 6878 ldr r0, [r7, #4]
800a410: f7ff f9a7 bl 8009762 <USBD_SetClassConfig>
800a414: 4603 mov r3, r0
800a416: 2b02 cmp r3, #2
800a418: d104 bne.n 800a424 <USBD_SetConfig+0xec>
USBD_CtlError(pdev, req);
800a41a: 6839 ldr r1, [r7, #0]
800a41c: 6878 ldr r0, [r7, #4]
800a41e: f000 f8ef bl 800a600 <USBD_CtlError>
return;
800a422: e012 b.n 800a44a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800a424: 6878 ldr r0, [r7, #4]
800a426: f000 f9b3 bl 800a790 <USBD_CtlSendStatus>
break;
800a42a: e00e b.n 800a44a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800a42c: 6878 ldr r0, [r7, #4]
800a42e: f000 f9af bl 800a790 <USBD_CtlSendStatus>
break;
800a432: e00a b.n 800a44a <USBD_SetConfig+0x112>
default:
USBD_CtlError(pdev, req);
800a434: 6839 ldr r1, [r7, #0]
800a436: 6878 ldr r0, [r7, #4]
800a438: f000 f8e2 bl 800a600 <USBD_CtlError>
USBD_ClrClassConfig(pdev, cfgidx);
800a43c: 4b04 ldr r3, [pc, #16] @ (800a450 <USBD_SetConfig+0x118>)
800a43e: 781b ldrb r3, [r3, #0]
800a440: 4619 mov r1, r3
800a442: 6878 ldr r0, [r7, #4]
800a444: f7ff f9ac bl 80097a0 <USBD_ClrClassConfig>
break;
800a448: bf00 nop
}
}
}
800a44a: 3708 adds r7, #8
800a44c: 46bd mov sp, r7
800a44e: bd80 pop {r7, pc}
800a450: 20000410 .word 0x20000410
0800a454 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a454: b580 push {r7, lr}
800a456: b082 sub sp, #8
800a458: af00 add r7, sp, #0
800a45a: 6078 str r0, [r7, #4]
800a45c: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
800a45e: 683b ldr r3, [r7, #0]
800a460: 88db ldrh r3, [r3, #6]
800a462: 2b01 cmp r3, #1
800a464: d004 beq.n 800a470 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
800a466: 6839 ldr r1, [r7, #0]
800a468: 6878 ldr r0, [r7, #4]
800a46a: f000 f8c9 bl 800a600 <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
800a46e: e022 b.n 800a4b6 <USBD_GetConfig+0x62>
switch (pdev->dev_state)
800a470: 687b ldr r3, [r7, #4]
800a472: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a476: 2b02 cmp r3, #2
800a478: dc02 bgt.n 800a480 <USBD_GetConfig+0x2c>
800a47a: 2b00 cmp r3, #0
800a47c: dc03 bgt.n 800a486 <USBD_GetConfig+0x32>
800a47e: e015 b.n 800a4ac <USBD_GetConfig+0x58>
800a480: 2b03 cmp r3, #3
800a482: d00b beq.n 800a49c <USBD_GetConfig+0x48>
800a484: e012 b.n 800a4ac <USBD_GetConfig+0x58>
pdev->dev_default_config = 0U;
800a486: 687b ldr r3, [r7, #4]
800a488: 2200 movs r2, #0
800a48a: 609a str r2, [r3, #8]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
800a48c: 687b ldr r3, [r7, #4]
800a48e: 3308 adds r3, #8
800a490: 2201 movs r2, #1
800a492: 4619 mov r1, r3
800a494: 6878 ldr r0, [r7, #4]
800a496: f000 f91d bl 800a6d4 <USBD_CtlSendData>
break;
800a49a: e00c b.n 800a4b6 <USBD_GetConfig+0x62>
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
800a49c: 687b ldr r3, [r7, #4]
800a49e: 3304 adds r3, #4
800a4a0: 2201 movs r2, #1
800a4a2: 4619 mov r1, r3
800a4a4: 6878 ldr r0, [r7, #4]
800a4a6: f000 f915 bl 800a6d4 <USBD_CtlSendData>
break;
800a4aa: e004 b.n 800a4b6 <USBD_GetConfig+0x62>
USBD_CtlError(pdev, req);
800a4ac: 6839 ldr r1, [r7, #0]
800a4ae: 6878 ldr r0, [r7, #4]
800a4b0: f000 f8a6 bl 800a600 <USBD_CtlError>
break;
800a4b4: bf00 nop
}
800a4b6: bf00 nop
800a4b8: 3708 adds r7, #8
800a4ba: 46bd mov sp, r7
800a4bc: bd80 pop {r7, pc}
0800a4be <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800a4be: b580 push {r7, lr}
800a4c0: b082 sub sp, #8
800a4c2: af00 add r7, sp, #0
800a4c4: 6078 str r0, [r7, #4]
800a4c6: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800a4c8: 687b ldr r3, [r7, #4]
800a4ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a4ce: 3b01 subs r3, #1
800a4d0: 2b02 cmp r3, #2
800a4d2: d81e bhi.n 800a512 <USBD_GetStatus+0x54>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
800a4d4: 683b ldr r3, [r7, #0]
800a4d6: 88db ldrh r3, [r3, #6]
800a4d8: 2b02 cmp r3, #2
800a4da: d004 beq.n 800a4e6 <USBD_GetStatus+0x28>
{
USBD_CtlError(pdev, req);
800a4dc: 6839 ldr r1, [r7, #0]
800a4de: 6878 ldr r0, [r7, #4]
800a4e0: f000 f88e bl 800a600 <USBD_CtlError>
break;
800a4e4: e01a b.n 800a51c <USBD_GetStatus+0x5e>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
800a4e6: 687b ldr r3, [r7, #4]
800a4e8: 2201 movs r2, #1
800a4ea: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif
if (pdev->dev_remote_wakeup)
800a4ec: 687b ldr r3, [r7, #4]
800a4ee: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
800a4f2: 2b00 cmp r3, #0
800a4f4: d005 beq.n 800a502 <USBD_GetStatus+0x44>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
800a4f6: 687b ldr r3, [r7, #4]
800a4f8: 68db ldr r3, [r3, #12]
800a4fa: f043 0202 orr.w r2, r3, #2
800a4fe: 687b ldr r3, [r7, #4]
800a500: 60da str r2, [r3, #12]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
800a502: 687b ldr r3, [r7, #4]
800a504: 330c adds r3, #12
800a506: 2202 movs r2, #2
800a508: 4619 mov r1, r3
800a50a: 6878 ldr r0, [r7, #4]
800a50c: f000 f8e2 bl 800a6d4 <USBD_CtlSendData>
break;
800a510: e004 b.n 800a51c <USBD_GetStatus+0x5e>
default:
USBD_CtlError(pdev, req);
800a512: 6839 ldr r1, [r7, #0]
800a514: 6878 ldr r0, [r7, #4]
800a516: f000 f873 bl 800a600 <USBD_CtlError>
break;
800a51a: bf00 nop
}
}
800a51c: bf00 nop
800a51e: 3708 adds r7, #8
800a520: 46bd mov sp, r7
800a522: bd80 pop {r7, pc}
0800a524 <USBD_SetFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a524: b580 push {r7, lr}
800a526: b082 sub sp, #8
800a528: af00 add r7, sp, #0
800a52a: 6078 str r0, [r7, #4]
800a52c: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800a52e: 683b ldr r3, [r7, #0]
800a530: 885b ldrh r3, [r3, #2]
800a532: 2b01 cmp r3, #1
800a534: d106 bne.n 800a544 <USBD_SetFeature+0x20>
{
pdev->dev_remote_wakeup = 1U;
800a536: 687b ldr r3, [r7, #4]
800a538: 2201 movs r2, #1
800a53a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800a53e: 6878 ldr r0, [r7, #4]
800a540: f000 f926 bl 800a790 <USBD_CtlSendStatus>
}
}
800a544: bf00 nop
800a546: 3708 adds r7, #8
800a548: 46bd mov sp, r7
800a54a: bd80 pop {r7, pc}
0800a54c <USBD_ClrFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a54c: b580 push {r7, lr}
800a54e: b082 sub sp, #8
800a550: af00 add r7, sp, #0
800a552: 6078 str r0, [r7, #4]
800a554: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800a556: 687b ldr r3, [r7, #4]
800a558: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a55c: 3b01 subs r3, #1
800a55e: 2b02 cmp r3, #2
800a560: d80b bhi.n 800a57a <USBD_ClrFeature+0x2e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800a562: 683b ldr r3, [r7, #0]
800a564: 885b ldrh r3, [r3, #2]
800a566: 2b01 cmp r3, #1
800a568: d10c bne.n 800a584 <USBD_ClrFeature+0x38>
{
pdev->dev_remote_wakeup = 0U;
800a56a: 687b ldr r3, [r7, #4]
800a56c: 2200 movs r2, #0
800a56e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800a572: 6878 ldr r0, [r7, #4]
800a574: f000 f90c bl 800a790 <USBD_CtlSendStatus>
}
break;
800a578: e004 b.n 800a584 <USBD_ClrFeature+0x38>
default:
USBD_CtlError(pdev, req);
800a57a: 6839 ldr r1, [r7, #0]
800a57c: 6878 ldr r0, [r7, #4]
800a57e: f000 f83f bl 800a600 <USBD_CtlError>
break;
800a582: e000 b.n 800a586 <USBD_ClrFeature+0x3a>
break;
800a584: bf00 nop
}
}
800a586: bf00 nop
800a588: 3708 adds r7, #8
800a58a: 46bd mov sp, r7
800a58c: bd80 pop {r7, pc}
0800a58e <USBD_ParseSetupRequest>:
* @param req: usb request
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
800a58e: b480 push {r7}
800a590: b083 sub sp, #12
800a592: af00 add r7, sp, #0
800a594: 6078 str r0, [r7, #4]
800a596: 6039 str r1, [r7, #0]
req->bmRequest = *(uint8_t *)(pdata);
800a598: 683b ldr r3, [r7, #0]
800a59a: 781a ldrb r2, [r3, #0]
800a59c: 687b ldr r3, [r7, #4]
800a59e: 701a strb r2, [r3, #0]
req->bRequest = *(uint8_t *)(pdata + 1U);
800a5a0: 683b ldr r3, [r7, #0]
800a5a2: 785a ldrb r2, [r3, #1]
800a5a4: 687b ldr r3, [r7, #4]
800a5a6: 705a strb r2, [r3, #1]
req->wValue = SWAPBYTE(pdata + 2U);
800a5a8: 683b ldr r3, [r7, #0]
800a5aa: 3302 adds r3, #2
800a5ac: 781b ldrb r3, [r3, #0]
800a5ae: 461a mov r2, r3
800a5b0: 683b ldr r3, [r7, #0]
800a5b2: 3303 adds r3, #3
800a5b4: 781b ldrb r3, [r3, #0]
800a5b6: 021b lsls r3, r3, #8
800a5b8: b29b uxth r3, r3
800a5ba: 4413 add r3, r2
800a5bc: b29a uxth r2, r3
800a5be: 687b ldr r3, [r7, #4]
800a5c0: 805a strh r2, [r3, #2]
req->wIndex = SWAPBYTE(pdata + 4U);
800a5c2: 683b ldr r3, [r7, #0]
800a5c4: 3304 adds r3, #4
800a5c6: 781b ldrb r3, [r3, #0]
800a5c8: 461a mov r2, r3
800a5ca: 683b ldr r3, [r7, #0]
800a5cc: 3305 adds r3, #5
800a5ce: 781b ldrb r3, [r3, #0]
800a5d0: 021b lsls r3, r3, #8
800a5d2: b29b uxth r3, r3
800a5d4: 4413 add r3, r2
800a5d6: b29a uxth r2, r3
800a5d8: 687b ldr r3, [r7, #4]
800a5da: 809a strh r2, [r3, #4]
req->wLength = SWAPBYTE(pdata + 6U);
800a5dc: 683b ldr r3, [r7, #0]
800a5de: 3306 adds r3, #6
800a5e0: 781b ldrb r3, [r3, #0]
800a5e2: 461a mov r2, r3
800a5e4: 683b ldr r3, [r7, #0]
800a5e6: 3307 adds r3, #7
800a5e8: 781b ldrb r3, [r3, #0]
800a5ea: 021b lsls r3, r3, #8
800a5ec: b29b uxth r3, r3
800a5ee: 4413 add r3, r2
800a5f0: b29a uxth r2, r3
800a5f2: 687b ldr r3, [r7, #4]
800a5f4: 80da strh r2, [r3, #6]
}
800a5f6: bf00 nop
800a5f8: 370c adds r7, #12
800a5fa: 46bd mov sp, r7
800a5fc: bc80 pop {r7}
800a5fe: 4770 bx lr
0800a600 <USBD_CtlError>:
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a600: b580 push {r7, lr}
800a602: b082 sub sp, #8
800a604: af00 add r7, sp, #0
800a606: 6078 str r0, [r7, #4]
800a608: 6039 str r1, [r7, #0]
USBD_LL_StallEP(pdev, 0x80U);
800a60a: 2180 movs r1, #128 @ 0x80
800a60c: 6878 ldr r0, [r7, #4]
800a60e: f000 fcd1 bl 800afb4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0U);
800a612: 2100 movs r1, #0
800a614: 6878 ldr r0, [r7, #4]
800a616: f000 fccd bl 800afb4 <USBD_LL_StallEP>
}
800a61a: bf00 nop
800a61c: 3708 adds r7, #8
800a61e: 46bd mov sp, r7
800a620: bd80 pop {r7, pc}
0800a622 <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
800a622: b580 push {r7, lr}
800a624: b086 sub sp, #24
800a626: af00 add r7, sp, #0
800a628: 60f8 str r0, [r7, #12]
800a62a: 60b9 str r1, [r7, #8]
800a62c: 607a str r2, [r7, #4]
uint8_t idx = 0U;
800a62e: 2300 movs r3, #0
800a630: 75fb strb r3, [r7, #23]
if (desc != NULL)
800a632: 68fb ldr r3, [r7, #12]
800a634: 2b00 cmp r3, #0
800a636: d032 beq.n 800a69e <USBD_GetString+0x7c>
{
*len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
800a638: 68f8 ldr r0, [r7, #12]
800a63a: f000 f834 bl 800a6a6 <USBD_GetLen>
800a63e: 4603 mov r3, r0
800a640: 3301 adds r3, #1
800a642: b29b uxth r3, r3
800a644: 005b lsls r3, r3, #1
800a646: b29a uxth r2, r3
800a648: 687b ldr r3, [r7, #4]
800a64a: 801a strh r2, [r3, #0]
unicode[idx++] = *(uint8_t *)(void *)len;
800a64c: 7dfb ldrb r3, [r7, #23]
800a64e: 1c5a adds r2, r3, #1
800a650: 75fa strb r2, [r7, #23]
800a652: 461a mov r2, r3
800a654: 68bb ldr r3, [r7, #8]
800a656: 4413 add r3, r2
800a658: 687a ldr r2, [r7, #4]
800a65a: 7812 ldrb r2, [r2, #0]
800a65c: 701a strb r2, [r3, #0]
unicode[idx++] = USB_DESC_TYPE_STRING;
800a65e: 7dfb ldrb r3, [r7, #23]
800a660: 1c5a adds r2, r3, #1
800a662: 75fa strb r2, [r7, #23]
800a664: 461a mov r2, r3
800a666: 68bb ldr r3, [r7, #8]
800a668: 4413 add r3, r2
800a66a: 2203 movs r2, #3
800a66c: 701a strb r2, [r3, #0]
while (*desc != '\0')
800a66e: e012 b.n 800a696 <USBD_GetString+0x74>
{
unicode[idx++] = *desc++;
800a670: 68fb ldr r3, [r7, #12]
800a672: 1c5a adds r2, r3, #1
800a674: 60fa str r2, [r7, #12]
800a676: 7dfa ldrb r2, [r7, #23]
800a678: 1c51 adds r1, r2, #1
800a67a: 75f9 strb r1, [r7, #23]
800a67c: 4611 mov r1, r2
800a67e: 68ba ldr r2, [r7, #8]
800a680: 440a add r2, r1
800a682: 781b ldrb r3, [r3, #0]
800a684: 7013 strb r3, [r2, #0]
unicode[idx++] = 0U;
800a686: 7dfb ldrb r3, [r7, #23]
800a688: 1c5a adds r2, r3, #1
800a68a: 75fa strb r2, [r7, #23]
800a68c: 461a mov r2, r3
800a68e: 68bb ldr r3, [r7, #8]
800a690: 4413 add r3, r2
800a692: 2200 movs r2, #0
800a694: 701a strb r2, [r3, #0]
while (*desc != '\0')
800a696: 68fb ldr r3, [r7, #12]
800a698: 781b ldrb r3, [r3, #0]
800a69a: 2b00 cmp r3, #0
800a69c: d1e8 bne.n 800a670 <USBD_GetString+0x4e>
}
}
}
800a69e: bf00 nop
800a6a0: 3718 adds r7, #24
800a6a2: 46bd mov sp, r7
800a6a4: bd80 pop {r7, pc}
0800a6a6 <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
800a6a6: b480 push {r7}
800a6a8: b085 sub sp, #20
800a6aa: af00 add r7, sp, #0
800a6ac: 6078 str r0, [r7, #4]
uint8_t len = 0U;
800a6ae: 2300 movs r3, #0
800a6b0: 73fb strb r3, [r7, #15]
while (*buf != '\0')
800a6b2: e005 b.n 800a6c0 <USBD_GetLen+0x1a>
{
len++;
800a6b4: 7bfb ldrb r3, [r7, #15]
800a6b6: 3301 adds r3, #1
800a6b8: 73fb strb r3, [r7, #15]
buf++;
800a6ba: 687b ldr r3, [r7, #4]
800a6bc: 3301 adds r3, #1
800a6be: 607b str r3, [r7, #4]
while (*buf != '\0')
800a6c0: 687b ldr r3, [r7, #4]
800a6c2: 781b ldrb r3, [r3, #0]
800a6c4: 2b00 cmp r3, #0
800a6c6: d1f5 bne.n 800a6b4 <USBD_GetLen+0xe>
}
return len;
800a6c8: 7bfb ldrb r3, [r7, #15]
}
800a6ca: 4618 mov r0, r3
800a6cc: 3714 adds r7, #20
800a6ce: 46bd mov sp, r7
800a6d0: bc80 pop {r7}
800a6d2: 4770 bx lr
0800a6d4 <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a6d4: b580 push {r7, lr}
800a6d6: b084 sub sp, #16
800a6d8: af00 add r7, sp, #0
800a6da: 60f8 str r0, [r7, #12]
800a6dc: 60b9 str r1, [r7, #8]
800a6de: 4613 mov r3, r2
800a6e0: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
800a6e2: 68fb ldr r3, [r7, #12]
800a6e4: 2202 movs r2, #2
800a6e6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
800a6ea: 88fa ldrh r2, [r7, #6]
800a6ec: 68fb ldr r3, [r7, #12]
800a6ee: 61da str r2, [r3, #28]
pdev->ep_in[0].rem_length = len;
800a6f0: 88fa ldrh r2, [r7, #6]
800a6f2: 68fb ldr r3, [r7, #12]
800a6f4: 621a str r2, [r3, #32]
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800a6f6: 88fb ldrh r3, [r7, #6]
800a6f8: 68ba ldr r2, [r7, #8]
800a6fa: 2100 movs r1, #0
800a6fc: 68f8 ldr r0, [r7, #12]
800a6fe: f000 fce1 bl 800b0c4 <USBD_LL_Transmit>
return USBD_OK;
800a702: 2300 movs r3, #0
}
800a704: 4618 mov r0, r3
800a706: 3710 adds r7, #16
800a708: 46bd mov sp, r7
800a70a: bd80 pop {r7, pc}
0800a70c <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a70c: b580 push {r7, lr}
800a70e: b084 sub sp, #16
800a710: af00 add r7, sp, #0
800a712: 60f8 str r0, [r7, #12]
800a714: 60b9 str r1, [r7, #8]
800a716: 4613 mov r3, r2
800a718: 80fb strh r3, [r7, #6]
/* Start the next transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800a71a: 88fb ldrh r3, [r7, #6]
800a71c: 68ba ldr r2, [r7, #8]
800a71e: 2100 movs r1, #0
800a720: 68f8 ldr r0, [r7, #12]
800a722: f000 fccf bl 800b0c4 <USBD_LL_Transmit>
return USBD_OK;
800a726: 2300 movs r3, #0
}
800a728: 4618 mov r0, r3
800a72a: 3710 adds r7, #16
800a72c: 46bd mov sp, r7
800a72e: bd80 pop {r7, pc}
0800a730 <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a730: b580 push {r7, lr}
800a732: b084 sub sp, #16
800a734: af00 add r7, sp, #0
800a736: 60f8 str r0, [r7, #12]
800a738: 60b9 str r1, [r7, #8]
800a73a: 4613 mov r3, r2
800a73c: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
800a73e: 68fb ldr r3, [r7, #12]
800a740: 2203 movs r2, #3
800a742: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_out[0].total_length = len;
800a746: 88fa ldrh r2, [r7, #6]
800a748: 68fb ldr r3, [r7, #12]
800a74a: f8c3 215c str.w r2, [r3, #348] @ 0x15c
pdev->ep_out[0].rem_length = len;
800a74e: 88fa ldrh r2, [r7, #6]
800a750: 68fb ldr r3, [r7, #12]
800a752: f8c3 2160 str.w r2, [r3, #352] @ 0x160
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800a756: 88fb ldrh r3, [r7, #6]
800a758: 68ba ldr r2, [r7, #8]
800a75a: 2100 movs r1, #0
800a75c: 68f8 ldr r0, [r7, #12]
800a75e: f000 fcd4 bl 800b10a <USBD_LL_PrepareReceive>
return USBD_OK;
800a762: 2300 movs r3, #0
}
800a764: 4618 mov r0, r3
800a766: 3710 adds r7, #16
800a768: 46bd mov sp, r7
800a76a: bd80 pop {r7, pc}
0800a76c <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800a76c: b580 push {r7, lr}
800a76e: b084 sub sp, #16
800a770: af00 add r7, sp, #0
800a772: 60f8 str r0, [r7, #12]
800a774: 60b9 str r1, [r7, #8]
800a776: 4613 mov r3, r2
800a778: 80fb strh r3, [r7, #6]
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800a77a: 88fb ldrh r3, [r7, #6]
800a77c: 68ba ldr r2, [r7, #8]
800a77e: 2100 movs r1, #0
800a780: 68f8 ldr r0, [r7, #12]
800a782: f000 fcc2 bl 800b10a <USBD_LL_PrepareReceive>
return USBD_OK;
800a786: 2300 movs r3, #0
}
800a788: 4618 mov r0, r3
800a78a: 3710 adds r7, #16
800a78c: 46bd mov sp, r7
800a78e: bd80 pop {r7, pc}
0800a790 <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
800a790: b580 push {r7, lr}
800a792: b082 sub sp, #8
800a794: af00 add r7, sp, #0
800a796: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
800a798: 687b ldr r3, [r7, #4]
800a79a: 2204 movs r2, #4
800a79c: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
800a7a0: 2300 movs r3, #0
800a7a2: 2200 movs r2, #0
800a7a4: 2100 movs r1, #0
800a7a6: 6878 ldr r0, [r7, #4]
800a7a8: f000 fc8c bl 800b0c4 <USBD_LL_Transmit>
return USBD_OK;
800a7ac: 2300 movs r3, #0
}
800a7ae: 4618 mov r0, r3
800a7b0: 3708 adds r7, #8
800a7b2: 46bd mov sp, r7
800a7b4: bd80 pop {r7, pc}
0800a7b6 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
800a7b6: b580 push {r7, lr}
800a7b8: b082 sub sp, #8
800a7ba: af00 add r7, sp, #0
800a7bc: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
800a7be: 687b ldr r3, [r7, #4]
800a7c0: 2205 movs r2, #5
800a7c2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800a7c6: 2300 movs r3, #0
800a7c8: 2200 movs r2, #0
800a7ca: 2100 movs r1, #0
800a7cc: 6878 ldr r0, [r7, #4]
800a7ce: f000 fc9c bl 800b10a <USBD_LL_PrepareReceive>
return USBD_OK;
800a7d2: 2300 movs r3, #0
}
800a7d4: 4618 mov r0, r3
800a7d6: 3708 adds r7, #8
800a7d8: 46bd mov sp, r7
800a7da: bd80 pop {r7, pc}
0800a7dc <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
800a7dc: b580 push {r7, lr}
800a7de: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
800a7e0: 2200 movs r2, #0
800a7e2: 4912 ldr r1, [pc, #72] @ (800a82c <MX_USB_DEVICE_Init+0x50>)
800a7e4: 4812 ldr r0, [pc, #72] @ (800a830 <MX_USB_DEVICE_Init+0x54>)
800a7e6: f7fe ff62 bl 80096ae <USBD_Init>
800a7ea: 4603 mov r3, r0
800a7ec: 2b00 cmp r3, #0
800a7ee: d001 beq.n 800a7f4 <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
800a7f0: f7f7 f870 bl 80018d4 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
800a7f4: 490f ldr r1, [pc, #60] @ (800a834 <MX_USB_DEVICE_Init+0x58>)
800a7f6: 480e ldr r0, [pc, #56] @ (800a830 <MX_USB_DEVICE_Init+0x54>)
800a7f8: f7fe ff84 bl 8009704 <USBD_RegisterClass>
800a7fc: 4603 mov r3, r0
800a7fe: 2b00 cmp r3, #0
800a800: d001 beq.n 800a806 <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
800a802: f7f7 f867 bl 80018d4 <Error_Handler>
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
800a806: 490c ldr r1, [pc, #48] @ (800a838 <MX_USB_DEVICE_Init+0x5c>)
800a808: 4809 ldr r0, [pc, #36] @ (800a830 <MX_USB_DEVICE_Init+0x54>)
800a80a: f7fe feb5 bl 8009578 <USBD_CDC_RegisterInterface>
800a80e: 4603 mov r3, r0
800a810: 2b00 cmp r3, #0
800a812: d001 beq.n 800a818 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
800a814: f7f7 f85e bl 80018d4 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
800a818: 4805 ldr r0, [pc, #20] @ (800a830 <MX_USB_DEVICE_Init+0x54>)
800a81a: f7fe ff8c bl 8009736 <USBD_Start>
800a81e: 4603 mov r3, r0
800a820: 2b00 cmp r3, #0
800a822: d001 beq.n 800a828 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
800a824: f7f7 f856 bl 80018d4 <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
800a828: bf00 nop
800a82a: bd80 pop {r7, pc}
800a82c: 20000130 .word 0x20000130
800a830: 20000414 .word 0x20000414
800a834: 2000001c .word 0x2000001c
800a838: 20000120 .word 0x20000120
0800a83c <fifo_push>:
/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
#define RX_FIFO_SZ 256
static uint8_t rx_fifo[RX_FIFO_SZ];
static volatile uint16_t rx_head = 0, rx_tail = 0;
static void fifo_push(const uint8_t* data, uint32_t len) {
800a83c: b480 push {r7}
800a83e: b085 sub sp, #20
800a840: af00 add r7, sp, #0
800a842: 6078 str r0, [r7, #4]
800a844: 6039 str r1, [r7, #0]
while (len--) {
800a846: e01e b.n 800a886 <fifo_push+0x4a>
uint16_t next = (rx_head + 1u) & (RX_FIFO_SZ - 1u);
800a848: 4b14 ldr r3, [pc, #80] @ (800a89c <fifo_push+0x60>)
800a84a: 881b ldrh r3, [r3, #0]
800a84c: b29b uxth r3, r3
800a84e: 3301 adds r3, #1
800a850: b29b uxth r3, r3
800a852: b2db uxtb r3, r3
800a854: 81fb strh r3, [r7, #14]
if (next == (rx_tail & (RX_FIFO_SZ - 1u))) {
800a856: 89fa ldrh r2, [r7, #14]
800a858: 4b11 ldr r3, [pc, #68] @ (800a8a0 <fifo_push+0x64>)
800a85a: 881b ldrh r3, [r3, #0]
800a85c: b29b uxth r3, r3
800a85e: b2db uxtb r3, r3
800a860: 429a cmp r2, r3
800a862: d103 bne.n 800a86c <fifo_push+0x30>
/* overflow — drop byte (or set a flag) */
data++;
800a864: 687b ldr r3, [r7, #4]
800a866: 3301 adds r3, #1
800a868: 607b str r3, [r7, #4]
continue;
800a86a: e00c b.n 800a886 <fifo_push+0x4a>
}
rx_fifo[rx_head & (RX_FIFO_SZ - 1u)] = *data++;
800a86c: 687b ldr r3, [r7, #4]
800a86e: 1c5a adds r2, r3, #1
800a870: 607a str r2, [r7, #4]
800a872: 4a0a ldr r2, [pc, #40] @ (800a89c <fifo_push+0x60>)
800a874: 8812 ldrh r2, [r2, #0]
800a876: b292 uxth r2, r2
800a878: b2d2 uxtb r2, r2
800a87a: 7819 ldrb r1, [r3, #0]
800a87c: 4b09 ldr r3, [pc, #36] @ (800a8a4 <fifo_push+0x68>)
800a87e: 5499 strb r1, [r3, r2]
rx_head = next;
800a880: 4a06 ldr r2, [pc, #24] @ (800a89c <fifo_push+0x60>)
800a882: 89fb ldrh r3, [r7, #14]
800a884: 8013 strh r3, [r2, #0]
while (len--) {
800a886: 683b ldr r3, [r7, #0]
800a888: 1e5a subs r2, r3, #1
800a88a: 603a str r2, [r7, #0]
800a88c: 2b00 cmp r3, #0
800a88e: d1db bne.n 800a848 <fifo_push+0xc>
}
}
800a890: bf00 nop
800a892: bf00 nop
800a894: 3714 adds r7, #20
800a896: 46bd mov sp, r7
800a898: bc80 pop {r7}
800a89a: 4770 bx lr
800a89c: 20000fd8 .word 0x20000fd8
800a8a0: 20000fda .word 0x20000fda
800a8a4: 20000ed8 .word 0x20000ed8
0800a8a8 <CDC_Available>:
uint32_t CDC_Available(void) {
800a8a8: b480 push {r7}
800a8aa: af00 add r7, sp, #0
return (uint16_t)((rx_head - rx_tail) & (RX_FIFO_SZ - 1u));
800a8ac: 4b06 ldr r3, [pc, #24] @ (800a8c8 <CDC_Available+0x20>)
800a8ae: 881b ldrh r3, [r3, #0]
800a8b0: b29a uxth r2, r3
800a8b2: 4b06 ldr r3, [pc, #24] @ (800a8cc <CDC_Available+0x24>)
800a8b4: 881b ldrh r3, [r3, #0]
800a8b6: b29b uxth r3, r3
800a8b8: 1ad3 subs r3, r2, r3
800a8ba: b29b uxth r3, r3
800a8bc: b2db uxtb r3, r3
}
800a8be: 4618 mov r0, r3
800a8c0: 46bd mov sp, r7
800a8c2: bc80 pop {r7}
800a8c4: 4770 bx lr
800a8c6: bf00 nop
800a8c8: 20000fd8 .word 0x20000fd8
800a8cc: 20000fda .word 0x20000fda
0800a8d0 <CDC_ReadByte>:
int CDC_ReadByte(void) {
800a8d0: b480 push {r7}
800a8d2: b083 sub sp, #12
800a8d4: af00 add r7, sp, #0
if (rx_tail == rx_head) return -1;
800a8d6: 4b10 ldr r3, [pc, #64] @ (800a918 <CDC_ReadByte+0x48>)
800a8d8: 881b ldrh r3, [r3, #0]
800a8da: b29a uxth r2, r3
800a8dc: 4b0f ldr r3, [pc, #60] @ (800a91c <CDC_ReadByte+0x4c>)
800a8de: 881b ldrh r3, [r3, #0]
800a8e0: b29b uxth r3, r3
800a8e2: 429a cmp r2, r3
800a8e4: d102 bne.n 800a8ec <CDC_ReadByte+0x1c>
800a8e6: f04f 33ff mov.w r3, #4294967295
800a8ea: e010 b.n 800a90e <CDC_ReadByte+0x3e>
int b = rx_fifo[rx_tail & (RX_FIFO_SZ - 1u)];
800a8ec: 4b0a ldr r3, [pc, #40] @ (800a918 <CDC_ReadByte+0x48>)
800a8ee: 881b ldrh r3, [r3, #0]
800a8f0: b29b uxth r3, r3
800a8f2: b2db uxtb r3, r3
800a8f4: 4a0a ldr r2, [pc, #40] @ (800a920 <CDC_ReadByte+0x50>)
800a8f6: 5cd3 ldrb r3, [r2, r3]
800a8f8: 607b str r3, [r7, #4]
rx_tail = (rx_tail + 1u) & (RX_FIFO_SZ - 1u);
800a8fa: 4b07 ldr r3, [pc, #28] @ (800a918 <CDC_ReadByte+0x48>)
800a8fc: 881b ldrh r3, [r3, #0]
800a8fe: b29b uxth r3, r3
800a900: 3301 adds r3, #1
800a902: b29b uxth r3, r3
800a904: b2db uxtb r3, r3
800a906: b29a uxth r2, r3
800a908: 4b03 ldr r3, [pc, #12] @ (800a918 <CDC_ReadByte+0x48>)
800a90a: 801a strh r2, [r3, #0]
return b;
800a90c: 687b ldr r3, [r7, #4]
}
800a90e: 4618 mov r0, r3
800a910: 370c adds r7, #12
800a912: 46bd mov sp, r7
800a914: bc80 pop {r7}
800a916: 4770 bx lr
800a918: 20000fda .word 0x20000fda
800a91c: 20000fd8 .word 0x20000fd8
800a920: 20000ed8 .word 0x20000ed8
0800a924 <CDC_Init_FS>:
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
800a924: b580 push {r7, lr}
800a926: af00 add r7, sp, #0
/* USER CODE BEGIN 3 */
/* Set Application Buffers */
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
800a928: 2200 movs r2, #0
800a92a: 4905 ldr r1, [pc, #20] @ (800a940 <CDC_Init_FS+0x1c>)
800a92c: 4805 ldr r0, [pc, #20] @ (800a944 <CDC_Init_FS+0x20>)
800a92e: f7fe fe39 bl 80095a4 <USBD_CDC_SetTxBuffer>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
800a932: 4905 ldr r1, [pc, #20] @ (800a948 <CDC_Init_FS+0x24>)
800a934: 4803 ldr r0, [pc, #12] @ (800a944 <CDC_Init_FS+0x20>)
800a936: f7fe fe4e bl 80095d6 <USBD_CDC_SetRxBuffer>
return (USBD_OK);
800a93a: 2300 movs r3, #0
/* USER CODE END 3 */
}
800a93c: 4618 mov r0, r3
800a93e: bd80 pop {r7, pc}
800a940: 20000ad8 .word 0x20000ad8
800a944: 20000414 .word 0x20000414
800a948: 200006d8 .word 0x200006d8
0800a94c <CDC_DeInit_FS>:
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
800a94c: b480 push {r7}
800a94e: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
800a950: 2300 movs r3, #0
/* USER CODE END 4 */
}
800a952: 4618 mov r0, r3
800a954: 46bd mov sp, r7
800a956: bc80 pop {r7}
800a958: 4770 bx lr
...
0800a95c <CDC_Control_FS>:
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
800a95c: b480 push {r7}
800a95e: b083 sub sp, #12
800a960: af00 add r7, sp, #0
800a962: 4603 mov r3, r0
800a964: 6039 str r1, [r7, #0]
800a966: 71fb strb r3, [r7, #7]
800a968: 4613 mov r3, r2
800a96a: 80bb strh r3, [r7, #4]
/* USER CODE BEGIN 5 */
switch(cmd)
800a96c: 79fb ldrb r3, [r7, #7]
800a96e: 2b23 cmp r3, #35 @ 0x23
800a970: d84a bhi.n 800aa08 <CDC_Control_FS+0xac>
800a972: a201 add r2, pc, #4 @ (adr r2, 800a978 <CDC_Control_FS+0x1c>)
800a974: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a978: 0800aa09 .word 0x0800aa09
800a97c: 0800aa09 .word 0x0800aa09
800a980: 0800aa09 .word 0x0800aa09
800a984: 0800aa09 .word 0x0800aa09
800a988: 0800aa09 .word 0x0800aa09
800a98c: 0800aa09 .word 0x0800aa09
800a990: 0800aa09 .word 0x0800aa09
800a994: 0800aa09 .word 0x0800aa09
800a998: 0800aa09 .word 0x0800aa09
800a99c: 0800aa09 .word 0x0800aa09
800a9a0: 0800aa09 .word 0x0800aa09
800a9a4: 0800aa09 .word 0x0800aa09
800a9a8: 0800aa09 .word 0x0800aa09
800a9ac: 0800aa09 .word 0x0800aa09
800a9b0: 0800aa09 .word 0x0800aa09
800a9b4: 0800aa09 .word 0x0800aa09
800a9b8: 0800aa09 .word 0x0800aa09
800a9bc: 0800aa09 .word 0x0800aa09
800a9c0: 0800aa09 .word 0x0800aa09
800a9c4: 0800aa09 .word 0x0800aa09
800a9c8: 0800aa09 .word 0x0800aa09
800a9cc: 0800aa09 .word 0x0800aa09
800a9d0: 0800aa09 .word 0x0800aa09
800a9d4: 0800aa09 .word 0x0800aa09
800a9d8: 0800aa09 .word 0x0800aa09
800a9dc: 0800aa09 .word 0x0800aa09
800a9e0: 0800aa09 .word 0x0800aa09
800a9e4: 0800aa09 .word 0x0800aa09
800a9e8: 0800aa09 .word 0x0800aa09
800a9ec: 0800aa09 .word 0x0800aa09
800a9f0: 0800aa09 .word 0x0800aa09
800a9f4: 0800aa09 .word 0x0800aa09
800a9f8: 0800aa09 .word 0x0800aa09
800a9fc: 0800aa09 .word 0x0800aa09
800aa00: 0800aa09 .word 0x0800aa09
800aa04: 0800aa09 .word 0x0800aa09
case CDC_SEND_BREAK:
break;
default:
break;
800aa08: bf00 nop
}
return (USBD_OK);
800aa0a: 2300 movs r3, #0
/* USER CODE END 5 */
}
800aa0c: 4618 mov r0, r3
800aa0e: 370c adds r7, #12
800aa10: 46bd mov sp, r7
800aa12: bc80 pop {r7}
800aa14: 4770 bx lr
800aa16: bf00 nop
0800aa18 <CDC_Receive_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
800aa18: b580 push {r7, lr}
800aa1a: b082 sub sp, #8
800aa1c: af00 add r7, sp, #0
800aa1e: 6078 str r0, [r7, #4]
800aa20: 6039 str r1, [r7, #0]
/* USER CODE BEGIN 6 */
if (*Len) fifo_push(Buf, *Len);
800aa22: 683b ldr r3, [r7, #0]
800aa24: 681b ldr r3, [r3, #0]
800aa26: 2b00 cmp r3, #0
800aa28: d005 beq.n 800aa36 <CDC_Receive_FS+0x1e>
800aa2a: 683b ldr r3, [r7, #0]
800aa2c: 681b ldr r3, [r3, #0]
800aa2e: 4619 mov r1, r3
800aa30: 6878 ldr r0, [r7, #4]
800aa32: f7ff ff03 bl 800a83c <fifo_push>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
800aa36: 6879 ldr r1, [r7, #4]
800aa38: 4805 ldr r0, [pc, #20] @ (800aa50 <CDC_Receive_FS+0x38>)
800aa3a: f7fe fdcc bl 80095d6 <USBD_CDC_SetRxBuffer>
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
800aa3e: 4804 ldr r0, [pc, #16] @ (800aa50 <CDC_Receive_FS+0x38>)
800aa40: f7fe fe0b bl 800965a <USBD_CDC_ReceivePacket>
return (USBD_OK);
800aa44: 2300 movs r3, #0
/* USER CODE END 6 */
}
800aa46: 4618 mov r0, r3
800aa48: 3708 adds r7, #8
800aa4a: 46bd mov sp, r7
800aa4c: bd80 pop {r7, pc}
800aa4e: bf00 nop
800aa50: 20000414 .word 0x20000414
0800aa54 <CDC_Transmit_FS>:
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
800aa54: b580 push {r7, lr}
800aa56: b084 sub sp, #16
800aa58: af00 add r7, sp, #0
800aa5a: 6078 str r0, [r7, #4]
800aa5c: 460b mov r3, r1
800aa5e: 807b strh r3, [r7, #2]
uint8_t result = USBD_OK;
800aa60: 2300 movs r3, #0
800aa62: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
800aa64: 4b0d ldr r3, [pc, #52] @ (800aa9c <CDC_Transmit_FS+0x48>)
800aa66: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800aa6a: 60bb str r3, [r7, #8]
if (hcdc->TxState != 0){
800aa6c: 68bb ldr r3, [r7, #8]
800aa6e: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800aa72: 2b00 cmp r3, #0
800aa74: d001 beq.n 800aa7a <CDC_Transmit_FS+0x26>
return USBD_BUSY;
800aa76: 2301 movs r3, #1
800aa78: e00b b.n 800aa92 <CDC_Transmit_FS+0x3e>
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
800aa7a: 887b ldrh r3, [r7, #2]
800aa7c: 461a mov r2, r3
800aa7e: 6879 ldr r1, [r7, #4]
800aa80: 4806 ldr r0, [pc, #24] @ (800aa9c <CDC_Transmit_FS+0x48>)
800aa82: f7fe fd8f bl 80095a4 <USBD_CDC_SetTxBuffer>
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
800aa86: 4805 ldr r0, [pc, #20] @ (800aa9c <CDC_Transmit_FS+0x48>)
800aa88: f7fe fdb8 bl 80095fc <USBD_CDC_TransmitPacket>
800aa8c: 4603 mov r3, r0
800aa8e: 73fb strb r3, [r7, #15]
/* USER CODE END 7 */
return result;
800aa90: 7bfb ldrb r3, [r7, #15]
}
800aa92: 4618 mov r0, r3
800aa94: 3710 adds r7, #16
800aa96: 46bd mov sp, r7
800aa98: bd80 pop {r7, pc}
800aa9a: bf00 nop
800aa9c: 20000414 .word 0x20000414
0800aaa0 <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aaa0: b480 push {r7}
800aaa2: b083 sub sp, #12
800aaa4: af00 add r7, sp, #0
800aaa6: 4603 mov r3, r0
800aaa8: 6039 str r1, [r7, #0]
800aaaa: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
800aaac: 683b ldr r3, [r7, #0]
800aaae: 2212 movs r2, #18
800aab0: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
800aab2: 4b03 ldr r3, [pc, #12] @ (800aac0 <USBD_FS_DeviceDescriptor+0x20>)
}
800aab4: 4618 mov r0, r3
800aab6: 370c adds r7, #12
800aab8: 46bd mov sp, r7
800aaba: bc80 pop {r7}
800aabc: 4770 bx lr
800aabe: bf00 nop
800aac0: 2000014c .word 0x2000014c
0800aac4 <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aac4: b480 push {r7}
800aac6: b083 sub sp, #12
800aac8: af00 add r7, sp, #0
800aaca: 4603 mov r3, r0
800aacc: 6039 str r1, [r7, #0]
800aace: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
800aad0: 683b ldr r3, [r7, #0]
800aad2: 2204 movs r2, #4
800aad4: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
800aad6: 4b03 ldr r3, [pc, #12] @ (800aae4 <USBD_FS_LangIDStrDescriptor+0x20>)
}
800aad8: 4618 mov r0, r3
800aada: 370c adds r7, #12
800aadc: 46bd mov sp, r7
800aade: bc80 pop {r7}
800aae0: 4770 bx lr
800aae2: bf00 nop
800aae4: 20000160 .word 0x20000160
0800aae8 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800aae8: b580 push {r7, lr}
800aaea: b082 sub sp, #8
800aaec: af00 add r7, sp, #0
800aaee: 4603 mov r3, r0
800aaf0: 6039 str r1, [r7, #0]
800aaf2: 71fb strb r3, [r7, #7]
if(speed == 0)
800aaf4: 79fb ldrb r3, [r7, #7]
800aaf6: 2b00 cmp r3, #0
800aaf8: d105 bne.n 800ab06 <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800aafa: 683a ldr r2, [r7, #0]
800aafc: 4907 ldr r1, [pc, #28] @ (800ab1c <USBD_FS_ProductStrDescriptor+0x34>)
800aafe: 4808 ldr r0, [pc, #32] @ (800ab20 <USBD_FS_ProductStrDescriptor+0x38>)
800ab00: f7ff fd8f bl 800a622 <USBD_GetString>
800ab04: e004 b.n 800ab10 <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800ab06: 683a ldr r2, [r7, #0]
800ab08: 4904 ldr r1, [pc, #16] @ (800ab1c <USBD_FS_ProductStrDescriptor+0x34>)
800ab0a: 4805 ldr r0, [pc, #20] @ (800ab20 <USBD_FS_ProductStrDescriptor+0x38>)
800ab0c: f7ff fd89 bl 800a622 <USBD_GetString>
}
return USBD_StrDesc;
800ab10: 4b02 ldr r3, [pc, #8] @ (800ab1c <USBD_FS_ProductStrDescriptor+0x34>)
}
800ab12: 4618 mov r0, r3
800ab14: 3708 adds r7, #8
800ab16: 46bd mov sp, r7
800ab18: bd80 pop {r7, pc}
800ab1a: bf00 nop
800ab1c: 20000fdc .word 0x20000fdc
800ab20: 0800bd60 .word 0x0800bd60
0800ab24 <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ab24: b580 push {r7, lr}
800ab26: b082 sub sp, #8
800ab28: af00 add r7, sp, #0
800ab2a: 4603 mov r3, r0
800ab2c: 6039 str r1, [r7, #0]
800ab2e: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
800ab30: 683a ldr r2, [r7, #0]
800ab32: 4904 ldr r1, [pc, #16] @ (800ab44 <USBD_FS_ManufacturerStrDescriptor+0x20>)
800ab34: 4804 ldr r0, [pc, #16] @ (800ab48 <USBD_FS_ManufacturerStrDescriptor+0x24>)
800ab36: f7ff fd74 bl 800a622 <USBD_GetString>
return USBD_StrDesc;
800ab3a: 4b02 ldr r3, [pc, #8] @ (800ab44 <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
800ab3c: 4618 mov r0, r3
800ab3e: 3708 adds r7, #8
800ab40: 46bd mov sp, r7
800ab42: bd80 pop {r7, pc}
800ab44: 20000fdc .word 0x20000fdc
800ab48: 0800bd78 .word 0x0800bd78
0800ab4c <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ab4c: b580 push {r7, lr}
800ab4e: b082 sub sp, #8
800ab50: af00 add r7, sp, #0
800ab52: 4603 mov r3, r0
800ab54: 6039 str r1, [r7, #0]
800ab56: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
800ab58: 683b ldr r3, [r7, #0]
800ab5a: 221a movs r2, #26
800ab5c: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
800ab5e: f000 f843 bl 800abe8 <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
800ab62: 4b02 ldr r3, [pc, #8] @ (800ab6c <USBD_FS_SerialStrDescriptor+0x20>)
}
800ab64: 4618 mov r0, r3
800ab66: 3708 adds r7, #8
800ab68: 46bd mov sp, r7
800ab6a: bd80 pop {r7, pc}
800ab6c: 20000164 .word 0x20000164
0800ab70 <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800ab70: b580 push {r7, lr}
800ab72: b082 sub sp, #8
800ab74: af00 add r7, sp, #0
800ab76: 4603 mov r3, r0
800ab78: 6039 str r1, [r7, #0]
800ab7a: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
800ab7c: 79fb ldrb r3, [r7, #7]
800ab7e: 2b00 cmp r3, #0
800ab80: d105 bne.n 800ab8e <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800ab82: 683a ldr r2, [r7, #0]
800ab84: 4907 ldr r1, [pc, #28] @ (800aba4 <USBD_FS_ConfigStrDescriptor+0x34>)
800ab86: 4808 ldr r0, [pc, #32] @ (800aba8 <USBD_FS_ConfigStrDescriptor+0x38>)
800ab88: f7ff fd4b bl 800a622 <USBD_GetString>
800ab8c: e004 b.n 800ab98 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800ab8e: 683a ldr r2, [r7, #0]
800ab90: 4904 ldr r1, [pc, #16] @ (800aba4 <USBD_FS_ConfigStrDescriptor+0x34>)
800ab92: 4805 ldr r0, [pc, #20] @ (800aba8 <USBD_FS_ConfigStrDescriptor+0x38>)
800ab94: f7ff fd45 bl 800a622 <USBD_GetString>
}
return USBD_StrDesc;
800ab98: 4b02 ldr r3, [pc, #8] @ (800aba4 <USBD_FS_ConfigStrDescriptor+0x34>)
}
800ab9a: 4618 mov r0, r3
800ab9c: 3708 adds r7, #8
800ab9e: 46bd mov sp, r7
800aba0: bd80 pop {r7, pc}
800aba2: bf00 nop
800aba4: 20000fdc .word 0x20000fdc
800aba8: 0800bd8c .word 0x0800bd8c
0800abac <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800abac: b580 push {r7, lr}
800abae: b082 sub sp, #8
800abb0: af00 add r7, sp, #0
800abb2: 4603 mov r3, r0
800abb4: 6039 str r1, [r7, #0]
800abb6: 71fb strb r3, [r7, #7]
if(speed == 0)
800abb8: 79fb ldrb r3, [r7, #7]
800abba: 2b00 cmp r3, #0
800abbc: d105 bne.n 800abca <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800abbe: 683a ldr r2, [r7, #0]
800abc0: 4907 ldr r1, [pc, #28] @ (800abe0 <USBD_FS_InterfaceStrDescriptor+0x34>)
800abc2: 4808 ldr r0, [pc, #32] @ (800abe4 <USBD_FS_InterfaceStrDescriptor+0x38>)
800abc4: f7ff fd2d bl 800a622 <USBD_GetString>
800abc8: e004 b.n 800abd4 <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800abca: 683a ldr r2, [r7, #0]
800abcc: 4904 ldr r1, [pc, #16] @ (800abe0 <USBD_FS_InterfaceStrDescriptor+0x34>)
800abce: 4805 ldr r0, [pc, #20] @ (800abe4 <USBD_FS_InterfaceStrDescriptor+0x38>)
800abd0: f7ff fd27 bl 800a622 <USBD_GetString>
}
return USBD_StrDesc;
800abd4: 4b02 ldr r3, [pc, #8] @ (800abe0 <USBD_FS_InterfaceStrDescriptor+0x34>)
}
800abd6: 4618 mov r0, r3
800abd8: 3708 adds r7, #8
800abda: 46bd mov sp, r7
800abdc: bd80 pop {r7, pc}
800abde: bf00 nop
800abe0: 20000fdc .word 0x20000fdc
800abe4: 0800bd98 .word 0x0800bd98
0800abe8 <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
800abe8: b580 push {r7, lr}
800abea: b084 sub sp, #16
800abec: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
800abee: 4b0f ldr r3, [pc, #60] @ (800ac2c <Get_SerialNum+0x44>)
800abf0: 681b ldr r3, [r3, #0]
800abf2: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
800abf4: 4b0e ldr r3, [pc, #56] @ (800ac30 <Get_SerialNum+0x48>)
800abf6: 681b ldr r3, [r3, #0]
800abf8: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
800abfa: 4b0e ldr r3, [pc, #56] @ (800ac34 <Get_SerialNum+0x4c>)
800abfc: 681b ldr r3, [r3, #0]
800abfe: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
800ac00: 68fa ldr r2, [r7, #12]
800ac02: 687b ldr r3, [r7, #4]
800ac04: 4413 add r3, r2
800ac06: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
800ac08: 68fb ldr r3, [r7, #12]
800ac0a: 2b00 cmp r3, #0
800ac0c: d009 beq.n 800ac22 <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
800ac0e: 2208 movs r2, #8
800ac10: 4909 ldr r1, [pc, #36] @ (800ac38 <Get_SerialNum+0x50>)
800ac12: 68f8 ldr r0, [r7, #12]
800ac14: f000 f814 bl 800ac40 <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
800ac18: 2204 movs r2, #4
800ac1a: 4908 ldr r1, [pc, #32] @ (800ac3c <Get_SerialNum+0x54>)
800ac1c: 68b8 ldr r0, [r7, #8]
800ac1e: f000 f80f bl 800ac40 <IntToUnicode>
}
}
800ac22: bf00 nop
800ac24: 3710 adds r7, #16
800ac26: 46bd mov sp, r7
800ac28: bd80 pop {r7, pc}
800ac2a: bf00 nop
800ac2c: 1ffff7e8 .word 0x1ffff7e8
800ac30: 1ffff7ec .word 0x1ffff7ec
800ac34: 1ffff7f0 .word 0x1ffff7f0
800ac38: 20000166 .word 0x20000166
800ac3c: 20000176 .word 0x20000176
0800ac40 <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
800ac40: b480 push {r7}
800ac42: b087 sub sp, #28
800ac44: af00 add r7, sp, #0
800ac46: 60f8 str r0, [r7, #12]
800ac48: 60b9 str r1, [r7, #8]
800ac4a: 4613 mov r3, r2
800ac4c: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
800ac4e: 2300 movs r3, #0
800ac50: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
800ac52: 2300 movs r3, #0
800ac54: 75fb strb r3, [r7, #23]
800ac56: e027 b.n 800aca8 <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
800ac58: 68fb ldr r3, [r7, #12]
800ac5a: 0f1b lsrs r3, r3, #28
800ac5c: 2b09 cmp r3, #9
800ac5e: d80b bhi.n 800ac78 <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
800ac60: 68fb ldr r3, [r7, #12]
800ac62: 0f1b lsrs r3, r3, #28
800ac64: b2da uxtb r2, r3
800ac66: 7dfb ldrb r3, [r7, #23]
800ac68: 005b lsls r3, r3, #1
800ac6a: 4619 mov r1, r3
800ac6c: 68bb ldr r3, [r7, #8]
800ac6e: 440b add r3, r1
800ac70: 3230 adds r2, #48 @ 0x30
800ac72: b2d2 uxtb r2, r2
800ac74: 701a strb r2, [r3, #0]
800ac76: e00a b.n 800ac8e <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
800ac78: 68fb ldr r3, [r7, #12]
800ac7a: 0f1b lsrs r3, r3, #28
800ac7c: b2da uxtb r2, r3
800ac7e: 7dfb ldrb r3, [r7, #23]
800ac80: 005b lsls r3, r3, #1
800ac82: 4619 mov r1, r3
800ac84: 68bb ldr r3, [r7, #8]
800ac86: 440b add r3, r1
800ac88: 3237 adds r2, #55 @ 0x37
800ac8a: b2d2 uxtb r2, r2
800ac8c: 701a strb r2, [r3, #0]
}
value = value << 4;
800ac8e: 68fb ldr r3, [r7, #12]
800ac90: 011b lsls r3, r3, #4
800ac92: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
800ac94: 7dfb ldrb r3, [r7, #23]
800ac96: 005b lsls r3, r3, #1
800ac98: 3301 adds r3, #1
800ac9a: 68ba ldr r2, [r7, #8]
800ac9c: 4413 add r3, r2
800ac9e: 2200 movs r2, #0
800aca0: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
800aca2: 7dfb ldrb r3, [r7, #23]
800aca4: 3301 adds r3, #1
800aca6: 75fb strb r3, [r7, #23]
800aca8: 7dfa ldrb r2, [r7, #23]
800acaa: 79fb ldrb r3, [r7, #7]
800acac: 429a cmp r2, r3
800acae: d3d3 bcc.n 800ac58 <IntToUnicode+0x18>
}
}
800acb0: bf00 nop
800acb2: bf00 nop
800acb4: 371c adds r7, #28
800acb6: 46bd mov sp, r7
800acb8: bc80 pop {r7}
800acba: 4770 bx lr
0800acbc <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
800acbc: b580 push {r7, lr}
800acbe: b084 sub sp, #16
800acc0: af00 add r7, sp, #0
800acc2: 6078 str r0, [r7, #4]
if(pcdHandle->Instance==USB)
800acc4: 687b ldr r3, [r7, #4]
800acc6: 681b ldr r3, [r3, #0]
800acc8: 4a0d ldr r2, [pc, #52] @ (800ad00 <HAL_PCD_MspInit+0x44>)
800acca: 4293 cmp r3, r2
800accc: d113 bne.n 800acf6 <HAL_PCD_MspInit+0x3a>
{
/* USER CODE BEGIN USB_MspInit 0 */
/* USER CODE END USB_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
800acce: 4b0d ldr r3, [pc, #52] @ (800ad04 <HAL_PCD_MspInit+0x48>)
800acd0: 69db ldr r3, [r3, #28]
800acd2: 4a0c ldr r2, [pc, #48] @ (800ad04 <HAL_PCD_MspInit+0x48>)
800acd4: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
800acd8: 61d3 str r3, [r2, #28]
800acda: 4b0a ldr r3, [pc, #40] @ (800ad04 <HAL_PCD_MspInit+0x48>)
800acdc: 69db ldr r3, [r3, #28]
800acde: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800ace2: 60fb str r3, [r7, #12]
800ace4: 68fb ldr r3, [r7, #12]
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
800ace6: 2200 movs r2, #0
800ace8: 2100 movs r1, #0
800acea: 2014 movs r0, #20
800acec: f7f7 ff0b bl 8002b06 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
800acf0: 2014 movs r0, #20
800acf2: f7f7 ff24 bl 8002b3e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
800acf6: bf00 nop
800acf8: 3710 adds r7, #16
800acfa: 46bd mov sp, r7
800acfc: bd80 pop {r7, pc}
800acfe: bf00 nop
800ad00: 40005c00 .word 0x40005c00
800ad04: 40021000 .word 0x40021000
0800ad08 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad08: b580 push {r7, lr}
800ad0a: b082 sub sp, #8
800ad0c: af00 add r7, sp, #0
800ad0e: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
800ad10: 687b ldr r3, [r7, #4]
800ad12: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800ad16: 687b ldr r3, [r7, #4]
800ad18: f503 7326 add.w r3, r3, #664 @ 0x298
800ad1c: 4619 mov r1, r3
800ad1e: 4610 mov r0, r2
800ad20: f7fe fd51 bl 80097c6 <USBD_LL_SetupStage>
}
800ad24: bf00 nop
800ad26: 3708 adds r7, #8
800ad28: 46bd mov sp, r7
800ad2a: bd80 pop {r7, pc}
0800ad2c <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad2c: b580 push {r7, lr}
800ad2e: b082 sub sp, #8
800ad30: af00 add r7, sp, #0
800ad32: 6078 str r0, [r7, #4]
800ad34: 460b mov r3, r1
800ad36: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
800ad38: 687b ldr r3, [r7, #4]
800ad3a: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
800ad3e: 78fa ldrb r2, [r7, #3]
800ad40: 6879 ldr r1, [r7, #4]
800ad42: 4613 mov r3, r2
800ad44: 009b lsls r3, r3, #2
800ad46: 4413 add r3, r2
800ad48: 00db lsls r3, r3, #3
800ad4a: 440b add r3, r1
800ad4c: f503 73b2 add.w r3, r3, #356 @ 0x164
800ad50: 681a ldr r2, [r3, #0]
800ad52: 78fb ldrb r3, [r7, #3]
800ad54: 4619 mov r1, r3
800ad56: f7fe fd83 bl 8009860 <USBD_LL_DataOutStage>
}
800ad5a: bf00 nop
800ad5c: 3708 adds r7, #8
800ad5e: 46bd mov sp, r7
800ad60: bd80 pop {r7, pc}
0800ad62 <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad62: b580 push {r7, lr}
800ad64: b082 sub sp, #8
800ad66: af00 add r7, sp, #0
800ad68: 6078 str r0, [r7, #4]
800ad6a: 460b mov r3, r1
800ad6c: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
800ad6e: 687b ldr r3, [r7, #4]
800ad70: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
800ad74: 78fa ldrb r2, [r7, #3]
800ad76: 6879 ldr r1, [r7, #4]
800ad78: 4613 mov r3, r2
800ad7a: 009b lsls r3, r3, #2
800ad7c: 4413 add r3, r2
800ad7e: 00db lsls r3, r3, #3
800ad80: 440b add r3, r1
800ad82: 3324 adds r3, #36 @ 0x24
800ad84: 681a ldr r2, [r3, #0]
800ad86: 78fb ldrb r3, [r7, #3]
800ad88: 4619 mov r1, r3
800ad8a: f7fe fdda bl 8009942 <USBD_LL_DataInStage>
}
800ad8e: bf00 nop
800ad90: 3708 adds r7, #8
800ad92: 46bd mov sp, r7
800ad94: bd80 pop {r7, pc}
0800ad96 <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ad96: b580 push {r7, lr}
800ad98: b082 sub sp, #8
800ad9a: af00 add r7, sp, #0
800ad9c: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
800ad9e: 687b ldr r3, [r7, #4]
800ada0: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ada4: 4618 mov r0, r3
800ada6: f7fe feea bl 8009b7e <USBD_LL_SOF>
}
800adaa: bf00 nop
800adac: 3708 adds r7, #8
800adae: 46bd mov sp, r7
800adb0: bd80 pop {r7, pc}
0800adb2 <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800adb2: b580 push {r7, lr}
800adb4: b084 sub sp, #16
800adb6: af00 add r7, sp, #0
800adb8: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
800adba: 2301 movs r3, #1
800adbc: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
800adbe: 687b ldr r3, [r7, #4]
800adc0: 799b ldrb r3, [r3, #6]
800adc2: 2b02 cmp r3, #2
800adc4: d001 beq.n 800adca <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
800adc6: f7f6 fd85 bl 80018d4 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
800adca: 687b ldr r3, [r7, #4]
800adcc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800add0: 7bfa ldrb r2, [r7, #15]
800add2: 4611 mov r1, r2
800add4: 4618 mov r0, r3
800add6: f7fe fe9a bl 8009b0e <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
800adda: 687b ldr r3, [r7, #4]
800addc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ade0: 4618 mov r0, r3
800ade2: f7fe fe53 bl 8009a8c <USBD_LL_Reset>
}
800ade6: bf00 nop
800ade8: 3710 adds r7, #16
800adea: 46bd mov sp, r7
800adec: bd80 pop {r7, pc}
...
0800adf0 <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800adf0: b580 push {r7, lr}
800adf2: b082 sub sp, #8
800adf4: af00 add r7, sp, #0
800adf6: 6078 str r0, [r7, #4]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
800adf8: 687b ldr r3, [r7, #4]
800adfa: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800adfe: 4618 mov r0, r3
800ae00: f7fe fe94 bl 8009b2c <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
800ae04: 687b ldr r3, [r7, #4]
800ae06: 7a9b ldrb r3, [r3, #10]
800ae08: 2b00 cmp r3, #0
800ae0a: d005 beq.n 800ae18 <HAL_PCD_SuspendCallback+0x28>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800ae0c: 4b04 ldr r3, [pc, #16] @ (800ae20 <HAL_PCD_SuspendCallback+0x30>)
800ae0e: 691b ldr r3, [r3, #16]
800ae10: 4a03 ldr r2, [pc, #12] @ (800ae20 <HAL_PCD_SuspendCallback+0x30>)
800ae12: f043 0306 orr.w r3, r3, #6
800ae16: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
800ae18: bf00 nop
800ae1a: 3708 adds r7, #8
800ae1c: 46bd mov sp, r7
800ae1e: bd80 pop {r7, pc}
800ae20: e000ed00 .word 0xe000ed00
0800ae24 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800ae24: b580 push {r7, lr}
800ae26: b082 sub sp, #8
800ae28: af00 add r7, sp, #0
800ae2a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
800ae2c: 687b ldr r3, [r7, #4]
800ae2e: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800ae32: 4618 mov r0, r3
800ae34: f7fe fe8e bl 8009b54 <USBD_LL_Resume>
}
800ae38: bf00 nop
800ae3a: 3708 adds r7, #8
800ae3c: 46bd mov sp, r7
800ae3e: bd80 pop {r7, pc}
0800ae40 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
800ae40: b580 push {r7, lr}
800ae42: b082 sub sp, #8
800ae44: af00 add r7, sp, #0
800ae46: 6078 str r0, [r7, #4]
/* Init USB Ip. */
/* Link the driver to the stack. */
hpcd_USB_FS.pData = pdev;
800ae48: 4a28 ldr r2, [pc, #160] @ (800aeec <USBD_LL_Init+0xac>)
800ae4a: 687b ldr r3, [r7, #4]
800ae4c: f8c2 32d4 str.w r3, [r2, #724] @ 0x2d4
pdev->pData = &hpcd_USB_FS;
800ae50: 687b ldr r3, [r7, #4]
800ae52: 4a26 ldr r2, [pc, #152] @ (800aeec <USBD_LL_Init+0xac>)
800ae54: f8c3 22c0 str.w r2, [r3, #704] @ 0x2c0
hpcd_USB_FS.Instance = USB;
800ae58: 4b24 ldr r3, [pc, #144] @ (800aeec <USBD_LL_Init+0xac>)
800ae5a: 4a25 ldr r2, [pc, #148] @ (800aef0 <USBD_LL_Init+0xb0>)
800ae5c: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
800ae5e: 4b23 ldr r3, [pc, #140] @ (800aeec <USBD_LL_Init+0xac>)
800ae60: 2208 movs r2, #8
800ae62: 711a strb r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
800ae64: 4b21 ldr r3, [pc, #132] @ (800aeec <USBD_LL_Init+0xac>)
800ae66: 2202 movs r2, #2
800ae68: 719a strb r2, [r3, #6]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
800ae6a: 4b20 ldr r3, [pc, #128] @ (800aeec <USBD_LL_Init+0xac>)
800ae6c: 2200 movs r2, #0
800ae6e: 729a strb r2, [r3, #10]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
800ae70: 4b1e ldr r3, [pc, #120] @ (800aeec <USBD_LL_Init+0xac>)
800ae72: 2200 movs r2, #0
800ae74: 72da strb r2, [r3, #11]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
800ae76: 4b1d ldr r3, [pc, #116] @ (800aeec <USBD_LL_Init+0xac>)
800ae78: 2200 movs r2, #0
800ae7a: 731a strb r2, [r3, #12]
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
800ae7c: 481b ldr r0, [pc, #108] @ (800aeec <USBD_LL_Init+0xac>)
800ae7e: f7f8 fc39 bl 80036f4 <HAL_PCD_Init>
800ae82: 4603 mov r3, r0
800ae84: 2b00 cmp r3, #0
800ae86: d001 beq.n 800ae8c <USBD_LL_Init+0x4c>
{
Error_Handler( );
800ae88: f7f6 fd24 bl 80018d4 <Error_Handler>
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
800ae8c: 687b ldr r3, [r7, #4]
800ae8e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800ae92: 2318 movs r3, #24
800ae94: 2200 movs r2, #0
800ae96: 2100 movs r1, #0
800ae98: f7fa f94a bl 8005130 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
800ae9c: 687b ldr r3, [r7, #4]
800ae9e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aea2: 2358 movs r3, #88 @ 0x58
800aea4: 2200 movs r2, #0
800aea6: 2180 movs r1, #128 @ 0x80
800aea8: f7fa f942 bl 8005130 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
800aeac: 687b ldr r3, [r7, #4]
800aeae: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aeb2: 23c0 movs r3, #192 @ 0xc0
800aeb4: 2200 movs r2, #0
800aeb6: 2181 movs r1, #129 @ 0x81
800aeb8: f7fa f93a bl 8005130 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
800aebc: 687b ldr r3, [r7, #4]
800aebe: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aec2: f44f 7388 mov.w r3, #272 @ 0x110
800aec6: 2200 movs r2, #0
800aec8: 2101 movs r1, #1
800aeca: f7fa f931 bl 8005130 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
800aece: 687b ldr r3, [r7, #4]
800aed0: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800aed4: f44f 7380 mov.w r3, #256 @ 0x100
800aed8: 2200 movs r2, #0
800aeda: 2182 movs r1, #130 @ 0x82
800aedc: f7fa f928 bl 8005130 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK;
800aee0: 2300 movs r3, #0
}
800aee2: 4618 mov r0, r3
800aee4: 3708 adds r7, #8
800aee6: 46bd mov sp, r7
800aee8: bd80 pop {r7, pc}
800aeea: bf00 nop
800aeec: 200011dc .word 0x200011dc
800aef0: 40005c00 .word 0x40005c00
0800aef4 <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
800aef4: b580 push {r7, lr}
800aef6: b084 sub sp, #16
800aef8: af00 add r7, sp, #0
800aefa: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
800aefc: 2300 movs r3, #0
800aefe: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800af00: 2300 movs r3, #0
800af02: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_Start(pdev->pData);
800af04: 687b ldr r3, [r7, #4]
800af06: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800af0a: 4618 mov r0, r3
800af0c: f7f8 fce8 bl 80038e0 <HAL_PCD_Start>
800af10: 4603 mov r3, r0
800af12: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800af14: 7bfb ldrb r3, [r7, #15]
800af16: 4618 mov r0, r3
800af18: f000 f94e bl 800b1b8 <USBD_Get_USB_Status>
800af1c: 4603 mov r3, r0
800af1e: 73bb strb r3, [r7, #14]
return usb_status;
800af20: 7bbb ldrb r3, [r7, #14]
}
800af22: 4618 mov r0, r3
800af24: 3710 adds r7, #16
800af26: 46bd mov sp, r7
800af28: bd80 pop {r7, pc}
0800af2a <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
800af2a: b580 push {r7, lr}
800af2c: b084 sub sp, #16
800af2e: af00 add r7, sp, #0
800af30: 6078 str r0, [r7, #4]
800af32: 4608 mov r0, r1
800af34: 4611 mov r1, r2
800af36: 461a mov r2, r3
800af38: 4603 mov r3, r0
800af3a: 70fb strb r3, [r7, #3]
800af3c: 460b mov r3, r1
800af3e: 70bb strb r3, [r7, #2]
800af40: 4613 mov r3, r2
800af42: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
800af44: 2300 movs r3, #0
800af46: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800af48: 2300 movs r3, #0
800af4a: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
800af4c: 687b ldr r3, [r7, #4]
800af4e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800af52: 78bb ldrb r3, [r7, #2]
800af54: 883a ldrh r2, [r7, #0]
800af56: 78f9 ldrb r1, [r7, #3]
800af58: f7f8 fe3c bl 8003bd4 <HAL_PCD_EP_Open>
800af5c: 4603 mov r3, r0
800af5e: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800af60: 7bfb ldrb r3, [r7, #15]
800af62: 4618 mov r0, r3
800af64: f000 f928 bl 800b1b8 <USBD_Get_USB_Status>
800af68: 4603 mov r3, r0
800af6a: 73bb strb r3, [r7, #14]
return usb_status;
800af6c: 7bbb ldrb r3, [r7, #14]
}
800af6e: 4618 mov r0, r3
800af70: 3710 adds r7, #16
800af72: 46bd mov sp, r7
800af74: bd80 pop {r7, pc}
0800af76 <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800af76: b580 push {r7, lr}
800af78: b084 sub sp, #16
800af7a: af00 add r7, sp, #0
800af7c: 6078 str r0, [r7, #4]
800af7e: 460b mov r3, r1
800af80: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800af82: 2300 movs r3, #0
800af84: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800af86: 2300 movs r3, #0
800af88: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
800af8a: 687b ldr r3, [r7, #4]
800af8c: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800af90: 78fa ldrb r2, [r7, #3]
800af92: 4611 mov r1, r2
800af94: 4618 mov r0, r3
800af96: f7f8 fe7a bl 8003c8e <HAL_PCD_EP_Close>
800af9a: 4603 mov r3, r0
800af9c: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800af9e: 7bfb ldrb r3, [r7, #15]
800afa0: 4618 mov r0, r3
800afa2: f000 f909 bl 800b1b8 <USBD_Get_USB_Status>
800afa6: 4603 mov r3, r0
800afa8: 73bb strb r3, [r7, #14]
return usb_status;
800afaa: 7bbb ldrb r3, [r7, #14]
}
800afac: 4618 mov r0, r3
800afae: 3710 adds r7, #16
800afb0: 46bd mov sp, r7
800afb2: bd80 pop {r7, pc}
0800afb4 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800afb4: b580 push {r7, lr}
800afb6: b084 sub sp, #16
800afb8: af00 add r7, sp, #0
800afba: 6078 str r0, [r7, #4]
800afbc: 460b mov r3, r1
800afbe: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800afc0: 2300 movs r3, #0
800afc2: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800afc4: 2300 movs r3, #0
800afc6: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
800afc8: 687b ldr r3, [r7, #4]
800afca: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800afce: 78fa ldrb r2, [r7, #3]
800afd0: 4611 mov r1, r2
800afd2: 4618 mov r0, r3
800afd4: f7f8 ff22 bl 8003e1c <HAL_PCD_EP_SetStall>
800afd8: 4603 mov r3, r0
800afda: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800afdc: 7bfb ldrb r3, [r7, #15]
800afde: 4618 mov r0, r3
800afe0: f000 f8ea bl 800b1b8 <USBD_Get_USB_Status>
800afe4: 4603 mov r3, r0
800afe6: 73bb strb r3, [r7, #14]
return usb_status;
800afe8: 7bbb ldrb r3, [r7, #14]
}
800afea: 4618 mov r0, r3
800afec: 3710 adds r7, #16
800afee: 46bd mov sp, r7
800aff0: bd80 pop {r7, pc}
0800aff2 <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800aff2: b580 push {r7, lr}
800aff4: b084 sub sp, #16
800aff6: af00 add r7, sp, #0
800aff8: 6078 str r0, [r7, #4]
800affa: 460b mov r3, r1
800affc: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800affe: 2300 movs r3, #0
800b000: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800b002: 2300 movs r3, #0
800b004: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
800b006: 687b ldr r3, [r7, #4]
800b008: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b00c: 78fa ldrb r2, [r7, #3]
800b00e: 4611 mov r1, r2
800b010: 4618 mov r0, r3
800b012: f7f8 ff63 bl 8003edc <HAL_PCD_EP_ClrStall>
800b016: 4603 mov r3, r0
800b018: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800b01a: 7bfb ldrb r3, [r7, #15]
800b01c: 4618 mov r0, r3
800b01e: f000 f8cb bl 800b1b8 <USBD_Get_USB_Status>
800b022: 4603 mov r3, r0
800b024: 73bb strb r3, [r7, #14]
return usb_status;
800b026: 7bbb ldrb r3, [r7, #14]
}
800b028: 4618 mov r0, r3
800b02a: 3710 adds r7, #16
800b02c: 46bd mov sp, r7
800b02e: bd80 pop {r7, pc}
0800b030 <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b030: b480 push {r7}
800b032: b085 sub sp, #20
800b034: af00 add r7, sp, #0
800b036: 6078 str r0, [r7, #4]
800b038: 460b mov r3, r1
800b03a: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
800b03c: 687b ldr r3, [r7, #4]
800b03e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b042: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
800b044: f997 3003 ldrsb.w r3, [r7, #3]
800b048: 2b00 cmp r3, #0
800b04a: da0b bge.n 800b064 <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
800b04c: 78fb ldrb r3, [r7, #3]
800b04e: f003 027f and.w r2, r3, #127 @ 0x7f
800b052: 68f9 ldr r1, [r7, #12]
800b054: 4613 mov r3, r2
800b056: 009b lsls r3, r3, #2
800b058: 4413 add r3, r2
800b05a: 00db lsls r3, r3, #3
800b05c: 440b add r3, r1
800b05e: 3312 adds r3, #18
800b060: 781b ldrb r3, [r3, #0]
800b062: e00b b.n 800b07c <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
800b064: 78fb ldrb r3, [r7, #3]
800b066: f003 027f and.w r2, r3, #127 @ 0x7f
800b06a: 68f9 ldr r1, [r7, #12]
800b06c: 4613 mov r3, r2
800b06e: 009b lsls r3, r3, #2
800b070: 4413 add r3, r2
800b072: 00db lsls r3, r3, #3
800b074: 440b add r3, r1
800b076: f503 73a9 add.w r3, r3, #338 @ 0x152
800b07a: 781b ldrb r3, [r3, #0]
}
}
800b07c: 4618 mov r0, r3
800b07e: 3714 adds r7, #20
800b080: 46bd mov sp, r7
800b082: bc80 pop {r7}
800b084: 4770 bx lr
0800b086 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
800b086: b580 push {r7, lr}
800b088: b084 sub sp, #16
800b08a: af00 add r7, sp, #0
800b08c: 6078 str r0, [r7, #4]
800b08e: 460b mov r3, r1
800b090: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800b092: 2300 movs r3, #0
800b094: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800b096: 2300 movs r3, #0
800b098: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
800b09a: 687b ldr r3, [r7, #4]
800b09c: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b0a0: 78fa ldrb r2, [r7, #3]
800b0a2: 4611 mov r1, r2
800b0a4: 4618 mov r0, r3
800b0a6: f7f8 fd71 bl 8003b8c <HAL_PCD_SetAddress>
800b0aa: 4603 mov r3, r0
800b0ac: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800b0ae: 7bfb ldrb r3, [r7, #15]
800b0b0: 4618 mov r0, r3
800b0b2: f000 f881 bl 800b1b8 <USBD_Get_USB_Status>
800b0b6: 4603 mov r3, r0
800b0b8: 73bb strb r3, [r7, #14]
return usb_status;
800b0ba: 7bbb ldrb r3, [r7, #14]
}
800b0bc: 4618 mov r0, r3
800b0be: 3710 adds r7, #16
800b0c0: 46bd mov sp, r7
800b0c2: bd80 pop {r7, pc}
0800b0c4 <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800b0c4: b580 push {r7, lr}
800b0c6: b086 sub sp, #24
800b0c8: af00 add r7, sp, #0
800b0ca: 60f8 str r0, [r7, #12]
800b0cc: 607a str r2, [r7, #4]
800b0ce: 461a mov r2, r3
800b0d0: 460b mov r3, r1
800b0d2: 72fb strb r3, [r7, #11]
800b0d4: 4613 mov r3, r2
800b0d6: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800b0d8: 2300 movs r3, #0
800b0da: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
800b0dc: 2300 movs r3, #0
800b0de: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
800b0e0: 68fb ldr r3, [r7, #12]
800b0e2: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800b0e6: 893b ldrh r3, [r7, #8]
800b0e8: 7af9 ldrb r1, [r7, #11]
800b0ea: 687a ldr r2, [r7, #4]
800b0ec: f7f8 fe5f bl 8003dae <HAL_PCD_EP_Transmit>
800b0f0: 4603 mov r3, r0
800b0f2: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800b0f4: 7dfb ldrb r3, [r7, #23]
800b0f6: 4618 mov r0, r3
800b0f8: f000 f85e bl 800b1b8 <USBD_Get_USB_Status>
800b0fc: 4603 mov r3, r0
800b0fe: 75bb strb r3, [r7, #22]
return usb_status;
800b100: 7dbb ldrb r3, [r7, #22]
}
800b102: 4618 mov r0, r3
800b104: 3718 adds r7, #24
800b106: 46bd mov sp, r7
800b108: bd80 pop {r7, pc}
0800b10a <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800b10a: b580 push {r7, lr}
800b10c: b086 sub sp, #24
800b10e: af00 add r7, sp, #0
800b110: 60f8 str r0, [r7, #12]
800b112: 607a str r2, [r7, #4]
800b114: 461a mov r2, r3
800b116: 460b mov r3, r1
800b118: 72fb strb r3, [r7, #11]
800b11a: 4613 mov r3, r2
800b11c: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800b11e: 2300 movs r3, #0
800b120: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
800b122: 2300 movs r3, #0
800b124: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
800b126: 68fb ldr r3, [r7, #12]
800b128: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800b12c: 893b ldrh r3, [r7, #8]
800b12e: 7af9 ldrb r1, [r7, #11]
800b130: 687a ldr r2, [r7, #4]
800b132: f7f8 fdf4 bl 8003d1e <HAL_PCD_EP_Receive>
800b136: 4603 mov r3, r0
800b138: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800b13a: 7dfb ldrb r3, [r7, #23]
800b13c: 4618 mov r0, r3
800b13e: f000 f83b bl 800b1b8 <USBD_Get_USB_Status>
800b142: 4603 mov r3, r0
800b144: 75bb strb r3, [r7, #22]
return usb_status;
800b146: 7dbb ldrb r3, [r7, #22]
}
800b148: 4618 mov r0, r3
800b14a: 3718 adds r7, #24
800b14c: 46bd mov sp, r7
800b14e: bd80 pop {r7, pc}
0800b150 <USBD_LL_GetRxDataSize>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Received Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800b150: b580 push {r7, lr}
800b152: b082 sub sp, #8
800b154: af00 add r7, sp, #0
800b156: 6078 str r0, [r7, #4]
800b158: 460b mov r3, r1
800b15a: 70fb strb r3, [r7, #3]
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
800b15c: 687b ldr r3, [r7, #4]
800b15e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800b162: 78fa ldrb r2, [r7, #3]
800b164: 4611 mov r1, r2
800b166: 4618 mov r0, r3
800b168: f7f8 fe0a bl 8003d80 <HAL_PCD_EP_GetRxCount>
800b16c: 4603 mov r3, r0
}
800b16e: 4618 mov r0, r3
800b170: 3708 adds r7, #8
800b172: 46bd mov sp, r7
800b174: bd80 pop {r7, pc}
...
0800b178 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
800b178: b480 push {r7}
800b17a: b083 sub sp, #12
800b17c: af00 add r7, sp, #0
800b17e: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
return mem;
800b180: 4b02 ldr r3, [pc, #8] @ (800b18c <USBD_static_malloc+0x14>)
}
800b182: 4618 mov r0, r3
800b184: 370c adds r7, #12
800b186: 46bd mov sp, r7
800b188: bc80 pop {r7}
800b18a: 4770 bx lr
800b18c: 200014b4 .word 0x200014b4
0800b190 <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
800b190: b480 push {r7}
800b192: b083 sub sp, #12
800b194: af00 add r7, sp, #0
800b196: 6078 str r0, [r7, #4]
}
800b198: bf00 nop
800b19a: 370c adds r7, #12
800b19c: 46bd mov sp, r7
800b19e: bc80 pop {r7}
800b1a0: 4770 bx lr
0800b1a2 <HAL_PCDEx_SetConnectionState>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800b1a2: b480 push {r7}
800b1a4: b083 sub sp, #12
800b1a6: af00 add r7, sp, #0
800b1a8: 6078 str r0, [r7, #4]
800b1aa: 460b mov r3, r1
800b1ac: 70fb strb r3, [r7, #3]
{
/* Configure High connection state. */
}
/* USER CODE END 6 */
}
800b1ae: bf00 nop
800b1b0: 370c adds r7, #12
800b1b2: 46bd mov sp, r7
800b1b4: bc80 pop {r7}
800b1b6: 4770 bx lr
0800b1b8 <USBD_Get_USB_Status>:
* @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
800b1b8: b480 push {r7}
800b1ba: b085 sub sp, #20
800b1bc: af00 add r7, sp, #0
800b1be: 4603 mov r3, r0
800b1c0: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef usb_status = USBD_OK;
800b1c2: 2300 movs r3, #0
800b1c4: 73fb strb r3, [r7, #15]
switch (hal_status)
800b1c6: 79fb ldrb r3, [r7, #7]
800b1c8: 2b03 cmp r3, #3
800b1ca: d817 bhi.n 800b1fc <USBD_Get_USB_Status+0x44>
800b1cc: a201 add r2, pc, #4 @ (adr r2, 800b1d4 <USBD_Get_USB_Status+0x1c>)
800b1ce: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b1d2: bf00 nop
800b1d4: 0800b1e5 .word 0x0800b1e5
800b1d8: 0800b1eb .word 0x0800b1eb
800b1dc: 0800b1f1 .word 0x0800b1f1
800b1e0: 0800b1f7 .word 0x0800b1f7
{
case HAL_OK :
usb_status = USBD_OK;
800b1e4: 2300 movs r3, #0
800b1e6: 73fb strb r3, [r7, #15]
break;
800b1e8: e00b b.n 800b202 <USBD_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBD_FAIL;
800b1ea: 2302 movs r3, #2
800b1ec: 73fb strb r3, [r7, #15]
break;
800b1ee: e008 b.n 800b202 <USBD_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBD_BUSY;
800b1f0: 2301 movs r3, #1
800b1f2: 73fb strb r3, [r7, #15]
break;
800b1f4: e005 b.n 800b202 <USBD_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800b1f6: 2302 movs r3, #2
800b1f8: 73fb strb r3, [r7, #15]
break;
800b1fa: e002 b.n 800b202 <USBD_Get_USB_Status+0x4a>
default :
usb_status = USBD_FAIL;
800b1fc: 2302 movs r3, #2
800b1fe: 73fb strb r3, [r7, #15]
break;
800b200: bf00 nop
}
return usb_status;
800b202: 7bfb ldrb r3, [r7, #15]
}
800b204: 4618 mov r0, r3
800b206: 3714 adds r7, #20
800b208: 46bd mov sp, r7
800b20a: bc80 pop {r7}
800b20c: 4770 bx lr
800b20e: bf00 nop
0800b210 <siprintf>:
800b210: b40e push {r1, r2, r3}
800b212: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
800b216: b510 push {r4, lr}
800b218: 2400 movs r4, #0
800b21a: b09d sub sp, #116 @ 0x74
800b21c: ab1f add r3, sp, #124 @ 0x7c
800b21e: 9002 str r0, [sp, #8]
800b220: 9006 str r0, [sp, #24]
800b222: 9107 str r1, [sp, #28]
800b224: 9104 str r1, [sp, #16]
800b226: 4809 ldr r0, [pc, #36] @ (800b24c <siprintf+0x3c>)
800b228: 4909 ldr r1, [pc, #36] @ (800b250 <siprintf+0x40>)
800b22a: f853 2b04 ldr.w r2, [r3], #4
800b22e: 9105 str r1, [sp, #20]
800b230: 6800 ldr r0, [r0, #0]
800b232: a902 add r1, sp, #8
800b234: 9301 str r3, [sp, #4]
800b236: 941b str r4, [sp, #108] @ 0x6c
800b238: f000 f992 bl 800b560 <_svfiprintf_r>
800b23c: 9b02 ldr r3, [sp, #8]
800b23e: 701c strb r4, [r3, #0]
800b240: b01d add sp, #116 @ 0x74
800b242: e8bd 4010 ldmia.w sp!, {r4, lr}
800b246: b003 add sp, #12
800b248: 4770 bx lr
800b24a: bf00 nop
800b24c: 20000180 .word 0x20000180
800b250: ffff0208 .word 0xffff0208
0800b254 <memset>:
800b254: 4603 mov r3, r0
800b256: 4402 add r2, r0
800b258: 4293 cmp r3, r2
800b25a: d100 bne.n 800b25e <memset+0xa>
800b25c: 4770 bx lr
800b25e: f803 1b01 strb.w r1, [r3], #1
800b262: e7f9 b.n 800b258 <memset+0x4>
0800b264 <__errno>:
800b264: 4b01 ldr r3, [pc, #4] @ (800b26c <__errno+0x8>)
800b266: 6818 ldr r0, [r3, #0]
800b268: 4770 bx lr
800b26a: bf00 nop
800b26c: 20000180 .word 0x20000180
0800b270 <__libc_init_array>:
800b270: b570 push {r4, r5, r6, lr}
800b272: 2600 movs r6, #0
800b274: 4d0c ldr r5, [pc, #48] @ (800b2a8 <__libc_init_array+0x38>)
800b276: 4c0d ldr r4, [pc, #52] @ (800b2ac <__libc_init_array+0x3c>)
800b278: 1b64 subs r4, r4, r5
800b27a: 10a4 asrs r4, r4, #2
800b27c: 42a6 cmp r6, r4
800b27e: d109 bne.n 800b294 <__libc_init_array+0x24>
800b280: f000 fc76 bl 800bb70 <_init>
800b284: 2600 movs r6, #0
800b286: 4d0a ldr r5, [pc, #40] @ (800b2b0 <__libc_init_array+0x40>)
800b288: 4c0a ldr r4, [pc, #40] @ (800b2b4 <__libc_init_array+0x44>)
800b28a: 1b64 subs r4, r4, r5
800b28c: 10a4 asrs r4, r4, #2
800b28e: 42a6 cmp r6, r4
800b290: d105 bne.n 800b29e <__libc_init_array+0x2e>
800b292: bd70 pop {r4, r5, r6, pc}
800b294: f855 3b04 ldr.w r3, [r5], #4
800b298: 4798 blx r3
800b29a: 3601 adds r6, #1
800b29c: e7ee b.n 800b27c <__libc_init_array+0xc>
800b29e: f855 3b04 ldr.w r3, [r5], #4
800b2a2: 4798 blx r3
800b2a4: 3601 adds r6, #1
800b2a6: e7f2 b.n 800b28e <__libc_init_array+0x1e>
800b2a8: 0800be50 .word 0x0800be50
800b2ac: 0800be50 .word 0x0800be50
800b2b0: 0800be50 .word 0x0800be50
800b2b4: 0800be54 .word 0x0800be54
0800b2b8 <__retarget_lock_acquire_recursive>:
800b2b8: 4770 bx lr
0800b2ba <__retarget_lock_release_recursive>:
800b2ba: 4770 bx lr
0800b2bc <_free_r>:
800b2bc: b538 push {r3, r4, r5, lr}
800b2be: 4605 mov r5, r0
800b2c0: 2900 cmp r1, #0
800b2c2: d040 beq.n 800b346 <_free_r+0x8a>
800b2c4: f851 3c04 ldr.w r3, [r1, #-4]
800b2c8: 1f0c subs r4, r1, #4
800b2ca: 2b00 cmp r3, #0
800b2cc: bfb8 it lt
800b2ce: 18e4 addlt r4, r4, r3
800b2d0: f000 f8de bl 800b490 <__malloc_lock>
800b2d4: 4a1c ldr r2, [pc, #112] @ (800b348 <_free_r+0x8c>)
800b2d6: 6813 ldr r3, [r2, #0]
800b2d8: b933 cbnz r3, 800b2e8 <_free_r+0x2c>
800b2da: 6063 str r3, [r4, #4]
800b2dc: 6014 str r4, [r2, #0]
800b2de: 4628 mov r0, r5
800b2e0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
800b2e4: f000 b8da b.w 800b49c <__malloc_unlock>
800b2e8: 42a3 cmp r3, r4
800b2ea: d908 bls.n 800b2fe <_free_r+0x42>
800b2ec: 6820 ldr r0, [r4, #0]
800b2ee: 1821 adds r1, r4, r0
800b2f0: 428b cmp r3, r1
800b2f2: bf01 itttt eq
800b2f4: 6819 ldreq r1, [r3, #0]
800b2f6: 685b ldreq r3, [r3, #4]
800b2f8: 1809 addeq r1, r1, r0
800b2fa: 6021 streq r1, [r4, #0]
800b2fc: e7ed b.n 800b2da <_free_r+0x1e>
800b2fe: 461a mov r2, r3
800b300: 685b ldr r3, [r3, #4]
800b302: b10b cbz r3, 800b308 <_free_r+0x4c>
800b304: 42a3 cmp r3, r4
800b306: d9fa bls.n 800b2fe <_free_r+0x42>
800b308: 6811 ldr r1, [r2, #0]
800b30a: 1850 adds r0, r2, r1
800b30c: 42a0 cmp r0, r4
800b30e: d10b bne.n 800b328 <_free_r+0x6c>
800b310: 6820 ldr r0, [r4, #0]
800b312: 4401 add r1, r0
800b314: 1850 adds r0, r2, r1
800b316: 4283 cmp r3, r0
800b318: 6011 str r1, [r2, #0]
800b31a: d1e0 bne.n 800b2de <_free_r+0x22>
800b31c: 6818 ldr r0, [r3, #0]
800b31e: 685b ldr r3, [r3, #4]
800b320: 4408 add r0, r1
800b322: 6010 str r0, [r2, #0]
800b324: 6053 str r3, [r2, #4]
800b326: e7da b.n 800b2de <_free_r+0x22>
800b328: d902 bls.n 800b330 <_free_r+0x74>
800b32a: 230c movs r3, #12
800b32c: 602b str r3, [r5, #0]
800b32e: e7d6 b.n 800b2de <_free_r+0x22>
800b330: 6820 ldr r0, [r4, #0]
800b332: 1821 adds r1, r4, r0
800b334: 428b cmp r3, r1
800b336: bf01 itttt eq
800b338: 6819 ldreq r1, [r3, #0]
800b33a: 685b ldreq r3, [r3, #4]
800b33c: 1809 addeq r1, r1, r0
800b33e: 6021 streq r1, [r4, #0]
800b340: 6063 str r3, [r4, #4]
800b342: 6054 str r4, [r2, #4]
800b344: e7cb b.n 800b2de <_free_r+0x22>
800b346: bd38 pop {r3, r4, r5, pc}
800b348: 20001818 .word 0x20001818
0800b34c <sbrk_aligned>:
800b34c: b570 push {r4, r5, r6, lr}
800b34e: 4e0f ldr r6, [pc, #60] @ (800b38c <sbrk_aligned+0x40>)
800b350: 460c mov r4, r1
800b352: 6831 ldr r1, [r6, #0]
800b354: 4605 mov r5, r0
800b356: b911 cbnz r1, 800b35e <sbrk_aligned+0x12>
800b358: f000 fba8 bl 800baac <_sbrk_r>
800b35c: 6030 str r0, [r6, #0]
800b35e: 4621 mov r1, r4
800b360: 4628 mov r0, r5
800b362: f000 fba3 bl 800baac <_sbrk_r>
800b366: 1c43 adds r3, r0, #1
800b368: d103 bne.n 800b372 <sbrk_aligned+0x26>
800b36a: f04f 34ff mov.w r4, #4294967295
800b36e: 4620 mov r0, r4
800b370: bd70 pop {r4, r5, r6, pc}
800b372: 1cc4 adds r4, r0, #3
800b374: f024 0403 bic.w r4, r4, #3
800b378: 42a0 cmp r0, r4
800b37a: d0f8 beq.n 800b36e <sbrk_aligned+0x22>
800b37c: 1a21 subs r1, r4, r0
800b37e: 4628 mov r0, r5
800b380: f000 fb94 bl 800baac <_sbrk_r>
800b384: 3001 adds r0, #1
800b386: d1f2 bne.n 800b36e <sbrk_aligned+0x22>
800b388: e7ef b.n 800b36a <sbrk_aligned+0x1e>
800b38a: bf00 nop
800b38c: 20001814 .word 0x20001814
0800b390 <_malloc_r>:
800b390: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800b394: 1ccd adds r5, r1, #3
800b396: f025 0503 bic.w r5, r5, #3
800b39a: 3508 adds r5, #8
800b39c: 2d0c cmp r5, #12
800b39e: bf38 it cc
800b3a0: 250c movcc r5, #12
800b3a2: 2d00 cmp r5, #0
800b3a4: 4606 mov r6, r0
800b3a6: db01 blt.n 800b3ac <_malloc_r+0x1c>
800b3a8: 42a9 cmp r1, r5
800b3aa: d904 bls.n 800b3b6 <_malloc_r+0x26>
800b3ac: 230c movs r3, #12
800b3ae: 6033 str r3, [r6, #0]
800b3b0: 2000 movs r0, #0
800b3b2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800b3b6: f8df 80d4 ldr.w r8, [pc, #212] @ 800b48c <_malloc_r+0xfc>
800b3ba: f000 f869 bl 800b490 <__malloc_lock>
800b3be: f8d8 3000 ldr.w r3, [r8]
800b3c2: 461c mov r4, r3
800b3c4: bb44 cbnz r4, 800b418 <_malloc_r+0x88>
800b3c6: 4629 mov r1, r5
800b3c8: 4630 mov r0, r6
800b3ca: f7ff ffbf bl 800b34c <sbrk_aligned>
800b3ce: 1c43 adds r3, r0, #1
800b3d0: 4604 mov r4, r0
800b3d2: d158 bne.n 800b486 <_malloc_r+0xf6>
800b3d4: f8d8 4000 ldr.w r4, [r8]
800b3d8: 4627 mov r7, r4
800b3da: 2f00 cmp r7, #0
800b3dc: d143 bne.n 800b466 <_malloc_r+0xd6>
800b3de: 2c00 cmp r4, #0
800b3e0: d04b beq.n 800b47a <_malloc_r+0xea>
800b3e2: 6823 ldr r3, [r4, #0]
800b3e4: 4639 mov r1, r7
800b3e6: 4630 mov r0, r6
800b3e8: eb04 0903 add.w r9, r4, r3
800b3ec: f000 fb5e bl 800baac <_sbrk_r>
800b3f0: 4581 cmp r9, r0
800b3f2: d142 bne.n 800b47a <_malloc_r+0xea>
800b3f4: 6821 ldr r1, [r4, #0]
800b3f6: 4630 mov r0, r6
800b3f8: 1a6d subs r5, r5, r1
800b3fa: 4629 mov r1, r5
800b3fc: f7ff ffa6 bl 800b34c <sbrk_aligned>
800b400: 3001 adds r0, #1
800b402: d03a beq.n 800b47a <_malloc_r+0xea>
800b404: 6823 ldr r3, [r4, #0]
800b406: 442b add r3, r5
800b408: 6023 str r3, [r4, #0]
800b40a: f8d8 3000 ldr.w r3, [r8]
800b40e: 685a ldr r2, [r3, #4]
800b410: bb62 cbnz r2, 800b46c <_malloc_r+0xdc>
800b412: f8c8 7000 str.w r7, [r8]
800b416: e00f b.n 800b438 <_malloc_r+0xa8>
800b418: 6822 ldr r2, [r4, #0]
800b41a: 1b52 subs r2, r2, r5
800b41c: d420 bmi.n 800b460 <_malloc_r+0xd0>
800b41e: 2a0b cmp r2, #11
800b420: d917 bls.n 800b452 <_malloc_r+0xc2>
800b422: 1961 adds r1, r4, r5
800b424: 42a3 cmp r3, r4
800b426: 6025 str r5, [r4, #0]
800b428: bf18 it ne
800b42a: 6059 strne r1, [r3, #4]
800b42c: 6863 ldr r3, [r4, #4]
800b42e: bf08 it eq
800b430: f8c8 1000 streq.w r1, [r8]
800b434: 5162 str r2, [r4, r5]
800b436: 604b str r3, [r1, #4]
800b438: 4630 mov r0, r6
800b43a: f000 f82f bl 800b49c <__malloc_unlock>
800b43e: f104 000b add.w r0, r4, #11
800b442: 1d23 adds r3, r4, #4
800b444: f020 0007 bic.w r0, r0, #7
800b448: 1ac2 subs r2, r0, r3
800b44a: bf1c itt ne
800b44c: 1a1b subne r3, r3, r0
800b44e: 50a3 strne r3, [r4, r2]
800b450: e7af b.n 800b3b2 <_malloc_r+0x22>
800b452: 6862 ldr r2, [r4, #4]
800b454: 42a3 cmp r3, r4
800b456: bf0c ite eq
800b458: f8c8 2000 streq.w r2, [r8]
800b45c: 605a strne r2, [r3, #4]
800b45e: e7eb b.n 800b438 <_malloc_r+0xa8>
800b460: 4623 mov r3, r4
800b462: 6864 ldr r4, [r4, #4]
800b464: e7ae b.n 800b3c4 <_malloc_r+0x34>
800b466: 463c mov r4, r7
800b468: 687f ldr r7, [r7, #4]
800b46a: e7b6 b.n 800b3da <_malloc_r+0x4a>
800b46c: 461a mov r2, r3
800b46e: 685b ldr r3, [r3, #4]
800b470: 42a3 cmp r3, r4
800b472: d1fb bne.n 800b46c <_malloc_r+0xdc>
800b474: 2300 movs r3, #0
800b476: 6053 str r3, [r2, #4]
800b478: e7de b.n 800b438 <_malloc_r+0xa8>
800b47a: 230c movs r3, #12
800b47c: 4630 mov r0, r6
800b47e: 6033 str r3, [r6, #0]
800b480: f000 f80c bl 800b49c <__malloc_unlock>
800b484: e794 b.n 800b3b0 <_malloc_r+0x20>
800b486: 6005 str r5, [r0, #0]
800b488: e7d6 b.n 800b438 <_malloc_r+0xa8>
800b48a: bf00 nop
800b48c: 20001818 .word 0x20001818
0800b490 <__malloc_lock>:
800b490: 4801 ldr r0, [pc, #4] @ (800b498 <__malloc_lock+0x8>)
800b492: f7ff bf11 b.w 800b2b8 <__retarget_lock_acquire_recursive>
800b496: bf00 nop
800b498: 20001810 .word 0x20001810
0800b49c <__malloc_unlock>:
800b49c: 4801 ldr r0, [pc, #4] @ (800b4a4 <__malloc_unlock+0x8>)
800b49e: f7ff bf0c b.w 800b2ba <__retarget_lock_release_recursive>
800b4a2: bf00 nop
800b4a4: 20001810 .word 0x20001810
0800b4a8 <__ssputs_r>:
800b4a8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800b4ac: 461f mov r7, r3
800b4ae: 688e ldr r6, [r1, #8]
800b4b0: 4682 mov sl, r0
800b4b2: 42be cmp r6, r7
800b4b4: 460c mov r4, r1
800b4b6: 4690 mov r8, r2
800b4b8: 680b ldr r3, [r1, #0]
800b4ba: d82d bhi.n 800b518 <__ssputs_r+0x70>
800b4bc: f9b1 200c ldrsh.w r2, [r1, #12]
800b4c0: f412 6f90 tst.w r2, #1152 @ 0x480
800b4c4: d026 beq.n 800b514 <__ssputs_r+0x6c>
800b4c6: 6965 ldr r5, [r4, #20]
800b4c8: 6909 ldr r1, [r1, #16]
800b4ca: eb05 0545 add.w r5, r5, r5, lsl #1
800b4ce: eba3 0901 sub.w r9, r3, r1
800b4d2: eb05 75d5 add.w r5, r5, r5, lsr #31
800b4d6: 1c7b adds r3, r7, #1
800b4d8: 444b add r3, r9
800b4da: 106d asrs r5, r5, #1
800b4dc: 429d cmp r5, r3
800b4de: bf38 it cc
800b4e0: 461d movcc r5, r3
800b4e2: 0553 lsls r3, r2, #21
800b4e4: d527 bpl.n 800b536 <__ssputs_r+0x8e>
800b4e6: 4629 mov r1, r5
800b4e8: f7ff ff52 bl 800b390 <_malloc_r>
800b4ec: 4606 mov r6, r0
800b4ee: b360 cbz r0, 800b54a <__ssputs_r+0xa2>
800b4f0: 464a mov r2, r9
800b4f2: 6921 ldr r1, [r4, #16]
800b4f4: f000 faf8 bl 800bae8 <memcpy>
800b4f8: 89a3 ldrh r3, [r4, #12]
800b4fa: f423 6390 bic.w r3, r3, #1152 @ 0x480
800b4fe: f043 0380 orr.w r3, r3, #128 @ 0x80
800b502: 81a3 strh r3, [r4, #12]
800b504: 6126 str r6, [r4, #16]
800b506: 444e add r6, r9
800b508: 6026 str r6, [r4, #0]
800b50a: 463e mov r6, r7
800b50c: 6165 str r5, [r4, #20]
800b50e: eba5 0509 sub.w r5, r5, r9
800b512: 60a5 str r5, [r4, #8]
800b514: 42be cmp r6, r7
800b516: d900 bls.n 800b51a <__ssputs_r+0x72>
800b518: 463e mov r6, r7
800b51a: 4632 mov r2, r6
800b51c: 4641 mov r1, r8
800b51e: 6820 ldr r0, [r4, #0]
800b520: f000 faaa bl 800ba78 <memmove>
800b524: 2000 movs r0, #0
800b526: 68a3 ldr r3, [r4, #8]
800b528: 1b9b subs r3, r3, r6
800b52a: 60a3 str r3, [r4, #8]
800b52c: 6823 ldr r3, [r4, #0]
800b52e: 4433 add r3, r6
800b530: 6023 str r3, [r4, #0]
800b532: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b536: 462a mov r2, r5
800b538: f000 fae4 bl 800bb04 <_realloc_r>
800b53c: 4606 mov r6, r0
800b53e: 2800 cmp r0, #0
800b540: d1e0 bne.n 800b504 <__ssputs_r+0x5c>
800b542: 4650 mov r0, sl
800b544: 6921 ldr r1, [r4, #16]
800b546: f7ff feb9 bl 800b2bc <_free_r>
800b54a: 230c movs r3, #12
800b54c: f8ca 3000 str.w r3, [sl]
800b550: 89a3 ldrh r3, [r4, #12]
800b552: f04f 30ff mov.w r0, #4294967295
800b556: f043 0340 orr.w r3, r3, #64 @ 0x40
800b55a: 81a3 strh r3, [r4, #12]
800b55c: e7e9 b.n 800b532 <__ssputs_r+0x8a>
...
0800b560 <_svfiprintf_r>:
800b560: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800b564: 4698 mov r8, r3
800b566: 898b ldrh r3, [r1, #12]
800b568: 4607 mov r7, r0
800b56a: 061b lsls r3, r3, #24
800b56c: 460d mov r5, r1
800b56e: 4614 mov r4, r2
800b570: b09d sub sp, #116 @ 0x74
800b572: d510 bpl.n 800b596 <_svfiprintf_r+0x36>
800b574: 690b ldr r3, [r1, #16]
800b576: b973 cbnz r3, 800b596 <_svfiprintf_r+0x36>
800b578: 2140 movs r1, #64 @ 0x40
800b57a: f7ff ff09 bl 800b390 <_malloc_r>
800b57e: 6028 str r0, [r5, #0]
800b580: 6128 str r0, [r5, #16]
800b582: b930 cbnz r0, 800b592 <_svfiprintf_r+0x32>
800b584: 230c movs r3, #12
800b586: 603b str r3, [r7, #0]
800b588: f04f 30ff mov.w r0, #4294967295
800b58c: b01d add sp, #116 @ 0x74
800b58e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800b592: 2340 movs r3, #64 @ 0x40
800b594: 616b str r3, [r5, #20]
800b596: 2300 movs r3, #0
800b598: 9309 str r3, [sp, #36] @ 0x24
800b59a: 2320 movs r3, #32
800b59c: f88d 3029 strb.w r3, [sp, #41] @ 0x29
800b5a0: 2330 movs r3, #48 @ 0x30
800b5a2: f04f 0901 mov.w r9, #1
800b5a6: f8cd 800c str.w r8, [sp, #12]
800b5aa: f8df 8198 ldr.w r8, [pc, #408] @ 800b744 <_svfiprintf_r+0x1e4>
800b5ae: f88d 302a strb.w r3, [sp, #42] @ 0x2a
800b5b2: 4623 mov r3, r4
800b5b4: 469a mov sl, r3
800b5b6: f813 2b01 ldrb.w r2, [r3], #1
800b5ba: b10a cbz r2, 800b5c0 <_svfiprintf_r+0x60>
800b5bc: 2a25 cmp r2, #37 @ 0x25
800b5be: d1f9 bne.n 800b5b4 <_svfiprintf_r+0x54>
800b5c0: ebba 0b04 subs.w fp, sl, r4
800b5c4: d00b beq.n 800b5de <_svfiprintf_r+0x7e>
800b5c6: 465b mov r3, fp
800b5c8: 4622 mov r2, r4
800b5ca: 4629 mov r1, r5
800b5cc: 4638 mov r0, r7
800b5ce: f7ff ff6b bl 800b4a8 <__ssputs_r>
800b5d2: 3001 adds r0, #1
800b5d4: f000 80a7 beq.w 800b726 <_svfiprintf_r+0x1c6>
800b5d8: 9a09 ldr r2, [sp, #36] @ 0x24
800b5da: 445a add r2, fp
800b5dc: 9209 str r2, [sp, #36] @ 0x24
800b5de: f89a 3000 ldrb.w r3, [sl]
800b5e2: 2b00 cmp r3, #0
800b5e4: f000 809f beq.w 800b726 <_svfiprintf_r+0x1c6>
800b5e8: 2300 movs r3, #0
800b5ea: f04f 32ff mov.w r2, #4294967295
800b5ee: e9cd 2305 strd r2, r3, [sp, #20]
800b5f2: f10a 0a01 add.w sl, sl, #1
800b5f6: 9304 str r3, [sp, #16]
800b5f8: 9307 str r3, [sp, #28]
800b5fa: f88d 3053 strb.w r3, [sp, #83] @ 0x53
800b5fe: 931a str r3, [sp, #104] @ 0x68
800b600: 4654 mov r4, sl
800b602: 2205 movs r2, #5
800b604: f814 1b01 ldrb.w r1, [r4], #1
800b608: 484e ldr r0, [pc, #312] @ (800b744 <_svfiprintf_r+0x1e4>)
800b60a: f000 fa5f bl 800bacc <memchr>
800b60e: 9a04 ldr r2, [sp, #16]
800b610: b9d8 cbnz r0, 800b64a <_svfiprintf_r+0xea>
800b612: 06d0 lsls r0, r2, #27
800b614: bf44 itt mi
800b616: 2320 movmi r3, #32
800b618: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800b61c: 0711 lsls r1, r2, #28
800b61e: bf44 itt mi
800b620: 232b movmi r3, #43 @ 0x2b
800b622: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800b626: f89a 3000 ldrb.w r3, [sl]
800b62a: 2b2a cmp r3, #42 @ 0x2a
800b62c: d015 beq.n 800b65a <_svfiprintf_r+0xfa>
800b62e: 4654 mov r4, sl
800b630: 2000 movs r0, #0
800b632: f04f 0c0a mov.w ip, #10
800b636: 9a07 ldr r2, [sp, #28]
800b638: 4621 mov r1, r4
800b63a: f811 3b01 ldrb.w r3, [r1], #1
800b63e: 3b30 subs r3, #48 @ 0x30
800b640: 2b09 cmp r3, #9
800b642: d94b bls.n 800b6dc <_svfiprintf_r+0x17c>
800b644: b1b0 cbz r0, 800b674 <_svfiprintf_r+0x114>
800b646: 9207 str r2, [sp, #28]
800b648: e014 b.n 800b674 <_svfiprintf_r+0x114>
800b64a: eba0 0308 sub.w r3, r0, r8
800b64e: fa09 f303 lsl.w r3, r9, r3
800b652: 4313 orrs r3, r2
800b654: 46a2 mov sl, r4
800b656: 9304 str r3, [sp, #16]
800b658: e7d2 b.n 800b600 <_svfiprintf_r+0xa0>
800b65a: 9b03 ldr r3, [sp, #12]
800b65c: 1d19 adds r1, r3, #4
800b65e: 681b ldr r3, [r3, #0]
800b660: 9103 str r1, [sp, #12]
800b662: 2b00 cmp r3, #0
800b664: bfbb ittet lt
800b666: 425b neglt r3, r3
800b668: f042 0202 orrlt.w r2, r2, #2
800b66c: 9307 strge r3, [sp, #28]
800b66e: 9307 strlt r3, [sp, #28]
800b670: bfb8 it lt
800b672: 9204 strlt r2, [sp, #16]
800b674: 7823 ldrb r3, [r4, #0]
800b676: 2b2e cmp r3, #46 @ 0x2e
800b678: d10a bne.n 800b690 <_svfiprintf_r+0x130>
800b67a: 7863 ldrb r3, [r4, #1]
800b67c: 2b2a cmp r3, #42 @ 0x2a
800b67e: d132 bne.n 800b6e6 <_svfiprintf_r+0x186>
800b680: 9b03 ldr r3, [sp, #12]
800b682: 3402 adds r4, #2
800b684: 1d1a adds r2, r3, #4
800b686: 681b ldr r3, [r3, #0]
800b688: 9203 str r2, [sp, #12]
800b68a: ea43 73e3 orr.w r3, r3, r3, asr #31
800b68e: 9305 str r3, [sp, #20]
800b690: f8df a0b4 ldr.w sl, [pc, #180] @ 800b748 <_svfiprintf_r+0x1e8>
800b694: 2203 movs r2, #3
800b696: 4650 mov r0, sl
800b698: 7821 ldrb r1, [r4, #0]
800b69a: f000 fa17 bl 800bacc <memchr>
800b69e: b138 cbz r0, 800b6b0 <_svfiprintf_r+0x150>
800b6a0: 2240 movs r2, #64 @ 0x40
800b6a2: 9b04 ldr r3, [sp, #16]
800b6a4: eba0 000a sub.w r0, r0, sl
800b6a8: 4082 lsls r2, r0
800b6aa: 4313 orrs r3, r2
800b6ac: 3401 adds r4, #1
800b6ae: 9304 str r3, [sp, #16]
800b6b0: f814 1b01 ldrb.w r1, [r4], #1
800b6b4: 2206 movs r2, #6
800b6b6: 4825 ldr r0, [pc, #148] @ (800b74c <_svfiprintf_r+0x1ec>)
800b6b8: f88d 1028 strb.w r1, [sp, #40] @ 0x28
800b6bc: f000 fa06 bl 800bacc <memchr>
800b6c0: 2800 cmp r0, #0
800b6c2: d036 beq.n 800b732 <_svfiprintf_r+0x1d2>
800b6c4: 4b22 ldr r3, [pc, #136] @ (800b750 <_svfiprintf_r+0x1f0>)
800b6c6: bb1b cbnz r3, 800b710 <_svfiprintf_r+0x1b0>
800b6c8: 9b03 ldr r3, [sp, #12]
800b6ca: 3307 adds r3, #7
800b6cc: f023 0307 bic.w r3, r3, #7
800b6d0: 3308 adds r3, #8
800b6d2: 9303 str r3, [sp, #12]
800b6d4: 9b09 ldr r3, [sp, #36] @ 0x24
800b6d6: 4433 add r3, r6
800b6d8: 9309 str r3, [sp, #36] @ 0x24
800b6da: e76a b.n 800b5b2 <_svfiprintf_r+0x52>
800b6dc: 460c mov r4, r1
800b6de: 2001 movs r0, #1
800b6e0: fb0c 3202 mla r2, ip, r2, r3
800b6e4: e7a8 b.n 800b638 <_svfiprintf_r+0xd8>
800b6e6: 2300 movs r3, #0
800b6e8: f04f 0c0a mov.w ip, #10
800b6ec: 4619 mov r1, r3
800b6ee: 3401 adds r4, #1
800b6f0: 9305 str r3, [sp, #20]
800b6f2: 4620 mov r0, r4
800b6f4: f810 2b01 ldrb.w r2, [r0], #1
800b6f8: 3a30 subs r2, #48 @ 0x30
800b6fa: 2a09 cmp r2, #9
800b6fc: d903 bls.n 800b706 <_svfiprintf_r+0x1a6>
800b6fe: 2b00 cmp r3, #0
800b700: d0c6 beq.n 800b690 <_svfiprintf_r+0x130>
800b702: 9105 str r1, [sp, #20]
800b704: e7c4 b.n 800b690 <_svfiprintf_r+0x130>
800b706: 4604 mov r4, r0
800b708: 2301 movs r3, #1
800b70a: fb0c 2101 mla r1, ip, r1, r2
800b70e: e7f0 b.n 800b6f2 <_svfiprintf_r+0x192>
800b710: ab03 add r3, sp, #12
800b712: 9300 str r3, [sp, #0]
800b714: 462a mov r2, r5
800b716: 4638 mov r0, r7
800b718: 4b0e ldr r3, [pc, #56] @ (800b754 <_svfiprintf_r+0x1f4>)
800b71a: a904 add r1, sp, #16
800b71c: f3af 8000 nop.w
800b720: 1c42 adds r2, r0, #1
800b722: 4606 mov r6, r0
800b724: d1d6 bne.n 800b6d4 <_svfiprintf_r+0x174>
800b726: 89ab ldrh r3, [r5, #12]
800b728: 065b lsls r3, r3, #25
800b72a: f53f af2d bmi.w 800b588 <_svfiprintf_r+0x28>
800b72e: 9809 ldr r0, [sp, #36] @ 0x24
800b730: e72c b.n 800b58c <_svfiprintf_r+0x2c>
800b732: ab03 add r3, sp, #12
800b734: 9300 str r3, [sp, #0]
800b736: 462a mov r2, r5
800b738: 4638 mov r0, r7
800b73a: 4b06 ldr r3, [pc, #24] @ (800b754 <_svfiprintf_r+0x1f4>)
800b73c: a904 add r1, sp, #16
800b73e: f000 f87d bl 800b83c <_printf_i>
800b742: e7ed b.n 800b720 <_svfiprintf_r+0x1c0>
800b744: 0800be12 .word 0x0800be12
800b748: 0800be18 .word 0x0800be18
800b74c: 0800be1c .word 0x0800be1c
800b750: 00000000 .word 0x00000000
800b754: 0800b4a9 .word 0x0800b4a9
0800b758 <_printf_common>:
800b758: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800b75c: 4616 mov r6, r2
800b75e: 4698 mov r8, r3
800b760: 688a ldr r2, [r1, #8]
800b762: 690b ldr r3, [r1, #16]
800b764: 4607 mov r7, r0
800b766: 4293 cmp r3, r2
800b768: bfb8 it lt
800b76a: 4613 movlt r3, r2
800b76c: 6033 str r3, [r6, #0]
800b76e: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
800b772: 460c mov r4, r1
800b774: f8dd 9020 ldr.w r9, [sp, #32]
800b778: b10a cbz r2, 800b77e <_printf_common+0x26>
800b77a: 3301 adds r3, #1
800b77c: 6033 str r3, [r6, #0]
800b77e: 6823 ldr r3, [r4, #0]
800b780: 0699 lsls r1, r3, #26
800b782: bf42 ittt mi
800b784: 6833 ldrmi r3, [r6, #0]
800b786: 3302 addmi r3, #2
800b788: 6033 strmi r3, [r6, #0]
800b78a: 6825 ldr r5, [r4, #0]
800b78c: f015 0506 ands.w r5, r5, #6
800b790: d106 bne.n 800b7a0 <_printf_common+0x48>
800b792: f104 0a19 add.w sl, r4, #25
800b796: 68e3 ldr r3, [r4, #12]
800b798: 6832 ldr r2, [r6, #0]
800b79a: 1a9b subs r3, r3, r2
800b79c: 42ab cmp r3, r5
800b79e: dc2b bgt.n 800b7f8 <_printf_common+0xa0>
800b7a0: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
800b7a4: 6822 ldr r2, [r4, #0]
800b7a6: 3b00 subs r3, #0
800b7a8: bf18 it ne
800b7aa: 2301 movne r3, #1
800b7ac: 0692 lsls r2, r2, #26
800b7ae: d430 bmi.n 800b812 <_printf_common+0xba>
800b7b0: 4641 mov r1, r8
800b7b2: 4638 mov r0, r7
800b7b4: f104 0243 add.w r2, r4, #67 @ 0x43
800b7b8: 47c8 blx r9
800b7ba: 3001 adds r0, #1
800b7bc: d023 beq.n 800b806 <_printf_common+0xae>
800b7be: 6823 ldr r3, [r4, #0]
800b7c0: 6922 ldr r2, [r4, #16]
800b7c2: f003 0306 and.w r3, r3, #6
800b7c6: 2b04 cmp r3, #4
800b7c8: bf14 ite ne
800b7ca: 2500 movne r5, #0
800b7cc: 6833 ldreq r3, [r6, #0]
800b7ce: f04f 0600 mov.w r6, #0
800b7d2: bf08 it eq
800b7d4: 68e5 ldreq r5, [r4, #12]
800b7d6: f104 041a add.w r4, r4, #26
800b7da: bf08 it eq
800b7dc: 1aed subeq r5, r5, r3
800b7de: f854 3c12 ldr.w r3, [r4, #-18]
800b7e2: bf08 it eq
800b7e4: ea25 75e5 biceq.w r5, r5, r5, asr #31
800b7e8: 4293 cmp r3, r2
800b7ea: bfc4 itt gt
800b7ec: 1a9b subgt r3, r3, r2
800b7ee: 18ed addgt r5, r5, r3
800b7f0: 42b5 cmp r5, r6
800b7f2: d11a bne.n 800b82a <_printf_common+0xd2>
800b7f4: 2000 movs r0, #0
800b7f6: e008 b.n 800b80a <_printf_common+0xb2>
800b7f8: 2301 movs r3, #1
800b7fa: 4652 mov r2, sl
800b7fc: 4641 mov r1, r8
800b7fe: 4638 mov r0, r7
800b800: 47c8 blx r9
800b802: 3001 adds r0, #1
800b804: d103 bne.n 800b80e <_printf_common+0xb6>
800b806: f04f 30ff mov.w r0, #4294967295
800b80a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b80e: 3501 adds r5, #1
800b810: e7c1 b.n 800b796 <_printf_common+0x3e>
800b812: 2030 movs r0, #48 @ 0x30
800b814: 18e1 adds r1, r4, r3
800b816: f881 0043 strb.w r0, [r1, #67] @ 0x43
800b81a: 1c5a adds r2, r3, #1
800b81c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
800b820: 4422 add r2, r4
800b822: 3302 adds r3, #2
800b824: f882 1043 strb.w r1, [r2, #67] @ 0x43
800b828: e7c2 b.n 800b7b0 <_printf_common+0x58>
800b82a: 2301 movs r3, #1
800b82c: 4622 mov r2, r4
800b82e: 4641 mov r1, r8
800b830: 4638 mov r0, r7
800b832: 47c8 blx r9
800b834: 3001 adds r0, #1
800b836: d0e6 beq.n 800b806 <_printf_common+0xae>
800b838: 3601 adds r6, #1
800b83a: e7d9 b.n 800b7f0 <_printf_common+0x98>
0800b83c <_printf_i>:
800b83c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
800b840: 7e0f ldrb r7, [r1, #24]
800b842: 4691 mov r9, r2
800b844: 2f78 cmp r7, #120 @ 0x78
800b846: 4680 mov r8, r0
800b848: 460c mov r4, r1
800b84a: 469a mov sl, r3
800b84c: 9e0c ldr r6, [sp, #48] @ 0x30
800b84e: f101 0243 add.w r2, r1, #67 @ 0x43
800b852: d807 bhi.n 800b864 <_printf_i+0x28>
800b854: 2f62 cmp r7, #98 @ 0x62
800b856: d80a bhi.n 800b86e <_printf_i+0x32>
800b858: 2f00 cmp r7, #0
800b85a: f000 80d1 beq.w 800ba00 <_printf_i+0x1c4>
800b85e: 2f58 cmp r7, #88 @ 0x58
800b860: f000 80b8 beq.w 800b9d4 <_printf_i+0x198>
800b864: f104 0642 add.w r6, r4, #66 @ 0x42
800b868: f884 7042 strb.w r7, [r4, #66] @ 0x42
800b86c: e03a b.n 800b8e4 <_printf_i+0xa8>
800b86e: f1a7 0363 sub.w r3, r7, #99 @ 0x63
800b872: 2b15 cmp r3, #21
800b874: d8f6 bhi.n 800b864 <_printf_i+0x28>
800b876: a101 add r1, pc, #4 @ (adr r1, 800b87c <_printf_i+0x40>)
800b878: f851 f023 ldr.w pc, [r1, r3, lsl #2]
800b87c: 0800b8d5 .word 0x0800b8d5
800b880: 0800b8e9 .word 0x0800b8e9
800b884: 0800b865 .word 0x0800b865
800b888: 0800b865 .word 0x0800b865
800b88c: 0800b865 .word 0x0800b865
800b890: 0800b865 .word 0x0800b865
800b894: 0800b8e9 .word 0x0800b8e9
800b898: 0800b865 .word 0x0800b865
800b89c: 0800b865 .word 0x0800b865
800b8a0: 0800b865 .word 0x0800b865
800b8a4: 0800b865 .word 0x0800b865
800b8a8: 0800b9e7 .word 0x0800b9e7
800b8ac: 0800b913 .word 0x0800b913
800b8b0: 0800b9a1 .word 0x0800b9a1
800b8b4: 0800b865 .word 0x0800b865
800b8b8: 0800b865 .word 0x0800b865
800b8bc: 0800ba09 .word 0x0800ba09
800b8c0: 0800b865 .word 0x0800b865
800b8c4: 0800b913 .word 0x0800b913
800b8c8: 0800b865 .word 0x0800b865
800b8cc: 0800b865 .word 0x0800b865
800b8d0: 0800b9a9 .word 0x0800b9a9
800b8d4: 6833 ldr r3, [r6, #0]
800b8d6: 1d1a adds r2, r3, #4
800b8d8: 681b ldr r3, [r3, #0]
800b8da: 6032 str r2, [r6, #0]
800b8dc: f104 0642 add.w r6, r4, #66 @ 0x42
800b8e0: f884 3042 strb.w r3, [r4, #66] @ 0x42
800b8e4: 2301 movs r3, #1
800b8e6: e09c b.n 800ba22 <_printf_i+0x1e6>
800b8e8: 6833 ldr r3, [r6, #0]
800b8ea: 6820 ldr r0, [r4, #0]
800b8ec: 1d19 adds r1, r3, #4
800b8ee: 6031 str r1, [r6, #0]
800b8f0: 0606 lsls r6, r0, #24
800b8f2: d501 bpl.n 800b8f8 <_printf_i+0xbc>
800b8f4: 681d ldr r5, [r3, #0]
800b8f6: e003 b.n 800b900 <_printf_i+0xc4>
800b8f8: 0645 lsls r5, r0, #25
800b8fa: d5fb bpl.n 800b8f4 <_printf_i+0xb8>
800b8fc: f9b3 5000 ldrsh.w r5, [r3]
800b900: 2d00 cmp r5, #0
800b902: da03 bge.n 800b90c <_printf_i+0xd0>
800b904: 232d movs r3, #45 @ 0x2d
800b906: 426d negs r5, r5
800b908: f884 3043 strb.w r3, [r4, #67] @ 0x43
800b90c: 230a movs r3, #10
800b90e: 4858 ldr r0, [pc, #352] @ (800ba70 <_printf_i+0x234>)
800b910: e011 b.n 800b936 <_printf_i+0xfa>
800b912: 6821 ldr r1, [r4, #0]
800b914: 6833 ldr r3, [r6, #0]
800b916: 0608 lsls r0, r1, #24
800b918: f853 5b04 ldr.w r5, [r3], #4
800b91c: d402 bmi.n 800b924 <_printf_i+0xe8>
800b91e: 0649 lsls r1, r1, #25
800b920: bf48 it mi
800b922: b2ad uxthmi r5, r5
800b924: 2f6f cmp r7, #111 @ 0x6f
800b926: 6033 str r3, [r6, #0]
800b928: bf14 ite ne
800b92a: 230a movne r3, #10
800b92c: 2308 moveq r3, #8
800b92e: 4850 ldr r0, [pc, #320] @ (800ba70 <_printf_i+0x234>)
800b930: 2100 movs r1, #0
800b932: f884 1043 strb.w r1, [r4, #67] @ 0x43
800b936: 6866 ldr r6, [r4, #4]
800b938: 2e00 cmp r6, #0
800b93a: 60a6 str r6, [r4, #8]
800b93c: db05 blt.n 800b94a <_printf_i+0x10e>
800b93e: 6821 ldr r1, [r4, #0]
800b940: 432e orrs r6, r5
800b942: f021 0104 bic.w r1, r1, #4
800b946: 6021 str r1, [r4, #0]
800b948: d04b beq.n 800b9e2 <_printf_i+0x1a6>
800b94a: 4616 mov r6, r2
800b94c: fbb5 f1f3 udiv r1, r5, r3
800b950: fb03 5711 mls r7, r3, r1, r5
800b954: 5dc7 ldrb r7, [r0, r7]
800b956: f806 7d01 strb.w r7, [r6, #-1]!
800b95a: 462f mov r7, r5
800b95c: 42bb cmp r3, r7
800b95e: 460d mov r5, r1
800b960: d9f4 bls.n 800b94c <_printf_i+0x110>
800b962: 2b08 cmp r3, #8
800b964: d10b bne.n 800b97e <_printf_i+0x142>
800b966: 6823 ldr r3, [r4, #0]
800b968: 07df lsls r7, r3, #31
800b96a: d508 bpl.n 800b97e <_printf_i+0x142>
800b96c: 6923 ldr r3, [r4, #16]
800b96e: 6861 ldr r1, [r4, #4]
800b970: 4299 cmp r1, r3
800b972: bfde ittt le
800b974: 2330 movle r3, #48 @ 0x30
800b976: f806 3c01 strble.w r3, [r6, #-1]
800b97a: f106 36ff addle.w r6, r6, #4294967295
800b97e: 1b92 subs r2, r2, r6
800b980: 6122 str r2, [r4, #16]
800b982: 464b mov r3, r9
800b984: 4621 mov r1, r4
800b986: 4640 mov r0, r8
800b988: f8cd a000 str.w sl, [sp]
800b98c: aa03 add r2, sp, #12
800b98e: f7ff fee3 bl 800b758 <_printf_common>
800b992: 3001 adds r0, #1
800b994: d14a bne.n 800ba2c <_printf_i+0x1f0>
800b996: f04f 30ff mov.w r0, #4294967295
800b99a: b004 add sp, #16
800b99c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800b9a0: 6823 ldr r3, [r4, #0]
800b9a2: f043 0320 orr.w r3, r3, #32
800b9a6: 6023 str r3, [r4, #0]
800b9a8: 2778 movs r7, #120 @ 0x78
800b9aa: 4832 ldr r0, [pc, #200] @ (800ba74 <_printf_i+0x238>)
800b9ac: f884 7045 strb.w r7, [r4, #69] @ 0x45
800b9b0: 6823 ldr r3, [r4, #0]
800b9b2: 6831 ldr r1, [r6, #0]
800b9b4: 061f lsls r7, r3, #24
800b9b6: f851 5b04 ldr.w r5, [r1], #4
800b9ba: d402 bmi.n 800b9c2 <_printf_i+0x186>
800b9bc: 065f lsls r7, r3, #25
800b9be: bf48 it mi
800b9c0: b2ad uxthmi r5, r5
800b9c2: 6031 str r1, [r6, #0]
800b9c4: 07d9 lsls r1, r3, #31
800b9c6: bf44 itt mi
800b9c8: f043 0320 orrmi.w r3, r3, #32
800b9cc: 6023 strmi r3, [r4, #0]
800b9ce: b11d cbz r5, 800b9d8 <_printf_i+0x19c>
800b9d0: 2310 movs r3, #16
800b9d2: e7ad b.n 800b930 <_printf_i+0xf4>
800b9d4: 4826 ldr r0, [pc, #152] @ (800ba70 <_printf_i+0x234>)
800b9d6: e7e9 b.n 800b9ac <_printf_i+0x170>
800b9d8: 6823 ldr r3, [r4, #0]
800b9da: f023 0320 bic.w r3, r3, #32
800b9de: 6023 str r3, [r4, #0]
800b9e0: e7f6 b.n 800b9d0 <_printf_i+0x194>
800b9e2: 4616 mov r6, r2
800b9e4: e7bd b.n 800b962 <_printf_i+0x126>
800b9e6: 6833 ldr r3, [r6, #0]
800b9e8: 6825 ldr r5, [r4, #0]
800b9ea: 1d18 adds r0, r3, #4
800b9ec: 6961 ldr r1, [r4, #20]
800b9ee: 6030 str r0, [r6, #0]
800b9f0: 062e lsls r6, r5, #24
800b9f2: 681b ldr r3, [r3, #0]
800b9f4: d501 bpl.n 800b9fa <_printf_i+0x1be>
800b9f6: 6019 str r1, [r3, #0]
800b9f8: e002 b.n 800ba00 <_printf_i+0x1c4>
800b9fa: 0668 lsls r0, r5, #25
800b9fc: d5fb bpl.n 800b9f6 <_printf_i+0x1ba>
800b9fe: 8019 strh r1, [r3, #0]
800ba00: 2300 movs r3, #0
800ba02: 4616 mov r6, r2
800ba04: 6123 str r3, [r4, #16]
800ba06: e7bc b.n 800b982 <_printf_i+0x146>
800ba08: 6833 ldr r3, [r6, #0]
800ba0a: 2100 movs r1, #0
800ba0c: 1d1a adds r2, r3, #4
800ba0e: 6032 str r2, [r6, #0]
800ba10: 681e ldr r6, [r3, #0]
800ba12: 6862 ldr r2, [r4, #4]
800ba14: 4630 mov r0, r6
800ba16: f000 f859 bl 800bacc <memchr>
800ba1a: b108 cbz r0, 800ba20 <_printf_i+0x1e4>
800ba1c: 1b80 subs r0, r0, r6
800ba1e: 6060 str r0, [r4, #4]
800ba20: 6863 ldr r3, [r4, #4]
800ba22: 6123 str r3, [r4, #16]
800ba24: 2300 movs r3, #0
800ba26: f884 3043 strb.w r3, [r4, #67] @ 0x43
800ba2a: e7aa b.n 800b982 <_printf_i+0x146>
800ba2c: 4632 mov r2, r6
800ba2e: 4649 mov r1, r9
800ba30: 4640 mov r0, r8
800ba32: 6923 ldr r3, [r4, #16]
800ba34: 47d0 blx sl
800ba36: 3001 adds r0, #1
800ba38: d0ad beq.n 800b996 <_printf_i+0x15a>
800ba3a: 6823 ldr r3, [r4, #0]
800ba3c: 079b lsls r3, r3, #30
800ba3e: d413 bmi.n 800ba68 <_printf_i+0x22c>
800ba40: 68e0 ldr r0, [r4, #12]
800ba42: 9b03 ldr r3, [sp, #12]
800ba44: 4298 cmp r0, r3
800ba46: bfb8 it lt
800ba48: 4618 movlt r0, r3
800ba4a: e7a6 b.n 800b99a <_printf_i+0x15e>
800ba4c: 2301 movs r3, #1
800ba4e: 4632 mov r2, r6
800ba50: 4649 mov r1, r9
800ba52: 4640 mov r0, r8
800ba54: 47d0 blx sl
800ba56: 3001 adds r0, #1
800ba58: d09d beq.n 800b996 <_printf_i+0x15a>
800ba5a: 3501 adds r5, #1
800ba5c: 68e3 ldr r3, [r4, #12]
800ba5e: 9903 ldr r1, [sp, #12]
800ba60: 1a5b subs r3, r3, r1
800ba62: 42ab cmp r3, r5
800ba64: dcf2 bgt.n 800ba4c <_printf_i+0x210>
800ba66: e7eb b.n 800ba40 <_printf_i+0x204>
800ba68: 2500 movs r5, #0
800ba6a: f104 0619 add.w r6, r4, #25
800ba6e: e7f5 b.n 800ba5c <_printf_i+0x220>
800ba70: 0800be23 .word 0x0800be23
800ba74: 0800be34 .word 0x0800be34
0800ba78 <memmove>:
800ba78: 4288 cmp r0, r1
800ba7a: b510 push {r4, lr}
800ba7c: eb01 0402 add.w r4, r1, r2
800ba80: d902 bls.n 800ba88 <memmove+0x10>
800ba82: 4284 cmp r4, r0
800ba84: 4623 mov r3, r4
800ba86: d807 bhi.n 800ba98 <memmove+0x20>
800ba88: 1e43 subs r3, r0, #1
800ba8a: 42a1 cmp r1, r4
800ba8c: d008 beq.n 800baa0 <memmove+0x28>
800ba8e: f811 2b01 ldrb.w r2, [r1], #1
800ba92: f803 2f01 strb.w r2, [r3, #1]!
800ba96: e7f8 b.n 800ba8a <memmove+0x12>
800ba98: 4601 mov r1, r0
800ba9a: 4402 add r2, r0
800ba9c: 428a cmp r2, r1
800ba9e: d100 bne.n 800baa2 <memmove+0x2a>
800baa0: bd10 pop {r4, pc}
800baa2: f813 4d01 ldrb.w r4, [r3, #-1]!
800baa6: f802 4d01 strb.w r4, [r2, #-1]!
800baaa: e7f7 b.n 800ba9c <memmove+0x24>
0800baac <_sbrk_r>:
800baac: b538 push {r3, r4, r5, lr}
800baae: 2300 movs r3, #0
800bab0: 4d05 ldr r5, [pc, #20] @ (800bac8 <_sbrk_r+0x1c>)
800bab2: 4604 mov r4, r0
800bab4: 4608 mov r0, r1
800bab6: 602b str r3, [r5, #0]
800bab8: f7f6 fabe bl 8002038 <_sbrk>
800babc: 1c43 adds r3, r0, #1
800babe: d102 bne.n 800bac6 <_sbrk_r+0x1a>
800bac0: 682b ldr r3, [r5, #0]
800bac2: b103 cbz r3, 800bac6 <_sbrk_r+0x1a>
800bac4: 6023 str r3, [r4, #0]
800bac6: bd38 pop {r3, r4, r5, pc}
800bac8: 2000180c .word 0x2000180c
0800bacc <memchr>:
800bacc: 4603 mov r3, r0
800bace: b510 push {r4, lr}
800bad0: b2c9 uxtb r1, r1
800bad2: 4402 add r2, r0
800bad4: 4293 cmp r3, r2
800bad6: 4618 mov r0, r3
800bad8: d101 bne.n 800bade <memchr+0x12>
800bada: 2000 movs r0, #0
800badc: e003 b.n 800bae6 <memchr+0x1a>
800bade: 7804 ldrb r4, [r0, #0]
800bae0: 3301 adds r3, #1
800bae2: 428c cmp r4, r1
800bae4: d1f6 bne.n 800bad4 <memchr+0x8>
800bae6: bd10 pop {r4, pc}
0800bae8 <memcpy>:
800bae8: 440a add r2, r1
800baea: 4291 cmp r1, r2
800baec: f100 33ff add.w r3, r0, #4294967295
800baf0: d100 bne.n 800baf4 <memcpy+0xc>
800baf2: 4770 bx lr
800baf4: b510 push {r4, lr}
800baf6: f811 4b01 ldrb.w r4, [r1], #1
800bafa: 4291 cmp r1, r2
800bafc: f803 4f01 strb.w r4, [r3, #1]!
800bb00: d1f9 bne.n 800baf6 <memcpy+0xe>
800bb02: bd10 pop {r4, pc}
0800bb04 <_realloc_r>:
800bb04: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800bb08: 4607 mov r7, r0
800bb0a: 4614 mov r4, r2
800bb0c: 460d mov r5, r1
800bb0e: b921 cbnz r1, 800bb1a <_realloc_r+0x16>
800bb10: 4611 mov r1, r2
800bb12: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
800bb16: f7ff bc3b b.w 800b390 <_malloc_r>
800bb1a: b92a cbnz r2, 800bb28 <_realloc_r+0x24>
800bb1c: f7ff fbce bl 800b2bc <_free_r>
800bb20: 4625 mov r5, r4
800bb22: 4628 mov r0, r5
800bb24: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
800bb28: f000 f81a bl 800bb60 <_malloc_usable_size_r>
800bb2c: 4284 cmp r4, r0
800bb2e: 4606 mov r6, r0
800bb30: d802 bhi.n 800bb38 <_realloc_r+0x34>
800bb32: ebb4 0f50 cmp.w r4, r0, lsr #1
800bb36: d8f4 bhi.n 800bb22 <_realloc_r+0x1e>
800bb38: 4621 mov r1, r4
800bb3a: 4638 mov r0, r7
800bb3c: f7ff fc28 bl 800b390 <_malloc_r>
800bb40: 4680 mov r8, r0
800bb42: b908 cbnz r0, 800bb48 <_realloc_r+0x44>
800bb44: 4645 mov r5, r8
800bb46: e7ec b.n 800bb22 <_realloc_r+0x1e>
800bb48: 42b4 cmp r4, r6
800bb4a: 4622 mov r2, r4
800bb4c: 4629 mov r1, r5
800bb4e: bf28 it cs
800bb50: 4632 movcs r2, r6
800bb52: f7ff ffc9 bl 800bae8 <memcpy>
800bb56: 4629 mov r1, r5
800bb58: 4638 mov r0, r7
800bb5a: f7ff fbaf bl 800b2bc <_free_r>
800bb5e: e7f1 b.n 800bb44 <_realloc_r+0x40>
0800bb60 <_malloc_usable_size_r>:
800bb60: f851 3c04 ldr.w r3, [r1, #-4]
800bb64: 1f18 subs r0, r3, #4
800bb66: 2b00 cmp r3, #0
800bb68: bfbc itt lt
800bb6a: 580b ldrlt r3, [r1, r0]
800bb6c: 18c0 addlt r0, r0, r3
800bb6e: 4770 bx lr
0800bb70 <_init>:
800bb70: b5f8 push {r3, r4, r5, r6, r7, lr}
800bb72: bf00 nop
800bb74: bcf8 pop {r3, r4, r5, r6, r7}
800bb76: bc08 pop {r3}
800bb78: 469e mov lr, r3
800bb7a: 4770 bx lr
0800bb7c <_fini>:
800bb7c: b5f8 push {r3, r4, r5, r6, r7, lr}
800bb7e: bf00 nop
800bb80: bcf8 pop {r3, r4, r5, r6, r7}
800bb82: bc08 pop {r3}
800bb84: 469e mov lr, r3
800bb86: 4770 bx lr
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