andrea/AUTOM
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
60536ed738f565c5ed11b03b8ee7377eeb5c6688
AUTOM/workspace/AUTOM10/Debug/AUTOM10.list
andrea 60536ed738 wip
2026-04-15 23:12:13 +02:00

31747 lines
1.2 MiB
Raw Blame History

AUTOM10.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000cdb8 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000030c 0800cec4 0800cec4 0000dec4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800d1d0 0800d1d0 0000f1d4 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800d1d0 0800d1d0 0000e1d0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800d1d8 0800d1d8 0000f1d4 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800d1d8 0800d1d8 0000e1d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800d1dc 0800d1dc 0000e1dc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 000001d4 20000000 0800d1e0 0000f000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000168c 200001d8 0800d3b4 0000f1d8 2**3
ALLOC
10 ._user_heap_stack 00000604 20001864 0800d3b4 0000f864 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000f1d4 2**0
CONTENTS, READONLY
12 .debug_info 00018bde 00000000 00000000 0000f1fd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00004586 00000000 00000000 00027ddb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001628 00000000 00000000 0002c368 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00001102 00000000 00000000 0002d990 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001c8d2 00000000 00000000 0002ea92 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001d46f 00000000 00000000 0004b364 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00095b38 00000000 00000000 000687d3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000fe30b 2**0
CONTENTS, READONLY
20 .debug_frame 00005fd8 00000000 00000000 000fe350 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 00104328 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 200001d8 .word 0x200001d8
8000128: 00000000 .word 0x00000000
800012c: 0800ceac .word 0x0800ceac
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 200001dc .word 0x200001dc
8000148: 0800ceac .word 0x0800ceac
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <manageAdc>:
uint16_t ch5 ;
uint16_t ch6 ;
uint16_t ch7 ;
uint16_t ch8 ;
void manageAdc(void){
800015c: b480 push {r7}
800015e: af00 add r7, sp, #0
if (adc_avg_ready)
8000160: 4b12 ldr r3, [pc, #72] @ (80001ac <manageAdc+0x50>)
8000162: 781b ldrb r3, [r3, #0]
8000164: b2db uxtb r3, r3
8000166: 2b00 cmp r3, #0
8000168: d01b beq.n 80001a2 <manageAdc+0x46>
{
adc_avg_ready = 0;
800016a: 4b10 ldr r3, [pc, #64] @ (80001ac <manageAdc+0x50>)
800016c: 2200 movs r2, #0
800016e: 701a strb r2, [r3, #0]
// Read averaged channels (example mapping)
ch4 = adc_avg[0];
8000170: 4b0f ldr r3, [pc, #60] @ (80001b0 <manageAdc+0x54>)
8000172: 881b ldrh r3, [r3, #0]
8000174: b29a uxth r2, r3
8000176: 4b0f ldr r3, [pc, #60] @ (80001b4 <manageAdc+0x58>)
8000178: 801a strh r2, [r3, #0]
ch5 = adc_avg[1];
800017a: 4b0d ldr r3, [pc, #52] @ (80001b0 <manageAdc+0x54>)
800017c: 885b ldrh r3, [r3, #2]
800017e: b29a uxth r2, r3
8000180: 4b0d ldr r3, [pc, #52] @ (80001b8 <manageAdc+0x5c>)
8000182: 801a strh r2, [r3, #0]
ch6 = adc_avg[2];
8000184: 4b0a ldr r3, [pc, #40] @ (80001b0 <manageAdc+0x54>)
8000186: 889b ldrh r3, [r3, #4]
8000188: b29a uxth r2, r3
800018a: 4b0c ldr r3, [pc, #48] @ (80001bc <manageAdc+0x60>)
800018c: 801a strh r2, [r3, #0]
ch7 = adc_avg[3];
800018e: 4b08 ldr r3, [pc, #32] @ (80001b0 <manageAdc+0x54>)
8000190: 88db ldrh r3, [r3, #6]
8000192: b29a uxth r2, r3
8000194: 4b0a ldr r3, [pc, #40] @ (80001c0 <manageAdc+0x64>)
8000196: 801a strh r2, [r3, #0]
ch8 = adc_avg[4];
8000198: 4b05 ldr r3, [pc, #20] @ (80001b0 <manageAdc+0x54>)
800019a: 891b ldrh r3, [r3, #8]
800019c: b29a uxth r2, r3
800019e: 4b09 ldr r3, [pc, #36] @ (80001c4 <manageAdc+0x68>)
80001a0: 801a strh r2, [r3, #0]
// Use them (convert to volts, control, etc.)
// float v4 = (3.3f * ch4) / 4095.0f;
}
}
80001a2: bf00 nop
80001a4: 46bd mov sp, r7
80001a6: bc80 pop {r7}
80001a8: 4770 bx lr
80001aa: bf00 nop
80001ac: 20000221 .word 0x20000221
80001b0: 20000200 .word 0x20000200
80001b4: 20000222 .word 0x20000222
80001b8: 20000224 .word 0x20000224
80001bc: 20000226 .word 0x20000226
80001c0: 20000228 .word 0x20000228
80001c4: 2000022a .word 0x2000022a
080001c8 <readAdc>:
void readAdc(void){
80001c8: b480 push {r7}
80001ca: b083 sub sp, #12
80001cc: af00 add r7, sp, #0
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
80001ce: 2300 movs r3, #0
80001d0: 71fb strb r3, [r7, #7]
80001d2: e010 b.n 80001f6 <readAdc+0x2e>
{
adc_sum[i] += adc_dma_buf[i];
80001d4: 79fb ldrb r3, [r7, #7]
80001d6: 4a21 ldr r2, [pc, #132] @ (800025c <readAdc+0x94>)
80001d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80001dc: b299 uxth r1, r3
80001de: 79fb ldrb r3, [r7, #7]
80001e0: 4a1f ldr r2, [pc, #124] @ (8000260 <readAdc+0x98>)
80001e2: f852 2023 ldr.w r2, [r2, r3, lsl #2]
80001e6: 79fb ldrb r3, [r7, #7]
80001e8: 440a add r2, r1
80001ea: 491d ldr r1, [pc, #116] @ (8000260 <readAdc+0x98>)
80001ec: f841 2023 str.w r2, [r1, r3, lsl #2]
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
80001f0: 79fb ldrb r3, [r7, #7]
80001f2: 3301 adds r3, #1
80001f4: 71fb strb r3, [r7, #7]
80001f6: 79fb ldrb r3, [r7, #7]
80001f8: 2b04 cmp r3, #4
80001fa: d9eb bls.n 80001d4 <readAdc+0xc>
}
adc_sum_count++;
80001fc: 4b19 ldr r3, [pc, #100] @ (8000264 <readAdc+0x9c>)
80001fe: 781b ldrb r3, [r3, #0]
8000200: 3301 adds r3, #1
8000202: b2da uxtb r2, r3
8000204: 4b17 ldr r3, [pc, #92] @ (8000264 <readAdc+0x9c>)
8000206: 701a strb r2, [r3, #0]
/* When we collected ADC_AVG_WINDOW samples → compute average */
if (adc_sum_count >= ADC_AVG_WINDOW)
8000208: 4b16 ldr r3, [pc, #88] @ (8000264 <readAdc+0x9c>)
800020a: 781b ldrb r3, [r3, #0]
800020c: 2b04 cmp r3, #4
800020e: d920 bls.n 8000252 <readAdc+0x8a>
{
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
8000210: 2300 movs r3, #0
8000212: 71bb strb r3, [r7, #6]
8000214: e014 b.n 8000240 <readAdc+0x78>
{
adc_avg[i] = (uint16_t)(adc_sum[i] / ADC_AVG_WINDOW);
8000216: 79bb ldrb r3, [r7, #6]
8000218: 4a11 ldr r2, [pc, #68] @ (8000260 <readAdc+0x98>)
800021a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800021e: 4a12 ldr r2, [pc, #72] @ (8000268 <readAdc+0xa0>)
8000220: fba2 2303 umull r2, r3, r2, r3
8000224: 089a lsrs r2, r3, #2
8000226: 79bb ldrb r3, [r7, #6]
8000228: b291 uxth r1, r2
800022a: 4a10 ldr r2, [pc, #64] @ (800026c <readAdc+0xa4>)
800022c: f822 1013 strh.w r1, [r2, r3, lsl #1]
adc_sum[i] = 0;
8000230: 79bb ldrb r3, [r7, #6]
8000232: 4a0b ldr r2, [pc, #44] @ (8000260 <readAdc+0x98>)
8000234: 2100 movs r1, #0
8000236: f842 1023 str.w r1, [r2, r3, lsl #2]
for (uint8_t i = 0; i < ADC_NUM_CHANNELS; i++)
800023a: 79bb ldrb r3, [r7, #6]
800023c: 3301 adds r3, #1
800023e: 71bb strb r3, [r7, #6]
8000240: 79bb ldrb r3, [r7, #6]
8000242: 2b04 cmp r3, #4
8000244: d9e7 bls.n 8000216 <readAdc+0x4e>
}
adc_sum_count = 0;
8000246: 4b07 ldr r3, [pc, #28] @ (8000264 <readAdc+0x9c>)
8000248: 2200 movs r2, #0
800024a: 701a strb r2, [r3, #0]
adc_avg_ready = 1; // tell main loop new data is ready
800024c: 4b08 ldr r3, [pc, #32] @ (8000270 <readAdc+0xa8>)
800024e: 2201 movs r2, #1
8000250: 701a strb r2, [r3, #0]
}
}
8000252: bf00 nop
8000254: 370c adds r7, #12
8000256: 46bd mov sp, r7
8000258: bc80 pop {r7}
800025a: 4770 bx lr
800025c: 200001f4 .word 0x200001f4
8000260: 2000020c .word 0x2000020c
8000264: 20000220 .word 0x20000220
8000268: cccccccd .word 0xcccccccd
800026c: 20000200 .word 0x20000200
8000270: 20000221 .word 0x20000221
08000274 <EEW_Read>:
uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data);
uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data);
void loadEE(void);
/* Pseudo-array accessor EEW[idx] */
static inline uint16_t EEW_Read(uint8_t idx, uint16_t *value)
{
8000274: b580 push {r7, lr}
8000276: b082 sub sp, #8
8000278: af00 add r7, sp, #0
800027a: 4603 mov r3, r0
800027c: 6039 str r1, [r7, #0]
800027e: 71fb strb r3, [r7, #7]
return EE_ReadVariable(EEW_ADDR(idx), value);
8000280: 79fb ldrb r3, [r7, #7]
8000282: b29b uxth r3, r3
8000284: 3301 adds r3, #1
8000286: b29b uxth r3, r3
8000288: 6839 ldr r1, [r7, #0]
800028a: 4618 mov r0, r3
800028c: f000 ff62 bl 8001154 <EE_ReadVariable>
8000290: 4603 mov r3, r0
}
8000292: 4618 mov r0, r3
8000294: 3708 adds r7, #8
8000296: 46bd mov sp, r7
8000298: bd80 pop {r7, pc}
0800029a <EEW_Write>:
static inline uint16_t EEW_Write(uint8_t idx, uint16_t value)
{
800029a: b580 push {r7, lr}
800029c: b082 sub sp, #8
800029e: af00 add r7, sp, #0
80002a0: 4603 mov r3, r0
80002a2: 460a mov r2, r1
80002a4: 71fb strb r3, [r7, #7]
80002a6: 4613 mov r3, r2
80002a8: 80bb strh r3, [r7, #4]
return EE_WriteVariable(EEW_ADDR(idx), value);
80002aa: 79fb ldrb r3, [r7, #7]
80002ac: b29b uxth r3, r3
80002ae: 3301 adds r3, #1
80002b0: b29b uxth r3, r3
80002b2: 88ba ldrh r2, [r7, #4]
80002b4: 4611 mov r1, r2
80002b6: 4618 mov r0, r3
80002b8: f000 ff68 bl 800118c <EE_WriteVariable>
80002bc: 4603 mov r3, r0
}
80002be: 4618 mov r0, r3
80002c0: 3708 adds r7, #8
80002c2: 46bd mov sp, r7
80002c4: bd80 pop {r7, pc}
080002c6 <toHex>:
extern const uint8_t deftab[];
extern omCiclo_st stCiclo;
extern omCiclo_st memstCiclo;
extern uint8_t stPulsanti;
bool toHex(char c1,char c2,char c3,char c4,uint16_t* retval){
80002c6: b490 push {r4, r7}
80002c8: b082 sub sp, #8
80002ca: af00 add r7, sp, #0
80002cc: 4604 mov r4, r0
80002ce: 4608 mov r0, r1
80002d0: 4611 mov r1, r2
80002d2: 461a mov r2, r3
80002d4: 4623 mov r3, r4
80002d6: 71fb strb r3, [r7, #7]
80002d8: 4603 mov r3, r0
80002da: 71bb strb r3, [r7, #6]
80002dc: 460b mov r3, r1
80002de: 717b strb r3, [r7, #5]
80002e0: 4613 mov r3, r2
80002e2: 713b strb r3, [r7, #4]
if((c1>='0')&&(c1<='9')){
80002e4: 79fb ldrb r3, [r7, #7]
80002e6: 2b2f cmp r3, #47 @ 0x2f
80002e8: d906 bls.n 80002f8 <toHex+0x32>
80002ea: 79fb ldrb r3, [r7, #7]
80002ec: 2b39 cmp r3, #57 @ 0x39
80002ee: d803 bhi.n 80002f8 <toHex+0x32>
c1-='0';
80002f0: 79fb ldrb r3, [r7, #7]
80002f2: 3b30 subs r3, #48 @ 0x30
80002f4: 71fb strb r3, [r7, #7]
80002f6: e00b b.n 8000310 <toHex+0x4a>
}else if((c1>='a')&&(c1<='f')){
80002f8: 79fb ldrb r3, [r7, #7]
80002fa: 2b60 cmp r3, #96 @ 0x60
80002fc: d906 bls.n 800030c <toHex+0x46>
80002fe: 79fb ldrb r3, [r7, #7]
8000300: 2b66 cmp r3, #102 @ 0x66
8000302: d803 bhi.n 800030c <toHex+0x46>
c1=(c1-'a')+10;
8000304: 79fb ldrb r3, [r7, #7]
8000306: 3b57 subs r3, #87 @ 0x57
8000308: 71fb strb r3, [r7, #7]
800030a: e001 b.n 8000310 <toHex+0x4a>
}else return false;
800030c: 2300 movs r3, #0
800030e: e070 b.n 80003f2 <toHex+0x12c>
if((c2>='0')&&(c2<='9')){
8000310: 79bb ldrb r3, [r7, #6]
8000312: 2b2f cmp r3, #47 @ 0x2f
8000314: d906 bls.n 8000324 <toHex+0x5e>
8000316: 79bb ldrb r3, [r7, #6]
8000318: 2b39 cmp r3, #57 @ 0x39
800031a: d803 bhi.n 8000324 <toHex+0x5e>
c2-='0';
800031c: 79bb ldrb r3, [r7, #6]
800031e: 3b30 subs r3, #48 @ 0x30
8000320: 71bb strb r3, [r7, #6]
8000322: e00b b.n 800033c <toHex+0x76>
}else if((c2>='a')&&(c2<='f')){
8000324: 79bb ldrb r3, [r7, #6]
8000326: 2b60 cmp r3, #96 @ 0x60
8000328: d906 bls.n 8000338 <toHex+0x72>
800032a: 79bb ldrb r3, [r7, #6]
800032c: 2b66 cmp r3, #102 @ 0x66
800032e: d803 bhi.n 8000338 <toHex+0x72>
c2=(c2-'a')+10;
8000330: 79bb ldrb r3, [r7, #6]
8000332: 3b57 subs r3, #87 @ 0x57
8000334: 71bb strb r3, [r7, #6]
8000336: e001 b.n 800033c <toHex+0x76>
}else return false;
8000338: 2300 movs r3, #0
800033a: e05a b.n 80003f2 <toHex+0x12c>
if((c3>='0')&&(c3<='9')){
800033c: 797b ldrb r3, [r7, #5]
800033e: 2b2f cmp r3, #47 @ 0x2f
8000340: d906 bls.n 8000350 <toHex+0x8a>
8000342: 797b ldrb r3, [r7, #5]
8000344: 2b39 cmp r3, #57 @ 0x39
8000346: d803 bhi.n 8000350 <toHex+0x8a>
c3-='0';
8000348: 797b ldrb r3, [r7, #5]
800034a: 3b30 subs r3, #48 @ 0x30
800034c: 717b strb r3, [r7, #5]
800034e: e00b b.n 8000368 <toHex+0xa2>
}else if((c3>='a')&&(c3<='f')){
8000350: 797b ldrb r3, [r7, #5]
8000352: 2b60 cmp r3, #96 @ 0x60
8000354: d906 bls.n 8000364 <toHex+0x9e>
8000356: 797b ldrb r3, [r7, #5]
8000358: 2b66 cmp r3, #102 @ 0x66
800035a: d803 bhi.n 8000364 <toHex+0x9e>
c3=(c3-'a')+10;
800035c: 797b ldrb r3, [r7, #5]
800035e: 3b57 subs r3, #87 @ 0x57
8000360: 717b strb r3, [r7, #5]
8000362: e001 b.n 8000368 <toHex+0xa2>
}else return false;
8000364: 2300 movs r3, #0
8000366: e044 b.n 80003f2 <toHex+0x12c>
if((c4>='0')&&(c4<='9')){
8000368: 793b ldrb r3, [r7, #4]
800036a: 2b2f cmp r3, #47 @ 0x2f
800036c: d906 bls.n 800037c <toHex+0xb6>
800036e: 793b ldrb r3, [r7, #4]
8000370: 2b39 cmp r3, #57 @ 0x39
8000372: d803 bhi.n 800037c <toHex+0xb6>
c4-='0';
8000374: 793b ldrb r3, [r7, #4]
8000376: 3b30 subs r3, #48 @ 0x30
8000378: 713b strb r3, [r7, #4]
800037a: e00b b.n 8000394 <toHex+0xce>
}else if((c4>='a')&&(c4<='f')){
800037c: 793b ldrb r3, [r7, #4]
800037e: 2b60 cmp r3, #96 @ 0x60
8000380: d906 bls.n 8000390 <toHex+0xca>
8000382: 793b ldrb r3, [r7, #4]
8000384: 2b66 cmp r3, #102 @ 0x66
8000386: d803 bhi.n 8000390 <toHex+0xca>
c4=(c4-'a')+10;
8000388: 793b ldrb r3, [r7, #4]
800038a: 3b57 subs r3, #87 @ 0x57
800038c: 713b strb r3, [r7, #4]
800038e: e001 b.n 8000394 <toHex+0xce>
}else return false;
8000390: 2300 movs r3, #0
8000392: e02e b.n 80003f2 <toHex+0x12c>
*retval=c1;
8000394: 79fb ldrb r3, [r7, #7]
8000396: b29a uxth r2, r3
8000398: 693b ldr r3, [r7, #16]
800039a: 801a strh r2, [r3, #0]
*retval*=16;
800039c: 693b ldr r3, [r7, #16]
800039e: 881b ldrh r3, [r3, #0]
80003a0: 011b lsls r3, r3, #4
80003a2: b29a uxth r2, r3
80003a4: 693b ldr r3, [r7, #16]
80003a6: 801a strh r2, [r3, #0]
*retval+=c2;
80003a8: 693b ldr r3, [r7, #16]
80003aa: 881a ldrh r2, [r3, #0]
80003ac: 79bb ldrb r3, [r7, #6]
80003ae: b29b uxth r3, r3
80003b0: 4413 add r3, r2
80003b2: b29a uxth r2, r3
80003b4: 693b ldr r3, [r7, #16]
80003b6: 801a strh r2, [r3, #0]
*retval*=16;
80003b8: 693b ldr r3, [r7, #16]
80003ba: 881b ldrh r3, [r3, #0]
80003bc: 011b lsls r3, r3, #4
80003be: b29a uxth r2, r3
80003c0: 693b ldr r3, [r7, #16]
80003c2: 801a strh r2, [r3, #0]
*retval+=c3;
80003c4: 693b ldr r3, [r7, #16]
80003c6: 881a ldrh r2, [r3, #0]
80003c8: 797b ldrb r3, [r7, #5]
80003ca: b29b uxth r3, r3
80003cc: 4413 add r3, r2
80003ce: b29a uxth r2, r3
80003d0: 693b ldr r3, [r7, #16]
80003d2: 801a strh r2, [r3, #0]
*retval*=16;
80003d4: 693b ldr r3, [r7, #16]
80003d6: 881b ldrh r3, [r3, #0]
80003d8: 011b lsls r3, r3, #4
80003da: b29a uxth r2, r3
80003dc: 693b ldr r3, [r7, #16]
80003de: 801a strh r2, [r3, #0]
*retval+=c4;
80003e0: 693b ldr r3, [r7, #16]
80003e2: 881a ldrh r2, [r3, #0]
80003e4: 793b ldrb r3, [r7, #4]
80003e6: b29b uxth r3, r3
80003e8: 4413 add r3, r2
80003ea: b29a uxth r2, r3
80003ec: 693b ldr r3, [r7, #16]
80003ee: 801a strh r2, [r3, #0]
return true;
80003f0: 2301 movs r3, #1
}
80003f2: 4618 mov r0, r3
80003f4: 3708 adds r7, #8
80003f6: 46bd mov sp, r7
80003f8: bc90 pop {r4, r7}
80003fa: 4770 bx lr
080003fc <manageCDC>:
void manageCDC(void){
80003fc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
8000400: b0a7 sub sp, #156 @ 0x9c
8000402: af06 add r7, sp, #24
uint16_t val;
uint16_t st;
uint16_t eeadd;
uint8_t i;
if (CDC_Available()) {
8000404: f00b fbee bl 800bbe4 <CDC_Available>
8000408: 4603 mov r3, r0
800040a: 2b00 cmp r3, #0
800040c: f000 84d2 beq.w 8000db4 <manageCDC+0x9b8>
int rx = CDC_ReadByte();
8000410: f00b fbfc bl 800bc0c <CDC_ReadByte>
8000414: 67b8 str r0, [r7, #120] @ 0x78
if (rx < 0) return;
8000416: 6fbb ldr r3, [r7, #120] @ 0x78
8000418: 2b00 cmp r3, #0
800041a: f2c0 84ca blt.w 8000db2 <manageCDC+0x9b6>
//uint8_t out = (uint8_t)c;
//if (out >= 'a' && out <= 'z') out -= 32; // to upper
rxbuf[rxidx]=rx;
800041e: 4bad ldr r3, [pc, #692] @ (80006d4 <manageCDC+0x2d8>)
8000420: 781b ldrb r3, [r3, #0]
8000422: 461a mov r2, r3
8000424: 6fbb ldr r3, [r7, #120] @ 0x78
8000426: b2d9 uxtb r1, r3
8000428: 4bab ldr r3, [pc, #684] @ (80006d8 <manageCDC+0x2dc>)
800042a: 5499 strb r1, [r3, r2]
while (CDC_Transmit_FS(&rxbuf[rxidx], 1) == USBD_BUSY);//echo
800042c: bf00 nop
800042e: 4ba9 ldr r3, [pc, #676] @ (80006d4 <manageCDC+0x2d8>)
8000430: 781b ldrb r3, [r3, #0]
8000432: 461a mov r2, r3
8000434: 4ba8 ldr r3, [pc, #672] @ (80006d8 <manageCDC+0x2dc>)
8000436: 4413 add r3, r2
8000438: 2101 movs r1, #1
800043a: 4618 mov r0, r3
800043c: f00b fca8 bl 800bd90 <CDC_Transmit_FS>
8000440: 4603 mov r3, r0
8000442: 2b01 cmp r3, #1
8000444: d0f3 beq.n 800042e <manageCDC+0x32>
if((rx==0x0d)||(rx==0x0a)){
8000446: 6fbb ldr r3, [r7, #120] @ 0x78
8000448: 2b0d cmp r3, #13
800044a: d003 beq.n 8000454 <manageCDC+0x58>
800044c: 6fbb ldr r3, [r7, #120] @ 0x78
800044e: 2b0a cmp r3, #10
8000450: f040 84a8 bne.w 8000da4 <manageCDC+0x9a8>
if(rxidx){
8000454: 4b9f ldr r3, [pc, #636] @ (80006d4 <manageCDC+0x2d8>)
8000456: 781b ldrb r3, [r3, #0]
8000458: 2b00 cmp r3, #0
800045a: f000 849f beq.w 8000d9c <manageCDC+0x9a0>
switch(rxbuf[0]){
800045e: 4b9e ldr r3, [pc, #632] @ (80006d8 <manageCDC+0x2dc>)
8000460: 781b ldrb r3, [r3, #0]
8000462: 2b6d cmp r3, #109 @ 0x6d
8000464: f000 80fb beq.w 800065e <manageCDC+0x262>
8000468: 2b6d cmp r3, #109 @ 0x6d
800046a: f300 8485 bgt.w 8000d78 <manageCDC+0x97c>
800046e: 2b69 cmp r3, #105 @ 0x69
8000470: d00a beq.n 8000488 <manageCDC+0x8c>
8000472: 2b69 cmp r3, #105 @ 0x69
8000474: f300 8480 bgt.w 8000d78 <manageCDC+0x97c>
8000478: 2b49 cmp r3, #73 @ 0x49
800047a: f000 80df beq.w 800063c <manageCDC+0x240>
800047e: 2b65 cmp r3, #101 @ 0x65
8000480: f000 8228 beq.w 80008d4 <manageCDC+0x4d8>
8000484: f000 bc78 b.w 8000d78 <manageCDC+0x97c>
case 'i':
sprintf((char*)s,"info\n");
8000488: f107 030c add.w r3, r7, #12
800048c: 4993 ldr r1, [pc, #588] @ (80006dc <manageCDC+0x2e0>)
800048e: 4618 mov r0, r3
8000490: f00c f85c bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 5) == USBD_BUSY);
8000494: bf00 nop
8000496: f107 030c add.w r3, r7, #12
800049a: 2105 movs r1, #5
800049c: 4618 mov r0, r3
800049e: f00b fc77 bl 800bd90 <CDC_Transmit_FS>
80004a2: 4603 mov r3, r0
80004a4: 2b01 cmp r3, #1
80004a6: d0f6 beq.n 8000496 <manageCDC+0x9a>
sprintf((char*)s,"\npwm %d%d%d%d%d%d%d%d",IsPwmRunning(timMot1,FWMot1),IsPwmRunning(timMot1,BWMot1),IsPwmRunning(timMot2,FWMot2),IsPwmRunning(timMot2,BWMot2),IsPwmRunning(timMot3,FWMot3),IsPwmRunning(timMot3,BWMot3),IsPwmRunning(timMot4,FWMot4),IsPwmRunning(timMot4,BWMot4));
80004a8: 2100 movs r1, #0
80004aa: 488d ldr r0, [pc, #564] @ (80006e0 <manageCDC+0x2e4>)
80004ac: f002 f96c bl 8002788 <IsPwmRunning>
80004b0: 4603 mov r3, r0
80004b2: 4698 mov r8, r3
80004b4: 2104 movs r1, #4
80004b6: 488a ldr r0, [pc, #552] @ (80006e0 <manageCDC+0x2e4>)
80004b8: f002 f966 bl 8002788 <IsPwmRunning>
80004bc: 4603 mov r3, r0
80004be: 4699 mov r9, r3
80004c0: 2108 movs r1, #8
80004c2: 4887 ldr r0, [pc, #540] @ (80006e0 <manageCDC+0x2e4>)
80004c4: f002 f960 bl 8002788 <IsPwmRunning>
80004c8: 4603 mov r3, r0
80004ca: 461c mov r4, r3
80004cc: 210c movs r1, #12
80004ce: 4884 ldr r0, [pc, #528] @ (80006e0 <manageCDC+0x2e4>)
80004d0: f002 f95a bl 8002788 <IsPwmRunning>
80004d4: 4603 mov r3, r0
80004d6: 461d mov r5, r3
80004d8: 2100 movs r1, #0
80004da: 4882 ldr r0, [pc, #520] @ (80006e4 <manageCDC+0x2e8>)
80004dc: f002 f954 bl 8002788 <IsPwmRunning>
80004e0: 4603 mov r3, r0
80004e2: 461e mov r6, r3
80004e4: 2104 movs r1, #4
80004e6: 487f ldr r0, [pc, #508] @ (80006e4 <manageCDC+0x2e8>)
80004e8: f002 f94e bl 8002788 <IsPwmRunning>
80004ec: 4603 mov r3, r0
80004ee: 607b str r3, [r7, #4]
80004f0: 2108 movs r1, #8
80004f2: 487c ldr r0, [pc, #496] @ (80006e4 <manageCDC+0x2e8>)
80004f4: f002 f948 bl 8002788 <IsPwmRunning>
80004f8: 4603 mov r3, r0
80004fa: 603b str r3, [r7, #0]
80004fc: 210c movs r1, #12
80004fe: 4879 ldr r0, [pc, #484] @ (80006e4 <manageCDC+0x2e8>)
8000500: f002 f942 bl 8002788 <IsPwmRunning>
8000504: 4603 mov r3, r0
8000506: f107 000c add.w r0, r7, #12
800050a: 9305 str r3, [sp, #20]
800050c: 683a ldr r2, [r7, #0]
800050e: 9204 str r2, [sp, #16]
8000510: 687b ldr r3, [r7, #4]
8000512: 9303 str r3, [sp, #12]
8000514: 9602 str r6, [sp, #8]
8000516: 9501 str r5, [sp, #4]
8000518: 9400 str r4, [sp, #0]
800051a: 464b mov r3, r9
800051c: 4642 mov r2, r8
800051e: 4972 ldr r1, [pc, #456] @ (80006e8 <manageCDC+0x2ec>)
8000520: f00c f814 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000524: bf00 nop
8000526: f107 030c add.w r3, r7, #12
800052a: 4618 mov r0, r3
800052c: f7ff fe0e bl 800014c <strlen>
8000530: 4603 mov r3, r0
8000532: b29a uxth r2, r3
8000534: f107 030c add.w r3, r7, #12
8000538: 4611 mov r1, r2
800053a: 4618 mov r0, r3
800053c: f00b fc28 bl 800bd90 <CDC_Transmit_FS>
8000540: 4603 mov r3, r0
8000542: 2b01 cmp r3, #1
8000544: d0ef beq.n 8000526 <manageCDC+0x12a>
sprintf((char*)s,"\n0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx",(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,FWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,BWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,FWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,BWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,FWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,BWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,FWMot4),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,BWMot4));
8000546: 4b66 ldr r3, [pc, #408] @ (80006e0 <manageCDC+0x2e4>)
8000548: 681b ldr r3, [r3, #0]
800054a: 6b5b ldr r3, [r3, #52] @ 0x34
800054c: 607b str r3, [r7, #4]
800054e: 4b64 ldr r3, [pc, #400] @ (80006e0 <manageCDC+0x2e4>)
8000550: 681b ldr r3, [r3, #0]
8000552: 6b99 ldr r1, [r3, #56] @ 0x38
8000554: 6039 str r1, [r7, #0]
8000556: 4b62 ldr r3, [pc, #392] @ (80006e0 <manageCDC+0x2e4>)
8000558: 681b ldr r3, [r3, #0]
800055a: 6bdb ldr r3, [r3, #60] @ 0x3c
800055c: 4a60 ldr r2, [pc, #384] @ (80006e0 <manageCDC+0x2e4>)
800055e: 6812 ldr r2, [r2, #0]
8000560: 6c12 ldr r2, [r2, #64] @ 0x40
8000562: 4960 ldr r1, [pc, #384] @ (80006e4 <manageCDC+0x2e8>)
8000564: 6809 ldr r1, [r1, #0]
8000566: 6b49 ldr r1, [r1, #52] @ 0x34
8000568: 485e ldr r0, [pc, #376] @ (80006e4 <manageCDC+0x2e8>)
800056a: 6800 ldr r0, [r0, #0]
800056c: 6b80 ldr r0, [r0, #56] @ 0x38
800056e: 4c5d ldr r4, [pc, #372] @ (80006e4 <manageCDC+0x2e8>)
8000570: 6824 ldr r4, [r4, #0]
8000572: 6be4 ldr r4, [r4, #60] @ 0x3c
8000574: 4d5b ldr r5, [pc, #364] @ (80006e4 <manageCDC+0x2e8>)
8000576: 682d ldr r5, [r5, #0]
8000578: 6c2d ldr r5, [r5, #64] @ 0x40
800057a: f107 060c add.w r6, r7, #12
800057e: 9505 str r5, [sp, #20]
8000580: 9404 str r4, [sp, #16]
8000582: 9003 str r0, [sp, #12]
8000584: 9102 str r1, [sp, #8]
8000586: 9201 str r2, [sp, #4]
8000588: 9300 str r3, [sp, #0]
800058a: 683b ldr r3, [r7, #0]
800058c: 687a ldr r2, [r7, #4]
800058e: 4957 ldr r1, [pc, #348] @ (80006ec <manageCDC+0x2f0>)
8000590: 4630 mov r0, r6
8000592: f00b ffdb bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000596: bf00 nop
8000598: f107 030c add.w r3, r7, #12
800059c: 4618 mov r0, r3
800059e: f7ff fdd5 bl 800014c <strlen>
80005a2: 4603 mov r3, r0
80005a4: b29a uxth r2, r3
80005a6: f107 030c add.w r3, r7, #12
80005aa: 4611 mov r1, r2
80005ac: 4618 mov r0, r3
80005ae: f00b fbef bl 800bd90 <CDC_Transmit_FS>
80005b2: 4603 mov r3, r0
80005b4: 2b01 cmp r3, #1
80005b6: d0ef beq.n 8000598 <manageCDC+0x19c>
sprintf((char*)s,"\nP=0x%x ch4=%05d ch5=%05d ch6=%05d ch7=%05d ch8=%05d",pulsanti,ch4,ch5,ch6,ch7,ch8);
80005b8: 4b4d ldr r3, [pc, #308] @ (80006f0 <manageCDC+0x2f4>)
80005ba: 781b ldrb r3, [r3, #0]
80005bc: 461d mov r5, r3
80005be: 4b4d ldr r3, [pc, #308] @ (80006f4 <manageCDC+0x2f8>)
80005c0: 881b ldrh r3, [r3, #0]
80005c2: 461e mov r6, r3
80005c4: 4b4c ldr r3, [pc, #304] @ (80006f8 <manageCDC+0x2fc>)
80005c6: 881b ldrh r3, [r3, #0]
80005c8: 461a mov r2, r3
80005ca: 4b4c ldr r3, [pc, #304] @ (80006fc <manageCDC+0x300>)
80005cc: 881b ldrh r3, [r3, #0]
80005ce: 4619 mov r1, r3
80005d0: 4b4b ldr r3, [pc, #300] @ (8000700 <manageCDC+0x304>)
80005d2: 881b ldrh r3, [r3, #0]
80005d4: 461c mov r4, r3
80005d6: 4b4b ldr r3, [pc, #300] @ (8000704 <manageCDC+0x308>)
80005d8: 881b ldrh r3, [r3, #0]
80005da: f107 000c add.w r0, r7, #12
80005de: 9303 str r3, [sp, #12]
80005e0: 9402 str r4, [sp, #8]
80005e2: 9101 str r1, [sp, #4]
80005e4: 9200 str r2, [sp, #0]
80005e6: 4633 mov r3, r6
80005e8: 462a mov r2, r5
80005ea: 4947 ldr r1, [pc, #284] @ (8000708 <manageCDC+0x30c>)
80005ec: f00b ffae bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
80005f0: bf00 nop
80005f2: f107 030c add.w r3, r7, #12
80005f6: 4618 mov r0, r3
80005f8: f7ff fda8 bl 800014c <strlen>
80005fc: 4603 mov r3, r0
80005fe: b29a uxth r2, r3
8000600: f107 030c add.w r3, r7, #12
8000604: 4611 mov r1, r2
8000606: 4618 mov r0, r3
8000608: f00b fbc2 bl 800bd90 <CDC_Transmit_FS>
800060c: 4603 mov r3, r0
800060e: 2b01 cmp r3, #1
8000610: d0ef beq.n 80005f2 <manageCDC+0x1f6>
sprintf((char*)s,"\nstCiclo=%05d stPulsanti=%05d",stCiclo,stPulsanti);
8000612: 4b3e ldr r3, [pc, #248] @ (800070c <manageCDC+0x310>)
8000614: 781b ldrb r3, [r3, #0]
8000616: 461a mov r2, r3
8000618: 4b3d ldr r3, [pc, #244] @ (8000710 <manageCDC+0x314>)
800061a: 781b ldrb r3, [r3, #0]
800061c: f107 000c add.w r0, r7, #12
8000620: 493c ldr r1, [pc, #240] @ (8000714 <manageCDC+0x318>)
8000622: f00b ff93 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 31) == USBD_BUSY);
8000626: bf00 nop
8000628: f107 030c add.w r3, r7, #12
800062c: 211f movs r1, #31
800062e: 4618 mov r0, r3
8000630: f00b fbae bl 800bd90 <CDC_Transmit_FS>
8000634: 4603 mov r3, r0
8000636: 2b01 cmp r3, #1
8000638: d0f6 beq.n 8000628 <manageCDC+0x22c>
break;
800063a: e3af b.n 8000d9c <manageCDC+0x9a0>
case 'I':
sprintf((char*)s,"\nID000000");
800063c: f107 030c add.w r3, r7, #12
8000640: 4935 ldr r1, [pc, #212] @ (8000718 <manageCDC+0x31c>)
8000642: 4618 mov r0, r3
8000644: f00b ff82 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 9) == USBD_BUSY);
8000648: bf00 nop
800064a: f107 030c add.w r3, r7, #12
800064e: 2109 movs r1, #9
8000650: 4618 mov r0, r3
8000652: f00b fb9d bl 800bd90 <CDC_Transmit_FS>
8000656: 4603 mov r3, r0
8000658: 2b01 cmp r3, #1
800065a: d0f6 beq.n 800064a <manageCDC+0x24e>
break;
800065c: e39e b.n 8000d9c <manageCDC+0x9a0>
case 'm':
if(rxidx==8){
800065e: 4b1d ldr r3, [pc, #116] @ (80006d4 <manageCDC+0x2d8>)
8000660: 781b ldrb r3, [r3, #0]
8000662: 2b08 cmp r3, #8
8000664: f040 8124 bne.w 80008b0 <manageCDC+0x4b4>
if((rxbuf[1]>='1')&&(rxbuf[1]<='4')){
8000668: 4b1b ldr r3, [pc, #108] @ (80006d8 <manageCDC+0x2dc>)
800066a: 785b ldrb r3, [r3, #1]
800066c: 2b30 cmp r3, #48 @ 0x30
800066e: f240 810e bls.w 800088e <manageCDC+0x492>
8000672: 4b19 ldr r3, [pc, #100] @ (80006d8 <manageCDC+0x2dc>)
8000674: 785b ldrb r3, [r3, #1]
8000676: 2b34 cmp r3, #52 @ 0x34
8000678: f200 8109 bhi.w 800088e <manageCDC+0x492>
mot=rxbuf[1]-='0';
800067c: 4b16 ldr r3, [pc, #88] @ (80006d8 <manageCDC+0x2dc>)
800067e: 785b ldrb r3, [r3, #1]
8000680: 3b30 subs r3, #48 @ 0x30
8000682: b2da uxtb r2, r3
8000684: 4b14 ldr r3, [pc, #80] @ (80006d8 <manageCDC+0x2dc>)
8000686: 705a strb r2, [r3, #1]
8000688: 4b13 ldr r3, [pc, #76] @ (80006d8 <manageCDC+0x2dc>)
800068a: 785b ldrb r3, [r3, #1]
800068c: f887 3077 strb.w r3, [r7, #119] @ 0x77
if(rxbuf[2]=='f'){
8000690: 4b11 ldr r3, [pc, #68] @ (80006d8 <manageCDC+0x2dc>)
8000692: 789b ldrb r3, [r3, #2]
8000694: 2b66 cmp r3, #102 @ 0x66
8000696: d103 bne.n 80006a0 <manageCDC+0x2a4>
dir=FW;
8000698: 2300 movs r3, #0
800069a: f887 307f strb.w r3, [r7, #127] @ 0x7f
800069e: e03f b.n 8000720 <manageCDC+0x324>
}else if(rxbuf[2]=='b'){
80006a0: 4b0d ldr r3, [pc, #52] @ (80006d8 <manageCDC+0x2dc>)
80006a2: 789b ldrb r3, [r3, #2]
80006a4: 2b62 cmp r3, #98 @ 0x62
80006a6: d103 bne.n 80006b0 <manageCDC+0x2b4>
dir=BW;
80006a8: 2301 movs r3, #1
80006aa: f887 307f strb.w r3, [r7, #127] @ 0x7f
80006ae: e037 b.n 8000720 <manageCDC+0x324>
}else{
sprintf((char*)s,"\n?mnsvvvvv s=f|b");//m nmotore senso valore
80006b0: f107 030c add.w r3, r7, #12
80006b4: 4919 ldr r1, [pc, #100] @ (800071c <manageCDC+0x320>)
80006b6: 4618 mov r0, r3
80006b8: f00b ff48 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 16) == USBD_BUSY);
80006bc: bf00 nop
80006be: f107 030c add.w r3, r7, #12
80006c2: 2110 movs r1, #16
80006c4: 4618 mov r0, r3
80006c6: f00b fb63 bl 800bd90 <CDC_Transmit_FS>
80006ca: 4603 mov r3, r0
80006cc: 2b01 cmp r3, #1
80006ce: d0f6 beq.n 80006be <manageCDC+0x2c2>
break;
80006d0: e364 b.n 8000d9c <manageCDC+0x9a0>
80006d2: bf00 nop
80006d4: 2000022c .word 0x2000022c
80006d8: 20000230 .word 0x20000230
80006dc: 0800cec4 .word 0x0800cec4
80006e0: 20000308 .word 0x20000308
80006e4: 20000350 .word 0x20000350
80006e8: 0800cecc .word 0x0800cecc
80006ec: 0800cee4 .word 0x0800cee4
80006f0: 200003e0 .word 0x200003e0
80006f4: 20000222 .word 0x20000222
80006f8: 20000224 .word 0x20000224
80006fc: 20000226 .word 0x20000226
8000700: 20000228 .word 0x20000228
8000704: 2000022a .word 0x2000022a
8000708: 0800cf18 .word 0x0800cf18
800070c: 2000041d .word 0x2000041d
8000710: 2000041c .word 0x2000041c
8000714: 0800cf50 .word 0x0800cf50
8000718: 0800cf70 .word 0x0800cf70
800071c: 0800cf7c .word 0x0800cf7c
}
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
8000720: 4bb4 ldr r3, [pc, #720] @ (80009f4 <manageCDC+0x5f8>)
8000722: 78db ldrb r3, [r3, #3]
8000724: 2b2f cmp r3, #47 @ 0x2f
8000726: f240 80a1 bls.w 800086c <manageCDC+0x470>
800072a: 4bb2 ldr r3, [pc, #712] @ (80009f4 <manageCDC+0x5f8>)
800072c: 78db ldrb r3, [r3, #3]
800072e: 2b39 cmp r3, #57 @ 0x39
8000730: f200 809c bhi.w 800086c <manageCDC+0x470>
8000734: 4baf ldr r3, [pc, #700] @ (80009f4 <manageCDC+0x5f8>)
8000736: 791b ldrb r3, [r3, #4]
8000738: 2b2f cmp r3, #47 @ 0x2f
800073a: f240 8097 bls.w 800086c <manageCDC+0x470>
800073e: 4bad ldr r3, [pc, #692] @ (80009f4 <manageCDC+0x5f8>)
8000740: 791b ldrb r3, [r3, #4]
8000742: 2b39 cmp r3, #57 @ 0x39
8000744: f200 8092 bhi.w 800086c <manageCDC+0x470>
8000748: 4baa ldr r3, [pc, #680] @ (80009f4 <manageCDC+0x5f8>)
800074a: 795b ldrb r3, [r3, #5]
800074c: 2b2f cmp r3, #47 @ 0x2f
800074e: f240 808d bls.w 800086c <manageCDC+0x470>
8000752: 4ba8 ldr r3, [pc, #672] @ (80009f4 <manageCDC+0x5f8>)
8000754: 795b ldrb r3, [r3, #5]
8000756: 2b39 cmp r3, #57 @ 0x39
8000758: f200 8088 bhi.w 800086c <manageCDC+0x470>
800075c: 4ba5 ldr r3, [pc, #660] @ (80009f4 <manageCDC+0x5f8>)
800075e: 799b ldrb r3, [r3, #6]
8000760: 2b2f cmp r3, #47 @ 0x2f
8000762: f240 8083 bls.w 800086c <manageCDC+0x470>
8000766: 4ba3 ldr r3, [pc, #652] @ (80009f4 <manageCDC+0x5f8>)
8000768: 799b ldrb r3, [r3, #6]
800076a: 2b39 cmp r3, #57 @ 0x39
800076c: d87e bhi.n 800086c <manageCDC+0x470>
800076e: 4ba1 ldr r3, [pc, #644] @ (80009f4 <manageCDC+0x5f8>)
8000770: 79db ldrb r3, [r3, #7]
8000772: 2b2f cmp r3, #47 @ 0x2f
8000774: d97a bls.n 800086c <manageCDC+0x470>
8000776: 4b9f ldr r3, [pc, #636] @ (80009f4 <manageCDC+0x5f8>)
8000778: 79db ldrb r3, [r3, #7]
800077a: 2b39 cmp r3, #57 @ 0x39
800077c: d876 bhi.n 800086c <manageCDC+0x470>
dm=rxbuf[3]-='0';
800077e: 4b9d ldr r3, [pc, #628] @ (80009f4 <manageCDC+0x5f8>)
8000780: 78db ldrb r3, [r3, #3]
8000782: 3b30 subs r3, #48 @ 0x30
8000784: b2da uxtb r2, r3
8000786: 4b9b ldr r3, [pc, #620] @ (80009f4 <manageCDC+0x5f8>)
8000788: 70da strb r2, [r3, #3]
800078a: 4b9a ldr r3, [pc, #616] @ (80009f4 <manageCDC+0x5f8>)
800078c: 78db ldrb r3, [r3, #3]
800078e: f887 3076 strb.w r3, [r7, #118] @ 0x76
m=rxbuf[4]-='0';
8000792: 4b98 ldr r3, [pc, #608] @ (80009f4 <manageCDC+0x5f8>)
8000794: 791b ldrb r3, [r3, #4]
8000796: 3b30 subs r3, #48 @ 0x30
8000798: b2da uxtb r2, r3
800079a: 4b96 ldr r3, [pc, #600] @ (80009f4 <manageCDC+0x5f8>)
800079c: 711a strb r2, [r3, #4]
800079e: 4b95 ldr r3, [pc, #596] @ (80009f4 <manageCDC+0x5f8>)
80007a0: 791b ldrb r3, [r3, #4]
80007a2: f887 3075 strb.w r3, [r7, #117] @ 0x75
c=rxbuf[5]-='0';
80007a6: 4b93 ldr r3, [pc, #588] @ (80009f4 <manageCDC+0x5f8>)
80007a8: 795b ldrb r3, [r3, #5]
80007aa: 3b30 subs r3, #48 @ 0x30
80007ac: b2da uxtb r2, r3
80007ae: 4b91 ldr r3, [pc, #580] @ (80009f4 <manageCDC+0x5f8>)
80007b0: 715a strb r2, [r3, #5]
80007b2: 4b90 ldr r3, [pc, #576] @ (80009f4 <manageCDC+0x5f8>)
80007b4: 795b ldrb r3, [r3, #5]
80007b6: f887 3074 strb.w r3, [r7, #116] @ 0x74
d=rxbuf[6]-='0';
80007ba: 4b8e ldr r3, [pc, #568] @ (80009f4 <manageCDC+0x5f8>)
80007bc: 799b ldrb r3, [r3, #6]
80007be: 3b30 subs r3, #48 @ 0x30
80007c0: b2da uxtb r2, r3
80007c2: 4b8c ldr r3, [pc, #560] @ (80009f4 <manageCDC+0x5f8>)
80007c4: 719a strb r2, [r3, #6]
80007c6: 4b8b ldr r3, [pc, #556] @ (80009f4 <manageCDC+0x5f8>)
80007c8: 799b ldrb r3, [r3, #6]
80007ca: f887 3073 strb.w r3, [r7, #115] @ 0x73
u=rxbuf[7]-='0';
80007ce: 4b89 ldr r3, [pc, #548] @ (80009f4 <manageCDC+0x5f8>)
80007d0: 79db ldrb r3, [r3, #7]
80007d2: 3b30 subs r3, #48 @ 0x30
80007d4: b2da uxtb r2, r3
80007d6: 4b87 ldr r3, [pc, #540] @ (80009f4 <manageCDC+0x5f8>)
80007d8: 71da strb r2, [r3, #7]
80007da: 4b86 ldr r3, [pc, #536] @ (80009f4 <manageCDC+0x5f8>)
80007dc: 79db ldrb r3, [r3, #7]
80007de: f887 3072 strb.w r3, [r7, #114] @ 0x72
val=dm;
80007e2: f897 3076 ldrb.w r3, [r7, #118] @ 0x76
80007e6: b29b uxth r3, r3
80007e8: 817b strh r3, [r7, #10]
val*=10;
80007ea: 897b ldrh r3, [r7, #10]
80007ec: 461a mov r2, r3
80007ee: 0092 lsls r2, r2, #2
80007f0: 4413 add r3, r2
80007f2: 005b lsls r3, r3, #1
80007f4: b29b uxth r3, r3
80007f6: 817b strh r3, [r7, #10]
val+=m;
80007f8: f897 3075 ldrb.w r3, [r7, #117] @ 0x75
80007fc: b29a uxth r2, r3
80007fe: 897b ldrh r3, [r7, #10]
8000800: 4413 add r3, r2
8000802: b29b uxth r3, r3
8000804: 817b strh r3, [r7, #10]
val*=10;
8000806: 897b ldrh r3, [r7, #10]
8000808: 461a mov r2, r3
800080a: 0092 lsls r2, r2, #2
800080c: 4413 add r3, r2
800080e: 005b lsls r3, r3, #1
8000810: b29b uxth r3, r3
8000812: 817b strh r3, [r7, #10]
val+=c;
8000814: f897 3074 ldrb.w r3, [r7, #116] @ 0x74
8000818: b29a uxth r2, r3
800081a: 897b ldrh r3, [r7, #10]
800081c: 4413 add r3, r2
800081e: b29b uxth r3, r3
8000820: 817b strh r3, [r7, #10]
val*=10;
8000822: 897b ldrh r3, [r7, #10]
8000824: 461a mov r2, r3
8000826: 0092 lsls r2, r2, #2
8000828: 4413 add r3, r2
800082a: 005b lsls r3, r3, #1
800082c: b29b uxth r3, r3
800082e: 817b strh r3, [r7, #10]
val+=d;
8000830: f897 3073 ldrb.w r3, [r7, #115] @ 0x73
8000834: b29a uxth r2, r3
8000836: 897b ldrh r3, [r7, #10]
8000838: 4413 add r3, r2
800083a: b29b uxth r3, r3
800083c: 817b strh r3, [r7, #10]
val*=10;
800083e: 897b ldrh r3, [r7, #10]
8000840: 461a mov r2, r3
8000842: 0092 lsls r2, r2, #2
8000844: 4413 add r3, r2
8000846: 005b lsls r3, r3, #1
8000848: b29b uxth r3, r3
800084a: 817b strh r3, [r7, #10]
val+=u;
800084c: f897 3072 ldrb.w r3, [r7, #114] @ 0x72
8000850: b29a uxth r2, r3
8000852: 897b ldrh r3, [r7, #10]
8000854: 4413 add r3, r2
8000856: b29b uxth r3, r3
8000858: 817b strh r3, [r7, #10]
SetMot(mot,dir,val);
800085a: 897a ldrh r2, [r7, #10]
800085c: f897 107f ldrb.w r1, [r7, #127] @ 0x7f
8000860: f897 3077 ldrb.w r3, [r7, #119] @ 0x77
8000864: 4618 mov r0, r3
8000866: f002 f805 bl 8002874 <SetMot>
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
800086a: e032 b.n 80008d2 <manageCDC+0x4d6>
}else{
sprintf((char*)s,"\n?mnsvvvvv 00000>=vvvvv<=99999");//m nmotore senso valore
800086c: f107 030c add.w r3, r7, #12
8000870: 4961 ldr r1, [pc, #388] @ (80009f8 <manageCDC+0x5fc>)
8000872: 4618 mov r0, r3
8000874: f00b fe6a bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
8000878: bf00 nop
800087a: f107 030c add.w r3, r7, #12
800087e: 2113 movs r1, #19
8000880: 4618 mov r0, r3
8000882: f00b fa85 bl 800bd90 <CDC_Transmit_FS>
8000886: 4603 mov r3, r0
8000888: 2b01 cmp r3, #1
800088a: d0f6 beq.n 800087a <manageCDC+0x47e>
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
800088c: e021 b.n 80008d2 <manageCDC+0x4d6>
}
}else{
sprintf((char*)s,"\n?mnsvvvvv 1>=m<=4");//m nmotore senso valore
800088e: f107 030c add.w r3, r7, #12
8000892: 495a ldr r1, [pc, #360] @ (80009fc <manageCDC+0x600>)
8000894: 4618 mov r0, r3
8000896: f00b fe59 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
800089a: bf00 nop
800089c: f107 030c add.w r3, r7, #12
80008a0: 2113 movs r1, #19
80008a2: 4618 mov r0, r3
80008a4: f00b fa74 bl 800bd90 <CDC_Transmit_FS>
80008a8: 4603 mov r3, r0
80008aa: 2b01 cmp r3, #1
80008ac: d0f6 beq.n 800089c <manageCDC+0x4a0>
}
}else{
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
}
break;
80008ae: e275 b.n 8000d9c <manageCDC+0x9a0>
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
80008b0: f107 030c add.w r3, r7, #12
80008b4: 4952 ldr r1, [pc, #328] @ (8000a00 <manageCDC+0x604>)
80008b6: 4618 mov r0, r3
80008b8: f00b fe48 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
80008bc: bf00 nop
80008be: f107 030c add.w r3, r7, #12
80008c2: 210a movs r1, #10
80008c4: 4618 mov r0, r3
80008c6: f00b fa63 bl 800bd90 <CDC_Transmit_FS>
80008ca: 4603 mov r3, r0
80008cc: 2b01 cmp r3, #1
80008ce: d0f6 beq.n 80008be <manageCDC+0x4c2>
break;
80008d0: e264 b.n 8000d9c <manageCDC+0x9a0>
80008d2: e263 b.n 8000d9c <manageCDC+0x9a0>
case 'e':
if(rxidx>1){
80008d4: 4b4b ldr r3, [pc, #300] @ (8000a04 <manageCDC+0x608>)
80008d6: 781b ldrb r3, [r3, #0]
80008d8: 2b01 cmp r3, #1
80008da: f240 8235 bls.w 8000d48 <manageCDC+0x94c>
if(rxbuf[1]=='r'){
80008de: 4b45 ldr r3, [pc, #276] @ (80009f4 <manageCDC+0x5f8>)
80008e0: 785b ldrb r3, [r3, #1]
80008e2: 2b72 cmp r3, #114 @ 0x72
80008e4: f040 8098 bne.w 8000a18 <manageCDC+0x61c>
if(rxidx==4){
80008e8: 4b46 ldr r3, [pc, #280] @ (8000a04 <manageCDC+0x608>)
80008ea: 781b ldrb r3, [r3, #0]
80008ec: 2b04 cmp r3, #4
80008ee: d169 bne.n 80009c4 <manageCDC+0x5c8>
if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){
80008f0: 4b40 ldr r3, [pc, #256] @ (80009f4 <manageCDC+0x5f8>)
80008f2: 789a ldrb r2, [r3, #2]
80008f4: 4b3f ldr r3, [pc, #252] @ (80009f4 <manageCDC+0x5f8>)
80008f6: 78d9 ldrb r1, [r3, #3]
80008f8: f107 0308 add.w r3, r7, #8
80008fc: 9300 str r3, [sp, #0]
80008fe: 460b mov r3, r1
8000900: 2130 movs r1, #48 @ 0x30
8000902: 2030 movs r0, #48 @ 0x30
8000904: f7ff fcdf bl 80002c6 <toHex>
8000908: 4603 mov r3, r0
800090a: 2b00 cmp r3, #0
800090c: d042 beq.n 8000994 <manageCDC+0x598>
st=EEW_Read(eeadd, &val);
800090e: 893b ldrh r3, [r7, #8]
8000910: b2db uxtb r3, r3
8000912: f107 020a add.w r2, r7, #10
8000916: 4611 mov r1, r2
8000918: 4618 mov r0, r3
800091a: f7ff fcab bl 8000274 <EEW_Read>
800091e: 4603 mov r3, r0
8000920: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK){
8000924: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000928: 2b00 cmp r3, #0
800092a: d119 bne.n 8000960 <manageCDC+0x564>
sprintf((char*)s,"\nee 0x%02x=0x%04x",eeadd,val);
800092c: 893b ldrh r3, [r7, #8]
800092e: 461a mov r2, r3
8000930: 897b ldrh r3, [r7, #10]
8000932: f107 000c add.w r0, r7, #12
8000936: 4934 ldr r1, [pc, #208] @ (8000a08 <manageCDC+0x60c>)
8000938: f00b fe08 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
800093c: bf00 nop
800093e: f107 030c add.w r3, r7, #12
8000942: 4618 mov r0, r3
8000944: f7ff fc02 bl 800014c <strlen>
8000948: 4603 mov r3, r0
800094a: b29a uxth r2, r3
800094c: f107 030c add.w r3, r7, #12
8000950: 4611 mov r1, r2
8000952: 4618 mov r0, r3
8000954: f00b fa1c bl 800bd90 <CDC_Transmit_FS>
8000958: 4603 mov r3, r0
800095a: 2b01 cmp r3, #1
800095c: d0ef beq.n 800093e <manageCDC+0x542>
}
}else{
sprintf((char*)s,"\n?eraa | ewaavvvv");
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
}
break;
800095e: e21c b.n 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\nee read error %d",st);
8000960: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000964: f107 030c add.w r3, r7, #12
8000968: 4928 ldr r1, [pc, #160] @ (8000a0c <manageCDC+0x610>)
800096a: 4618 mov r0, r3
800096c: f00b fdee bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000970: bf00 nop
8000972: f107 030c add.w r3, r7, #12
8000976: 4618 mov r0, r3
8000978: f7ff fbe8 bl 800014c <strlen>
800097c: 4603 mov r3, r0
800097e: b29a uxth r2, r3
8000980: f107 030c add.w r3, r7, #12
8000984: 4611 mov r1, r2
8000986: 4618 mov r0, r3
8000988: f00b fa02 bl 800bd90 <CDC_Transmit_FS>
800098c: 4603 mov r3, r0
800098e: 2b01 cmp r3, #1
8000990: d0ef beq.n 8000972 <manageCDC+0x576>
break;
8000992: e202 b.n 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\n?eraa hex values");
8000994: f107 030c add.w r3, r7, #12
8000998: 491d ldr r1, [pc, #116] @ (8000a10 <manageCDC+0x614>)
800099a: 4618 mov r0, r3
800099c: f00b fdd6 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
80009a0: bf00 nop
80009a2: f107 030c add.w r3, r7, #12
80009a6: 4618 mov r0, r3
80009a8: f7ff fbd0 bl 800014c <strlen>
80009ac: 4603 mov r3, r0
80009ae: b29a uxth r2, r3
80009b0: f107 030c add.w r3, r7, #12
80009b4: 4611 mov r1, r2
80009b6: 4618 mov r0, r3
80009b8: f00b f9ea bl 800bd90 <CDC_Transmit_FS>
80009bc: 4603 mov r3, r0
80009be: 2b01 cmp r3, #1
80009c0: d0ef beq.n 80009a2 <manageCDC+0x5a6>
break;
80009c2: e1ea b.n 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\n?eraa");
80009c4: f107 030c add.w r3, r7, #12
80009c8: 4912 ldr r1, [pc, #72] @ (8000a14 <manageCDC+0x618>)
80009ca: 4618 mov r0, r3
80009cc: f00b fdbe bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
80009d0: bf00 nop
80009d2: f107 030c add.w r3, r7, #12
80009d6: 4618 mov r0, r3
80009d8: f7ff fbb8 bl 800014c <strlen>
80009dc: 4603 mov r3, r0
80009de: b29a uxth r2, r3
80009e0: f107 030c add.w r3, r7, #12
80009e4: 4611 mov r1, r2
80009e6: 4618 mov r0, r3
80009e8: f00b f9d2 bl 800bd90 <CDC_Transmit_FS>
80009ec: 4603 mov r3, r0
80009ee: 2b01 cmp r3, #1
80009f0: d0ef beq.n 80009d2 <manageCDC+0x5d6>
break;
80009f2: e1d2 b.n 8000d9a <manageCDC+0x99e>
80009f4: 20000230 .word 0x20000230
80009f8: 0800cf90 .word 0x0800cf90
80009fc: 0800cfb0 .word 0x0800cfb0
8000a00: 0800cfc4 .word 0x0800cfc4
8000a04: 2000022c .word 0x2000022c
8000a08: 0800cfd0 .word 0x0800cfd0
8000a0c: 0800cfe4 .word 0x0800cfe4
8000a10: 0800cff8 .word 0x0800cff8
8000a14: 0800d00c .word 0x0800d00c
}else if(rxbuf[1]=='w'){
8000a18: 4bbd ldr r3, [pc, #756] @ (8000d10 <manageCDC+0x914>)
8000a1a: 785b ldrb r3, [r3, #1]
8000a1c: 2b77 cmp r3, #119 @ 0x77
8000a1e: d169 bne.n 8000af4 <manageCDC+0x6f8>
if(rxidx==8){
8000a20: 4bbc ldr r3, [pc, #752] @ (8000d14 <manageCDC+0x918>)
8000a22: 781b ldrb r3, [r3, #0]
8000a24: 2b08 cmp r3, #8
8000a26: d14d bne.n 8000ac4 <manageCDC+0x6c8>
if(toHex('0','0',rxbuf[2],rxbuf[3],&eeadd)){
8000a28: 4bb9 ldr r3, [pc, #740] @ (8000d10 <manageCDC+0x914>)
8000a2a: 789a ldrb r2, [r3, #2]
8000a2c: 4bb8 ldr r3, [pc, #736] @ (8000d10 <manageCDC+0x914>)
8000a2e: 78d9 ldrb r1, [r3, #3]
8000a30: f107 0308 add.w r3, r7, #8
8000a34: 9300 str r3, [sp, #0]
8000a36: 460b mov r3, r1
8000a38: 2130 movs r1, #48 @ 0x30
8000a3a: 2030 movs r0, #48 @ 0x30
8000a3c: f7ff fc43 bl 80002c6 <toHex>
8000a40: 4603 mov r3, r0
8000a42: 2b00 cmp r3, #0
8000a44: d037 beq.n 8000ab6 <manageCDC+0x6ba>
if(toHex(rxbuf[4],rxbuf[5],rxbuf[6],rxbuf[7],&val)){
8000a46: 4bb2 ldr r3, [pc, #712] @ (8000d10 <manageCDC+0x914>)
8000a48: 7918 ldrb r0, [r3, #4]
8000a4a: 4bb1 ldr r3, [pc, #708] @ (8000d10 <manageCDC+0x914>)
8000a4c: 7959 ldrb r1, [r3, #5]
8000a4e: 4bb0 ldr r3, [pc, #704] @ (8000d10 <manageCDC+0x914>)
8000a50: 799a ldrb r2, [r3, #6]
8000a52: 4baf ldr r3, [pc, #700] @ (8000d10 <manageCDC+0x914>)
8000a54: 79dc ldrb r4, [r3, #7]
8000a56: f107 030a add.w r3, r7, #10
8000a5a: 9300 str r3, [sp, #0]
8000a5c: 4623 mov r3, r4
8000a5e: f7ff fc32 bl 80002c6 <toHex>
8000a62: 4603 mov r3, r0
8000a64: 2b00 cmp r3, #0
8000a66: d01f beq.n 8000aa8 <manageCDC+0x6ac>
st=EEW_Write(eeadd, val);
8000a68: 893b ldrh r3, [r7, #8]
8000a6a: b2db uxtb r3, r3
8000a6c: 897a ldrh r2, [r7, #10]
8000a6e: 4611 mov r1, r2
8000a70: 4618 mov r0, r3
8000a72: f7ff fc12 bl 800029a <EEW_Write>
8000a76: 4603 mov r3, r0
8000a78: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK)sprintf((char*)s,"\ndone 0x%02x=0x%04x",eeadd,val);
8000a7c: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000a80: 2b00 cmp r3, #0
8000a82: d108 bne.n 8000a96 <manageCDC+0x69a>
8000a84: 893b ldrh r3, [r7, #8]
8000a86: 461a mov r2, r3
8000a88: 897b ldrh r3, [r7, #10]
8000a8a: f107 000c add.w r0, r7, #12
8000a8e: 49a2 ldr r1, [pc, #648] @ (8000d18 <manageCDC+0x91c>)
8000a90: f00b fd5c bl 800c54c <siprintf>
8000a94: e01c b.n 8000ad0 <manageCDC+0x6d4>
else sprintf((char*)s,"\nee write error %d", st);
8000a96: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000a9a: f107 030c add.w r3, r7, #12
8000a9e: 499f ldr r1, [pc, #636] @ (8000d1c <manageCDC+0x920>)
8000aa0: 4618 mov r0, r3
8000aa2: f00b fd53 bl 800c54c <siprintf>
8000aa6: e013 b.n 8000ad0 <manageCDC+0x6d4>
}else sprintf((char*)s,"\n?ewaavvvv hex values");
8000aa8: f107 030c add.w r3, r7, #12
8000aac: 499c ldr r1, [pc, #624] @ (8000d20 <manageCDC+0x924>)
8000aae: 4618 mov r0, r3
8000ab0: f00b fd4c bl 800c54c <siprintf>
8000ab4: e00c b.n 8000ad0 <manageCDC+0x6d4>
}else sprintf((char*)s,"\n?ewaa hex values");
8000ab6: f107 030c add.w r3, r7, #12
8000aba: 499a ldr r1, [pc, #616] @ (8000d24 <manageCDC+0x928>)
8000abc: 4618 mov r0, r3
8000abe: f00b fd45 bl 800c54c <siprintf>
8000ac2: e005 b.n 8000ad0 <manageCDC+0x6d4>
}else sprintf((char*)s,"\n?ewaavvvv");
8000ac4: f107 030c add.w r3, r7, #12
8000ac8: 4997 ldr r1, [pc, #604] @ (8000d28 <manageCDC+0x92c>)
8000aca: 4618 mov r0, r3
8000acc: f00b fd3e bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000ad0: bf00 nop
8000ad2: f107 030c add.w r3, r7, #12
8000ad6: 4618 mov r0, r3
8000ad8: f7ff fb38 bl 800014c <strlen>
8000adc: 4603 mov r3, r0
8000ade: b29a uxth r2, r3
8000ae0: f107 030c add.w r3, r7, #12
8000ae4: 4611 mov r1, r2
8000ae6: 4618 mov r0, r3
8000ae8: f00b f952 bl 800bd90 <CDC_Transmit_FS>
8000aec: 4603 mov r3, r0
8000aee: 2b01 cmp r3, #1
8000af0: d0ef beq.n 8000ad2 <manageCDC+0x6d6>
break;
8000af2: e152 b.n 8000d9a <manageCDC+0x99e>
}else if(rxbuf[1]=='d'){
8000af4: 4b86 ldr r3, [pc, #536] @ (8000d10 <manageCDC+0x914>)
8000af6: 785b ldrb r3, [r3, #1]
8000af8: 2b64 cmp r3, #100 @ 0x64
8000afa: f040 808b bne.w 8000c14 <manageCDC+0x818>
if(rxidx==2){
8000afe: 4b85 ldr r3, [pc, #532] @ (8000d14 <manageCDC+0x918>)
8000b00: 781b ldrb r3, [r3, #0]
8000b02: 2b02 cmp r3, #2
8000b04: d16e bne.n 8000be4 <manageCDC+0x7e8>
for(i=0;i<32;i++){
8000b06: 2300 movs r3, #0
8000b08: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000b0c: e046 b.n 8000b9c <manageCDC+0x7a0>
st=EEW_Read(i, &val);
8000b0e: f107 020a add.w r2, r7, #10
8000b12: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000b16: 4611 mov r1, r2
8000b18: 4618 mov r0, r3
8000b1a: f7ff fbab bl 8000274 <EEW_Read>
8000b1e: 4603 mov r3, r0
8000b20: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK){
8000b24: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000b28: 2b00 cmp r3, #0
8000b2a: d119 bne.n 8000b60 <manageCDC+0x764>
sprintf((char*)s,"0x%02x=0x%04x ",i,val);
8000b2c: f897 207e ldrb.w r2, [r7, #126] @ 0x7e
8000b30: 897b ldrh r3, [r7, #10]
8000b32: f107 000c add.w r0, r7, #12
8000b36: 497d ldr r1, [pc, #500] @ (8000d2c <manageCDC+0x930>)
8000b38: f00b fd08 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b3c: bf00 nop
8000b3e: f107 030c add.w r3, r7, #12
8000b42: 4618 mov r0, r3
8000b44: f7ff fb02 bl 800014c <strlen>
8000b48: 4603 mov r3, r0
8000b4a: b29a uxth r2, r3
8000b4c: f107 030c add.w r3, r7, #12
8000b50: 4611 mov r1, r2
8000b52: 4618 mov r0, r3
8000b54: f00b f91c bl 800bd90 <CDC_Transmit_FS>
8000b58: 4603 mov r3, r0
8000b5a: 2b01 cmp r3, #1
8000b5c: d0ef beq.n 8000b3e <manageCDC+0x742>
8000b5e: e018 b.n 8000b92 <manageCDC+0x796>
sprintf((char*)s,"rderr %d ",st);
8000b60: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000b64: f107 030c add.w r3, r7, #12
8000b68: 4971 ldr r1, [pc, #452] @ (8000d30 <manageCDC+0x934>)
8000b6a: 4618 mov r0, r3
8000b6c: f00b fcee bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000b70: bf00 nop
8000b72: f107 030c add.w r3, r7, #12
8000b76: 4618 mov r0, r3
8000b78: f7ff fae8 bl 800014c <strlen>
8000b7c: 4603 mov r3, r0
8000b7e: b29a uxth r2, r3
8000b80: f107 030c add.w r3, r7, #12
8000b84: 4611 mov r1, r2
8000b86: 4618 mov r0, r3
8000b88: f00b f902 bl 800bd90 <CDC_Transmit_FS>
8000b8c: 4603 mov r3, r0
8000b8e: 2b01 cmp r3, #1
8000b90: d0ef beq.n 8000b72 <manageCDC+0x776>
for(i=0;i<32;i++){
8000b92: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000b96: 3301 adds r3, #1
8000b98: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000b9c: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000ba0: 2b1f cmp r3, #31
8000ba2: d9b4 bls.n 8000b0e <manageCDC+0x712>
if((i%4)==0){
8000ba4: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000ba8: f003 0303 and.w r3, r3, #3
8000bac: b2db uxtb r3, r3
8000bae: 2b00 cmp r3, #0
8000bb0: f040 80f3 bne.w 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\n");
8000bb4: f107 030c add.w r3, r7, #12
8000bb8: 495e ldr r1, [pc, #376] @ (8000d34 <manageCDC+0x938>)
8000bba: 4618 mov r0, r3
8000bbc: f00b fcc6 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000bc0: bf00 nop
8000bc2: f107 030c add.w r3, r7, #12
8000bc6: 4618 mov r0, r3
8000bc8: f7ff fac0 bl 800014c <strlen>
8000bcc: 4603 mov r3, r0
8000bce: b29a uxth r2, r3
8000bd0: f107 030c add.w r3, r7, #12
8000bd4: 4611 mov r1, r2
8000bd6: 4618 mov r0, r3
8000bd8: f00b f8da bl 800bd90 <CDC_Transmit_FS>
8000bdc: 4603 mov r3, r0
8000bde: 2b01 cmp r3, #1
8000be0: d0ef beq.n 8000bc2 <manageCDC+0x7c6>
break;
8000be2: e0da b.n 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\n?ed");
8000be4: f107 030c add.w r3, r7, #12
8000be8: 4953 ldr r1, [pc, #332] @ (8000d38 <manageCDC+0x93c>)
8000bea: 4618 mov r0, r3
8000bec: f00b fcae bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000bf0: bf00 nop
8000bf2: f107 030c add.w r3, r7, #12
8000bf6: 4618 mov r0, r3
8000bf8: f7ff faa8 bl 800014c <strlen>
8000bfc: 4603 mov r3, r0
8000bfe: b29a uxth r2, r3
8000c00: f107 030c add.w r3, r7, #12
8000c04: 4611 mov r1, r2
8000c06: 4618 mov r0, r3
8000c08: f00b f8c2 bl 800bd90 <CDC_Transmit_FS>
8000c0c: 4603 mov r3, r0
8000c0e: 2b01 cmp r3, #1
8000c10: d0ef beq.n 8000bf2 <manageCDC+0x7f6>
break;
8000c12: e0c2 b.n 8000d9a <manageCDC+0x99e>
}else if(rxbuf[1]=='x'){
8000c14: 4b3e ldr r3, [pc, #248] @ (8000d10 <manageCDC+0x914>)
8000c16: 785b ldrb r3, [r3, #1]
8000c18: 2b78 cmp r3, #120 @ 0x78
8000c1a: d160 bne.n 8000cde <manageCDC+0x8e2>
if(rxidx==2){
8000c1c: 4b3d ldr r3, [pc, #244] @ (8000d14 <manageCDC+0x918>)
8000c1e: 781b ldrb r3, [r3, #0]
8000c20: 2b02 cmp r3, #2
8000c22: d144 bne.n 8000cae <manageCDC+0x8b2>
for(i=0;i<32;i++){
8000c24: 2300 movs r3, #0
8000c26: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000c2a: e03b b.n 8000ca4 <manageCDC+0x8a8>
st=EEW_Write(i,deftab[i]);
8000c2c: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000c30: 4a42 ldr r2, [pc, #264] @ (8000d3c <manageCDC+0x940>)
8000c32: 5cd3 ldrb r3, [r2, r3]
8000c34: 461a mov r2, r3
8000c36: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000c3a: 4611 mov r1, r2
8000c3c: 4618 mov r0, r3
8000c3e: f7ff fb2c bl 800029a <EEW_Write>
8000c42: 4603 mov r3, r0
8000c44: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
if (st == EE_OK)sprintf((char*)s,"\ndone 0x%02x=0x%04x",i,deftab[i]);
8000c48: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
8000c4c: 2b00 cmp r3, #0
8000c4e: d10b bne.n 8000c68 <manageCDC+0x86c>
8000c50: f897 207e ldrb.w r2, [r7, #126] @ 0x7e
8000c54: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000c58: 4938 ldr r1, [pc, #224] @ (8000d3c <manageCDC+0x940>)
8000c5a: 5ccb ldrb r3, [r1, r3]
8000c5c: f107 000c add.w r0, r7, #12
8000c60: 492d ldr r1, [pc, #180] @ (8000d18 <manageCDC+0x91c>)
8000c62: f00b fc73 bl 800c54c <siprintf>
8000c66: e007 b.n 8000c78 <manageCDC+0x87c>
else sprintf((char*)s,"\nee write error %d", st);
8000c68: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
8000c6c: f107 030c add.w r3, r7, #12
8000c70: 492a ldr r1, [pc, #168] @ (8000d1c <manageCDC+0x920>)
8000c72: 4618 mov r0, r3
8000c74: f00b fc6a bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000c78: bf00 nop
8000c7a: f107 030c add.w r3, r7, #12
8000c7e: 4618 mov r0, r3
8000c80: f7ff fa64 bl 800014c <strlen>
8000c84: 4603 mov r3, r0
8000c86: b29a uxth r2, r3
8000c88: f107 030c add.w r3, r7, #12
8000c8c: 4611 mov r1, r2
8000c8e: 4618 mov r0, r3
8000c90: f00b f87e bl 800bd90 <CDC_Transmit_FS>
8000c94: 4603 mov r3, r0
8000c96: 2b01 cmp r3, #1
8000c98: d0ef beq.n 8000c7a <manageCDC+0x87e>
for(i=0;i<32;i++){
8000c9a: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000c9e: 3301 adds r3, #1
8000ca0: f887 307e strb.w r3, [r7, #126] @ 0x7e
8000ca4: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
8000ca8: 2b1f cmp r3, #31
8000caa: d9bf bls.n 8000c2c <manageCDC+0x830>
break;
8000cac: e075 b.n 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\n?ex");
8000cae: f107 030c add.w r3, r7, #12
8000cb2: 4923 ldr r1, [pc, #140] @ (8000d40 <manageCDC+0x944>)
8000cb4: 4618 mov r0, r3
8000cb6: f00b fc49 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000cba: bf00 nop
8000cbc: f107 030c add.w r3, r7, #12
8000cc0: 4618 mov r0, r3
8000cc2: f7ff fa43 bl 800014c <strlen>
8000cc6: 4603 mov r3, r0
8000cc8: b29a uxth r2, r3
8000cca: f107 030c add.w r3, r7, #12
8000cce: 4611 mov r1, r2
8000cd0: 4618 mov r0, r3
8000cd2: f00b f85d bl 800bd90 <CDC_Transmit_FS>
8000cd6: 4603 mov r3, r0
8000cd8: 2b01 cmp r3, #1
8000cda: d0ef beq.n 8000cbc <manageCDC+0x8c0>
break;
8000cdc: e05d b.n 8000d9a <manageCDC+0x99e>
sprintf((char*)s,"\n?er|w|d|x");
8000cde: f107 030c add.w r3, r7, #12
8000ce2: 4918 ldr r1, [pc, #96] @ (8000d44 <manageCDC+0x948>)
8000ce4: 4618 mov r0, r3
8000ce6: f00b fc31 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000cea: bf00 nop
8000cec: f107 030c add.w r3, r7, #12
8000cf0: 4618 mov r0, r3
8000cf2: f7ff fa2b bl 800014c <strlen>
8000cf6: 4603 mov r3, r0
8000cf8: b29a uxth r2, r3
8000cfa: f107 030c add.w r3, r7, #12
8000cfe: 4611 mov r1, r2
8000d00: 4618 mov r0, r3
8000d02: f00b f845 bl 800bd90 <CDC_Transmit_FS>
8000d06: 4603 mov r3, r0
8000d08: 2b01 cmp r3, #1
8000d0a: d0ef beq.n 8000cec <manageCDC+0x8f0>
break;
8000d0c: e045 b.n 8000d9a <manageCDC+0x99e>
8000d0e: bf00 nop
8000d10: 20000230 .word 0x20000230
8000d14: 2000022c .word 0x2000022c
8000d18: 0800d014 .word 0x0800d014
8000d1c: 0800d028 .word 0x0800d028
8000d20: 0800d03c .word 0x0800d03c
8000d24: 0800d054 .word 0x0800d054
8000d28: 0800d068 .word 0x0800d068
8000d2c: 0800d074 .word 0x0800d074
8000d30: 0800d084 .word 0x0800d084
8000d34: 0800d090 .word 0x0800d090
8000d38: 0800d094 .word 0x0800d094
8000d3c: 0800d110 .word 0x0800d110
8000d40: 0800d09c .word 0x0800d09c
8000d44: 0800d0a4 .word 0x0800d0a4
sprintf((char*)s,"\n?eraa | ewaavvvv");
8000d48: f107 030c add.w r3, r7, #12
8000d4c: 491b ldr r1, [pc, #108] @ (8000dbc <manageCDC+0x9c0>)
8000d4e: 4618 mov r0, r3
8000d50: f00b fbfc bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
8000d54: bf00 nop
8000d56: f107 030c add.w r3, r7, #12
8000d5a: 4618 mov r0, r3
8000d5c: f7ff f9f6 bl 800014c <strlen>
8000d60: 4603 mov r3, r0
8000d62: b29a uxth r2, r3
8000d64: f107 030c add.w r3, r7, #12
8000d68: 4611 mov r1, r2
8000d6a: 4618 mov r0, r3
8000d6c: f00b f810 bl 800bd90 <CDC_Transmit_FS>
8000d70: 4603 mov r3, r0
8000d72: 2b01 cmp r3, #1
8000d74: d0ef beq.n 8000d56 <manageCDC+0x95a>
break;
8000d76: e010 b.n 8000d9a <manageCDC+0x99e>
default:
sprintf((char*)s,"\n?");
8000d78: f107 030c add.w r3, r7, #12
8000d7c: 4910 ldr r1, [pc, #64] @ (8000dc0 <manageCDC+0x9c4>)
8000d7e: 4618 mov r0, r3
8000d80: f00b fbe4 bl 800c54c <siprintf>
while (CDC_Transmit_FS(s, 2) == USBD_BUSY);
8000d84: bf00 nop
8000d86: f107 030c add.w r3, r7, #12
8000d8a: 2102 movs r1, #2
8000d8c: 4618 mov r0, r3
8000d8e: f00a ffff bl 800bd90 <CDC_Transmit_FS>
8000d92: 4603 mov r3, r0
8000d94: 2b01 cmp r3, #1
8000d96: d0f6 beq.n 8000d86 <manageCDC+0x98a>
break;
8000d98: e000 b.n 8000d9c <manageCDC+0x9a0>
break;
8000d9a: bf00 nop
}
}
rxidx=0;
8000d9c: 4b09 ldr r3, [pc, #36] @ (8000dc4 <manageCDC+0x9c8>)
8000d9e: 2200 movs r2, #0
8000da0: 701a strb r2, [r3, #0]
8000da2: e007 b.n 8000db4 <manageCDC+0x9b8>
}else rxidx++;
8000da4: 4b07 ldr r3, [pc, #28] @ (8000dc4 <manageCDC+0x9c8>)
8000da6: 781b ldrb r3, [r3, #0]
8000da8: 3301 adds r3, #1
8000daa: b2da uxtb r2, r3
8000dac: 4b05 ldr r3, [pc, #20] @ (8000dc4 <manageCDC+0x9c8>)
8000dae: 701a strb r2, [r3, #0]
8000db0: e000 b.n 8000db4 <manageCDC+0x9b8>
if (rx < 0) return;
8000db2: bf00 nop
// tiny spin or yield
}
}
8000db4: 3784 adds r7, #132 @ 0x84
8000db6: 46bd mov sp, r7
8000db8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8000dbc: 0800d0b0 .word 0x0800d0b0
8000dc0: 0800d0c4 .word 0x0800d0c4
8000dc4: 2000022c .word 0x2000022c
08000dc8 <EEW_Read>:
{
8000dc8: b580 push {r7, lr}
8000dca: b082 sub sp, #8
8000dcc: af00 add r7, sp, #0
8000dce: 4603 mov r3, r0
8000dd0: 6039 str r1, [r7, #0]
8000dd2: 71fb strb r3, [r7, #7]
return EE_ReadVariable(EEW_ADDR(idx), value);
8000dd4: 79fb ldrb r3, [r7, #7]
8000dd6: b29b uxth r3, r3
8000dd8: 3301 adds r3, #1
8000dda: b29b uxth r3, r3
8000ddc: 6839 ldr r1, [r7, #0]
8000dde: 4618 mov r0, r3
8000de0: f000 f9b8 bl 8001154 <EE_ReadVariable>
8000de4: 4603 mov r3, r0
}
8000de6: 4618 mov r0, r3
8000de8: 3708 adds r7, #8
8000dea: 46bd mov sp, r7
8000dec: bd80 pop {r7, pc}
08000dee <EE_GetPageStatus>:
/* ========================================================================= */
/* --- Internal helpers ---------------------------------------------------- */
static uint16_t EE_GetPageStatus(uint32_t pageBase)
{
8000dee: b480 push {r7}
8000df0: b083 sub sp, #12
8000df2: af00 add r7, sp, #0
8000df4: 6078 str r0, [r7, #4]
return *(__IO uint16_t *)pageBase;
8000df6: 687b ldr r3, [r7, #4]
8000df8: 881b ldrh r3, [r3, #0]
8000dfa: b29b uxth r3, r3
}
8000dfc: 4618 mov r0, r3
8000dfe: 370c adds r7, #12
8000e00: 46bd mov sp, r7
8000e02: bc80 pop {r7}
8000e04: 4770 bx lr
08000e06 <EE_FlashProgramHalfWord>:
static HAL_StatusTypeDef EE_FlashProgramHalfWord(uint32_t Address, uint16_t Data)
{
8000e06: b5b0 push {r4, r5, r7, lr}
8000e08: b084 sub sp, #16
8000e0a: af00 add r7, sp, #0
8000e0c: 6078 str r0, [r7, #4]
8000e0e: 460b mov r3, r1
8000e10: 807b strh r3, [r7, #2]
HAL_StatusTypeDef status;
HAL_FLASH_Unlock();
8000e12: f003 faaf bl 8004374 <HAL_FLASH_Unlock>
status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, Address, Data);
8000e16: 887b ldrh r3, [r7, #2]
8000e18: 2200 movs r2, #0
8000e1a: 461c mov r4, r3
8000e1c: 4615 mov r5, r2
8000e1e: 4622 mov r2, r4
8000e20: 462b mov r3, r5
8000e22: 6879 ldr r1, [r7, #4]
8000e24: 2001 movs r0, #1
8000e26: f003 fa35 bl 8004294 <HAL_FLASH_Program>
8000e2a: 4603 mov r3, r0
8000e2c: 73fb strb r3, [r7, #15]
HAL_FLASH_Lock();
8000e2e: f003 fac7 bl 80043c0 <HAL_FLASH_Lock>
return status;
8000e32: 7bfb ldrb r3, [r7, #15]
}
8000e34: 4618 mov r0, r3
8000e36: 3710 adds r7, #16
8000e38: 46bd mov sp, r7
8000e3a: bdb0 pop {r4, r5, r7, pc}
08000e3c <EE_FlashErasePage>:
static HAL_StatusTypeDef EE_FlashErasePage(uint32_t PageAddress)
{
8000e3c: b580 push {r7, lr}
8000e3e: b088 sub sp, #32
8000e40: af00 add r7, sp, #0
8000e42: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
FLASH_EraseInitTypeDef EraseInit;
uint32_t PageError = 0;
8000e44: 2300 movs r3, #0
8000e46: 60bb str r3, [r7, #8]
HAL_FLASH_Unlock();
8000e48: f003 fa94 bl 8004374 <HAL_FLASH_Unlock>
EraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
8000e4c: 2300 movs r3, #0
8000e4e: 60fb str r3, [r7, #12]
EraseInit.PageAddress = PageAddress;
8000e50: 687b ldr r3, [r7, #4]
8000e52: 617b str r3, [r7, #20]
EraseInit.NbPages = 1;
8000e54: 2301 movs r3, #1
8000e56: 61bb str r3, [r7, #24]
status = HAL_FLASHEx_Erase(&EraseInit, &PageError);
8000e58: f107 0208 add.w r2, r7, #8
8000e5c: f107 030c add.w r3, r7, #12
8000e60: 4611 mov r1, r2
8000e62: 4618 mov r0, r3
8000e64: f003 fb6e bl 8004544 <HAL_FLASHEx_Erase>
8000e68: 4603 mov r3, r0
8000e6a: 77fb strb r3, [r7, #31]
HAL_FLASH_Lock();
8000e6c: f003 faa8 bl 80043c0 <HAL_FLASH_Lock>
return status;
8000e70: 7ffb ldrb r3, [r7, #31]
}
8000e72: 4618 mov r0, r3
8000e74: 3720 adds r7, #32
8000e76: 46bd mov sp, r7
8000e78: bd80 pop {r7, pc}
08000e7a <EE_FindFreeAddress>:
/* Find first free record address in given page (returns 0 if full) */
static uint32_t EE_FindFreeAddress(uint32_t pageBase)
{
8000e7a: b480 push {r7}
8000e7c: b087 sub sp, #28
8000e7e: af00 add r7, sp, #0
8000e80: 6078 str r0, [r7, #4]
uint32_t addr = pageBase + 2U; /* Skip status word */
8000e82: 687b ldr r3, [r7, #4]
8000e84: 3302 adds r3, #2
8000e86: 617b str r3, [r7, #20]
uint32_t pageEnd = pageBase + EE_PAGE_SIZE;
8000e88: 687b ldr r3, [r7, #4]
8000e8a: f503 6380 add.w r3, r3, #1024 @ 0x400
8000e8e: 613b str r3, [r7, #16]
while (addr < (pageEnd - sizeof(EE_Record_t) + 1U))
8000e90: e00c b.n 8000eac <EE_FindFreeAddress+0x32>
{
uint16_t vaddr = *(__IO uint16_t *)addr;
8000e92: 697b ldr r3, [r7, #20]
8000e94: 881b ldrh r3, [r3, #0]
8000e96: 81fb strh r3, [r7, #14]
if (vaddr == 0xFFFFU)
8000e98: 89fb ldrh r3, [r7, #14]
8000e9a: f64f 72ff movw r2, #65535 @ 0xffff
8000e9e: 4293 cmp r3, r2
8000ea0: d101 bne.n 8000ea6 <EE_FindFreeAddress+0x2c>
{
/* Empty slot */
return addr;
8000ea2: 697b ldr r3, [r7, #20]
8000ea4: e008 b.n 8000eb8 <EE_FindFreeAddress+0x3e>
}
addr += sizeof(EE_Record_t);
8000ea6: 697b ldr r3, [r7, #20]
8000ea8: 3304 adds r3, #4
8000eaa: 617b str r3, [r7, #20]
while (addr < (pageEnd - sizeof(EE_Record_t) + 1U))
8000eac: 693b ldr r3, [r7, #16]
8000eae: 3b03 subs r3, #3
8000eb0: 697a ldr r2, [r7, #20]
8000eb2: 429a cmp r2, r3
8000eb4: d3ed bcc.n 8000e92 <EE_FindFreeAddress+0x18>
}
return 0U; /* No space */
8000eb6: 2300 movs r3, #0
}
8000eb8: 4618 mov r0, r3
8000eba: 371c adds r7, #28
8000ebc: 46bd mov sp, r7
8000ebe: bc80 pop {r7}
8000ec0: 4770 bx lr
08000ec2 <EE_FindInPage>:
/* Find latest value of VirtAddress in a specific page (internal, uses EE_Status) */
/* Find latest value of VirtAddress in a specific page (scan forward) */
static EE_Status EE_FindInPage(uint32_t pageBase, uint16_t VirtAddress, uint16_t *Data)
{
8000ec2: b480 push {r7}
8000ec4: b089 sub sp, #36 @ 0x24
8000ec6: af00 add r7, sp, #0
8000ec8: 60f8 str r0, [r7, #12]
8000eca: 460b mov r3, r1
8000ecc: 607a str r2, [r7, #4]
8000ece: 817b strh r3, [r7, #10]
uint32_t addr = pageBase + 2U; // skip status halfword
8000ed0: 68fb ldr r3, [r7, #12]
8000ed2: 3302 adds r3, #2
8000ed4: 61fb str r3, [r7, #28]
uint32_t pageEnd = pageBase + EE_PAGE_SIZE;
8000ed6: 68fb ldr r3, [r7, #12]
8000ed8: f503 6380 add.w r3, r3, #1024 @ 0x400
8000edc: 617b str r3, [r7, #20]
EE_Status result = EE_NOT_FOUND;
8000ede: 2302 movs r3, #2
8000ee0: 76fb strb r3, [r7, #27]
uint16_t lastVal = 0;
8000ee2: 2300 movs r3, #0
8000ee4: 833b strh r3, [r7, #24]
if (Data == NULL)
8000ee6: 687b ldr r3, [r7, #4]
8000ee8: 2b00 cmp r3, #0
8000eea: d118 bne.n 8000f1e <EE_FindInPage+0x5c>
return EE_ERROR;
8000eec: 2301 movs r3, #1
8000eee: e024 b.n 8000f3a <EE_FindInPage+0x78>
while (addr <= (pageEnd - sizeof(EE_Record_t)))
{
uint16_t vaddr = *(__IO uint16_t *)addr;
8000ef0: 69fb ldr r3, [r7, #28]
8000ef2: 881b ldrh r3, [r3, #0]
8000ef4: 827b strh r3, [r7, #18]
if (vaddr == 0xFFFFU)
8000ef6: 8a7b ldrh r3, [r7, #18]
8000ef8: f64f 72ff movw r2, #65535 @ 0xffff
8000efc: 4293 cmp r3, r2
8000efe: d014 beq.n 8000f2a <EE_FindInPage+0x68>
{
// First empty slot => no more records in this page
break;
}
uint16_t value = *(__IO uint16_t *)(addr + 2U);
8000f00: 69fb ldr r3, [r7, #28]
8000f02: 3302 adds r3, #2
8000f04: 881b ldrh r3, [r3, #0]
8000f06: 823b strh r3, [r7, #16]
if (vaddr == VirtAddress)
8000f08: 8a7a ldrh r2, [r7, #18]
8000f0a: 897b ldrh r3, [r7, #10]
8000f0c: 429a cmp r2, r3
8000f0e: d103 bne.n 8000f18 <EE_FindInPage+0x56>
{
lastVal = value; // keep most recent
8000f10: 8a3b ldrh r3, [r7, #16]
8000f12: 833b strh r3, [r7, #24]
result = EE_OK;
8000f14: 2300 movs r3, #0
8000f16: 76fb strb r3, [r7, #27]
}
addr += sizeof(EE_Record_t); // move 4 bytes forward
8000f18: 69fb ldr r3, [r7, #28]
8000f1a: 3304 adds r3, #4
8000f1c: 61fb str r3, [r7, #28]
while (addr <= (pageEnd - sizeof(EE_Record_t)))
8000f1e: 697b ldr r3, [r7, #20]
8000f20: 3b04 subs r3, #4
8000f22: 69fa ldr r2, [r7, #28]
8000f24: 429a cmp r2, r3
8000f26: d9e3 bls.n 8000ef0 <EE_FindInPage+0x2e>
8000f28: e000 b.n 8000f2c <EE_FindInPage+0x6a>
break;
8000f2a: bf00 nop
}
if (result == EE_OK)
8000f2c: 7efb ldrb r3, [r7, #27]
8000f2e: 2b00 cmp r3, #0
8000f30: d102 bne.n 8000f38 <EE_FindInPage+0x76>
*Data = lastVal;
8000f32: 687b ldr r3, [r7, #4]
8000f34: 8b3a ldrh r2, [r7, #24]
8000f36: 801a strh r2, [r3, #0]
return result;
8000f38: 7efb ldrb r3, [r7, #27]
}
8000f3a: 4618 mov r0, r3
8000f3c: 3724 adds r7, #36 @ 0x24
8000f3e: 46bd mov sp, r7
8000f40: bc80 pop {r7}
8000f42: 4770 bx lr
08000f44 <EE_Format>:
/* Format both pages: erase and set PAGE0 as VALID */
static EE_Status EE_Format(void)
{
8000f44: b580 push {r7, lr}
8000f46: af00 add r7, sp, #0
if (EE_FlashErasePage(EE_PAGE0_BASE) != HAL_OK)
8000f48: 480f ldr r0, [pc, #60] @ (8000f88 <EE_Format+0x44>)
8000f4a: f7ff ff77 bl 8000e3c <EE_FlashErasePage>
8000f4e: 4603 mov r3, r0
8000f50: 2b00 cmp r3, #0
8000f52: d001 beq.n 8000f58 <EE_Format+0x14>
return EE_STATUS_ERROR;
8000f54: 2301 movs r3, #1
8000f56: e015 b.n 8000f84 <EE_Format+0x40>
if (EE_FlashErasePage(EE_PAGE1_BASE) != HAL_OK)
8000f58: 480c ldr r0, [pc, #48] @ (8000f8c <EE_Format+0x48>)
8000f5a: f7ff ff6f bl 8000e3c <EE_FlashErasePage>
8000f5e: 4603 mov r3, r0
8000f60: 2b00 cmp r3, #0
8000f62: d001 beq.n 8000f68 <EE_Format+0x24>
return EE_STATUS_ERROR;
8000f64: 2301 movs r3, #1
8000f66: e00d b.n 8000f84 <EE_Format+0x40>
if (EE_FlashProgramHalfWord(EE_PAGE0_BASE, EE_PAGE_STATUS_VALID) != HAL_OK)
8000f68: f64a 21aa movw r1, #43690 @ 0xaaaa
8000f6c: 4806 ldr r0, [pc, #24] @ (8000f88 <EE_Format+0x44>)
8000f6e: f7ff ff4a bl 8000e06 <EE_FlashProgramHalfWord>
8000f72: 4603 mov r3, r0
8000f74: 2b00 cmp r3, #0
8000f76: d001 beq.n 8000f7c <EE_Format+0x38>
return EE_STATUS_ERROR;
8000f78: 2301 movs r3, #1
8000f7a: e003 b.n 8000f84 <EE_Format+0x40>
/* PAGE1 will remain erased (status = 0xFFFF) */
EE_ActivePageBase = EE_PAGE0_BASE;
8000f7c: 4b04 ldr r3, [pc, #16] @ (8000f90 <EE_Format+0x4c>)
8000f7e: 4a02 ldr r2, [pc, #8] @ (8000f88 <EE_Format+0x44>)
8000f80: 601a str r2, [r3, #0]
return EE_STATUS_OK;
8000f82: 2300 movs r3, #0
}
8000f84: 4618 mov r0, r3
8000f86: bd80 pop {r7, pc}
8000f88: 0800f800 .word 0x0800f800
8000f8c: 0800fc00 .word 0x0800fc00
8000f90: 20000000 .word 0x20000000
08000f94 <EE_GetOtherPageBase>:
/* Get the base of the other page */
static uint32_t EE_GetOtherPageBase(uint32_t pageBase)
{
8000f94: b480 push {r7}
8000f96: b083 sub sp, #12
8000f98: af00 add r7, sp, #0
8000f9a: 6078 str r0, [r7, #4]
return (pageBase == EE_PAGE0_BASE) ? EE_PAGE1_BASE : EE_PAGE0_BASE;
8000f9c: 687b ldr r3, [r7, #4]
8000f9e: 4a05 ldr r2, [pc, #20] @ (8000fb4 <EE_GetOtherPageBase+0x20>)
8000fa0: 4293 cmp r3, r2
8000fa2: d101 bne.n 8000fa8 <EE_GetOtherPageBase+0x14>
8000fa4: 4b04 ldr r3, [pc, #16] @ (8000fb8 <EE_GetOtherPageBase+0x24>)
8000fa6: e000 b.n 8000faa <EE_GetOtherPageBase+0x16>
8000fa8: 4b02 ldr r3, [pc, #8] @ (8000fb4 <EE_GetOtherPageBase+0x20>)
}
8000faa: 4618 mov r0, r3
8000fac: 370c adds r7, #12
8000fae: 46bd mov sp, r7
8000fb0: bc80 pop {r7}
8000fb2: 4770 bx lr
8000fb4: 0800f800 .word 0x0800f800
8000fb8: 0800fc00 .word 0x0800fc00
08000fbc <EE_PageTransfer>:
/* Page transfer (garbage collection + new write) */
static EE_Status EE_PageTransfer(uint16_t VirtAddress, uint16_t Data)
{
8000fbc: b580 push {r7, lr}
8000fbe: b088 sub sp, #32
8000fc0: af00 add r7, sp, #0
8000fc2: 4603 mov r3, r0
8000fc4: 460a mov r2, r1
8000fc6: 80fb strh r3, [r7, #6]
8000fc8: 4613 mov r3, r2
8000fca: 80bb strh r3, [r7, #4]
uint32_t oldBase = EE_ActivePageBase;
8000fcc: 4b3c ldr r3, [pc, #240] @ (80010c0 <EE_PageTransfer+0x104>)
8000fce: 681b ldr r3, [r3, #0]
8000fd0: 617b str r3, [r7, #20]
uint32_t newBase = EE_GetOtherPageBase(oldBase);
8000fd2: 6978 ldr r0, [r7, #20]
8000fd4: f7ff ffde bl 8000f94 <EE_GetOtherPageBase>
8000fd8: 6138 str r0, [r7, #16]
uint32_t addr;
uint16_t value;
EE_Status st;
/* Erase new page */
if (EE_FlashErasePage(newBase) != HAL_OK)
8000fda: 6938 ldr r0, [r7, #16]
8000fdc: f7ff ff2e bl 8000e3c <EE_FlashErasePage>
8000fe0: 4603 mov r3, r0
8000fe2: 2b00 cmp r3, #0
8000fe4: d001 beq.n 8000fea <EE_PageTransfer+0x2e>
return EE_STATUS_ERROR;
8000fe6: 2301 movs r3, #1
8000fe8: e065 b.n 80010b6 <EE_PageTransfer+0xfa>
/* Mark new page as RECEIVE */
if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_RECEIVE) != HAL_OK)
8000fea: f245 5155 movw r1, #21845 @ 0x5555
8000fee: 6938 ldr r0, [r7, #16]
8000ff0: f7ff ff09 bl 8000e06 <EE_FlashProgramHalfWord>
8000ff4: 4603 mov r3, r0
8000ff6: 2b00 cmp r3, #0
8000ff8: d001 beq.n 8000ffe <EE_PageTransfer+0x42>
return EE_STATUS_ERROR;
8000ffa: 2301 movs r3, #1
8000ffc: e05b b.n 80010b6 <EE_PageTransfer+0xfa>
/* Start writing records just after status */
addr = newBase + 2U;
8000ffe: 693b ldr r3, [r7, #16]
8001000: 3302 adds r3, #2
8001002: 61fb str r3, [r7, #28]
/* For each known virtual variable */
for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++)
8001004: 2300 movs r3, #0
8001006: 837b strh r3, [r7, #26]
8001008: e03c b.n 8001084 <EE_PageTransfer+0xc8>
{
uint16_t vaddr = EE_VirtAddrs[i];
800100a: 8b7b ldrh r3, [r7, #26]
800100c: 4a2d ldr r2, [pc, #180] @ (80010c4 <EE_PageTransfer+0x108>)
800100e: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8001012: 81fb strh r3, [r7, #14]
if (vaddr == VirtAddress)
8001014: 89fa ldrh r2, [r7, #14]
8001016: 88fb ldrh r3, [r7, #6]
8001018: 429a cmp r2, r3
800101a: d102 bne.n 8001022 <EE_PageTransfer+0x66>
{
/* Use the new data passed into PageTransfer */
value = Data;
800101c: 88bb ldrh r3, [r7, #4]
800101e: 817b strh r3, [r7, #10]
8001020: e00b b.n 800103a <EE_PageTransfer+0x7e>
}
else
{
/* Read latest value from old active page */
st = EE_FindInPage(oldBase, vaddr, &value);
8001022: f107 020a add.w r2, r7, #10
8001026: 89fb ldrh r3, [r7, #14]
8001028: 4619 mov r1, r3
800102a: 6978 ldr r0, [r7, #20]
800102c: f7ff ff49 bl 8000ec2 <EE_FindInPage>
8001030: 4603 mov r3, r0
8001032: 737b strb r3, [r7, #13]
if (st != EE_STATUS_OK)
8001034: 7b7b ldrb r3, [r7, #13]
8001036: 2b00 cmp r3, #0
8001038: d120 bne.n 800107c <EE_PageTransfer+0xc0>
continue;
}
}
/* Write record to new page */
if (EE_FlashProgramHalfWord(addr, vaddr) != HAL_OK)
800103a: 89fb ldrh r3, [r7, #14]
800103c: 4619 mov r1, r3
800103e: 69f8 ldr r0, [r7, #28]
8001040: f7ff fee1 bl 8000e06 <EE_FlashProgramHalfWord>
8001044: 4603 mov r3, r0
8001046: 2b00 cmp r3, #0
8001048: d001 beq.n 800104e <EE_PageTransfer+0x92>
return EE_STATUS_ERROR;
800104a: 2301 movs r3, #1
800104c: e033 b.n 80010b6 <EE_PageTransfer+0xfa>
if (EE_FlashProgramHalfWord(addr + 2U, value) != HAL_OK)
800104e: 69fb ldr r3, [r7, #28]
8001050: 3302 adds r3, #2
8001052: 897a ldrh r2, [r7, #10]
8001054: 4611 mov r1, r2
8001056: 4618 mov r0, r3
8001058: f7ff fed5 bl 8000e06 <EE_FlashProgramHalfWord>
800105c: 4603 mov r3, r0
800105e: 2b00 cmp r3, #0
8001060: d001 beq.n 8001066 <EE_PageTransfer+0xaa>
return EE_STATUS_ERROR;
8001062: 2301 movs r3, #1
8001064: e027 b.n 80010b6 <EE_PageTransfer+0xfa>
addr += sizeof(EE_Record_t);
8001066: 69fb ldr r3, [r7, #28]
8001068: 3304 adds r3, #4
800106a: 61fb str r3, [r7, #28]
if (addr >= (newBase + EE_PAGE_SIZE))
800106c: 693b ldr r3, [r7, #16]
800106e: f503 6380 add.w r3, r3, #1024 @ 0x400
8001072: 69fa ldr r2, [r7, #28]
8001074: 429a cmp r2, r3
8001076: d302 bcc.n 800107e <EE_PageTransfer+0xc2>
return EE_STATUS_NO_SPACE;
8001078: 2303 movs r3, #3
800107a: e01c b.n 80010b6 <EE_PageTransfer+0xfa>
continue;
800107c: bf00 nop
for (uint16_t i = 0; i < EE_NUM_VIRTUAL_ADDR; i++)
800107e: 8b7b ldrh r3, [r7, #26]
8001080: 3301 adds r3, #1
8001082: 837b strh r3, [r7, #26]
8001084: 8b7b ldrh r3, [r7, #26]
8001086: 2b1f cmp r3, #31
8001088: d9bf bls.n 800100a <EE_PageTransfer+0x4e>
}
/* Erase old page */
if (EE_FlashErasePage(oldBase) != HAL_OK)
800108a: 6978 ldr r0, [r7, #20]
800108c: f7ff fed6 bl 8000e3c <EE_FlashErasePage>
8001090: 4603 mov r3, r0
8001092: 2b00 cmp r3, #0
8001094: d001 beq.n 800109a <EE_PageTransfer+0xde>
return EE_STATUS_ERROR;
8001096: 2301 movs r3, #1
8001098: e00d b.n 80010b6 <EE_PageTransfer+0xfa>
/* Mark new page as VALID */
if (EE_FlashProgramHalfWord(newBase, EE_PAGE_STATUS_VALID) != HAL_OK)
800109a: f64a 21aa movw r1, #43690 @ 0xaaaa
800109e: 6938 ldr r0, [r7, #16]
80010a0: f7ff feb1 bl 8000e06 <EE_FlashProgramHalfWord>
80010a4: 4603 mov r3, r0
80010a6: 2b00 cmp r3, #0
80010a8: d001 beq.n 80010ae <EE_PageTransfer+0xf2>
return EE_STATUS_ERROR;
80010aa: 2301 movs r3, #1
80010ac: e003 b.n 80010b6 <EE_PageTransfer+0xfa>
/* Update active page */
EE_ActivePageBase = newBase;
80010ae: 4a04 ldr r2, [pc, #16] @ (80010c0 <EE_PageTransfer+0x104>)
80010b0: 693b ldr r3, [r7, #16]
80010b2: 6013 str r3, [r2, #0]
return EE_STATUS_OK;
80010b4: 2300 movs r3, #0
}
80010b6: 4618 mov r0, r3
80010b8: 3720 adds r7, #32
80010ba: 46bd mov sp, r7
80010bc: bd80 pop {r7, pc}
80010be: bf00 nop
80010c0: 20000000 .word 0x20000000
80010c4: 0800d130 .word 0x0800d130
080010c8 <EE_Init>:
* - Checks page statuses and chooses the active page.
* - If inconsistent or blank, formats pages.
* PUBLIC RETURN TYPE: uint16_t (EE_OK / EE_ERROR / ...)
*/
uint16_t EE_Init(void)
{
80010c8: b580 push {r7, lr}
80010ca: b082 sub sp, #8
80010cc: af00 add r7, sp, #0
uint16_t status0 = EE_GetPageStatus(EE_PAGE0_BASE);
80010ce: 481e ldr r0, [pc, #120] @ (8001148 <EE_Init+0x80>)
80010d0: f7ff fe8d bl 8000dee <EE_GetPageStatus>
80010d4: 4603 mov r3, r0
80010d6: 80fb strh r3, [r7, #6]
uint16_t status1 = EE_GetPageStatus(EE_PAGE1_BASE);
80010d8: 481c ldr r0, [pc, #112] @ (800114c <EE_Init+0x84>)
80010da: f7ff fe88 bl 8000dee <EE_GetPageStatus>
80010de: 4603 mov r3, r0
80010e0: 80bb strh r3, [r7, #4]
if ((status0 == EE_PAGE_STATUS_ERASED) && (status1 == EE_PAGE_STATUS_ERASED))
80010e2: 88fb ldrh r3, [r7, #6]
80010e4: f64f 72ff movw r2, #65535 @ 0xffff
80010e8: 4293 cmp r3, r2
80010ea: d108 bne.n 80010fe <EE_Init+0x36>
80010ec: 88bb ldrh r3, [r7, #4]
80010ee: f64f 72ff movw r2, #65535 @ 0xffff
80010f2: 4293 cmp r3, r2
80010f4: d103 bne.n 80010fe <EE_Init+0x36>
{
/* Fresh device -> format */
return (uint16_t)EE_Format();
80010f6: f7ff ff25 bl 8000f44 <EE_Format>
80010fa: 4603 mov r3, r0
80010fc: e020 b.n 8001140 <EE_Init+0x78>
}
else if ((status0 == EE_PAGE_STATUS_VALID) && (status1 == EE_PAGE_STATUS_ERASED))
80010fe: 88fb ldrh r3, [r7, #6]
8001100: f64a 22aa movw r2, #43690 @ 0xaaaa
8001104: 4293 cmp r3, r2
8001106: d109 bne.n 800111c <EE_Init+0x54>
8001108: 88bb ldrh r3, [r7, #4]
800110a: f64f 72ff movw r2, #65535 @ 0xffff
800110e: 4293 cmp r3, r2
8001110: d104 bne.n 800111c <EE_Init+0x54>
{
EE_ActivePageBase = EE_PAGE0_BASE;
8001112: 4b0f ldr r3, [pc, #60] @ (8001150 <EE_Init+0x88>)
8001114: 4a0c ldr r2, [pc, #48] @ (8001148 <EE_Init+0x80>)
8001116: 601a str r2, [r3, #0]
return EE_OK;
8001118: 2300 movs r3, #0
800111a: e011 b.n 8001140 <EE_Init+0x78>
}
else if ((status1 == EE_PAGE_STATUS_VALID) && (status0 == EE_PAGE_STATUS_ERASED))
800111c: 88bb ldrh r3, [r7, #4]
800111e: f64a 22aa movw r2, #43690 @ 0xaaaa
8001122: 4293 cmp r3, r2
8001124: d109 bne.n 800113a <EE_Init+0x72>
8001126: 88fb ldrh r3, [r7, #6]
8001128: f64f 72ff movw r2, #65535 @ 0xffff
800112c: 4293 cmp r3, r2
800112e: d104 bne.n 800113a <EE_Init+0x72>
{
EE_ActivePageBase = EE_PAGE1_BASE;
8001130: 4b07 ldr r3, [pc, #28] @ (8001150 <EE_Init+0x88>)
8001132: 4a06 ldr r2, [pc, #24] @ (800114c <EE_Init+0x84>)
8001134: 601a str r2, [r3, #0]
return EE_OK;
8001136: 2300 movs r3, #0
8001138: e002 b.n 8001140 <EE_Init+0x78>
}
else
{
/* Any weird or inconsistent state -> reformat */
return (uint16_t)EE_Format();
800113a: f7ff ff03 bl 8000f44 <EE_Format>
800113e: 4603 mov r3, r0
}
}
8001140: 4618 mov r0, r3
8001142: 3708 adds r7, #8
8001144: 46bd mov sp, r7
8001146: bd80 pop {r7, pc}
8001148: 0800f800 .word 0x0800f800
800114c: 0800fc00 .word 0x0800fc00
8001150: 20000000 .word 0x20000000
08001154 <EE_ReadVariable>:
/*
* Read a 16-bit variable by its virtual address.
* PUBLIC RETURN: EE_OK / EE_NOT_FOUND / EE_ERROR (as uint16_t)
*/
uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t *Data)
{
8001154: b580 push {r7, lr}
8001156: b084 sub sp, #16
8001158: af00 add r7, sp, #0
800115a: 4603 mov r3, r0
800115c: 6039 str r1, [r7, #0]
800115e: 80fb strh r3, [r7, #6]
EE_Status st;
if (Data == NULL)
8001160: 683b ldr r3, [r7, #0]
8001162: 2b00 cmp r3, #0
8001164: d101 bne.n 800116a <EE_ReadVariable+0x16>
return EE_ERROR;
8001166: 2301 movs r3, #1
8001168: e00a b.n 8001180 <EE_ReadVariable+0x2c>
st = EE_FindInPage(EE_ActivePageBase, VirtAddress, Data);
800116a: 4b07 ldr r3, [pc, #28] @ (8001188 <EE_ReadVariable+0x34>)
800116c: 681b ldr r3, [r3, #0]
800116e: 88f9 ldrh r1, [r7, #6]
8001170: 683a ldr r2, [r7, #0]
8001172: 4618 mov r0, r3
8001174: f7ff fea5 bl 8000ec2 <EE_FindInPage>
8001178: 4603 mov r3, r0
800117a: 73fb strb r3, [r7, #15]
return (uint16_t)st;
800117c: 7bfb ldrb r3, [r7, #15]
800117e: b29b uxth r3, r3
}
8001180: 4618 mov r0, r3
8001182: 3710 adds r7, #16
8001184: 46bd mov sp, r7
8001186: bd80 pop {r7, pc}
8001188: 20000000 .word 0x20000000
0800118c <EE_WriteVariable>:
* - Writes a new record in the active page.
* - If the page is full, triggers a page transfer (GC).
* PUBLIC RETURN: EE_OK / EE_ERROR / EE_NO_SPACE (as uint16_t)
*/
uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data)
{
800118c: b580 push {r7, lr}
800118e: b084 sub sp, #16
8001190: af00 add r7, sp, #0
8001192: 4603 mov r3, r0
8001194: 460a mov r2, r1
8001196: 80fb strh r3, [r7, #6]
8001198: 4613 mov r3, r2
800119a: 80bb strh r3, [r7, #4]
uint32_t freeAddr;
EE_Status st;
/* Find free space in active page */
freeAddr = EE_FindFreeAddress(EE_ActivePageBase);
800119c: 4b17 ldr r3, [pc, #92] @ (80011fc <EE_WriteVariable+0x70>)
800119e: 681b ldr r3, [r3, #0]
80011a0: 4618 mov r0, r3
80011a2: f7ff fe6a bl 8000e7a <EE_FindFreeAddress>
80011a6: 60f8 str r0, [r7, #12]
if (freeAddr != 0U)
80011a8: 68fb ldr r3, [r7, #12]
80011aa: 2b00 cmp r3, #0
80011ac: d017 beq.n 80011de <EE_WriteVariable+0x52>
{
/* Write new record */
if (EE_FlashProgramHalfWord(freeAddr, VirtAddress) != HAL_OK)
80011ae: 88fb ldrh r3, [r7, #6]
80011b0: 4619 mov r1, r3
80011b2: 68f8 ldr r0, [r7, #12]
80011b4: f7ff fe27 bl 8000e06 <EE_FlashProgramHalfWord>
80011b8: 4603 mov r3, r0
80011ba: 2b00 cmp r3, #0
80011bc: d001 beq.n 80011c2 <EE_WriteVariable+0x36>
return EE_ERROR;
80011be: 2301 movs r3, #1
80011c0: e017 b.n 80011f2 <EE_WriteVariable+0x66>
if (EE_FlashProgramHalfWord(freeAddr + 2U, Data) != HAL_OK)
80011c2: 68fb ldr r3, [r7, #12]
80011c4: 3302 adds r3, #2
80011c6: 88ba ldrh r2, [r7, #4]
80011c8: 4611 mov r1, r2
80011ca: 4618 mov r0, r3
80011cc: f7ff fe1b bl 8000e06 <EE_FlashProgramHalfWord>
80011d0: 4603 mov r3, r0
80011d2: 2b00 cmp r3, #0
80011d4: d001 beq.n 80011da <EE_WriteVariable+0x4e>
return EE_ERROR;
80011d6: 2301 movs r3, #1
80011d8: e00b b.n 80011f2 <EE_WriteVariable+0x66>
return EE_OK;
80011da: 2300 movs r3, #0
80011dc: e009 b.n 80011f2 <EE_WriteVariable+0x66>
}
/* No space -> page transfer */
st = EE_PageTransfer(VirtAddress, Data);
80011de: 88ba ldrh r2, [r7, #4]
80011e0: 88fb ldrh r3, [r7, #6]
80011e2: 4611 mov r1, r2
80011e4: 4618 mov r0, r3
80011e6: f7ff fee9 bl 8000fbc <EE_PageTransfer>
80011ea: 4603 mov r3, r0
80011ec: 72fb strb r3, [r7, #11]
return (uint16_t)st;
80011ee: 7afb ldrb r3, [r7, #11]
80011f0: b29b uxth r3, r3
}
80011f2: 4618 mov r0, r3
80011f4: 3710 adds r7, #16
80011f6: 46bd mov sp, r7
80011f8: bd80 pop {r7, pc}
80011fa: bf00 nop
80011fc: 20000000 .word 0x20000000
08001200 <loadEE>:
void loadEE(void){
8001200: b580 push {r7, lr}
8001202: af00 add r7, sp, #0
EEW_Read(M1PWMAP, &m1pwmap);
8001204: 4924 ldr r1, [pc, #144] @ (8001298 <loadEE+0x98>)
8001206: 2000 movs r0, #0
8001208: f7ff fdde bl 8000dc8 <EEW_Read>
EEW_Read(M1PWMCH, &m1pwmch);
800120c: 4923 ldr r1, [pc, #140] @ (800129c <loadEE+0x9c>)
800120e: 2001 movs r0, #1
8001210: f7ff fdda bl 8000dc8 <EEW_Read>
EEW_Read(M2PWMAP, &m2pwmap);
8001214: 4922 ldr r1, [pc, #136] @ (80012a0 <loadEE+0xa0>)
8001216: 2002 movs r0, #2
8001218: f7ff fdd6 bl 8000dc8 <EEW_Read>
EEW_Read(M2PWMCH, &m2pwmch);
800121c: 4921 ldr r1, [pc, #132] @ (80012a4 <loadEE+0xa4>)
800121e: 2003 movs r0, #3
8001220: f7ff fdd2 bl 8000dc8 <EEW_Read>
EEW_Read(M3PWMAP, &m3pwmap);
8001224: 4920 ldr r1, [pc, #128] @ (80012a8 <loadEE+0xa8>)
8001226: 2004 movs r0, #4
8001228: f7ff fdce bl 8000dc8 <EEW_Read>
EEW_Read(M3PWMCH, &m3pwmch);
800122c: 491f ldr r1, [pc, #124] @ (80012ac <loadEE+0xac>)
800122e: 2005 movs r0, #5
8001230: f7ff fdca bl 8000dc8 <EEW_Read>
EEW_Read(M4PWMAP, &m4pwmap);
8001234: 491e ldr r1, [pc, #120] @ (80012b0 <loadEE+0xb0>)
8001236: 2006 movs r0, #6
8001238: f7ff fdc6 bl 8000dc8 <EEW_Read>
EEW_Read(M4PWMCH, &m4pwmch);
800123c: 491d ldr r1, [pc, #116] @ (80012b4 <loadEE+0xb4>)
800123e: 2007 movs r0, #7
8001240: f7ff fdc2 bl 8000dc8 <EEW_Read>
EEW_Read(T1AP, &t1ap);
8001244: 491c ldr r1, [pc, #112] @ (80012b8 <loadEE+0xb8>)
8001246: 200c movs r0, #12
8001248: f7ff fdbe bl 8000dc8 <EEW_Read>
EEW_Read(T2AP, &t2ap);
800124c: 491b ldr r1, [pc, #108] @ (80012bc <loadEE+0xbc>)
800124e: 200d movs r0, #13
8001250: f7ff fdba bl 8000dc8 <EEW_Read>
EEW_Read(T3AP, &t3ap);
8001254: 491a ldr r1, [pc, #104] @ (80012c0 <loadEE+0xc0>)
8001256: 200e movs r0, #14
8001258: f7ff fdb6 bl 8000dc8 <EEW_Read>
EEW_Read(T4AP, &t4ap);
800125c: 4919 ldr r1, [pc, #100] @ (80012c4 <loadEE+0xc4>)
800125e: 200f movs r0, #15
8001260: f7ff fdb2 bl 8000dc8 <EEW_Read>
EEW_Read(TWAP, &twap);
8001264: 4918 ldr r1, [pc, #96] @ (80012c8 <loadEE+0xc8>)
8001266: 2010 movs r0, #16
8001268: f7ff fdae bl 8000dc8 <EEW_Read>
EEW_Read(T1CH, &t1ch);
800126c: 4917 ldr r1, [pc, #92] @ (80012cc <loadEE+0xcc>)
800126e: 2011 movs r0, #17
8001270: f7ff fdaa bl 8000dc8 <EEW_Read>
EEW_Read(T2CH, &t2ch);
8001274: 4916 ldr r1, [pc, #88] @ (80012d0 <loadEE+0xd0>)
8001276: 2012 movs r0, #18
8001278: f7ff fda6 bl 8000dc8 <EEW_Read>
EEW_Read(T3CH, &t3ch);
800127c: 4915 ldr r1, [pc, #84] @ (80012d4 <loadEE+0xd4>)
800127e: 2013 movs r0, #19
8001280: f7ff fda2 bl 8000dc8 <EEW_Read>
EEW_Read(TWCH, &twch);
8001284: 4914 ldr r1, [pc, #80] @ (80012d8 <loadEE+0xd8>)
8001286: 2014 movs r0, #20
8001288: f7ff fd9e bl 8000dc8 <EEW_Read>
EEW_Read(TRAMP, &tramp);
800128c: 4913 ldr r1, [pc, #76] @ (80012dc <loadEE+0xdc>)
800128e: 201f movs r0, #31
8001290: f7ff fd9a bl 8000dc8 <EEW_Read>
}
8001294: bf00 nop
8001296: bd80 pop {r7, pc}
8001298: 200003ee .word 0x200003ee
800129c: 200003f0 .word 0x200003f0
80012a0: 200003f2 .word 0x200003f2
80012a4: 200003f4 .word 0x200003f4
80012a8: 200003f6 .word 0x200003f6
80012ac: 200003f8 .word 0x200003f8
80012b0: 200003fa .word 0x200003fa
80012b4: 200003fc .word 0x200003fc
80012b8: 200003fe .word 0x200003fe
80012bc: 20000400 .word 0x20000400
80012c0: 20000402 .word 0x20000402
80012c4: 20000404 .word 0x20000404
80012c8: 20000406 .word 0x20000406
80012cc: 20000408 .word 0x20000408
80012d0: 2000040a .word 0x2000040a
80012d4: 2000040c .word 0x2000040c
80012d8: 2000040e .word 0x2000040e
80012dc: 20000410 .word 0x20000410
080012e0 <HAL_SYSTICK_Callback>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_SYSTICK_Callback(void){
80012e0: b580 push {r7, lr}
80012e2: b082 sub sp, #8
80012e4: af00 add r7, sp, #0
static uint8_t c1s = 0;
static uint8_t inidx=0;
static uint8_t inbuf[4];
uint8_t i;
if (++c10ms >= 10) { // 10 ms
80012e6: 4b82 ldr r3, [pc, #520] @ (80014f0 <HAL_SYSTICK_Callback+0x210>)
80012e8: 781b ldrb r3, [r3, #0]
80012ea: 3301 adds r3, #1
80012ec: b2da uxtb r2, r3
80012ee: 4b80 ldr r3, [pc, #512] @ (80014f0 <HAL_SYSTICK_Callback+0x210>)
80012f0: 701a strb r2, [r3, #0]
80012f2: 4b7f ldr r3, [pc, #508] @ (80014f0 <HAL_SYSTICK_Callback+0x210>)
80012f4: 781b ldrb r3, [r3, #0]
80012f6: 2b09 cmp r3, #9
80012f8: f240 80f6 bls.w 80014e8 <HAL_SYSTICK_Callback+0x208>
c10ms = 0;
80012fc: 4b7c ldr r3, [pc, #496] @ (80014f0 <HAL_SYSTICK_Callback+0x210>)
80012fe: 2200 movs r2, #0
8001300: 701a strb r2, [r3, #0]
if(rtP1)rtP1--;
8001302: 4b7c ldr r3, [pc, #496] @ (80014f4 <HAL_SYSTICK_Callback+0x214>)
8001304: 781b ldrb r3, [r3, #0]
8001306: b2db uxtb r3, r3
8001308: 2b00 cmp r3, #0
800130a: d006 beq.n 800131a <HAL_SYSTICK_Callback+0x3a>
800130c: 4b79 ldr r3, [pc, #484] @ (80014f4 <HAL_SYSTICK_Callback+0x214>)
800130e: 781b ldrb r3, [r3, #0]
8001310: b2db uxtb r3, r3
8001312: 3b01 subs r3, #1
8001314: b2da uxtb r2, r3
8001316: 4b77 ldr r3, [pc, #476] @ (80014f4 <HAL_SYSTICK_Callback+0x214>)
8001318: 701a strb r2, [r3, #0]
if(rtP2)rtP2--;
800131a: 4b77 ldr r3, [pc, #476] @ (80014f8 <HAL_SYSTICK_Callback+0x218>)
800131c: 781b ldrb r3, [r3, #0]
800131e: b2db uxtb r3, r3
8001320: 2b00 cmp r3, #0
8001322: d006 beq.n 8001332 <HAL_SYSTICK_Callback+0x52>
8001324: 4b74 ldr r3, [pc, #464] @ (80014f8 <HAL_SYSTICK_Callback+0x218>)
8001326: 781b ldrb r3, [r3, #0]
8001328: b2db uxtb r3, r3
800132a: 3b01 subs r3, #1
800132c: b2da uxtb r2, r3
800132e: 4b72 ldr r3, [pc, #456] @ (80014f8 <HAL_SYSTICK_Callback+0x218>)
8001330: 701a strb r2, [r3, #0]
//**** legge i tasti********************************************************************************
inidx++;
8001332: 4b72 ldr r3, [pc, #456] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
8001334: 781b ldrb r3, [r3, #0]
8001336: 3301 adds r3, #1
8001338: b2da uxtb r2, r3
800133a: 4b70 ldr r3, [pc, #448] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
800133c: 701a strb r2, [r3, #0]
inidx&=0x03;
800133e: 4b6f ldr r3, [pc, #444] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
8001340: 781b ldrb r3, [r3, #0]
8001342: f003 0303 and.w r3, r3, #3
8001346: b2da uxtb r2, r3
8001348: 4b6c ldr r3, [pc, #432] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
800134a: 701a strb r2, [r3, #0]
if(HAL_GPIO_ReadPin(P1_GPIO_Port, P1_Pin)==GPIO_PIN_RESET)inbuf[inidx]|=INP1;else inbuf[inidx]&=(~INP1);
800134c: f44f 4180 mov.w r1, #16384 @ 0x4000
8001350: 486b ldr r0, [pc, #428] @ (8001500 <HAL_SYSTICK_Callback+0x220>)
8001352: f003 fb23 bl 800499c <HAL_GPIO_ReadPin>
8001356: 4603 mov r3, r0
8001358: 2b00 cmp r3, #0
800135a: d10c bne.n 8001376 <HAL_SYSTICK_Callback+0x96>
800135c: 4b67 ldr r3, [pc, #412] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
800135e: 781b ldrb r3, [r3, #0]
8001360: 461a mov r2, r3
8001362: 4b68 ldr r3, [pc, #416] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
8001364: 5c9b ldrb r3, [r3, r2]
8001366: 4a65 ldr r2, [pc, #404] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
8001368: 7812 ldrb r2, [r2, #0]
800136a: f043 0301 orr.w r3, r3, #1
800136e: b2d9 uxtb r1, r3
8001370: 4b64 ldr r3, [pc, #400] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
8001372: 5499 strb r1, [r3, r2]
8001374: e00b b.n 800138e <HAL_SYSTICK_Callback+0xae>
8001376: 4b61 ldr r3, [pc, #388] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
8001378: 781b ldrb r3, [r3, #0]
800137a: 461a mov r2, r3
800137c: 4b61 ldr r3, [pc, #388] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
800137e: 5c9b ldrb r3, [r3, r2]
8001380: 4a5e ldr r2, [pc, #376] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
8001382: 7812 ldrb r2, [r2, #0]
8001384: f023 0301 bic.w r3, r3, #1
8001388: b2d9 uxtb r1, r3
800138a: 4b5e ldr r3, [pc, #376] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
800138c: 5499 strb r1, [r3, r2]
if(HAL_GPIO_ReadPin(P2_GPIO_Port, P2_Pin)==GPIO_PIN_RESET)inbuf[inidx]|=INP2;else inbuf[inidx]&=(~INP2);
800138e: f44f 4100 mov.w r1, #32768 @ 0x8000
8001392: 485b ldr r0, [pc, #364] @ (8001500 <HAL_SYSTICK_Callback+0x220>)
8001394: f003 fb02 bl 800499c <HAL_GPIO_ReadPin>
8001398: 4603 mov r3, r0
800139a: 2b00 cmp r3, #0
800139c: d10c bne.n 80013b8 <HAL_SYSTICK_Callback+0xd8>
800139e: 4b57 ldr r3, [pc, #348] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
80013a0: 781b ldrb r3, [r3, #0]
80013a2: 461a mov r2, r3
80013a4: 4b57 ldr r3, [pc, #348] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013a6: 5c9b ldrb r3, [r3, r2]
80013a8: 4a54 ldr r2, [pc, #336] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
80013aa: 7812 ldrb r2, [r2, #0]
80013ac: f043 0302 orr.w r3, r3, #2
80013b0: b2d9 uxtb r1, r3
80013b2: 4b54 ldr r3, [pc, #336] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013b4: 5499 strb r1, [r3, r2]
80013b6: e00b b.n 80013d0 <HAL_SYSTICK_Callback+0xf0>
80013b8: 4b50 ldr r3, [pc, #320] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
80013ba: 781b ldrb r3, [r3, #0]
80013bc: 461a mov r2, r3
80013be: 4b51 ldr r3, [pc, #324] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013c0: 5c9b ldrb r3, [r3, r2]
80013c2: 4a4e ldr r2, [pc, #312] @ (80014fc <HAL_SYSTICK_Callback+0x21c>)
80013c4: 7812 ldrb r2, [r2, #0]
80013c6: f023 0302 bic.w r3, r3, #2
80013ca: b2d9 uxtb r1, r3
80013cc: 4b4d ldr r3, [pc, #308] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013ce: 5499 strb r1, [r3, r2]
pulsanti|=(inbuf[0]&inbuf[1]&inbuf[2]&inbuf[3]);
80013d0: 4b4c ldr r3, [pc, #304] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013d2: 781a ldrb r2, [r3, #0]
80013d4: 4b4b ldr r3, [pc, #300] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013d6: 785b ldrb r3, [r3, #1]
80013d8: 4013 ands r3, r2
80013da: b2da uxtb r2, r3
80013dc: 4b49 ldr r3, [pc, #292] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013de: 789b ldrb r3, [r3, #2]
80013e0: 4013 ands r3, r2
80013e2: b2da uxtb r2, r3
80013e4: 4b47 ldr r3, [pc, #284] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013e6: 78db ldrb r3, [r3, #3]
80013e8: 4013 ands r3, r2
80013ea: b2da uxtb r2, r3
80013ec: 4b46 ldr r3, [pc, #280] @ (8001508 <HAL_SYSTICK_Callback+0x228>)
80013ee: 781b ldrb r3, [r3, #0]
80013f0: 4313 orrs r3, r2
80013f2: b2da uxtb r2, r3
80013f4: 4b44 ldr r3, [pc, #272] @ (8001508 <HAL_SYSTICK_Callback+0x228>)
80013f6: 701a strb r2, [r3, #0]
pulsanti&=(inbuf[0]|inbuf[1]|inbuf[2]|inbuf[3]);
80013f8: 4b42 ldr r3, [pc, #264] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013fa: 781a ldrb r2, [r3, #0]
80013fc: 4b41 ldr r3, [pc, #260] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
80013fe: 785b ldrb r3, [r3, #1]
8001400: 4313 orrs r3, r2
8001402: b2da uxtb r2, r3
8001404: 4b3f ldr r3, [pc, #252] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
8001406: 789b ldrb r3, [r3, #2]
8001408: 4313 orrs r3, r2
800140a: b2da uxtb r2, r3
800140c: 4b3d ldr r3, [pc, #244] @ (8001504 <HAL_SYSTICK_Callback+0x224>)
800140e: 78db ldrb r3, [r3, #3]
8001410: 4313 orrs r3, r2
8001412: b2da uxtb r2, r3
8001414: 4b3c ldr r3, [pc, #240] @ (8001508 <HAL_SYSTICK_Callback+0x228>)
8001416: 781b ldrb r3, [r3, #0]
8001418: 4013 ands r3, r2
800141a: b2da uxtb r2, r3
800141c: 4b3a ldr r3, [pc, #232] @ (8001508 <HAL_SYSTICK_Callback+0x228>)
800141e: 701a strb r2, [r3, #0]
//**** legge adc ***********************************************************************************
readAdc();
8001420: f7fe fed2 bl 80001c8 <readAdc>
if (++c100ms >= 10) { // 10 ms
8001424: 4b39 ldr r3, [pc, #228] @ (800150c <HAL_SYSTICK_Callback+0x22c>)
8001426: 781b ldrb r3, [r3, #0]
8001428: 3301 adds r3, #1
800142a: b2da uxtb r2, r3
800142c: 4b37 ldr r3, [pc, #220] @ (800150c <HAL_SYSTICK_Callback+0x22c>)
800142e: 701a strb r2, [r3, #0]
8001430: 4b36 ldr r3, [pc, #216] @ (800150c <HAL_SYSTICK_Callback+0x22c>)
8001432: 781b ldrb r3, [r3, #0]
8001434: 2b09 cmp r3, #9
8001436: d957 bls.n 80014e8 <HAL_SYSTICK_Callback+0x208>
c100ms = 0; //flag_10ms = 1; // set a flag; do real work in main loop
8001438: 4b34 ldr r3, [pc, #208] @ (800150c <HAL_SYSTICK_Callback+0x22c>)
800143a: 2200 movs r2, #0
800143c: 701a strb r2, [r3, #0]
for(i=0;i<4;i++){
800143e: 2300 movs r3, #0
8001440: 71fb strb r3, [r7, #7]
8001442: e013 b.n 800146c <HAL_SYSTICK_Callback+0x18c>
if(rtramp[i])rtramp[i]--;
8001444: 79fb ldrb r3, [r7, #7]
8001446: 4a32 ldr r2, [pc, #200] @ (8001510 <HAL_SYSTICK_Callback+0x230>)
8001448: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800144c: b29b uxth r3, r3
800144e: 2b00 cmp r3, #0
8001450: d009 beq.n 8001466 <HAL_SYSTICK_Callback+0x186>
8001452: 79fb ldrb r3, [r7, #7]
8001454: 4a2e ldr r2, [pc, #184] @ (8001510 <HAL_SYSTICK_Callback+0x230>)
8001456: f832 2013 ldrh.w r2, [r2, r3, lsl #1]
800145a: b292 uxth r2, r2
800145c: 3a01 subs r2, #1
800145e: b291 uxth r1, r2
8001460: 4a2b ldr r2, [pc, #172] @ (8001510 <HAL_SYSTICK_Callback+0x230>)
8001462: f822 1013 strh.w r1, [r2, r3, lsl #1]
for(i=0;i<4;i++){
8001466: 79fb ldrb r3, [r7, #7]
8001468: 3301 adds r3, #1
800146a: 71fb strb r3, [r7, #7]
800146c: 79fb ldrb r3, [r7, #7]
800146e: 2b03 cmp r3, #3
8001470: d9e8 bls.n 8001444 <HAL_SYSTICK_Callback+0x164>
}
//**** gestione buzzer *****************************************************************************
if(stBuz==bzmoving){
8001472: 4b28 ldr r3, [pc, #160] @ (8001514 <HAL_SYSTICK_Callback+0x234>)
8001474: 781b ldrb r3, [r3, #0]
8001476: b2db uxtb r3, r3
8001478: 2b01 cmp r3, #1
800147a: d111 bne.n 80014a0 <HAL_SYSTICK_Callback+0x1c0>
if(c1s>=5)HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_RESET);else HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_SET);
800147c: 4b26 ldr r3, [pc, #152] @ (8001518 <HAL_SYSTICK_Callback+0x238>)
800147e: 781b ldrb r3, [r3, #0]
8001480: 2b04 cmp r3, #4
8001482: d906 bls.n 8001492 <HAL_SYSTICK_Callback+0x1b2>
8001484: 2200 movs r2, #0
8001486: f44f 7180 mov.w r1, #256 @ 0x100
800148a: 4824 ldr r0, [pc, #144] @ (800151c <HAL_SYSTICK_Callback+0x23c>)
800148c: f003 fa9d bl 80049ca <HAL_GPIO_WritePin>
8001490: e00c b.n 80014ac <HAL_SYSTICK_Callback+0x1cc>
8001492: 2201 movs r2, #1
8001494: f44f 7180 mov.w r1, #256 @ 0x100
8001498: 4820 ldr r0, [pc, #128] @ (800151c <HAL_SYSTICK_Callback+0x23c>)
800149a: f003 fa96 bl 80049ca <HAL_GPIO_WritePin>
800149e: e005 b.n 80014ac <HAL_SYSTICK_Callback+0x1cc>
}else{//bzoff
HAL_GPIO_WritePin(GPIOA, BUZ_Pin, GPIO_PIN_RESET);
80014a0: 2200 movs r2, #0
80014a2: f44f 7180 mov.w r1, #256 @ 0x100
80014a6: 481d ldr r0, [pc, #116] @ (800151c <HAL_SYSTICK_Callback+0x23c>)
80014a8: f003 fa8f bl 80049ca <HAL_GPIO_WritePin>
}
//**************************************************************************************************
if (++c1s >= 10) { // 10 ms
80014ac: 4b1a ldr r3, [pc, #104] @ (8001518 <HAL_SYSTICK_Callback+0x238>)
80014ae: 781b ldrb r3, [r3, #0]
80014b0: 3301 adds r3, #1
80014b2: b2da uxtb r2, r3
80014b4: 4b18 ldr r3, [pc, #96] @ (8001518 <HAL_SYSTICK_Callback+0x238>)
80014b6: 701a strb r2, [r3, #0]
80014b8: 4b17 ldr r3, [pc, #92] @ (8001518 <HAL_SYSTICK_Callback+0x238>)
80014ba: 781b ldrb r3, [r3, #0]
80014bc: 2b09 cmp r3, #9
80014be: d913 bls.n 80014e8 <HAL_SYSTICK_Callback+0x208>
c1s = 0;
80014c0: 4b15 ldr r3, [pc, #84] @ (8001518 <HAL_SYSTICK_Callback+0x238>)
80014c2: 2200 movs r2, #0
80014c4: 701a strb r2, [r3, #0]
if(rtCiclo)rtCiclo--;
80014c6: 4b16 ldr r3, [pc, #88] @ (8001520 <HAL_SYSTICK_Callback+0x240>)
80014c8: 881b ldrh r3, [r3, #0]
80014ca: b29b uxth r3, r3
80014cc: 2b00 cmp r3, #0
80014ce: d006 beq.n 80014de <HAL_SYSTICK_Callback+0x1fe>
80014d0: 4b13 ldr r3, [pc, #76] @ (8001520 <HAL_SYSTICK_Callback+0x240>)
80014d2: 881b ldrh r3, [r3, #0]
80014d4: b29b uxth r3, r3
80014d6: 3b01 subs r3, #1
80014d8: b29a uxth r2, r3
80014da: 4b11 ldr r3, [pc, #68] @ (8001520 <HAL_SYSTICK_Callback+0x240>)
80014dc: 801a strh r2, [r3, #0]
HAL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
80014de: f44f 5100 mov.w r1, #8192 @ 0x2000
80014e2: 4807 ldr r0, [pc, #28] @ (8001500 <HAL_SYSTICK_Callback+0x220>)
80014e4: f003 fa89 bl 80049fa <HAL_GPIO_TogglePin>
}
}
}
}
80014e8: bf00 nop
80014ea: 3708 adds r7, #8
80014ec: 46bd mov sp, r7
80014ee: bd80 pop {r7, pc}
80014f0: 2000041f .word 0x2000041f
80014f4: 20000004 .word 0x20000004
80014f8: 20000005 .word 0x20000005
80014fc: 20000420 .word 0x20000420
8001500: 40011000 .word 0x40011000
8001504: 20000424 .word 0x20000424
8001508: 200003e0 .word 0x200003e0
800150c: 20000428 .word 0x20000428
8001510: 200003e4 .word 0x200003e4
8001514: 2000041e .word 0x2000041e
8001518: 20000429 .word 0x20000429
800151c: 40010800 .word 0x40010800
8001520: 200003ec .word 0x200003ec
08001524 <managePulsanti>:
void managePulsanti(void){
8001524: b480 push {r7}
8001526: af00 add r7, sp, #0
if(pulsanti&INP1){
8001528: 4b31 ldr r3, [pc, #196] @ (80015f0 <managePulsanti+0xcc>)
800152a: 781b ldrb r3, [r3, #0]
800152c: f003 0301 and.w r3, r3, #1
8001530: 2b00 cmp r3, #0
8001532: d00c beq.n 800154e <managePulsanti+0x2a>
if(rtP1==0)stPulsanti|=P1START;
8001534: 4b2f ldr r3, [pc, #188] @ (80015f4 <managePulsanti+0xd0>)
8001536: 781b ldrb r3, [r3, #0]
8001538: b2db uxtb r3, r3
800153a: 2b00 cmp r3, #0
800153c: d124 bne.n 8001588 <managePulsanti+0x64>
800153e: 4b2e ldr r3, [pc, #184] @ (80015f8 <managePulsanti+0xd4>)
8001540: 781b ldrb r3, [r3, #0]
8001542: f043 0301 orr.w r3, r3, #1
8001546: b2da uxtb r2, r3
8001548: 4b2b ldr r3, [pc, #172] @ (80015f8 <managePulsanti+0xd4>)
800154a: 701a strb r2, [r3, #0]
800154c: e01c b.n 8001588 <managePulsanti+0x64>
}else{
if(stPulsanti&P1START)stPulsanti&=(~P1START);
800154e: 4b2a ldr r3, [pc, #168] @ (80015f8 <managePulsanti+0xd4>)
8001550: 781b ldrb r3, [r3, #0]
8001552: f003 0301 and.w r3, r3, #1
8001556: 2b00 cmp r3, #0
8001558: d007 beq.n 800156a <managePulsanti+0x46>
800155a: 4b27 ldr r3, [pc, #156] @ (80015f8 <managePulsanti+0xd4>)
800155c: 781b ldrb r3, [r3, #0]
800155e: f023 0301 bic.w r3, r3, #1
8001562: b2da uxtb r2, r3
8001564: 4b24 ldr r3, [pc, #144] @ (80015f8 <managePulsanti+0xd4>)
8001566: 701a strb r2, [r3, #0]
8001568: e00b b.n 8001582 <managePulsanti+0x5e>
else if(rtP1<=190){
800156a: 4b22 ldr r3, [pc, #136] @ (80015f4 <managePulsanti+0xd0>)
800156c: 781b ldrb r3, [r3, #0]
800156e: b2db uxtb r3, r3
8001570: 2bbe cmp r3, #190 @ 0xbe
8001572: d806 bhi.n 8001582 <managePulsanti+0x5e>
stPulsanti|=P1STOP;
8001574: 4b20 ldr r3, [pc, #128] @ (80015f8 <managePulsanti+0xd4>)
8001576: 781b ldrb r3, [r3, #0]
8001578: f043 0302 orr.w r3, r3, #2
800157c: b2da uxtb r2, r3
800157e: 4b1e ldr r3, [pc, #120] @ (80015f8 <managePulsanti+0xd4>)
8001580: 701a strb r2, [r3, #0]
}
rtP1=200;
8001582: 4b1c ldr r3, [pc, #112] @ (80015f4 <managePulsanti+0xd0>)
8001584: 22c8 movs r2, #200 @ 0xc8
8001586: 701a strb r2, [r3, #0]
}
if(pulsanti&INP2){
8001588: 4b19 ldr r3, [pc, #100] @ (80015f0 <managePulsanti+0xcc>)
800158a: 781b ldrb r3, [r3, #0]
800158c: f003 0302 and.w r3, r3, #2
8001590: 2b00 cmp r3, #0
8001592: d00c beq.n 80015ae <managePulsanti+0x8a>
if(rtP2==0)stPulsanti|=P2START;
8001594: 4b19 ldr r3, [pc, #100] @ (80015fc <managePulsanti+0xd8>)
8001596: 781b ldrb r3, [r3, #0]
8001598: b2db uxtb r3, r3
800159a: 2b00 cmp r3, #0
800159c: d124 bne.n 80015e8 <managePulsanti+0xc4>
800159e: 4b16 ldr r3, [pc, #88] @ (80015f8 <managePulsanti+0xd4>)
80015a0: 781b ldrb r3, [r3, #0]
80015a2: f043 0304 orr.w r3, r3, #4
80015a6: b2da uxtb r2, r3
80015a8: 4b13 ldr r3, [pc, #76] @ (80015f8 <managePulsanti+0xd4>)
80015aa: 701a strb r2, [r3, #0]
}else{
if(stPulsanti&P2START)stPulsanti&=(~P2START);
else if(rtP2<=190)stPulsanti|=P2STOP;
rtP2=200;
}
}
80015ac: e01c b.n 80015e8 <managePulsanti+0xc4>
if(stPulsanti&P2START)stPulsanti&=(~P2START);
80015ae: 4b12 ldr r3, [pc, #72] @ (80015f8 <managePulsanti+0xd4>)
80015b0: 781b ldrb r3, [r3, #0]
80015b2: f003 0304 and.w r3, r3, #4
80015b6: 2b00 cmp r3, #0
80015b8: d007 beq.n 80015ca <managePulsanti+0xa6>
80015ba: 4b0f ldr r3, [pc, #60] @ (80015f8 <managePulsanti+0xd4>)
80015bc: 781b ldrb r3, [r3, #0]
80015be: f023 0304 bic.w r3, r3, #4
80015c2: b2da uxtb r2, r3
80015c4: 4b0c ldr r3, [pc, #48] @ (80015f8 <managePulsanti+0xd4>)
80015c6: 701a strb r2, [r3, #0]
80015c8: e00b b.n 80015e2 <managePulsanti+0xbe>
else if(rtP2<=190)stPulsanti|=P2STOP;
80015ca: 4b0c ldr r3, [pc, #48] @ (80015fc <managePulsanti+0xd8>)
80015cc: 781b ldrb r3, [r3, #0]
80015ce: b2db uxtb r3, r3
80015d0: 2bbe cmp r3, #190 @ 0xbe
80015d2: d806 bhi.n 80015e2 <managePulsanti+0xbe>
80015d4: 4b08 ldr r3, [pc, #32] @ (80015f8 <managePulsanti+0xd4>)
80015d6: 781b ldrb r3, [r3, #0]
80015d8: f043 0308 orr.w r3, r3, #8
80015dc: b2da uxtb r2, r3
80015de: 4b06 ldr r3, [pc, #24] @ (80015f8 <managePulsanti+0xd4>)
80015e0: 701a strb r2, [r3, #0]
rtP2=200;
80015e2: 4b06 ldr r3, [pc, #24] @ (80015fc <managePulsanti+0xd8>)
80015e4: 22c8 movs r2, #200 @ 0xc8
80015e6: 701a strb r2, [r3, #0]
}
80015e8: bf00 nop
80015ea: 46bd mov sp, r7
80015ec: bc80 pop {r7}
80015ee: 4770 bx lr
80015f0: 200003e0 .word 0x200003e0
80015f4: 20000004 .word 0x20000004
80015f8: 2000041c .word 0x2000041c
80015fc: 20000005 .word 0x20000005
08001600 <manageCiclo>:
void manageCiclo(void){
8001600: b580 push {r7, lr}
8001602: b082 sub sp, #8
8001604: af02 add r7, sp, #8
switch(stCiclo){
8001606: 4ba5 ldr r3, [pc, #660] @ (800189c <manageCiclo+0x29c>)
8001608: 781b ldrb r3, [r3, #0]
800160a: 2b1d cmp r3, #29
800160c: f200 853d bhi.w 800208a <manageCiclo+0xa8a>
8001610: a201 add r2, pc, #4 @ (adr r2, 8001618 <manageCiclo+0x18>)
8001612: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001616: bf00 nop
8001618: 08001691 .word 0x08001691
800161c: 080016e3 .word 0x080016e3
8001620: 08001731 .word 0x08001731
8001624: 08001775 .word 0x08001775
8001628: 080017bd .word 0x080017bd
800162c: 08001807 .word 0x08001807
8001630: 08001853 .word 0x08001853
8001634: 080018cd .word 0x080018cd
8001638: 08001919 .word 0x08001919
800163c: 08001977 .word 0x08001977
8001640: 080019df .word 0x080019df
8001644: 08001a27 .word 0x08001a27
8001648: 08001a73 .word 0x08001a73
800164c: 08001ab5 .word 0x08001ab5
8001650: 08001afb .word 0x08001afb
8001654: 08001b59 .word 0x08001b59
8001658: 08001b9d .word 0x08001b9d
800165c: 08001c0f .word 0x08001c0f
8001660: 08001c83 .word 0x08001c83
8001664: 08001ce1 .word 0x08001ce1
8001668: 08001d49 .word 0x08001d49
800166c: 08001d91 .word 0x08001d91
8001670: 08001e0d .word 0x08001e0d
8001674: 08001e4f .word 0x08001e4f
8001678: 08001e95 .word 0x08001e95
800167c: 08001edd .word 0x08001edd
8001680: 08001f29 .word 0x08001f29
8001684: 08001f6b .word 0x08001f6b
8001688: 08001faf .word 0x08001faf
800168c: 08001fd9 .word 0x08001fd9
case omchiuso:
if(stPulsanti&P1START){
8001690: 4b83 ldr r3, [pc, #524] @ (80018a0 <manageCiclo+0x2a0>)
8001692: 781b ldrb r3, [r3, #0]
8001694: f003 0301 and.w r3, r3, #1
8001698: 2b00 cmp r3, #0
800169a: d016 beq.n 80016ca <manageCiclo+0xca>
stBuz=bzmoving;
800169c: 4b81 ldr r3, [pc, #516] @ (80018a4 <manageCiclo+0x2a4>)
800169e: 2201 movs r2, #1
80016a0: 701a strb r2, [r3, #0]
(void)ramp(M2,BW,mrampstart[M2-1],m2pwmap,tramp,RAMPINIT);
80016a2: 4b81 ldr r3, [pc, #516] @ (80018a8 <manageCiclo+0x2a8>)
80016a4: 885b ldrh r3, [r3, #2]
80016a6: b2da uxtb r2, r3
80016a8: 4b80 ldr r3, [pc, #512] @ (80018ac <manageCiclo+0x2ac>)
80016aa: 881b ldrh r3, [r3, #0]
80016ac: b2d9 uxtb r1, r3
80016ae: 4b80 ldr r3, [pc, #512] @ (80018b0 <manageCiclo+0x2b0>)
80016b0: 881b ldrh r3, [r3, #0]
80016b2: b2db uxtb r3, r3
80016b4: 2000 movs r0, #0
80016b6: 9001 str r0, [sp, #4]
80016b8: 9300 str r3, [sp, #0]
80016ba: 460b mov r3, r1
80016bc: 2101 movs r1, #1
80016be: 2002 movs r0, #2
80016c0: f001 fbca bl 8002e58 <ramp>
stCiclo=omapertura1;
80016c4: 4b75 ldr r3, [pc, #468] @ (800189c <manageCiclo+0x29c>)
80016c6: 2201 movs r2, #1
80016c8: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
80016ca: 4b75 ldr r3, [pc, #468] @ (80018a0 <manageCiclo+0x2a0>)
80016cc: 781b ldrb r3, [r3, #0]
80016ce: f003 0302 and.w r3, r3, #2
80016d2: 2b00 cmp r3, #0
80016d4: f000 84a2 beq.w 800201c <manageCiclo+0xa1c>
80016d8: 4b70 ldr r3, [pc, #448] @ (800189c <manageCiclo+0x29c>)
80016da: 220f movs r2, #15
80016dc: 701a strb r2, [r3, #0]
break;
80016de: f000 bc9d b.w 800201c <manageCiclo+0xa1c>
case omapertura1:
if(ramp(M2,BW,mrampstart[M2-1],m2pwmap,tramp,RAMPRUN)==DONE){
80016e2: 4b71 ldr r3, [pc, #452] @ (80018a8 <manageCiclo+0x2a8>)
80016e4: 885b ldrh r3, [r3, #2]
80016e6: b2da uxtb r2, r3
80016e8: 4b70 ldr r3, [pc, #448] @ (80018ac <manageCiclo+0x2ac>)
80016ea: 881b ldrh r3, [r3, #0]
80016ec: b2d9 uxtb r1, r3
80016ee: 4b70 ldr r3, [pc, #448] @ (80018b0 <manageCiclo+0x2b0>)
80016f0: 881b ldrh r3, [r3, #0]
80016f2: b2db uxtb r3, r3
80016f4: 200a movs r0, #10
80016f6: 9001 str r0, [sp, #4]
80016f8: 9300 str r3, [sp, #0]
80016fa: 460b mov r3, r1
80016fc: 2101 movs r1, #1
80016fe: 2002 movs r0, #2
8001700: f001 fbaa bl 8002e58 <ramp>
8001704: 4603 mov r3, r0
8001706: 2b00 cmp r3, #0
8001708: d106 bne.n 8001718 <manageCiclo+0x118>
rtCiclo=t1ap;
800170a: 4b6a ldr r3, [pc, #424] @ (80018b4 <manageCiclo+0x2b4>)
800170c: 881a ldrh r2, [r3, #0]
800170e: 4b6a ldr r3, [pc, #424] @ (80018b8 <manageCiclo+0x2b8>)
8001710: 801a strh r2, [r3, #0]
stCiclo=omapertura2;
8001712: 4b62 ldr r3, [pc, #392] @ (800189c <manageCiclo+0x29c>)
8001714: 2202 movs r2, #2
8001716: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001718: 4b61 ldr r3, [pc, #388] @ (80018a0 <manageCiclo+0x2a0>)
800171a: 781b ldrb r3, [r3, #0]
800171c: f003 0302 and.w r3, r3, #2
8001720: 2b00 cmp r3, #0
8001722: f000 847d beq.w 8002020 <manageCiclo+0xa20>
8001726: 4b5d ldr r3, [pc, #372] @ (800189c <manageCiclo+0x29c>)
8001728: 220f movs r2, #15
800172a: 701a strb r2, [r3, #0]
break;
800172c: f000 bc78 b.w 8002020 <manageCiclo+0xa20>
case omapertura2:
if(rtCiclo==0){
8001730: 4b61 ldr r3, [pc, #388] @ (80018b8 <manageCiclo+0x2b8>)
8001732: 881b ldrh r3, [r3, #0]
8001734: b29b uxth r3, r3
8001736: 2b00 cmp r3, #0
8001738: d110 bne.n 800175c <manageCiclo+0x15c>
(void)ramp(M2,BW,m2pwmap,0,tramp,RAMPINIT);
800173a: 4b5c ldr r3, [pc, #368] @ (80018ac <manageCiclo+0x2ac>)
800173c: 881b ldrh r3, [r3, #0]
800173e: b2da uxtb r2, r3
8001740: 4b5b ldr r3, [pc, #364] @ (80018b0 <manageCiclo+0x2b0>)
8001742: 881b ldrh r3, [r3, #0]
8001744: b2db uxtb r3, r3
8001746: 2100 movs r1, #0
8001748: 9101 str r1, [sp, #4]
800174a: 9300 str r3, [sp, #0]
800174c: 2300 movs r3, #0
800174e: 2101 movs r1, #1
8001750: 2002 movs r0, #2
8001752: f001 fb81 bl 8002e58 <ramp>
stCiclo=omapertura3;
8001756: 4b51 ldr r3, [pc, #324] @ (800189c <manageCiclo+0x29c>)
8001758: 2203 movs r2, #3
800175a: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
800175c: 4b50 ldr r3, [pc, #320] @ (80018a0 <manageCiclo+0x2a0>)
800175e: 781b ldrb r3, [r3, #0]
8001760: f003 0302 and.w r3, r3, #2
8001764: 2b00 cmp r3, #0
8001766: f000 845d beq.w 8002024 <manageCiclo+0xa24>
800176a: 4b4c ldr r3, [pc, #304] @ (800189c <manageCiclo+0x29c>)
800176c: 220f movs r2, #15
800176e: 701a strb r2, [r3, #0]
break;
8001770: f000 bc58 b.w 8002024 <manageCiclo+0xa24>
case omapertura3:
if(ramp(M2,BW,m2pwmap,0,tramp,RAMPRUN)==DONE){
8001774: 4b4d ldr r3, [pc, #308] @ (80018ac <manageCiclo+0x2ac>)
8001776: 881b ldrh r3, [r3, #0]
8001778: b2da uxtb r2, r3
800177a: 4b4d ldr r3, [pc, #308] @ (80018b0 <manageCiclo+0x2b0>)
800177c: 881b ldrh r3, [r3, #0]
800177e: b2db uxtb r3, r3
8001780: 210a movs r1, #10
8001782: 9101 str r1, [sp, #4]
8001784: 9300 str r3, [sp, #0]
8001786: 2300 movs r3, #0
8001788: 2101 movs r1, #1
800178a: 2002 movs r0, #2
800178c: f001 fb64 bl 8002e58 <ramp>
8001790: 4603 mov r3, r0
8001792: 2b00 cmp r3, #0
8001794: d106 bne.n 80017a4 <manageCiclo+0x1a4>
rtCiclo=twap;
8001796: 4b49 ldr r3, [pc, #292] @ (80018bc <manageCiclo+0x2bc>)
8001798: 881a ldrh r2, [r3, #0]
800179a: 4b47 ldr r3, [pc, #284] @ (80018b8 <manageCiclo+0x2b8>)
800179c: 801a strh r2, [r3, #0]
stCiclo=omapertura4;
800179e: 4b3f ldr r3, [pc, #252] @ (800189c <manageCiclo+0x29c>)
80017a0: 2204 movs r2, #4
80017a2: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
80017a4: 4b3e ldr r3, [pc, #248] @ (80018a0 <manageCiclo+0x2a0>)
80017a6: 781b ldrb r3, [r3, #0]
80017a8: f003 0302 and.w r3, r3, #2
80017ac: 2b00 cmp r3, #0
80017ae: f000 843b beq.w 8002028 <manageCiclo+0xa28>
80017b2: 4b3a ldr r3, [pc, #232] @ (800189c <manageCiclo+0x29c>)
80017b4: 220f movs r2, #15
80017b6: 701a strb r2, [r3, #0]
break;
80017b8: f000 bc36 b.w 8002028 <manageCiclo+0xa28>
case omapertura4:
if(rtCiclo==0){
80017bc: 4b3e ldr r3, [pc, #248] @ (80018b8 <manageCiclo+0x2b8>)
80017be: 881b ldrh r3, [r3, #0]
80017c0: b29b uxth r3, r3
80017c2: 2b00 cmp r3, #0
80017c4: d113 bne.n 80017ee <manageCiclo+0x1ee>
(void)ramp(M1,FW,mrampstart[M1-1],m1pwmap,tramp,RAMPINIT);
80017c6: 4b38 ldr r3, [pc, #224] @ (80018a8 <manageCiclo+0x2a8>)
80017c8: 881b ldrh r3, [r3, #0]
80017ca: b2da uxtb r2, r3
80017cc: 4b3c ldr r3, [pc, #240] @ (80018c0 <manageCiclo+0x2c0>)
80017ce: 881b ldrh r3, [r3, #0]
80017d0: b2d9 uxtb r1, r3
80017d2: 4b37 ldr r3, [pc, #220] @ (80018b0 <manageCiclo+0x2b0>)
80017d4: 881b ldrh r3, [r3, #0]
80017d6: b2db uxtb r3, r3
80017d8: 2000 movs r0, #0
80017da: 9001 str r0, [sp, #4]
80017dc: 9300 str r3, [sp, #0]
80017de: 460b mov r3, r1
80017e0: 2100 movs r1, #0
80017e2: 2001 movs r0, #1
80017e4: f001 fb38 bl 8002e58 <ramp>
stCiclo=omapertura5;
80017e8: 4b2c ldr r3, [pc, #176] @ (800189c <manageCiclo+0x29c>)
80017ea: 2205 movs r2, #5
80017ec: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
80017ee: 4b2c ldr r3, [pc, #176] @ (80018a0 <manageCiclo+0x2a0>)
80017f0: 781b ldrb r3, [r3, #0]
80017f2: f003 0302 and.w r3, r3, #2
80017f6: 2b00 cmp r3, #0
80017f8: f000 8418 beq.w 800202c <manageCiclo+0xa2c>
80017fc: 4b27 ldr r3, [pc, #156] @ (800189c <manageCiclo+0x29c>)
80017fe: 220f movs r2, #15
8001800: 701a strb r2, [r3, #0]
break;
8001802: f000 bc13 b.w 800202c <manageCiclo+0xa2c>
case omapertura5:
if(ramp(M1,FW,mrampstart[M1-1],m1pwmap,tramp,RAMPRUN)==DONE){
8001806: 4b28 ldr r3, [pc, #160] @ (80018a8 <manageCiclo+0x2a8>)
8001808: 881b ldrh r3, [r3, #0]
800180a: b2da uxtb r2, r3
800180c: 4b2c ldr r3, [pc, #176] @ (80018c0 <manageCiclo+0x2c0>)
800180e: 881b ldrh r3, [r3, #0]
8001810: b2d9 uxtb r1, r3
8001812: 4b27 ldr r3, [pc, #156] @ (80018b0 <manageCiclo+0x2b0>)
8001814: 881b ldrh r3, [r3, #0]
8001816: b2db uxtb r3, r3
8001818: 200a movs r0, #10
800181a: 9001 str r0, [sp, #4]
800181c: 9300 str r3, [sp, #0]
800181e: 460b mov r3, r1
8001820: 2100 movs r1, #0
8001822: 2001 movs r0, #1
8001824: f001 fb18 bl 8002e58 <ramp>
8001828: 4603 mov r3, r0
800182a: 2b00 cmp r3, #0
800182c: d106 bne.n 800183c <manageCiclo+0x23c>
rtCiclo=t2ap;
800182e: 4b25 ldr r3, [pc, #148] @ (80018c4 <manageCiclo+0x2c4>)
8001830: 881a ldrh r2, [r3, #0]
8001832: 4b21 ldr r3, [pc, #132] @ (80018b8 <manageCiclo+0x2b8>)
8001834: 801a strh r2, [r3, #0]
stCiclo=omapertura6;
8001836: 4b19 ldr r3, [pc, #100] @ (800189c <manageCiclo+0x29c>)
8001838: 2206 movs r2, #6
800183a: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
800183c: 4b18 ldr r3, [pc, #96] @ (80018a0 <manageCiclo+0x2a0>)
800183e: 781b ldrb r3, [r3, #0]
8001840: f003 0302 and.w r3, r3, #2
8001844: 2b00 cmp r3, #0
8001846: f000 83f3 beq.w 8002030 <manageCiclo+0xa30>
800184a: 4b14 ldr r3, [pc, #80] @ (800189c <manageCiclo+0x29c>)
800184c: 220f movs r2, #15
800184e: 701a strb r2, [r3, #0]
break;
8001850: e3ee b.n 8002030 <manageCiclo+0xa30>
case omapertura6:
if(rtCiclo==0){
8001852: 4b19 ldr r3, [pc, #100] @ (80018b8 <manageCiclo+0x2b8>)
8001854: 881b ldrh r3, [r3, #0]
8001856: b29b uxth r3, r3
8001858: 2b00 cmp r3, #0
800185a: d113 bne.n 8001884 <manageCiclo+0x284>
(void)ramp(M3,FW,mrampstart[M3-1],m3pwmap,tramp,RAMPINIT);
800185c: 4b12 ldr r3, [pc, #72] @ (80018a8 <manageCiclo+0x2a8>)
800185e: 889b ldrh r3, [r3, #4]
8001860: b2da uxtb r2, r3
8001862: 4b19 ldr r3, [pc, #100] @ (80018c8 <manageCiclo+0x2c8>)
8001864: 881b ldrh r3, [r3, #0]
8001866: b2d9 uxtb r1, r3
8001868: 4b11 ldr r3, [pc, #68] @ (80018b0 <manageCiclo+0x2b0>)
800186a: 881b ldrh r3, [r3, #0]
800186c: b2db uxtb r3, r3
800186e: 2000 movs r0, #0
8001870: 9001 str r0, [sp, #4]
8001872: 9300 str r3, [sp, #0]
8001874: 460b mov r3, r1
8001876: 2100 movs r1, #0
8001878: 2003 movs r0, #3
800187a: f001 faed bl 8002e58 <ramp>
stCiclo=omapertura7;
800187e: 4b07 ldr r3, [pc, #28] @ (800189c <manageCiclo+0x29c>)
8001880: 2207 movs r2, #7
8001882: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001884: 4b06 ldr r3, [pc, #24] @ (80018a0 <manageCiclo+0x2a0>)
8001886: 781b ldrb r3, [r3, #0]
8001888: f003 0302 and.w r3, r3, #2
800188c: 2b00 cmp r3, #0
800188e: f000 83d1 beq.w 8002034 <manageCiclo+0xa34>
8001892: 4b02 ldr r3, [pc, #8] @ (800189c <manageCiclo+0x29c>)
8001894: 220f movs r2, #15
8001896: 701a strb r2, [r3, #0]
break;
8001898: e3cc b.n 8002034 <manageCiclo+0xa34>
800189a: bf00 nop
800189c: 2000041d .word 0x2000041d
80018a0: 2000041c .word 0x2000041c
80018a4: 2000041e .word 0x2000041e
80018a8: 20000414 .word 0x20000414
80018ac: 200003f2 .word 0x200003f2
80018b0: 20000410 .word 0x20000410
80018b4: 200003fe .word 0x200003fe
80018b8: 200003ec .word 0x200003ec
80018bc: 20000406 .word 0x20000406
80018c0: 200003ee .word 0x200003ee
80018c4: 20000400 .word 0x20000400
80018c8: 200003f6 .word 0x200003f6
case omapertura7:
if(ramp(M3,FW,mrampstart[M3-1],m3pwmap,tramp,RAMPRUN)==DONE){
80018cc: 4b96 ldr r3, [pc, #600] @ (8001b28 <manageCiclo+0x528>)
80018ce: 889b ldrh r3, [r3, #4]
80018d0: b2da uxtb r2, r3
80018d2: 4b96 ldr r3, [pc, #600] @ (8001b2c <manageCiclo+0x52c>)
80018d4: 881b ldrh r3, [r3, #0]
80018d6: b2d9 uxtb r1, r3
80018d8: 4b95 ldr r3, [pc, #596] @ (8001b30 <manageCiclo+0x530>)
80018da: 881b ldrh r3, [r3, #0]
80018dc: b2db uxtb r3, r3
80018de: 200a movs r0, #10
80018e0: 9001 str r0, [sp, #4]
80018e2: 9300 str r3, [sp, #0]
80018e4: 460b mov r3, r1
80018e6: 2100 movs r1, #0
80018e8: 2003 movs r0, #3
80018ea: f001 fab5 bl 8002e58 <ramp>
80018ee: 4603 mov r3, r0
80018f0: 2b00 cmp r3, #0
80018f2: d106 bne.n 8001902 <manageCiclo+0x302>
rtCiclo=t3ap;
80018f4: 4b8f ldr r3, [pc, #572] @ (8001b34 <manageCiclo+0x534>)
80018f6: 881a ldrh r2, [r3, #0]
80018f8: 4b8f ldr r3, [pc, #572] @ (8001b38 <manageCiclo+0x538>)
80018fa: 801a strh r2, [r3, #0]
stCiclo=omapertura8;
80018fc: 4b8f ldr r3, [pc, #572] @ (8001b3c <manageCiclo+0x53c>)
80018fe: 2208 movs r2, #8
8001900: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001902: 4b8f ldr r3, [pc, #572] @ (8001b40 <manageCiclo+0x540>)
8001904: 781b ldrb r3, [r3, #0]
8001906: f003 0302 and.w r3, r3, #2
800190a: 2b00 cmp r3, #0
800190c: f000 8394 beq.w 8002038 <manageCiclo+0xa38>
8001910: 4b8a ldr r3, [pc, #552] @ (8001b3c <manageCiclo+0x53c>)
8001912: 220f movs r2, #15
8001914: 701a strb r2, [r3, #0]
break;
8001916: e38f b.n 8002038 <manageCiclo+0xa38>
case omapertura8:
if(rtCiclo==0){
8001918: 4b87 ldr r3, [pc, #540] @ (8001b38 <manageCiclo+0x538>)
800191a: 881b ldrh r3, [r3, #0]
800191c: b29b uxth r3, r3
800191e: 2b00 cmp r3, #0
8001920: d11e bne.n 8001960 <manageCiclo+0x360>
(void)ramp(M3,FW,m3pwmap,0,tramp,RAMPINIT);
8001922: 4b82 ldr r3, [pc, #520] @ (8001b2c <manageCiclo+0x52c>)
8001924: 881b ldrh r3, [r3, #0]
8001926: b2da uxtb r2, r3
8001928: 4b81 ldr r3, [pc, #516] @ (8001b30 <manageCiclo+0x530>)
800192a: 881b ldrh r3, [r3, #0]
800192c: b2db uxtb r3, r3
800192e: 2100 movs r1, #0
8001930: 9101 str r1, [sp, #4]
8001932: 9300 str r3, [sp, #0]
8001934: 2300 movs r3, #0
8001936: 2100 movs r1, #0
8001938: 2003 movs r0, #3
800193a: f001 fa8d bl 8002e58 <ramp>
(void)ramp(M1,FW,m1pwmap,0,tramp,RAMPINIT);
800193e: 4b81 ldr r3, [pc, #516] @ (8001b44 <manageCiclo+0x544>)
8001940: 881b ldrh r3, [r3, #0]
8001942: b2da uxtb r2, r3
8001944: 4b7a ldr r3, [pc, #488] @ (8001b30 <manageCiclo+0x530>)
8001946: 881b ldrh r3, [r3, #0]
8001948: b2db uxtb r3, r3
800194a: 2100 movs r1, #0
800194c: 9101 str r1, [sp, #4]
800194e: 9300 str r3, [sp, #0]
8001950: 2300 movs r3, #0
8001952: 2100 movs r1, #0
8001954: 2001 movs r0, #1
8001956: f001 fa7f bl 8002e58 <ramp>
stCiclo=omapertura9;
800195a: 4b78 ldr r3, [pc, #480] @ (8001b3c <manageCiclo+0x53c>)
800195c: 2209 movs r2, #9
800195e: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001960: 4b77 ldr r3, [pc, #476] @ (8001b40 <manageCiclo+0x540>)
8001962: 781b ldrb r3, [r3, #0]
8001964: f003 0302 and.w r3, r3, #2
8001968: 2b00 cmp r3, #0
800196a: f000 8367 beq.w 800203c <manageCiclo+0xa3c>
800196e: 4b73 ldr r3, [pc, #460] @ (8001b3c <manageCiclo+0x53c>)
8001970: 220f movs r2, #15
8001972: 701a strb r2, [r3, #0]
break;
8001974: e362 b.n 800203c <manageCiclo+0xa3c>
case omapertura9:
if((ramp(M3,FW,m3pwmap,0,tramp,RAMPRUN)==DONE)&&(ramp(M1,FW,m1pwmap,0,tramp,RAMPRUN)==DONE)){
8001976: 4b6d ldr r3, [pc, #436] @ (8001b2c <manageCiclo+0x52c>)
8001978: 881b ldrh r3, [r3, #0]
800197a: b2da uxtb r2, r3
800197c: 4b6c ldr r3, [pc, #432] @ (8001b30 <manageCiclo+0x530>)
800197e: 881b ldrh r3, [r3, #0]
8001980: b2db uxtb r3, r3
8001982: 210a movs r1, #10
8001984: 9101 str r1, [sp, #4]
8001986: 9300 str r3, [sp, #0]
8001988: 2300 movs r3, #0
800198a: 2100 movs r1, #0
800198c: 2003 movs r0, #3
800198e: f001 fa63 bl 8002e58 <ramp>
8001992: 4603 mov r3, r0
8001994: 2b00 cmp r3, #0
8001996: d117 bne.n 80019c8 <manageCiclo+0x3c8>
8001998: 4b6a ldr r3, [pc, #424] @ (8001b44 <manageCiclo+0x544>)
800199a: 881b ldrh r3, [r3, #0]
800199c: b2da uxtb r2, r3
800199e: 4b64 ldr r3, [pc, #400] @ (8001b30 <manageCiclo+0x530>)
80019a0: 881b ldrh r3, [r3, #0]
80019a2: b2db uxtb r3, r3
80019a4: 210a movs r1, #10
80019a6: 9101 str r1, [sp, #4]
80019a8: 9300 str r3, [sp, #0]
80019aa: 2300 movs r3, #0
80019ac: 2100 movs r1, #0
80019ae: 2001 movs r0, #1
80019b0: f001 fa52 bl 8002e58 <ramp>
80019b4: 4603 mov r3, r0
80019b6: 2b00 cmp r3, #0
80019b8: d106 bne.n 80019c8 <manageCiclo+0x3c8>
rtCiclo=twap;
80019ba: 4b63 ldr r3, [pc, #396] @ (8001b48 <manageCiclo+0x548>)
80019bc: 881a ldrh r2, [r3, #0]
80019be: 4b5e ldr r3, [pc, #376] @ (8001b38 <manageCiclo+0x538>)
80019c0: 801a strh r2, [r3, #0]
stCiclo=omapertura10;
80019c2: 4b5e ldr r3, [pc, #376] @ (8001b3c <manageCiclo+0x53c>)
80019c4: 220a movs r2, #10
80019c6: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
80019c8: 4b5d ldr r3, [pc, #372] @ (8001b40 <manageCiclo+0x540>)
80019ca: 781b ldrb r3, [r3, #0]
80019cc: f003 0302 and.w r3, r3, #2
80019d0: 2b00 cmp r3, #0
80019d2: f000 8335 beq.w 8002040 <manageCiclo+0xa40>
80019d6: 4b59 ldr r3, [pc, #356] @ (8001b3c <manageCiclo+0x53c>)
80019d8: 220f movs r2, #15
80019da: 701a strb r2, [r3, #0]
break;
80019dc: e330 b.n 8002040 <manageCiclo+0xa40>
case omapertura10:
if(rtCiclo==0){
80019de: 4b56 ldr r3, [pc, #344] @ (8001b38 <manageCiclo+0x538>)
80019e0: 881b ldrh r3, [r3, #0]
80019e2: b29b uxth r3, r3
80019e4: 2b00 cmp r3, #0
80019e6: d113 bne.n 8001a10 <manageCiclo+0x410>
(void)ramp(M4,FW,mrampstart[M4-1],m4pwmap,tramp,RAMPINIT);
80019e8: 4b4f ldr r3, [pc, #316] @ (8001b28 <manageCiclo+0x528>)
80019ea: 88db ldrh r3, [r3, #6]
80019ec: b2da uxtb r2, r3
80019ee: 4b57 ldr r3, [pc, #348] @ (8001b4c <manageCiclo+0x54c>)
80019f0: 881b ldrh r3, [r3, #0]
80019f2: b2d9 uxtb r1, r3
80019f4: 4b4e ldr r3, [pc, #312] @ (8001b30 <manageCiclo+0x530>)
80019f6: 881b ldrh r3, [r3, #0]
80019f8: b2db uxtb r3, r3
80019fa: 2000 movs r0, #0
80019fc: 9001 str r0, [sp, #4]
80019fe: 9300 str r3, [sp, #0]
8001a00: 460b mov r3, r1
8001a02: 2100 movs r1, #0
8001a04: 2004 movs r0, #4
8001a06: f001 fa27 bl 8002e58 <ramp>
stCiclo=omapertura11;
8001a0a: 4b4c ldr r3, [pc, #304] @ (8001b3c <manageCiclo+0x53c>)
8001a0c: 220b movs r2, #11
8001a0e: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001a10: 4b4b ldr r3, [pc, #300] @ (8001b40 <manageCiclo+0x540>)
8001a12: 781b ldrb r3, [r3, #0]
8001a14: f003 0302 and.w r3, r3, #2
8001a18: 2b00 cmp r3, #0
8001a1a: f000 8313 beq.w 8002044 <manageCiclo+0xa44>
8001a1e: 4b47 ldr r3, [pc, #284] @ (8001b3c <manageCiclo+0x53c>)
8001a20: 220f movs r2, #15
8001a22: 701a strb r2, [r3, #0]
break;
8001a24: e30e b.n 8002044 <manageCiclo+0xa44>
case omapertura11:
if(ramp(M4,FW,mrampstart[M4-1],m4pwmap,tramp,RAMPRUN)==DONE){
8001a26: 4b40 ldr r3, [pc, #256] @ (8001b28 <manageCiclo+0x528>)
8001a28: 88db ldrh r3, [r3, #6]
8001a2a: b2da uxtb r2, r3
8001a2c: 4b47 ldr r3, [pc, #284] @ (8001b4c <manageCiclo+0x54c>)
8001a2e: 881b ldrh r3, [r3, #0]
8001a30: b2d9 uxtb r1, r3
8001a32: 4b3f ldr r3, [pc, #252] @ (8001b30 <manageCiclo+0x530>)
8001a34: 881b ldrh r3, [r3, #0]
8001a36: b2db uxtb r3, r3
8001a38: 200a movs r0, #10
8001a3a: 9001 str r0, [sp, #4]
8001a3c: 9300 str r3, [sp, #0]
8001a3e: 460b mov r3, r1
8001a40: 2100 movs r1, #0
8001a42: 2004 movs r0, #4
8001a44: f001 fa08 bl 8002e58 <ramp>
8001a48: 4603 mov r3, r0
8001a4a: 2b00 cmp r3, #0
8001a4c: d106 bne.n 8001a5c <manageCiclo+0x45c>
rtCiclo=t4ap;
8001a4e: 4b40 ldr r3, [pc, #256] @ (8001b50 <manageCiclo+0x550>)
8001a50: 881a ldrh r2, [r3, #0]
8001a52: 4b39 ldr r3, [pc, #228] @ (8001b38 <manageCiclo+0x538>)
8001a54: 801a strh r2, [r3, #0]
stCiclo=omapertura12;
8001a56: 4b39 ldr r3, [pc, #228] @ (8001b3c <manageCiclo+0x53c>)
8001a58: 220c movs r2, #12
8001a5a: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001a5c: 4b38 ldr r3, [pc, #224] @ (8001b40 <manageCiclo+0x540>)
8001a5e: 781b ldrb r3, [r3, #0]
8001a60: f003 0302 and.w r3, r3, #2
8001a64: 2b00 cmp r3, #0
8001a66: f000 82ef beq.w 8002048 <manageCiclo+0xa48>
8001a6a: 4b34 ldr r3, [pc, #208] @ (8001b3c <manageCiclo+0x53c>)
8001a6c: 220f movs r2, #15
8001a6e: 701a strb r2, [r3, #0]
break;
8001a70: e2ea b.n 8002048 <manageCiclo+0xa48>
case omapertura12:
if(rtCiclo==0){
8001a72: 4b31 ldr r3, [pc, #196] @ (8001b38 <manageCiclo+0x538>)
8001a74: 881b ldrh r3, [r3, #0]
8001a76: b29b uxth r3, r3
8001a78: 2b00 cmp r3, #0
8001a7a: d110 bne.n 8001a9e <manageCiclo+0x49e>
(void)ramp(M4,FW,m4pwmap,0,tramp,RAMPINIT);
8001a7c: 4b33 ldr r3, [pc, #204] @ (8001b4c <manageCiclo+0x54c>)
8001a7e: 881b ldrh r3, [r3, #0]
8001a80: b2da uxtb r2, r3
8001a82: 4b2b ldr r3, [pc, #172] @ (8001b30 <manageCiclo+0x530>)
8001a84: 881b ldrh r3, [r3, #0]
8001a86: b2db uxtb r3, r3
8001a88: 2100 movs r1, #0
8001a8a: 9101 str r1, [sp, #4]
8001a8c: 9300 str r3, [sp, #0]
8001a8e: 2300 movs r3, #0
8001a90: 2100 movs r1, #0
8001a92: 2004 movs r0, #4
8001a94: f001 f9e0 bl 8002e58 <ramp>
stCiclo=omapertura13;
8001a98: 4b28 ldr r3, [pc, #160] @ (8001b3c <manageCiclo+0x53c>)
8001a9a: 220d movs r2, #13
8001a9c: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001a9e: 4b28 ldr r3, [pc, #160] @ (8001b40 <manageCiclo+0x540>)
8001aa0: 781b ldrb r3, [r3, #0]
8001aa2: f003 0302 and.w r3, r3, #2
8001aa6: 2b00 cmp r3, #0
8001aa8: f000 82d0 beq.w 800204c <manageCiclo+0xa4c>
8001aac: 4b23 ldr r3, [pc, #140] @ (8001b3c <manageCiclo+0x53c>)
8001aae: 220f movs r2, #15
8001ab0: 701a strb r2, [r3, #0]
break;
8001ab2: e2cb b.n 800204c <manageCiclo+0xa4c>
case omapertura13:
if(ramp(M4,FW,m4pwmap,0,tramp,RAMPRUN)==DONE){
8001ab4: 4b25 ldr r3, [pc, #148] @ (8001b4c <manageCiclo+0x54c>)
8001ab6: 881b ldrh r3, [r3, #0]
8001ab8: b2da uxtb r2, r3
8001aba: 4b1d ldr r3, [pc, #116] @ (8001b30 <manageCiclo+0x530>)
8001abc: 881b ldrh r3, [r3, #0]
8001abe: b2db uxtb r3, r3
8001ac0: 210a movs r1, #10
8001ac2: 9101 str r1, [sp, #4]
8001ac4: 9300 str r3, [sp, #0]
8001ac6: 2300 movs r3, #0
8001ac8: 2100 movs r1, #0
8001aca: 2004 movs r0, #4
8001acc: f001 f9c4 bl 8002e58 <ramp>
8001ad0: 4603 mov r3, r0
8001ad2: 2b00 cmp r3, #0
8001ad4: d106 bne.n 8001ae4 <manageCiclo+0x4e4>
rtCiclo=twap;
8001ad6: 4b1c ldr r3, [pc, #112] @ (8001b48 <manageCiclo+0x548>)
8001ad8: 881a ldrh r2, [r3, #0]
8001ada: 4b17 ldr r3, [pc, #92] @ (8001b38 <manageCiclo+0x538>)
8001adc: 801a strh r2, [r3, #0]
stCiclo=omapertura14;
8001ade: 4b17 ldr r3, [pc, #92] @ (8001b3c <manageCiclo+0x53c>)
8001ae0: 220e movs r2, #14
8001ae2: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001ae4: 4b16 ldr r3, [pc, #88] @ (8001b40 <manageCiclo+0x540>)
8001ae6: 781b ldrb r3, [r3, #0]
8001ae8: f003 0302 and.w r3, r3, #2
8001aec: 2b00 cmp r3, #0
8001aee: f000 82af beq.w 8002050 <manageCiclo+0xa50>
8001af2: 4b12 ldr r3, [pc, #72] @ (8001b3c <manageCiclo+0x53c>)
8001af4: 220f movs r2, #15
8001af6: 701a strb r2, [r3, #0]
break;
8001af8: e2aa b.n 8002050 <manageCiclo+0xa50>
case omapertura14:
if(rtCiclo==0){
8001afa: 4b0f ldr r3, [pc, #60] @ (8001b38 <manageCiclo+0x538>)
8001afc: 881b ldrh r3, [r3, #0]
8001afe: b29b uxth r3, r3
8001b00: 2b00 cmp r3, #0
8001b02: d105 bne.n 8001b10 <manageCiclo+0x510>
stBuz=bzoff;
8001b04: 4b13 ldr r3, [pc, #76] @ (8001b54 <manageCiclo+0x554>)
8001b06: 2200 movs r2, #0
8001b08: 701a strb r2, [r3, #0]
stCiclo=omaperto;
8001b0a: 4b0c ldr r3, [pc, #48] @ (8001b3c <manageCiclo+0x53c>)
8001b0c: 2210 movs r2, #16
8001b0e: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopapertura;
8001b10: 4b0b ldr r3, [pc, #44] @ (8001b40 <manageCiclo+0x540>)
8001b12: 781b ldrb r3, [r3, #0]
8001b14: f003 0302 and.w r3, r3, #2
8001b18: 2b00 cmp r3, #0
8001b1a: f000 829b beq.w 8002054 <manageCiclo+0xa54>
8001b1e: 4b07 ldr r3, [pc, #28] @ (8001b3c <manageCiclo+0x53c>)
8001b20: 220f movs r2, #15
8001b22: 701a strb r2, [r3, #0]
break;
8001b24: e296 b.n 8002054 <manageCiclo+0xa54>
8001b26: bf00 nop
8001b28: 20000414 .word 0x20000414
8001b2c: 200003f6 .word 0x200003f6
8001b30: 20000410 .word 0x20000410
8001b34: 20000402 .word 0x20000402
8001b38: 200003ec .word 0x200003ec
8001b3c: 2000041d .word 0x2000041d
8001b40: 2000041c .word 0x2000041c
8001b44: 200003ee .word 0x200003ee
8001b48: 20000406 .word 0x20000406
8001b4c: 200003fa .word 0x200003fa
8001b50: 20000404 .word 0x20000404
8001b54: 2000041e .word 0x2000041e
case omstopapertura:
SetMotPerc(M1,FW,0);
8001b58: 2200 movs r2, #0
8001b5a: 2100 movs r1, #0
8001b5c: 2001 movs r0, #1
8001b5e: f000 fffb bl 8002b58 <SetMotPerc>
SetMotPerc(M2,FW,0);
8001b62: 2200 movs r2, #0
8001b64: 2100 movs r1, #0
8001b66: 2002 movs r0, #2
8001b68: f000 fff6 bl 8002b58 <SetMotPerc>
SetMotPerc(M3,FW,0);
8001b6c: 2200 movs r2, #0
8001b6e: 2100 movs r1, #0
8001b70: 2003 movs r0, #3
8001b72: f000 fff1 bl 8002b58 <SetMotPerc>
SetMotPerc(M4,FW,0);
8001b76: 2200 movs r2, #0
8001b78: 2100 movs r1, #0
8001b7a: 2004 movs r0, #4
8001b7c: f000 ffec bl 8002b58 <SetMotPerc>
stBuz=bzoff;
8001b80: 4b96 ldr r3, [pc, #600] @ (8001ddc <manageCiclo+0x7dc>)
8001b82: 2200 movs r2, #0
8001b84: 701a strb r2, [r3, #0]
stCiclo=omchiuso;
8001b86: 4b96 ldr r3, [pc, #600] @ (8001de0 <manageCiclo+0x7e0>)
8001b88: 2200 movs r2, #0
8001b8a: 701a strb r2, [r3, #0]
stPulsanti&=(~P1STOP);
8001b8c: 4b95 ldr r3, [pc, #596] @ (8001de4 <manageCiclo+0x7e4>)
8001b8e: 781b ldrb r3, [r3, #0]
8001b90: f023 0302 bic.w r3, r3, #2
8001b94: b2da uxtb r2, r3
8001b96: 4b93 ldr r3, [pc, #588] @ (8001de4 <manageCiclo+0x7e4>)
8001b98: 701a strb r2, [r3, #0]
break;
8001b9a: e276 b.n 800208a <manageCiclo+0xa8a>
case omaperto:
if(stPulsanti&P1START){
8001b9c: 4b91 ldr r3, [pc, #580] @ (8001de4 <manageCiclo+0x7e4>)
8001b9e: 781b ldrb r3, [r3, #0]
8001ba0: f003 0301 and.w r3, r3, #1
8001ba4: 2b00 cmp r3, #0
8001ba6: d027 beq.n 8001bf8 <manageCiclo+0x5f8>
stBuz=bzmoving;
8001ba8: 4b8c ldr r3, [pc, #560] @ (8001ddc <manageCiclo+0x7dc>)
8001baa: 2201 movs r2, #1
8001bac: 701a strb r2, [r3, #0]
(void)ramp(M3,BW,mrampstart[M3-1],m3pwmch,tramp,RAMPINIT);
8001bae: 4b8e ldr r3, [pc, #568] @ (8001de8 <manageCiclo+0x7e8>)
8001bb0: 889b ldrh r3, [r3, #4]
8001bb2: b2da uxtb r2, r3
8001bb4: 4b8d ldr r3, [pc, #564] @ (8001dec <manageCiclo+0x7ec>)
8001bb6: 881b ldrh r3, [r3, #0]
8001bb8: b2d9 uxtb r1, r3
8001bba: 4b8d ldr r3, [pc, #564] @ (8001df0 <manageCiclo+0x7f0>)
8001bbc: 881b ldrh r3, [r3, #0]
8001bbe: b2db uxtb r3, r3
8001bc0: 2000 movs r0, #0
8001bc2: 9001 str r0, [sp, #4]
8001bc4: 9300 str r3, [sp, #0]
8001bc6: 460b mov r3, r1
8001bc8: 2101 movs r1, #1
8001bca: 2003 movs r0, #3
8001bcc: f001 f944 bl 8002e58 <ramp>
(void)ramp(M1,BW,mrampstart[M1-1],m1pwmch,tramp,RAMPINIT);
8001bd0: 4b85 ldr r3, [pc, #532] @ (8001de8 <manageCiclo+0x7e8>)
8001bd2: 881b ldrh r3, [r3, #0]
8001bd4: b2da uxtb r2, r3
8001bd6: 4b87 ldr r3, [pc, #540] @ (8001df4 <manageCiclo+0x7f4>)
8001bd8: 881b ldrh r3, [r3, #0]
8001bda: b2d9 uxtb r1, r3
8001bdc: 4b84 ldr r3, [pc, #528] @ (8001df0 <manageCiclo+0x7f0>)
8001bde: 881b ldrh r3, [r3, #0]
8001be0: b2db uxtb r3, r3
8001be2: 2000 movs r0, #0
8001be4: 9001 str r0, [sp, #4]
8001be6: 9300 str r3, [sp, #0]
8001be8: 460b mov r3, r1
8001bea: 2101 movs r1, #1
8001bec: 2001 movs r0, #1
8001bee: f001 f933 bl 8002e58 <ramp>
stCiclo=omchiusura1;
8001bf2: 4b7b ldr r3, [pc, #492] @ (8001de0 <manageCiclo+0x7e0>)
8001bf4: 2211 movs r2, #17
8001bf6: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001bf8: 4b7a ldr r3, [pc, #488] @ (8001de4 <manageCiclo+0x7e4>)
8001bfa: 781b ldrb r3, [r3, #0]
8001bfc: f003 0302 and.w r3, r3, #2
8001c00: 2b00 cmp r3, #0
8001c02: f000 8229 beq.w 8002058 <manageCiclo+0xa58>
8001c06: 4b76 ldr r3, [pc, #472] @ (8001de0 <manageCiclo+0x7e0>)
8001c08: 221d movs r2, #29
8001c0a: 701a strb r2, [r3, #0]
break;
8001c0c: e224 b.n 8002058 <manageCiclo+0xa58>
case omchiusura1:
if((ramp(M3,BW,mrampstart[M3-1],m3pwmch,tramp,RAMPRUN)==DONE)&&(ramp(M1,BW,mrampstart[M1-1],m1pwmch,tramp,RAMPRUN)==DONE)){
8001c0e: 4b76 ldr r3, [pc, #472] @ (8001de8 <manageCiclo+0x7e8>)
8001c10: 889b ldrh r3, [r3, #4]
8001c12: b2da uxtb r2, r3
8001c14: 4b75 ldr r3, [pc, #468] @ (8001dec <manageCiclo+0x7ec>)
8001c16: 881b ldrh r3, [r3, #0]
8001c18: b2d9 uxtb r1, r3
8001c1a: 4b75 ldr r3, [pc, #468] @ (8001df0 <manageCiclo+0x7f0>)
8001c1c: 881b ldrh r3, [r3, #0]
8001c1e: b2db uxtb r3, r3
8001c20: 200a movs r0, #10
8001c22: 9001 str r0, [sp, #4]
8001c24: 9300 str r3, [sp, #0]
8001c26: 460b mov r3, r1
8001c28: 2101 movs r1, #1
8001c2a: 2003 movs r0, #3
8001c2c: f001 f914 bl 8002e58 <ramp>
8001c30: 4603 mov r3, r0
8001c32: 2b00 cmp r3, #0
8001c34: d11a bne.n 8001c6c <manageCiclo+0x66c>
8001c36: 4b6c ldr r3, [pc, #432] @ (8001de8 <manageCiclo+0x7e8>)
8001c38: 881b ldrh r3, [r3, #0]
8001c3a: b2da uxtb r2, r3
8001c3c: 4b6d ldr r3, [pc, #436] @ (8001df4 <manageCiclo+0x7f4>)
8001c3e: 881b ldrh r3, [r3, #0]
8001c40: b2d9 uxtb r1, r3
8001c42: 4b6b ldr r3, [pc, #428] @ (8001df0 <manageCiclo+0x7f0>)
8001c44: 881b ldrh r3, [r3, #0]
8001c46: b2db uxtb r3, r3
8001c48: 200a movs r0, #10
8001c4a: 9001 str r0, [sp, #4]
8001c4c: 9300 str r3, [sp, #0]
8001c4e: 460b mov r3, r1
8001c50: 2101 movs r1, #1
8001c52: 2001 movs r0, #1
8001c54: f001 f900 bl 8002e58 <ramp>
8001c58: 4603 mov r3, r0
8001c5a: 2b00 cmp r3, #0
8001c5c: d106 bne.n 8001c6c <manageCiclo+0x66c>
rtCiclo=t1ch;
8001c5e: 4b66 ldr r3, [pc, #408] @ (8001df8 <manageCiclo+0x7f8>)
8001c60: 881a ldrh r2, [r3, #0]
8001c62: 4b66 ldr r3, [pc, #408] @ (8001dfc <manageCiclo+0x7fc>)
8001c64: 801a strh r2, [r3, #0]
stCiclo=omchiusura2;
8001c66: 4b5e ldr r3, [pc, #376] @ (8001de0 <manageCiclo+0x7e0>)
8001c68: 2212 movs r2, #18
8001c6a: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001c6c: 4b5d ldr r3, [pc, #372] @ (8001de4 <manageCiclo+0x7e4>)
8001c6e: 781b ldrb r3, [r3, #0]
8001c70: f003 0302 and.w r3, r3, #2
8001c74: 2b00 cmp r3, #0
8001c76: f000 81f1 beq.w 800205c <manageCiclo+0xa5c>
8001c7a: 4b59 ldr r3, [pc, #356] @ (8001de0 <manageCiclo+0x7e0>)
8001c7c: 221d movs r2, #29
8001c7e: 701a strb r2, [r3, #0]
break;
8001c80: e1ec b.n 800205c <manageCiclo+0xa5c>
case omchiusura2:
if(rtCiclo==0){
8001c82: 4b5e ldr r3, [pc, #376] @ (8001dfc <manageCiclo+0x7fc>)
8001c84: 881b ldrh r3, [r3, #0]
8001c86: b29b uxth r3, r3
8001c88: 2b00 cmp r3, #0
8001c8a: d11e bne.n 8001cca <manageCiclo+0x6ca>
(void)ramp(M3,BW,m3pwmch,0,tramp,RAMPINIT);
8001c8c: 4b57 ldr r3, [pc, #348] @ (8001dec <manageCiclo+0x7ec>)
8001c8e: 881b ldrh r3, [r3, #0]
8001c90: b2da uxtb r2, r3
8001c92: 4b57 ldr r3, [pc, #348] @ (8001df0 <manageCiclo+0x7f0>)
8001c94: 881b ldrh r3, [r3, #0]
8001c96: b2db uxtb r3, r3
8001c98: 2100 movs r1, #0
8001c9a: 9101 str r1, [sp, #4]
8001c9c: 9300 str r3, [sp, #0]
8001c9e: 2300 movs r3, #0
8001ca0: 2101 movs r1, #1
8001ca2: 2003 movs r0, #3
8001ca4: f001 f8d8 bl 8002e58 <ramp>
(void)ramp(M1,BW,m1pwmch,0,tramp,RAMPINIT);
8001ca8: 4b52 ldr r3, [pc, #328] @ (8001df4 <manageCiclo+0x7f4>)
8001caa: 881b ldrh r3, [r3, #0]
8001cac: b2da uxtb r2, r3
8001cae: 4b50 ldr r3, [pc, #320] @ (8001df0 <manageCiclo+0x7f0>)
8001cb0: 881b ldrh r3, [r3, #0]
8001cb2: b2db uxtb r3, r3
8001cb4: 2100 movs r1, #0
8001cb6: 9101 str r1, [sp, #4]
8001cb8: 9300 str r3, [sp, #0]
8001cba: 2300 movs r3, #0
8001cbc: 2101 movs r1, #1
8001cbe: 2001 movs r0, #1
8001cc0: f001 f8ca bl 8002e58 <ramp>
stCiclo=omchiusura3;
8001cc4: 4b46 ldr r3, [pc, #280] @ (8001de0 <manageCiclo+0x7e0>)
8001cc6: 2213 movs r2, #19
8001cc8: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001cca: 4b46 ldr r3, [pc, #280] @ (8001de4 <manageCiclo+0x7e4>)
8001ccc: 781b ldrb r3, [r3, #0]
8001cce: f003 0302 and.w r3, r3, #2
8001cd2: 2b00 cmp r3, #0
8001cd4: f000 81c4 beq.w 8002060 <manageCiclo+0xa60>
8001cd8: 4b41 ldr r3, [pc, #260] @ (8001de0 <manageCiclo+0x7e0>)
8001cda: 221d movs r2, #29
8001cdc: 701a strb r2, [r3, #0]
break;
8001cde: e1bf b.n 8002060 <manageCiclo+0xa60>
case omchiusura3:
if((ramp(M3,BW,m3pwmch,0,tramp,RAMPRUN)==DONE)&&(ramp(M1,BW,m1pwmch,0,tramp,RAMPRUN)==DONE)){
8001ce0: 4b42 ldr r3, [pc, #264] @ (8001dec <manageCiclo+0x7ec>)
8001ce2: 881b ldrh r3, [r3, #0]
8001ce4: b2da uxtb r2, r3
8001ce6: 4b42 ldr r3, [pc, #264] @ (8001df0 <manageCiclo+0x7f0>)
8001ce8: 881b ldrh r3, [r3, #0]
8001cea: b2db uxtb r3, r3
8001cec: 210a movs r1, #10
8001cee: 9101 str r1, [sp, #4]
8001cf0: 9300 str r3, [sp, #0]
8001cf2: 2300 movs r3, #0
8001cf4: 2101 movs r1, #1
8001cf6: 2003 movs r0, #3
8001cf8: f001 f8ae bl 8002e58 <ramp>
8001cfc: 4603 mov r3, r0
8001cfe: 2b00 cmp r3, #0
8001d00: d117 bne.n 8001d32 <manageCiclo+0x732>
8001d02: 4b3c ldr r3, [pc, #240] @ (8001df4 <manageCiclo+0x7f4>)
8001d04: 881b ldrh r3, [r3, #0]
8001d06: b2da uxtb r2, r3
8001d08: 4b39 ldr r3, [pc, #228] @ (8001df0 <manageCiclo+0x7f0>)
8001d0a: 881b ldrh r3, [r3, #0]
8001d0c: b2db uxtb r3, r3
8001d0e: 210a movs r1, #10
8001d10: 9101 str r1, [sp, #4]
8001d12: 9300 str r3, [sp, #0]
8001d14: 2300 movs r3, #0
8001d16: 2101 movs r1, #1
8001d18: 2001 movs r0, #1
8001d1a: f001 f89d bl 8002e58 <ramp>
8001d1e: 4603 mov r3, r0
8001d20: 2b00 cmp r3, #0
8001d22: d106 bne.n 8001d32 <manageCiclo+0x732>
rtCiclo=twch;
8001d24: 4b36 ldr r3, [pc, #216] @ (8001e00 <manageCiclo+0x800>)
8001d26: 881a ldrh r2, [r3, #0]
8001d28: 4b34 ldr r3, [pc, #208] @ (8001dfc <manageCiclo+0x7fc>)
8001d2a: 801a strh r2, [r3, #0]
stCiclo=omchiusura4;
8001d2c: 4b2c ldr r3, [pc, #176] @ (8001de0 <manageCiclo+0x7e0>)
8001d2e: 2214 movs r2, #20
8001d30: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001d32: 4b2c ldr r3, [pc, #176] @ (8001de4 <manageCiclo+0x7e4>)
8001d34: 781b ldrb r3, [r3, #0]
8001d36: f003 0302 and.w r3, r3, #2
8001d3a: 2b00 cmp r3, #0
8001d3c: f000 8192 beq.w 8002064 <manageCiclo+0xa64>
8001d40: 4b27 ldr r3, [pc, #156] @ (8001de0 <manageCiclo+0x7e0>)
8001d42: 221d movs r2, #29
8001d44: 701a strb r2, [r3, #0]
break;
8001d46: e18d b.n 8002064 <manageCiclo+0xa64>
case omchiusura4:
if(rtCiclo==0){
8001d48: 4b2c ldr r3, [pc, #176] @ (8001dfc <manageCiclo+0x7fc>)
8001d4a: 881b ldrh r3, [r3, #0]
8001d4c: b29b uxth r3, r3
8001d4e: 2b00 cmp r3, #0
8001d50: d113 bne.n 8001d7a <manageCiclo+0x77a>
(void)ramp(M2,FW,mrampstart[M2-1],m2pwmch,tramp,RAMPINIT);
8001d52: 4b25 ldr r3, [pc, #148] @ (8001de8 <manageCiclo+0x7e8>)
8001d54: 885b ldrh r3, [r3, #2]
8001d56: b2da uxtb r2, r3
8001d58: 4b2a ldr r3, [pc, #168] @ (8001e04 <manageCiclo+0x804>)
8001d5a: 881b ldrh r3, [r3, #0]
8001d5c: b2d9 uxtb r1, r3
8001d5e: 4b24 ldr r3, [pc, #144] @ (8001df0 <manageCiclo+0x7f0>)
8001d60: 881b ldrh r3, [r3, #0]
8001d62: b2db uxtb r3, r3
8001d64: 2000 movs r0, #0
8001d66: 9001 str r0, [sp, #4]
8001d68: 9300 str r3, [sp, #0]
8001d6a: 460b mov r3, r1
8001d6c: 2100 movs r1, #0
8001d6e: 2002 movs r0, #2
8001d70: f001 f872 bl 8002e58 <ramp>
stCiclo=omchiusura5;
8001d74: 4b1a ldr r3, [pc, #104] @ (8001de0 <manageCiclo+0x7e0>)
8001d76: 2215 movs r2, #21
8001d78: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001d7a: 4b1a ldr r3, [pc, #104] @ (8001de4 <manageCiclo+0x7e4>)
8001d7c: 781b ldrb r3, [r3, #0]
8001d7e: f003 0302 and.w r3, r3, #2
8001d82: 2b00 cmp r3, #0
8001d84: f000 8170 beq.w 8002068 <manageCiclo+0xa68>
8001d88: 4b15 ldr r3, [pc, #84] @ (8001de0 <manageCiclo+0x7e0>)
8001d8a: 221d movs r2, #29
8001d8c: 701a strb r2, [r3, #0]
break;
8001d8e: e16b b.n 8002068 <manageCiclo+0xa68>
case omchiusura5:
if(ramp(M2,FW,mrampstart[M2-1],m2pwmch,tramp,RAMPRUN)==DONE){
8001d90: 4b15 ldr r3, [pc, #84] @ (8001de8 <manageCiclo+0x7e8>)
8001d92: 885b ldrh r3, [r3, #2]
8001d94: b2da uxtb r2, r3
8001d96: 4b1b ldr r3, [pc, #108] @ (8001e04 <manageCiclo+0x804>)
8001d98: 881b ldrh r3, [r3, #0]
8001d9a: b2d9 uxtb r1, r3
8001d9c: 4b14 ldr r3, [pc, #80] @ (8001df0 <manageCiclo+0x7f0>)
8001d9e: 881b ldrh r3, [r3, #0]
8001da0: b2db uxtb r3, r3
8001da2: 200a movs r0, #10
8001da4: 9001 str r0, [sp, #4]
8001da6: 9300 str r3, [sp, #0]
8001da8: 460b mov r3, r1
8001daa: 2100 movs r1, #0
8001dac: 2002 movs r0, #2
8001dae: f001 f853 bl 8002e58 <ramp>
8001db2: 4603 mov r3, r0
8001db4: 2b00 cmp r3, #0
8001db6: d106 bne.n 8001dc6 <manageCiclo+0x7c6>
rtCiclo=t2ch;
8001db8: 4b13 ldr r3, [pc, #76] @ (8001e08 <manageCiclo+0x808>)
8001dba: 881a ldrh r2, [r3, #0]
8001dbc: 4b0f ldr r3, [pc, #60] @ (8001dfc <manageCiclo+0x7fc>)
8001dbe: 801a strh r2, [r3, #0]
stCiclo=omchiusura6;
8001dc0: 4b07 ldr r3, [pc, #28] @ (8001de0 <manageCiclo+0x7e0>)
8001dc2: 2216 movs r2, #22
8001dc4: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001dc6: 4b07 ldr r3, [pc, #28] @ (8001de4 <manageCiclo+0x7e4>)
8001dc8: 781b ldrb r3, [r3, #0]
8001dca: f003 0302 and.w r3, r3, #2
8001dce: 2b00 cmp r3, #0
8001dd0: f000 814c beq.w 800206c <manageCiclo+0xa6c>
8001dd4: 4b02 ldr r3, [pc, #8] @ (8001de0 <manageCiclo+0x7e0>)
8001dd6: 221d movs r2, #29
8001dd8: 701a strb r2, [r3, #0]
break;
8001dda: e147 b.n 800206c <manageCiclo+0xa6c>
8001ddc: 2000041e .word 0x2000041e
8001de0: 2000041d .word 0x2000041d
8001de4: 2000041c .word 0x2000041c
8001de8: 20000414 .word 0x20000414
8001dec: 200003f8 .word 0x200003f8
8001df0: 20000410 .word 0x20000410
8001df4: 200003f0 .word 0x200003f0
8001df8: 20000408 .word 0x20000408
8001dfc: 200003ec .word 0x200003ec
8001e00: 2000040e .word 0x2000040e
8001e04: 200003f4 .word 0x200003f4
8001e08: 2000040a .word 0x2000040a
case omchiusura6:
if(rtCiclo==0){
8001e0c: 4ba0 ldr r3, [pc, #640] @ (8002090 <manageCiclo+0xa90>)
8001e0e: 881b ldrh r3, [r3, #0]
8001e10: b29b uxth r3, r3
8001e12: 2b00 cmp r3, #0
8001e14: d110 bne.n 8001e38 <manageCiclo+0x838>
(void)ramp(M2,FW,m2pwmch,0,tramp,RAMPINIT);
8001e16: 4b9f ldr r3, [pc, #636] @ (8002094 <manageCiclo+0xa94>)
8001e18: 881b ldrh r3, [r3, #0]
8001e1a: b2da uxtb r2, r3
8001e1c: 4b9e ldr r3, [pc, #632] @ (8002098 <manageCiclo+0xa98>)
8001e1e: 881b ldrh r3, [r3, #0]
8001e20: b2db uxtb r3, r3
8001e22: 2100 movs r1, #0
8001e24: 9101 str r1, [sp, #4]
8001e26: 9300 str r3, [sp, #0]
8001e28: 2300 movs r3, #0
8001e2a: 2100 movs r1, #0
8001e2c: 2002 movs r0, #2
8001e2e: f001 f813 bl 8002e58 <ramp>
stCiclo=omchiusura7;
8001e32: 4b9a ldr r3, [pc, #616] @ (800209c <manageCiclo+0xa9c>)
8001e34: 2217 movs r2, #23
8001e36: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001e38: 4b99 ldr r3, [pc, #612] @ (80020a0 <manageCiclo+0xaa0>)
8001e3a: 781b ldrb r3, [r3, #0]
8001e3c: f003 0302 and.w r3, r3, #2
8001e40: 2b00 cmp r3, #0
8001e42: f000 8115 beq.w 8002070 <manageCiclo+0xa70>
8001e46: 4b95 ldr r3, [pc, #596] @ (800209c <manageCiclo+0xa9c>)
8001e48: 221d movs r2, #29
8001e4a: 701a strb r2, [r3, #0]
break;
8001e4c: e110 b.n 8002070 <manageCiclo+0xa70>
case omchiusura7:
if(ramp(M2,FW,m2pwmch,0,tramp,RAMPRUN)==DONE){
8001e4e: 4b91 ldr r3, [pc, #580] @ (8002094 <manageCiclo+0xa94>)
8001e50: 881b ldrh r3, [r3, #0]
8001e52: b2da uxtb r2, r3
8001e54: 4b90 ldr r3, [pc, #576] @ (8002098 <manageCiclo+0xa98>)
8001e56: 881b ldrh r3, [r3, #0]
8001e58: b2db uxtb r3, r3
8001e5a: 210a movs r1, #10
8001e5c: 9101 str r1, [sp, #4]
8001e5e: 9300 str r3, [sp, #0]
8001e60: 2300 movs r3, #0
8001e62: 2100 movs r1, #0
8001e64: 2002 movs r0, #2
8001e66: f000 fff7 bl 8002e58 <ramp>
8001e6a: 4603 mov r3, r0
8001e6c: 2b00 cmp r3, #0
8001e6e: d106 bne.n 8001e7e <manageCiclo+0x87e>
rtCiclo=twch;
8001e70: 4b8c ldr r3, [pc, #560] @ (80020a4 <manageCiclo+0xaa4>)
8001e72: 881a ldrh r2, [r3, #0]
8001e74: 4b86 ldr r3, [pc, #536] @ (8002090 <manageCiclo+0xa90>)
8001e76: 801a strh r2, [r3, #0]
stCiclo=omchiusura8;
8001e78: 4b88 ldr r3, [pc, #544] @ (800209c <manageCiclo+0xa9c>)
8001e7a: 2218 movs r2, #24
8001e7c: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001e7e: 4b88 ldr r3, [pc, #544] @ (80020a0 <manageCiclo+0xaa0>)
8001e80: 781b ldrb r3, [r3, #0]
8001e82: f003 0302 and.w r3, r3, #2
8001e86: 2b00 cmp r3, #0
8001e88: f000 80f4 beq.w 8002074 <manageCiclo+0xa74>
8001e8c: 4b83 ldr r3, [pc, #524] @ (800209c <manageCiclo+0xa9c>)
8001e8e: 221d movs r2, #29
8001e90: 701a strb r2, [r3, #0]
break;
8001e92: e0ef b.n 8002074 <manageCiclo+0xa74>
case omchiusura8:
if(rtCiclo==0){
8001e94: 4b7e ldr r3, [pc, #504] @ (8002090 <manageCiclo+0xa90>)
8001e96: 881b ldrh r3, [r3, #0]
8001e98: b29b uxth r3, r3
8001e9a: 2b00 cmp r3, #0
8001e9c: d113 bne.n 8001ec6 <manageCiclo+0x8c6>
(void)ramp(M4,BW,mrampstart[M4-1],m4pwmch,tramp,RAMPINIT);
8001e9e: 4b82 ldr r3, [pc, #520] @ (80020a8 <manageCiclo+0xaa8>)
8001ea0: 88db ldrh r3, [r3, #6]
8001ea2: b2da uxtb r2, r3
8001ea4: 4b81 ldr r3, [pc, #516] @ (80020ac <manageCiclo+0xaac>)
8001ea6: 881b ldrh r3, [r3, #0]
8001ea8: b2d9 uxtb r1, r3
8001eaa: 4b7b ldr r3, [pc, #492] @ (8002098 <manageCiclo+0xa98>)
8001eac: 881b ldrh r3, [r3, #0]
8001eae: b2db uxtb r3, r3
8001eb0: 2000 movs r0, #0
8001eb2: 9001 str r0, [sp, #4]
8001eb4: 9300 str r3, [sp, #0]
8001eb6: 460b mov r3, r1
8001eb8: 2101 movs r1, #1
8001eba: 2004 movs r0, #4
8001ebc: f000 ffcc bl 8002e58 <ramp>
stCiclo=omchiusura9;
8001ec0: 4b76 ldr r3, [pc, #472] @ (800209c <manageCiclo+0xa9c>)
8001ec2: 2219 movs r2, #25
8001ec4: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001ec6: 4b76 ldr r3, [pc, #472] @ (80020a0 <manageCiclo+0xaa0>)
8001ec8: 781b ldrb r3, [r3, #0]
8001eca: f003 0302 and.w r3, r3, #2
8001ece: 2b00 cmp r3, #0
8001ed0: f000 80d2 beq.w 8002078 <manageCiclo+0xa78>
8001ed4: 4b71 ldr r3, [pc, #452] @ (800209c <manageCiclo+0xa9c>)
8001ed6: 221d movs r2, #29
8001ed8: 701a strb r2, [r3, #0]
break;
8001eda: e0cd b.n 8002078 <manageCiclo+0xa78>
case omchiusura9:
if(ramp(M4,BW,mrampstart[M4-1],m4pwmch,tramp,RAMPRUN)==DONE){
8001edc: 4b72 ldr r3, [pc, #456] @ (80020a8 <manageCiclo+0xaa8>)
8001ede: 88db ldrh r3, [r3, #6]
8001ee0: b2da uxtb r2, r3
8001ee2: 4b72 ldr r3, [pc, #456] @ (80020ac <manageCiclo+0xaac>)
8001ee4: 881b ldrh r3, [r3, #0]
8001ee6: b2d9 uxtb r1, r3
8001ee8: 4b6b ldr r3, [pc, #428] @ (8002098 <manageCiclo+0xa98>)
8001eea: 881b ldrh r3, [r3, #0]
8001eec: b2db uxtb r3, r3
8001eee: 200a movs r0, #10
8001ef0: 9001 str r0, [sp, #4]
8001ef2: 9300 str r3, [sp, #0]
8001ef4: 460b mov r3, r1
8001ef6: 2101 movs r1, #1
8001ef8: 2004 movs r0, #4
8001efa: f000 ffad bl 8002e58 <ramp>
8001efe: 4603 mov r3, r0
8001f00: 2b00 cmp r3, #0
8001f02: d106 bne.n 8001f12 <manageCiclo+0x912>
rtCiclo=t3ch;
8001f04: 4b6a ldr r3, [pc, #424] @ (80020b0 <manageCiclo+0xab0>)
8001f06: 881a ldrh r2, [r3, #0]
8001f08: 4b61 ldr r3, [pc, #388] @ (8002090 <manageCiclo+0xa90>)
8001f0a: 801a strh r2, [r3, #0]
stCiclo=omchiusura10;
8001f0c: 4b63 ldr r3, [pc, #396] @ (800209c <manageCiclo+0xa9c>)
8001f0e: 221a movs r2, #26
8001f10: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001f12: 4b63 ldr r3, [pc, #396] @ (80020a0 <manageCiclo+0xaa0>)
8001f14: 781b ldrb r3, [r3, #0]
8001f16: f003 0302 and.w r3, r3, #2
8001f1a: 2b00 cmp r3, #0
8001f1c: f000 80ae beq.w 800207c <manageCiclo+0xa7c>
8001f20: 4b5e ldr r3, [pc, #376] @ (800209c <manageCiclo+0xa9c>)
8001f22: 221d movs r2, #29
8001f24: 701a strb r2, [r3, #0]
break;
8001f26: e0a9 b.n 800207c <manageCiclo+0xa7c>
case omchiusura10:
if(rtCiclo==0){
8001f28: 4b59 ldr r3, [pc, #356] @ (8002090 <manageCiclo+0xa90>)
8001f2a: 881b ldrh r3, [r3, #0]
8001f2c: b29b uxth r3, r3
8001f2e: 2b00 cmp r3, #0
8001f30: d110 bne.n 8001f54 <manageCiclo+0x954>
(void)ramp(M4,BW,m4pwmch,0,tramp,RAMPINIT);
8001f32: 4b5e ldr r3, [pc, #376] @ (80020ac <manageCiclo+0xaac>)
8001f34: 881b ldrh r3, [r3, #0]
8001f36: b2da uxtb r2, r3
8001f38: 4b57 ldr r3, [pc, #348] @ (8002098 <manageCiclo+0xa98>)
8001f3a: 881b ldrh r3, [r3, #0]
8001f3c: b2db uxtb r3, r3
8001f3e: 2100 movs r1, #0
8001f40: 9101 str r1, [sp, #4]
8001f42: 9300 str r3, [sp, #0]
8001f44: 2300 movs r3, #0
8001f46: 2101 movs r1, #1
8001f48: 2004 movs r0, #4
8001f4a: f000 ff85 bl 8002e58 <ramp>
stCiclo=omchiusura11;
8001f4e: 4b53 ldr r3, [pc, #332] @ (800209c <manageCiclo+0xa9c>)
8001f50: 221b movs r2, #27
8001f52: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001f54: 4b52 ldr r3, [pc, #328] @ (80020a0 <manageCiclo+0xaa0>)
8001f56: 781b ldrb r3, [r3, #0]
8001f58: f003 0302 and.w r3, r3, #2
8001f5c: 2b00 cmp r3, #0
8001f5e: f000 808f beq.w 8002080 <manageCiclo+0xa80>
8001f62: 4b4e ldr r3, [pc, #312] @ (800209c <manageCiclo+0xa9c>)
8001f64: 221d movs r2, #29
8001f66: 701a strb r2, [r3, #0]
break;
8001f68: e08a b.n 8002080 <manageCiclo+0xa80>
case omchiusura11:
if(ramp(M4,BW,m4pwmch,0,tramp,RAMPRUN)==DONE){
8001f6a: 4b50 ldr r3, [pc, #320] @ (80020ac <manageCiclo+0xaac>)
8001f6c: 881b ldrh r3, [r3, #0]
8001f6e: b2da uxtb r2, r3
8001f70: 4b49 ldr r3, [pc, #292] @ (8002098 <manageCiclo+0xa98>)
8001f72: 881b ldrh r3, [r3, #0]
8001f74: b2db uxtb r3, r3
8001f76: 210a movs r1, #10
8001f78: 9101 str r1, [sp, #4]
8001f7a: 9300 str r3, [sp, #0]
8001f7c: 2300 movs r3, #0
8001f7e: 2101 movs r1, #1
8001f80: 2004 movs r0, #4
8001f82: f000 ff69 bl 8002e58 <ramp>
8001f86: 4603 mov r3, r0
8001f88: 2b00 cmp r3, #0
8001f8a: d106 bne.n 8001f9a <manageCiclo+0x99a>
rtCiclo=twch;
8001f8c: 4b45 ldr r3, [pc, #276] @ (80020a4 <manageCiclo+0xaa4>)
8001f8e: 881a ldrh r2, [r3, #0]
8001f90: 4b3f ldr r3, [pc, #252] @ (8002090 <manageCiclo+0xa90>)
8001f92: 801a strh r2, [r3, #0]
stCiclo=omchiusura12;
8001f94: 4b41 ldr r3, [pc, #260] @ (800209c <manageCiclo+0xa9c>)
8001f96: 221c movs r2, #28
8001f98: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001f9a: 4b41 ldr r3, [pc, #260] @ (80020a0 <manageCiclo+0xaa0>)
8001f9c: 781b ldrb r3, [r3, #0]
8001f9e: f003 0302 and.w r3, r3, #2
8001fa2: 2b00 cmp r3, #0
8001fa4: d06e beq.n 8002084 <manageCiclo+0xa84>
8001fa6: 4b3d ldr r3, [pc, #244] @ (800209c <manageCiclo+0xa9c>)
8001fa8: 221d movs r2, #29
8001faa: 701a strb r2, [r3, #0]
break;
8001fac: e06a b.n 8002084 <manageCiclo+0xa84>
case omchiusura12:
if(rtCiclo==0){
8001fae: 4b38 ldr r3, [pc, #224] @ (8002090 <manageCiclo+0xa90>)
8001fb0: 881b ldrh r3, [r3, #0]
8001fb2: b29b uxth r3, r3
8001fb4: 2b00 cmp r3, #0
8001fb6: d105 bne.n 8001fc4 <manageCiclo+0x9c4>
stBuz=bzoff;
8001fb8: 4b3e ldr r3, [pc, #248] @ (80020b4 <manageCiclo+0xab4>)
8001fba: 2200 movs r2, #0
8001fbc: 701a strb r2, [r3, #0]
stCiclo=omchiuso;
8001fbe: 4b37 ldr r3, [pc, #220] @ (800209c <manageCiclo+0xa9c>)
8001fc0: 2200 movs r2, #0
8001fc2: 701a strb r2, [r3, #0]
}
if(stPulsanti&P1STOP)stCiclo=omstopchiusura;
8001fc4: 4b36 ldr r3, [pc, #216] @ (80020a0 <manageCiclo+0xaa0>)
8001fc6: 781b ldrb r3, [r3, #0]
8001fc8: f003 0302 and.w r3, r3, #2
8001fcc: 2b00 cmp r3, #0
8001fce: d05b beq.n 8002088 <manageCiclo+0xa88>
8001fd0: 4b32 ldr r3, [pc, #200] @ (800209c <manageCiclo+0xa9c>)
8001fd2: 221d movs r2, #29
8001fd4: 701a strb r2, [r3, #0]
break;
8001fd6: e057 b.n 8002088 <manageCiclo+0xa88>
case omstopchiusura:
SetMotPerc(M1,FW,0);
8001fd8: 2200 movs r2, #0
8001fda: 2100 movs r1, #0
8001fdc: 2001 movs r0, #1
8001fde: f000 fdbb bl 8002b58 <SetMotPerc>
SetMotPerc(M2,FW,0);
8001fe2: 2200 movs r2, #0
8001fe4: 2100 movs r1, #0
8001fe6: 2002 movs r0, #2
8001fe8: f000 fdb6 bl 8002b58 <SetMotPerc>
SetMotPerc(M3,FW,0);
8001fec: 2200 movs r2, #0
8001fee: 2100 movs r1, #0
8001ff0: 2003 movs r0, #3
8001ff2: f000 fdb1 bl 8002b58 <SetMotPerc>
SetMotPerc(M4,FW,0);
8001ff6: 2200 movs r2, #0
8001ff8: 2100 movs r1, #0
8001ffa: 2004 movs r0, #4
8001ffc: f000 fdac bl 8002b58 <SetMotPerc>
stBuz=bzoff;
8002000: 4b2c ldr r3, [pc, #176] @ (80020b4 <manageCiclo+0xab4>)
8002002: 2200 movs r2, #0
8002004: 701a strb r2, [r3, #0]
stCiclo=omaperto;
8002006: 4b25 ldr r3, [pc, #148] @ (800209c <manageCiclo+0xa9c>)
8002008: 2210 movs r2, #16
800200a: 701a strb r2, [r3, #0]
stPulsanti&=(~P1STOP);
800200c: 4b24 ldr r3, [pc, #144] @ (80020a0 <manageCiclo+0xaa0>)
800200e: 781b ldrb r3, [r3, #0]
8002010: f023 0302 bic.w r3, r3, #2
8002014: b2da uxtb r2, r3
8002016: 4b22 ldr r3, [pc, #136] @ (80020a0 <manageCiclo+0xaa0>)
8002018: 701a strb r2, [r3, #0]
break;
800201a: e036 b.n 800208a <manageCiclo+0xa8a>
break;
800201c: bf00 nop
800201e: e034 b.n 800208a <manageCiclo+0xa8a>
break;
8002020: bf00 nop
8002022: e032 b.n 800208a <manageCiclo+0xa8a>
break;
8002024: bf00 nop
8002026: e030 b.n 800208a <manageCiclo+0xa8a>
break;
8002028: bf00 nop
800202a: e02e b.n 800208a <manageCiclo+0xa8a>
break;
800202c: bf00 nop
800202e: e02c b.n 800208a <manageCiclo+0xa8a>
break;
8002030: bf00 nop
8002032: e02a b.n 800208a <manageCiclo+0xa8a>
break;
8002034: bf00 nop
8002036: e028 b.n 800208a <manageCiclo+0xa8a>
break;
8002038: bf00 nop
800203a: e026 b.n 800208a <manageCiclo+0xa8a>
break;
800203c: bf00 nop
800203e: e024 b.n 800208a <manageCiclo+0xa8a>
break;
8002040: bf00 nop
8002042: e022 b.n 800208a <manageCiclo+0xa8a>
break;
8002044: bf00 nop
8002046: e020 b.n 800208a <manageCiclo+0xa8a>
break;
8002048: bf00 nop
800204a: e01e b.n 800208a <manageCiclo+0xa8a>
break;
800204c: bf00 nop
800204e: e01c b.n 800208a <manageCiclo+0xa8a>
break;
8002050: bf00 nop
8002052: e01a b.n 800208a <manageCiclo+0xa8a>
break;
8002054: bf00 nop
8002056: e018 b.n 800208a <manageCiclo+0xa8a>
break;
8002058: bf00 nop
800205a: e016 b.n 800208a <manageCiclo+0xa8a>
break;
800205c: bf00 nop
800205e: e014 b.n 800208a <manageCiclo+0xa8a>
break;
8002060: bf00 nop
8002062: e012 b.n 800208a <manageCiclo+0xa8a>
break;
8002064: bf00 nop
8002066: e010 b.n 800208a <manageCiclo+0xa8a>
break;
8002068: bf00 nop
800206a: e00e b.n 800208a <manageCiclo+0xa8a>
break;
800206c: bf00 nop
800206e: e00c b.n 800208a <manageCiclo+0xa8a>
break;
8002070: bf00 nop
8002072: e00a b.n 800208a <manageCiclo+0xa8a>
break;
8002074: bf00 nop
8002076: e008 b.n 800208a <manageCiclo+0xa8a>
break;
8002078: bf00 nop
800207a: e006 b.n 800208a <manageCiclo+0xa8a>
break;
800207c: bf00 nop
800207e: e004 b.n 800208a <manageCiclo+0xa8a>
break;
8002080: bf00 nop
8002082: e002 b.n 800208a <manageCiclo+0xa8a>
break;
8002084: bf00 nop
8002086: e000 b.n 800208a <manageCiclo+0xa8a>
break;
8002088: bf00 nop
}
}
800208a: bf00 nop
800208c: 46bd mov sp, r7
800208e: bd80 pop {r7, pc}
8002090: 200003ec .word 0x200003ec
8002094: 200003f4 .word 0x200003f4
8002098: 20000410 .word 0x20000410
800209c: 2000041d .word 0x2000041d
80020a0: 2000041c .word 0x2000041c
80020a4: 2000040e .word 0x2000040e
80020a8: 20000414 .word 0x20000414
80020ac: 200003fc .word 0x200003fc
80020b0: 2000040c .word 0x2000040c
80020b4: 2000041e .word 0x2000041e
080020b8 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80020b8: b580 push {r7, lr}
80020ba: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80020bc: f001 f9ba bl 8003434 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80020c0: f000 f84e bl 8002160 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80020c4: f000 fab0 bl 8002628 <MX_GPIO_Init>
MX_DMA_Init();
80020c8: f000 fa90 bl 80025ec <MX_DMA_Init>
MX_USB_DEVICE_Init();
80020cc: f009 fd24 bl 800bb18 <MX_USB_DEVICE_Init>
MX_TIM2_Init();
80020d0: f000 f91c bl 800230c <MX_TIM2_Init>
MX_TIM4_Init();
80020d4: f000 f9be bl 8002454 <MX_TIM4_Init>
MX_ADC1_Init();
80020d8: f000 f8a0 bl 800221c <MX_ADC1_Init>
MX_USART1_UART_Init();
80020dc: f000 fa5c bl 8002598 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_buf, ADC_NUM_CHANNELS);
80020e0: 2205 movs r2, #5
80020e2: 491b ldr r1, [pc, #108] @ (8002150 <main+0x98>)
80020e4: 481b ldr r0, [pc, #108] @ (8002154 <main+0x9c>)
80020e6: f001 fadf bl 80036a8 <HAL_ADC_Start_DMA>
StopMot(timMot1,FWMot1);
80020ea: 2100 movs r1, #0
80020ec: 481a ldr r0, [pc, #104] @ (8002158 <main+0xa0>)
80020ee: f000 fb60 bl 80027b2 <StopMot>
StopMot(timMot1,BWMot1);
80020f2: 2104 movs r1, #4
80020f4: 4818 ldr r0, [pc, #96] @ (8002158 <main+0xa0>)
80020f6: f000 fb5c bl 80027b2 <StopMot>
StopMot(timMot2,FWMot2);
80020fa: 2108 movs r1, #8
80020fc: 4816 ldr r0, [pc, #88] @ (8002158 <main+0xa0>)
80020fe: f000 fb58 bl 80027b2 <StopMot>
StopMot(timMot2,BWMot2);
8002102: 210c movs r1, #12
8002104: 4814 ldr r0, [pc, #80] @ (8002158 <main+0xa0>)
8002106: f000 fb54 bl 80027b2 <StopMot>
StopMot(timMot3,FWMot3);
800210a: 2100 movs r1, #0
800210c: 4813 ldr r0, [pc, #76] @ (800215c <main+0xa4>)
800210e: f000 fb50 bl 80027b2 <StopMot>
StopMot(timMot3,BWMot3);
8002112: 2104 movs r1, #4
8002114: 4811 ldr r0, [pc, #68] @ (800215c <main+0xa4>)
8002116: f000 fb4c bl 80027b2 <StopMot>
StopMot(timMot4,FWMot4);
800211a: 2108 movs r1, #8
800211c: 480f ldr r0, [pc, #60] @ (800215c <main+0xa4>)
800211e: f000 fb48 bl 80027b2 <StopMot>
StopMot(timMot4,BWMot4);
8002122: 210c movs r1, #12
8002124: 480d ldr r0, [pc, #52] @ (800215c <main+0xa4>)
8002126: f000 fb44 bl 80027b2 <StopMot>
//CDC_Transmit_FS((uint8_t*)"Start\r\n", 7);
//while (CDC_Transmit_FS((uint8_t*)"Start\r\n", 7) == USBD_BUSY);
if (EE_Init() != EE_OK){
800212a: f7fe ffcd bl 80010c8 <EE_Init>
800212e: 4603 mov r3, r0
8002130: 2b00 cmp r3, #0
8002132: d001 beq.n 8002138 <main+0x80>
for(;;);//errore eeprom
8002134: bf00 nop
8002136: e7fd b.n 8002134 <main+0x7c>
}
loadEE();
8002138: f7ff f862 bl 8001200 <loadEE>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1){
manageCDC();
800213c: f7fe f95e bl 80003fc <manageCDC>
manageAdc();
8002140: f7fe f80c bl 800015c <manageAdc>
managePulsanti();
8002144: f7ff f9ee bl 8001524 <managePulsanti>
manageCiclo();
8002148: f7ff fa5a bl 8001600 <manageCiclo>
manageCDC();
800214c: bf00 nop
800214e: e7f5 b.n 800213c <main+0x84>
8002150: 200001f4 .word 0x200001f4
8002154: 20000294 .word 0x20000294
8002158: 20000308 .word 0x20000308
800215c: 20000350 .word 0x20000350
08002160 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8002160: b580 push {r7, lr}
8002162: b094 sub sp, #80 @ 0x50
8002164: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8002166: f107 0328 add.w r3, r7, #40 @ 0x28
800216a: 2228 movs r2, #40 @ 0x28
800216c: 2100 movs r1, #0
800216e: 4618 mov r0, r3
8002170: f00a fa0e bl 800c590 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8002174: f107 0314 add.w r3, r7, #20
8002178: 2200 movs r2, #0
800217a: 601a str r2, [r3, #0]
800217c: 605a str r2, [r3, #4]
800217e: 609a str r2, [r3, #8]
8002180: 60da str r2, [r3, #12]
8002182: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8002184: 1d3b adds r3, r7, #4
8002186: 2200 movs r2, #0
8002188: 601a str r2, [r3, #0]
800218a: 605a str r2, [r3, #4]
800218c: 609a str r2, [r3, #8]
800218e: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8002190: 2301 movs r3, #1
8002192: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8002194: f44f 3380 mov.w r3, #65536 @ 0x10000
8002198: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
800219a: 2300 movs r3, #0
800219c: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800219e: 2301 movs r3, #1
80021a0: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80021a2: 2302 movs r3, #2
80021a4: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80021a6: f44f 3380 mov.w r3, #65536 @ 0x10000
80021aa: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
80021ac: f44f 1380 mov.w r3, #1048576 @ 0x100000
80021b0: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80021b2: f107 0328 add.w r3, r7, #40 @ 0x28
80021b6: 4618 mov r0, r3
80021b8: f004 f998 bl 80064ec <HAL_RCC_OscConfig>
80021bc: 4603 mov r3, r0
80021be: 2b00 cmp r3, #0
80021c0: d001 beq.n 80021c6 <SystemClock_Config+0x66>
{
Error_Handler();
80021c2: f000 fadb bl 800277c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80021c6: 230f movs r3, #15
80021c8: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80021ca: 2302 movs r3, #2
80021cc: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80021ce: 2300 movs r3, #0
80021d0: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80021d2: f44f 6380 mov.w r3, #1024 @ 0x400
80021d6: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80021d8: 2300 movs r3, #0
80021da: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80021dc: f107 0314 add.w r3, r7, #20
80021e0: 2102 movs r1, #2
80021e2: 4618 mov r0, r3
80021e4: f004 fc04 bl 80069f0 <HAL_RCC_ClockConfig>
80021e8: 4603 mov r3, r0
80021ea: 2b00 cmp r3, #0
80021ec: d001 beq.n 80021f2 <SystemClock_Config+0x92>
{
Error_Handler();
80021ee: f000 fac5 bl 800277c <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
80021f2: 2312 movs r3, #18
80021f4: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
80021f6: f44f 4300 mov.w r3, #32768 @ 0x8000
80021fa: 60fb str r3, [r7, #12]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
80021fc: 2300 movs r3, #0
80021fe: 613b str r3, [r7, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002200: 1d3b adds r3, r7, #4
8002202: 4618 mov r0, r3
8002204: f004 fd84 bl 8006d10 <HAL_RCCEx_PeriphCLKConfig>
8002208: 4603 mov r3, r0
800220a: 2b00 cmp r3, #0
800220c: d001 beq.n 8002212 <SystemClock_Config+0xb2>
{
Error_Handler();
800220e: f000 fab5 bl 800277c <Error_Handler>
}
}
8002212: bf00 nop
8002214: 3750 adds r7, #80 @ 0x50
8002216: 46bd mov sp, r7
8002218: bd80 pop {r7, pc}
...
0800221c <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
800221c: b580 push {r7, lr}
800221e: b084 sub sp, #16
8002220: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8002222: 1d3b adds r3, r7, #4
8002224: 2200 movs r2, #0
8002226: 601a str r2, [r3, #0]
8002228: 605a str r2, [r3, #4]
800222a: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
800222c: 4b35 ldr r3, [pc, #212] @ (8002304 <MX_ADC1_Init+0xe8>)
800222e: 4a36 ldr r2, [pc, #216] @ (8002308 <MX_ADC1_Init+0xec>)
8002230: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
8002232: 4b34 ldr r3, [pc, #208] @ (8002304 <MX_ADC1_Init+0xe8>)
8002234: f44f 7280 mov.w r2, #256 @ 0x100
8002238: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = ENABLE;
800223a: 4b32 ldr r3, [pc, #200] @ (8002304 <MX_ADC1_Init+0xe8>)
800223c: 2201 movs r2, #1
800223e: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8002240: 4b30 ldr r3, [pc, #192] @ (8002304 <MX_ADC1_Init+0xe8>)
8002242: 2200 movs r2, #0
8002244: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8002246: 4b2f ldr r3, [pc, #188] @ (8002304 <MX_ADC1_Init+0xe8>)
8002248: f44f 2260 mov.w r2, #917504 @ 0xe0000
800224c: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800224e: 4b2d ldr r3, [pc, #180] @ (8002304 <MX_ADC1_Init+0xe8>)
8002250: 2200 movs r2, #0
8002252: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 5;
8002254: 4b2b ldr r3, [pc, #172] @ (8002304 <MX_ADC1_Init+0xe8>)
8002256: 2205 movs r2, #5
8002258: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
800225a: 482a ldr r0, [pc, #168] @ (8002304 <MX_ADC1_Init+0xe8>)
800225c: f001 f94c bl 80034f8 <HAL_ADC_Init>
8002260: 4603 mov r3, r0
8002262: 2b00 cmp r3, #0
8002264: d001 beq.n 800226a <MX_ADC1_Init+0x4e>
{
Error_Handler();
8002266: f000 fa89 bl 800277c <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
800226a: 2304 movs r3, #4
800226c: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
800226e: 2301 movs r3, #1
8002270: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_28CYCLES_5;
8002272: 2303 movs r3, #3
8002274: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8002276: 1d3b adds r3, r7, #4
8002278: 4619 mov r1, r3
800227a: 4822 ldr r0, [pc, #136] @ (8002304 <MX_ADC1_Init+0xe8>)
800227c: f001 fb0e bl 800389c <HAL_ADC_ConfigChannel>
8002280: 4603 mov r3, r0
8002282: 2b00 cmp r3, #0
8002284: d001 beq.n 800228a <MX_ADC1_Init+0x6e>
{
Error_Handler();
8002286: f000 fa79 bl 800277c <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
800228a: 2305 movs r3, #5
800228c: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_2;
800228e: 2302 movs r3, #2
8002290: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8002292: 1d3b adds r3, r7, #4
8002294: 4619 mov r1, r3
8002296: 481b ldr r0, [pc, #108] @ (8002304 <MX_ADC1_Init+0xe8>)
8002298: f001 fb00 bl 800389c <HAL_ADC_ConfigChannel>
800229c: 4603 mov r3, r0
800229e: 2b00 cmp r3, #0
80022a0: d001 beq.n 80022a6 <MX_ADC1_Init+0x8a>
{
Error_Handler();
80022a2: f000 fa6b bl 800277c <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_6;
80022a6: 2306 movs r3, #6
80022a8: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_3;
80022aa: 2303 movs r3, #3
80022ac: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80022ae: 1d3b adds r3, r7, #4
80022b0: 4619 mov r1, r3
80022b2: 4814 ldr r0, [pc, #80] @ (8002304 <MX_ADC1_Init+0xe8>)
80022b4: f001 faf2 bl 800389c <HAL_ADC_ConfigChannel>
80022b8: 4603 mov r3, r0
80022ba: 2b00 cmp r3, #0
80022bc: d001 beq.n 80022c2 <MX_ADC1_Init+0xa6>
{
Error_Handler();
80022be: f000 fa5d bl 800277c <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_7;
80022c2: 2307 movs r3, #7
80022c4: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_4;
80022c6: 2304 movs r3, #4
80022c8: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80022ca: 1d3b adds r3, r7, #4
80022cc: 4619 mov r1, r3
80022ce: 480d ldr r0, [pc, #52] @ (8002304 <MX_ADC1_Init+0xe8>)
80022d0: f001 fae4 bl 800389c <HAL_ADC_ConfigChannel>
80022d4: 4603 mov r3, r0
80022d6: 2b00 cmp r3, #0
80022d8: d001 beq.n 80022de <MX_ADC1_Init+0xc2>
{
Error_Handler();
80022da: f000 fa4f bl 800277c <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_8;
80022de: 2308 movs r3, #8
80022e0: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_5;
80022e2: 2305 movs r3, #5
80022e4: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80022e6: 1d3b adds r3, r7, #4
80022e8: 4619 mov r1, r3
80022ea: 4806 ldr r0, [pc, #24] @ (8002304 <MX_ADC1_Init+0xe8>)
80022ec: f001 fad6 bl 800389c <HAL_ADC_ConfigChannel>
80022f0: 4603 mov r3, r0
80022f2: 2b00 cmp r3, #0
80022f4: d001 beq.n 80022fa <MX_ADC1_Init+0xde>
{
Error_Handler();
80022f6: f000 fa41 bl 800277c <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
80022fa: bf00 nop
80022fc: 3710 adds r7, #16
80022fe: 46bd mov sp, r7
8002300: bd80 pop {r7, pc}
8002302: bf00 nop
8002304: 20000294 .word 0x20000294
8002308: 40012400 .word 0x40012400
0800230c <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
800230c: b580 push {r7, lr}
800230e: b08e sub sp, #56 @ 0x38
8002310: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8002312: f107 0328 add.w r3, r7, #40 @ 0x28
8002316: 2200 movs r2, #0
8002318: 601a str r2, [r3, #0]
800231a: 605a str r2, [r3, #4]
800231c: 609a str r2, [r3, #8]
800231e: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8002320: f107 0320 add.w r3, r7, #32
8002324: 2200 movs r2, #0
8002326: 601a str r2, [r3, #0]
8002328: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
800232a: 1d3b adds r3, r7, #4
800232c: 2200 movs r2, #0
800232e: 601a str r2, [r3, #0]
8002330: 605a str r2, [r3, #4]
8002332: 609a str r2, [r3, #8]
8002334: 60da str r2, [r3, #12]
8002336: 611a str r2, [r3, #16]
8002338: 615a str r2, [r3, #20]
800233a: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
800233c: 4b44 ldr r3, [pc, #272] @ (8002450 <MX_TIM2_Init+0x144>)
800233e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8002342: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8002344: 4b42 ldr r3, [pc, #264] @ (8002450 <MX_TIM2_Init+0x144>)
8002346: 2200 movs r2, #0
8002348: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
800234a: 4b41 ldr r3, [pc, #260] @ (8002450 <MX_TIM2_Init+0x144>)
800234c: 2200 movs r2, #0
800234e: 609a str r2, [r3, #8]
htim2.Init.Period = 17999;
8002350: 4b3f ldr r3, [pc, #252] @ (8002450 <MX_TIM2_Init+0x144>)
8002352: f244 624f movw r2, #17999 @ 0x464f
8002356: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8002358: 4b3d ldr r3, [pc, #244] @ (8002450 <MX_TIM2_Init+0x144>)
800235a: 2200 movs r2, #0
800235c: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800235e: 4b3c ldr r3, [pc, #240] @ (8002450 <MX_TIM2_Init+0x144>)
8002360: 2200 movs r2, #0
8002362: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8002364: 483a ldr r0, [pc, #232] @ (8002450 <MX_TIM2_Init+0x144>)
8002366: f004 fd89 bl 8006e7c <HAL_TIM_Base_Init>
800236a: 4603 mov r3, r0
800236c: 2b00 cmp r3, #0
800236e: d001 beq.n 8002374 <MX_TIM2_Init+0x68>
{
Error_Handler();
8002370: f000 fa04 bl 800277c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8002374: f44f 5380 mov.w r3, #4096 @ 0x1000
8002378: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
800237a: f107 0328 add.w r3, r7, #40 @ 0x28
800237e: 4619 mov r1, r3
8002380: 4833 ldr r0, [pc, #204] @ (8002450 <MX_TIM2_Init+0x144>)
8002382: f004 ffeb bl 800735c <HAL_TIM_ConfigClockSource>
8002386: 4603 mov r3, r0
8002388: 2b00 cmp r3, #0
800238a: d001 beq.n 8002390 <MX_TIM2_Init+0x84>
{
Error_Handler();
800238c: f000 f9f6 bl 800277c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8002390: 482f ldr r0, [pc, #188] @ (8002450 <MX_TIM2_Init+0x144>)
8002392: f004 fdc2 bl 8006f1a <HAL_TIM_PWM_Init>
8002396: 4603 mov r3, r0
8002398: 2b00 cmp r3, #0
800239a: d001 beq.n 80023a0 <MX_TIM2_Init+0x94>
{
Error_Handler();
800239c: f000 f9ee bl 800277c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80023a0: 2300 movs r3, #0
80023a2: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80023a4: 2300 movs r3, #0
80023a6: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
80023a8: f107 0320 add.w r3, r7, #32
80023ac: 4619 mov r1, r3
80023ae: 4828 ldr r0, [pc, #160] @ (8002450 <MX_TIM2_Init+0x144>)
80023b0: f005 fb74 bl 8007a9c <HAL_TIMEx_MasterConfigSynchronization>
80023b4: 4603 mov r3, r0
80023b6: 2b00 cmp r3, #0
80023b8: d001 beq.n 80023be <MX_TIM2_Init+0xb2>
{
Error_Handler();
80023ba: f000 f9df bl 800277c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80023be: 2360 movs r3, #96 @ 0x60
80023c0: 607b str r3, [r7, #4]
sConfigOC.Pulse = 1000;
80023c2: f44f 737a mov.w r3, #1000 @ 0x3e8
80023c6: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80023c8: 2300 movs r3, #0
80023ca: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
80023cc: 2304 movs r3, #4
80023ce: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80023d0: 1d3b adds r3, r7, #4
80023d2: 2200 movs r2, #0
80023d4: 4619 mov r1, r3
80023d6: 481e ldr r0, [pc, #120] @ (8002450 <MX_TIM2_Init+0x144>)
80023d8: f004 fefe bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
80023dc: 4603 mov r3, r0
80023de: 2b00 cmp r3, #0
80023e0: d001 beq.n 80023e6 <MX_TIM2_Init+0xda>
{
Error_Handler();
80023e2: f000 f9cb bl 800277c <Error_Handler>
}
sConfigOC.Pulse = 2000;
80023e6: f44f 63fa mov.w r3, #2000 @ 0x7d0
80023ea: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80023ec: 1d3b adds r3, r7, #4
80023ee: 2204 movs r2, #4
80023f0: 4619 mov r1, r3
80023f2: 4817 ldr r0, [pc, #92] @ (8002450 <MX_TIM2_Init+0x144>)
80023f4: f004 fef0 bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
80023f8: 4603 mov r3, r0
80023fa: 2b00 cmp r3, #0
80023fc: d001 beq.n 8002402 <MX_TIM2_Init+0xf6>
{
Error_Handler();
80023fe: f000 f9bd bl 800277c <Error_Handler>
}
sConfigOC.Pulse = 3000;
8002402: f640 33b8 movw r3, #3000 @ 0xbb8
8002406: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8002408: 2300 movs r3, #0
800240a: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
800240c: 1d3b adds r3, r7, #4
800240e: 2208 movs r2, #8
8002410: 4619 mov r1, r3
8002412: 480f ldr r0, [pc, #60] @ (8002450 <MX_TIM2_Init+0x144>)
8002414: f004 fee0 bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
8002418: 4603 mov r3, r0
800241a: 2b00 cmp r3, #0
800241c: d001 beq.n 8002422 <MX_TIM2_Init+0x116>
{
Error_Handler();
800241e: f000 f9ad bl 800277c <Error_Handler>
}
sConfigOC.Pulse = 4000;
8002422: f44f 637a mov.w r3, #4000 @ 0xfa0
8002426: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8002428: 2304 movs r3, #4
800242a: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
800242c: 1d3b adds r3, r7, #4
800242e: 220c movs r2, #12
8002430: 4619 mov r1, r3
8002432: 4807 ldr r0, [pc, #28] @ (8002450 <MX_TIM2_Init+0x144>)
8002434: f004 fed0 bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
8002438: 4603 mov r3, r0
800243a: 2b00 cmp r3, #0
800243c: d001 beq.n 8002442 <MX_TIM2_Init+0x136>
{
Error_Handler();
800243e: f000 f99d bl 800277c <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8002442: 4803 ldr r0, [pc, #12] @ (8002450 <MX_TIM2_Init+0x144>)
8002444: f000 feb2 bl 80031ac <HAL_TIM_MspPostInit>
}
8002448: bf00 nop
800244a: 3738 adds r7, #56 @ 0x38
800244c: 46bd mov sp, r7
800244e: bd80 pop {r7, pc}
8002450: 20000308 .word 0x20000308
08002454 <MX_TIM4_Init>:
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
8002454: b580 push {r7, lr}
8002456: b08e sub sp, #56 @ 0x38
8002458: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800245a: f107 0328 add.w r3, r7, #40 @ 0x28
800245e: 2200 movs r2, #0
8002460: 601a str r2, [r3, #0]
8002462: 605a str r2, [r3, #4]
8002464: 609a str r2, [r3, #8]
8002466: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8002468: f107 0320 add.w r3, r7, #32
800246c: 2200 movs r2, #0
800246e: 601a str r2, [r3, #0]
8002470: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8002472: 1d3b adds r3, r7, #4
8002474: 2200 movs r2, #0
8002476: 601a str r2, [r3, #0]
8002478: 605a str r2, [r3, #4]
800247a: 609a str r2, [r3, #8]
800247c: 60da str r2, [r3, #12]
800247e: 611a str r2, [r3, #16]
8002480: 615a str r2, [r3, #20]
8002482: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
8002484: 4b42 ldr r3, [pc, #264] @ (8002590 <MX_TIM4_Init+0x13c>)
8002486: 4a43 ldr r2, [pc, #268] @ (8002594 <MX_TIM4_Init+0x140>)
8002488: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 0;
800248a: 4b41 ldr r3, [pc, #260] @ (8002590 <MX_TIM4_Init+0x13c>)
800248c: 2200 movs r2, #0
800248e: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
8002490: 4b3f ldr r3, [pc, #252] @ (8002590 <MX_TIM4_Init+0x13c>)
8002492: 2200 movs r2, #0
8002494: 609a str r2, [r3, #8]
htim4.Init.Period = 17999;
8002496: 4b3e ldr r3, [pc, #248] @ (8002590 <MX_TIM4_Init+0x13c>)
8002498: f244 624f movw r2, #17999 @ 0x464f
800249c: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800249e: 4b3c ldr r3, [pc, #240] @ (8002590 <MX_TIM4_Init+0x13c>)
80024a0: 2200 movs r2, #0
80024a2: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80024a4: 4b3a ldr r3, [pc, #232] @ (8002590 <MX_TIM4_Init+0x13c>)
80024a6: 2200 movs r2, #0
80024a8: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
80024aa: 4839 ldr r0, [pc, #228] @ (8002590 <MX_TIM4_Init+0x13c>)
80024ac: f004 fce6 bl 8006e7c <HAL_TIM_Base_Init>
80024b0: 4603 mov r3, r0
80024b2: 2b00 cmp r3, #0
80024b4: d001 beq.n 80024ba <MX_TIM4_Init+0x66>
{
Error_Handler();
80024b6: f000 f961 bl 800277c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80024ba: f44f 5380 mov.w r3, #4096 @ 0x1000
80024be: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
80024c0: f107 0328 add.w r3, r7, #40 @ 0x28
80024c4: 4619 mov r1, r3
80024c6: 4832 ldr r0, [pc, #200] @ (8002590 <MX_TIM4_Init+0x13c>)
80024c8: f004 ff48 bl 800735c <HAL_TIM_ConfigClockSource>
80024cc: 4603 mov r3, r0
80024ce: 2b00 cmp r3, #0
80024d0: d001 beq.n 80024d6 <MX_TIM4_Init+0x82>
{
Error_Handler();
80024d2: f000 f953 bl 800277c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
80024d6: 482e ldr r0, [pc, #184] @ (8002590 <MX_TIM4_Init+0x13c>)
80024d8: f004 fd1f bl 8006f1a <HAL_TIM_PWM_Init>
80024dc: 4603 mov r3, r0
80024de: 2b00 cmp r3, #0
80024e0: d001 beq.n 80024e6 <MX_TIM4_Init+0x92>
{
Error_Handler();
80024e2: f000 f94b bl 800277c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80024e6: 2300 movs r3, #0
80024e8: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80024ea: 2300 movs r3, #0
80024ec: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
80024ee: f107 0320 add.w r3, r7, #32
80024f2: 4619 mov r1, r3
80024f4: 4826 ldr r0, [pc, #152] @ (8002590 <MX_TIM4_Init+0x13c>)
80024f6: f005 fad1 bl 8007a9c <HAL_TIMEx_MasterConfigSynchronization>
80024fa: 4603 mov r3, r0
80024fc: 2b00 cmp r3, #0
80024fe: d001 beq.n 8002504 <MX_TIM4_Init+0xb0>
{
Error_Handler();
8002500: f000 f93c bl 800277c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8002504: 2360 movs r3, #96 @ 0x60
8002506: 607b str r3, [r7, #4]
sConfigOC.Pulse = 5000;
8002508: f241 3388 movw r3, #5000 @ 0x1388
800250c: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800250e: 2300 movs r3, #0
8002510: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8002512: 2304 movs r3, #4
8002514: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8002516: 1d3b adds r3, r7, #4
8002518: 2200 movs r2, #0
800251a: 4619 mov r1, r3
800251c: 481c ldr r0, [pc, #112] @ (8002590 <MX_TIM4_Init+0x13c>)
800251e: f004 fe5b bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
8002522: 4603 mov r3, r0
8002524: 2b00 cmp r3, #0
8002526: d001 beq.n 800252c <MX_TIM4_Init+0xd8>
{
Error_Handler();
8002528: f000 f928 bl 800277c <Error_Handler>
}
sConfigOC.Pulse = 6000;
800252c: f241 7370 movw r3, #6000 @ 0x1770
8002530: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8002532: 1d3b adds r3, r7, #4
8002534: 2204 movs r2, #4
8002536: 4619 mov r1, r3
8002538: 4815 ldr r0, [pc, #84] @ (8002590 <MX_TIM4_Init+0x13c>)
800253a: f004 fe4d bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
800253e: 4603 mov r3, r0
8002540: 2b00 cmp r3, #0
8002542: d001 beq.n 8002548 <MX_TIM4_Init+0xf4>
{
Error_Handler();
8002544: f000 f91a bl 800277c <Error_Handler>
}
sConfigOC.Pulse = 7000;
8002548: f641 3358 movw r3, #7000 @ 0x1b58
800254c: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
800254e: 1d3b adds r3, r7, #4
8002550: 2208 movs r2, #8
8002552: 4619 mov r1, r3
8002554: 480e ldr r0, [pc, #56] @ (8002590 <MX_TIM4_Init+0x13c>)
8002556: f004 fe3f bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
800255a: 4603 mov r3, r0
800255c: 2b00 cmp r3, #0
800255e: d001 beq.n 8002564 <MX_TIM4_Init+0x110>
{
Error_Handler();
8002560: f000 f90c bl 800277c <Error_Handler>
}
sConfigOC.Pulse = 8000;
8002564: f44f 53fa mov.w r3, #8000 @ 0x1f40
8002568: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
800256a: 1d3b adds r3, r7, #4
800256c: 220c movs r2, #12
800256e: 4619 mov r1, r3
8002570: 4807 ldr r0, [pc, #28] @ (8002590 <MX_TIM4_Init+0x13c>)
8002572: f004 fe31 bl 80071d8 <HAL_TIM_PWM_ConfigChannel>
8002576: 4603 mov r3, r0
8002578: 2b00 cmp r3, #0
800257a: d001 beq.n 8002580 <MX_TIM4_Init+0x12c>
{
Error_Handler();
800257c: f000 f8fe bl 800277c <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
8002580: 4803 ldr r0, [pc, #12] @ (8002590 <MX_TIM4_Init+0x13c>)
8002582: f000 fe13 bl 80031ac <HAL_TIM_MspPostInit>
}
8002586: bf00 nop
8002588: 3738 adds r7, #56 @ 0x38
800258a: 46bd mov sp, r7
800258c: bd80 pop {r7, pc}
800258e: bf00 nop
8002590: 20000350 .word 0x20000350
8002594: 40000800 .word 0x40000800
08002598 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8002598: b580 push {r7, lr}
800259a: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
800259c: 4b11 ldr r3, [pc, #68] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
800259e: 4a12 ldr r2, [pc, #72] @ (80025e8 <MX_USART1_UART_Init+0x50>)
80025a0: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
80025a2: 4b10 ldr r3, [pc, #64] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025a4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
80025a8: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
80025aa: 4b0e ldr r3, [pc, #56] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025ac: 2200 movs r2, #0
80025ae: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
80025b0: 4b0c ldr r3, [pc, #48] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025b2: 2200 movs r2, #0
80025b4: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
80025b6: 4b0b ldr r3, [pc, #44] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025b8: 2200 movs r2, #0
80025ba: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
80025bc: 4b09 ldr r3, [pc, #36] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025be: 220c movs r2, #12
80025c0: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80025c2: 4b08 ldr r3, [pc, #32] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025c4: 2200 movs r2, #0
80025c6: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80025c8: 4b06 ldr r3, [pc, #24] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025ca: 2200 movs r2, #0
80025cc: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
80025ce: 4805 ldr r0, [pc, #20] @ (80025e4 <MX_USART1_UART_Init+0x4c>)
80025d0: f005 fac2 bl 8007b58 <HAL_UART_Init>
80025d4: 4603 mov r3, r0
80025d6: 2b00 cmp r3, #0
80025d8: d001 beq.n 80025de <MX_USART1_UART_Init+0x46>
{
Error_Handler();
80025da: f000 f8cf bl 800277c <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80025de: bf00 nop
80025e0: bd80 pop {r7, pc}
80025e2: bf00 nop
80025e4: 20000398 .word 0x20000398
80025e8: 40013800 .word 0x40013800
080025ec <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
80025ec: b580 push {r7, lr}
80025ee: b082 sub sp, #8
80025f0: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
80025f2: 4b0c ldr r3, [pc, #48] @ (8002624 <MX_DMA_Init+0x38>)
80025f4: 695b ldr r3, [r3, #20]
80025f6: 4a0b ldr r2, [pc, #44] @ (8002624 <MX_DMA_Init+0x38>)
80025f8: f043 0301 orr.w r3, r3, #1
80025fc: 6153 str r3, [r2, #20]
80025fe: 4b09 ldr r3, [pc, #36] @ (8002624 <MX_DMA_Init+0x38>)
8002600: 695b ldr r3, [r3, #20]
8002602: f003 0301 and.w r3, r3, #1
8002606: 607b str r3, [r7, #4]
8002608: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
800260a: 2200 movs r2, #0
800260c: 2100 movs r1, #0
800260e: 200b movs r0, #11
8002610: f001 fc15 bl 8003e3e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8002614: 200b movs r0, #11
8002616: f001 fc2e bl 8003e76 <HAL_NVIC_EnableIRQ>
}
800261a: bf00 nop
800261c: 3708 adds r7, #8
800261e: 46bd mov sp, r7
8002620: bd80 pop {r7, pc}
8002622: bf00 nop
8002624: 40021000 .word 0x40021000
08002628 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8002628: b580 push {r7, lr}
800262a: b088 sub sp, #32
800262c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800262e: f107 0310 add.w r3, r7, #16
8002632: 2200 movs r2, #0
8002634: 601a str r2, [r3, #0]
8002636: 605a str r2, [r3, #4]
8002638: 609a str r2, [r3, #8]
800263a: 60da str r2, [r3, #12]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
800263c: 4b4b ldr r3, [pc, #300] @ (800276c <MX_GPIO_Init+0x144>)
800263e: 699b ldr r3, [r3, #24]
8002640: 4a4a ldr r2, [pc, #296] @ (800276c <MX_GPIO_Init+0x144>)
8002642: f043 0310 orr.w r3, r3, #16
8002646: 6193 str r3, [r2, #24]
8002648: 4b48 ldr r3, [pc, #288] @ (800276c <MX_GPIO_Init+0x144>)
800264a: 699b ldr r3, [r3, #24]
800264c: f003 0310 and.w r3, r3, #16
8002650: 60fb str r3, [r7, #12]
8002652: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8002654: 4b45 ldr r3, [pc, #276] @ (800276c <MX_GPIO_Init+0x144>)
8002656: 699b ldr r3, [r3, #24]
8002658: 4a44 ldr r2, [pc, #272] @ (800276c <MX_GPIO_Init+0x144>)
800265a: f043 0320 orr.w r3, r3, #32
800265e: 6193 str r3, [r2, #24]
8002660: 4b42 ldr r3, [pc, #264] @ (800276c <MX_GPIO_Init+0x144>)
8002662: 699b ldr r3, [r3, #24]
8002664: f003 0320 and.w r3, r3, #32
8002668: 60bb str r3, [r7, #8]
800266a: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800266c: 4b3f ldr r3, [pc, #252] @ (800276c <MX_GPIO_Init+0x144>)
800266e: 699b ldr r3, [r3, #24]
8002670: 4a3e ldr r2, [pc, #248] @ (800276c <MX_GPIO_Init+0x144>)
8002672: f043 0304 orr.w r3, r3, #4
8002676: 6193 str r3, [r2, #24]
8002678: 4b3c ldr r3, [pc, #240] @ (800276c <MX_GPIO_Init+0x144>)
800267a: 699b ldr r3, [r3, #24]
800267c: f003 0304 and.w r3, r3, #4
8002680: 607b str r3, [r7, #4]
8002682: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002684: 4b39 ldr r3, [pc, #228] @ (800276c <MX_GPIO_Init+0x144>)
8002686: 699b ldr r3, [r3, #24]
8002688: 4a38 ldr r2, [pc, #224] @ (800276c <MX_GPIO_Init+0x144>)
800268a: f043 0308 orr.w r3, r3, #8
800268e: 6193 str r3, [r2, #24]
8002690: 4b36 ldr r3, [pc, #216] @ (800276c <MX_GPIO_Init+0x144>)
8002692: 699b ldr r3, [r3, #24]
8002694: f003 0308 and.w r3, r3, #8
8002698: 603b str r3, [r7, #0]
800269a: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
800269c: 2200 movs r2, #0
800269e: f44f 5100 mov.w r1, #8192 @ 0x2000
80026a2: 4833 ldr r0, [pc, #204] @ (8002770 <MX_GPIO_Init+0x148>)
80026a4: f002 f991 bl 80049ca <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
80026a8: 2200 movs r2, #0
80026aa: f640 413e movw r1, #3134 @ 0xc3e
80026ae: 4831 ldr r0, [pc, #196] @ (8002774 <MX_GPIO_Init+0x14c>)
80026b0: f002 f98b bl 80049ca <HAL_GPIO_WritePin>
|EXP1_Pin|EXP2_Pin|EXP3_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, BUZ_Pin|LED1_Pin, GPIO_PIN_RESET);
80026b4: 2200 movs r2, #0
80026b6: f44f 4101 mov.w r1, #33024 @ 0x8100
80026ba: 482f ldr r0, [pc, #188] @ (8002778 <MX_GPIO_Init+0x150>)
80026bc: f002 f985 bl 80049ca <HAL_GPIO_WritePin>
/*Configure GPIO pin : LED2_Pin */
GPIO_InitStruct.Pin = LED2_Pin;
80026c0: f44f 5300 mov.w r3, #8192 @ 0x2000
80026c4: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80026c6: 2301 movs r3, #1
80026c8: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80026ca: 2300 movs r3, #0
80026cc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80026ce: 2302 movs r3, #2
80026d0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
80026d2: f107 0310 add.w r3, r7, #16
80026d6: 4619 mov r1, r3
80026d8: 4825 ldr r0, [pc, #148] @ (8002770 <MX_GPIO_Init+0x148>)
80026da: f001 ffdb bl 8004694 <HAL_GPIO_Init>
/*Configure GPIO pins : P1_Pin P2_Pin */
GPIO_InitStruct.Pin = P1_Pin|P2_Pin;
80026de: f44f 4340 mov.w r3, #49152 @ 0xc000
80026e2: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80026e4: 2300 movs r3, #0
80026e6: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80026e8: 2300 movs r3, #0
80026ea: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80026ec: f107 0310 add.w r3, r7, #16
80026f0: 4619 mov r1, r3
80026f2: 481f ldr r0, [pc, #124] @ (8002770 <MX_GPIO_Init+0x148>)
80026f4: f001 ffce bl 8004694 <HAL_GPIO_Init>
/*Configure GPIO pin : AIN1_Pin */
GPIO_InitStruct.Pin = AIN1_Pin;
80026f8: 2310 movs r3, #16
80026fa: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80026fc: 2303 movs r3, #3
80026fe: 617b str r3, [r7, #20]
HAL_GPIO_Init(AIN1_GPIO_Port, &GPIO_InitStruct);
8002700: f107 0310 add.w r3, r7, #16
8002704: 4619 mov r1, r3
8002706: 481c ldr r0, [pc, #112] @ (8002778 <MX_GPIO_Init+0x150>)
8002708: f001 ffc4 bl 8004694 <HAL_GPIO_Init>
/*Configure GPIO pins : INH1_Pin INH2_Pin INH3_Pin INH4_Pin
EXP1_Pin EXP2_Pin EXP3_Pin */
GPIO_InitStruct.Pin = INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
800270c: f640 433e movw r3, #3134 @ 0xc3e
8002710: 613b str r3, [r7, #16]
|EXP1_Pin|EXP2_Pin|EXP3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8002712: 2301 movs r3, #1
8002714: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002716: 2300 movs r3, #0
8002718: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800271a: 2302 movs r3, #2
800271c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800271e: f107 0310 add.w r3, r7, #16
8002722: 4619 mov r1, r3
8002724: 4813 ldr r0, [pc, #76] @ (8002774 <MX_GPIO_Init+0x14c>)
8002726: f001 ffb5 bl 8004694 <HAL_GPIO_Init>
/*Configure GPIO pins : CH1_Pin CH2_Pin CH3_Pin CH4_Pin */
GPIO_InitStruct.Pin = CH1_Pin|CH2_Pin|CH3_Pin|CH4_Pin;
800272a: f44f 4370 mov.w r3, #61440 @ 0xf000
800272e: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8002730: 2300 movs r3, #0
8002732: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002734: 2300 movs r3, #0
8002736: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002738: f107 0310 add.w r3, r7, #16
800273c: 4619 mov r1, r3
800273e: 480d ldr r0, [pc, #52] @ (8002774 <MX_GPIO_Init+0x14c>)
8002740: f001 ffa8 bl 8004694 <HAL_GPIO_Init>
/*Configure GPIO pins : BUZ_Pin LED1_Pin */
GPIO_InitStruct.Pin = BUZ_Pin|LED1_Pin;
8002744: f44f 4301 mov.w r3, #33024 @ 0x8100
8002748: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800274a: 2301 movs r3, #1
800274c: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800274e: 2300 movs r3, #0
8002750: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002752: 2302 movs r3, #2
8002754: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8002756: f107 0310 add.w r3, r7, #16
800275a: 4619 mov r1, r3
800275c: 4806 ldr r0, [pc, #24] @ (8002778 <MX_GPIO_Init+0x150>)
800275e: f001 ff99 bl 8004694 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8002762: bf00 nop
8002764: 3720 adds r7, #32
8002766: 46bd mov sp, r7
8002768: bd80 pop {r7, pc}
800276a: bf00 nop
800276c: 40021000 .word 0x40021000
8002770: 40011000 .word 0x40011000
8002774: 40010c00 .word 0x40010c00
8002778: 40010800 .word 0x40010800
0800277c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800277c: b480 push {r7}
800277e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8002780: b672 cpsid i
}
8002782: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8002784: bf00 nop
8002786: e7fd b.n 8002784 <Error_Handler+0x8>
08002788 <IsPwmRunning>:
extern TIM_HandleTypeDef htim3;
extern TIM_HandleTypeDef htim4;
extern volatile uint8_t rtramp[4];
extern uint8_t mrampstart[4];
bool IsPwmRunning(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8002788: b580 push {r7, lr}
800278a: b084 sub sp, #16
800278c: af00 add r7, sp, #0
800278e: 6078 str r0, [r7, #4]
8002790: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef chState = HAL_TIM_GetChannelState(htim, Channel);
8002792: 6839 ldr r1, [r7, #0]
8002794: 6878 ldr r0, [r7, #4]
8002796: f004 fea8 bl 80074ea <HAL_TIM_GetChannelState>
800279a: 4603 mov r3, r0
800279c: 73fb strb r3, [r7, #15]
return (chState == HAL_TIM_CHANNEL_STATE_BUSY);
800279e: 7bfb ldrb r3, [r7, #15]
80027a0: 2b02 cmp r3, #2
80027a2: bf0c ite eq
80027a4: 2301 moveq r3, #1
80027a6: 2300 movne r3, #0
80027a8: b2db uxtb r3, r3
}
80027aa: 4618 mov r0, r3
80027ac: 3710 adds r7, #16
80027ae: 46bd mov sp, r7
80027b0: bd80 pop {r7, pc}
080027b2 <StopMot>:
void StopMot(TIM_HandleTypeDef *htim,uint32_t Channel){
80027b2: b580 push {r7, lr}
80027b4: b082 sub sp, #8
80027b6: af00 add r7, sp, #0
80027b8: 6078 str r0, [r7, #4]
80027ba: 6039 str r1, [r7, #0]
HAL_TIM_PWM_Stop(htim, Channel);
80027bc: 6839 ldr r1, [r7, #0]
80027be: 6878 ldr r0, [r7, #4]
80027c0: f004 fca6 bl 8007110 <HAL_TIM_PWM_Stop>
}
80027c4: bf00 nop
80027c6: 3708 adds r7, #8
80027c8: 46bd mov sp, r7
80027ca: bd80 pop {r7, pc}
080027cc <StartMot>:
void StartMot(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
80027cc: b580 push {r7, lr}
80027ce: b084 sub sp, #16
80027d0: af00 add r7, sp, #0
80027d2: 60f8 str r0, [r7, #12]
80027d4: 60b9 str r1, [r7, #8]
80027d6: 4613 mov r3, r2
80027d8: 80fb strh r3, [r7, #6]
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
80027da: 68bb ldr r3, [r7, #8]
80027dc: 2b00 cmp r3, #0
80027de: d104 bne.n 80027ea <StartMot+0x1e>
80027e0: 68fb ldr r3, [r7, #12]
80027e2: 681b ldr r3, [r3, #0]
80027e4: 88fa ldrh r2, [r7, #6]
80027e6: 635a str r2, [r3, #52] @ 0x34
80027e8: e013 b.n 8002812 <StartMot+0x46>
80027ea: 68bb ldr r3, [r7, #8]
80027ec: 2b04 cmp r3, #4
80027ee: d104 bne.n 80027fa <StartMot+0x2e>
80027f0: 68fb ldr r3, [r7, #12]
80027f2: 681a ldr r2, [r3, #0]
80027f4: 88fb ldrh r3, [r7, #6]
80027f6: 6393 str r3, [r2, #56] @ 0x38
80027f8: e00b b.n 8002812 <StartMot+0x46>
80027fa: 68bb ldr r3, [r7, #8]
80027fc: 2b08 cmp r3, #8
80027fe: d104 bne.n 800280a <StartMot+0x3e>
8002800: 68fb ldr r3, [r7, #12]
8002802: 681a ldr r2, [r3, #0]
8002804: 88fb ldrh r3, [r7, #6]
8002806: 63d3 str r3, [r2, #60] @ 0x3c
8002808: e003 b.n 8002812 <StartMot+0x46>
800280a: 68fb ldr r3, [r7, #12]
800280c: 681a ldr r2, [r3, #0]
800280e: 88fb ldrh r3, [r7, #6]
8002810: 6413 str r3, [r2, #64] @ 0x40
HAL_TIM_PWM_Start(htim, Channel);
8002812: 68b9 ldr r1, [r7, #8]
8002814: 68f8 ldr r0, [r7, #12]
8002816: f004 fbd9 bl 8006fcc <HAL_TIM_PWM_Start>
}
800281a: bf00 nop
800281c: 3710 adds r7, #16
800281e: 46bd mov sp, r7
8002820: bd80 pop {r7, pc}
08002822 <SetMotPwm>:
void SetMotPwm(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
8002822: b480 push {r7}
8002824: b085 sub sp, #20
8002826: af00 add r7, sp, #0
8002828: 60f8 str r0, [r7, #12]
800282a: 60b9 str r1, [r7, #8]
800282c: 4613 mov r3, r2
800282e: 80fb strh r3, [r7, #6]
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8002830: 68bb ldr r3, [r7, #8]
8002832: 2b00 cmp r3, #0
8002834: d104 bne.n 8002840 <SetMotPwm+0x1e>
8002836: 68fb ldr r3, [r7, #12]
8002838: 681b ldr r3, [r3, #0]
800283a: 88fa ldrh r2, [r7, #6]
800283c: 635a str r2, [r3, #52] @ 0x34
}
800283e: e013 b.n 8002868 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8002840: 68bb ldr r3, [r7, #8]
8002842: 2b04 cmp r3, #4
8002844: d104 bne.n 8002850 <SetMotPwm+0x2e>
8002846: 68fb ldr r3, [r7, #12]
8002848: 681a ldr r2, [r3, #0]
800284a: 88fb ldrh r3, [r7, #6]
800284c: 6393 str r3, [r2, #56] @ 0x38
}
800284e: e00b b.n 8002868 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8002850: 68bb ldr r3, [r7, #8]
8002852: 2b08 cmp r3, #8
8002854: d104 bne.n 8002860 <SetMotPwm+0x3e>
8002856: 68fb ldr r3, [r7, #12]
8002858: 681a ldr r2, [r3, #0]
800285a: 88fb ldrh r3, [r7, #6]
800285c: 63d3 str r3, [r2, #60] @ 0x3c
}
800285e: e003 b.n 8002868 <SetMotPwm+0x46>
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
8002860: 68fb ldr r3, [r7, #12]
8002862: 681a ldr r2, [r3, #0]
8002864: 88fb ldrh r3, [r7, #6]
8002866: 6413 str r3, [r2, #64] @ 0x40
}
8002868: bf00 nop
800286a: 3714 adds r7, #20
800286c: 46bd mov sp, r7
800286e: bc80 pop {r7}
8002870: 4770 bx lr
...
08002874 <SetMot>:
void SetMot(uint8_t mot,uint8_t dir,uint16_t pwmval){
8002874: b580 push {r7, lr}
8002876: b082 sub sp, #8
8002878: af00 add r7, sp, #0
800287a: 4603 mov r3, r0
800287c: 71fb strb r3, [r7, #7]
800287e: 460b mov r3, r1
8002880: 71bb strb r3, [r7, #6]
8002882: 4613 mov r3, r2
8002884: 80bb strh r3, [r7, #4]
switch(mot){
8002886: 79fb ldrb r3, [r7, #7]
8002888: 3b01 subs r3, #1
800288a: 2b03 cmp r3, #3
800288c: f200 8158 bhi.w 8002b40 <SetMot+0x2cc>
8002890: a201 add r2, pc, #4 @ (adr r2, 8002898 <SetMot+0x24>)
8002892: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002896: bf00 nop
8002898: 080028a9 .word 0x080028a9
800289c: 0800294b .word 0x0800294b
80028a0: 080029ed .word 0x080029ed
80028a4: 08002a97 .word 0x08002a97
case 1:
if(dir==FW){
80028a8: 79bb ldrb r3, [r7, #6]
80028aa: 2b00 cmp r3, #0
80028ac: d126 bne.n 80028fc <SetMot+0x88>
if(pwmval==0){
80028ae: 88bb ldrh r3, [r7, #4]
80028b0: 2b00 cmp r3, #0
80028b2: d109 bne.n 80028c8 <SetMot+0x54>
StopMot(timMot1,FWMot1);
80028b4: 2100 movs r1, #0
80028b6: 48a5 ldr r0, [pc, #660] @ (8002b4c <SetMot+0x2d8>)
80028b8: f7ff ff7b bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
80028bc: 2200 movs r2, #0
80028be: 2102 movs r1, #2
80028c0: 48a3 ldr r0, [pc, #652] @ (8002b50 <SetMot+0x2dc>)
80028c2: f002 f882 bl 80049ca <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
StartMot(timMot1,BWMot1,pwmval);
}
}
break;
80028c6: e13c b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot1, FWMot1)){
80028c8: 2100 movs r1, #0
80028ca: 48a0 ldr r0, [pc, #640] @ (8002b4c <SetMot+0x2d8>)
80028cc: f7ff ff5c bl 8002788 <IsPwmRunning>
80028d0: 4603 mov r3, r0
80028d2: 2b00 cmp r3, #0
80028d4: d006 beq.n 80028e4 <SetMot+0x70>
SetMotPwm(timMot1,FWMot1,pwmval);
80028d6: 88bb ldrh r3, [r7, #4]
80028d8: 461a mov r2, r3
80028da: 2100 movs r1, #0
80028dc: 489b ldr r0, [pc, #620] @ (8002b4c <SetMot+0x2d8>)
80028de: f7ff ffa0 bl 8002822 <SetMotPwm>
break;
80028e2: e12e b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
80028e4: 2201 movs r2, #1
80028e6: 2102 movs r1, #2
80028e8: 4899 ldr r0, [pc, #612] @ (8002b50 <SetMot+0x2dc>)
80028ea: f002 f86e bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot1,FWMot1,pwmval);
80028ee: 88bb ldrh r3, [r7, #4]
80028f0: 461a mov r2, r3
80028f2: 2100 movs r1, #0
80028f4: 4895 ldr r0, [pc, #596] @ (8002b4c <SetMot+0x2d8>)
80028f6: f7ff ff69 bl 80027cc <StartMot>
break;
80028fa: e122 b.n 8002b42 <SetMot+0x2ce>
if(pwmval==0){
80028fc: 88bb ldrh r3, [r7, #4]
80028fe: 2b00 cmp r3, #0
8002900: d109 bne.n 8002916 <SetMot+0xa2>
StopMot(timMot1,BWMot1);
8002902: 2104 movs r1, #4
8002904: 4891 ldr r0, [pc, #580] @ (8002b4c <SetMot+0x2d8>)
8002906: f7ff ff54 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
800290a: 2200 movs r2, #0
800290c: 2102 movs r1, #2
800290e: 4890 ldr r0, [pc, #576] @ (8002b50 <SetMot+0x2dc>)
8002910: f002 f85b bl 80049ca <HAL_GPIO_WritePin>
break;
8002914: e115 b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot1, BWMot1)){
8002916: 2104 movs r1, #4
8002918: 488c ldr r0, [pc, #560] @ (8002b4c <SetMot+0x2d8>)
800291a: f7ff ff35 bl 8002788 <IsPwmRunning>
800291e: 4603 mov r3, r0
8002920: 2b00 cmp r3, #0
8002922: d006 beq.n 8002932 <SetMot+0xbe>
SetMotPwm(timMot1,BWMot1,pwmval);
8002924: 88bb ldrh r3, [r7, #4]
8002926: 461a mov r2, r3
8002928: 2104 movs r1, #4
800292a: 4888 ldr r0, [pc, #544] @ (8002b4c <SetMot+0x2d8>)
800292c: f7ff ff79 bl 8002822 <SetMotPwm>
break;
8002930: e107 b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8002932: 2201 movs r2, #1
8002934: 2102 movs r1, #2
8002936: 4886 ldr r0, [pc, #536] @ (8002b50 <SetMot+0x2dc>)
8002938: f002 f847 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot1,BWMot1,pwmval);
800293c: 88bb ldrh r3, [r7, #4]
800293e: 461a mov r2, r3
8002940: 2104 movs r1, #4
8002942: 4882 ldr r0, [pc, #520] @ (8002b4c <SetMot+0x2d8>)
8002944: f7ff ff42 bl 80027cc <StartMot>
break;
8002948: e0fb b.n 8002b42 <SetMot+0x2ce>
case 2:
if(dir==FW){
800294a: 79bb ldrb r3, [r7, #6]
800294c: 2b00 cmp r3, #0
800294e: d126 bne.n 800299e <SetMot+0x12a>
if(pwmval==0){
8002950: 88bb ldrh r3, [r7, #4]
8002952: 2b00 cmp r3, #0
8002954: d109 bne.n 800296a <SetMot+0xf6>
StopMot(timMot2,FWMot2);
8002956: 2108 movs r1, #8
8002958: 487c ldr r0, [pc, #496] @ (8002b4c <SetMot+0x2d8>)
800295a: f7ff ff2a bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
800295e: 2200 movs r2, #0
8002960: 2104 movs r1, #4
8002962: 487b ldr r0, [pc, #492] @ (8002b50 <SetMot+0x2dc>)
8002964: f002 f831 bl 80049ca <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
StartMot(timMot2,BWMot2,pwmval);
}
}
break;
8002968: e0eb b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot2, FWMot2)){
800296a: 2108 movs r1, #8
800296c: 4877 ldr r0, [pc, #476] @ (8002b4c <SetMot+0x2d8>)
800296e: f7ff ff0b bl 8002788 <IsPwmRunning>
8002972: 4603 mov r3, r0
8002974: 2b00 cmp r3, #0
8002976: d006 beq.n 8002986 <SetMot+0x112>
SetMotPwm(timMot2,FWMot2,pwmval);
8002978: 88bb ldrh r3, [r7, #4]
800297a: 461a mov r2, r3
800297c: 2108 movs r1, #8
800297e: 4873 ldr r0, [pc, #460] @ (8002b4c <SetMot+0x2d8>)
8002980: f7ff ff4f bl 8002822 <SetMotPwm>
break;
8002984: e0dd b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8002986: 2201 movs r2, #1
8002988: 2104 movs r1, #4
800298a: 4871 ldr r0, [pc, #452] @ (8002b50 <SetMot+0x2dc>)
800298c: f002 f81d bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot2,FWMot2,pwmval);
8002990: 88bb ldrh r3, [r7, #4]
8002992: 461a mov r2, r3
8002994: 2108 movs r1, #8
8002996: 486d ldr r0, [pc, #436] @ (8002b4c <SetMot+0x2d8>)
8002998: f7ff ff18 bl 80027cc <StartMot>
break;
800299c: e0d1 b.n 8002b42 <SetMot+0x2ce>
if(pwmval==0){
800299e: 88bb ldrh r3, [r7, #4]
80029a0: 2b00 cmp r3, #0
80029a2: d109 bne.n 80029b8 <SetMot+0x144>
StopMot(timMot2,BWMot2);
80029a4: 210c movs r1, #12
80029a6: 4869 ldr r0, [pc, #420] @ (8002b4c <SetMot+0x2d8>)
80029a8: f7ff ff03 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
80029ac: 2200 movs r2, #0
80029ae: 2104 movs r1, #4
80029b0: 4867 ldr r0, [pc, #412] @ (8002b50 <SetMot+0x2dc>)
80029b2: f002 f80a bl 80049ca <HAL_GPIO_WritePin>
break;
80029b6: e0c4 b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot2, BWMot2)){
80029b8: 210c movs r1, #12
80029ba: 4864 ldr r0, [pc, #400] @ (8002b4c <SetMot+0x2d8>)
80029bc: f7ff fee4 bl 8002788 <IsPwmRunning>
80029c0: 4603 mov r3, r0
80029c2: 2b00 cmp r3, #0
80029c4: d006 beq.n 80029d4 <SetMot+0x160>
SetMotPwm(timMot2,BWMot2,pwmval);
80029c6: 88bb ldrh r3, [r7, #4]
80029c8: 461a mov r2, r3
80029ca: 210c movs r1, #12
80029cc: 485f ldr r0, [pc, #380] @ (8002b4c <SetMot+0x2d8>)
80029ce: f7ff ff28 bl 8002822 <SetMotPwm>
break;
80029d2: e0b6 b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
80029d4: 2201 movs r2, #1
80029d6: 2104 movs r1, #4
80029d8: 485d ldr r0, [pc, #372] @ (8002b50 <SetMot+0x2dc>)
80029da: f001 fff6 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot2,BWMot2,pwmval);
80029de: 88bb ldrh r3, [r7, #4]
80029e0: 461a mov r2, r3
80029e2: 210c movs r1, #12
80029e4: 4859 ldr r0, [pc, #356] @ (8002b4c <SetMot+0x2d8>)
80029e6: f7ff fef1 bl 80027cc <StartMot>
break;
80029ea: e0aa b.n 8002b42 <SetMot+0x2ce>
case 3:
if(dir==FW){
80029ec: 79bb ldrb r3, [r7, #6]
80029ee: 2b00 cmp r3, #0
80029f0: d128 bne.n 8002a44 <SetMot+0x1d0>
if(pwmval==0){
80029f2: 88bb ldrh r3, [r7, #4]
80029f4: 2b00 cmp r3, #0
80029f6: d10a bne.n 8002a0e <SetMot+0x19a>
StopMot(timMot3,FWMot3);
80029f8: 2100 movs r1, #0
80029fa: 4856 ldr r0, [pc, #344] @ (8002b54 <SetMot+0x2e0>)
80029fc: f7ff fed9 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8002a00: 2200 movs r2, #0
8002a02: f44f 6180 mov.w r1, #1024 @ 0x400
8002a06: 4852 ldr r0, [pc, #328] @ (8002b50 <SetMot+0x2dc>)
8002a08: f001 ffdf bl 80049ca <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
StartMot(timMot3,BWMot3,pwmval);
}
}
break;
8002a0c: e099 b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot3, FWMot3)){
8002a0e: 2100 movs r1, #0
8002a10: 4850 ldr r0, [pc, #320] @ (8002b54 <SetMot+0x2e0>)
8002a12: f7ff feb9 bl 8002788 <IsPwmRunning>
8002a16: 4603 mov r3, r0
8002a18: 2b00 cmp r3, #0
8002a1a: d006 beq.n 8002a2a <SetMot+0x1b6>
SetMotPwm(timMot3,FWMot3,pwmval);
8002a1c: 88bb ldrh r3, [r7, #4]
8002a1e: 461a mov r2, r3
8002a20: 2100 movs r1, #0
8002a22: 484c ldr r0, [pc, #304] @ (8002b54 <SetMot+0x2e0>)
8002a24: f7ff fefd bl 8002822 <SetMotPwm>
break;
8002a28: e08b b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8002a2a: 2201 movs r2, #1
8002a2c: f44f 6180 mov.w r1, #1024 @ 0x400
8002a30: 4847 ldr r0, [pc, #284] @ (8002b50 <SetMot+0x2dc>)
8002a32: f001 ffca bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot3,FWMot3,pwmval);
8002a36: 88bb ldrh r3, [r7, #4]
8002a38: 461a mov r2, r3
8002a3a: 2100 movs r1, #0
8002a3c: 4845 ldr r0, [pc, #276] @ (8002b54 <SetMot+0x2e0>)
8002a3e: f7ff fec5 bl 80027cc <StartMot>
break;
8002a42: e07e b.n 8002b42 <SetMot+0x2ce>
if(pwmval==0){
8002a44: 88bb ldrh r3, [r7, #4]
8002a46: 2b00 cmp r3, #0
8002a48: d10a bne.n 8002a60 <SetMot+0x1ec>
StopMot(timMot3,BWMot3);
8002a4a: 2104 movs r1, #4
8002a4c: 4841 ldr r0, [pc, #260] @ (8002b54 <SetMot+0x2e0>)
8002a4e: f7ff feb0 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8002a52: 2200 movs r2, #0
8002a54: f44f 6180 mov.w r1, #1024 @ 0x400
8002a58: 483d ldr r0, [pc, #244] @ (8002b50 <SetMot+0x2dc>)
8002a5a: f001 ffb6 bl 80049ca <HAL_GPIO_WritePin>
break;
8002a5e: e070 b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot3, BWMot3)){
8002a60: 2104 movs r1, #4
8002a62: 483c ldr r0, [pc, #240] @ (8002b54 <SetMot+0x2e0>)
8002a64: f7ff fe90 bl 8002788 <IsPwmRunning>
8002a68: 4603 mov r3, r0
8002a6a: 2b00 cmp r3, #0
8002a6c: d006 beq.n 8002a7c <SetMot+0x208>
SetMotPwm(timMot3,BWMot3,pwmval);
8002a6e: 88bb ldrh r3, [r7, #4]
8002a70: 461a mov r2, r3
8002a72: 2104 movs r1, #4
8002a74: 4837 ldr r0, [pc, #220] @ (8002b54 <SetMot+0x2e0>)
8002a76: f7ff fed4 bl 8002822 <SetMotPwm>
break;
8002a7a: e062 b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8002a7c: 2201 movs r2, #1
8002a7e: f44f 6180 mov.w r1, #1024 @ 0x400
8002a82: 4833 ldr r0, [pc, #204] @ (8002b50 <SetMot+0x2dc>)
8002a84: f001 ffa1 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot3,BWMot3,pwmval);
8002a88: 88bb ldrh r3, [r7, #4]
8002a8a: 461a mov r2, r3
8002a8c: 2104 movs r1, #4
8002a8e: 4831 ldr r0, [pc, #196] @ (8002b54 <SetMot+0x2e0>)
8002a90: f7ff fe9c bl 80027cc <StartMot>
break;
8002a94: e055 b.n 8002b42 <SetMot+0x2ce>
case 4:
if(dir==FW){
8002a96: 79bb ldrb r3, [r7, #6]
8002a98: 2b00 cmp r3, #0
8002a9a: d128 bne.n 8002aee <SetMot+0x27a>
if(pwmval==0){
8002a9c: 88bb ldrh r3, [r7, #4]
8002a9e: 2b00 cmp r3, #0
8002aa0: d10a bne.n 8002ab8 <SetMot+0x244>
StopMot(timMot4,FWMot4);
8002aa2: 2108 movs r1, #8
8002aa4: 482b ldr r0, [pc, #172] @ (8002b54 <SetMot+0x2e0>)
8002aa6: f7ff fe84 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8002aaa: 2200 movs r2, #0
8002aac: f44f 6100 mov.w r1, #2048 @ 0x800
8002ab0: 4827 ldr r0, [pc, #156] @ (8002b50 <SetMot+0x2dc>)
8002ab2: f001 ff8a bl 80049ca <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
StartMot(timMot4,BWMot4,pwmval);
}
}
break;
8002ab6: e044 b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot4, FWMot4)){
8002ab8: 2108 movs r1, #8
8002aba: 4826 ldr r0, [pc, #152] @ (8002b54 <SetMot+0x2e0>)
8002abc: f7ff fe64 bl 8002788 <IsPwmRunning>
8002ac0: 4603 mov r3, r0
8002ac2: 2b00 cmp r3, #0
8002ac4: d006 beq.n 8002ad4 <SetMot+0x260>
SetMotPwm(timMot4,FWMot4,pwmval);
8002ac6: 88bb ldrh r3, [r7, #4]
8002ac8: 461a mov r2, r3
8002aca: 2108 movs r1, #8
8002acc: 4821 ldr r0, [pc, #132] @ (8002b54 <SetMot+0x2e0>)
8002ace: f7ff fea8 bl 8002822 <SetMotPwm>
break;
8002ad2: e036 b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8002ad4: 2201 movs r2, #1
8002ad6: f44f 6100 mov.w r1, #2048 @ 0x800
8002ada: 481d ldr r0, [pc, #116] @ (8002b50 <SetMot+0x2dc>)
8002adc: f001 ff75 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot4,FWMot4,pwmval);
8002ae0: 88bb ldrh r3, [r7, #4]
8002ae2: 461a mov r2, r3
8002ae4: 2108 movs r1, #8
8002ae6: 481b ldr r0, [pc, #108] @ (8002b54 <SetMot+0x2e0>)
8002ae8: f7ff fe70 bl 80027cc <StartMot>
break;
8002aec: e029 b.n 8002b42 <SetMot+0x2ce>
if(pwmval==0){
8002aee: 88bb ldrh r3, [r7, #4]
8002af0: 2b00 cmp r3, #0
8002af2: d10a bne.n 8002b0a <SetMot+0x296>
StopMot(timMot4,BWMot4);
8002af4: 210c movs r1, #12
8002af6: 4817 ldr r0, [pc, #92] @ (8002b54 <SetMot+0x2e0>)
8002af8: f7ff fe5b bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8002afc: 2200 movs r2, #0
8002afe: f44f 6100 mov.w r1, #2048 @ 0x800
8002b02: 4813 ldr r0, [pc, #76] @ (8002b50 <SetMot+0x2dc>)
8002b04: f001 ff61 bl 80049ca <HAL_GPIO_WritePin>
break;
8002b08: e01b b.n 8002b42 <SetMot+0x2ce>
}else if(IsPwmRunning(timMot4, BWMot4)){
8002b0a: 210c movs r1, #12
8002b0c: 4811 ldr r0, [pc, #68] @ (8002b54 <SetMot+0x2e0>)
8002b0e: f7ff fe3b bl 8002788 <IsPwmRunning>
8002b12: 4603 mov r3, r0
8002b14: 2b00 cmp r3, #0
8002b16: d006 beq.n 8002b26 <SetMot+0x2b2>
SetMotPwm(timMot4,BWMot4,pwmval);
8002b18: 88bb ldrh r3, [r7, #4]
8002b1a: 461a mov r2, r3
8002b1c: 210c movs r1, #12
8002b1e: 480d ldr r0, [pc, #52] @ (8002b54 <SetMot+0x2e0>)
8002b20: f7ff fe7f bl 8002822 <SetMotPwm>
break;
8002b24: e00d b.n 8002b42 <SetMot+0x2ce>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8002b26: 2201 movs r2, #1
8002b28: f44f 6100 mov.w r1, #2048 @ 0x800
8002b2c: 4808 ldr r0, [pc, #32] @ (8002b50 <SetMot+0x2dc>)
8002b2e: f001 ff4c bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot4,BWMot4,pwmval);
8002b32: 88bb ldrh r3, [r7, #4]
8002b34: 461a mov r2, r3
8002b36: 210c movs r1, #12
8002b38: 4806 ldr r0, [pc, #24] @ (8002b54 <SetMot+0x2e0>)
8002b3a: f7ff fe47 bl 80027cc <StartMot>
break;
8002b3e: e000 b.n 8002b42 <SetMot+0x2ce>
default:
break;
8002b40: bf00 nop
}
}
8002b42: bf00 nop
8002b44: 3708 adds r7, #8
8002b46: 46bd mov sp, r7
8002b48: bd80 pop {r7, pc}
8002b4a: bf00 nop
8002b4c: 20000308 .word 0x20000308
8002b50: 40010c00 .word 0x40010c00
8002b54: 20000350 .word 0x20000350
08002b58 <SetMotPerc>:
void SetMotPerc(uint8_t mot,uint8_t dir,uint8_t perc){
8002b58: b580 push {r7, lr}
8002b5a: b084 sub sp, #16
8002b5c: af00 add r7, sp, #0
8002b5e: 4603 mov r3, r0
8002b60: 71fb strb r3, [r7, #7]
8002b62: 460b mov r3, r1
8002b64: 71bb strb r3, [r7, #6]
8002b66: 4613 mov r3, r2
8002b68: 717b strb r3, [r7, #5]
uint16_t pwmval;
uint32_t tempval;
tempval=perc;
8002b6a: 797b ldrb r3, [r7, #5]
8002b6c: 60fb str r3, [r7, #12]
tempval*=16384;
8002b6e: 68fb ldr r3, [r7, #12]
8002b70: 039b lsls r3, r3, #14
8002b72: 60fb str r3, [r7, #12]
tempval/=100;
8002b74: 68fb ldr r3, [r7, #12]
8002b76: 4ab4 ldr r2, [pc, #720] @ (8002e48 <SetMotPerc+0x2f0>)
8002b78: fba2 2303 umull r2, r3, r2, r3
8002b7c: 095b lsrs r3, r3, #5
8002b7e: 60fb str r3, [r7, #12]
pwmval=(uint16_t)tempval;
8002b80: 68fb ldr r3, [r7, #12]
8002b82: 817b strh r3, [r7, #10]
switch(mot){
8002b84: 79fb ldrb r3, [r7, #7]
8002b86: 3b01 subs r3, #1
8002b88: 2b03 cmp r3, #3
8002b8a: f200 8157 bhi.w 8002e3c <SetMotPerc+0x2e4>
8002b8e: a201 add r2, pc, #4 @ (adr r2, 8002b94 <SetMotPerc+0x3c>)
8002b90: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002b94: 08002ba5 .word 0x08002ba5
8002b98: 08002c47 .word 0x08002c47
8002b9c: 08002ce9 .word 0x08002ce9
8002ba0: 08002d93 .word 0x08002d93
case 1:
if(dir==FW){
8002ba4: 79bb ldrb r3, [r7, #6]
8002ba6: 2b00 cmp r3, #0
8002ba8: d126 bne.n 8002bf8 <SetMotPerc+0xa0>
if(pwmval==0){
8002baa: 897b ldrh r3, [r7, #10]
8002bac: 2b00 cmp r3, #0
8002bae: d109 bne.n 8002bc4 <SetMotPerc+0x6c>
StopMot(timMot1,FWMot1);
8002bb0: 2100 movs r1, #0
8002bb2: 48a6 ldr r0, [pc, #664] @ (8002e4c <SetMotPerc+0x2f4>)
8002bb4: f7ff fdfd bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
8002bb8: 2200 movs r2, #0
8002bba: 2102 movs r1, #2
8002bbc: 48a4 ldr r0, [pc, #656] @ (8002e50 <SetMotPerc+0x2f8>)
8002bbe: f001 ff04 bl 80049ca <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
StartMot(timMot1,BWMot1,pwmval);
}
}
break;
8002bc2: e13c b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot1, FWMot1)){
8002bc4: 2100 movs r1, #0
8002bc6: 48a1 ldr r0, [pc, #644] @ (8002e4c <SetMotPerc+0x2f4>)
8002bc8: f7ff fdde bl 8002788 <IsPwmRunning>
8002bcc: 4603 mov r3, r0
8002bce: 2b00 cmp r3, #0
8002bd0: d006 beq.n 8002be0 <SetMotPerc+0x88>
SetMotPwm(timMot1,FWMot1,pwmval);
8002bd2: 897b ldrh r3, [r7, #10]
8002bd4: 461a mov r2, r3
8002bd6: 2100 movs r1, #0
8002bd8: 489c ldr r0, [pc, #624] @ (8002e4c <SetMotPerc+0x2f4>)
8002bda: f7ff fe22 bl 8002822 <SetMotPwm>
break;
8002bde: e12e b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8002be0: 2201 movs r2, #1
8002be2: 2102 movs r1, #2
8002be4: 489a ldr r0, [pc, #616] @ (8002e50 <SetMotPerc+0x2f8>)
8002be6: f001 fef0 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot1,FWMot1,pwmval);
8002bea: 897b ldrh r3, [r7, #10]
8002bec: 461a mov r2, r3
8002bee: 2100 movs r1, #0
8002bf0: 4896 ldr r0, [pc, #600] @ (8002e4c <SetMotPerc+0x2f4>)
8002bf2: f7ff fdeb bl 80027cc <StartMot>
break;
8002bf6: e122 b.n 8002e3e <SetMotPerc+0x2e6>
if(pwmval==0){
8002bf8: 897b ldrh r3, [r7, #10]
8002bfa: 2b00 cmp r3, #0
8002bfc: d109 bne.n 8002c12 <SetMotPerc+0xba>
StopMot(timMot1,BWMot1);
8002bfe: 2104 movs r1, #4
8002c00: 4892 ldr r0, [pc, #584] @ (8002e4c <SetMotPerc+0x2f4>)
8002c02: f7ff fdd6 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
8002c06: 2200 movs r2, #0
8002c08: 2102 movs r1, #2
8002c0a: 4891 ldr r0, [pc, #580] @ (8002e50 <SetMotPerc+0x2f8>)
8002c0c: f001 fedd bl 80049ca <HAL_GPIO_WritePin>
break;
8002c10: e115 b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot1, BWMot1)){
8002c12: 2104 movs r1, #4
8002c14: 488d ldr r0, [pc, #564] @ (8002e4c <SetMotPerc+0x2f4>)
8002c16: f7ff fdb7 bl 8002788 <IsPwmRunning>
8002c1a: 4603 mov r3, r0
8002c1c: 2b00 cmp r3, #0
8002c1e: d006 beq.n 8002c2e <SetMotPerc+0xd6>
SetMotPwm(timMot1,BWMot1,pwmval);
8002c20: 897b ldrh r3, [r7, #10]
8002c22: 461a mov r2, r3
8002c24: 2104 movs r1, #4
8002c26: 4889 ldr r0, [pc, #548] @ (8002e4c <SetMotPerc+0x2f4>)
8002c28: f7ff fdfb bl 8002822 <SetMotPwm>
break;
8002c2c: e107 b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
8002c2e: 2201 movs r2, #1
8002c30: 2102 movs r1, #2
8002c32: 4887 ldr r0, [pc, #540] @ (8002e50 <SetMotPerc+0x2f8>)
8002c34: f001 fec9 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot1,BWMot1,pwmval);
8002c38: 897b ldrh r3, [r7, #10]
8002c3a: 461a mov r2, r3
8002c3c: 2104 movs r1, #4
8002c3e: 4883 ldr r0, [pc, #524] @ (8002e4c <SetMotPerc+0x2f4>)
8002c40: f7ff fdc4 bl 80027cc <StartMot>
break;
8002c44: e0fb b.n 8002e3e <SetMotPerc+0x2e6>
case 2:
if(dir==FW){
8002c46: 79bb ldrb r3, [r7, #6]
8002c48: 2b00 cmp r3, #0
8002c4a: d126 bne.n 8002c9a <SetMotPerc+0x142>
if(pwmval==0){
8002c4c: 897b ldrh r3, [r7, #10]
8002c4e: 2b00 cmp r3, #0
8002c50: d109 bne.n 8002c66 <SetMotPerc+0x10e>
StopMot(timMot2,FWMot2);
8002c52: 2108 movs r1, #8
8002c54: 487d ldr r0, [pc, #500] @ (8002e4c <SetMotPerc+0x2f4>)
8002c56: f7ff fdac bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
8002c5a: 2200 movs r2, #0
8002c5c: 2104 movs r1, #4
8002c5e: 487c ldr r0, [pc, #496] @ (8002e50 <SetMotPerc+0x2f8>)
8002c60: f001 feb3 bl 80049ca <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
StartMot(timMot2,BWMot2,pwmval);
}
}
break;
8002c64: e0eb b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot2, FWMot2)){
8002c66: 2108 movs r1, #8
8002c68: 4878 ldr r0, [pc, #480] @ (8002e4c <SetMotPerc+0x2f4>)
8002c6a: f7ff fd8d bl 8002788 <IsPwmRunning>
8002c6e: 4603 mov r3, r0
8002c70: 2b00 cmp r3, #0
8002c72: d006 beq.n 8002c82 <SetMotPerc+0x12a>
SetMotPwm(timMot2,FWMot2,pwmval);
8002c74: 897b ldrh r3, [r7, #10]
8002c76: 461a mov r2, r3
8002c78: 2108 movs r1, #8
8002c7a: 4874 ldr r0, [pc, #464] @ (8002e4c <SetMotPerc+0x2f4>)
8002c7c: f7ff fdd1 bl 8002822 <SetMotPwm>
break;
8002c80: e0dd b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8002c82: 2201 movs r2, #1
8002c84: 2104 movs r1, #4
8002c86: 4872 ldr r0, [pc, #456] @ (8002e50 <SetMotPerc+0x2f8>)
8002c88: f001 fe9f bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot2,FWMot2,pwmval);
8002c8c: 897b ldrh r3, [r7, #10]
8002c8e: 461a mov r2, r3
8002c90: 2108 movs r1, #8
8002c92: 486e ldr r0, [pc, #440] @ (8002e4c <SetMotPerc+0x2f4>)
8002c94: f7ff fd9a bl 80027cc <StartMot>
break;
8002c98: e0d1 b.n 8002e3e <SetMotPerc+0x2e6>
if(pwmval==0){
8002c9a: 897b ldrh r3, [r7, #10]
8002c9c: 2b00 cmp r3, #0
8002c9e: d109 bne.n 8002cb4 <SetMotPerc+0x15c>
StopMot(timMot2,BWMot2);
8002ca0: 210c movs r1, #12
8002ca2: 486a ldr r0, [pc, #424] @ (8002e4c <SetMotPerc+0x2f4>)
8002ca4: f7ff fd85 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
8002ca8: 2200 movs r2, #0
8002caa: 2104 movs r1, #4
8002cac: 4868 ldr r0, [pc, #416] @ (8002e50 <SetMotPerc+0x2f8>)
8002cae: f001 fe8c bl 80049ca <HAL_GPIO_WritePin>
break;
8002cb2: e0c4 b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot2, BWMot2)){
8002cb4: 210c movs r1, #12
8002cb6: 4865 ldr r0, [pc, #404] @ (8002e4c <SetMotPerc+0x2f4>)
8002cb8: f7ff fd66 bl 8002788 <IsPwmRunning>
8002cbc: 4603 mov r3, r0
8002cbe: 2b00 cmp r3, #0
8002cc0: d006 beq.n 8002cd0 <SetMotPerc+0x178>
SetMotPwm(timMot2,BWMot2,pwmval);
8002cc2: 897b ldrh r3, [r7, #10]
8002cc4: 461a mov r2, r3
8002cc6: 210c movs r1, #12
8002cc8: 4860 ldr r0, [pc, #384] @ (8002e4c <SetMotPerc+0x2f4>)
8002cca: f7ff fdaa bl 8002822 <SetMotPwm>
break;
8002cce: e0b6 b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
8002cd0: 2201 movs r2, #1
8002cd2: 2104 movs r1, #4
8002cd4: 485e ldr r0, [pc, #376] @ (8002e50 <SetMotPerc+0x2f8>)
8002cd6: f001 fe78 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot2,BWMot2,pwmval);
8002cda: 897b ldrh r3, [r7, #10]
8002cdc: 461a mov r2, r3
8002cde: 210c movs r1, #12
8002ce0: 485a ldr r0, [pc, #360] @ (8002e4c <SetMotPerc+0x2f4>)
8002ce2: f7ff fd73 bl 80027cc <StartMot>
break;
8002ce6: e0aa b.n 8002e3e <SetMotPerc+0x2e6>
case 3:
if(dir==FW){
8002ce8: 79bb ldrb r3, [r7, #6]
8002cea: 2b00 cmp r3, #0
8002cec: d128 bne.n 8002d40 <SetMotPerc+0x1e8>
if(pwmval==0){
8002cee: 897b ldrh r3, [r7, #10]
8002cf0: 2b00 cmp r3, #0
8002cf2: d10a bne.n 8002d0a <SetMotPerc+0x1b2>
StopMot(timMot3,FWMot3);
8002cf4: 2100 movs r1, #0
8002cf6: 4857 ldr r0, [pc, #348] @ (8002e54 <SetMotPerc+0x2fc>)
8002cf8: f7ff fd5b bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8002cfc: 2200 movs r2, #0
8002cfe: f44f 6180 mov.w r1, #1024 @ 0x400
8002d02: 4853 ldr r0, [pc, #332] @ (8002e50 <SetMotPerc+0x2f8>)
8002d04: f001 fe61 bl 80049ca <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
StartMot(timMot3,BWMot3,pwmval);
}
}
break;
8002d08: e099 b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot3, FWMot3)){
8002d0a: 2100 movs r1, #0
8002d0c: 4851 ldr r0, [pc, #324] @ (8002e54 <SetMotPerc+0x2fc>)
8002d0e: f7ff fd3b bl 8002788 <IsPwmRunning>
8002d12: 4603 mov r3, r0
8002d14: 2b00 cmp r3, #0
8002d16: d006 beq.n 8002d26 <SetMotPerc+0x1ce>
SetMotPwm(timMot3,FWMot3,pwmval);
8002d18: 897b ldrh r3, [r7, #10]
8002d1a: 461a mov r2, r3
8002d1c: 2100 movs r1, #0
8002d1e: 484d ldr r0, [pc, #308] @ (8002e54 <SetMotPerc+0x2fc>)
8002d20: f7ff fd7f bl 8002822 <SetMotPwm>
break;
8002d24: e08b b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8002d26: 2201 movs r2, #1
8002d28: f44f 6180 mov.w r1, #1024 @ 0x400
8002d2c: 4848 ldr r0, [pc, #288] @ (8002e50 <SetMotPerc+0x2f8>)
8002d2e: f001 fe4c bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot3,FWMot3,pwmval);
8002d32: 897b ldrh r3, [r7, #10]
8002d34: 461a mov r2, r3
8002d36: 2100 movs r1, #0
8002d38: 4846 ldr r0, [pc, #280] @ (8002e54 <SetMotPerc+0x2fc>)
8002d3a: f7ff fd47 bl 80027cc <StartMot>
break;
8002d3e: e07e b.n 8002e3e <SetMotPerc+0x2e6>
if(pwmval==0){
8002d40: 897b ldrh r3, [r7, #10]
8002d42: 2b00 cmp r3, #0
8002d44: d10a bne.n 8002d5c <SetMotPerc+0x204>
StopMot(timMot3,BWMot3);
8002d46: 2104 movs r1, #4
8002d48: 4842 ldr r0, [pc, #264] @ (8002e54 <SetMotPerc+0x2fc>)
8002d4a: f7ff fd32 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
8002d4e: 2200 movs r2, #0
8002d50: f44f 6180 mov.w r1, #1024 @ 0x400
8002d54: 483e ldr r0, [pc, #248] @ (8002e50 <SetMotPerc+0x2f8>)
8002d56: f001 fe38 bl 80049ca <HAL_GPIO_WritePin>
break;
8002d5a: e070 b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot3, BWMot3)){
8002d5c: 2104 movs r1, #4
8002d5e: 483d ldr r0, [pc, #244] @ (8002e54 <SetMotPerc+0x2fc>)
8002d60: f7ff fd12 bl 8002788 <IsPwmRunning>
8002d64: 4603 mov r3, r0
8002d66: 2b00 cmp r3, #0
8002d68: d006 beq.n 8002d78 <SetMotPerc+0x220>
SetMotPwm(timMot3,BWMot3,pwmval);
8002d6a: 897b ldrh r3, [r7, #10]
8002d6c: 461a mov r2, r3
8002d6e: 2104 movs r1, #4
8002d70: 4838 ldr r0, [pc, #224] @ (8002e54 <SetMotPerc+0x2fc>)
8002d72: f7ff fd56 bl 8002822 <SetMotPwm>
break;
8002d76: e062 b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
8002d78: 2201 movs r2, #1
8002d7a: f44f 6180 mov.w r1, #1024 @ 0x400
8002d7e: 4834 ldr r0, [pc, #208] @ (8002e50 <SetMotPerc+0x2f8>)
8002d80: f001 fe23 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot3,BWMot3,pwmval);
8002d84: 897b ldrh r3, [r7, #10]
8002d86: 461a mov r2, r3
8002d88: 2104 movs r1, #4
8002d8a: 4832 ldr r0, [pc, #200] @ (8002e54 <SetMotPerc+0x2fc>)
8002d8c: f7ff fd1e bl 80027cc <StartMot>
break;
8002d90: e055 b.n 8002e3e <SetMotPerc+0x2e6>
case 4:
if(dir==FW){
8002d92: 79bb ldrb r3, [r7, #6]
8002d94: 2b00 cmp r3, #0
8002d96: d128 bne.n 8002dea <SetMotPerc+0x292>
if(pwmval==0){
8002d98: 897b ldrh r3, [r7, #10]
8002d9a: 2b00 cmp r3, #0
8002d9c: d10a bne.n 8002db4 <SetMotPerc+0x25c>
StopMot(timMot4,FWMot4);
8002d9e: 2108 movs r1, #8
8002da0: 482c ldr r0, [pc, #176] @ (8002e54 <SetMotPerc+0x2fc>)
8002da2: f7ff fd06 bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8002da6: 2200 movs r2, #0
8002da8: f44f 6100 mov.w r1, #2048 @ 0x800
8002dac: 4828 ldr r0, [pc, #160] @ (8002e50 <SetMotPerc+0x2f8>)
8002dae: f001 fe0c bl 80049ca <HAL_GPIO_WritePin>
}else{
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
StartMot(timMot4,BWMot4,pwmval);
}
}
break;
8002db2: e044 b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot4, FWMot4)){
8002db4: 2108 movs r1, #8
8002db6: 4827 ldr r0, [pc, #156] @ (8002e54 <SetMotPerc+0x2fc>)
8002db8: f7ff fce6 bl 8002788 <IsPwmRunning>
8002dbc: 4603 mov r3, r0
8002dbe: 2b00 cmp r3, #0
8002dc0: d006 beq.n 8002dd0 <SetMotPerc+0x278>
SetMotPwm(timMot4,FWMot4,pwmval);
8002dc2: 897b ldrh r3, [r7, #10]
8002dc4: 461a mov r2, r3
8002dc6: 2108 movs r1, #8
8002dc8: 4822 ldr r0, [pc, #136] @ (8002e54 <SetMotPerc+0x2fc>)
8002dca: f7ff fd2a bl 8002822 <SetMotPwm>
break;
8002dce: e036 b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8002dd0: 2201 movs r2, #1
8002dd2: f44f 6100 mov.w r1, #2048 @ 0x800
8002dd6: 481e ldr r0, [pc, #120] @ (8002e50 <SetMotPerc+0x2f8>)
8002dd8: f001 fdf7 bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot4,FWMot4,pwmval);
8002ddc: 897b ldrh r3, [r7, #10]
8002dde: 461a mov r2, r3
8002de0: 2108 movs r1, #8
8002de2: 481c ldr r0, [pc, #112] @ (8002e54 <SetMotPerc+0x2fc>)
8002de4: f7ff fcf2 bl 80027cc <StartMot>
break;
8002de8: e029 b.n 8002e3e <SetMotPerc+0x2e6>
if(pwmval==0){
8002dea: 897b ldrh r3, [r7, #10]
8002dec: 2b00 cmp r3, #0
8002dee: d10a bne.n 8002e06 <SetMotPerc+0x2ae>
StopMot(timMot4,BWMot4);
8002df0: 210c movs r1, #12
8002df2: 4818 ldr r0, [pc, #96] @ (8002e54 <SetMotPerc+0x2fc>)
8002df4: f7ff fcdd bl 80027b2 <StopMot>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
8002df8: 2200 movs r2, #0
8002dfa: f44f 6100 mov.w r1, #2048 @ 0x800
8002dfe: 4814 ldr r0, [pc, #80] @ (8002e50 <SetMotPerc+0x2f8>)
8002e00: f001 fde3 bl 80049ca <HAL_GPIO_WritePin>
break;
8002e04: e01b b.n 8002e3e <SetMotPerc+0x2e6>
}else if(IsPwmRunning(timMot4, BWMot4)){
8002e06: 210c movs r1, #12
8002e08: 4812 ldr r0, [pc, #72] @ (8002e54 <SetMotPerc+0x2fc>)
8002e0a: f7ff fcbd bl 8002788 <IsPwmRunning>
8002e0e: 4603 mov r3, r0
8002e10: 2b00 cmp r3, #0
8002e12: d006 beq.n 8002e22 <SetMotPerc+0x2ca>
SetMotPwm(timMot4,BWMot4,pwmval);
8002e14: 897b ldrh r3, [r7, #10]
8002e16: 461a mov r2, r3
8002e18: 210c movs r1, #12
8002e1a: 480e ldr r0, [pc, #56] @ (8002e54 <SetMotPerc+0x2fc>)
8002e1c: f7ff fd01 bl 8002822 <SetMotPwm>
break;
8002e20: e00d b.n 8002e3e <SetMotPerc+0x2e6>
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
8002e22: 2201 movs r2, #1
8002e24: f44f 6100 mov.w r1, #2048 @ 0x800
8002e28: 4809 ldr r0, [pc, #36] @ (8002e50 <SetMotPerc+0x2f8>)
8002e2a: f001 fdce bl 80049ca <HAL_GPIO_WritePin>
StartMot(timMot4,BWMot4,pwmval);
8002e2e: 897b ldrh r3, [r7, #10]
8002e30: 461a mov r2, r3
8002e32: 210c movs r1, #12
8002e34: 4807 ldr r0, [pc, #28] @ (8002e54 <SetMotPerc+0x2fc>)
8002e36: f7ff fcc9 bl 80027cc <StartMot>
break;
8002e3a: e000 b.n 8002e3e <SetMotPerc+0x2e6>
default:
break;
8002e3c: bf00 nop
}
}
8002e3e: bf00 nop
8002e40: 3710 adds r7, #16
8002e42: 46bd mov sp, r7
8002e44: bd80 pop {r7, pc}
8002e46: bf00 nop
8002e48: 51eb851f .word 0x51eb851f
8002e4c: 20000308 .word 0x20000308
8002e50: 40010c00 .word 0x40010c00
8002e54: 20000350 .word 0x20000350
08002e58 <ramp>:
uint8_t ramp(uint8_t mot,uint8_t dir,uint8_t percStart,uint8_t percEnd,uint8_t tr,uint8_t mode){
8002e58: b590 push {r4, r7, lr}
8002e5a: b085 sub sp, #20
8002e5c: af00 add r7, sp, #0
8002e5e: 4604 mov r4, r0
8002e60: 4608 mov r0, r1
8002e62: 4611 mov r1, r2
8002e64: 461a mov r2, r3
8002e66: 4623 mov r3, r4
8002e68: 71fb strb r3, [r7, #7]
8002e6a: 4603 mov r3, r0
8002e6c: 71bb strb r3, [r7, #6]
8002e6e: 460b mov r3, r1
8002e70: 717b strb r3, [r7, #5]
8002e72: 4613 mov r3, r2
8002e74: 713b strb r3, [r7, #4]
static uint8_t memrtramp[4];
uint16_t delta;
switch(mode){
8002e76: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8002e7a: 2b00 cmp r3, #0
8002e7c: d002 beq.n 8002e84 <ramp+0x2c>
8002e7e: 2b0a cmp r3, #10
8002e80: d013 beq.n 8002eaa <ramp+0x52>
8002e82: e0a5 b.n 8002fd0 <ramp+0x178>
case RAMPINIT:
memrtramp[mot-1]=percStart=tr;
8002e84: f897 3020 ldrb.w r3, [r7, #32]
8002e88: 717b strb r3, [r7, #5]
8002e8a: 79fb ldrb r3, [r7, #7]
8002e8c: 3b01 subs r3, #1
8002e8e: 4953 ldr r1, [pc, #332] @ (8002fdc <ramp+0x184>)
8002e90: 797a ldrb r2, [r7, #5]
8002e92: 54ca strb r2, [r1, r3]
SetMotPerc(mot,dir,mrampstart[mot-1]);
8002e94: 79fb ldrb r3, [r7, #7]
8002e96: 3b01 subs r3, #1
8002e98: 4a51 ldr r2, [pc, #324] @ (8002fe0 <ramp+0x188>)
8002e9a: 5cd2 ldrb r2, [r2, r3]
8002e9c: 79b9 ldrb r1, [r7, #6]
8002e9e: 79fb ldrb r3, [r7, #7]
8002ea0: 4618 mov r0, r3
8002ea2: f7ff fe59 bl 8002b58 <SetMotPerc>
return DONE;
8002ea6: 2300 movs r3, #0
8002ea8: e093 b.n 8002fd2 <ramp+0x17a>
case RAMPRUN:
if(memrtramp[mot-1]!=rtramp[mot-1]){
8002eaa: 79fb ldrb r3, [r7, #7]
8002eac: 3b01 subs r3, #1
8002eae: 4a4b ldr r2, [pc, #300] @ (8002fdc <ramp+0x184>)
8002eb0: 5cd2 ldrb r2, [r2, r3]
8002eb2: 79fb ldrb r3, [r7, #7]
8002eb4: 3b01 subs r3, #1
8002eb6: 494b ldr r1, [pc, #300] @ (8002fe4 <ramp+0x18c>)
8002eb8: 5ccb ldrb r3, [r1, r3]
8002eba: b2db uxtb r3, r3
8002ebc: 429a cmp r2, r3
8002ebe: f000 8085 beq.w 8002fcc <ramp+0x174>
memrtramp[mot-1]=rtramp[mot-1];
8002ec2: 79fb ldrb r3, [r7, #7]
8002ec4: 1e5a subs r2, r3, #1
8002ec6: 79fb ldrb r3, [r7, #7]
8002ec8: 3b01 subs r3, #1
8002eca: 4946 ldr r1, [pc, #280] @ (8002fe4 <ramp+0x18c>)
8002ecc: 5c8a ldrb r2, [r1, r2]
8002ece: b2d1 uxtb r1, r2
8002ed0: 4a42 ldr r2, [pc, #264] @ (8002fdc <ramp+0x184>)
8002ed2: 54d1 strb r1, [r2, r3]
if(rtramp[mot-1]){
8002ed4: 79fb ldrb r3, [r7, #7]
8002ed6: 3b01 subs r3, #1
8002ed8: 4a42 ldr r2, [pc, #264] @ (8002fe4 <ramp+0x18c>)
8002eda: 5cd3 ldrb r3, [r2, r3]
8002edc: b2db uxtb r3, r3
8002ede: 2b00 cmp r3, #0
8002ee0: d06c beq.n 8002fbc <ramp+0x164>
if(mrampstart[mot-1]>percEnd){
8002ee2: 79fb ldrb r3, [r7, #7]
8002ee4: 3b01 subs r3, #1
8002ee6: 4a3e ldr r2, [pc, #248] @ (8002fe0 <ramp+0x188>)
8002ee8: 5cd3 ldrb r3, [r2, r3]
8002eea: 793a ldrb r2, [r7, #4]
8002eec: 429a cmp r2, r3
8002eee: d22b bcs.n 8002f48 <ramp+0xf0>
delta=mrampstart[mot-1]-percEnd;
8002ef0: 79fb ldrb r3, [r7, #7]
8002ef2: 3b01 subs r3, #1
8002ef4: 4a3a ldr r2, [pc, #232] @ (8002fe0 <ramp+0x188>)
8002ef6: 5cd3 ldrb r3, [r2, r3]
8002ef8: 461a mov r2, r3
8002efa: 793b ldrb r3, [r7, #4]
8002efc: b29b uxth r3, r3
8002efe: 1ad3 subs r3, r2, r3
8002f00: 81fb strh r3, [r7, #14]
delta=delta*(uint16_t)(tr-rtramp[mot-1]);
8002f02: f897 3020 ldrb.w r3, [r7, #32]
8002f06: b29b uxth r3, r3
8002f08: 79fa ldrb r2, [r7, #7]
8002f0a: 3a01 subs r2, #1
8002f0c: 4935 ldr r1, [pc, #212] @ (8002fe4 <ramp+0x18c>)
8002f0e: 5c8a ldrb r2, [r1, r2]
8002f10: b2d2 uxtb r2, r2
8002f12: 1a9b subs r3, r3, r2
8002f14: b29b uxth r3, r3
8002f16: 89fa ldrh r2, [r7, #14]
8002f18: fb02 f303 mul.w r3, r2, r3
8002f1c: 81fb strh r3, [r7, #14]
delta=delta/tr;
8002f1e: 89fa ldrh r2, [r7, #14]
8002f20: f897 3020 ldrb.w r3, [r7, #32]
8002f24: fb92 f3f3 sdiv r3, r2, r3
8002f28: 81fb strh r3, [r7, #14]
SetMotPerc(mot,dir,mrampstart[mot-1]-delta);
8002f2a: 79fb ldrb r3, [r7, #7]
8002f2c: 3b01 subs r3, #1
8002f2e: 4a2c ldr r2, [pc, #176] @ (8002fe0 <ramp+0x188>)
8002f30: 5cd2 ldrb r2, [r2, r3]
8002f32: 89fb ldrh r3, [r7, #14]
8002f34: b2db uxtb r3, r3
8002f36: 1ad3 subs r3, r2, r3
8002f38: b2da uxtb r2, r3
8002f3a: 79b9 ldrb r1, [r7, #6]
8002f3c: 79fb ldrb r3, [r7, #7]
8002f3e: 4618 mov r0, r3
8002f40: f7ff fe0a bl 8002b58 <SetMotPerc>
return RUNNING;
8002f44: 2301 movs r3, #1
8002f46: e044 b.n 8002fd2 <ramp+0x17a>
}else if(mrampstart[mot-1]<percEnd){
8002f48: 79fb ldrb r3, [r7, #7]
8002f4a: 3b01 subs r3, #1
8002f4c: 4a24 ldr r2, [pc, #144] @ (8002fe0 <ramp+0x188>)
8002f4e: 5cd3 ldrb r3, [r2, r3]
8002f50: 793a ldrb r2, [r7, #4]
8002f52: 429a cmp r2, r3
8002f54: d92a bls.n 8002fac <ramp+0x154>
delta=percEnd-mrampstart[mot-1];
8002f56: 793b ldrb r3, [r7, #4]
8002f58: b29b uxth r3, r3
8002f5a: 79fa ldrb r2, [r7, #7]
8002f5c: 3a01 subs r2, #1
8002f5e: 4920 ldr r1, [pc, #128] @ (8002fe0 <ramp+0x188>)
8002f60: 5c8a ldrb r2, [r1, r2]
8002f62: 1a9b subs r3, r3, r2
8002f64: 81fb strh r3, [r7, #14]
delta=delta*(uint16_t)(tr-rtramp[mot-1]);
8002f66: f897 3020 ldrb.w r3, [r7, #32]
8002f6a: b29b uxth r3, r3
8002f6c: 79fa ldrb r2, [r7, #7]
8002f6e: 3a01 subs r2, #1
8002f70: 491c ldr r1, [pc, #112] @ (8002fe4 <ramp+0x18c>)
8002f72: 5c8a ldrb r2, [r1, r2]
8002f74: b2d2 uxtb r2, r2
8002f76: 1a9b subs r3, r3, r2
8002f78: b29b uxth r3, r3
8002f7a: 89fa ldrh r2, [r7, #14]
8002f7c: fb02 f303 mul.w r3, r2, r3
8002f80: 81fb strh r3, [r7, #14]
delta=delta/tr;
8002f82: 89fa ldrh r2, [r7, #14]
8002f84: f897 3020 ldrb.w r3, [r7, #32]
8002f88: fb92 f3f3 sdiv r3, r2, r3
8002f8c: 81fb strh r3, [r7, #14]
SetMotPerc(mot,dir,mrampstart[mot-1]+delta);
8002f8e: 79fb ldrb r3, [r7, #7]
8002f90: 3b01 subs r3, #1
8002f92: 4a13 ldr r2, [pc, #76] @ (8002fe0 <ramp+0x188>)
8002f94: 5cd2 ldrb r2, [r2, r3]
8002f96: 89fb ldrh r3, [r7, #14]
8002f98: b2db uxtb r3, r3
8002f9a: 4413 add r3, r2
8002f9c: b2da uxtb r2, r3
8002f9e: 79b9 ldrb r1, [r7, #6]
8002fa0: 79fb ldrb r3, [r7, #7]
8002fa2: 4618 mov r0, r3
8002fa4: f7ff fdd8 bl 8002b58 <SetMotPerc>
return RUNNING;
8002fa8: 2301 movs r3, #1
8002faa: e012 b.n 8002fd2 <ramp+0x17a>
}else{
SetMotPerc(mot,dir,percEnd);
8002fac: 793a ldrb r2, [r7, #4]
8002fae: 79b9 ldrb r1, [r7, #6]
8002fb0: 79fb ldrb r3, [r7, #7]
8002fb2: 4618 mov r0, r3
8002fb4: f7ff fdd0 bl 8002b58 <SetMotPerc>
return DONE;
8002fb8: 2300 movs r3, #0
8002fba: e00a b.n 8002fd2 <ramp+0x17a>
}
}else{
SetMotPerc(mot,dir,percEnd);
8002fbc: 793a ldrb r2, [r7, #4]
8002fbe: 79b9 ldrb r1, [r7, #6]
8002fc0: 79fb ldrb r3, [r7, #7]
8002fc2: 4618 mov r0, r3
8002fc4: f7ff fdc8 bl 8002b58 <SetMotPerc>
return DONE;
8002fc8: 2300 movs r3, #0
8002fca: e002 b.n 8002fd2 <ramp+0x17a>
}
}else return RUNNING;
8002fcc: 2301 movs r3, #1
8002fce: e000 b.n 8002fd2 <ramp+0x17a>
break;
}
return DONE;
8002fd0: 2300 movs r3, #0
}
8002fd2: 4618 mov r0, r3
8002fd4: 3714 adds r7, #20
8002fd6: 46bd mov sp, r7
8002fd8: bd90 pop {r4, r7, pc}
8002fda: bf00 nop
8002fdc: 2000042c .word 0x2000042c
8002fe0: 20000414 .word 0x20000414
8002fe4: 200003e4 .word 0x200003e4
08002fe8 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8002fe8: b480 push {r7}
8002fea: b085 sub sp, #20
8002fec: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8002fee: 4b15 ldr r3, [pc, #84] @ (8003044 <HAL_MspInit+0x5c>)
8002ff0: 699b ldr r3, [r3, #24]
8002ff2: 4a14 ldr r2, [pc, #80] @ (8003044 <HAL_MspInit+0x5c>)
8002ff4: f043 0301 orr.w r3, r3, #1
8002ff8: 6193 str r3, [r2, #24]
8002ffa: 4b12 ldr r3, [pc, #72] @ (8003044 <HAL_MspInit+0x5c>)
8002ffc: 699b ldr r3, [r3, #24]
8002ffe: f003 0301 and.w r3, r3, #1
8003002: 60bb str r3, [r7, #8]
8003004: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8003006: 4b0f ldr r3, [pc, #60] @ (8003044 <HAL_MspInit+0x5c>)
8003008: 69db ldr r3, [r3, #28]
800300a: 4a0e ldr r2, [pc, #56] @ (8003044 <HAL_MspInit+0x5c>)
800300c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003010: 61d3 str r3, [r2, #28]
8003012: 4b0c ldr r3, [pc, #48] @ (8003044 <HAL_MspInit+0x5c>)
8003014: 69db ldr r3, [r3, #28]
8003016: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800301a: 607b str r3, [r7, #4]
800301c: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
800301e: 4b0a ldr r3, [pc, #40] @ (8003048 <HAL_MspInit+0x60>)
8003020: 685b ldr r3, [r3, #4]
8003022: 60fb str r3, [r7, #12]
8003024: 68fb ldr r3, [r7, #12]
8003026: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
800302a: 60fb str r3, [r7, #12]
800302c: 68fb ldr r3, [r7, #12]
800302e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8003032: 60fb str r3, [r7, #12]
8003034: 4a04 ldr r2, [pc, #16] @ (8003048 <HAL_MspInit+0x60>)
8003036: 68fb ldr r3, [r7, #12]
8003038: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800303a: bf00 nop
800303c: 3714 adds r7, #20
800303e: 46bd mov sp, r7
8003040: bc80 pop {r7}
8003042: 4770 bx lr
8003044: 40021000 .word 0x40021000
8003048: 40010000 .word 0x40010000
0800304c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
800304c: b580 push {r7, lr}
800304e: b08a sub sp, #40 @ 0x28
8003050: af00 add r7, sp, #0
8003052: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003054: f107 0318 add.w r3, r7, #24
8003058: 2200 movs r2, #0
800305a: 601a str r2, [r3, #0]
800305c: 605a str r2, [r3, #4]
800305e: 609a str r2, [r3, #8]
8003060: 60da str r2, [r3, #12]
if(hadc->Instance==ADC1)
8003062: 687b ldr r3, [r7, #4]
8003064: 681b ldr r3, [r3, #0]
8003066: 4a33 ldr r2, [pc, #204] @ (8003134 <HAL_ADC_MspInit+0xe8>)
8003068: 4293 cmp r3, r2
800306a: d15f bne.n 800312c <HAL_ADC_MspInit+0xe0>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
800306c: 4b32 ldr r3, [pc, #200] @ (8003138 <HAL_ADC_MspInit+0xec>)
800306e: 699b ldr r3, [r3, #24]
8003070: 4a31 ldr r2, [pc, #196] @ (8003138 <HAL_ADC_MspInit+0xec>)
8003072: f443 7300 orr.w r3, r3, #512 @ 0x200
8003076: 6193 str r3, [r2, #24]
8003078: 4b2f ldr r3, [pc, #188] @ (8003138 <HAL_ADC_MspInit+0xec>)
800307a: 699b ldr r3, [r3, #24]
800307c: f403 7300 and.w r3, r3, #512 @ 0x200
8003080: 617b str r3, [r7, #20]
8003082: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8003084: 4b2c ldr r3, [pc, #176] @ (8003138 <HAL_ADC_MspInit+0xec>)
8003086: 699b ldr r3, [r3, #24]
8003088: 4a2b ldr r2, [pc, #172] @ (8003138 <HAL_ADC_MspInit+0xec>)
800308a: f043 0304 orr.w r3, r3, #4
800308e: 6193 str r3, [r2, #24]
8003090: 4b29 ldr r3, [pc, #164] @ (8003138 <HAL_ADC_MspInit+0xec>)
8003092: 699b ldr r3, [r3, #24]
8003094: f003 0304 and.w r3, r3, #4
8003098: 613b str r3, [r7, #16]
800309a: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
800309c: 4b26 ldr r3, [pc, #152] @ (8003138 <HAL_ADC_MspInit+0xec>)
800309e: 699b ldr r3, [r3, #24]
80030a0: 4a25 ldr r2, [pc, #148] @ (8003138 <HAL_ADC_MspInit+0xec>)
80030a2: f043 0308 orr.w r3, r3, #8
80030a6: 6193 str r3, [r2, #24]
80030a8: 4b23 ldr r3, [pc, #140] @ (8003138 <HAL_ADC_MspInit+0xec>)
80030aa: 699b ldr r3, [r3, #24]
80030ac: f003 0308 and.w r3, r3, #8
80030b0: 60fb str r3, [r7, #12]
80030b2: 68fb ldr r3, [r7, #12]
PA5 ------> ADC1_IN5
PA6 ------> ADC1_IN6
PA7 ------> ADC1_IN7
PB0 ------> ADC1_IN8
*/
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin|AIN3_Pin|AIN4_Pin;
80030b4: 23f0 movs r3, #240 @ 0xf0
80030b6: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80030b8: 2303 movs r3, #3
80030ba: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80030bc: f107 0318 add.w r3, r7, #24
80030c0: 4619 mov r1, r3
80030c2: 481e ldr r0, [pc, #120] @ (800313c <HAL_ADC_MspInit+0xf0>)
80030c4: f001 fae6 bl 8004694 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ANEM_Pin;
80030c8: 2301 movs r3, #1
80030ca: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80030cc: 2303 movs r3, #3
80030ce: 61fb str r3, [r7, #28]
HAL_GPIO_Init(ANEM_GPIO_Port, &GPIO_InitStruct);
80030d0: f107 0318 add.w r3, r7, #24
80030d4: 4619 mov r1, r3
80030d6: 481a ldr r0, [pc, #104] @ (8003140 <HAL_ADC_MspInit+0xf4>)
80030d8: f001 fadc bl 8004694 <HAL_GPIO_Init>
/* ADC1 DMA Init */
/* ADC1 Init */
hdma_adc1.Instance = DMA1_Channel1;
80030dc: 4b19 ldr r3, [pc, #100] @ (8003144 <HAL_ADC_MspInit+0xf8>)
80030de: 4a1a ldr r2, [pc, #104] @ (8003148 <HAL_ADC_MspInit+0xfc>)
80030e0: 601a str r2, [r3, #0]
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
80030e2: 4b18 ldr r3, [pc, #96] @ (8003144 <HAL_ADC_MspInit+0xf8>)
80030e4: 2200 movs r2, #0
80030e6: 605a str r2, [r3, #4]
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
80030e8: 4b16 ldr r3, [pc, #88] @ (8003144 <HAL_ADC_MspInit+0xf8>)
80030ea: 2200 movs r2, #0
80030ec: 609a str r2, [r3, #8]
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
80030ee: 4b15 ldr r3, [pc, #84] @ (8003144 <HAL_ADC_MspInit+0xf8>)
80030f0: 2280 movs r2, #128 @ 0x80
80030f2: 60da str r2, [r3, #12]
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
80030f4: 4b13 ldr r3, [pc, #76] @ (8003144 <HAL_ADC_MspInit+0xf8>)
80030f6: f44f 7280 mov.w r2, #256 @ 0x100
80030fa: 611a str r2, [r3, #16]
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
80030fc: 4b11 ldr r3, [pc, #68] @ (8003144 <HAL_ADC_MspInit+0xf8>)
80030fe: f44f 6280 mov.w r2, #1024 @ 0x400
8003102: 615a str r2, [r3, #20]
hdma_adc1.Init.Mode = DMA_CIRCULAR;
8003104: 4b0f ldr r3, [pc, #60] @ (8003144 <HAL_ADC_MspInit+0xf8>)
8003106: 2220 movs r2, #32
8003108: 619a str r2, [r3, #24]
hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
800310a: 4b0e ldr r3, [pc, #56] @ (8003144 <HAL_ADC_MspInit+0xf8>)
800310c: 2200 movs r2, #0
800310e: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
8003110: 480c ldr r0, [pc, #48] @ (8003144 <HAL_ADC_MspInit+0xf8>)
8003112: f000 fed1 bl 8003eb8 <HAL_DMA_Init>
8003116: 4603 mov r3, r0
8003118: 2b00 cmp r3, #0
800311a: d001 beq.n 8003120 <HAL_ADC_MspInit+0xd4>
{
Error_Handler();
800311c: f7ff fb2e bl 800277c <Error_Handler>
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
8003120: 687b ldr r3, [r7, #4]
8003122: 4a08 ldr r2, [pc, #32] @ (8003144 <HAL_ADC_MspInit+0xf8>)
8003124: 621a str r2, [r3, #32]
8003126: 4a07 ldr r2, [pc, #28] @ (8003144 <HAL_ADC_MspInit+0xf8>)
8003128: 687b ldr r3, [r7, #4]
800312a: 6253 str r3, [r2, #36] @ 0x24
/* USER CODE END ADC1_MspInit 1 */
}
}
800312c: bf00 nop
800312e: 3728 adds r7, #40 @ 0x28
8003130: 46bd mov sp, r7
8003132: bd80 pop {r7, pc}
8003134: 40012400 .word 0x40012400
8003138: 40021000 .word 0x40021000
800313c: 40010800 .word 0x40010800
8003140: 40010c00 .word 0x40010c00
8003144: 200002c4 .word 0x200002c4
8003148: 40020008 .word 0x40020008
0800314c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
800314c: b480 push {r7}
800314e: b085 sub sp, #20
8003150: af00 add r7, sp, #0
8003152: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
8003154: 687b ldr r3, [r7, #4]
8003156: 681b ldr r3, [r3, #0]
8003158: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800315c: d10c bne.n 8003178 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
800315e: 4b11 ldr r3, [pc, #68] @ (80031a4 <HAL_TIM_Base_MspInit+0x58>)
8003160: 69db ldr r3, [r3, #28]
8003162: 4a10 ldr r2, [pc, #64] @ (80031a4 <HAL_TIM_Base_MspInit+0x58>)
8003164: f043 0301 orr.w r3, r3, #1
8003168: 61d3 str r3, [r2, #28]
800316a: 4b0e ldr r3, [pc, #56] @ (80031a4 <HAL_TIM_Base_MspInit+0x58>)
800316c: 69db ldr r3, [r3, #28]
800316e: f003 0301 and.w r3, r3, #1
8003172: 60fb str r3, [r7, #12]
8003174: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
8003176: e010 b.n 800319a <HAL_TIM_Base_MspInit+0x4e>
else if(htim_base->Instance==TIM4)
8003178: 687b ldr r3, [r7, #4]
800317a: 681b ldr r3, [r3, #0]
800317c: 4a0a ldr r2, [pc, #40] @ (80031a8 <HAL_TIM_Base_MspInit+0x5c>)
800317e: 4293 cmp r3, r2
8003180: d10b bne.n 800319a <HAL_TIM_Base_MspInit+0x4e>
__HAL_RCC_TIM4_CLK_ENABLE();
8003182: 4b08 ldr r3, [pc, #32] @ (80031a4 <HAL_TIM_Base_MspInit+0x58>)
8003184: 69db ldr r3, [r3, #28]
8003186: 4a07 ldr r2, [pc, #28] @ (80031a4 <HAL_TIM_Base_MspInit+0x58>)
8003188: f043 0304 orr.w r3, r3, #4
800318c: 61d3 str r3, [r2, #28]
800318e: 4b05 ldr r3, [pc, #20] @ (80031a4 <HAL_TIM_Base_MspInit+0x58>)
8003190: 69db ldr r3, [r3, #28]
8003192: f003 0304 and.w r3, r3, #4
8003196: 60bb str r3, [r7, #8]
8003198: 68bb ldr r3, [r7, #8]
}
800319a: bf00 nop
800319c: 3714 adds r7, #20
800319e: 46bd mov sp, r7
80031a0: bc80 pop {r7}
80031a2: 4770 bx lr
80031a4: 40021000 .word 0x40021000
80031a8: 40000800 .word 0x40000800
080031ac <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
80031ac: b580 push {r7, lr}
80031ae: b088 sub sp, #32
80031b0: af00 add r7, sp, #0
80031b2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80031b4: f107 0310 add.w r3, r7, #16
80031b8: 2200 movs r2, #0
80031ba: 601a str r2, [r3, #0]
80031bc: 605a str r2, [r3, #4]
80031be: 609a str r2, [r3, #8]
80031c0: 60da str r2, [r3, #12]
if(htim->Instance==TIM2)
80031c2: 687b ldr r3, [r7, #4]
80031c4: 681b ldr r3, [r3, #0]
80031c6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80031ca: d118 bne.n 80031fe <HAL_TIM_MspPostInit+0x52>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
80031cc: 4b1d ldr r3, [pc, #116] @ (8003244 <HAL_TIM_MspPostInit+0x98>)
80031ce: 699b ldr r3, [r3, #24]
80031d0: 4a1c ldr r2, [pc, #112] @ (8003244 <HAL_TIM_MspPostInit+0x98>)
80031d2: f043 0304 orr.w r3, r3, #4
80031d6: 6193 str r3, [r2, #24]
80031d8: 4b1a ldr r3, [pc, #104] @ (8003244 <HAL_TIM_MspPostInit+0x98>)
80031da: 699b ldr r3, [r3, #24]
80031dc: f003 0304 and.w r3, r3, #4
80031e0: 60fb str r3, [r7, #12]
80031e2: 68fb ldr r3, [r7, #12]
PA0-WKUP ------> TIM2_CH1
PA1 ------> TIM2_CH2
PA2 ------> TIM2_CH3
PA3 ------> TIM2_CH4
*/
GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|IN3_Pin|IN4_Pin;
80031e4: 230f movs r3, #15
80031e6: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80031e8: 2302 movs r3, #2
80031ea: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80031ec: 2302 movs r3, #2
80031ee: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80031f0: f107 0310 add.w r3, r7, #16
80031f4: 4619 mov r1, r3
80031f6: 4814 ldr r0, [pc, #80] @ (8003248 <HAL_TIM_MspPostInit+0x9c>)
80031f8: f001 fa4c bl 8004694 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
80031fc: e01d b.n 800323a <HAL_TIM_MspPostInit+0x8e>
else if(htim->Instance==TIM4)
80031fe: 687b ldr r3, [r7, #4]
8003200: 681b ldr r3, [r3, #0]
8003202: 4a12 ldr r2, [pc, #72] @ (800324c <HAL_TIM_MspPostInit+0xa0>)
8003204: 4293 cmp r3, r2
8003206: d118 bne.n 800323a <HAL_TIM_MspPostInit+0x8e>
__HAL_RCC_GPIOB_CLK_ENABLE();
8003208: 4b0e ldr r3, [pc, #56] @ (8003244 <HAL_TIM_MspPostInit+0x98>)
800320a: 699b ldr r3, [r3, #24]
800320c: 4a0d ldr r2, [pc, #52] @ (8003244 <HAL_TIM_MspPostInit+0x98>)
800320e: f043 0308 orr.w r3, r3, #8
8003212: 6193 str r3, [r2, #24]
8003214: 4b0b ldr r3, [pc, #44] @ (8003244 <HAL_TIM_MspPostInit+0x98>)
8003216: 699b ldr r3, [r3, #24]
8003218: f003 0308 and.w r3, r3, #8
800321c: 60bb str r3, [r7, #8]
800321e: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = IN5_Pin|IN6_Pin|IN7_Pin|IN8_Pin;
8003220: f44f 7370 mov.w r3, #960 @ 0x3c0
8003224: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003226: 2302 movs r3, #2
8003228: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800322a: 2302 movs r3, #2
800322c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800322e: f107 0310 add.w r3, r7, #16
8003232: 4619 mov r1, r3
8003234: 4806 ldr r0, [pc, #24] @ (8003250 <HAL_TIM_MspPostInit+0xa4>)
8003236: f001 fa2d bl 8004694 <HAL_GPIO_Init>
}
800323a: bf00 nop
800323c: 3720 adds r7, #32
800323e: 46bd mov sp, r7
8003240: bd80 pop {r7, pc}
8003242: bf00 nop
8003244: 40021000 .word 0x40021000
8003248: 40010800 .word 0x40010800
800324c: 40000800 .word 0x40000800
8003250: 40010c00 .word 0x40010c00
08003254 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8003254: b580 push {r7, lr}
8003256: b088 sub sp, #32
8003258: af00 add r7, sp, #0
800325a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800325c: f107 0310 add.w r3, r7, #16
8003260: 2200 movs r2, #0
8003262: 601a str r2, [r3, #0]
8003264: 605a str r2, [r3, #4]
8003266: 609a str r2, [r3, #8]
8003268: 60da str r2, [r3, #12]
if(huart->Instance==USART1)
800326a: 687b ldr r3, [r7, #4]
800326c: 681b ldr r3, [r3, #0]
800326e: 4a1c ldr r2, [pc, #112] @ (80032e0 <HAL_UART_MspInit+0x8c>)
8003270: 4293 cmp r3, r2
8003272: d131 bne.n 80032d8 <HAL_UART_MspInit+0x84>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8003274: 4b1b ldr r3, [pc, #108] @ (80032e4 <HAL_UART_MspInit+0x90>)
8003276: 699b ldr r3, [r3, #24]
8003278: 4a1a ldr r2, [pc, #104] @ (80032e4 <HAL_UART_MspInit+0x90>)
800327a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
800327e: 6193 str r3, [r2, #24]
8003280: 4b18 ldr r3, [pc, #96] @ (80032e4 <HAL_UART_MspInit+0x90>)
8003282: 699b ldr r3, [r3, #24]
8003284: f403 4380 and.w r3, r3, #16384 @ 0x4000
8003288: 60fb str r3, [r7, #12]
800328a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800328c: 4b15 ldr r3, [pc, #84] @ (80032e4 <HAL_UART_MspInit+0x90>)
800328e: 699b ldr r3, [r3, #24]
8003290: 4a14 ldr r2, [pc, #80] @ (80032e4 <HAL_UART_MspInit+0x90>)
8003292: f043 0304 orr.w r3, r3, #4
8003296: 6193 str r3, [r2, #24]
8003298: 4b12 ldr r3, [pc, #72] @ (80032e4 <HAL_UART_MspInit+0x90>)
800329a: 699b ldr r3, [r3, #24]
800329c: f003 0304 and.w r3, r3, #4
80032a0: 60bb str r3, [r7, #8]
80032a2: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
80032a4: f44f 7300 mov.w r3, #512 @ 0x200
80032a8: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80032aa: 2302 movs r3, #2
80032ac: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80032ae: 2303 movs r3, #3
80032b0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80032b2: f107 0310 add.w r3, r7, #16
80032b6: 4619 mov r1, r3
80032b8: 480b ldr r0, [pc, #44] @ (80032e8 <HAL_UART_MspInit+0x94>)
80032ba: f001 f9eb bl 8004694 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_10;
80032be: f44f 6380 mov.w r3, #1024 @ 0x400
80032c2: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80032c4: 2300 movs r3, #0
80032c6: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80032c8: 2300 movs r3, #0
80032ca: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80032cc: f107 0310 add.w r3, r7, #16
80032d0: 4619 mov r1, r3
80032d2: 4805 ldr r0, [pc, #20] @ (80032e8 <HAL_UART_MspInit+0x94>)
80032d4: f001 f9de bl 8004694 <HAL_GPIO_Init>
/* USER CODE END USART1_MspInit 1 */
}
}
80032d8: bf00 nop
80032da: 3720 adds r7, #32
80032dc: 46bd mov sp, r7
80032de: bd80 pop {r7, pc}
80032e0: 40013800 .word 0x40013800
80032e4: 40021000 .word 0x40021000
80032e8: 40010800 .word 0x40010800
080032ec <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80032ec: b480 push {r7}
80032ee: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80032f0: bf00 nop
80032f2: e7fd b.n 80032f0 <NMI_Handler+0x4>
080032f4 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80032f4: b480 push {r7}
80032f6: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80032f8: bf00 nop
80032fa: e7fd b.n 80032f8 <HardFault_Handler+0x4>
080032fc <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80032fc: b480 push {r7}
80032fe: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8003300: bf00 nop
8003302: e7fd b.n 8003300 <MemManage_Handler+0x4>
08003304 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8003304: b480 push {r7}
8003306: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8003308: bf00 nop
800330a: e7fd b.n 8003308 <BusFault_Handler+0x4>
0800330c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
800330c: b480 push {r7}
800330e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8003310: bf00 nop
8003312: e7fd b.n 8003310 <UsageFault_Handler+0x4>
08003314 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8003314: b480 push {r7}
8003316: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8003318: bf00 nop
800331a: 46bd mov sp, r7
800331c: bc80 pop {r7}
800331e: 4770 bx lr
08003320 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8003320: b480 push {r7}
8003322: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8003324: bf00 nop
8003326: 46bd mov sp, r7
8003328: bc80 pop {r7}
800332a: 4770 bx lr
0800332c <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800332c: b480 push {r7}
800332e: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8003330: bf00 nop
8003332: 46bd mov sp, r7
8003334: bc80 pop {r7}
8003336: 4770 bx lr
08003338 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8003338: b580 push {r7, lr}
800333a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800333c: f000 f8c0 bl 80034c0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
HAL_SYSTICK_IRQHandler();
8003340: f000 fdb3 bl 8003eaa <HAL_SYSTICK_IRQHandler>
/* USER CODE END SysTick_IRQn 1 */
}
8003344: bf00 nop
8003346: bd80 pop {r7, pc}
08003348 <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
8003348: b580 push {r7, lr}
800334a: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc1);
800334c: 4802 ldr r0, [pc, #8] @ (8003358 <DMA1_Channel1_IRQHandler+0x10>)
800334e: f000 fe6d bl 800402c <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
8003352: bf00 nop
8003354: bd80 pop {r7, pc}
8003356: bf00 nop
8003358: 200002c4 .word 0x200002c4
0800335c <USB_LP_CAN1_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN RX0 interrupts.
*/
void USB_LP_CAN1_RX0_IRQHandler(void)
{
800335c: b580 push {r7, lr}
800335e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_FS);
8003360: 4802 ldr r0, [pc, #8] @ (800336c <USB_LP_CAN1_RX0_IRQHandler+0x10>)
8003362: f001 fc7f bl 8004c64 <HAL_PCD_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
}
8003366: bf00 nop
8003368: bd80 pop {r7, pc}
800336a: bf00 nop
800336c: 20001224 .word 0x20001224
08003370 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8003370: b580 push {r7, lr}
8003372: b086 sub sp, #24
8003374: af00 add r7, sp, #0
8003376: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8003378: 4a14 ldr r2, [pc, #80] @ (80033cc <_sbrk+0x5c>)
800337a: 4b15 ldr r3, [pc, #84] @ (80033d0 <_sbrk+0x60>)
800337c: 1ad3 subs r3, r2, r3
800337e: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8003380: 697b ldr r3, [r7, #20]
8003382: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8003384: 4b13 ldr r3, [pc, #76] @ (80033d4 <_sbrk+0x64>)
8003386: 681b ldr r3, [r3, #0]
8003388: 2b00 cmp r3, #0
800338a: d102 bne.n 8003392 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
800338c: 4b11 ldr r3, [pc, #68] @ (80033d4 <_sbrk+0x64>)
800338e: 4a12 ldr r2, [pc, #72] @ (80033d8 <_sbrk+0x68>)
8003390: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8003392: 4b10 ldr r3, [pc, #64] @ (80033d4 <_sbrk+0x64>)
8003394: 681a ldr r2, [r3, #0]
8003396: 687b ldr r3, [r7, #4]
8003398: 4413 add r3, r2
800339a: 693a ldr r2, [r7, #16]
800339c: 429a cmp r2, r3
800339e: d207 bcs.n 80033b0 <_sbrk+0x40>
{
errno = ENOMEM;
80033a0: f009 f8fe bl 800c5a0 <__errno>
80033a4: 4603 mov r3, r0
80033a6: 220c movs r2, #12
80033a8: 601a str r2, [r3, #0]
return (void *)-1;
80033aa: f04f 33ff mov.w r3, #4294967295
80033ae: e009 b.n 80033c4 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
80033b0: 4b08 ldr r3, [pc, #32] @ (80033d4 <_sbrk+0x64>)
80033b2: 681b ldr r3, [r3, #0]
80033b4: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80033b6: 4b07 ldr r3, [pc, #28] @ (80033d4 <_sbrk+0x64>)
80033b8: 681a ldr r2, [r3, #0]
80033ba: 687b ldr r3, [r7, #4]
80033bc: 4413 add r3, r2
80033be: 4a05 ldr r2, [pc, #20] @ (80033d4 <_sbrk+0x64>)
80033c0: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80033c2: 68fb ldr r3, [r7, #12]
}
80033c4: 4618 mov r0, r3
80033c6: 3718 adds r7, #24
80033c8: 46bd mov sp, r7
80033ca: bd80 pop {r7, pc}
80033cc: 20005000 .word 0x20005000
80033d0: 00000400 .word 0x00000400
80033d4: 20000430 .word 0x20000430
80033d8: 20001868 .word 0x20001868
080033dc <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80033dc: b480 push {r7}
80033de: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80033e0: bf00 nop
80033e2: 46bd mov sp, r7
80033e4: bc80 pop {r7}
80033e6: 4770 bx lr
080033e8 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80033e8: f7ff fff8 bl 80033dc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80033ec: 480b ldr r0, [pc, #44] @ (800341c <LoopFillZerobss+0xe>)
ldr r1, =_edata
80033ee: 490c ldr r1, [pc, #48] @ (8003420 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
80033f0: 4a0c ldr r2, [pc, #48] @ (8003424 <LoopFillZerobss+0x16>)
movs r3, #0
80033f2: 2300 movs r3, #0
b LoopCopyDataInit
80033f4: e002 b.n 80033fc <LoopCopyDataInit>
080033f6 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80033f6: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80033f8: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80033fa: 3304 adds r3, #4
080033fc <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80033fc: 18c4 adds r4, r0, r3
cmp r4, r1
80033fe: 428c cmp r4, r1
bcc CopyDataInit
8003400: d3f9 bcc.n 80033f6 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8003402: 4a09 ldr r2, [pc, #36] @ (8003428 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8003404: 4c09 ldr r4, [pc, #36] @ (800342c <LoopFillZerobss+0x1e>)
movs r3, #0
8003406: 2300 movs r3, #0
b LoopFillZerobss
8003408: e001 b.n 800340e <LoopFillZerobss>
0800340a <FillZerobss>:
FillZerobss:
str r3, [r2]
800340a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800340c: 3204 adds r2, #4
0800340e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800340e: 42a2 cmp r2, r4
bcc FillZerobss
8003410: d3fb bcc.n 800340a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8003412: f009 f8cb bl 800c5ac <__libc_init_array>
/* Call the application's entry point.*/
bl main
8003416: f7fe fe4f bl 80020b8 <main>
bx lr
800341a: 4770 bx lr
ldr r0, =_sdata
800341c: 20000000 .word 0x20000000
ldr r1, =_edata
8003420: 200001d4 .word 0x200001d4
ldr r2, =_sidata
8003424: 0800d1e0 .word 0x0800d1e0
ldr r2, =_sbss
8003428: 200001d8 .word 0x200001d8
ldr r4, =_ebss
800342c: 20001864 .word 0x20001864
08003430 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8003430: e7fe b.n 8003430 <ADC1_2_IRQHandler>
...
08003434 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8003434: b580 push {r7, lr}
8003436: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8003438: 4b08 ldr r3, [pc, #32] @ (800345c <HAL_Init+0x28>)
800343a: 681b ldr r3, [r3, #0]
800343c: 4a07 ldr r2, [pc, #28] @ (800345c <HAL_Init+0x28>)
800343e: f043 0310 orr.w r3, r3, #16
8003442: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8003444: 2003 movs r0, #3
8003446: f000 fcef bl 8003e28 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
800344a: 200f movs r0, #15
800344c: f000 f808 bl 8003460 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8003450: f7ff fdca bl 8002fe8 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8003454: 2300 movs r3, #0
}
8003456: 4618 mov r0, r3
8003458: bd80 pop {r7, pc}
800345a: bf00 nop
800345c: 40022000 .word 0x40022000
08003460 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8003460: b580 push {r7, lr}
8003462: b082 sub sp, #8
8003464: af00 add r7, sp, #0
8003466: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8003468: 4b12 ldr r3, [pc, #72] @ (80034b4 <HAL_InitTick+0x54>)
800346a: 681a ldr r2, [r3, #0]
800346c: 4b12 ldr r3, [pc, #72] @ (80034b8 <HAL_InitTick+0x58>)
800346e: 781b ldrb r3, [r3, #0]
8003470: 4619 mov r1, r3
8003472: f44f 737a mov.w r3, #1000 @ 0x3e8
8003476: fbb3 f3f1 udiv r3, r3, r1
800347a: fbb2 f3f3 udiv r3, r2, r3
800347e: 4618 mov r0, r3
8003480: f000 fd07 bl 8003e92 <HAL_SYSTICK_Config>
8003484: 4603 mov r3, r0
8003486: 2b00 cmp r3, #0
8003488: d001 beq.n 800348e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800348a: 2301 movs r3, #1
800348c: e00e b.n 80034ac <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800348e: 687b ldr r3, [r7, #4]
8003490: 2b0f cmp r3, #15
8003492: d80a bhi.n 80034aa <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8003494: 2200 movs r2, #0
8003496: 6879 ldr r1, [r7, #4]
8003498: f04f 30ff mov.w r0, #4294967295
800349c: f000 fccf bl 8003e3e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80034a0: 4a06 ldr r2, [pc, #24] @ (80034bc <HAL_InitTick+0x5c>)
80034a2: 687b ldr r3, [r7, #4]
80034a4: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80034a6: 2300 movs r3, #0
80034a8: e000 b.n 80034ac <HAL_InitTick+0x4c>
return HAL_ERROR;
80034aa: 2301 movs r3, #1
}
80034ac: 4618 mov r0, r3
80034ae: 3708 adds r7, #8
80034b0: 46bd mov sp, r7
80034b2: bd80 pop {r7, pc}
80034b4: 20000008 .word 0x20000008
80034b8: 20000010 .word 0x20000010
80034bc: 2000000c .word 0x2000000c
080034c0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80034c0: b480 push {r7}
80034c2: af00 add r7, sp, #0
uwTick += uwTickFreq;
80034c4: 4b05 ldr r3, [pc, #20] @ (80034dc <HAL_IncTick+0x1c>)
80034c6: 781b ldrb r3, [r3, #0]
80034c8: 461a mov r2, r3
80034ca: 4b05 ldr r3, [pc, #20] @ (80034e0 <HAL_IncTick+0x20>)
80034cc: 681b ldr r3, [r3, #0]
80034ce: 4413 add r3, r2
80034d0: 4a03 ldr r2, [pc, #12] @ (80034e0 <HAL_IncTick+0x20>)
80034d2: 6013 str r3, [r2, #0]
}
80034d4: bf00 nop
80034d6: 46bd mov sp, r7
80034d8: bc80 pop {r7}
80034da: 4770 bx lr
80034dc: 20000010 .word 0x20000010
80034e0: 20000434 .word 0x20000434
080034e4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80034e4: b480 push {r7}
80034e6: af00 add r7, sp, #0
return uwTick;
80034e8: 4b02 ldr r3, [pc, #8] @ (80034f4 <HAL_GetTick+0x10>)
80034ea: 681b ldr r3, [r3, #0]
}
80034ec: 4618 mov r0, r3
80034ee: 46bd mov sp, r7
80034f0: bc80 pop {r7}
80034f2: 4770 bx lr
80034f4: 20000434 .word 0x20000434
080034f8 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80034f8: b580 push {r7, lr}
80034fa: b086 sub sp, #24
80034fc: af00 add r7, sp, #0
80034fe: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8003500: 2300 movs r3, #0
8003502: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
8003504: 2300 movs r3, #0
8003506: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
8003508: 2300 movs r3, #0
800350a: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
800350c: 2300 movs r3, #0
800350e: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
8003510: 687b ldr r3, [r7, #4]
8003512: 2b00 cmp r3, #0
8003514: d101 bne.n 800351a <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
8003516: 2301 movs r3, #1
8003518: e0be b.n 8003698 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
800351a: 687b ldr r3, [r7, #4]
800351c: 689b ldr r3, [r3, #8]
800351e: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8003520: 687b ldr r3, [r7, #4]
8003522: 6a9b ldr r3, [r3, #40] @ 0x28
8003524: 2b00 cmp r3, #0
8003526: d109 bne.n 800353c <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8003528: 687b ldr r3, [r7, #4]
800352a: 2200 movs r2, #0
800352c: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
800352e: 687b ldr r3, [r7, #4]
8003530: 2200 movs r2, #0
8003532: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8003536: 6878 ldr r0, [r7, #4]
8003538: f7ff fd88 bl 800304c <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
800353c: 6878 ldr r0, [r7, #4]
800353e: f000 faff bl 8003b40 <ADC_ConversionStop_Disable>
8003542: 4603 mov r3, r0
8003544: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8003546: 687b ldr r3, [r7, #4]
8003548: 6a9b ldr r3, [r3, #40] @ 0x28
800354a: f003 0310 and.w r3, r3, #16
800354e: 2b00 cmp r3, #0
8003550: f040 8099 bne.w 8003686 <HAL_ADC_Init+0x18e>
8003554: 7dfb ldrb r3, [r7, #23]
8003556: 2b00 cmp r3, #0
8003558: f040 8095 bne.w 8003686 <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800355c: 687b ldr r3, [r7, #4]
800355e: 6a9b ldr r3, [r3, #40] @ 0x28
8003560: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8003564: f023 0302 bic.w r3, r3, #2
8003568: f043 0202 orr.w r2, r3, #2
800356c: 687b ldr r3, [r7, #4]
800356e: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8003570: 687b ldr r3, [r7, #4]
8003572: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8003574: 687b ldr r3, [r7, #4]
8003576: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8003578: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
800357a: 687b ldr r3, [r7, #4]
800357c: 7b1b ldrb r3, [r3, #12]
800357e: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8003580: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
8003582: 68ba ldr r2, [r7, #8]
8003584: 4313 orrs r3, r2
8003586: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8003588: 687b ldr r3, [r7, #4]
800358a: 689b ldr r3, [r3, #8]
800358c: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003590: d003 beq.n 800359a <HAL_ADC_Init+0xa2>
8003592: 687b ldr r3, [r7, #4]
8003594: 689b ldr r3, [r3, #8]
8003596: 2b01 cmp r3, #1
8003598: d102 bne.n 80035a0 <HAL_ADC_Init+0xa8>
800359a: f44f 7380 mov.w r3, #256 @ 0x100
800359e: e000 b.n 80035a2 <HAL_ADC_Init+0xaa>
80035a0: 2300 movs r3, #0
80035a2: 693a ldr r2, [r7, #16]
80035a4: 4313 orrs r3, r2
80035a6: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80035a8: 687b ldr r3, [r7, #4]
80035aa: 7d1b ldrb r3, [r3, #20]
80035ac: 2b01 cmp r3, #1
80035ae: d119 bne.n 80035e4 <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
80035b0: 687b ldr r3, [r7, #4]
80035b2: 7b1b ldrb r3, [r3, #12]
80035b4: 2b00 cmp r3, #0
80035b6: d109 bne.n 80035cc <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
80035b8: 687b ldr r3, [r7, #4]
80035ba: 699b ldr r3, [r3, #24]
80035bc: 3b01 subs r3, #1
80035be: 035a lsls r2, r3, #13
80035c0: 693b ldr r3, [r7, #16]
80035c2: 4313 orrs r3, r2
80035c4: f443 6300 orr.w r3, r3, #2048 @ 0x800
80035c8: 613b str r3, [r7, #16]
80035ca: e00b b.n 80035e4 <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80035cc: 687b ldr r3, [r7, #4]
80035ce: 6a9b ldr r3, [r3, #40] @ 0x28
80035d0: f043 0220 orr.w r2, r3, #32
80035d4: 687b ldr r3, [r7, #4]
80035d6: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80035d8: 687b ldr r3, [r7, #4]
80035da: 6adb ldr r3, [r3, #44] @ 0x2c
80035dc: f043 0201 orr.w r2, r3, #1
80035e0: 687b ldr r3, [r7, #4]
80035e2: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
80035e4: 687b ldr r3, [r7, #4]
80035e6: 681b ldr r3, [r3, #0]
80035e8: 685b ldr r3, [r3, #4]
80035ea: f423 4169 bic.w r1, r3, #59648 @ 0xe900
80035ee: 687b ldr r3, [r7, #4]
80035f0: 681b ldr r3, [r3, #0]
80035f2: 693a ldr r2, [r7, #16]
80035f4: 430a orrs r2, r1
80035f6: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
80035f8: 687b ldr r3, [r7, #4]
80035fa: 681b ldr r3, [r3, #0]
80035fc: 689a ldr r2, [r3, #8]
80035fe: 4b28 ldr r3, [pc, #160] @ (80036a0 <HAL_ADC_Init+0x1a8>)
8003600: 4013 ands r3, r2
8003602: 687a ldr r2, [r7, #4]
8003604: 6812 ldr r2, [r2, #0]
8003606: 68b9 ldr r1, [r7, #8]
8003608: 430b orrs r3, r1
800360a: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
800360c: 687b ldr r3, [r7, #4]
800360e: 689b ldr r3, [r3, #8]
8003610: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003614: d003 beq.n 800361e <HAL_ADC_Init+0x126>
8003616: 687b ldr r3, [r7, #4]
8003618: 689b ldr r3, [r3, #8]
800361a: 2b01 cmp r3, #1
800361c: d104 bne.n 8003628 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
800361e: 687b ldr r3, [r7, #4]
8003620: 691b ldr r3, [r3, #16]
8003622: 3b01 subs r3, #1
8003624: 051b lsls r3, r3, #20
8003626: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
8003628: 687b ldr r3, [r7, #4]
800362a: 681b ldr r3, [r3, #0]
800362c: 6adb ldr r3, [r3, #44] @ 0x2c
800362e: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
8003632: 687b ldr r3, [r7, #4]
8003634: 681b ldr r3, [r3, #0]
8003636: 68fa ldr r2, [r7, #12]
8003638: 430a orrs r2, r1
800363a: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800363c: 687b ldr r3, [r7, #4]
800363e: 681b ldr r3, [r3, #0]
8003640: 689a ldr r2, [r3, #8]
8003642: 4b18 ldr r3, [pc, #96] @ (80036a4 <HAL_ADC_Init+0x1ac>)
8003644: 4013 ands r3, r2
8003646: 68ba ldr r2, [r7, #8]
8003648: 429a cmp r2, r3
800364a: d10b bne.n 8003664 <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
800364c: 687b ldr r3, [r7, #4]
800364e: 2200 movs r2, #0
8003650: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8003652: 687b ldr r3, [r7, #4]
8003654: 6a9b ldr r3, [r3, #40] @ 0x28
8003656: f023 0303 bic.w r3, r3, #3
800365a: f043 0201 orr.w r2, r3, #1
800365e: 687b ldr r3, [r7, #4]
8003660: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8003662: e018 b.n 8003696 <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8003664: 687b ldr r3, [r7, #4]
8003666: 6a9b ldr r3, [r3, #40] @ 0x28
8003668: f023 0312 bic.w r3, r3, #18
800366c: f043 0210 orr.w r2, r3, #16
8003670: 687b ldr r3, [r7, #4]
8003672: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003674: 687b ldr r3, [r7, #4]
8003676: 6adb ldr r3, [r3, #44] @ 0x2c
8003678: f043 0201 orr.w r2, r3, #1
800367c: 687b ldr r3, [r7, #4]
800367e: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8003680: 2301 movs r3, #1
8003682: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8003684: e007 b.n 8003696 <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003686: 687b ldr r3, [r7, #4]
8003688: 6a9b ldr r3, [r3, #40] @ 0x28
800368a: f043 0210 orr.w r2, r3, #16
800368e: 687b ldr r3, [r7, #4]
8003690: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8003692: 2301 movs r3, #1
8003694: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
8003696: 7dfb ldrb r3, [r7, #23]
}
8003698: 4618 mov r0, r3
800369a: 3718 adds r7, #24
800369c: 46bd mov sp, r7
800369e: bd80 pop {r7, pc}
80036a0: ffe1f7fd .word 0xffe1f7fd
80036a4: ff1f0efe .word 0xff1f0efe
080036a8 <HAL_ADC_Start_DMA>:
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
80036a8: b580 push {r7, lr}
80036aa: b086 sub sp, #24
80036ac: af00 add r7, sp, #0
80036ae: 60f8 str r0, [r7, #12]
80036b0: 60b9 str r1, [r7, #8]
80036b2: 607a str r2, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80036b4: 2300 movs r3, #0
80036b6: 75fb strb r3, [r7, #23]
assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
/* Verification if multimode is disabled (for devices with several ADC) */
/* If multimode is enabled, dedicated function multimode conversion */
/* start DMA must be used. */
if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
80036b8: 68fb ldr r3, [r7, #12]
80036ba: 681b ldr r3, [r3, #0]
80036bc: 4a64 ldr r2, [pc, #400] @ (8003850 <HAL_ADC_Start_DMA+0x1a8>)
80036be: 4293 cmp r3, r2
80036c0: d004 beq.n 80036cc <HAL_ADC_Start_DMA+0x24>
80036c2: 68fb ldr r3, [r7, #12]
80036c4: 681b ldr r3, [r3, #0]
80036c6: 4a63 ldr r2, [pc, #396] @ (8003854 <HAL_ADC_Start_DMA+0x1ac>)
80036c8: 4293 cmp r3, r2
80036ca: d106 bne.n 80036da <HAL_ADC_Start_DMA+0x32>
80036cc: 4b60 ldr r3, [pc, #384] @ (8003850 <HAL_ADC_Start_DMA+0x1a8>)
80036ce: 685b ldr r3, [r3, #4]
80036d0: f403 2370 and.w r3, r3, #983040 @ 0xf0000
80036d4: 2b00 cmp r3, #0
80036d6: f040 80b3 bne.w 8003840 <HAL_ADC_Start_DMA+0x198>
{
/* Process locked */
__HAL_LOCK(hadc);
80036da: 68fb ldr r3, [r7, #12]
80036dc: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80036e0: 2b01 cmp r3, #1
80036e2: d101 bne.n 80036e8 <HAL_ADC_Start_DMA+0x40>
80036e4: 2302 movs r3, #2
80036e6: e0ae b.n 8003846 <HAL_ADC_Start_DMA+0x19e>
80036e8: 68fb ldr r3, [r7, #12]
80036ea: 2201 movs r2, #1
80036ec: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
80036f0: 68f8 ldr r0, [r7, #12]
80036f2: f000 f9cb bl 8003a8c <ADC_Enable>
80036f6: 4603 mov r3, r0
80036f8: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
80036fa: 7dfb ldrb r3, [r7, #23]
80036fc: 2b00 cmp r3, #0
80036fe: f040 809a bne.w 8003836 <HAL_ADC_Start_DMA+0x18e>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
8003702: 68fb ldr r3, [r7, #12]
8003704: 6a9b ldr r3, [r3, #40] @ 0x28
8003706: f423 6370 bic.w r3, r3, #3840 @ 0xf00
800370a: f023 0301 bic.w r3, r3, #1
800370e: f443 7280 orr.w r2, r3, #256 @ 0x100
8003712: 68fb ldr r3, [r7, #12]
8003714: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_REG_BUSY);
/* Set group injected state (from auto-injection) and multimode state */
/* for all cases of multimode: independent mode, multimode ADC master */
/* or multimode ADC slave (for devices with several ADCs): */
if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
8003716: 68fb ldr r3, [r7, #12]
8003718: 681b ldr r3, [r3, #0]
800371a: 4a4e ldr r2, [pc, #312] @ (8003854 <HAL_ADC_Start_DMA+0x1ac>)
800371c: 4293 cmp r3, r2
800371e: d105 bne.n 800372c <HAL_ADC_Start_DMA+0x84>
8003720: 4b4b ldr r3, [pc, #300] @ (8003850 <HAL_ADC_Start_DMA+0x1a8>)
8003722: 685b ldr r3, [r3, #4]
8003724: f403 2370 and.w r3, r3, #983040 @ 0xf0000
8003728: 2b00 cmp r3, #0
800372a: d115 bne.n 8003758 <HAL_ADC_Start_DMA+0xb0>
{
/* Set ADC state (ADC independent or master) */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
800372c: 68fb ldr r3, [r7, #12]
800372e: 6a9b ldr r3, [r3, #40] @ 0x28
8003730: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8003734: 68fb ldr r3, [r7, #12]
8003736: 629a str r2, [r3, #40] @ 0x28
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8003738: 68fb ldr r3, [r7, #12]
800373a: 681b ldr r3, [r3, #0]
800373c: 685b ldr r3, [r3, #4]
800373e: f403 6380 and.w r3, r3, #1024 @ 0x400
8003742: 2b00 cmp r3, #0
8003744: d026 beq.n 8003794 <HAL_ADC_Start_DMA+0xec>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8003746: 68fb ldr r3, [r7, #12]
8003748: 6a9b ldr r3, [r3, #40] @ 0x28
800374a: f423 5340 bic.w r3, r3, #12288 @ 0x3000
800374e: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8003752: 68fb ldr r3, [r7, #12]
8003754: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8003756: e01d b.n 8003794 <HAL_ADC_Start_DMA+0xec>
}
}
else
{
/* Set ADC state (ADC slave) */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8003758: 68fb ldr r3, [r7, #12]
800375a: 6a9b ldr r3, [r3, #40] @ 0x28
800375c: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
8003760: 68fb ldr r3, [r7, #12]
8003762: 629a str r2, [r3, #40] @ 0x28
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
8003764: 68fb ldr r3, [r7, #12]
8003766: 681b ldr r3, [r3, #0]
8003768: 4a39 ldr r2, [pc, #228] @ (8003850 <HAL_ADC_Start_DMA+0x1a8>)
800376a: 4293 cmp r3, r2
800376c: d004 beq.n 8003778 <HAL_ADC_Start_DMA+0xd0>
800376e: 68fb ldr r3, [r7, #12]
8003770: 681b ldr r3, [r3, #0]
8003772: 4a38 ldr r2, [pc, #224] @ (8003854 <HAL_ADC_Start_DMA+0x1ac>)
8003774: 4293 cmp r3, r2
8003776: d10d bne.n 8003794 <HAL_ADC_Start_DMA+0xec>
8003778: 4b35 ldr r3, [pc, #212] @ (8003850 <HAL_ADC_Start_DMA+0x1a8>)
800377a: 685b ldr r3, [r3, #4]
800377c: f403 6380 and.w r3, r3, #1024 @ 0x400
8003780: 2b00 cmp r3, #0
8003782: d007 beq.n 8003794 <HAL_ADC_Start_DMA+0xec>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8003784: 68fb ldr r3, [r7, #12]
8003786: 6a9b ldr r3, [r3, #40] @ 0x28
8003788: f423 5340 bic.w r3, r3, #12288 @ 0x3000
800378c: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8003790: 68fb ldr r3, [r7, #12]
8003792: 629a str r2, [r3, #40] @ 0x28
}
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8003794: 68fb ldr r3, [r7, #12]
8003796: 6a9b ldr r3, [r3, #40] @ 0x28
8003798: f403 5380 and.w r3, r3, #4096 @ 0x1000
800379c: 2b00 cmp r3, #0
800379e: d006 beq.n 80037ae <HAL_ADC_Start_DMA+0x106>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
80037a0: 68fb ldr r3, [r7, #12]
80037a2: 6adb ldr r3, [r3, #44] @ 0x2c
80037a4: f023 0206 bic.w r2, r3, #6
80037a8: 68fb ldr r3, [r7, #12]
80037aa: 62da str r2, [r3, #44] @ 0x2c
80037ac: e002 b.n 80037b4 <HAL_ADC_Start_DMA+0x10c>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80037ae: 68fb ldr r3, [r7, #12]
80037b0: 2200 movs r2, #0
80037b2: 62da str r2, [r3, #44] @ 0x2c
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80037b4: 68fb ldr r3, [r7, #12]
80037b6: 2200 movs r2, #0
80037b8: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
80037bc: 68fb ldr r3, [r7, #12]
80037be: 6a1b ldr r3, [r3, #32]
80037c0: 4a25 ldr r2, [pc, #148] @ (8003858 <HAL_ADC_Start_DMA+0x1b0>)
80037c2: 629a str r2, [r3, #40] @ 0x28
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
80037c4: 68fb ldr r3, [r7, #12]
80037c6: 6a1b ldr r3, [r3, #32]
80037c8: 4a24 ldr r2, [pc, #144] @ (800385c <HAL_ADC_Start_DMA+0x1b4>)
80037ca: 62da str r2, [r3, #44] @ 0x2c
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
80037cc: 68fb ldr r3, [r7, #12]
80037ce: 6a1b ldr r3, [r3, #32]
80037d0: 4a23 ldr r2, [pc, #140] @ (8003860 <HAL_ADC_Start_DMA+0x1b8>)
80037d2: 631a str r2, [r3, #48] @ 0x30
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
80037d4: 68fb ldr r3, [r7, #12]
80037d6: 681b ldr r3, [r3, #0]
80037d8: f06f 0202 mvn.w r2, #2
80037dc: 601a str r2, [r3, #0]
/* Enable ADC DMA mode */
SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
80037de: 68fb ldr r3, [r7, #12]
80037e0: 681b ldr r3, [r3, #0]
80037e2: 689a ldr r2, [r3, #8]
80037e4: 68fb ldr r3, [r7, #12]
80037e6: 681b ldr r3, [r3, #0]
80037e8: f442 7280 orr.w r2, r2, #256 @ 0x100
80037ec: 609a str r2, [r3, #8]
/* Start the DMA channel */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
80037ee: 68fb ldr r3, [r7, #12]
80037f0: 6a18 ldr r0, [r3, #32]
80037f2: 68fb ldr r3, [r7, #12]
80037f4: 681b ldr r3, [r3, #0]
80037f6: 334c adds r3, #76 @ 0x4c
80037f8: 4619 mov r1, r3
80037fa: 68ba ldr r2, [r7, #8]
80037fc: 687b ldr r3, [r7, #4]
80037fe: f000 fbb5 bl 8003f6c <HAL_DMA_Start_IT>
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
8003802: 68fb ldr r3, [r7, #12]
8003804: 681b ldr r3, [r3, #0]
8003806: 689b ldr r3, [r3, #8]
8003808: f403 2360 and.w r3, r3, #917504 @ 0xe0000
800380c: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000
8003810: d108 bne.n 8003824 <HAL_ADC_Start_DMA+0x17c>
{
/* Start ADC conversion on regular group with SW start */
SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
8003812: 68fb ldr r3, [r7, #12]
8003814: 681b ldr r3, [r3, #0]
8003816: 689a ldr r2, [r3, #8]
8003818: 68fb ldr r3, [r7, #12]
800381a: 681b ldr r3, [r3, #0]
800381c: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000
8003820: 609a str r2, [r3, #8]
if (tmp_hal_status == HAL_OK)
8003822: e00f b.n 8003844 <HAL_ADC_Start_DMA+0x19c>
}
else
{
/* Start ADC conversion on regular group with external trigger */
SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
8003824: 68fb ldr r3, [r7, #12]
8003826: 681b ldr r3, [r3, #0]
8003828: 689a ldr r2, [r3, #8]
800382a: 68fb ldr r3, [r7, #12]
800382c: 681b ldr r3, [r3, #0]
800382e: f442 1280 orr.w r2, r2, #1048576 @ 0x100000
8003832: 609a str r2, [r3, #8]
if (tmp_hal_status == HAL_OK)
8003834: e006 b.n 8003844 <HAL_ADC_Start_DMA+0x19c>
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003836: 68fb ldr r3, [r7, #12]
8003838: 2200 movs r2, #0
800383a: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (tmp_hal_status == HAL_OK)
800383e: e001 b.n 8003844 <HAL_ADC_Start_DMA+0x19c>
}
}
else
{
tmp_hal_status = HAL_ERROR;
8003840: 2301 movs r3, #1
8003842: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
8003844: 7dfb ldrb r3, [r7, #23]
}
8003846: 4618 mov r0, r3
8003848: 3718 adds r7, #24
800384a: 46bd mov sp, r7
800384c: bd80 pop {r7, pc}
800384e: bf00 nop
8003850: 40012400 .word 0x40012400
8003854: 40012800 .word 0x40012800
8003858: 08003bc3 .word 0x08003bc3
800385c: 08003c3f .word 0x08003c3f
8003860: 08003c5b .word 0x08003c5b
08003864 <HAL_ADC_ConvCpltCallback>:
* @brief Conversion complete callback in non blocking mode
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
8003864: b480 push {r7}
8003866: b083 sub sp, #12
8003868: af00 add r7, sp, #0
800386a: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
800386c: bf00 nop
800386e: 370c adds r7, #12
8003870: 46bd mov sp, r7
8003872: bc80 pop {r7}
8003874: 4770 bx lr
08003876 <HAL_ADC_ConvHalfCpltCallback>:
* @brief Conversion DMA half-transfer callback in non blocking mode
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
8003876: b480 push {r7}
8003878: b083 sub sp, #12
800387a: af00 add r7, sp, #0
800387c: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
800387e: bf00 nop
8003880: 370c adds r7, #12
8003882: 46bd mov sp, r7
8003884: bc80 pop {r7}
8003886: 4770 bx lr
08003888 <HAL_ADC_ErrorCallback>:
* (ADC conversion with interruption or transfer by DMA)
* @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
8003888: b480 push {r7}
800388a: b083 sub sp, #12
800388c: af00 add r7, sp, #0
800388e: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
8003890: bf00 nop
8003892: 370c adds r7, #12
8003894: 46bd mov sp, r7
8003896: bc80 pop {r7}
8003898: 4770 bx lr
...
0800389c <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
800389c: b480 push {r7}
800389e: b085 sub sp, #20
80038a0: af00 add r7, sp, #0
80038a2: 6078 str r0, [r7, #4]
80038a4: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80038a6: 2300 movs r3, #0
80038a8: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
80038aa: 2300 movs r3, #0
80038ac: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
80038ae: 687b ldr r3, [r7, #4]
80038b0: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80038b4: 2b01 cmp r3, #1
80038b6: d101 bne.n 80038bc <HAL_ADC_ConfigChannel+0x20>
80038b8: 2302 movs r3, #2
80038ba: e0dc b.n 8003a76 <HAL_ADC_ConfigChannel+0x1da>
80038bc: 687b ldr r3, [r7, #4]
80038be: 2201 movs r2, #1
80038c0: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
80038c4: 683b ldr r3, [r7, #0]
80038c6: 685b ldr r3, [r3, #4]
80038c8: 2b06 cmp r3, #6
80038ca: d81c bhi.n 8003906 <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
80038cc: 687b ldr r3, [r7, #4]
80038ce: 681b ldr r3, [r3, #0]
80038d0: 6b59 ldr r1, [r3, #52] @ 0x34
80038d2: 683b ldr r3, [r7, #0]
80038d4: 685a ldr r2, [r3, #4]
80038d6: 4613 mov r3, r2
80038d8: 009b lsls r3, r3, #2
80038da: 4413 add r3, r2
80038dc: 3b05 subs r3, #5
80038de: 221f movs r2, #31
80038e0: fa02 f303 lsl.w r3, r2, r3
80038e4: 43db mvns r3, r3
80038e6: 4019 ands r1, r3
80038e8: 683b ldr r3, [r7, #0]
80038ea: 6818 ldr r0, [r3, #0]
80038ec: 683b ldr r3, [r7, #0]
80038ee: 685a ldr r2, [r3, #4]
80038f0: 4613 mov r3, r2
80038f2: 009b lsls r3, r3, #2
80038f4: 4413 add r3, r2
80038f6: 3b05 subs r3, #5
80038f8: fa00 f203 lsl.w r2, r0, r3
80038fc: 687b ldr r3, [r7, #4]
80038fe: 681b ldr r3, [r3, #0]
8003900: 430a orrs r2, r1
8003902: 635a str r2, [r3, #52] @ 0x34
8003904: e03c b.n 8003980 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
8003906: 683b ldr r3, [r7, #0]
8003908: 685b ldr r3, [r3, #4]
800390a: 2b0c cmp r3, #12
800390c: d81c bhi.n 8003948 <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
800390e: 687b ldr r3, [r7, #4]
8003910: 681b ldr r3, [r3, #0]
8003912: 6b19 ldr r1, [r3, #48] @ 0x30
8003914: 683b ldr r3, [r7, #0]
8003916: 685a ldr r2, [r3, #4]
8003918: 4613 mov r3, r2
800391a: 009b lsls r3, r3, #2
800391c: 4413 add r3, r2
800391e: 3b23 subs r3, #35 @ 0x23
8003920: 221f movs r2, #31
8003922: fa02 f303 lsl.w r3, r2, r3
8003926: 43db mvns r3, r3
8003928: 4019 ands r1, r3
800392a: 683b ldr r3, [r7, #0]
800392c: 6818 ldr r0, [r3, #0]
800392e: 683b ldr r3, [r7, #0]
8003930: 685a ldr r2, [r3, #4]
8003932: 4613 mov r3, r2
8003934: 009b lsls r3, r3, #2
8003936: 4413 add r3, r2
8003938: 3b23 subs r3, #35 @ 0x23
800393a: fa00 f203 lsl.w r2, r0, r3
800393e: 687b ldr r3, [r7, #4]
8003940: 681b ldr r3, [r3, #0]
8003942: 430a orrs r2, r1
8003944: 631a str r2, [r3, #48] @ 0x30
8003946: e01b b.n 8003980 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
8003948: 687b ldr r3, [r7, #4]
800394a: 681b ldr r3, [r3, #0]
800394c: 6ad9 ldr r1, [r3, #44] @ 0x2c
800394e: 683b ldr r3, [r7, #0]
8003950: 685a ldr r2, [r3, #4]
8003952: 4613 mov r3, r2
8003954: 009b lsls r3, r3, #2
8003956: 4413 add r3, r2
8003958: 3b41 subs r3, #65 @ 0x41
800395a: 221f movs r2, #31
800395c: fa02 f303 lsl.w r3, r2, r3
8003960: 43db mvns r3, r3
8003962: 4019 ands r1, r3
8003964: 683b ldr r3, [r7, #0]
8003966: 6818 ldr r0, [r3, #0]
8003968: 683b ldr r3, [r7, #0]
800396a: 685a ldr r2, [r3, #4]
800396c: 4613 mov r3, r2
800396e: 009b lsls r3, r3, #2
8003970: 4413 add r3, r2
8003972: 3b41 subs r3, #65 @ 0x41
8003974: fa00 f203 lsl.w r2, r0, r3
8003978: 687b ldr r3, [r7, #4]
800397a: 681b ldr r3, [r3, #0]
800397c: 430a orrs r2, r1
800397e: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8003980: 683b ldr r3, [r7, #0]
8003982: 681b ldr r3, [r3, #0]
8003984: 2b09 cmp r3, #9
8003986: d91c bls.n 80039c2 <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
8003988: 687b ldr r3, [r7, #4]
800398a: 681b ldr r3, [r3, #0]
800398c: 68d9 ldr r1, [r3, #12]
800398e: 683b ldr r3, [r7, #0]
8003990: 681a ldr r2, [r3, #0]
8003992: 4613 mov r3, r2
8003994: 005b lsls r3, r3, #1
8003996: 4413 add r3, r2
8003998: 3b1e subs r3, #30
800399a: 2207 movs r2, #7
800399c: fa02 f303 lsl.w r3, r2, r3
80039a0: 43db mvns r3, r3
80039a2: 4019 ands r1, r3
80039a4: 683b ldr r3, [r7, #0]
80039a6: 6898 ldr r0, [r3, #8]
80039a8: 683b ldr r3, [r7, #0]
80039aa: 681a ldr r2, [r3, #0]
80039ac: 4613 mov r3, r2
80039ae: 005b lsls r3, r3, #1
80039b0: 4413 add r3, r2
80039b2: 3b1e subs r3, #30
80039b4: fa00 f203 lsl.w r2, r0, r3
80039b8: 687b ldr r3, [r7, #4]
80039ba: 681b ldr r3, [r3, #0]
80039bc: 430a orrs r2, r1
80039be: 60da str r2, [r3, #12]
80039c0: e019 b.n 80039f6 <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
80039c2: 687b ldr r3, [r7, #4]
80039c4: 681b ldr r3, [r3, #0]
80039c6: 6919 ldr r1, [r3, #16]
80039c8: 683b ldr r3, [r7, #0]
80039ca: 681a ldr r2, [r3, #0]
80039cc: 4613 mov r3, r2
80039ce: 005b lsls r3, r3, #1
80039d0: 4413 add r3, r2
80039d2: 2207 movs r2, #7
80039d4: fa02 f303 lsl.w r3, r2, r3
80039d8: 43db mvns r3, r3
80039da: 4019 ands r1, r3
80039dc: 683b ldr r3, [r7, #0]
80039de: 6898 ldr r0, [r3, #8]
80039e0: 683b ldr r3, [r7, #0]
80039e2: 681a ldr r2, [r3, #0]
80039e4: 4613 mov r3, r2
80039e6: 005b lsls r3, r3, #1
80039e8: 4413 add r3, r2
80039ea: fa00 f203 lsl.w r2, r0, r3
80039ee: 687b ldr r3, [r7, #4]
80039f0: 681b ldr r3, [r3, #0]
80039f2: 430a orrs r2, r1
80039f4: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80039f6: 683b ldr r3, [r7, #0]
80039f8: 681b ldr r3, [r3, #0]
80039fa: 2b10 cmp r3, #16
80039fc: d003 beq.n 8003a06 <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
80039fe: 683b ldr r3, [r7, #0]
8003a00: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
8003a02: 2b11 cmp r3, #17
8003a04: d132 bne.n 8003a6c <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
8003a06: 687b ldr r3, [r7, #4]
8003a08: 681b ldr r3, [r3, #0]
8003a0a: 4a1d ldr r2, [pc, #116] @ (8003a80 <HAL_ADC_ConfigChannel+0x1e4>)
8003a0c: 4293 cmp r3, r2
8003a0e: d125 bne.n 8003a5c <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
8003a10: 687b ldr r3, [r7, #4]
8003a12: 681b ldr r3, [r3, #0]
8003a14: 689b ldr r3, [r3, #8]
8003a16: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8003a1a: 2b00 cmp r3, #0
8003a1c: d126 bne.n 8003a6c <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
8003a1e: 687b ldr r3, [r7, #4]
8003a20: 681b ldr r3, [r3, #0]
8003a22: 689a ldr r2, [r3, #8]
8003a24: 687b ldr r3, [r7, #4]
8003a26: 681b ldr r3, [r3, #0]
8003a28: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8003a2c: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8003a2e: 683b ldr r3, [r7, #0]
8003a30: 681b ldr r3, [r3, #0]
8003a32: 2b10 cmp r3, #16
8003a34: d11a bne.n 8003a6c <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8003a36: 4b13 ldr r3, [pc, #76] @ (8003a84 <HAL_ADC_ConfigChannel+0x1e8>)
8003a38: 681b ldr r3, [r3, #0]
8003a3a: 4a13 ldr r2, [pc, #76] @ (8003a88 <HAL_ADC_ConfigChannel+0x1ec>)
8003a3c: fba2 2303 umull r2, r3, r2, r3
8003a40: 0c9a lsrs r2, r3, #18
8003a42: 4613 mov r3, r2
8003a44: 009b lsls r3, r3, #2
8003a46: 4413 add r3, r2
8003a48: 005b lsls r3, r3, #1
8003a4a: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003a4c: e002 b.n 8003a54 <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
8003a4e: 68bb ldr r3, [r7, #8]
8003a50: 3b01 subs r3, #1
8003a52: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003a54: 68bb ldr r3, [r7, #8]
8003a56: 2b00 cmp r3, #0
8003a58: d1f9 bne.n 8003a4e <HAL_ADC_ConfigChannel+0x1b2>
8003a5a: e007 b.n 8003a6c <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003a5c: 687b ldr r3, [r7, #4]
8003a5e: 6a9b ldr r3, [r3, #40] @ 0x28
8003a60: f043 0220 orr.w r2, r3, #32
8003a64: 687b ldr r3, [r7, #4]
8003a66: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
8003a68: 2301 movs r3, #1
8003a6a: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 2200 movs r2, #0
8003a70: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
8003a74: 7bfb ldrb r3, [r7, #15]
}
8003a76: 4618 mov r0, r3
8003a78: 3714 adds r7, #20
8003a7a: 46bd mov sp, r7
8003a7c: bc80 pop {r7}
8003a7e: 4770 bx lr
8003a80: 40012400 .word 0x40012400
8003a84: 20000008 .word 0x20000008
8003a88: 431bde83 .word 0x431bde83
08003a8c <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
8003a8c: b580 push {r7, lr}
8003a8e: b084 sub sp, #16
8003a90: af00 add r7, sp, #0
8003a92: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8003a94: 2300 movs r3, #0
8003a96: 60fb str r3, [r7, #12]
__IO uint32_t wait_loop_index = 0U;
8003a98: 2300 movs r3, #0
8003a9a: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (ADC_IS_ENABLE(hadc) == RESET)
8003a9c: 687b ldr r3, [r7, #4]
8003a9e: 681b ldr r3, [r3, #0]
8003aa0: 689b ldr r3, [r3, #8]
8003aa2: f003 0301 and.w r3, r3, #1
8003aa6: 2b01 cmp r3, #1
8003aa8: d040 beq.n 8003b2c <ADC_Enable+0xa0>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8003aaa: 687b ldr r3, [r7, #4]
8003aac: 681b ldr r3, [r3, #0]
8003aae: 689a ldr r2, [r3, #8]
8003ab0: 687b ldr r3, [r7, #4]
8003ab2: 681b ldr r3, [r3, #0]
8003ab4: f042 0201 orr.w r2, r2, #1
8003ab8: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
8003aba: 4b1f ldr r3, [pc, #124] @ (8003b38 <ADC_Enable+0xac>)
8003abc: 681b ldr r3, [r3, #0]
8003abe: 4a1f ldr r2, [pc, #124] @ (8003b3c <ADC_Enable+0xb0>)
8003ac0: fba2 2303 umull r2, r3, r2, r3
8003ac4: 0c9b lsrs r3, r3, #18
8003ac6: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003ac8: e002 b.n 8003ad0 <ADC_Enable+0x44>
{
wait_loop_index--;
8003aca: 68bb ldr r3, [r7, #8]
8003acc: 3b01 subs r3, #1
8003ace: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8003ad0: 68bb ldr r3, [r7, #8]
8003ad2: 2b00 cmp r3, #0
8003ad4: d1f9 bne.n 8003aca <ADC_Enable+0x3e>
}
/* Get tick count */
tickstart = HAL_GetTick();
8003ad6: f7ff fd05 bl 80034e4 <HAL_GetTick>
8003ada: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively enabled */
while(ADC_IS_ENABLE(hadc) == RESET)
8003adc: e01f b.n 8003b1e <ADC_Enable+0x92>
{
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8003ade: f7ff fd01 bl 80034e4 <HAL_GetTick>
8003ae2: 4602 mov r2, r0
8003ae4: 68fb ldr r3, [r7, #12]
8003ae6: 1ad3 subs r3, r2, r3
8003ae8: 2b02 cmp r3, #2
8003aea: d918 bls.n 8003b1e <ADC_Enable+0x92>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) == RESET)
8003aec: 687b ldr r3, [r7, #4]
8003aee: 681b ldr r3, [r3, #0]
8003af0: 689b ldr r3, [r3, #8]
8003af2: f003 0301 and.w r3, r3, #1
8003af6: 2b01 cmp r3, #1
8003af8: d011 beq.n 8003b1e <ADC_Enable+0x92>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003afa: 687b ldr r3, [r7, #4]
8003afc: 6a9b ldr r3, [r3, #40] @ 0x28
8003afe: f043 0210 orr.w r2, r3, #16
8003b02: 687b ldr r3, [r7, #4]
8003b04: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003b06: 687b ldr r3, [r7, #4]
8003b08: 6adb ldr r3, [r3, #44] @ 0x2c
8003b0a: f043 0201 orr.w r2, r3, #1
8003b0e: 687b ldr r3, [r7, #4]
8003b10: 62da str r2, [r3, #44] @ 0x2c
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003b12: 687b ldr r3, [r7, #4]
8003b14: 2200 movs r2, #0
8003b16: f883 2024 strb.w r2, [r3, #36] @ 0x24
return HAL_ERROR;
8003b1a: 2301 movs r3, #1
8003b1c: e007 b.n 8003b2e <ADC_Enable+0xa2>
while(ADC_IS_ENABLE(hadc) == RESET)
8003b1e: 687b ldr r3, [r7, #4]
8003b20: 681b ldr r3, [r3, #0]
8003b22: 689b ldr r3, [r3, #8]
8003b24: f003 0301 and.w r3, r3, #1
8003b28: 2b01 cmp r3, #1
8003b2a: d1d8 bne.n 8003ade <ADC_Enable+0x52>
}
}
}
/* Return HAL status */
return HAL_OK;
8003b2c: 2300 movs r3, #0
}
8003b2e: 4618 mov r0, r3
8003b30: 3710 adds r7, #16
8003b32: 46bd mov sp, r7
8003b34: bd80 pop {r7, pc}
8003b36: bf00 nop
8003b38: 20000008 .word 0x20000008
8003b3c: 431bde83 .word 0x431bde83
08003b40 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8003b40: b580 push {r7, lr}
8003b42: b084 sub sp, #16
8003b44: af00 add r7, sp, #0
8003b46: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8003b48: 2300 movs r3, #0
8003b4a: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
8003b4c: 687b ldr r3, [r7, #4]
8003b4e: 681b ldr r3, [r3, #0]
8003b50: 689b ldr r3, [r3, #8]
8003b52: f003 0301 and.w r3, r3, #1
8003b56: 2b01 cmp r3, #1
8003b58: d12e bne.n 8003bb8 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8003b5a: 687b ldr r3, [r7, #4]
8003b5c: 681b ldr r3, [r3, #0]
8003b5e: 689a ldr r2, [r3, #8]
8003b60: 687b ldr r3, [r7, #4]
8003b62: 681b ldr r3, [r3, #0]
8003b64: f022 0201 bic.w r2, r2, #1
8003b68: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
8003b6a: f7ff fcbb bl 80034e4 <HAL_GetTick>
8003b6e: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
8003b70: e01b b.n 8003baa <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8003b72: f7ff fcb7 bl 80034e4 <HAL_GetTick>
8003b76: 4602 mov r2, r0
8003b78: 68fb ldr r3, [r7, #12]
8003b7a: 1ad3 subs r3, r2, r3
8003b7c: 2b02 cmp r3, #2
8003b7e: d914 bls.n 8003baa <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
8003b80: 687b ldr r3, [r7, #4]
8003b82: 681b ldr r3, [r3, #0]
8003b84: 689b ldr r3, [r3, #8]
8003b86: f003 0301 and.w r3, r3, #1
8003b8a: 2b01 cmp r3, #1
8003b8c: d10d bne.n 8003baa <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003b8e: 687b ldr r3, [r7, #4]
8003b90: 6a9b ldr r3, [r3, #40] @ 0x28
8003b92: f043 0210 orr.w r2, r3, #16
8003b96: 687b ldr r3, [r7, #4]
8003b98: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003b9a: 687b ldr r3, [r7, #4]
8003b9c: 6adb ldr r3, [r3, #44] @ 0x2c
8003b9e: f043 0201 orr.w r2, r3, #1
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
8003ba6: 2301 movs r3, #1
8003ba8: e007 b.n 8003bba <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
8003baa: 687b ldr r3, [r7, #4]
8003bac: 681b ldr r3, [r3, #0]
8003bae: 689b ldr r3, [r3, #8]
8003bb0: f003 0301 and.w r3, r3, #1
8003bb4: 2b01 cmp r3, #1
8003bb6: d0dc beq.n 8003b72 <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
8003bb8: 2300 movs r3, #0
}
8003bba: 4618 mov r0, r3
8003bbc: 3710 adds r7, #16
8003bbe: 46bd mov sp, r7
8003bc0: bd80 pop {r7, pc}
08003bc2 <ADC_DMAConvCplt>:
* @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
8003bc2: b580 push {r7, lr}
8003bc4: b084 sub sp, #16
8003bc6: af00 add r7, sp, #0
8003bc8: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
8003bca: 687b ldr r3, [r7, #4]
8003bcc: 6a5b ldr r3, [r3, #36] @ 0x24
8003bce: 60fb str r3, [r7, #12]
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
8003bd0: 68fb ldr r3, [r7, #12]
8003bd2: 6a9b ldr r3, [r3, #40] @ 0x28
8003bd4: f003 0350 and.w r3, r3, #80 @ 0x50
8003bd8: 2b00 cmp r3, #0
8003bda: d127 bne.n 8003c2c <ADC_DMAConvCplt+0x6a>
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8003bdc: 68fb ldr r3, [r7, #12]
8003bde: 6a9b ldr r3, [r3, #40] @ 0x28
8003be0: f443 7200 orr.w r2, r3, #512 @ 0x200
8003be4: 68fb ldr r3, [r7, #12]
8003be6: 629a str r2, [r3, #40] @ 0x28
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F1 devices, in case of sequencer enabled */
/* (several ranks selected), end of conversion flag is raised */
/* at the end of the sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8003be8: 68fb ldr r3, [r7, #12]
8003bea: 681b ldr r3, [r3, #0]
8003bec: 689b ldr r3, [r3, #8]
8003bee: f403 2360 and.w r3, r3, #917504 @ 0xe0000
8003bf2: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000
8003bf6: d115 bne.n 8003c24 <ADC_DMAConvCplt+0x62>
(hadc->Init.ContinuousConvMode == DISABLE) )
8003bf8: 68fb ldr r3, [r7, #12]
8003bfa: 7b1b ldrb r3, [r3, #12]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8003bfc: 2b00 cmp r3, #0
8003bfe: d111 bne.n 8003c24 <ADC_DMAConvCplt+0x62>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8003c00: 68fb ldr r3, [r7, #12]
8003c02: 6a9b ldr r3, [r3, #40] @ 0x28
8003c04: f423 7280 bic.w r2, r3, #256 @ 0x100
8003c08: 68fb ldr r3, [r7, #12]
8003c0a: 629a str r2, [r3, #40] @ 0x28
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8003c0c: 68fb ldr r3, [r7, #12]
8003c0e: 6a9b ldr r3, [r3, #40] @ 0x28
8003c10: f403 5380 and.w r3, r3, #4096 @ 0x1000
8003c14: 2b00 cmp r3, #0
8003c16: d105 bne.n 8003c24 <ADC_DMAConvCplt+0x62>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8003c18: 68fb ldr r3, [r7, #12]
8003c1a: 6a9b ldr r3, [r3, #40] @ 0x28
8003c1c: f043 0201 orr.w r2, r3, #1
8003c20: 68fb ldr r3, [r7, #12]
8003c22: 629a str r2, [r3, #40] @ 0x28
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
8003c24: 68f8 ldr r0, [r7, #12]
8003c26: f7ff fe1d bl 8003864 <HAL_ADC_ConvCpltCallback>
else
{
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
8003c2a: e004 b.n 8003c36 <ADC_DMAConvCplt+0x74>
hadc->DMA_Handle->XferErrorCallback(hdma);
8003c2c: 68fb ldr r3, [r7, #12]
8003c2e: 6a1b ldr r3, [r3, #32]
8003c30: 6b1b ldr r3, [r3, #48] @ 0x30
8003c32: 6878 ldr r0, [r7, #4]
8003c34: 4798 blx r3
}
8003c36: bf00 nop
8003c38: 3710 adds r7, #16
8003c3a: 46bd mov sp, r7
8003c3c: bd80 pop {r7, pc}
08003c3e <ADC_DMAHalfConvCplt>:
* @brief DMA half transfer complete callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
8003c3e: b580 push {r7, lr}
8003c40: b084 sub sp, #16
8003c42: af00 add r7, sp, #0
8003c44: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
8003c46: 687b ldr r3, [r7, #4]
8003c48: 6a5b ldr r3, [r3, #36] @ 0x24
8003c4a: 60fb str r3, [r7, #12]
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc);
8003c4c: 68f8 ldr r0, [r7, #12]
8003c4e: f7ff fe12 bl 8003876 <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
8003c52: bf00 nop
8003c54: 3710 adds r7, #16
8003c56: 46bd mov sp, r7
8003c58: bd80 pop {r7, pc}
08003c5a <ADC_DMAError>:
* @brief DMA error callback
* @param hdma: pointer to DMA handle.
* @retval None
*/
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
8003c5a: b580 push {r7, lr}
8003c5c: b084 sub sp, #16
8003c5e: af00 add r7, sp, #0
8003c60: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
8003c62: 687b ldr r3, [r7, #4]
8003c64: 6a5b ldr r3, [r3, #36] @ 0x24
8003c66: 60fb str r3, [r7, #12]
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
8003c68: 68fb ldr r3, [r7, #12]
8003c6a: 6a9b ldr r3, [r3, #40] @ 0x28
8003c6c: f043 0240 orr.w r2, r3, #64 @ 0x40
8003c70: 68fb ldr r3, [r7, #12]
8003c72: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to DMA error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
8003c74: 68fb ldr r3, [r7, #12]
8003c76: 6adb ldr r3, [r3, #44] @ 0x2c
8003c78: f043 0204 orr.w r2, r3, #4
8003c7c: 68fb ldr r3, [r7, #12]
8003c7e: 62da str r2, [r3, #44] @ 0x2c
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8003c80: 68f8 ldr r0, [r7, #12]
8003c82: f7ff fe01 bl 8003888 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
8003c86: bf00 nop
8003c88: 3710 adds r7, #16
8003c8a: 46bd mov sp, r7
8003c8c: bd80 pop {r7, pc}
...
08003c90 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003c90: b480 push {r7}
8003c92: b085 sub sp, #20
8003c94: af00 add r7, sp, #0
8003c96: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003c98: 687b ldr r3, [r7, #4]
8003c9a: f003 0307 and.w r3, r3, #7
8003c9e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8003ca0: 4b0c ldr r3, [pc, #48] @ (8003cd4 <__NVIC_SetPriorityGrouping+0x44>)
8003ca2: 68db ldr r3, [r3, #12]
8003ca4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8003ca6: 68ba ldr r2, [r7, #8]
8003ca8: f64f 03ff movw r3, #63743 @ 0xf8ff
8003cac: 4013 ands r3, r2
8003cae: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003cb0: 68fb ldr r3, [r7, #12]
8003cb2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8003cb4: 68bb ldr r3, [r7, #8]
8003cb6: 4313 orrs r3, r2
reg_value = (reg_value |
8003cb8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003cbc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003cc0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8003cc2: 4a04 ldr r2, [pc, #16] @ (8003cd4 <__NVIC_SetPriorityGrouping+0x44>)
8003cc4: 68bb ldr r3, [r7, #8]
8003cc6: 60d3 str r3, [r2, #12]
}
8003cc8: bf00 nop
8003cca: 3714 adds r7, #20
8003ccc: 46bd mov sp, r7
8003cce: bc80 pop {r7}
8003cd0: 4770 bx lr
8003cd2: bf00 nop
8003cd4: e000ed00 .word 0xe000ed00
08003cd8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8003cd8: b480 push {r7}
8003cda: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003cdc: 4b04 ldr r3, [pc, #16] @ (8003cf0 <__NVIC_GetPriorityGrouping+0x18>)
8003cde: 68db ldr r3, [r3, #12]
8003ce0: 0a1b lsrs r3, r3, #8
8003ce2: f003 0307 and.w r3, r3, #7
}
8003ce6: 4618 mov r0, r3
8003ce8: 46bd mov sp, r7
8003cea: bc80 pop {r7}
8003cec: 4770 bx lr
8003cee: bf00 nop
8003cf0: e000ed00 .word 0xe000ed00
08003cf4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003cf4: b480 push {r7}
8003cf6: b083 sub sp, #12
8003cf8: af00 add r7, sp, #0
8003cfa: 4603 mov r3, r0
8003cfc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003cfe: f997 3007 ldrsb.w r3, [r7, #7]
8003d02: 2b00 cmp r3, #0
8003d04: db0b blt.n 8003d1e <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8003d06: 79fb ldrb r3, [r7, #7]
8003d08: f003 021f and.w r2, r3, #31
8003d0c: 4906 ldr r1, [pc, #24] @ (8003d28 <__NVIC_EnableIRQ+0x34>)
8003d0e: f997 3007 ldrsb.w r3, [r7, #7]
8003d12: 095b lsrs r3, r3, #5
8003d14: 2001 movs r0, #1
8003d16: fa00 f202 lsl.w r2, r0, r2
8003d1a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8003d1e: bf00 nop
8003d20: 370c adds r7, #12
8003d22: 46bd mov sp, r7
8003d24: bc80 pop {r7}
8003d26: 4770 bx lr
8003d28: e000e100 .word 0xe000e100
08003d2c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003d2c: b480 push {r7}
8003d2e: b083 sub sp, #12
8003d30: af00 add r7, sp, #0
8003d32: 4603 mov r3, r0
8003d34: 6039 str r1, [r7, #0]
8003d36: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003d38: f997 3007 ldrsb.w r3, [r7, #7]
8003d3c: 2b00 cmp r3, #0
8003d3e: db0a blt.n 8003d56 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003d40: 683b ldr r3, [r7, #0]
8003d42: b2da uxtb r2, r3
8003d44: 490c ldr r1, [pc, #48] @ (8003d78 <__NVIC_SetPriority+0x4c>)
8003d46: f997 3007 ldrsb.w r3, [r7, #7]
8003d4a: 0112 lsls r2, r2, #4
8003d4c: b2d2 uxtb r2, r2
8003d4e: 440b add r3, r1
8003d50: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003d54: e00a b.n 8003d6c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003d56: 683b ldr r3, [r7, #0]
8003d58: b2da uxtb r2, r3
8003d5a: 4908 ldr r1, [pc, #32] @ (8003d7c <__NVIC_SetPriority+0x50>)
8003d5c: 79fb ldrb r3, [r7, #7]
8003d5e: f003 030f and.w r3, r3, #15
8003d62: 3b04 subs r3, #4
8003d64: 0112 lsls r2, r2, #4
8003d66: b2d2 uxtb r2, r2
8003d68: 440b add r3, r1
8003d6a: 761a strb r2, [r3, #24]
}
8003d6c: bf00 nop
8003d6e: 370c adds r7, #12
8003d70: 46bd mov sp, r7
8003d72: bc80 pop {r7}
8003d74: 4770 bx lr
8003d76: bf00 nop
8003d78: e000e100 .word 0xe000e100
8003d7c: e000ed00 .word 0xe000ed00
08003d80 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003d80: b480 push {r7}
8003d82: b089 sub sp, #36 @ 0x24
8003d84: af00 add r7, sp, #0
8003d86: 60f8 str r0, [r7, #12]
8003d88: 60b9 str r1, [r7, #8]
8003d8a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003d8c: 68fb ldr r3, [r7, #12]
8003d8e: f003 0307 and.w r3, r3, #7
8003d92: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8003d94: 69fb ldr r3, [r7, #28]
8003d96: f1c3 0307 rsb r3, r3, #7
8003d9a: 2b04 cmp r3, #4
8003d9c: bf28 it cs
8003d9e: 2304 movcs r3, #4
8003da0: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8003da2: 69fb ldr r3, [r7, #28]
8003da4: 3304 adds r3, #4
8003da6: 2b06 cmp r3, #6
8003da8: d902 bls.n 8003db0 <NVIC_EncodePriority+0x30>
8003daa: 69fb ldr r3, [r7, #28]
8003dac: 3b03 subs r3, #3
8003dae: e000 b.n 8003db2 <NVIC_EncodePriority+0x32>
8003db0: 2300 movs r3, #0
8003db2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003db4: f04f 32ff mov.w r2, #4294967295
8003db8: 69bb ldr r3, [r7, #24]
8003dba: fa02 f303 lsl.w r3, r2, r3
8003dbe: 43da mvns r2, r3
8003dc0: 68bb ldr r3, [r7, #8]
8003dc2: 401a ands r2, r3
8003dc4: 697b ldr r3, [r7, #20]
8003dc6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8003dc8: f04f 31ff mov.w r1, #4294967295
8003dcc: 697b ldr r3, [r7, #20]
8003dce: fa01 f303 lsl.w r3, r1, r3
8003dd2: 43d9 mvns r1, r3
8003dd4: 687b ldr r3, [r7, #4]
8003dd6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003dd8: 4313 orrs r3, r2
);
}
8003dda: 4618 mov r0, r3
8003ddc: 3724 adds r7, #36 @ 0x24
8003dde: 46bd mov sp, r7
8003de0: bc80 pop {r7}
8003de2: 4770 bx lr
08003de4 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003de4: b580 push {r7, lr}
8003de6: b082 sub sp, #8
8003de8: af00 add r7, sp, #0
8003dea: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003dec: 687b ldr r3, [r7, #4]
8003dee: 3b01 subs r3, #1
8003df0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003df4: d301 bcc.n 8003dfa <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8003df6: 2301 movs r3, #1
8003df8: e00f b.n 8003e1a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003dfa: 4a0a ldr r2, [pc, #40] @ (8003e24 <SysTick_Config+0x40>)
8003dfc: 687b ldr r3, [r7, #4]
8003dfe: 3b01 subs r3, #1
8003e00: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8003e02: 210f movs r1, #15
8003e04: f04f 30ff mov.w r0, #4294967295
8003e08: f7ff ff90 bl 8003d2c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003e0c: 4b05 ldr r3, [pc, #20] @ (8003e24 <SysTick_Config+0x40>)
8003e0e: 2200 movs r2, #0
8003e10: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8003e12: 4b04 ldr r3, [pc, #16] @ (8003e24 <SysTick_Config+0x40>)
8003e14: 2207 movs r2, #7
8003e16: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003e18: 2300 movs r3, #0
}
8003e1a: 4618 mov r0, r3
8003e1c: 3708 adds r7, #8
8003e1e: 46bd mov sp, r7
8003e20: bd80 pop {r7, pc}
8003e22: bf00 nop
8003e24: e000e010 .word 0xe000e010
08003e28 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003e28: b580 push {r7, lr}
8003e2a: b082 sub sp, #8
8003e2c: af00 add r7, sp, #0
8003e2e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003e30: 6878 ldr r0, [r7, #4]
8003e32: f7ff ff2d bl 8003c90 <__NVIC_SetPriorityGrouping>
}
8003e36: bf00 nop
8003e38: 3708 adds r7, #8
8003e3a: 46bd mov sp, r7
8003e3c: bd80 pop {r7, pc}
08003e3e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003e3e: b580 push {r7, lr}
8003e40: b086 sub sp, #24
8003e42: af00 add r7, sp, #0
8003e44: 4603 mov r3, r0
8003e46: 60b9 str r1, [r7, #8]
8003e48: 607a str r2, [r7, #4]
8003e4a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8003e4c: 2300 movs r3, #0
8003e4e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003e50: f7ff ff42 bl 8003cd8 <__NVIC_GetPriorityGrouping>
8003e54: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8003e56: 687a ldr r2, [r7, #4]
8003e58: 68b9 ldr r1, [r7, #8]
8003e5a: 6978 ldr r0, [r7, #20]
8003e5c: f7ff ff90 bl 8003d80 <NVIC_EncodePriority>
8003e60: 4602 mov r2, r0
8003e62: f997 300f ldrsb.w r3, [r7, #15]
8003e66: 4611 mov r1, r2
8003e68: 4618 mov r0, r3
8003e6a: f7ff ff5f bl 8003d2c <__NVIC_SetPriority>
}
8003e6e: bf00 nop
8003e70: 3718 adds r7, #24
8003e72: 46bd mov sp, r7
8003e74: bd80 pop {r7, pc}
08003e76 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003e76: b580 push {r7, lr}
8003e78: b082 sub sp, #8
8003e7a: af00 add r7, sp, #0
8003e7c: 4603 mov r3, r0
8003e7e: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003e80: f997 3007 ldrsb.w r3, [r7, #7]
8003e84: 4618 mov r0, r3
8003e86: f7ff ff35 bl 8003cf4 <__NVIC_EnableIRQ>
}
8003e8a: bf00 nop
8003e8c: 3708 adds r7, #8
8003e8e: 46bd mov sp, r7
8003e90: bd80 pop {r7, pc}
08003e92 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8003e92: b580 push {r7, lr}
8003e94: b082 sub sp, #8
8003e96: af00 add r7, sp, #0
8003e98: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8003e9a: 6878 ldr r0, [r7, #4]
8003e9c: f7ff ffa2 bl 8003de4 <SysTick_Config>
8003ea0: 4603 mov r3, r0
}
8003ea2: 4618 mov r0, r3
8003ea4: 3708 adds r7, #8
8003ea6: 46bd mov sp, r7
8003ea8: bd80 pop {r7, pc}
08003eaa <HAL_SYSTICK_IRQHandler>:
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
8003eaa: b580 push {r7, lr}
8003eac: af00 add r7, sp, #0
HAL_SYSTICK_Callback();
8003eae: f7fd fa17 bl 80012e0 <HAL_SYSTICK_Callback>
}
8003eb2: bf00 nop
8003eb4: bd80 pop {r7, pc}
...
08003eb8 <HAL_DMA_Init>:
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8003eb8: b480 push {r7}
8003eba: b085 sub sp, #20
8003ebc: af00 add r7, sp, #0
8003ebe: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
8003ec0: 2300 movs r3, #0
8003ec2: 60fb str r3, [r7, #12]
/* Check the DMA handle allocation */
if(hdma == NULL)
8003ec4: 687b ldr r3, [r7, #4]
8003ec6: 2b00 cmp r3, #0
8003ec8: d101 bne.n 8003ece <HAL_DMA_Init+0x16>
{
return HAL_ERROR;
8003eca: 2301 movs r3, #1
8003ecc: e043 b.n 8003f56 <HAL_DMA_Init+0x9e>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
8003ece: 687b ldr r3, [r7, #4]
8003ed0: 681b ldr r3, [r3, #0]
8003ed2: 461a mov r2, r3
8003ed4: 4b22 ldr r3, [pc, #136] @ (8003f60 <HAL_DMA_Init+0xa8>)
8003ed6: 4413 add r3, r2
8003ed8: 4a22 ldr r2, [pc, #136] @ (8003f64 <HAL_DMA_Init+0xac>)
8003eda: fba2 2303 umull r2, r3, r2, r3
8003ede: 091b lsrs r3, r3, #4
8003ee0: 009a lsls r2, r3, #2
8003ee2: 687b ldr r3, [r7, #4]
8003ee4: 641a str r2, [r3, #64] @ 0x40
hdma->DmaBaseAddress = DMA1;
8003ee6: 687b ldr r3, [r7, #4]
8003ee8: 4a1f ldr r2, [pc, #124] @ (8003f68 <HAL_DMA_Init+0xb0>)
8003eea: 63da str r2, [r3, #60] @ 0x3c
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8003eec: 687b ldr r3, [r7, #4]
8003eee: 2202 movs r2, #2
8003ef0: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Get the CR register value */
tmp = hdma->Instance->CCR;
8003ef4: 687b ldr r3, [r7, #4]
8003ef6: 681b ldr r3, [r3, #0]
8003ef8: 681b ldr r3, [r3, #0]
8003efa: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8003efc: 68fb ldr r3, [r7, #12]
8003efe: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8003f02: f023 0330 bic.w r3, r3, #48 @ 0x30
8003f06: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
8003f08: 687b ldr r3, [r7, #4]
8003f0a: 685a ldr r2, [r3, #4]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8003f0c: 687b ldr r3, [r7, #4]
8003f0e: 689b ldr r3, [r3, #8]
tmp |= hdma->Init.Direction |
8003f10: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8003f12: 687b ldr r3, [r7, #4]
8003f14: 68db ldr r3, [r3, #12]
8003f16: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8003f18: 687b ldr r3, [r7, #4]
8003f1a: 691b ldr r3, [r3, #16]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8003f1c: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8003f1e: 687b ldr r3, [r7, #4]
8003f20: 695b ldr r3, [r3, #20]
8003f22: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8003f24: 687b ldr r3, [r7, #4]
8003f26: 699b ldr r3, [r3, #24]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8003f28: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8003f2a: 687b ldr r3, [r7, #4]
8003f2c: 69db ldr r3, [r3, #28]
8003f2e: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8003f30: 68fa ldr r2, [r7, #12]
8003f32: 4313 orrs r3, r2
8003f34: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
8003f36: 687b ldr r3, [r7, #4]
8003f38: 681b ldr r3, [r3, #0]
8003f3a: 68fa ldr r2, [r7, #12]
8003f3c: 601a str r2, [r3, #0]
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8003f3e: 687b ldr r3, [r7, #4]
8003f40: 2200 movs r2, #0
8003f42: 639a str r2, [r3, #56] @ 0x38
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8003f44: 687b ldr r3, [r7, #4]
8003f46: 2201 movs r2, #1
8003f48: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
8003f4c: 687b ldr r3, [r7, #4]
8003f4e: 2200 movs r2, #0
8003f50: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
8003f54: 2300 movs r3, #0
}
8003f56: 4618 mov r0, r3
8003f58: 3714 adds r7, #20
8003f5a: 46bd mov sp, r7
8003f5c: bc80 pop {r7}
8003f5e: 4770 bx lr
8003f60: bffdfff8 .word 0xbffdfff8
8003f64: cccccccd .word 0xcccccccd
8003f68: 40020000 .word 0x40020000
08003f6c <HAL_DMA_Start_IT>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8003f6c: b580 push {r7, lr}
8003f6e: b086 sub sp, #24
8003f70: af00 add r7, sp, #0
8003f72: 60f8 str r0, [r7, #12]
8003f74: 60b9 str r1, [r7, #8]
8003f76: 607a str r2, [r7, #4]
8003f78: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8003f7a: 2300 movs r3, #0
8003f7c: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8003f7e: 68fb ldr r3, [r7, #12]
8003f80: f893 3020 ldrb.w r3, [r3, #32]
8003f84: 2b01 cmp r3, #1
8003f86: d101 bne.n 8003f8c <HAL_DMA_Start_IT+0x20>
8003f88: 2302 movs r3, #2
8003f8a: e04b b.n 8004024 <HAL_DMA_Start_IT+0xb8>
8003f8c: 68fb ldr r3, [r7, #12]
8003f8e: 2201 movs r2, #1
8003f90: f883 2020 strb.w r2, [r3, #32]
if(HAL_DMA_STATE_READY == hdma->State)
8003f94: 68fb ldr r3, [r7, #12]
8003f96: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003f9a: b2db uxtb r3, r3
8003f9c: 2b01 cmp r3, #1
8003f9e: d13a bne.n 8004016 <HAL_DMA_Start_IT+0xaa>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8003fa0: 68fb ldr r3, [r7, #12]
8003fa2: 2202 movs r2, #2
8003fa4: f883 2021 strb.w r2, [r3, #33] @ 0x21
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8003fa8: 68fb ldr r3, [r7, #12]
8003faa: 2200 movs r2, #0
8003fac: 639a str r2, [r3, #56] @ 0x38
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8003fae: 68fb ldr r3, [r7, #12]
8003fb0: 681b ldr r3, [r3, #0]
8003fb2: 681a ldr r2, [r3, #0]
8003fb4: 68fb ldr r3, [r7, #12]
8003fb6: 681b ldr r3, [r3, #0]
8003fb8: f022 0201 bic.w r2, r2, #1
8003fbc: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8003fbe: 683b ldr r3, [r7, #0]
8003fc0: 687a ldr r2, [r7, #4]
8003fc2: 68b9 ldr r1, [r7, #8]
8003fc4: 68f8 ldr r0, [r7, #12]
8003fc6: f000 f937 bl 8004238 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback)
8003fca: 68fb ldr r3, [r7, #12]
8003fcc: 6adb ldr r3, [r3, #44] @ 0x2c
8003fce: 2b00 cmp r3, #0
8003fd0: d008 beq.n 8003fe4 <HAL_DMA_Start_IT+0x78>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003fd2: 68fb ldr r3, [r7, #12]
8003fd4: 681b ldr r3, [r3, #0]
8003fd6: 681a ldr r2, [r3, #0]
8003fd8: 68fb ldr r3, [r7, #12]
8003fda: 681b ldr r3, [r3, #0]
8003fdc: f042 020e orr.w r2, r2, #14
8003fe0: 601a str r2, [r3, #0]
8003fe2: e00f b.n 8004004 <HAL_DMA_Start_IT+0x98>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8003fe4: 68fb ldr r3, [r7, #12]
8003fe6: 681b ldr r3, [r3, #0]
8003fe8: 681a ldr r2, [r3, #0]
8003fea: 68fb ldr r3, [r7, #12]
8003fec: 681b ldr r3, [r3, #0]
8003fee: f022 0204 bic.w r2, r2, #4
8003ff2: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8003ff4: 68fb ldr r3, [r7, #12]
8003ff6: 681b ldr r3, [r3, #0]
8003ff8: 681a ldr r2, [r3, #0]
8003ffa: 68fb ldr r3, [r7, #12]
8003ffc: 681b ldr r3, [r3, #0]
8003ffe: f042 020a orr.w r2, r2, #10
8004002: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8004004: 68fb ldr r3, [r7, #12]
8004006: 681b ldr r3, [r3, #0]
8004008: 681a ldr r2, [r3, #0]
800400a: 68fb ldr r3, [r7, #12]
800400c: 681b ldr r3, [r3, #0]
800400e: f042 0201 orr.w r2, r2, #1
8004012: 601a str r2, [r3, #0]
8004014: e005 b.n 8004022 <HAL_DMA_Start_IT+0xb6>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8004016: 68fb ldr r3, [r7, #12]
8004018: 2200 movs r2, #0
800401a: f883 2020 strb.w r2, [r3, #32]
/* Remain BUSY */
status = HAL_BUSY;
800401e: 2302 movs r3, #2
8004020: 75fb strb r3, [r7, #23]
}
return status;
8004022: 7dfb ldrb r3, [r7, #23]
}
8004024: 4618 mov r0, r3
8004026: 3718 adds r7, #24
8004028: 46bd mov sp, r7
800402a: bd80 pop {r7, pc}
0800402c <HAL_DMA_IRQHandler>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
800402c: b580 push {r7, lr}
800402e: b084 sub sp, #16
8004030: af00 add r7, sp, #0
8004032: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8004034: 687b ldr r3, [r7, #4]
8004036: 6bdb ldr r3, [r3, #60] @ 0x3c
8004038: 681b ldr r3, [r3, #0]
800403a: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
800403c: 687b ldr r3, [r7, #4]
800403e: 681b ldr r3, [r3, #0]
8004040: 681b ldr r3, [r3, #0]
8004042: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
8004044: 687b ldr r3, [r7, #4]
8004046: 6c1b ldr r3, [r3, #64] @ 0x40
8004048: 2204 movs r2, #4
800404a: 409a lsls r2, r3
800404c: 68fb ldr r3, [r7, #12]
800404e: 4013 ands r3, r2
8004050: 2b00 cmp r3, #0
8004052: d04f beq.n 80040f4 <HAL_DMA_IRQHandler+0xc8>
8004054: 68bb ldr r3, [r7, #8]
8004056: f003 0304 and.w r3, r3, #4
800405a: 2b00 cmp r3, #0
800405c: d04a beq.n 80040f4 <HAL_DMA_IRQHandler+0xc8>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
800405e: 687b ldr r3, [r7, #4]
8004060: 681b ldr r3, [r3, #0]
8004062: 681b ldr r3, [r3, #0]
8004064: f003 0320 and.w r3, r3, #32
8004068: 2b00 cmp r3, #0
800406a: d107 bne.n 800407c <HAL_DMA_IRQHandler+0x50>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
800406c: 687b ldr r3, [r7, #4]
800406e: 681b ldr r3, [r3, #0]
8004070: 681a ldr r2, [r3, #0]
8004072: 687b ldr r3, [r7, #4]
8004074: 681b ldr r3, [r3, #0]
8004076: f022 0204 bic.w r2, r2, #4
800407a: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
800407c: 687b ldr r3, [r7, #4]
800407e: 681b ldr r3, [r3, #0]
8004080: 4a66 ldr r2, [pc, #408] @ (800421c <HAL_DMA_IRQHandler+0x1f0>)
8004082: 4293 cmp r3, r2
8004084: d029 beq.n 80040da <HAL_DMA_IRQHandler+0xae>
8004086: 687b ldr r3, [r7, #4]
8004088: 681b ldr r3, [r3, #0]
800408a: 4a65 ldr r2, [pc, #404] @ (8004220 <HAL_DMA_IRQHandler+0x1f4>)
800408c: 4293 cmp r3, r2
800408e: d022 beq.n 80040d6 <HAL_DMA_IRQHandler+0xaa>
8004090: 687b ldr r3, [r7, #4]
8004092: 681b ldr r3, [r3, #0]
8004094: 4a63 ldr r2, [pc, #396] @ (8004224 <HAL_DMA_IRQHandler+0x1f8>)
8004096: 4293 cmp r3, r2
8004098: d01a beq.n 80040d0 <HAL_DMA_IRQHandler+0xa4>
800409a: 687b ldr r3, [r7, #4]
800409c: 681b ldr r3, [r3, #0]
800409e: 4a62 ldr r2, [pc, #392] @ (8004228 <HAL_DMA_IRQHandler+0x1fc>)
80040a0: 4293 cmp r3, r2
80040a2: d012 beq.n 80040ca <HAL_DMA_IRQHandler+0x9e>
80040a4: 687b ldr r3, [r7, #4]
80040a6: 681b ldr r3, [r3, #0]
80040a8: 4a60 ldr r2, [pc, #384] @ (800422c <HAL_DMA_IRQHandler+0x200>)
80040aa: 4293 cmp r3, r2
80040ac: d00a beq.n 80040c4 <HAL_DMA_IRQHandler+0x98>
80040ae: 687b ldr r3, [r7, #4]
80040b0: 681b ldr r3, [r3, #0]
80040b2: 4a5f ldr r2, [pc, #380] @ (8004230 <HAL_DMA_IRQHandler+0x204>)
80040b4: 4293 cmp r3, r2
80040b6: d102 bne.n 80040be <HAL_DMA_IRQHandler+0x92>
80040b8: f44f 0380 mov.w r3, #4194304 @ 0x400000
80040bc: e00e b.n 80040dc <HAL_DMA_IRQHandler+0xb0>
80040be: f04f 6380 mov.w r3, #67108864 @ 0x4000000
80040c2: e00b b.n 80040dc <HAL_DMA_IRQHandler+0xb0>
80040c4: f44f 2380 mov.w r3, #262144 @ 0x40000
80040c8: e008 b.n 80040dc <HAL_DMA_IRQHandler+0xb0>
80040ca: f44f 4380 mov.w r3, #16384 @ 0x4000
80040ce: e005 b.n 80040dc <HAL_DMA_IRQHandler+0xb0>
80040d0: f44f 6380 mov.w r3, #1024 @ 0x400
80040d4: e002 b.n 80040dc <HAL_DMA_IRQHandler+0xb0>
80040d6: 2340 movs r3, #64 @ 0x40
80040d8: e000 b.n 80040dc <HAL_DMA_IRQHandler+0xb0>
80040da: 2304 movs r3, #4
80040dc: 4a55 ldr r2, [pc, #340] @ (8004234 <HAL_DMA_IRQHandler+0x208>)
80040de: 6053 str r3, [r2, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
80040e0: 687b ldr r3, [r7, #4]
80040e2: 6adb ldr r3, [r3, #44] @ 0x2c
80040e4: 2b00 cmp r3, #0
80040e6: f000 8094 beq.w 8004212 <HAL_DMA_IRQHandler+0x1e6>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
80040ea: 687b ldr r3, [r7, #4]
80040ec: 6adb ldr r3, [r3, #44] @ 0x2c
80040ee: 6878 ldr r0, [r7, #4]
80040f0: 4798 blx r3
if(hdma->XferHalfCpltCallback != NULL)
80040f2: e08e b.n 8004212 <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
80040f4: 687b ldr r3, [r7, #4]
80040f6: 6c1b ldr r3, [r3, #64] @ 0x40
80040f8: 2202 movs r2, #2
80040fa: 409a lsls r2, r3
80040fc: 68fb ldr r3, [r7, #12]
80040fe: 4013 ands r3, r2
8004100: 2b00 cmp r3, #0
8004102: d056 beq.n 80041b2 <HAL_DMA_IRQHandler+0x186>
8004104: 68bb ldr r3, [r7, #8]
8004106: f003 0302 and.w r3, r3, #2
800410a: 2b00 cmp r3, #0
800410c: d051 beq.n 80041b2 <HAL_DMA_IRQHandler+0x186>
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
800410e: 687b ldr r3, [r7, #4]
8004110: 681b ldr r3, [r3, #0]
8004112: 681b ldr r3, [r3, #0]
8004114: f003 0320 and.w r3, r3, #32
8004118: 2b00 cmp r3, #0
800411a: d10b bne.n 8004134 <HAL_DMA_IRQHandler+0x108>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
800411c: 687b ldr r3, [r7, #4]
800411e: 681b ldr r3, [r3, #0]
8004120: 681a ldr r2, [r3, #0]
8004122: 687b ldr r3, [r7, #4]
8004124: 681b ldr r3, [r3, #0]
8004126: f022 020a bic.w r2, r2, #10
800412a: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800412c: 687b ldr r3, [r7, #4]
800412e: 2201 movs r2, #1
8004130: f883 2021 strb.w r2, [r3, #33] @ 0x21
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
8004134: 687b ldr r3, [r7, #4]
8004136: 681b ldr r3, [r3, #0]
8004138: 4a38 ldr r2, [pc, #224] @ (800421c <HAL_DMA_IRQHandler+0x1f0>)
800413a: 4293 cmp r3, r2
800413c: d029 beq.n 8004192 <HAL_DMA_IRQHandler+0x166>
800413e: 687b ldr r3, [r7, #4]
8004140: 681b ldr r3, [r3, #0]
8004142: 4a37 ldr r2, [pc, #220] @ (8004220 <HAL_DMA_IRQHandler+0x1f4>)
8004144: 4293 cmp r3, r2
8004146: d022 beq.n 800418e <HAL_DMA_IRQHandler+0x162>
8004148: 687b ldr r3, [r7, #4]
800414a: 681b ldr r3, [r3, #0]
800414c: 4a35 ldr r2, [pc, #212] @ (8004224 <HAL_DMA_IRQHandler+0x1f8>)
800414e: 4293 cmp r3, r2
8004150: d01a beq.n 8004188 <HAL_DMA_IRQHandler+0x15c>
8004152: 687b ldr r3, [r7, #4]
8004154: 681b ldr r3, [r3, #0]
8004156: 4a34 ldr r2, [pc, #208] @ (8004228 <HAL_DMA_IRQHandler+0x1fc>)
8004158: 4293 cmp r3, r2
800415a: d012 beq.n 8004182 <HAL_DMA_IRQHandler+0x156>
800415c: 687b ldr r3, [r7, #4]
800415e: 681b ldr r3, [r3, #0]
8004160: 4a32 ldr r2, [pc, #200] @ (800422c <HAL_DMA_IRQHandler+0x200>)
8004162: 4293 cmp r3, r2
8004164: d00a beq.n 800417c <HAL_DMA_IRQHandler+0x150>
8004166: 687b ldr r3, [r7, #4]
8004168: 681b ldr r3, [r3, #0]
800416a: 4a31 ldr r2, [pc, #196] @ (8004230 <HAL_DMA_IRQHandler+0x204>)
800416c: 4293 cmp r3, r2
800416e: d102 bne.n 8004176 <HAL_DMA_IRQHandler+0x14a>
8004170: f44f 1300 mov.w r3, #2097152 @ 0x200000
8004174: e00e b.n 8004194 <HAL_DMA_IRQHandler+0x168>
8004176: f04f 7300 mov.w r3, #33554432 @ 0x2000000
800417a: e00b b.n 8004194 <HAL_DMA_IRQHandler+0x168>
800417c: f44f 3300 mov.w r3, #131072 @ 0x20000
8004180: e008 b.n 8004194 <HAL_DMA_IRQHandler+0x168>
8004182: f44f 5300 mov.w r3, #8192 @ 0x2000
8004186: e005 b.n 8004194 <HAL_DMA_IRQHandler+0x168>
8004188: f44f 7300 mov.w r3, #512 @ 0x200
800418c: e002 b.n 8004194 <HAL_DMA_IRQHandler+0x168>
800418e: 2320 movs r3, #32
8004190: e000 b.n 8004194 <HAL_DMA_IRQHandler+0x168>
8004192: 2302 movs r3, #2
8004194: 4a27 ldr r2, [pc, #156] @ (8004234 <HAL_DMA_IRQHandler+0x208>)
8004196: 6053 str r3, [r2, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8004198: 687b ldr r3, [r7, #4]
800419a: 2200 movs r2, #0
800419c: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferCpltCallback != NULL)
80041a0: 687b ldr r3, [r7, #4]
80041a2: 6a9b ldr r3, [r3, #40] @ 0x28
80041a4: 2b00 cmp r3, #0
80041a6: d034 beq.n 8004212 <HAL_DMA_IRQHandler+0x1e6>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
80041a8: 687b ldr r3, [r7, #4]
80041aa: 6a9b ldr r3, [r3, #40] @ 0x28
80041ac: 6878 ldr r0, [r7, #4]
80041ae: 4798 blx r3
if(hdma->XferCpltCallback != NULL)
80041b0: e02f b.n 8004212 <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
80041b2: 687b ldr r3, [r7, #4]
80041b4: 6c1b ldr r3, [r3, #64] @ 0x40
80041b6: 2208 movs r2, #8
80041b8: 409a lsls r2, r3
80041ba: 68fb ldr r3, [r7, #12]
80041bc: 4013 ands r3, r2
80041be: 2b00 cmp r3, #0
80041c0: d028 beq.n 8004214 <HAL_DMA_IRQHandler+0x1e8>
80041c2: 68bb ldr r3, [r7, #8]
80041c4: f003 0308 and.w r3, r3, #8
80041c8: 2b00 cmp r3, #0
80041ca: d023 beq.n 8004214 <HAL_DMA_IRQHandler+0x1e8>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80041cc: 687b ldr r3, [r7, #4]
80041ce: 681b ldr r3, [r3, #0]
80041d0: 681a ldr r2, [r3, #0]
80041d2: 687b ldr r3, [r7, #4]
80041d4: 681b ldr r3, [r3, #0]
80041d6: f022 020e bic.w r2, r2, #14
80041da: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
80041dc: 687b ldr r3, [r7, #4]
80041de: 6c1a ldr r2, [r3, #64] @ 0x40
80041e0: 687b ldr r3, [r7, #4]
80041e2: 6bdb ldr r3, [r3, #60] @ 0x3c
80041e4: 2101 movs r1, #1
80041e6: fa01 f202 lsl.w r2, r1, r2
80041ea: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
80041ec: 687b ldr r3, [r7, #4]
80041ee: 2201 movs r2, #1
80041f0: 639a str r2, [r3, #56] @ 0x38
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80041f2: 687b ldr r3, [r7, #4]
80041f4: 2201 movs r2, #1
80041f6: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80041fa: 687b ldr r3, [r7, #4]
80041fc: 2200 movs r2, #0
80041fe: f883 2020 strb.w r2, [r3, #32]
if (hdma->XferErrorCallback != NULL)
8004202: 687b ldr r3, [r7, #4]
8004204: 6b1b ldr r3, [r3, #48] @ 0x30
8004206: 2b00 cmp r3, #0
8004208: d004 beq.n 8004214 <HAL_DMA_IRQHandler+0x1e8>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
800420a: 687b ldr r3, [r7, #4]
800420c: 6b1b ldr r3, [r3, #48] @ 0x30
800420e: 6878 ldr r0, [r7, #4]
8004210: 4798 blx r3
}
}
return;
8004212: bf00 nop
8004214: bf00 nop
}
8004216: 3710 adds r7, #16
8004218: 46bd mov sp, r7
800421a: bd80 pop {r7, pc}
800421c: 40020008 .word 0x40020008
8004220: 4002001c .word 0x4002001c
8004224: 40020030 .word 0x40020030
8004228: 40020044 .word 0x40020044
800422c: 40020058 .word 0x40020058
8004230: 4002006c .word 0x4002006c
8004234: 40020000 .word 0x40020000
08004238 <DMA_SetConfig>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8004238: b480 push {r7}
800423a: b085 sub sp, #20
800423c: af00 add r7, sp, #0
800423e: 60f8 str r0, [r7, #12]
8004240: 60b9 str r1, [r7, #8]
8004242: 607a str r2, [r7, #4]
8004244: 603b str r3, [r7, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8004246: 68fb ldr r3, [r7, #12]
8004248: 6c1a ldr r2, [r3, #64] @ 0x40
800424a: 68fb ldr r3, [r7, #12]
800424c: 6bdb ldr r3, [r3, #60] @ 0x3c
800424e: 2101 movs r1, #1
8004250: fa01 f202 lsl.w r2, r1, r2
8004254: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8004256: 68fb ldr r3, [r7, #12]
8004258: 681b ldr r3, [r3, #0]
800425a: 683a ldr r2, [r7, #0]
800425c: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
800425e: 68fb ldr r3, [r7, #12]
8004260: 685b ldr r3, [r3, #4]
8004262: 2b10 cmp r3, #16
8004264: d108 bne.n 8004278 <DMA_SetConfig+0x40>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8004266: 68fb ldr r3, [r7, #12]
8004268: 681b ldr r3, [r3, #0]
800426a: 687a ldr r2, [r7, #4]
800426c: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
800426e: 68fb ldr r3, [r7, #12]
8004270: 681b ldr r3, [r3, #0]
8004272: 68ba ldr r2, [r7, #8]
8004274: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8004276: e007 b.n 8004288 <DMA_SetConfig+0x50>
hdma->Instance->CPAR = SrcAddress;
8004278: 68fb ldr r3, [r7, #12]
800427a: 681b ldr r3, [r3, #0]
800427c: 68ba ldr r2, [r7, #8]
800427e: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8004280: 68fb ldr r3, [r7, #12]
8004282: 681b ldr r3, [r3, #0]
8004284: 687a ldr r2, [r7, #4]
8004286: 60da str r2, [r3, #12]
}
8004288: bf00 nop
800428a: 3714 adds r7, #20
800428c: 46bd mov sp, r7
800428e: bc80 pop {r7}
8004290: 4770 bx lr
...
08004294 <HAL_FLASH_Program>:
* @param Data: Specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
8004294: b5f0 push {r4, r5, r6, r7, lr}
8004296: b087 sub sp, #28
8004298: af00 add r7, sp, #0
800429a: 60f8 str r0, [r7, #12]
800429c: 60b9 str r1, [r7, #8]
800429e: e9c7 2300 strd r2, r3, [r7]
HAL_StatusTypeDef status = HAL_ERROR;
80042a2: 2301 movs r3, #1
80042a4: 75fb strb r3, [r7, #23]
uint8_t index = 0;
80042a6: 2300 movs r3, #0
80042a8: 75bb strb r3, [r7, #22]
uint8_t nbiterations = 0;
80042aa: 2300 movs r3, #0
80042ac: 757b strb r3, [r7, #21]
/* Process Locked */
__HAL_LOCK(&pFlash);
80042ae: 4b2f ldr r3, [pc, #188] @ (800436c <HAL_FLASH_Program+0xd8>)
80042b0: 7e1b ldrb r3, [r3, #24]
80042b2: 2b01 cmp r3, #1
80042b4: d101 bne.n 80042ba <HAL_FLASH_Program+0x26>
80042b6: 2302 movs r3, #2
80042b8: e054 b.n 8004364 <HAL_FLASH_Program+0xd0>
80042ba: 4b2c ldr r3, [pc, #176] @ (800436c <HAL_FLASH_Program+0xd8>)
80042bc: 2201 movs r2, #1
80042be: 761a strb r2, [r3, #24]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
80042c0: f24c 3050 movw r0, #50000 @ 0xc350
80042c4: f000 f8a8 bl 8004418 <FLASH_WaitForLastOperation>
80042c8: 4603 mov r3, r0
80042ca: 75fb strb r3, [r7, #23]
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
if(status == HAL_OK)
80042cc: 7dfb ldrb r3, [r7, #23]
80042ce: 2b00 cmp r3, #0
80042d0: d144 bne.n 800435c <HAL_FLASH_Program+0xc8>
{
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
80042d2: 68fb ldr r3, [r7, #12]
80042d4: 2b01 cmp r3, #1
80042d6: d102 bne.n 80042de <HAL_FLASH_Program+0x4a>
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1U;
80042d8: 2301 movs r3, #1
80042da: 757b strb r3, [r7, #21]
80042dc: e007 b.n 80042ee <HAL_FLASH_Program+0x5a>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
80042de: 68fb ldr r3, [r7, #12]
80042e0: 2b02 cmp r3, #2
80042e2: d102 bne.n 80042ea <HAL_FLASH_Program+0x56>
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2U;
80042e4: 2302 movs r3, #2
80042e6: 757b strb r3, [r7, #21]
80042e8: e001 b.n 80042ee <HAL_FLASH_Program+0x5a>
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
nbiterations = 4U;
80042ea: 2304 movs r3, #4
80042ec: 757b strb r3, [r7, #21]
}
for (index = 0U; index < nbiterations; index++)
80042ee: 2300 movs r3, #0
80042f0: 75bb strb r3, [r7, #22]
80042f2: e02d b.n 8004350 <HAL_FLASH_Program+0xbc>
{
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
80042f4: 7dbb ldrb r3, [r7, #22]
80042f6: 005a lsls r2, r3, #1
80042f8: 68bb ldr r3, [r7, #8]
80042fa: eb02 0c03 add.w ip, r2, r3
80042fe: 7dbb ldrb r3, [r7, #22]
8004300: 0119 lsls r1, r3, #4
8004302: e9d7 2300 ldrd r2, r3, [r7]
8004306: f1c1 0620 rsb r6, r1, #32
800430a: f1a1 0020 sub.w r0, r1, #32
800430e: fa22 f401 lsr.w r4, r2, r1
8004312: fa03 f606 lsl.w r6, r3, r6
8004316: 4334 orrs r4, r6
8004318: fa23 f000 lsr.w r0, r3, r0
800431c: 4304 orrs r4, r0
800431e: fa23 f501 lsr.w r5, r3, r1
8004322: b2a3 uxth r3, r4
8004324: 4619 mov r1, r3
8004326: 4660 mov r0, ip
8004328: f000 f85a bl 80043e0 <FLASH_Program_HalfWord>
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
800432c: f24c 3050 movw r0, #50000 @ 0xc350
8004330: f000 f872 bl 8004418 <FLASH_WaitForLastOperation>
8004334: 4603 mov r3, r0
8004336: 75fb strb r3, [r7, #23]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
8004338: 4b0d ldr r3, [pc, #52] @ (8004370 <HAL_FLASH_Program+0xdc>)
800433a: 691b ldr r3, [r3, #16]
800433c: 4a0c ldr r2, [pc, #48] @ (8004370 <HAL_FLASH_Program+0xdc>)
800433e: f023 0301 bic.w r3, r3, #1
8004342: 6113 str r3, [r2, #16]
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* In case of error, stop programation procedure */
if (status != HAL_OK)
8004344: 7dfb ldrb r3, [r7, #23]
8004346: 2b00 cmp r3, #0
8004348: d107 bne.n 800435a <HAL_FLASH_Program+0xc6>
for (index = 0U; index < nbiterations; index++)
800434a: 7dbb ldrb r3, [r7, #22]
800434c: 3301 adds r3, #1
800434e: 75bb strb r3, [r7, #22]
8004350: 7dba ldrb r2, [r7, #22]
8004352: 7d7b ldrb r3, [r7, #21]
8004354: 429a cmp r2, r3
8004356: d3cd bcc.n 80042f4 <HAL_FLASH_Program+0x60>
8004358: e000 b.n 800435c <HAL_FLASH_Program+0xc8>
{
break;
800435a: bf00 nop
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
800435c: 4b03 ldr r3, [pc, #12] @ (800436c <HAL_FLASH_Program+0xd8>)
800435e: 2200 movs r2, #0
8004360: 761a strb r2, [r3, #24]
return status;
8004362: 7dfb ldrb r3, [r7, #23]
}
8004364: 4618 mov r0, r3
8004366: 371c adds r7, #28
8004368: 46bd mov sp, r7
800436a: bdf0 pop {r4, r5, r6, r7, pc}
800436c: 20000438 .word 0x20000438
8004370: 40022000 .word 0x40022000
08004374 <HAL_FLASH_Unlock>:
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
8004374: b480 push {r7}
8004376: b083 sub sp, #12
8004378: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
800437a: 2300 movs r3, #0
800437c: 71fb strb r3, [r7, #7]
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
800437e: 4b0d ldr r3, [pc, #52] @ (80043b4 <HAL_FLASH_Unlock+0x40>)
8004380: 691b ldr r3, [r3, #16]
8004382: f003 0380 and.w r3, r3, #128 @ 0x80
8004386: 2b00 cmp r3, #0
8004388: d00d beq.n 80043a6 <HAL_FLASH_Unlock+0x32>
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
800438a: 4b0a ldr r3, [pc, #40] @ (80043b4 <HAL_FLASH_Unlock+0x40>)
800438c: 4a0a ldr r2, [pc, #40] @ (80043b8 <HAL_FLASH_Unlock+0x44>)
800438e: 605a str r2, [r3, #4]
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
8004390: 4b08 ldr r3, [pc, #32] @ (80043b4 <HAL_FLASH_Unlock+0x40>)
8004392: 4a0a ldr r2, [pc, #40] @ (80043bc <HAL_FLASH_Unlock+0x48>)
8004394: 605a str r2, [r3, #4]
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
8004396: 4b07 ldr r3, [pc, #28] @ (80043b4 <HAL_FLASH_Unlock+0x40>)
8004398: 691b ldr r3, [r3, #16]
800439a: f003 0380 and.w r3, r3, #128 @ 0x80
800439e: 2b00 cmp r3, #0
80043a0: d001 beq.n 80043a6 <HAL_FLASH_Unlock+0x32>
{
status = HAL_ERROR;
80043a2: 2301 movs r3, #1
80043a4: 71fb strb r3, [r7, #7]
status = HAL_ERROR;
}
}
#endif /* FLASH_BANK2_END */
return status;
80043a6: 79fb ldrb r3, [r7, #7]
}
80043a8: 4618 mov r0, r3
80043aa: 370c adds r7, #12
80043ac: 46bd mov sp, r7
80043ae: bc80 pop {r7}
80043b0: 4770 bx lr
80043b2: bf00 nop
80043b4: 40022000 .word 0x40022000
80043b8: 45670123 .word 0x45670123
80043bc: cdef89ab .word 0xcdef89ab
080043c0 <HAL_FLASH_Lock>:
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
80043c0: b480 push {r7}
80043c2: af00 add r7, sp, #0
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
80043c4: 4b05 ldr r3, [pc, #20] @ (80043dc <HAL_FLASH_Lock+0x1c>)
80043c6: 691b ldr r3, [r3, #16]
80043c8: 4a04 ldr r2, [pc, #16] @ (80043dc <HAL_FLASH_Lock+0x1c>)
80043ca: f043 0380 orr.w r3, r3, #128 @ 0x80
80043ce: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
#endif /* FLASH_BANK2_END */
return HAL_OK;
80043d0: 2300 movs r3, #0
}
80043d2: 4618 mov r0, r3
80043d4: 46bd mov sp, r7
80043d6: bc80 pop {r7}
80043d8: 4770 bx lr
80043da: bf00 nop
80043dc: 40022000 .word 0x40022000
080043e0 <FLASH_Program_HalfWord>:
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
80043e0: b480 push {r7}
80043e2: b083 sub sp, #12
80043e4: af00 add r7, sp, #0
80043e6: 6078 str r0, [r7, #4]
80043e8: 460b mov r3, r1
80043ea: 807b strh r3, [r7, #2]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
80043ec: 4b08 ldr r3, [pc, #32] @ (8004410 <FLASH_Program_HalfWord+0x30>)
80043ee: 2200 movs r2, #0
80043f0: 61da str r2, [r3, #28]
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Proceed to program the new data */
SET_BIT(FLASH->CR, FLASH_CR_PG);
80043f2: 4b08 ldr r3, [pc, #32] @ (8004414 <FLASH_Program_HalfWord+0x34>)
80043f4: 691b ldr r3, [r3, #16]
80043f6: 4a07 ldr r2, [pc, #28] @ (8004414 <FLASH_Program_HalfWord+0x34>)
80043f8: f043 0301 orr.w r3, r3, #1
80043fc: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR2, FLASH_CR2_PG);
}
#endif /* FLASH_BANK2_END */
/* Write data in the address */
*(__IO uint16_t*)Address = Data;
80043fe: 687b ldr r3, [r7, #4]
8004400: 887a ldrh r2, [r7, #2]
8004402: 801a strh r2, [r3, #0]
}
8004404: bf00 nop
8004406: 370c adds r7, #12
8004408: 46bd mov sp, r7
800440a: bc80 pop {r7}
800440c: 4770 bx lr
800440e: bf00 nop
8004410: 20000438 .word 0x20000438
8004414: 40022000 .word 0x40022000
08004418 <FLASH_WaitForLastOperation>:
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
8004418: b580 push {r7, lr}
800441a: b084 sub sp, #16
800441c: af00 add r7, sp, #0
800441e: 6078 str r0, [r7, #4]
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
8004420: f7ff f860 bl 80034e4 <HAL_GetTick>
8004424: 60f8 str r0, [r7, #12]
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
8004426: e010 b.n 800444a <FLASH_WaitForLastOperation+0x32>
{
if (Timeout != HAL_MAX_DELAY)
8004428: 687b ldr r3, [r7, #4]
800442a: f1b3 3fff cmp.w r3, #4294967295
800442e: d00c beq.n 800444a <FLASH_WaitForLastOperation+0x32>
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
8004430: 687b ldr r3, [r7, #4]
8004432: 2b00 cmp r3, #0
8004434: d007 beq.n 8004446 <FLASH_WaitForLastOperation+0x2e>
8004436: f7ff f855 bl 80034e4 <HAL_GetTick>
800443a: 4602 mov r2, r0
800443c: 68fb ldr r3, [r7, #12]
800443e: 1ad3 subs r3, r2, r3
8004440: 687a ldr r2, [r7, #4]
8004442: 429a cmp r2, r3
8004444: d201 bcs.n 800444a <FLASH_WaitForLastOperation+0x32>
{
return HAL_TIMEOUT;
8004446: 2303 movs r3, #3
8004448: e025 b.n 8004496 <FLASH_WaitForLastOperation+0x7e>
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
800444a: 4b15 ldr r3, [pc, #84] @ (80044a0 <FLASH_WaitForLastOperation+0x88>)
800444c: 68db ldr r3, [r3, #12]
800444e: f003 0301 and.w r3, r3, #1
8004452: 2b00 cmp r3, #0
8004454: d1e8 bne.n 8004428 <FLASH_WaitForLastOperation+0x10>
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
8004456: 4b12 ldr r3, [pc, #72] @ (80044a0 <FLASH_WaitForLastOperation+0x88>)
8004458: 68db ldr r3, [r3, #12]
800445a: f003 0320 and.w r3, r3, #32
800445e: 2b00 cmp r3, #0
8004460: d002 beq.n 8004468 <FLASH_WaitForLastOperation+0x50>
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
8004462: 4b0f ldr r3, [pc, #60] @ (80044a0 <FLASH_WaitForLastOperation+0x88>)
8004464: 2220 movs r2, #32
8004466: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
8004468: 4b0d ldr r3, [pc, #52] @ (80044a0 <FLASH_WaitForLastOperation+0x88>)
800446a: 68db ldr r3, [r3, #12]
800446c: f003 0310 and.w r3, r3, #16
8004470: 2b00 cmp r3, #0
8004472: d10b bne.n 800448c <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
8004474: 4b0a ldr r3, [pc, #40] @ (80044a0 <FLASH_WaitForLastOperation+0x88>)
8004476: 69db ldr r3, [r3, #28]
8004478: f003 0301 and.w r3, r3, #1
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
800447c: 2b00 cmp r3, #0
800447e: d105 bne.n 800448c <FLASH_WaitForLastOperation+0x74>
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
8004480: 4b07 ldr r3, [pc, #28] @ (80044a0 <FLASH_WaitForLastOperation+0x88>)
8004482: 68db ldr r3, [r3, #12]
8004484: f003 0304 and.w r3, r3, #4
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
8004488: 2b00 cmp r3, #0
800448a: d003 beq.n 8004494 <FLASH_WaitForLastOperation+0x7c>
{
/*Save the error code*/
FLASH_SetErrorCode();
800448c: f000 f80a bl 80044a4 <FLASH_SetErrorCode>
return HAL_ERROR;
8004490: 2301 movs r3, #1
8004492: e000 b.n 8004496 <FLASH_WaitForLastOperation+0x7e>
}
/* There is no error flag set */
return HAL_OK;
8004494: 2300 movs r3, #0
}
8004496: 4618 mov r0, r3
8004498: 3710 adds r7, #16
800449a: 46bd mov sp, r7
800449c: bd80 pop {r7, pc}
800449e: bf00 nop
80044a0: 40022000 .word 0x40022000
080044a4 <FLASH_SetErrorCode>:
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
80044a4: b480 push {r7}
80044a6: b083 sub sp, #12
80044a8: af00 add r7, sp, #0
uint32_t flags = 0U;
80044aa: 2300 movs r3, #0
80044ac: 607b str r3, [r7, #4]
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
80044ae: 4b23 ldr r3, [pc, #140] @ (800453c <FLASH_SetErrorCode+0x98>)
80044b0: 68db ldr r3, [r3, #12]
80044b2: f003 0310 and.w r3, r3, #16
80044b6: 2b00 cmp r3, #0
80044b8: d009 beq.n 80044ce <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
80044ba: 4b21 ldr r3, [pc, #132] @ (8004540 <FLASH_SetErrorCode+0x9c>)
80044bc: 69db ldr r3, [r3, #28]
80044be: f043 0302 orr.w r3, r3, #2
80044c2: 4a1f ldr r2, [pc, #124] @ (8004540 <FLASH_SetErrorCode+0x9c>)
80044c4: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
flags |= FLASH_FLAG_WRPERR;
80044c6: 687b ldr r3, [r7, #4]
80044c8: f043 0310 orr.w r3, r3, #16
80044cc: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
80044ce: 4b1b ldr r3, [pc, #108] @ (800453c <FLASH_SetErrorCode+0x98>)
80044d0: 68db ldr r3, [r3, #12]
80044d2: f003 0304 and.w r3, r3, #4
80044d6: 2b00 cmp r3, #0
80044d8: d009 beq.n 80044ee <FLASH_SetErrorCode+0x4a>
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
80044da: 4b19 ldr r3, [pc, #100] @ (8004540 <FLASH_SetErrorCode+0x9c>)
80044dc: 69db ldr r3, [r3, #28]
80044de: f043 0301 orr.w r3, r3, #1
80044e2: 4a17 ldr r2, [pc, #92] @ (8004540 <FLASH_SetErrorCode+0x9c>)
80044e4: 61d3 str r3, [r2, #28]
#if defined(FLASH_BANK2_END)
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
flags |= FLASH_FLAG_PGERR;
80044e6: 687b ldr r3, [r7, #4]
80044e8: f043 0304 orr.w r3, r3, #4
80044ec: 607b str r3, [r7, #4]
#endif /* FLASH_BANK2_END */
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
80044ee: 4b13 ldr r3, [pc, #76] @ (800453c <FLASH_SetErrorCode+0x98>)
80044f0: 69db ldr r3, [r3, #28]
80044f2: f003 0301 and.w r3, r3, #1
80044f6: 2b00 cmp r3, #0
80044f8: d00b beq.n 8004512 <FLASH_SetErrorCode+0x6e>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
80044fa: 4b11 ldr r3, [pc, #68] @ (8004540 <FLASH_SetErrorCode+0x9c>)
80044fc: 69db ldr r3, [r3, #28]
80044fe: f043 0304 orr.w r3, r3, #4
8004502: 4a0f ldr r2, [pc, #60] @ (8004540 <FLASH_SetErrorCode+0x9c>)
8004504: 61d3 str r3, [r2, #28]
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
8004506: 4b0d ldr r3, [pc, #52] @ (800453c <FLASH_SetErrorCode+0x98>)
8004508: 69db ldr r3, [r3, #28]
800450a: 4a0c ldr r2, [pc, #48] @ (800453c <FLASH_SetErrorCode+0x98>)
800450c: f023 0301 bic.w r3, r3, #1
8004510: 61d3 str r3, [r2, #28]
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
8004512: 687b ldr r3, [r7, #4]
8004514: f240 1201 movw r2, #257 @ 0x101
8004518: 4293 cmp r3, r2
800451a: d106 bne.n 800452a <FLASH_SetErrorCode+0x86>
800451c: 4b07 ldr r3, [pc, #28] @ (800453c <FLASH_SetErrorCode+0x98>)
800451e: 69db ldr r3, [r3, #28]
8004520: 4a06 ldr r2, [pc, #24] @ (800453c <FLASH_SetErrorCode+0x98>)
8004522: f023 0301 bic.w r3, r3, #1
8004526: 61d3 str r3, [r2, #28]
}
8004528: e002 b.n 8004530 <FLASH_SetErrorCode+0x8c>
__HAL_FLASH_CLEAR_FLAG(flags);
800452a: 4a04 ldr r2, [pc, #16] @ (800453c <FLASH_SetErrorCode+0x98>)
800452c: 687b ldr r3, [r7, #4]
800452e: 60d3 str r3, [r2, #12]
}
8004530: bf00 nop
8004532: 370c adds r7, #12
8004534: 46bd mov sp, r7
8004536: bc80 pop {r7}
8004538: 4770 bx lr
800453a: bf00 nop
800453c: 40022000 .word 0x40022000
8004540: 20000438 .word 0x20000438
08004544 <HAL_FLASHEx_Erase>:
* (0xFFFFFFFF means that all the pages have been correctly erased)
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
8004544: b580 push {r7, lr}
8004546: b084 sub sp, #16
8004548: af00 add r7, sp, #0
800454a: 6078 str r0, [r7, #4]
800454c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_ERROR;
800454e: 2301 movs r3, #1
8004550: 73fb strb r3, [r7, #15]
uint32_t address = 0U;
8004552: 2300 movs r3, #0
8004554: 60bb str r3, [r7, #8]
/* Process Locked */
__HAL_LOCK(&pFlash);
8004556: 4b2f ldr r3, [pc, #188] @ (8004614 <HAL_FLASHEx_Erase+0xd0>)
8004558: 7e1b ldrb r3, [r3, #24]
800455a: 2b01 cmp r3, #1
800455c: d101 bne.n 8004562 <HAL_FLASHEx_Erase+0x1e>
800455e: 2302 movs r3, #2
8004560: e053 b.n 800460a <HAL_FLASHEx_Erase+0xc6>
8004562: 4b2c ldr r3, [pc, #176] @ (8004614 <HAL_FLASHEx_Erase+0xd0>)
8004564: 2201 movs r2, #1
8004566: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
8004568: 687b ldr r3, [r7, #4]
800456a: 681b ldr r3, [r3, #0]
800456c: 2b02 cmp r3, #2
800456e: d116 bne.n 800459e <HAL_FLASHEx_Erase+0x5a>
else
#endif /* FLASH_BANK2_END */
{
/* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
8004570: f24c 3050 movw r0, #50000 @ 0xc350
8004574: f7ff ff50 bl 8004418 <FLASH_WaitForLastOperation>
8004578: 4603 mov r3, r0
800457a: 2b00 cmp r3, #0
800457c: d141 bne.n 8004602 <HAL_FLASHEx_Erase+0xbe>
{
/*Mass erase to be done*/
FLASH_MassErase(FLASH_BANK_1);
800457e: 2001 movs r0, #1
8004580: f000 f84c bl 800461c <FLASH_MassErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8004584: f24c 3050 movw r0, #50000 @ 0xc350
8004588: f7ff ff46 bl 8004418 <FLASH_WaitForLastOperation>
800458c: 4603 mov r3, r0
800458e: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
8004590: 4b21 ldr r3, [pc, #132] @ (8004618 <HAL_FLASHEx_Erase+0xd4>)
8004592: 691b ldr r3, [r3, #16]
8004594: 4a20 ldr r2, [pc, #128] @ (8004618 <HAL_FLASHEx_Erase+0xd4>)
8004596: f023 0304 bic.w r3, r3, #4
800459a: 6113 str r3, [r2, #16]
800459c: e031 b.n 8004602 <HAL_FLASHEx_Erase+0xbe>
else
#endif /* FLASH_BANK2_END */
{
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
800459e: f24c 3050 movw r0, #50000 @ 0xc350
80045a2: f7ff ff39 bl 8004418 <FLASH_WaitForLastOperation>
80045a6: 4603 mov r3, r0
80045a8: 2b00 cmp r3, #0
80045aa: d12a bne.n 8004602 <HAL_FLASHEx_Erase+0xbe>
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
80045ac: 683b ldr r3, [r7, #0]
80045ae: f04f 32ff mov.w r2, #4294967295
80045b2: 601a str r2, [r3, #0]
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
80045b4: 687b ldr r3, [r7, #4]
80045b6: 689b ldr r3, [r3, #8]
80045b8: 60bb str r3, [r7, #8]
80045ba: e019 b.n 80045f0 <HAL_FLASHEx_Erase+0xac>
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
80045bc: 68b8 ldr r0, [r7, #8]
80045be: f000 f849 bl 8004654 <FLASH_PageErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
80045c2: f24c 3050 movw r0, #50000 @ 0xc350
80045c6: f7ff ff27 bl 8004418 <FLASH_WaitForLastOperation>
80045ca: 4603 mov r3, r0
80045cc: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
80045ce: 4b12 ldr r3, [pc, #72] @ (8004618 <HAL_FLASHEx_Erase+0xd4>)
80045d0: 691b ldr r3, [r3, #16]
80045d2: 4a11 ldr r2, [pc, #68] @ (8004618 <HAL_FLASHEx_Erase+0xd4>)
80045d4: f023 0302 bic.w r3, r3, #2
80045d8: 6113 str r3, [r2, #16]
if (status != HAL_OK)
80045da: 7bfb ldrb r3, [r7, #15]
80045dc: 2b00 cmp r3, #0
80045de: d003 beq.n 80045e8 <HAL_FLASHEx_Erase+0xa4>
{
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
80045e0: 683b ldr r3, [r7, #0]
80045e2: 68ba ldr r2, [r7, #8]
80045e4: 601a str r2, [r3, #0]
break;
80045e6: e00c b.n 8004602 <HAL_FLASHEx_Erase+0xbe>
address += FLASH_PAGE_SIZE)
80045e8: 68bb ldr r3, [r7, #8]
80045ea: f503 6380 add.w r3, r3, #1024 @ 0x400
80045ee: 60bb str r3, [r7, #8]
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
80045f0: 687b ldr r3, [r7, #4]
80045f2: 68db ldr r3, [r3, #12]
80045f4: 029a lsls r2, r3, #10
80045f6: 687b ldr r3, [r7, #4]
80045f8: 689b ldr r3, [r3, #8]
80045fa: 4413 add r3, r2
80045fc: 68ba ldr r2, [r7, #8]
80045fe: 429a cmp r2, r3
8004600: d3dc bcc.n 80045bc <HAL_FLASHEx_Erase+0x78>
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8004602: 4b04 ldr r3, [pc, #16] @ (8004614 <HAL_FLASHEx_Erase+0xd0>)
8004604: 2200 movs r2, #0
8004606: 761a strb r2, [r3, #24]
return status;
8004608: 7bfb ldrb r3, [r7, #15]
}
800460a: 4618 mov r0, r3
800460c: 3710 adds r7, #16
800460e: 46bd mov sp, r7
8004610: bd80 pop {r7, pc}
8004612: bf00 nop
8004614: 20000438 .word 0x20000438
8004618: 40022000 .word 0x40022000
0800461c <FLASH_MassErase>:
@endif
*
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
800461c: b480 push {r7}
800461e: b083 sub sp, #12
8004620: af00 add r7, sp, #0
8004622: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8004624: 4b09 ldr r3, [pc, #36] @ (800464c <FLASH_MassErase+0x30>)
8004626: 2200 movs r2, #0
8004628: 61da str r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH->CR, FLASH_CR_MER);
800462a: 4b09 ldr r3, [pc, #36] @ (8004650 <FLASH_MassErase+0x34>)
800462c: 691b ldr r3, [r3, #16]
800462e: 4a08 ldr r2, [pc, #32] @ (8004650 <FLASH_MassErase+0x34>)
8004630: f043 0304 orr.w r3, r3, #4
8004634: 6113 str r3, [r2, #16]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
8004636: 4b06 ldr r3, [pc, #24] @ (8004650 <FLASH_MassErase+0x34>)
8004638: 691b ldr r3, [r3, #16]
800463a: 4a05 ldr r2, [pc, #20] @ (8004650 <FLASH_MassErase+0x34>)
800463c: f043 0340 orr.w r3, r3, #64 @ 0x40
8004640: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8004642: bf00 nop
8004644: 370c adds r7, #12
8004646: 46bd mov sp, r7
8004648: bc80 pop {r7}
800464a: 4770 bx lr
800464c: 20000438 .word 0x20000438
8004650: 40022000 .word 0x40022000
08004654 <FLASH_PageErase>:
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)
{
8004654: b480 push {r7}
8004656: b083 sub sp, #12
8004658: af00 add r7, sp, #0
800465a: 6078 str r0, [r7, #4]
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
800465c: 4b0b ldr r3, [pc, #44] @ (800468c <FLASH_PageErase+0x38>)
800465e: 2200 movs r2, #0
8004660: 61da str r2, [r3, #28]
}
else
{
#endif /* FLASH_BANK2_END */
/* Proceed to erase the page */
SET_BIT(FLASH->CR, FLASH_CR_PER);
8004662: 4b0b ldr r3, [pc, #44] @ (8004690 <FLASH_PageErase+0x3c>)
8004664: 691b ldr r3, [r3, #16]
8004666: 4a0a ldr r2, [pc, #40] @ (8004690 <FLASH_PageErase+0x3c>)
8004668: f043 0302 orr.w r3, r3, #2
800466c: 6113 str r3, [r2, #16]
WRITE_REG(FLASH->AR, PageAddress);
800466e: 4a08 ldr r2, [pc, #32] @ (8004690 <FLASH_PageErase+0x3c>)
8004670: 687b ldr r3, [r7, #4]
8004672: 6153 str r3, [r2, #20]
SET_BIT(FLASH->CR, FLASH_CR_STRT);
8004674: 4b06 ldr r3, [pc, #24] @ (8004690 <FLASH_PageErase+0x3c>)
8004676: 691b ldr r3, [r3, #16]
8004678: 4a05 ldr r2, [pc, #20] @ (8004690 <FLASH_PageErase+0x3c>)
800467a: f043 0340 orr.w r3, r3, #64 @ 0x40
800467e: 6113 str r3, [r2, #16]
#if defined(FLASH_BANK2_END)
}
#endif /* FLASH_BANK2_END */
}
8004680: bf00 nop
8004682: 370c adds r7, #12
8004684: 46bd mov sp, r7
8004686: bc80 pop {r7}
8004688: 4770 bx lr
800468a: bf00 nop
800468c: 20000438 .word 0x20000438
8004690: 40022000 .word 0x40022000
08004694 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8004694: b480 push {r7}
8004696: b08b sub sp, #44 @ 0x2c
8004698: af00 add r7, sp, #0
800469a: 6078 str r0, [r7, #4]
800469c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800469e: 2300 movs r3, #0
80046a0: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
80046a2: 2300 movs r3, #0
80046a4: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80046a6: e169 b.n 800497c <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
80046a8: 2201 movs r2, #1
80046aa: 6a7b ldr r3, [r7, #36] @ 0x24
80046ac: fa02 f303 lsl.w r3, r2, r3
80046b0: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80046b2: 683b ldr r3, [r7, #0]
80046b4: 681b ldr r3, [r3, #0]
80046b6: 69fa ldr r2, [r7, #28]
80046b8: 4013 ands r3, r2
80046ba: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
80046bc: 69ba ldr r2, [r7, #24]
80046be: 69fb ldr r3, [r7, #28]
80046c0: 429a cmp r2, r3
80046c2: f040 8158 bne.w 8004976 <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
80046c6: 683b ldr r3, [r7, #0]
80046c8: 685b ldr r3, [r3, #4]
80046ca: 4a9a ldr r2, [pc, #616] @ (8004934 <HAL_GPIO_Init+0x2a0>)
80046cc: 4293 cmp r3, r2
80046ce: d05e beq.n 800478e <HAL_GPIO_Init+0xfa>
80046d0: 4a98 ldr r2, [pc, #608] @ (8004934 <HAL_GPIO_Init+0x2a0>)
80046d2: 4293 cmp r3, r2
80046d4: d875 bhi.n 80047c2 <HAL_GPIO_Init+0x12e>
80046d6: 4a98 ldr r2, [pc, #608] @ (8004938 <HAL_GPIO_Init+0x2a4>)
80046d8: 4293 cmp r3, r2
80046da: d058 beq.n 800478e <HAL_GPIO_Init+0xfa>
80046dc: 4a96 ldr r2, [pc, #600] @ (8004938 <HAL_GPIO_Init+0x2a4>)
80046de: 4293 cmp r3, r2
80046e0: d86f bhi.n 80047c2 <HAL_GPIO_Init+0x12e>
80046e2: 4a96 ldr r2, [pc, #600] @ (800493c <HAL_GPIO_Init+0x2a8>)
80046e4: 4293 cmp r3, r2
80046e6: d052 beq.n 800478e <HAL_GPIO_Init+0xfa>
80046e8: 4a94 ldr r2, [pc, #592] @ (800493c <HAL_GPIO_Init+0x2a8>)
80046ea: 4293 cmp r3, r2
80046ec: d869 bhi.n 80047c2 <HAL_GPIO_Init+0x12e>
80046ee: 4a94 ldr r2, [pc, #592] @ (8004940 <HAL_GPIO_Init+0x2ac>)
80046f0: 4293 cmp r3, r2
80046f2: d04c beq.n 800478e <HAL_GPIO_Init+0xfa>
80046f4: 4a92 ldr r2, [pc, #584] @ (8004940 <HAL_GPIO_Init+0x2ac>)
80046f6: 4293 cmp r3, r2
80046f8: d863 bhi.n 80047c2 <HAL_GPIO_Init+0x12e>
80046fa: 4a92 ldr r2, [pc, #584] @ (8004944 <HAL_GPIO_Init+0x2b0>)
80046fc: 4293 cmp r3, r2
80046fe: d046 beq.n 800478e <HAL_GPIO_Init+0xfa>
8004700: 4a90 ldr r2, [pc, #576] @ (8004944 <HAL_GPIO_Init+0x2b0>)
8004702: 4293 cmp r3, r2
8004704: d85d bhi.n 80047c2 <HAL_GPIO_Init+0x12e>
8004706: 2b12 cmp r3, #18
8004708: d82a bhi.n 8004760 <HAL_GPIO_Init+0xcc>
800470a: 2b12 cmp r3, #18
800470c: d859 bhi.n 80047c2 <HAL_GPIO_Init+0x12e>
800470e: a201 add r2, pc, #4 @ (adr r2, 8004714 <HAL_GPIO_Init+0x80>)
8004710: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004714: 0800478f .word 0x0800478f
8004718: 08004769 .word 0x08004769
800471c: 0800477b .word 0x0800477b
8004720: 080047bd .word 0x080047bd
8004724: 080047c3 .word 0x080047c3
8004728: 080047c3 .word 0x080047c3
800472c: 080047c3 .word 0x080047c3
8004730: 080047c3 .word 0x080047c3
8004734: 080047c3 .word 0x080047c3
8004738: 080047c3 .word 0x080047c3
800473c: 080047c3 .word 0x080047c3
8004740: 080047c3 .word 0x080047c3
8004744: 080047c3 .word 0x080047c3
8004748: 080047c3 .word 0x080047c3
800474c: 080047c3 .word 0x080047c3
8004750: 080047c3 .word 0x080047c3
8004754: 080047c3 .word 0x080047c3
8004758: 08004771 .word 0x08004771
800475c: 08004785 .word 0x08004785
8004760: 4a79 ldr r2, [pc, #484] @ (8004948 <HAL_GPIO_Init+0x2b4>)
8004762: 4293 cmp r3, r2
8004764: d013 beq.n 800478e <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8004766: e02c b.n 80047c2 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8004768: 683b ldr r3, [r7, #0]
800476a: 68db ldr r3, [r3, #12]
800476c: 623b str r3, [r7, #32]
break;
800476e: e029 b.n 80047c4 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8004770: 683b ldr r3, [r7, #0]
8004772: 68db ldr r3, [r3, #12]
8004774: 3304 adds r3, #4
8004776: 623b str r3, [r7, #32]
break;
8004778: e024 b.n 80047c4 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
800477a: 683b ldr r3, [r7, #0]
800477c: 68db ldr r3, [r3, #12]
800477e: 3308 adds r3, #8
8004780: 623b str r3, [r7, #32]
break;
8004782: e01f b.n 80047c4 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8004784: 683b ldr r3, [r7, #0]
8004786: 68db ldr r3, [r3, #12]
8004788: 330c adds r3, #12
800478a: 623b str r3, [r7, #32]
break;
800478c: e01a b.n 80047c4 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
800478e: 683b ldr r3, [r7, #0]
8004790: 689b ldr r3, [r3, #8]
8004792: 2b00 cmp r3, #0
8004794: d102 bne.n 800479c <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8004796: 2304 movs r3, #4
8004798: 623b str r3, [r7, #32]
break;
800479a: e013 b.n 80047c4 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
800479c: 683b ldr r3, [r7, #0]
800479e: 689b ldr r3, [r3, #8]
80047a0: 2b01 cmp r3, #1
80047a2: d105 bne.n 80047b0 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
80047a4: 2308 movs r3, #8
80047a6: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
80047a8: 687b ldr r3, [r7, #4]
80047aa: 69fa ldr r2, [r7, #28]
80047ac: 611a str r2, [r3, #16]
break;
80047ae: e009 b.n 80047c4 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
80047b0: 2308 movs r3, #8
80047b2: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
80047b4: 687b ldr r3, [r7, #4]
80047b6: 69fa ldr r2, [r7, #28]
80047b8: 615a str r2, [r3, #20]
break;
80047ba: e003 b.n 80047c4 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
80047bc: 2300 movs r3, #0
80047be: 623b str r3, [r7, #32]
break;
80047c0: e000 b.n 80047c4 <HAL_GPIO_Init+0x130>
break;
80047c2: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
80047c4: 69bb ldr r3, [r7, #24]
80047c6: 2bff cmp r3, #255 @ 0xff
80047c8: d801 bhi.n 80047ce <HAL_GPIO_Init+0x13a>
80047ca: 687b ldr r3, [r7, #4]
80047cc: e001 b.n 80047d2 <HAL_GPIO_Init+0x13e>
80047ce: 687b ldr r3, [r7, #4]
80047d0: 3304 adds r3, #4
80047d2: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
80047d4: 69bb ldr r3, [r7, #24]
80047d6: 2bff cmp r3, #255 @ 0xff
80047d8: d802 bhi.n 80047e0 <HAL_GPIO_Init+0x14c>
80047da: 6a7b ldr r3, [r7, #36] @ 0x24
80047dc: 009b lsls r3, r3, #2
80047de: e002 b.n 80047e6 <HAL_GPIO_Init+0x152>
80047e0: 6a7b ldr r3, [r7, #36] @ 0x24
80047e2: 3b08 subs r3, #8
80047e4: 009b lsls r3, r3, #2
80047e6: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80047e8: 697b ldr r3, [r7, #20]
80047ea: 681a ldr r2, [r3, #0]
80047ec: 210f movs r1, #15
80047ee: 693b ldr r3, [r7, #16]
80047f0: fa01 f303 lsl.w r3, r1, r3
80047f4: 43db mvns r3, r3
80047f6: 401a ands r2, r3
80047f8: 6a39 ldr r1, [r7, #32]
80047fa: 693b ldr r3, [r7, #16]
80047fc: fa01 f303 lsl.w r3, r1, r3
8004800: 431a orrs r2, r3
8004802: 697b ldr r3, [r7, #20]
8004804: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8004806: 683b ldr r3, [r7, #0]
8004808: 685b ldr r3, [r3, #4]
800480a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800480e: 2b00 cmp r3, #0
8004810: f000 80b1 beq.w 8004976 <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8004814: 4b4d ldr r3, [pc, #308] @ (800494c <HAL_GPIO_Init+0x2b8>)
8004816: 699b ldr r3, [r3, #24]
8004818: 4a4c ldr r2, [pc, #304] @ (800494c <HAL_GPIO_Init+0x2b8>)
800481a: f043 0301 orr.w r3, r3, #1
800481e: 6193 str r3, [r2, #24]
8004820: 4b4a ldr r3, [pc, #296] @ (800494c <HAL_GPIO_Init+0x2b8>)
8004822: 699b ldr r3, [r3, #24]
8004824: f003 0301 and.w r3, r3, #1
8004828: 60bb str r3, [r7, #8]
800482a: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
800482c: 4a48 ldr r2, [pc, #288] @ (8004950 <HAL_GPIO_Init+0x2bc>)
800482e: 6a7b ldr r3, [r7, #36] @ 0x24
8004830: 089b lsrs r3, r3, #2
8004832: 3302 adds r3, #2
8004834: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8004838: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
800483a: 6a7b ldr r3, [r7, #36] @ 0x24
800483c: f003 0303 and.w r3, r3, #3
8004840: 009b lsls r3, r3, #2
8004842: 220f movs r2, #15
8004844: fa02 f303 lsl.w r3, r2, r3
8004848: 43db mvns r3, r3
800484a: 68fa ldr r2, [r7, #12]
800484c: 4013 ands r3, r2
800484e: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8004850: 687b ldr r3, [r7, #4]
8004852: 4a40 ldr r2, [pc, #256] @ (8004954 <HAL_GPIO_Init+0x2c0>)
8004854: 4293 cmp r3, r2
8004856: d013 beq.n 8004880 <HAL_GPIO_Init+0x1ec>
8004858: 687b ldr r3, [r7, #4]
800485a: 4a3f ldr r2, [pc, #252] @ (8004958 <HAL_GPIO_Init+0x2c4>)
800485c: 4293 cmp r3, r2
800485e: d00d beq.n 800487c <HAL_GPIO_Init+0x1e8>
8004860: 687b ldr r3, [r7, #4]
8004862: 4a3e ldr r2, [pc, #248] @ (800495c <HAL_GPIO_Init+0x2c8>)
8004864: 4293 cmp r3, r2
8004866: d007 beq.n 8004878 <HAL_GPIO_Init+0x1e4>
8004868: 687b ldr r3, [r7, #4]
800486a: 4a3d ldr r2, [pc, #244] @ (8004960 <HAL_GPIO_Init+0x2cc>)
800486c: 4293 cmp r3, r2
800486e: d101 bne.n 8004874 <HAL_GPIO_Init+0x1e0>
8004870: 2303 movs r3, #3
8004872: e006 b.n 8004882 <HAL_GPIO_Init+0x1ee>
8004874: 2304 movs r3, #4
8004876: e004 b.n 8004882 <HAL_GPIO_Init+0x1ee>
8004878: 2302 movs r3, #2
800487a: e002 b.n 8004882 <HAL_GPIO_Init+0x1ee>
800487c: 2301 movs r3, #1
800487e: e000 b.n 8004882 <HAL_GPIO_Init+0x1ee>
8004880: 2300 movs r3, #0
8004882: 6a7a ldr r2, [r7, #36] @ 0x24
8004884: f002 0203 and.w r2, r2, #3
8004888: 0092 lsls r2, r2, #2
800488a: 4093 lsls r3, r2
800488c: 68fa ldr r2, [r7, #12]
800488e: 4313 orrs r3, r2
8004890: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8004892: 492f ldr r1, [pc, #188] @ (8004950 <HAL_GPIO_Init+0x2bc>)
8004894: 6a7b ldr r3, [r7, #36] @ 0x24
8004896: 089b lsrs r3, r3, #2
8004898: 3302 adds r3, #2
800489a: 68fa ldr r2, [r7, #12]
800489c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
80048a0: 683b ldr r3, [r7, #0]
80048a2: 685b ldr r3, [r3, #4]
80048a4: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80048a8: 2b00 cmp r3, #0
80048aa: d006 beq.n 80048ba <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
80048ac: 4b2d ldr r3, [pc, #180] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048ae: 689a ldr r2, [r3, #8]
80048b0: 492c ldr r1, [pc, #176] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048b2: 69bb ldr r3, [r7, #24]
80048b4: 4313 orrs r3, r2
80048b6: 608b str r3, [r1, #8]
80048b8: e006 b.n 80048c8 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
80048ba: 4b2a ldr r3, [pc, #168] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048bc: 689a ldr r2, [r3, #8]
80048be: 69bb ldr r3, [r7, #24]
80048c0: 43db mvns r3, r3
80048c2: 4928 ldr r1, [pc, #160] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048c4: 4013 ands r3, r2
80048c6: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
80048c8: 683b ldr r3, [r7, #0]
80048ca: 685b ldr r3, [r3, #4]
80048cc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80048d0: 2b00 cmp r3, #0
80048d2: d006 beq.n 80048e2 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
80048d4: 4b23 ldr r3, [pc, #140] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048d6: 68da ldr r2, [r3, #12]
80048d8: 4922 ldr r1, [pc, #136] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048da: 69bb ldr r3, [r7, #24]
80048dc: 4313 orrs r3, r2
80048de: 60cb str r3, [r1, #12]
80048e0: e006 b.n 80048f0 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
80048e2: 4b20 ldr r3, [pc, #128] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048e4: 68da ldr r2, [r3, #12]
80048e6: 69bb ldr r3, [r7, #24]
80048e8: 43db mvns r3, r3
80048ea: 491e ldr r1, [pc, #120] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048ec: 4013 ands r3, r2
80048ee: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
80048f0: 683b ldr r3, [r7, #0]
80048f2: 685b ldr r3, [r3, #4]
80048f4: f403 3300 and.w r3, r3, #131072 @ 0x20000
80048f8: 2b00 cmp r3, #0
80048fa: d006 beq.n 800490a <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
80048fc: 4b19 ldr r3, [pc, #100] @ (8004964 <HAL_GPIO_Init+0x2d0>)
80048fe: 685a ldr r2, [r3, #4]
8004900: 4918 ldr r1, [pc, #96] @ (8004964 <HAL_GPIO_Init+0x2d0>)
8004902: 69bb ldr r3, [r7, #24]
8004904: 4313 orrs r3, r2
8004906: 604b str r3, [r1, #4]
8004908: e006 b.n 8004918 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
800490a: 4b16 ldr r3, [pc, #88] @ (8004964 <HAL_GPIO_Init+0x2d0>)
800490c: 685a ldr r2, [r3, #4]
800490e: 69bb ldr r3, [r7, #24]
8004910: 43db mvns r3, r3
8004912: 4914 ldr r1, [pc, #80] @ (8004964 <HAL_GPIO_Init+0x2d0>)
8004914: 4013 ands r3, r2
8004916: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8004918: 683b ldr r3, [r7, #0]
800491a: 685b ldr r3, [r3, #4]
800491c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004920: 2b00 cmp r3, #0
8004922: d021 beq.n 8004968 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
8004924: 4b0f ldr r3, [pc, #60] @ (8004964 <HAL_GPIO_Init+0x2d0>)
8004926: 681a ldr r2, [r3, #0]
8004928: 490e ldr r1, [pc, #56] @ (8004964 <HAL_GPIO_Init+0x2d0>)
800492a: 69bb ldr r3, [r7, #24]
800492c: 4313 orrs r3, r2
800492e: 600b str r3, [r1, #0]
8004930: e021 b.n 8004976 <HAL_GPIO_Init+0x2e2>
8004932: bf00 nop
8004934: 10320000 .word 0x10320000
8004938: 10310000 .word 0x10310000
800493c: 10220000 .word 0x10220000
8004940: 10210000 .word 0x10210000
8004944: 10120000 .word 0x10120000
8004948: 10110000 .word 0x10110000
800494c: 40021000 .word 0x40021000
8004950: 40010000 .word 0x40010000
8004954: 40010800 .word 0x40010800
8004958: 40010c00 .word 0x40010c00
800495c: 40011000 .word 0x40011000
8004960: 40011400 .word 0x40011400
8004964: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8004968: 4b0b ldr r3, [pc, #44] @ (8004998 <HAL_GPIO_Init+0x304>)
800496a: 681a ldr r2, [r3, #0]
800496c: 69bb ldr r3, [r7, #24]
800496e: 43db mvns r3, r3
8004970: 4909 ldr r1, [pc, #36] @ (8004998 <HAL_GPIO_Init+0x304>)
8004972: 4013 ands r3, r2
8004974: 600b str r3, [r1, #0]
}
}
}
position++;
8004976: 6a7b ldr r3, [r7, #36] @ 0x24
8004978: 3301 adds r3, #1
800497a: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
800497c: 683b ldr r3, [r7, #0]
800497e: 681a ldr r2, [r3, #0]
8004980: 6a7b ldr r3, [r7, #36] @ 0x24
8004982: fa22 f303 lsr.w r3, r2, r3
8004986: 2b00 cmp r3, #0
8004988: f47f ae8e bne.w 80046a8 <HAL_GPIO_Init+0x14>
}
}
800498c: bf00 nop
800498e: bf00 nop
8004990: 372c adds r7, #44 @ 0x2c
8004992: 46bd mov sp, r7
8004994: bc80 pop {r7}
8004996: 4770 bx lr
8004998: 40010400 .word 0x40010400
0800499c <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
800499c: b480 push {r7}
800499e: b085 sub sp, #20
80049a0: af00 add r7, sp, #0
80049a2: 6078 str r0, [r7, #4]
80049a4: 460b mov r3, r1
80049a6: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
80049a8: 687b ldr r3, [r7, #4]
80049aa: 689a ldr r2, [r3, #8]
80049ac: 887b ldrh r3, [r7, #2]
80049ae: 4013 ands r3, r2
80049b0: 2b00 cmp r3, #0
80049b2: d002 beq.n 80049ba <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
80049b4: 2301 movs r3, #1
80049b6: 73fb strb r3, [r7, #15]
80049b8: e001 b.n 80049be <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
80049ba: 2300 movs r3, #0
80049bc: 73fb strb r3, [r7, #15]
}
return bitstatus;
80049be: 7bfb ldrb r3, [r7, #15]
}
80049c0: 4618 mov r0, r3
80049c2: 3714 adds r7, #20
80049c4: 46bd mov sp, r7
80049c6: bc80 pop {r7}
80049c8: 4770 bx lr
080049ca <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80049ca: b480 push {r7}
80049cc: b083 sub sp, #12
80049ce: af00 add r7, sp, #0
80049d0: 6078 str r0, [r7, #4]
80049d2: 460b mov r3, r1
80049d4: 807b strh r3, [r7, #2]
80049d6: 4613 mov r3, r2
80049d8: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80049da: 787b ldrb r3, [r7, #1]
80049dc: 2b00 cmp r3, #0
80049de: d003 beq.n 80049e8 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80049e0: 887a ldrh r2, [r7, #2]
80049e2: 687b ldr r3, [r7, #4]
80049e4: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
80049e6: e003 b.n 80049f0 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
80049e8: 887b ldrh r3, [r7, #2]
80049ea: 041a lsls r2, r3, #16
80049ec: 687b ldr r3, [r7, #4]
80049ee: 611a str r2, [r3, #16]
}
80049f0: bf00 nop
80049f2: 370c adds r7, #12
80049f4: 46bd mov sp, r7
80049f6: bc80 pop {r7}
80049f8: 4770 bx lr
080049fa <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80049fa: b480 push {r7}
80049fc: b085 sub sp, #20
80049fe: af00 add r7, sp, #0
8004a00: 6078 str r0, [r7, #4]
8004a02: 460b mov r3, r1
8004a04: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8004a06: 687b ldr r3, [r7, #4]
8004a08: 68db ldr r3, [r3, #12]
8004a0a: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8004a0c: 887a ldrh r2, [r7, #2]
8004a0e: 68fb ldr r3, [r7, #12]
8004a10: 4013 ands r3, r2
8004a12: 041a lsls r2, r3, #16
8004a14: 68fb ldr r3, [r7, #12]
8004a16: 43d9 mvns r1, r3
8004a18: 887b ldrh r3, [r7, #2]
8004a1a: 400b ands r3, r1
8004a1c: 431a orrs r2, r3
8004a1e: 687b ldr r3, [r7, #4]
8004a20: 611a str r2, [r3, #16]
}
8004a22: bf00 nop
8004a24: 3714 adds r7, #20
8004a26: 46bd mov sp, r7
8004a28: bc80 pop {r7}
8004a2a: 4770 bx lr
08004a2c <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8004a2c: b580 push {r7, lr}
8004a2e: b084 sub sp, #16
8004a30: af00 add r7, sp, #0
8004a32: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
8004a34: 687b ldr r3, [r7, #4]
8004a36: 2b00 cmp r3, #0
8004a38: d101 bne.n 8004a3e <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8004a3a: 2301 movs r3, #1
8004a3c: e0e8 b.n 8004c10 <HAL_PCD_Init+0x1e4>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8004a3e: 687b ldr r3, [r7, #4]
8004a40: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
8004a44: b2db uxtb r3, r3
8004a46: 2b00 cmp r3, #0
8004a48: d106 bne.n 8004a58 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8004a4a: 687b ldr r3, [r7, #4]
8004a4c: 2200 movs r2, #0
8004a4e: f883 2290 strb.w r2, [r3, #656] @ 0x290
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
8004a52: 6878 ldr r0, [r7, #4]
8004a54: f007 fad0 bl 800bff8 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8004a58: 687b ldr r3, [r7, #4]
8004a5a: 2203 movs r2, #3
8004a5c: f883 2291 strb.w r2, [r3, #657] @ 0x291
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
8004a60: 687b ldr r3, [r7, #4]
8004a62: 2200 movs r2, #0
8004a64: 715a strb r2, [r3, #5]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8004a66: 687b ldr r3, [r7, #4]
8004a68: 681b ldr r3, [r3, #0]
8004a6a: 4618 mov r0, r3
8004a6c: f003 f975 bl 8007d5a <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8004a70: 687b ldr r3, [r7, #4]
8004a72: 6818 ldr r0, [r3, #0]
8004a74: 687b ldr r3, [r7, #4]
8004a76: 3304 adds r3, #4
8004a78: cb0e ldmia r3, {r1, r2, r3}
8004a7a: f003 f94b bl 8007d14 <USB_CoreInit>
8004a7e: 4603 mov r3, r0
8004a80: 2b00 cmp r3, #0
8004a82: d005 beq.n 8004a90 <HAL_PCD_Init+0x64>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8004a84: 687b ldr r3, [r7, #4]
8004a86: 2202 movs r2, #2
8004a88: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8004a8c: 2301 movs r3, #1
8004a8e: e0bf b.n 8004c10 <HAL_PCD_Init+0x1e4>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
8004a90: 687b ldr r3, [r7, #4]
8004a92: 681b ldr r3, [r3, #0]
8004a94: 2100 movs r1, #0
8004a96: 4618 mov r0, r3
8004a98: f003 f979 bl 8007d8e <USB_SetCurrentMode>
8004a9c: 4603 mov r3, r0
8004a9e: 2b00 cmp r3, #0
8004aa0: d005 beq.n 8004aae <HAL_PCD_Init+0x82>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8004aa2: 687b ldr r3, [r7, #4]
8004aa4: 2202 movs r2, #2
8004aa6: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8004aaa: 2301 movs r3, #1
8004aac: e0b0 b.n 8004c10 <HAL_PCD_Init+0x1e4>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8004aae: 2300 movs r3, #0
8004ab0: 73fb strb r3, [r7, #15]
8004ab2: e03e b.n 8004b32 <HAL_PCD_Init+0x106>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
8004ab4: 7bfa ldrb r2, [r7, #15]
8004ab6: 6879 ldr r1, [r7, #4]
8004ab8: 4613 mov r3, r2
8004aba: 009b lsls r3, r3, #2
8004abc: 4413 add r3, r2
8004abe: 00db lsls r3, r3, #3
8004ac0: 440b add r3, r1
8004ac2: 3311 adds r3, #17
8004ac4: 2201 movs r2, #1
8004ac6: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8004ac8: 7bfa ldrb r2, [r7, #15]
8004aca: 6879 ldr r1, [r7, #4]
8004acc: 4613 mov r3, r2
8004ace: 009b lsls r3, r3, #2
8004ad0: 4413 add r3, r2
8004ad2: 00db lsls r3, r3, #3
8004ad4: 440b add r3, r1
8004ad6: 3310 adds r3, #16
8004ad8: 7bfa ldrb r2, [r7, #15]
8004ada: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8004adc: 7bfa ldrb r2, [r7, #15]
8004ade: 6879 ldr r1, [r7, #4]
8004ae0: 4613 mov r3, r2
8004ae2: 009b lsls r3, r3, #2
8004ae4: 4413 add r3, r2
8004ae6: 00db lsls r3, r3, #3
8004ae8: 440b add r3, r1
8004aea: 3313 adds r3, #19
8004aec: 2200 movs r2, #0
8004aee: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
8004af0: 7bfa ldrb r2, [r7, #15]
8004af2: 6879 ldr r1, [r7, #4]
8004af4: 4613 mov r3, r2
8004af6: 009b lsls r3, r3, #2
8004af8: 4413 add r3, r2
8004afa: 00db lsls r3, r3, #3
8004afc: 440b add r3, r1
8004afe: 3320 adds r3, #32
8004b00: 2200 movs r2, #0
8004b02: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
8004b04: 7bfa ldrb r2, [r7, #15]
8004b06: 6879 ldr r1, [r7, #4]
8004b08: 4613 mov r3, r2
8004b0a: 009b lsls r3, r3, #2
8004b0c: 4413 add r3, r2
8004b0e: 00db lsls r3, r3, #3
8004b10: 440b add r3, r1
8004b12: 3324 adds r3, #36 @ 0x24
8004b14: 2200 movs r2, #0
8004b16: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8004b18: 7bfb ldrb r3, [r7, #15]
8004b1a: 6879 ldr r1, [r7, #4]
8004b1c: 1c5a adds r2, r3, #1
8004b1e: 4613 mov r3, r2
8004b20: 009b lsls r3, r3, #2
8004b22: 4413 add r3, r2
8004b24: 00db lsls r3, r3, #3
8004b26: 440b add r3, r1
8004b28: 2200 movs r2, #0
8004b2a: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8004b2c: 7bfb ldrb r3, [r7, #15]
8004b2e: 3301 adds r3, #1
8004b30: 73fb strb r3, [r7, #15]
8004b32: 687b ldr r3, [r7, #4]
8004b34: 791b ldrb r3, [r3, #4]
8004b36: 7bfa ldrb r2, [r7, #15]
8004b38: 429a cmp r2, r3
8004b3a: d3bb bcc.n 8004ab4 <HAL_PCD_Init+0x88>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8004b3c: 2300 movs r3, #0
8004b3e: 73fb strb r3, [r7, #15]
8004b40: e044 b.n 8004bcc <HAL_PCD_Init+0x1a0>
{
hpcd->OUT_ep[i].is_in = 0U;
8004b42: 7bfa ldrb r2, [r7, #15]
8004b44: 6879 ldr r1, [r7, #4]
8004b46: 4613 mov r3, r2
8004b48: 009b lsls r3, r3, #2
8004b4a: 4413 add r3, r2
8004b4c: 00db lsls r3, r3, #3
8004b4e: 440b add r3, r1
8004b50: f203 1351 addw r3, r3, #337 @ 0x151
8004b54: 2200 movs r2, #0
8004b56: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8004b58: 7bfa ldrb r2, [r7, #15]
8004b5a: 6879 ldr r1, [r7, #4]
8004b5c: 4613 mov r3, r2
8004b5e: 009b lsls r3, r3, #2
8004b60: 4413 add r3, r2
8004b62: 00db lsls r3, r3, #3
8004b64: 440b add r3, r1
8004b66: f503 73a8 add.w r3, r3, #336 @ 0x150
8004b6a: 7bfa ldrb r2, [r7, #15]
8004b6c: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8004b6e: 7bfa ldrb r2, [r7, #15]
8004b70: 6879 ldr r1, [r7, #4]
8004b72: 4613 mov r3, r2
8004b74: 009b lsls r3, r3, #2
8004b76: 4413 add r3, r2
8004b78: 00db lsls r3, r3, #3
8004b7a: 440b add r3, r1
8004b7c: f203 1353 addw r3, r3, #339 @ 0x153
8004b80: 2200 movs r2, #0
8004b82: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
8004b84: 7bfa ldrb r2, [r7, #15]
8004b86: 6879 ldr r1, [r7, #4]
8004b88: 4613 mov r3, r2
8004b8a: 009b lsls r3, r3, #2
8004b8c: 4413 add r3, r2
8004b8e: 00db lsls r3, r3, #3
8004b90: 440b add r3, r1
8004b92: f503 73b0 add.w r3, r3, #352 @ 0x160
8004b96: 2200 movs r2, #0
8004b98: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8004b9a: 7bfa ldrb r2, [r7, #15]
8004b9c: 6879 ldr r1, [r7, #4]
8004b9e: 4613 mov r3, r2
8004ba0: 009b lsls r3, r3, #2
8004ba2: 4413 add r3, r2
8004ba4: 00db lsls r3, r3, #3
8004ba6: 440b add r3, r1
8004ba8: f503 73b2 add.w r3, r3, #356 @ 0x164
8004bac: 2200 movs r2, #0
8004bae: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8004bb0: 7bfa ldrb r2, [r7, #15]
8004bb2: 6879 ldr r1, [r7, #4]
8004bb4: 4613 mov r3, r2
8004bb6: 009b lsls r3, r3, #2
8004bb8: 4413 add r3, r2
8004bba: 00db lsls r3, r3, #3
8004bbc: 440b add r3, r1
8004bbe: f503 73b4 add.w r3, r3, #360 @ 0x168
8004bc2: 2200 movs r2, #0
8004bc4: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8004bc6: 7bfb ldrb r3, [r7, #15]
8004bc8: 3301 adds r3, #1
8004bca: 73fb strb r3, [r7, #15]
8004bcc: 687b ldr r3, [r7, #4]
8004bce: 791b ldrb r3, [r3, #4]
8004bd0: 7bfa ldrb r2, [r7, #15]
8004bd2: 429a cmp r2, r3
8004bd4: d3b5 bcc.n 8004b42 <HAL_PCD_Init+0x116>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8004bd6: 687b ldr r3, [r7, #4]
8004bd8: 6818 ldr r0, [r3, #0]
8004bda: 687b ldr r3, [r7, #4]
8004bdc: 3304 adds r3, #4
8004bde: cb0e ldmia r3, {r1, r2, r3}
8004be0: f003 f8e1 bl 8007da6 <USB_DevInit>
8004be4: 4603 mov r3, r0
8004be6: 2b00 cmp r3, #0
8004be8: d005 beq.n 8004bf6 <HAL_PCD_Init+0x1ca>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8004bea: 687b ldr r3, [r7, #4]
8004bec: 2202 movs r2, #2
8004bee: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8004bf2: 2301 movs r3, #1
8004bf4: e00c b.n 8004c10 <HAL_PCD_Init+0x1e4>
}
hpcd->USB_Address = 0U;
8004bf6: 687b ldr r3, [r7, #4]
8004bf8: 2200 movs r2, #0
8004bfa: 735a strb r2, [r3, #13]
hpcd->State = HAL_PCD_STATE_READY;
8004bfc: 687b ldr r3, [r7, #4]
8004bfe: 2201 movs r2, #1
8004c00: f883 2291 strb.w r2, [r3, #657] @ 0x291
(void)USB_DevDisconnect(hpcd->Instance);
8004c04: 687b ldr r3, [r7, #4]
8004c06: 681b ldr r3, [r3, #0]
8004c08: 4618 mov r0, r3
8004c0a: f005 fb60 bl 800a2ce <USB_DevDisconnect>
return HAL_OK;
8004c0e: 2300 movs r3, #0
}
8004c10: 4618 mov r0, r3
8004c12: 3710 adds r7, #16
8004c14: 46bd mov sp, r7
8004c16: bd80 pop {r7, pc}
08004c18 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
8004c18: b580 push {r7, lr}
8004c1a: b082 sub sp, #8
8004c1c: af00 add r7, sp, #0
8004c1e: 6078 str r0, [r7, #4]
__HAL_LOCK(hpcd);
8004c20: 687b ldr r3, [r7, #4]
8004c22: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8004c26: 2b01 cmp r3, #1
8004c28: d101 bne.n 8004c2e <HAL_PCD_Start+0x16>
8004c2a: 2302 movs r3, #2
8004c2c: e016 b.n 8004c5c <HAL_PCD_Start+0x44>
8004c2e: 687b ldr r3, [r7, #4]
8004c30: 2201 movs r2, #1
8004c32: f883 2290 strb.w r2, [r3, #656] @ 0x290
__HAL_PCD_ENABLE(hpcd);
8004c36: 687b ldr r3, [r7, #4]
8004c38: 681b ldr r3, [r3, #0]
8004c3a: 4618 mov r0, r3
8004c3c: f003 f877 bl 8007d2e <USB_EnableGlobalInt>
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
8004c40: 2101 movs r1, #1
8004c42: 6878 ldr r0, [r7, #4]
8004c44: f007 fc4b bl 800c4de <HAL_PCDEx_SetConnectionState>
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
8004c48: 687b ldr r3, [r7, #4]
8004c4a: 681b ldr r3, [r3, #0]
8004c4c: 4618 mov r0, r3
8004c4e: f005 fb34 bl 800a2ba <USB_DevConnect>
__HAL_UNLOCK(hpcd);
8004c52: 687b ldr r3, [r7, #4]
8004c54: 2200 movs r2, #0
8004c56: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8004c5a: 2300 movs r3, #0
}
8004c5c: 4618 mov r0, r3
8004c5e: 3708 adds r7, #8
8004c60: 46bd mov sp, r7
8004c62: bd80 pop {r7, pc}
08004c64 <HAL_PCD_IRQHandler>:
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
8004c64: b580 push {r7, lr}
8004c66: b088 sub sp, #32
8004c68: af00 add r7, sp, #0
8004c6a: 6078 str r0, [r7, #4]
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
8004c6c: 687b ldr r3, [r7, #4]
8004c6e: 681b ldr r3, [r3, #0]
8004c70: 4618 mov r0, r3
8004c72: f005 fb36 bl 800a2e2 <USB_ReadInterrupts>
8004c76: 61b8 str r0, [r7, #24]
uint16_t store_ep[8];
uint8_t i;
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
8004c78: 69bb ldr r3, [r7, #24]
8004c7a: f403 4300 and.w r3, r3, #32768 @ 0x8000
8004c7e: 2b00 cmp r3, #0
8004c80: d003 beq.n 8004c8a <HAL_PCD_IRQHandler+0x26>
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
8004c82: 6878 ldr r0, [r7, #4]
8004c84: f000 fb1a bl 80052bc <PCD_EP_ISR_Handler>
return;
8004c88: e119 b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
8004c8a: 69bb ldr r3, [r7, #24]
8004c8c: f403 6380 and.w r3, r3, #1024 @ 0x400
8004c90: 2b00 cmp r3, #0
8004c92: d013 beq.n 8004cbc <HAL_PCD_IRQHandler+0x58>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8004c94: 687b ldr r3, [r7, #4]
8004c96: 681b ldr r3, [r3, #0]
8004c98: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004c9c: b29a uxth r2, r3
8004c9e: 687b ldr r3, [r7, #4]
8004ca0: 681b ldr r3, [r3, #0]
8004ca2: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004ca6: b292 uxth r2, r2
8004ca8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
8004cac: 6878 ldr r0, [r7, #4]
8004cae: f007 fa1e bl 800c0ee <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
8004cb2: 2100 movs r1, #0
8004cb4: 6878 ldr r0, [r7, #4]
8004cb6: f000 f905 bl 8004ec4 <HAL_PCD_SetAddress>
return;
8004cba: e100 b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
8004cbc: 69bb ldr r3, [r7, #24]
8004cbe: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004cc2: 2b00 cmp r3, #0
8004cc4: d00c beq.n 8004ce0 <HAL_PCD_IRQHandler+0x7c>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
8004cc6: 687b ldr r3, [r7, #4]
8004cc8: 681b ldr r3, [r3, #0]
8004cca: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004cce: b29a uxth r2, r3
8004cd0: 687b ldr r3, [r7, #4]
8004cd2: 681b ldr r3, [r3, #0]
8004cd4: f422 4280 bic.w r2, r2, #16384 @ 0x4000
8004cd8: b292 uxth r2, r2
8004cda: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8004cde: e0ee b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
8004ce0: 69bb ldr r3, [r7, #24]
8004ce2: f403 5300 and.w r3, r3, #8192 @ 0x2000
8004ce6: 2b00 cmp r3, #0
8004ce8: d00c beq.n 8004d04 <HAL_PCD_IRQHandler+0xa0>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
8004cea: 687b ldr r3, [r7, #4]
8004cec: 681b ldr r3, [r3, #0]
8004cee: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004cf2: b29a uxth r2, r3
8004cf4: 687b ldr r3, [r7, #4]
8004cf6: 681b ldr r3, [r3, #0]
8004cf8: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8004cfc: b292 uxth r2, r2
8004cfe: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8004d02: e0dc b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
8004d04: 69bb ldr r3, [r7, #24]
8004d06: f403 5380 and.w r3, r3, #4096 @ 0x1000
8004d0a: 2b00 cmp r3, #0
8004d0c: d027 beq.n 8004d5e <HAL_PCD_IRQHandler+0xfa>
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
8004d0e: 687b ldr r3, [r7, #4]
8004d10: 681b ldr r3, [r3, #0]
8004d12: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004d16: b29a uxth r2, r3
8004d18: 687b ldr r3, [r7, #4]
8004d1a: 681b ldr r3, [r3, #0]
8004d1c: f022 0204 bic.w r2, r2, #4
8004d20: b292 uxth r2, r2
8004d22: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
8004d26: 687b ldr r3, [r7, #4]
8004d28: 681b ldr r3, [r3, #0]
8004d2a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004d2e: b29a uxth r2, r3
8004d30: 687b ldr r3, [r7, #4]
8004d32: 681b ldr r3, [r3, #0]
8004d34: f022 0208 bic.w r2, r2, #8
8004d38: b292 uxth r2, r2
8004d3a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
8004d3e: 6878 ldr r0, [r7, #4]
8004d40: f007 fa0e bl 800c160 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
8004d44: 687b ldr r3, [r7, #4]
8004d46: 681b ldr r3, [r3, #0]
8004d48: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004d4c: b29a uxth r2, r3
8004d4e: 687b ldr r3, [r7, #4]
8004d50: 681b ldr r3, [r3, #0]
8004d52: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8004d56: b292 uxth r2, r2
8004d58: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8004d5c: e0af b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
8004d5e: 69bb ldr r3, [r7, #24]
8004d60: f403 6300 and.w r3, r3, #2048 @ 0x800
8004d64: 2b00 cmp r3, #0
8004d66: f000 8083 beq.w 8004e70 <HAL_PCD_IRQHandler+0x20c>
{
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint registers */
for (i = 0U; i < 8U; i++)
8004d6a: 2300 movs r3, #0
8004d6c: 77fb strb r3, [r7, #31]
8004d6e: e010 b.n 8004d92 <HAL_PCD_IRQHandler+0x12e>
{
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
8004d70: 687b ldr r3, [r7, #4]
8004d72: 681b ldr r3, [r3, #0]
8004d74: 461a mov r2, r3
8004d76: 7ffb ldrb r3, [r7, #31]
8004d78: 009b lsls r3, r3, #2
8004d7a: 441a add r2, r3
8004d7c: 7ffb ldrb r3, [r7, #31]
8004d7e: 8812 ldrh r2, [r2, #0]
8004d80: b292 uxth r2, r2
8004d82: 005b lsls r3, r3, #1
8004d84: 3320 adds r3, #32
8004d86: 443b add r3, r7
8004d88: f823 2c18 strh.w r2, [r3, #-24]
for (i = 0U; i < 8U; i++)
8004d8c: 7ffb ldrb r3, [r7, #31]
8004d8e: 3301 adds r3, #1
8004d90: 77fb strb r3, [r7, #31]
8004d92: 7ffb ldrb r3, [r7, #31]
8004d94: 2b07 cmp r3, #7
8004d96: d9eb bls.n 8004d70 <HAL_PCD_IRQHandler+0x10c>
}
/* FORCE RESET */
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
8004d98: 687b ldr r3, [r7, #4]
8004d9a: 681b ldr r3, [r3, #0]
8004d9c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004da0: b29a uxth r2, r3
8004da2: 687b ldr r3, [r7, #4]
8004da4: 681b ldr r3, [r3, #0]
8004da6: f042 0201 orr.w r2, r2, #1
8004daa: b292 uxth r2, r2
8004dac: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CLEAR RESET */
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
8004db0: 687b ldr r3, [r7, #4]
8004db2: 681b ldr r3, [r3, #0]
8004db4: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004db8: b29a uxth r2, r3
8004dba: 687b ldr r3, [r7, #4]
8004dbc: 681b ldr r3, [r3, #0]
8004dbe: f022 0201 bic.w r2, r2, #1
8004dc2: b292 uxth r2, r2
8004dc4: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* wait for reset flag in ISTR */
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
8004dc8: bf00 nop
8004dca: 687b ldr r3, [r7, #4]
8004dcc: 681b ldr r3, [r3, #0]
8004dce: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004dd2: b29b uxth r3, r3
8004dd4: f403 6380 and.w r3, r3, #1024 @ 0x400
8004dd8: 2b00 cmp r3, #0
8004dda: d0f6 beq.n 8004dca <HAL_PCD_IRQHandler+0x166>
{
}
/* Clear Reset Flag */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8004ddc: 687b ldr r3, [r7, #4]
8004dde: 681b ldr r3, [r3, #0]
8004de0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004de4: b29a uxth r2, r3
8004de6: 687b ldr r3, [r7, #4]
8004de8: 681b ldr r3, [r3, #0]
8004dea: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004dee: b292 uxth r2, r2
8004df0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Restore Registre */
for (i = 0U; i < 8U; i++)
8004df4: 2300 movs r3, #0
8004df6: 77fb strb r3, [r7, #31]
8004df8: e00f b.n 8004e1a <HAL_PCD_IRQHandler+0x1b6>
{
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
8004dfa: 7ffb ldrb r3, [r7, #31]
8004dfc: 687a ldr r2, [r7, #4]
8004dfe: 6812 ldr r2, [r2, #0]
8004e00: 4611 mov r1, r2
8004e02: 7ffa ldrb r2, [r7, #31]
8004e04: 0092 lsls r2, r2, #2
8004e06: 440a add r2, r1
8004e08: 005b lsls r3, r3, #1
8004e0a: 3320 adds r3, #32
8004e0c: 443b add r3, r7
8004e0e: f833 3c18 ldrh.w r3, [r3, #-24]
8004e12: 8013 strh r3, [r2, #0]
for (i = 0U; i < 8U; i++)
8004e14: 7ffb ldrb r3, [r7, #31]
8004e16: 3301 adds r3, #1
8004e18: 77fb strb r3, [r7, #31]
8004e1a: 7ffb ldrb r3, [r7, #31]
8004e1c: 2b07 cmp r3, #7
8004e1e: d9ec bls.n 8004dfa <HAL_PCD_IRQHandler+0x196>
}
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
8004e20: 687b ldr r3, [r7, #4]
8004e22: 681b ldr r3, [r3, #0]
8004e24: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004e28: b29a uxth r2, r3
8004e2a: 687b ldr r3, [r7, #4]
8004e2c: 681b ldr r3, [r3, #0]
8004e2e: f042 0208 orr.w r2, r2, #8
8004e32: b292 uxth r2, r2
8004e34: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
8004e38: 687b ldr r3, [r7, #4]
8004e3a: 681b ldr r3, [r3, #0]
8004e3c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004e40: b29a uxth r2, r3
8004e42: 687b ldr r3, [r7, #4]
8004e44: 681b ldr r3, [r3, #0]
8004e46: f422 6200 bic.w r2, r2, #2048 @ 0x800
8004e4a: b292 uxth r2, r2
8004e4c: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
8004e50: 687b ldr r3, [r7, #4]
8004e52: 681b ldr r3, [r3, #0]
8004e54: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004e58: b29a uxth r2, r3
8004e5a: 687b ldr r3, [r7, #4]
8004e5c: 681b ldr r3, [r3, #0]
8004e5e: f042 0204 orr.w r2, r2, #4
8004e62: b292 uxth r2, r2
8004e64: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
8004e68: 6878 ldr r0, [r7, #4]
8004e6a: f007 f95f bl 800c12c <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8004e6e: e026 b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
8004e70: 69bb ldr r3, [r7, #24]
8004e72: f403 7300 and.w r3, r3, #512 @ 0x200
8004e76: 2b00 cmp r3, #0
8004e78: d00f beq.n 8004e9a <HAL_PCD_IRQHandler+0x236>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
8004e7a: 687b ldr r3, [r7, #4]
8004e7c: 681b ldr r3, [r3, #0]
8004e7e: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004e82: b29a uxth r2, r3
8004e84: 687b ldr r3, [r7, #4]
8004e86: 681b ldr r3, [r3, #0]
8004e88: f422 7200 bic.w r2, r2, #512 @ 0x200
8004e8c: b292 uxth r2, r2
8004e8e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
8004e92: 6878 ldr r0, [r7, #4]
8004e94: f007 f91d bl 800c0d2 <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8004e98: e011 b.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
8004e9a: 69bb ldr r3, [r7, #24]
8004e9c: f403 7380 and.w r3, r3, #256 @ 0x100
8004ea0: 2b00 cmp r3, #0
8004ea2: d00c beq.n 8004ebe <HAL_PCD_IRQHandler+0x25a>
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
8004ea4: 687b ldr r3, [r7, #4]
8004ea6: 681b ldr r3, [r3, #0]
8004ea8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8004eac: b29a uxth r2, r3
8004eae: 687b ldr r3, [r7, #4]
8004eb0: 681b ldr r3, [r3, #0]
8004eb2: f422 7280 bic.w r2, r2, #256 @ 0x100
8004eb6: b292 uxth r2, r2
8004eb8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8004ebc: bf00 nop
}
}
8004ebe: 3720 adds r7, #32
8004ec0: 46bd mov sp, r7
8004ec2: bd80 pop {r7, pc}
08004ec4 <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
8004ec4: b580 push {r7, lr}
8004ec6: b082 sub sp, #8
8004ec8: af00 add r7, sp, #0
8004eca: 6078 str r0, [r7, #4]
8004ecc: 460b mov r3, r1
8004ece: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8004ed6: 2b01 cmp r3, #1
8004ed8: d101 bne.n 8004ede <HAL_PCD_SetAddress+0x1a>
8004eda: 2302 movs r3, #2
8004edc: e012 b.n 8004f04 <HAL_PCD_SetAddress+0x40>
8004ede: 687b ldr r3, [r7, #4]
8004ee0: 2201 movs r2, #1
8004ee2: f883 2290 strb.w r2, [r3, #656] @ 0x290
hpcd->USB_Address = address;
8004ee6: 687b ldr r3, [r7, #4]
8004ee8: 78fa ldrb r2, [r7, #3]
8004eea: 735a strb r2, [r3, #13]
(void)USB_SetDevAddress(hpcd->Instance, address);
8004eec: 687b ldr r3, [r7, #4]
8004eee: 681b ldr r3, [r3, #0]
8004ef0: 78fa ldrb r2, [r7, #3]
8004ef2: 4611 mov r1, r2
8004ef4: 4618 mov r0, r3
8004ef6: f005 f9cd bl 800a294 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8004efa: 687b ldr r3, [r7, #4]
8004efc: 2200 movs r2, #0
8004efe: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8004f02: 2300 movs r3, #0
}
8004f04: 4618 mov r0, r3
8004f06: 3708 adds r7, #8
8004f08: 46bd mov sp, r7
8004f0a: bd80 pop {r7, pc}
08004f0c <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
8004f0c: b580 push {r7, lr}
8004f0e: b084 sub sp, #16
8004f10: af00 add r7, sp, #0
8004f12: 6078 str r0, [r7, #4]
8004f14: 4608 mov r0, r1
8004f16: 4611 mov r1, r2
8004f18: 461a mov r2, r3
8004f1a: 4603 mov r3, r0
8004f1c: 70fb strb r3, [r7, #3]
8004f1e: 460b mov r3, r1
8004f20: 803b strh r3, [r7, #0]
8004f22: 4613 mov r3, r2
8004f24: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8004f26: 2300 movs r3, #0
8004f28: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8004f2a: f997 3003 ldrsb.w r3, [r7, #3]
8004f2e: 2b00 cmp r3, #0
8004f30: da0e bge.n 8004f50 <HAL_PCD_EP_Open+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8004f32: 78fb ldrb r3, [r7, #3]
8004f34: f003 0207 and.w r2, r3, #7
8004f38: 4613 mov r3, r2
8004f3a: 009b lsls r3, r3, #2
8004f3c: 4413 add r3, r2
8004f3e: 00db lsls r3, r3, #3
8004f40: 3310 adds r3, #16
8004f42: 687a ldr r2, [r7, #4]
8004f44: 4413 add r3, r2
8004f46: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8004f48: 68fb ldr r3, [r7, #12]
8004f4a: 2201 movs r2, #1
8004f4c: 705a strb r2, [r3, #1]
8004f4e: e00e b.n 8004f6e <HAL_PCD_EP_Open+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8004f50: 78fb ldrb r3, [r7, #3]
8004f52: f003 0207 and.w r2, r3, #7
8004f56: 4613 mov r3, r2
8004f58: 009b lsls r3, r3, #2
8004f5a: 4413 add r3, r2
8004f5c: 00db lsls r3, r3, #3
8004f5e: f503 73a8 add.w r3, r3, #336 @ 0x150
8004f62: 687a ldr r2, [r7, #4]
8004f64: 4413 add r3, r2
8004f66: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8004f68: 68fb ldr r3, [r7, #12]
8004f6a: 2200 movs r2, #0
8004f6c: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8004f6e: 78fb ldrb r3, [r7, #3]
8004f70: f003 0307 and.w r3, r3, #7
8004f74: b2da uxtb r2, r3
8004f76: 68fb ldr r3, [r7, #12]
8004f78: 701a strb r2, [r3, #0]
ep->maxpacket = ep_mps;
8004f7a: 883a ldrh r2, [r7, #0]
8004f7c: 68fb ldr r3, [r7, #12]
8004f7e: 611a str r2, [r3, #16]
ep->type = ep_type;
8004f80: 68fb ldr r3, [r7, #12]
8004f82: 78ba ldrb r2, [r7, #2]
8004f84: 70da strb r2, [r3, #3]
ep->tx_fifo_num = ep->num;
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
8004f86: 78bb ldrb r3, [r7, #2]
8004f88: 2b02 cmp r3, #2
8004f8a: d102 bne.n 8004f92 <HAL_PCD_EP_Open+0x86>
{
ep->data_pid_start = 0U;
8004f8c: 68fb ldr r3, [r7, #12]
8004f8e: 2200 movs r2, #0
8004f90: 711a strb r2, [r3, #4]
}
__HAL_LOCK(hpcd);
8004f92: 687b ldr r3, [r7, #4]
8004f94: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8004f98: 2b01 cmp r3, #1
8004f9a: d101 bne.n 8004fa0 <HAL_PCD_EP_Open+0x94>
8004f9c: 2302 movs r3, #2
8004f9e: e00e b.n 8004fbe <HAL_PCD_EP_Open+0xb2>
8004fa0: 687b ldr r3, [r7, #4]
8004fa2: 2201 movs r2, #1
8004fa4: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
8004fa8: 687b ldr r3, [r7, #4]
8004faa: 681b ldr r3, [r3, #0]
8004fac: 68f9 ldr r1, [r7, #12]
8004fae: 4618 mov r0, r3
8004fb0: f002 ff16 bl 8007de0 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
8004fb4: 687b ldr r3, [r7, #4]
8004fb6: 2200 movs r2, #0
8004fb8: f883 2290 strb.w r2, [r3, #656] @ 0x290
return ret;
8004fbc: 7afb ldrb r3, [r7, #11]
}
8004fbe: 4618 mov r0, r3
8004fc0: 3710 adds r7, #16
8004fc2: 46bd mov sp, r7
8004fc4: bd80 pop {r7, pc}
08004fc6 <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8004fc6: b580 push {r7, lr}
8004fc8: b084 sub sp, #16
8004fca: af00 add r7, sp, #0
8004fcc: 6078 str r0, [r7, #4]
8004fce: 460b mov r3, r1
8004fd0: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8004fd2: f997 3003 ldrsb.w r3, [r7, #3]
8004fd6: 2b00 cmp r3, #0
8004fd8: da0e bge.n 8004ff8 <HAL_PCD_EP_Close+0x32>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8004fda: 78fb ldrb r3, [r7, #3]
8004fdc: f003 0207 and.w r2, r3, #7
8004fe0: 4613 mov r3, r2
8004fe2: 009b lsls r3, r3, #2
8004fe4: 4413 add r3, r2
8004fe6: 00db lsls r3, r3, #3
8004fe8: 3310 adds r3, #16
8004fea: 687a ldr r2, [r7, #4]
8004fec: 4413 add r3, r2
8004fee: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8004ff0: 68fb ldr r3, [r7, #12]
8004ff2: 2201 movs r2, #1
8004ff4: 705a strb r2, [r3, #1]
8004ff6: e00e b.n 8005016 <HAL_PCD_EP_Close+0x50>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8004ff8: 78fb ldrb r3, [r7, #3]
8004ffa: f003 0207 and.w r2, r3, #7
8004ffe: 4613 mov r3, r2
8005000: 009b lsls r3, r3, #2
8005002: 4413 add r3, r2
8005004: 00db lsls r3, r3, #3
8005006: f503 73a8 add.w r3, r3, #336 @ 0x150
800500a: 687a ldr r2, [r7, #4]
800500c: 4413 add r3, r2
800500e: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8005010: 68fb ldr r3, [r7, #12]
8005012: 2200 movs r2, #0
8005014: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8005016: 78fb ldrb r3, [r7, #3]
8005018: f003 0307 and.w r3, r3, #7
800501c: b2da uxtb r2, r3
800501e: 68fb ldr r3, [r7, #12]
8005020: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8005022: 687b ldr r3, [r7, #4]
8005024: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8005028: 2b01 cmp r3, #1
800502a: d101 bne.n 8005030 <HAL_PCD_EP_Close+0x6a>
800502c: 2302 movs r3, #2
800502e: e00e b.n 800504e <HAL_PCD_EP_Close+0x88>
8005030: 687b ldr r3, [r7, #4]
8005032: 2201 movs r2, #1
8005034: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
8005038: 687b ldr r3, [r7, #4]
800503a: 681b ldr r3, [r3, #0]
800503c: 68f9 ldr r1, [r7, #12]
800503e: 4618 mov r0, r3
8005040: f003 fa8e bl 8008560 <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
8005044: 687b ldr r3, [r7, #4]
8005046: 2200 movs r2, #0
8005048: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
800504c: 2300 movs r3, #0
}
800504e: 4618 mov r0, r3
8005050: 3710 adds r7, #16
8005052: 46bd mov sp, r7
8005054: bd80 pop {r7, pc}
08005056 <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8005056: b580 push {r7, lr}
8005058: b086 sub sp, #24
800505a: af00 add r7, sp, #0
800505c: 60f8 str r0, [r7, #12]
800505e: 607a str r2, [r7, #4]
8005060: 603b str r3, [r7, #0]
8005062: 460b mov r3, r1
8005064: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8005066: 7afb ldrb r3, [r7, #11]
8005068: f003 0207 and.w r2, r3, #7
800506c: 4613 mov r3, r2
800506e: 009b lsls r3, r3, #2
8005070: 4413 add r3, r2
8005072: 00db lsls r3, r3, #3
8005074: f503 73a8 add.w r3, r3, #336 @ 0x150
8005078: 68fa ldr r2, [r7, #12]
800507a: 4413 add r3, r2
800507c: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
800507e: 697b ldr r3, [r7, #20]
8005080: 687a ldr r2, [r7, #4]
8005082: 615a str r2, [r3, #20]
ep->xfer_len = len;
8005084: 697b ldr r3, [r7, #20]
8005086: 683a ldr r2, [r7, #0]
8005088: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
800508a: 697b ldr r3, [r7, #20]
800508c: 2200 movs r2, #0
800508e: 61da str r2, [r3, #28]
ep->is_in = 0U;
8005090: 697b ldr r3, [r7, #20]
8005092: 2200 movs r2, #0
8005094: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8005096: 7afb ldrb r3, [r7, #11]
8005098: f003 0307 and.w r3, r3, #7
800509c: b2da uxtb r2, r3
800509e: 697b ldr r3, [r7, #20]
80050a0: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
80050a2: 68fb ldr r3, [r7, #12]
80050a4: 681b ldr r3, [r3, #0]
80050a6: 6979 ldr r1, [r7, #20]
80050a8: 4618 mov r0, r3
80050aa: f003 fc45 bl 8008938 <USB_EPStartXfer>
return HAL_OK;
80050ae: 2300 movs r3, #0
}
80050b0: 4618 mov r0, r3
80050b2: 3718 adds r7, #24
80050b4: 46bd mov sp, r7
80050b6: bd80 pop {r7, pc}
080050b8 <HAL_PCD_EP_GetRxCount>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
80050b8: b480 push {r7}
80050ba: b083 sub sp, #12
80050bc: af00 add r7, sp, #0
80050be: 6078 str r0, [r7, #4]
80050c0: 460b mov r3, r1
80050c2: 70fb strb r3, [r7, #3]
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
80050c4: 78fb ldrb r3, [r7, #3]
80050c6: f003 0207 and.w r2, r3, #7
80050ca: 6879 ldr r1, [r7, #4]
80050cc: 4613 mov r3, r2
80050ce: 009b lsls r3, r3, #2
80050d0: 4413 add r3, r2
80050d2: 00db lsls r3, r3, #3
80050d4: 440b add r3, r1
80050d6: f503 73b6 add.w r3, r3, #364 @ 0x16c
80050da: 681b ldr r3, [r3, #0]
}
80050dc: 4618 mov r0, r3
80050de: 370c adds r7, #12
80050e0: 46bd mov sp, r7
80050e2: bc80 pop {r7}
80050e4: 4770 bx lr
080050e6 <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
80050e6: b580 push {r7, lr}
80050e8: b086 sub sp, #24
80050ea: af00 add r7, sp, #0
80050ec: 60f8 str r0, [r7, #12]
80050ee: 607a str r2, [r7, #4]
80050f0: 603b str r3, [r7, #0]
80050f2: 460b mov r3, r1
80050f4: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80050f6: 7afb ldrb r3, [r7, #11]
80050f8: f003 0207 and.w r2, r3, #7
80050fc: 4613 mov r3, r2
80050fe: 009b lsls r3, r3, #2
8005100: 4413 add r3, r2
8005102: 00db lsls r3, r3, #3
8005104: 3310 adds r3, #16
8005106: 68fa ldr r2, [r7, #12]
8005108: 4413 add r3, r2
800510a: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
800510c: 697b ldr r3, [r7, #20]
800510e: 687a ldr r2, [r7, #4]
8005110: 615a str r2, [r3, #20]
ep->xfer_len = len;
8005112: 697b ldr r3, [r7, #20]
8005114: 683a ldr r2, [r7, #0]
8005116: 619a str r2, [r3, #24]
#if defined (USB)
ep->xfer_fill_db = 1U;
8005118: 697b ldr r3, [r7, #20]
800511a: 2201 movs r2, #1
800511c: f883 2024 strb.w r2, [r3, #36] @ 0x24
ep->xfer_len_db = len;
8005120: 697b ldr r3, [r7, #20]
8005122: 683a ldr r2, [r7, #0]
8005124: 621a str r2, [r3, #32]
#endif /* defined (USB) */
ep->xfer_count = 0U;
8005126: 697b ldr r3, [r7, #20]
8005128: 2200 movs r2, #0
800512a: 61da str r2, [r3, #28]
ep->is_in = 1U;
800512c: 697b ldr r3, [r7, #20]
800512e: 2201 movs r2, #1
8005130: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8005132: 7afb ldrb r3, [r7, #11]
8005134: f003 0307 and.w r3, r3, #7
8005138: b2da uxtb r2, r3
800513a: 697b ldr r3, [r7, #20]
800513c: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
800513e: 68fb ldr r3, [r7, #12]
8005140: 681b ldr r3, [r3, #0]
8005142: 6979 ldr r1, [r7, #20]
8005144: 4618 mov r0, r3
8005146: f003 fbf7 bl 8008938 <USB_EPStartXfer>
return HAL_OK;
800514a: 2300 movs r3, #0
}
800514c: 4618 mov r0, r3
800514e: 3718 adds r7, #24
8005150: 46bd mov sp, r7
8005152: bd80 pop {r7, pc}
08005154 <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8005154: b580 push {r7, lr}
8005156: b084 sub sp, #16
8005158: af00 add r7, sp, #0
800515a: 6078 str r0, [r7, #4]
800515c: 460b mov r3, r1
800515e: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8005160: 78fb ldrb r3, [r7, #3]
8005162: f003 0307 and.w r3, r3, #7
8005166: 687a ldr r2, [r7, #4]
8005168: 7912 ldrb r2, [r2, #4]
800516a: 4293 cmp r3, r2
800516c: d901 bls.n 8005172 <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
800516e: 2301 movs r3, #1
8005170: e04c b.n 800520c <HAL_PCD_EP_SetStall+0xb8>
}
if ((0x80U & ep_addr) == 0x80U)
8005172: f997 3003 ldrsb.w r3, [r7, #3]
8005176: 2b00 cmp r3, #0
8005178: da0e bge.n 8005198 <HAL_PCD_EP_SetStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800517a: 78fb ldrb r3, [r7, #3]
800517c: f003 0207 and.w r2, r3, #7
8005180: 4613 mov r3, r2
8005182: 009b lsls r3, r3, #2
8005184: 4413 add r3, r2
8005186: 00db lsls r3, r3, #3
8005188: 3310 adds r3, #16
800518a: 687a ldr r2, [r7, #4]
800518c: 4413 add r3, r2
800518e: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8005190: 68fb ldr r3, [r7, #12]
8005192: 2201 movs r2, #1
8005194: 705a strb r2, [r3, #1]
8005196: e00c b.n 80051b2 <HAL_PCD_EP_SetStall+0x5e>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8005198: 78fa ldrb r2, [r7, #3]
800519a: 4613 mov r3, r2
800519c: 009b lsls r3, r3, #2
800519e: 4413 add r3, r2
80051a0: 00db lsls r3, r3, #3
80051a2: f503 73a8 add.w r3, r3, #336 @ 0x150
80051a6: 687a ldr r2, [r7, #4]
80051a8: 4413 add r3, r2
80051aa: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80051ac: 68fb ldr r3, [r7, #12]
80051ae: 2200 movs r2, #0
80051b0: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
80051b2: 68fb ldr r3, [r7, #12]
80051b4: 2201 movs r2, #1
80051b6: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
80051b8: 78fb ldrb r3, [r7, #3]
80051ba: f003 0307 and.w r3, r3, #7
80051be: b2da uxtb r2, r3
80051c0: 68fb ldr r3, [r7, #12]
80051c2: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80051c4: 687b ldr r3, [r7, #4]
80051c6: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
80051ca: 2b01 cmp r3, #1
80051cc: d101 bne.n 80051d2 <HAL_PCD_EP_SetStall+0x7e>
80051ce: 2302 movs r3, #2
80051d0: e01c b.n 800520c <HAL_PCD_EP_SetStall+0xb8>
80051d2: 687b ldr r3, [r7, #4]
80051d4: 2201 movs r2, #1
80051d6: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPSetStall(hpcd->Instance, ep);
80051da: 687b ldr r3, [r7, #4]
80051dc: 681b ldr r3, [r3, #0]
80051de: 68f9 ldr r1, [r7, #12]
80051e0: 4618 mov r0, r3
80051e2: f004 ff5a bl 800a09a <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
80051e6: 78fb ldrb r3, [r7, #3]
80051e8: f003 0307 and.w r3, r3, #7
80051ec: 2b00 cmp r3, #0
80051ee: d108 bne.n 8005202 <HAL_PCD_EP_SetStall+0xae>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
80051f0: 687b ldr r3, [r7, #4]
80051f2: 681a ldr r2, [r3, #0]
80051f4: 687b ldr r3, [r7, #4]
80051f6: f503 7326 add.w r3, r3, #664 @ 0x298
80051fa: 4619 mov r1, r3
80051fc: 4610 mov r0, r2
80051fe: f005 f87f bl 800a300 <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
8005202: 687b ldr r3, [r7, #4]
8005204: 2200 movs r2, #0
8005206: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
800520a: 2300 movs r3, #0
}
800520c: 4618 mov r0, r3
800520e: 3710 adds r7, #16
8005210: 46bd mov sp, r7
8005212: bd80 pop {r7, pc}
08005214 <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8005214: b580 push {r7, lr}
8005216: b084 sub sp, #16
8005218: af00 add r7, sp, #0
800521a: 6078 str r0, [r7, #4]
800521c: 460b mov r3, r1
800521e: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
8005220: 78fb ldrb r3, [r7, #3]
8005222: f003 030f and.w r3, r3, #15
8005226: 687a ldr r2, [r7, #4]
8005228: 7912 ldrb r2, [r2, #4]
800522a: 4293 cmp r3, r2
800522c: d901 bls.n 8005232 <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
800522e: 2301 movs r3, #1
8005230: e040 b.n 80052b4 <HAL_PCD_EP_ClrStall+0xa0>
}
if ((0x80U & ep_addr) == 0x80U)
8005232: f997 3003 ldrsb.w r3, [r7, #3]
8005236: 2b00 cmp r3, #0
8005238: da0e bge.n 8005258 <HAL_PCD_EP_ClrStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800523a: 78fb ldrb r3, [r7, #3]
800523c: f003 0207 and.w r2, r3, #7
8005240: 4613 mov r3, r2
8005242: 009b lsls r3, r3, #2
8005244: 4413 add r3, r2
8005246: 00db lsls r3, r3, #3
8005248: 3310 adds r3, #16
800524a: 687a ldr r2, [r7, #4]
800524c: 4413 add r3, r2
800524e: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8005250: 68fb ldr r3, [r7, #12]
8005252: 2201 movs r2, #1
8005254: 705a strb r2, [r3, #1]
8005256: e00e b.n 8005276 <HAL_PCD_EP_ClrStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8005258: 78fb ldrb r3, [r7, #3]
800525a: f003 0207 and.w r2, r3, #7
800525e: 4613 mov r3, r2
8005260: 009b lsls r3, r3, #2
8005262: 4413 add r3, r2
8005264: 00db lsls r3, r3, #3
8005266: f503 73a8 add.w r3, r3, #336 @ 0x150
800526a: 687a ldr r2, [r7, #4]
800526c: 4413 add r3, r2
800526e: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8005270: 68fb ldr r3, [r7, #12]
8005272: 2200 movs r2, #0
8005274: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
8005276: 68fb ldr r3, [r7, #12]
8005278: 2200 movs r2, #0
800527a: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
800527c: 78fb ldrb r3, [r7, #3]
800527e: f003 0307 and.w r3, r3, #7
8005282: b2da uxtb r2, r3
8005284: 68fb ldr r3, [r7, #12]
8005286: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8005288: 687b ldr r3, [r7, #4]
800528a: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
800528e: 2b01 cmp r3, #1
8005290: d101 bne.n 8005296 <HAL_PCD_EP_ClrStall+0x82>
8005292: 2302 movs r3, #2
8005294: e00e b.n 80052b4 <HAL_PCD_EP_ClrStall+0xa0>
8005296: 687b ldr r3, [r7, #4]
8005298: 2201 movs r2, #1
800529a: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPClearStall(hpcd->Instance, ep);
800529e: 687b ldr r3, [r7, #4]
80052a0: 681b ldr r3, [r3, #0]
80052a2: 68f9 ldr r1, [r7, #12]
80052a4: 4618 mov r0, r3
80052a6: f004 ff48 bl 800a13a <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
80052aa: 687b ldr r3, [r7, #4]
80052ac: 2200 movs r2, #0
80052ae: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
80052b2: 2300 movs r3, #0
}
80052b4: 4618 mov r0, r3
80052b6: 3710 adds r7, #16
80052b8: 46bd mov sp, r7
80052ba: bd80 pop {r7, pc}
080052bc <PCD_EP_ISR_Handler>:
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
80052bc: b580 push {r7, lr}
80052be: b096 sub sp, #88 @ 0x58
80052c0: af00 add r7, sp, #0
80052c2: 6078 str r0, [r7, #4]
#if (USE_USB_DOUBLE_BUFFER != 1U)
count = 0U;
#endif /* USE_USB_DOUBLE_BUFFER */
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
80052c4: e3bb b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
{
wIstr = hpcd->Instance->ISTR;
80052c6: 687b ldr r3, [r7, #4]
80052c8: 681b ldr r3, [r3, #0]
80052ca: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80052ce: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
80052d2: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80052d6: b2db uxtb r3, r3
80052d8: f003 030f and.w r3, r3, #15
80052dc: f887 304d strb.w r3, [r7, #77] @ 0x4d
if (epindex == 0U)
80052e0: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80052e4: 2b00 cmp r3, #0
80052e6: f040 8175 bne.w 80055d4 <PCD_EP_ISR_Handler+0x318>
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
80052ea: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80052ee: f003 0310 and.w r3, r3, #16
80052f2: 2b00 cmp r3, #0
80052f4: d14e bne.n 8005394 <PCD_EP_ISR_Handler+0xd8>
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
80052f6: 687b ldr r3, [r7, #4]
80052f8: 681b ldr r3, [r3, #0]
80052fa: 881b ldrh r3, [r3, #0]
80052fc: b29b uxth r3, r3
80052fe: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
8005302: f023 0370 bic.w r3, r3, #112 @ 0x70
8005306: 81fb strh r3, [r7, #14]
8005308: 687b ldr r3, [r7, #4]
800530a: 681a ldr r2, [r3, #0]
800530c: 89fb ldrh r3, [r7, #14]
800530e: ea6f 4343 mvn.w r3, r3, lsl #17
8005312: ea6f 4353 mvn.w r3, r3, lsr #17
8005316: b29b uxth r3, r3
8005318: 8013 strh r3, [r2, #0]
ep = &hpcd->IN_ep[0];
800531a: 687b ldr r3, [r7, #4]
800531c: 3310 adds r3, #16
800531e: 657b str r3, [r7, #84] @ 0x54
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
8005320: 687b ldr r3, [r7, #4]
8005322: 681b ldr r3, [r3, #0]
8005324: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005328: b29b uxth r3, r3
800532a: 461a mov r2, r3
800532c: 6d7b ldr r3, [r7, #84] @ 0x54
800532e: 781b ldrb r3, [r3, #0]
8005330: 00db lsls r3, r3, #3
8005332: 4413 add r3, r2
8005334: 3302 adds r3, #2
8005336: 005b lsls r3, r3, #1
8005338: 687a ldr r2, [r7, #4]
800533a: 6812 ldr r2, [r2, #0]
800533c: 4413 add r3, r2
800533e: f503 6380 add.w r3, r3, #1024 @ 0x400
8005342: 881b ldrh r3, [r3, #0]
8005344: f3c3 0209 ubfx r2, r3, #0, #10
8005348: 6d7b ldr r3, [r7, #84] @ 0x54
800534a: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
800534c: 6d7b ldr r3, [r7, #84] @ 0x54
800534e: 695a ldr r2, [r3, #20]
8005350: 6d7b ldr r3, [r7, #84] @ 0x54
8005352: 69db ldr r3, [r3, #28]
8005354: 441a add r2, r3
8005356: 6d7b ldr r3, [r7, #84] @ 0x54
8005358: 615a str r2, [r3, #20]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
800535a: 2100 movs r1, #0
800535c: 6878 ldr r0, [r7, #4]
800535e: f006 fe9e bl 800c09e <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
8005362: 687b ldr r3, [r7, #4]
8005364: 7b5b ldrb r3, [r3, #13]
8005366: b2db uxtb r3, r3
8005368: 2b00 cmp r3, #0
800536a: f000 8368 beq.w 8005a3e <PCD_EP_ISR_Handler+0x782>
800536e: 6d7b ldr r3, [r7, #84] @ 0x54
8005370: 699b ldr r3, [r3, #24]
8005372: 2b00 cmp r3, #0
8005374: f040 8363 bne.w 8005a3e <PCD_EP_ISR_Handler+0x782>
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
8005378: 687b ldr r3, [r7, #4]
800537a: 7b5b ldrb r3, [r3, #13]
800537c: b2db uxtb r3, r3
800537e: f063 037f orn r3, r3, #127 @ 0x7f
8005382: b2da uxtb r2, r3
8005384: 687b ldr r3, [r7, #4]
8005386: 681b ldr r3, [r3, #0]
8005388: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
hpcd->USB_Address = 0U;
800538c: 687b ldr r3, [r7, #4]
800538e: 2200 movs r2, #0
8005390: 735a strb r2, [r3, #13]
8005392: e354 b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
8005394: 687b ldr r3, [r7, #4]
8005396: f503 73a8 add.w r3, r3, #336 @ 0x150
800539a: 657b str r3, [r7, #84] @ 0x54
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
800539c: 687b ldr r3, [r7, #4]
800539e: 681b ldr r3, [r3, #0]
80053a0: 881b ldrh r3, [r3, #0]
80053a2: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_SETUP) != 0U)
80053a6: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80053aa: f403 6300 and.w r3, r3, #2048 @ 0x800
80053ae: 2b00 cmp r3, #0
80053b0: d034 beq.n 800541c <PCD_EP_ISR_Handler+0x160>
{
/* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
80053b2: 687b ldr r3, [r7, #4]
80053b4: 681b ldr r3, [r3, #0]
80053b6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80053ba: b29b uxth r3, r3
80053bc: 461a mov r2, r3
80053be: 6d7b ldr r3, [r7, #84] @ 0x54
80053c0: 781b ldrb r3, [r3, #0]
80053c2: 00db lsls r3, r3, #3
80053c4: 4413 add r3, r2
80053c6: 3306 adds r3, #6
80053c8: 005b lsls r3, r3, #1
80053ca: 687a ldr r2, [r7, #4]
80053cc: 6812 ldr r2, [r2, #0]
80053ce: 4413 add r3, r2
80053d0: f503 6380 add.w r3, r3, #1024 @ 0x400
80053d4: 881b ldrh r3, [r3, #0]
80053d6: f3c3 0209 ubfx r2, r3, #0, #10
80053da: 6d7b ldr r3, [r7, #84] @ 0x54
80053dc: 61da str r2, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
80053de: 687b ldr r3, [r7, #4]
80053e0: 6818 ldr r0, [r3, #0]
80053e2: 687b ldr r3, [r7, #4]
80053e4: f503 7126 add.w r1, r3, #664 @ 0x298
80053e8: 6d7b ldr r3, [r7, #84] @ 0x54
80053ea: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
80053ec: 6d7b ldr r3, [r7, #84] @ 0x54
80053ee: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
80053f0: b29b uxth r3, r3
80053f2: f004 ffd6 bl 800a3a2 <USB_ReadPMA>
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
80053f6: 687b ldr r3, [r7, #4]
80053f8: 681b ldr r3, [r3, #0]
80053fa: 881b ldrh r3, [r3, #0]
80053fc: b29a uxth r2, r3
80053fe: f640 738f movw r3, #3983 @ 0xf8f
8005402: 4013 ands r3, r2
8005404: 823b strh r3, [r7, #16]
8005406: 687b ldr r3, [r7, #4]
8005408: 681b ldr r3, [r3, #0]
800540a: 8a3a ldrh r2, [r7, #16]
800540c: f042 0280 orr.w r2, r2, #128 @ 0x80
8005410: b292 uxth r2, r2
8005412: 801a strh r2, [r3, #0]
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
8005414: 6878 ldr r0, [r7, #4]
8005416: f006 fe15 bl 800c044 <HAL_PCD_SetupStageCallback>
800541a: e310 b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
800541c: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
8005420: 2b00 cmp r3, #0
8005422: f280 830c bge.w 8005a3e <PCD_EP_ISR_Handler+0x782>
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8005426: 687b ldr r3, [r7, #4]
8005428: 681b ldr r3, [r3, #0]
800542a: 881b ldrh r3, [r3, #0]
800542c: b29a uxth r2, r3
800542e: f640 738f movw r3, #3983 @ 0xf8f
8005432: 4013 ands r3, r2
8005434: 83fb strh r3, [r7, #30]
8005436: 687b ldr r3, [r7, #4]
8005438: 681b ldr r3, [r3, #0]
800543a: 8bfa ldrh r2, [r7, #30]
800543c: f042 0280 orr.w r2, r2, #128 @ 0x80
8005440: b292 uxth r2, r2
8005442: 801a strh r2, [r3, #0]
/* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
8005444: 687b ldr r3, [r7, #4]
8005446: 681b ldr r3, [r3, #0]
8005448: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800544c: b29b uxth r3, r3
800544e: 461a mov r2, r3
8005450: 6d7b ldr r3, [r7, #84] @ 0x54
8005452: 781b ldrb r3, [r3, #0]
8005454: 00db lsls r3, r3, #3
8005456: 4413 add r3, r2
8005458: 3306 adds r3, #6
800545a: 005b lsls r3, r3, #1
800545c: 687a ldr r2, [r7, #4]
800545e: 6812 ldr r2, [r2, #0]
8005460: 4413 add r3, r2
8005462: f503 6380 add.w r3, r3, #1024 @ 0x400
8005466: 881b ldrh r3, [r3, #0]
8005468: f3c3 0209 ubfx r2, r3, #0, #10
800546c: 6d7b ldr r3, [r7, #84] @ 0x54
800546e: 61da str r2, [r3, #28]
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
8005470: 6d7b ldr r3, [r7, #84] @ 0x54
8005472: 69db ldr r3, [r3, #28]
8005474: 2b00 cmp r3, #0
8005476: d019 beq.n 80054ac <PCD_EP_ISR_Handler+0x1f0>
8005478: 6d7b ldr r3, [r7, #84] @ 0x54
800547a: 695b ldr r3, [r3, #20]
800547c: 2b00 cmp r3, #0
800547e: d015 beq.n 80054ac <PCD_EP_ISR_Handler+0x1f0>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8005480: 687b ldr r3, [r7, #4]
8005482: 6818 ldr r0, [r3, #0]
8005484: 6d7b ldr r3, [r7, #84] @ 0x54
8005486: 6959 ldr r1, [r3, #20]
8005488: 6d7b ldr r3, [r7, #84] @ 0x54
800548a: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
800548c: 6d7b ldr r3, [r7, #84] @ 0x54
800548e: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8005490: b29b uxth r3, r3
8005492: f004 ff86 bl 800a3a2 <USB_ReadPMA>
ep->xfer_buff += ep->xfer_count;
8005496: 6d7b ldr r3, [r7, #84] @ 0x54
8005498: 695a ldr r2, [r3, #20]
800549a: 6d7b ldr r3, [r7, #84] @ 0x54
800549c: 69db ldr r3, [r3, #28]
800549e: 441a add r2, r3
80054a0: 6d7b ldr r3, [r7, #84] @ 0x54
80054a2: 615a str r2, [r3, #20]
/* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
80054a4: 2100 movs r1, #0
80054a6: 6878 ldr r0, [r7, #4]
80054a8: f006 fdde bl 800c068 <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
80054ac: 687b ldr r3, [r7, #4]
80054ae: 681b ldr r3, [r3, #0]
80054b0: 881b ldrh r3, [r3, #0]
80054b2: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
80054b6: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80054ba: f403 6300 and.w r3, r3, #2048 @ 0x800
80054be: 2b00 cmp r3, #0
80054c0: f040 82bd bne.w 8005a3e <PCD_EP_ISR_Handler+0x782>
80054c4: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80054c8: f403 5340 and.w r3, r3, #12288 @ 0x3000
80054cc: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80054d0: f000 82b5 beq.w 8005a3e <PCD_EP_ISR_Handler+0x782>
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
80054d4: 687b ldr r3, [r7, #4]
80054d6: 681b ldr r3, [r3, #0]
80054d8: 61bb str r3, [r7, #24]
80054da: 687b ldr r3, [r7, #4]
80054dc: 681b ldr r3, [r3, #0]
80054de: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80054e2: b29b uxth r3, r3
80054e4: 461a mov r2, r3
80054e6: 69bb ldr r3, [r7, #24]
80054e8: 4413 add r3, r2
80054ea: 61bb str r3, [r7, #24]
80054ec: 69bb ldr r3, [r7, #24]
80054ee: f203 430c addw r3, r3, #1036 @ 0x40c
80054f2: 617b str r3, [r7, #20]
80054f4: 697b ldr r3, [r7, #20]
80054f6: 881b ldrh r3, [r3, #0]
80054f8: b29b uxth r3, r3
80054fa: f3c3 0309 ubfx r3, r3, #0, #10
80054fe: b29a uxth r2, r3
8005500: 697b ldr r3, [r7, #20]
8005502: 801a strh r2, [r3, #0]
8005504: 6d7b ldr r3, [r7, #84] @ 0x54
8005506: 691b ldr r3, [r3, #16]
8005508: 2b3e cmp r3, #62 @ 0x3e
800550a: d91d bls.n 8005548 <PCD_EP_ISR_Handler+0x28c>
800550c: 6d7b ldr r3, [r7, #84] @ 0x54
800550e: 691b ldr r3, [r3, #16]
8005510: 095b lsrs r3, r3, #5
8005512: 647b str r3, [r7, #68] @ 0x44
8005514: 6d7b ldr r3, [r7, #84] @ 0x54
8005516: 691b ldr r3, [r3, #16]
8005518: f003 031f and.w r3, r3, #31
800551c: 2b00 cmp r3, #0
800551e: d102 bne.n 8005526 <PCD_EP_ISR_Handler+0x26a>
8005520: 6c7b ldr r3, [r7, #68] @ 0x44
8005522: 3b01 subs r3, #1
8005524: 647b str r3, [r7, #68] @ 0x44
8005526: 697b ldr r3, [r7, #20]
8005528: 881b ldrh r3, [r3, #0]
800552a: b29a uxth r2, r3
800552c: 6c7b ldr r3, [r7, #68] @ 0x44
800552e: b29b uxth r3, r3
8005530: 029b lsls r3, r3, #10
8005532: b29b uxth r3, r3
8005534: 4313 orrs r3, r2
8005536: b29b uxth r3, r3
8005538: ea6f 4343 mvn.w r3, r3, lsl #17
800553c: ea6f 4353 mvn.w r3, r3, lsr #17
8005540: b29a uxth r2, r3
8005542: 697b ldr r3, [r7, #20]
8005544: 801a strh r2, [r3, #0]
8005546: e026 b.n 8005596 <PCD_EP_ISR_Handler+0x2da>
8005548: 6d7b ldr r3, [r7, #84] @ 0x54
800554a: 691b ldr r3, [r3, #16]
800554c: 2b00 cmp r3, #0
800554e: d10a bne.n 8005566 <PCD_EP_ISR_Handler+0x2aa>
8005550: 697b ldr r3, [r7, #20]
8005552: 881b ldrh r3, [r3, #0]
8005554: b29b uxth r3, r3
8005556: ea6f 4343 mvn.w r3, r3, lsl #17
800555a: ea6f 4353 mvn.w r3, r3, lsr #17
800555e: b29a uxth r2, r3
8005560: 697b ldr r3, [r7, #20]
8005562: 801a strh r2, [r3, #0]
8005564: e017 b.n 8005596 <PCD_EP_ISR_Handler+0x2da>
8005566: 6d7b ldr r3, [r7, #84] @ 0x54
8005568: 691b ldr r3, [r3, #16]
800556a: 085b lsrs r3, r3, #1
800556c: 647b str r3, [r7, #68] @ 0x44
800556e: 6d7b ldr r3, [r7, #84] @ 0x54
8005570: 691b ldr r3, [r3, #16]
8005572: f003 0301 and.w r3, r3, #1
8005576: 2b00 cmp r3, #0
8005578: d002 beq.n 8005580 <PCD_EP_ISR_Handler+0x2c4>
800557a: 6c7b ldr r3, [r7, #68] @ 0x44
800557c: 3301 adds r3, #1
800557e: 647b str r3, [r7, #68] @ 0x44
8005580: 697b ldr r3, [r7, #20]
8005582: 881b ldrh r3, [r3, #0]
8005584: b29a uxth r2, r3
8005586: 6c7b ldr r3, [r7, #68] @ 0x44
8005588: b29b uxth r3, r3
800558a: 029b lsls r3, r3, #10
800558c: b29b uxth r3, r3
800558e: 4313 orrs r3, r2
8005590: b29a uxth r2, r3
8005592: 697b ldr r3, [r7, #20]
8005594: 801a strh r2, [r3, #0]
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
8005596: 687b ldr r3, [r7, #4]
8005598: 681b ldr r3, [r3, #0]
800559a: 881b ldrh r3, [r3, #0]
800559c: b29b uxth r3, r3
800559e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80055a2: f023 0370 bic.w r3, r3, #112 @ 0x70
80055a6: 827b strh r3, [r7, #18]
80055a8: 8a7b ldrh r3, [r7, #18]
80055aa: f483 5380 eor.w r3, r3, #4096 @ 0x1000
80055ae: 827b strh r3, [r7, #18]
80055b0: 8a7b ldrh r3, [r7, #18]
80055b2: f483 5300 eor.w r3, r3, #8192 @ 0x2000
80055b6: 827b strh r3, [r7, #18]
80055b8: 687b ldr r3, [r7, #4]
80055ba: 681a ldr r2, [r3, #0]
80055bc: 8a7b ldrh r3, [r7, #18]
80055be: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80055c2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80055c6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80055ca: f043 0380 orr.w r3, r3, #128 @ 0x80
80055ce: b29b uxth r3, r3
80055d0: 8013 strh r3, [r2, #0]
80055d2: e234 b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
80055d4: 687b ldr r3, [r7, #4]
80055d6: 681b ldr r3, [r3, #0]
80055d8: 461a mov r2, r3
80055da: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80055de: 009b lsls r3, r3, #2
80055e0: 4413 add r3, r2
80055e2: 881b ldrh r3, [r3, #0]
80055e4: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_CTR_RX) != 0U)
80055e8: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
80055ec: 2b00 cmp r3, #0
80055ee: f280 80fc bge.w 80057ea <PCD_EP_ISR_Handler+0x52e>
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
80055f2: 687b ldr r3, [r7, #4]
80055f4: 681b ldr r3, [r3, #0]
80055f6: 461a mov r2, r3
80055f8: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
80055fc: 009b lsls r3, r3, #2
80055fe: 4413 add r3, r2
8005600: 881b ldrh r3, [r3, #0]
8005602: b29a uxth r2, r3
8005604: f640 738f movw r3, #3983 @ 0xf8f
8005608: 4013 ands r3, r2
800560a: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
800560e: 687b ldr r3, [r7, #4]
8005610: 681b ldr r3, [r3, #0]
8005612: 461a mov r2, r3
8005614: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8005618: 009b lsls r3, r3, #2
800561a: 4413 add r3, r2
800561c: f8b7 2048 ldrh.w r2, [r7, #72] @ 0x48
8005620: f042 0280 orr.w r2, r2, #128 @ 0x80
8005624: b292 uxth r2, r2
8005626: 801a strh r2, [r3, #0]
ep = &hpcd->OUT_ep[epindex];
8005628: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
800562c: 4613 mov r3, r2
800562e: 009b lsls r3, r3, #2
8005630: 4413 add r3, r2
8005632: 00db lsls r3, r3, #3
8005634: f503 73a8 add.w r3, r3, #336 @ 0x150
8005638: 687a ldr r2, [r7, #4]
800563a: 4413 add r3, r2
800563c: 657b str r3, [r7, #84] @ 0x54
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
800563e: 6d7b ldr r3, [r7, #84] @ 0x54
8005640: 7b1b ldrb r3, [r3, #12]
8005642: 2b00 cmp r3, #0
8005644: d125 bne.n 8005692 <PCD_EP_ISR_Handler+0x3d6>
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
8005646: 687b ldr r3, [r7, #4]
8005648: 681b ldr r3, [r3, #0]
800564a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800564e: b29b uxth r3, r3
8005650: 461a mov r2, r3
8005652: 6d7b ldr r3, [r7, #84] @ 0x54
8005654: 781b ldrb r3, [r3, #0]
8005656: 00db lsls r3, r3, #3
8005658: 4413 add r3, r2
800565a: 3306 adds r3, #6
800565c: 005b lsls r3, r3, #1
800565e: 687a ldr r2, [r7, #4]
8005660: 6812 ldr r2, [r2, #0]
8005662: 4413 add r3, r2
8005664: f503 6380 add.w r3, r3, #1024 @ 0x400
8005668: 881b ldrh r3, [r3, #0]
800566a: f3c3 0309 ubfx r3, r3, #0, #10
800566e: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
8005672: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8005676: 2b00 cmp r3, #0
8005678: f000 8092 beq.w 80057a0 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
800567c: 687b ldr r3, [r7, #4]
800567e: 6818 ldr r0, [r3, #0]
8005680: 6d7b ldr r3, [r7, #84] @ 0x54
8005682: 6959 ldr r1, [r3, #20]
8005684: 6d7b ldr r3, [r7, #84] @ 0x54
8005686: 88da ldrh r2, [r3, #6]
8005688: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800568c: f004 fe89 bl 800a3a2 <USB_ReadPMA>
8005690: e086 b.n 80057a0 <PCD_EP_ISR_Handler+0x4e4>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
8005692: 6d7b ldr r3, [r7, #84] @ 0x54
8005694: 78db ldrb r3, [r3, #3]
8005696: 2b02 cmp r3, #2
8005698: d10a bne.n 80056b0 <PCD_EP_ISR_Handler+0x3f4>
{
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
800569a: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
800569e: 461a mov r2, r3
80056a0: 6d79 ldr r1, [r7, #84] @ 0x54
80056a2: 6878 ldr r0, [r7, #4]
80056a4: f000 f9d9 bl 8005a5a <HAL_PCD_EP_DB_Receive>
80056a8: 4603 mov r3, r0
80056aa: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
80056ae: e077 b.n 80057a0 <PCD_EP_ISR_Handler+0x4e4>
}
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
80056b0: 687b ldr r3, [r7, #4]
80056b2: 681b ldr r3, [r3, #0]
80056b4: 461a mov r2, r3
80056b6: 6d7b ldr r3, [r7, #84] @ 0x54
80056b8: 781b ldrb r3, [r3, #0]
80056ba: 009b lsls r3, r3, #2
80056bc: 4413 add r3, r2
80056be: 881b ldrh r3, [r3, #0]
80056c0: b29b uxth r3, r3
80056c2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80056c6: f023 0370 bic.w r3, r3, #112 @ 0x70
80056ca: f8a7 3052 strh.w r3, [r7, #82] @ 0x52
80056ce: 687b ldr r3, [r7, #4]
80056d0: 681b ldr r3, [r3, #0]
80056d2: 461a mov r2, r3
80056d4: 6d7b ldr r3, [r7, #84] @ 0x54
80056d6: 781b ldrb r3, [r3, #0]
80056d8: 009b lsls r3, r3, #2
80056da: 441a add r2, r3
80056dc: f8b7 3052 ldrh.w r3, [r7, #82] @ 0x52
80056e0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80056e4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80056e8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80056ec: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80056f0: b29b uxth r3, r3
80056f2: 8013 strh r3, [r2, #0]
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
80056f4: 687b ldr r3, [r7, #4]
80056f6: 681b ldr r3, [r3, #0]
80056f8: 461a mov r2, r3
80056fa: 6d7b ldr r3, [r7, #84] @ 0x54
80056fc: 781b ldrb r3, [r3, #0]
80056fe: 009b lsls r3, r3, #2
8005700: 4413 add r3, r2
8005702: 881b ldrh r3, [r3, #0]
8005704: b29b uxth r3, r3
8005706: f403 4380 and.w r3, r3, #16384 @ 0x4000
800570a: 2b00 cmp r3, #0
800570c: d024 beq.n 8005758 <PCD_EP_ISR_Handler+0x49c>
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
800570e: 687b ldr r3, [r7, #4]
8005710: 681b ldr r3, [r3, #0]
8005712: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005716: b29b uxth r3, r3
8005718: 461a mov r2, r3
800571a: 6d7b ldr r3, [r7, #84] @ 0x54
800571c: 781b ldrb r3, [r3, #0]
800571e: 00db lsls r3, r3, #3
8005720: 4413 add r3, r2
8005722: 3302 adds r3, #2
8005724: 005b lsls r3, r3, #1
8005726: 687a ldr r2, [r7, #4]
8005728: 6812 ldr r2, [r2, #0]
800572a: 4413 add r3, r2
800572c: f503 6380 add.w r3, r3, #1024 @ 0x400
8005730: 881b ldrh r3, [r3, #0]
8005732: f3c3 0309 ubfx r3, r3, #0, #10
8005736: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
800573a: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800573e: 2b00 cmp r3, #0
8005740: d02e beq.n 80057a0 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
8005742: 687b ldr r3, [r7, #4]
8005744: 6818 ldr r0, [r3, #0]
8005746: 6d7b ldr r3, [r7, #84] @ 0x54
8005748: 6959 ldr r1, [r3, #20]
800574a: 6d7b ldr r3, [r7, #84] @ 0x54
800574c: 891a ldrh r2, [r3, #8]
800574e: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8005752: f004 fe26 bl 800a3a2 <USB_ReadPMA>
8005756: e023 b.n 80057a0 <PCD_EP_ISR_Handler+0x4e4>
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8005758: 687b ldr r3, [r7, #4]
800575a: 681b ldr r3, [r3, #0]
800575c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005760: b29b uxth r3, r3
8005762: 461a mov r2, r3
8005764: 6d7b ldr r3, [r7, #84] @ 0x54
8005766: 781b ldrb r3, [r3, #0]
8005768: 00db lsls r3, r3, #3
800576a: 4413 add r3, r2
800576c: 3306 adds r3, #6
800576e: 005b lsls r3, r3, #1
8005770: 687a ldr r2, [r7, #4]
8005772: 6812 ldr r2, [r2, #0]
8005774: 4413 add r3, r2
8005776: f503 6380 add.w r3, r3, #1024 @ 0x400
800577a: 881b ldrh r3, [r3, #0]
800577c: f3c3 0309 ubfx r3, r3, #0, #10
8005780: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
8005784: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8005788: 2b00 cmp r3, #0
800578a: d009 beq.n 80057a0 <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
800578c: 687b ldr r3, [r7, #4]
800578e: 6818 ldr r0, [r3, #0]
8005790: 6d7b ldr r3, [r7, #84] @ 0x54
8005792: 6959 ldr r1, [r3, #20]
8005794: 6d7b ldr r3, [r7, #84] @ 0x54
8005796: 895a ldrh r2, [r3, #10]
8005798: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
800579c: f004 fe01 bl 800a3a2 <USB_ReadPMA>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
80057a0: 6d7b ldr r3, [r7, #84] @ 0x54
80057a2: 69da ldr r2, [r3, #28]
80057a4: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80057a8: 441a add r2, r3
80057aa: 6d7b ldr r3, [r7, #84] @ 0x54
80057ac: 61da str r2, [r3, #28]
ep->xfer_buff += count;
80057ae: 6d7b ldr r3, [r7, #84] @ 0x54
80057b0: 695a ldr r2, [r3, #20]
80057b2: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80057b6: 441a add r2, r3
80057b8: 6d7b ldr r3, [r7, #84] @ 0x54
80057ba: 615a str r2, [r3, #20]
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
80057bc: 6d7b ldr r3, [r7, #84] @ 0x54
80057be: 699b ldr r3, [r3, #24]
80057c0: 2b00 cmp r3, #0
80057c2: d005 beq.n 80057d0 <PCD_EP_ISR_Handler+0x514>
80057c4: f8b7 2050 ldrh.w r2, [r7, #80] @ 0x50
80057c8: 6d7b ldr r3, [r7, #84] @ 0x54
80057ca: 691b ldr r3, [r3, #16]
80057cc: 429a cmp r2, r3
80057ce: d206 bcs.n 80057de <PCD_EP_ISR_Handler+0x522>
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
80057d0: 6d7b ldr r3, [r7, #84] @ 0x54
80057d2: 781b ldrb r3, [r3, #0]
80057d4: 4619 mov r1, r3
80057d6: 6878 ldr r0, [r7, #4]
80057d8: f006 fc46 bl 800c068 <HAL_PCD_DataOutStageCallback>
80057dc: e005 b.n 80057ea <PCD_EP_ISR_Handler+0x52e>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
80057de: 687b ldr r3, [r7, #4]
80057e0: 681b ldr r3, [r3, #0]
80057e2: 6d79 ldr r1, [r7, #84] @ 0x54
80057e4: 4618 mov r0, r3
80057e6: f003 f8a7 bl 8008938 <USB_EPStartXfer>
}
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
80057ea: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80057ee: f003 0380 and.w r3, r3, #128 @ 0x80
80057f2: 2b00 cmp r3, #0
80057f4: f000 8123 beq.w 8005a3e <PCD_EP_ISR_Handler+0x782>
{
ep = &hpcd->IN_ep[epindex];
80057f8: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
80057fc: 4613 mov r3, r2
80057fe: 009b lsls r3, r3, #2
8005800: 4413 add r3, r2
8005802: 00db lsls r3, r3, #3
8005804: 3310 adds r3, #16
8005806: 687a ldr r2, [r7, #4]
8005808: 4413 add r3, r2
800580a: 657b str r3, [r7, #84] @ 0x54
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
800580c: 687b ldr r3, [r7, #4]
800580e: 681b ldr r3, [r3, #0]
8005810: 461a mov r2, r3
8005812: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8005816: 009b lsls r3, r3, #2
8005818: 4413 add r3, r2
800581a: 881b ldrh r3, [r3, #0]
800581c: b29b uxth r3, r3
800581e: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
8005822: f023 0370 bic.w r3, r3, #112 @ 0x70
8005826: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
800582a: 687b ldr r3, [r7, #4]
800582c: 681b ldr r3, [r3, #0]
800582e: 461a mov r2, r3
8005830: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8005834: 009b lsls r3, r3, #2
8005836: 441a add r2, r3
8005838: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
800583c: ea6f 4343 mvn.w r3, r3, lsl #17
8005840: ea6f 4353 mvn.w r3, r3, lsr #17
8005844: b29b uxth r3, r3
8005846: 8013 strh r3, [r2, #0]
if (ep->type == EP_TYPE_ISOC)
8005848: 6d7b ldr r3, [r7, #84] @ 0x54
800584a: 78db ldrb r3, [r3, #3]
800584c: 2b01 cmp r3, #1
800584e: f040 80a2 bne.w 8005996 <PCD_EP_ISR_Handler+0x6da>
{
ep->xfer_len = 0U;
8005852: 6d7b ldr r3, [r7, #84] @ 0x54
8005854: 2200 movs r2, #0
8005856: 619a str r2, [r3, #24]
#if (USE_USB_DOUBLE_BUFFER == 1U)
if (ep->doublebuffer != 0U)
8005858: 6d7b ldr r3, [r7, #84] @ 0x54
800585a: 7b1b ldrb r3, [r3, #12]
800585c: 2b00 cmp r3, #0
800585e: f000 8093 beq.w 8005988 <PCD_EP_ISR_Handler+0x6cc>
{
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8005862: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8005866: f003 0340 and.w r3, r3, #64 @ 0x40
800586a: 2b00 cmp r3, #0
800586c: d046 beq.n 80058fc <PCD_EP_ISR_Handler+0x640>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
800586e: 6d7b ldr r3, [r7, #84] @ 0x54
8005870: 785b ldrb r3, [r3, #1]
8005872: 2b00 cmp r3, #0
8005874: d126 bne.n 80058c4 <PCD_EP_ISR_Handler+0x608>
8005876: 687b ldr r3, [r7, #4]
8005878: 681b ldr r3, [r3, #0]
800587a: 627b str r3, [r7, #36] @ 0x24
800587c: 687b ldr r3, [r7, #4]
800587e: 681b ldr r3, [r3, #0]
8005880: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005884: b29b uxth r3, r3
8005886: 461a mov r2, r3
8005888: 6a7b ldr r3, [r7, #36] @ 0x24
800588a: 4413 add r3, r2
800588c: 627b str r3, [r7, #36] @ 0x24
800588e: 6d7b ldr r3, [r7, #84] @ 0x54
8005890: 781b ldrb r3, [r3, #0]
8005892: 011a lsls r2, r3, #4
8005894: 6a7b ldr r3, [r7, #36] @ 0x24
8005896: 4413 add r3, r2
8005898: f203 4304 addw r3, r3, #1028 @ 0x404
800589c: 623b str r3, [r7, #32]
800589e: 6a3b ldr r3, [r7, #32]
80058a0: 881b ldrh r3, [r3, #0]
80058a2: b29b uxth r3, r3
80058a4: f3c3 0309 ubfx r3, r3, #0, #10
80058a8: b29a uxth r2, r3
80058aa: 6a3b ldr r3, [r7, #32]
80058ac: 801a strh r2, [r3, #0]
80058ae: 6a3b ldr r3, [r7, #32]
80058b0: 881b ldrh r3, [r3, #0]
80058b2: b29b uxth r3, r3
80058b4: ea6f 4343 mvn.w r3, r3, lsl #17
80058b8: ea6f 4353 mvn.w r3, r3, lsr #17
80058bc: b29a uxth r2, r3
80058be: 6a3b ldr r3, [r7, #32]
80058c0: 801a strh r2, [r3, #0]
80058c2: e061 b.n 8005988 <PCD_EP_ISR_Handler+0x6cc>
80058c4: 6d7b ldr r3, [r7, #84] @ 0x54
80058c6: 785b ldrb r3, [r3, #1]
80058c8: 2b01 cmp r3, #1
80058ca: d15d bne.n 8005988 <PCD_EP_ISR_Handler+0x6cc>
80058cc: 687b ldr r3, [r7, #4]
80058ce: 681b ldr r3, [r3, #0]
80058d0: 62fb str r3, [r7, #44] @ 0x2c
80058d2: 687b ldr r3, [r7, #4]
80058d4: 681b ldr r3, [r3, #0]
80058d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80058da: b29b uxth r3, r3
80058dc: 461a mov r2, r3
80058de: 6afb ldr r3, [r7, #44] @ 0x2c
80058e0: 4413 add r3, r2
80058e2: 62fb str r3, [r7, #44] @ 0x2c
80058e4: 6d7b ldr r3, [r7, #84] @ 0x54
80058e6: 781b ldrb r3, [r3, #0]
80058e8: 011a lsls r2, r3, #4
80058ea: 6afb ldr r3, [r7, #44] @ 0x2c
80058ec: 4413 add r3, r2
80058ee: f203 4304 addw r3, r3, #1028 @ 0x404
80058f2: 62bb str r3, [r7, #40] @ 0x28
80058f4: 6abb ldr r3, [r7, #40] @ 0x28
80058f6: 2200 movs r2, #0
80058f8: 801a strh r2, [r3, #0]
80058fa: e045 b.n 8005988 <PCD_EP_ISR_Handler+0x6cc>
}
else
{
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80058fc: 687b ldr r3, [r7, #4]
80058fe: 681b ldr r3, [r3, #0]
8005900: 63fb str r3, [r7, #60] @ 0x3c
8005902: 6d7b ldr r3, [r7, #84] @ 0x54
8005904: 785b ldrb r3, [r3, #1]
8005906: 2b00 cmp r3, #0
8005908: d126 bne.n 8005958 <PCD_EP_ISR_Handler+0x69c>
800590a: 687b ldr r3, [r7, #4]
800590c: 681b ldr r3, [r3, #0]
800590e: 637b str r3, [r7, #52] @ 0x34
8005910: 687b ldr r3, [r7, #4]
8005912: 681b ldr r3, [r3, #0]
8005914: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005918: b29b uxth r3, r3
800591a: 461a mov r2, r3
800591c: 6b7b ldr r3, [r7, #52] @ 0x34
800591e: 4413 add r3, r2
8005920: 637b str r3, [r7, #52] @ 0x34
8005922: 6d7b ldr r3, [r7, #84] @ 0x54
8005924: 781b ldrb r3, [r3, #0]
8005926: 011a lsls r2, r3, #4
8005928: 6b7b ldr r3, [r7, #52] @ 0x34
800592a: 4413 add r3, r2
800592c: f203 430c addw r3, r3, #1036 @ 0x40c
8005930: 633b str r3, [r7, #48] @ 0x30
8005932: 6b3b ldr r3, [r7, #48] @ 0x30
8005934: 881b ldrh r3, [r3, #0]
8005936: b29b uxth r3, r3
8005938: f3c3 0309 ubfx r3, r3, #0, #10
800593c: b29a uxth r2, r3
800593e: 6b3b ldr r3, [r7, #48] @ 0x30
8005940: 801a strh r2, [r3, #0]
8005942: 6b3b ldr r3, [r7, #48] @ 0x30
8005944: 881b ldrh r3, [r3, #0]
8005946: b29b uxth r3, r3
8005948: ea6f 4343 mvn.w r3, r3, lsl #17
800594c: ea6f 4353 mvn.w r3, r3, lsr #17
8005950: b29a uxth r2, r3
8005952: 6b3b ldr r3, [r7, #48] @ 0x30
8005954: 801a strh r2, [r3, #0]
8005956: e017 b.n 8005988 <PCD_EP_ISR_Handler+0x6cc>
8005958: 6d7b ldr r3, [r7, #84] @ 0x54
800595a: 785b ldrb r3, [r3, #1]
800595c: 2b01 cmp r3, #1
800595e: d113 bne.n 8005988 <PCD_EP_ISR_Handler+0x6cc>
8005960: 687b ldr r3, [r7, #4]
8005962: 681b ldr r3, [r3, #0]
8005964: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005968: b29b uxth r3, r3
800596a: 461a mov r2, r3
800596c: 6bfb ldr r3, [r7, #60] @ 0x3c
800596e: 4413 add r3, r2
8005970: 63fb str r3, [r7, #60] @ 0x3c
8005972: 6d7b ldr r3, [r7, #84] @ 0x54
8005974: 781b ldrb r3, [r3, #0]
8005976: 011a lsls r2, r3, #4
8005978: 6bfb ldr r3, [r7, #60] @ 0x3c
800597a: 4413 add r3, r2
800597c: f203 430c addw r3, r3, #1036 @ 0x40c
8005980: 63bb str r3, [r7, #56] @ 0x38
8005982: 6bbb ldr r3, [r7, #56] @ 0x38
8005984: 2200 movs r2, #0
8005986: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8005988: 6d7b ldr r3, [r7, #84] @ 0x54
800598a: 781b ldrb r3, [r3, #0]
800598c: 4619 mov r1, r3
800598e: 6878 ldr r0, [r7, #4]
8005990: f006 fb85 bl 800c09e <HAL_PCD_DataInStageCallback>
8005994: e053 b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
8005996: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
800599a: f403 7380 and.w r3, r3, #256 @ 0x100
800599e: 2b00 cmp r3, #0
80059a0: d146 bne.n 8005a30 <PCD_EP_ISR_Handler+0x774>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
80059a2: 687b ldr r3, [r7, #4]
80059a4: 681b ldr r3, [r3, #0]
80059a6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80059aa: b29b uxth r3, r3
80059ac: 461a mov r2, r3
80059ae: 6d7b ldr r3, [r7, #84] @ 0x54
80059b0: 781b ldrb r3, [r3, #0]
80059b2: 00db lsls r3, r3, #3
80059b4: 4413 add r3, r2
80059b6: 3302 adds r3, #2
80059b8: 005b lsls r3, r3, #1
80059ba: 687a ldr r2, [r7, #4]
80059bc: 6812 ldr r2, [r2, #0]
80059be: 4413 add r3, r2
80059c0: f503 6380 add.w r3, r3, #1024 @ 0x400
80059c4: 881b ldrh r3, [r3, #0]
80059c6: f3c3 0309 ubfx r3, r3, #0, #10
80059ca: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
if (ep->xfer_len > TxPctSize)
80059ce: 6d7b ldr r3, [r7, #84] @ 0x54
80059d0: 699a ldr r2, [r3, #24]
80059d2: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80059d6: 429a cmp r2, r3
80059d8: d907 bls.n 80059ea <PCD_EP_ISR_Handler+0x72e>
{
ep->xfer_len -= TxPctSize;
80059da: 6d7b ldr r3, [r7, #84] @ 0x54
80059dc: 699a ldr r2, [r3, #24]
80059de: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80059e2: 1ad2 subs r2, r2, r3
80059e4: 6d7b ldr r3, [r7, #84] @ 0x54
80059e6: 619a str r2, [r3, #24]
80059e8: e002 b.n 80059f0 <PCD_EP_ISR_Handler+0x734>
}
else
{
ep->xfer_len = 0U;
80059ea: 6d7b ldr r3, [r7, #84] @ 0x54
80059ec: 2200 movs r2, #0
80059ee: 619a str r2, [r3, #24]
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
80059f0: 6d7b ldr r3, [r7, #84] @ 0x54
80059f2: 699b ldr r3, [r3, #24]
80059f4: 2b00 cmp r3, #0
80059f6: d106 bne.n 8005a06 <PCD_EP_ISR_Handler+0x74a>
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80059f8: 6d7b ldr r3, [r7, #84] @ 0x54
80059fa: 781b ldrb r3, [r3, #0]
80059fc: 4619 mov r1, r3
80059fe: 6878 ldr r0, [r7, #4]
8005a00: f006 fb4d bl 800c09e <HAL_PCD_DataInStageCallback>
8005a04: e01b b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxPctSize;
8005a06: 6d7b ldr r3, [r7, #84] @ 0x54
8005a08: 695a ldr r2, [r3, #20]
8005a0a: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8005a0e: 441a add r2, r3
8005a10: 6d7b ldr r3, [r7, #84] @ 0x54
8005a12: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8005a14: 6d7b ldr r3, [r7, #84] @ 0x54
8005a16: 69da ldr r2, [r3, #28]
8005a18: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8005a1c: 441a add r2, r3
8005a1e: 6d7b ldr r3, [r7, #84] @ 0x54
8005a20: 61da str r2, [r3, #28]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8005a22: 687b ldr r3, [r7, #4]
8005a24: 681b ldr r3, [r3, #0]
8005a26: 6d79 ldr r1, [r7, #84] @ 0x54
8005a28: 4618 mov r0, r3
8005a2a: f002 ff85 bl 8008938 <USB_EPStartXfer>
8005a2e: e006 b.n 8005a3e <PCD_EP_ISR_Handler+0x782>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
8005a30: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8005a34: 461a mov r2, r3
8005a36: 6d79 ldr r1, [r7, #84] @ 0x54
8005a38: 6878 ldr r0, [r7, #4]
8005a3a: f000 f91b bl 8005c74 <HAL_PCD_EP_DB_Transmit>
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8005a3e: 687b ldr r3, [r7, #4]
8005a40: 681b ldr r3, [r3, #0]
8005a42: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8005a46: b29b uxth r3, r3
8005a48: b21b sxth r3, r3
8005a4a: 2b00 cmp r3, #0
8005a4c: f6ff ac3b blt.w 80052c6 <PCD_EP_ISR_Handler+0xa>
}
}
}
}
return HAL_OK;
8005a50: 2300 movs r3, #0
}
8005a52: 4618 mov r0, r3
8005a54: 3758 adds r7, #88 @ 0x58
8005a56: 46bd mov sp, r7
8005a58: bd80 pop {r7, pc}
08005a5a <HAL_PCD_EP_DB_Receive>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8005a5a: b580 push {r7, lr}
8005a5c: b088 sub sp, #32
8005a5e: af00 add r7, sp, #0
8005a60: 60f8 str r0, [r7, #12]
8005a62: 60b9 str r1, [r7, #8]
8005a64: 4613 mov r3, r2
8005a66: 80fb strh r3, [r7, #6]
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8005a68: 88fb ldrh r3, [r7, #6]
8005a6a: f403 4380 and.w r3, r3, #16384 @ 0x4000
8005a6e: 2b00 cmp r3, #0
8005a70: d07e beq.n 8005b70 <HAL_PCD_EP_DB_Receive+0x116>
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8005a72: 68fb ldr r3, [r7, #12]
8005a74: 681b ldr r3, [r3, #0]
8005a76: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005a7a: b29b uxth r3, r3
8005a7c: 461a mov r2, r3
8005a7e: 68bb ldr r3, [r7, #8]
8005a80: 781b ldrb r3, [r3, #0]
8005a82: 00db lsls r3, r3, #3
8005a84: 4413 add r3, r2
8005a86: 3302 adds r3, #2
8005a88: 005b lsls r3, r3, #1
8005a8a: 68fa ldr r2, [r7, #12]
8005a8c: 6812 ldr r2, [r2, #0]
8005a8e: 4413 add r3, r2
8005a90: f503 6380 add.w r3, r3, #1024 @ 0x400
8005a94: 881b ldrh r3, [r3, #0]
8005a96: f3c3 0309 ubfx r3, r3, #0, #10
8005a9a: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8005a9c: 68bb ldr r3, [r7, #8]
8005a9e: 699a ldr r2, [r3, #24]
8005aa0: 8b7b ldrh r3, [r7, #26]
8005aa2: 429a cmp r2, r3
8005aa4: d306 bcc.n 8005ab4 <HAL_PCD_EP_DB_Receive+0x5a>
{
ep->xfer_len -= count;
8005aa6: 68bb ldr r3, [r7, #8]
8005aa8: 699a ldr r2, [r3, #24]
8005aaa: 8b7b ldrh r3, [r7, #26]
8005aac: 1ad2 subs r2, r2, r3
8005aae: 68bb ldr r3, [r7, #8]
8005ab0: 619a str r2, [r3, #24]
8005ab2: e002 b.n 8005aba <HAL_PCD_EP_DB_Receive+0x60>
}
else
{
ep->xfer_len = 0U;
8005ab4: 68bb ldr r3, [r7, #8]
8005ab6: 2200 movs r2, #0
8005ab8: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8005aba: 68bb ldr r3, [r7, #8]
8005abc: 699b ldr r3, [r3, #24]
8005abe: 2b00 cmp r3, #0
8005ac0: d123 bne.n 8005b0a <HAL_PCD_EP_DB_Receive+0xb0>
{
/* set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
8005ac2: 68fb ldr r3, [r7, #12]
8005ac4: 681b ldr r3, [r3, #0]
8005ac6: 461a mov r2, r3
8005ac8: 68bb ldr r3, [r7, #8]
8005aca: 781b ldrb r3, [r3, #0]
8005acc: 009b lsls r3, r3, #2
8005ace: 4413 add r3, r2
8005ad0: 881b ldrh r3, [r3, #0]
8005ad2: b29b uxth r3, r3
8005ad4: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005ad8: f023 0370 bic.w r3, r3, #112 @ 0x70
8005adc: 833b strh r3, [r7, #24]
8005ade: 8b3b ldrh r3, [r7, #24]
8005ae0: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8005ae4: 833b strh r3, [r7, #24]
8005ae6: 68fb ldr r3, [r7, #12]
8005ae8: 681b ldr r3, [r3, #0]
8005aea: 461a mov r2, r3
8005aec: 68bb ldr r3, [r7, #8]
8005aee: 781b ldrb r3, [r3, #0]
8005af0: 009b lsls r3, r3, #2
8005af2: 441a add r2, r3
8005af4: 8b3b ldrh r3, [r7, #24]
8005af6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005afa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005afe: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005b02: f043 0380 orr.w r3, r3, #128 @ 0x80
8005b06: b29b uxth r3, r3
8005b08: 8013 strh r3, [r2, #0]
}
/* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8005b0a: 88fb ldrh r3, [r7, #6]
8005b0c: f003 0340 and.w r3, r3, #64 @ 0x40
8005b10: 2b00 cmp r3, #0
8005b12: d01f beq.n 8005b54 <HAL_PCD_EP_DB_Receive+0xfa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8005b14: 68fb ldr r3, [r7, #12]
8005b16: 681b ldr r3, [r3, #0]
8005b18: 461a mov r2, r3
8005b1a: 68bb ldr r3, [r7, #8]
8005b1c: 781b ldrb r3, [r3, #0]
8005b1e: 009b lsls r3, r3, #2
8005b20: 4413 add r3, r2
8005b22: 881b ldrh r3, [r3, #0]
8005b24: b29b uxth r3, r3
8005b26: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005b2a: f023 0370 bic.w r3, r3, #112 @ 0x70
8005b2e: 82fb strh r3, [r7, #22]
8005b30: 68fb ldr r3, [r7, #12]
8005b32: 681b ldr r3, [r3, #0]
8005b34: 461a mov r2, r3
8005b36: 68bb ldr r3, [r7, #8]
8005b38: 781b ldrb r3, [r3, #0]
8005b3a: 009b lsls r3, r3, #2
8005b3c: 441a add r2, r3
8005b3e: 8afb ldrh r3, [r7, #22]
8005b40: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005b44: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005b48: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005b4c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8005b50: b29b uxth r3, r3
8005b52: 8013 strh r3, [r2, #0]
}
if (count != 0U)
8005b54: 8b7b ldrh r3, [r7, #26]
8005b56: 2b00 cmp r3, #0
8005b58: f000 8087 beq.w 8005c6a <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
8005b5c: 68fb ldr r3, [r7, #12]
8005b5e: 6818 ldr r0, [r3, #0]
8005b60: 68bb ldr r3, [r7, #8]
8005b62: 6959 ldr r1, [r3, #20]
8005b64: 68bb ldr r3, [r7, #8]
8005b66: 891a ldrh r2, [r3, #8]
8005b68: 8b7b ldrh r3, [r7, #26]
8005b6a: f004 fc1a bl 800a3a2 <USB_ReadPMA>
8005b6e: e07c b.n 8005c6a <HAL_PCD_EP_DB_Receive+0x210>
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8005b70: 68fb ldr r3, [r7, #12]
8005b72: 681b ldr r3, [r3, #0]
8005b74: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005b78: b29b uxth r3, r3
8005b7a: 461a mov r2, r3
8005b7c: 68bb ldr r3, [r7, #8]
8005b7e: 781b ldrb r3, [r3, #0]
8005b80: 00db lsls r3, r3, #3
8005b82: 4413 add r3, r2
8005b84: 3306 adds r3, #6
8005b86: 005b lsls r3, r3, #1
8005b88: 68fa ldr r2, [r7, #12]
8005b8a: 6812 ldr r2, [r2, #0]
8005b8c: 4413 add r3, r2
8005b8e: f503 6380 add.w r3, r3, #1024 @ 0x400
8005b92: 881b ldrh r3, [r3, #0]
8005b94: f3c3 0309 ubfx r3, r3, #0, #10
8005b98: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8005b9a: 68bb ldr r3, [r7, #8]
8005b9c: 699a ldr r2, [r3, #24]
8005b9e: 8b7b ldrh r3, [r7, #26]
8005ba0: 429a cmp r2, r3
8005ba2: d306 bcc.n 8005bb2 <HAL_PCD_EP_DB_Receive+0x158>
{
ep->xfer_len -= count;
8005ba4: 68bb ldr r3, [r7, #8]
8005ba6: 699a ldr r2, [r3, #24]
8005ba8: 8b7b ldrh r3, [r7, #26]
8005baa: 1ad2 subs r2, r2, r3
8005bac: 68bb ldr r3, [r7, #8]
8005bae: 619a str r2, [r3, #24]
8005bb0: e002 b.n 8005bb8 <HAL_PCD_EP_DB_Receive+0x15e>
}
else
{
ep->xfer_len = 0U;
8005bb2: 68bb ldr r3, [r7, #8]
8005bb4: 2200 movs r2, #0
8005bb6: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8005bb8: 68bb ldr r3, [r7, #8]
8005bba: 699b ldr r3, [r3, #24]
8005bbc: 2b00 cmp r3, #0
8005bbe: d123 bne.n 8005c08 <HAL_PCD_EP_DB_Receive+0x1ae>
{
/* set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
8005bc0: 68fb ldr r3, [r7, #12]
8005bc2: 681b ldr r3, [r3, #0]
8005bc4: 461a mov r2, r3
8005bc6: 68bb ldr r3, [r7, #8]
8005bc8: 781b ldrb r3, [r3, #0]
8005bca: 009b lsls r3, r3, #2
8005bcc: 4413 add r3, r2
8005bce: 881b ldrh r3, [r3, #0]
8005bd0: b29b uxth r3, r3
8005bd2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005bd6: f023 0370 bic.w r3, r3, #112 @ 0x70
8005bda: 83fb strh r3, [r7, #30]
8005bdc: 8bfb ldrh r3, [r7, #30]
8005bde: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8005be2: 83fb strh r3, [r7, #30]
8005be4: 68fb ldr r3, [r7, #12]
8005be6: 681b ldr r3, [r3, #0]
8005be8: 461a mov r2, r3
8005bea: 68bb ldr r3, [r7, #8]
8005bec: 781b ldrb r3, [r3, #0]
8005bee: 009b lsls r3, r3, #2
8005bf0: 441a add r2, r3
8005bf2: 8bfb ldrh r3, [r7, #30]
8005bf4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005bf8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005bfc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005c00: f043 0380 orr.w r3, r3, #128 @ 0x80
8005c04: b29b uxth r3, r3
8005c06: 8013 strh r3, [r2, #0]
}
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
8005c08: 88fb ldrh r3, [r7, #6]
8005c0a: f003 0340 and.w r3, r3, #64 @ 0x40
8005c0e: 2b00 cmp r3, #0
8005c10: d11f bne.n 8005c52 <HAL_PCD_EP_DB_Receive+0x1f8>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8005c12: 68fb ldr r3, [r7, #12]
8005c14: 681b ldr r3, [r3, #0]
8005c16: 461a mov r2, r3
8005c18: 68bb ldr r3, [r7, #8]
8005c1a: 781b ldrb r3, [r3, #0]
8005c1c: 009b lsls r3, r3, #2
8005c1e: 4413 add r3, r2
8005c20: 881b ldrh r3, [r3, #0]
8005c22: b29b uxth r3, r3
8005c24: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005c28: f023 0370 bic.w r3, r3, #112 @ 0x70
8005c2c: 83bb strh r3, [r7, #28]
8005c2e: 68fb ldr r3, [r7, #12]
8005c30: 681b ldr r3, [r3, #0]
8005c32: 461a mov r2, r3
8005c34: 68bb ldr r3, [r7, #8]
8005c36: 781b ldrb r3, [r3, #0]
8005c38: 009b lsls r3, r3, #2
8005c3a: 441a add r2, r3
8005c3c: 8bbb ldrh r3, [r7, #28]
8005c3e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005c42: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005c46: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005c4a: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8005c4e: b29b uxth r3, r3
8005c50: 8013 strh r3, [r2, #0]
}
if (count != 0U)
8005c52: 8b7b ldrh r3, [r7, #26]
8005c54: 2b00 cmp r3, #0
8005c56: d008 beq.n 8005c6a <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8005c58: 68fb ldr r3, [r7, #12]
8005c5a: 6818 ldr r0, [r3, #0]
8005c5c: 68bb ldr r3, [r7, #8]
8005c5e: 6959 ldr r1, [r3, #20]
8005c60: 68bb ldr r3, [r7, #8]
8005c62: 895a ldrh r2, [r3, #10]
8005c64: 8b7b ldrh r3, [r7, #26]
8005c66: f004 fb9c bl 800a3a2 <USB_ReadPMA>
}
}
return count;
8005c6a: 8b7b ldrh r3, [r7, #26]
}
8005c6c: 4618 mov r0, r3
8005c6e: 3720 adds r7, #32
8005c70: 46bd mov sp, r7
8005c72: bd80 pop {r7, pc}
08005c74 <HAL_PCD_EP_DB_Transmit>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8005c74: b580 push {r7, lr}
8005c76: b0a4 sub sp, #144 @ 0x90
8005c78: af00 add r7, sp, #0
8005c7a: 60f8 str r0, [r7, #12]
8005c7c: 60b9 str r1, [r7, #8]
8005c7e: 4613 mov r3, r2
8005c80: 80fb strh r3, [r7, #6]
uint32_t len;
uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8005c82: 88fb ldrh r3, [r7, #6]
8005c84: f003 0340 and.w r3, r3, #64 @ 0x40
8005c88: 2b00 cmp r3, #0
8005c8a: f000 81dd beq.w 8006048 <HAL_PCD_EP_DB_Transmit+0x3d4>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8005c8e: 68fb ldr r3, [r7, #12]
8005c90: 681b ldr r3, [r3, #0]
8005c92: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005c96: b29b uxth r3, r3
8005c98: 461a mov r2, r3
8005c9a: 68bb ldr r3, [r7, #8]
8005c9c: 781b ldrb r3, [r3, #0]
8005c9e: 00db lsls r3, r3, #3
8005ca0: 4413 add r3, r2
8005ca2: 3302 adds r3, #2
8005ca4: 005b lsls r3, r3, #1
8005ca6: 68fa ldr r2, [r7, #12]
8005ca8: 6812 ldr r2, [r2, #0]
8005caa: 4413 add r3, r2
8005cac: f503 6380 add.w r3, r3, #1024 @ 0x400
8005cb0: 881b ldrh r3, [r3, #0]
8005cb2: f3c3 0309 ubfx r3, r3, #0, #10
8005cb6: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len > TxPctSize)
8005cba: 68bb ldr r3, [r7, #8]
8005cbc: 699a ldr r2, [r3, #24]
8005cbe: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8005cc2: 429a cmp r2, r3
8005cc4: d907 bls.n 8005cd6 <HAL_PCD_EP_DB_Transmit+0x62>
{
ep->xfer_len -= TxPctSize;
8005cc6: 68bb ldr r3, [r7, #8]
8005cc8: 699a ldr r2, [r3, #24]
8005cca: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8005cce: 1ad2 subs r2, r2, r3
8005cd0: 68bb ldr r3, [r7, #8]
8005cd2: 619a str r2, [r3, #24]
8005cd4: e002 b.n 8005cdc <HAL_PCD_EP_DB_Transmit+0x68>
}
else
{
ep->xfer_len = 0U;
8005cd6: 68bb ldr r3, [r7, #8]
8005cd8: 2200 movs r2, #0
8005cda: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8005cdc: 68bb ldr r3, [r7, #8]
8005cde: 699b ldr r3, [r3, #24]
8005ce0: 2b00 cmp r3, #0
8005ce2: f040 80b9 bne.w 8005e58 <HAL_PCD_EP_DB_Transmit+0x1e4>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8005ce6: 68bb ldr r3, [r7, #8]
8005ce8: 785b ldrb r3, [r3, #1]
8005cea: 2b00 cmp r3, #0
8005cec: d126 bne.n 8005d3c <HAL_PCD_EP_DB_Transmit+0xc8>
8005cee: 68fb ldr r3, [r7, #12]
8005cf0: 681b ldr r3, [r3, #0]
8005cf2: 62fb str r3, [r7, #44] @ 0x2c
8005cf4: 68fb ldr r3, [r7, #12]
8005cf6: 681b ldr r3, [r3, #0]
8005cf8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005cfc: b29b uxth r3, r3
8005cfe: 461a mov r2, r3
8005d00: 6afb ldr r3, [r7, #44] @ 0x2c
8005d02: 4413 add r3, r2
8005d04: 62fb str r3, [r7, #44] @ 0x2c
8005d06: 68bb ldr r3, [r7, #8]
8005d08: 781b ldrb r3, [r3, #0]
8005d0a: 011a lsls r2, r3, #4
8005d0c: 6afb ldr r3, [r7, #44] @ 0x2c
8005d0e: 4413 add r3, r2
8005d10: f203 4304 addw r3, r3, #1028 @ 0x404
8005d14: 62bb str r3, [r7, #40] @ 0x28
8005d16: 6abb ldr r3, [r7, #40] @ 0x28
8005d18: 881b ldrh r3, [r3, #0]
8005d1a: b29b uxth r3, r3
8005d1c: f3c3 0309 ubfx r3, r3, #0, #10
8005d20: b29a uxth r2, r3
8005d22: 6abb ldr r3, [r7, #40] @ 0x28
8005d24: 801a strh r2, [r3, #0]
8005d26: 6abb ldr r3, [r7, #40] @ 0x28
8005d28: 881b ldrh r3, [r3, #0]
8005d2a: b29b uxth r3, r3
8005d2c: ea6f 4343 mvn.w r3, r3, lsl #17
8005d30: ea6f 4353 mvn.w r3, r3, lsr #17
8005d34: b29a uxth r2, r3
8005d36: 6abb ldr r3, [r7, #40] @ 0x28
8005d38: 801a strh r2, [r3, #0]
8005d3a: e01a b.n 8005d72 <HAL_PCD_EP_DB_Transmit+0xfe>
8005d3c: 68bb ldr r3, [r7, #8]
8005d3e: 785b ldrb r3, [r3, #1]
8005d40: 2b01 cmp r3, #1
8005d42: d116 bne.n 8005d72 <HAL_PCD_EP_DB_Transmit+0xfe>
8005d44: 68fb ldr r3, [r7, #12]
8005d46: 681b ldr r3, [r3, #0]
8005d48: 637b str r3, [r7, #52] @ 0x34
8005d4a: 68fb ldr r3, [r7, #12]
8005d4c: 681b ldr r3, [r3, #0]
8005d4e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005d52: b29b uxth r3, r3
8005d54: 461a mov r2, r3
8005d56: 6b7b ldr r3, [r7, #52] @ 0x34
8005d58: 4413 add r3, r2
8005d5a: 637b str r3, [r7, #52] @ 0x34
8005d5c: 68bb ldr r3, [r7, #8]
8005d5e: 781b ldrb r3, [r3, #0]
8005d60: 011a lsls r2, r3, #4
8005d62: 6b7b ldr r3, [r7, #52] @ 0x34
8005d64: 4413 add r3, r2
8005d66: f203 4304 addw r3, r3, #1028 @ 0x404
8005d6a: 633b str r3, [r7, #48] @ 0x30
8005d6c: 6b3b ldr r3, [r7, #48] @ 0x30
8005d6e: 2200 movs r2, #0
8005d70: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8005d72: 68fb ldr r3, [r7, #12]
8005d74: 681b ldr r3, [r3, #0]
8005d76: 627b str r3, [r7, #36] @ 0x24
8005d78: 68bb ldr r3, [r7, #8]
8005d7a: 785b ldrb r3, [r3, #1]
8005d7c: 2b00 cmp r3, #0
8005d7e: d126 bne.n 8005dce <HAL_PCD_EP_DB_Transmit+0x15a>
8005d80: 68fb ldr r3, [r7, #12]
8005d82: 681b ldr r3, [r3, #0]
8005d84: 61fb str r3, [r7, #28]
8005d86: 68fb ldr r3, [r7, #12]
8005d88: 681b ldr r3, [r3, #0]
8005d8a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005d8e: b29b uxth r3, r3
8005d90: 461a mov r2, r3
8005d92: 69fb ldr r3, [r7, #28]
8005d94: 4413 add r3, r2
8005d96: 61fb str r3, [r7, #28]
8005d98: 68bb ldr r3, [r7, #8]
8005d9a: 781b ldrb r3, [r3, #0]
8005d9c: 011a lsls r2, r3, #4
8005d9e: 69fb ldr r3, [r7, #28]
8005da0: 4413 add r3, r2
8005da2: f203 430c addw r3, r3, #1036 @ 0x40c
8005da6: 61bb str r3, [r7, #24]
8005da8: 69bb ldr r3, [r7, #24]
8005daa: 881b ldrh r3, [r3, #0]
8005dac: b29b uxth r3, r3
8005dae: f3c3 0309 ubfx r3, r3, #0, #10
8005db2: b29a uxth r2, r3
8005db4: 69bb ldr r3, [r7, #24]
8005db6: 801a strh r2, [r3, #0]
8005db8: 69bb ldr r3, [r7, #24]
8005dba: 881b ldrh r3, [r3, #0]
8005dbc: b29b uxth r3, r3
8005dbe: ea6f 4343 mvn.w r3, r3, lsl #17
8005dc2: ea6f 4353 mvn.w r3, r3, lsr #17
8005dc6: b29a uxth r2, r3
8005dc8: 69bb ldr r3, [r7, #24]
8005dca: 801a strh r2, [r3, #0]
8005dcc: e017 b.n 8005dfe <HAL_PCD_EP_DB_Transmit+0x18a>
8005dce: 68bb ldr r3, [r7, #8]
8005dd0: 785b ldrb r3, [r3, #1]
8005dd2: 2b01 cmp r3, #1
8005dd4: d113 bne.n 8005dfe <HAL_PCD_EP_DB_Transmit+0x18a>
8005dd6: 68fb ldr r3, [r7, #12]
8005dd8: 681b ldr r3, [r3, #0]
8005dda: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005dde: b29b uxth r3, r3
8005de0: 461a mov r2, r3
8005de2: 6a7b ldr r3, [r7, #36] @ 0x24
8005de4: 4413 add r3, r2
8005de6: 627b str r3, [r7, #36] @ 0x24
8005de8: 68bb ldr r3, [r7, #8]
8005dea: 781b ldrb r3, [r3, #0]
8005dec: 011a lsls r2, r3, #4
8005dee: 6a7b ldr r3, [r7, #36] @ 0x24
8005df0: 4413 add r3, r2
8005df2: f203 430c addw r3, r3, #1036 @ 0x40c
8005df6: 623b str r3, [r7, #32]
8005df8: 6a3b ldr r3, [r7, #32]
8005dfa: 2200 movs r2, #0
8005dfc: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8005dfe: 68bb ldr r3, [r7, #8]
8005e00: 781b ldrb r3, [r3, #0]
8005e02: 4619 mov r1, r3
8005e04: 68f8 ldr r0, [r7, #12]
8005e06: f006 f94a bl 800c09e <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8005e0a: 88fb ldrh r3, [r7, #6]
8005e0c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8005e10: 2b00 cmp r3, #0
8005e12: f000 82fc beq.w 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8005e16: 68fb ldr r3, [r7, #12]
8005e18: 681b ldr r3, [r3, #0]
8005e1a: 461a mov r2, r3
8005e1c: 68bb ldr r3, [r7, #8]
8005e1e: 781b ldrb r3, [r3, #0]
8005e20: 009b lsls r3, r3, #2
8005e22: 4413 add r3, r2
8005e24: 881b ldrh r3, [r3, #0]
8005e26: b29b uxth r3, r3
8005e28: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005e2c: f023 0370 bic.w r3, r3, #112 @ 0x70
8005e30: 82fb strh r3, [r7, #22]
8005e32: 68fb ldr r3, [r7, #12]
8005e34: 681b ldr r3, [r3, #0]
8005e36: 461a mov r2, r3
8005e38: 68bb ldr r3, [r7, #8]
8005e3a: 781b ldrb r3, [r3, #0]
8005e3c: 009b lsls r3, r3, #2
8005e3e: 441a add r2, r3
8005e40: 8afb ldrh r3, [r7, #22]
8005e42: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005e46: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005e4a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8005e4e: f043 0380 orr.w r3, r3, #128 @ 0x80
8005e52: b29b uxth r3, r3
8005e54: 8013 strh r3, [r2, #0]
8005e56: e2da b.n 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8005e58: 88fb ldrh r3, [r7, #6]
8005e5a: f403 4380 and.w r3, r3, #16384 @ 0x4000
8005e5e: 2b00 cmp r3, #0
8005e60: d021 beq.n 8005ea6 <HAL_PCD_EP_DB_Transmit+0x232>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8005e62: 68fb ldr r3, [r7, #12]
8005e64: 681b ldr r3, [r3, #0]
8005e66: 461a mov r2, r3
8005e68: 68bb ldr r3, [r7, #8]
8005e6a: 781b ldrb r3, [r3, #0]
8005e6c: 009b lsls r3, r3, #2
8005e6e: 4413 add r3, r2
8005e70: 881b ldrh r3, [r3, #0]
8005e72: b29b uxth r3, r3
8005e74: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005e78: f023 0370 bic.w r3, r3, #112 @ 0x70
8005e7c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8005e80: 68fb ldr r3, [r7, #12]
8005e82: 681b ldr r3, [r3, #0]
8005e84: 461a mov r2, r3
8005e86: 68bb ldr r3, [r7, #8]
8005e88: 781b ldrb r3, [r3, #0]
8005e8a: 009b lsls r3, r3, #2
8005e8c: 441a add r2, r3
8005e8e: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8005e92: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005e96: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005e9a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8005e9e: f043 0380 orr.w r3, r3, #128 @ 0x80
8005ea2: b29b uxth r3, r3
8005ea4: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8005ea6: 68bb ldr r3, [r7, #8]
8005ea8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8005eac: 2b01 cmp r3, #1
8005eae: f040 82ae bne.w 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
8005eb2: 68bb ldr r3, [r7, #8]
8005eb4: 695a ldr r2, [r3, #20]
8005eb6: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8005eba: 441a add r2, r3
8005ebc: 68bb ldr r3, [r7, #8]
8005ebe: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8005ec0: 68bb ldr r3, [r7, #8]
8005ec2: 69da ldr r2, [r3, #28]
8005ec4: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8005ec8: 441a add r2, r3
8005eca: 68bb ldr r3, [r7, #8]
8005ecc: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8005ece: 68bb ldr r3, [r7, #8]
8005ed0: 6a1a ldr r2, [r3, #32]
8005ed2: 68bb ldr r3, [r7, #8]
8005ed4: 691b ldr r3, [r3, #16]
8005ed6: 429a cmp r2, r3
8005ed8: d30b bcc.n 8005ef2 <HAL_PCD_EP_DB_Transmit+0x27e>
{
len = ep->maxpacket;
8005eda: 68bb ldr r3, [r7, #8]
8005edc: 691b ldr r3, [r3, #16]
8005ede: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8005ee2: 68bb ldr r3, [r7, #8]
8005ee4: 6a1a ldr r2, [r3, #32]
8005ee6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005eea: 1ad2 subs r2, r2, r3
8005eec: 68bb ldr r3, [r7, #8]
8005eee: 621a str r2, [r3, #32]
8005ef0: e017 b.n 8005f22 <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else if (ep->xfer_len_db == 0U)
8005ef2: 68bb ldr r3, [r7, #8]
8005ef4: 6a1b ldr r3, [r3, #32]
8005ef6: 2b00 cmp r3, #0
8005ef8: d108 bne.n 8005f0c <HAL_PCD_EP_DB_Transmit+0x298>
{
len = TxPctSize;
8005efa: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8005efe: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8005f02: 68bb ldr r3, [r7, #8]
8005f04: 2200 movs r2, #0
8005f06: f883 2024 strb.w r2, [r3, #36] @ 0x24
8005f0a: e00a b.n 8005f22 <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else
{
ep->xfer_fill_db = 0U;
8005f0c: 68bb ldr r3, [r7, #8]
8005f0e: 2200 movs r2, #0
8005f10: f883 2024 strb.w r2, [r3, #36] @ 0x24
len = ep->xfer_len_db;
8005f14: 68bb ldr r3, [r7, #8]
8005f16: 6a1b ldr r3, [r3, #32]
8005f18: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8005f1c: 68bb ldr r3, [r7, #8]
8005f1e: 2200 movs r2, #0
8005f20: 621a str r2, [r3, #32]
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8005f22: 68bb ldr r3, [r7, #8]
8005f24: 785b ldrb r3, [r3, #1]
8005f26: 2b00 cmp r3, #0
8005f28: d165 bne.n 8005ff6 <HAL_PCD_EP_DB_Transmit+0x382>
8005f2a: 68fb ldr r3, [r7, #12]
8005f2c: 681b ldr r3, [r3, #0]
8005f2e: 63fb str r3, [r7, #60] @ 0x3c
8005f30: 68fb ldr r3, [r7, #12]
8005f32: 681b ldr r3, [r3, #0]
8005f34: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005f38: b29b uxth r3, r3
8005f3a: 461a mov r2, r3
8005f3c: 6bfb ldr r3, [r7, #60] @ 0x3c
8005f3e: 4413 add r3, r2
8005f40: 63fb str r3, [r7, #60] @ 0x3c
8005f42: 68bb ldr r3, [r7, #8]
8005f44: 781b ldrb r3, [r3, #0]
8005f46: 011a lsls r2, r3, #4
8005f48: 6bfb ldr r3, [r7, #60] @ 0x3c
8005f4a: 4413 add r3, r2
8005f4c: f203 4304 addw r3, r3, #1028 @ 0x404
8005f50: 63bb str r3, [r7, #56] @ 0x38
8005f52: 6bbb ldr r3, [r7, #56] @ 0x38
8005f54: 881b ldrh r3, [r3, #0]
8005f56: b29b uxth r3, r3
8005f58: f3c3 0309 ubfx r3, r3, #0, #10
8005f5c: b29a uxth r2, r3
8005f5e: 6bbb ldr r3, [r7, #56] @ 0x38
8005f60: 801a strh r2, [r3, #0]
8005f62: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005f66: 2b3e cmp r3, #62 @ 0x3e
8005f68: d91d bls.n 8005fa6 <HAL_PCD_EP_DB_Transmit+0x332>
8005f6a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005f6e: 095b lsrs r3, r3, #5
8005f70: 64bb str r3, [r7, #72] @ 0x48
8005f72: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005f76: f003 031f and.w r3, r3, #31
8005f7a: 2b00 cmp r3, #0
8005f7c: d102 bne.n 8005f84 <HAL_PCD_EP_DB_Transmit+0x310>
8005f7e: 6cbb ldr r3, [r7, #72] @ 0x48
8005f80: 3b01 subs r3, #1
8005f82: 64bb str r3, [r7, #72] @ 0x48
8005f84: 6bbb ldr r3, [r7, #56] @ 0x38
8005f86: 881b ldrh r3, [r3, #0]
8005f88: b29a uxth r2, r3
8005f8a: 6cbb ldr r3, [r7, #72] @ 0x48
8005f8c: b29b uxth r3, r3
8005f8e: 029b lsls r3, r3, #10
8005f90: b29b uxth r3, r3
8005f92: 4313 orrs r3, r2
8005f94: b29b uxth r3, r3
8005f96: ea6f 4343 mvn.w r3, r3, lsl #17
8005f9a: ea6f 4353 mvn.w r3, r3, lsr #17
8005f9e: b29a uxth r2, r3
8005fa0: 6bbb ldr r3, [r7, #56] @ 0x38
8005fa2: 801a strh r2, [r3, #0]
8005fa4: e044 b.n 8006030 <HAL_PCD_EP_DB_Transmit+0x3bc>
8005fa6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005faa: 2b00 cmp r3, #0
8005fac: d10a bne.n 8005fc4 <HAL_PCD_EP_DB_Transmit+0x350>
8005fae: 6bbb ldr r3, [r7, #56] @ 0x38
8005fb0: 881b ldrh r3, [r3, #0]
8005fb2: b29b uxth r3, r3
8005fb4: ea6f 4343 mvn.w r3, r3, lsl #17
8005fb8: ea6f 4353 mvn.w r3, r3, lsr #17
8005fbc: b29a uxth r2, r3
8005fbe: 6bbb ldr r3, [r7, #56] @ 0x38
8005fc0: 801a strh r2, [r3, #0]
8005fc2: e035 b.n 8006030 <HAL_PCD_EP_DB_Transmit+0x3bc>
8005fc4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005fc8: 085b lsrs r3, r3, #1
8005fca: 64bb str r3, [r7, #72] @ 0x48
8005fcc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8005fd0: f003 0301 and.w r3, r3, #1
8005fd4: 2b00 cmp r3, #0
8005fd6: d002 beq.n 8005fde <HAL_PCD_EP_DB_Transmit+0x36a>
8005fd8: 6cbb ldr r3, [r7, #72] @ 0x48
8005fda: 3301 adds r3, #1
8005fdc: 64bb str r3, [r7, #72] @ 0x48
8005fde: 6bbb ldr r3, [r7, #56] @ 0x38
8005fe0: 881b ldrh r3, [r3, #0]
8005fe2: b29a uxth r2, r3
8005fe4: 6cbb ldr r3, [r7, #72] @ 0x48
8005fe6: b29b uxth r3, r3
8005fe8: 029b lsls r3, r3, #10
8005fea: b29b uxth r3, r3
8005fec: 4313 orrs r3, r2
8005fee: b29a uxth r2, r3
8005ff0: 6bbb ldr r3, [r7, #56] @ 0x38
8005ff2: 801a strh r2, [r3, #0]
8005ff4: e01c b.n 8006030 <HAL_PCD_EP_DB_Transmit+0x3bc>
8005ff6: 68bb ldr r3, [r7, #8]
8005ff8: 785b ldrb r3, [r3, #1]
8005ffa: 2b01 cmp r3, #1
8005ffc: d118 bne.n 8006030 <HAL_PCD_EP_DB_Transmit+0x3bc>
8005ffe: 68fb ldr r3, [r7, #12]
8006000: 681b ldr r3, [r3, #0]
8006002: 647b str r3, [r7, #68] @ 0x44
8006004: 68fb ldr r3, [r7, #12]
8006006: 681b ldr r3, [r3, #0]
8006008: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800600c: b29b uxth r3, r3
800600e: 461a mov r2, r3
8006010: 6c7b ldr r3, [r7, #68] @ 0x44
8006012: 4413 add r3, r2
8006014: 647b str r3, [r7, #68] @ 0x44
8006016: 68bb ldr r3, [r7, #8]
8006018: 781b ldrb r3, [r3, #0]
800601a: 011a lsls r2, r3, #4
800601c: 6c7b ldr r3, [r7, #68] @ 0x44
800601e: 4413 add r3, r2
8006020: f203 4304 addw r3, r3, #1028 @ 0x404
8006024: 643b str r3, [r7, #64] @ 0x40
8006026: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800602a: b29a uxth r2, r3
800602c: 6c3b ldr r3, [r7, #64] @ 0x40
800602e: 801a strh r2, [r3, #0]
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
8006030: 68fb ldr r3, [r7, #12]
8006032: 6818 ldr r0, [r3, #0]
8006034: 68bb ldr r3, [r7, #8]
8006036: 6959 ldr r1, [r3, #20]
8006038: 68bb ldr r3, [r7, #8]
800603a: 891a ldrh r2, [r3, #8]
800603c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006040: b29b uxth r3, r3
8006042: f004 f968 bl 800a316 <USB_WritePMA>
8006046: e1e2 b.n 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8006048: 68fb ldr r3, [r7, #12]
800604a: 681b ldr r3, [r3, #0]
800604c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006050: b29b uxth r3, r3
8006052: 461a mov r2, r3
8006054: 68bb ldr r3, [r7, #8]
8006056: 781b ldrb r3, [r3, #0]
8006058: 00db lsls r3, r3, #3
800605a: 4413 add r3, r2
800605c: 3306 adds r3, #6
800605e: 005b lsls r3, r3, #1
8006060: 68fa ldr r2, [r7, #12]
8006062: 6812 ldr r2, [r2, #0]
8006064: 4413 add r3, r2
8006066: f503 6380 add.w r3, r3, #1024 @ 0x400
800606a: 881b ldrh r3, [r3, #0]
800606c: f3c3 0309 ubfx r3, r3, #0, #10
8006070: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len >= TxPctSize)
8006074: 68bb ldr r3, [r7, #8]
8006076: 699a ldr r2, [r3, #24]
8006078: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
800607c: 429a cmp r2, r3
800607e: d307 bcc.n 8006090 <HAL_PCD_EP_DB_Transmit+0x41c>
{
ep->xfer_len -= TxPctSize;
8006080: 68bb ldr r3, [r7, #8]
8006082: 699a ldr r2, [r3, #24]
8006084: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8006088: 1ad2 subs r2, r2, r3
800608a: 68bb ldr r3, [r7, #8]
800608c: 619a str r2, [r3, #24]
800608e: e002 b.n 8006096 <HAL_PCD_EP_DB_Transmit+0x422>
}
else
{
ep->xfer_len = 0U;
8006090: 68bb ldr r3, [r7, #8]
8006092: 2200 movs r2, #0
8006094: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8006096: 68bb ldr r3, [r7, #8]
8006098: 699b ldr r3, [r3, #24]
800609a: 2b00 cmp r3, #0
800609c: f040 80c0 bne.w 8006220 <HAL_PCD_EP_DB_Transmit+0x5ac>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80060a0: 68bb ldr r3, [r7, #8]
80060a2: 785b ldrb r3, [r3, #1]
80060a4: 2b00 cmp r3, #0
80060a6: d126 bne.n 80060f6 <HAL_PCD_EP_DB_Transmit+0x482>
80060a8: 68fb ldr r3, [r7, #12]
80060aa: 681b ldr r3, [r3, #0]
80060ac: 67fb str r3, [r7, #124] @ 0x7c
80060ae: 68fb ldr r3, [r7, #12]
80060b0: 681b ldr r3, [r3, #0]
80060b2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80060b6: b29b uxth r3, r3
80060b8: 461a mov r2, r3
80060ba: 6ffb ldr r3, [r7, #124] @ 0x7c
80060bc: 4413 add r3, r2
80060be: 67fb str r3, [r7, #124] @ 0x7c
80060c0: 68bb ldr r3, [r7, #8]
80060c2: 781b ldrb r3, [r3, #0]
80060c4: 011a lsls r2, r3, #4
80060c6: 6ffb ldr r3, [r7, #124] @ 0x7c
80060c8: 4413 add r3, r2
80060ca: f203 4304 addw r3, r3, #1028 @ 0x404
80060ce: 67bb str r3, [r7, #120] @ 0x78
80060d0: 6fbb ldr r3, [r7, #120] @ 0x78
80060d2: 881b ldrh r3, [r3, #0]
80060d4: b29b uxth r3, r3
80060d6: f3c3 0309 ubfx r3, r3, #0, #10
80060da: b29a uxth r2, r3
80060dc: 6fbb ldr r3, [r7, #120] @ 0x78
80060de: 801a strh r2, [r3, #0]
80060e0: 6fbb ldr r3, [r7, #120] @ 0x78
80060e2: 881b ldrh r3, [r3, #0]
80060e4: b29b uxth r3, r3
80060e6: ea6f 4343 mvn.w r3, r3, lsl #17
80060ea: ea6f 4353 mvn.w r3, r3, lsr #17
80060ee: b29a uxth r2, r3
80060f0: 6fbb ldr r3, [r7, #120] @ 0x78
80060f2: 801a strh r2, [r3, #0]
80060f4: e01a b.n 800612c <HAL_PCD_EP_DB_Transmit+0x4b8>
80060f6: 68bb ldr r3, [r7, #8]
80060f8: 785b ldrb r3, [r3, #1]
80060fa: 2b01 cmp r3, #1
80060fc: d116 bne.n 800612c <HAL_PCD_EP_DB_Transmit+0x4b8>
80060fe: 68fb ldr r3, [r7, #12]
8006100: 681b ldr r3, [r3, #0]
8006102: 667b str r3, [r7, #100] @ 0x64
8006104: 68fb ldr r3, [r7, #12]
8006106: 681b ldr r3, [r3, #0]
8006108: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800610c: b29b uxth r3, r3
800610e: 461a mov r2, r3
8006110: 6e7b ldr r3, [r7, #100] @ 0x64
8006112: 4413 add r3, r2
8006114: 667b str r3, [r7, #100] @ 0x64
8006116: 68bb ldr r3, [r7, #8]
8006118: 781b ldrb r3, [r3, #0]
800611a: 011a lsls r2, r3, #4
800611c: 6e7b ldr r3, [r7, #100] @ 0x64
800611e: 4413 add r3, r2
8006120: f203 4304 addw r3, r3, #1028 @ 0x404
8006124: 663b str r3, [r7, #96] @ 0x60
8006126: 6e3b ldr r3, [r7, #96] @ 0x60
8006128: 2200 movs r2, #0
800612a: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
800612c: 68fb ldr r3, [r7, #12]
800612e: 681b ldr r3, [r3, #0]
8006130: 677b str r3, [r7, #116] @ 0x74
8006132: 68bb ldr r3, [r7, #8]
8006134: 785b ldrb r3, [r3, #1]
8006136: 2b00 cmp r3, #0
8006138: d12b bne.n 8006192 <HAL_PCD_EP_DB_Transmit+0x51e>
800613a: 68fb ldr r3, [r7, #12]
800613c: 681b ldr r3, [r3, #0]
800613e: 66fb str r3, [r7, #108] @ 0x6c
8006140: 68fb ldr r3, [r7, #12]
8006142: 681b ldr r3, [r3, #0]
8006144: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006148: b29b uxth r3, r3
800614a: 461a mov r2, r3
800614c: 6efb ldr r3, [r7, #108] @ 0x6c
800614e: 4413 add r3, r2
8006150: 66fb str r3, [r7, #108] @ 0x6c
8006152: 68bb ldr r3, [r7, #8]
8006154: 781b ldrb r3, [r3, #0]
8006156: 011a lsls r2, r3, #4
8006158: 6efb ldr r3, [r7, #108] @ 0x6c
800615a: 4413 add r3, r2
800615c: f203 430c addw r3, r3, #1036 @ 0x40c
8006160: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8006164: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8006168: 881b ldrh r3, [r3, #0]
800616a: b29b uxth r3, r3
800616c: f3c3 0309 ubfx r3, r3, #0, #10
8006170: b29a uxth r2, r3
8006172: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8006176: 801a strh r2, [r3, #0]
8006178: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
800617c: 881b ldrh r3, [r3, #0]
800617e: b29b uxth r3, r3
8006180: ea6f 4343 mvn.w r3, r3, lsl #17
8006184: ea6f 4353 mvn.w r3, r3, lsr #17
8006188: b29a uxth r2, r3
800618a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
800618e: 801a strh r2, [r3, #0]
8006190: e017 b.n 80061c2 <HAL_PCD_EP_DB_Transmit+0x54e>
8006192: 68bb ldr r3, [r7, #8]
8006194: 785b ldrb r3, [r3, #1]
8006196: 2b01 cmp r3, #1
8006198: d113 bne.n 80061c2 <HAL_PCD_EP_DB_Transmit+0x54e>
800619a: 68fb ldr r3, [r7, #12]
800619c: 681b ldr r3, [r3, #0]
800619e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80061a2: b29b uxth r3, r3
80061a4: 461a mov r2, r3
80061a6: 6f7b ldr r3, [r7, #116] @ 0x74
80061a8: 4413 add r3, r2
80061aa: 677b str r3, [r7, #116] @ 0x74
80061ac: 68bb ldr r3, [r7, #8]
80061ae: 781b ldrb r3, [r3, #0]
80061b0: 011a lsls r2, r3, #4
80061b2: 6f7b ldr r3, [r7, #116] @ 0x74
80061b4: 4413 add r3, r2
80061b6: f203 430c addw r3, r3, #1036 @ 0x40c
80061ba: 673b str r3, [r7, #112] @ 0x70
80061bc: 6f3b ldr r3, [r7, #112] @ 0x70
80061be: 2200 movs r2, #0
80061c0: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80061c2: 68bb ldr r3, [r7, #8]
80061c4: 781b ldrb r3, [r3, #0]
80061c6: 4619 mov r1, r3
80061c8: 68f8 ldr r0, [r7, #12]
80061ca: f005 ff68 bl 800c09e <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
80061ce: 88fb ldrh r3, [r7, #6]
80061d0: f403 4380 and.w r3, r3, #16384 @ 0x4000
80061d4: 2b00 cmp r3, #0
80061d6: f040 811a bne.w 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
80061da: 68fb ldr r3, [r7, #12]
80061dc: 681b ldr r3, [r3, #0]
80061de: 461a mov r2, r3
80061e0: 68bb ldr r3, [r7, #8]
80061e2: 781b ldrb r3, [r3, #0]
80061e4: 009b lsls r3, r3, #2
80061e6: 4413 add r3, r2
80061e8: 881b ldrh r3, [r3, #0]
80061ea: b29b uxth r3, r3
80061ec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80061f0: f023 0370 bic.w r3, r3, #112 @ 0x70
80061f4: f8a7 3088 strh.w r3, [r7, #136] @ 0x88
80061f8: 68fb ldr r3, [r7, #12]
80061fa: 681b ldr r3, [r3, #0]
80061fc: 461a mov r2, r3
80061fe: 68bb ldr r3, [r7, #8]
8006200: 781b ldrb r3, [r3, #0]
8006202: 009b lsls r3, r3, #2
8006204: 441a add r2, r3
8006206: f8b7 3088 ldrh.w r3, [r7, #136] @ 0x88
800620a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800620e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006212: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006216: f043 0380 orr.w r3, r3, #128 @ 0x80
800621a: b29b uxth r3, r3
800621c: 8013 strh r3, [r2, #0]
800621e: e0f6 b.n 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8006220: 88fb ldrh r3, [r7, #6]
8006222: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006226: 2b00 cmp r3, #0
8006228: d121 bne.n 800626e <HAL_PCD_EP_DB_Transmit+0x5fa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
800622a: 68fb ldr r3, [r7, #12]
800622c: 681b ldr r3, [r3, #0]
800622e: 461a mov r2, r3
8006230: 68bb ldr r3, [r7, #8]
8006232: 781b ldrb r3, [r3, #0]
8006234: 009b lsls r3, r3, #2
8006236: 4413 add r3, r2
8006238: 881b ldrh r3, [r3, #0]
800623a: b29b uxth r3, r3
800623c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006240: f023 0370 bic.w r3, r3, #112 @ 0x70
8006244: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
8006248: 68fb ldr r3, [r7, #12]
800624a: 681b ldr r3, [r3, #0]
800624c: 461a mov r2, r3
800624e: 68bb ldr r3, [r7, #8]
8006250: 781b ldrb r3, [r3, #0]
8006252: 009b lsls r3, r3, #2
8006254: 441a add r2, r3
8006256: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
800625a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800625e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006262: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006266: f043 0380 orr.w r3, r3, #128 @ 0x80
800626a: b29b uxth r3, r3
800626c: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
800626e: 68bb ldr r3, [r7, #8]
8006270: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8006274: 2b01 cmp r3, #1
8006276: f040 80ca bne.w 800640e <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
800627a: 68bb ldr r3, [r7, #8]
800627c: 695a ldr r2, [r3, #20]
800627e: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8006282: 441a add r2, r3
8006284: 68bb ldr r3, [r7, #8]
8006286: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8006288: 68bb ldr r3, [r7, #8]
800628a: 69da ldr r2, [r3, #28]
800628c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8006290: 441a add r2, r3
8006292: 68bb ldr r3, [r7, #8]
8006294: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8006296: 68bb ldr r3, [r7, #8]
8006298: 6a1a ldr r2, [r3, #32]
800629a: 68bb ldr r3, [r7, #8]
800629c: 691b ldr r3, [r3, #16]
800629e: 429a cmp r2, r3
80062a0: d30b bcc.n 80062ba <HAL_PCD_EP_DB_Transmit+0x646>
{
len = ep->maxpacket;
80062a2: 68bb ldr r3, [r7, #8]
80062a4: 691b ldr r3, [r3, #16]
80062a6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
80062aa: 68bb ldr r3, [r7, #8]
80062ac: 6a1a ldr r2, [r3, #32]
80062ae: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80062b2: 1ad2 subs r2, r2, r3
80062b4: 68bb ldr r3, [r7, #8]
80062b6: 621a str r2, [r3, #32]
80062b8: e017 b.n 80062ea <HAL_PCD_EP_DB_Transmit+0x676>
}
else if (ep->xfer_len_db == 0U)
80062ba: 68bb ldr r3, [r7, #8]
80062bc: 6a1b ldr r3, [r3, #32]
80062be: 2b00 cmp r3, #0
80062c0: d108 bne.n 80062d4 <HAL_PCD_EP_DB_Transmit+0x660>
{
len = TxPctSize;
80062c2: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
80062c6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
80062ca: 68bb ldr r3, [r7, #8]
80062cc: 2200 movs r2, #0
80062ce: f883 2024 strb.w r2, [r3, #36] @ 0x24
80062d2: e00a b.n 80062ea <HAL_PCD_EP_DB_Transmit+0x676>
}
else
{
len = ep->xfer_len_db;
80062d4: 68bb ldr r3, [r7, #8]
80062d6: 6a1b ldr r3, [r3, #32]
80062d8: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
80062dc: 68bb ldr r3, [r7, #8]
80062de: 2200 movs r2, #0
80062e0: 621a str r2, [r3, #32]
ep->xfer_fill_db = 0;
80062e2: 68bb ldr r3, [r7, #8]
80062e4: 2200 movs r2, #0
80062e6: f883 2024 strb.w r2, [r3, #36] @ 0x24
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
80062ea: 68fb ldr r3, [r7, #12]
80062ec: 681b ldr r3, [r3, #0]
80062ee: 657b str r3, [r7, #84] @ 0x54
80062f0: 68bb ldr r3, [r7, #8]
80062f2: 785b ldrb r3, [r3, #1]
80062f4: 2b00 cmp r3, #0
80062f6: d165 bne.n 80063c4 <HAL_PCD_EP_DB_Transmit+0x750>
80062f8: 68fb ldr r3, [r7, #12]
80062fa: 681b ldr r3, [r3, #0]
80062fc: 65fb str r3, [r7, #92] @ 0x5c
80062fe: 68fb ldr r3, [r7, #12]
8006300: 681b ldr r3, [r3, #0]
8006302: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006306: b29b uxth r3, r3
8006308: 461a mov r2, r3
800630a: 6dfb ldr r3, [r7, #92] @ 0x5c
800630c: 4413 add r3, r2
800630e: 65fb str r3, [r7, #92] @ 0x5c
8006310: 68bb ldr r3, [r7, #8]
8006312: 781b ldrb r3, [r3, #0]
8006314: 011a lsls r2, r3, #4
8006316: 6dfb ldr r3, [r7, #92] @ 0x5c
8006318: 4413 add r3, r2
800631a: f203 430c addw r3, r3, #1036 @ 0x40c
800631e: 65bb str r3, [r7, #88] @ 0x58
8006320: 6dbb ldr r3, [r7, #88] @ 0x58
8006322: 881b ldrh r3, [r3, #0]
8006324: b29b uxth r3, r3
8006326: f3c3 0309 ubfx r3, r3, #0, #10
800632a: b29a uxth r2, r3
800632c: 6dbb ldr r3, [r7, #88] @ 0x58
800632e: 801a strh r2, [r3, #0]
8006330: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006334: 2b3e cmp r3, #62 @ 0x3e
8006336: d91d bls.n 8006374 <HAL_PCD_EP_DB_Transmit+0x700>
8006338: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800633c: 095b lsrs r3, r3, #5
800633e: 66bb str r3, [r7, #104] @ 0x68
8006340: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006344: f003 031f and.w r3, r3, #31
8006348: 2b00 cmp r3, #0
800634a: d102 bne.n 8006352 <HAL_PCD_EP_DB_Transmit+0x6de>
800634c: 6ebb ldr r3, [r7, #104] @ 0x68
800634e: 3b01 subs r3, #1
8006350: 66bb str r3, [r7, #104] @ 0x68
8006352: 6dbb ldr r3, [r7, #88] @ 0x58
8006354: 881b ldrh r3, [r3, #0]
8006356: b29a uxth r2, r3
8006358: 6ebb ldr r3, [r7, #104] @ 0x68
800635a: b29b uxth r3, r3
800635c: 029b lsls r3, r3, #10
800635e: b29b uxth r3, r3
8006360: 4313 orrs r3, r2
8006362: b29b uxth r3, r3
8006364: ea6f 4343 mvn.w r3, r3, lsl #17
8006368: ea6f 4353 mvn.w r3, r3, lsr #17
800636c: b29a uxth r2, r3
800636e: 6dbb ldr r3, [r7, #88] @ 0x58
8006370: 801a strh r2, [r3, #0]
8006372: e041 b.n 80063f8 <HAL_PCD_EP_DB_Transmit+0x784>
8006374: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006378: 2b00 cmp r3, #0
800637a: d10a bne.n 8006392 <HAL_PCD_EP_DB_Transmit+0x71e>
800637c: 6dbb ldr r3, [r7, #88] @ 0x58
800637e: 881b ldrh r3, [r3, #0]
8006380: b29b uxth r3, r3
8006382: ea6f 4343 mvn.w r3, r3, lsl #17
8006386: ea6f 4353 mvn.w r3, r3, lsr #17
800638a: b29a uxth r2, r3
800638c: 6dbb ldr r3, [r7, #88] @ 0x58
800638e: 801a strh r2, [r3, #0]
8006390: e032 b.n 80063f8 <HAL_PCD_EP_DB_Transmit+0x784>
8006392: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006396: 085b lsrs r3, r3, #1
8006398: 66bb str r3, [r7, #104] @ 0x68
800639a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800639e: f003 0301 and.w r3, r3, #1
80063a2: 2b00 cmp r3, #0
80063a4: d002 beq.n 80063ac <HAL_PCD_EP_DB_Transmit+0x738>
80063a6: 6ebb ldr r3, [r7, #104] @ 0x68
80063a8: 3301 adds r3, #1
80063aa: 66bb str r3, [r7, #104] @ 0x68
80063ac: 6dbb ldr r3, [r7, #88] @ 0x58
80063ae: 881b ldrh r3, [r3, #0]
80063b0: b29a uxth r2, r3
80063b2: 6ebb ldr r3, [r7, #104] @ 0x68
80063b4: b29b uxth r3, r3
80063b6: 029b lsls r3, r3, #10
80063b8: b29b uxth r3, r3
80063ba: 4313 orrs r3, r2
80063bc: b29a uxth r2, r3
80063be: 6dbb ldr r3, [r7, #88] @ 0x58
80063c0: 801a strh r2, [r3, #0]
80063c2: e019 b.n 80063f8 <HAL_PCD_EP_DB_Transmit+0x784>
80063c4: 68bb ldr r3, [r7, #8]
80063c6: 785b ldrb r3, [r3, #1]
80063c8: 2b01 cmp r3, #1
80063ca: d115 bne.n 80063f8 <HAL_PCD_EP_DB_Transmit+0x784>
80063cc: 68fb ldr r3, [r7, #12]
80063ce: 681b ldr r3, [r3, #0]
80063d0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80063d4: b29b uxth r3, r3
80063d6: 461a mov r2, r3
80063d8: 6d7b ldr r3, [r7, #84] @ 0x54
80063da: 4413 add r3, r2
80063dc: 657b str r3, [r7, #84] @ 0x54
80063de: 68bb ldr r3, [r7, #8]
80063e0: 781b ldrb r3, [r3, #0]
80063e2: 011a lsls r2, r3, #4
80063e4: 6d7b ldr r3, [r7, #84] @ 0x54
80063e6: 4413 add r3, r2
80063e8: f203 430c addw r3, r3, #1036 @ 0x40c
80063ec: 653b str r3, [r7, #80] @ 0x50
80063ee: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80063f2: b29a uxth r2, r3
80063f4: 6d3b ldr r3, [r7, #80] @ 0x50
80063f6: 801a strh r2, [r3, #0]
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
80063f8: 68fb ldr r3, [r7, #12]
80063fa: 6818 ldr r0, [r3, #0]
80063fc: 68bb ldr r3, [r7, #8]
80063fe: 6959 ldr r1, [r3, #20]
8006400: 68bb ldr r3, [r7, #8]
8006402: 895a ldrh r2, [r3, #10]
8006404: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006408: b29b uxth r3, r3
800640a: f003 ff84 bl 800a316 <USB_WritePMA>
}
}
}
/*enable endpoint IN*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
800640e: 68fb ldr r3, [r7, #12]
8006410: 681b ldr r3, [r3, #0]
8006412: 461a mov r2, r3
8006414: 68bb ldr r3, [r7, #8]
8006416: 781b ldrb r3, [r3, #0]
8006418: 009b lsls r3, r3, #2
800641a: 4413 add r3, r2
800641c: 881b ldrh r3, [r3, #0]
800641e: b29b uxth r3, r3
8006420: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006424: f023 0340 bic.w r3, r3, #64 @ 0x40
8006428: 82bb strh r3, [r7, #20]
800642a: 8abb ldrh r3, [r7, #20]
800642c: f083 0310 eor.w r3, r3, #16
8006430: 82bb strh r3, [r7, #20]
8006432: 8abb ldrh r3, [r7, #20]
8006434: f083 0320 eor.w r3, r3, #32
8006438: 82bb strh r3, [r7, #20]
800643a: 68fb ldr r3, [r7, #12]
800643c: 681b ldr r3, [r3, #0]
800643e: 461a mov r2, r3
8006440: 68bb ldr r3, [r7, #8]
8006442: 781b ldrb r3, [r3, #0]
8006444: 009b lsls r3, r3, #2
8006446: 441a add r2, r3
8006448: 8abb ldrh r3, [r7, #20]
800644a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800644e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006452: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006456: f043 0380 orr.w r3, r3, #128 @ 0x80
800645a: b29b uxth r3, r3
800645c: 8013 strh r3, [r2, #0]
return HAL_OK;
800645e: 2300 movs r3, #0
}
8006460: 4618 mov r0, r3
8006462: 3790 adds r7, #144 @ 0x90
8006464: 46bd mov sp, r7
8006466: bd80 pop {r7, pc}
08006468 <HAL_PCDEx_PMAConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
8006468: b480 push {r7}
800646a: b087 sub sp, #28
800646c: af00 add r7, sp, #0
800646e: 60f8 str r0, [r7, #12]
8006470: 607b str r3, [r7, #4]
8006472: 460b mov r3, r1
8006474: 817b strh r3, [r7, #10]
8006476: 4613 mov r3, r2
8006478: 813b strh r3, [r7, #8]
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
800647a: 897b ldrh r3, [r7, #10]
800647c: f003 0380 and.w r3, r3, #128 @ 0x80
8006480: b29b uxth r3, r3
8006482: 2b00 cmp r3, #0
8006484: d00b beq.n 800649e <HAL_PCDEx_PMAConfig+0x36>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8006486: 897b ldrh r3, [r7, #10]
8006488: f003 0207 and.w r2, r3, #7
800648c: 4613 mov r3, r2
800648e: 009b lsls r3, r3, #2
8006490: 4413 add r3, r2
8006492: 00db lsls r3, r3, #3
8006494: 3310 adds r3, #16
8006496: 68fa ldr r2, [r7, #12]
8006498: 4413 add r3, r2
800649a: 617b str r3, [r7, #20]
800649c: e009 b.n 80064b2 <HAL_PCDEx_PMAConfig+0x4a>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
800649e: 897a ldrh r2, [r7, #10]
80064a0: 4613 mov r3, r2
80064a2: 009b lsls r3, r3, #2
80064a4: 4413 add r3, r2
80064a6: 00db lsls r3, r3, #3
80064a8: f503 73a8 add.w r3, r3, #336 @ 0x150
80064ac: 68fa ldr r2, [r7, #12]
80064ae: 4413 add r3, r2
80064b0: 617b str r3, [r7, #20]
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
80064b2: 893b ldrh r3, [r7, #8]
80064b4: 2b00 cmp r3, #0
80064b6: d107 bne.n 80064c8 <HAL_PCDEx_PMAConfig+0x60>
{
/* Single Buffer */
ep->doublebuffer = 0U;
80064b8: 697b ldr r3, [r7, #20]
80064ba: 2200 movs r2, #0
80064bc: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
80064be: 687b ldr r3, [r7, #4]
80064c0: b29a uxth r2, r3
80064c2: 697b ldr r3, [r7, #20]
80064c4: 80da strh r2, [r3, #6]
80064c6: e00b b.n 80064e0 <HAL_PCDEx_PMAConfig+0x78>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
80064c8: 697b ldr r3, [r7, #20]
80064ca: 2201 movs r2, #1
80064cc: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
80064ce: 687b ldr r3, [r7, #4]
80064d0: b29a uxth r2, r3
80064d2: 697b ldr r3, [r7, #20]
80064d4: 811a strh r2, [r3, #8]
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
80064d6: 687b ldr r3, [r7, #4]
80064d8: 0c1b lsrs r3, r3, #16
80064da: b29a uxth r2, r3
80064dc: 697b ldr r3, [r7, #20]
80064de: 815a strh r2, [r3, #10]
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
80064e0: 2300 movs r3, #0
}
80064e2: 4618 mov r0, r3
80064e4: 371c adds r7, #28
80064e6: 46bd mov sp, r7
80064e8: bc80 pop {r7}
80064ea: 4770 bx lr
080064ec <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80064ec: b580 push {r7, lr}
80064ee: b086 sub sp, #24
80064f0: af00 add r7, sp, #0
80064f2: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80064f4: 687b ldr r3, [r7, #4]
80064f6: 2b00 cmp r3, #0
80064f8: d101 bne.n 80064fe <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80064fa: 2301 movs r3, #1
80064fc: e272 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80064fe: 687b ldr r3, [r7, #4]
8006500: 681b ldr r3, [r3, #0]
8006502: f003 0301 and.w r3, r3, #1
8006506: 2b00 cmp r3, #0
8006508: f000 8087 beq.w 800661a <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
800650c: 4b92 ldr r3, [pc, #584] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800650e: 685b ldr r3, [r3, #4]
8006510: f003 030c and.w r3, r3, #12
8006514: 2b04 cmp r3, #4
8006516: d00c beq.n 8006532 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8006518: 4b8f ldr r3, [pc, #572] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800651a: 685b ldr r3, [r3, #4]
800651c: f003 030c and.w r3, r3, #12
8006520: 2b08 cmp r3, #8
8006522: d112 bne.n 800654a <HAL_RCC_OscConfig+0x5e>
8006524: 4b8c ldr r3, [pc, #560] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006526: 685b ldr r3, [r3, #4]
8006528: f403 3380 and.w r3, r3, #65536 @ 0x10000
800652c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8006530: d10b bne.n 800654a <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8006532: 4b89 ldr r3, [pc, #548] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006534: 681b ldr r3, [r3, #0]
8006536: f403 3300 and.w r3, r3, #131072 @ 0x20000
800653a: 2b00 cmp r3, #0
800653c: d06c beq.n 8006618 <HAL_RCC_OscConfig+0x12c>
800653e: 687b ldr r3, [r7, #4]
8006540: 685b ldr r3, [r3, #4]
8006542: 2b00 cmp r3, #0
8006544: d168 bne.n 8006618 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8006546: 2301 movs r3, #1
8006548: e24c b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800654a: 687b ldr r3, [r7, #4]
800654c: 685b ldr r3, [r3, #4]
800654e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8006552: d106 bne.n 8006562 <HAL_RCC_OscConfig+0x76>
8006554: 4b80 ldr r3, [pc, #512] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006556: 681b ldr r3, [r3, #0]
8006558: 4a7f ldr r2, [pc, #508] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800655a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800655e: 6013 str r3, [r2, #0]
8006560: e02e b.n 80065c0 <HAL_RCC_OscConfig+0xd4>
8006562: 687b ldr r3, [r7, #4]
8006564: 685b ldr r3, [r3, #4]
8006566: 2b00 cmp r3, #0
8006568: d10c bne.n 8006584 <HAL_RCC_OscConfig+0x98>
800656a: 4b7b ldr r3, [pc, #492] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800656c: 681b ldr r3, [r3, #0]
800656e: 4a7a ldr r2, [pc, #488] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006570: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8006574: 6013 str r3, [r2, #0]
8006576: 4b78 ldr r3, [pc, #480] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006578: 681b ldr r3, [r3, #0]
800657a: 4a77 ldr r2, [pc, #476] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800657c: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8006580: 6013 str r3, [r2, #0]
8006582: e01d b.n 80065c0 <HAL_RCC_OscConfig+0xd4>
8006584: 687b ldr r3, [r7, #4]
8006586: 685b ldr r3, [r3, #4]
8006588: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
800658c: d10c bne.n 80065a8 <HAL_RCC_OscConfig+0xbc>
800658e: 4b72 ldr r3, [pc, #456] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006590: 681b ldr r3, [r3, #0]
8006592: 4a71 ldr r2, [pc, #452] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006594: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8006598: 6013 str r3, [r2, #0]
800659a: 4b6f ldr r3, [pc, #444] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800659c: 681b ldr r3, [r3, #0]
800659e: 4a6e ldr r2, [pc, #440] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80065a0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80065a4: 6013 str r3, [r2, #0]
80065a6: e00b b.n 80065c0 <HAL_RCC_OscConfig+0xd4>
80065a8: 4b6b ldr r3, [pc, #428] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80065aa: 681b ldr r3, [r3, #0]
80065ac: 4a6a ldr r2, [pc, #424] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80065ae: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80065b2: 6013 str r3, [r2, #0]
80065b4: 4b68 ldr r3, [pc, #416] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80065b6: 681b ldr r3, [r3, #0]
80065b8: 4a67 ldr r2, [pc, #412] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80065ba: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80065be: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80065c0: 687b ldr r3, [r7, #4]
80065c2: 685b ldr r3, [r3, #4]
80065c4: 2b00 cmp r3, #0
80065c6: d013 beq.n 80065f0 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80065c8: f7fc ff8c bl 80034e4 <HAL_GetTick>
80065cc: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80065ce: e008 b.n 80065e2 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80065d0: f7fc ff88 bl 80034e4 <HAL_GetTick>
80065d4: 4602 mov r2, r0
80065d6: 693b ldr r3, [r7, #16]
80065d8: 1ad3 subs r3, r2, r3
80065da: 2b64 cmp r3, #100 @ 0x64
80065dc: d901 bls.n 80065e2 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
80065de: 2303 movs r3, #3
80065e0: e200 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80065e2: 4b5d ldr r3, [pc, #372] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80065e4: 681b ldr r3, [r3, #0]
80065e6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80065ea: 2b00 cmp r3, #0
80065ec: d0f0 beq.n 80065d0 <HAL_RCC_OscConfig+0xe4>
80065ee: e014 b.n 800661a <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80065f0: f7fc ff78 bl 80034e4 <HAL_GetTick>
80065f4: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80065f6: e008 b.n 800660a <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80065f8: f7fc ff74 bl 80034e4 <HAL_GetTick>
80065fc: 4602 mov r2, r0
80065fe: 693b ldr r3, [r7, #16]
8006600: 1ad3 subs r3, r2, r3
8006602: 2b64 cmp r3, #100 @ 0x64
8006604: d901 bls.n 800660a <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8006606: 2303 movs r3, #3
8006608: e1ec b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800660a: 4b53 ldr r3, [pc, #332] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800660c: 681b ldr r3, [r3, #0]
800660e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8006612: 2b00 cmp r3, #0
8006614: d1f0 bne.n 80065f8 <HAL_RCC_OscConfig+0x10c>
8006616: e000 b.n 800661a <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8006618: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800661a: 687b ldr r3, [r7, #4]
800661c: 681b ldr r3, [r3, #0]
800661e: f003 0302 and.w r3, r3, #2
8006622: 2b00 cmp r3, #0
8006624: d063 beq.n 80066ee <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8006626: 4b4c ldr r3, [pc, #304] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006628: 685b ldr r3, [r3, #4]
800662a: f003 030c and.w r3, r3, #12
800662e: 2b00 cmp r3, #0
8006630: d00b beq.n 800664a <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8006632: 4b49 ldr r3, [pc, #292] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006634: 685b ldr r3, [r3, #4]
8006636: f003 030c and.w r3, r3, #12
800663a: 2b08 cmp r3, #8
800663c: d11c bne.n 8006678 <HAL_RCC_OscConfig+0x18c>
800663e: 4b46 ldr r3, [pc, #280] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006640: 685b ldr r3, [r3, #4]
8006642: f403 3380 and.w r3, r3, #65536 @ 0x10000
8006646: 2b00 cmp r3, #0
8006648: d116 bne.n 8006678 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800664a: 4b43 ldr r3, [pc, #268] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
800664c: 681b ldr r3, [r3, #0]
800664e: f003 0302 and.w r3, r3, #2
8006652: 2b00 cmp r3, #0
8006654: d005 beq.n 8006662 <HAL_RCC_OscConfig+0x176>
8006656: 687b ldr r3, [r7, #4]
8006658: 691b ldr r3, [r3, #16]
800665a: 2b01 cmp r3, #1
800665c: d001 beq.n 8006662 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
800665e: 2301 movs r3, #1
8006660: e1c0 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8006662: 4b3d ldr r3, [pc, #244] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006664: 681b ldr r3, [r3, #0]
8006666: f023 02f8 bic.w r2, r3, #248 @ 0xf8
800666a: 687b ldr r3, [r7, #4]
800666c: 695b ldr r3, [r3, #20]
800666e: 00db lsls r3, r3, #3
8006670: 4939 ldr r1, [pc, #228] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006672: 4313 orrs r3, r2
8006674: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8006676: e03a b.n 80066ee <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8006678: 687b ldr r3, [r7, #4]
800667a: 691b ldr r3, [r3, #16]
800667c: 2b00 cmp r3, #0
800667e: d020 beq.n 80066c2 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8006680: 4b36 ldr r3, [pc, #216] @ (800675c <HAL_RCC_OscConfig+0x270>)
8006682: 2201 movs r2, #1
8006684: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8006686: f7fc ff2d bl 80034e4 <HAL_GetTick>
800668a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800668c: e008 b.n 80066a0 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800668e: f7fc ff29 bl 80034e4 <HAL_GetTick>
8006692: 4602 mov r2, r0
8006694: 693b ldr r3, [r7, #16]
8006696: 1ad3 subs r3, r2, r3
8006698: 2b02 cmp r3, #2
800669a: d901 bls.n 80066a0 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
800669c: 2303 movs r3, #3
800669e: e1a1 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80066a0: 4b2d ldr r3, [pc, #180] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80066a2: 681b ldr r3, [r3, #0]
80066a4: f003 0302 and.w r3, r3, #2
80066a8: 2b00 cmp r3, #0
80066aa: d0f0 beq.n 800668e <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80066ac: 4b2a ldr r3, [pc, #168] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80066ae: 681b ldr r3, [r3, #0]
80066b0: f023 02f8 bic.w r2, r3, #248 @ 0xf8
80066b4: 687b ldr r3, [r7, #4]
80066b6: 695b ldr r3, [r3, #20]
80066b8: 00db lsls r3, r3, #3
80066ba: 4927 ldr r1, [pc, #156] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80066bc: 4313 orrs r3, r2
80066be: 600b str r3, [r1, #0]
80066c0: e015 b.n 80066ee <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80066c2: 4b26 ldr r3, [pc, #152] @ (800675c <HAL_RCC_OscConfig+0x270>)
80066c4: 2200 movs r2, #0
80066c6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80066c8: f7fc ff0c bl 80034e4 <HAL_GetTick>
80066cc: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80066ce: e008 b.n 80066e2 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80066d0: f7fc ff08 bl 80034e4 <HAL_GetTick>
80066d4: 4602 mov r2, r0
80066d6: 693b ldr r3, [r7, #16]
80066d8: 1ad3 subs r3, r2, r3
80066da: 2b02 cmp r3, #2
80066dc: d901 bls.n 80066e2 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
80066de: 2303 movs r3, #3
80066e0: e180 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80066e2: 4b1d ldr r3, [pc, #116] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
80066e4: 681b ldr r3, [r3, #0]
80066e6: f003 0302 and.w r3, r3, #2
80066ea: 2b00 cmp r3, #0
80066ec: d1f0 bne.n 80066d0 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80066ee: 687b ldr r3, [r7, #4]
80066f0: 681b ldr r3, [r3, #0]
80066f2: f003 0308 and.w r3, r3, #8
80066f6: 2b00 cmp r3, #0
80066f8: d03a beq.n 8006770 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80066fa: 687b ldr r3, [r7, #4]
80066fc: 699b ldr r3, [r3, #24]
80066fe: 2b00 cmp r3, #0
8006700: d019 beq.n 8006736 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8006702: 4b17 ldr r3, [pc, #92] @ (8006760 <HAL_RCC_OscConfig+0x274>)
8006704: 2201 movs r2, #1
8006706: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8006708: f7fc feec bl 80034e4 <HAL_GetTick>
800670c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800670e: e008 b.n 8006722 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8006710: f7fc fee8 bl 80034e4 <HAL_GetTick>
8006714: 4602 mov r2, r0
8006716: 693b ldr r3, [r7, #16]
8006718: 1ad3 subs r3, r2, r3
800671a: 2b02 cmp r3, #2
800671c: d901 bls.n 8006722 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
800671e: 2303 movs r3, #3
8006720: e160 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8006722: 4b0d ldr r3, [pc, #52] @ (8006758 <HAL_RCC_OscConfig+0x26c>)
8006724: 6a5b ldr r3, [r3, #36] @ 0x24
8006726: f003 0302 and.w r3, r3, #2
800672a: 2b00 cmp r3, #0
800672c: d0f0 beq.n 8006710 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
800672e: 2001 movs r0, #1
8006730: f000 fad0 bl 8006cd4 <RCC_Delay>
8006734: e01c b.n 8006770 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8006736: 4b0a ldr r3, [pc, #40] @ (8006760 <HAL_RCC_OscConfig+0x274>)
8006738: 2200 movs r2, #0
800673a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800673c: f7fc fed2 bl 80034e4 <HAL_GetTick>
8006740: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8006742: e00f b.n 8006764 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8006744: f7fc fece bl 80034e4 <HAL_GetTick>
8006748: 4602 mov r2, r0
800674a: 693b ldr r3, [r7, #16]
800674c: 1ad3 subs r3, r2, r3
800674e: 2b02 cmp r3, #2
8006750: d908 bls.n 8006764 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8006752: 2303 movs r3, #3
8006754: e146 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
8006756: bf00 nop
8006758: 40021000 .word 0x40021000
800675c: 42420000 .word 0x42420000
8006760: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8006764: 4b92 ldr r3, [pc, #584] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006766: 6a5b ldr r3, [r3, #36] @ 0x24
8006768: f003 0302 and.w r3, r3, #2
800676c: 2b00 cmp r3, #0
800676e: d1e9 bne.n 8006744 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8006770: 687b ldr r3, [r7, #4]
8006772: 681b ldr r3, [r3, #0]
8006774: f003 0304 and.w r3, r3, #4
8006778: 2b00 cmp r3, #0
800677a: f000 80a6 beq.w 80068ca <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
800677e: 2300 movs r3, #0
8006780: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8006782: 4b8b ldr r3, [pc, #556] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006784: 69db ldr r3, [r3, #28]
8006786: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800678a: 2b00 cmp r3, #0
800678c: d10d bne.n 80067aa <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
800678e: 4b88 ldr r3, [pc, #544] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006790: 69db ldr r3, [r3, #28]
8006792: 4a87 ldr r2, [pc, #540] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006794: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8006798: 61d3 str r3, [r2, #28]
800679a: 4b85 ldr r3, [pc, #532] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800679c: 69db ldr r3, [r3, #28]
800679e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80067a2: 60bb str r3, [r7, #8]
80067a4: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80067a6: 2301 movs r3, #1
80067a8: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80067aa: 4b82 ldr r3, [pc, #520] @ (80069b4 <HAL_RCC_OscConfig+0x4c8>)
80067ac: 681b ldr r3, [r3, #0]
80067ae: f403 7380 and.w r3, r3, #256 @ 0x100
80067b2: 2b00 cmp r3, #0
80067b4: d118 bne.n 80067e8 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80067b6: 4b7f ldr r3, [pc, #508] @ (80069b4 <HAL_RCC_OscConfig+0x4c8>)
80067b8: 681b ldr r3, [r3, #0]
80067ba: 4a7e ldr r2, [pc, #504] @ (80069b4 <HAL_RCC_OscConfig+0x4c8>)
80067bc: f443 7380 orr.w r3, r3, #256 @ 0x100
80067c0: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80067c2: f7fc fe8f bl 80034e4 <HAL_GetTick>
80067c6: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80067c8: e008 b.n 80067dc <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80067ca: f7fc fe8b bl 80034e4 <HAL_GetTick>
80067ce: 4602 mov r2, r0
80067d0: 693b ldr r3, [r7, #16]
80067d2: 1ad3 subs r3, r2, r3
80067d4: 2b64 cmp r3, #100 @ 0x64
80067d6: d901 bls.n 80067dc <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
80067d8: 2303 movs r3, #3
80067da: e103 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80067dc: 4b75 ldr r3, [pc, #468] @ (80069b4 <HAL_RCC_OscConfig+0x4c8>)
80067de: 681b ldr r3, [r3, #0]
80067e0: f403 7380 and.w r3, r3, #256 @ 0x100
80067e4: 2b00 cmp r3, #0
80067e6: d0f0 beq.n 80067ca <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80067e8: 687b ldr r3, [r7, #4]
80067ea: 68db ldr r3, [r3, #12]
80067ec: 2b01 cmp r3, #1
80067ee: d106 bne.n 80067fe <HAL_RCC_OscConfig+0x312>
80067f0: 4b6f ldr r3, [pc, #444] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
80067f2: 6a1b ldr r3, [r3, #32]
80067f4: 4a6e ldr r2, [pc, #440] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
80067f6: f043 0301 orr.w r3, r3, #1
80067fa: 6213 str r3, [r2, #32]
80067fc: e02d b.n 800685a <HAL_RCC_OscConfig+0x36e>
80067fe: 687b ldr r3, [r7, #4]
8006800: 68db ldr r3, [r3, #12]
8006802: 2b00 cmp r3, #0
8006804: d10c bne.n 8006820 <HAL_RCC_OscConfig+0x334>
8006806: 4b6a ldr r3, [pc, #424] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006808: 6a1b ldr r3, [r3, #32]
800680a: 4a69 ldr r2, [pc, #420] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800680c: f023 0301 bic.w r3, r3, #1
8006810: 6213 str r3, [r2, #32]
8006812: 4b67 ldr r3, [pc, #412] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006814: 6a1b ldr r3, [r3, #32]
8006816: 4a66 ldr r2, [pc, #408] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006818: f023 0304 bic.w r3, r3, #4
800681c: 6213 str r3, [r2, #32]
800681e: e01c b.n 800685a <HAL_RCC_OscConfig+0x36e>
8006820: 687b ldr r3, [r7, #4]
8006822: 68db ldr r3, [r3, #12]
8006824: 2b05 cmp r3, #5
8006826: d10c bne.n 8006842 <HAL_RCC_OscConfig+0x356>
8006828: 4b61 ldr r3, [pc, #388] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800682a: 6a1b ldr r3, [r3, #32]
800682c: 4a60 ldr r2, [pc, #384] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800682e: f043 0304 orr.w r3, r3, #4
8006832: 6213 str r3, [r2, #32]
8006834: 4b5e ldr r3, [pc, #376] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006836: 6a1b ldr r3, [r3, #32]
8006838: 4a5d ldr r2, [pc, #372] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800683a: f043 0301 orr.w r3, r3, #1
800683e: 6213 str r3, [r2, #32]
8006840: e00b b.n 800685a <HAL_RCC_OscConfig+0x36e>
8006842: 4b5b ldr r3, [pc, #364] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006844: 6a1b ldr r3, [r3, #32]
8006846: 4a5a ldr r2, [pc, #360] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006848: f023 0301 bic.w r3, r3, #1
800684c: 6213 str r3, [r2, #32]
800684e: 4b58 ldr r3, [pc, #352] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006850: 6a1b ldr r3, [r3, #32]
8006852: 4a57 ldr r2, [pc, #348] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006854: f023 0304 bic.w r3, r3, #4
8006858: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800685a: 687b ldr r3, [r7, #4]
800685c: 68db ldr r3, [r3, #12]
800685e: 2b00 cmp r3, #0
8006860: d015 beq.n 800688e <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8006862: f7fc fe3f bl 80034e4 <HAL_GetTick>
8006866: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8006868: e00a b.n 8006880 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800686a: f7fc fe3b bl 80034e4 <HAL_GetTick>
800686e: 4602 mov r2, r0
8006870: 693b ldr r3, [r7, #16]
8006872: 1ad3 subs r3, r2, r3
8006874: f241 3288 movw r2, #5000 @ 0x1388
8006878: 4293 cmp r3, r2
800687a: d901 bls.n 8006880 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
800687c: 2303 movs r3, #3
800687e: e0b1 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8006880: 4b4b ldr r3, [pc, #300] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006882: 6a1b ldr r3, [r3, #32]
8006884: f003 0302 and.w r3, r3, #2
8006888: 2b00 cmp r3, #0
800688a: d0ee beq.n 800686a <HAL_RCC_OscConfig+0x37e>
800688c: e014 b.n 80068b8 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800688e: f7fc fe29 bl 80034e4 <HAL_GetTick>
8006892: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8006894: e00a b.n 80068ac <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8006896: f7fc fe25 bl 80034e4 <HAL_GetTick>
800689a: 4602 mov r2, r0
800689c: 693b ldr r3, [r7, #16]
800689e: 1ad3 subs r3, r2, r3
80068a0: f241 3288 movw r2, #5000 @ 0x1388
80068a4: 4293 cmp r3, r2
80068a6: d901 bls.n 80068ac <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
80068a8: 2303 movs r3, #3
80068aa: e09b b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80068ac: 4b40 ldr r3, [pc, #256] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
80068ae: 6a1b ldr r3, [r3, #32]
80068b0: f003 0302 and.w r3, r3, #2
80068b4: 2b00 cmp r3, #0
80068b6: d1ee bne.n 8006896 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
80068b8: 7dfb ldrb r3, [r7, #23]
80068ba: 2b01 cmp r3, #1
80068bc: d105 bne.n 80068ca <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
80068be: 4b3c ldr r3, [pc, #240] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
80068c0: 69db ldr r3, [r3, #28]
80068c2: 4a3b ldr r2, [pc, #236] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
80068c4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80068c8: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80068ca: 687b ldr r3, [r7, #4]
80068cc: 69db ldr r3, [r3, #28]
80068ce: 2b00 cmp r3, #0
80068d0: f000 8087 beq.w 80069e2 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80068d4: 4b36 ldr r3, [pc, #216] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
80068d6: 685b ldr r3, [r3, #4]
80068d8: f003 030c and.w r3, r3, #12
80068dc: 2b08 cmp r3, #8
80068de: d061 beq.n 80069a4 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80068e0: 687b ldr r3, [r7, #4]
80068e2: 69db ldr r3, [r3, #28]
80068e4: 2b02 cmp r3, #2
80068e6: d146 bne.n 8006976 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80068e8: 4b33 ldr r3, [pc, #204] @ (80069b8 <HAL_RCC_OscConfig+0x4cc>)
80068ea: 2200 movs r2, #0
80068ec: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80068ee: f7fc fdf9 bl 80034e4 <HAL_GetTick>
80068f2: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80068f4: e008 b.n 8006908 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80068f6: f7fc fdf5 bl 80034e4 <HAL_GetTick>
80068fa: 4602 mov r2, r0
80068fc: 693b ldr r3, [r7, #16]
80068fe: 1ad3 subs r3, r2, r3
8006900: 2b02 cmp r3, #2
8006902: d901 bls.n 8006908 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8006904: 2303 movs r3, #3
8006906: e06d b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8006908: 4b29 ldr r3, [pc, #164] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800690a: 681b ldr r3, [r3, #0]
800690c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006910: 2b00 cmp r3, #0
8006912: d1f0 bne.n 80068f6 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8006914: 687b ldr r3, [r7, #4]
8006916: 6a1b ldr r3, [r3, #32]
8006918: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800691c: d108 bne.n 8006930 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
800691e: 4b24 ldr r3, [pc, #144] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006920: 685b ldr r3, [r3, #4]
8006922: f423 3200 bic.w r2, r3, #131072 @ 0x20000
8006926: 687b ldr r3, [r7, #4]
8006928: 689b ldr r3, [r3, #8]
800692a: 4921 ldr r1, [pc, #132] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800692c: 4313 orrs r3, r2
800692e: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8006930: 4b1f ldr r3, [pc, #124] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006932: 685b ldr r3, [r3, #4]
8006934: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8006938: 687b ldr r3, [r7, #4]
800693a: 6a19 ldr r1, [r3, #32]
800693c: 687b ldr r3, [r7, #4]
800693e: 6a5b ldr r3, [r3, #36] @ 0x24
8006940: 430b orrs r3, r1
8006942: 491b ldr r1, [pc, #108] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006944: 4313 orrs r3, r2
8006946: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8006948: 4b1b ldr r3, [pc, #108] @ (80069b8 <HAL_RCC_OscConfig+0x4cc>)
800694a: 2201 movs r2, #1
800694c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800694e: f7fc fdc9 bl 80034e4 <HAL_GetTick>
8006952: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8006954: e008 b.n 8006968 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8006956: f7fc fdc5 bl 80034e4 <HAL_GetTick>
800695a: 4602 mov r2, r0
800695c: 693b ldr r3, [r7, #16]
800695e: 1ad3 subs r3, r2, r3
8006960: 2b02 cmp r3, #2
8006962: d901 bls.n 8006968 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8006964: 2303 movs r3, #3
8006966: e03d b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8006968: 4b11 ldr r3, [pc, #68] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
800696a: 681b ldr r3, [r3, #0]
800696c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006970: 2b00 cmp r3, #0
8006972: d0f0 beq.n 8006956 <HAL_RCC_OscConfig+0x46a>
8006974: e035 b.n 80069e2 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8006976: 4b10 ldr r3, [pc, #64] @ (80069b8 <HAL_RCC_OscConfig+0x4cc>)
8006978: 2200 movs r2, #0
800697a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800697c: f7fc fdb2 bl 80034e4 <HAL_GetTick>
8006980: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8006982: e008 b.n 8006996 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8006984: f7fc fdae bl 80034e4 <HAL_GetTick>
8006988: 4602 mov r2, r0
800698a: 693b ldr r3, [r7, #16]
800698c: 1ad3 subs r3, r2, r3
800698e: 2b02 cmp r3, #2
8006990: d901 bls.n 8006996 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8006992: 2303 movs r3, #3
8006994: e026 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8006996: 4b06 ldr r3, [pc, #24] @ (80069b0 <HAL_RCC_OscConfig+0x4c4>)
8006998: 681b ldr r3, [r3, #0]
800699a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800699e: 2b00 cmp r3, #0
80069a0: d1f0 bne.n 8006984 <HAL_RCC_OscConfig+0x498>
80069a2: e01e b.n 80069e2 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80069a4: 687b ldr r3, [r7, #4]
80069a6: 69db ldr r3, [r3, #28]
80069a8: 2b01 cmp r3, #1
80069aa: d107 bne.n 80069bc <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
80069ac: 2301 movs r3, #1
80069ae: e019 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
80069b0: 40021000 .word 0x40021000
80069b4: 40007000 .word 0x40007000
80069b8: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80069bc: 4b0b ldr r3, [pc, #44] @ (80069ec <HAL_RCC_OscConfig+0x500>)
80069be: 685b ldr r3, [r3, #4]
80069c0: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80069c2: 68fb ldr r3, [r7, #12]
80069c4: f403 3280 and.w r2, r3, #65536 @ 0x10000
80069c8: 687b ldr r3, [r7, #4]
80069ca: 6a1b ldr r3, [r3, #32]
80069cc: 429a cmp r2, r3
80069ce: d106 bne.n 80069de <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
80069d0: 68fb ldr r3, [r7, #12]
80069d2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
80069d6: 687b ldr r3, [r7, #4]
80069d8: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80069da: 429a cmp r2, r3
80069dc: d001 beq.n 80069e2 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80069de: 2301 movs r3, #1
80069e0: e000 b.n 80069e4 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80069e2: 2300 movs r3, #0
}
80069e4: 4618 mov r0, r3
80069e6: 3718 adds r7, #24
80069e8: 46bd mov sp, r7
80069ea: bd80 pop {r7, pc}
80069ec: 40021000 .word 0x40021000
080069f0 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80069f0: b580 push {r7, lr}
80069f2: b084 sub sp, #16
80069f4: af00 add r7, sp, #0
80069f6: 6078 str r0, [r7, #4]
80069f8: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80069fa: 687b ldr r3, [r7, #4]
80069fc: 2b00 cmp r3, #0
80069fe: d101 bne.n 8006a04 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8006a00: 2301 movs r3, #1
8006a02: e0d0 b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8006a04: 4b6a ldr r3, [pc, #424] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006a06: 681b ldr r3, [r3, #0]
8006a08: f003 0307 and.w r3, r3, #7
8006a0c: 683a ldr r2, [r7, #0]
8006a0e: 429a cmp r2, r3
8006a10: d910 bls.n 8006a34 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8006a12: 4b67 ldr r3, [pc, #412] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006a14: 681b ldr r3, [r3, #0]
8006a16: f023 0207 bic.w r2, r3, #7
8006a1a: 4965 ldr r1, [pc, #404] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006a1c: 683b ldr r3, [r7, #0]
8006a1e: 4313 orrs r3, r2
8006a20: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8006a22: 4b63 ldr r3, [pc, #396] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006a24: 681b ldr r3, [r3, #0]
8006a26: f003 0307 and.w r3, r3, #7
8006a2a: 683a ldr r2, [r7, #0]
8006a2c: 429a cmp r2, r3
8006a2e: d001 beq.n 8006a34 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8006a30: 2301 movs r3, #1
8006a32: e0b8 b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8006a34: 687b ldr r3, [r7, #4]
8006a36: 681b ldr r3, [r3, #0]
8006a38: f003 0302 and.w r3, r3, #2
8006a3c: 2b00 cmp r3, #0
8006a3e: d020 beq.n 8006a82 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8006a40: 687b ldr r3, [r7, #4]
8006a42: 681b ldr r3, [r3, #0]
8006a44: f003 0304 and.w r3, r3, #4
8006a48: 2b00 cmp r3, #0
8006a4a: d005 beq.n 8006a58 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8006a4c: 4b59 ldr r3, [pc, #356] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a4e: 685b ldr r3, [r3, #4]
8006a50: 4a58 ldr r2, [pc, #352] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a52: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8006a56: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8006a58: 687b ldr r3, [r7, #4]
8006a5a: 681b ldr r3, [r3, #0]
8006a5c: f003 0308 and.w r3, r3, #8
8006a60: 2b00 cmp r3, #0
8006a62: d005 beq.n 8006a70 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8006a64: 4b53 ldr r3, [pc, #332] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a66: 685b ldr r3, [r3, #4]
8006a68: 4a52 ldr r2, [pc, #328] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a6a: f443 5360 orr.w r3, r3, #14336 @ 0x3800
8006a6e: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8006a70: 4b50 ldr r3, [pc, #320] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a72: 685b ldr r3, [r3, #4]
8006a74: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8006a78: 687b ldr r3, [r7, #4]
8006a7a: 689b ldr r3, [r3, #8]
8006a7c: 494d ldr r1, [pc, #308] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a7e: 4313 orrs r3, r2
8006a80: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8006a82: 687b ldr r3, [r7, #4]
8006a84: 681b ldr r3, [r3, #0]
8006a86: f003 0301 and.w r3, r3, #1
8006a8a: 2b00 cmp r3, #0
8006a8c: d040 beq.n 8006b10 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8006a8e: 687b ldr r3, [r7, #4]
8006a90: 685b ldr r3, [r3, #4]
8006a92: 2b01 cmp r3, #1
8006a94: d107 bne.n 8006aa6 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8006a96: 4b47 ldr r3, [pc, #284] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006a98: 681b ldr r3, [r3, #0]
8006a9a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8006a9e: 2b00 cmp r3, #0
8006aa0: d115 bne.n 8006ace <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8006aa2: 2301 movs r3, #1
8006aa4: e07f b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8006aa6: 687b ldr r3, [r7, #4]
8006aa8: 685b ldr r3, [r3, #4]
8006aaa: 2b02 cmp r3, #2
8006aac: d107 bne.n 8006abe <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8006aae: 4b41 ldr r3, [pc, #260] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006ab0: 681b ldr r3, [r3, #0]
8006ab2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006ab6: 2b00 cmp r3, #0
8006ab8: d109 bne.n 8006ace <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8006aba: 2301 movs r3, #1
8006abc: e073 b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8006abe: 4b3d ldr r3, [pc, #244] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006ac0: 681b ldr r3, [r3, #0]
8006ac2: f003 0302 and.w r3, r3, #2
8006ac6: 2b00 cmp r3, #0
8006ac8: d101 bne.n 8006ace <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8006aca: 2301 movs r3, #1
8006acc: e06b b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8006ace: 4b39 ldr r3, [pc, #228] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006ad0: 685b ldr r3, [r3, #4]
8006ad2: f023 0203 bic.w r2, r3, #3
8006ad6: 687b ldr r3, [r7, #4]
8006ad8: 685b ldr r3, [r3, #4]
8006ada: 4936 ldr r1, [pc, #216] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006adc: 4313 orrs r3, r2
8006ade: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8006ae0: f7fc fd00 bl 80034e4 <HAL_GetTick>
8006ae4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8006ae6: e00a b.n 8006afe <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8006ae8: f7fc fcfc bl 80034e4 <HAL_GetTick>
8006aec: 4602 mov r2, r0
8006aee: 68fb ldr r3, [r7, #12]
8006af0: 1ad3 subs r3, r2, r3
8006af2: f241 3288 movw r2, #5000 @ 0x1388
8006af6: 4293 cmp r3, r2
8006af8: d901 bls.n 8006afe <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8006afa: 2303 movs r3, #3
8006afc: e053 b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8006afe: 4b2d ldr r3, [pc, #180] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006b00: 685b ldr r3, [r3, #4]
8006b02: f003 020c and.w r2, r3, #12
8006b06: 687b ldr r3, [r7, #4]
8006b08: 685b ldr r3, [r3, #4]
8006b0a: 009b lsls r3, r3, #2
8006b0c: 429a cmp r2, r3
8006b0e: d1eb bne.n 8006ae8 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8006b10: 4b27 ldr r3, [pc, #156] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006b12: 681b ldr r3, [r3, #0]
8006b14: f003 0307 and.w r3, r3, #7
8006b18: 683a ldr r2, [r7, #0]
8006b1a: 429a cmp r2, r3
8006b1c: d210 bcs.n 8006b40 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8006b1e: 4b24 ldr r3, [pc, #144] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006b20: 681b ldr r3, [r3, #0]
8006b22: f023 0207 bic.w r2, r3, #7
8006b26: 4922 ldr r1, [pc, #136] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006b28: 683b ldr r3, [r7, #0]
8006b2a: 4313 orrs r3, r2
8006b2c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8006b2e: 4b20 ldr r3, [pc, #128] @ (8006bb0 <HAL_RCC_ClockConfig+0x1c0>)
8006b30: 681b ldr r3, [r3, #0]
8006b32: f003 0307 and.w r3, r3, #7
8006b36: 683a ldr r2, [r7, #0]
8006b38: 429a cmp r2, r3
8006b3a: d001 beq.n 8006b40 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8006b3c: 2301 movs r3, #1
8006b3e: e032 b.n 8006ba6 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8006b40: 687b ldr r3, [r7, #4]
8006b42: 681b ldr r3, [r3, #0]
8006b44: f003 0304 and.w r3, r3, #4
8006b48: 2b00 cmp r3, #0
8006b4a: d008 beq.n 8006b5e <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8006b4c: 4b19 ldr r3, [pc, #100] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006b4e: 685b ldr r3, [r3, #4]
8006b50: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8006b54: 687b ldr r3, [r7, #4]
8006b56: 68db ldr r3, [r3, #12]
8006b58: 4916 ldr r1, [pc, #88] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006b5a: 4313 orrs r3, r2
8006b5c: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8006b5e: 687b ldr r3, [r7, #4]
8006b60: 681b ldr r3, [r3, #0]
8006b62: f003 0308 and.w r3, r3, #8
8006b66: 2b00 cmp r3, #0
8006b68: d009 beq.n 8006b7e <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8006b6a: 4b12 ldr r3, [pc, #72] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006b6c: 685b ldr r3, [r3, #4]
8006b6e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8006b72: 687b ldr r3, [r7, #4]
8006b74: 691b ldr r3, [r3, #16]
8006b76: 00db lsls r3, r3, #3
8006b78: 490e ldr r1, [pc, #56] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006b7a: 4313 orrs r3, r2
8006b7c: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8006b7e: f000 f821 bl 8006bc4 <HAL_RCC_GetSysClockFreq>
8006b82: 4602 mov r2, r0
8006b84: 4b0b ldr r3, [pc, #44] @ (8006bb4 <HAL_RCC_ClockConfig+0x1c4>)
8006b86: 685b ldr r3, [r3, #4]
8006b88: 091b lsrs r3, r3, #4
8006b8a: f003 030f and.w r3, r3, #15
8006b8e: 490a ldr r1, [pc, #40] @ (8006bb8 <HAL_RCC_ClockConfig+0x1c8>)
8006b90: 5ccb ldrb r3, [r1, r3]
8006b92: fa22 f303 lsr.w r3, r2, r3
8006b96: 4a09 ldr r2, [pc, #36] @ (8006bbc <HAL_RCC_ClockConfig+0x1cc>)
8006b98: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8006b9a: 4b09 ldr r3, [pc, #36] @ (8006bc0 <HAL_RCC_ClockConfig+0x1d0>)
8006b9c: 681b ldr r3, [r3, #0]
8006b9e: 4618 mov r0, r3
8006ba0: f7fc fc5e bl 8003460 <HAL_InitTick>
return HAL_OK;
8006ba4: 2300 movs r3, #0
}
8006ba6: 4618 mov r0, r3
8006ba8: 3710 adds r7, #16
8006baa: 46bd mov sp, r7
8006bac: bd80 pop {r7, pc}
8006bae: bf00 nop
8006bb0: 40022000 .word 0x40022000
8006bb4: 40021000 .word 0x40021000
8006bb8: 0800d170 .word 0x0800d170
8006bbc: 20000008 .word 0x20000008
8006bc0: 2000000c .word 0x2000000c
08006bc4 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8006bc4: b480 push {r7}
8006bc6: b087 sub sp, #28
8006bc8: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8006bca: 2300 movs r3, #0
8006bcc: 60fb str r3, [r7, #12]
8006bce: 2300 movs r3, #0
8006bd0: 60bb str r3, [r7, #8]
8006bd2: 2300 movs r3, #0
8006bd4: 617b str r3, [r7, #20]
8006bd6: 2300 movs r3, #0
8006bd8: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
8006bda: 2300 movs r3, #0
8006bdc: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8006bde: 4b1e ldr r3, [pc, #120] @ (8006c58 <HAL_RCC_GetSysClockFreq+0x94>)
8006be0: 685b ldr r3, [r3, #4]
8006be2: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8006be4: 68fb ldr r3, [r7, #12]
8006be6: f003 030c and.w r3, r3, #12
8006bea: 2b04 cmp r3, #4
8006bec: d002 beq.n 8006bf4 <HAL_RCC_GetSysClockFreq+0x30>
8006bee: 2b08 cmp r3, #8
8006bf0: d003 beq.n 8006bfa <HAL_RCC_GetSysClockFreq+0x36>
8006bf2: e027 b.n 8006c44 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8006bf4: 4b19 ldr r3, [pc, #100] @ (8006c5c <HAL_RCC_GetSysClockFreq+0x98>)
8006bf6: 613b str r3, [r7, #16]
break;
8006bf8: e027 b.n 8006c4a <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8006bfa: 68fb ldr r3, [r7, #12]
8006bfc: 0c9b lsrs r3, r3, #18
8006bfe: f003 030f and.w r3, r3, #15
8006c02: 4a17 ldr r2, [pc, #92] @ (8006c60 <HAL_RCC_GetSysClockFreq+0x9c>)
8006c04: 5cd3 ldrb r3, [r2, r3]
8006c06: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8006c08: 68fb ldr r3, [r7, #12]
8006c0a: f403 3380 and.w r3, r3, #65536 @ 0x10000
8006c0e: 2b00 cmp r3, #0
8006c10: d010 beq.n 8006c34 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8006c12: 4b11 ldr r3, [pc, #68] @ (8006c58 <HAL_RCC_GetSysClockFreq+0x94>)
8006c14: 685b ldr r3, [r3, #4]
8006c16: 0c5b lsrs r3, r3, #17
8006c18: f003 0301 and.w r3, r3, #1
8006c1c: 4a11 ldr r2, [pc, #68] @ (8006c64 <HAL_RCC_GetSysClockFreq+0xa0>)
8006c1e: 5cd3 ldrb r3, [r2, r3]
8006c20: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8006c22: 687b ldr r3, [r7, #4]
8006c24: 4a0d ldr r2, [pc, #52] @ (8006c5c <HAL_RCC_GetSysClockFreq+0x98>)
8006c26: fb03 f202 mul.w r2, r3, r2
8006c2a: 68bb ldr r3, [r7, #8]
8006c2c: fbb2 f3f3 udiv r3, r2, r3
8006c30: 617b str r3, [r7, #20]
8006c32: e004 b.n 8006c3e <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8006c34: 687b ldr r3, [r7, #4]
8006c36: 4a0c ldr r2, [pc, #48] @ (8006c68 <HAL_RCC_GetSysClockFreq+0xa4>)
8006c38: fb02 f303 mul.w r3, r2, r3
8006c3c: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
8006c3e: 697b ldr r3, [r7, #20]
8006c40: 613b str r3, [r7, #16]
break;
8006c42: e002 b.n 8006c4a <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8006c44: 4b09 ldr r3, [pc, #36] @ (8006c6c <HAL_RCC_GetSysClockFreq+0xa8>)
8006c46: 613b str r3, [r7, #16]
break;
8006c48: bf00 nop
}
}
return sysclockfreq;
8006c4a: 693b ldr r3, [r7, #16]
}
8006c4c: 4618 mov r0, r3
8006c4e: 371c adds r7, #28
8006c50: 46bd mov sp, r7
8006c52: bc80 pop {r7}
8006c54: 4770 bx lr
8006c56: bf00 nop
8006c58: 40021000 .word 0x40021000
8006c5c: 00b71b00 .word 0x00b71b00
8006c60: 0800d188 .word 0x0800d188
8006c64: 0800d198 .word 0x0800d198
8006c68: 003d0900 .word 0x003d0900
8006c6c: 007a1200 .word 0x007a1200
08006c70 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8006c70: b480 push {r7}
8006c72: af00 add r7, sp, #0
return SystemCoreClock;
8006c74: 4b02 ldr r3, [pc, #8] @ (8006c80 <HAL_RCC_GetHCLKFreq+0x10>)
8006c76: 681b ldr r3, [r3, #0]
}
8006c78: 4618 mov r0, r3
8006c7a: 46bd mov sp, r7
8006c7c: bc80 pop {r7}
8006c7e: 4770 bx lr
8006c80: 20000008 .word 0x20000008
08006c84 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8006c84: b580 push {r7, lr}
8006c86: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8006c88: f7ff fff2 bl 8006c70 <HAL_RCC_GetHCLKFreq>
8006c8c: 4602 mov r2, r0
8006c8e: 4b05 ldr r3, [pc, #20] @ (8006ca4 <HAL_RCC_GetPCLK1Freq+0x20>)
8006c90: 685b ldr r3, [r3, #4]
8006c92: 0a1b lsrs r3, r3, #8
8006c94: f003 0307 and.w r3, r3, #7
8006c98: 4903 ldr r1, [pc, #12] @ (8006ca8 <HAL_RCC_GetPCLK1Freq+0x24>)
8006c9a: 5ccb ldrb r3, [r1, r3]
8006c9c: fa22 f303 lsr.w r3, r2, r3
}
8006ca0: 4618 mov r0, r3
8006ca2: bd80 pop {r7, pc}
8006ca4: 40021000 .word 0x40021000
8006ca8: 0800d180 .word 0x0800d180
08006cac <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8006cac: b580 push {r7, lr}
8006cae: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8006cb0: f7ff ffde bl 8006c70 <HAL_RCC_GetHCLKFreq>
8006cb4: 4602 mov r2, r0
8006cb6: 4b05 ldr r3, [pc, #20] @ (8006ccc <HAL_RCC_GetPCLK2Freq+0x20>)
8006cb8: 685b ldr r3, [r3, #4]
8006cba: 0adb lsrs r3, r3, #11
8006cbc: f003 0307 and.w r3, r3, #7
8006cc0: 4903 ldr r1, [pc, #12] @ (8006cd0 <HAL_RCC_GetPCLK2Freq+0x24>)
8006cc2: 5ccb ldrb r3, [r1, r3]
8006cc4: fa22 f303 lsr.w r3, r2, r3
}
8006cc8: 4618 mov r0, r3
8006cca: bd80 pop {r7, pc}
8006ccc: 40021000 .word 0x40021000
8006cd0: 0800d180 .word 0x0800d180
08006cd4 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8006cd4: b480 push {r7}
8006cd6: b085 sub sp, #20
8006cd8: af00 add r7, sp, #0
8006cda: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8006cdc: 4b0a ldr r3, [pc, #40] @ (8006d08 <RCC_Delay+0x34>)
8006cde: 681b ldr r3, [r3, #0]
8006ce0: 4a0a ldr r2, [pc, #40] @ (8006d0c <RCC_Delay+0x38>)
8006ce2: fba2 2303 umull r2, r3, r2, r3
8006ce6: 0a5b lsrs r3, r3, #9
8006ce8: 687a ldr r2, [r7, #4]
8006cea: fb02 f303 mul.w r3, r2, r3
8006cee: 60fb str r3, [r7, #12]
do
{
__NOP();
8006cf0: bf00 nop
}
while (Delay --);
8006cf2: 68fb ldr r3, [r7, #12]
8006cf4: 1e5a subs r2, r3, #1
8006cf6: 60fa str r2, [r7, #12]
8006cf8: 2b00 cmp r3, #0
8006cfa: d1f9 bne.n 8006cf0 <RCC_Delay+0x1c>
}
8006cfc: bf00 nop
8006cfe: bf00 nop
8006d00: 3714 adds r7, #20
8006d02: 46bd mov sp, r7
8006d04: bc80 pop {r7}
8006d06: 4770 bx lr
8006d08: 20000008 .word 0x20000008
8006d0c: 10624dd3 .word 0x10624dd3
08006d10 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8006d10: b580 push {r7, lr}
8006d12: b086 sub sp, #24
8006d14: af00 add r7, sp, #0
8006d16: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8006d18: 2300 movs r3, #0
8006d1a: 613b str r3, [r7, #16]
8006d1c: 2300 movs r3, #0
8006d1e: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8006d20: 687b ldr r3, [r7, #4]
8006d22: 681b ldr r3, [r3, #0]
8006d24: f003 0301 and.w r3, r3, #1
8006d28: 2b00 cmp r3, #0
8006d2a: d07d beq.n 8006e28 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8006d2c: 2300 movs r3, #0
8006d2e: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8006d30: 4b4f ldr r3, [pc, #316] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006d32: 69db ldr r3, [r3, #28]
8006d34: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006d38: 2b00 cmp r3, #0
8006d3a: d10d bne.n 8006d58 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8006d3c: 4b4c ldr r3, [pc, #304] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006d3e: 69db ldr r3, [r3, #28]
8006d40: 4a4b ldr r2, [pc, #300] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006d42: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8006d46: 61d3 str r3, [r2, #28]
8006d48: 4b49 ldr r3, [pc, #292] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006d4a: 69db ldr r3, [r3, #28]
8006d4c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006d50: 60bb str r3, [r7, #8]
8006d52: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8006d54: 2301 movs r3, #1
8006d56: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8006d58: 4b46 ldr r3, [pc, #280] @ (8006e74 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8006d5a: 681b ldr r3, [r3, #0]
8006d5c: f403 7380 and.w r3, r3, #256 @ 0x100
8006d60: 2b00 cmp r3, #0
8006d62: d118 bne.n 8006d96 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8006d64: 4b43 ldr r3, [pc, #268] @ (8006e74 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8006d66: 681b ldr r3, [r3, #0]
8006d68: 4a42 ldr r2, [pc, #264] @ (8006e74 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8006d6a: f443 7380 orr.w r3, r3, #256 @ 0x100
8006d6e: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8006d70: f7fc fbb8 bl 80034e4 <HAL_GetTick>
8006d74: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8006d76: e008 b.n 8006d8a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8006d78: f7fc fbb4 bl 80034e4 <HAL_GetTick>
8006d7c: 4602 mov r2, r0
8006d7e: 693b ldr r3, [r7, #16]
8006d80: 1ad3 subs r3, r2, r3
8006d82: 2b64 cmp r3, #100 @ 0x64
8006d84: d901 bls.n 8006d8a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8006d86: 2303 movs r3, #3
8006d88: e06d b.n 8006e66 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8006d8a: 4b3a ldr r3, [pc, #232] @ (8006e74 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8006d8c: 681b ldr r3, [r3, #0]
8006d8e: f403 7380 and.w r3, r3, #256 @ 0x100
8006d92: 2b00 cmp r3, #0
8006d94: d0f0 beq.n 8006d78 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8006d96: 4b36 ldr r3, [pc, #216] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006d98: 6a1b ldr r3, [r3, #32]
8006d9a: f403 7340 and.w r3, r3, #768 @ 0x300
8006d9e: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8006da0: 68fb ldr r3, [r7, #12]
8006da2: 2b00 cmp r3, #0
8006da4: d02e beq.n 8006e04 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8006da6: 687b ldr r3, [r7, #4]
8006da8: 685b ldr r3, [r3, #4]
8006daa: f403 7340 and.w r3, r3, #768 @ 0x300
8006dae: 68fa ldr r2, [r7, #12]
8006db0: 429a cmp r2, r3
8006db2: d027 beq.n 8006e04 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8006db4: 4b2e ldr r3, [pc, #184] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006db6: 6a1b ldr r3, [r3, #32]
8006db8: f423 7340 bic.w r3, r3, #768 @ 0x300
8006dbc: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8006dbe: 4b2e ldr r3, [pc, #184] @ (8006e78 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8006dc0: 2201 movs r2, #1
8006dc2: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8006dc4: 4b2c ldr r3, [pc, #176] @ (8006e78 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8006dc6: 2200 movs r2, #0
8006dc8: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8006dca: 4a29 ldr r2, [pc, #164] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006dcc: 68fb ldr r3, [r7, #12]
8006dce: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8006dd0: 68fb ldr r3, [r7, #12]
8006dd2: f003 0301 and.w r3, r3, #1
8006dd6: 2b00 cmp r3, #0
8006dd8: d014 beq.n 8006e04 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8006dda: f7fc fb83 bl 80034e4 <HAL_GetTick>
8006dde: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8006de0: e00a b.n 8006df8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8006de2: f7fc fb7f bl 80034e4 <HAL_GetTick>
8006de6: 4602 mov r2, r0
8006de8: 693b ldr r3, [r7, #16]
8006dea: 1ad3 subs r3, r2, r3
8006dec: f241 3288 movw r2, #5000 @ 0x1388
8006df0: 4293 cmp r3, r2
8006df2: d901 bls.n 8006df8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8006df4: 2303 movs r3, #3
8006df6: e036 b.n 8006e66 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8006df8: 4b1d ldr r3, [pc, #116] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006dfa: 6a1b ldr r3, [r3, #32]
8006dfc: f003 0302 and.w r3, r3, #2
8006e00: 2b00 cmp r3, #0
8006e02: d0ee beq.n 8006de2 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8006e04: 4b1a ldr r3, [pc, #104] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e06: 6a1b ldr r3, [r3, #32]
8006e08: f423 7240 bic.w r2, r3, #768 @ 0x300
8006e0c: 687b ldr r3, [r7, #4]
8006e0e: 685b ldr r3, [r3, #4]
8006e10: 4917 ldr r1, [pc, #92] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e12: 4313 orrs r3, r2
8006e14: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8006e16: 7dfb ldrb r3, [r7, #23]
8006e18: 2b01 cmp r3, #1
8006e1a: d105 bne.n 8006e28 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8006e1c: 4b14 ldr r3, [pc, #80] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e1e: 69db ldr r3, [r3, #28]
8006e20: 4a13 ldr r2, [pc, #76] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e22: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8006e26: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8006e28: 687b ldr r3, [r7, #4]
8006e2a: 681b ldr r3, [r3, #0]
8006e2c: f003 0302 and.w r3, r3, #2
8006e30: 2b00 cmp r3, #0
8006e32: d008 beq.n 8006e46 <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8006e34: 4b0e ldr r3, [pc, #56] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e36: 685b ldr r3, [r3, #4]
8006e38: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8006e3c: 687b ldr r3, [r7, #4]
8006e3e: 689b ldr r3, [r3, #8]
8006e40: 490b ldr r1, [pc, #44] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e42: 4313 orrs r3, r2
8006e44: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8006e46: 687b ldr r3, [r7, #4]
8006e48: 681b ldr r3, [r3, #0]
8006e4a: f003 0310 and.w r3, r3, #16
8006e4e: 2b00 cmp r3, #0
8006e50: d008 beq.n 8006e64 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8006e52: 4b07 ldr r3, [pc, #28] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e54: 685b ldr r3, [r3, #4]
8006e56: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
8006e5a: 687b ldr r3, [r7, #4]
8006e5c: 68db ldr r3, [r3, #12]
8006e5e: 4904 ldr r1, [pc, #16] @ (8006e70 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8006e60: 4313 orrs r3, r2
8006e62: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8006e64: 2300 movs r3, #0
}
8006e66: 4618 mov r0, r3
8006e68: 3718 adds r7, #24
8006e6a: 46bd mov sp, r7
8006e6c: bd80 pop {r7, pc}
8006e6e: bf00 nop
8006e70: 40021000 .word 0x40021000
8006e74: 40007000 .word 0x40007000
8006e78: 42420440 .word 0x42420440
08006e7c <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8006e7c: b580 push {r7, lr}
8006e7e: b082 sub sp, #8
8006e80: af00 add r7, sp, #0
8006e82: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8006e84: 687b ldr r3, [r7, #4]
8006e86: 2b00 cmp r3, #0
8006e88: d101 bne.n 8006e8e <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8006e8a: 2301 movs r3, #1
8006e8c: e041 b.n 8006f12 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8006e8e: 687b ldr r3, [r7, #4]
8006e90: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8006e94: b2db uxtb r3, r3
8006e96: 2b00 cmp r3, #0
8006e98: d106 bne.n 8006ea8 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8006e9a: 687b ldr r3, [r7, #4]
8006e9c: 2200 movs r2, #0
8006e9e: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8006ea2: 6878 ldr r0, [r7, #4]
8006ea4: f7fc f952 bl 800314c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8006ea8: 687b ldr r3, [r7, #4]
8006eaa: 2202 movs r2, #2
8006eac: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8006eb0: 687b ldr r3, [r7, #4]
8006eb2: 681a ldr r2, [r3, #0]
8006eb4: 687b ldr r3, [r7, #4]
8006eb6: 3304 adds r3, #4
8006eb8: 4619 mov r1, r3
8006eba: 4610 mov r0, r2
8006ebc: f000 fb3e bl 800753c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8006ec0: 687b ldr r3, [r7, #4]
8006ec2: 2201 movs r2, #1
8006ec4: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8006ec8: 687b ldr r3, [r7, #4]
8006eca: 2201 movs r2, #1
8006ecc: f883 203e strb.w r2, [r3, #62] @ 0x3e
8006ed0: 687b ldr r3, [r7, #4]
8006ed2: 2201 movs r2, #1
8006ed4: f883 203f strb.w r2, [r3, #63] @ 0x3f
8006ed8: 687b ldr r3, [r7, #4]
8006eda: 2201 movs r2, #1
8006edc: f883 2040 strb.w r2, [r3, #64] @ 0x40
8006ee0: 687b ldr r3, [r7, #4]
8006ee2: 2201 movs r2, #1
8006ee4: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8006ee8: 687b ldr r3, [r7, #4]
8006eea: 2201 movs r2, #1
8006eec: f883 2042 strb.w r2, [r3, #66] @ 0x42
8006ef0: 687b ldr r3, [r7, #4]
8006ef2: 2201 movs r2, #1
8006ef4: f883 2043 strb.w r2, [r3, #67] @ 0x43
8006ef8: 687b ldr r3, [r7, #4]
8006efa: 2201 movs r2, #1
8006efc: f883 2044 strb.w r2, [r3, #68] @ 0x44
8006f00: 687b ldr r3, [r7, #4]
8006f02: 2201 movs r2, #1
8006f04: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8006f08: 687b ldr r3, [r7, #4]
8006f0a: 2201 movs r2, #1
8006f0c: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8006f10: 2300 movs r3, #0
}
8006f12: 4618 mov r0, r3
8006f14: 3708 adds r7, #8
8006f16: 46bd mov sp, r7
8006f18: bd80 pop {r7, pc}
08006f1a <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8006f1a: b580 push {r7, lr}
8006f1c: b082 sub sp, #8
8006f1e: af00 add r7, sp, #0
8006f20: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8006f22: 687b ldr r3, [r7, #4]
8006f24: 2b00 cmp r3, #0
8006f26: d101 bne.n 8006f2c <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8006f28: 2301 movs r3, #1
8006f2a: e041 b.n 8006fb0 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8006f2c: 687b ldr r3, [r7, #4]
8006f2e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8006f32: b2db uxtb r3, r3
8006f34: 2b00 cmp r3, #0
8006f36: d106 bne.n 8006f46 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8006f38: 687b ldr r3, [r7, #4]
8006f3a: 2200 movs r2, #0
8006f3c: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8006f40: 6878 ldr r0, [r7, #4]
8006f42: f000 f839 bl 8006fb8 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8006f46: 687b ldr r3, [r7, #4]
8006f48: 2202 movs r2, #2
8006f4a: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8006f4e: 687b ldr r3, [r7, #4]
8006f50: 681a ldr r2, [r3, #0]
8006f52: 687b ldr r3, [r7, #4]
8006f54: 3304 adds r3, #4
8006f56: 4619 mov r1, r3
8006f58: 4610 mov r0, r2
8006f5a: f000 faef bl 800753c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8006f5e: 687b ldr r3, [r7, #4]
8006f60: 2201 movs r2, #1
8006f62: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8006f66: 687b ldr r3, [r7, #4]
8006f68: 2201 movs r2, #1
8006f6a: f883 203e strb.w r2, [r3, #62] @ 0x3e
8006f6e: 687b ldr r3, [r7, #4]
8006f70: 2201 movs r2, #1
8006f72: f883 203f strb.w r2, [r3, #63] @ 0x3f
8006f76: 687b ldr r3, [r7, #4]
8006f78: 2201 movs r2, #1
8006f7a: f883 2040 strb.w r2, [r3, #64] @ 0x40
8006f7e: 687b ldr r3, [r7, #4]
8006f80: 2201 movs r2, #1
8006f82: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8006f86: 687b ldr r3, [r7, #4]
8006f88: 2201 movs r2, #1
8006f8a: f883 2042 strb.w r2, [r3, #66] @ 0x42
8006f8e: 687b ldr r3, [r7, #4]
8006f90: 2201 movs r2, #1
8006f92: f883 2043 strb.w r2, [r3, #67] @ 0x43
8006f96: 687b ldr r3, [r7, #4]
8006f98: 2201 movs r2, #1
8006f9a: f883 2044 strb.w r2, [r3, #68] @ 0x44
8006f9e: 687b ldr r3, [r7, #4]
8006fa0: 2201 movs r2, #1
8006fa2: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8006fa6: 687b ldr r3, [r7, #4]
8006fa8: 2201 movs r2, #1
8006faa: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8006fae: 2300 movs r3, #0
}
8006fb0: 4618 mov r0, r3
8006fb2: 3708 adds r7, #8
8006fb4: 46bd mov sp, r7
8006fb6: bd80 pop {r7, pc}
08006fb8 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8006fb8: b480 push {r7}
8006fba: b083 sub sp, #12
8006fbc: af00 add r7, sp, #0
8006fbe: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8006fc0: bf00 nop
8006fc2: 370c adds r7, #12
8006fc4: 46bd mov sp, r7
8006fc6: bc80 pop {r7}
8006fc8: 4770 bx lr
...
08006fcc <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8006fcc: b580 push {r7, lr}
8006fce: b084 sub sp, #16
8006fd0: af00 add r7, sp, #0
8006fd2: 6078 str r0, [r7, #4]
8006fd4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8006fd6: 683b ldr r3, [r7, #0]
8006fd8: 2b00 cmp r3, #0
8006fda: d109 bne.n 8006ff0 <HAL_TIM_PWM_Start+0x24>
8006fdc: 687b ldr r3, [r7, #4]
8006fde: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8006fe2: b2db uxtb r3, r3
8006fe4: 2b01 cmp r3, #1
8006fe6: bf14 ite ne
8006fe8: 2301 movne r3, #1
8006fea: 2300 moveq r3, #0
8006fec: b2db uxtb r3, r3
8006fee: e022 b.n 8007036 <HAL_TIM_PWM_Start+0x6a>
8006ff0: 683b ldr r3, [r7, #0]
8006ff2: 2b04 cmp r3, #4
8006ff4: d109 bne.n 800700a <HAL_TIM_PWM_Start+0x3e>
8006ff6: 687b ldr r3, [r7, #4]
8006ff8: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8006ffc: b2db uxtb r3, r3
8006ffe: 2b01 cmp r3, #1
8007000: bf14 ite ne
8007002: 2301 movne r3, #1
8007004: 2300 moveq r3, #0
8007006: b2db uxtb r3, r3
8007008: e015 b.n 8007036 <HAL_TIM_PWM_Start+0x6a>
800700a: 683b ldr r3, [r7, #0]
800700c: 2b08 cmp r3, #8
800700e: d109 bne.n 8007024 <HAL_TIM_PWM_Start+0x58>
8007010: 687b ldr r3, [r7, #4]
8007012: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8007016: b2db uxtb r3, r3
8007018: 2b01 cmp r3, #1
800701a: bf14 ite ne
800701c: 2301 movne r3, #1
800701e: 2300 moveq r3, #0
8007020: b2db uxtb r3, r3
8007022: e008 b.n 8007036 <HAL_TIM_PWM_Start+0x6a>
8007024: 687b ldr r3, [r7, #4]
8007026: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800702a: b2db uxtb r3, r3
800702c: 2b01 cmp r3, #1
800702e: bf14 ite ne
8007030: 2301 movne r3, #1
8007032: 2300 moveq r3, #0
8007034: b2db uxtb r3, r3
8007036: 2b00 cmp r3, #0
8007038: d001 beq.n 800703e <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
800703a: 2301 movs r3, #1
800703c: e05e b.n 80070fc <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
800703e: 683b ldr r3, [r7, #0]
8007040: 2b00 cmp r3, #0
8007042: d104 bne.n 800704e <HAL_TIM_PWM_Start+0x82>
8007044: 687b ldr r3, [r7, #4]
8007046: 2202 movs r2, #2
8007048: f883 203e strb.w r2, [r3, #62] @ 0x3e
800704c: e013 b.n 8007076 <HAL_TIM_PWM_Start+0xaa>
800704e: 683b ldr r3, [r7, #0]
8007050: 2b04 cmp r3, #4
8007052: d104 bne.n 800705e <HAL_TIM_PWM_Start+0x92>
8007054: 687b ldr r3, [r7, #4]
8007056: 2202 movs r2, #2
8007058: f883 203f strb.w r2, [r3, #63] @ 0x3f
800705c: e00b b.n 8007076 <HAL_TIM_PWM_Start+0xaa>
800705e: 683b ldr r3, [r7, #0]
8007060: 2b08 cmp r3, #8
8007062: d104 bne.n 800706e <HAL_TIM_PWM_Start+0xa2>
8007064: 687b ldr r3, [r7, #4]
8007066: 2202 movs r2, #2
8007068: f883 2040 strb.w r2, [r3, #64] @ 0x40
800706c: e003 b.n 8007076 <HAL_TIM_PWM_Start+0xaa>
800706e: 687b ldr r3, [r7, #4]
8007070: 2202 movs r2, #2
8007072: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8007076: 687b ldr r3, [r7, #4]
8007078: 681b ldr r3, [r3, #0]
800707a: 2201 movs r2, #1
800707c: 6839 ldr r1, [r7, #0]
800707e: 4618 mov r0, r3
8007080: f000 fce8 bl 8007a54 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8007084: 687b ldr r3, [r7, #4]
8007086: 681b ldr r3, [r3, #0]
8007088: 4a1e ldr r2, [pc, #120] @ (8007104 <HAL_TIM_PWM_Start+0x138>)
800708a: 4293 cmp r3, r2
800708c: d107 bne.n 800709e <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
800708e: 687b ldr r3, [r7, #4]
8007090: 681b ldr r3, [r3, #0]
8007092: 6c5a ldr r2, [r3, #68] @ 0x44
8007094: 687b ldr r3, [r7, #4]
8007096: 681b ldr r3, [r3, #0]
8007098: f442 4200 orr.w r2, r2, #32768 @ 0x8000
800709c: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800709e: 687b ldr r3, [r7, #4]
80070a0: 681b ldr r3, [r3, #0]
80070a2: 4a18 ldr r2, [pc, #96] @ (8007104 <HAL_TIM_PWM_Start+0x138>)
80070a4: 4293 cmp r3, r2
80070a6: d00e beq.n 80070c6 <HAL_TIM_PWM_Start+0xfa>
80070a8: 687b ldr r3, [r7, #4]
80070aa: 681b ldr r3, [r3, #0]
80070ac: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80070b0: d009 beq.n 80070c6 <HAL_TIM_PWM_Start+0xfa>
80070b2: 687b ldr r3, [r7, #4]
80070b4: 681b ldr r3, [r3, #0]
80070b6: 4a14 ldr r2, [pc, #80] @ (8007108 <HAL_TIM_PWM_Start+0x13c>)
80070b8: 4293 cmp r3, r2
80070ba: d004 beq.n 80070c6 <HAL_TIM_PWM_Start+0xfa>
80070bc: 687b ldr r3, [r7, #4]
80070be: 681b ldr r3, [r3, #0]
80070c0: 4a12 ldr r2, [pc, #72] @ (800710c <HAL_TIM_PWM_Start+0x140>)
80070c2: 4293 cmp r3, r2
80070c4: d111 bne.n 80070ea <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80070c6: 687b ldr r3, [r7, #4]
80070c8: 681b ldr r3, [r3, #0]
80070ca: 689b ldr r3, [r3, #8]
80070cc: f003 0307 and.w r3, r3, #7
80070d0: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80070d2: 68fb ldr r3, [r7, #12]
80070d4: 2b06 cmp r3, #6
80070d6: d010 beq.n 80070fa <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
80070d8: 687b ldr r3, [r7, #4]
80070da: 681b ldr r3, [r3, #0]
80070dc: 681a ldr r2, [r3, #0]
80070de: 687b ldr r3, [r7, #4]
80070e0: 681b ldr r3, [r3, #0]
80070e2: f042 0201 orr.w r2, r2, #1
80070e6: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80070e8: e007 b.n 80070fa <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80070ea: 687b ldr r3, [r7, #4]
80070ec: 681b ldr r3, [r3, #0]
80070ee: 681a ldr r2, [r3, #0]
80070f0: 687b ldr r3, [r7, #4]
80070f2: 681b ldr r3, [r3, #0]
80070f4: f042 0201 orr.w r2, r2, #1
80070f8: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
80070fa: 2300 movs r3, #0
}
80070fc: 4618 mov r0, r3
80070fe: 3710 adds r7, #16
8007100: 46bd mov sp, r7
8007102: bd80 pop {r7, pc}
8007104: 40012c00 .word 0x40012c00
8007108: 40000400 .word 0x40000400
800710c: 40000800 .word 0x40000800
08007110 <HAL_TIM_PWM_Stop>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8007110: b580 push {r7, lr}
8007112: b082 sub sp, #8
8007114: af00 add r7, sp, #0
8007116: 6078 str r0, [r7, #4]
8007118: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
800711a: 687b ldr r3, [r7, #4]
800711c: 681b ldr r3, [r3, #0]
800711e: 2200 movs r2, #0
8007120: 6839 ldr r1, [r7, #0]
8007122: 4618 mov r0, r3
8007124: f000 fc96 bl 8007a54 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8007128: 687b ldr r3, [r7, #4]
800712a: 681b ldr r3, [r3, #0]
800712c: 4a29 ldr r2, [pc, #164] @ (80071d4 <HAL_TIM_PWM_Stop+0xc4>)
800712e: 4293 cmp r3, r2
8007130: d117 bne.n 8007162 <HAL_TIM_PWM_Stop+0x52>
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
8007132: 687b ldr r3, [r7, #4]
8007134: 681b ldr r3, [r3, #0]
8007136: 6a1a ldr r2, [r3, #32]
8007138: f241 1311 movw r3, #4369 @ 0x1111
800713c: 4013 ands r3, r2
800713e: 2b00 cmp r3, #0
8007140: d10f bne.n 8007162 <HAL_TIM_PWM_Stop+0x52>
8007142: 687b ldr r3, [r7, #4]
8007144: 681b ldr r3, [r3, #0]
8007146: 6a1a ldr r2, [r3, #32]
8007148: f240 4344 movw r3, #1092 @ 0x444
800714c: 4013 ands r3, r2
800714e: 2b00 cmp r3, #0
8007150: d107 bne.n 8007162 <HAL_TIM_PWM_Stop+0x52>
8007152: 687b ldr r3, [r7, #4]
8007154: 681b ldr r3, [r3, #0]
8007156: 6c5a ldr r2, [r3, #68] @ 0x44
8007158: 687b ldr r3, [r7, #4]
800715a: 681b ldr r3, [r3, #0]
800715c: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8007160: 645a str r2, [r3, #68] @ 0x44
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
8007162: 687b ldr r3, [r7, #4]
8007164: 681b ldr r3, [r3, #0]
8007166: 6a1a ldr r2, [r3, #32]
8007168: f241 1311 movw r3, #4369 @ 0x1111
800716c: 4013 ands r3, r2
800716e: 2b00 cmp r3, #0
8007170: d10f bne.n 8007192 <HAL_TIM_PWM_Stop+0x82>
8007172: 687b ldr r3, [r7, #4]
8007174: 681b ldr r3, [r3, #0]
8007176: 6a1a ldr r2, [r3, #32]
8007178: f240 4344 movw r3, #1092 @ 0x444
800717c: 4013 ands r3, r2
800717e: 2b00 cmp r3, #0
8007180: d107 bne.n 8007192 <HAL_TIM_PWM_Stop+0x82>
8007182: 687b ldr r3, [r7, #4]
8007184: 681b ldr r3, [r3, #0]
8007186: 681a ldr r2, [r3, #0]
8007188: 687b ldr r3, [r7, #4]
800718a: 681b ldr r3, [r3, #0]
800718c: f022 0201 bic.w r2, r2, #1
8007190: 601a str r2, [r3, #0]
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
8007192: 683b ldr r3, [r7, #0]
8007194: 2b00 cmp r3, #0
8007196: d104 bne.n 80071a2 <HAL_TIM_PWM_Stop+0x92>
8007198: 687b ldr r3, [r7, #4]
800719a: 2201 movs r2, #1
800719c: f883 203e strb.w r2, [r3, #62] @ 0x3e
80071a0: e013 b.n 80071ca <HAL_TIM_PWM_Stop+0xba>
80071a2: 683b ldr r3, [r7, #0]
80071a4: 2b04 cmp r3, #4
80071a6: d104 bne.n 80071b2 <HAL_TIM_PWM_Stop+0xa2>
80071a8: 687b ldr r3, [r7, #4]
80071aa: 2201 movs r2, #1
80071ac: f883 203f strb.w r2, [r3, #63] @ 0x3f
80071b0: e00b b.n 80071ca <HAL_TIM_PWM_Stop+0xba>
80071b2: 683b ldr r3, [r7, #0]
80071b4: 2b08 cmp r3, #8
80071b6: d104 bne.n 80071c2 <HAL_TIM_PWM_Stop+0xb2>
80071b8: 687b ldr r3, [r7, #4]
80071ba: 2201 movs r2, #1
80071bc: f883 2040 strb.w r2, [r3, #64] @ 0x40
80071c0: e003 b.n 80071ca <HAL_TIM_PWM_Stop+0xba>
80071c2: 687b ldr r3, [r7, #4]
80071c4: 2201 movs r2, #1
80071c6: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Return function status */
return HAL_OK;
80071ca: 2300 movs r3, #0
}
80071cc: 4618 mov r0, r3
80071ce: 3708 adds r7, #8
80071d0: 46bd mov sp, r7
80071d2: bd80 pop {r7, pc}
80071d4: 40012c00 .word 0x40012c00
080071d8 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80071d8: b580 push {r7, lr}
80071da: b086 sub sp, #24
80071dc: af00 add r7, sp, #0
80071de: 60f8 str r0, [r7, #12]
80071e0: 60b9 str r1, [r7, #8]
80071e2: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80071e4: 2300 movs r3, #0
80071e6: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
80071e8: 68fb ldr r3, [r7, #12]
80071ea: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80071ee: 2b01 cmp r3, #1
80071f0: d101 bne.n 80071f6 <HAL_TIM_PWM_ConfigChannel+0x1e>
80071f2: 2302 movs r3, #2
80071f4: e0ae b.n 8007354 <HAL_TIM_PWM_ConfigChannel+0x17c>
80071f6: 68fb ldr r3, [r7, #12]
80071f8: 2201 movs r2, #1
80071fa: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
80071fe: 687b ldr r3, [r7, #4]
8007200: 2b0c cmp r3, #12
8007202: f200 809f bhi.w 8007344 <HAL_TIM_PWM_ConfigChannel+0x16c>
8007206: a201 add r2, pc, #4 @ (adr r2, 800720c <HAL_TIM_PWM_ConfigChannel+0x34>)
8007208: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800720c: 08007241 .word 0x08007241
8007210: 08007345 .word 0x08007345
8007214: 08007345 .word 0x08007345
8007218: 08007345 .word 0x08007345
800721c: 08007281 .word 0x08007281
8007220: 08007345 .word 0x08007345
8007224: 08007345 .word 0x08007345
8007228: 08007345 .word 0x08007345
800722c: 080072c3 .word 0x080072c3
8007230: 08007345 .word 0x08007345
8007234: 08007345 .word 0x08007345
8007238: 08007345 .word 0x08007345
800723c: 08007303 .word 0x08007303
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8007240: 68fb ldr r3, [r7, #12]
8007242: 681b ldr r3, [r3, #0]
8007244: 68b9 ldr r1, [r7, #8]
8007246: 4618 mov r0, r3
8007248: f000 f9e6 bl 8007618 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
800724c: 68fb ldr r3, [r7, #12]
800724e: 681b ldr r3, [r3, #0]
8007250: 699a ldr r2, [r3, #24]
8007252: 68fb ldr r3, [r7, #12]
8007254: 681b ldr r3, [r3, #0]
8007256: f042 0208 orr.w r2, r2, #8
800725a: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
800725c: 68fb ldr r3, [r7, #12]
800725e: 681b ldr r3, [r3, #0]
8007260: 699a ldr r2, [r3, #24]
8007262: 68fb ldr r3, [r7, #12]
8007264: 681b ldr r3, [r3, #0]
8007266: f022 0204 bic.w r2, r2, #4
800726a: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
800726c: 68fb ldr r3, [r7, #12]
800726e: 681b ldr r3, [r3, #0]
8007270: 6999 ldr r1, [r3, #24]
8007272: 68bb ldr r3, [r7, #8]
8007274: 691a ldr r2, [r3, #16]
8007276: 68fb ldr r3, [r7, #12]
8007278: 681b ldr r3, [r3, #0]
800727a: 430a orrs r2, r1
800727c: 619a str r2, [r3, #24]
break;
800727e: e064 b.n 800734a <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8007280: 68fb ldr r3, [r7, #12]
8007282: 681b ldr r3, [r3, #0]
8007284: 68b9 ldr r1, [r7, #8]
8007286: 4618 mov r0, r3
8007288: f000 fa2c bl 80076e4 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
800728c: 68fb ldr r3, [r7, #12]
800728e: 681b ldr r3, [r3, #0]
8007290: 699a ldr r2, [r3, #24]
8007292: 68fb ldr r3, [r7, #12]
8007294: 681b ldr r3, [r3, #0]
8007296: f442 6200 orr.w r2, r2, #2048 @ 0x800
800729a: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
800729c: 68fb ldr r3, [r7, #12]
800729e: 681b ldr r3, [r3, #0]
80072a0: 699a ldr r2, [r3, #24]
80072a2: 68fb ldr r3, [r7, #12]
80072a4: 681b ldr r3, [r3, #0]
80072a6: f422 6280 bic.w r2, r2, #1024 @ 0x400
80072aa: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80072ac: 68fb ldr r3, [r7, #12]
80072ae: 681b ldr r3, [r3, #0]
80072b0: 6999 ldr r1, [r3, #24]
80072b2: 68bb ldr r3, [r7, #8]
80072b4: 691b ldr r3, [r3, #16]
80072b6: 021a lsls r2, r3, #8
80072b8: 68fb ldr r3, [r7, #12]
80072ba: 681b ldr r3, [r3, #0]
80072bc: 430a orrs r2, r1
80072be: 619a str r2, [r3, #24]
break;
80072c0: e043 b.n 800734a <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80072c2: 68fb ldr r3, [r7, #12]
80072c4: 681b ldr r3, [r3, #0]
80072c6: 68b9 ldr r1, [r7, #8]
80072c8: 4618 mov r0, r3
80072ca: f000 fa75 bl 80077b8 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80072ce: 68fb ldr r3, [r7, #12]
80072d0: 681b ldr r3, [r3, #0]
80072d2: 69da ldr r2, [r3, #28]
80072d4: 68fb ldr r3, [r7, #12]
80072d6: 681b ldr r3, [r3, #0]
80072d8: f042 0208 orr.w r2, r2, #8
80072dc: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80072de: 68fb ldr r3, [r7, #12]
80072e0: 681b ldr r3, [r3, #0]
80072e2: 69da ldr r2, [r3, #28]
80072e4: 68fb ldr r3, [r7, #12]
80072e6: 681b ldr r3, [r3, #0]
80072e8: f022 0204 bic.w r2, r2, #4
80072ec: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80072ee: 68fb ldr r3, [r7, #12]
80072f0: 681b ldr r3, [r3, #0]
80072f2: 69d9 ldr r1, [r3, #28]
80072f4: 68bb ldr r3, [r7, #8]
80072f6: 691a ldr r2, [r3, #16]
80072f8: 68fb ldr r3, [r7, #12]
80072fa: 681b ldr r3, [r3, #0]
80072fc: 430a orrs r2, r1
80072fe: 61da str r2, [r3, #28]
break;
8007300: e023 b.n 800734a <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8007302: 68fb ldr r3, [r7, #12]
8007304: 681b ldr r3, [r3, #0]
8007306: 68b9 ldr r1, [r7, #8]
8007308: 4618 mov r0, r3
800730a: f000 fabf bl 800788c <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800730e: 68fb ldr r3, [r7, #12]
8007310: 681b ldr r3, [r3, #0]
8007312: 69da ldr r2, [r3, #28]
8007314: 68fb ldr r3, [r7, #12]
8007316: 681b ldr r3, [r3, #0]
8007318: f442 6200 orr.w r2, r2, #2048 @ 0x800
800731c: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800731e: 68fb ldr r3, [r7, #12]
8007320: 681b ldr r3, [r3, #0]
8007322: 69da ldr r2, [r3, #28]
8007324: 68fb ldr r3, [r7, #12]
8007326: 681b ldr r3, [r3, #0]
8007328: f422 6280 bic.w r2, r2, #1024 @ 0x400
800732c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800732e: 68fb ldr r3, [r7, #12]
8007330: 681b ldr r3, [r3, #0]
8007332: 69d9 ldr r1, [r3, #28]
8007334: 68bb ldr r3, [r7, #8]
8007336: 691b ldr r3, [r3, #16]
8007338: 021a lsls r2, r3, #8
800733a: 68fb ldr r3, [r7, #12]
800733c: 681b ldr r3, [r3, #0]
800733e: 430a orrs r2, r1
8007340: 61da str r2, [r3, #28]
break;
8007342: e002 b.n 800734a <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8007344: 2301 movs r3, #1
8007346: 75fb strb r3, [r7, #23]
break;
8007348: bf00 nop
}
__HAL_UNLOCK(htim);
800734a: 68fb ldr r3, [r7, #12]
800734c: 2200 movs r2, #0
800734e: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8007352: 7dfb ldrb r3, [r7, #23]
}
8007354: 4618 mov r0, r3
8007356: 3718 adds r7, #24
8007358: 46bd mov sp, r7
800735a: bd80 pop {r7, pc}
0800735c <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800735c: b580 push {r7, lr}
800735e: b084 sub sp, #16
8007360: af00 add r7, sp, #0
8007362: 6078 str r0, [r7, #4]
8007364: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8007366: 2300 movs r3, #0
8007368: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800736a: 687b ldr r3, [r7, #4]
800736c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8007370: 2b01 cmp r3, #1
8007372: d101 bne.n 8007378 <HAL_TIM_ConfigClockSource+0x1c>
8007374: 2302 movs r3, #2
8007376: e0b4 b.n 80074e2 <HAL_TIM_ConfigClockSource+0x186>
8007378: 687b ldr r3, [r7, #4]
800737a: 2201 movs r2, #1
800737c: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8007380: 687b ldr r3, [r7, #4]
8007382: 2202 movs r2, #2
8007384: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8007388: 687b ldr r3, [r7, #4]
800738a: 681b ldr r3, [r3, #0]
800738c: 689b ldr r3, [r3, #8]
800738e: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8007390: 68bb ldr r3, [r7, #8]
8007392: f023 0377 bic.w r3, r3, #119 @ 0x77
8007396: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8007398: 68bb ldr r3, [r7, #8]
800739a: f423 437f bic.w r3, r3, #65280 @ 0xff00
800739e: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80073a0: 687b ldr r3, [r7, #4]
80073a2: 681b ldr r3, [r3, #0]
80073a4: 68ba ldr r2, [r7, #8]
80073a6: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80073a8: 683b ldr r3, [r7, #0]
80073aa: 681b ldr r3, [r3, #0]
80073ac: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80073b0: d03e beq.n 8007430 <HAL_TIM_ConfigClockSource+0xd4>
80073b2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80073b6: f200 8087 bhi.w 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073ba: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80073be: f000 8086 beq.w 80074ce <HAL_TIM_ConfigClockSource+0x172>
80073c2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80073c6: d87f bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073c8: 2b70 cmp r3, #112 @ 0x70
80073ca: d01a beq.n 8007402 <HAL_TIM_ConfigClockSource+0xa6>
80073cc: 2b70 cmp r3, #112 @ 0x70
80073ce: d87b bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073d0: 2b60 cmp r3, #96 @ 0x60
80073d2: d050 beq.n 8007476 <HAL_TIM_ConfigClockSource+0x11a>
80073d4: 2b60 cmp r3, #96 @ 0x60
80073d6: d877 bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073d8: 2b50 cmp r3, #80 @ 0x50
80073da: d03c beq.n 8007456 <HAL_TIM_ConfigClockSource+0xfa>
80073dc: 2b50 cmp r3, #80 @ 0x50
80073de: d873 bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073e0: 2b40 cmp r3, #64 @ 0x40
80073e2: d058 beq.n 8007496 <HAL_TIM_ConfigClockSource+0x13a>
80073e4: 2b40 cmp r3, #64 @ 0x40
80073e6: d86f bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073e8: 2b30 cmp r3, #48 @ 0x30
80073ea: d064 beq.n 80074b6 <HAL_TIM_ConfigClockSource+0x15a>
80073ec: 2b30 cmp r3, #48 @ 0x30
80073ee: d86b bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073f0: 2b20 cmp r3, #32
80073f2: d060 beq.n 80074b6 <HAL_TIM_ConfigClockSource+0x15a>
80073f4: 2b20 cmp r3, #32
80073f6: d867 bhi.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
80073f8: 2b00 cmp r3, #0
80073fa: d05c beq.n 80074b6 <HAL_TIM_ConfigClockSource+0x15a>
80073fc: 2b10 cmp r3, #16
80073fe: d05a beq.n 80074b6 <HAL_TIM_ConfigClockSource+0x15a>
8007400: e062 b.n 80074c8 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8007402: 687b ldr r3, [r7, #4]
8007404: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8007406: 683b ldr r3, [r7, #0]
8007408: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800740a: 683b ldr r3, [r7, #0]
800740c: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800740e: 683b ldr r3, [r7, #0]
8007410: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8007412: f000 fb00 bl 8007a16 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8007416: 687b ldr r3, [r7, #4]
8007418: 681b ldr r3, [r3, #0]
800741a: 689b ldr r3, [r3, #8]
800741c: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800741e: 68bb ldr r3, [r7, #8]
8007420: f043 0377 orr.w r3, r3, #119 @ 0x77
8007424: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8007426: 687b ldr r3, [r7, #4]
8007428: 681b ldr r3, [r3, #0]
800742a: 68ba ldr r2, [r7, #8]
800742c: 609a str r2, [r3, #8]
break;
800742e: e04f b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8007430: 687b ldr r3, [r7, #4]
8007432: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8007434: 683b ldr r3, [r7, #0]
8007436: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8007438: 683b ldr r3, [r7, #0]
800743a: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800743c: 683b ldr r3, [r7, #0]
800743e: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8007440: f000 fae9 bl 8007a16 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8007444: 687b ldr r3, [r7, #4]
8007446: 681b ldr r3, [r3, #0]
8007448: 689a ldr r2, [r3, #8]
800744a: 687b ldr r3, [r7, #4]
800744c: 681b ldr r3, [r3, #0]
800744e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8007452: 609a str r2, [r3, #8]
break;
8007454: e03c b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8007456: 687b ldr r3, [r7, #4]
8007458: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800745a: 683b ldr r3, [r7, #0]
800745c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800745e: 683b ldr r3, [r7, #0]
8007460: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8007462: 461a mov r2, r3
8007464: f000 fa60 bl 8007928 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8007468: 687b ldr r3, [r7, #4]
800746a: 681b ldr r3, [r3, #0]
800746c: 2150 movs r1, #80 @ 0x50
800746e: 4618 mov r0, r3
8007470: f000 fab7 bl 80079e2 <TIM_ITRx_SetConfig>
break;
8007474: e02c b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8007476: 687b ldr r3, [r7, #4]
8007478: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800747a: 683b ldr r3, [r7, #0]
800747c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800747e: 683b ldr r3, [r7, #0]
8007480: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8007482: 461a mov r2, r3
8007484: f000 fa7e bl 8007984 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8007488: 687b ldr r3, [r7, #4]
800748a: 681b ldr r3, [r3, #0]
800748c: 2160 movs r1, #96 @ 0x60
800748e: 4618 mov r0, r3
8007490: f000 faa7 bl 80079e2 <TIM_ITRx_SetConfig>
break;
8007494: e01c b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8007496: 687b ldr r3, [r7, #4]
8007498: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800749a: 683b ldr r3, [r7, #0]
800749c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800749e: 683b ldr r3, [r7, #0]
80074a0: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80074a2: 461a mov r2, r3
80074a4: f000 fa40 bl 8007928 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80074a8: 687b ldr r3, [r7, #4]
80074aa: 681b ldr r3, [r3, #0]
80074ac: 2140 movs r1, #64 @ 0x40
80074ae: 4618 mov r0, r3
80074b0: f000 fa97 bl 80079e2 <TIM_ITRx_SetConfig>
break;
80074b4: e00c b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80074b6: 687b ldr r3, [r7, #4]
80074b8: 681a ldr r2, [r3, #0]
80074ba: 683b ldr r3, [r7, #0]
80074bc: 681b ldr r3, [r3, #0]
80074be: 4619 mov r1, r3
80074c0: 4610 mov r0, r2
80074c2: f000 fa8e bl 80079e2 <TIM_ITRx_SetConfig>
break;
80074c6: e003 b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
80074c8: 2301 movs r3, #1
80074ca: 73fb strb r3, [r7, #15]
break;
80074cc: e000 b.n 80074d0 <HAL_TIM_ConfigClockSource+0x174>
break;
80074ce: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
80074d0: 687b ldr r3, [r7, #4]
80074d2: 2201 movs r2, #1
80074d4: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80074d8: 687b ldr r3, [r7, #4]
80074da: 2200 movs r2, #0
80074dc: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80074e0: 7bfb ldrb r3, [r7, #15]
}
80074e2: 4618 mov r0, r3
80074e4: 3710 adds r7, #16
80074e6: 46bd mov sp, r7
80074e8: bd80 pop {r7, pc}
080074ea <HAL_TIM_GetChannelState>:
* @arg TIM_CHANNEL_5: TIM Channel 5
* @arg TIM_CHANNEL_6: TIM Channel 6
* @retval TIM Channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
80074ea: b480 push {r7}
80074ec: b085 sub sp, #20
80074ee: af00 add r7, sp, #0
80074f0: 6078 str r0, [r7, #4]
80074f2: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
80074f4: 683b ldr r3, [r7, #0]
80074f6: 2b00 cmp r3, #0
80074f8: d104 bne.n 8007504 <HAL_TIM_GetChannelState+0x1a>
80074fa: 687b ldr r3, [r7, #4]
80074fc: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8007500: b2db uxtb r3, r3
8007502: e013 b.n 800752c <HAL_TIM_GetChannelState+0x42>
8007504: 683b ldr r3, [r7, #0]
8007506: 2b04 cmp r3, #4
8007508: d104 bne.n 8007514 <HAL_TIM_GetChannelState+0x2a>
800750a: 687b ldr r3, [r7, #4]
800750c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8007510: b2db uxtb r3, r3
8007512: e00b b.n 800752c <HAL_TIM_GetChannelState+0x42>
8007514: 683b ldr r3, [r7, #0]
8007516: 2b08 cmp r3, #8
8007518: d104 bne.n 8007524 <HAL_TIM_GetChannelState+0x3a>
800751a: 687b ldr r3, [r7, #4]
800751c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8007520: b2db uxtb r3, r3
8007522: e003 b.n 800752c <HAL_TIM_GetChannelState+0x42>
8007524: 687b ldr r3, [r7, #4]
8007526: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800752a: b2db uxtb r3, r3
800752c: 73fb strb r3, [r7, #15]
return channel_state;
800752e: 7bfb ldrb r3, [r7, #15]
}
8007530: 4618 mov r0, r3
8007532: 3714 adds r7, #20
8007534: 46bd mov sp, r7
8007536: bc80 pop {r7}
8007538: 4770 bx lr
...
0800753c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
800753c: b480 push {r7}
800753e: b085 sub sp, #20
8007540: af00 add r7, sp, #0
8007542: 6078 str r0, [r7, #4]
8007544: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8007546: 687b ldr r3, [r7, #4]
8007548: 681b ldr r3, [r3, #0]
800754a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800754c: 687b ldr r3, [r7, #4]
800754e: 4a2f ldr r2, [pc, #188] @ (800760c <TIM_Base_SetConfig+0xd0>)
8007550: 4293 cmp r3, r2
8007552: d00b beq.n 800756c <TIM_Base_SetConfig+0x30>
8007554: 687b ldr r3, [r7, #4]
8007556: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800755a: d007 beq.n 800756c <TIM_Base_SetConfig+0x30>
800755c: 687b ldr r3, [r7, #4]
800755e: 4a2c ldr r2, [pc, #176] @ (8007610 <TIM_Base_SetConfig+0xd4>)
8007560: 4293 cmp r3, r2
8007562: d003 beq.n 800756c <TIM_Base_SetConfig+0x30>
8007564: 687b ldr r3, [r7, #4]
8007566: 4a2b ldr r2, [pc, #172] @ (8007614 <TIM_Base_SetConfig+0xd8>)
8007568: 4293 cmp r3, r2
800756a: d108 bne.n 800757e <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800756c: 68fb ldr r3, [r7, #12]
800756e: f023 0370 bic.w r3, r3, #112 @ 0x70
8007572: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8007574: 683b ldr r3, [r7, #0]
8007576: 685b ldr r3, [r3, #4]
8007578: 68fa ldr r2, [r7, #12]
800757a: 4313 orrs r3, r2
800757c: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800757e: 687b ldr r3, [r7, #4]
8007580: 4a22 ldr r2, [pc, #136] @ (800760c <TIM_Base_SetConfig+0xd0>)
8007582: 4293 cmp r3, r2
8007584: d00b beq.n 800759e <TIM_Base_SetConfig+0x62>
8007586: 687b ldr r3, [r7, #4]
8007588: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800758c: d007 beq.n 800759e <TIM_Base_SetConfig+0x62>
800758e: 687b ldr r3, [r7, #4]
8007590: 4a1f ldr r2, [pc, #124] @ (8007610 <TIM_Base_SetConfig+0xd4>)
8007592: 4293 cmp r3, r2
8007594: d003 beq.n 800759e <TIM_Base_SetConfig+0x62>
8007596: 687b ldr r3, [r7, #4]
8007598: 4a1e ldr r2, [pc, #120] @ (8007614 <TIM_Base_SetConfig+0xd8>)
800759a: 4293 cmp r3, r2
800759c: d108 bne.n 80075b0 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800759e: 68fb ldr r3, [r7, #12]
80075a0: f423 7340 bic.w r3, r3, #768 @ 0x300
80075a4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80075a6: 683b ldr r3, [r7, #0]
80075a8: 68db ldr r3, [r3, #12]
80075aa: 68fa ldr r2, [r7, #12]
80075ac: 4313 orrs r3, r2
80075ae: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80075b0: 68fb ldr r3, [r7, #12]
80075b2: f023 0280 bic.w r2, r3, #128 @ 0x80
80075b6: 683b ldr r3, [r7, #0]
80075b8: 695b ldr r3, [r3, #20]
80075ba: 4313 orrs r3, r2
80075bc: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80075be: 687b ldr r3, [r7, #4]
80075c0: 68fa ldr r2, [r7, #12]
80075c2: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80075c4: 683b ldr r3, [r7, #0]
80075c6: 689a ldr r2, [r3, #8]
80075c8: 687b ldr r3, [r7, #4]
80075ca: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80075cc: 683b ldr r3, [r7, #0]
80075ce: 681a ldr r2, [r3, #0]
80075d0: 687b ldr r3, [r7, #4]
80075d2: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80075d4: 687b ldr r3, [r7, #4]
80075d6: 4a0d ldr r2, [pc, #52] @ (800760c <TIM_Base_SetConfig+0xd0>)
80075d8: 4293 cmp r3, r2
80075da: d103 bne.n 80075e4 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80075dc: 683b ldr r3, [r7, #0]
80075de: 691a ldr r2, [r3, #16]
80075e0: 687b ldr r3, [r7, #4]
80075e2: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80075e4: 687b ldr r3, [r7, #4]
80075e6: 2201 movs r2, #1
80075e8: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
80075ea: 687b ldr r3, [r7, #4]
80075ec: 691b ldr r3, [r3, #16]
80075ee: f003 0301 and.w r3, r3, #1
80075f2: 2b00 cmp r3, #0
80075f4: d005 beq.n 8007602 <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
80075f6: 687b ldr r3, [r7, #4]
80075f8: 691b ldr r3, [r3, #16]
80075fa: f023 0201 bic.w r2, r3, #1
80075fe: 687b ldr r3, [r7, #4]
8007600: 611a str r2, [r3, #16]
}
}
8007602: bf00 nop
8007604: 3714 adds r7, #20
8007606: 46bd mov sp, r7
8007608: bc80 pop {r7}
800760a: 4770 bx lr
800760c: 40012c00 .word 0x40012c00
8007610: 40000400 .word 0x40000400
8007614: 40000800 .word 0x40000800
08007618 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8007618: b480 push {r7}
800761a: b087 sub sp, #28
800761c: af00 add r7, sp, #0
800761e: 6078 str r0, [r7, #4]
8007620: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007622: 687b ldr r3, [r7, #4]
8007624: 6a1b ldr r3, [r3, #32]
8007626: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8007628: 687b ldr r3, [r7, #4]
800762a: 6a1b ldr r3, [r3, #32]
800762c: f023 0201 bic.w r2, r3, #1
8007630: 687b ldr r3, [r7, #4]
8007632: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007634: 687b ldr r3, [r7, #4]
8007636: 685b ldr r3, [r3, #4]
8007638: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800763a: 687b ldr r3, [r7, #4]
800763c: 699b ldr r3, [r3, #24]
800763e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8007640: 68fb ldr r3, [r7, #12]
8007642: f023 0370 bic.w r3, r3, #112 @ 0x70
8007646: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8007648: 68fb ldr r3, [r7, #12]
800764a: f023 0303 bic.w r3, r3, #3
800764e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8007650: 683b ldr r3, [r7, #0]
8007652: 681b ldr r3, [r3, #0]
8007654: 68fa ldr r2, [r7, #12]
8007656: 4313 orrs r3, r2
8007658: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800765a: 697b ldr r3, [r7, #20]
800765c: f023 0302 bic.w r3, r3, #2
8007660: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8007662: 683b ldr r3, [r7, #0]
8007664: 689b ldr r3, [r3, #8]
8007666: 697a ldr r2, [r7, #20]
8007668: 4313 orrs r3, r2
800766a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
800766c: 687b ldr r3, [r7, #4]
800766e: 4a1c ldr r2, [pc, #112] @ (80076e0 <TIM_OC1_SetConfig+0xc8>)
8007670: 4293 cmp r3, r2
8007672: d10c bne.n 800768e <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8007674: 697b ldr r3, [r7, #20]
8007676: f023 0308 bic.w r3, r3, #8
800767a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
800767c: 683b ldr r3, [r7, #0]
800767e: 68db ldr r3, [r3, #12]
8007680: 697a ldr r2, [r7, #20]
8007682: 4313 orrs r3, r2
8007684: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8007686: 697b ldr r3, [r7, #20]
8007688: f023 0304 bic.w r3, r3, #4
800768c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800768e: 687b ldr r3, [r7, #4]
8007690: 4a13 ldr r2, [pc, #76] @ (80076e0 <TIM_OC1_SetConfig+0xc8>)
8007692: 4293 cmp r3, r2
8007694: d111 bne.n 80076ba <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8007696: 693b ldr r3, [r7, #16]
8007698: f423 7380 bic.w r3, r3, #256 @ 0x100
800769c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800769e: 693b ldr r3, [r7, #16]
80076a0: f423 7300 bic.w r3, r3, #512 @ 0x200
80076a4: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
80076a6: 683b ldr r3, [r7, #0]
80076a8: 695b ldr r3, [r3, #20]
80076aa: 693a ldr r2, [r7, #16]
80076ac: 4313 orrs r3, r2
80076ae: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
80076b0: 683b ldr r3, [r7, #0]
80076b2: 699b ldr r3, [r3, #24]
80076b4: 693a ldr r2, [r7, #16]
80076b6: 4313 orrs r3, r2
80076b8: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80076ba: 687b ldr r3, [r7, #4]
80076bc: 693a ldr r2, [r7, #16]
80076be: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80076c0: 687b ldr r3, [r7, #4]
80076c2: 68fa ldr r2, [r7, #12]
80076c4: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80076c6: 683b ldr r3, [r7, #0]
80076c8: 685a ldr r2, [r3, #4]
80076ca: 687b ldr r3, [r7, #4]
80076cc: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80076ce: 687b ldr r3, [r7, #4]
80076d0: 697a ldr r2, [r7, #20]
80076d2: 621a str r2, [r3, #32]
}
80076d4: bf00 nop
80076d6: 371c adds r7, #28
80076d8: 46bd mov sp, r7
80076da: bc80 pop {r7}
80076dc: 4770 bx lr
80076de: bf00 nop
80076e0: 40012c00 .word 0x40012c00
080076e4 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80076e4: b480 push {r7}
80076e6: b087 sub sp, #28
80076e8: af00 add r7, sp, #0
80076ea: 6078 str r0, [r7, #4]
80076ec: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80076ee: 687b ldr r3, [r7, #4]
80076f0: 6a1b ldr r3, [r3, #32]
80076f2: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80076f4: 687b ldr r3, [r7, #4]
80076f6: 6a1b ldr r3, [r3, #32]
80076f8: f023 0210 bic.w r2, r3, #16
80076fc: 687b ldr r3, [r7, #4]
80076fe: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007700: 687b ldr r3, [r7, #4]
8007702: 685b ldr r3, [r3, #4]
8007704: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8007706: 687b ldr r3, [r7, #4]
8007708: 699b ldr r3, [r3, #24]
800770a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800770c: 68fb ldr r3, [r7, #12]
800770e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007712: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8007714: 68fb ldr r3, [r7, #12]
8007716: f423 7340 bic.w r3, r3, #768 @ 0x300
800771a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800771c: 683b ldr r3, [r7, #0]
800771e: 681b ldr r3, [r3, #0]
8007720: 021b lsls r3, r3, #8
8007722: 68fa ldr r2, [r7, #12]
8007724: 4313 orrs r3, r2
8007726: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8007728: 697b ldr r3, [r7, #20]
800772a: f023 0320 bic.w r3, r3, #32
800772e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8007730: 683b ldr r3, [r7, #0]
8007732: 689b ldr r3, [r3, #8]
8007734: 011b lsls r3, r3, #4
8007736: 697a ldr r2, [r7, #20]
8007738: 4313 orrs r3, r2
800773a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800773c: 687b ldr r3, [r7, #4]
800773e: 4a1d ldr r2, [pc, #116] @ (80077b4 <TIM_OC2_SetConfig+0xd0>)
8007740: 4293 cmp r3, r2
8007742: d10d bne.n 8007760 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8007744: 697b ldr r3, [r7, #20]
8007746: f023 0380 bic.w r3, r3, #128 @ 0x80
800774a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800774c: 683b ldr r3, [r7, #0]
800774e: 68db ldr r3, [r3, #12]
8007750: 011b lsls r3, r3, #4
8007752: 697a ldr r2, [r7, #20]
8007754: 4313 orrs r3, r2
8007756: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8007758: 697b ldr r3, [r7, #20]
800775a: f023 0340 bic.w r3, r3, #64 @ 0x40
800775e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8007760: 687b ldr r3, [r7, #4]
8007762: 4a14 ldr r2, [pc, #80] @ (80077b4 <TIM_OC2_SetConfig+0xd0>)
8007764: 4293 cmp r3, r2
8007766: d113 bne.n 8007790 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8007768: 693b ldr r3, [r7, #16]
800776a: f423 6380 bic.w r3, r3, #1024 @ 0x400
800776e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8007770: 693b ldr r3, [r7, #16]
8007772: f423 6300 bic.w r3, r3, #2048 @ 0x800
8007776: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8007778: 683b ldr r3, [r7, #0]
800777a: 695b ldr r3, [r3, #20]
800777c: 009b lsls r3, r3, #2
800777e: 693a ldr r2, [r7, #16]
8007780: 4313 orrs r3, r2
8007782: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8007784: 683b ldr r3, [r7, #0]
8007786: 699b ldr r3, [r3, #24]
8007788: 009b lsls r3, r3, #2
800778a: 693a ldr r2, [r7, #16]
800778c: 4313 orrs r3, r2
800778e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007790: 687b ldr r3, [r7, #4]
8007792: 693a ldr r2, [r7, #16]
8007794: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8007796: 687b ldr r3, [r7, #4]
8007798: 68fa ldr r2, [r7, #12]
800779a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800779c: 683b ldr r3, [r7, #0]
800779e: 685a ldr r2, [r3, #4]
80077a0: 687b ldr r3, [r7, #4]
80077a2: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80077a4: 687b ldr r3, [r7, #4]
80077a6: 697a ldr r2, [r7, #20]
80077a8: 621a str r2, [r3, #32]
}
80077aa: bf00 nop
80077ac: 371c adds r7, #28
80077ae: 46bd mov sp, r7
80077b0: bc80 pop {r7}
80077b2: 4770 bx lr
80077b4: 40012c00 .word 0x40012c00
080077b8 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80077b8: b480 push {r7}
80077ba: b087 sub sp, #28
80077bc: af00 add r7, sp, #0
80077be: 6078 str r0, [r7, #4]
80077c0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80077c2: 687b ldr r3, [r7, #4]
80077c4: 6a1b ldr r3, [r3, #32]
80077c6: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
80077c8: 687b ldr r3, [r7, #4]
80077ca: 6a1b ldr r3, [r3, #32]
80077cc: f423 7280 bic.w r2, r3, #256 @ 0x100
80077d0: 687b ldr r3, [r7, #4]
80077d2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80077d4: 687b ldr r3, [r7, #4]
80077d6: 685b ldr r3, [r3, #4]
80077d8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80077da: 687b ldr r3, [r7, #4]
80077dc: 69db ldr r3, [r3, #28]
80077de: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
80077e0: 68fb ldr r3, [r7, #12]
80077e2: f023 0370 bic.w r3, r3, #112 @ 0x70
80077e6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80077e8: 68fb ldr r3, [r7, #12]
80077ea: f023 0303 bic.w r3, r3, #3
80077ee: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80077f0: 683b ldr r3, [r7, #0]
80077f2: 681b ldr r3, [r3, #0]
80077f4: 68fa ldr r2, [r7, #12]
80077f6: 4313 orrs r3, r2
80077f8: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80077fa: 697b ldr r3, [r7, #20]
80077fc: f423 7300 bic.w r3, r3, #512 @ 0x200
8007800: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8007802: 683b ldr r3, [r7, #0]
8007804: 689b ldr r3, [r3, #8]
8007806: 021b lsls r3, r3, #8
8007808: 697a ldr r2, [r7, #20]
800780a: 4313 orrs r3, r2
800780c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800780e: 687b ldr r3, [r7, #4]
8007810: 4a1d ldr r2, [pc, #116] @ (8007888 <TIM_OC3_SetConfig+0xd0>)
8007812: 4293 cmp r3, r2
8007814: d10d bne.n 8007832 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8007816: 697b ldr r3, [r7, #20]
8007818: f423 6300 bic.w r3, r3, #2048 @ 0x800
800781c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800781e: 683b ldr r3, [r7, #0]
8007820: 68db ldr r3, [r3, #12]
8007822: 021b lsls r3, r3, #8
8007824: 697a ldr r2, [r7, #20]
8007826: 4313 orrs r3, r2
8007828: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800782a: 697b ldr r3, [r7, #20]
800782c: f423 6380 bic.w r3, r3, #1024 @ 0x400
8007830: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8007832: 687b ldr r3, [r7, #4]
8007834: 4a14 ldr r2, [pc, #80] @ (8007888 <TIM_OC3_SetConfig+0xd0>)
8007836: 4293 cmp r3, r2
8007838: d113 bne.n 8007862 <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800783a: 693b ldr r3, [r7, #16]
800783c: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8007840: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8007842: 693b ldr r3, [r7, #16]
8007844: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8007848: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800784a: 683b ldr r3, [r7, #0]
800784c: 695b ldr r3, [r3, #20]
800784e: 011b lsls r3, r3, #4
8007850: 693a ldr r2, [r7, #16]
8007852: 4313 orrs r3, r2
8007854: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8007856: 683b ldr r3, [r7, #0]
8007858: 699b ldr r3, [r3, #24]
800785a: 011b lsls r3, r3, #4
800785c: 693a ldr r2, [r7, #16]
800785e: 4313 orrs r3, r2
8007860: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007862: 687b ldr r3, [r7, #4]
8007864: 693a ldr r2, [r7, #16]
8007866: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8007868: 687b ldr r3, [r7, #4]
800786a: 68fa ldr r2, [r7, #12]
800786c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800786e: 683b ldr r3, [r7, #0]
8007870: 685a ldr r2, [r3, #4]
8007872: 687b ldr r3, [r7, #4]
8007874: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007876: 687b ldr r3, [r7, #4]
8007878: 697a ldr r2, [r7, #20]
800787a: 621a str r2, [r3, #32]
}
800787c: bf00 nop
800787e: 371c adds r7, #28
8007880: 46bd mov sp, r7
8007882: bc80 pop {r7}
8007884: 4770 bx lr
8007886: bf00 nop
8007888: 40012c00 .word 0x40012c00
0800788c <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800788c: b480 push {r7}
800788e: b087 sub sp, #28
8007890: af00 add r7, sp, #0
8007892: 6078 str r0, [r7, #4]
8007894: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007896: 687b ldr r3, [r7, #4]
8007898: 6a1b ldr r3, [r3, #32]
800789a: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800789c: 687b ldr r3, [r7, #4]
800789e: 6a1b ldr r3, [r3, #32]
80078a0: f423 5280 bic.w r2, r3, #4096 @ 0x1000
80078a4: 687b ldr r3, [r7, #4]
80078a6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80078a8: 687b ldr r3, [r7, #4]
80078aa: 685b ldr r3, [r3, #4]
80078ac: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80078ae: 687b ldr r3, [r7, #4]
80078b0: 69db ldr r3, [r3, #28]
80078b2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
80078b4: 68fb ldr r3, [r7, #12]
80078b6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80078ba: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80078bc: 68fb ldr r3, [r7, #12]
80078be: f423 7340 bic.w r3, r3, #768 @ 0x300
80078c2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80078c4: 683b ldr r3, [r7, #0]
80078c6: 681b ldr r3, [r3, #0]
80078c8: 021b lsls r3, r3, #8
80078ca: 68fa ldr r2, [r7, #12]
80078cc: 4313 orrs r3, r2
80078ce: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80078d0: 693b ldr r3, [r7, #16]
80078d2: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80078d6: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80078d8: 683b ldr r3, [r7, #0]
80078da: 689b ldr r3, [r3, #8]
80078dc: 031b lsls r3, r3, #12
80078de: 693a ldr r2, [r7, #16]
80078e0: 4313 orrs r3, r2
80078e2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80078e4: 687b ldr r3, [r7, #4]
80078e6: 4a0f ldr r2, [pc, #60] @ (8007924 <TIM_OC4_SetConfig+0x98>)
80078e8: 4293 cmp r3, r2
80078ea: d109 bne.n 8007900 <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80078ec: 697b ldr r3, [r7, #20]
80078ee: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80078f2: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80078f4: 683b ldr r3, [r7, #0]
80078f6: 695b ldr r3, [r3, #20]
80078f8: 019b lsls r3, r3, #6
80078fa: 697a ldr r2, [r7, #20]
80078fc: 4313 orrs r3, r2
80078fe: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8007900: 687b ldr r3, [r7, #4]
8007902: 697a ldr r2, [r7, #20]
8007904: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8007906: 687b ldr r3, [r7, #4]
8007908: 68fa ldr r2, [r7, #12]
800790a: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
800790c: 683b ldr r3, [r7, #0]
800790e: 685a ldr r2, [r3, #4]
8007910: 687b ldr r3, [r7, #4]
8007912: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8007914: 687b ldr r3, [r7, #4]
8007916: 693a ldr r2, [r7, #16]
8007918: 621a str r2, [r3, #32]
}
800791a: bf00 nop
800791c: 371c adds r7, #28
800791e: 46bd mov sp, r7
8007920: bc80 pop {r7}
8007922: 4770 bx lr
8007924: 40012c00 .word 0x40012c00
08007928 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8007928: b480 push {r7}
800792a: b087 sub sp, #28
800792c: af00 add r7, sp, #0
800792e: 60f8 str r0, [r7, #12]
8007930: 60b9 str r1, [r7, #8]
8007932: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8007934: 68fb ldr r3, [r7, #12]
8007936: 6a1b ldr r3, [r3, #32]
8007938: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
800793a: 68fb ldr r3, [r7, #12]
800793c: 6a1b ldr r3, [r3, #32]
800793e: f023 0201 bic.w r2, r3, #1
8007942: 68fb ldr r3, [r7, #12]
8007944: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8007946: 68fb ldr r3, [r7, #12]
8007948: 699b ldr r3, [r3, #24]
800794a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800794c: 693b ldr r3, [r7, #16]
800794e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8007952: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8007954: 687b ldr r3, [r7, #4]
8007956: 011b lsls r3, r3, #4
8007958: 693a ldr r2, [r7, #16]
800795a: 4313 orrs r3, r2
800795c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800795e: 697b ldr r3, [r7, #20]
8007960: f023 030a bic.w r3, r3, #10
8007964: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8007966: 697a ldr r2, [r7, #20]
8007968: 68bb ldr r3, [r7, #8]
800796a: 4313 orrs r3, r2
800796c: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800796e: 68fb ldr r3, [r7, #12]
8007970: 693a ldr r2, [r7, #16]
8007972: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8007974: 68fb ldr r3, [r7, #12]
8007976: 697a ldr r2, [r7, #20]
8007978: 621a str r2, [r3, #32]
}
800797a: bf00 nop
800797c: 371c adds r7, #28
800797e: 46bd mov sp, r7
8007980: bc80 pop {r7}
8007982: 4770 bx lr
08007984 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8007984: b480 push {r7}
8007986: b087 sub sp, #28
8007988: af00 add r7, sp, #0
800798a: 60f8 str r0, [r7, #12]
800798c: 60b9 str r1, [r7, #8]
800798e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8007990: 68fb ldr r3, [r7, #12]
8007992: 6a1b ldr r3, [r3, #32]
8007994: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8007996: 68fb ldr r3, [r7, #12]
8007998: 6a1b ldr r3, [r3, #32]
800799a: f023 0210 bic.w r2, r3, #16
800799e: 68fb ldr r3, [r7, #12]
80079a0: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80079a2: 68fb ldr r3, [r7, #12]
80079a4: 699b ldr r3, [r3, #24]
80079a6: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80079a8: 693b ldr r3, [r7, #16]
80079aa: f423 4370 bic.w r3, r3, #61440 @ 0xf000
80079ae: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
80079b0: 687b ldr r3, [r7, #4]
80079b2: 031b lsls r3, r3, #12
80079b4: 693a ldr r2, [r7, #16]
80079b6: 4313 orrs r3, r2
80079b8: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80079ba: 697b ldr r3, [r7, #20]
80079bc: f023 03a0 bic.w r3, r3, #160 @ 0xa0
80079c0: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
80079c2: 68bb ldr r3, [r7, #8]
80079c4: 011b lsls r3, r3, #4
80079c6: 697a ldr r2, [r7, #20]
80079c8: 4313 orrs r3, r2
80079ca: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80079cc: 68fb ldr r3, [r7, #12]
80079ce: 693a ldr r2, [r7, #16]
80079d0: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80079d2: 68fb ldr r3, [r7, #12]
80079d4: 697a ldr r2, [r7, #20]
80079d6: 621a str r2, [r3, #32]
}
80079d8: bf00 nop
80079da: 371c adds r7, #28
80079dc: 46bd mov sp, r7
80079de: bc80 pop {r7}
80079e0: 4770 bx lr
080079e2 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80079e2: b480 push {r7}
80079e4: b085 sub sp, #20
80079e6: af00 add r7, sp, #0
80079e8: 6078 str r0, [r7, #4]
80079ea: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80079ec: 687b ldr r3, [r7, #4]
80079ee: 689b ldr r3, [r3, #8]
80079f0: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80079f2: 68fb ldr r3, [r7, #12]
80079f4: f023 0370 bic.w r3, r3, #112 @ 0x70
80079f8: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80079fa: 683a ldr r2, [r7, #0]
80079fc: 68fb ldr r3, [r7, #12]
80079fe: 4313 orrs r3, r2
8007a00: f043 0307 orr.w r3, r3, #7
8007a04: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8007a06: 687b ldr r3, [r7, #4]
8007a08: 68fa ldr r2, [r7, #12]
8007a0a: 609a str r2, [r3, #8]
}
8007a0c: bf00 nop
8007a0e: 3714 adds r7, #20
8007a10: 46bd mov sp, r7
8007a12: bc80 pop {r7}
8007a14: 4770 bx lr
08007a16 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8007a16: b480 push {r7}
8007a18: b087 sub sp, #28
8007a1a: af00 add r7, sp, #0
8007a1c: 60f8 str r0, [r7, #12]
8007a1e: 60b9 str r1, [r7, #8]
8007a20: 607a str r2, [r7, #4]
8007a22: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8007a24: 68fb ldr r3, [r7, #12]
8007a26: 689b ldr r3, [r3, #8]
8007a28: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8007a2a: 697b ldr r3, [r7, #20]
8007a2c: f423 437f bic.w r3, r3, #65280 @ 0xff00
8007a30: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8007a32: 683b ldr r3, [r7, #0]
8007a34: 021a lsls r2, r3, #8
8007a36: 687b ldr r3, [r7, #4]
8007a38: 431a orrs r2, r3
8007a3a: 68bb ldr r3, [r7, #8]
8007a3c: 4313 orrs r3, r2
8007a3e: 697a ldr r2, [r7, #20]
8007a40: 4313 orrs r3, r2
8007a42: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8007a44: 68fb ldr r3, [r7, #12]
8007a46: 697a ldr r2, [r7, #20]
8007a48: 609a str r2, [r3, #8]
}
8007a4a: bf00 nop
8007a4c: 371c adds r7, #28
8007a4e: 46bd mov sp, r7
8007a50: bc80 pop {r7}
8007a52: 4770 bx lr
08007a54 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8007a54: b480 push {r7}
8007a56: b087 sub sp, #28
8007a58: af00 add r7, sp, #0
8007a5a: 60f8 str r0, [r7, #12]
8007a5c: 60b9 str r1, [r7, #8]
8007a5e: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8007a60: 68bb ldr r3, [r7, #8]
8007a62: f003 031f and.w r3, r3, #31
8007a66: 2201 movs r2, #1
8007a68: fa02 f303 lsl.w r3, r2, r3
8007a6c: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8007a6e: 68fb ldr r3, [r7, #12]
8007a70: 6a1a ldr r2, [r3, #32]
8007a72: 697b ldr r3, [r7, #20]
8007a74: 43db mvns r3, r3
8007a76: 401a ands r2, r3
8007a78: 68fb ldr r3, [r7, #12]
8007a7a: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8007a7c: 68fb ldr r3, [r7, #12]
8007a7e: 6a1a ldr r2, [r3, #32]
8007a80: 68bb ldr r3, [r7, #8]
8007a82: f003 031f and.w r3, r3, #31
8007a86: 6879 ldr r1, [r7, #4]
8007a88: fa01 f303 lsl.w r3, r1, r3
8007a8c: 431a orrs r2, r3
8007a8e: 68fb ldr r3, [r7, #12]
8007a90: 621a str r2, [r3, #32]
}
8007a92: bf00 nop
8007a94: 371c adds r7, #28
8007a96: 46bd mov sp, r7
8007a98: bc80 pop {r7}
8007a9a: 4770 bx lr
08007a9c <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8007a9c: b480 push {r7}
8007a9e: b085 sub sp, #20
8007aa0: af00 add r7, sp, #0
8007aa2: 6078 str r0, [r7, #4]
8007aa4: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8007aa6: 687b ldr r3, [r7, #4]
8007aa8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8007aac: 2b01 cmp r3, #1
8007aae: d101 bne.n 8007ab4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8007ab0: 2302 movs r3, #2
8007ab2: e046 b.n 8007b42 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8007ab4: 687b ldr r3, [r7, #4]
8007ab6: 2201 movs r2, #1
8007ab8: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8007abc: 687b ldr r3, [r7, #4]
8007abe: 2202 movs r2, #2
8007ac0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8007ac4: 687b ldr r3, [r7, #4]
8007ac6: 681b ldr r3, [r3, #0]
8007ac8: 685b ldr r3, [r3, #4]
8007aca: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8007acc: 687b ldr r3, [r7, #4]
8007ace: 681b ldr r3, [r3, #0]
8007ad0: 689b ldr r3, [r3, #8]
8007ad2: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8007ad4: 68fb ldr r3, [r7, #12]
8007ad6: f023 0370 bic.w r3, r3, #112 @ 0x70
8007ada: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8007adc: 683b ldr r3, [r7, #0]
8007ade: 681b ldr r3, [r3, #0]
8007ae0: 68fa ldr r2, [r7, #12]
8007ae2: 4313 orrs r3, r2
8007ae4: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8007ae6: 687b ldr r3, [r7, #4]
8007ae8: 681b ldr r3, [r3, #0]
8007aea: 68fa ldr r2, [r7, #12]
8007aec: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8007aee: 687b ldr r3, [r7, #4]
8007af0: 681b ldr r3, [r3, #0]
8007af2: 4a16 ldr r2, [pc, #88] @ (8007b4c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8007af4: 4293 cmp r3, r2
8007af6: d00e beq.n 8007b16 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8007af8: 687b ldr r3, [r7, #4]
8007afa: 681b ldr r3, [r3, #0]
8007afc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8007b00: d009 beq.n 8007b16 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8007b02: 687b ldr r3, [r7, #4]
8007b04: 681b ldr r3, [r3, #0]
8007b06: 4a12 ldr r2, [pc, #72] @ (8007b50 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8007b08: 4293 cmp r3, r2
8007b0a: d004 beq.n 8007b16 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8007b0c: 687b ldr r3, [r7, #4]
8007b0e: 681b ldr r3, [r3, #0]
8007b10: 4a10 ldr r2, [pc, #64] @ (8007b54 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8007b12: 4293 cmp r3, r2
8007b14: d10c bne.n 8007b30 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8007b16: 68bb ldr r3, [r7, #8]
8007b18: f023 0380 bic.w r3, r3, #128 @ 0x80
8007b1c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8007b1e: 683b ldr r3, [r7, #0]
8007b20: 685b ldr r3, [r3, #4]
8007b22: 68ba ldr r2, [r7, #8]
8007b24: 4313 orrs r3, r2
8007b26: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8007b28: 687b ldr r3, [r7, #4]
8007b2a: 681b ldr r3, [r3, #0]
8007b2c: 68ba ldr r2, [r7, #8]
8007b2e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8007b30: 687b ldr r3, [r7, #4]
8007b32: 2201 movs r2, #1
8007b34: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8007b38: 687b ldr r3, [r7, #4]
8007b3a: 2200 movs r2, #0
8007b3c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8007b40: 2300 movs r3, #0
}
8007b42: 4618 mov r0, r3
8007b44: 3714 adds r7, #20
8007b46: 46bd mov sp, r7
8007b48: bc80 pop {r7}
8007b4a: 4770 bx lr
8007b4c: 40012c00 .word 0x40012c00
8007b50: 40000400 .word 0x40000400
8007b54: 40000800 .word 0x40000800
08007b58 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8007b58: b580 push {r7, lr}
8007b5a: b082 sub sp, #8
8007b5c: af00 add r7, sp, #0
8007b5e: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8007b60: 687b ldr r3, [r7, #4]
8007b62: 2b00 cmp r3, #0
8007b64: d101 bne.n 8007b6a <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8007b66: 2301 movs r3, #1
8007b68: e042 b.n 8007bf0 <HAL_UART_Init+0x98>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
8007b6a: 687b ldr r3, [r7, #4]
8007b6c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007b70: b2db uxtb r3, r3
8007b72: 2b00 cmp r3, #0
8007b74: d106 bne.n 8007b84 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8007b76: 687b ldr r3, [r7, #4]
8007b78: 2200 movs r2, #0
8007b7a: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8007b7e: 6878 ldr r0, [r7, #4]
8007b80: f7fb fb68 bl 8003254 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8007b84: 687b ldr r3, [r7, #4]
8007b86: 2224 movs r2, #36 @ 0x24
8007b88: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8007b8c: 687b ldr r3, [r7, #4]
8007b8e: 681b ldr r3, [r3, #0]
8007b90: 68da ldr r2, [r3, #12]
8007b92: 687b ldr r3, [r7, #4]
8007b94: 681b ldr r3, [r3, #0]
8007b96: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8007b9a: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8007b9c: 6878 ldr r0, [r7, #4]
8007b9e: f000 f82b bl 8007bf8 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8007ba2: 687b ldr r3, [r7, #4]
8007ba4: 681b ldr r3, [r3, #0]
8007ba6: 691a ldr r2, [r3, #16]
8007ba8: 687b ldr r3, [r7, #4]
8007baa: 681b ldr r3, [r3, #0]
8007bac: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8007bb0: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8007bb2: 687b ldr r3, [r7, #4]
8007bb4: 681b ldr r3, [r3, #0]
8007bb6: 695a ldr r2, [r3, #20]
8007bb8: 687b ldr r3, [r7, #4]
8007bba: 681b ldr r3, [r3, #0]
8007bbc: f022 022a bic.w r2, r2, #42 @ 0x2a
8007bc0: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8007bc2: 687b ldr r3, [r7, #4]
8007bc4: 681b ldr r3, [r3, #0]
8007bc6: 68da ldr r2, [r3, #12]
8007bc8: 687b ldr r3, [r7, #4]
8007bca: 681b ldr r3, [r3, #0]
8007bcc: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8007bd0: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007bd2: 687b ldr r3, [r7, #4]
8007bd4: 2200 movs r2, #0
8007bd6: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
8007bd8: 687b ldr r3, [r7, #4]
8007bda: 2220 movs r2, #32
8007bdc: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8007be0: 687b ldr r3, [r7, #4]
8007be2: 2220 movs r2, #32
8007be4: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007be8: 687b ldr r3, [r7, #4]
8007bea: 2200 movs r2, #0
8007bec: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8007bee: 2300 movs r3, #0
}
8007bf0: 4618 mov r0, r3
8007bf2: 3708 adds r7, #8
8007bf4: 46bd mov sp, r7
8007bf6: bd80 pop {r7, pc}
08007bf8 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8007bf8: b580 push {r7, lr}
8007bfa: b084 sub sp, #16
8007bfc: af00 add r7, sp, #0
8007bfe: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8007c00: 687b ldr r3, [r7, #4]
8007c02: 681b ldr r3, [r3, #0]
8007c04: 691b ldr r3, [r3, #16]
8007c06: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8007c0a: 687b ldr r3, [r7, #4]
8007c0c: 68da ldr r2, [r3, #12]
8007c0e: 687b ldr r3, [r7, #4]
8007c10: 681b ldr r3, [r3, #0]
8007c12: 430a orrs r2, r1
8007c14: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
8007c16: 687b ldr r3, [r7, #4]
8007c18: 689a ldr r2, [r3, #8]
8007c1a: 687b ldr r3, [r7, #4]
8007c1c: 691b ldr r3, [r3, #16]
8007c1e: 431a orrs r2, r3
8007c20: 687b ldr r3, [r7, #4]
8007c22: 695b ldr r3, [r3, #20]
8007c24: 4313 orrs r3, r2
8007c26: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
8007c28: 687b ldr r3, [r7, #4]
8007c2a: 681b ldr r3, [r3, #0]
8007c2c: 68db ldr r3, [r3, #12]
8007c2e: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
8007c32: f023 030c bic.w r3, r3, #12
8007c36: 687a ldr r2, [r7, #4]
8007c38: 6812 ldr r2, [r2, #0]
8007c3a: 68b9 ldr r1, [r7, #8]
8007c3c: 430b orrs r3, r1
8007c3e: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8007c40: 687b ldr r3, [r7, #4]
8007c42: 681b ldr r3, [r3, #0]
8007c44: 695b ldr r3, [r3, #20]
8007c46: f423 7140 bic.w r1, r3, #768 @ 0x300
8007c4a: 687b ldr r3, [r7, #4]
8007c4c: 699a ldr r2, [r3, #24]
8007c4e: 687b ldr r3, [r7, #4]
8007c50: 681b ldr r3, [r3, #0]
8007c52: 430a orrs r2, r1
8007c54: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
8007c56: 687b ldr r3, [r7, #4]
8007c58: 681b ldr r3, [r3, #0]
8007c5a: 4a2c ldr r2, [pc, #176] @ (8007d0c <UART_SetConfig+0x114>)
8007c5c: 4293 cmp r3, r2
8007c5e: d103 bne.n 8007c68 <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8007c60: f7ff f824 bl 8006cac <HAL_RCC_GetPCLK2Freq>
8007c64: 60f8 str r0, [r7, #12]
8007c66: e002 b.n 8007c6e <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8007c68: f7ff f80c bl 8006c84 <HAL_RCC_GetPCLK1Freq>
8007c6c: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8007c6e: 68fa ldr r2, [r7, #12]
8007c70: 4613 mov r3, r2
8007c72: 009b lsls r3, r3, #2
8007c74: 4413 add r3, r2
8007c76: 009a lsls r2, r3, #2
8007c78: 441a add r2, r3
8007c7a: 687b ldr r3, [r7, #4]
8007c7c: 685b ldr r3, [r3, #4]
8007c7e: 009b lsls r3, r3, #2
8007c80: fbb2 f3f3 udiv r3, r2, r3
8007c84: 4a22 ldr r2, [pc, #136] @ (8007d10 <UART_SetConfig+0x118>)
8007c86: fba2 2303 umull r2, r3, r2, r3
8007c8a: 095b lsrs r3, r3, #5
8007c8c: 0119 lsls r1, r3, #4
8007c8e: 68fa ldr r2, [r7, #12]
8007c90: 4613 mov r3, r2
8007c92: 009b lsls r3, r3, #2
8007c94: 4413 add r3, r2
8007c96: 009a lsls r2, r3, #2
8007c98: 441a add r2, r3
8007c9a: 687b ldr r3, [r7, #4]
8007c9c: 685b ldr r3, [r3, #4]
8007c9e: 009b lsls r3, r3, #2
8007ca0: fbb2 f2f3 udiv r2, r2, r3
8007ca4: 4b1a ldr r3, [pc, #104] @ (8007d10 <UART_SetConfig+0x118>)
8007ca6: fba3 0302 umull r0, r3, r3, r2
8007caa: 095b lsrs r3, r3, #5
8007cac: 2064 movs r0, #100 @ 0x64
8007cae: fb00 f303 mul.w r3, r0, r3
8007cb2: 1ad3 subs r3, r2, r3
8007cb4: 011b lsls r3, r3, #4
8007cb6: 3332 adds r3, #50 @ 0x32
8007cb8: 4a15 ldr r2, [pc, #84] @ (8007d10 <UART_SetConfig+0x118>)
8007cba: fba2 2303 umull r2, r3, r2, r3
8007cbe: 095b lsrs r3, r3, #5
8007cc0: f003 03f0 and.w r3, r3, #240 @ 0xf0
8007cc4: 4419 add r1, r3
8007cc6: 68fa ldr r2, [r7, #12]
8007cc8: 4613 mov r3, r2
8007cca: 009b lsls r3, r3, #2
8007ccc: 4413 add r3, r2
8007cce: 009a lsls r2, r3, #2
8007cd0: 441a add r2, r3
8007cd2: 687b ldr r3, [r7, #4]
8007cd4: 685b ldr r3, [r3, #4]
8007cd6: 009b lsls r3, r3, #2
8007cd8: fbb2 f2f3 udiv r2, r2, r3
8007cdc: 4b0c ldr r3, [pc, #48] @ (8007d10 <UART_SetConfig+0x118>)
8007cde: fba3 0302 umull r0, r3, r3, r2
8007ce2: 095b lsrs r3, r3, #5
8007ce4: 2064 movs r0, #100 @ 0x64
8007ce6: fb00 f303 mul.w r3, r0, r3
8007cea: 1ad3 subs r3, r2, r3
8007cec: 011b lsls r3, r3, #4
8007cee: 3332 adds r3, #50 @ 0x32
8007cf0: 4a07 ldr r2, [pc, #28] @ (8007d10 <UART_SetConfig+0x118>)
8007cf2: fba2 2303 umull r2, r3, r2, r3
8007cf6: 095b lsrs r3, r3, #5
8007cf8: f003 020f and.w r2, r3, #15
8007cfc: 687b ldr r3, [r7, #4]
8007cfe: 681b ldr r3, [r3, #0]
8007d00: 440a add r2, r1
8007d02: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
8007d04: bf00 nop
8007d06: 3710 adds r7, #16
8007d08: 46bd mov sp, r7
8007d0a: bd80 pop {r7, pc}
8007d0c: 40013800 .word 0x40013800
8007d10: 51eb851f .word 0x51eb851f
08007d14 <USB_CoreInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8007d14: b480 push {r7}
8007d16: b085 sub sp, #20
8007d18: af00 add r7, sp, #0
8007d1a: 60f8 str r0, [r7, #12]
8007d1c: 4638 mov r0, r7
8007d1e: e880 000e stmia.w r0, {r1, r2, r3}
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8007d22: 2300 movs r3, #0
}
8007d24: 4618 mov r0, r3
8007d26: 3714 adds r7, #20
8007d28: 46bd mov sp, r7
8007d2a: bc80 pop {r7}
8007d2c: 4770 bx lr
08007d2e <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
8007d2e: b480 push {r7}
8007d30: b085 sub sp, #20
8007d32: af00 add r7, sp, #0
8007d34: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
8007d36: 687b ldr r3, [r7, #4]
8007d38: 2200 movs r2, #0
8007d3a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8007d3e: f44f 433f mov.w r3, #48896 @ 0xbf00
8007d42: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR = (uint16_t)winterruptmask;
8007d44: 68fb ldr r3, [r7, #12]
8007d46: b29a uxth r2, r3
8007d48: 687b ldr r3, [r7, #4]
8007d4a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8007d4e: 2300 movs r3, #0
}
8007d50: 4618 mov r0, r3
8007d52: 3714 adds r7, #20
8007d54: 46bd mov sp, r7
8007d56: bc80 pop {r7}
8007d58: 4770 bx lr
08007d5a <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
8007d5a: b480 push {r7}
8007d5c: b085 sub sp, #20
8007d5e: af00 add r7, sp, #0
8007d60: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8007d62: f44f 433f mov.w r3, #48896 @ 0xbf00
8007d66: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= (uint16_t)(~winterruptmask);
8007d68: 687b ldr r3, [r7, #4]
8007d6a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8007d6e: b29a uxth r2, r3
8007d70: 68fb ldr r3, [r7, #12]
8007d72: b29b uxth r3, r3
8007d74: 43db mvns r3, r3
8007d76: b29b uxth r3, r3
8007d78: 4013 ands r3, r2
8007d7a: b29a uxth r2, r3
8007d7c: 687b ldr r3, [r7, #4]
8007d7e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8007d82: 2300 movs r3, #0
}
8007d84: 4618 mov r0, r3
8007d86: 3714 adds r7, #20
8007d88: 46bd mov sp, r7
8007d8a: bc80 pop {r7}
8007d8c: 4770 bx lr
08007d8e <USB_SetCurrentMode>:
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
8007d8e: b480 push {r7}
8007d90: b083 sub sp, #12
8007d92: af00 add r7, sp, #0
8007d94: 6078 str r0, [r7, #4]
8007d96: 460b mov r3, r1
8007d98: 70fb strb r3, [r7, #3]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8007d9a: 2300 movs r3, #0
}
8007d9c: 4618 mov r0, r3
8007d9e: 370c adds r7, #12
8007da0: 46bd mov sp, r7
8007da2: bc80 pop {r7}
8007da4: 4770 bx lr
08007da6 <USB_DevInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8007da6: b480 push {r7}
8007da8: b085 sub sp, #20
8007daa: af00 add r7, sp, #0
8007dac: 60f8 str r0, [r7, #12]
8007dae: 4638 mov r0, r7
8007db0: e880 000e stmia.w r0, {r1, r2, r3}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
8007db4: 68fb ldr r3, [r7, #12]
8007db6: 2201 movs r2, #1
8007db8: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
8007dbc: 68fb ldr r3, [r7, #12]
8007dbe: 2200 movs r2, #0
8007dc0: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* Clear pending interrupts */
USBx->ISTR = 0U;
8007dc4: 68fb ldr r3, [r7, #12]
8007dc6: 2200 movs r2, #0
8007dc8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
8007dcc: 68fb ldr r3, [r7, #12]
8007dce: 2200 movs r2, #0
8007dd0: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
return HAL_OK;
8007dd4: 2300 movs r3, #0
}
8007dd6: 4618 mov r0, r3
8007dd8: 3714 adds r7, #20
8007dda: 46bd mov sp, r7
8007ddc: bc80 pop {r7}
8007dde: 4770 bx lr
08007de0 <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8007de0: b480 push {r7}
8007de2: b09d sub sp, #116 @ 0x74
8007de4: af00 add r7, sp, #0
8007de6: 6078 str r0, [r7, #4]
8007de8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef ret = HAL_OK;
8007dea: 2300 movs r3, #0
8007dec: f887 306f strb.w r3, [r7, #111] @ 0x6f
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
8007df0: 687a ldr r2, [r7, #4]
8007df2: 683b ldr r3, [r7, #0]
8007df4: 781b ldrb r3, [r3, #0]
8007df6: 009b lsls r3, r3, #2
8007df8: 4413 add r3, r2
8007dfa: 881b ldrh r3, [r3, #0]
8007dfc: b29b uxth r3, r3
8007dfe: f423 43ec bic.w r3, r3, #30208 @ 0x7600
8007e02: f023 0370 bic.w r3, r3, #112 @ 0x70
8007e06: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
/* initialize Endpoint */
switch (ep->type)
8007e0a: 683b ldr r3, [r7, #0]
8007e0c: 78db ldrb r3, [r3, #3]
8007e0e: 2b03 cmp r3, #3
8007e10: d81f bhi.n 8007e52 <USB_ActivateEndpoint+0x72>
8007e12: a201 add r2, pc, #4 @ (adr r2, 8007e18 <USB_ActivateEndpoint+0x38>)
8007e14: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007e18: 08007e29 .word 0x08007e29
8007e1c: 08007e45 .word 0x08007e45
8007e20: 08007e5b .word 0x08007e5b
8007e24: 08007e37 .word 0x08007e37
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
8007e28: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8007e2c: f443 7300 orr.w r3, r3, #512 @ 0x200
8007e30: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8007e34: e012 b.n 8007e5c <USB_ActivateEndpoint+0x7c>
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
8007e36: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8007e3a: f443 63c0 orr.w r3, r3, #1536 @ 0x600
8007e3e: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8007e42: e00b b.n 8007e5c <USB_ActivateEndpoint+0x7c>
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
8007e44: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8007e48: f443 6380 orr.w r3, r3, #1024 @ 0x400
8007e4c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8007e50: e004 b.n 8007e5c <USB_ActivateEndpoint+0x7c>
default:
ret = HAL_ERROR;
8007e52: 2301 movs r3, #1
8007e54: f887 306f strb.w r3, [r7, #111] @ 0x6f
break;
8007e58: e000 b.n 8007e5c <USB_ActivateEndpoint+0x7c>
break;
8007e5a: bf00 nop
}
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
8007e5c: 687a ldr r2, [r7, #4]
8007e5e: 683b ldr r3, [r7, #0]
8007e60: 781b ldrb r3, [r3, #0]
8007e62: 009b lsls r3, r3, #2
8007e64: 441a add r2, r3
8007e66: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8007e6a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007e6e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007e72: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007e76: f043 0380 orr.w r3, r3, #128 @ 0x80
8007e7a: b29b uxth r3, r3
8007e7c: 8013 strh r3, [r2, #0]
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
8007e7e: 687a ldr r2, [r7, #4]
8007e80: 683b ldr r3, [r7, #0]
8007e82: 781b ldrb r3, [r3, #0]
8007e84: 009b lsls r3, r3, #2
8007e86: 4413 add r3, r2
8007e88: 881b ldrh r3, [r3, #0]
8007e8a: b29b uxth r3, r3
8007e8c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007e90: f023 0370 bic.w r3, r3, #112 @ 0x70
8007e94: b29b uxth r3, r3
8007e96: 683a ldr r2, [r7, #0]
8007e98: 7812 ldrb r2, [r2, #0]
8007e9a: 4313 orrs r3, r2
8007e9c: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
8007ea0: 687a ldr r2, [r7, #4]
8007ea2: 683b ldr r3, [r7, #0]
8007ea4: 781b ldrb r3, [r3, #0]
8007ea6: 009b lsls r3, r3, #2
8007ea8: 441a add r2, r3
8007eaa: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
8007eae: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007eb2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007eb6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007eba: f043 0380 orr.w r3, r3, #128 @ 0x80
8007ebe: b29b uxth r3, r3
8007ec0: 8013 strh r3, [r2, #0]
if (ep->doublebuffer == 0U)
8007ec2: 683b ldr r3, [r7, #0]
8007ec4: 7b1b ldrb r3, [r3, #12]
8007ec6: 2b00 cmp r3, #0
8007ec8: f040 8178 bne.w 80081bc <USB_ActivateEndpoint+0x3dc>
{
if (ep->is_in != 0U)
8007ecc: 683b ldr r3, [r7, #0]
8007ece: 785b ldrb r3, [r3, #1]
8007ed0: 2b00 cmp r3, #0
8007ed2: f000 8084 beq.w 8007fde <USB_ActivateEndpoint+0x1fe>
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
8007ed6: 687b ldr r3, [r7, #4]
8007ed8: 61bb str r3, [r7, #24]
8007eda: 687b ldr r3, [r7, #4]
8007edc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007ee0: b29b uxth r3, r3
8007ee2: 461a mov r2, r3
8007ee4: 69bb ldr r3, [r7, #24]
8007ee6: 4413 add r3, r2
8007ee8: 61bb str r3, [r7, #24]
8007eea: 683b ldr r3, [r7, #0]
8007eec: 781b ldrb r3, [r3, #0]
8007eee: 011a lsls r2, r3, #4
8007ef0: 69bb ldr r3, [r7, #24]
8007ef2: 4413 add r3, r2
8007ef4: f503 6380 add.w r3, r3, #1024 @ 0x400
8007ef8: 617b str r3, [r7, #20]
8007efa: 683b ldr r3, [r7, #0]
8007efc: 88db ldrh r3, [r3, #6]
8007efe: 085b lsrs r3, r3, #1
8007f00: b29b uxth r3, r3
8007f02: 005b lsls r3, r3, #1
8007f04: b29a uxth r2, r3
8007f06: 697b ldr r3, [r7, #20]
8007f08: 801a strh r2, [r3, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8007f0a: 687a ldr r2, [r7, #4]
8007f0c: 683b ldr r3, [r7, #0]
8007f0e: 781b ldrb r3, [r3, #0]
8007f10: 009b lsls r3, r3, #2
8007f12: 4413 add r3, r2
8007f14: 881b ldrh r3, [r3, #0]
8007f16: 827b strh r3, [r7, #18]
8007f18: 8a7b ldrh r3, [r7, #18]
8007f1a: f003 0340 and.w r3, r3, #64 @ 0x40
8007f1e: 2b00 cmp r3, #0
8007f20: d01b beq.n 8007f5a <USB_ActivateEndpoint+0x17a>
8007f22: 687a ldr r2, [r7, #4]
8007f24: 683b ldr r3, [r7, #0]
8007f26: 781b ldrb r3, [r3, #0]
8007f28: 009b lsls r3, r3, #2
8007f2a: 4413 add r3, r2
8007f2c: 881b ldrh r3, [r3, #0]
8007f2e: b29b uxth r3, r3
8007f30: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007f34: f023 0370 bic.w r3, r3, #112 @ 0x70
8007f38: 823b strh r3, [r7, #16]
8007f3a: 687a ldr r2, [r7, #4]
8007f3c: 683b ldr r3, [r7, #0]
8007f3e: 781b ldrb r3, [r3, #0]
8007f40: 009b lsls r3, r3, #2
8007f42: 441a add r2, r3
8007f44: 8a3b ldrh r3, [r7, #16]
8007f46: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007f4a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007f4e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007f52: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8007f56: b29b uxth r3, r3
8007f58: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8007f5a: 683b ldr r3, [r7, #0]
8007f5c: 78db ldrb r3, [r3, #3]
8007f5e: 2b01 cmp r3, #1
8007f60: d020 beq.n 8007fa4 <USB_ActivateEndpoint+0x1c4>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8007f62: 687a ldr r2, [r7, #4]
8007f64: 683b ldr r3, [r7, #0]
8007f66: 781b ldrb r3, [r3, #0]
8007f68: 009b lsls r3, r3, #2
8007f6a: 4413 add r3, r2
8007f6c: 881b ldrh r3, [r3, #0]
8007f6e: b29b uxth r3, r3
8007f70: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007f74: f023 0340 bic.w r3, r3, #64 @ 0x40
8007f78: 81bb strh r3, [r7, #12]
8007f7a: 89bb ldrh r3, [r7, #12]
8007f7c: f083 0320 eor.w r3, r3, #32
8007f80: 81bb strh r3, [r7, #12]
8007f82: 687a ldr r2, [r7, #4]
8007f84: 683b ldr r3, [r7, #0]
8007f86: 781b ldrb r3, [r3, #0]
8007f88: 009b lsls r3, r3, #2
8007f8a: 441a add r2, r3
8007f8c: 89bb ldrh r3, [r7, #12]
8007f8e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007f92: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007f96: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007f9a: f043 0380 orr.w r3, r3, #128 @ 0x80
8007f9e: b29b uxth r3, r3
8007fa0: 8013 strh r3, [r2, #0]
8007fa2: e2d5 b.n 8008550 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8007fa4: 687a ldr r2, [r7, #4]
8007fa6: 683b ldr r3, [r7, #0]
8007fa8: 781b ldrb r3, [r3, #0]
8007faa: 009b lsls r3, r3, #2
8007fac: 4413 add r3, r2
8007fae: 881b ldrh r3, [r3, #0]
8007fb0: b29b uxth r3, r3
8007fb2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8007fb6: f023 0340 bic.w r3, r3, #64 @ 0x40
8007fba: 81fb strh r3, [r7, #14]
8007fbc: 687a ldr r2, [r7, #4]
8007fbe: 683b ldr r3, [r7, #0]
8007fc0: 781b ldrb r3, [r3, #0]
8007fc2: 009b lsls r3, r3, #2
8007fc4: 441a add r2, r3
8007fc6: 89fb ldrh r3, [r7, #14]
8007fc8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8007fcc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8007fd0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8007fd4: f043 0380 orr.w r3, r3, #128 @ 0x80
8007fd8: b29b uxth r3, r3
8007fda: 8013 strh r3, [r2, #0]
8007fdc: e2b8 b.n 8008550 <USB_ActivateEndpoint+0x770>
}
}
else
{
/* Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
8007fde: 687b ldr r3, [r7, #4]
8007fe0: 633b str r3, [r7, #48] @ 0x30
8007fe2: 687b ldr r3, [r7, #4]
8007fe4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8007fe8: b29b uxth r3, r3
8007fea: 461a mov r2, r3
8007fec: 6b3b ldr r3, [r7, #48] @ 0x30
8007fee: 4413 add r3, r2
8007ff0: 633b str r3, [r7, #48] @ 0x30
8007ff2: 683b ldr r3, [r7, #0]
8007ff4: 781b ldrb r3, [r3, #0]
8007ff6: 011a lsls r2, r3, #4
8007ff8: 6b3b ldr r3, [r7, #48] @ 0x30
8007ffa: 4413 add r3, r2
8007ffc: f503 6381 add.w r3, r3, #1032 @ 0x408
8008000: 62fb str r3, [r7, #44] @ 0x2c
8008002: 683b ldr r3, [r7, #0]
8008004: 88db ldrh r3, [r3, #6]
8008006: 085b lsrs r3, r3, #1
8008008: b29b uxth r3, r3
800800a: 005b lsls r3, r3, #1
800800c: b29a uxth r2, r3
800800e: 6afb ldr r3, [r7, #44] @ 0x2c
8008010: 801a strh r2, [r3, #0]
/* Set the endpoint Receive buffer counter */
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
8008012: 687b ldr r3, [r7, #4]
8008014: 62bb str r3, [r7, #40] @ 0x28
8008016: 687b ldr r3, [r7, #4]
8008018: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800801c: b29b uxth r3, r3
800801e: 461a mov r2, r3
8008020: 6abb ldr r3, [r7, #40] @ 0x28
8008022: 4413 add r3, r2
8008024: 62bb str r3, [r7, #40] @ 0x28
8008026: 683b ldr r3, [r7, #0]
8008028: 781b ldrb r3, [r3, #0]
800802a: 011a lsls r2, r3, #4
800802c: 6abb ldr r3, [r7, #40] @ 0x28
800802e: 4413 add r3, r2
8008030: f203 430c addw r3, r3, #1036 @ 0x40c
8008034: 627b str r3, [r7, #36] @ 0x24
8008036: 6a7b ldr r3, [r7, #36] @ 0x24
8008038: 881b ldrh r3, [r3, #0]
800803a: b29b uxth r3, r3
800803c: f3c3 0309 ubfx r3, r3, #0, #10
8008040: b29a uxth r2, r3
8008042: 6a7b ldr r3, [r7, #36] @ 0x24
8008044: 801a strh r2, [r3, #0]
8008046: 683b ldr r3, [r7, #0]
8008048: 691b ldr r3, [r3, #16]
800804a: 2b3e cmp r3, #62 @ 0x3e
800804c: d91d bls.n 800808a <USB_ActivateEndpoint+0x2aa>
800804e: 683b ldr r3, [r7, #0]
8008050: 691b ldr r3, [r3, #16]
8008052: 095b lsrs r3, r3, #5
8008054: 66bb str r3, [r7, #104] @ 0x68
8008056: 683b ldr r3, [r7, #0]
8008058: 691b ldr r3, [r3, #16]
800805a: f003 031f and.w r3, r3, #31
800805e: 2b00 cmp r3, #0
8008060: d102 bne.n 8008068 <USB_ActivateEndpoint+0x288>
8008062: 6ebb ldr r3, [r7, #104] @ 0x68
8008064: 3b01 subs r3, #1
8008066: 66bb str r3, [r7, #104] @ 0x68
8008068: 6a7b ldr r3, [r7, #36] @ 0x24
800806a: 881b ldrh r3, [r3, #0]
800806c: b29a uxth r2, r3
800806e: 6ebb ldr r3, [r7, #104] @ 0x68
8008070: b29b uxth r3, r3
8008072: 029b lsls r3, r3, #10
8008074: b29b uxth r3, r3
8008076: 4313 orrs r3, r2
8008078: b29b uxth r3, r3
800807a: ea6f 4343 mvn.w r3, r3, lsl #17
800807e: ea6f 4353 mvn.w r3, r3, lsr #17
8008082: b29a uxth r2, r3
8008084: 6a7b ldr r3, [r7, #36] @ 0x24
8008086: 801a strh r2, [r3, #0]
8008088: e026 b.n 80080d8 <USB_ActivateEndpoint+0x2f8>
800808a: 683b ldr r3, [r7, #0]
800808c: 691b ldr r3, [r3, #16]
800808e: 2b00 cmp r3, #0
8008090: d10a bne.n 80080a8 <USB_ActivateEndpoint+0x2c8>
8008092: 6a7b ldr r3, [r7, #36] @ 0x24
8008094: 881b ldrh r3, [r3, #0]
8008096: b29b uxth r3, r3
8008098: ea6f 4343 mvn.w r3, r3, lsl #17
800809c: ea6f 4353 mvn.w r3, r3, lsr #17
80080a0: b29a uxth r2, r3
80080a2: 6a7b ldr r3, [r7, #36] @ 0x24
80080a4: 801a strh r2, [r3, #0]
80080a6: e017 b.n 80080d8 <USB_ActivateEndpoint+0x2f8>
80080a8: 683b ldr r3, [r7, #0]
80080aa: 691b ldr r3, [r3, #16]
80080ac: 085b lsrs r3, r3, #1
80080ae: 66bb str r3, [r7, #104] @ 0x68
80080b0: 683b ldr r3, [r7, #0]
80080b2: 691b ldr r3, [r3, #16]
80080b4: f003 0301 and.w r3, r3, #1
80080b8: 2b00 cmp r3, #0
80080ba: d002 beq.n 80080c2 <USB_ActivateEndpoint+0x2e2>
80080bc: 6ebb ldr r3, [r7, #104] @ 0x68
80080be: 3301 adds r3, #1
80080c0: 66bb str r3, [r7, #104] @ 0x68
80080c2: 6a7b ldr r3, [r7, #36] @ 0x24
80080c4: 881b ldrh r3, [r3, #0]
80080c6: b29a uxth r2, r3
80080c8: 6ebb ldr r3, [r7, #104] @ 0x68
80080ca: b29b uxth r3, r3
80080cc: 029b lsls r3, r3, #10
80080ce: b29b uxth r3, r3
80080d0: 4313 orrs r3, r2
80080d2: b29a uxth r2, r3
80080d4: 6a7b ldr r3, [r7, #36] @ 0x24
80080d6: 801a strh r2, [r3, #0]
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80080d8: 687a ldr r2, [r7, #4]
80080da: 683b ldr r3, [r7, #0]
80080dc: 781b ldrb r3, [r3, #0]
80080de: 009b lsls r3, r3, #2
80080e0: 4413 add r3, r2
80080e2: 881b ldrh r3, [r3, #0]
80080e4: 847b strh r3, [r7, #34] @ 0x22
80080e6: 8c7b ldrh r3, [r7, #34] @ 0x22
80080e8: f403 4380 and.w r3, r3, #16384 @ 0x4000
80080ec: 2b00 cmp r3, #0
80080ee: d01b beq.n 8008128 <USB_ActivateEndpoint+0x348>
80080f0: 687a ldr r2, [r7, #4]
80080f2: 683b ldr r3, [r7, #0]
80080f4: 781b ldrb r3, [r3, #0]
80080f6: 009b lsls r3, r3, #2
80080f8: 4413 add r3, r2
80080fa: 881b ldrh r3, [r3, #0]
80080fc: b29b uxth r3, r3
80080fe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008102: f023 0370 bic.w r3, r3, #112 @ 0x70
8008106: 843b strh r3, [r7, #32]
8008108: 687a ldr r2, [r7, #4]
800810a: 683b ldr r3, [r7, #0]
800810c: 781b ldrb r3, [r3, #0]
800810e: 009b lsls r3, r3, #2
8008110: 441a add r2, r3
8008112: 8c3b ldrh r3, [r7, #32]
8008114: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008118: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800811c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8008120: f043 0380 orr.w r3, r3, #128 @ 0x80
8008124: b29b uxth r3, r3
8008126: 8013 strh r3, [r2, #0]
if (ep->num == 0U)
8008128: 683b ldr r3, [r7, #0]
800812a: 781b ldrb r3, [r3, #0]
800812c: 2b00 cmp r3, #0
800812e: d124 bne.n 800817a <USB_ActivateEndpoint+0x39a>
{
/* Configure VALID status for EP0 */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8008130: 687a ldr r2, [r7, #4]
8008132: 683b ldr r3, [r7, #0]
8008134: 781b ldrb r3, [r3, #0]
8008136: 009b lsls r3, r3, #2
8008138: 4413 add r3, r2
800813a: 881b ldrh r3, [r3, #0]
800813c: b29b uxth r3, r3
800813e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008142: f023 0370 bic.w r3, r3, #112 @ 0x70
8008146: 83bb strh r3, [r7, #28]
8008148: 8bbb ldrh r3, [r7, #28]
800814a: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800814e: 83bb strh r3, [r7, #28]
8008150: 8bbb ldrh r3, [r7, #28]
8008152: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008156: 83bb strh r3, [r7, #28]
8008158: 687a ldr r2, [r7, #4]
800815a: 683b ldr r3, [r7, #0]
800815c: 781b ldrb r3, [r3, #0]
800815e: 009b lsls r3, r3, #2
8008160: 441a add r2, r3
8008162: 8bbb ldrh r3, [r7, #28]
8008164: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008168: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800816c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008170: f043 0380 orr.w r3, r3, #128 @ 0x80
8008174: b29b uxth r3, r3
8008176: 8013 strh r3, [r2, #0]
8008178: e1ea b.n 8008550 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure NAK status for OUT Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
800817a: 687a ldr r2, [r7, #4]
800817c: 683b ldr r3, [r7, #0]
800817e: 781b ldrb r3, [r3, #0]
8008180: 009b lsls r3, r3, #2
8008182: 4413 add r3, r2
8008184: 881b ldrh r3, [r3, #0]
8008186: b29b uxth r3, r3
8008188: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800818c: f023 0370 bic.w r3, r3, #112 @ 0x70
8008190: 83fb strh r3, [r7, #30]
8008192: 8bfb ldrh r3, [r7, #30]
8008194: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008198: 83fb strh r3, [r7, #30]
800819a: 687a ldr r2, [r7, #4]
800819c: 683b ldr r3, [r7, #0]
800819e: 781b ldrb r3, [r3, #0]
80081a0: 009b lsls r3, r3, #2
80081a2: 441a add r2, r3
80081a4: 8bfb ldrh r3, [r7, #30]
80081a6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80081aa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80081ae: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80081b2: f043 0380 orr.w r3, r3, #128 @ 0x80
80081b6: b29b uxth r3, r3
80081b8: 8013 strh r3, [r2, #0]
80081ba: e1c9 b.n 8008550 <USB_ActivateEndpoint+0x770>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->type == EP_TYPE_BULK)
80081bc: 683b ldr r3, [r7, #0]
80081be: 78db ldrb r3, [r3, #3]
80081c0: 2b02 cmp r3, #2
80081c2: d11e bne.n 8008202 <USB_ActivateEndpoint+0x422>
{
/* Set bulk endpoint as double buffered */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
80081c4: 687a ldr r2, [r7, #4]
80081c6: 683b ldr r3, [r7, #0]
80081c8: 781b ldrb r3, [r3, #0]
80081ca: 009b lsls r3, r3, #2
80081cc: 4413 add r3, r2
80081ce: 881b ldrh r3, [r3, #0]
80081d0: b29b uxth r3, r3
80081d2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80081d6: f023 0370 bic.w r3, r3, #112 @ 0x70
80081da: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
80081de: 687a ldr r2, [r7, #4]
80081e0: 683b ldr r3, [r7, #0]
80081e2: 781b ldrb r3, [r3, #0]
80081e4: 009b lsls r3, r3, #2
80081e6: 441a add r2, r3
80081e8: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
80081ec: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80081f0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80081f4: f443 4301 orr.w r3, r3, #33024 @ 0x8100
80081f8: f043 0380 orr.w r3, r3, #128 @ 0x80
80081fc: b29b uxth r3, r3
80081fe: 8013 strh r3, [r2, #0]
8008200: e01d b.n 800823e <USB_ActivateEndpoint+0x45e>
}
else
{
/* Set the ISOC endpoint in double buffer mode */
PCD_CLEAR_EP_KIND(USBx, ep->num);
8008202: 687a ldr r2, [r7, #4]
8008204: 683b ldr r3, [r7, #0]
8008206: 781b ldrb r3, [r3, #0]
8008208: 009b lsls r3, r3, #2
800820a: 4413 add r3, r2
800820c: 881b ldrh r3, [r3, #0]
800820e: b29b uxth r3, r3
8008210: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8008214: f023 0370 bic.w r3, r3, #112 @ 0x70
8008218: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
800821c: 687a ldr r2, [r7, #4]
800821e: 683b ldr r3, [r7, #0]
8008220: 781b ldrb r3, [r3, #0]
8008222: 009b lsls r3, r3, #2
8008224: 441a add r2, r3
8008226: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
800822a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800822e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008232: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008236: f043 0380 orr.w r3, r3, #128 @ 0x80
800823a: b29b uxth r3, r3
800823c: 8013 strh r3, [r2, #0]
}
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
800823e: 687b ldr r3, [r7, #4]
8008240: 65fb str r3, [r7, #92] @ 0x5c
8008242: 687b ldr r3, [r7, #4]
8008244: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008248: b29b uxth r3, r3
800824a: 461a mov r2, r3
800824c: 6dfb ldr r3, [r7, #92] @ 0x5c
800824e: 4413 add r3, r2
8008250: 65fb str r3, [r7, #92] @ 0x5c
8008252: 683b ldr r3, [r7, #0]
8008254: 781b ldrb r3, [r3, #0]
8008256: 011a lsls r2, r3, #4
8008258: 6dfb ldr r3, [r7, #92] @ 0x5c
800825a: 4413 add r3, r2
800825c: f503 6380 add.w r3, r3, #1024 @ 0x400
8008260: 65bb str r3, [r7, #88] @ 0x58
8008262: 683b ldr r3, [r7, #0]
8008264: 891b ldrh r3, [r3, #8]
8008266: 085b lsrs r3, r3, #1
8008268: b29b uxth r3, r3
800826a: 005b lsls r3, r3, #1
800826c: b29a uxth r2, r3
800826e: 6dbb ldr r3, [r7, #88] @ 0x58
8008270: 801a strh r2, [r3, #0]
8008272: 687b ldr r3, [r7, #4]
8008274: 657b str r3, [r7, #84] @ 0x54
8008276: 687b ldr r3, [r7, #4]
8008278: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800827c: b29b uxth r3, r3
800827e: 461a mov r2, r3
8008280: 6d7b ldr r3, [r7, #84] @ 0x54
8008282: 4413 add r3, r2
8008284: 657b str r3, [r7, #84] @ 0x54
8008286: 683b ldr r3, [r7, #0]
8008288: 781b ldrb r3, [r3, #0]
800828a: 011a lsls r2, r3, #4
800828c: 6d7b ldr r3, [r7, #84] @ 0x54
800828e: 4413 add r3, r2
8008290: f503 6381 add.w r3, r3, #1032 @ 0x408
8008294: 653b str r3, [r7, #80] @ 0x50
8008296: 683b ldr r3, [r7, #0]
8008298: 895b ldrh r3, [r3, #10]
800829a: 085b lsrs r3, r3, #1
800829c: b29b uxth r3, r3
800829e: 005b lsls r3, r3, #1
80082a0: b29a uxth r2, r3
80082a2: 6d3b ldr r3, [r7, #80] @ 0x50
80082a4: 801a strh r2, [r3, #0]
if (ep->is_in == 0U)
80082a6: 683b ldr r3, [r7, #0]
80082a8: 785b ldrb r3, [r3, #1]
80082aa: 2b00 cmp r3, #0
80082ac: f040 8093 bne.w 80083d6 <USB_ActivateEndpoint+0x5f6>
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80082b0: 687a ldr r2, [r7, #4]
80082b2: 683b ldr r3, [r7, #0]
80082b4: 781b ldrb r3, [r3, #0]
80082b6: 009b lsls r3, r3, #2
80082b8: 4413 add r3, r2
80082ba: 881b ldrh r3, [r3, #0]
80082bc: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
80082c0: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
80082c4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80082c8: 2b00 cmp r3, #0
80082ca: d01b beq.n 8008304 <USB_ActivateEndpoint+0x524>
80082cc: 687a ldr r2, [r7, #4]
80082ce: 683b ldr r3, [r7, #0]
80082d0: 781b ldrb r3, [r3, #0]
80082d2: 009b lsls r3, r3, #2
80082d4: 4413 add r3, r2
80082d6: 881b ldrh r3, [r3, #0]
80082d8: b29b uxth r3, r3
80082da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80082de: f023 0370 bic.w r3, r3, #112 @ 0x70
80082e2: 87fb strh r3, [r7, #62] @ 0x3e
80082e4: 687a ldr r2, [r7, #4]
80082e6: 683b ldr r3, [r7, #0]
80082e8: 781b ldrb r3, [r3, #0]
80082ea: 009b lsls r3, r3, #2
80082ec: 441a add r2, r3
80082ee: 8ffb ldrh r3, [r7, #62] @ 0x3e
80082f0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80082f4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80082f8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80082fc: f043 0380 orr.w r3, r3, #128 @ 0x80
8008300: b29b uxth r3, r3
8008302: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8008304: 687a ldr r2, [r7, #4]
8008306: 683b ldr r3, [r7, #0]
8008308: 781b ldrb r3, [r3, #0]
800830a: 009b lsls r3, r3, #2
800830c: 4413 add r3, r2
800830e: 881b ldrh r3, [r3, #0]
8008310: 87bb strh r3, [r7, #60] @ 0x3c
8008312: 8fbb ldrh r3, [r7, #60] @ 0x3c
8008314: f003 0340 and.w r3, r3, #64 @ 0x40
8008318: 2b00 cmp r3, #0
800831a: d01b beq.n 8008354 <USB_ActivateEndpoint+0x574>
800831c: 687a ldr r2, [r7, #4]
800831e: 683b ldr r3, [r7, #0]
8008320: 781b ldrb r3, [r3, #0]
8008322: 009b lsls r3, r3, #2
8008324: 4413 add r3, r2
8008326: 881b ldrh r3, [r3, #0]
8008328: b29b uxth r3, r3
800832a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800832e: f023 0370 bic.w r3, r3, #112 @ 0x70
8008332: 877b strh r3, [r7, #58] @ 0x3a
8008334: 687a ldr r2, [r7, #4]
8008336: 683b ldr r3, [r7, #0]
8008338: 781b ldrb r3, [r3, #0]
800833a: 009b lsls r3, r3, #2
800833c: 441a add r2, r3
800833e: 8f7b ldrh r3, [r7, #58] @ 0x3a
8008340: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008344: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008348: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800834c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008350: b29b uxth r3, r3
8008352: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8008354: 687a ldr r2, [r7, #4]
8008356: 683b ldr r3, [r7, #0]
8008358: 781b ldrb r3, [r3, #0]
800835a: 009b lsls r3, r3, #2
800835c: 4413 add r3, r2
800835e: 881b ldrh r3, [r3, #0]
8008360: b29b uxth r3, r3
8008362: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008366: f023 0370 bic.w r3, r3, #112 @ 0x70
800836a: 873b strh r3, [r7, #56] @ 0x38
800836c: 8f3b ldrh r3, [r7, #56] @ 0x38
800836e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8008372: 873b strh r3, [r7, #56] @ 0x38
8008374: 8f3b ldrh r3, [r7, #56] @ 0x38
8008376: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800837a: 873b strh r3, [r7, #56] @ 0x38
800837c: 687a ldr r2, [r7, #4]
800837e: 683b ldr r3, [r7, #0]
8008380: 781b ldrb r3, [r3, #0]
8008382: 009b lsls r3, r3, #2
8008384: 441a add r2, r3
8008386: 8f3b ldrh r3, [r7, #56] @ 0x38
8008388: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800838c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008390: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008394: f043 0380 orr.w r3, r3, #128 @ 0x80
8008398: b29b uxth r3, r3
800839a: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800839c: 687a ldr r2, [r7, #4]
800839e: 683b ldr r3, [r7, #0]
80083a0: 781b ldrb r3, [r3, #0]
80083a2: 009b lsls r3, r3, #2
80083a4: 4413 add r3, r2
80083a6: 881b ldrh r3, [r3, #0]
80083a8: b29b uxth r3, r3
80083aa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80083ae: f023 0340 bic.w r3, r3, #64 @ 0x40
80083b2: 86fb strh r3, [r7, #54] @ 0x36
80083b4: 687a ldr r2, [r7, #4]
80083b6: 683b ldr r3, [r7, #0]
80083b8: 781b ldrb r3, [r3, #0]
80083ba: 009b lsls r3, r3, #2
80083bc: 441a add r2, r3
80083be: 8efb ldrh r3, [r7, #54] @ 0x36
80083c0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80083c4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80083c8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80083cc: f043 0380 orr.w r3, r3, #128 @ 0x80
80083d0: b29b uxth r3, r3
80083d2: 8013 strh r3, [r2, #0]
80083d4: e0bc b.n 8008550 <USB_ActivateEndpoint+0x770>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80083d6: 687a ldr r2, [r7, #4]
80083d8: 683b ldr r3, [r7, #0]
80083da: 781b ldrb r3, [r3, #0]
80083dc: 009b lsls r3, r3, #2
80083de: 4413 add r3, r2
80083e0: 881b ldrh r3, [r3, #0]
80083e2: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
80083e6: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80083ea: f403 4380 and.w r3, r3, #16384 @ 0x4000
80083ee: 2b00 cmp r3, #0
80083f0: d01d beq.n 800842e <USB_ActivateEndpoint+0x64e>
80083f2: 687a ldr r2, [r7, #4]
80083f4: 683b ldr r3, [r7, #0]
80083f6: 781b ldrb r3, [r3, #0]
80083f8: 009b lsls r3, r3, #2
80083fa: 4413 add r3, r2
80083fc: 881b ldrh r3, [r3, #0]
80083fe: b29b uxth r3, r3
8008400: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008404: f023 0370 bic.w r3, r3, #112 @ 0x70
8008408: f8a7 304c strh.w r3, [r7, #76] @ 0x4c
800840c: 687a ldr r2, [r7, #4]
800840e: 683b ldr r3, [r7, #0]
8008410: 781b ldrb r3, [r3, #0]
8008412: 009b lsls r3, r3, #2
8008414: 441a add r2, r3
8008416: f8b7 304c ldrh.w r3, [r7, #76] @ 0x4c
800841a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800841e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008422: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8008426: f043 0380 orr.w r3, r3, #128 @ 0x80
800842a: b29b uxth r3, r3
800842c: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800842e: 687a ldr r2, [r7, #4]
8008430: 683b ldr r3, [r7, #0]
8008432: 781b ldrb r3, [r3, #0]
8008434: 009b lsls r3, r3, #2
8008436: 4413 add r3, r2
8008438: 881b ldrh r3, [r3, #0]
800843a: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
800843e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8008442: f003 0340 and.w r3, r3, #64 @ 0x40
8008446: 2b00 cmp r3, #0
8008448: d01d beq.n 8008486 <USB_ActivateEndpoint+0x6a6>
800844a: 687a ldr r2, [r7, #4]
800844c: 683b ldr r3, [r7, #0]
800844e: 781b ldrb r3, [r3, #0]
8008450: 009b lsls r3, r3, #2
8008452: 4413 add r3, r2
8008454: 881b ldrh r3, [r3, #0]
8008456: b29b uxth r3, r3
8008458: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800845c: f023 0370 bic.w r3, r3, #112 @ 0x70
8008460: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
8008464: 687a ldr r2, [r7, #4]
8008466: 683b ldr r3, [r7, #0]
8008468: 781b ldrb r3, [r3, #0]
800846a: 009b lsls r3, r3, #2
800846c: 441a add r2, r3
800846e: f8b7 3048 ldrh.w r3, [r7, #72] @ 0x48
8008472: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008476: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800847a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800847e: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008482: b29b uxth r3, r3
8008484: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8008486: 683b ldr r3, [r7, #0]
8008488: 78db ldrb r3, [r3, #3]
800848a: 2b01 cmp r3, #1
800848c: d024 beq.n 80084d8 <USB_ActivateEndpoint+0x6f8>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
800848e: 687a ldr r2, [r7, #4]
8008490: 683b ldr r3, [r7, #0]
8008492: 781b ldrb r3, [r3, #0]
8008494: 009b lsls r3, r3, #2
8008496: 4413 add r3, r2
8008498: 881b ldrh r3, [r3, #0]
800849a: b29b uxth r3, r3
800849c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80084a0: f023 0340 bic.w r3, r3, #64 @ 0x40
80084a4: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
80084a8: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
80084ac: f083 0320 eor.w r3, r3, #32
80084b0: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
80084b4: 687a ldr r2, [r7, #4]
80084b6: 683b ldr r3, [r7, #0]
80084b8: 781b ldrb r3, [r3, #0]
80084ba: 009b lsls r3, r3, #2
80084bc: 441a add r2, r3
80084be: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
80084c2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80084c6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80084ca: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80084ce: f043 0380 orr.w r3, r3, #128 @ 0x80
80084d2: b29b uxth r3, r3
80084d4: 8013 strh r3, [r2, #0]
80084d6: e01d b.n 8008514 <USB_ActivateEndpoint+0x734>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80084d8: 687a ldr r2, [r7, #4]
80084da: 683b ldr r3, [r7, #0]
80084dc: 781b ldrb r3, [r3, #0]
80084de: 009b lsls r3, r3, #2
80084e0: 4413 add r3, r2
80084e2: 881b ldrh r3, [r3, #0]
80084e4: b29b uxth r3, r3
80084e6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80084ea: f023 0340 bic.w r3, r3, #64 @ 0x40
80084ee: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
80084f2: 687a ldr r2, [r7, #4]
80084f4: 683b ldr r3, [r7, #0]
80084f6: 781b ldrb r3, [r3, #0]
80084f8: 009b lsls r3, r3, #2
80084fa: 441a add r2, r3
80084fc: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46
8008500: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008504: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008508: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800850c: f043 0380 orr.w r3, r3, #128 @ 0x80
8008510: b29b uxth r3, r3
8008512: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8008514: 687a ldr r2, [r7, #4]
8008516: 683b ldr r3, [r7, #0]
8008518: 781b ldrb r3, [r3, #0]
800851a: 009b lsls r3, r3, #2
800851c: 4413 add r3, r2
800851e: 881b ldrh r3, [r3, #0]
8008520: b29b uxth r3, r3
8008522: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008526: f023 0370 bic.w r3, r3, #112 @ 0x70
800852a: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
800852e: 687a ldr r2, [r7, #4]
8008530: 683b ldr r3, [r7, #0]
8008532: 781b ldrb r3, [r3, #0]
8008534: 009b lsls r3, r3, #2
8008536: 441a add r2, r3
8008538: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
800853c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008540: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008544: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008548: f043 0380 orr.w r3, r3, #128 @ 0x80
800854c: b29b uxth r3, r3
800854e: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
8008550: f897 306f ldrb.w r3, [r7, #111] @ 0x6f
}
8008554: 4618 mov r0, r3
8008556: 3774 adds r7, #116 @ 0x74
8008558: 46bd mov sp, r7
800855a: bc80 pop {r7}
800855c: 4770 bx lr
800855e: bf00 nop
08008560 <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8008560: b480 push {r7}
8008562: b08d sub sp, #52 @ 0x34
8008564: af00 add r7, sp, #0
8008566: 6078 str r0, [r7, #4]
8008568: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
800856a: 683b ldr r3, [r7, #0]
800856c: 7b1b ldrb r3, [r3, #12]
800856e: 2b00 cmp r3, #0
8008570: f040 808e bne.w 8008690 <USB_DeactivateEndpoint+0x130>
{
if (ep->is_in != 0U)
8008574: 683b ldr r3, [r7, #0]
8008576: 785b ldrb r3, [r3, #1]
8008578: 2b00 cmp r3, #0
800857a: d044 beq.n 8008606 <USB_DeactivateEndpoint+0xa6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800857c: 687a ldr r2, [r7, #4]
800857e: 683b ldr r3, [r7, #0]
8008580: 781b ldrb r3, [r3, #0]
8008582: 009b lsls r3, r3, #2
8008584: 4413 add r3, r2
8008586: 881b ldrh r3, [r3, #0]
8008588: 81bb strh r3, [r7, #12]
800858a: 89bb ldrh r3, [r7, #12]
800858c: f003 0340 and.w r3, r3, #64 @ 0x40
8008590: 2b00 cmp r3, #0
8008592: d01b beq.n 80085cc <USB_DeactivateEndpoint+0x6c>
8008594: 687a ldr r2, [r7, #4]
8008596: 683b ldr r3, [r7, #0]
8008598: 781b ldrb r3, [r3, #0]
800859a: 009b lsls r3, r3, #2
800859c: 4413 add r3, r2
800859e: 881b ldrh r3, [r3, #0]
80085a0: b29b uxth r3, r3
80085a2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80085a6: f023 0370 bic.w r3, r3, #112 @ 0x70
80085aa: 817b strh r3, [r7, #10]
80085ac: 687a ldr r2, [r7, #4]
80085ae: 683b ldr r3, [r7, #0]
80085b0: 781b ldrb r3, [r3, #0]
80085b2: 009b lsls r3, r3, #2
80085b4: 441a add r2, r3
80085b6: 897b ldrh r3, [r7, #10]
80085b8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80085bc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80085c0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80085c4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80085c8: b29b uxth r3, r3
80085ca: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80085cc: 687a ldr r2, [r7, #4]
80085ce: 683b ldr r3, [r7, #0]
80085d0: 781b ldrb r3, [r3, #0]
80085d2: 009b lsls r3, r3, #2
80085d4: 4413 add r3, r2
80085d6: 881b ldrh r3, [r3, #0]
80085d8: b29b uxth r3, r3
80085da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80085de: f023 0340 bic.w r3, r3, #64 @ 0x40
80085e2: 813b strh r3, [r7, #8]
80085e4: 687a ldr r2, [r7, #4]
80085e6: 683b ldr r3, [r7, #0]
80085e8: 781b ldrb r3, [r3, #0]
80085ea: 009b lsls r3, r3, #2
80085ec: 441a add r2, r3
80085ee: 893b ldrh r3, [r7, #8]
80085f0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80085f4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80085f8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80085fc: f043 0380 orr.w r3, r3, #128 @ 0x80
8008600: b29b uxth r3, r3
8008602: 8013 strh r3, [r2, #0]
8008604: e192 b.n 800892c <USB_DeactivateEndpoint+0x3cc>
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8008606: 687a ldr r2, [r7, #4]
8008608: 683b ldr r3, [r7, #0]
800860a: 781b ldrb r3, [r3, #0]
800860c: 009b lsls r3, r3, #2
800860e: 4413 add r3, r2
8008610: 881b ldrh r3, [r3, #0]
8008612: 827b strh r3, [r7, #18]
8008614: 8a7b ldrh r3, [r7, #18]
8008616: f403 4380 and.w r3, r3, #16384 @ 0x4000
800861a: 2b00 cmp r3, #0
800861c: d01b beq.n 8008656 <USB_DeactivateEndpoint+0xf6>
800861e: 687a ldr r2, [r7, #4]
8008620: 683b ldr r3, [r7, #0]
8008622: 781b ldrb r3, [r3, #0]
8008624: 009b lsls r3, r3, #2
8008626: 4413 add r3, r2
8008628: 881b ldrh r3, [r3, #0]
800862a: b29b uxth r3, r3
800862c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008630: f023 0370 bic.w r3, r3, #112 @ 0x70
8008634: 823b strh r3, [r7, #16]
8008636: 687a ldr r2, [r7, #4]
8008638: 683b ldr r3, [r7, #0]
800863a: 781b ldrb r3, [r3, #0]
800863c: 009b lsls r3, r3, #2
800863e: 441a add r2, r3
8008640: 8a3b ldrh r3, [r7, #16]
8008642: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008646: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800864a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800864e: f043 0380 orr.w r3, r3, #128 @ 0x80
8008652: b29b uxth r3, r3
8008654: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8008656: 687a ldr r2, [r7, #4]
8008658: 683b ldr r3, [r7, #0]
800865a: 781b ldrb r3, [r3, #0]
800865c: 009b lsls r3, r3, #2
800865e: 4413 add r3, r2
8008660: 881b ldrh r3, [r3, #0]
8008662: b29b uxth r3, r3
8008664: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008668: f023 0370 bic.w r3, r3, #112 @ 0x70
800866c: 81fb strh r3, [r7, #14]
800866e: 687a ldr r2, [r7, #4]
8008670: 683b ldr r3, [r7, #0]
8008672: 781b ldrb r3, [r3, #0]
8008674: 009b lsls r3, r3, #2
8008676: 441a add r2, r3
8008678: 89fb ldrh r3, [r7, #14]
800867a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800867e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008682: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008686: f043 0380 orr.w r3, r3, #128 @ 0x80
800868a: b29b uxth r3, r3
800868c: 8013 strh r3, [r2, #0]
800868e: e14d b.n 800892c <USB_DeactivateEndpoint+0x3cc>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->is_in == 0U)
8008690: 683b ldr r3, [r7, #0]
8008692: 785b ldrb r3, [r3, #1]
8008694: 2b00 cmp r3, #0
8008696: f040 80a5 bne.w 80087e4 <USB_DeactivateEndpoint+0x284>
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800869a: 687a ldr r2, [r7, #4]
800869c: 683b ldr r3, [r7, #0]
800869e: 781b ldrb r3, [r3, #0]
80086a0: 009b lsls r3, r3, #2
80086a2: 4413 add r3, r2
80086a4: 881b ldrh r3, [r3, #0]
80086a6: 843b strh r3, [r7, #32]
80086a8: 8c3b ldrh r3, [r7, #32]
80086aa: f403 4380 and.w r3, r3, #16384 @ 0x4000
80086ae: 2b00 cmp r3, #0
80086b0: d01b beq.n 80086ea <USB_DeactivateEndpoint+0x18a>
80086b2: 687a ldr r2, [r7, #4]
80086b4: 683b ldr r3, [r7, #0]
80086b6: 781b ldrb r3, [r3, #0]
80086b8: 009b lsls r3, r3, #2
80086ba: 4413 add r3, r2
80086bc: 881b ldrh r3, [r3, #0]
80086be: b29b uxth r3, r3
80086c0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80086c4: f023 0370 bic.w r3, r3, #112 @ 0x70
80086c8: 83fb strh r3, [r7, #30]
80086ca: 687a ldr r2, [r7, #4]
80086cc: 683b ldr r3, [r7, #0]
80086ce: 781b ldrb r3, [r3, #0]
80086d0: 009b lsls r3, r3, #2
80086d2: 441a add r2, r3
80086d4: 8bfb ldrh r3, [r7, #30]
80086d6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80086da: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80086de: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80086e2: f043 0380 orr.w r3, r3, #128 @ 0x80
80086e6: b29b uxth r3, r3
80086e8: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80086ea: 687a ldr r2, [r7, #4]
80086ec: 683b ldr r3, [r7, #0]
80086ee: 781b ldrb r3, [r3, #0]
80086f0: 009b lsls r3, r3, #2
80086f2: 4413 add r3, r2
80086f4: 881b ldrh r3, [r3, #0]
80086f6: 83bb strh r3, [r7, #28]
80086f8: 8bbb ldrh r3, [r7, #28]
80086fa: f003 0340 and.w r3, r3, #64 @ 0x40
80086fe: 2b00 cmp r3, #0
8008700: d01b beq.n 800873a <USB_DeactivateEndpoint+0x1da>
8008702: 687a ldr r2, [r7, #4]
8008704: 683b ldr r3, [r7, #0]
8008706: 781b ldrb r3, [r3, #0]
8008708: 009b lsls r3, r3, #2
800870a: 4413 add r3, r2
800870c: 881b ldrh r3, [r3, #0]
800870e: b29b uxth r3, r3
8008710: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008714: f023 0370 bic.w r3, r3, #112 @ 0x70
8008718: 837b strh r3, [r7, #26]
800871a: 687a ldr r2, [r7, #4]
800871c: 683b ldr r3, [r7, #0]
800871e: 781b ldrb r3, [r3, #0]
8008720: 009b lsls r3, r3, #2
8008722: 441a add r2, r3
8008724: 8b7b ldrh r3, [r7, #26]
8008726: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800872a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800872e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008732: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008736: b29b uxth r3, r3
8008738: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
800873a: 687a ldr r2, [r7, #4]
800873c: 683b ldr r3, [r7, #0]
800873e: 781b ldrb r3, [r3, #0]
8008740: 009b lsls r3, r3, #2
8008742: 4413 add r3, r2
8008744: 881b ldrh r3, [r3, #0]
8008746: b29b uxth r3, r3
8008748: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800874c: f023 0370 bic.w r3, r3, #112 @ 0x70
8008750: 833b strh r3, [r7, #24]
8008752: 687a ldr r2, [r7, #4]
8008754: 683b ldr r3, [r7, #0]
8008756: 781b ldrb r3, [r3, #0]
8008758: 009b lsls r3, r3, #2
800875a: 441a add r2, r3
800875c: 8b3b ldrh r3, [r7, #24]
800875e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008762: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008766: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800876a: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800876e: b29b uxth r3, r3
8008770: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8008772: 687a ldr r2, [r7, #4]
8008774: 683b ldr r3, [r7, #0]
8008776: 781b ldrb r3, [r3, #0]
8008778: 009b lsls r3, r3, #2
800877a: 4413 add r3, r2
800877c: 881b ldrh r3, [r3, #0]
800877e: b29b uxth r3, r3
8008780: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008784: f023 0370 bic.w r3, r3, #112 @ 0x70
8008788: 82fb strh r3, [r7, #22]
800878a: 687a ldr r2, [r7, #4]
800878c: 683b ldr r3, [r7, #0]
800878e: 781b ldrb r3, [r3, #0]
8008790: 009b lsls r3, r3, #2
8008792: 441a add r2, r3
8008794: 8afb ldrh r3, [r7, #22]
8008796: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800879a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800879e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80087a2: f043 0380 orr.w r3, r3, #128 @ 0x80
80087a6: b29b uxth r3, r3
80087a8: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80087aa: 687a ldr r2, [r7, #4]
80087ac: 683b ldr r3, [r7, #0]
80087ae: 781b ldrb r3, [r3, #0]
80087b0: 009b lsls r3, r3, #2
80087b2: 4413 add r3, r2
80087b4: 881b ldrh r3, [r3, #0]
80087b6: b29b uxth r3, r3
80087b8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80087bc: f023 0340 bic.w r3, r3, #64 @ 0x40
80087c0: 82bb strh r3, [r7, #20]
80087c2: 687a ldr r2, [r7, #4]
80087c4: 683b ldr r3, [r7, #0]
80087c6: 781b ldrb r3, [r3, #0]
80087c8: 009b lsls r3, r3, #2
80087ca: 441a add r2, r3
80087cc: 8abb ldrh r3, [r7, #20]
80087ce: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80087d2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80087d6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80087da: f043 0380 orr.w r3, r3, #128 @ 0x80
80087de: b29b uxth r3, r3
80087e0: 8013 strh r3, [r2, #0]
80087e2: e0a3 b.n 800892c <USB_DeactivateEndpoint+0x3cc>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80087e4: 687a ldr r2, [r7, #4]
80087e6: 683b ldr r3, [r7, #0]
80087e8: 781b ldrb r3, [r3, #0]
80087ea: 009b lsls r3, r3, #2
80087ec: 4413 add r3, r2
80087ee: 881b ldrh r3, [r3, #0]
80087f0: 85fb strh r3, [r7, #46] @ 0x2e
80087f2: 8dfb ldrh r3, [r7, #46] @ 0x2e
80087f4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80087f8: 2b00 cmp r3, #0
80087fa: d01b beq.n 8008834 <USB_DeactivateEndpoint+0x2d4>
80087fc: 687a ldr r2, [r7, #4]
80087fe: 683b ldr r3, [r7, #0]
8008800: 781b ldrb r3, [r3, #0]
8008802: 009b lsls r3, r3, #2
8008804: 4413 add r3, r2
8008806: 881b ldrh r3, [r3, #0]
8008808: b29b uxth r3, r3
800880a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800880e: f023 0370 bic.w r3, r3, #112 @ 0x70
8008812: 85bb strh r3, [r7, #44] @ 0x2c
8008814: 687a ldr r2, [r7, #4]
8008816: 683b ldr r3, [r7, #0]
8008818: 781b ldrb r3, [r3, #0]
800881a: 009b lsls r3, r3, #2
800881c: 441a add r2, r3
800881e: 8dbb ldrh r3, [r7, #44] @ 0x2c
8008820: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008824: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008828: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800882c: f043 0380 orr.w r3, r3, #128 @ 0x80
8008830: b29b uxth r3, r3
8008832: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8008834: 687a ldr r2, [r7, #4]
8008836: 683b ldr r3, [r7, #0]
8008838: 781b ldrb r3, [r3, #0]
800883a: 009b lsls r3, r3, #2
800883c: 4413 add r3, r2
800883e: 881b ldrh r3, [r3, #0]
8008840: 857b strh r3, [r7, #42] @ 0x2a
8008842: 8d7b ldrh r3, [r7, #42] @ 0x2a
8008844: f003 0340 and.w r3, r3, #64 @ 0x40
8008848: 2b00 cmp r3, #0
800884a: d01b beq.n 8008884 <USB_DeactivateEndpoint+0x324>
800884c: 687a ldr r2, [r7, #4]
800884e: 683b ldr r3, [r7, #0]
8008850: 781b ldrb r3, [r3, #0]
8008852: 009b lsls r3, r3, #2
8008854: 4413 add r3, r2
8008856: 881b ldrh r3, [r3, #0]
8008858: b29b uxth r3, r3
800885a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800885e: f023 0370 bic.w r3, r3, #112 @ 0x70
8008862: 853b strh r3, [r7, #40] @ 0x28
8008864: 687a ldr r2, [r7, #4]
8008866: 683b ldr r3, [r7, #0]
8008868: 781b ldrb r3, [r3, #0]
800886a: 009b lsls r3, r3, #2
800886c: 441a add r2, r3
800886e: 8d3b ldrh r3, [r7, #40] @ 0x28
8008870: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008874: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008878: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800887c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008880: b29b uxth r3, r3
8008882: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
8008884: 687a ldr r2, [r7, #4]
8008886: 683b ldr r3, [r7, #0]
8008888: 781b ldrb r3, [r3, #0]
800888a: 009b lsls r3, r3, #2
800888c: 4413 add r3, r2
800888e: 881b ldrh r3, [r3, #0]
8008890: b29b uxth r3, r3
8008892: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008896: f023 0370 bic.w r3, r3, #112 @ 0x70
800889a: 84fb strh r3, [r7, #38] @ 0x26
800889c: 687a ldr r2, [r7, #4]
800889e: 683b ldr r3, [r7, #0]
80088a0: 781b ldrb r3, [r3, #0]
80088a2: 009b lsls r3, r3, #2
80088a4: 441a add r2, r3
80088a6: 8cfb ldrh r3, [r7, #38] @ 0x26
80088a8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80088ac: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80088b0: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80088b4: f043 0380 orr.w r3, r3, #128 @ 0x80
80088b8: b29b uxth r3, r3
80088ba: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80088bc: 687a ldr r2, [r7, #4]
80088be: 683b ldr r3, [r7, #0]
80088c0: 781b ldrb r3, [r3, #0]
80088c2: 009b lsls r3, r3, #2
80088c4: 4413 add r3, r2
80088c6: 881b ldrh r3, [r3, #0]
80088c8: b29b uxth r3, r3
80088ca: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80088ce: f023 0340 bic.w r3, r3, #64 @ 0x40
80088d2: 84bb strh r3, [r7, #36] @ 0x24
80088d4: 687a ldr r2, [r7, #4]
80088d6: 683b ldr r3, [r7, #0]
80088d8: 781b ldrb r3, [r3, #0]
80088da: 009b lsls r3, r3, #2
80088dc: 441a add r2, r3
80088de: 8cbb ldrh r3, [r7, #36] @ 0x24
80088e0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80088e4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80088e8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80088ec: f043 0380 orr.w r3, r3, #128 @ 0x80
80088f0: b29b uxth r3, r3
80088f2: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80088f4: 687a ldr r2, [r7, #4]
80088f6: 683b ldr r3, [r7, #0]
80088f8: 781b ldrb r3, [r3, #0]
80088fa: 009b lsls r3, r3, #2
80088fc: 4413 add r3, r2
80088fe: 881b ldrh r3, [r3, #0]
8008900: b29b uxth r3, r3
8008902: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008906: f023 0370 bic.w r3, r3, #112 @ 0x70
800890a: 847b strh r3, [r7, #34] @ 0x22
800890c: 687a ldr r2, [r7, #4]
800890e: 683b ldr r3, [r7, #0]
8008910: 781b ldrb r3, [r3, #0]
8008912: 009b lsls r3, r3, #2
8008914: 441a add r2, r3
8008916: 8c7b ldrh r3, [r7, #34] @ 0x22
8008918: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800891c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008920: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008924: f043 0380 orr.w r3, r3, #128 @ 0x80
8008928: b29b uxth r3, r3
800892a: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
800892c: 2300 movs r3, #0
}
800892e: 4618 mov r0, r3
8008930: 3734 adds r7, #52 @ 0x34
8008932: 46bd mov sp, r7
8008934: bc80 pop {r7}
8008936: 4770 bx lr
08008938 <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8008938: b580 push {r7, lr}
800893a: b0c2 sub sp, #264 @ 0x108
800893c: af00 add r7, sp, #0
800893e: f507 7384 add.w r3, r7, #264 @ 0x108
8008942: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008946: 6018 str r0, [r3, #0]
8008948: f507 7384 add.w r3, r7, #264 @ 0x108
800894c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008950: 6019 str r1, [r3, #0]
uint16_t pmabuffer;
uint16_t wEPVal;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
8008952: f507 7384 add.w r3, r7, #264 @ 0x108
8008956: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800895a: 681b ldr r3, [r3, #0]
800895c: 785b ldrb r3, [r3, #1]
800895e: 2b01 cmp r3, #1
8008960: f040 86b7 bne.w 80096d2 <USB_EPStartXfer+0xd9a>
{
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
8008964: f507 7384 add.w r3, r7, #264 @ 0x108
8008968: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800896c: 681b ldr r3, [r3, #0]
800896e: 699a ldr r2, [r3, #24]
8008970: f507 7384 add.w r3, r7, #264 @ 0x108
8008974: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008978: 681b ldr r3, [r3, #0]
800897a: 691b ldr r3, [r3, #16]
800897c: 429a cmp r2, r3
800897e: d908 bls.n 8008992 <USB_EPStartXfer+0x5a>
{
len = ep->maxpacket;
8008980: f507 7384 add.w r3, r7, #264 @ 0x108
8008984: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008988: 681b ldr r3, [r3, #0]
800898a: 691b ldr r3, [r3, #16]
800898c: f8c7 3104 str.w r3, [r7, #260] @ 0x104
8008990: e007 b.n 80089a2 <USB_EPStartXfer+0x6a>
}
else
{
len = ep->xfer_len;
8008992: f507 7384 add.w r3, r7, #264 @ 0x108
8008996: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800899a: 681b ldr r3, [r3, #0]
800899c: 699b ldr r3, [r3, #24]
800899e: f8c7 3104 str.w r3, [r7, #260] @ 0x104
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
80089a2: f507 7384 add.w r3, r7, #264 @ 0x108
80089a6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089aa: 681b ldr r3, [r3, #0]
80089ac: 7b1b ldrb r3, [r3, #12]
80089ae: 2b00 cmp r3, #0
80089b0: d13a bne.n 8008a28 <USB_EPStartXfer+0xf0>
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
80089b2: f507 7384 add.w r3, r7, #264 @ 0x108
80089b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089ba: 681b ldr r3, [r3, #0]
80089bc: 6959 ldr r1, [r3, #20]
80089be: f507 7384 add.w r3, r7, #264 @ 0x108
80089c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80089c6: 681b ldr r3, [r3, #0]
80089c8: 88da ldrh r2, [r3, #6]
80089ca: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80089ce: b29b uxth r3, r3
80089d0: f507 7084 add.w r0, r7, #264 @ 0x108
80089d4: f5a0 7082 sub.w r0, r0, #260 @ 0x104
80089d8: 6800 ldr r0, [r0, #0]
80089da: f001 fc9c bl 800a316 <USB_WritePMA>
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
80089de: f507 7384 add.w r3, r7, #264 @ 0x108
80089e2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80089e6: 681b ldr r3, [r3, #0]
80089e8: 613b str r3, [r7, #16]
80089ea: f507 7384 add.w r3, r7, #264 @ 0x108
80089ee: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80089f2: 681b ldr r3, [r3, #0]
80089f4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80089f8: b29b uxth r3, r3
80089fa: 461a mov r2, r3
80089fc: 693b ldr r3, [r7, #16]
80089fe: 4413 add r3, r2
8008a00: 613b str r3, [r7, #16]
8008a02: f507 7384 add.w r3, r7, #264 @ 0x108
8008a06: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a0a: 681b ldr r3, [r3, #0]
8008a0c: 781b ldrb r3, [r3, #0]
8008a0e: 011a lsls r2, r3, #4
8008a10: 693b ldr r3, [r7, #16]
8008a12: 4413 add r3, r2
8008a14: f203 4304 addw r3, r3, #1028 @ 0x404
8008a18: 60fb str r3, [r7, #12]
8008a1a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008a1e: b29a uxth r2, r3
8008a20: 68fb ldr r3, [r7, #12]
8008a22: 801a strh r2, [r3, #0]
8008a24: f000 be1f b.w 8009666 <USB_EPStartXfer+0xd2e>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
8008a28: f507 7384 add.w r3, r7, #264 @ 0x108
8008a2c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a30: 681b ldr r3, [r3, #0]
8008a32: 78db ldrb r3, [r3, #3]
8008a34: 2b02 cmp r3, #2
8008a36: f040 8462 bne.w 80092fe <USB_EPStartXfer+0x9c6>
{
if (ep->xfer_len_db > ep->maxpacket)
8008a3a: f507 7384 add.w r3, r7, #264 @ 0x108
8008a3e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a42: 681b ldr r3, [r3, #0]
8008a44: 6a1a ldr r2, [r3, #32]
8008a46: f507 7384 add.w r3, r7, #264 @ 0x108
8008a4a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a4e: 681b ldr r3, [r3, #0]
8008a50: 691b ldr r3, [r3, #16]
8008a52: 429a cmp r2, r3
8008a54: f240 83df bls.w 8009216 <USB_EPStartXfer+0x8de>
{
/* enable double buffer */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
8008a58: f507 7384 add.w r3, r7, #264 @ 0x108
8008a5c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008a60: 681a ldr r2, [r3, #0]
8008a62: f507 7384 add.w r3, r7, #264 @ 0x108
8008a66: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a6a: 681b ldr r3, [r3, #0]
8008a6c: 781b ldrb r3, [r3, #0]
8008a6e: 009b lsls r3, r3, #2
8008a70: 4413 add r3, r2
8008a72: 881b ldrh r3, [r3, #0]
8008a74: b29b uxth r3, r3
8008a76: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008a7a: f023 0370 bic.w r3, r3, #112 @ 0x70
8008a7e: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
8008a82: f507 7384 add.w r3, r7, #264 @ 0x108
8008a86: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008a8a: 681a ldr r2, [r3, #0]
8008a8c: f507 7384 add.w r3, r7, #264 @ 0x108
8008a90: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008a94: 681b ldr r3, [r3, #0]
8008a96: 781b ldrb r3, [r3, #0]
8008a98: 009b lsls r3, r3, #2
8008a9a: 441a add r2, r3
8008a9c: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
8008aa0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008aa4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008aa8: f443 4301 orr.w r3, r3, #33024 @ 0x8100
8008aac: f043 0380 orr.w r3, r3, #128 @ 0x80
8008ab0: b29b uxth r3, r3
8008ab2: 8013 strh r3, [r2, #0]
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
8008ab4: f507 7384 add.w r3, r7, #264 @ 0x108
8008ab8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008abc: 681b ldr r3, [r3, #0]
8008abe: 6a1a ldr r2, [r3, #32]
8008ac0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008ac4: 1ad2 subs r2, r2, r3
8008ac6: f507 7384 add.w r3, r7, #264 @ 0x108
8008aca: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ace: 681b ldr r3, [r3, #0]
8008ad0: 621a str r2, [r3, #32]
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8008ad2: f507 7384 add.w r3, r7, #264 @ 0x108
8008ad6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008ada: 681a ldr r2, [r3, #0]
8008adc: f507 7384 add.w r3, r7, #264 @ 0x108
8008ae0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ae4: 681b ldr r3, [r3, #0]
8008ae6: 781b ldrb r3, [r3, #0]
8008ae8: 009b lsls r3, r3, #2
8008aea: 4413 add r3, r2
8008aec: 881b ldrh r3, [r3, #0]
8008aee: b29b uxth r3, r3
8008af0: f003 0340 and.w r3, r3, #64 @ 0x40
8008af4: 2b00 cmp r3, #0
8008af6: f000 81c7 beq.w 8008e88 <USB_EPStartXfer+0x550>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8008afa: f507 7384 add.w r3, r7, #264 @ 0x108
8008afe: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b02: 681b ldr r3, [r3, #0]
8008b04: 633b str r3, [r7, #48] @ 0x30
8008b06: f507 7384 add.w r3, r7, #264 @ 0x108
8008b0a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b0e: 681b ldr r3, [r3, #0]
8008b10: 785b ldrb r3, [r3, #1]
8008b12: 2b00 cmp r3, #0
8008b14: d177 bne.n 8008c06 <USB_EPStartXfer+0x2ce>
8008b16: f507 7384 add.w r3, r7, #264 @ 0x108
8008b1a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b1e: 681b ldr r3, [r3, #0]
8008b20: 62bb str r3, [r7, #40] @ 0x28
8008b22: f507 7384 add.w r3, r7, #264 @ 0x108
8008b26: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008b2a: 681b ldr r3, [r3, #0]
8008b2c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008b30: b29b uxth r3, r3
8008b32: 461a mov r2, r3
8008b34: 6abb ldr r3, [r7, #40] @ 0x28
8008b36: 4413 add r3, r2
8008b38: 62bb str r3, [r7, #40] @ 0x28
8008b3a: f507 7384 add.w r3, r7, #264 @ 0x108
8008b3e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008b42: 681b ldr r3, [r3, #0]
8008b44: 781b ldrb r3, [r3, #0]
8008b46: 011a lsls r2, r3, #4
8008b48: 6abb ldr r3, [r7, #40] @ 0x28
8008b4a: 4413 add r3, r2
8008b4c: f203 430c addw r3, r3, #1036 @ 0x40c
8008b50: 627b str r3, [r7, #36] @ 0x24
8008b52: 6a7b ldr r3, [r7, #36] @ 0x24
8008b54: 881b ldrh r3, [r3, #0]
8008b56: b29b uxth r3, r3
8008b58: f3c3 0309 ubfx r3, r3, #0, #10
8008b5c: b29a uxth r2, r3
8008b5e: 6a7b ldr r3, [r7, #36] @ 0x24
8008b60: 801a strh r2, [r3, #0]
8008b62: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008b66: 2b3e cmp r3, #62 @ 0x3e
8008b68: d921 bls.n 8008bae <USB_EPStartXfer+0x276>
8008b6a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008b6e: 095b lsrs r3, r3, #5
8008b70: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8008b74: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008b78: f003 031f and.w r3, r3, #31
8008b7c: 2b00 cmp r3, #0
8008b7e: d104 bne.n 8008b8a <USB_EPStartXfer+0x252>
8008b80: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8008b84: 3b01 subs r3, #1
8008b86: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8008b8a: 6a7b ldr r3, [r7, #36] @ 0x24
8008b8c: 881b ldrh r3, [r3, #0]
8008b8e: b29a uxth r2, r3
8008b90: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8008b94: b29b uxth r3, r3
8008b96: 029b lsls r3, r3, #10
8008b98: b29b uxth r3, r3
8008b9a: 4313 orrs r3, r2
8008b9c: b29b uxth r3, r3
8008b9e: ea6f 4343 mvn.w r3, r3, lsl #17
8008ba2: ea6f 4353 mvn.w r3, r3, lsr #17
8008ba6: b29a uxth r2, r3
8008ba8: 6a7b ldr r3, [r7, #36] @ 0x24
8008baa: 801a strh r2, [r3, #0]
8008bac: e050 b.n 8008c50 <USB_EPStartXfer+0x318>
8008bae: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008bb2: 2b00 cmp r3, #0
8008bb4: d10a bne.n 8008bcc <USB_EPStartXfer+0x294>
8008bb6: 6a7b ldr r3, [r7, #36] @ 0x24
8008bb8: 881b ldrh r3, [r3, #0]
8008bba: b29b uxth r3, r3
8008bbc: ea6f 4343 mvn.w r3, r3, lsl #17
8008bc0: ea6f 4353 mvn.w r3, r3, lsr #17
8008bc4: b29a uxth r2, r3
8008bc6: 6a7b ldr r3, [r7, #36] @ 0x24
8008bc8: 801a strh r2, [r3, #0]
8008bca: e041 b.n 8008c50 <USB_EPStartXfer+0x318>
8008bcc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008bd0: 085b lsrs r3, r3, #1
8008bd2: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8008bd6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008bda: f003 0301 and.w r3, r3, #1
8008bde: 2b00 cmp r3, #0
8008be0: d004 beq.n 8008bec <USB_EPStartXfer+0x2b4>
8008be2: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8008be6: 3301 adds r3, #1
8008be8: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8008bec: 6a7b ldr r3, [r7, #36] @ 0x24
8008bee: 881b ldrh r3, [r3, #0]
8008bf0: b29a uxth r2, r3
8008bf2: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8008bf6: b29b uxth r3, r3
8008bf8: 029b lsls r3, r3, #10
8008bfa: b29b uxth r3, r3
8008bfc: 4313 orrs r3, r2
8008bfe: b29a uxth r2, r3
8008c00: 6a7b ldr r3, [r7, #36] @ 0x24
8008c02: 801a strh r2, [r3, #0]
8008c04: e024 b.n 8008c50 <USB_EPStartXfer+0x318>
8008c06: f507 7384 add.w r3, r7, #264 @ 0x108
8008c0a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c0e: 681b ldr r3, [r3, #0]
8008c10: 785b ldrb r3, [r3, #1]
8008c12: 2b01 cmp r3, #1
8008c14: d11c bne.n 8008c50 <USB_EPStartXfer+0x318>
8008c16: f507 7384 add.w r3, r7, #264 @ 0x108
8008c1a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008c1e: 681b ldr r3, [r3, #0]
8008c20: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008c24: b29b uxth r3, r3
8008c26: 461a mov r2, r3
8008c28: 6b3b ldr r3, [r7, #48] @ 0x30
8008c2a: 4413 add r3, r2
8008c2c: 633b str r3, [r7, #48] @ 0x30
8008c2e: f507 7384 add.w r3, r7, #264 @ 0x108
8008c32: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c36: 681b ldr r3, [r3, #0]
8008c38: 781b ldrb r3, [r3, #0]
8008c3a: 011a lsls r2, r3, #4
8008c3c: 6b3b ldr r3, [r7, #48] @ 0x30
8008c3e: 4413 add r3, r2
8008c40: f203 430c addw r3, r3, #1036 @ 0x40c
8008c44: 62fb str r3, [r7, #44] @ 0x2c
8008c46: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c4a: b29a uxth r2, r3
8008c4c: 6afb ldr r3, [r7, #44] @ 0x2c
8008c4e: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8008c50: f507 7384 add.w r3, r7, #264 @ 0x108
8008c54: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c58: 681b ldr r3, [r3, #0]
8008c5a: 895b ldrh r3, [r3, #10]
8008c5c: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8008c60: f507 7384 add.w r3, r7, #264 @ 0x108
8008c64: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c68: 681b ldr r3, [r3, #0]
8008c6a: 6959 ldr r1, [r3, #20]
8008c6c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c70: b29b uxth r3, r3
8008c72: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8008c76: f507 7084 add.w r0, r7, #264 @ 0x108
8008c7a: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8008c7e: 6800 ldr r0, [r0, #0]
8008c80: f001 fb49 bl 800a316 <USB_WritePMA>
ep->xfer_buff += len;
8008c84: f507 7384 add.w r3, r7, #264 @ 0x108
8008c88: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c8c: 681b ldr r3, [r3, #0]
8008c8e: 695a ldr r2, [r3, #20]
8008c90: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008c94: 441a add r2, r3
8008c96: f507 7384 add.w r3, r7, #264 @ 0x108
8008c9a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008c9e: 681b ldr r3, [r3, #0]
8008ca0: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8008ca2: f507 7384 add.w r3, r7, #264 @ 0x108
8008ca6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008caa: 681b ldr r3, [r3, #0]
8008cac: 6a1a ldr r2, [r3, #32]
8008cae: f507 7384 add.w r3, r7, #264 @ 0x108
8008cb2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cb6: 681b ldr r3, [r3, #0]
8008cb8: 691b ldr r3, [r3, #16]
8008cba: 429a cmp r2, r3
8008cbc: d90f bls.n 8008cde <USB_EPStartXfer+0x3a6>
{
ep->xfer_len_db -= len;
8008cbe: f507 7384 add.w r3, r7, #264 @ 0x108
8008cc2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cc6: 681b ldr r3, [r3, #0]
8008cc8: 6a1a ldr r2, [r3, #32]
8008cca: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008cce: 1ad2 subs r2, r2, r3
8008cd0: f507 7384 add.w r3, r7, #264 @ 0x108
8008cd4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cd8: 681b ldr r3, [r3, #0]
8008cda: 621a str r2, [r3, #32]
8008cdc: e00e b.n 8008cfc <USB_EPStartXfer+0x3c4>
}
else
{
len = ep->xfer_len_db;
8008cde: f507 7384 add.w r3, r7, #264 @ 0x108
8008ce2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ce6: 681b ldr r3, [r3, #0]
8008ce8: 6a1b ldr r3, [r3, #32]
8008cea: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
8008cee: f507 7384 add.w r3, r7, #264 @ 0x108
8008cf2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008cf6: 681b ldr r3, [r3, #0]
8008cf8: 2200 movs r2, #0
8008cfa: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8008cfc: f507 7384 add.w r3, r7, #264 @ 0x108
8008d00: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008d04: 681b ldr r3, [r3, #0]
8008d06: 785b ldrb r3, [r3, #1]
8008d08: 2b00 cmp r3, #0
8008d0a: d177 bne.n 8008dfc <USB_EPStartXfer+0x4c4>
8008d0c: f507 7384 add.w r3, r7, #264 @ 0x108
8008d10: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008d14: 681b ldr r3, [r3, #0]
8008d16: 61bb str r3, [r7, #24]
8008d18: f507 7384 add.w r3, r7, #264 @ 0x108
8008d1c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008d20: 681b ldr r3, [r3, #0]
8008d22: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008d26: b29b uxth r3, r3
8008d28: 461a mov r2, r3
8008d2a: 69bb ldr r3, [r7, #24]
8008d2c: 4413 add r3, r2
8008d2e: 61bb str r3, [r7, #24]
8008d30: f507 7384 add.w r3, r7, #264 @ 0x108
8008d34: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008d38: 681b ldr r3, [r3, #0]
8008d3a: 781b ldrb r3, [r3, #0]
8008d3c: 011a lsls r2, r3, #4
8008d3e: 69bb ldr r3, [r7, #24]
8008d40: 4413 add r3, r2
8008d42: f203 4304 addw r3, r3, #1028 @ 0x404
8008d46: 617b str r3, [r7, #20]
8008d48: 697b ldr r3, [r7, #20]
8008d4a: 881b ldrh r3, [r3, #0]
8008d4c: b29b uxth r3, r3
8008d4e: f3c3 0309 ubfx r3, r3, #0, #10
8008d52: b29a uxth r2, r3
8008d54: 697b ldr r3, [r7, #20]
8008d56: 801a strh r2, [r3, #0]
8008d58: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008d5c: 2b3e cmp r3, #62 @ 0x3e
8008d5e: d921 bls.n 8008da4 <USB_EPStartXfer+0x46c>
8008d60: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008d64: 095b lsrs r3, r3, #5
8008d66: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8008d6a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008d6e: f003 031f and.w r3, r3, #31
8008d72: 2b00 cmp r3, #0
8008d74: d104 bne.n 8008d80 <USB_EPStartXfer+0x448>
8008d76: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8008d7a: 3b01 subs r3, #1
8008d7c: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8008d80: 697b ldr r3, [r7, #20]
8008d82: 881b ldrh r3, [r3, #0]
8008d84: b29a uxth r2, r3
8008d86: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8008d8a: b29b uxth r3, r3
8008d8c: 029b lsls r3, r3, #10
8008d8e: b29b uxth r3, r3
8008d90: 4313 orrs r3, r2
8008d92: b29b uxth r3, r3
8008d94: ea6f 4343 mvn.w r3, r3, lsl #17
8008d98: ea6f 4353 mvn.w r3, r3, lsr #17
8008d9c: b29a uxth r2, r3
8008d9e: 697b ldr r3, [r7, #20]
8008da0: 801a strh r2, [r3, #0]
8008da2: e056 b.n 8008e52 <USB_EPStartXfer+0x51a>
8008da4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008da8: 2b00 cmp r3, #0
8008daa: d10a bne.n 8008dc2 <USB_EPStartXfer+0x48a>
8008dac: 697b ldr r3, [r7, #20]
8008dae: 881b ldrh r3, [r3, #0]
8008db0: b29b uxth r3, r3
8008db2: ea6f 4343 mvn.w r3, r3, lsl #17
8008db6: ea6f 4353 mvn.w r3, r3, lsr #17
8008dba: b29a uxth r2, r3
8008dbc: 697b ldr r3, [r7, #20]
8008dbe: 801a strh r2, [r3, #0]
8008dc0: e047 b.n 8008e52 <USB_EPStartXfer+0x51a>
8008dc2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008dc6: 085b lsrs r3, r3, #1
8008dc8: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8008dcc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008dd0: f003 0301 and.w r3, r3, #1
8008dd4: 2b00 cmp r3, #0
8008dd6: d004 beq.n 8008de2 <USB_EPStartXfer+0x4aa>
8008dd8: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8008ddc: 3301 adds r3, #1
8008dde: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8008de2: 697b ldr r3, [r7, #20]
8008de4: 881b ldrh r3, [r3, #0]
8008de6: b29a uxth r2, r3
8008de8: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8008dec: b29b uxth r3, r3
8008dee: 029b lsls r3, r3, #10
8008df0: b29b uxth r3, r3
8008df2: 4313 orrs r3, r2
8008df4: b29a uxth r2, r3
8008df6: 697b ldr r3, [r7, #20]
8008df8: 801a strh r2, [r3, #0]
8008dfa: e02a b.n 8008e52 <USB_EPStartXfer+0x51a>
8008dfc: f507 7384 add.w r3, r7, #264 @ 0x108
8008e00: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008e04: 681b ldr r3, [r3, #0]
8008e06: 785b ldrb r3, [r3, #1]
8008e08: 2b01 cmp r3, #1
8008e0a: d122 bne.n 8008e52 <USB_EPStartXfer+0x51a>
8008e0c: f507 7384 add.w r3, r7, #264 @ 0x108
8008e10: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008e14: 681b ldr r3, [r3, #0]
8008e16: 623b str r3, [r7, #32]
8008e18: f507 7384 add.w r3, r7, #264 @ 0x108
8008e1c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008e20: 681b ldr r3, [r3, #0]
8008e22: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008e26: b29b uxth r3, r3
8008e28: 461a mov r2, r3
8008e2a: 6a3b ldr r3, [r7, #32]
8008e2c: 4413 add r3, r2
8008e2e: 623b str r3, [r7, #32]
8008e30: f507 7384 add.w r3, r7, #264 @ 0x108
8008e34: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008e38: 681b ldr r3, [r3, #0]
8008e3a: 781b ldrb r3, [r3, #0]
8008e3c: 011a lsls r2, r3, #4
8008e3e: 6a3b ldr r3, [r7, #32]
8008e40: 4413 add r3, r2
8008e42: f203 4304 addw r3, r3, #1028 @ 0x404
8008e46: 61fb str r3, [r7, #28]
8008e48: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008e4c: b29a uxth r2, r3
8008e4e: 69fb ldr r3, [r7, #28]
8008e50: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8008e52: f507 7384 add.w r3, r7, #264 @ 0x108
8008e56: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008e5a: 681b ldr r3, [r3, #0]
8008e5c: 891b ldrh r3, [r3, #8]
8008e5e: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8008e62: f507 7384 add.w r3, r7, #264 @ 0x108
8008e66: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008e6a: 681b ldr r3, [r3, #0]
8008e6c: 6959 ldr r1, [r3, #20]
8008e6e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008e72: b29b uxth r3, r3
8008e74: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8008e78: f507 7084 add.w r0, r7, #264 @ 0x108
8008e7c: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8008e80: 6800 ldr r0, [r0, #0]
8008e82: f001 fa48 bl 800a316 <USB_WritePMA>
8008e86: e3ee b.n 8009666 <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8008e88: f507 7384 add.w r3, r7, #264 @ 0x108
8008e8c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008e90: 681b ldr r3, [r3, #0]
8008e92: 785b ldrb r3, [r3, #1]
8008e94: 2b00 cmp r3, #0
8008e96: d177 bne.n 8008f88 <USB_EPStartXfer+0x650>
8008e98: f507 7384 add.w r3, r7, #264 @ 0x108
8008e9c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008ea0: 681b ldr r3, [r3, #0]
8008ea2: 64bb str r3, [r7, #72] @ 0x48
8008ea4: f507 7384 add.w r3, r7, #264 @ 0x108
8008ea8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008eac: 681b ldr r3, [r3, #0]
8008eae: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008eb2: b29b uxth r3, r3
8008eb4: 461a mov r2, r3
8008eb6: 6cbb ldr r3, [r7, #72] @ 0x48
8008eb8: 4413 add r3, r2
8008eba: 64bb str r3, [r7, #72] @ 0x48
8008ebc: f507 7384 add.w r3, r7, #264 @ 0x108
8008ec0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ec4: 681b ldr r3, [r3, #0]
8008ec6: 781b ldrb r3, [r3, #0]
8008ec8: 011a lsls r2, r3, #4
8008eca: 6cbb ldr r3, [r7, #72] @ 0x48
8008ecc: 4413 add r3, r2
8008ece: f203 4304 addw r3, r3, #1028 @ 0x404
8008ed2: 647b str r3, [r7, #68] @ 0x44
8008ed4: 6c7b ldr r3, [r7, #68] @ 0x44
8008ed6: 881b ldrh r3, [r3, #0]
8008ed8: b29b uxth r3, r3
8008eda: f3c3 0309 ubfx r3, r3, #0, #10
8008ede: b29a uxth r2, r3
8008ee0: 6c7b ldr r3, [r7, #68] @ 0x44
8008ee2: 801a strh r2, [r3, #0]
8008ee4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008ee8: 2b3e cmp r3, #62 @ 0x3e
8008eea: d921 bls.n 8008f30 <USB_EPStartXfer+0x5f8>
8008eec: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008ef0: 095b lsrs r3, r3, #5
8008ef2: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8008ef6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008efa: f003 031f and.w r3, r3, #31
8008efe: 2b00 cmp r3, #0
8008f00: d104 bne.n 8008f0c <USB_EPStartXfer+0x5d4>
8008f02: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8008f06: 3b01 subs r3, #1
8008f08: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8008f0c: 6c7b ldr r3, [r7, #68] @ 0x44
8008f0e: 881b ldrh r3, [r3, #0]
8008f10: b29a uxth r2, r3
8008f12: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8008f16: b29b uxth r3, r3
8008f18: 029b lsls r3, r3, #10
8008f1a: b29b uxth r3, r3
8008f1c: 4313 orrs r3, r2
8008f1e: b29b uxth r3, r3
8008f20: ea6f 4343 mvn.w r3, r3, lsl #17
8008f24: ea6f 4353 mvn.w r3, r3, lsr #17
8008f28: b29a uxth r2, r3
8008f2a: 6c7b ldr r3, [r7, #68] @ 0x44
8008f2c: 801a strh r2, [r3, #0]
8008f2e: e056 b.n 8008fde <USB_EPStartXfer+0x6a6>
8008f30: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008f34: 2b00 cmp r3, #0
8008f36: d10a bne.n 8008f4e <USB_EPStartXfer+0x616>
8008f38: 6c7b ldr r3, [r7, #68] @ 0x44
8008f3a: 881b ldrh r3, [r3, #0]
8008f3c: b29b uxth r3, r3
8008f3e: ea6f 4343 mvn.w r3, r3, lsl #17
8008f42: ea6f 4353 mvn.w r3, r3, lsr #17
8008f46: b29a uxth r2, r3
8008f48: 6c7b ldr r3, [r7, #68] @ 0x44
8008f4a: 801a strh r2, [r3, #0]
8008f4c: e047 b.n 8008fde <USB_EPStartXfer+0x6a6>
8008f4e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008f52: 085b lsrs r3, r3, #1
8008f54: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8008f58: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008f5c: f003 0301 and.w r3, r3, #1
8008f60: 2b00 cmp r3, #0
8008f62: d004 beq.n 8008f6e <USB_EPStartXfer+0x636>
8008f64: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8008f68: 3301 adds r3, #1
8008f6a: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8008f6e: 6c7b ldr r3, [r7, #68] @ 0x44
8008f70: 881b ldrh r3, [r3, #0]
8008f72: b29a uxth r2, r3
8008f74: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8008f78: b29b uxth r3, r3
8008f7a: 029b lsls r3, r3, #10
8008f7c: b29b uxth r3, r3
8008f7e: 4313 orrs r3, r2
8008f80: b29a uxth r2, r3
8008f82: 6c7b ldr r3, [r7, #68] @ 0x44
8008f84: 801a strh r2, [r3, #0]
8008f86: e02a b.n 8008fde <USB_EPStartXfer+0x6a6>
8008f88: f507 7384 add.w r3, r7, #264 @ 0x108
8008f8c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008f90: 681b ldr r3, [r3, #0]
8008f92: 785b ldrb r3, [r3, #1]
8008f94: 2b01 cmp r3, #1
8008f96: d122 bne.n 8008fde <USB_EPStartXfer+0x6a6>
8008f98: f507 7384 add.w r3, r7, #264 @ 0x108
8008f9c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008fa0: 681b ldr r3, [r3, #0]
8008fa2: 653b str r3, [r7, #80] @ 0x50
8008fa4: f507 7384 add.w r3, r7, #264 @ 0x108
8008fa8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8008fac: 681b ldr r3, [r3, #0]
8008fae: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008fb2: b29b uxth r3, r3
8008fb4: 461a mov r2, r3
8008fb6: 6d3b ldr r3, [r7, #80] @ 0x50
8008fb8: 4413 add r3, r2
8008fba: 653b str r3, [r7, #80] @ 0x50
8008fbc: f507 7384 add.w r3, r7, #264 @ 0x108
8008fc0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008fc4: 681b ldr r3, [r3, #0]
8008fc6: 781b ldrb r3, [r3, #0]
8008fc8: 011a lsls r2, r3, #4
8008fca: 6d3b ldr r3, [r7, #80] @ 0x50
8008fcc: 4413 add r3, r2
8008fce: f203 4304 addw r3, r3, #1028 @ 0x404
8008fd2: 64fb str r3, [r7, #76] @ 0x4c
8008fd4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008fd8: b29a uxth r2, r3
8008fda: 6cfb ldr r3, [r7, #76] @ 0x4c
8008fdc: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8008fde: f507 7384 add.w r3, r7, #264 @ 0x108
8008fe2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008fe6: 681b ldr r3, [r3, #0]
8008fe8: 891b ldrh r3, [r3, #8]
8008fea: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8008fee: f507 7384 add.w r3, r7, #264 @ 0x108
8008ff2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8008ff6: 681b ldr r3, [r3, #0]
8008ff8: 6959 ldr r1, [r3, #20]
8008ffa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8008ffe: b29b uxth r3, r3
8009000: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8009004: f507 7084 add.w r0, r7, #264 @ 0x108
8009008: f5a0 7082 sub.w r0, r0, #260 @ 0x104
800900c: 6800 ldr r0, [r0, #0]
800900e: f001 f982 bl 800a316 <USB_WritePMA>
ep->xfer_buff += len;
8009012: f507 7384 add.w r3, r7, #264 @ 0x108
8009016: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800901a: 681b ldr r3, [r3, #0]
800901c: 695a ldr r2, [r3, #20]
800901e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009022: 441a add r2, r3
8009024: f507 7384 add.w r3, r7, #264 @ 0x108
8009028: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800902c: 681b ldr r3, [r3, #0]
800902e: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8009030: f507 7384 add.w r3, r7, #264 @ 0x108
8009034: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009038: 681b ldr r3, [r3, #0]
800903a: 6a1a ldr r2, [r3, #32]
800903c: f507 7384 add.w r3, r7, #264 @ 0x108
8009040: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009044: 681b ldr r3, [r3, #0]
8009046: 691b ldr r3, [r3, #16]
8009048: 429a cmp r2, r3
800904a: d90f bls.n 800906c <USB_EPStartXfer+0x734>
{
ep->xfer_len_db -= len;
800904c: f507 7384 add.w r3, r7, #264 @ 0x108
8009050: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009054: 681b ldr r3, [r3, #0]
8009056: 6a1a ldr r2, [r3, #32]
8009058: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800905c: 1ad2 subs r2, r2, r3
800905e: f507 7384 add.w r3, r7, #264 @ 0x108
8009062: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009066: 681b ldr r3, [r3, #0]
8009068: 621a str r2, [r3, #32]
800906a: e00e b.n 800908a <USB_EPStartXfer+0x752>
}
else
{
len = ep->xfer_len_db;
800906c: f507 7384 add.w r3, r7, #264 @ 0x108
8009070: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009074: 681b ldr r3, [r3, #0]
8009076: 6a1b ldr r3, [r3, #32]
8009078: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
800907c: f507 7384 add.w r3, r7, #264 @ 0x108
8009080: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009084: 681b ldr r3, [r3, #0]
8009086: 2200 movs r2, #0
8009088: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
800908a: f507 7384 add.w r3, r7, #264 @ 0x108
800908e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009092: 681b ldr r3, [r3, #0]
8009094: 643b str r3, [r7, #64] @ 0x40
8009096: f507 7384 add.w r3, r7, #264 @ 0x108
800909a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800909e: 681b ldr r3, [r3, #0]
80090a0: 785b ldrb r3, [r3, #1]
80090a2: 2b00 cmp r3, #0
80090a4: d177 bne.n 8009196 <USB_EPStartXfer+0x85e>
80090a6: f507 7384 add.w r3, r7, #264 @ 0x108
80090aa: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80090ae: 681b ldr r3, [r3, #0]
80090b0: 63bb str r3, [r7, #56] @ 0x38
80090b2: f507 7384 add.w r3, r7, #264 @ 0x108
80090b6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80090ba: 681b ldr r3, [r3, #0]
80090bc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80090c0: b29b uxth r3, r3
80090c2: 461a mov r2, r3
80090c4: 6bbb ldr r3, [r7, #56] @ 0x38
80090c6: 4413 add r3, r2
80090c8: 63bb str r3, [r7, #56] @ 0x38
80090ca: f507 7384 add.w r3, r7, #264 @ 0x108
80090ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80090d2: 681b ldr r3, [r3, #0]
80090d4: 781b ldrb r3, [r3, #0]
80090d6: 011a lsls r2, r3, #4
80090d8: 6bbb ldr r3, [r7, #56] @ 0x38
80090da: 4413 add r3, r2
80090dc: f203 430c addw r3, r3, #1036 @ 0x40c
80090e0: 637b str r3, [r7, #52] @ 0x34
80090e2: 6b7b ldr r3, [r7, #52] @ 0x34
80090e4: 881b ldrh r3, [r3, #0]
80090e6: b29b uxth r3, r3
80090e8: f3c3 0309 ubfx r3, r3, #0, #10
80090ec: b29a uxth r2, r3
80090ee: 6b7b ldr r3, [r7, #52] @ 0x34
80090f0: 801a strh r2, [r3, #0]
80090f2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80090f6: 2b3e cmp r3, #62 @ 0x3e
80090f8: d921 bls.n 800913e <USB_EPStartXfer+0x806>
80090fa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80090fe: 095b lsrs r3, r3, #5
8009100: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8009104: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009108: f003 031f and.w r3, r3, #31
800910c: 2b00 cmp r3, #0
800910e: d104 bne.n 800911a <USB_EPStartXfer+0x7e2>
8009110: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8009114: 3b01 subs r3, #1
8009116: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
800911a: 6b7b ldr r3, [r7, #52] @ 0x34
800911c: 881b ldrh r3, [r3, #0]
800911e: b29a uxth r2, r3
8009120: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8009124: b29b uxth r3, r3
8009126: 029b lsls r3, r3, #10
8009128: b29b uxth r3, r3
800912a: 4313 orrs r3, r2
800912c: b29b uxth r3, r3
800912e: ea6f 4343 mvn.w r3, r3, lsl #17
8009132: ea6f 4353 mvn.w r3, r3, lsr #17
8009136: b29a uxth r2, r3
8009138: 6b7b ldr r3, [r7, #52] @ 0x34
800913a: 801a strh r2, [r3, #0]
800913c: e050 b.n 80091e0 <USB_EPStartXfer+0x8a8>
800913e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009142: 2b00 cmp r3, #0
8009144: d10a bne.n 800915c <USB_EPStartXfer+0x824>
8009146: 6b7b ldr r3, [r7, #52] @ 0x34
8009148: 881b ldrh r3, [r3, #0]
800914a: b29b uxth r3, r3
800914c: ea6f 4343 mvn.w r3, r3, lsl #17
8009150: ea6f 4353 mvn.w r3, r3, lsr #17
8009154: b29a uxth r2, r3
8009156: 6b7b ldr r3, [r7, #52] @ 0x34
8009158: 801a strh r2, [r3, #0]
800915a: e041 b.n 80091e0 <USB_EPStartXfer+0x8a8>
800915c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009160: 085b lsrs r3, r3, #1
8009162: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8009166: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800916a: f003 0301 and.w r3, r3, #1
800916e: 2b00 cmp r3, #0
8009170: d004 beq.n 800917c <USB_EPStartXfer+0x844>
8009172: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8009176: 3301 adds r3, #1
8009178: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
800917c: 6b7b ldr r3, [r7, #52] @ 0x34
800917e: 881b ldrh r3, [r3, #0]
8009180: b29a uxth r2, r3
8009182: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8009186: b29b uxth r3, r3
8009188: 029b lsls r3, r3, #10
800918a: b29b uxth r3, r3
800918c: 4313 orrs r3, r2
800918e: b29a uxth r2, r3
8009190: 6b7b ldr r3, [r7, #52] @ 0x34
8009192: 801a strh r2, [r3, #0]
8009194: e024 b.n 80091e0 <USB_EPStartXfer+0x8a8>
8009196: f507 7384 add.w r3, r7, #264 @ 0x108
800919a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800919e: 681b ldr r3, [r3, #0]
80091a0: 785b ldrb r3, [r3, #1]
80091a2: 2b01 cmp r3, #1
80091a4: d11c bne.n 80091e0 <USB_EPStartXfer+0x8a8>
80091a6: f507 7384 add.w r3, r7, #264 @ 0x108
80091aa: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80091ae: 681b ldr r3, [r3, #0]
80091b0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80091b4: b29b uxth r3, r3
80091b6: 461a mov r2, r3
80091b8: 6c3b ldr r3, [r7, #64] @ 0x40
80091ba: 4413 add r3, r2
80091bc: 643b str r3, [r7, #64] @ 0x40
80091be: f507 7384 add.w r3, r7, #264 @ 0x108
80091c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80091c6: 681b ldr r3, [r3, #0]
80091c8: 781b ldrb r3, [r3, #0]
80091ca: 011a lsls r2, r3, #4
80091cc: 6c3b ldr r3, [r7, #64] @ 0x40
80091ce: 4413 add r3, r2
80091d0: f203 430c addw r3, r3, #1036 @ 0x40c
80091d4: 63fb str r3, [r7, #60] @ 0x3c
80091d6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80091da: b29a uxth r2, r3
80091dc: 6bfb ldr r3, [r7, #60] @ 0x3c
80091de: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
80091e0: f507 7384 add.w r3, r7, #264 @ 0x108
80091e4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80091e8: 681b ldr r3, [r3, #0]
80091ea: 895b ldrh r3, [r3, #10]
80091ec: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
80091f0: f507 7384 add.w r3, r7, #264 @ 0x108
80091f4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80091f8: 681b ldr r3, [r3, #0]
80091fa: 6959 ldr r1, [r3, #20]
80091fc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009200: b29b uxth r3, r3
8009202: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8009206: f507 7084 add.w r0, r7, #264 @ 0x108
800920a: f5a0 7082 sub.w r0, r0, #260 @ 0x104
800920e: 6800 ldr r0, [r0, #0]
8009210: f001 f881 bl 800a316 <USB_WritePMA>
8009214: e227 b.n 8009666 <USB_EPStartXfer+0xd2e>
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
8009216: f507 7384 add.w r3, r7, #264 @ 0x108
800921a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800921e: 681b ldr r3, [r3, #0]
8009220: 6a1b ldr r3, [r3, #32]
8009222: f8c7 3104 str.w r3, [r7, #260] @ 0x104
/* disable double buffer mode for Bulk endpoint */
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
8009226: f507 7384 add.w r3, r7, #264 @ 0x108
800922a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800922e: 681a ldr r2, [r3, #0]
8009230: f507 7384 add.w r3, r7, #264 @ 0x108
8009234: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009238: 681b ldr r3, [r3, #0]
800923a: 781b ldrb r3, [r3, #0]
800923c: 009b lsls r3, r3, #2
800923e: 4413 add r3, r2
8009240: 881b ldrh r3, [r3, #0]
8009242: b29b uxth r3, r3
8009244: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8009248: f023 0370 bic.w r3, r3, #112 @ 0x70
800924c: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8009250: f507 7384 add.w r3, r7, #264 @ 0x108
8009254: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009258: 681a ldr r2, [r3, #0]
800925a: f507 7384 add.w r3, r7, #264 @ 0x108
800925e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009262: 681b ldr r3, [r3, #0]
8009264: 781b ldrb r3, [r3, #0]
8009266: 009b lsls r3, r3, #2
8009268: 441a add r2, r3
800926a: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
800926e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8009272: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8009276: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800927a: f043 0380 orr.w r3, r3, #128 @ 0x80
800927e: b29b uxth r3, r3
8009280: 8013 strh r3, [r2, #0]
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
8009282: f507 7384 add.w r3, r7, #264 @ 0x108
8009286: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800928a: 681b ldr r3, [r3, #0]
800928c: 65fb str r3, [r7, #92] @ 0x5c
800928e: f507 7384 add.w r3, r7, #264 @ 0x108
8009292: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009296: 681b ldr r3, [r3, #0]
8009298: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800929c: b29b uxth r3, r3
800929e: 461a mov r2, r3
80092a0: 6dfb ldr r3, [r7, #92] @ 0x5c
80092a2: 4413 add r3, r2
80092a4: 65fb str r3, [r7, #92] @ 0x5c
80092a6: f507 7384 add.w r3, r7, #264 @ 0x108
80092aa: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80092ae: 681b ldr r3, [r3, #0]
80092b0: 781b ldrb r3, [r3, #0]
80092b2: 011a lsls r2, r3, #4
80092b4: 6dfb ldr r3, [r7, #92] @ 0x5c
80092b6: 4413 add r3, r2
80092b8: f203 4304 addw r3, r3, #1028 @ 0x404
80092bc: 65bb str r3, [r7, #88] @ 0x58
80092be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80092c2: b29a uxth r2, r3
80092c4: 6dbb ldr r3, [r7, #88] @ 0x58
80092c6: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
80092c8: f507 7384 add.w r3, r7, #264 @ 0x108
80092cc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80092d0: 681b ldr r3, [r3, #0]
80092d2: 891b ldrh r3, [r3, #8]
80092d4: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
80092d8: f507 7384 add.w r3, r7, #264 @ 0x108
80092dc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80092e0: 681b ldr r3, [r3, #0]
80092e2: 6959 ldr r1, [r3, #20]
80092e4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80092e8: b29b uxth r3, r3
80092ea: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
80092ee: f507 7084 add.w r0, r7, #264 @ 0x108
80092f2: f5a0 7082 sub.w r0, r0, #260 @ 0x104
80092f6: 6800 ldr r0, [r0, #0]
80092f8: f001 f80d bl 800a316 <USB_WritePMA>
80092fc: e1b3 b.n 8009666 <USB_EPStartXfer+0xd2e>
}
}
else /* manage isochronous double buffer IN mode */
{
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
80092fe: f507 7384 add.w r3, r7, #264 @ 0x108
8009302: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009306: 681b ldr r3, [r3, #0]
8009308: 6a1a ldr r2, [r3, #32]
800930a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800930e: 1ad2 subs r2, r2, r3
8009310: f507 7384 add.w r3, r7, #264 @ 0x108
8009314: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009318: 681b ldr r3, [r3, #0]
800931a: 621a str r2, [r3, #32]
/* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
800931c: f507 7384 add.w r3, r7, #264 @ 0x108
8009320: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009324: 681a ldr r2, [r3, #0]
8009326: f507 7384 add.w r3, r7, #264 @ 0x108
800932a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800932e: 681b ldr r3, [r3, #0]
8009330: 781b ldrb r3, [r3, #0]
8009332: 009b lsls r3, r3, #2
8009334: 4413 add r3, r2
8009336: 881b ldrh r3, [r3, #0]
8009338: b29b uxth r3, r3
800933a: f003 0340 and.w r3, r3, #64 @ 0x40
800933e: 2b00 cmp r3, #0
8009340: f000 80c6 beq.w 80094d0 <USB_EPStartXfer+0xb98>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8009344: f507 7384 add.w r3, r7, #264 @ 0x108
8009348: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800934c: 681b ldr r3, [r3, #0]
800934e: 673b str r3, [r7, #112] @ 0x70
8009350: f507 7384 add.w r3, r7, #264 @ 0x108
8009354: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009358: 681b ldr r3, [r3, #0]
800935a: 785b ldrb r3, [r3, #1]
800935c: 2b00 cmp r3, #0
800935e: d177 bne.n 8009450 <USB_EPStartXfer+0xb18>
8009360: f507 7384 add.w r3, r7, #264 @ 0x108
8009364: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009368: 681b ldr r3, [r3, #0]
800936a: 66bb str r3, [r7, #104] @ 0x68
800936c: f507 7384 add.w r3, r7, #264 @ 0x108
8009370: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009374: 681b ldr r3, [r3, #0]
8009376: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800937a: b29b uxth r3, r3
800937c: 461a mov r2, r3
800937e: 6ebb ldr r3, [r7, #104] @ 0x68
8009380: 4413 add r3, r2
8009382: 66bb str r3, [r7, #104] @ 0x68
8009384: f507 7384 add.w r3, r7, #264 @ 0x108
8009388: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800938c: 681b ldr r3, [r3, #0]
800938e: 781b ldrb r3, [r3, #0]
8009390: 011a lsls r2, r3, #4
8009392: 6ebb ldr r3, [r7, #104] @ 0x68
8009394: 4413 add r3, r2
8009396: f203 430c addw r3, r3, #1036 @ 0x40c
800939a: 667b str r3, [r7, #100] @ 0x64
800939c: 6e7b ldr r3, [r7, #100] @ 0x64
800939e: 881b ldrh r3, [r3, #0]
80093a0: b29b uxth r3, r3
80093a2: f3c3 0309 ubfx r3, r3, #0, #10
80093a6: b29a uxth r2, r3
80093a8: 6e7b ldr r3, [r7, #100] @ 0x64
80093aa: 801a strh r2, [r3, #0]
80093ac: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80093b0: 2b3e cmp r3, #62 @ 0x3e
80093b2: d921 bls.n 80093f8 <USB_EPStartXfer+0xac0>
80093b4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80093b8: 095b lsrs r3, r3, #5
80093ba: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
80093be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80093c2: f003 031f and.w r3, r3, #31
80093c6: 2b00 cmp r3, #0
80093c8: d104 bne.n 80093d4 <USB_EPStartXfer+0xa9c>
80093ca: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
80093ce: 3b01 subs r3, #1
80093d0: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
80093d4: 6e7b ldr r3, [r7, #100] @ 0x64
80093d6: 881b ldrh r3, [r3, #0]
80093d8: b29a uxth r2, r3
80093da: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
80093de: b29b uxth r3, r3
80093e0: 029b lsls r3, r3, #10
80093e2: b29b uxth r3, r3
80093e4: 4313 orrs r3, r2
80093e6: b29b uxth r3, r3
80093e8: ea6f 4343 mvn.w r3, r3, lsl #17
80093ec: ea6f 4353 mvn.w r3, r3, lsr #17
80093f0: b29a uxth r2, r3
80093f2: 6e7b ldr r3, [r7, #100] @ 0x64
80093f4: 801a strh r2, [r3, #0]
80093f6: e050 b.n 800949a <USB_EPStartXfer+0xb62>
80093f8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80093fc: 2b00 cmp r3, #0
80093fe: d10a bne.n 8009416 <USB_EPStartXfer+0xade>
8009400: 6e7b ldr r3, [r7, #100] @ 0x64
8009402: 881b ldrh r3, [r3, #0]
8009404: b29b uxth r3, r3
8009406: ea6f 4343 mvn.w r3, r3, lsl #17
800940a: ea6f 4353 mvn.w r3, r3, lsr #17
800940e: b29a uxth r2, r3
8009410: 6e7b ldr r3, [r7, #100] @ 0x64
8009412: 801a strh r2, [r3, #0]
8009414: e041 b.n 800949a <USB_EPStartXfer+0xb62>
8009416: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800941a: 085b lsrs r3, r3, #1
800941c: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8009420: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009424: f003 0301 and.w r3, r3, #1
8009428: 2b00 cmp r3, #0
800942a: d004 beq.n 8009436 <USB_EPStartXfer+0xafe>
800942c: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8009430: 3301 adds r3, #1
8009432: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8009436: 6e7b ldr r3, [r7, #100] @ 0x64
8009438: 881b ldrh r3, [r3, #0]
800943a: b29a uxth r2, r3
800943c: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8009440: b29b uxth r3, r3
8009442: 029b lsls r3, r3, #10
8009444: b29b uxth r3, r3
8009446: 4313 orrs r3, r2
8009448: b29a uxth r2, r3
800944a: 6e7b ldr r3, [r7, #100] @ 0x64
800944c: 801a strh r2, [r3, #0]
800944e: e024 b.n 800949a <USB_EPStartXfer+0xb62>
8009450: f507 7384 add.w r3, r7, #264 @ 0x108
8009454: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009458: 681b ldr r3, [r3, #0]
800945a: 785b ldrb r3, [r3, #1]
800945c: 2b01 cmp r3, #1
800945e: d11c bne.n 800949a <USB_EPStartXfer+0xb62>
8009460: f507 7384 add.w r3, r7, #264 @ 0x108
8009464: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009468: 681b ldr r3, [r3, #0]
800946a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800946e: b29b uxth r3, r3
8009470: 461a mov r2, r3
8009472: 6f3b ldr r3, [r7, #112] @ 0x70
8009474: 4413 add r3, r2
8009476: 673b str r3, [r7, #112] @ 0x70
8009478: f507 7384 add.w r3, r7, #264 @ 0x108
800947c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009480: 681b ldr r3, [r3, #0]
8009482: 781b ldrb r3, [r3, #0]
8009484: 011a lsls r2, r3, #4
8009486: 6f3b ldr r3, [r7, #112] @ 0x70
8009488: 4413 add r3, r2
800948a: f203 430c addw r3, r3, #1036 @ 0x40c
800948e: 66fb str r3, [r7, #108] @ 0x6c
8009490: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009494: b29a uxth r2, r3
8009496: 6efb ldr r3, [r7, #108] @ 0x6c
8009498: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800949a: f507 7384 add.w r3, r7, #264 @ 0x108
800949e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80094a2: 681b ldr r3, [r3, #0]
80094a4: 895b ldrh r3, [r3, #10]
80094a6: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
80094aa: f507 7384 add.w r3, r7, #264 @ 0x108
80094ae: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80094b2: 681b ldr r3, [r3, #0]
80094b4: 6959 ldr r1, [r3, #20]
80094b6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80094ba: b29b uxth r3, r3
80094bc: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
80094c0: f507 7084 add.w r0, r7, #264 @ 0x108
80094c4: f5a0 7082 sub.w r0, r0, #260 @ 0x104
80094c8: 6800 ldr r0, [r0, #0]
80094ca: f000 ff24 bl 800a316 <USB_WritePMA>
80094ce: e0ca b.n 8009666 <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
80094d0: f507 7384 add.w r3, r7, #264 @ 0x108
80094d4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80094d8: 681b ldr r3, [r3, #0]
80094da: 785b ldrb r3, [r3, #1]
80094dc: 2b00 cmp r3, #0
80094de: d177 bne.n 80095d0 <USB_EPStartXfer+0xc98>
80094e0: f507 7384 add.w r3, r7, #264 @ 0x108
80094e4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80094e8: 681b ldr r3, [r3, #0]
80094ea: 67fb str r3, [r7, #124] @ 0x7c
80094ec: f507 7384 add.w r3, r7, #264 @ 0x108
80094f0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80094f4: 681b ldr r3, [r3, #0]
80094f6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80094fa: b29b uxth r3, r3
80094fc: 461a mov r2, r3
80094fe: 6ffb ldr r3, [r7, #124] @ 0x7c
8009500: 4413 add r3, r2
8009502: 67fb str r3, [r7, #124] @ 0x7c
8009504: f507 7384 add.w r3, r7, #264 @ 0x108
8009508: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800950c: 681b ldr r3, [r3, #0]
800950e: 781b ldrb r3, [r3, #0]
8009510: 011a lsls r2, r3, #4
8009512: 6ffb ldr r3, [r7, #124] @ 0x7c
8009514: 4413 add r3, r2
8009516: f203 4304 addw r3, r3, #1028 @ 0x404
800951a: 67bb str r3, [r7, #120] @ 0x78
800951c: 6fbb ldr r3, [r7, #120] @ 0x78
800951e: 881b ldrh r3, [r3, #0]
8009520: b29b uxth r3, r3
8009522: f3c3 0309 ubfx r3, r3, #0, #10
8009526: b29a uxth r2, r3
8009528: 6fbb ldr r3, [r7, #120] @ 0x78
800952a: 801a strh r2, [r3, #0]
800952c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009530: 2b3e cmp r3, #62 @ 0x3e
8009532: d921 bls.n 8009578 <USB_EPStartXfer+0xc40>
8009534: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009538: 095b lsrs r3, r3, #5
800953a: f8c7 30ec str.w r3, [r7, #236] @ 0xec
800953e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009542: f003 031f and.w r3, r3, #31
8009546: 2b00 cmp r3, #0
8009548: d104 bne.n 8009554 <USB_EPStartXfer+0xc1c>
800954a: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
800954e: 3b01 subs r3, #1
8009550: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8009554: 6fbb ldr r3, [r7, #120] @ 0x78
8009556: 881b ldrh r3, [r3, #0]
8009558: b29a uxth r2, r3
800955a: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
800955e: b29b uxth r3, r3
8009560: 029b lsls r3, r3, #10
8009562: b29b uxth r3, r3
8009564: 4313 orrs r3, r2
8009566: b29b uxth r3, r3
8009568: ea6f 4343 mvn.w r3, r3, lsl #17
800956c: ea6f 4353 mvn.w r3, r3, lsr #17
8009570: b29a uxth r2, r3
8009572: 6fbb ldr r3, [r7, #120] @ 0x78
8009574: 801a strh r2, [r3, #0]
8009576: e05c b.n 8009632 <USB_EPStartXfer+0xcfa>
8009578: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800957c: 2b00 cmp r3, #0
800957e: d10a bne.n 8009596 <USB_EPStartXfer+0xc5e>
8009580: 6fbb ldr r3, [r7, #120] @ 0x78
8009582: 881b ldrh r3, [r3, #0]
8009584: b29b uxth r3, r3
8009586: ea6f 4343 mvn.w r3, r3, lsl #17
800958a: ea6f 4353 mvn.w r3, r3, lsr #17
800958e: b29a uxth r2, r3
8009590: 6fbb ldr r3, [r7, #120] @ 0x78
8009592: 801a strh r2, [r3, #0]
8009594: e04d b.n 8009632 <USB_EPStartXfer+0xcfa>
8009596: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800959a: 085b lsrs r3, r3, #1
800959c: f8c7 30ec str.w r3, [r7, #236] @ 0xec
80095a0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80095a4: f003 0301 and.w r3, r3, #1
80095a8: 2b00 cmp r3, #0
80095aa: d004 beq.n 80095b6 <USB_EPStartXfer+0xc7e>
80095ac: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
80095b0: 3301 adds r3, #1
80095b2: f8c7 30ec str.w r3, [r7, #236] @ 0xec
80095b6: 6fbb ldr r3, [r7, #120] @ 0x78
80095b8: 881b ldrh r3, [r3, #0]
80095ba: b29a uxth r2, r3
80095bc: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
80095c0: b29b uxth r3, r3
80095c2: 029b lsls r3, r3, #10
80095c4: b29b uxth r3, r3
80095c6: 4313 orrs r3, r2
80095c8: b29a uxth r2, r3
80095ca: 6fbb ldr r3, [r7, #120] @ 0x78
80095cc: 801a strh r2, [r3, #0]
80095ce: e030 b.n 8009632 <USB_EPStartXfer+0xcfa>
80095d0: f507 7384 add.w r3, r7, #264 @ 0x108
80095d4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80095d8: 681b ldr r3, [r3, #0]
80095da: 785b ldrb r3, [r3, #1]
80095dc: 2b01 cmp r3, #1
80095de: d128 bne.n 8009632 <USB_EPStartXfer+0xcfa>
80095e0: f507 7384 add.w r3, r7, #264 @ 0x108
80095e4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80095e8: 681b ldr r3, [r3, #0]
80095ea: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80095ee: f507 7384 add.w r3, r7, #264 @ 0x108
80095f2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80095f6: 681b ldr r3, [r3, #0]
80095f8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80095fc: b29b uxth r3, r3
80095fe: 461a mov r2, r3
8009600: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8009604: 4413 add r3, r2
8009606: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800960a: f507 7384 add.w r3, r7, #264 @ 0x108
800960e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009612: 681b ldr r3, [r3, #0]
8009614: 781b ldrb r3, [r3, #0]
8009616: 011a lsls r2, r3, #4
8009618: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800961c: 4413 add r3, r2
800961e: f203 4304 addw r3, r3, #1028 @ 0x404
8009622: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8009626: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800962a: b29a uxth r2, r3
800962c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8009630: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8009632: f507 7384 add.w r3, r7, #264 @ 0x108
8009636: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800963a: 681b ldr r3, [r3, #0]
800963c: 891b ldrh r3, [r3, #8]
800963e: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8009642: f507 7384 add.w r3, r7, #264 @ 0x108
8009646: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800964a: 681b ldr r3, [r3, #0]
800964c: 6959 ldr r1, [r3, #20]
800964e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009652: b29b uxth r3, r3
8009654: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8009658: f507 7084 add.w r0, r7, #264 @ 0x108
800965c: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8009660: 6800 ldr r0, [r0, #0]
8009662: f000 fe58 bl 800a316 <USB_WritePMA>
}
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
8009666: f507 7384 add.w r3, r7, #264 @ 0x108
800966a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800966e: 681a ldr r2, [r3, #0]
8009670: f507 7384 add.w r3, r7, #264 @ 0x108
8009674: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009678: 681b ldr r3, [r3, #0]
800967a: 781b ldrb r3, [r3, #0]
800967c: 009b lsls r3, r3, #2
800967e: 4413 add r3, r2
8009680: 881b ldrh r3, [r3, #0]
8009682: b29b uxth r3, r3
8009684: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8009688: f023 0340 bic.w r3, r3, #64 @ 0x40
800968c: 817b strh r3, [r7, #10]
800968e: 897b ldrh r3, [r7, #10]
8009690: f083 0310 eor.w r3, r3, #16
8009694: 817b strh r3, [r7, #10]
8009696: 897b ldrh r3, [r7, #10]
8009698: f083 0320 eor.w r3, r3, #32
800969c: 817b strh r3, [r7, #10]
800969e: f507 7384 add.w r3, r7, #264 @ 0x108
80096a2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80096a6: 681a ldr r2, [r3, #0]
80096a8: f507 7384 add.w r3, r7, #264 @ 0x108
80096ac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80096b0: 681b ldr r3, [r3, #0]
80096b2: 781b ldrb r3, [r3, #0]
80096b4: 009b lsls r3, r3, #2
80096b6: 441a add r2, r3
80096b8: 897b ldrh r3, [r7, #10]
80096ba: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80096be: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80096c2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80096c6: f043 0380 orr.w r3, r3, #128 @ 0x80
80096ca: b29b uxth r3, r3
80096cc: 8013 strh r3, [r2, #0]
80096ce: f000 bcde b.w 800a08e <USB_EPStartXfer+0x1756>
}
else /* OUT endpoint */
{
if (ep->doublebuffer == 0U)
80096d2: f507 7384 add.w r3, r7, #264 @ 0x108
80096d6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80096da: 681b ldr r3, [r3, #0]
80096dc: 7b1b ldrb r3, [r3, #12]
80096de: 2b00 cmp r3, #0
80096e0: f040 80bb bne.w 800985a <USB_EPStartXfer+0xf22>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
80096e4: f507 7384 add.w r3, r7, #264 @ 0x108
80096e8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80096ec: 681b ldr r3, [r3, #0]
80096ee: 699a ldr r2, [r3, #24]
80096f0: f507 7384 add.w r3, r7, #264 @ 0x108
80096f4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80096f8: 681b ldr r3, [r3, #0]
80096fa: 691b ldr r3, [r3, #16]
80096fc: 429a cmp r2, r3
80096fe: d917 bls.n 8009730 <USB_EPStartXfer+0xdf8>
{
len = ep->maxpacket;
8009700: f507 7384 add.w r3, r7, #264 @ 0x108
8009704: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009708: 681b ldr r3, [r3, #0]
800970a: 691b ldr r3, [r3, #16]
800970c: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
8009710: f507 7384 add.w r3, r7, #264 @ 0x108
8009714: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009718: 681b ldr r3, [r3, #0]
800971a: 699a ldr r2, [r3, #24]
800971c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009720: 1ad2 subs r2, r2, r3
8009722: f507 7384 add.w r3, r7, #264 @ 0x108
8009726: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800972a: 681b ldr r3, [r3, #0]
800972c: 619a str r2, [r3, #24]
800972e: e00e b.n 800974e <USB_EPStartXfer+0xe16>
}
else
{
len = ep->xfer_len;
8009730: f507 7384 add.w r3, r7, #264 @ 0x108
8009734: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009738: 681b ldr r3, [r3, #0]
800973a: 699b ldr r3, [r3, #24]
800973c: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
8009740: f507 7384 add.w r3, r7, #264 @ 0x108
8009744: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009748: 681b ldr r3, [r3, #0]
800974a: 2200 movs r2, #0
800974c: 619a str r2, [r3, #24]
}
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
800974e: f507 7384 add.w r3, r7, #264 @ 0x108
8009752: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009756: 681b ldr r3, [r3, #0]
8009758: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800975c: f507 7384 add.w r3, r7, #264 @ 0x108
8009760: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009764: 681b ldr r3, [r3, #0]
8009766: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800976a: b29b uxth r3, r3
800976c: 461a mov r2, r3
800976e: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8009772: 4413 add r3, r2
8009774: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8009778: f507 7384 add.w r3, r7, #264 @ 0x108
800977c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009780: 681b ldr r3, [r3, #0]
8009782: 781b ldrb r3, [r3, #0]
8009784: 011a lsls r2, r3, #4
8009786: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800978a: 4413 add r3, r2
800978c: f203 430c addw r3, r3, #1036 @ 0x40c
8009790: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8009794: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8009798: 881b ldrh r3, [r3, #0]
800979a: b29b uxth r3, r3
800979c: f3c3 0309 ubfx r3, r3, #0, #10
80097a0: b29a uxth r2, r3
80097a2: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80097a6: 801a strh r2, [r3, #0]
80097a8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80097ac: 2b3e cmp r3, #62 @ 0x3e
80097ae: d924 bls.n 80097fa <USB_EPStartXfer+0xec2>
80097b0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80097b4: 095b lsrs r3, r3, #5
80097b6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
80097ba: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80097be: f003 031f and.w r3, r3, #31
80097c2: 2b00 cmp r3, #0
80097c4: d104 bne.n 80097d0 <USB_EPStartXfer+0xe98>
80097c6: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80097ca: 3b01 subs r3, #1
80097cc: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
80097d0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80097d4: 881b ldrh r3, [r3, #0]
80097d6: b29a uxth r2, r3
80097d8: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80097dc: b29b uxth r3, r3
80097de: 029b lsls r3, r3, #10
80097e0: b29b uxth r3, r3
80097e2: 4313 orrs r3, r2
80097e4: b29b uxth r3, r3
80097e6: ea6f 4343 mvn.w r3, r3, lsl #17
80097ea: ea6f 4353 mvn.w r3, r3, lsr #17
80097ee: b29a uxth r2, r3
80097f0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80097f4: 801a strh r2, [r3, #0]
80097f6: f000 bc10 b.w 800a01a <USB_EPStartXfer+0x16e2>
80097fa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80097fe: 2b00 cmp r3, #0
8009800: d10c bne.n 800981c <USB_EPStartXfer+0xee4>
8009802: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8009806: 881b ldrh r3, [r3, #0]
8009808: b29b uxth r3, r3
800980a: ea6f 4343 mvn.w r3, r3, lsl #17
800980e: ea6f 4353 mvn.w r3, r3, lsr #17
8009812: b29a uxth r2, r3
8009814: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8009818: 801a strh r2, [r3, #0]
800981a: e3fe b.n 800a01a <USB_EPStartXfer+0x16e2>
800981c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009820: 085b lsrs r3, r3, #1
8009822: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8009826: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800982a: f003 0301 and.w r3, r3, #1
800982e: 2b00 cmp r3, #0
8009830: d004 beq.n 800983c <USB_EPStartXfer+0xf04>
8009832: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
8009836: 3301 adds r3, #1
8009838: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
800983c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8009840: 881b ldrh r3, [r3, #0]
8009842: b29a uxth r2, r3
8009844: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
8009848: b29b uxth r3, r3
800984a: 029b lsls r3, r3, #10
800984c: b29b uxth r3, r3
800984e: 4313 orrs r3, r2
8009850: b29a uxth r2, r3
8009852: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8009856: 801a strh r2, [r3, #0]
8009858: e3df b.n 800a01a <USB_EPStartXfer+0x16e2>
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
800985a: f507 7384 add.w r3, r7, #264 @ 0x108
800985e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009862: 681b ldr r3, [r3, #0]
8009864: 78db ldrb r3, [r3, #3]
8009866: 2b02 cmp r3, #2
8009868: f040 8218 bne.w 8009c9c <USB_EPStartXfer+0x1364>
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
800986c: f507 7384 add.w r3, r7, #264 @ 0x108
8009870: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009874: 681b ldr r3, [r3, #0]
8009876: 785b ldrb r3, [r3, #1]
8009878: 2b00 cmp r3, #0
800987a: f040 809d bne.w 80099b8 <USB_EPStartXfer+0x1080>
800987e: f507 7384 add.w r3, r7, #264 @ 0x108
8009882: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009886: 681b ldr r3, [r3, #0]
8009888: f8c7 30ac str.w r3, [r7, #172] @ 0xac
800988c: f507 7384 add.w r3, r7, #264 @ 0x108
8009890: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009894: 681b ldr r3, [r3, #0]
8009896: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800989a: b29b uxth r3, r3
800989c: 461a mov r2, r3
800989e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80098a2: 4413 add r3, r2
80098a4: f8c7 30ac str.w r3, [r7, #172] @ 0xac
80098a8: f507 7384 add.w r3, r7, #264 @ 0x108
80098ac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80098b0: 681b ldr r3, [r3, #0]
80098b2: 781b ldrb r3, [r3, #0]
80098b4: 011a lsls r2, r3, #4
80098b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80098ba: 4413 add r3, r2
80098bc: f203 4304 addw r3, r3, #1028 @ 0x404
80098c0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
80098c4: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80098c8: 881b ldrh r3, [r3, #0]
80098ca: b29b uxth r3, r3
80098cc: f3c3 0309 ubfx r3, r3, #0, #10
80098d0: b29a uxth r2, r3
80098d2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80098d6: 801a strh r2, [r3, #0]
80098d8: f507 7384 add.w r3, r7, #264 @ 0x108
80098dc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80098e0: 681b ldr r3, [r3, #0]
80098e2: 691b ldr r3, [r3, #16]
80098e4: 2b3e cmp r3, #62 @ 0x3e
80098e6: d92b bls.n 8009940 <USB_EPStartXfer+0x1008>
80098e8: f507 7384 add.w r3, r7, #264 @ 0x108
80098ec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80098f0: 681b ldr r3, [r3, #0]
80098f2: 691b ldr r3, [r3, #16]
80098f4: 095b lsrs r3, r3, #5
80098f6: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80098fa: f507 7384 add.w r3, r7, #264 @ 0x108
80098fe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009902: 681b ldr r3, [r3, #0]
8009904: 691b ldr r3, [r3, #16]
8009906: f003 031f and.w r3, r3, #31
800990a: 2b00 cmp r3, #0
800990c: d104 bne.n 8009918 <USB_EPStartXfer+0xfe0>
800990e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8009912: 3b01 subs r3, #1
8009914: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
8009918: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800991c: 881b ldrh r3, [r3, #0]
800991e: b29a uxth r2, r3
8009920: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8009924: b29b uxth r3, r3
8009926: 029b lsls r3, r3, #10
8009928: b29b uxth r3, r3
800992a: 4313 orrs r3, r2
800992c: b29b uxth r3, r3
800992e: ea6f 4343 mvn.w r3, r3, lsl #17
8009932: ea6f 4353 mvn.w r3, r3, lsr #17
8009936: b29a uxth r2, r3
8009938: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800993c: 801a strh r2, [r3, #0]
800993e: e070 b.n 8009a22 <USB_EPStartXfer+0x10ea>
8009940: f507 7384 add.w r3, r7, #264 @ 0x108
8009944: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009948: 681b ldr r3, [r3, #0]
800994a: 691b ldr r3, [r3, #16]
800994c: 2b00 cmp r3, #0
800994e: d10c bne.n 800996a <USB_EPStartXfer+0x1032>
8009950: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8009954: 881b ldrh r3, [r3, #0]
8009956: b29b uxth r3, r3
8009958: ea6f 4343 mvn.w r3, r3, lsl #17
800995c: ea6f 4353 mvn.w r3, r3, lsr #17
8009960: b29a uxth r2, r3
8009962: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8009966: 801a strh r2, [r3, #0]
8009968: e05b b.n 8009a22 <USB_EPStartXfer+0x10ea>
800996a: f507 7384 add.w r3, r7, #264 @ 0x108
800996e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009972: 681b ldr r3, [r3, #0]
8009974: 691b ldr r3, [r3, #16]
8009976: 085b lsrs r3, r3, #1
8009978: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
800997c: f507 7384 add.w r3, r7, #264 @ 0x108
8009980: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009984: 681b ldr r3, [r3, #0]
8009986: 691b ldr r3, [r3, #16]
8009988: f003 0301 and.w r3, r3, #1
800998c: 2b00 cmp r3, #0
800998e: d004 beq.n 800999a <USB_EPStartXfer+0x1062>
8009990: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8009994: 3301 adds r3, #1
8009996: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
800999a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800999e: 881b ldrh r3, [r3, #0]
80099a0: b29a uxth r2, r3
80099a2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80099a6: b29b uxth r3, r3
80099a8: 029b lsls r3, r3, #10
80099aa: b29b uxth r3, r3
80099ac: 4313 orrs r3, r2
80099ae: b29a uxth r2, r3
80099b0: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80099b4: 801a strh r2, [r3, #0]
80099b6: e034 b.n 8009a22 <USB_EPStartXfer+0x10ea>
80099b8: f507 7384 add.w r3, r7, #264 @ 0x108
80099bc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80099c0: 681b ldr r3, [r3, #0]
80099c2: 785b ldrb r3, [r3, #1]
80099c4: 2b01 cmp r3, #1
80099c6: d12c bne.n 8009a22 <USB_EPStartXfer+0x10ea>
80099c8: f507 7384 add.w r3, r7, #264 @ 0x108
80099cc: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80099d0: 681b ldr r3, [r3, #0]
80099d2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80099d6: f507 7384 add.w r3, r7, #264 @ 0x108
80099da: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80099de: 681b ldr r3, [r3, #0]
80099e0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80099e4: b29b uxth r3, r3
80099e6: 461a mov r2, r3
80099e8: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80099ec: 4413 add r3, r2
80099ee: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80099f2: f507 7384 add.w r3, r7, #264 @ 0x108
80099f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80099fa: 681b ldr r3, [r3, #0]
80099fc: 781b ldrb r3, [r3, #0]
80099fe: 011a lsls r2, r3, #4
8009a00: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8009a04: 4413 add r3, r2
8009a06: f203 4304 addw r3, r3, #1028 @ 0x404
8009a0a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8009a0e: f507 7384 add.w r3, r7, #264 @ 0x108
8009a12: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009a16: 681b ldr r3, [r3, #0]
8009a18: 691b ldr r3, [r3, #16]
8009a1a: b29a uxth r2, r3
8009a1c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
8009a20: 801a strh r2, [r3, #0]
8009a22: f507 7384 add.w r3, r7, #264 @ 0x108
8009a26: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009a2a: 681b ldr r3, [r3, #0]
8009a2c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
8009a30: f507 7384 add.w r3, r7, #264 @ 0x108
8009a34: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009a38: 681b ldr r3, [r3, #0]
8009a3a: 785b ldrb r3, [r3, #1]
8009a3c: 2b00 cmp r3, #0
8009a3e: f040 809d bne.w 8009b7c <USB_EPStartXfer+0x1244>
8009a42: f507 7384 add.w r3, r7, #264 @ 0x108
8009a46: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009a4a: 681b ldr r3, [r3, #0]
8009a4c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8009a50: f507 7384 add.w r3, r7, #264 @ 0x108
8009a54: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009a58: 681b ldr r3, [r3, #0]
8009a5a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009a5e: b29b uxth r3, r3
8009a60: 461a mov r2, r3
8009a62: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8009a66: 4413 add r3, r2
8009a68: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8009a6c: f507 7384 add.w r3, r7, #264 @ 0x108
8009a70: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009a74: 681b ldr r3, [r3, #0]
8009a76: 781b ldrb r3, [r3, #0]
8009a78: 011a lsls r2, r3, #4
8009a7a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8009a7e: 4413 add r3, r2
8009a80: f203 430c addw r3, r3, #1036 @ 0x40c
8009a84: f8c7 3098 str.w r3, [r7, #152] @ 0x98
8009a88: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009a8c: 881b ldrh r3, [r3, #0]
8009a8e: b29b uxth r3, r3
8009a90: f3c3 0309 ubfx r3, r3, #0, #10
8009a94: b29a uxth r2, r3
8009a96: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009a9a: 801a strh r2, [r3, #0]
8009a9c: f507 7384 add.w r3, r7, #264 @ 0x108
8009aa0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009aa4: 681b ldr r3, [r3, #0]
8009aa6: 691b ldr r3, [r3, #16]
8009aa8: 2b3e cmp r3, #62 @ 0x3e
8009aaa: d92b bls.n 8009b04 <USB_EPStartXfer+0x11cc>
8009aac: f507 7384 add.w r3, r7, #264 @ 0x108
8009ab0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009ab4: 681b ldr r3, [r3, #0]
8009ab6: 691b ldr r3, [r3, #16]
8009ab8: 095b lsrs r3, r3, #5
8009aba: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8009abe: f507 7384 add.w r3, r7, #264 @ 0x108
8009ac2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009ac6: 681b ldr r3, [r3, #0]
8009ac8: 691b ldr r3, [r3, #16]
8009aca: f003 031f and.w r3, r3, #31
8009ace: 2b00 cmp r3, #0
8009ad0: d104 bne.n 8009adc <USB_EPStartXfer+0x11a4>
8009ad2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8009ad6: 3b01 subs r3, #1
8009ad8: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8009adc: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009ae0: 881b ldrh r3, [r3, #0]
8009ae2: b29a uxth r2, r3
8009ae4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8009ae8: b29b uxth r3, r3
8009aea: 029b lsls r3, r3, #10
8009aec: b29b uxth r3, r3
8009aee: 4313 orrs r3, r2
8009af0: b29b uxth r3, r3
8009af2: ea6f 4343 mvn.w r3, r3, lsl #17
8009af6: ea6f 4353 mvn.w r3, r3, lsr #17
8009afa: b29a uxth r2, r3
8009afc: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009b00: 801a strh r2, [r3, #0]
8009b02: e069 b.n 8009bd8 <USB_EPStartXfer+0x12a0>
8009b04: f507 7384 add.w r3, r7, #264 @ 0x108
8009b08: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009b0c: 681b ldr r3, [r3, #0]
8009b0e: 691b ldr r3, [r3, #16]
8009b10: 2b00 cmp r3, #0
8009b12: d10c bne.n 8009b2e <USB_EPStartXfer+0x11f6>
8009b14: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009b18: 881b ldrh r3, [r3, #0]
8009b1a: b29b uxth r3, r3
8009b1c: ea6f 4343 mvn.w r3, r3, lsl #17
8009b20: ea6f 4353 mvn.w r3, r3, lsr #17
8009b24: b29a uxth r2, r3
8009b26: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009b2a: 801a strh r2, [r3, #0]
8009b2c: e054 b.n 8009bd8 <USB_EPStartXfer+0x12a0>
8009b2e: f507 7384 add.w r3, r7, #264 @ 0x108
8009b32: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009b36: 681b ldr r3, [r3, #0]
8009b38: 691b ldr r3, [r3, #16]
8009b3a: 085b lsrs r3, r3, #1
8009b3c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8009b40: f507 7384 add.w r3, r7, #264 @ 0x108
8009b44: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009b48: 681b ldr r3, [r3, #0]
8009b4a: 691b ldr r3, [r3, #16]
8009b4c: f003 0301 and.w r3, r3, #1
8009b50: 2b00 cmp r3, #0
8009b52: d004 beq.n 8009b5e <USB_EPStartXfer+0x1226>
8009b54: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8009b58: 3301 adds r3, #1
8009b5a: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8009b5e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009b62: 881b ldrh r3, [r3, #0]
8009b64: b29a uxth r2, r3
8009b66: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8009b6a: b29b uxth r3, r3
8009b6c: 029b lsls r3, r3, #10
8009b6e: b29b uxth r3, r3
8009b70: 4313 orrs r3, r2
8009b72: b29a uxth r2, r3
8009b74: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8009b78: 801a strh r2, [r3, #0]
8009b7a: e02d b.n 8009bd8 <USB_EPStartXfer+0x12a0>
8009b7c: f507 7384 add.w r3, r7, #264 @ 0x108
8009b80: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009b84: 681b ldr r3, [r3, #0]
8009b86: 785b ldrb r3, [r3, #1]
8009b88: 2b01 cmp r3, #1
8009b8a: d125 bne.n 8009bd8 <USB_EPStartXfer+0x12a0>
8009b8c: f507 7384 add.w r3, r7, #264 @ 0x108
8009b90: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009b94: 681b ldr r3, [r3, #0]
8009b96: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009b9a: b29b uxth r3, r3
8009b9c: 461a mov r2, r3
8009b9e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8009ba2: 4413 add r3, r2
8009ba4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
8009ba8: f507 7384 add.w r3, r7, #264 @ 0x108
8009bac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009bb0: 681b ldr r3, [r3, #0]
8009bb2: 781b ldrb r3, [r3, #0]
8009bb4: 011a lsls r2, r3, #4
8009bb6: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8009bba: 4413 add r3, r2
8009bbc: f203 430c addw r3, r3, #1036 @ 0x40c
8009bc0: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
8009bc4: f507 7384 add.w r3, r7, #264 @ 0x108
8009bc8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009bcc: 681b ldr r3, [r3, #0]
8009bce: 691b ldr r3, [r3, #16]
8009bd0: b29a uxth r2, r3
8009bd2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8009bd6: 801a strh r2, [r3, #0]
/* Coming from ISR */
if (ep->xfer_count != 0U)
8009bd8: f507 7384 add.w r3, r7, #264 @ 0x108
8009bdc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009be0: 681b ldr r3, [r3, #0]
8009be2: 69db ldr r3, [r3, #28]
8009be4: 2b00 cmp r3, #0
8009be6: f000 8218 beq.w 800a01a <USB_EPStartXfer+0x16e2>
{
/* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
8009bea: f507 7384 add.w r3, r7, #264 @ 0x108
8009bee: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009bf2: 681a ldr r2, [r3, #0]
8009bf4: f507 7384 add.w r3, r7, #264 @ 0x108
8009bf8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009bfc: 681b ldr r3, [r3, #0]
8009bfe: 781b ldrb r3, [r3, #0]
8009c00: 009b lsls r3, r3, #2
8009c02: 4413 add r3, r2
8009c04: 881b ldrh r3, [r3, #0]
8009c06: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
8009c0a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8009c0e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8009c12: 2b00 cmp r3, #0
8009c14: d005 beq.n 8009c22 <USB_EPStartXfer+0x12ea>
8009c16: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8009c1a: f003 0340 and.w r3, r3, #64 @ 0x40
8009c1e: 2b00 cmp r3, #0
8009c20: d10d bne.n 8009c3e <USB_EPStartXfer+0x1306>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
8009c22: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8009c26: f403 4380 and.w r3, r3, #16384 @ 0x4000
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
8009c2a: 2b00 cmp r3, #0
8009c2c: f040 81f5 bne.w 800a01a <USB_EPStartXfer+0x16e2>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
8009c30: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8009c34: f003 0340 and.w r3, r3, #64 @ 0x40
8009c38: 2b00 cmp r3, #0
8009c3a: f040 81ee bne.w 800a01a <USB_EPStartXfer+0x16e2>
{
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
8009c3e: f507 7384 add.w r3, r7, #264 @ 0x108
8009c42: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009c46: 681a ldr r2, [r3, #0]
8009c48: f507 7384 add.w r3, r7, #264 @ 0x108
8009c4c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009c50: 681b ldr r3, [r3, #0]
8009c52: 781b ldrb r3, [r3, #0]
8009c54: 009b lsls r3, r3, #2
8009c56: 4413 add r3, r2
8009c58: 881b ldrh r3, [r3, #0]
8009c5a: b29b uxth r3, r3
8009c5c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8009c60: f023 0370 bic.w r3, r3, #112 @ 0x70
8009c64: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
8009c68: f507 7384 add.w r3, r7, #264 @ 0x108
8009c6c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009c70: 681a ldr r2, [r3, #0]
8009c72: f507 7384 add.w r3, r7, #264 @ 0x108
8009c76: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009c7a: 681b ldr r3, [r3, #0]
8009c7c: 781b ldrb r3, [r3, #0]
8009c7e: 009b lsls r3, r3, #2
8009c80: 441a add r2, r3
8009c82: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
8009c86: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8009c8a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8009c8e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8009c92: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8009c96: b29b uxth r3, r3
8009c98: 8013 strh r3, [r2, #0]
8009c9a: e1be b.n 800a01a <USB_EPStartXfer+0x16e2>
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
8009c9c: f507 7384 add.w r3, r7, #264 @ 0x108
8009ca0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009ca4: 681b ldr r3, [r3, #0]
8009ca6: 78db ldrb r3, [r3, #3]
8009ca8: 2b01 cmp r3, #1
8009caa: f040 81b4 bne.w 800a016 <USB_EPStartXfer+0x16de>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
8009cae: f507 7384 add.w r3, r7, #264 @ 0x108
8009cb2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009cb6: 681b ldr r3, [r3, #0]
8009cb8: 699a ldr r2, [r3, #24]
8009cba: f507 7384 add.w r3, r7, #264 @ 0x108
8009cbe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009cc2: 681b ldr r3, [r3, #0]
8009cc4: 691b ldr r3, [r3, #16]
8009cc6: 429a cmp r2, r3
8009cc8: d917 bls.n 8009cfa <USB_EPStartXfer+0x13c2>
{
len = ep->maxpacket;
8009cca: f507 7384 add.w r3, r7, #264 @ 0x108
8009cce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009cd2: 681b ldr r3, [r3, #0]
8009cd4: 691b ldr r3, [r3, #16]
8009cd6: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
8009cda: f507 7384 add.w r3, r7, #264 @ 0x108
8009cde: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009ce2: 681b ldr r3, [r3, #0]
8009ce4: 699a ldr r2, [r3, #24]
8009ce6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009cea: 1ad2 subs r2, r2, r3
8009cec: f507 7384 add.w r3, r7, #264 @ 0x108
8009cf0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009cf4: 681b ldr r3, [r3, #0]
8009cf6: 619a str r2, [r3, #24]
8009cf8: e00e b.n 8009d18 <USB_EPStartXfer+0x13e0>
}
else
{
len = ep->xfer_len;
8009cfa: f507 7384 add.w r3, r7, #264 @ 0x108
8009cfe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009d02: 681b ldr r3, [r3, #0]
8009d04: 699b ldr r3, [r3, #24]
8009d06: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
8009d0a: f507 7384 add.w r3, r7, #264 @ 0x108
8009d0e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009d12: 681b ldr r3, [r3, #0]
8009d14: 2200 movs r2, #0
8009d16: 619a str r2, [r3, #24]
}
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
8009d18: f507 7384 add.w r3, r7, #264 @ 0x108
8009d1c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009d20: 681b ldr r3, [r3, #0]
8009d22: 785b ldrb r3, [r3, #1]
8009d24: 2b00 cmp r3, #0
8009d26: f040 8085 bne.w 8009e34 <USB_EPStartXfer+0x14fc>
8009d2a: f507 7384 add.w r3, r7, #264 @ 0x108
8009d2e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009d32: 681b ldr r3, [r3, #0]
8009d34: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8009d38: f507 7384 add.w r3, r7, #264 @ 0x108
8009d3c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009d40: 681b ldr r3, [r3, #0]
8009d42: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009d46: b29b uxth r3, r3
8009d48: 461a mov r2, r3
8009d4a: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8009d4e: 4413 add r3, r2
8009d50: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8009d54: f507 7384 add.w r3, r7, #264 @ 0x108
8009d58: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009d5c: 681b ldr r3, [r3, #0]
8009d5e: 781b ldrb r3, [r3, #0]
8009d60: 011a lsls r2, r3, #4
8009d62: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8009d66: 4413 add r3, r2
8009d68: f203 4304 addw r3, r3, #1028 @ 0x404
8009d6c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8009d70: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009d74: 881b ldrh r3, [r3, #0]
8009d76: b29b uxth r3, r3
8009d78: f3c3 0309 ubfx r3, r3, #0, #10
8009d7c: b29a uxth r2, r3
8009d7e: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009d82: 801a strh r2, [r3, #0]
8009d84: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009d88: 2b3e cmp r3, #62 @ 0x3e
8009d8a: d923 bls.n 8009dd4 <USB_EPStartXfer+0x149c>
8009d8c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009d90: 095b lsrs r3, r3, #5
8009d92: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8009d96: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009d9a: f003 031f and.w r3, r3, #31
8009d9e: 2b00 cmp r3, #0
8009da0: d104 bne.n 8009dac <USB_EPStartXfer+0x1474>
8009da2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8009da6: 3b01 subs r3, #1
8009da8: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8009dac: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009db0: 881b ldrh r3, [r3, #0]
8009db2: b29a uxth r2, r3
8009db4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8009db8: b29b uxth r3, r3
8009dba: 029b lsls r3, r3, #10
8009dbc: b29b uxth r3, r3
8009dbe: 4313 orrs r3, r2
8009dc0: b29b uxth r3, r3
8009dc2: ea6f 4343 mvn.w r3, r3, lsl #17
8009dc6: ea6f 4353 mvn.w r3, r3, lsr #17
8009dca: b29a uxth r2, r3
8009dcc: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009dd0: 801a strh r2, [r3, #0]
8009dd2: e060 b.n 8009e96 <USB_EPStartXfer+0x155e>
8009dd4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009dd8: 2b00 cmp r3, #0
8009dda: d10c bne.n 8009df6 <USB_EPStartXfer+0x14be>
8009ddc: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009de0: 881b ldrh r3, [r3, #0]
8009de2: b29b uxth r3, r3
8009de4: ea6f 4343 mvn.w r3, r3, lsl #17
8009de8: ea6f 4353 mvn.w r3, r3, lsr #17
8009dec: b29a uxth r2, r3
8009dee: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009df2: 801a strh r2, [r3, #0]
8009df4: e04f b.n 8009e96 <USB_EPStartXfer+0x155e>
8009df6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009dfa: 085b lsrs r3, r3, #1
8009dfc: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8009e00: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009e04: f003 0301 and.w r3, r3, #1
8009e08: 2b00 cmp r3, #0
8009e0a: d004 beq.n 8009e16 <USB_EPStartXfer+0x14de>
8009e0c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8009e10: 3301 adds r3, #1
8009e12: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8009e16: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009e1a: 881b ldrh r3, [r3, #0]
8009e1c: b29a uxth r2, r3
8009e1e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8009e22: b29b uxth r3, r3
8009e24: 029b lsls r3, r3, #10
8009e26: b29b uxth r3, r3
8009e28: 4313 orrs r3, r2
8009e2a: b29a uxth r2, r3
8009e2c: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8009e30: 801a strh r2, [r3, #0]
8009e32: e030 b.n 8009e96 <USB_EPStartXfer+0x155e>
8009e34: f507 7384 add.w r3, r7, #264 @ 0x108
8009e38: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009e3c: 681b ldr r3, [r3, #0]
8009e3e: 785b ldrb r3, [r3, #1]
8009e40: 2b01 cmp r3, #1
8009e42: d128 bne.n 8009e96 <USB_EPStartXfer+0x155e>
8009e44: f507 7384 add.w r3, r7, #264 @ 0x108
8009e48: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009e4c: 681b ldr r3, [r3, #0]
8009e4e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8009e52: f507 7384 add.w r3, r7, #264 @ 0x108
8009e56: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009e5a: 681b ldr r3, [r3, #0]
8009e5c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009e60: b29b uxth r3, r3
8009e62: 461a mov r2, r3
8009e64: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8009e68: 4413 add r3, r2
8009e6a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8009e6e: f507 7384 add.w r3, r7, #264 @ 0x108
8009e72: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009e76: 681b ldr r3, [r3, #0]
8009e78: 781b ldrb r3, [r3, #0]
8009e7a: 011a lsls r2, r3, #4
8009e7c: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8009e80: 4413 add r3, r2
8009e82: f203 4304 addw r3, r3, #1028 @ 0x404
8009e86: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8009e8a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009e8e: b29a uxth r2, r3
8009e90: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
8009e94: 801a strh r2, [r3, #0]
8009e96: f507 7384 add.w r3, r7, #264 @ 0x108
8009e9a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009e9e: 681b ldr r3, [r3, #0]
8009ea0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8009ea4: f507 7384 add.w r3, r7, #264 @ 0x108
8009ea8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009eac: 681b ldr r3, [r3, #0]
8009eae: 785b ldrb r3, [r3, #1]
8009eb0: 2b00 cmp r3, #0
8009eb2: f040 8085 bne.w 8009fc0 <USB_EPStartXfer+0x1688>
8009eb6: f507 7384 add.w r3, r7, #264 @ 0x108
8009eba: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009ebe: 681b ldr r3, [r3, #0]
8009ec0: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8009ec4: f507 7384 add.w r3, r7, #264 @ 0x108
8009ec8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009ecc: 681b ldr r3, [r3, #0]
8009ece: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009ed2: b29b uxth r3, r3
8009ed4: 461a mov r2, r3
8009ed6: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8009eda: 4413 add r3, r2
8009edc: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8009ee0: f507 7384 add.w r3, r7, #264 @ 0x108
8009ee4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009ee8: 681b ldr r3, [r3, #0]
8009eea: 781b ldrb r3, [r3, #0]
8009eec: 011a lsls r2, r3, #4
8009eee: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8009ef2: 4413 add r3, r2
8009ef4: f203 430c addw r3, r3, #1036 @ 0x40c
8009ef8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8009efc: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009f00: 881b ldrh r3, [r3, #0]
8009f02: b29b uxth r3, r3
8009f04: f3c3 0309 ubfx r3, r3, #0, #10
8009f08: b29a uxth r2, r3
8009f0a: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009f0e: 801a strh r2, [r3, #0]
8009f10: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009f14: 2b3e cmp r3, #62 @ 0x3e
8009f16: d923 bls.n 8009f60 <USB_EPStartXfer+0x1628>
8009f18: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009f1c: 095b lsrs r3, r3, #5
8009f1e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8009f22: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009f26: f003 031f and.w r3, r3, #31
8009f2a: 2b00 cmp r3, #0
8009f2c: d104 bne.n 8009f38 <USB_EPStartXfer+0x1600>
8009f2e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8009f32: 3b01 subs r3, #1
8009f34: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8009f38: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009f3c: 881b ldrh r3, [r3, #0]
8009f3e: b29a uxth r2, r3
8009f40: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8009f44: b29b uxth r3, r3
8009f46: 029b lsls r3, r3, #10
8009f48: b29b uxth r3, r3
8009f4a: 4313 orrs r3, r2
8009f4c: b29b uxth r3, r3
8009f4e: ea6f 4343 mvn.w r3, r3, lsl #17
8009f52: ea6f 4353 mvn.w r3, r3, lsr #17
8009f56: b29a uxth r2, r3
8009f58: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009f5c: 801a strh r2, [r3, #0]
8009f5e: e05c b.n 800a01a <USB_EPStartXfer+0x16e2>
8009f60: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009f64: 2b00 cmp r3, #0
8009f66: d10c bne.n 8009f82 <USB_EPStartXfer+0x164a>
8009f68: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009f6c: 881b ldrh r3, [r3, #0]
8009f6e: b29b uxth r3, r3
8009f70: ea6f 4343 mvn.w r3, r3, lsl #17
8009f74: ea6f 4353 mvn.w r3, r3, lsr #17
8009f78: b29a uxth r2, r3
8009f7a: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009f7e: 801a strh r2, [r3, #0]
8009f80: e04b b.n 800a01a <USB_EPStartXfer+0x16e2>
8009f82: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009f86: 085b lsrs r3, r3, #1
8009f88: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8009f8c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8009f90: f003 0301 and.w r3, r3, #1
8009f94: 2b00 cmp r3, #0
8009f96: d004 beq.n 8009fa2 <USB_EPStartXfer+0x166a>
8009f98: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8009f9c: 3301 adds r3, #1
8009f9e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8009fa2: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009fa6: 881b ldrh r3, [r3, #0]
8009fa8: b29a uxth r2, r3
8009faa: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8009fae: b29b uxth r3, r3
8009fb0: 029b lsls r3, r3, #10
8009fb2: b29b uxth r3, r3
8009fb4: 4313 orrs r3, r2
8009fb6: b29a uxth r2, r3
8009fb8: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8009fbc: 801a strh r2, [r3, #0]
8009fbe: e02c b.n 800a01a <USB_EPStartXfer+0x16e2>
8009fc0: f507 7384 add.w r3, r7, #264 @ 0x108
8009fc4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009fc8: 681b ldr r3, [r3, #0]
8009fca: 785b ldrb r3, [r3, #1]
8009fcc: 2b01 cmp r3, #1
8009fce: d124 bne.n 800a01a <USB_EPStartXfer+0x16e2>
8009fd0: f507 7384 add.w r3, r7, #264 @ 0x108
8009fd4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8009fd8: 681b ldr r3, [r3, #0]
8009fda: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009fde: b29b uxth r3, r3
8009fe0: 461a mov r2, r3
8009fe2: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8009fe6: 4413 add r3, r2
8009fe8: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8009fec: f507 7384 add.w r3, r7, #264 @ 0x108
8009ff0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8009ff4: 681b ldr r3, [r3, #0]
8009ff6: 781b ldrb r3, [r3, #0]
8009ff8: 011a lsls r2, r3, #4
8009ffa: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8009ffe: 4413 add r3, r2
800a000: f203 430c addw r3, r3, #1036 @ 0x40c
800a004: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
800a008: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800a00c: b29a uxth r2, r3
800a00e: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
800a012: 801a strh r2, [r3, #0]
800a014: e001 b.n 800a01a <USB_EPStartXfer+0x16e2>
}
else
{
return HAL_ERROR;
800a016: 2301 movs r3, #1
800a018: e03a b.n 800a090 <USB_EPStartXfer+0x1758>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800a01a: f507 7384 add.w r3, r7, #264 @ 0x108
800a01e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800a022: 681a ldr r2, [r3, #0]
800a024: f507 7384 add.w r3, r7, #264 @ 0x108
800a028: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800a02c: 681b ldr r3, [r3, #0]
800a02e: 781b ldrb r3, [r3, #0]
800a030: 009b lsls r3, r3, #2
800a032: 4413 add r3, r2
800a034: 881b ldrh r3, [r3, #0]
800a036: b29b uxth r3, r3
800a038: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800a03c: f023 0370 bic.w r3, r3, #112 @ 0x70
800a040: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
800a044: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
800a048: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800a04c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
800a050: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
800a054: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800a058: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
800a05c: f507 7384 add.w r3, r7, #264 @ 0x108
800a060: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800a064: 681a ldr r2, [r3, #0]
800a066: f507 7384 add.w r3, r7, #264 @ 0x108
800a06a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800a06e: 681b ldr r3, [r3, #0]
800a070: 781b ldrb r3, [r3, #0]
800a072: 009b lsls r3, r3, #2
800a074: 441a add r2, r3
800a076: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
800a07a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a07e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a082: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800a086: f043 0380 orr.w r3, r3, #128 @ 0x80
800a08a: b29b uxth r3, r3
800a08c: 8013 strh r3, [r2, #0]
}
return HAL_OK;
800a08e: 2300 movs r3, #0
}
800a090: 4618 mov r0, r3
800a092: f507 7784 add.w r7, r7, #264 @ 0x108
800a096: 46bd mov sp, r7
800a098: bd80 pop {r7, pc}
0800a09a <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800a09a: b480 push {r7}
800a09c: b085 sub sp, #20
800a09e: af00 add r7, sp, #0
800a0a0: 6078 str r0, [r7, #4]
800a0a2: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
800a0a4: 683b ldr r3, [r7, #0]
800a0a6: 785b ldrb r3, [r3, #1]
800a0a8: 2b00 cmp r3, #0
800a0aa: d020 beq.n 800a0ee <USB_EPSetStall+0x54>
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
800a0ac: 687a ldr r2, [r7, #4]
800a0ae: 683b ldr r3, [r7, #0]
800a0b0: 781b ldrb r3, [r3, #0]
800a0b2: 009b lsls r3, r3, #2
800a0b4: 4413 add r3, r2
800a0b6: 881b ldrh r3, [r3, #0]
800a0b8: b29b uxth r3, r3
800a0ba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800a0be: f023 0340 bic.w r3, r3, #64 @ 0x40
800a0c2: 81bb strh r3, [r7, #12]
800a0c4: 89bb ldrh r3, [r7, #12]
800a0c6: f083 0310 eor.w r3, r3, #16
800a0ca: 81bb strh r3, [r7, #12]
800a0cc: 687a ldr r2, [r7, #4]
800a0ce: 683b ldr r3, [r7, #0]
800a0d0: 781b ldrb r3, [r3, #0]
800a0d2: 009b lsls r3, r3, #2
800a0d4: 441a add r2, r3
800a0d6: 89bb ldrh r3, [r7, #12]
800a0d8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a0dc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a0e0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800a0e4: f043 0380 orr.w r3, r3, #128 @ 0x80
800a0e8: b29b uxth r3, r3
800a0ea: 8013 strh r3, [r2, #0]
800a0ec: e01f b.n 800a12e <USB_EPSetStall+0x94>
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
800a0ee: 687a ldr r2, [r7, #4]
800a0f0: 683b ldr r3, [r7, #0]
800a0f2: 781b ldrb r3, [r3, #0]
800a0f4: 009b lsls r3, r3, #2
800a0f6: 4413 add r3, r2
800a0f8: 881b ldrh r3, [r3, #0]
800a0fa: b29b uxth r3, r3
800a0fc: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800a100: f023 0370 bic.w r3, r3, #112 @ 0x70
800a104: 81fb strh r3, [r7, #14]
800a106: 89fb ldrh r3, [r7, #14]
800a108: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800a10c: 81fb strh r3, [r7, #14]
800a10e: 687a ldr r2, [r7, #4]
800a110: 683b ldr r3, [r7, #0]
800a112: 781b ldrb r3, [r3, #0]
800a114: 009b lsls r3, r3, #2
800a116: 441a add r2, r3
800a118: 89fb ldrh r3, [r7, #14]
800a11a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a11e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a122: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800a126: f043 0380 orr.w r3, r3, #128 @ 0x80
800a12a: b29b uxth r3, r3
800a12c: 8013 strh r3, [r2, #0]
}
return HAL_OK;
800a12e: 2300 movs r3, #0
}
800a130: 4618 mov r0, r3
800a132: 3714 adds r7, #20
800a134: 46bd mov sp, r7
800a136: bc80 pop {r7}
800a138: 4770 bx lr
0800a13a <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800a13a: b480 push {r7}
800a13c: b087 sub sp, #28
800a13e: af00 add r7, sp, #0
800a140: 6078 str r0, [r7, #4]
800a142: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
800a144: 683b ldr r3, [r7, #0]
800a146: 7b1b ldrb r3, [r3, #12]
800a148: 2b00 cmp r3, #0
800a14a: f040 809d bne.w 800a288 <USB_EPClearStall+0x14e>
{
if (ep->is_in != 0U)
800a14e: 683b ldr r3, [r7, #0]
800a150: 785b ldrb r3, [r3, #1]
800a152: 2b00 cmp r3, #0
800a154: d04c beq.n 800a1f0 <USB_EPClearStall+0xb6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800a156: 687a ldr r2, [r7, #4]
800a158: 683b ldr r3, [r7, #0]
800a15a: 781b ldrb r3, [r3, #0]
800a15c: 009b lsls r3, r3, #2
800a15e: 4413 add r3, r2
800a160: 881b ldrh r3, [r3, #0]
800a162: 823b strh r3, [r7, #16]
800a164: 8a3b ldrh r3, [r7, #16]
800a166: f003 0340 and.w r3, r3, #64 @ 0x40
800a16a: 2b00 cmp r3, #0
800a16c: d01b beq.n 800a1a6 <USB_EPClearStall+0x6c>
800a16e: 687a ldr r2, [r7, #4]
800a170: 683b ldr r3, [r7, #0]
800a172: 781b ldrb r3, [r3, #0]
800a174: 009b lsls r3, r3, #2
800a176: 4413 add r3, r2
800a178: 881b ldrh r3, [r3, #0]
800a17a: b29b uxth r3, r3
800a17c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800a180: f023 0370 bic.w r3, r3, #112 @ 0x70
800a184: 81fb strh r3, [r7, #14]
800a186: 687a ldr r2, [r7, #4]
800a188: 683b ldr r3, [r7, #0]
800a18a: 781b ldrb r3, [r3, #0]
800a18c: 009b lsls r3, r3, #2
800a18e: 441a add r2, r3
800a190: 89fb ldrh r3, [r7, #14]
800a192: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a196: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a19a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800a19e: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800a1a2: b29b uxth r3, r3
800a1a4: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800a1a6: 683b ldr r3, [r7, #0]
800a1a8: 78db ldrb r3, [r3, #3]
800a1aa: 2b01 cmp r3, #1
800a1ac: d06c beq.n 800a288 <USB_EPClearStall+0x14e>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
800a1ae: 687a ldr r2, [r7, #4]
800a1b0: 683b ldr r3, [r7, #0]
800a1b2: 781b ldrb r3, [r3, #0]
800a1b4: 009b lsls r3, r3, #2
800a1b6: 4413 add r3, r2
800a1b8: 881b ldrh r3, [r3, #0]
800a1ba: b29b uxth r3, r3
800a1bc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800a1c0: f023 0340 bic.w r3, r3, #64 @ 0x40
800a1c4: 81bb strh r3, [r7, #12]
800a1c6: 89bb ldrh r3, [r7, #12]
800a1c8: f083 0320 eor.w r3, r3, #32
800a1cc: 81bb strh r3, [r7, #12]
800a1ce: 687a ldr r2, [r7, #4]
800a1d0: 683b ldr r3, [r7, #0]
800a1d2: 781b ldrb r3, [r3, #0]
800a1d4: 009b lsls r3, r3, #2
800a1d6: 441a add r2, r3
800a1d8: 89bb ldrh r3, [r7, #12]
800a1da: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a1de: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a1e2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800a1e6: f043 0380 orr.w r3, r3, #128 @ 0x80
800a1ea: b29b uxth r3, r3
800a1ec: 8013 strh r3, [r2, #0]
800a1ee: e04b b.n 800a288 <USB_EPClearStall+0x14e>
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800a1f0: 687a ldr r2, [r7, #4]
800a1f2: 683b ldr r3, [r7, #0]
800a1f4: 781b ldrb r3, [r3, #0]
800a1f6: 009b lsls r3, r3, #2
800a1f8: 4413 add r3, r2
800a1fa: 881b ldrh r3, [r3, #0]
800a1fc: 82fb strh r3, [r7, #22]
800a1fe: 8afb ldrh r3, [r7, #22]
800a200: f403 4380 and.w r3, r3, #16384 @ 0x4000
800a204: 2b00 cmp r3, #0
800a206: d01b beq.n 800a240 <USB_EPClearStall+0x106>
800a208: 687a ldr r2, [r7, #4]
800a20a: 683b ldr r3, [r7, #0]
800a20c: 781b ldrb r3, [r3, #0]
800a20e: 009b lsls r3, r3, #2
800a210: 4413 add r3, r2
800a212: 881b ldrh r3, [r3, #0]
800a214: b29b uxth r3, r3
800a216: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800a21a: f023 0370 bic.w r3, r3, #112 @ 0x70
800a21e: 82bb strh r3, [r7, #20]
800a220: 687a ldr r2, [r7, #4]
800a222: 683b ldr r3, [r7, #0]
800a224: 781b ldrb r3, [r3, #0]
800a226: 009b lsls r3, r3, #2
800a228: 441a add r2, r3
800a22a: 8abb ldrh r3, [r7, #20]
800a22c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a230: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a234: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800a238: f043 0380 orr.w r3, r3, #128 @ 0x80
800a23c: b29b uxth r3, r3
800a23e: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800a240: 687a ldr r2, [r7, #4]
800a242: 683b ldr r3, [r7, #0]
800a244: 781b ldrb r3, [r3, #0]
800a246: 009b lsls r3, r3, #2
800a248: 4413 add r3, r2
800a24a: 881b ldrh r3, [r3, #0]
800a24c: b29b uxth r3, r3
800a24e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800a252: f023 0370 bic.w r3, r3, #112 @ 0x70
800a256: 827b strh r3, [r7, #18]
800a258: 8a7b ldrh r3, [r7, #18]
800a25a: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800a25e: 827b strh r3, [r7, #18]
800a260: 8a7b ldrh r3, [r7, #18]
800a262: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800a266: 827b strh r3, [r7, #18]
800a268: 687a ldr r2, [r7, #4]
800a26a: 683b ldr r3, [r7, #0]
800a26c: 781b ldrb r3, [r3, #0]
800a26e: 009b lsls r3, r3, #2
800a270: 441a add r2, r3
800a272: 8a7b ldrh r3, [r7, #18]
800a274: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800a278: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800a27c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800a280: f043 0380 orr.w r3, r3, #128 @ 0x80
800a284: b29b uxth r3, r3
800a286: 8013 strh r3, [r2, #0]
}
}
return HAL_OK;
800a288: 2300 movs r3, #0
}
800a28a: 4618 mov r0, r3
800a28c: 371c adds r7, #28
800a28e: 46bd mov sp, r7
800a290: bc80 pop {r7}
800a292: 4770 bx lr
0800a294 <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
800a294: b480 push {r7}
800a296: b083 sub sp, #12
800a298: af00 add r7, sp, #0
800a29a: 6078 str r0, [r7, #4]
800a29c: 460b mov r3, r1
800a29e: 70fb strb r3, [r7, #3]
if (address == 0U)
800a2a0: 78fb ldrb r3, [r7, #3]
800a2a2: 2b00 cmp r3, #0
800a2a4: d103 bne.n 800a2ae <USB_SetDevAddress+0x1a>
{
/* set device address and enable function */
USBx->DADDR = (uint16_t)USB_DADDR_EF;
800a2a6: 687b ldr r3, [r7, #4]
800a2a8: 2280 movs r2, #128 @ 0x80
800a2aa: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
}
return HAL_OK;
800a2ae: 2300 movs r3, #0
}
800a2b0: 4618 mov r0, r3
800a2b2: 370c adds r7, #12
800a2b4: 46bd mov sp, r7
800a2b6: bc80 pop {r7}
800a2b8: 4770 bx lr
0800a2ba <USB_DevConnect>:
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
800a2ba: b480 push {r7}
800a2bc: b083 sub sp, #12
800a2be: af00 add r7, sp, #0
800a2c0: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
800a2c2: 2300 movs r3, #0
}
800a2c4: 4618 mov r0, r3
800a2c6: 370c adds r7, #12
800a2c8: 46bd mov sp, r7
800a2ca: bc80 pop {r7}
800a2cc: 4770 bx lr
0800a2ce <USB_DevDisconnect>:
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
800a2ce: b480 push {r7}
800a2d0: b083 sub sp, #12
800a2d2: af00 add r7, sp, #0
800a2d4: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
800a2d6: 2300 movs r3, #0
}
800a2d8: 4618 mov r0, r3
800a2da: 370c adds r7, #12
800a2dc: 46bd mov sp, r7
800a2de: bc80 pop {r7}
800a2e0: 4770 bx lr
0800a2e2 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
800a2e2: b480 push {r7}
800a2e4: b085 sub sp, #20
800a2e6: af00 add r7, sp, #0
800a2e8: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->ISTR;
800a2ea: 687b ldr r3, [r7, #4]
800a2ec: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
800a2f0: b29b uxth r3, r3
800a2f2: 60fb str r3, [r7, #12]
return tmpreg;
800a2f4: 68fb ldr r3, [r7, #12]
}
800a2f6: 4618 mov r0, r3
800a2f8: 3714 adds r7, #20
800a2fa: 46bd mov sp, r7
800a2fc: bc80 pop {r7}
800a2fe: 4770 bx lr
0800a300 <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
800a300: b480 push {r7}
800a302: b083 sub sp, #12
800a304: af00 add r7, sp, #0
800a306: 6078 str r0, [r7, #4]
800a308: 6039 str r1, [r7, #0]
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
800a30a: 2300 movs r3, #0
}
800a30c: 4618 mov r0, r3
800a30e: 370c adds r7, #12
800a310: 46bd mov sp, r7
800a312: bc80 pop {r7}
800a314: 4770 bx lr
0800a316 <USB_WritePMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
800a316: b480 push {r7}
800a318: b08b sub sp, #44 @ 0x2c
800a31a: af00 add r7, sp, #0
800a31c: 60f8 str r0, [r7, #12]
800a31e: 60b9 str r1, [r7, #8]
800a320: 4611 mov r1, r2
800a322: 461a mov r2, r3
800a324: 460b mov r3, r1
800a326: 80fb strh r3, [r7, #6]
800a328: 4613 mov r3, r2
800a32a: 80bb strh r3, [r7, #4]
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
800a32c: 88bb ldrh r3, [r7, #4]
800a32e: 3301 adds r3, #1
800a330: 085b lsrs r3, r3, #1
800a332: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
800a334: 68fb ldr r3, [r7, #12]
800a336: 617b str r3, [r7, #20]
uint32_t count;
uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
800a338: 68bb ldr r3, [r7, #8]
800a33a: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
800a33c: 88fb ldrh r3, [r7, #6]
800a33e: 005a lsls r2, r3, #1
800a340: 697b ldr r3, [r7, #20]
800a342: 4413 add r3, r2
800a344: f503 6380 add.w r3, r3, #1024 @ 0x400
800a348: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800a34a: 69bb ldr r3, [r7, #24]
800a34c: 627b str r3, [r7, #36] @ 0x24
800a34e: e01f b.n 800a390 <USB_WritePMA+0x7a>
{
WrVal = pBuf[0];
800a350: 69fb ldr r3, [r7, #28]
800a352: 781b ldrb r3, [r3, #0]
800a354: 827b strh r3, [r7, #18]
WrVal |= (uint16_t)pBuf[1] << 8;
800a356: 69fb ldr r3, [r7, #28]
800a358: 3301 adds r3, #1
800a35a: 781b ldrb r3, [r3, #0]
800a35c: b21b sxth r3, r3
800a35e: 021b lsls r3, r3, #8
800a360: b21a sxth r2, r3
800a362: f9b7 3012 ldrsh.w r3, [r7, #18]
800a366: 4313 orrs r3, r2
800a368: b21b sxth r3, r3
800a36a: 827b strh r3, [r7, #18]
*pdwVal = (WrVal & 0xFFFFU);
800a36c: 6a3b ldr r3, [r7, #32]
800a36e: 8a7a ldrh r2, [r7, #18]
800a370: 801a strh r2, [r3, #0]
pdwVal++;
800a372: 6a3b ldr r3, [r7, #32]
800a374: 3302 adds r3, #2
800a376: 623b str r3, [r7, #32]
#if PMA_ACCESS > 1U
pdwVal++;
800a378: 6a3b ldr r3, [r7, #32]
800a37a: 3302 adds r3, #2
800a37c: 623b str r3, [r7, #32]
#endif /* PMA_ACCESS */
pBuf++;
800a37e: 69fb ldr r3, [r7, #28]
800a380: 3301 adds r3, #1
800a382: 61fb str r3, [r7, #28]
pBuf++;
800a384: 69fb ldr r3, [r7, #28]
800a386: 3301 adds r3, #1
800a388: 61fb str r3, [r7, #28]
for (count = n; count != 0U; count--)
800a38a: 6a7b ldr r3, [r7, #36] @ 0x24
800a38c: 3b01 subs r3, #1
800a38e: 627b str r3, [r7, #36] @ 0x24
800a390: 6a7b ldr r3, [r7, #36] @ 0x24
800a392: 2b00 cmp r3, #0
800a394: d1dc bne.n 800a350 <USB_WritePMA+0x3a>
}
}
800a396: bf00 nop
800a398: bf00 nop
800a39a: 372c adds r7, #44 @ 0x2c
800a39c: 46bd mov sp, r7
800a39e: bc80 pop {r7}
800a3a0: 4770 bx lr
0800a3a2 <USB_ReadPMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
800a3a2: b480 push {r7}
800a3a4: b08b sub sp, #44 @ 0x2c
800a3a6: af00 add r7, sp, #0
800a3a8: 60f8 str r0, [r7, #12]
800a3aa: 60b9 str r1, [r7, #8]
800a3ac: 4611 mov r1, r2
800a3ae: 461a mov r2, r3
800a3b0: 460b mov r3, r1
800a3b2: 80fb strh r3, [r7, #6]
800a3b4: 4613 mov r3, r2
800a3b6: 80bb strh r3, [r7, #4]
uint32_t n = (uint32_t)wNBytes >> 1;
800a3b8: 88bb ldrh r3, [r7, #4]
800a3ba: 085b lsrs r3, r3, #1
800a3bc: b29b uxth r3, r3
800a3be: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
800a3c0: 68fb ldr r3, [r7, #12]
800a3c2: 617b str r3, [r7, #20]
uint32_t count;
uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
800a3c4: 68bb ldr r3, [r7, #8]
800a3c6: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
800a3c8: 88fb ldrh r3, [r7, #6]
800a3ca: 005a lsls r2, r3, #1
800a3cc: 697b ldr r3, [r7, #20]
800a3ce: 4413 add r3, r2
800a3d0: f503 6380 add.w r3, r3, #1024 @ 0x400
800a3d4: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800a3d6: 69bb ldr r3, [r7, #24]
800a3d8: 627b str r3, [r7, #36] @ 0x24
800a3da: e01b b.n 800a414 <USB_ReadPMA+0x72>
{
RdVal = *(__IO uint16_t *)pdwVal;
800a3dc: 6a3b ldr r3, [r7, #32]
800a3de: 881b ldrh r3, [r3, #0]
800a3e0: b29b uxth r3, r3
800a3e2: 613b str r3, [r7, #16]
pdwVal++;
800a3e4: 6a3b ldr r3, [r7, #32]
800a3e6: 3302 adds r3, #2
800a3e8: 623b str r3, [r7, #32]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
800a3ea: 693b ldr r3, [r7, #16]
800a3ec: b2da uxtb r2, r3
800a3ee: 69fb ldr r3, [r7, #28]
800a3f0: 701a strb r2, [r3, #0]
pBuf++;
800a3f2: 69fb ldr r3, [r7, #28]
800a3f4: 3301 adds r3, #1
800a3f6: 61fb str r3, [r7, #28]
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
800a3f8: 693b ldr r3, [r7, #16]
800a3fa: 0a1b lsrs r3, r3, #8
800a3fc: b2da uxtb r2, r3
800a3fe: 69fb ldr r3, [r7, #28]
800a400: 701a strb r2, [r3, #0]
pBuf++;
800a402: 69fb ldr r3, [r7, #28]
800a404: 3301 adds r3, #1
800a406: 61fb str r3, [r7, #28]
#if PMA_ACCESS > 1U
pdwVal++;
800a408: 6a3b ldr r3, [r7, #32]
800a40a: 3302 adds r3, #2
800a40c: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800a40e: 6a7b ldr r3, [r7, #36] @ 0x24
800a410: 3b01 subs r3, #1
800a412: 627b str r3, [r7, #36] @ 0x24
800a414: 6a7b ldr r3, [r7, #36] @ 0x24
800a416: 2b00 cmp r3, #0
800a418: d1e0 bne.n 800a3dc <USB_ReadPMA+0x3a>
#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
800a41a: 88bb ldrh r3, [r7, #4]
800a41c: f003 0301 and.w r3, r3, #1
800a420: b29b uxth r3, r3
800a422: 2b00 cmp r3, #0
800a424: d007 beq.n 800a436 <USB_ReadPMA+0x94>
{
RdVal = *pdwVal;
800a426: 6a3b ldr r3, [r7, #32]
800a428: 881b ldrh r3, [r3, #0]
800a42a: b29b uxth r3, r3
800a42c: 613b str r3, [r7, #16]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
800a42e: 693b ldr r3, [r7, #16]
800a430: b2da uxtb r2, r3
800a432: 69fb ldr r3, [r7, #28]
800a434: 701a strb r2, [r3, #0]
}
}
800a436: bf00 nop
800a438: 372c adds r7, #44 @ 0x2c
800a43a: 46bd mov sp, r7
800a43c: bc80 pop {r7}
800a43e: 4770 bx lr
0800a440 <USBD_CDC_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800a440: b580 push {r7, lr}
800a442: b084 sub sp, #16
800a444: af00 add r7, sp, #0
800a446: 6078 str r0, [r7, #4]
800a448: 460b mov r3, r1
800a44a: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
800a44c: 2300 movs r3, #0
800a44e: 73fb strb r3, [r7, #15]
USBD_CDC_HandleTypeDef *hcdc;
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a450: 687b ldr r3, [r7, #4]
800a452: 7c1b ldrb r3, [r3, #16]
800a454: 2b00 cmp r3, #0
800a456: d115 bne.n 800a484 <USBD_CDC_Init+0x44>
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
800a458: f44f 7300 mov.w r3, #512 @ 0x200
800a45c: 2202 movs r2, #2
800a45e: 2181 movs r1, #129 @ 0x81
800a460: 6878 ldr r0, [r7, #4]
800a462: f001 ff00 bl 800c266 <USBD_LL_OpenEP>
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
800a466: 687b ldr r3, [r7, #4]
800a468: 2201 movs r2, #1
800a46a: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
800a46c: f44f 7300 mov.w r3, #512 @ 0x200
800a470: 2202 movs r2, #2
800a472: 2101 movs r1, #1
800a474: 6878 ldr r0, [r7, #4]
800a476: f001 fef6 bl 800c266 <USBD_LL_OpenEP>
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
800a47a: 687b ldr r3, [r7, #4]
800a47c: 2201 movs r2, #1
800a47e: f8c3 216c str.w r2, [r3, #364] @ 0x16c
800a482: e012 b.n 800a4aa <USBD_CDC_Init+0x6a>
}
else
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
800a484: 2340 movs r3, #64 @ 0x40
800a486: 2202 movs r2, #2
800a488: 2181 movs r1, #129 @ 0x81
800a48a: 6878 ldr r0, [r7, #4]
800a48c: f001 feeb bl 800c266 <USBD_LL_OpenEP>
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
800a490: 687b ldr r3, [r7, #4]
800a492: 2201 movs r2, #1
800a494: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
800a496: 2340 movs r3, #64 @ 0x40
800a498: 2202 movs r2, #2
800a49a: 2101 movs r1, #1
800a49c: 6878 ldr r0, [r7, #4]
800a49e: f001 fee2 bl 800c266 <USBD_LL_OpenEP>
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
800a4a2: 687b ldr r3, [r7, #4]
800a4a4: 2201 movs r2, #1
800a4a6: f8c3 216c str.w r2, [r3, #364] @ 0x16c
}
/* Open Command IN EP */
USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
800a4aa: 2308 movs r3, #8
800a4ac: 2203 movs r2, #3
800a4ae: 2182 movs r1, #130 @ 0x82
800a4b0: 6878 ldr r0, [r7, #4]
800a4b2: f001 fed8 bl 800c266 <USBD_LL_OpenEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
800a4b6: 687b ldr r3, [r7, #4]
800a4b8: 2201 movs r2, #1
800a4ba: 641a str r2, [r3, #64] @ 0x40
pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
800a4bc: f44f 7007 mov.w r0, #540 @ 0x21c
800a4c0: f001 fff8 bl 800c4b4 <USBD_static_malloc>
800a4c4: 4602 mov r2, r0
800a4c6: 687b ldr r3, [r7, #4]
800a4c8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClassData == NULL)
800a4cc: 687b ldr r3, [r7, #4]
800a4ce: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a4d2: 2b00 cmp r3, #0
800a4d4: d102 bne.n 800a4dc <USBD_CDC_Init+0x9c>
{
ret = 1U;
800a4d6: 2301 movs r3, #1
800a4d8: 73fb strb r3, [r7, #15]
800a4da: e026 b.n 800a52a <USBD_CDC_Init+0xea>
}
else
{
hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a4dc: 687b ldr r3, [r7, #4]
800a4de: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a4e2: 60bb str r3, [r7, #8]
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
800a4e4: 687b ldr r3, [r7, #4]
800a4e6: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a4ea: 681b ldr r3, [r3, #0]
800a4ec: 4798 blx r3
/* Init Xfer states */
hcdc->TxState = 0U;
800a4ee: 68bb ldr r3, [r7, #8]
800a4f0: 2200 movs r2, #0
800a4f2: f8c3 2214 str.w r2, [r3, #532] @ 0x214
hcdc->RxState = 0U;
800a4f6: 68bb ldr r3, [r7, #8]
800a4f8: 2200 movs r2, #0
800a4fa: f8c3 2218 str.w r2, [r3, #536] @ 0x218
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a4fe: 687b ldr r3, [r7, #4]
800a500: 7c1b ldrb r3, [r3, #16]
800a502: 2b00 cmp r3, #0
800a504: d109 bne.n 800a51a <USBD_CDC_Init+0xda>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
800a506: 68bb ldr r3, [r7, #8]
800a508: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800a50c: f44f 7300 mov.w r3, #512 @ 0x200
800a510: 2101 movs r1, #1
800a512: 6878 ldr r0, [r7, #4]
800a514: f001 ff97 bl 800c446 <USBD_LL_PrepareReceive>
800a518: e007 b.n 800a52a <USBD_CDC_Init+0xea>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
800a51a: 68bb ldr r3, [r7, #8]
800a51c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800a520: 2340 movs r3, #64 @ 0x40
800a522: 2101 movs r1, #1
800a524: 6878 ldr r0, [r7, #4]
800a526: f001 ff8e bl 800c446 <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
}
return ret;
800a52a: 7bfb ldrb r3, [r7, #15]
}
800a52c: 4618 mov r0, r3
800a52e: 3710 adds r7, #16
800a530: 46bd mov sp, r7
800a532: bd80 pop {r7, pc}
0800a534 <USBD_CDC_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800a534: b580 push {r7, lr}
800a536: b084 sub sp, #16
800a538: af00 add r7, sp, #0
800a53a: 6078 str r0, [r7, #4]
800a53c: 460b mov r3, r1
800a53e: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
800a540: 2300 movs r3, #0
800a542: 73fb strb r3, [r7, #15]
/* Close EP IN */
USBD_LL_CloseEP(pdev, CDC_IN_EP);
800a544: 2181 movs r1, #129 @ 0x81
800a546: 6878 ldr r0, [r7, #4]
800a548: f001 feb3 bl 800c2b2 <USBD_LL_CloseEP>
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
800a54c: 687b ldr r3, [r7, #4]
800a54e: 2200 movs r2, #0
800a550: 62da str r2, [r3, #44] @ 0x2c
/* Close EP OUT */
USBD_LL_CloseEP(pdev, CDC_OUT_EP);
800a552: 2101 movs r1, #1
800a554: 6878 ldr r0, [r7, #4]
800a556: f001 feac bl 800c2b2 <USBD_LL_CloseEP>
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
800a55a: 687b ldr r3, [r7, #4]
800a55c: 2200 movs r2, #0
800a55e: f8c3 216c str.w r2, [r3, #364] @ 0x16c
/* Close Command IN EP */
USBD_LL_CloseEP(pdev, CDC_CMD_EP);
800a562: 2182 movs r1, #130 @ 0x82
800a564: 6878 ldr r0, [r7, #4]
800a566: f001 fea4 bl 800c2b2 <USBD_LL_CloseEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
800a56a: 687b ldr r3, [r7, #4]
800a56c: 2200 movs r2, #0
800a56e: 641a str r2, [r3, #64] @ 0x40
/* DeInit physical Interface components */
if (pdev->pClassData != NULL)
800a570: 687b ldr r3, [r7, #4]
800a572: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a576: 2b00 cmp r3, #0
800a578: d00e beq.n 800a598 <USBD_CDC_DeInit+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
800a57a: 687b ldr r3, [r7, #4]
800a57c: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a580: 685b ldr r3, [r3, #4]
800a582: 4798 blx r3
USBD_free(pdev->pClassData);
800a584: 687b ldr r3, [r7, #4]
800a586: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a58a: 4618 mov r0, r3
800a58c: f001 ff9e bl 800c4cc <USBD_static_free>
pdev->pClassData = NULL;
800a590: 687b ldr r3, [r7, #4]
800a592: 2200 movs r2, #0
800a594: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
}
return ret;
800a598: 7bfb ldrb r3, [r7, #15]
}
800a59a: 4618 mov r0, r3
800a59c: 3710 adds r7, #16
800a59e: 46bd mov sp, r7
800a5a0: bd80 pop {r7, pc}
0800a5a2 <USBD_CDC_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800a5a2: b580 push {r7, lr}
800a5a4: b086 sub sp, #24
800a5a6: af00 add r7, sp, #0
800a5a8: 6078 str r0, [r7, #4]
800a5aa: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a5ac: 687b ldr r3, [r7, #4]
800a5ae: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a5b2: 613b str r3, [r7, #16]
uint8_t ifalt = 0U;
800a5b4: 2300 movs r3, #0
800a5b6: 73fb strb r3, [r7, #15]
uint16_t status_info = 0U;
800a5b8: 2300 movs r3, #0
800a5ba: 81bb strh r3, [r7, #12]
uint8_t ret = USBD_OK;
800a5bc: 2300 movs r3, #0
800a5be: 75fb strb r3, [r7, #23]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800a5c0: 683b ldr r3, [r7, #0]
800a5c2: 781b ldrb r3, [r3, #0]
800a5c4: f003 0360 and.w r3, r3, #96 @ 0x60
800a5c8: 2b00 cmp r3, #0
800a5ca: d039 beq.n 800a640 <USBD_CDC_Setup+0x9e>
800a5cc: 2b20 cmp r3, #32
800a5ce: d17f bne.n 800a6d0 <USBD_CDC_Setup+0x12e>
{
case USB_REQ_TYPE_CLASS :
if (req->wLength)
800a5d0: 683b ldr r3, [r7, #0]
800a5d2: 88db ldrh r3, [r3, #6]
800a5d4: 2b00 cmp r3, #0
800a5d6: d029 beq.n 800a62c <USBD_CDC_Setup+0x8a>
{
if (req->bmRequest & 0x80U)
800a5d8: 683b ldr r3, [r7, #0]
800a5da: 781b ldrb r3, [r3, #0]
800a5dc: b25b sxtb r3, r3
800a5de: 2b00 cmp r3, #0
800a5e0: da11 bge.n 800a606 <USBD_CDC_Setup+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
800a5e2: 687b ldr r3, [r7, #4]
800a5e4: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a5e8: 689b ldr r3, [r3, #8]
800a5ea: 683a ldr r2, [r7, #0]
800a5ec: 7850 ldrb r0, [r2, #1]
(uint8_t *)(void *)hcdc->data,
800a5ee: 6939 ldr r1, [r7, #16]
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
800a5f0: 683a ldr r2, [r7, #0]
800a5f2: 88d2 ldrh r2, [r2, #6]
800a5f4: 4798 blx r3
req->wLength);
USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
800a5f6: 6939 ldr r1, [r7, #16]
800a5f8: 683b ldr r3, [r7, #0]
800a5fa: 88db ldrh r3, [r3, #6]
800a5fc: 461a mov r2, r3
800a5fe: 6878 ldr r0, [r7, #4]
800a600: f001 fa06 bl 800ba10 <USBD_CtlSendData>
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
(uint8_t *)(void *)req, 0U);
}
break;
800a604: e06b b.n 800a6de <USBD_CDC_Setup+0x13c>
hcdc->CmdOpCode = req->bRequest;
800a606: 683b ldr r3, [r7, #0]
800a608: 785a ldrb r2, [r3, #1]
800a60a: 693b ldr r3, [r7, #16]
800a60c: f883 2200 strb.w r2, [r3, #512] @ 0x200
hcdc->CmdLength = (uint8_t)req->wLength;
800a610: 683b ldr r3, [r7, #0]
800a612: 88db ldrh r3, [r3, #6]
800a614: b2da uxtb r2, r3
800a616: 693b ldr r3, [r7, #16]
800a618: f883 2201 strb.w r2, [r3, #513] @ 0x201
USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
800a61c: 6939 ldr r1, [r7, #16]
800a61e: 683b ldr r3, [r7, #0]
800a620: 88db ldrh r3, [r3, #6]
800a622: 461a mov r2, r3
800a624: 6878 ldr r0, [r7, #4]
800a626: f001 fa21 bl 800ba6c <USBD_CtlPrepareRx>
break;
800a62a: e058 b.n 800a6de <USBD_CDC_Setup+0x13c>
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
800a62c: 687b ldr r3, [r7, #4]
800a62e: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a632: 689b ldr r3, [r3, #8]
800a634: 683a ldr r2, [r7, #0]
800a636: 7850 ldrb r0, [r2, #1]
800a638: 2200 movs r2, #0
800a63a: 6839 ldr r1, [r7, #0]
800a63c: 4798 blx r3
break;
800a63e: e04e b.n 800a6de <USBD_CDC_Setup+0x13c>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
800a640: 683b ldr r3, [r7, #0]
800a642: 785b ldrb r3, [r3, #1]
800a644: 2b0b cmp r3, #11
800a646: d02e beq.n 800a6a6 <USBD_CDC_Setup+0x104>
800a648: 2b0b cmp r3, #11
800a64a: dc38 bgt.n 800a6be <USBD_CDC_Setup+0x11c>
800a64c: 2b00 cmp r3, #0
800a64e: d002 beq.n 800a656 <USBD_CDC_Setup+0xb4>
800a650: 2b0a cmp r3, #10
800a652: d014 beq.n 800a67e <USBD_CDC_Setup+0xdc>
800a654: e033 b.n 800a6be <USBD_CDC_Setup+0x11c>
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a656: 687b ldr r3, [r7, #4]
800a658: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a65c: 2b03 cmp r3, #3
800a65e: d107 bne.n 800a670 <USBD_CDC_Setup+0xce>
{
USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
800a660: f107 030c add.w r3, r7, #12
800a664: 2202 movs r2, #2
800a666: 4619 mov r1, r3
800a668: 6878 ldr r0, [r7, #4]
800a66a: f001 f9d1 bl 800ba10 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800a66e: e02e b.n 800a6ce <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
800a670: 6839 ldr r1, [r7, #0]
800a672: 6878 ldr r0, [r7, #4]
800a674: f001 f962 bl 800b93c <USBD_CtlError>
ret = USBD_FAIL;
800a678: 2302 movs r3, #2
800a67a: 75fb strb r3, [r7, #23]
break;
800a67c: e027 b.n 800a6ce <USBD_CDC_Setup+0x12c>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800a67e: 687b ldr r3, [r7, #4]
800a680: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a684: 2b03 cmp r3, #3
800a686: d107 bne.n 800a698 <USBD_CDC_Setup+0xf6>
{
USBD_CtlSendData(pdev, &ifalt, 1U);
800a688: f107 030f add.w r3, r7, #15
800a68c: 2201 movs r2, #1
800a68e: 4619 mov r1, r3
800a690: 6878 ldr r0, [r7, #4]
800a692: f001 f9bd bl 800ba10 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800a696: e01a b.n 800a6ce <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
800a698: 6839 ldr r1, [r7, #0]
800a69a: 6878 ldr r0, [r7, #4]
800a69c: f001 f94e bl 800b93c <USBD_CtlError>
ret = USBD_FAIL;
800a6a0: 2302 movs r3, #2
800a6a2: 75fb strb r3, [r7, #23]
break;
800a6a4: e013 b.n 800a6ce <USBD_CDC_Setup+0x12c>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
800a6a6: 687b ldr r3, [r7, #4]
800a6a8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800a6ac: 2b03 cmp r3, #3
800a6ae: d00d beq.n 800a6cc <USBD_CDC_Setup+0x12a>
{
USBD_CtlError(pdev, req);
800a6b0: 6839 ldr r1, [r7, #0]
800a6b2: 6878 ldr r0, [r7, #4]
800a6b4: f001 f942 bl 800b93c <USBD_CtlError>
ret = USBD_FAIL;
800a6b8: 2302 movs r3, #2
800a6ba: 75fb strb r3, [r7, #23]
}
break;
800a6bc: e006 b.n 800a6cc <USBD_CDC_Setup+0x12a>
default:
USBD_CtlError(pdev, req);
800a6be: 6839 ldr r1, [r7, #0]
800a6c0: 6878 ldr r0, [r7, #4]
800a6c2: f001 f93b bl 800b93c <USBD_CtlError>
ret = USBD_FAIL;
800a6c6: 2302 movs r3, #2
800a6c8: 75fb strb r3, [r7, #23]
break;
800a6ca: e000 b.n 800a6ce <USBD_CDC_Setup+0x12c>
break;
800a6cc: bf00 nop
}
break;
800a6ce: e006 b.n 800a6de <USBD_CDC_Setup+0x13c>
default:
USBD_CtlError(pdev, req);
800a6d0: 6839 ldr r1, [r7, #0]
800a6d2: 6878 ldr r0, [r7, #4]
800a6d4: f001 f932 bl 800b93c <USBD_CtlError>
ret = USBD_FAIL;
800a6d8: 2302 movs r3, #2
800a6da: 75fb strb r3, [r7, #23]
break;
800a6dc: bf00 nop
}
return ret;
800a6de: 7dfb ldrb r3, [r7, #23]
}
800a6e0: 4618 mov r0, r3
800a6e2: 3718 adds r7, #24
800a6e4: 46bd mov sp, r7
800a6e6: bd80 pop {r7, pc}
0800a6e8 <USBD_CDC_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
800a6e8: b580 push {r7, lr}
800a6ea: b084 sub sp, #16
800a6ec: af00 add r7, sp, #0
800a6ee: 6078 str r0, [r7, #4]
800a6f0: 460b mov r3, r1
800a6f2: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
800a6f4: 687b ldr r3, [r7, #4]
800a6f6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a6fa: 60fb str r3, [r7, #12]
PCD_HandleTypeDef *hpcd = pdev->pData;
800a6fc: 687b ldr r3, [r7, #4]
800a6fe: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800a702: 60bb str r3, [r7, #8]
if (pdev->pClassData != NULL)
800a704: 687b ldr r3, [r7, #4]
800a706: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a70a: 2b00 cmp r3, #0
800a70c: d03a beq.n 800a784 <USBD_CDC_DataIn+0x9c>
{
if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
800a70e: 78fa ldrb r2, [r7, #3]
800a710: 6879 ldr r1, [r7, #4]
800a712: 4613 mov r3, r2
800a714: 009b lsls r3, r3, #2
800a716: 4413 add r3, r2
800a718: 009b lsls r3, r3, #2
800a71a: 440b add r3, r1
800a71c: 331c adds r3, #28
800a71e: 681b ldr r3, [r3, #0]
800a720: 2b00 cmp r3, #0
800a722: d029 beq.n 800a778 <USBD_CDC_DataIn+0x90>
800a724: 78fa ldrb r2, [r7, #3]
800a726: 6879 ldr r1, [r7, #4]
800a728: 4613 mov r3, r2
800a72a: 009b lsls r3, r3, #2
800a72c: 4413 add r3, r2
800a72e: 009b lsls r3, r3, #2
800a730: 440b add r3, r1
800a732: 331c adds r3, #28
800a734: 681a ldr r2, [r3, #0]
800a736: 78f9 ldrb r1, [r7, #3]
800a738: 68b8 ldr r0, [r7, #8]
800a73a: 460b mov r3, r1
800a73c: 009b lsls r3, r3, #2
800a73e: 440b add r3, r1
800a740: 00db lsls r3, r3, #3
800a742: 4403 add r3, r0
800a744: 3320 adds r3, #32
800a746: 681b ldr r3, [r3, #0]
800a748: fbb2 f1f3 udiv r1, r2, r3
800a74c: fb01 f303 mul.w r3, r1, r3
800a750: 1ad3 subs r3, r2, r3
800a752: 2b00 cmp r3, #0
800a754: d110 bne.n 800a778 <USBD_CDC_DataIn+0x90>
{
/* Update the packet total length */
pdev->ep_in[epnum].total_length = 0U;
800a756: 78fa ldrb r2, [r7, #3]
800a758: 6879 ldr r1, [r7, #4]
800a75a: 4613 mov r3, r2
800a75c: 009b lsls r3, r3, #2
800a75e: 4413 add r3, r2
800a760: 009b lsls r3, r3, #2
800a762: 440b add r3, r1
800a764: 331c adds r3, #28
800a766: 2200 movs r2, #0
800a768: 601a str r2, [r3, #0]
/* Send ZLP */
USBD_LL_Transmit(pdev, epnum, NULL, 0U);
800a76a: 78f9 ldrb r1, [r7, #3]
800a76c: 2300 movs r3, #0
800a76e: 2200 movs r2, #0
800a770: 6878 ldr r0, [r7, #4]
800a772: f001 fe45 bl 800c400 <USBD_LL_Transmit>
800a776: e003 b.n 800a780 <USBD_CDC_DataIn+0x98>
}
else
{
hcdc->TxState = 0U;
800a778: 68fb ldr r3, [r7, #12]
800a77a: 2200 movs r2, #0
800a77c: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
return USBD_OK;
800a780: 2300 movs r3, #0
800a782: e000 b.n 800a786 <USBD_CDC_DataIn+0x9e>
}
else
{
return USBD_FAIL;
800a784: 2302 movs r3, #2
}
}
800a786: 4618 mov r0, r3
800a788: 3710 adds r7, #16
800a78a: 46bd mov sp, r7
800a78c: bd80 pop {r7, pc}
0800a78e <USBD_CDC_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
800a78e: b580 push {r7, lr}
800a790: b084 sub sp, #16
800a792: af00 add r7, sp, #0
800a794: 6078 str r0, [r7, #4]
800a796: 460b mov r3, r1
800a798: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a79a: 687b ldr r3, [r7, #4]
800a79c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a7a0: 60fb str r3, [r7, #12]
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
800a7a2: 78fb ldrb r3, [r7, #3]
800a7a4: 4619 mov r1, r3
800a7a6: 6878 ldr r0, [r7, #4]
800a7a8: f001 fe70 bl 800c48c <USBD_LL_GetRxDataSize>
800a7ac: 4602 mov r2, r0
800a7ae: 68fb ldr r3, [r7, #12]
800a7b0: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
if (pdev->pClassData != NULL)
800a7b4: 687b ldr r3, [r7, #4]
800a7b6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a7ba: 2b00 cmp r3, #0
800a7bc: d00d beq.n 800a7da <USBD_CDC_DataOut+0x4c>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
800a7be: 687b ldr r3, [r7, #4]
800a7c0: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a7c4: 68db ldr r3, [r3, #12]
800a7c6: 68fa ldr r2, [r7, #12]
800a7c8: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
800a7cc: 68fa ldr r2, [r7, #12]
800a7ce: f502 7203 add.w r2, r2, #524 @ 0x20c
800a7d2: 4611 mov r1, r2
800a7d4: 4798 blx r3
return USBD_OK;
800a7d6: 2300 movs r3, #0
800a7d8: e000 b.n 800a7dc <USBD_CDC_DataOut+0x4e>
}
else
{
return USBD_FAIL;
800a7da: 2302 movs r3, #2
}
}
800a7dc: 4618 mov r0, r3
800a7de: 3710 adds r7, #16
800a7e0: 46bd mov sp, r7
800a7e2: bd80 pop {r7, pc}
0800a7e4 <USBD_CDC_EP0_RxReady>:
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
800a7e4: b580 push {r7, lr}
800a7e6: b084 sub sp, #16
800a7e8: af00 add r7, sp, #0
800a7ea: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a7ec: 687b ldr r3, [r7, #4]
800a7ee: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a7f2: 60fb str r3, [r7, #12]
if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
800a7f4: 687b ldr r3, [r7, #4]
800a7f6: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a7fa: 2b00 cmp r3, #0
800a7fc: d014 beq.n 800a828 <USBD_CDC_EP0_RxReady+0x44>
800a7fe: 68fb ldr r3, [r7, #12]
800a800: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
800a804: 2bff cmp r3, #255 @ 0xff
800a806: d00f beq.n 800a828 <USBD_CDC_EP0_RxReady+0x44>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
800a808: 687b ldr r3, [r7, #4]
800a80a: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
800a80e: 689b ldr r3, [r3, #8]
800a810: 68fa ldr r2, [r7, #12]
800a812: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
(uint8_t *)(void *)hcdc->data,
800a816: 68f9 ldr r1, [r7, #12]
(uint16_t)hcdc->CmdLength);
800a818: 68fa ldr r2, [r7, #12]
800a81a: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
800a81e: 4798 blx r3
hcdc->CmdOpCode = 0xFFU;
800a820: 68fb ldr r3, [r7, #12]
800a822: 22ff movs r2, #255 @ 0xff
800a824: f883 2200 strb.w r2, [r3, #512] @ 0x200
}
return USBD_OK;
800a828: 2300 movs r3, #0
}
800a82a: 4618 mov r0, r3
800a82c: 3710 adds r7, #16
800a82e: 46bd mov sp, r7
800a830: bd80 pop {r7, pc}
...
0800a834 <USBD_CDC_GetFSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
800a834: b480 push {r7}
800a836: b083 sub sp, #12
800a838: af00 add r7, sp, #0
800a83a: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgFSDesc);
800a83c: 687b ldr r3, [r7, #4]
800a83e: 2243 movs r2, #67 @ 0x43
800a840: 801a strh r2, [r3, #0]
return USBD_CDC_CfgFSDesc;
800a842: 4b03 ldr r3, [pc, #12] @ (800a850 <USBD_CDC_GetFSCfgDesc+0x1c>)
}
800a844: 4618 mov r0, r3
800a846: 370c adds r7, #12
800a848: 46bd mov sp, r7
800a84a: bc80 pop {r7}
800a84c: 4770 bx lr
800a84e: bf00 nop
800a850: 2000009c .word 0x2000009c
0800a854 <USBD_CDC_GetHSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
800a854: b480 push {r7}
800a856: b083 sub sp, #12
800a858: af00 add r7, sp, #0
800a85a: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgHSDesc);
800a85c: 687b ldr r3, [r7, #4]
800a85e: 2243 movs r2, #67 @ 0x43
800a860: 801a strh r2, [r3, #0]
return USBD_CDC_CfgHSDesc;
800a862: 4b03 ldr r3, [pc, #12] @ (800a870 <USBD_CDC_GetHSCfgDesc+0x1c>)
}
800a864: 4618 mov r0, r3
800a866: 370c adds r7, #12
800a868: 46bd mov sp, r7
800a86a: bc80 pop {r7}
800a86c: 4770 bx lr
800a86e: bf00 nop
800a870: 20000058 .word 0x20000058
0800a874 <USBD_CDC_GetOtherSpeedCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
800a874: b480 push {r7}
800a876: b083 sub sp, #12
800a878: af00 add r7, sp, #0
800a87a: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_OtherSpeedCfgDesc);
800a87c: 687b ldr r3, [r7, #4]
800a87e: 2243 movs r2, #67 @ 0x43
800a880: 801a strh r2, [r3, #0]
return USBD_CDC_OtherSpeedCfgDesc;
800a882: 4b03 ldr r3, [pc, #12] @ (800a890 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
}
800a884: 4618 mov r0, r3
800a886: 370c adds r7, #12
800a888: 46bd mov sp, r7
800a88a: bc80 pop {r7}
800a88c: 4770 bx lr
800a88e: bf00 nop
800a890: 200000e0 .word 0x200000e0
0800a894 <USBD_CDC_GetDeviceQualifierDescriptor>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
800a894: b480 push {r7}
800a896: b083 sub sp, #12
800a898: af00 add r7, sp, #0
800a89a: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_DeviceQualifierDesc);
800a89c: 687b ldr r3, [r7, #4]
800a89e: 220a movs r2, #10
800a8a0: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceQualifierDesc;
800a8a2: 4b03 ldr r3, [pc, #12] @ (800a8b0 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
}
800a8a4: 4618 mov r0, r3
800a8a6: 370c adds r7, #12
800a8a8: 46bd mov sp, r7
800a8aa: bc80 pop {r7}
800a8ac: 4770 bx lr
800a8ae: bf00 nop
800a8b0: 20000014 .word 0x20000014
0800a8b4 <USBD_CDC_RegisterInterface>:
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
800a8b4: b480 push {r7}
800a8b6: b085 sub sp, #20
800a8b8: af00 add r7, sp, #0
800a8ba: 6078 str r0, [r7, #4]
800a8bc: 6039 str r1, [r7, #0]
uint8_t ret = USBD_FAIL;
800a8be: 2302 movs r3, #2
800a8c0: 73fb strb r3, [r7, #15]
if (fops != NULL)
800a8c2: 683b ldr r3, [r7, #0]
800a8c4: 2b00 cmp r3, #0
800a8c6: d005 beq.n 800a8d4 <USBD_CDC_RegisterInterface+0x20>
{
pdev->pUserData = fops;
800a8c8: 687b ldr r3, [r7, #4]
800a8ca: 683a ldr r2, [r7, #0]
800a8cc: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
ret = USBD_OK;
800a8d0: 2300 movs r3, #0
800a8d2: 73fb strb r3, [r7, #15]
}
return ret;
800a8d4: 7bfb ldrb r3, [r7, #15]
}
800a8d6: 4618 mov r0, r3
800a8d8: 3714 adds r7, #20
800a8da: 46bd mov sp, r7
800a8dc: bc80 pop {r7}
800a8de: 4770 bx lr
0800a8e0 <USBD_CDC_SetTxBuffer>:
* @retval status
*/
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff,
uint16_t length)
{
800a8e0: b480 push {r7}
800a8e2: b087 sub sp, #28
800a8e4: af00 add r7, sp, #0
800a8e6: 60f8 str r0, [r7, #12]
800a8e8: 60b9 str r1, [r7, #8]
800a8ea: 4613 mov r3, r2
800a8ec: 80fb strh r3, [r7, #6]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a8ee: 68fb ldr r3, [r7, #12]
800a8f0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a8f4: 617b str r3, [r7, #20]
hcdc->TxBuffer = pbuff;
800a8f6: 697b ldr r3, [r7, #20]
800a8f8: 68ba ldr r2, [r7, #8]
800a8fa: f8c3 2208 str.w r2, [r3, #520] @ 0x208
hcdc->TxLength = length;
800a8fe: 88fa ldrh r2, [r7, #6]
800a900: 697b ldr r3, [r7, #20]
800a902: f8c3 2210 str.w r2, [r3, #528] @ 0x210
return USBD_OK;
800a906: 2300 movs r3, #0
}
800a908: 4618 mov r0, r3
800a90a: 371c adds r7, #28
800a90c: 46bd mov sp, r7
800a90e: bc80 pop {r7}
800a910: 4770 bx lr
0800a912 <USBD_CDC_SetRxBuffer>:
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff)
{
800a912: b480 push {r7}
800a914: b085 sub sp, #20
800a916: af00 add r7, sp, #0
800a918: 6078 str r0, [r7, #4]
800a91a: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a91c: 687b ldr r3, [r7, #4]
800a91e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a922: 60fb str r3, [r7, #12]
hcdc->RxBuffer = pbuff;
800a924: 68fb ldr r3, [r7, #12]
800a926: 683a ldr r2, [r7, #0]
800a928: f8c3 2204 str.w r2, [r3, #516] @ 0x204
return USBD_OK;
800a92c: 2300 movs r3, #0
}
800a92e: 4618 mov r0, r3
800a930: 3714 adds r7, #20
800a932: 46bd mov sp, r7
800a934: bc80 pop {r7}
800a936: 4770 bx lr
0800a938 <USBD_CDC_TransmitPacket>:
* Transmit packet on IN endpoint
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
800a938: b580 push {r7, lr}
800a93a: b084 sub sp, #16
800a93c: af00 add r7, sp, #0
800a93e: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a940: 687b ldr r3, [r7, #4]
800a942: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a946: 60fb str r3, [r7, #12]
if (pdev->pClassData != NULL)
800a948: 687b ldr r3, [r7, #4]
800a94a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a94e: 2b00 cmp r3, #0
800a950: d01c beq.n 800a98c <USBD_CDC_TransmitPacket+0x54>
{
if (hcdc->TxState == 0U)
800a952: 68fb ldr r3, [r7, #12]
800a954: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800a958: 2b00 cmp r3, #0
800a95a: d115 bne.n 800a988 <USBD_CDC_TransmitPacket+0x50>
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
800a95c: 68fb ldr r3, [r7, #12]
800a95e: 2201 movs r2, #1
800a960: f8c3 2214 str.w r2, [r3, #532] @ 0x214
/* Update the packet total length */
pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
800a964: 68fb ldr r3, [r7, #12]
800a966: f8d3 2210 ldr.w r2, [r3, #528] @ 0x210
800a96a: 687b ldr r3, [r7, #4]
800a96c: 631a str r2, [r3, #48] @ 0x30
/* Transmit next packet */
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
800a96e: 68fb ldr r3, [r7, #12]
800a970: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
(uint16_t)hcdc->TxLength);
800a974: 68fb ldr r3, [r7, #12]
800a976: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
800a97a: b29b uxth r3, r3
800a97c: 2181 movs r1, #129 @ 0x81
800a97e: 6878 ldr r0, [r7, #4]
800a980: f001 fd3e bl 800c400 <USBD_LL_Transmit>
return USBD_OK;
800a984: 2300 movs r3, #0
800a986: e002 b.n 800a98e <USBD_CDC_TransmitPacket+0x56>
}
else
{
return USBD_BUSY;
800a988: 2301 movs r3, #1
800a98a: e000 b.n 800a98e <USBD_CDC_TransmitPacket+0x56>
}
}
else
{
return USBD_FAIL;
800a98c: 2302 movs r3, #2
}
}
800a98e: 4618 mov r0, r3
800a990: 3710 adds r7, #16
800a992: 46bd mov sp, r7
800a994: bd80 pop {r7, pc}
0800a996 <USBD_CDC_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
800a996: b580 push {r7, lr}
800a998: b084 sub sp, #16
800a99a: af00 add r7, sp, #0
800a99c: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800a99e: 687b ldr r3, [r7, #4]
800a9a0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a9a4: 60fb str r3, [r7, #12]
/* Suspend or Resume USB Out process */
if (pdev->pClassData != NULL)
800a9a6: 687b ldr r3, [r7, #4]
800a9a8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800a9ac: 2b00 cmp r3, #0
800a9ae: d017 beq.n 800a9e0 <USBD_CDC_ReceivePacket+0x4a>
{
if (pdev->dev_speed == USBD_SPEED_HIGH)
800a9b0: 687b ldr r3, [r7, #4]
800a9b2: 7c1b ldrb r3, [r3, #16]
800a9b4: 2b00 cmp r3, #0
800a9b6: d109 bne.n 800a9cc <USBD_CDC_ReceivePacket+0x36>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
800a9b8: 68fb ldr r3, [r7, #12]
800a9ba: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800a9be: f44f 7300 mov.w r3, #512 @ 0x200
800a9c2: 2101 movs r1, #1
800a9c4: 6878 ldr r0, [r7, #4]
800a9c6: f001 fd3e bl 800c446 <USBD_LL_PrepareReceive>
800a9ca: e007 b.n 800a9dc <USBD_CDC_ReceivePacket+0x46>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
800a9cc: 68fb ldr r3, [r7, #12]
800a9ce: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800a9d2: 2340 movs r3, #64 @ 0x40
800a9d4: 2101 movs r1, #1
800a9d6: 6878 ldr r0, [r7, #4]
800a9d8: f001 fd35 bl 800c446 <USBD_LL_PrepareReceive>
CDC_OUT_EP,
hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return USBD_OK;
800a9dc: 2300 movs r3, #0
800a9de: e000 b.n 800a9e2 <USBD_CDC_ReceivePacket+0x4c>
}
else
{
return USBD_FAIL;
800a9e0: 2302 movs r3, #2
}
}
800a9e2: 4618 mov r0, r3
800a9e4: 3710 adds r7, #16
800a9e6: 46bd mov sp, r7
800a9e8: bd80 pop {r7, pc}
0800a9ea <USBD_Init>:
* @param id: Low level core index
* @retval None
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
800a9ea: b580 push {r7, lr}
800a9ec: b084 sub sp, #16
800a9ee: af00 add r7, sp, #0
800a9f0: 60f8 str r0, [r7, #12]
800a9f2: 60b9 str r1, [r7, #8]
800a9f4: 4613 mov r3, r2
800a9f6: 71fb strb r3, [r7, #7]
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
800a9f8: 68fb ldr r3, [r7, #12]
800a9fa: 2b00 cmp r3, #0
800a9fc: d101 bne.n 800aa02 <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif
return USBD_FAIL;
800a9fe: 2302 movs r3, #2
800aa00: e01a b.n 800aa38 <USBD_Init+0x4e>
}
/* Unlink previous class*/
if (pdev->pClass != NULL)
800aa02: 68fb ldr r3, [r7, #12]
800aa04: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800aa08: 2b00 cmp r3, #0
800aa0a: d003 beq.n 800aa14 <USBD_Init+0x2a>
{
pdev->pClass = NULL;
800aa0c: 68fb ldr r3, [r7, #12]
800aa0e: 2200 movs r2, #0
800aa10: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Assign USBD Descriptors */
if (pdesc != NULL)
800aa14: 68bb ldr r3, [r7, #8]
800aa16: 2b00 cmp r3, #0
800aa18: d003 beq.n 800aa22 <USBD_Init+0x38>
{
pdev->pDesc = pdesc;
800aa1a: 68fb ldr r3, [r7, #12]
800aa1c: 68ba ldr r2, [r7, #8]
800aa1e: f8c3 22b0 str.w r2, [r3, #688] @ 0x2b0
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
800aa22: 68fb ldr r3, [r7, #12]
800aa24: 2201 movs r2, #1
800aa26: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
800aa2a: 68fb ldr r3, [r7, #12]
800aa2c: 79fa ldrb r2, [r7, #7]
800aa2e: 701a strb r2, [r3, #0]
/* Initialize low level driver */
USBD_LL_Init(pdev);
800aa30: 68f8 ldr r0, [r7, #12]
800aa32: f001 fba3 bl 800c17c <USBD_LL_Init>
return USBD_OK;
800aa36: 2300 movs r3, #0
}
800aa38: 4618 mov r0, r3
800aa3a: 3710 adds r7, #16
800aa3c: 46bd mov sp, r7
800aa3e: bd80 pop {r7, pc}
0800aa40 <USBD_RegisterClass>:
* @param pDevice : Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
800aa40: b480 push {r7}
800aa42: b085 sub sp, #20
800aa44: af00 add r7, sp, #0
800aa46: 6078 str r0, [r7, #4]
800aa48: 6039 str r1, [r7, #0]
USBD_StatusTypeDef status = USBD_OK;
800aa4a: 2300 movs r3, #0
800aa4c: 73fb strb r3, [r7, #15]
if (pclass != NULL)
800aa4e: 683b ldr r3, [r7, #0]
800aa50: 2b00 cmp r3, #0
800aa52: d006 beq.n 800aa62 <USBD_RegisterClass+0x22>
{
/* link the class to the USB Device handle */
pdev->pClass = pclass;
800aa54: 687b ldr r3, [r7, #4]
800aa56: 683a ldr r2, [r7, #0]
800aa58: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
status = USBD_OK;
800aa5c: 2300 movs r3, #0
800aa5e: 73fb strb r3, [r7, #15]
800aa60: e001 b.n 800aa66 <USBD_RegisterClass+0x26>
else
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif
status = USBD_FAIL;
800aa62: 2302 movs r3, #2
800aa64: 73fb strb r3, [r7, #15]
}
return status;
800aa66: 7bfb ldrb r3, [r7, #15]
}
800aa68: 4618 mov r0, r3
800aa6a: 3714 adds r7, #20
800aa6c: 46bd mov sp, r7
800aa6e: bc80 pop {r7}
800aa70: 4770 bx lr
0800aa72 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
800aa72: b580 push {r7, lr}
800aa74: b082 sub sp, #8
800aa76: af00 add r7, sp, #0
800aa78: 6078 str r0, [r7, #4]
/* Start the low level driver */
USBD_LL_Start(pdev);
800aa7a: 6878 ldr r0, [r7, #4]
800aa7c: f001 fbd8 bl 800c230 <USBD_LL_Start>
return USBD_OK;
800aa80: 2300 movs r3, #0
}
800aa82: 4618 mov r0, r3
800aa84: 3708 adds r7, #8
800aa86: 46bd mov sp, r7
800aa88: bd80 pop {r7, pc}
0800aa8a <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
800aa8a: b480 push {r7}
800aa8c: b083 sub sp, #12
800aa8e: af00 add r7, sp, #0
800aa90: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
800aa92: 2300 movs r3, #0
}
800aa94: 4618 mov r0, r3
800aa96: 370c adds r7, #12
800aa98: 46bd mov sp, r7
800aa9a: bc80 pop {r7}
800aa9c: 4770 bx lr
0800aa9e <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800aa9e: b580 push {r7, lr}
800aaa0: b084 sub sp, #16
800aaa2: af00 add r7, sp, #0
800aaa4: 6078 str r0, [r7, #4]
800aaa6: 460b mov r3, r1
800aaa8: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_FAIL;
800aaaa: 2302 movs r3, #2
800aaac: 73fb strb r3, [r7, #15]
if (pdev->pClass != NULL)
800aaae: 687b ldr r3, [r7, #4]
800aab0: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800aab4: 2b00 cmp r3, #0
800aab6: d00c beq.n 800aad2 <USBD_SetClassConfig+0x34>
{
/* Set configuration and Start the Class*/
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
800aab8: 687b ldr r3, [r7, #4]
800aaba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800aabe: 681b ldr r3, [r3, #0]
800aac0: 78fa ldrb r2, [r7, #3]
800aac2: 4611 mov r1, r2
800aac4: 6878 ldr r0, [r7, #4]
800aac6: 4798 blx r3
800aac8: 4603 mov r3, r0
800aaca: 2b00 cmp r3, #0
800aacc: d101 bne.n 800aad2 <USBD_SetClassConfig+0x34>
{
ret = USBD_OK;
800aace: 2300 movs r3, #0
800aad0: 73fb strb r3, [r7, #15]
}
}
return ret;
800aad2: 7bfb ldrb r3, [r7, #15]
}
800aad4: 4618 mov r0, r3
800aad6: 3710 adds r7, #16
800aad8: 46bd mov sp, r7
800aada: bd80 pop {r7, pc}
0800aadc <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status: USBD_StatusTypeDef
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800aadc: b580 push {r7, lr}
800aade: b082 sub sp, #8
800aae0: af00 add r7, sp, #0
800aae2: 6078 str r0, [r7, #4]
800aae4: 460b mov r3, r1
800aae6: 70fb strb r3, [r7, #3]
/* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx);
800aae8: 687b ldr r3, [r7, #4]
800aaea: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800aaee: 685b ldr r3, [r3, #4]
800aaf0: 78fa ldrb r2, [r7, #3]
800aaf2: 4611 mov r1, r2
800aaf4: 6878 ldr r0, [r7, #4]
800aaf6: 4798 blx r3
return USBD_OK;
800aaf8: 2300 movs r3, #0
}
800aafa: 4618 mov r0, r3
800aafc: 3708 adds r7, #8
800aafe: 46bd mov sp, r7
800ab00: bd80 pop {r7, pc}
0800ab02 <USBD_LL_SetupStage>:
* Handle the setup stage
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
800ab02: b580 push {r7, lr}
800ab04: b082 sub sp, #8
800ab06: af00 add r7, sp, #0
800ab08: 6078 str r0, [r7, #4]
800ab0a: 6039 str r1, [r7, #0]
USBD_ParseSetupRequest(&pdev->request, psetup);
800ab0c: 687b ldr r3, [r7, #4]
800ab0e: f503 732a add.w r3, r3, #680 @ 0x2a8
800ab12: 6839 ldr r1, [r7, #0]
800ab14: 4618 mov r0, r3
800ab16: f000 fed8 bl 800b8ca <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
800ab1a: 687b ldr r3, [r7, #4]
800ab1c: 2201 movs r2, #1
800ab1e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
800ab22: 687b ldr r3, [r7, #4]
800ab24: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
800ab28: 461a mov r2, r3
800ab2a: 687b ldr r3, [r7, #4]
800ab2c: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
800ab30: 687b ldr r3, [r7, #4]
800ab32: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
800ab36: f003 031f and.w r3, r3, #31
800ab3a: 2b02 cmp r3, #2
800ab3c: d016 beq.n 800ab6c <USBD_LL_SetupStage+0x6a>
800ab3e: 2b02 cmp r3, #2
800ab40: d81c bhi.n 800ab7c <USBD_LL_SetupStage+0x7a>
800ab42: 2b00 cmp r3, #0
800ab44: d002 beq.n 800ab4c <USBD_LL_SetupStage+0x4a>
800ab46: 2b01 cmp r3, #1
800ab48: d008 beq.n 800ab5c <USBD_LL_SetupStage+0x5a>
800ab4a: e017 b.n 800ab7c <USBD_LL_SetupStage+0x7a>
{
case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq(pdev, &pdev->request);
800ab4c: 687b ldr r3, [r7, #4]
800ab4e: f503 732a add.w r3, r3, #680 @ 0x2a8
800ab52: 4619 mov r1, r3
800ab54: 6878 ldr r0, [r7, #4]
800ab56: f000 f9cb bl 800aef0 <USBD_StdDevReq>
break;
800ab5a: e01a b.n 800ab92 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request);
800ab5c: 687b ldr r3, [r7, #4]
800ab5e: f503 732a add.w r3, r3, #680 @ 0x2a8
800ab62: 4619 mov r1, r3
800ab64: 6878 ldr r0, [r7, #4]
800ab66: f000 fa2d bl 800afc4 <USBD_StdItfReq>
break;
800ab6a: e012 b.n 800ab92 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request);
800ab6c: 687b ldr r3, [r7, #4]
800ab6e: f503 732a add.w r3, r3, #680 @ 0x2a8
800ab72: 4619 mov r1, r3
800ab74: 6878 ldr r0, [r7, #4]
800ab76: f000 fa6d bl 800b054 <USBD_StdEPReq>
break;
800ab7a: e00a b.n 800ab92 <USBD_LL_SetupStage+0x90>
default:
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
800ab7c: 687b ldr r3, [r7, #4]
800ab7e: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
800ab82: f023 037f bic.w r3, r3, #127 @ 0x7f
800ab86: b2db uxtb r3, r3
800ab88: 4619 mov r1, r3
800ab8a: 6878 ldr r0, [r7, #4]
800ab8c: f001 fbb0 bl 800c2f0 <USBD_LL_StallEP>
break;
800ab90: bf00 nop
}
return USBD_OK;
800ab92: 2300 movs r3, #0
}
800ab94: 4618 mov r0, r3
800ab96: 3708 adds r7, #8
800ab98: 46bd mov sp, r7
800ab9a: bd80 pop {r7, pc}
0800ab9c <USBD_LL_DataOutStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
800ab9c: b580 push {r7, lr}
800ab9e: b086 sub sp, #24
800aba0: af00 add r7, sp, #0
800aba2: 60f8 str r0, [r7, #12]
800aba4: 460b mov r3, r1
800aba6: 607a str r2, [r7, #4]
800aba8: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
800abaa: 7afb ldrb r3, [r7, #11]
800abac: 2b00 cmp r3, #0
800abae: d14b bne.n 800ac48 <USBD_LL_DataOutStage+0xac>
{
pep = &pdev->ep_out[0];
800abb0: 68fb ldr r3, [r7, #12]
800abb2: f503 73aa add.w r3, r3, #340 @ 0x154
800abb6: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
800abb8: 68fb ldr r3, [r7, #12]
800abba: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
800abbe: 2b03 cmp r3, #3
800abc0: d134 bne.n 800ac2c <USBD_LL_DataOutStage+0x90>
{
if (pep->rem_length > pep->maxpacket)
800abc2: 697b ldr r3, [r7, #20]
800abc4: 68da ldr r2, [r3, #12]
800abc6: 697b ldr r3, [r7, #20]
800abc8: 691b ldr r3, [r3, #16]
800abca: 429a cmp r2, r3
800abcc: d919 bls.n 800ac02 <USBD_LL_DataOutStage+0x66>
{
pep->rem_length -= pep->maxpacket;
800abce: 697b ldr r3, [r7, #20]
800abd0: 68da ldr r2, [r3, #12]
800abd2: 697b ldr r3, [r7, #20]
800abd4: 691b ldr r3, [r3, #16]
800abd6: 1ad2 subs r2, r2, r3
800abd8: 697b ldr r3, [r7, #20]
800abda: 60da str r2, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
800abdc: 697b ldr r3, [r7, #20]
800abde: 68da ldr r2, [r3, #12]
800abe0: 697b ldr r3, [r7, #20]
800abe2: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
800abe4: 429a cmp r2, r3
800abe6: d203 bcs.n 800abf0 <USBD_LL_DataOutStage+0x54>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
800abe8: 697b ldr r3, [r7, #20]
800abea: 68db ldr r3, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
800abec: b29b uxth r3, r3
800abee: e002 b.n 800abf6 <USBD_LL_DataOutStage+0x5a>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
800abf0: 697b ldr r3, [r7, #20]
800abf2: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
800abf4: b29b uxth r3, r3
800abf6: 461a mov r2, r3
800abf8: 6879 ldr r1, [r7, #4]
800abfa: 68f8 ldr r0, [r7, #12]
800abfc: f000 ff54 bl 800baa8 <USBD_CtlContinueRx>
800ac00: e038 b.n 800ac74 <USBD_LL_DataOutStage+0xd8>
}
else
{
if ((pdev->pClass->EP0_RxReady != NULL) &&
800ac02: 68fb ldr r3, [r7, #12]
800ac04: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ac08: 691b ldr r3, [r3, #16]
800ac0a: 2b00 cmp r3, #0
800ac0c: d00a beq.n 800ac24 <USBD_LL_DataOutStage+0x88>
(pdev->dev_state == USBD_STATE_CONFIGURED))
800ac0e: 68fb ldr r3, [r7, #12]
800ac10: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_RxReady != NULL) &&
800ac14: 2b03 cmp r3, #3
800ac16: d105 bne.n 800ac24 <USBD_LL_DataOutStage+0x88>
{
pdev->pClass->EP0_RxReady(pdev);
800ac18: 68fb ldr r3, [r7, #12]
800ac1a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ac1e: 691b ldr r3, [r3, #16]
800ac20: 68f8 ldr r0, [r7, #12]
800ac22: 4798 blx r3
}
USBD_CtlSendStatus(pdev);
800ac24: 68f8 ldr r0, [r7, #12]
800ac26: f000 ff51 bl 800bacc <USBD_CtlSendStatus>
800ac2a: e023 b.n 800ac74 <USBD_LL_DataOutStage+0xd8>
}
}
else
{
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
800ac2c: 68fb ldr r3, [r7, #12]
800ac2e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
800ac32: 2b05 cmp r3, #5
800ac34: d11e bne.n 800ac74 <USBD_LL_DataOutStage+0xd8>
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
800ac36: 68fb ldr r3, [r7, #12]
800ac38: 2200 movs r2, #0
800ac3a: f8c3 2294 str.w r2, [r3, #660] @ 0x294
USBD_LL_StallEP(pdev, 0U);
800ac3e: 2100 movs r1, #0
800ac40: 68f8 ldr r0, [r7, #12]
800ac42: f001 fb55 bl 800c2f0 <USBD_LL_StallEP>
800ac46: e015 b.n 800ac74 <USBD_LL_DataOutStage+0xd8>
}
}
}
else if ((pdev->pClass->DataOut != NULL) &&
800ac48: 68fb ldr r3, [r7, #12]
800ac4a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ac4e: 699b ldr r3, [r3, #24]
800ac50: 2b00 cmp r3, #0
800ac52: d00d beq.n 800ac70 <USBD_LL_DataOutStage+0xd4>
(pdev->dev_state == USBD_STATE_CONFIGURED))
800ac54: 68fb ldr r3, [r7, #12]
800ac56: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataOut != NULL) &&
800ac5a: 2b03 cmp r3, #3
800ac5c: d108 bne.n 800ac70 <USBD_LL_DataOutStage+0xd4>
{
pdev->pClass->DataOut(pdev, epnum);
800ac5e: 68fb ldr r3, [r7, #12]
800ac60: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ac64: 699b ldr r3, [r3, #24]
800ac66: 7afa ldrb r2, [r7, #11]
800ac68: 4611 mov r1, r2
800ac6a: 68f8 ldr r0, [r7, #12]
800ac6c: 4798 blx r3
800ac6e: e001 b.n 800ac74 <USBD_LL_DataOutStage+0xd8>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
800ac70: 2302 movs r3, #2
800ac72: e000 b.n 800ac76 <USBD_LL_DataOutStage+0xda>
}
return USBD_OK;
800ac74: 2300 movs r3, #0
}
800ac76: 4618 mov r0, r3
800ac78: 3718 adds r7, #24
800ac7a: 46bd mov sp, r7
800ac7c: bd80 pop {r7, pc}
0800ac7e <USBD_LL_DataInStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
800ac7e: b580 push {r7, lr}
800ac80: b086 sub sp, #24
800ac82: af00 add r7, sp, #0
800ac84: 60f8 str r0, [r7, #12]
800ac86: 460b mov r3, r1
800ac88: 607a str r2, [r7, #4]
800ac8a: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
800ac8c: 7afb ldrb r3, [r7, #11]
800ac8e: 2b00 cmp r3, #0
800ac90: d17f bne.n 800ad92 <USBD_LL_DataInStage+0x114>
{
pep = &pdev->ep_in[0];
800ac92: 68fb ldr r3, [r7, #12]
800ac94: 3314 adds r3, #20
800ac96: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
800ac98: 68fb ldr r3, [r7, #12]
800ac9a: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
800ac9e: 2b02 cmp r3, #2
800aca0: d15c bne.n 800ad5c <USBD_LL_DataInStage+0xde>
{
if (pep->rem_length > pep->maxpacket)
800aca2: 697b ldr r3, [r7, #20]
800aca4: 68da ldr r2, [r3, #12]
800aca6: 697b ldr r3, [r7, #20]
800aca8: 691b ldr r3, [r3, #16]
800acaa: 429a cmp r2, r3
800acac: d915 bls.n 800acda <USBD_LL_DataInStage+0x5c>
{
pep->rem_length -= pep->maxpacket;
800acae: 697b ldr r3, [r7, #20]
800acb0: 68da ldr r2, [r3, #12]
800acb2: 697b ldr r3, [r7, #20]
800acb4: 691b ldr r3, [r3, #16]
800acb6: 1ad2 subs r2, r2, r3
800acb8: 697b ldr r3, [r7, #20]
800acba: 60da str r2, [r3, #12]
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
800acbc: 697b ldr r3, [r7, #20]
800acbe: 68db ldr r3, [r3, #12]
800acc0: b29b uxth r3, r3
800acc2: 461a mov r2, r3
800acc4: 6879 ldr r1, [r7, #4]
800acc6: 68f8 ldr r0, [r7, #12]
800acc8: f000 febe bl 800ba48 <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800accc: 2300 movs r3, #0
800acce: 2200 movs r2, #0
800acd0: 2100 movs r1, #0
800acd2: 68f8 ldr r0, [r7, #12]
800acd4: f001 fbb7 bl 800c446 <USBD_LL_PrepareReceive>
800acd8: e04e b.n 800ad78 <USBD_LL_DataInStage+0xfa>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->total_length % pep->maxpacket == 0U) &&
800acda: 697b ldr r3, [r7, #20]
800acdc: 689b ldr r3, [r3, #8]
800acde: 697a ldr r2, [r7, #20]
800ace0: 6912 ldr r2, [r2, #16]
800ace2: fbb3 f1f2 udiv r1, r3, r2
800ace6: fb01 f202 mul.w r2, r1, r2
800acea: 1a9b subs r3, r3, r2
800acec: 2b00 cmp r3, #0
800acee: d11c bne.n 800ad2a <USBD_LL_DataInStage+0xac>
(pep->total_length >= pep->maxpacket) &&
800acf0: 697b ldr r3, [r7, #20]
800acf2: 689a ldr r2, [r3, #8]
800acf4: 697b ldr r3, [r7, #20]
800acf6: 691b ldr r3, [r3, #16]
if ((pep->total_length % pep->maxpacket == 0U) &&
800acf8: 429a cmp r2, r3
800acfa: d316 bcc.n 800ad2a <USBD_LL_DataInStage+0xac>
(pep->total_length < pdev->ep0_data_len))
800acfc: 697b ldr r3, [r7, #20]
800acfe: 689a ldr r2, [r3, #8]
800ad00: 68fb ldr r3, [r7, #12]
800ad02: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
800ad06: 429a cmp r2, r3
800ad08: d20f bcs.n 800ad2a <USBD_LL_DataInStage+0xac>
{
USBD_CtlContinueSendData(pdev, NULL, 0U);
800ad0a: 2200 movs r2, #0
800ad0c: 2100 movs r1, #0
800ad0e: 68f8 ldr r0, [r7, #12]
800ad10: f000 fe9a bl 800ba48 <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
800ad14: 68fb ldr r3, [r7, #12]
800ad16: 2200 movs r2, #0
800ad18: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800ad1c: 2300 movs r3, #0
800ad1e: 2200 movs r2, #0
800ad20: 2100 movs r1, #0
800ad22: 68f8 ldr r0, [r7, #12]
800ad24: f001 fb8f bl 800c446 <USBD_LL_PrepareReceive>
800ad28: e026 b.n 800ad78 <USBD_LL_DataInStage+0xfa>
}
else
{
if ((pdev->pClass->EP0_TxSent != NULL) &&
800ad2a: 68fb ldr r3, [r7, #12]
800ad2c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ad30: 68db ldr r3, [r3, #12]
800ad32: 2b00 cmp r3, #0
800ad34: d00a beq.n 800ad4c <USBD_LL_DataInStage+0xce>
(pdev->dev_state == USBD_STATE_CONFIGURED))
800ad36: 68fb ldr r3, [r7, #12]
800ad38: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_TxSent != NULL) &&
800ad3c: 2b03 cmp r3, #3
800ad3e: d105 bne.n 800ad4c <USBD_LL_DataInStage+0xce>
{
pdev->pClass->EP0_TxSent(pdev);
800ad40: 68fb ldr r3, [r7, #12]
800ad42: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ad46: 68db ldr r3, [r3, #12]
800ad48: 68f8 ldr r0, [r7, #12]
800ad4a: 4798 blx r3
}
USBD_LL_StallEP(pdev, 0x80U);
800ad4c: 2180 movs r1, #128 @ 0x80
800ad4e: 68f8 ldr r0, [r7, #12]
800ad50: f001 face bl 800c2f0 <USBD_LL_StallEP>
USBD_CtlReceiveStatus(pdev);
800ad54: 68f8 ldr r0, [r7, #12]
800ad56: f000 fecc bl 800baf2 <USBD_CtlReceiveStatus>
800ad5a: e00d b.n 800ad78 <USBD_LL_DataInStage+0xfa>
}
}
}
else
{
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
800ad5c: 68fb ldr r3, [r7, #12]
800ad5e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
800ad62: 2b04 cmp r3, #4
800ad64: d004 beq.n 800ad70 <USBD_LL_DataInStage+0xf2>
(pdev->ep0_state == USBD_EP0_IDLE))
800ad66: 68fb ldr r3, [r7, #12]
800ad68: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
800ad6c: 2b00 cmp r3, #0
800ad6e: d103 bne.n 800ad78 <USBD_LL_DataInStage+0xfa>
{
USBD_LL_StallEP(pdev, 0x80U);
800ad70: 2180 movs r1, #128 @ 0x80
800ad72: 68f8 ldr r0, [r7, #12]
800ad74: f001 fabc bl 800c2f0 <USBD_LL_StallEP>
}
}
if (pdev->dev_test_mode == 1U)
800ad78: 68fb ldr r3, [r7, #12]
800ad7a: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
800ad7e: 2b01 cmp r3, #1
800ad80: d11d bne.n 800adbe <USBD_LL_DataInStage+0x140>
{
USBD_RunTestMode(pdev);
800ad82: 68f8 ldr r0, [r7, #12]
800ad84: f7ff fe81 bl 800aa8a <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
800ad88: 68fb ldr r3, [r7, #12]
800ad8a: 2200 movs r2, #0
800ad8c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
800ad90: e015 b.n 800adbe <USBD_LL_DataInStage+0x140>
}
}
else if ((pdev->pClass->DataIn != NULL) &&
800ad92: 68fb ldr r3, [r7, #12]
800ad94: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ad98: 695b ldr r3, [r3, #20]
800ad9a: 2b00 cmp r3, #0
800ad9c: d00d beq.n 800adba <USBD_LL_DataInStage+0x13c>
(pdev->dev_state == USBD_STATE_CONFIGURED))
800ad9e: 68fb ldr r3, [r7, #12]
800ada0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataIn != NULL) &&
800ada4: 2b03 cmp r3, #3
800ada6: d108 bne.n 800adba <USBD_LL_DataInStage+0x13c>
{
pdev->pClass->DataIn(pdev, epnum);
800ada8: 68fb ldr r3, [r7, #12]
800adaa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800adae: 695b ldr r3, [r3, #20]
800adb0: 7afa ldrb r2, [r7, #11]
800adb2: 4611 mov r1, r2
800adb4: 68f8 ldr r0, [r7, #12]
800adb6: 4798 blx r3
800adb8: e001 b.n 800adbe <USBD_LL_DataInStage+0x140>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
800adba: 2302 movs r3, #2
800adbc: e000 b.n 800adc0 <USBD_LL_DataInStage+0x142>
}
return USBD_OK;
800adbe: 2300 movs r3, #0
}
800adc0: 4618 mov r0, r3
800adc2: 3718 adds r7, #24
800adc4: 46bd mov sp, r7
800adc6: bd80 pop {r7, pc}
0800adc8 <USBD_LL_Reset>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
800adc8: b580 push {r7, lr}
800adca: b082 sub sp, #8
800adcc: af00 add r7, sp, #0
800adce: 6078 str r0, [r7, #4]
/* Open EP0 OUT */
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
800add0: 2340 movs r3, #64 @ 0x40
800add2: 2200 movs r2, #0
800add4: 2100 movs r1, #0
800add6: 6878 ldr r0, [r7, #4]
800add8: f001 fa45 bl 800c266 <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
800addc: 687b ldr r3, [r7, #4]
800adde: 2201 movs r2, #1
800ade0: f8c3 2158 str.w r2, [r3, #344] @ 0x158
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
800ade4: 687b ldr r3, [r7, #4]
800ade6: 2240 movs r2, #64 @ 0x40
800ade8: f8c3 2164 str.w r2, [r3, #356] @ 0x164
/* Open EP0 IN */
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
800adec: 2340 movs r3, #64 @ 0x40
800adee: 2200 movs r2, #0
800adf0: 2180 movs r1, #128 @ 0x80
800adf2: 6878 ldr r0, [r7, #4]
800adf4: f001 fa37 bl 800c266 <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
800adf8: 687b ldr r3, [r7, #4]
800adfa: 2201 movs r2, #1
800adfc: 619a str r2, [r3, #24]
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
800adfe: 687b ldr r3, [r7, #4]
800ae00: 2240 movs r2, #64 @ 0x40
800ae02: 625a str r2, [r3, #36] @ 0x24
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
800ae04: 687b ldr r3, [r7, #4]
800ae06: 2201 movs r2, #1
800ae08: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
800ae0c: 687b ldr r3, [r7, #4]
800ae0e: 2200 movs r2, #0
800ae10: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
800ae14: 687b ldr r3, [r7, #4]
800ae16: 2200 movs r2, #0
800ae18: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
800ae1a: 687b ldr r3, [r7, #4]
800ae1c: 2200 movs r2, #0
800ae1e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
if (pdev->pClassData)
800ae22: 687b ldr r3, [r7, #4]
800ae24: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800ae28: 2b00 cmp r3, #0
800ae2a: d009 beq.n 800ae40 <USBD_LL_Reset+0x78>
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
800ae2c: 687b ldr r3, [r7, #4]
800ae2e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800ae32: 685b ldr r3, [r3, #4]
800ae34: 687a ldr r2, [r7, #4]
800ae36: 6852 ldr r2, [r2, #4]
800ae38: b2d2 uxtb r2, r2
800ae3a: 4611 mov r1, r2
800ae3c: 6878 ldr r0, [r7, #4]
800ae3e: 4798 blx r3
}
return USBD_OK;
800ae40: 2300 movs r3, #0
}
800ae42: 4618 mov r0, r3
800ae44: 3708 adds r7, #8
800ae46: 46bd mov sp, r7
800ae48: bd80 pop {r7, pc}
0800ae4a <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
800ae4a: b480 push {r7}
800ae4c: b083 sub sp, #12
800ae4e: af00 add r7, sp, #0
800ae50: 6078 str r0, [r7, #4]
800ae52: 460b mov r3, r1
800ae54: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
800ae56: 687b ldr r3, [r7, #4]
800ae58: 78fa ldrb r2, [r7, #3]
800ae5a: 741a strb r2, [r3, #16]
return USBD_OK;
800ae5c: 2300 movs r3, #0
}
800ae5e: 4618 mov r0, r3
800ae60: 370c adds r7, #12
800ae62: 46bd mov sp, r7
800ae64: bc80 pop {r7}
800ae66: 4770 bx lr
0800ae68 <USBD_LL_Suspend>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
800ae68: b480 push {r7}
800ae6a: b083 sub sp, #12
800ae6c: af00 add r7, sp, #0
800ae6e: 6078 str r0, [r7, #4]
pdev->dev_old_state = pdev->dev_state;
800ae70: 687b ldr r3, [r7, #4]
800ae72: f893 229c ldrb.w r2, [r3, #668] @ 0x29c
800ae76: 687b ldr r3, [r7, #4]
800ae78: f883 229d strb.w r2, [r3, #669] @ 0x29d
pdev->dev_state = USBD_STATE_SUSPENDED;
800ae7c: 687b ldr r3, [r7, #4]
800ae7e: 2204 movs r2, #4
800ae80: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
800ae84: 2300 movs r3, #0
}
800ae86: 4618 mov r0, r3
800ae88: 370c adds r7, #12
800ae8a: 46bd mov sp, r7
800ae8c: bc80 pop {r7}
800ae8e: 4770 bx lr
0800ae90 <USBD_LL_Resume>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
800ae90: b480 push {r7}
800ae92: b083 sub sp, #12
800ae94: af00 add r7, sp, #0
800ae96: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
800ae98: 687b ldr r3, [r7, #4]
800ae9a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800ae9e: 2b04 cmp r3, #4
800aea0: d105 bne.n 800aeae <USBD_LL_Resume+0x1e>
{
pdev->dev_state = pdev->dev_old_state;
800aea2: 687b ldr r3, [r7, #4]
800aea4: f893 229d ldrb.w r2, [r3, #669] @ 0x29d
800aea8: 687b ldr r3, [r7, #4]
800aeaa: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
800aeae: 2300 movs r3, #0
}
800aeb0: 4618 mov r0, r3
800aeb2: 370c adds r7, #12
800aeb4: 46bd mov sp, r7
800aeb6: bc80 pop {r7}
800aeb8: 4770 bx lr
0800aeba <USBD_LL_SOF>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
800aeba: b580 push {r7, lr}
800aebc: b082 sub sp, #8
800aebe: af00 add r7, sp, #0
800aec0: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800aec2: 687b ldr r3, [r7, #4]
800aec4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800aec8: 2b03 cmp r3, #3
800aeca: d10b bne.n 800aee4 <USBD_LL_SOF+0x2a>
{
if (pdev->pClass->SOF != NULL)
800aecc: 687b ldr r3, [r7, #4]
800aece: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800aed2: 69db ldr r3, [r3, #28]
800aed4: 2b00 cmp r3, #0
800aed6: d005 beq.n 800aee4 <USBD_LL_SOF+0x2a>
{
pdev->pClass->SOF(pdev);
800aed8: 687b ldr r3, [r7, #4]
800aeda: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800aede: 69db ldr r3, [r3, #28]
800aee0: 6878 ldr r0, [r7, #4]
800aee2: 4798 blx r3
}
}
return USBD_OK;
800aee4: 2300 movs r3, #0
}
800aee6: 4618 mov r0, r3
800aee8: 3708 adds r7, #8
800aeea: 46bd mov sp, r7
800aeec: bd80 pop {r7, pc}
...
0800aef0 <USBD_StdDevReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800aef0: b580 push {r7, lr}
800aef2: b084 sub sp, #16
800aef4: af00 add r7, sp, #0
800aef6: 6078 str r0, [r7, #4]
800aef8: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
800aefa: 2300 movs r3, #0
800aefc: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800aefe: 683b ldr r3, [r7, #0]
800af00: 781b ldrb r3, [r3, #0]
800af02: f003 0360 and.w r3, r3, #96 @ 0x60
800af06: 2b40 cmp r3, #64 @ 0x40
800af08: d005 beq.n 800af16 <USBD_StdDevReq+0x26>
800af0a: 2b40 cmp r3, #64 @ 0x40
800af0c: d84f bhi.n 800afae <USBD_StdDevReq+0xbe>
800af0e: 2b00 cmp r3, #0
800af10: d009 beq.n 800af26 <USBD_StdDevReq+0x36>
800af12: 2b20 cmp r3, #32
800af14: d14b bne.n 800afae <USBD_StdDevReq+0xbe>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
800af16: 687b ldr r3, [r7, #4]
800af18: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800af1c: 689b ldr r3, [r3, #8]
800af1e: 6839 ldr r1, [r7, #0]
800af20: 6878 ldr r0, [r7, #4]
800af22: 4798 blx r3
break;
800af24: e048 b.n 800afb8 <USBD_StdDevReq+0xc8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
800af26: 683b ldr r3, [r7, #0]
800af28: 785b ldrb r3, [r3, #1]
800af2a: 2b09 cmp r3, #9
800af2c: d839 bhi.n 800afa2 <USBD_StdDevReq+0xb2>
800af2e: a201 add r2, pc, #4 @ (adr r2, 800af34 <USBD_StdDevReq+0x44>)
800af30: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800af34: 0800af85 .word 0x0800af85
800af38: 0800af99 .word 0x0800af99
800af3c: 0800afa3 .word 0x0800afa3
800af40: 0800af8f .word 0x0800af8f
800af44: 0800afa3 .word 0x0800afa3
800af48: 0800af67 .word 0x0800af67
800af4c: 0800af5d .word 0x0800af5d
800af50: 0800afa3 .word 0x0800afa3
800af54: 0800af7b .word 0x0800af7b
800af58: 0800af71 .word 0x0800af71
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
800af5c: 6839 ldr r1, [r7, #0]
800af5e: 6878 ldr r0, [r7, #4]
800af60: f000 f9dc bl 800b31c <USBD_GetDescriptor>
break;
800af64: e022 b.n 800afac <USBD_StdDevReq+0xbc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
800af66: 6839 ldr r1, [r7, #0]
800af68: 6878 ldr r0, [r7, #4]
800af6a: f000 fb3f bl 800b5ec <USBD_SetAddress>
break;
800af6e: e01d b.n 800afac <USBD_StdDevReq+0xbc>
case USB_REQ_SET_CONFIGURATION:
USBD_SetConfig(pdev, req);
800af70: 6839 ldr r1, [r7, #0]
800af72: 6878 ldr r0, [r7, #4]
800af74: f000 fb7e bl 800b674 <USBD_SetConfig>
break;
800af78: e018 b.n 800afac <USBD_StdDevReq+0xbc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
800af7a: 6839 ldr r1, [r7, #0]
800af7c: 6878 ldr r0, [r7, #4]
800af7e: f000 fc07 bl 800b790 <USBD_GetConfig>
break;
800af82: e013 b.n 800afac <USBD_StdDevReq+0xbc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
800af84: 6839 ldr r1, [r7, #0]
800af86: 6878 ldr r0, [r7, #4]
800af88: f000 fc37 bl 800b7fa <USBD_GetStatus>
break;
800af8c: e00e b.n 800afac <USBD_StdDevReq+0xbc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
800af8e: 6839 ldr r1, [r7, #0]
800af90: 6878 ldr r0, [r7, #4]
800af92: f000 fc65 bl 800b860 <USBD_SetFeature>
break;
800af96: e009 b.n 800afac <USBD_StdDevReq+0xbc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
800af98: 6839 ldr r1, [r7, #0]
800af9a: 6878 ldr r0, [r7, #4]
800af9c: f000 fc74 bl 800b888 <USBD_ClrFeature>
break;
800afa0: e004 b.n 800afac <USBD_StdDevReq+0xbc>
default:
USBD_CtlError(pdev, req);
800afa2: 6839 ldr r1, [r7, #0]
800afa4: 6878 ldr r0, [r7, #4]
800afa6: f000 fcc9 bl 800b93c <USBD_CtlError>
break;
800afaa: bf00 nop
}
break;
800afac: e004 b.n 800afb8 <USBD_StdDevReq+0xc8>
default:
USBD_CtlError(pdev, req);
800afae: 6839 ldr r1, [r7, #0]
800afb0: 6878 ldr r0, [r7, #4]
800afb2: f000 fcc3 bl 800b93c <USBD_CtlError>
break;
800afb6: bf00 nop
}
return ret;
800afb8: 7bfb ldrb r3, [r7, #15]
}
800afba: 4618 mov r0, r3
800afbc: 3710 adds r7, #16
800afbe: 46bd mov sp, r7
800afc0: bd80 pop {r7, pc}
800afc2: bf00 nop
0800afc4 <USBD_StdItfReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800afc4: b580 push {r7, lr}
800afc6: b084 sub sp, #16
800afc8: af00 add r7, sp, #0
800afca: 6078 str r0, [r7, #4]
800afcc: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
800afce: 2300 movs r3, #0
800afd0: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800afd2: 683b ldr r3, [r7, #0]
800afd4: 781b ldrb r3, [r3, #0]
800afd6: f003 0360 and.w r3, r3, #96 @ 0x60
800afda: 2b40 cmp r3, #64 @ 0x40
800afdc: d005 beq.n 800afea <USBD_StdItfReq+0x26>
800afde: 2b40 cmp r3, #64 @ 0x40
800afe0: d82e bhi.n 800b040 <USBD_StdItfReq+0x7c>
800afe2: 2b00 cmp r3, #0
800afe4: d001 beq.n 800afea <USBD_StdItfReq+0x26>
800afe6: 2b20 cmp r3, #32
800afe8: d12a bne.n 800b040 <USBD_StdItfReq+0x7c>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
800afea: 687b ldr r3, [r7, #4]
800afec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800aff0: 3b01 subs r3, #1
800aff2: 2b02 cmp r3, #2
800aff4: d81d bhi.n 800b032 <USBD_StdItfReq+0x6e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
800aff6: 683b ldr r3, [r7, #0]
800aff8: 889b ldrh r3, [r3, #4]
800affa: b2db uxtb r3, r3
800affc: 2b01 cmp r3, #1
800affe: d813 bhi.n 800b028 <USBD_StdItfReq+0x64>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
800b000: 687b ldr r3, [r7, #4]
800b002: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b006: 689b ldr r3, [r3, #8]
800b008: 6839 ldr r1, [r7, #0]
800b00a: 6878 ldr r0, [r7, #4]
800b00c: 4798 blx r3
800b00e: 4603 mov r3, r0
800b010: 73fb strb r3, [r7, #15]
if ((req->wLength == 0U) && (ret == USBD_OK))
800b012: 683b ldr r3, [r7, #0]
800b014: 88db ldrh r3, [r3, #6]
800b016: 2b00 cmp r3, #0
800b018: d110 bne.n 800b03c <USBD_StdItfReq+0x78>
800b01a: 7bfb ldrb r3, [r7, #15]
800b01c: 2b00 cmp r3, #0
800b01e: d10d bne.n 800b03c <USBD_StdItfReq+0x78>
{
USBD_CtlSendStatus(pdev);
800b020: 6878 ldr r0, [r7, #4]
800b022: f000 fd53 bl 800bacc <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
800b026: e009 b.n 800b03c <USBD_StdItfReq+0x78>
USBD_CtlError(pdev, req);
800b028: 6839 ldr r1, [r7, #0]
800b02a: 6878 ldr r0, [r7, #4]
800b02c: f000 fc86 bl 800b93c <USBD_CtlError>
break;
800b030: e004 b.n 800b03c <USBD_StdItfReq+0x78>
default:
USBD_CtlError(pdev, req);
800b032: 6839 ldr r1, [r7, #0]
800b034: 6878 ldr r0, [r7, #4]
800b036: f000 fc81 bl 800b93c <USBD_CtlError>
break;
800b03a: e000 b.n 800b03e <USBD_StdItfReq+0x7a>
break;
800b03c: bf00 nop
}
break;
800b03e: e004 b.n 800b04a <USBD_StdItfReq+0x86>
default:
USBD_CtlError(pdev, req);
800b040: 6839 ldr r1, [r7, #0]
800b042: 6878 ldr r0, [r7, #4]
800b044: f000 fc7a bl 800b93c <USBD_CtlError>
break;
800b048: bf00 nop
}
return USBD_OK;
800b04a: 2300 movs r3, #0
}
800b04c: 4618 mov r0, r3
800b04e: 3710 adds r7, #16
800b050: 46bd mov sp, r7
800b052: bd80 pop {r7, pc}
0800b054 <USBD_StdEPReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800b054: b580 push {r7, lr}
800b056: b084 sub sp, #16
800b058: af00 add r7, sp, #0
800b05a: 6078 str r0, [r7, #4]
800b05c: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
USBD_StatusTypeDef ret = USBD_OK;
800b05e: 2300 movs r3, #0
800b060: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
800b062: 683b ldr r3, [r7, #0]
800b064: 889b ldrh r3, [r3, #4]
800b066: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800b068: 683b ldr r3, [r7, #0]
800b06a: 781b ldrb r3, [r3, #0]
800b06c: f003 0360 and.w r3, r3, #96 @ 0x60
800b070: 2b40 cmp r3, #64 @ 0x40
800b072: d007 beq.n 800b084 <USBD_StdEPReq+0x30>
800b074: 2b40 cmp r3, #64 @ 0x40
800b076: f200 8146 bhi.w 800b306 <USBD_StdEPReq+0x2b2>
800b07a: 2b00 cmp r3, #0
800b07c: d00a beq.n 800b094 <USBD_StdEPReq+0x40>
800b07e: 2b20 cmp r3, #32
800b080: f040 8141 bne.w 800b306 <USBD_StdEPReq+0x2b2>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
800b084: 687b ldr r3, [r7, #4]
800b086: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b08a: 689b ldr r3, [r3, #8]
800b08c: 6839 ldr r1, [r7, #0]
800b08e: 6878 ldr r0, [r7, #4]
800b090: 4798 blx r3
break;
800b092: e13d b.n 800b310 <USBD_StdEPReq+0x2bc>
case USB_REQ_TYPE_STANDARD:
/* Check if it is a class request */
if ((req->bmRequest & 0x60U) == 0x20U)
800b094: 683b ldr r3, [r7, #0]
800b096: 781b ldrb r3, [r3, #0]
800b098: f003 0360 and.w r3, r3, #96 @ 0x60
800b09c: 2b20 cmp r3, #32
800b09e: d10a bne.n 800b0b6 <USBD_StdEPReq+0x62>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
800b0a0: 687b ldr r3, [r7, #4]
800b0a2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b0a6: 689b ldr r3, [r3, #8]
800b0a8: 6839 ldr r1, [r7, #0]
800b0aa: 6878 ldr r0, [r7, #4]
800b0ac: 4798 blx r3
800b0ae: 4603 mov r3, r0
800b0b0: 73fb strb r3, [r7, #15]
return ret;
800b0b2: 7bfb ldrb r3, [r7, #15]
800b0b4: e12d b.n 800b312 <USBD_StdEPReq+0x2be>
}
switch (req->bRequest)
800b0b6: 683b ldr r3, [r7, #0]
800b0b8: 785b ldrb r3, [r3, #1]
800b0ba: 2b03 cmp r3, #3
800b0bc: d007 beq.n 800b0ce <USBD_StdEPReq+0x7a>
800b0be: 2b03 cmp r3, #3
800b0c0: f300 811b bgt.w 800b2fa <USBD_StdEPReq+0x2a6>
800b0c4: 2b00 cmp r3, #0
800b0c6: d072 beq.n 800b1ae <USBD_StdEPReq+0x15a>
800b0c8: 2b01 cmp r3, #1
800b0ca: d03a beq.n 800b142 <USBD_StdEPReq+0xee>
800b0cc: e115 b.n 800b2fa <USBD_StdEPReq+0x2a6>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
800b0ce: 687b ldr r3, [r7, #4]
800b0d0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b0d4: 2b02 cmp r3, #2
800b0d6: d002 beq.n 800b0de <USBD_StdEPReq+0x8a>
800b0d8: 2b03 cmp r3, #3
800b0da: d015 beq.n 800b108 <USBD_StdEPReq+0xb4>
800b0dc: e02b b.n 800b136 <USBD_StdEPReq+0xe2>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
800b0de: 7bbb ldrb r3, [r7, #14]
800b0e0: 2b00 cmp r3, #0
800b0e2: d00c beq.n 800b0fe <USBD_StdEPReq+0xaa>
800b0e4: 7bbb ldrb r3, [r7, #14]
800b0e6: 2b80 cmp r3, #128 @ 0x80
800b0e8: d009 beq.n 800b0fe <USBD_StdEPReq+0xaa>
{
USBD_LL_StallEP(pdev, ep_addr);
800b0ea: 7bbb ldrb r3, [r7, #14]
800b0ec: 4619 mov r1, r3
800b0ee: 6878 ldr r0, [r7, #4]
800b0f0: f001 f8fe bl 800c2f0 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
800b0f4: 2180 movs r1, #128 @ 0x80
800b0f6: 6878 ldr r0, [r7, #4]
800b0f8: f001 f8fa bl 800c2f0 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
800b0fc: e020 b.n 800b140 <USBD_StdEPReq+0xec>
USBD_CtlError(pdev, req);
800b0fe: 6839 ldr r1, [r7, #0]
800b100: 6878 ldr r0, [r7, #4]
800b102: f000 fc1b bl 800b93c <USBD_CtlError>
break;
800b106: e01b b.n 800b140 <USBD_StdEPReq+0xec>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
800b108: 683b ldr r3, [r7, #0]
800b10a: 885b ldrh r3, [r3, #2]
800b10c: 2b00 cmp r3, #0
800b10e: d10e bne.n 800b12e <USBD_StdEPReq+0xda>
{
if ((ep_addr != 0x00U) &&
800b110: 7bbb ldrb r3, [r7, #14]
800b112: 2b00 cmp r3, #0
800b114: d00b beq.n 800b12e <USBD_StdEPReq+0xda>
800b116: 7bbb ldrb r3, [r7, #14]
800b118: 2b80 cmp r3, #128 @ 0x80
800b11a: d008 beq.n 800b12e <USBD_StdEPReq+0xda>
(ep_addr != 0x80U) && (req->wLength == 0x00U))
800b11c: 683b ldr r3, [r7, #0]
800b11e: 88db ldrh r3, [r3, #6]
800b120: 2b00 cmp r3, #0
800b122: d104 bne.n 800b12e <USBD_StdEPReq+0xda>
{
USBD_LL_StallEP(pdev, ep_addr);
800b124: 7bbb ldrb r3, [r7, #14]
800b126: 4619 mov r1, r3
800b128: 6878 ldr r0, [r7, #4]
800b12a: f001 f8e1 bl 800c2f0 <USBD_LL_StallEP>
}
}
USBD_CtlSendStatus(pdev);
800b12e: 6878 ldr r0, [r7, #4]
800b130: f000 fccc bl 800bacc <USBD_CtlSendStatus>
break;
800b134: e004 b.n 800b140 <USBD_StdEPReq+0xec>
default:
USBD_CtlError(pdev, req);
800b136: 6839 ldr r1, [r7, #0]
800b138: 6878 ldr r0, [r7, #4]
800b13a: f000 fbff bl 800b93c <USBD_CtlError>
break;
800b13e: bf00 nop
}
break;
800b140: e0e0 b.n 800b304 <USBD_StdEPReq+0x2b0>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
800b142: 687b ldr r3, [r7, #4]
800b144: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b148: 2b02 cmp r3, #2
800b14a: d002 beq.n 800b152 <USBD_StdEPReq+0xfe>
800b14c: 2b03 cmp r3, #3
800b14e: d015 beq.n 800b17c <USBD_StdEPReq+0x128>
800b150: e026 b.n 800b1a0 <USBD_StdEPReq+0x14c>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
800b152: 7bbb ldrb r3, [r7, #14]
800b154: 2b00 cmp r3, #0
800b156: d00c beq.n 800b172 <USBD_StdEPReq+0x11e>
800b158: 7bbb ldrb r3, [r7, #14]
800b15a: 2b80 cmp r3, #128 @ 0x80
800b15c: d009 beq.n 800b172 <USBD_StdEPReq+0x11e>
{
USBD_LL_StallEP(pdev, ep_addr);
800b15e: 7bbb ldrb r3, [r7, #14]
800b160: 4619 mov r1, r3
800b162: 6878 ldr r0, [r7, #4]
800b164: f001 f8c4 bl 800c2f0 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
800b168: 2180 movs r1, #128 @ 0x80
800b16a: 6878 ldr r0, [r7, #4]
800b16c: f001 f8c0 bl 800c2f0 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
800b170: e01c b.n 800b1ac <USBD_StdEPReq+0x158>
USBD_CtlError(pdev, req);
800b172: 6839 ldr r1, [r7, #0]
800b174: 6878 ldr r0, [r7, #4]
800b176: f000 fbe1 bl 800b93c <USBD_CtlError>
break;
800b17a: e017 b.n 800b1ac <USBD_StdEPReq+0x158>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
800b17c: 683b ldr r3, [r7, #0]
800b17e: 885b ldrh r3, [r3, #2]
800b180: 2b00 cmp r3, #0
800b182: d112 bne.n 800b1aa <USBD_StdEPReq+0x156>
{
if ((ep_addr & 0x7FU) != 0x00U)
800b184: 7bbb ldrb r3, [r7, #14]
800b186: f003 037f and.w r3, r3, #127 @ 0x7f
800b18a: 2b00 cmp r3, #0
800b18c: d004 beq.n 800b198 <USBD_StdEPReq+0x144>
{
USBD_LL_ClearStallEP(pdev, ep_addr);
800b18e: 7bbb ldrb r3, [r7, #14]
800b190: 4619 mov r1, r3
800b192: 6878 ldr r0, [r7, #4]
800b194: f001 f8cb bl 800c32e <USBD_LL_ClearStallEP>
}
USBD_CtlSendStatus(pdev);
800b198: 6878 ldr r0, [r7, #4]
800b19a: f000 fc97 bl 800bacc <USBD_CtlSendStatus>
}
break;
800b19e: e004 b.n 800b1aa <USBD_StdEPReq+0x156>
default:
USBD_CtlError(pdev, req);
800b1a0: 6839 ldr r1, [r7, #0]
800b1a2: 6878 ldr r0, [r7, #4]
800b1a4: f000 fbca bl 800b93c <USBD_CtlError>
break;
800b1a8: e000 b.n 800b1ac <USBD_StdEPReq+0x158>
break;
800b1aa: bf00 nop
}
break;
800b1ac: e0aa b.n 800b304 <USBD_StdEPReq+0x2b0>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
800b1ae: 687b ldr r3, [r7, #4]
800b1b0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b1b4: 2b02 cmp r3, #2
800b1b6: d002 beq.n 800b1be <USBD_StdEPReq+0x16a>
800b1b8: 2b03 cmp r3, #3
800b1ba: d032 beq.n 800b222 <USBD_StdEPReq+0x1ce>
800b1bc: e097 b.n 800b2ee <USBD_StdEPReq+0x29a>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
800b1be: 7bbb ldrb r3, [r7, #14]
800b1c0: 2b00 cmp r3, #0
800b1c2: d007 beq.n 800b1d4 <USBD_StdEPReq+0x180>
800b1c4: 7bbb ldrb r3, [r7, #14]
800b1c6: 2b80 cmp r3, #128 @ 0x80
800b1c8: d004 beq.n 800b1d4 <USBD_StdEPReq+0x180>
{
USBD_CtlError(pdev, req);
800b1ca: 6839 ldr r1, [r7, #0]
800b1cc: 6878 ldr r0, [r7, #4]
800b1ce: f000 fbb5 bl 800b93c <USBD_CtlError>
break;
800b1d2: e091 b.n 800b2f8 <USBD_StdEPReq+0x2a4>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800b1d4: f997 300e ldrsb.w r3, [r7, #14]
800b1d8: 2b00 cmp r3, #0
800b1da: da0b bge.n 800b1f4 <USBD_StdEPReq+0x1a0>
800b1dc: 7bbb ldrb r3, [r7, #14]
800b1de: f003 027f and.w r2, r3, #127 @ 0x7f
800b1e2: 4613 mov r3, r2
800b1e4: 009b lsls r3, r3, #2
800b1e6: 4413 add r3, r2
800b1e8: 009b lsls r3, r3, #2
800b1ea: 3310 adds r3, #16
800b1ec: 687a ldr r2, [r7, #4]
800b1ee: 4413 add r3, r2
800b1f0: 3304 adds r3, #4
800b1f2: e00b b.n 800b20c <USBD_StdEPReq+0x1b8>
&pdev->ep_out[ep_addr & 0x7FU];
800b1f4: 7bbb ldrb r3, [r7, #14]
800b1f6: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800b1fa: 4613 mov r3, r2
800b1fc: 009b lsls r3, r3, #2
800b1fe: 4413 add r3, r2
800b200: 009b lsls r3, r3, #2
800b202: f503 73a8 add.w r3, r3, #336 @ 0x150
800b206: 687a ldr r2, [r7, #4]
800b208: 4413 add r3, r2
800b20a: 3304 adds r3, #4
800b20c: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
800b20e: 68bb ldr r3, [r7, #8]
800b210: 2200 movs r2, #0
800b212: 601a str r2, [r3, #0]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
800b214: 68bb ldr r3, [r7, #8]
800b216: 2202 movs r2, #2
800b218: 4619 mov r1, r3
800b21a: 6878 ldr r0, [r7, #4]
800b21c: f000 fbf8 bl 800ba10 <USBD_CtlSendData>
break;
800b220: e06a b.n 800b2f8 <USBD_StdEPReq+0x2a4>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
800b222: f997 300e ldrsb.w r3, [r7, #14]
800b226: 2b00 cmp r3, #0
800b228: da11 bge.n 800b24e <USBD_StdEPReq+0x1fa>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
800b22a: 7bbb ldrb r3, [r7, #14]
800b22c: f003 020f and.w r2, r3, #15
800b230: 6879 ldr r1, [r7, #4]
800b232: 4613 mov r3, r2
800b234: 009b lsls r3, r3, #2
800b236: 4413 add r3, r2
800b238: 009b lsls r3, r3, #2
800b23a: 440b add r3, r1
800b23c: 3318 adds r3, #24
800b23e: 681b ldr r3, [r3, #0]
800b240: 2b00 cmp r3, #0
800b242: d117 bne.n 800b274 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
800b244: 6839 ldr r1, [r7, #0]
800b246: 6878 ldr r0, [r7, #4]
800b248: f000 fb78 bl 800b93c <USBD_CtlError>
break;
800b24c: e054 b.n 800b2f8 <USBD_StdEPReq+0x2a4>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
800b24e: 7bbb ldrb r3, [r7, #14]
800b250: f003 020f and.w r2, r3, #15
800b254: 6879 ldr r1, [r7, #4]
800b256: 4613 mov r3, r2
800b258: 009b lsls r3, r3, #2
800b25a: 4413 add r3, r2
800b25c: 009b lsls r3, r3, #2
800b25e: 440b add r3, r1
800b260: f503 73ac add.w r3, r3, #344 @ 0x158
800b264: 681b ldr r3, [r3, #0]
800b266: 2b00 cmp r3, #0
800b268: d104 bne.n 800b274 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
800b26a: 6839 ldr r1, [r7, #0]
800b26c: 6878 ldr r0, [r7, #4]
800b26e: f000 fb65 bl 800b93c <USBD_CtlError>
break;
800b272: e041 b.n 800b2f8 <USBD_StdEPReq+0x2a4>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800b274: f997 300e ldrsb.w r3, [r7, #14]
800b278: 2b00 cmp r3, #0
800b27a: da0b bge.n 800b294 <USBD_StdEPReq+0x240>
800b27c: 7bbb ldrb r3, [r7, #14]
800b27e: f003 027f and.w r2, r3, #127 @ 0x7f
800b282: 4613 mov r3, r2
800b284: 009b lsls r3, r3, #2
800b286: 4413 add r3, r2
800b288: 009b lsls r3, r3, #2
800b28a: 3310 adds r3, #16
800b28c: 687a ldr r2, [r7, #4]
800b28e: 4413 add r3, r2
800b290: 3304 adds r3, #4
800b292: e00b b.n 800b2ac <USBD_StdEPReq+0x258>
&pdev->ep_out[ep_addr & 0x7FU];
800b294: 7bbb ldrb r3, [r7, #14]
800b296: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
800b29a: 4613 mov r3, r2
800b29c: 009b lsls r3, r3, #2
800b29e: 4413 add r3, r2
800b2a0: 009b lsls r3, r3, #2
800b2a2: f503 73a8 add.w r3, r3, #336 @ 0x150
800b2a6: 687a ldr r2, [r7, #4]
800b2a8: 4413 add r3, r2
800b2aa: 3304 adds r3, #4
800b2ac: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
800b2ae: 7bbb ldrb r3, [r7, #14]
800b2b0: 2b00 cmp r3, #0
800b2b2: d002 beq.n 800b2ba <USBD_StdEPReq+0x266>
800b2b4: 7bbb ldrb r3, [r7, #14]
800b2b6: 2b80 cmp r3, #128 @ 0x80
800b2b8: d103 bne.n 800b2c2 <USBD_StdEPReq+0x26e>
{
pep->status = 0x0000U;
800b2ba: 68bb ldr r3, [r7, #8]
800b2bc: 2200 movs r2, #0
800b2be: 601a str r2, [r3, #0]
800b2c0: e00e b.n 800b2e0 <USBD_StdEPReq+0x28c>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr))
800b2c2: 7bbb ldrb r3, [r7, #14]
800b2c4: 4619 mov r1, r3
800b2c6: 6878 ldr r0, [r7, #4]
800b2c8: f001 f850 bl 800c36c <USBD_LL_IsStallEP>
800b2cc: 4603 mov r3, r0
800b2ce: 2b00 cmp r3, #0
800b2d0: d003 beq.n 800b2da <USBD_StdEPReq+0x286>
{
pep->status = 0x0001U;
800b2d2: 68bb ldr r3, [r7, #8]
800b2d4: 2201 movs r2, #1
800b2d6: 601a str r2, [r3, #0]
800b2d8: e002 b.n 800b2e0 <USBD_StdEPReq+0x28c>
}
else
{
pep->status = 0x0000U;
800b2da: 68bb ldr r3, [r7, #8]
800b2dc: 2200 movs r2, #0
800b2de: 601a str r2, [r3, #0]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
800b2e0: 68bb ldr r3, [r7, #8]
800b2e2: 2202 movs r2, #2
800b2e4: 4619 mov r1, r3
800b2e6: 6878 ldr r0, [r7, #4]
800b2e8: f000 fb92 bl 800ba10 <USBD_CtlSendData>
break;
800b2ec: e004 b.n 800b2f8 <USBD_StdEPReq+0x2a4>
default:
USBD_CtlError(pdev, req);
800b2ee: 6839 ldr r1, [r7, #0]
800b2f0: 6878 ldr r0, [r7, #4]
800b2f2: f000 fb23 bl 800b93c <USBD_CtlError>
break;
800b2f6: bf00 nop
}
break;
800b2f8: e004 b.n 800b304 <USBD_StdEPReq+0x2b0>
default:
USBD_CtlError(pdev, req);
800b2fa: 6839 ldr r1, [r7, #0]
800b2fc: 6878 ldr r0, [r7, #4]
800b2fe: f000 fb1d bl 800b93c <USBD_CtlError>
break;
800b302: bf00 nop
}
break;
800b304: e004 b.n 800b310 <USBD_StdEPReq+0x2bc>
default:
USBD_CtlError(pdev, req);
800b306: 6839 ldr r1, [r7, #0]
800b308: 6878 ldr r0, [r7, #4]
800b30a: f000 fb17 bl 800b93c <USBD_CtlError>
break;
800b30e: bf00 nop
}
return ret;
800b310: 7bfb ldrb r3, [r7, #15]
}
800b312: 4618 mov r0, r3
800b314: 3710 adds r7, #16
800b316: 46bd mov sp, r7
800b318: bd80 pop {r7, pc}
...
0800b31c <USBD_GetDescriptor>:
* @param req: usb request
* @retval status
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800b31c: b580 push {r7, lr}
800b31e: b084 sub sp, #16
800b320: af00 add r7, sp, #0
800b322: 6078 str r0, [r7, #4]
800b324: 6039 str r1, [r7, #0]
uint16_t len = 0U;
800b326: 2300 movs r3, #0
800b328: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
800b32a: 2300 movs r3, #0
800b32c: 60fb str r3, [r7, #12]
uint8_t err = 0U;
800b32e: 2300 movs r3, #0
800b330: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
800b332: 683b ldr r3, [r7, #0]
800b334: 885b ldrh r3, [r3, #2]
800b336: 0a1b lsrs r3, r3, #8
800b338: b29b uxth r3, r3
800b33a: 3b01 subs r3, #1
800b33c: 2b06 cmp r3, #6
800b33e: f200 8128 bhi.w 800b592 <USBD_GetDescriptor+0x276>
800b342: a201 add r2, pc, #4 @ (adr r2, 800b348 <USBD_GetDescriptor+0x2c>)
800b344: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b348: 0800b365 .word 0x0800b365
800b34c: 0800b37d .word 0x0800b37d
800b350: 0800b3bd .word 0x0800b3bd
800b354: 0800b593 .word 0x0800b593
800b358: 0800b593 .word 0x0800b593
800b35c: 0800b533 .word 0x0800b533
800b360: 0800b55f .word 0x0800b55f
err++;
}
break;
#endif
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
800b364: 687b ldr r3, [r7, #4]
800b366: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b36a: 681b ldr r3, [r3, #0]
800b36c: 687a ldr r2, [r7, #4]
800b36e: 7c12 ldrb r2, [r2, #16]
800b370: f107 0108 add.w r1, r7, #8
800b374: 4610 mov r0, r2
800b376: 4798 blx r3
800b378: 60f8 str r0, [r7, #12]
break;
800b37a: e112 b.n 800b5a2 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800b37c: 687b ldr r3, [r7, #4]
800b37e: 7c1b ldrb r3, [r3, #16]
800b380: 2b00 cmp r3, #0
800b382: d10d bne.n 800b3a0 <USBD_GetDescriptor+0x84>
{
pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
800b384: 687b ldr r3, [r7, #4]
800b386: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b38a: 6a9b ldr r3, [r3, #40] @ 0x28
800b38c: f107 0208 add.w r2, r7, #8
800b390: 4610 mov r0, r2
800b392: 4798 blx r3
800b394: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800b396: 68fb ldr r3, [r7, #12]
800b398: 3301 adds r3, #1
800b39a: 2202 movs r2, #2
800b39c: 701a strb r2, [r3, #0]
else
{
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
800b39e: e100 b.n 800b5a2 <USBD_GetDescriptor+0x286>
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
800b3a0: 687b ldr r3, [r7, #4]
800b3a2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b3a6: 6adb ldr r3, [r3, #44] @ 0x2c
800b3a8: f107 0208 add.w r2, r7, #8
800b3ac: 4610 mov r0, r2
800b3ae: 4798 blx r3
800b3b0: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800b3b2: 68fb ldr r3, [r7, #12]
800b3b4: 3301 adds r3, #1
800b3b6: 2202 movs r2, #2
800b3b8: 701a strb r2, [r3, #0]
break;
800b3ba: e0f2 b.n 800b5a2 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
800b3bc: 683b ldr r3, [r7, #0]
800b3be: 885b ldrh r3, [r3, #2]
800b3c0: b2db uxtb r3, r3
800b3c2: 2b05 cmp r3, #5
800b3c4: f200 80ac bhi.w 800b520 <USBD_GetDescriptor+0x204>
800b3c8: a201 add r2, pc, #4 @ (adr r2, 800b3d0 <USBD_GetDescriptor+0xb4>)
800b3ca: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800b3ce: bf00 nop
800b3d0: 0800b3e9 .word 0x0800b3e9
800b3d4: 0800b41d .word 0x0800b41d
800b3d8: 0800b451 .word 0x0800b451
800b3dc: 0800b485 .word 0x0800b485
800b3e0: 0800b4b9 .word 0x0800b4b9
800b3e4: 0800b4ed .word 0x0800b4ed
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
800b3e8: 687b ldr r3, [r7, #4]
800b3ea: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b3ee: 685b ldr r3, [r3, #4]
800b3f0: 2b00 cmp r3, #0
800b3f2: d00b beq.n 800b40c <USBD_GetDescriptor+0xf0>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
800b3f4: 687b ldr r3, [r7, #4]
800b3f6: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b3fa: 685b ldr r3, [r3, #4]
800b3fc: 687a ldr r2, [r7, #4]
800b3fe: 7c12 ldrb r2, [r2, #16]
800b400: f107 0108 add.w r1, r7, #8
800b404: 4610 mov r0, r2
800b406: 4798 blx r3
800b408: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b40a: e091 b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800b40c: 6839 ldr r1, [r7, #0]
800b40e: 6878 ldr r0, [r7, #4]
800b410: f000 fa94 bl 800b93c <USBD_CtlError>
err++;
800b414: 7afb ldrb r3, [r7, #11]
800b416: 3301 adds r3, #1
800b418: 72fb strb r3, [r7, #11]
break;
800b41a: e089 b.n 800b530 <USBD_GetDescriptor+0x214>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
800b41c: 687b ldr r3, [r7, #4]
800b41e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b422: 689b ldr r3, [r3, #8]
800b424: 2b00 cmp r3, #0
800b426: d00b beq.n 800b440 <USBD_GetDescriptor+0x124>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
800b428: 687b ldr r3, [r7, #4]
800b42a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b42e: 689b ldr r3, [r3, #8]
800b430: 687a ldr r2, [r7, #4]
800b432: 7c12 ldrb r2, [r2, #16]
800b434: f107 0108 add.w r1, r7, #8
800b438: 4610 mov r0, r2
800b43a: 4798 blx r3
800b43c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b43e: e077 b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800b440: 6839 ldr r1, [r7, #0]
800b442: 6878 ldr r0, [r7, #4]
800b444: f000 fa7a bl 800b93c <USBD_CtlError>
err++;
800b448: 7afb ldrb r3, [r7, #11]
800b44a: 3301 adds r3, #1
800b44c: 72fb strb r3, [r7, #11]
break;
800b44e: e06f b.n 800b530 <USBD_GetDescriptor+0x214>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
800b450: 687b ldr r3, [r7, #4]
800b452: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b456: 68db ldr r3, [r3, #12]
800b458: 2b00 cmp r3, #0
800b45a: d00b beq.n 800b474 <USBD_GetDescriptor+0x158>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
800b45c: 687b ldr r3, [r7, #4]
800b45e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b462: 68db ldr r3, [r3, #12]
800b464: 687a ldr r2, [r7, #4]
800b466: 7c12 ldrb r2, [r2, #16]
800b468: f107 0108 add.w r1, r7, #8
800b46c: 4610 mov r0, r2
800b46e: 4798 blx r3
800b470: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b472: e05d b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800b474: 6839 ldr r1, [r7, #0]
800b476: 6878 ldr r0, [r7, #4]
800b478: f000 fa60 bl 800b93c <USBD_CtlError>
err++;
800b47c: 7afb ldrb r3, [r7, #11]
800b47e: 3301 adds r3, #1
800b480: 72fb strb r3, [r7, #11]
break;
800b482: e055 b.n 800b530 <USBD_GetDescriptor+0x214>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
800b484: 687b ldr r3, [r7, #4]
800b486: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b48a: 691b ldr r3, [r3, #16]
800b48c: 2b00 cmp r3, #0
800b48e: d00b beq.n 800b4a8 <USBD_GetDescriptor+0x18c>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
800b490: 687b ldr r3, [r7, #4]
800b492: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b496: 691b ldr r3, [r3, #16]
800b498: 687a ldr r2, [r7, #4]
800b49a: 7c12 ldrb r2, [r2, #16]
800b49c: f107 0108 add.w r1, r7, #8
800b4a0: 4610 mov r0, r2
800b4a2: 4798 blx r3
800b4a4: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b4a6: e043 b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800b4a8: 6839 ldr r1, [r7, #0]
800b4aa: 6878 ldr r0, [r7, #4]
800b4ac: f000 fa46 bl 800b93c <USBD_CtlError>
err++;
800b4b0: 7afb ldrb r3, [r7, #11]
800b4b2: 3301 adds r3, #1
800b4b4: 72fb strb r3, [r7, #11]
break;
800b4b6: e03b b.n 800b530 <USBD_GetDescriptor+0x214>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
800b4b8: 687b ldr r3, [r7, #4]
800b4ba: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b4be: 695b ldr r3, [r3, #20]
800b4c0: 2b00 cmp r3, #0
800b4c2: d00b beq.n 800b4dc <USBD_GetDescriptor+0x1c0>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
800b4c4: 687b ldr r3, [r7, #4]
800b4c6: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b4ca: 695b ldr r3, [r3, #20]
800b4cc: 687a ldr r2, [r7, #4]
800b4ce: 7c12 ldrb r2, [r2, #16]
800b4d0: f107 0108 add.w r1, r7, #8
800b4d4: 4610 mov r0, r2
800b4d6: 4798 blx r3
800b4d8: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b4da: e029 b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800b4dc: 6839 ldr r1, [r7, #0]
800b4de: 6878 ldr r0, [r7, #4]
800b4e0: f000 fa2c bl 800b93c <USBD_CtlError>
err++;
800b4e4: 7afb ldrb r3, [r7, #11]
800b4e6: 3301 adds r3, #1
800b4e8: 72fb strb r3, [r7, #11]
break;
800b4ea: e021 b.n 800b530 <USBD_GetDescriptor+0x214>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
800b4ec: 687b ldr r3, [r7, #4]
800b4ee: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b4f2: 699b ldr r3, [r3, #24]
800b4f4: 2b00 cmp r3, #0
800b4f6: d00b beq.n 800b510 <USBD_GetDescriptor+0x1f4>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
800b4f8: 687b ldr r3, [r7, #4]
800b4fa: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800b4fe: 699b ldr r3, [r3, #24]
800b500: 687a ldr r2, [r7, #4]
800b502: 7c12 ldrb r2, [r2, #16]
800b504: f107 0108 add.w r1, r7, #8
800b508: 4610 mov r0, r2
800b50a: 4798 blx r3
800b50c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b50e: e00f b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800b510: 6839 ldr r1, [r7, #0]
800b512: 6878 ldr r0, [r7, #4]
800b514: f000 fa12 bl 800b93c <USBD_CtlError>
err++;
800b518: 7afb ldrb r3, [r7, #11]
800b51a: 3301 adds r3, #1
800b51c: 72fb strb r3, [r7, #11]
break;
800b51e: e007 b.n 800b530 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
err++;
}
break;
#else
USBD_CtlError(pdev, req);
800b520: 6839 ldr r1, [r7, #0]
800b522: 6878 ldr r0, [r7, #4]
800b524: f000 fa0a bl 800b93c <USBD_CtlError>
err++;
800b528: 7afb ldrb r3, [r7, #11]
800b52a: 3301 adds r3, #1
800b52c: 72fb strb r3, [r7, #11]
#endif
}
break;
800b52e: e038 b.n 800b5a2 <USBD_GetDescriptor+0x286>
800b530: e037 b.n 800b5a2 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800b532: 687b ldr r3, [r7, #4]
800b534: 7c1b ldrb r3, [r3, #16]
800b536: 2b00 cmp r3, #0
800b538: d109 bne.n 800b54e <USBD_GetDescriptor+0x232>
{
pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
800b53a: 687b ldr r3, [r7, #4]
800b53c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b540: 6b5b ldr r3, [r3, #52] @ 0x34
800b542: f107 0208 add.w r2, r7, #8
800b546: 4610 mov r0, r2
800b548: 4798 blx r3
800b54a: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b54c: e029 b.n 800b5a2 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
800b54e: 6839 ldr r1, [r7, #0]
800b550: 6878 ldr r0, [r7, #4]
800b552: f000 f9f3 bl 800b93c <USBD_CtlError>
err++;
800b556: 7afb ldrb r3, [r7, #11]
800b558: 3301 adds r3, #1
800b55a: 72fb strb r3, [r7, #11]
break;
800b55c: e021 b.n 800b5a2 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800b55e: 687b ldr r3, [r7, #4]
800b560: 7c1b ldrb r3, [r3, #16]
800b562: 2b00 cmp r3, #0
800b564: d10d bne.n 800b582 <USBD_GetDescriptor+0x266>
{
pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
800b566: 687b ldr r3, [r7, #4]
800b568: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800b56c: 6b1b ldr r3, [r3, #48] @ 0x30
800b56e: f107 0208 add.w r2, r7, #8
800b572: 4610 mov r0, r2
800b574: 4798 blx r3
800b576: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
800b578: 68fb ldr r3, [r7, #12]
800b57a: 3301 adds r3, #1
800b57c: 2207 movs r2, #7
800b57e: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800b580: e00f b.n 800b5a2 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
800b582: 6839 ldr r1, [r7, #0]
800b584: 6878 ldr r0, [r7, #4]
800b586: f000 f9d9 bl 800b93c <USBD_CtlError>
err++;
800b58a: 7afb ldrb r3, [r7, #11]
800b58c: 3301 adds r3, #1
800b58e: 72fb strb r3, [r7, #11]
break;
800b590: e007 b.n 800b5a2 <USBD_GetDescriptor+0x286>
default:
USBD_CtlError(pdev, req);
800b592: 6839 ldr r1, [r7, #0]
800b594: 6878 ldr r0, [r7, #4]
800b596: f000 f9d1 bl 800b93c <USBD_CtlError>
err++;
800b59a: 7afb ldrb r3, [r7, #11]
800b59c: 3301 adds r3, #1
800b59e: 72fb strb r3, [r7, #11]
break;
800b5a0: bf00 nop
}
if (err != 0U)
800b5a2: 7afb ldrb r3, [r7, #11]
800b5a4: 2b00 cmp r3, #0
800b5a6: d11c bne.n 800b5e2 <USBD_GetDescriptor+0x2c6>
{
return;
}
else
{
if ((len != 0U) && (req->wLength != 0U))
800b5a8: 893b ldrh r3, [r7, #8]
800b5aa: 2b00 cmp r3, #0
800b5ac: d011 beq.n 800b5d2 <USBD_GetDescriptor+0x2b6>
800b5ae: 683b ldr r3, [r7, #0]
800b5b0: 88db ldrh r3, [r3, #6]
800b5b2: 2b00 cmp r3, #0
800b5b4: d00d beq.n 800b5d2 <USBD_GetDescriptor+0x2b6>
{
len = MIN(len, req->wLength);
800b5b6: 683b ldr r3, [r7, #0]
800b5b8: 88da ldrh r2, [r3, #6]
800b5ba: 893b ldrh r3, [r7, #8]
800b5bc: 4293 cmp r3, r2
800b5be: bf28 it cs
800b5c0: 4613 movcs r3, r2
800b5c2: b29b uxth r3, r3
800b5c4: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
800b5c6: 893b ldrh r3, [r7, #8]
800b5c8: 461a mov r2, r3
800b5ca: 68f9 ldr r1, [r7, #12]
800b5cc: 6878 ldr r0, [r7, #4]
800b5ce: f000 fa1f bl 800ba10 <USBD_CtlSendData>
}
if (req->wLength == 0U)
800b5d2: 683b ldr r3, [r7, #0]
800b5d4: 88db ldrh r3, [r3, #6]
800b5d6: 2b00 cmp r3, #0
800b5d8: d104 bne.n 800b5e4 <USBD_GetDescriptor+0x2c8>
{
(void)USBD_CtlSendStatus(pdev);
800b5da: 6878 ldr r0, [r7, #4]
800b5dc: f000 fa76 bl 800bacc <USBD_CtlSendStatus>
800b5e0: e000 b.n 800b5e4 <USBD_GetDescriptor+0x2c8>
return;
800b5e2: bf00 nop
}
}
}
800b5e4: 3710 adds r7, #16
800b5e6: 46bd mov sp, r7
800b5e8: bd80 pop {r7, pc}
800b5ea: bf00 nop
0800b5ec <USBD_SetAddress>:
* @param req: usb request
* @retval status
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800b5ec: b580 push {r7, lr}
800b5ee: b084 sub sp, #16
800b5f0: af00 add r7, sp, #0
800b5f2: 6078 str r0, [r7, #4]
800b5f4: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
800b5f6: 683b ldr r3, [r7, #0]
800b5f8: 889b ldrh r3, [r3, #4]
800b5fa: 2b00 cmp r3, #0
800b5fc: d130 bne.n 800b660 <USBD_SetAddress+0x74>
800b5fe: 683b ldr r3, [r7, #0]
800b600: 88db ldrh r3, [r3, #6]
800b602: 2b00 cmp r3, #0
800b604: d12c bne.n 800b660 <USBD_SetAddress+0x74>
800b606: 683b ldr r3, [r7, #0]
800b608: 885b ldrh r3, [r3, #2]
800b60a: 2b7f cmp r3, #127 @ 0x7f
800b60c: d828 bhi.n 800b660 <USBD_SetAddress+0x74>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
800b60e: 683b ldr r3, [r7, #0]
800b610: 885b ldrh r3, [r3, #2]
800b612: b2db uxtb r3, r3
800b614: f003 037f and.w r3, r3, #127 @ 0x7f
800b618: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800b61a: 687b ldr r3, [r7, #4]
800b61c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b620: 2b03 cmp r3, #3
800b622: d104 bne.n 800b62e <USBD_SetAddress+0x42>
{
USBD_CtlError(pdev, req);
800b624: 6839 ldr r1, [r7, #0]
800b626: 6878 ldr r0, [r7, #4]
800b628: f000 f988 bl 800b93c <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800b62c: e01d b.n 800b66a <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_address = dev_addr;
800b62e: 687b ldr r3, [r7, #4]
800b630: 7bfa ldrb r2, [r7, #15]
800b632: f883 229e strb.w r2, [r3, #670] @ 0x29e
USBD_LL_SetUSBAddress(pdev, dev_addr);
800b636: 7bfb ldrb r3, [r7, #15]
800b638: 4619 mov r1, r3
800b63a: 6878 ldr r0, [r7, #4]
800b63c: f000 fec1 bl 800c3c2 <USBD_LL_SetUSBAddress>
USBD_CtlSendStatus(pdev);
800b640: 6878 ldr r0, [r7, #4]
800b642: f000 fa43 bl 800bacc <USBD_CtlSendStatus>
if (dev_addr != 0U)
800b646: 7bfb ldrb r3, [r7, #15]
800b648: 2b00 cmp r3, #0
800b64a: d004 beq.n 800b656 <USBD_SetAddress+0x6a>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800b64c: 687b ldr r3, [r7, #4]
800b64e: 2202 movs r2, #2
800b650: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800b654: e009 b.n 800b66a <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
800b656: 687b ldr r3, [r7, #4]
800b658: 2201 movs r2, #1
800b65a: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800b65e: e004 b.n 800b66a <USBD_SetAddress+0x7e>
}
}
}
else
{
USBD_CtlError(pdev, req);
800b660: 6839 ldr r1, [r7, #0]
800b662: 6878 ldr r0, [r7, #4]
800b664: f000 f96a bl 800b93c <USBD_CtlError>
}
}
800b668: bf00 nop
800b66a: bf00 nop
800b66c: 3710 adds r7, #16
800b66e: 46bd mov sp, r7
800b670: bd80 pop {r7, pc}
...
0800b674 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800b674: b580 push {r7, lr}
800b676: b082 sub sp, #8
800b678: af00 add r7, sp, #0
800b67a: 6078 str r0, [r7, #4]
800b67c: 6039 str r1, [r7, #0]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
800b67e: 683b ldr r3, [r7, #0]
800b680: 885b ldrh r3, [r3, #2]
800b682: b2da uxtb r2, r3
800b684: 4b41 ldr r3, [pc, #260] @ (800b78c <USBD_SetConfig+0x118>)
800b686: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
800b688: 4b40 ldr r3, [pc, #256] @ (800b78c <USBD_SetConfig+0x118>)
800b68a: 781b ldrb r3, [r3, #0]
800b68c: 2b01 cmp r3, #1
800b68e: d904 bls.n 800b69a <USBD_SetConfig+0x26>
{
USBD_CtlError(pdev, req);
800b690: 6839 ldr r1, [r7, #0]
800b692: 6878 ldr r0, [r7, #4]
800b694: f000 f952 bl 800b93c <USBD_CtlError>
800b698: e075 b.n 800b786 <USBD_SetConfig+0x112>
}
else
{
switch (pdev->dev_state)
800b69a: 687b ldr r3, [r7, #4]
800b69c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b6a0: 2b02 cmp r3, #2
800b6a2: d002 beq.n 800b6aa <USBD_SetConfig+0x36>
800b6a4: 2b03 cmp r3, #3
800b6a6: d023 beq.n 800b6f0 <USBD_SetConfig+0x7c>
800b6a8: e062 b.n 800b770 <USBD_SetConfig+0xfc>
{
case USBD_STATE_ADDRESSED:
if (cfgidx)
800b6aa: 4b38 ldr r3, [pc, #224] @ (800b78c <USBD_SetConfig+0x118>)
800b6ac: 781b ldrb r3, [r3, #0]
800b6ae: 2b00 cmp r3, #0
800b6b0: d01a beq.n 800b6e8 <USBD_SetConfig+0x74>
{
pdev->dev_config = cfgidx;
800b6b2: 4b36 ldr r3, [pc, #216] @ (800b78c <USBD_SetConfig+0x118>)
800b6b4: 781b ldrb r3, [r3, #0]
800b6b6: 461a mov r2, r3
800b6b8: 687b ldr r3, [r7, #4]
800b6ba: 605a str r2, [r3, #4]
pdev->dev_state = USBD_STATE_CONFIGURED;
800b6bc: 687b ldr r3, [r7, #4]
800b6be: 2203 movs r2, #3
800b6c0: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800b6c4: 4b31 ldr r3, [pc, #196] @ (800b78c <USBD_SetConfig+0x118>)
800b6c6: 781b ldrb r3, [r3, #0]
800b6c8: 4619 mov r1, r3
800b6ca: 6878 ldr r0, [r7, #4]
800b6cc: f7ff f9e7 bl 800aa9e <USBD_SetClassConfig>
800b6d0: 4603 mov r3, r0
800b6d2: 2b02 cmp r3, #2
800b6d4: d104 bne.n 800b6e0 <USBD_SetConfig+0x6c>
{
USBD_CtlError(pdev, req);
800b6d6: 6839 ldr r1, [r7, #0]
800b6d8: 6878 ldr r0, [r7, #4]
800b6da: f000 f92f bl 800b93c <USBD_CtlError>
return;
800b6de: e052 b.n 800b786 <USBD_SetConfig+0x112>
}
USBD_CtlSendStatus(pdev);
800b6e0: 6878 ldr r0, [r7, #4]
800b6e2: f000 f9f3 bl 800bacc <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800b6e6: e04e b.n 800b786 <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800b6e8: 6878 ldr r0, [r7, #4]
800b6ea: f000 f9ef bl 800bacc <USBD_CtlSendStatus>
break;
800b6ee: e04a b.n 800b786 <USBD_SetConfig+0x112>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
800b6f0: 4b26 ldr r3, [pc, #152] @ (800b78c <USBD_SetConfig+0x118>)
800b6f2: 781b ldrb r3, [r3, #0]
800b6f4: 2b00 cmp r3, #0
800b6f6: d112 bne.n 800b71e <USBD_SetConfig+0xaa>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
800b6f8: 687b ldr r3, [r7, #4]
800b6fa: 2202 movs r2, #2
800b6fc: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
800b700: 4b22 ldr r3, [pc, #136] @ (800b78c <USBD_SetConfig+0x118>)
800b702: 781b ldrb r3, [r3, #0]
800b704: 461a mov r2, r3
800b706: 687b ldr r3, [r7, #4]
800b708: 605a str r2, [r3, #4]
USBD_ClrClassConfig(pdev, cfgidx);
800b70a: 4b20 ldr r3, [pc, #128] @ (800b78c <USBD_SetConfig+0x118>)
800b70c: 781b ldrb r3, [r3, #0]
800b70e: 4619 mov r1, r3
800b710: 6878 ldr r0, [r7, #4]
800b712: f7ff f9e3 bl 800aadc <USBD_ClrClassConfig>
USBD_CtlSendStatus(pdev);
800b716: 6878 ldr r0, [r7, #4]
800b718: f000 f9d8 bl 800bacc <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800b71c: e033 b.n 800b786 <USBD_SetConfig+0x112>
else if (cfgidx != pdev->dev_config)
800b71e: 4b1b ldr r3, [pc, #108] @ (800b78c <USBD_SetConfig+0x118>)
800b720: 781b ldrb r3, [r3, #0]
800b722: 461a mov r2, r3
800b724: 687b ldr r3, [r7, #4]
800b726: 685b ldr r3, [r3, #4]
800b728: 429a cmp r2, r3
800b72a: d01d beq.n 800b768 <USBD_SetConfig+0xf4>
USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
800b72c: 687b ldr r3, [r7, #4]
800b72e: 685b ldr r3, [r3, #4]
800b730: b2db uxtb r3, r3
800b732: 4619 mov r1, r3
800b734: 6878 ldr r0, [r7, #4]
800b736: f7ff f9d1 bl 800aadc <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
800b73a: 4b14 ldr r3, [pc, #80] @ (800b78c <USBD_SetConfig+0x118>)
800b73c: 781b ldrb r3, [r3, #0]
800b73e: 461a mov r2, r3
800b740: 687b ldr r3, [r7, #4]
800b742: 605a str r2, [r3, #4]
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800b744: 4b11 ldr r3, [pc, #68] @ (800b78c <USBD_SetConfig+0x118>)
800b746: 781b ldrb r3, [r3, #0]
800b748: 4619 mov r1, r3
800b74a: 6878 ldr r0, [r7, #4]
800b74c: f7ff f9a7 bl 800aa9e <USBD_SetClassConfig>
800b750: 4603 mov r3, r0
800b752: 2b02 cmp r3, #2
800b754: d104 bne.n 800b760 <USBD_SetConfig+0xec>
USBD_CtlError(pdev, req);
800b756: 6839 ldr r1, [r7, #0]
800b758: 6878 ldr r0, [r7, #4]
800b75a: f000 f8ef bl 800b93c <USBD_CtlError>
return;
800b75e: e012 b.n 800b786 <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800b760: 6878 ldr r0, [r7, #4]
800b762: f000 f9b3 bl 800bacc <USBD_CtlSendStatus>
break;
800b766: e00e b.n 800b786 <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800b768: 6878 ldr r0, [r7, #4]
800b76a: f000 f9af bl 800bacc <USBD_CtlSendStatus>
break;
800b76e: e00a b.n 800b786 <USBD_SetConfig+0x112>
default:
USBD_CtlError(pdev, req);
800b770: 6839 ldr r1, [r7, #0]
800b772: 6878 ldr r0, [r7, #4]
800b774: f000 f8e2 bl 800b93c <USBD_CtlError>
USBD_ClrClassConfig(pdev, cfgidx);
800b778: 4b04 ldr r3, [pc, #16] @ (800b78c <USBD_SetConfig+0x118>)
800b77a: 781b ldrb r3, [r3, #0]
800b77c: 4619 mov r1, r3
800b77e: 6878 ldr r0, [r7, #4]
800b780: f7ff f9ac bl 800aadc <USBD_ClrClassConfig>
break;
800b784: bf00 nop
}
}
}
800b786: 3708 adds r7, #8
800b788: 46bd mov sp, r7
800b78a: bd80 pop {r7, pc}
800b78c: 20000458 .word 0x20000458
0800b790 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800b790: b580 push {r7, lr}
800b792: b082 sub sp, #8
800b794: af00 add r7, sp, #0
800b796: 6078 str r0, [r7, #4]
800b798: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
800b79a: 683b ldr r3, [r7, #0]
800b79c: 88db ldrh r3, [r3, #6]
800b79e: 2b01 cmp r3, #1
800b7a0: d004 beq.n 800b7ac <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
800b7a2: 6839 ldr r1, [r7, #0]
800b7a4: 6878 ldr r0, [r7, #4]
800b7a6: f000 f8c9 bl 800b93c <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
800b7aa: e022 b.n 800b7f2 <USBD_GetConfig+0x62>
switch (pdev->dev_state)
800b7ac: 687b ldr r3, [r7, #4]
800b7ae: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b7b2: 2b02 cmp r3, #2
800b7b4: dc02 bgt.n 800b7bc <USBD_GetConfig+0x2c>
800b7b6: 2b00 cmp r3, #0
800b7b8: dc03 bgt.n 800b7c2 <USBD_GetConfig+0x32>
800b7ba: e015 b.n 800b7e8 <USBD_GetConfig+0x58>
800b7bc: 2b03 cmp r3, #3
800b7be: d00b beq.n 800b7d8 <USBD_GetConfig+0x48>
800b7c0: e012 b.n 800b7e8 <USBD_GetConfig+0x58>
pdev->dev_default_config = 0U;
800b7c2: 687b ldr r3, [r7, #4]
800b7c4: 2200 movs r2, #0
800b7c6: 609a str r2, [r3, #8]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
800b7c8: 687b ldr r3, [r7, #4]
800b7ca: 3308 adds r3, #8
800b7cc: 2201 movs r2, #1
800b7ce: 4619 mov r1, r3
800b7d0: 6878 ldr r0, [r7, #4]
800b7d2: f000 f91d bl 800ba10 <USBD_CtlSendData>
break;
800b7d6: e00c b.n 800b7f2 <USBD_GetConfig+0x62>
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
800b7d8: 687b ldr r3, [r7, #4]
800b7da: 3304 adds r3, #4
800b7dc: 2201 movs r2, #1
800b7de: 4619 mov r1, r3
800b7e0: 6878 ldr r0, [r7, #4]
800b7e2: f000 f915 bl 800ba10 <USBD_CtlSendData>
break;
800b7e6: e004 b.n 800b7f2 <USBD_GetConfig+0x62>
USBD_CtlError(pdev, req);
800b7e8: 6839 ldr r1, [r7, #0]
800b7ea: 6878 ldr r0, [r7, #4]
800b7ec: f000 f8a6 bl 800b93c <USBD_CtlError>
break;
800b7f0: bf00 nop
}
800b7f2: bf00 nop
800b7f4: 3708 adds r7, #8
800b7f6: 46bd mov sp, r7
800b7f8: bd80 pop {r7, pc}
0800b7fa <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
800b7fa: b580 push {r7, lr}
800b7fc: b082 sub sp, #8
800b7fe: af00 add r7, sp, #0
800b800: 6078 str r0, [r7, #4]
800b802: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800b804: 687b ldr r3, [r7, #4]
800b806: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b80a: 3b01 subs r3, #1
800b80c: 2b02 cmp r3, #2
800b80e: d81e bhi.n 800b84e <USBD_GetStatus+0x54>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
800b810: 683b ldr r3, [r7, #0]
800b812: 88db ldrh r3, [r3, #6]
800b814: 2b02 cmp r3, #2
800b816: d004 beq.n 800b822 <USBD_GetStatus+0x28>
{
USBD_CtlError(pdev, req);
800b818: 6839 ldr r1, [r7, #0]
800b81a: 6878 ldr r0, [r7, #4]
800b81c: f000 f88e bl 800b93c <USBD_CtlError>
break;
800b820: e01a b.n 800b858 <USBD_GetStatus+0x5e>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
800b822: 687b ldr r3, [r7, #4]
800b824: 2201 movs r2, #1
800b826: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif
if (pdev->dev_remote_wakeup)
800b828: 687b ldr r3, [r7, #4]
800b82a: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
800b82e: 2b00 cmp r3, #0
800b830: d005 beq.n 800b83e <USBD_GetStatus+0x44>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
800b832: 687b ldr r3, [r7, #4]
800b834: 68db ldr r3, [r3, #12]
800b836: f043 0202 orr.w r2, r3, #2
800b83a: 687b ldr r3, [r7, #4]
800b83c: 60da str r2, [r3, #12]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
800b83e: 687b ldr r3, [r7, #4]
800b840: 330c adds r3, #12
800b842: 2202 movs r2, #2
800b844: 4619 mov r1, r3
800b846: 6878 ldr r0, [r7, #4]
800b848: f000 f8e2 bl 800ba10 <USBD_CtlSendData>
break;
800b84c: e004 b.n 800b858 <USBD_GetStatus+0x5e>
default:
USBD_CtlError(pdev, req);
800b84e: 6839 ldr r1, [r7, #0]
800b850: 6878 ldr r0, [r7, #4]
800b852: f000 f873 bl 800b93c <USBD_CtlError>
break;
800b856: bf00 nop
}
}
800b858: bf00 nop
800b85a: 3708 adds r7, #8
800b85c: 46bd mov sp, r7
800b85e: bd80 pop {r7, pc}
0800b860 <USBD_SetFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800b860: b580 push {r7, lr}
800b862: b082 sub sp, #8
800b864: af00 add r7, sp, #0
800b866: 6078 str r0, [r7, #4]
800b868: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800b86a: 683b ldr r3, [r7, #0]
800b86c: 885b ldrh r3, [r3, #2]
800b86e: 2b01 cmp r3, #1
800b870: d106 bne.n 800b880 <USBD_SetFeature+0x20>
{
pdev->dev_remote_wakeup = 1U;
800b872: 687b ldr r3, [r7, #4]
800b874: 2201 movs r2, #1
800b876: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800b87a: 6878 ldr r0, [r7, #4]
800b87c: f000 f926 bl 800bacc <USBD_CtlSendStatus>
}
}
800b880: bf00 nop
800b882: 3708 adds r7, #8
800b884: 46bd mov sp, r7
800b886: bd80 pop {r7, pc}
0800b888 <USBD_ClrFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800b888: b580 push {r7, lr}
800b88a: b082 sub sp, #8
800b88c: af00 add r7, sp, #0
800b88e: 6078 str r0, [r7, #4]
800b890: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800b892: 687b ldr r3, [r7, #4]
800b894: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800b898: 3b01 subs r3, #1
800b89a: 2b02 cmp r3, #2
800b89c: d80b bhi.n 800b8b6 <USBD_ClrFeature+0x2e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800b89e: 683b ldr r3, [r7, #0]
800b8a0: 885b ldrh r3, [r3, #2]
800b8a2: 2b01 cmp r3, #1
800b8a4: d10c bne.n 800b8c0 <USBD_ClrFeature+0x38>
{
pdev->dev_remote_wakeup = 0U;
800b8a6: 687b ldr r3, [r7, #4]
800b8a8: 2200 movs r2, #0
800b8aa: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800b8ae: 6878 ldr r0, [r7, #4]
800b8b0: f000 f90c bl 800bacc <USBD_CtlSendStatus>
}
break;
800b8b4: e004 b.n 800b8c0 <USBD_ClrFeature+0x38>
default:
USBD_CtlError(pdev, req);
800b8b6: 6839 ldr r1, [r7, #0]
800b8b8: 6878 ldr r0, [r7, #4]
800b8ba: f000 f83f bl 800b93c <USBD_CtlError>
break;
800b8be: e000 b.n 800b8c2 <USBD_ClrFeature+0x3a>
break;
800b8c0: bf00 nop
}
}
800b8c2: bf00 nop
800b8c4: 3708 adds r7, #8
800b8c6: 46bd mov sp, r7
800b8c8: bd80 pop {r7, pc}
0800b8ca <USBD_ParseSetupRequest>:
* @param req: usb request
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
800b8ca: b480 push {r7}
800b8cc: b083 sub sp, #12
800b8ce: af00 add r7, sp, #0
800b8d0: 6078 str r0, [r7, #4]
800b8d2: 6039 str r1, [r7, #0]
req->bmRequest = *(uint8_t *)(pdata);
800b8d4: 683b ldr r3, [r7, #0]
800b8d6: 781a ldrb r2, [r3, #0]
800b8d8: 687b ldr r3, [r7, #4]
800b8da: 701a strb r2, [r3, #0]
req->bRequest = *(uint8_t *)(pdata + 1U);
800b8dc: 683b ldr r3, [r7, #0]
800b8de: 785a ldrb r2, [r3, #1]
800b8e0: 687b ldr r3, [r7, #4]
800b8e2: 705a strb r2, [r3, #1]
req->wValue = SWAPBYTE(pdata + 2U);
800b8e4: 683b ldr r3, [r7, #0]
800b8e6: 3302 adds r3, #2
800b8e8: 781b ldrb r3, [r3, #0]
800b8ea: 461a mov r2, r3
800b8ec: 683b ldr r3, [r7, #0]
800b8ee: 3303 adds r3, #3
800b8f0: 781b ldrb r3, [r3, #0]
800b8f2: 021b lsls r3, r3, #8
800b8f4: b29b uxth r3, r3
800b8f6: 4413 add r3, r2
800b8f8: b29a uxth r2, r3
800b8fa: 687b ldr r3, [r7, #4]
800b8fc: 805a strh r2, [r3, #2]
req->wIndex = SWAPBYTE(pdata + 4U);
800b8fe: 683b ldr r3, [r7, #0]
800b900: 3304 adds r3, #4
800b902: 781b ldrb r3, [r3, #0]
800b904: 461a mov r2, r3
800b906: 683b ldr r3, [r7, #0]
800b908: 3305 adds r3, #5
800b90a: 781b ldrb r3, [r3, #0]
800b90c: 021b lsls r3, r3, #8
800b90e: b29b uxth r3, r3
800b910: 4413 add r3, r2
800b912: b29a uxth r2, r3
800b914: 687b ldr r3, [r7, #4]
800b916: 809a strh r2, [r3, #4]
req->wLength = SWAPBYTE(pdata + 6U);
800b918: 683b ldr r3, [r7, #0]
800b91a: 3306 adds r3, #6
800b91c: 781b ldrb r3, [r3, #0]
800b91e: 461a mov r2, r3
800b920: 683b ldr r3, [r7, #0]
800b922: 3307 adds r3, #7
800b924: 781b ldrb r3, [r3, #0]
800b926: 021b lsls r3, r3, #8
800b928: b29b uxth r3, r3
800b92a: 4413 add r3, r2
800b92c: b29a uxth r2, r3
800b92e: 687b ldr r3, [r7, #4]
800b930: 80da strh r2, [r3, #6]
}
800b932: bf00 nop
800b934: 370c adds r7, #12
800b936: 46bd mov sp, r7
800b938: bc80 pop {r7}
800b93a: 4770 bx lr
0800b93c <USBD_CtlError>:
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800b93c: b580 push {r7, lr}
800b93e: b082 sub sp, #8
800b940: af00 add r7, sp, #0
800b942: 6078 str r0, [r7, #4]
800b944: 6039 str r1, [r7, #0]
USBD_LL_StallEP(pdev, 0x80U);
800b946: 2180 movs r1, #128 @ 0x80
800b948: 6878 ldr r0, [r7, #4]
800b94a: f000 fcd1 bl 800c2f0 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0U);
800b94e: 2100 movs r1, #0
800b950: 6878 ldr r0, [r7, #4]
800b952: f000 fccd bl 800c2f0 <USBD_LL_StallEP>
}
800b956: bf00 nop
800b958: 3708 adds r7, #8
800b95a: 46bd mov sp, r7
800b95c: bd80 pop {r7, pc}
0800b95e <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
800b95e: b580 push {r7, lr}
800b960: b086 sub sp, #24
800b962: af00 add r7, sp, #0
800b964: 60f8 str r0, [r7, #12]
800b966: 60b9 str r1, [r7, #8]
800b968: 607a str r2, [r7, #4]
uint8_t idx = 0U;
800b96a: 2300 movs r3, #0
800b96c: 75fb strb r3, [r7, #23]
if (desc != NULL)
800b96e: 68fb ldr r3, [r7, #12]
800b970: 2b00 cmp r3, #0
800b972: d032 beq.n 800b9da <USBD_GetString+0x7c>
{
*len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
800b974: 68f8 ldr r0, [r7, #12]
800b976: f000 f834 bl 800b9e2 <USBD_GetLen>
800b97a: 4603 mov r3, r0
800b97c: 3301 adds r3, #1
800b97e: b29b uxth r3, r3
800b980: 005b lsls r3, r3, #1
800b982: b29a uxth r2, r3
800b984: 687b ldr r3, [r7, #4]
800b986: 801a strh r2, [r3, #0]
unicode[idx++] = *(uint8_t *)(void *)len;
800b988: 7dfb ldrb r3, [r7, #23]
800b98a: 1c5a adds r2, r3, #1
800b98c: 75fa strb r2, [r7, #23]
800b98e: 461a mov r2, r3
800b990: 68bb ldr r3, [r7, #8]
800b992: 4413 add r3, r2
800b994: 687a ldr r2, [r7, #4]
800b996: 7812 ldrb r2, [r2, #0]
800b998: 701a strb r2, [r3, #0]
unicode[idx++] = USB_DESC_TYPE_STRING;
800b99a: 7dfb ldrb r3, [r7, #23]
800b99c: 1c5a adds r2, r3, #1
800b99e: 75fa strb r2, [r7, #23]
800b9a0: 461a mov r2, r3
800b9a2: 68bb ldr r3, [r7, #8]
800b9a4: 4413 add r3, r2
800b9a6: 2203 movs r2, #3
800b9a8: 701a strb r2, [r3, #0]
while (*desc != '\0')
800b9aa: e012 b.n 800b9d2 <USBD_GetString+0x74>
{
unicode[idx++] = *desc++;
800b9ac: 68fb ldr r3, [r7, #12]
800b9ae: 1c5a adds r2, r3, #1
800b9b0: 60fa str r2, [r7, #12]
800b9b2: 7dfa ldrb r2, [r7, #23]
800b9b4: 1c51 adds r1, r2, #1
800b9b6: 75f9 strb r1, [r7, #23]
800b9b8: 4611 mov r1, r2
800b9ba: 68ba ldr r2, [r7, #8]
800b9bc: 440a add r2, r1
800b9be: 781b ldrb r3, [r3, #0]
800b9c0: 7013 strb r3, [r2, #0]
unicode[idx++] = 0U;
800b9c2: 7dfb ldrb r3, [r7, #23]
800b9c4: 1c5a adds r2, r3, #1
800b9c6: 75fa strb r2, [r7, #23]
800b9c8: 461a mov r2, r3
800b9ca: 68bb ldr r3, [r7, #8]
800b9cc: 4413 add r3, r2
800b9ce: 2200 movs r2, #0
800b9d0: 701a strb r2, [r3, #0]
while (*desc != '\0')
800b9d2: 68fb ldr r3, [r7, #12]
800b9d4: 781b ldrb r3, [r3, #0]
800b9d6: 2b00 cmp r3, #0
800b9d8: d1e8 bne.n 800b9ac <USBD_GetString+0x4e>
}
}
}
800b9da: bf00 nop
800b9dc: 3718 adds r7, #24
800b9de: 46bd mov sp, r7
800b9e0: bd80 pop {r7, pc}
0800b9e2 <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
800b9e2: b480 push {r7}
800b9e4: b085 sub sp, #20
800b9e6: af00 add r7, sp, #0
800b9e8: 6078 str r0, [r7, #4]
uint8_t len = 0U;
800b9ea: 2300 movs r3, #0
800b9ec: 73fb strb r3, [r7, #15]
while (*buf != '\0')
800b9ee: e005 b.n 800b9fc <USBD_GetLen+0x1a>
{
len++;
800b9f0: 7bfb ldrb r3, [r7, #15]
800b9f2: 3301 adds r3, #1
800b9f4: 73fb strb r3, [r7, #15]
buf++;
800b9f6: 687b ldr r3, [r7, #4]
800b9f8: 3301 adds r3, #1
800b9fa: 607b str r3, [r7, #4]
while (*buf != '\0')
800b9fc: 687b ldr r3, [r7, #4]
800b9fe: 781b ldrb r3, [r3, #0]
800ba00: 2b00 cmp r3, #0
800ba02: d1f5 bne.n 800b9f0 <USBD_GetLen+0xe>
}
return len;
800ba04: 7bfb ldrb r3, [r7, #15]
}
800ba06: 4618 mov r0, r3
800ba08: 3714 adds r7, #20
800ba0a: 46bd mov sp, r7
800ba0c: bc80 pop {r7}
800ba0e: 4770 bx lr
0800ba10 <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800ba10: b580 push {r7, lr}
800ba12: b084 sub sp, #16
800ba14: af00 add r7, sp, #0
800ba16: 60f8 str r0, [r7, #12]
800ba18: 60b9 str r1, [r7, #8]
800ba1a: 4613 mov r3, r2
800ba1c: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
800ba1e: 68fb ldr r3, [r7, #12]
800ba20: 2202 movs r2, #2
800ba22: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
800ba26: 88fa ldrh r2, [r7, #6]
800ba28: 68fb ldr r3, [r7, #12]
800ba2a: 61da str r2, [r3, #28]
pdev->ep_in[0].rem_length = len;
800ba2c: 88fa ldrh r2, [r7, #6]
800ba2e: 68fb ldr r3, [r7, #12]
800ba30: 621a str r2, [r3, #32]
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800ba32: 88fb ldrh r3, [r7, #6]
800ba34: 68ba ldr r2, [r7, #8]
800ba36: 2100 movs r1, #0
800ba38: 68f8 ldr r0, [r7, #12]
800ba3a: f000 fce1 bl 800c400 <USBD_LL_Transmit>
return USBD_OK;
800ba3e: 2300 movs r3, #0
}
800ba40: 4618 mov r0, r3
800ba42: 3710 adds r7, #16
800ba44: 46bd mov sp, r7
800ba46: bd80 pop {r7, pc}
0800ba48 <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800ba48: b580 push {r7, lr}
800ba4a: b084 sub sp, #16
800ba4c: af00 add r7, sp, #0
800ba4e: 60f8 str r0, [r7, #12]
800ba50: 60b9 str r1, [r7, #8]
800ba52: 4613 mov r3, r2
800ba54: 80fb strh r3, [r7, #6]
/* Start the next transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800ba56: 88fb ldrh r3, [r7, #6]
800ba58: 68ba ldr r2, [r7, #8]
800ba5a: 2100 movs r1, #0
800ba5c: 68f8 ldr r0, [r7, #12]
800ba5e: f000 fccf bl 800c400 <USBD_LL_Transmit>
return USBD_OK;
800ba62: 2300 movs r3, #0
}
800ba64: 4618 mov r0, r3
800ba66: 3710 adds r7, #16
800ba68: 46bd mov sp, r7
800ba6a: bd80 pop {r7, pc}
0800ba6c <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800ba6c: b580 push {r7, lr}
800ba6e: b084 sub sp, #16
800ba70: af00 add r7, sp, #0
800ba72: 60f8 str r0, [r7, #12]
800ba74: 60b9 str r1, [r7, #8]
800ba76: 4613 mov r3, r2
800ba78: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
800ba7a: 68fb ldr r3, [r7, #12]
800ba7c: 2203 movs r2, #3
800ba7e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_out[0].total_length = len;
800ba82: 88fa ldrh r2, [r7, #6]
800ba84: 68fb ldr r3, [r7, #12]
800ba86: f8c3 215c str.w r2, [r3, #348] @ 0x15c
pdev->ep_out[0].rem_length = len;
800ba8a: 88fa ldrh r2, [r7, #6]
800ba8c: 68fb ldr r3, [r7, #12]
800ba8e: f8c3 2160 str.w r2, [r3, #352] @ 0x160
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800ba92: 88fb ldrh r3, [r7, #6]
800ba94: 68ba ldr r2, [r7, #8]
800ba96: 2100 movs r1, #0
800ba98: 68f8 ldr r0, [r7, #12]
800ba9a: f000 fcd4 bl 800c446 <USBD_LL_PrepareReceive>
return USBD_OK;
800ba9e: 2300 movs r3, #0
}
800baa0: 4618 mov r0, r3
800baa2: 3710 adds r7, #16
800baa4: 46bd mov sp, r7
800baa6: bd80 pop {r7, pc}
0800baa8 <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800baa8: b580 push {r7, lr}
800baaa: b084 sub sp, #16
800baac: af00 add r7, sp, #0
800baae: 60f8 str r0, [r7, #12]
800bab0: 60b9 str r1, [r7, #8]
800bab2: 4613 mov r3, r2
800bab4: 80fb strh r3, [r7, #6]
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800bab6: 88fb ldrh r3, [r7, #6]
800bab8: 68ba ldr r2, [r7, #8]
800baba: 2100 movs r1, #0
800babc: 68f8 ldr r0, [r7, #12]
800babe: f000 fcc2 bl 800c446 <USBD_LL_PrepareReceive>
return USBD_OK;
800bac2: 2300 movs r3, #0
}
800bac4: 4618 mov r0, r3
800bac6: 3710 adds r7, #16
800bac8: 46bd mov sp, r7
800baca: bd80 pop {r7, pc}
0800bacc <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
800bacc: b580 push {r7, lr}
800bace: b082 sub sp, #8
800bad0: af00 add r7, sp, #0
800bad2: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
800bad4: 687b ldr r3, [r7, #4]
800bad6: 2204 movs r2, #4
800bad8: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
800badc: 2300 movs r3, #0
800bade: 2200 movs r2, #0
800bae0: 2100 movs r1, #0
800bae2: 6878 ldr r0, [r7, #4]
800bae4: f000 fc8c bl 800c400 <USBD_LL_Transmit>
return USBD_OK;
800bae8: 2300 movs r3, #0
}
800baea: 4618 mov r0, r3
800baec: 3708 adds r7, #8
800baee: 46bd mov sp, r7
800baf0: bd80 pop {r7, pc}
0800baf2 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
800baf2: b580 push {r7, lr}
800baf4: b082 sub sp, #8
800baf6: af00 add r7, sp, #0
800baf8: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
800bafa: 687b ldr r3, [r7, #4]
800bafc: 2205 movs r2, #5
800bafe: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800bb02: 2300 movs r3, #0
800bb04: 2200 movs r2, #0
800bb06: 2100 movs r1, #0
800bb08: 6878 ldr r0, [r7, #4]
800bb0a: f000 fc9c bl 800c446 <USBD_LL_PrepareReceive>
return USBD_OK;
800bb0e: 2300 movs r3, #0
}
800bb10: 4618 mov r0, r3
800bb12: 3708 adds r7, #8
800bb14: 46bd mov sp, r7
800bb16: bd80 pop {r7, pc}
0800bb18 <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
800bb18: b580 push {r7, lr}
800bb1a: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
800bb1c: 2200 movs r2, #0
800bb1e: 4912 ldr r1, [pc, #72] @ (800bb68 <MX_USB_DEVICE_Init+0x50>)
800bb20: 4812 ldr r0, [pc, #72] @ (800bb6c <MX_USB_DEVICE_Init+0x54>)
800bb22: f7fe ff62 bl 800a9ea <USBD_Init>
800bb26: 4603 mov r3, r0
800bb28: 2b00 cmp r3, #0
800bb2a: d001 beq.n 800bb30 <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
800bb2c: f7f6 fe26 bl 800277c <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
800bb30: 490f ldr r1, [pc, #60] @ (800bb70 <MX_USB_DEVICE_Init+0x58>)
800bb32: 480e ldr r0, [pc, #56] @ (800bb6c <MX_USB_DEVICE_Init+0x54>)
800bb34: f7fe ff84 bl 800aa40 <USBD_RegisterClass>
800bb38: 4603 mov r3, r0
800bb3a: 2b00 cmp r3, #0
800bb3c: d001 beq.n 800bb42 <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
800bb3e: f7f6 fe1d bl 800277c <Error_Handler>
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
800bb42: 490c ldr r1, [pc, #48] @ (800bb74 <MX_USB_DEVICE_Init+0x5c>)
800bb44: 4809 ldr r0, [pc, #36] @ (800bb6c <MX_USB_DEVICE_Init+0x54>)
800bb46: f7fe feb5 bl 800a8b4 <USBD_CDC_RegisterInterface>
800bb4a: 4603 mov r3, r0
800bb4c: 2b00 cmp r3, #0
800bb4e: d001 beq.n 800bb54 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
800bb50: f7f6 fe14 bl 800277c <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
800bb54: 4805 ldr r0, [pc, #20] @ (800bb6c <MX_USB_DEVICE_Init+0x54>)
800bb56: f7fe ff8c bl 800aa72 <USBD_Start>
800bb5a: 4603 mov r3, r0
800bb5c: 2b00 cmp r3, #0
800bb5e: d001 beq.n 800bb64 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
800bb60: f7f6 fe0c bl 800277c <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
800bb64: bf00 nop
800bb66: bd80 pop {r7, pc}
800bb68: 20000134 .word 0x20000134
800bb6c: 2000045c .word 0x2000045c
800bb70: 20000020 .word 0x20000020
800bb74: 20000124 .word 0x20000124
0800bb78 <fifo_push>:
/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
#define RX_FIFO_SZ 256
static uint8_t rx_fifo[RX_FIFO_SZ];
static volatile uint16_t rx_head = 0, rx_tail = 0;
static void fifo_push(const uint8_t* data, uint32_t len) {
800bb78: b480 push {r7}
800bb7a: b085 sub sp, #20
800bb7c: af00 add r7, sp, #0
800bb7e: 6078 str r0, [r7, #4]
800bb80: 6039 str r1, [r7, #0]
while (len--) {
800bb82: e01e b.n 800bbc2 <fifo_push+0x4a>
uint16_t next = (rx_head + 1u) & (RX_FIFO_SZ - 1u);
800bb84: 4b14 ldr r3, [pc, #80] @ (800bbd8 <fifo_push+0x60>)
800bb86: 881b ldrh r3, [r3, #0]
800bb88: b29b uxth r3, r3
800bb8a: 3301 adds r3, #1
800bb8c: b29b uxth r3, r3
800bb8e: b2db uxtb r3, r3
800bb90: 81fb strh r3, [r7, #14]
if (next == (rx_tail & (RX_FIFO_SZ - 1u))) {
800bb92: 89fa ldrh r2, [r7, #14]
800bb94: 4b11 ldr r3, [pc, #68] @ (800bbdc <fifo_push+0x64>)
800bb96: 881b ldrh r3, [r3, #0]
800bb98: b29b uxth r3, r3
800bb9a: b2db uxtb r3, r3
800bb9c: 429a cmp r2, r3
800bb9e: d103 bne.n 800bba8 <fifo_push+0x30>
/* overflow — drop byte (or set a flag) */
data++;
800bba0: 687b ldr r3, [r7, #4]
800bba2: 3301 adds r3, #1
800bba4: 607b str r3, [r7, #4]
continue;
800bba6: e00c b.n 800bbc2 <fifo_push+0x4a>
}
rx_fifo[rx_head & (RX_FIFO_SZ - 1u)] = *data++;
800bba8: 687b ldr r3, [r7, #4]
800bbaa: 1c5a adds r2, r3, #1
800bbac: 607a str r2, [r7, #4]
800bbae: 4a0a ldr r2, [pc, #40] @ (800bbd8 <fifo_push+0x60>)
800bbb0: 8812 ldrh r2, [r2, #0]
800bbb2: b292 uxth r2, r2
800bbb4: b2d2 uxtb r2, r2
800bbb6: 7819 ldrb r1, [r3, #0]
800bbb8: 4b09 ldr r3, [pc, #36] @ (800bbe0 <fifo_push+0x68>)
800bbba: 5499 strb r1, [r3, r2]
rx_head = next;
800bbbc: 4a06 ldr r2, [pc, #24] @ (800bbd8 <fifo_push+0x60>)
800bbbe: 89fb ldrh r3, [r7, #14]
800bbc0: 8013 strh r3, [r2, #0]
while (len--) {
800bbc2: 683b ldr r3, [r7, #0]
800bbc4: 1e5a subs r2, r3, #1
800bbc6: 603a str r2, [r7, #0]
800bbc8: 2b00 cmp r3, #0
800bbca: d1db bne.n 800bb84 <fifo_push+0xc>
}
}
800bbcc: bf00 nop
800bbce: bf00 nop
800bbd0: 3714 adds r7, #20
800bbd2: 46bd mov sp, r7
800bbd4: bc80 pop {r7}
800bbd6: 4770 bx lr
800bbd8: 20001020 .word 0x20001020
800bbdc: 20001022 .word 0x20001022
800bbe0: 20000f20 .word 0x20000f20
0800bbe4 <CDC_Available>:
uint32_t CDC_Available(void) {
800bbe4: b480 push {r7}
800bbe6: af00 add r7, sp, #0
return (uint16_t)((rx_head - rx_tail) & (RX_FIFO_SZ - 1u));
800bbe8: 4b06 ldr r3, [pc, #24] @ (800bc04 <CDC_Available+0x20>)
800bbea: 881b ldrh r3, [r3, #0]
800bbec: b29a uxth r2, r3
800bbee: 4b06 ldr r3, [pc, #24] @ (800bc08 <CDC_Available+0x24>)
800bbf0: 881b ldrh r3, [r3, #0]
800bbf2: b29b uxth r3, r3
800bbf4: 1ad3 subs r3, r2, r3
800bbf6: b29b uxth r3, r3
800bbf8: b2db uxtb r3, r3
}
800bbfa: 4618 mov r0, r3
800bbfc: 46bd mov sp, r7
800bbfe: bc80 pop {r7}
800bc00: 4770 bx lr
800bc02: bf00 nop
800bc04: 20001020 .word 0x20001020
800bc08: 20001022 .word 0x20001022
0800bc0c <CDC_ReadByte>:
int CDC_ReadByte(void) {
800bc0c: b480 push {r7}
800bc0e: b083 sub sp, #12
800bc10: af00 add r7, sp, #0
if (rx_tail == rx_head) return -1;
800bc12: 4b10 ldr r3, [pc, #64] @ (800bc54 <CDC_ReadByte+0x48>)
800bc14: 881b ldrh r3, [r3, #0]
800bc16: b29a uxth r2, r3
800bc18: 4b0f ldr r3, [pc, #60] @ (800bc58 <CDC_ReadByte+0x4c>)
800bc1a: 881b ldrh r3, [r3, #0]
800bc1c: b29b uxth r3, r3
800bc1e: 429a cmp r2, r3
800bc20: d102 bne.n 800bc28 <CDC_ReadByte+0x1c>
800bc22: f04f 33ff mov.w r3, #4294967295
800bc26: e010 b.n 800bc4a <CDC_ReadByte+0x3e>
int b = rx_fifo[rx_tail & (RX_FIFO_SZ - 1u)];
800bc28: 4b0a ldr r3, [pc, #40] @ (800bc54 <CDC_ReadByte+0x48>)
800bc2a: 881b ldrh r3, [r3, #0]
800bc2c: b29b uxth r3, r3
800bc2e: b2db uxtb r3, r3
800bc30: 4a0a ldr r2, [pc, #40] @ (800bc5c <CDC_ReadByte+0x50>)
800bc32: 5cd3 ldrb r3, [r2, r3]
800bc34: 607b str r3, [r7, #4]
rx_tail = (rx_tail + 1u) & (RX_FIFO_SZ - 1u);
800bc36: 4b07 ldr r3, [pc, #28] @ (800bc54 <CDC_ReadByte+0x48>)
800bc38: 881b ldrh r3, [r3, #0]
800bc3a: b29b uxth r3, r3
800bc3c: 3301 adds r3, #1
800bc3e: b29b uxth r3, r3
800bc40: b2db uxtb r3, r3
800bc42: b29a uxth r2, r3
800bc44: 4b03 ldr r3, [pc, #12] @ (800bc54 <CDC_ReadByte+0x48>)
800bc46: 801a strh r2, [r3, #0]
return b;
800bc48: 687b ldr r3, [r7, #4]
}
800bc4a: 4618 mov r0, r3
800bc4c: 370c adds r7, #12
800bc4e: 46bd mov sp, r7
800bc50: bc80 pop {r7}
800bc52: 4770 bx lr
800bc54: 20001022 .word 0x20001022
800bc58: 20001020 .word 0x20001020
800bc5c: 20000f20 .word 0x20000f20
0800bc60 <CDC_Init_FS>:
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
800bc60: b580 push {r7, lr}
800bc62: af00 add r7, sp, #0
/* USER CODE BEGIN 3 */
/* Set Application Buffers */
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
800bc64: 2200 movs r2, #0
800bc66: 4905 ldr r1, [pc, #20] @ (800bc7c <CDC_Init_FS+0x1c>)
800bc68: 4805 ldr r0, [pc, #20] @ (800bc80 <CDC_Init_FS+0x20>)
800bc6a: f7fe fe39 bl 800a8e0 <USBD_CDC_SetTxBuffer>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
800bc6e: 4905 ldr r1, [pc, #20] @ (800bc84 <CDC_Init_FS+0x24>)
800bc70: 4803 ldr r0, [pc, #12] @ (800bc80 <CDC_Init_FS+0x20>)
800bc72: f7fe fe4e bl 800a912 <USBD_CDC_SetRxBuffer>
return (USBD_OK);
800bc76: 2300 movs r3, #0
/* USER CODE END 3 */
}
800bc78: 4618 mov r0, r3
800bc7a: bd80 pop {r7, pc}
800bc7c: 20000b20 .word 0x20000b20
800bc80: 2000045c .word 0x2000045c
800bc84: 20000720 .word 0x20000720
0800bc88 <CDC_DeInit_FS>:
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
800bc88: b480 push {r7}
800bc8a: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
800bc8c: 2300 movs r3, #0
/* USER CODE END 4 */
}
800bc8e: 4618 mov r0, r3
800bc90: 46bd mov sp, r7
800bc92: bc80 pop {r7}
800bc94: 4770 bx lr
...
0800bc98 <CDC_Control_FS>:
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
800bc98: b480 push {r7}
800bc9a: b083 sub sp, #12
800bc9c: af00 add r7, sp, #0
800bc9e: 4603 mov r3, r0
800bca0: 6039 str r1, [r7, #0]
800bca2: 71fb strb r3, [r7, #7]
800bca4: 4613 mov r3, r2
800bca6: 80bb strh r3, [r7, #4]
/* USER CODE BEGIN 5 */
switch(cmd)
800bca8: 79fb ldrb r3, [r7, #7]
800bcaa: 2b23 cmp r3, #35 @ 0x23
800bcac: d84a bhi.n 800bd44 <CDC_Control_FS+0xac>
800bcae: a201 add r2, pc, #4 @ (adr r2, 800bcb4 <CDC_Control_FS+0x1c>)
800bcb0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800bcb4: 0800bd45 .word 0x0800bd45
800bcb8: 0800bd45 .word 0x0800bd45
800bcbc: 0800bd45 .word 0x0800bd45
800bcc0: 0800bd45 .word 0x0800bd45
800bcc4: 0800bd45 .word 0x0800bd45
800bcc8: 0800bd45 .word 0x0800bd45
800bccc: 0800bd45 .word 0x0800bd45
800bcd0: 0800bd45 .word 0x0800bd45
800bcd4: 0800bd45 .word 0x0800bd45
800bcd8: 0800bd45 .word 0x0800bd45
800bcdc: 0800bd45 .word 0x0800bd45
800bce0: 0800bd45 .word 0x0800bd45
800bce4: 0800bd45 .word 0x0800bd45
800bce8: 0800bd45 .word 0x0800bd45
800bcec: 0800bd45 .word 0x0800bd45
800bcf0: 0800bd45 .word 0x0800bd45
800bcf4: 0800bd45 .word 0x0800bd45
800bcf8: 0800bd45 .word 0x0800bd45
800bcfc: 0800bd45 .word 0x0800bd45
800bd00: 0800bd45 .word 0x0800bd45
800bd04: 0800bd45 .word 0x0800bd45
800bd08: 0800bd45 .word 0x0800bd45
800bd0c: 0800bd45 .word 0x0800bd45
800bd10: 0800bd45 .word 0x0800bd45
800bd14: 0800bd45 .word 0x0800bd45
800bd18: 0800bd45 .word 0x0800bd45
800bd1c: 0800bd45 .word 0x0800bd45
800bd20: 0800bd45 .word 0x0800bd45
800bd24: 0800bd45 .word 0x0800bd45
800bd28: 0800bd45 .word 0x0800bd45
800bd2c: 0800bd45 .word 0x0800bd45
800bd30: 0800bd45 .word 0x0800bd45
800bd34: 0800bd45 .word 0x0800bd45
800bd38: 0800bd45 .word 0x0800bd45
800bd3c: 0800bd45 .word 0x0800bd45
800bd40: 0800bd45 .word 0x0800bd45
case CDC_SEND_BREAK:
break;
default:
break;
800bd44: bf00 nop
}
return (USBD_OK);
800bd46: 2300 movs r3, #0
/* USER CODE END 5 */
}
800bd48: 4618 mov r0, r3
800bd4a: 370c adds r7, #12
800bd4c: 46bd mov sp, r7
800bd4e: bc80 pop {r7}
800bd50: 4770 bx lr
800bd52: bf00 nop
0800bd54 <CDC_Receive_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
800bd54: b580 push {r7, lr}
800bd56: b082 sub sp, #8
800bd58: af00 add r7, sp, #0
800bd5a: 6078 str r0, [r7, #4]
800bd5c: 6039 str r1, [r7, #0]
/* USER CODE BEGIN 6 */
if (*Len) fifo_push(Buf, *Len);
800bd5e: 683b ldr r3, [r7, #0]
800bd60: 681b ldr r3, [r3, #0]
800bd62: 2b00 cmp r3, #0
800bd64: d005 beq.n 800bd72 <CDC_Receive_FS+0x1e>
800bd66: 683b ldr r3, [r7, #0]
800bd68: 681b ldr r3, [r3, #0]
800bd6a: 4619 mov r1, r3
800bd6c: 6878 ldr r0, [r7, #4]
800bd6e: f7ff ff03 bl 800bb78 <fifo_push>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
800bd72: 6879 ldr r1, [r7, #4]
800bd74: 4805 ldr r0, [pc, #20] @ (800bd8c <CDC_Receive_FS+0x38>)
800bd76: f7fe fdcc bl 800a912 <USBD_CDC_SetRxBuffer>
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
800bd7a: 4804 ldr r0, [pc, #16] @ (800bd8c <CDC_Receive_FS+0x38>)
800bd7c: f7fe fe0b bl 800a996 <USBD_CDC_ReceivePacket>
return (USBD_OK);
800bd80: 2300 movs r3, #0
/* USER CODE END 6 */
}
800bd82: 4618 mov r0, r3
800bd84: 3708 adds r7, #8
800bd86: 46bd mov sp, r7
800bd88: bd80 pop {r7, pc}
800bd8a: bf00 nop
800bd8c: 2000045c .word 0x2000045c
0800bd90 <CDC_Transmit_FS>:
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
800bd90: b580 push {r7, lr}
800bd92: b084 sub sp, #16
800bd94: af00 add r7, sp, #0
800bd96: 6078 str r0, [r7, #4]
800bd98: 460b mov r3, r1
800bd9a: 807b strh r3, [r7, #2]
uint8_t result = USBD_OK;
800bd9c: 2300 movs r3, #0
800bd9e: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
800bda0: 4b0d ldr r3, [pc, #52] @ (800bdd8 <CDC_Transmit_FS+0x48>)
800bda2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800bda6: 60bb str r3, [r7, #8]
if (hcdc->TxState != 0){
800bda8: 68bb ldr r3, [r7, #8]
800bdaa: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800bdae: 2b00 cmp r3, #0
800bdb0: d001 beq.n 800bdb6 <CDC_Transmit_FS+0x26>
return USBD_BUSY;
800bdb2: 2301 movs r3, #1
800bdb4: e00b b.n 800bdce <CDC_Transmit_FS+0x3e>
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
800bdb6: 887b ldrh r3, [r7, #2]
800bdb8: 461a mov r2, r3
800bdba: 6879 ldr r1, [r7, #4]
800bdbc: 4806 ldr r0, [pc, #24] @ (800bdd8 <CDC_Transmit_FS+0x48>)
800bdbe: f7fe fd8f bl 800a8e0 <USBD_CDC_SetTxBuffer>
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
800bdc2: 4805 ldr r0, [pc, #20] @ (800bdd8 <CDC_Transmit_FS+0x48>)
800bdc4: f7fe fdb8 bl 800a938 <USBD_CDC_TransmitPacket>
800bdc8: 4603 mov r3, r0
800bdca: 73fb strb r3, [r7, #15]
/* USER CODE END 7 */
return result;
800bdcc: 7bfb ldrb r3, [r7, #15]
}
800bdce: 4618 mov r0, r3
800bdd0: 3710 adds r7, #16
800bdd2: 46bd mov sp, r7
800bdd4: bd80 pop {r7, pc}
800bdd6: bf00 nop
800bdd8: 2000045c .word 0x2000045c
0800bddc <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800bddc: b480 push {r7}
800bdde: b083 sub sp, #12
800bde0: af00 add r7, sp, #0
800bde2: 4603 mov r3, r0
800bde4: 6039 str r1, [r7, #0]
800bde6: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
800bde8: 683b ldr r3, [r7, #0]
800bdea: 2212 movs r2, #18
800bdec: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
800bdee: 4b03 ldr r3, [pc, #12] @ (800bdfc <USBD_FS_DeviceDescriptor+0x20>)
}
800bdf0: 4618 mov r0, r3
800bdf2: 370c adds r7, #12
800bdf4: 46bd mov sp, r7
800bdf6: bc80 pop {r7}
800bdf8: 4770 bx lr
800bdfa: bf00 nop
800bdfc: 20000150 .word 0x20000150
0800be00 <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800be00: b480 push {r7}
800be02: b083 sub sp, #12
800be04: af00 add r7, sp, #0
800be06: 4603 mov r3, r0
800be08: 6039 str r1, [r7, #0]
800be0a: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
800be0c: 683b ldr r3, [r7, #0]
800be0e: 2204 movs r2, #4
800be10: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
800be12: 4b03 ldr r3, [pc, #12] @ (800be20 <USBD_FS_LangIDStrDescriptor+0x20>)
}
800be14: 4618 mov r0, r3
800be16: 370c adds r7, #12
800be18: 46bd mov sp, r7
800be1a: bc80 pop {r7}
800be1c: 4770 bx lr
800be1e: bf00 nop
800be20: 20000164 .word 0x20000164
0800be24 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800be24: b580 push {r7, lr}
800be26: b082 sub sp, #8
800be28: af00 add r7, sp, #0
800be2a: 4603 mov r3, r0
800be2c: 6039 str r1, [r7, #0]
800be2e: 71fb strb r3, [r7, #7]
if(speed == 0)
800be30: 79fb ldrb r3, [r7, #7]
800be32: 2b00 cmp r3, #0
800be34: d105 bne.n 800be42 <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800be36: 683a ldr r2, [r7, #0]
800be38: 4907 ldr r1, [pc, #28] @ (800be58 <USBD_FS_ProductStrDescriptor+0x34>)
800be3a: 4808 ldr r0, [pc, #32] @ (800be5c <USBD_FS_ProductStrDescriptor+0x38>)
800be3c: f7ff fd8f bl 800b95e <USBD_GetString>
800be40: e004 b.n 800be4c <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
800be42: 683a ldr r2, [r7, #0]
800be44: 4904 ldr r1, [pc, #16] @ (800be58 <USBD_FS_ProductStrDescriptor+0x34>)
800be46: 4805 ldr r0, [pc, #20] @ (800be5c <USBD_FS_ProductStrDescriptor+0x38>)
800be48: f7ff fd89 bl 800b95e <USBD_GetString>
}
return USBD_StrDesc;
800be4c: 4b02 ldr r3, [pc, #8] @ (800be58 <USBD_FS_ProductStrDescriptor+0x34>)
}
800be4e: 4618 mov r0, r3
800be50: 3708 adds r7, #8
800be52: 46bd mov sp, r7
800be54: bd80 pop {r7, pc}
800be56: bf00 nop
800be58: 20001024 .word 0x20001024
800be5c: 0800d0c8 .word 0x0800d0c8
0800be60 <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800be60: b580 push {r7, lr}
800be62: b082 sub sp, #8
800be64: af00 add r7, sp, #0
800be66: 4603 mov r3, r0
800be68: 6039 str r1, [r7, #0]
800be6a: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
800be6c: 683a ldr r2, [r7, #0]
800be6e: 4904 ldr r1, [pc, #16] @ (800be80 <USBD_FS_ManufacturerStrDescriptor+0x20>)
800be70: 4804 ldr r0, [pc, #16] @ (800be84 <USBD_FS_ManufacturerStrDescriptor+0x24>)
800be72: f7ff fd74 bl 800b95e <USBD_GetString>
return USBD_StrDesc;
800be76: 4b02 ldr r3, [pc, #8] @ (800be80 <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
800be78: 4618 mov r0, r3
800be7a: 3708 adds r7, #8
800be7c: 46bd mov sp, r7
800be7e: bd80 pop {r7, pc}
800be80: 20001024 .word 0x20001024
800be84: 0800d0e0 .word 0x0800d0e0
0800be88 <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800be88: b580 push {r7, lr}
800be8a: b082 sub sp, #8
800be8c: af00 add r7, sp, #0
800be8e: 4603 mov r3, r0
800be90: 6039 str r1, [r7, #0]
800be92: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
800be94: 683b ldr r3, [r7, #0]
800be96: 221a movs r2, #26
800be98: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
800be9a: f000 f843 bl 800bf24 <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
800be9e: 4b02 ldr r3, [pc, #8] @ (800bea8 <USBD_FS_SerialStrDescriptor+0x20>)
}
800bea0: 4618 mov r0, r3
800bea2: 3708 adds r7, #8
800bea4: 46bd mov sp, r7
800bea6: bd80 pop {r7, pc}
800bea8: 20000168 .word 0x20000168
0800beac <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800beac: b580 push {r7, lr}
800beae: b082 sub sp, #8
800beb0: af00 add r7, sp, #0
800beb2: 4603 mov r3, r0
800beb4: 6039 str r1, [r7, #0]
800beb6: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
800beb8: 79fb ldrb r3, [r7, #7]
800beba: 2b00 cmp r3, #0
800bebc: d105 bne.n 800beca <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800bebe: 683a ldr r2, [r7, #0]
800bec0: 4907 ldr r1, [pc, #28] @ (800bee0 <USBD_FS_ConfigStrDescriptor+0x34>)
800bec2: 4808 ldr r0, [pc, #32] @ (800bee4 <USBD_FS_ConfigStrDescriptor+0x38>)
800bec4: f7ff fd4b bl 800b95e <USBD_GetString>
800bec8: e004 b.n 800bed4 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
800beca: 683a ldr r2, [r7, #0]
800becc: 4904 ldr r1, [pc, #16] @ (800bee0 <USBD_FS_ConfigStrDescriptor+0x34>)
800bece: 4805 ldr r0, [pc, #20] @ (800bee4 <USBD_FS_ConfigStrDescriptor+0x38>)
800bed0: f7ff fd45 bl 800b95e <USBD_GetString>
}
return USBD_StrDesc;
800bed4: 4b02 ldr r3, [pc, #8] @ (800bee0 <USBD_FS_ConfigStrDescriptor+0x34>)
}
800bed6: 4618 mov r0, r3
800bed8: 3708 adds r7, #8
800beda: 46bd mov sp, r7
800bedc: bd80 pop {r7, pc}
800bede: bf00 nop
800bee0: 20001024 .word 0x20001024
800bee4: 0800d0f4 .word 0x0800d0f4
0800bee8 <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
800bee8: b580 push {r7, lr}
800beea: b082 sub sp, #8
800beec: af00 add r7, sp, #0
800beee: 4603 mov r3, r0
800bef0: 6039 str r1, [r7, #0]
800bef2: 71fb strb r3, [r7, #7]
if(speed == 0)
800bef4: 79fb ldrb r3, [r7, #7]
800bef6: 2b00 cmp r3, #0
800bef8: d105 bne.n 800bf06 <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800befa: 683a ldr r2, [r7, #0]
800befc: 4907 ldr r1, [pc, #28] @ (800bf1c <USBD_FS_InterfaceStrDescriptor+0x34>)
800befe: 4808 ldr r0, [pc, #32] @ (800bf20 <USBD_FS_InterfaceStrDescriptor+0x38>)
800bf00: f7ff fd2d bl 800b95e <USBD_GetString>
800bf04: e004 b.n 800bf10 <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
800bf06: 683a ldr r2, [r7, #0]
800bf08: 4904 ldr r1, [pc, #16] @ (800bf1c <USBD_FS_InterfaceStrDescriptor+0x34>)
800bf0a: 4805 ldr r0, [pc, #20] @ (800bf20 <USBD_FS_InterfaceStrDescriptor+0x38>)
800bf0c: f7ff fd27 bl 800b95e <USBD_GetString>
}
return USBD_StrDesc;
800bf10: 4b02 ldr r3, [pc, #8] @ (800bf1c <USBD_FS_InterfaceStrDescriptor+0x34>)
}
800bf12: 4618 mov r0, r3
800bf14: 3708 adds r7, #8
800bf16: 46bd mov sp, r7
800bf18: bd80 pop {r7, pc}
800bf1a: bf00 nop
800bf1c: 20001024 .word 0x20001024
800bf20: 0800d100 .word 0x0800d100
0800bf24 <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
800bf24: b580 push {r7, lr}
800bf26: b084 sub sp, #16
800bf28: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
800bf2a: 4b0f ldr r3, [pc, #60] @ (800bf68 <Get_SerialNum+0x44>)
800bf2c: 681b ldr r3, [r3, #0]
800bf2e: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
800bf30: 4b0e ldr r3, [pc, #56] @ (800bf6c <Get_SerialNum+0x48>)
800bf32: 681b ldr r3, [r3, #0]
800bf34: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
800bf36: 4b0e ldr r3, [pc, #56] @ (800bf70 <Get_SerialNum+0x4c>)
800bf38: 681b ldr r3, [r3, #0]
800bf3a: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
800bf3c: 68fa ldr r2, [r7, #12]
800bf3e: 687b ldr r3, [r7, #4]
800bf40: 4413 add r3, r2
800bf42: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
800bf44: 68fb ldr r3, [r7, #12]
800bf46: 2b00 cmp r3, #0
800bf48: d009 beq.n 800bf5e <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
800bf4a: 2208 movs r2, #8
800bf4c: 4909 ldr r1, [pc, #36] @ (800bf74 <Get_SerialNum+0x50>)
800bf4e: 68f8 ldr r0, [r7, #12]
800bf50: f000 f814 bl 800bf7c <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
800bf54: 2204 movs r2, #4
800bf56: 4908 ldr r1, [pc, #32] @ (800bf78 <Get_SerialNum+0x54>)
800bf58: 68b8 ldr r0, [r7, #8]
800bf5a: f000 f80f bl 800bf7c <IntToUnicode>
}
}
800bf5e: bf00 nop
800bf60: 3710 adds r7, #16
800bf62: 46bd mov sp, r7
800bf64: bd80 pop {r7, pc}
800bf66: bf00 nop
800bf68: 1ffff7e8 .word 0x1ffff7e8
800bf6c: 1ffff7ec .word 0x1ffff7ec
800bf70: 1ffff7f0 .word 0x1ffff7f0
800bf74: 2000016a .word 0x2000016a
800bf78: 2000017a .word 0x2000017a
0800bf7c <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
800bf7c: b480 push {r7}
800bf7e: b087 sub sp, #28
800bf80: af00 add r7, sp, #0
800bf82: 60f8 str r0, [r7, #12]
800bf84: 60b9 str r1, [r7, #8]
800bf86: 4613 mov r3, r2
800bf88: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
800bf8a: 2300 movs r3, #0
800bf8c: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
800bf8e: 2300 movs r3, #0
800bf90: 75fb strb r3, [r7, #23]
800bf92: e027 b.n 800bfe4 <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
800bf94: 68fb ldr r3, [r7, #12]
800bf96: 0f1b lsrs r3, r3, #28
800bf98: 2b09 cmp r3, #9
800bf9a: d80b bhi.n 800bfb4 <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
800bf9c: 68fb ldr r3, [r7, #12]
800bf9e: 0f1b lsrs r3, r3, #28
800bfa0: b2da uxtb r2, r3
800bfa2: 7dfb ldrb r3, [r7, #23]
800bfa4: 005b lsls r3, r3, #1
800bfa6: 4619 mov r1, r3
800bfa8: 68bb ldr r3, [r7, #8]
800bfaa: 440b add r3, r1
800bfac: 3230 adds r2, #48 @ 0x30
800bfae: b2d2 uxtb r2, r2
800bfb0: 701a strb r2, [r3, #0]
800bfb2: e00a b.n 800bfca <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
800bfb4: 68fb ldr r3, [r7, #12]
800bfb6: 0f1b lsrs r3, r3, #28
800bfb8: b2da uxtb r2, r3
800bfba: 7dfb ldrb r3, [r7, #23]
800bfbc: 005b lsls r3, r3, #1
800bfbe: 4619 mov r1, r3
800bfc0: 68bb ldr r3, [r7, #8]
800bfc2: 440b add r3, r1
800bfc4: 3237 adds r2, #55 @ 0x37
800bfc6: b2d2 uxtb r2, r2
800bfc8: 701a strb r2, [r3, #0]
}
value = value << 4;
800bfca: 68fb ldr r3, [r7, #12]
800bfcc: 011b lsls r3, r3, #4
800bfce: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
800bfd0: 7dfb ldrb r3, [r7, #23]
800bfd2: 005b lsls r3, r3, #1
800bfd4: 3301 adds r3, #1
800bfd6: 68ba ldr r2, [r7, #8]
800bfd8: 4413 add r3, r2
800bfda: 2200 movs r2, #0
800bfdc: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
800bfde: 7dfb ldrb r3, [r7, #23]
800bfe0: 3301 adds r3, #1
800bfe2: 75fb strb r3, [r7, #23]
800bfe4: 7dfa ldrb r2, [r7, #23]
800bfe6: 79fb ldrb r3, [r7, #7]
800bfe8: 429a cmp r2, r3
800bfea: d3d3 bcc.n 800bf94 <IntToUnicode+0x18>
}
}
800bfec: bf00 nop
800bfee: bf00 nop
800bff0: 371c adds r7, #28
800bff2: 46bd mov sp, r7
800bff4: bc80 pop {r7}
800bff6: 4770 bx lr
0800bff8 <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
800bff8: b580 push {r7, lr}
800bffa: b084 sub sp, #16
800bffc: af00 add r7, sp, #0
800bffe: 6078 str r0, [r7, #4]
if(pcdHandle->Instance==USB)
800c000: 687b ldr r3, [r7, #4]
800c002: 681b ldr r3, [r3, #0]
800c004: 4a0d ldr r2, [pc, #52] @ (800c03c <HAL_PCD_MspInit+0x44>)
800c006: 4293 cmp r3, r2
800c008: d113 bne.n 800c032 <HAL_PCD_MspInit+0x3a>
{
/* USER CODE BEGIN USB_MspInit 0 */
/* USER CODE END USB_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
800c00a: 4b0d ldr r3, [pc, #52] @ (800c040 <HAL_PCD_MspInit+0x48>)
800c00c: 69db ldr r3, [r3, #28]
800c00e: 4a0c ldr r2, [pc, #48] @ (800c040 <HAL_PCD_MspInit+0x48>)
800c010: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
800c014: 61d3 str r3, [r2, #28]
800c016: 4b0a ldr r3, [pc, #40] @ (800c040 <HAL_PCD_MspInit+0x48>)
800c018: 69db ldr r3, [r3, #28]
800c01a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800c01e: 60fb str r3, [r7, #12]
800c020: 68fb ldr r3, [r7, #12]
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
800c022: 2200 movs r2, #0
800c024: 2100 movs r1, #0
800c026: 2014 movs r0, #20
800c028: f7f7 ff09 bl 8003e3e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
800c02c: 2014 movs r0, #20
800c02e: f7f7 ff22 bl 8003e76 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
800c032: bf00 nop
800c034: 3710 adds r7, #16
800c036: 46bd mov sp, r7
800c038: bd80 pop {r7, pc}
800c03a: bf00 nop
800c03c: 40005c00 .word 0x40005c00
800c040: 40021000 .word 0x40021000
0800c044 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c044: b580 push {r7, lr}
800c046: b082 sub sp, #8
800c048: af00 add r7, sp, #0
800c04a: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
800c04c: 687b ldr r3, [r7, #4]
800c04e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800c052: 687b ldr r3, [r7, #4]
800c054: f503 7326 add.w r3, r3, #664 @ 0x298
800c058: 4619 mov r1, r3
800c05a: 4610 mov r0, r2
800c05c: f7fe fd51 bl 800ab02 <USBD_LL_SetupStage>
}
800c060: bf00 nop
800c062: 3708 adds r7, #8
800c064: 46bd mov sp, r7
800c066: bd80 pop {r7, pc}
0800c068 <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c068: b580 push {r7, lr}
800c06a: b082 sub sp, #8
800c06c: af00 add r7, sp, #0
800c06e: 6078 str r0, [r7, #4]
800c070: 460b mov r3, r1
800c072: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
800c074: 687b ldr r3, [r7, #4]
800c076: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
800c07a: 78fa ldrb r2, [r7, #3]
800c07c: 6879 ldr r1, [r7, #4]
800c07e: 4613 mov r3, r2
800c080: 009b lsls r3, r3, #2
800c082: 4413 add r3, r2
800c084: 00db lsls r3, r3, #3
800c086: 440b add r3, r1
800c088: f503 73b2 add.w r3, r3, #356 @ 0x164
800c08c: 681a ldr r2, [r3, #0]
800c08e: 78fb ldrb r3, [r7, #3]
800c090: 4619 mov r1, r3
800c092: f7fe fd83 bl 800ab9c <USBD_LL_DataOutStage>
}
800c096: bf00 nop
800c098: 3708 adds r7, #8
800c09a: 46bd mov sp, r7
800c09c: bd80 pop {r7, pc}
0800c09e <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c09e: b580 push {r7, lr}
800c0a0: b082 sub sp, #8
800c0a2: af00 add r7, sp, #0
800c0a4: 6078 str r0, [r7, #4]
800c0a6: 460b mov r3, r1
800c0a8: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
800c0aa: 687b ldr r3, [r7, #4]
800c0ac: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
800c0b0: 78fa ldrb r2, [r7, #3]
800c0b2: 6879 ldr r1, [r7, #4]
800c0b4: 4613 mov r3, r2
800c0b6: 009b lsls r3, r3, #2
800c0b8: 4413 add r3, r2
800c0ba: 00db lsls r3, r3, #3
800c0bc: 440b add r3, r1
800c0be: 3324 adds r3, #36 @ 0x24
800c0c0: 681a ldr r2, [r3, #0]
800c0c2: 78fb ldrb r3, [r7, #3]
800c0c4: 4619 mov r1, r3
800c0c6: f7fe fdda bl 800ac7e <USBD_LL_DataInStage>
}
800c0ca: bf00 nop
800c0cc: 3708 adds r7, #8
800c0ce: 46bd mov sp, r7
800c0d0: bd80 pop {r7, pc}
0800c0d2 <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c0d2: b580 push {r7, lr}
800c0d4: b082 sub sp, #8
800c0d6: af00 add r7, sp, #0
800c0d8: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
800c0da: 687b ldr r3, [r7, #4]
800c0dc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800c0e0: 4618 mov r0, r3
800c0e2: f7fe feea bl 800aeba <USBD_LL_SOF>
}
800c0e6: bf00 nop
800c0e8: 3708 adds r7, #8
800c0ea: 46bd mov sp, r7
800c0ec: bd80 pop {r7, pc}
0800c0ee <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c0ee: b580 push {r7, lr}
800c0f0: b084 sub sp, #16
800c0f2: af00 add r7, sp, #0
800c0f4: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
800c0f6: 2301 movs r3, #1
800c0f8: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
800c0fa: 687b ldr r3, [r7, #4]
800c0fc: 799b ldrb r3, [r3, #6]
800c0fe: 2b02 cmp r3, #2
800c100: d001 beq.n 800c106 <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
800c102: f7f6 fb3b bl 800277c <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
800c106: 687b ldr r3, [r7, #4]
800c108: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800c10c: 7bfa ldrb r2, [r7, #15]
800c10e: 4611 mov r1, r2
800c110: 4618 mov r0, r3
800c112: f7fe fe9a bl 800ae4a <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
800c116: 687b ldr r3, [r7, #4]
800c118: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800c11c: 4618 mov r0, r3
800c11e: f7fe fe53 bl 800adc8 <USBD_LL_Reset>
}
800c122: bf00 nop
800c124: 3710 adds r7, #16
800c126: 46bd mov sp, r7
800c128: bd80 pop {r7, pc}
...
0800c12c <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c12c: b580 push {r7, lr}
800c12e: b082 sub sp, #8
800c130: af00 add r7, sp, #0
800c132: 6078 str r0, [r7, #4]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
800c134: 687b ldr r3, [r7, #4]
800c136: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800c13a: 4618 mov r0, r3
800c13c: f7fe fe94 bl 800ae68 <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
800c140: 687b ldr r3, [r7, #4]
800c142: 7a9b ldrb r3, [r3, #10]
800c144: 2b00 cmp r3, #0
800c146: d005 beq.n 800c154 <HAL_PCD_SuspendCallback+0x28>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
800c148: 4b04 ldr r3, [pc, #16] @ (800c15c <HAL_PCD_SuspendCallback+0x30>)
800c14a: 691b ldr r3, [r3, #16]
800c14c: 4a03 ldr r2, [pc, #12] @ (800c15c <HAL_PCD_SuspendCallback+0x30>)
800c14e: f043 0306 orr.w r3, r3, #6
800c152: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
800c154: bf00 nop
800c156: 3708 adds r7, #8
800c158: 46bd mov sp, r7
800c15a: bd80 pop {r7, pc}
800c15c: e000ed00 .word 0xe000ed00
0800c160 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c160: b580 push {r7, lr}
800c162: b082 sub sp, #8
800c164: af00 add r7, sp, #0
800c166: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
800c168: 687b ldr r3, [r7, #4]
800c16a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800c16e: 4618 mov r0, r3
800c170: f7fe fe8e bl 800ae90 <USBD_LL_Resume>
}
800c174: bf00 nop
800c176: 3708 adds r7, #8
800c178: 46bd mov sp, r7
800c17a: bd80 pop {r7, pc}
0800c17c <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
800c17c: b580 push {r7, lr}
800c17e: b082 sub sp, #8
800c180: af00 add r7, sp, #0
800c182: 6078 str r0, [r7, #4]
/* Init USB Ip. */
/* Link the driver to the stack. */
hpcd_USB_FS.pData = pdev;
800c184: 4a28 ldr r2, [pc, #160] @ (800c228 <USBD_LL_Init+0xac>)
800c186: 687b ldr r3, [r7, #4]
800c188: f8c2 32d4 str.w r3, [r2, #724] @ 0x2d4
pdev->pData = &hpcd_USB_FS;
800c18c: 687b ldr r3, [r7, #4]
800c18e: 4a26 ldr r2, [pc, #152] @ (800c228 <USBD_LL_Init+0xac>)
800c190: f8c3 22c0 str.w r2, [r3, #704] @ 0x2c0
hpcd_USB_FS.Instance = USB;
800c194: 4b24 ldr r3, [pc, #144] @ (800c228 <USBD_LL_Init+0xac>)
800c196: 4a25 ldr r2, [pc, #148] @ (800c22c <USBD_LL_Init+0xb0>)
800c198: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
800c19a: 4b23 ldr r3, [pc, #140] @ (800c228 <USBD_LL_Init+0xac>)
800c19c: 2208 movs r2, #8
800c19e: 711a strb r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
800c1a0: 4b21 ldr r3, [pc, #132] @ (800c228 <USBD_LL_Init+0xac>)
800c1a2: 2202 movs r2, #2
800c1a4: 719a strb r2, [r3, #6]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
800c1a6: 4b20 ldr r3, [pc, #128] @ (800c228 <USBD_LL_Init+0xac>)
800c1a8: 2200 movs r2, #0
800c1aa: 729a strb r2, [r3, #10]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
800c1ac: 4b1e ldr r3, [pc, #120] @ (800c228 <USBD_LL_Init+0xac>)
800c1ae: 2200 movs r2, #0
800c1b0: 72da strb r2, [r3, #11]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
800c1b2: 4b1d ldr r3, [pc, #116] @ (800c228 <USBD_LL_Init+0xac>)
800c1b4: 2200 movs r2, #0
800c1b6: 731a strb r2, [r3, #12]
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
800c1b8: 481b ldr r0, [pc, #108] @ (800c228 <USBD_LL_Init+0xac>)
800c1ba: f7f8 fc37 bl 8004a2c <HAL_PCD_Init>
800c1be: 4603 mov r3, r0
800c1c0: 2b00 cmp r3, #0
800c1c2: d001 beq.n 800c1c8 <USBD_LL_Init+0x4c>
{
Error_Handler( );
800c1c4: f7f6 fada bl 800277c <Error_Handler>
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
800c1c8: 687b ldr r3, [r7, #4]
800c1ca: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c1ce: 2318 movs r3, #24
800c1d0: 2200 movs r2, #0
800c1d2: 2100 movs r1, #0
800c1d4: f7fa f948 bl 8006468 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
800c1d8: 687b ldr r3, [r7, #4]
800c1da: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c1de: 2358 movs r3, #88 @ 0x58
800c1e0: 2200 movs r2, #0
800c1e2: 2180 movs r1, #128 @ 0x80
800c1e4: f7fa f940 bl 8006468 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
800c1e8: 687b ldr r3, [r7, #4]
800c1ea: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c1ee: 23c0 movs r3, #192 @ 0xc0
800c1f0: 2200 movs r2, #0
800c1f2: 2181 movs r1, #129 @ 0x81
800c1f4: f7fa f938 bl 8006468 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
800c1f8: 687b ldr r3, [r7, #4]
800c1fa: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c1fe: f44f 7388 mov.w r3, #272 @ 0x110
800c202: 2200 movs r2, #0
800c204: 2101 movs r1, #1
800c206: f7fa f92f bl 8006468 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
800c20a: 687b ldr r3, [r7, #4]
800c20c: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c210: f44f 7380 mov.w r3, #256 @ 0x100
800c214: 2200 movs r2, #0
800c216: 2182 movs r1, #130 @ 0x82
800c218: f7fa f926 bl 8006468 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK;
800c21c: 2300 movs r3, #0
}
800c21e: 4618 mov r0, r3
800c220: 3708 adds r7, #8
800c222: 46bd mov sp, r7
800c224: bd80 pop {r7, pc}
800c226: bf00 nop
800c228: 20001224 .word 0x20001224
800c22c: 40005c00 .word 0x40005c00
0800c230 <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
800c230: b580 push {r7, lr}
800c232: b084 sub sp, #16
800c234: af00 add r7, sp, #0
800c236: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
800c238: 2300 movs r3, #0
800c23a: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800c23c: 2300 movs r3, #0
800c23e: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_Start(pdev->pData);
800c240: 687b ldr r3, [r7, #4]
800c242: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c246: 4618 mov r0, r3
800c248: f7f8 fce6 bl 8004c18 <HAL_PCD_Start>
800c24c: 4603 mov r3, r0
800c24e: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800c250: 7bfb ldrb r3, [r7, #15]
800c252: 4618 mov r0, r3
800c254: f000 f94e bl 800c4f4 <USBD_Get_USB_Status>
800c258: 4603 mov r3, r0
800c25a: 73bb strb r3, [r7, #14]
return usb_status;
800c25c: 7bbb ldrb r3, [r7, #14]
}
800c25e: 4618 mov r0, r3
800c260: 3710 adds r7, #16
800c262: 46bd mov sp, r7
800c264: bd80 pop {r7, pc}
0800c266 <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
800c266: b580 push {r7, lr}
800c268: b084 sub sp, #16
800c26a: af00 add r7, sp, #0
800c26c: 6078 str r0, [r7, #4]
800c26e: 4608 mov r0, r1
800c270: 4611 mov r1, r2
800c272: 461a mov r2, r3
800c274: 4603 mov r3, r0
800c276: 70fb strb r3, [r7, #3]
800c278: 460b mov r3, r1
800c27a: 70bb strb r3, [r7, #2]
800c27c: 4613 mov r3, r2
800c27e: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
800c280: 2300 movs r3, #0
800c282: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800c284: 2300 movs r3, #0
800c286: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
800c288: 687b ldr r3, [r7, #4]
800c28a: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c28e: 78bb ldrb r3, [r7, #2]
800c290: 883a ldrh r2, [r7, #0]
800c292: 78f9 ldrb r1, [r7, #3]
800c294: f7f8 fe3a bl 8004f0c <HAL_PCD_EP_Open>
800c298: 4603 mov r3, r0
800c29a: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800c29c: 7bfb ldrb r3, [r7, #15]
800c29e: 4618 mov r0, r3
800c2a0: f000 f928 bl 800c4f4 <USBD_Get_USB_Status>
800c2a4: 4603 mov r3, r0
800c2a6: 73bb strb r3, [r7, #14]
return usb_status;
800c2a8: 7bbb ldrb r3, [r7, #14]
}
800c2aa: 4618 mov r0, r3
800c2ac: 3710 adds r7, #16
800c2ae: 46bd mov sp, r7
800c2b0: bd80 pop {r7, pc}
0800c2b2 <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800c2b2: b580 push {r7, lr}
800c2b4: b084 sub sp, #16
800c2b6: af00 add r7, sp, #0
800c2b8: 6078 str r0, [r7, #4]
800c2ba: 460b mov r3, r1
800c2bc: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800c2be: 2300 movs r3, #0
800c2c0: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800c2c2: 2300 movs r3, #0
800c2c4: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
800c2c6: 687b ldr r3, [r7, #4]
800c2c8: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c2cc: 78fa ldrb r2, [r7, #3]
800c2ce: 4611 mov r1, r2
800c2d0: 4618 mov r0, r3
800c2d2: f7f8 fe78 bl 8004fc6 <HAL_PCD_EP_Close>
800c2d6: 4603 mov r3, r0
800c2d8: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800c2da: 7bfb ldrb r3, [r7, #15]
800c2dc: 4618 mov r0, r3
800c2de: f000 f909 bl 800c4f4 <USBD_Get_USB_Status>
800c2e2: 4603 mov r3, r0
800c2e4: 73bb strb r3, [r7, #14]
return usb_status;
800c2e6: 7bbb ldrb r3, [r7, #14]
}
800c2e8: 4618 mov r0, r3
800c2ea: 3710 adds r7, #16
800c2ec: 46bd mov sp, r7
800c2ee: bd80 pop {r7, pc}
0800c2f0 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800c2f0: b580 push {r7, lr}
800c2f2: b084 sub sp, #16
800c2f4: af00 add r7, sp, #0
800c2f6: 6078 str r0, [r7, #4]
800c2f8: 460b mov r3, r1
800c2fa: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800c2fc: 2300 movs r3, #0
800c2fe: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800c300: 2300 movs r3, #0
800c302: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
800c304: 687b ldr r3, [r7, #4]
800c306: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c30a: 78fa ldrb r2, [r7, #3]
800c30c: 4611 mov r1, r2
800c30e: 4618 mov r0, r3
800c310: f7f8 ff20 bl 8005154 <HAL_PCD_EP_SetStall>
800c314: 4603 mov r3, r0
800c316: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800c318: 7bfb ldrb r3, [r7, #15]
800c31a: 4618 mov r0, r3
800c31c: f000 f8ea bl 800c4f4 <USBD_Get_USB_Status>
800c320: 4603 mov r3, r0
800c322: 73bb strb r3, [r7, #14]
return usb_status;
800c324: 7bbb ldrb r3, [r7, #14]
}
800c326: 4618 mov r0, r3
800c328: 3710 adds r7, #16
800c32a: 46bd mov sp, r7
800c32c: bd80 pop {r7, pc}
0800c32e <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800c32e: b580 push {r7, lr}
800c330: b084 sub sp, #16
800c332: af00 add r7, sp, #0
800c334: 6078 str r0, [r7, #4]
800c336: 460b mov r3, r1
800c338: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800c33a: 2300 movs r3, #0
800c33c: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800c33e: 2300 movs r3, #0
800c340: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
800c342: 687b ldr r3, [r7, #4]
800c344: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c348: 78fa ldrb r2, [r7, #3]
800c34a: 4611 mov r1, r2
800c34c: 4618 mov r0, r3
800c34e: f7f8 ff61 bl 8005214 <HAL_PCD_EP_ClrStall>
800c352: 4603 mov r3, r0
800c354: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800c356: 7bfb ldrb r3, [r7, #15]
800c358: 4618 mov r0, r3
800c35a: f000 f8cb bl 800c4f4 <USBD_Get_USB_Status>
800c35e: 4603 mov r3, r0
800c360: 73bb strb r3, [r7, #14]
return usb_status;
800c362: 7bbb ldrb r3, [r7, #14]
}
800c364: 4618 mov r0, r3
800c366: 3710 adds r7, #16
800c368: 46bd mov sp, r7
800c36a: bd80 pop {r7, pc}
0800c36c <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800c36c: b480 push {r7}
800c36e: b085 sub sp, #20
800c370: af00 add r7, sp, #0
800c372: 6078 str r0, [r7, #4]
800c374: 460b mov r3, r1
800c376: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
800c378: 687b ldr r3, [r7, #4]
800c37a: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c37e: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
800c380: f997 3003 ldrsb.w r3, [r7, #3]
800c384: 2b00 cmp r3, #0
800c386: da0b bge.n 800c3a0 <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
800c388: 78fb ldrb r3, [r7, #3]
800c38a: f003 027f and.w r2, r3, #127 @ 0x7f
800c38e: 68f9 ldr r1, [r7, #12]
800c390: 4613 mov r3, r2
800c392: 009b lsls r3, r3, #2
800c394: 4413 add r3, r2
800c396: 00db lsls r3, r3, #3
800c398: 440b add r3, r1
800c39a: 3312 adds r3, #18
800c39c: 781b ldrb r3, [r3, #0]
800c39e: e00b b.n 800c3b8 <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
800c3a0: 78fb ldrb r3, [r7, #3]
800c3a2: f003 027f and.w r2, r3, #127 @ 0x7f
800c3a6: 68f9 ldr r1, [r7, #12]
800c3a8: 4613 mov r3, r2
800c3aa: 009b lsls r3, r3, #2
800c3ac: 4413 add r3, r2
800c3ae: 00db lsls r3, r3, #3
800c3b0: 440b add r3, r1
800c3b2: f503 73a9 add.w r3, r3, #338 @ 0x152
800c3b6: 781b ldrb r3, [r3, #0]
}
}
800c3b8: 4618 mov r0, r3
800c3ba: 3714 adds r7, #20
800c3bc: 46bd mov sp, r7
800c3be: bc80 pop {r7}
800c3c0: 4770 bx lr
0800c3c2 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
800c3c2: b580 push {r7, lr}
800c3c4: b084 sub sp, #16
800c3c6: af00 add r7, sp, #0
800c3c8: 6078 str r0, [r7, #4]
800c3ca: 460b mov r3, r1
800c3cc: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
800c3ce: 2300 movs r3, #0
800c3d0: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
800c3d2: 2300 movs r3, #0
800c3d4: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
800c3d6: 687b ldr r3, [r7, #4]
800c3d8: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c3dc: 78fa ldrb r2, [r7, #3]
800c3de: 4611 mov r1, r2
800c3e0: 4618 mov r0, r3
800c3e2: f7f8 fd6f bl 8004ec4 <HAL_PCD_SetAddress>
800c3e6: 4603 mov r3, r0
800c3e8: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
800c3ea: 7bfb ldrb r3, [r7, #15]
800c3ec: 4618 mov r0, r3
800c3ee: f000 f881 bl 800c4f4 <USBD_Get_USB_Status>
800c3f2: 4603 mov r3, r0
800c3f4: 73bb strb r3, [r7, #14]
return usb_status;
800c3f6: 7bbb ldrb r3, [r7, #14]
}
800c3f8: 4618 mov r0, r3
800c3fa: 3710 adds r7, #16
800c3fc: 46bd mov sp, r7
800c3fe: bd80 pop {r7, pc}
0800c400 <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800c400: b580 push {r7, lr}
800c402: b086 sub sp, #24
800c404: af00 add r7, sp, #0
800c406: 60f8 str r0, [r7, #12]
800c408: 607a str r2, [r7, #4]
800c40a: 461a mov r2, r3
800c40c: 460b mov r3, r1
800c40e: 72fb strb r3, [r7, #11]
800c410: 4613 mov r3, r2
800c412: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800c414: 2300 movs r3, #0
800c416: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
800c418: 2300 movs r3, #0
800c41a: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
800c41c: 68fb ldr r3, [r7, #12]
800c41e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c422: 893b ldrh r3, [r7, #8]
800c424: 7af9 ldrb r1, [r7, #11]
800c426: 687a ldr r2, [r7, #4]
800c428: f7f8 fe5d bl 80050e6 <HAL_PCD_EP_Transmit>
800c42c: 4603 mov r3, r0
800c42e: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800c430: 7dfb ldrb r3, [r7, #23]
800c432: 4618 mov r0, r3
800c434: f000 f85e bl 800c4f4 <USBD_Get_USB_Status>
800c438: 4603 mov r3, r0
800c43a: 75bb strb r3, [r7, #22]
return usb_status;
800c43c: 7dbb ldrb r3, [r7, #22]
}
800c43e: 4618 mov r0, r3
800c440: 3718 adds r7, #24
800c442: 46bd mov sp, r7
800c444: bd80 pop {r7, pc}
0800c446 <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800c446: b580 push {r7, lr}
800c448: b086 sub sp, #24
800c44a: af00 add r7, sp, #0
800c44c: 60f8 str r0, [r7, #12]
800c44e: 607a str r2, [r7, #4]
800c450: 461a mov r2, r3
800c452: 460b mov r3, r1
800c454: 72fb strb r3, [r7, #11]
800c456: 4613 mov r3, r2
800c458: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800c45a: 2300 movs r3, #0
800c45c: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
800c45e: 2300 movs r3, #0
800c460: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
800c462: 68fb ldr r3, [r7, #12]
800c464: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800c468: 893b ldrh r3, [r7, #8]
800c46a: 7af9 ldrb r1, [r7, #11]
800c46c: 687a ldr r2, [r7, #4]
800c46e: f7f8 fdf2 bl 8005056 <HAL_PCD_EP_Receive>
800c472: 4603 mov r3, r0
800c474: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800c476: 7dfb ldrb r3, [r7, #23]
800c478: 4618 mov r0, r3
800c47a: f000 f83b bl 800c4f4 <USBD_Get_USB_Status>
800c47e: 4603 mov r3, r0
800c480: 75bb strb r3, [r7, #22]
return usb_status;
800c482: 7dbb ldrb r3, [r7, #22]
}
800c484: 4618 mov r0, r3
800c486: 3718 adds r7, #24
800c488: 46bd mov sp, r7
800c48a: bd80 pop {r7, pc}
0800c48c <USBD_LL_GetRxDataSize>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Received Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
800c48c: b580 push {r7, lr}
800c48e: b082 sub sp, #8
800c490: af00 add r7, sp, #0
800c492: 6078 str r0, [r7, #4]
800c494: 460b mov r3, r1
800c496: 70fb strb r3, [r7, #3]
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
800c498: 687b ldr r3, [r7, #4]
800c49a: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
800c49e: 78fa ldrb r2, [r7, #3]
800c4a0: 4611 mov r1, r2
800c4a2: 4618 mov r0, r3
800c4a4: f7f8 fe08 bl 80050b8 <HAL_PCD_EP_GetRxCount>
800c4a8: 4603 mov r3, r0
}
800c4aa: 4618 mov r0, r3
800c4ac: 3708 adds r7, #8
800c4ae: 46bd mov sp, r7
800c4b0: bd80 pop {r7, pc}
...
0800c4b4 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
800c4b4: b480 push {r7}
800c4b6: b083 sub sp, #12
800c4b8: af00 add r7, sp, #0
800c4ba: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
return mem;
800c4bc: 4b02 ldr r3, [pc, #8] @ (800c4c8 <USBD_static_malloc+0x14>)
}
800c4be: 4618 mov r0, r3
800c4c0: 370c adds r7, #12
800c4c2: 46bd mov sp, r7
800c4c4: bc80 pop {r7}
800c4c6: 4770 bx lr
800c4c8: 200014fc .word 0x200014fc
0800c4cc <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
800c4cc: b480 push {r7}
800c4ce: b083 sub sp, #12
800c4d0: af00 add r7, sp, #0
800c4d2: 6078 str r0, [r7, #4]
}
800c4d4: bf00 nop
800c4d6: 370c adds r7, #12
800c4d8: 46bd mov sp, r7
800c4da: bc80 pop {r7}
800c4dc: 4770 bx lr
0800c4de <HAL_PCDEx_SetConnectionState>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800c4de: b480 push {r7}
800c4e0: b083 sub sp, #12
800c4e2: af00 add r7, sp, #0
800c4e4: 6078 str r0, [r7, #4]
800c4e6: 460b mov r3, r1
800c4e8: 70fb strb r3, [r7, #3]
{
/* Configure High connection state. */
}
/* USER CODE END 6 */
}
800c4ea: bf00 nop
800c4ec: 370c adds r7, #12
800c4ee: 46bd mov sp, r7
800c4f0: bc80 pop {r7}
800c4f2: 4770 bx lr
0800c4f4 <USBD_Get_USB_Status>:
* @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
800c4f4: b480 push {r7}
800c4f6: b085 sub sp, #20
800c4f8: af00 add r7, sp, #0
800c4fa: 4603 mov r3, r0
800c4fc: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef usb_status = USBD_OK;
800c4fe: 2300 movs r3, #0
800c500: 73fb strb r3, [r7, #15]
switch (hal_status)
800c502: 79fb ldrb r3, [r7, #7]
800c504: 2b03 cmp r3, #3
800c506: d817 bhi.n 800c538 <USBD_Get_USB_Status+0x44>
800c508: a201 add r2, pc, #4 @ (adr r2, 800c510 <USBD_Get_USB_Status+0x1c>)
800c50a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800c50e: bf00 nop
800c510: 0800c521 .word 0x0800c521
800c514: 0800c527 .word 0x0800c527
800c518: 0800c52d .word 0x0800c52d
800c51c: 0800c533 .word 0x0800c533
{
case HAL_OK :
usb_status = USBD_OK;
800c520: 2300 movs r3, #0
800c522: 73fb strb r3, [r7, #15]
break;
800c524: e00b b.n 800c53e <USBD_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBD_FAIL;
800c526: 2302 movs r3, #2
800c528: 73fb strb r3, [r7, #15]
break;
800c52a: e008 b.n 800c53e <USBD_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBD_BUSY;
800c52c: 2301 movs r3, #1
800c52e: 73fb strb r3, [r7, #15]
break;
800c530: e005 b.n 800c53e <USBD_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
800c532: 2302 movs r3, #2
800c534: 73fb strb r3, [r7, #15]
break;
800c536: e002 b.n 800c53e <USBD_Get_USB_Status+0x4a>
default :
usb_status = USBD_FAIL;
800c538: 2302 movs r3, #2
800c53a: 73fb strb r3, [r7, #15]
break;
800c53c: bf00 nop
}
return usb_status;
800c53e: 7bfb ldrb r3, [r7, #15]
}
800c540: 4618 mov r0, r3
800c542: 3714 adds r7, #20
800c544: 46bd mov sp, r7
800c546: bc80 pop {r7}
800c548: 4770 bx lr
800c54a: bf00 nop
0800c54c <siprintf>:
800c54c: b40e push {r1, r2, r3}
800c54e: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
800c552: b510 push {r4, lr}
800c554: 2400 movs r4, #0
800c556: b09d sub sp, #116 @ 0x74
800c558: ab1f add r3, sp, #124 @ 0x7c
800c55a: 9002 str r0, [sp, #8]
800c55c: 9006 str r0, [sp, #24]
800c55e: 9107 str r1, [sp, #28]
800c560: 9104 str r1, [sp, #16]
800c562: 4809 ldr r0, [pc, #36] @ (800c588 <siprintf+0x3c>)
800c564: 4909 ldr r1, [pc, #36] @ (800c58c <siprintf+0x40>)
800c566: f853 2b04 ldr.w r2, [r3], #4
800c56a: 9105 str r1, [sp, #20]
800c56c: 6800 ldr r0, [r0, #0]
800c56e: a902 add r1, sp, #8
800c570: 9301 str r3, [sp, #4]
800c572: 941b str r4, [sp, #108] @ 0x6c
800c574: f000 f992 bl 800c89c <_svfiprintf_r>
800c578: 9b02 ldr r3, [sp, #8]
800c57a: 701c strb r4, [r3, #0]
800c57c: b01d add sp, #116 @ 0x74
800c57e: e8bd 4010 ldmia.w sp!, {r4, lr}
800c582: b003 add sp, #12
800c584: 4770 bx lr
800c586: bf00 nop
800c588: 20000184 .word 0x20000184
800c58c: ffff0208 .word 0xffff0208
0800c590 <memset>:
800c590: 4603 mov r3, r0
800c592: 4402 add r2, r0
800c594: 4293 cmp r3, r2
800c596: d100 bne.n 800c59a <memset+0xa>
800c598: 4770 bx lr
800c59a: f803 1b01 strb.w r1, [r3], #1
800c59e: e7f9 b.n 800c594 <memset+0x4>
0800c5a0 <__errno>:
800c5a0: 4b01 ldr r3, [pc, #4] @ (800c5a8 <__errno+0x8>)
800c5a2: 6818 ldr r0, [r3, #0]
800c5a4: 4770 bx lr
800c5a6: bf00 nop
800c5a8: 20000184 .word 0x20000184
0800c5ac <__libc_init_array>:
800c5ac: b570 push {r4, r5, r6, lr}
800c5ae: 2600 movs r6, #0
800c5b0: 4d0c ldr r5, [pc, #48] @ (800c5e4 <__libc_init_array+0x38>)
800c5b2: 4c0d ldr r4, [pc, #52] @ (800c5e8 <__libc_init_array+0x3c>)
800c5b4: 1b64 subs r4, r4, r5
800c5b6: 10a4 asrs r4, r4, #2
800c5b8: 42a6 cmp r6, r4
800c5ba: d109 bne.n 800c5d0 <__libc_init_array+0x24>
800c5bc: f000 fc76 bl 800ceac <_init>
800c5c0: 2600 movs r6, #0
800c5c2: 4d0a ldr r5, [pc, #40] @ (800c5ec <__libc_init_array+0x40>)
800c5c4: 4c0a ldr r4, [pc, #40] @ (800c5f0 <__libc_init_array+0x44>)
800c5c6: 1b64 subs r4, r4, r5
800c5c8: 10a4 asrs r4, r4, #2
800c5ca: 42a6 cmp r6, r4
800c5cc: d105 bne.n 800c5da <__libc_init_array+0x2e>
800c5ce: bd70 pop {r4, r5, r6, pc}
800c5d0: f855 3b04 ldr.w r3, [r5], #4
800c5d4: 4798 blx r3
800c5d6: 3601 adds r6, #1
800c5d8: e7ee b.n 800c5b8 <__libc_init_array+0xc>
800c5da: f855 3b04 ldr.w r3, [r5], #4
800c5de: 4798 blx r3
800c5e0: 3601 adds r6, #1
800c5e2: e7f2 b.n 800c5ca <__libc_init_array+0x1e>
800c5e4: 0800d1d8 .word 0x0800d1d8
800c5e8: 0800d1d8 .word 0x0800d1d8
800c5ec: 0800d1d8 .word 0x0800d1d8
800c5f0: 0800d1dc .word 0x0800d1dc
0800c5f4 <__retarget_lock_acquire_recursive>:
800c5f4: 4770 bx lr
0800c5f6 <__retarget_lock_release_recursive>:
800c5f6: 4770 bx lr
0800c5f8 <_free_r>:
800c5f8: b538 push {r3, r4, r5, lr}
800c5fa: 4605 mov r5, r0
800c5fc: 2900 cmp r1, #0
800c5fe: d040 beq.n 800c682 <_free_r+0x8a>
800c600: f851 3c04 ldr.w r3, [r1, #-4]
800c604: 1f0c subs r4, r1, #4
800c606: 2b00 cmp r3, #0
800c608: bfb8 it lt
800c60a: 18e4 addlt r4, r4, r3
800c60c: f000 f8de bl 800c7cc <__malloc_lock>
800c610: 4a1c ldr r2, [pc, #112] @ (800c684 <_free_r+0x8c>)
800c612: 6813 ldr r3, [r2, #0]
800c614: b933 cbnz r3, 800c624 <_free_r+0x2c>
800c616: 6063 str r3, [r4, #4]
800c618: 6014 str r4, [r2, #0]
800c61a: 4628 mov r0, r5
800c61c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
800c620: f000 b8da b.w 800c7d8 <__malloc_unlock>
800c624: 42a3 cmp r3, r4
800c626: d908 bls.n 800c63a <_free_r+0x42>
800c628: 6820 ldr r0, [r4, #0]
800c62a: 1821 adds r1, r4, r0
800c62c: 428b cmp r3, r1
800c62e: bf01 itttt eq
800c630: 6819 ldreq r1, [r3, #0]
800c632: 685b ldreq r3, [r3, #4]
800c634: 1809 addeq r1, r1, r0
800c636: 6021 streq r1, [r4, #0]
800c638: e7ed b.n 800c616 <_free_r+0x1e>
800c63a: 461a mov r2, r3
800c63c: 685b ldr r3, [r3, #4]
800c63e: b10b cbz r3, 800c644 <_free_r+0x4c>
800c640: 42a3 cmp r3, r4
800c642: d9fa bls.n 800c63a <_free_r+0x42>
800c644: 6811 ldr r1, [r2, #0]
800c646: 1850 adds r0, r2, r1
800c648: 42a0 cmp r0, r4
800c64a: d10b bne.n 800c664 <_free_r+0x6c>
800c64c: 6820 ldr r0, [r4, #0]
800c64e: 4401 add r1, r0
800c650: 1850 adds r0, r2, r1
800c652: 4283 cmp r3, r0
800c654: 6011 str r1, [r2, #0]
800c656: d1e0 bne.n 800c61a <_free_r+0x22>
800c658: 6818 ldr r0, [r3, #0]
800c65a: 685b ldr r3, [r3, #4]
800c65c: 4408 add r0, r1
800c65e: 6010 str r0, [r2, #0]
800c660: 6053 str r3, [r2, #4]
800c662: e7da b.n 800c61a <_free_r+0x22>
800c664: d902 bls.n 800c66c <_free_r+0x74>
800c666: 230c movs r3, #12
800c668: 602b str r3, [r5, #0]
800c66a: e7d6 b.n 800c61a <_free_r+0x22>
800c66c: 6820 ldr r0, [r4, #0]
800c66e: 1821 adds r1, r4, r0
800c670: 428b cmp r3, r1
800c672: bf01 itttt eq
800c674: 6819 ldreq r1, [r3, #0]
800c676: 685b ldreq r3, [r3, #4]
800c678: 1809 addeq r1, r1, r0
800c67a: 6021 streq r1, [r4, #0]
800c67c: 6063 str r3, [r4, #4]
800c67e: 6054 str r4, [r2, #4]
800c680: e7cb b.n 800c61a <_free_r+0x22>
800c682: bd38 pop {r3, r4, r5, pc}
800c684: 20001860 .word 0x20001860
0800c688 <sbrk_aligned>:
800c688: b570 push {r4, r5, r6, lr}
800c68a: 4e0f ldr r6, [pc, #60] @ (800c6c8 <sbrk_aligned+0x40>)
800c68c: 460c mov r4, r1
800c68e: 6831 ldr r1, [r6, #0]
800c690: 4605 mov r5, r0
800c692: b911 cbnz r1, 800c69a <sbrk_aligned+0x12>
800c694: f000 fba8 bl 800cde8 <_sbrk_r>
800c698: 6030 str r0, [r6, #0]
800c69a: 4621 mov r1, r4
800c69c: 4628 mov r0, r5
800c69e: f000 fba3 bl 800cde8 <_sbrk_r>
800c6a2: 1c43 adds r3, r0, #1
800c6a4: d103 bne.n 800c6ae <sbrk_aligned+0x26>
800c6a6: f04f 34ff mov.w r4, #4294967295
800c6aa: 4620 mov r0, r4
800c6ac: bd70 pop {r4, r5, r6, pc}
800c6ae: 1cc4 adds r4, r0, #3
800c6b0: f024 0403 bic.w r4, r4, #3
800c6b4: 42a0 cmp r0, r4
800c6b6: d0f8 beq.n 800c6aa <sbrk_aligned+0x22>
800c6b8: 1a21 subs r1, r4, r0
800c6ba: 4628 mov r0, r5
800c6bc: f000 fb94 bl 800cde8 <_sbrk_r>
800c6c0: 3001 adds r0, #1
800c6c2: d1f2 bne.n 800c6aa <sbrk_aligned+0x22>
800c6c4: e7ef b.n 800c6a6 <sbrk_aligned+0x1e>
800c6c6: bf00 nop
800c6c8: 2000185c .word 0x2000185c
0800c6cc <_malloc_r>:
800c6cc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
800c6d0: 1ccd adds r5, r1, #3
800c6d2: f025 0503 bic.w r5, r5, #3
800c6d6: 3508 adds r5, #8
800c6d8: 2d0c cmp r5, #12
800c6da: bf38 it cc
800c6dc: 250c movcc r5, #12
800c6de: 2d00 cmp r5, #0
800c6e0: 4606 mov r6, r0
800c6e2: db01 blt.n 800c6e8 <_malloc_r+0x1c>
800c6e4: 42a9 cmp r1, r5
800c6e6: d904 bls.n 800c6f2 <_malloc_r+0x26>
800c6e8: 230c movs r3, #12
800c6ea: 6033 str r3, [r6, #0]
800c6ec: 2000 movs r0, #0
800c6ee: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
800c6f2: f8df 80d4 ldr.w r8, [pc, #212] @ 800c7c8 <_malloc_r+0xfc>
800c6f6: f000 f869 bl 800c7cc <__malloc_lock>
800c6fa: f8d8 3000 ldr.w r3, [r8]
800c6fe: 461c mov r4, r3
800c700: bb44 cbnz r4, 800c754 <_malloc_r+0x88>
800c702: 4629 mov r1, r5
800c704: 4630 mov r0, r6
800c706: f7ff ffbf bl 800c688 <sbrk_aligned>
800c70a: 1c43 adds r3, r0, #1
800c70c: 4604 mov r4, r0
800c70e: d158 bne.n 800c7c2 <_malloc_r+0xf6>
800c710: f8d8 4000 ldr.w r4, [r8]
800c714: 4627 mov r7, r4
800c716: 2f00 cmp r7, #0
800c718: d143 bne.n 800c7a2 <_malloc_r+0xd6>
800c71a: 2c00 cmp r4, #0
800c71c: d04b beq.n 800c7b6 <_malloc_r+0xea>
800c71e: 6823 ldr r3, [r4, #0]
800c720: 4639 mov r1, r7
800c722: 4630 mov r0, r6
800c724: eb04 0903 add.w r9, r4, r3
800c728: f000 fb5e bl 800cde8 <_sbrk_r>
800c72c: 4581 cmp r9, r0
800c72e: d142 bne.n 800c7b6 <_malloc_r+0xea>
800c730: 6821 ldr r1, [r4, #0]
800c732: 4630 mov r0, r6
800c734: 1a6d subs r5, r5, r1
800c736: 4629 mov r1, r5
800c738: f7ff ffa6 bl 800c688 <sbrk_aligned>
800c73c: 3001 adds r0, #1
800c73e: d03a beq.n 800c7b6 <_malloc_r+0xea>
800c740: 6823 ldr r3, [r4, #0]
800c742: 442b add r3, r5
800c744: 6023 str r3, [r4, #0]
800c746: f8d8 3000 ldr.w r3, [r8]
800c74a: 685a ldr r2, [r3, #4]
800c74c: bb62 cbnz r2, 800c7a8 <_malloc_r+0xdc>
800c74e: f8c8 7000 str.w r7, [r8]
800c752: e00f b.n 800c774 <_malloc_r+0xa8>
800c754: 6822 ldr r2, [r4, #0]
800c756: 1b52 subs r2, r2, r5
800c758: d420 bmi.n 800c79c <_malloc_r+0xd0>
800c75a: 2a0b cmp r2, #11
800c75c: d917 bls.n 800c78e <_malloc_r+0xc2>
800c75e: 1961 adds r1, r4, r5
800c760: 42a3 cmp r3, r4
800c762: 6025 str r5, [r4, #0]
800c764: bf18 it ne
800c766: 6059 strne r1, [r3, #4]
800c768: 6863 ldr r3, [r4, #4]
800c76a: bf08 it eq
800c76c: f8c8 1000 streq.w r1, [r8]
800c770: 5162 str r2, [r4, r5]
800c772: 604b str r3, [r1, #4]
800c774: 4630 mov r0, r6
800c776: f000 f82f bl 800c7d8 <__malloc_unlock>
800c77a: f104 000b add.w r0, r4, #11
800c77e: 1d23 adds r3, r4, #4
800c780: f020 0007 bic.w r0, r0, #7
800c784: 1ac2 subs r2, r0, r3
800c786: bf1c itt ne
800c788: 1a1b subne r3, r3, r0
800c78a: 50a3 strne r3, [r4, r2]
800c78c: e7af b.n 800c6ee <_malloc_r+0x22>
800c78e: 6862 ldr r2, [r4, #4]
800c790: 42a3 cmp r3, r4
800c792: bf0c ite eq
800c794: f8c8 2000 streq.w r2, [r8]
800c798: 605a strne r2, [r3, #4]
800c79a: e7eb b.n 800c774 <_malloc_r+0xa8>
800c79c: 4623 mov r3, r4
800c79e: 6864 ldr r4, [r4, #4]
800c7a0: e7ae b.n 800c700 <_malloc_r+0x34>
800c7a2: 463c mov r4, r7
800c7a4: 687f ldr r7, [r7, #4]
800c7a6: e7b6 b.n 800c716 <_malloc_r+0x4a>
800c7a8: 461a mov r2, r3
800c7aa: 685b ldr r3, [r3, #4]
800c7ac: 42a3 cmp r3, r4
800c7ae: d1fb bne.n 800c7a8 <_malloc_r+0xdc>
800c7b0: 2300 movs r3, #0
800c7b2: 6053 str r3, [r2, #4]
800c7b4: e7de b.n 800c774 <_malloc_r+0xa8>
800c7b6: 230c movs r3, #12
800c7b8: 4630 mov r0, r6
800c7ba: 6033 str r3, [r6, #0]
800c7bc: f000 f80c bl 800c7d8 <__malloc_unlock>
800c7c0: e794 b.n 800c6ec <_malloc_r+0x20>
800c7c2: 6005 str r5, [r0, #0]
800c7c4: e7d6 b.n 800c774 <_malloc_r+0xa8>
800c7c6: bf00 nop
800c7c8: 20001860 .word 0x20001860
0800c7cc <__malloc_lock>:
800c7cc: 4801 ldr r0, [pc, #4] @ (800c7d4 <__malloc_lock+0x8>)
800c7ce: f7ff bf11 b.w 800c5f4 <__retarget_lock_acquire_recursive>
800c7d2: bf00 nop
800c7d4: 20001858 .word 0x20001858
0800c7d8 <__malloc_unlock>:
800c7d8: 4801 ldr r0, [pc, #4] @ (800c7e0 <__malloc_unlock+0x8>)
800c7da: f7ff bf0c b.w 800c5f6 <__retarget_lock_release_recursive>
800c7de: bf00 nop
800c7e0: 20001858 .word 0x20001858
0800c7e4 <__ssputs_r>:
800c7e4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800c7e8: 461f mov r7, r3
800c7ea: 688e ldr r6, [r1, #8]
800c7ec: 4682 mov sl, r0
800c7ee: 42be cmp r6, r7
800c7f0: 460c mov r4, r1
800c7f2: 4690 mov r8, r2
800c7f4: 680b ldr r3, [r1, #0]
800c7f6: d82d bhi.n 800c854 <__ssputs_r+0x70>
800c7f8: f9b1 200c ldrsh.w r2, [r1, #12]
800c7fc: f412 6f90 tst.w r2, #1152 @ 0x480
800c800: d026 beq.n 800c850 <__ssputs_r+0x6c>
800c802: 6965 ldr r5, [r4, #20]
800c804: 6909 ldr r1, [r1, #16]
800c806: eb05 0545 add.w r5, r5, r5, lsl #1
800c80a: eba3 0901 sub.w r9, r3, r1
800c80e: eb05 75d5 add.w r5, r5, r5, lsr #31
800c812: 1c7b adds r3, r7, #1
800c814: 444b add r3, r9
800c816: 106d asrs r5, r5, #1
800c818: 429d cmp r5, r3
800c81a: bf38 it cc
800c81c: 461d movcc r5, r3
800c81e: 0553 lsls r3, r2, #21
800c820: d527 bpl.n 800c872 <__ssputs_r+0x8e>
800c822: 4629 mov r1, r5
800c824: f7ff ff52 bl 800c6cc <_malloc_r>
800c828: 4606 mov r6, r0
800c82a: b360 cbz r0, 800c886 <__ssputs_r+0xa2>
800c82c: 464a mov r2, r9
800c82e: 6921 ldr r1, [r4, #16]
800c830: f000 faf8 bl 800ce24 <memcpy>
800c834: 89a3 ldrh r3, [r4, #12]
800c836: f423 6390 bic.w r3, r3, #1152 @ 0x480
800c83a: f043 0380 orr.w r3, r3, #128 @ 0x80
800c83e: 81a3 strh r3, [r4, #12]
800c840: 6126 str r6, [r4, #16]
800c842: 444e add r6, r9
800c844: 6026 str r6, [r4, #0]
800c846: 463e mov r6, r7
800c848: 6165 str r5, [r4, #20]
800c84a: eba5 0509 sub.w r5, r5, r9
800c84e: 60a5 str r5, [r4, #8]
800c850: 42be cmp r6, r7
800c852: d900 bls.n 800c856 <__ssputs_r+0x72>
800c854: 463e mov r6, r7
800c856: 4632 mov r2, r6
800c858: 4641 mov r1, r8
800c85a: 6820 ldr r0, [r4, #0]
800c85c: f000 faaa bl 800cdb4 <memmove>
800c860: 2000 movs r0, #0
800c862: 68a3 ldr r3, [r4, #8]
800c864: 1b9b subs r3, r3, r6
800c866: 60a3 str r3, [r4, #8]
800c868: 6823 ldr r3, [r4, #0]
800c86a: 4433 add r3, r6
800c86c: 6023 str r3, [r4, #0]
800c86e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800c872: 462a mov r2, r5
800c874: f000 fae4 bl 800ce40 <_realloc_r>
800c878: 4606 mov r6, r0
800c87a: 2800 cmp r0, #0
800c87c: d1e0 bne.n 800c840 <__ssputs_r+0x5c>
800c87e: 4650 mov r0, sl
800c880: 6921 ldr r1, [r4, #16]
800c882: f7ff feb9 bl 800c5f8 <_free_r>
800c886: 230c movs r3, #12
800c888: f8ca 3000 str.w r3, [sl]
800c88c: 89a3 ldrh r3, [r4, #12]
800c88e: f04f 30ff mov.w r0, #4294967295
800c892: f043 0340 orr.w r3, r3, #64 @ 0x40
800c896: 81a3 strh r3, [r4, #12]
800c898: e7e9 b.n 800c86e <__ssputs_r+0x8a>
...
0800c89c <_svfiprintf_r>:
800c89c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800c8a0: 4698 mov r8, r3
800c8a2: 898b ldrh r3, [r1, #12]
800c8a4: 4607 mov r7, r0
800c8a6: 061b lsls r3, r3, #24
800c8a8: 460d mov r5, r1
800c8aa: 4614 mov r4, r2
800c8ac: b09d sub sp, #116 @ 0x74
800c8ae: d510 bpl.n 800c8d2 <_svfiprintf_r+0x36>
800c8b0: 690b ldr r3, [r1, #16]
800c8b2: b973 cbnz r3, 800c8d2 <_svfiprintf_r+0x36>
800c8b4: 2140 movs r1, #64 @ 0x40
800c8b6: f7ff ff09 bl 800c6cc <_malloc_r>
800c8ba: 6028 str r0, [r5, #0]
800c8bc: 6128 str r0, [r5, #16]
800c8be: b930 cbnz r0, 800c8ce <_svfiprintf_r+0x32>
800c8c0: 230c movs r3, #12
800c8c2: 603b str r3, [r7, #0]
800c8c4: f04f 30ff mov.w r0, #4294967295
800c8c8: b01d add sp, #116 @ 0x74
800c8ca: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800c8ce: 2340 movs r3, #64 @ 0x40
800c8d0: 616b str r3, [r5, #20]
800c8d2: 2300 movs r3, #0
800c8d4: 9309 str r3, [sp, #36] @ 0x24
800c8d6: 2320 movs r3, #32
800c8d8: f88d 3029 strb.w r3, [sp, #41] @ 0x29
800c8dc: 2330 movs r3, #48 @ 0x30
800c8de: f04f 0901 mov.w r9, #1
800c8e2: f8cd 800c str.w r8, [sp, #12]
800c8e6: f8df 8198 ldr.w r8, [pc, #408] @ 800ca80 <_svfiprintf_r+0x1e4>
800c8ea: f88d 302a strb.w r3, [sp, #42] @ 0x2a
800c8ee: 4623 mov r3, r4
800c8f0: 469a mov sl, r3
800c8f2: f813 2b01 ldrb.w r2, [r3], #1
800c8f6: b10a cbz r2, 800c8fc <_svfiprintf_r+0x60>
800c8f8: 2a25 cmp r2, #37 @ 0x25
800c8fa: d1f9 bne.n 800c8f0 <_svfiprintf_r+0x54>
800c8fc: ebba 0b04 subs.w fp, sl, r4
800c900: d00b beq.n 800c91a <_svfiprintf_r+0x7e>
800c902: 465b mov r3, fp
800c904: 4622 mov r2, r4
800c906: 4629 mov r1, r5
800c908: 4638 mov r0, r7
800c90a: f7ff ff6b bl 800c7e4 <__ssputs_r>
800c90e: 3001 adds r0, #1
800c910: f000 80a7 beq.w 800ca62 <_svfiprintf_r+0x1c6>
800c914: 9a09 ldr r2, [sp, #36] @ 0x24
800c916: 445a add r2, fp
800c918: 9209 str r2, [sp, #36] @ 0x24
800c91a: f89a 3000 ldrb.w r3, [sl]
800c91e: 2b00 cmp r3, #0
800c920: f000 809f beq.w 800ca62 <_svfiprintf_r+0x1c6>
800c924: 2300 movs r3, #0
800c926: f04f 32ff mov.w r2, #4294967295
800c92a: e9cd 2305 strd r2, r3, [sp, #20]
800c92e: f10a 0a01 add.w sl, sl, #1
800c932: 9304 str r3, [sp, #16]
800c934: 9307 str r3, [sp, #28]
800c936: f88d 3053 strb.w r3, [sp, #83] @ 0x53
800c93a: 931a str r3, [sp, #104] @ 0x68
800c93c: 4654 mov r4, sl
800c93e: 2205 movs r2, #5
800c940: f814 1b01 ldrb.w r1, [r4], #1
800c944: 484e ldr r0, [pc, #312] @ (800ca80 <_svfiprintf_r+0x1e4>)
800c946: f000 fa5f bl 800ce08 <memchr>
800c94a: 9a04 ldr r2, [sp, #16]
800c94c: b9d8 cbnz r0, 800c986 <_svfiprintf_r+0xea>
800c94e: 06d0 lsls r0, r2, #27
800c950: bf44 itt mi
800c952: 2320 movmi r3, #32
800c954: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800c958: 0711 lsls r1, r2, #28
800c95a: bf44 itt mi
800c95c: 232b movmi r3, #43 @ 0x2b
800c95e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800c962: f89a 3000 ldrb.w r3, [sl]
800c966: 2b2a cmp r3, #42 @ 0x2a
800c968: d015 beq.n 800c996 <_svfiprintf_r+0xfa>
800c96a: 4654 mov r4, sl
800c96c: 2000 movs r0, #0
800c96e: f04f 0c0a mov.w ip, #10
800c972: 9a07 ldr r2, [sp, #28]
800c974: 4621 mov r1, r4
800c976: f811 3b01 ldrb.w r3, [r1], #1
800c97a: 3b30 subs r3, #48 @ 0x30
800c97c: 2b09 cmp r3, #9
800c97e: d94b bls.n 800ca18 <_svfiprintf_r+0x17c>
800c980: b1b0 cbz r0, 800c9b0 <_svfiprintf_r+0x114>
800c982: 9207 str r2, [sp, #28]
800c984: e014 b.n 800c9b0 <_svfiprintf_r+0x114>
800c986: eba0 0308 sub.w r3, r0, r8
800c98a: fa09 f303 lsl.w r3, r9, r3
800c98e: 4313 orrs r3, r2
800c990: 46a2 mov sl, r4
800c992: 9304 str r3, [sp, #16]
800c994: e7d2 b.n 800c93c <_svfiprintf_r+0xa0>
800c996: 9b03 ldr r3, [sp, #12]
800c998: 1d19 adds r1, r3, #4
800c99a: 681b ldr r3, [r3, #0]
800c99c: 9103 str r1, [sp, #12]
800c99e: 2b00 cmp r3, #0
800c9a0: bfbb ittet lt
800c9a2: 425b neglt r3, r3
800c9a4: f042 0202 orrlt.w r2, r2, #2
800c9a8: 9307 strge r3, [sp, #28]
800c9aa: 9307 strlt r3, [sp, #28]
800c9ac: bfb8 it lt
800c9ae: 9204 strlt r2, [sp, #16]
800c9b0: 7823 ldrb r3, [r4, #0]
800c9b2: 2b2e cmp r3, #46 @ 0x2e
800c9b4: d10a bne.n 800c9cc <_svfiprintf_r+0x130>
800c9b6: 7863 ldrb r3, [r4, #1]
800c9b8: 2b2a cmp r3, #42 @ 0x2a
800c9ba: d132 bne.n 800ca22 <_svfiprintf_r+0x186>
800c9bc: 9b03 ldr r3, [sp, #12]
800c9be: 3402 adds r4, #2
800c9c0: 1d1a adds r2, r3, #4
800c9c2: 681b ldr r3, [r3, #0]
800c9c4: 9203 str r2, [sp, #12]
800c9c6: ea43 73e3 orr.w r3, r3, r3, asr #31
800c9ca: 9305 str r3, [sp, #20]
800c9cc: f8df a0b4 ldr.w sl, [pc, #180] @ 800ca84 <_svfiprintf_r+0x1e8>
800c9d0: 2203 movs r2, #3
800c9d2: 4650 mov r0, sl
800c9d4: 7821 ldrb r1, [r4, #0]
800c9d6: f000 fa17 bl 800ce08 <memchr>
800c9da: b138 cbz r0, 800c9ec <_svfiprintf_r+0x150>
800c9dc: 2240 movs r2, #64 @ 0x40
800c9de: 9b04 ldr r3, [sp, #16]
800c9e0: eba0 000a sub.w r0, r0, sl
800c9e4: 4082 lsls r2, r0
800c9e6: 4313 orrs r3, r2
800c9e8: 3401 adds r4, #1
800c9ea: 9304 str r3, [sp, #16]
800c9ec: f814 1b01 ldrb.w r1, [r4], #1
800c9f0: 2206 movs r2, #6
800c9f2: 4825 ldr r0, [pc, #148] @ (800ca88 <_svfiprintf_r+0x1ec>)
800c9f4: f88d 1028 strb.w r1, [sp, #40] @ 0x28
800c9f8: f000 fa06 bl 800ce08 <memchr>
800c9fc: 2800 cmp r0, #0
800c9fe: d036 beq.n 800ca6e <_svfiprintf_r+0x1d2>
800ca00: 4b22 ldr r3, [pc, #136] @ (800ca8c <_svfiprintf_r+0x1f0>)
800ca02: bb1b cbnz r3, 800ca4c <_svfiprintf_r+0x1b0>
800ca04: 9b03 ldr r3, [sp, #12]
800ca06: 3307 adds r3, #7
800ca08: f023 0307 bic.w r3, r3, #7
800ca0c: 3308 adds r3, #8
800ca0e: 9303 str r3, [sp, #12]
800ca10: 9b09 ldr r3, [sp, #36] @ 0x24
800ca12: 4433 add r3, r6
800ca14: 9309 str r3, [sp, #36] @ 0x24
800ca16: e76a b.n 800c8ee <_svfiprintf_r+0x52>
800ca18: 460c mov r4, r1
800ca1a: 2001 movs r0, #1
800ca1c: fb0c 3202 mla r2, ip, r2, r3
800ca20: e7a8 b.n 800c974 <_svfiprintf_r+0xd8>
800ca22: 2300 movs r3, #0
800ca24: f04f 0c0a mov.w ip, #10
800ca28: 4619 mov r1, r3
800ca2a: 3401 adds r4, #1
800ca2c: 9305 str r3, [sp, #20]
800ca2e: 4620 mov r0, r4
800ca30: f810 2b01 ldrb.w r2, [r0], #1
800ca34: 3a30 subs r2, #48 @ 0x30
800ca36: 2a09 cmp r2, #9
800ca38: d903 bls.n 800ca42 <_svfiprintf_r+0x1a6>
800ca3a: 2b00 cmp r3, #0
800ca3c: d0c6 beq.n 800c9cc <_svfiprintf_r+0x130>
800ca3e: 9105 str r1, [sp, #20]
800ca40: e7c4 b.n 800c9cc <_svfiprintf_r+0x130>
800ca42: 4604 mov r4, r0
800ca44: 2301 movs r3, #1
800ca46: fb0c 2101 mla r1, ip, r1, r2
800ca4a: e7f0 b.n 800ca2e <_svfiprintf_r+0x192>
800ca4c: ab03 add r3, sp, #12
800ca4e: 9300 str r3, [sp, #0]
800ca50: 462a mov r2, r5
800ca52: 4638 mov r0, r7
800ca54: 4b0e ldr r3, [pc, #56] @ (800ca90 <_svfiprintf_r+0x1f4>)
800ca56: a904 add r1, sp, #16
800ca58: f3af 8000 nop.w
800ca5c: 1c42 adds r2, r0, #1
800ca5e: 4606 mov r6, r0
800ca60: d1d6 bne.n 800ca10 <_svfiprintf_r+0x174>
800ca62: 89ab ldrh r3, [r5, #12]
800ca64: 065b lsls r3, r3, #25
800ca66: f53f af2d bmi.w 800c8c4 <_svfiprintf_r+0x28>
800ca6a: 9809 ldr r0, [sp, #36] @ 0x24
800ca6c: e72c b.n 800c8c8 <_svfiprintf_r+0x2c>
800ca6e: ab03 add r3, sp, #12
800ca70: 9300 str r3, [sp, #0]
800ca72: 462a mov r2, r5
800ca74: 4638 mov r0, r7
800ca76: 4b06 ldr r3, [pc, #24] @ (800ca90 <_svfiprintf_r+0x1f4>)
800ca78: a904 add r1, sp, #16
800ca7a: f000 f87d bl 800cb78 <_printf_i>
800ca7e: e7ed b.n 800ca5c <_svfiprintf_r+0x1c0>
800ca80: 0800d19a .word 0x0800d19a
800ca84: 0800d1a0 .word 0x0800d1a0
800ca88: 0800d1a4 .word 0x0800d1a4
800ca8c: 00000000 .word 0x00000000
800ca90: 0800c7e5 .word 0x0800c7e5
0800ca94 <_printf_common>:
800ca94: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800ca98: 4616 mov r6, r2
800ca9a: 4698 mov r8, r3
800ca9c: 688a ldr r2, [r1, #8]
800ca9e: 690b ldr r3, [r1, #16]
800caa0: 4607 mov r7, r0
800caa2: 4293 cmp r3, r2
800caa4: bfb8 it lt
800caa6: 4613 movlt r3, r2
800caa8: 6033 str r3, [r6, #0]
800caaa: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
800caae: 460c mov r4, r1
800cab0: f8dd 9020 ldr.w r9, [sp, #32]
800cab4: b10a cbz r2, 800caba <_printf_common+0x26>
800cab6: 3301 adds r3, #1
800cab8: 6033 str r3, [r6, #0]
800caba: 6823 ldr r3, [r4, #0]
800cabc: 0699 lsls r1, r3, #26
800cabe: bf42 ittt mi
800cac0: 6833 ldrmi r3, [r6, #0]
800cac2: 3302 addmi r3, #2
800cac4: 6033 strmi r3, [r6, #0]
800cac6: 6825 ldr r5, [r4, #0]
800cac8: f015 0506 ands.w r5, r5, #6
800cacc: d106 bne.n 800cadc <_printf_common+0x48>
800cace: f104 0a19 add.w sl, r4, #25
800cad2: 68e3 ldr r3, [r4, #12]
800cad4: 6832 ldr r2, [r6, #0]
800cad6: 1a9b subs r3, r3, r2
800cad8: 42ab cmp r3, r5
800cada: dc2b bgt.n 800cb34 <_printf_common+0xa0>
800cadc: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
800cae0: 6822 ldr r2, [r4, #0]
800cae2: 3b00 subs r3, #0
800cae4: bf18 it ne
800cae6: 2301 movne r3, #1
800cae8: 0692 lsls r2, r2, #26
800caea: d430 bmi.n 800cb4e <_printf_common+0xba>
800caec: 4641 mov r1, r8
800caee: 4638 mov r0, r7
800caf0: f104 0243 add.w r2, r4, #67 @ 0x43
800caf4: 47c8 blx r9
800caf6: 3001 adds r0, #1
800caf8: d023 beq.n 800cb42 <_printf_common+0xae>
800cafa: 6823 ldr r3, [r4, #0]
800cafc: 6922 ldr r2, [r4, #16]
800cafe: f003 0306 and.w r3, r3, #6
800cb02: 2b04 cmp r3, #4
800cb04: bf14 ite ne
800cb06: 2500 movne r5, #0
800cb08: 6833 ldreq r3, [r6, #0]
800cb0a: f04f 0600 mov.w r6, #0
800cb0e: bf08 it eq
800cb10: 68e5 ldreq r5, [r4, #12]
800cb12: f104 041a add.w r4, r4, #26
800cb16: bf08 it eq
800cb18: 1aed subeq r5, r5, r3
800cb1a: f854 3c12 ldr.w r3, [r4, #-18]
800cb1e: bf08 it eq
800cb20: ea25 75e5 biceq.w r5, r5, r5, asr #31
800cb24: 4293 cmp r3, r2
800cb26: bfc4 itt gt
800cb28: 1a9b subgt r3, r3, r2
800cb2a: 18ed addgt r5, r5, r3
800cb2c: 42b5 cmp r5, r6
800cb2e: d11a bne.n 800cb66 <_printf_common+0xd2>
800cb30: 2000 movs r0, #0
800cb32: e008 b.n 800cb46 <_printf_common+0xb2>
800cb34: 2301 movs r3, #1
800cb36: 4652 mov r2, sl
800cb38: 4641 mov r1, r8
800cb3a: 4638 mov r0, r7
800cb3c: 47c8 blx r9
800cb3e: 3001 adds r0, #1
800cb40: d103 bne.n 800cb4a <_printf_common+0xb6>
800cb42: f04f 30ff mov.w r0, #4294967295
800cb46: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800cb4a: 3501 adds r5, #1
800cb4c: e7c1 b.n 800cad2 <_printf_common+0x3e>
800cb4e: 2030 movs r0, #48 @ 0x30
800cb50: 18e1 adds r1, r4, r3
800cb52: f881 0043 strb.w r0, [r1, #67] @ 0x43
800cb56: 1c5a adds r2, r3, #1
800cb58: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
800cb5c: 4422 add r2, r4
800cb5e: 3302 adds r3, #2
800cb60: f882 1043 strb.w r1, [r2, #67] @ 0x43
800cb64: e7c2 b.n 800caec <_printf_common+0x58>
800cb66: 2301 movs r3, #1
800cb68: 4622 mov r2, r4
800cb6a: 4641 mov r1, r8
800cb6c: 4638 mov r0, r7
800cb6e: 47c8 blx r9
800cb70: 3001 adds r0, #1
800cb72: d0e6 beq.n 800cb42 <_printf_common+0xae>
800cb74: 3601 adds r6, #1
800cb76: e7d9 b.n 800cb2c <_printf_common+0x98>
0800cb78 <_printf_i>:
800cb78: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
800cb7c: 7e0f ldrb r7, [r1, #24]
800cb7e: 4691 mov r9, r2
800cb80: 2f78 cmp r7, #120 @ 0x78
800cb82: 4680 mov r8, r0
800cb84: 460c mov r4, r1
800cb86: 469a mov sl, r3
800cb88: 9e0c ldr r6, [sp, #48] @ 0x30
800cb8a: f101 0243 add.w r2, r1, #67 @ 0x43
800cb8e: d807 bhi.n 800cba0 <_printf_i+0x28>
800cb90: 2f62 cmp r7, #98 @ 0x62
800cb92: d80a bhi.n 800cbaa <_printf_i+0x32>
800cb94: 2f00 cmp r7, #0
800cb96: f000 80d1 beq.w 800cd3c <_printf_i+0x1c4>
800cb9a: 2f58 cmp r7, #88 @ 0x58
800cb9c: f000 80b8 beq.w 800cd10 <_printf_i+0x198>
800cba0: f104 0642 add.w r6, r4, #66 @ 0x42
800cba4: f884 7042 strb.w r7, [r4, #66] @ 0x42
800cba8: e03a b.n 800cc20 <_printf_i+0xa8>
800cbaa: f1a7 0363 sub.w r3, r7, #99 @ 0x63
800cbae: 2b15 cmp r3, #21
800cbb0: d8f6 bhi.n 800cba0 <_printf_i+0x28>
800cbb2: a101 add r1, pc, #4 @ (adr r1, 800cbb8 <_printf_i+0x40>)
800cbb4: f851 f023 ldr.w pc, [r1, r3, lsl #2]
800cbb8: 0800cc11 .word 0x0800cc11
800cbbc: 0800cc25 .word 0x0800cc25
800cbc0: 0800cba1 .word 0x0800cba1
800cbc4: 0800cba1 .word 0x0800cba1
800cbc8: 0800cba1 .word 0x0800cba1
800cbcc: 0800cba1 .word 0x0800cba1
800cbd0: 0800cc25 .word 0x0800cc25
800cbd4: 0800cba1 .word 0x0800cba1
800cbd8: 0800cba1 .word 0x0800cba1
800cbdc: 0800cba1 .word 0x0800cba1
800cbe0: 0800cba1 .word 0x0800cba1
800cbe4: 0800cd23 .word 0x0800cd23
800cbe8: 0800cc4f .word 0x0800cc4f
800cbec: 0800ccdd .word 0x0800ccdd
800cbf0: 0800cba1 .word 0x0800cba1
800cbf4: 0800cba1 .word 0x0800cba1
800cbf8: 0800cd45 .word 0x0800cd45
800cbfc: 0800cba1 .word 0x0800cba1
800cc00: 0800cc4f .word 0x0800cc4f
800cc04: 0800cba1 .word 0x0800cba1
800cc08: 0800cba1 .word 0x0800cba1
800cc0c: 0800cce5 .word 0x0800cce5
800cc10: 6833 ldr r3, [r6, #0]
800cc12: 1d1a adds r2, r3, #4
800cc14: 681b ldr r3, [r3, #0]
800cc16: 6032 str r2, [r6, #0]
800cc18: f104 0642 add.w r6, r4, #66 @ 0x42
800cc1c: f884 3042 strb.w r3, [r4, #66] @ 0x42
800cc20: 2301 movs r3, #1
800cc22: e09c b.n 800cd5e <_printf_i+0x1e6>
800cc24: 6833 ldr r3, [r6, #0]
800cc26: 6820 ldr r0, [r4, #0]
800cc28: 1d19 adds r1, r3, #4
800cc2a: 6031 str r1, [r6, #0]
800cc2c: 0606 lsls r6, r0, #24
800cc2e: d501 bpl.n 800cc34 <_printf_i+0xbc>
800cc30: 681d ldr r5, [r3, #0]
800cc32: e003 b.n 800cc3c <_printf_i+0xc4>
800cc34: 0645 lsls r5, r0, #25
800cc36: d5fb bpl.n 800cc30 <_printf_i+0xb8>
800cc38: f9b3 5000 ldrsh.w r5, [r3]
800cc3c: 2d00 cmp r5, #0
800cc3e: da03 bge.n 800cc48 <_printf_i+0xd0>
800cc40: 232d movs r3, #45 @ 0x2d
800cc42: 426d negs r5, r5
800cc44: f884 3043 strb.w r3, [r4, #67] @ 0x43
800cc48: 230a movs r3, #10
800cc4a: 4858 ldr r0, [pc, #352] @ (800cdac <_printf_i+0x234>)
800cc4c: e011 b.n 800cc72 <_printf_i+0xfa>
800cc4e: 6821 ldr r1, [r4, #0]
800cc50: 6833 ldr r3, [r6, #0]
800cc52: 0608 lsls r0, r1, #24
800cc54: f853 5b04 ldr.w r5, [r3], #4
800cc58: d402 bmi.n 800cc60 <_printf_i+0xe8>
800cc5a: 0649 lsls r1, r1, #25
800cc5c: bf48 it mi
800cc5e: b2ad uxthmi r5, r5
800cc60: 2f6f cmp r7, #111 @ 0x6f
800cc62: 6033 str r3, [r6, #0]
800cc64: bf14 ite ne
800cc66: 230a movne r3, #10
800cc68: 2308 moveq r3, #8
800cc6a: 4850 ldr r0, [pc, #320] @ (800cdac <_printf_i+0x234>)
800cc6c: 2100 movs r1, #0
800cc6e: f884 1043 strb.w r1, [r4, #67] @ 0x43
800cc72: 6866 ldr r6, [r4, #4]
800cc74: 2e00 cmp r6, #0
800cc76: 60a6 str r6, [r4, #8]
800cc78: db05 blt.n 800cc86 <_printf_i+0x10e>
800cc7a: 6821 ldr r1, [r4, #0]
800cc7c: 432e orrs r6, r5
800cc7e: f021 0104 bic.w r1, r1, #4
800cc82: 6021 str r1, [r4, #0]
800cc84: d04b beq.n 800cd1e <_printf_i+0x1a6>
800cc86: 4616 mov r6, r2
800cc88: fbb5 f1f3 udiv r1, r5, r3
800cc8c: fb03 5711 mls r7, r3, r1, r5
800cc90: 5dc7 ldrb r7, [r0, r7]
800cc92: f806 7d01 strb.w r7, [r6, #-1]!
800cc96: 462f mov r7, r5
800cc98: 42bb cmp r3, r7
800cc9a: 460d mov r5, r1
800cc9c: d9f4 bls.n 800cc88 <_printf_i+0x110>
800cc9e: 2b08 cmp r3, #8
800cca0: d10b bne.n 800ccba <_printf_i+0x142>
800cca2: 6823 ldr r3, [r4, #0]
800cca4: 07df lsls r7, r3, #31
800cca6: d508 bpl.n 800ccba <_printf_i+0x142>
800cca8: 6923 ldr r3, [r4, #16]
800ccaa: 6861 ldr r1, [r4, #4]
800ccac: 4299 cmp r1, r3
800ccae: bfde ittt le
800ccb0: 2330 movle r3, #48 @ 0x30
800ccb2: f806 3c01 strble.w r3, [r6, #-1]
800ccb6: f106 36ff addle.w r6, r6, #4294967295
800ccba: 1b92 subs r2, r2, r6
800ccbc: 6122 str r2, [r4, #16]
800ccbe: 464b mov r3, r9
800ccc0: 4621 mov r1, r4
800ccc2: 4640 mov r0, r8
800ccc4: f8cd a000 str.w sl, [sp]
800ccc8: aa03 add r2, sp, #12
800ccca: f7ff fee3 bl 800ca94 <_printf_common>
800ccce: 3001 adds r0, #1
800ccd0: d14a bne.n 800cd68 <_printf_i+0x1f0>
800ccd2: f04f 30ff mov.w r0, #4294967295
800ccd6: b004 add sp, #16
800ccd8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800ccdc: 6823 ldr r3, [r4, #0]
800ccde: f043 0320 orr.w r3, r3, #32
800cce2: 6023 str r3, [r4, #0]
800cce4: 2778 movs r7, #120 @ 0x78
800cce6: 4832 ldr r0, [pc, #200] @ (800cdb0 <_printf_i+0x238>)
800cce8: f884 7045 strb.w r7, [r4, #69] @ 0x45
800ccec: 6823 ldr r3, [r4, #0]
800ccee: 6831 ldr r1, [r6, #0]
800ccf0: 061f lsls r7, r3, #24
800ccf2: f851 5b04 ldr.w r5, [r1], #4
800ccf6: d402 bmi.n 800ccfe <_printf_i+0x186>
800ccf8: 065f lsls r7, r3, #25
800ccfa: bf48 it mi
800ccfc: b2ad uxthmi r5, r5
800ccfe: 6031 str r1, [r6, #0]
800cd00: 07d9 lsls r1, r3, #31
800cd02: bf44 itt mi
800cd04: f043 0320 orrmi.w r3, r3, #32
800cd08: 6023 strmi r3, [r4, #0]
800cd0a: b11d cbz r5, 800cd14 <_printf_i+0x19c>
800cd0c: 2310 movs r3, #16
800cd0e: e7ad b.n 800cc6c <_printf_i+0xf4>
800cd10: 4826 ldr r0, [pc, #152] @ (800cdac <_printf_i+0x234>)
800cd12: e7e9 b.n 800cce8 <_printf_i+0x170>
800cd14: 6823 ldr r3, [r4, #0]
800cd16: f023 0320 bic.w r3, r3, #32
800cd1a: 6023 str r3, [r4, #0]
800cd1c: e7f6 b.n 800cd0c <_printf_i+0x194>
800cd1e: 4616 mov r6, r2
800cd20: e7bd b.n 800cc9e <_printf_i+0x126>
800cd22: 6833 ldr r3, [r6, #0]
800cd24: 6825 ldr r5, [r4, #0]
800cd26: 1d18 adds r0, r3, #4
800cd28: 6961 ldr r1, [r4, #20]
800cd2a: 6030 str r0, [r6, #0]
800cd2c: 062e lsls r6, r5, #24
800cd2e: 681b ldr r3, [r3, #0]
800cd30: d501 bpl.n 800cd36 <_printf_i+0x1be>
800cd32: 6019 str r1, [r3, #0]
800cd34: e002 b.n 800cd3c <_printf_i+0x1c4>
800cd36: 0668 lsls r0, r5, #25
800cd38: d5fb bpl.n 800cd32 <_printf_i+0x1ba>
800cd3a: 8019 strh r1, [r3, #0]
800cd3c: 2300 movs r3, #0
800cd3e: 4616 mov r6, r2
800cd40: 6123 str r3, [r4, #16]
800cd42: e7bc b.n 800ccbe <_printf_i+0x146>
800cd44: 6833 ldr r3, [r6, #0]
800cd46: 2100 movs r1, #0
800cd48: 1d1a adds r2, r3, #4
800cd4a: 6032 str r2, [r6, #0]
800cd4c: 681e ldr r6, [r3, #0]
800cd4e: 6862 ldr r2, [r4, #4]
800cd50: 4630 mov r0, r6
800cd52: f000 f859 bl 800ce08 <memchr>
800cd56: b108 cbz r0, 800cd5c <_printf_i+0x1e4>
800cd58: 1b80 subs r0, r0, r6
800cd5a: 6060 str r0, [r4, #4]
800cd5c: 6863 ldr r3, [r4, #4]
800cd5e: 6123 str r3, [r4, #16]
800cd60: 2300 movs r3, #0
800cd62: f884 3043 strb.w r3, [r4, #67] @ 0x43
800cd66: e7aa b.n 800ccbe <_printf_i+0x146>
800cd68: 4632 mov r2, r6
800cd6a: 4649 mov r1, r9
800cd6c: 4640 mov r0, r8
800cd6e: 6923 ldr r3, [r4, #16]
800cd70: 47d0 blx sl
800cd72: 3001 adds r0, #1
800cd74: d0ad beq.n 800ccd2 <_printf_i+0x15a>
800cd76: 6823 ldr r3, [r4, #0]
800cd78: 079b lsls r3, r3, #30
800cd7a: d413 bmi.n 800cda4 <_printf_i+0x22c>
800cd7c: 68e0 ldr r0, [r4, #12]
800cd7e: 9b03 ldr r3, [sp, #12]
800cd80: 4298 cmp r0, r3
800cd82: bfb8 it lt
800cd84: 4618 movlt r0, r3
800cd86: e7a6 b.n 800ccd6 <_printf_i+0x15e>
800cd88: 2301 movs r3, #1
800cd8a: 4632 mov r2, r6
800cd8c: 4649 mov r1, r9
800cd8e: 4640 mov r0, r8
800cd90: 47d0 blx sl
800cd92: 3001 adds r0, #1
800cd94: d09d beq.n 800ccd2 <_printf_i+0x15a>
800cd96: 3501 adds r5, #1
800cd98: 68e3 ldr r3, [r4, #12]
800cd9a: 9903 ldr r1, [sp, #12]
800cd9c: 1a5b subs r3, r3, r1
800cd9e: 42ab cmp r3, r5
800cda0: dcf2 bgt.n 800cd88 <_printf_i+0x210>
800cda2: e7eb b.n 800cd7c <_printf_i+0x204>
800cda4: 2500 movs r5, #0
800cda6: f104 0619 add.w r6, r4, #25
800cdaa: e7f5 b.n 800cd98 <_printf_i+0x220>
800cdac: 0800d1ab .word 0x0800d1ab
800cdb0: 0800d1bc .word 0x0800d1bc
0800cdb4 <memmove>:
800cdb4: 4288 cmp r0, r1
800cdb6: b510 push {r4, lr}
800cdb8: eb01 0402 add.w r4, r1, r2
800cdbc: d902 bls.n 800cdc4 <memmove+0x10>
800cdbe: 4284 cmp r4, r0
800cdc0: 4623 mov r3, r4
800cdc2: d807 bhi.n 800cdd4 <memmove+0x20>
800cdc4: 1e43 subs r3, r0, #1
800cdc6: 42a1 cmp r1, r4
800cdc8: d008 beq.n 800cddc <memmove+0x28>
800cdca: f811 2b01 ldrb.w r2, [r1], #1
800cdce: f803 2f01 strb.w r2, [r3, #1]!
800cdd2: e7f8 b.n 800cdc6 <memmove+0x12>
800cdd4: 4601 mov r1, r0
800cdd6: 4402 add r2, r0
800cdd8: 428a cmp r2, r1
800cdda: d100 bne.n 800cdde <memmove+0x2a>
800cddc: bd10 pop {r4, pc}
800cdde: f813 4d01 ldrb.w r4, [r3, #-1]!
800cde2: f802 4d01 strb.w r4, [r2, #-1]!
800cde6: e7f7 b.n 800cdd8 <memmove+0x24>
0800cde8 <_sbrk_r>:
800cde8: b538 push {r3, r4, r5, lr}
800cdea: 2300 movs r3, #0
800cdec: 4d05 ldr r5, [pc, #20] @ (800ce04 <_sbrk_r+0x1c>)
800cdee: 4604 mov r4, r0
800cdf0: 4608 mov r0, r1
800cdf2: 602b str r3, [r5, #0]
800cdf4: f7f6 fabc bl 8003370 <_sbrk>
800cdf8: 1c43 adds r3, r0, #1
800cdfa: d102 bne.n 800ce02 <_sbrk_r+0x1a>
800cdfc: 682b ldr r3, [r5, #0]
800cdfe: b103 cbz r3, 800ce02 <_sbrk_r+0x1a>
800ce00: 6023 str r3, [r4, #0]
800ce02: bd38 pop {r3, r4, r5, pc}
800ce04: 20001854 .word 0x20001854
0800ce08 <memchr>:
800ce08: 4603 mov r3, r0
800ce0a: b510 push {r4, lr}
800ce0c: b2c9 uxtb r1, r1
800ce0e: 4402 add r2, r0
800ce10: 4293 cmp r3, r2
800ce12: 4618 mov r0, r3
800ce14: d101 bne.n 800ce1a <memchr+0x12>
800ce16: 2000 movs r0, #0
800ce18: e003 b.n 800ce22 <memchr+0x1a>
800ce1a: 7804 ldrb r4, [r0, #0]
800ce1c: 3301 adds r3, #1
800ce1e: 428c cmp r4, r1
800ce20: d1f6 bne.n 800ce10 <memchr+0x8>
800ce22: bd10 pop {r4, pc}
0800ce24 <memcpy>:
800ce24: 440a add r2, r1
800ce26: 4291 cmp r1, r2
800ce28: f100 33ff add.w r3, r0, #4294967295
800ce2c: d100 bne.n 800ce30 <memcpy+0xc>
800ce2e: 4770 bx lr
800ce30: b510 push {r4, lr}
800ce32: f811 4b01 ldrb.w r4, [r1], #1
800ce36: 4291 cmp r1, r2
800ce38: f803 4f01 strb.w r4, [r3, #1]!
800ce3c: d1f9 bne.n 800ce32 <memcpy+0xe>
800ce3e: bd10 pop {r4, pc}
0800ce40 <_realloc_r>:
800ce40: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
800ce44: 4607 mov r7, r0
800ce46: 4614 mov r4, r2
800ce48: 460d mov r5, r1
800ce4a: b921 cbnz r1, 800ce56 <_realloc_r+0x16>
800ce4c: 4611 mov r1, r2
800ce4e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
800ce52: f7ff bc3b b.w 800c6cc <_malloc_r>
800ce56: b92a cbnz r2, 800ce64 <_realloc_r+0x24>
800ce58: f7ff fbce bl 800c5f8 <_free_r>
800ce5c: 4625 mov r5, r4
800ce5e: 4628 mov r0, r5
800ce60: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
800ce64: f000 f81a bl 800ce9c <_malloc_usable_size_r>
800ce68: 4284 cmp r4, r0
800ce6a: 4606 mov r6, r0
800ce6c: d802 bhi.n 800ce74 <_realloc_r+0x34>
800ce6e: ebb4 0f50 cmp.w r4, r0, lsr #1
800ce72: d8f4 bhi.n 800ce5e <_realloc_r+0x1e>
800ce74: 4621 mov r1, r4
800ce76: 4638 mov r0, r7
800ce78: f7ff fc28 bl 800c6cc <_malloc_r>
800ce7c: 4680 mov r8, r0
800ce7e: b908 cbnz r0, 800ce84 <_realloc_r+0x44>
800ce80: 4645 mov r5, r8
800ce82: e7ec b.n 800ce5e <_realloc_r+0x1e>
800ce84: 42b4 cmp r4, r6
800ce86: 4622 mov r2, r4
800ce88: 4629 mov r1, r5
800ce8a: bf28 it cs
800ce8c: 4632 movcs r2, r6
800ce8e: f7ff ffc9 bl 800ce24 <memcpy>
800ce92: 4629 mov r1, r5
800ce94: 4638 mov r0, r7
800ce96: f7ff fbaf bl 800c5f8 <_free_r>
800ce9a: e7f1 b.n 800ce80 <_realloc_r+0x40>
0800ce9c <_malloc_usable_size_r>:
800ce9c: f851 3c04 ldr.w r3, [r1, #-4]
800cea0: 1f18 subs r0, r3, #4
800cea2: 2b00 cmp r3, #0
800cea4: bfbc itt lt
800cea6: 580b ldrlt r3, [r1, r0]
800cea8: 18c0 addlt r0, r0, r3
800ceaa: 4770 bx lr
0800ceac <_init>:
800ceac: b5f8 push {r3, r4, r5, r6, r7, lr}
800ceae: bf00 nop
800ceb0: bcf8 pop {r3, r4, r5, r6, r7}
800ceb2: bc08 pop {r3}
800ceb4: 469e mov lr, r3
800ceb6: 4770 bx lr
0800ceb8 <_fini>:
800ceb8: b5f8 push {r3, r4, r5, r6, r7, lr}
800ceba: bf00 nop
800cebc: bcf8 pop {r3, r4, r5, r6, r7}
800cebe: bc08 pop {r3}
800cec0: 469e mov lr, r3
800cec2: 4770 bx lr
Reference in New Issue View Git Blame Copy Permalink