andrea/AUTOM
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
6e6074a1f73c5de6745745b4c720c054713bc0ee
AUTOM/workspace/AUTOM10/Debug/AUTOM10.list
andrea ab563e0ce0 wip
2025-09-03 23:49:45 +02:00

23754 lines
885 KiB
Plaintext
Raw Blame History

AUTOM10.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000997c 0800010c 0800010c 0000110c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000b0 08009a88 08009a88 0000aa88 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08009b38 08009b38 0000b1cc 2**0
CONTENTS, READONLY
4 .ARM 00000000 08009b38 08009b38 0000b1cc 2**0
CONTENTS, READONLY
5 .preinit_array 00000000 08009b38 08009b38 0000b1cc 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08009b38 08009b38 0000ab38 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08009b3c 08009b3c 0000ab3c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 000001cc 20000000 08009b40 0000b000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00001584 200001cc 08009d0c 0000b1cc 2**2
ALLOC
10 ._user_heap_stack 00000600 20001750 08009d0c 0000b750 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000b1cc 2**0
CONTENTS, READONLY
12 .debug_info 00012100 00000000 00000000 0000b1f5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003383 00000000 00000000 0001d2f5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001128 00000000 00000000 00020678 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000d03 00000000 00000000 000217a0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001ac13 00000000 00000000 000224a3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000154bc 00000000 00000000 0003d0b6 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0009207c 00000000 00000000 00052572 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000e45ee 2**0
CONTENTS, READONLY
20 .debug_frame 00004b6c 00000000 00000000 000e4634 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000052 00000000 00000000 000e91a0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 200001cc .word 0x200001cc
8000128: 00000000 .word 0x00000000
800012c: 08009a70 .word 0x08009a70
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 200001d0 .word 0x200001d0
8000148: 08009a70 .word 0x08009a70
0800014c <HAL_SYSTICK_Callback>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_SYSTICK_Callback(void){
800014c: b580 push {r7, lr}
800014e: af00 add r7, sp, #0
static unsigned char c10ms = 0;
static uint8_t c100ms = 0;
static uint8_t c1s = 0;
if (++c10ms >= 10) { // 10 ms
8000150: 4b16 ldr r3, [pc, #88] @ (80001ac <HAL_SYSTICK_Callback+0x60>)
8000152: 781b ldrb r3, [r3, #0]
8000154: 3301 adds r3, #1
8000156: b2da uxtb r2, r3
8000158: 4b14 ldr r3, [pc, #80] @ (80001ac <HAL_SYSTICK_Callback+0x60>)
800015a: 701a strb r2, [r3, #0]
800015c: 4b13 ldr r3, [pc, #76] @ (80001ac <HAL_SYSTICK_Callback+0x60>)
800015e: 781b ldrb r3, [r3, #0]
8000160: 2b09 cmp r3, #9
8000162: d921 bls.n 80001a8 <HAL_SYSTICK_Callback+0x5c>
c10ms = 0;
8000164: 4b11 ldr r3, [pc, #68] @ (80001ac <HAL_SYSTICK_Callback+0x60>)
8000166: 2200 movs r2, #0
8000168: 701a strb r2, [r3, #0]
if (++c100ms >= 10) { // 10 ms
800016a: 4b11 ldr r3, [pc, #68] @ (80001b0 <HAL_SYSTICK_Callback+0x64>)
800016c: 781b ldrb r3, [r3, #0]
800016e: 3301 adds r3, #1
8000170: b2da uxtb r2, r3
8000172: 4b0f ldr r3, [pc, #60] @ (80001b0 <HAL_SYSTICK_Callback+0x64>)
8000174: 701a strb r2, [r3, #0]
8000176: 4b0e ldr r3, [pc, #56] @ (80001b0 <HAL_SYSTICK_Callback+0x64>)
8000178: 781b ldrb r3, [r3, #0]
800017a: 2b09 cmp r3, #9
800017c: d914 bls.n 80001a8 <HAL_SYSTICK_Callback+0x5c>
c100ms = 0; //flag_10ms = 1; // set a flag; do real work in main loop
800017e: 4b0c ldr r3, [pc, #48] @ (80001b0 <HAL_SYSTICK_Callback+0x64>)
8000180: 2200 movs r2, #0
8000182: 701a strb r2, [r3, #0]
if (++c1s >= 10) { // 10 ms
8000184: 4b0b ldr r3, [pc, #44] @ (80001b4 <HAL_SYSTICK_Callback+0x68>)
8000186: 781b ldrb r3, [r3, #0]
8000188: 3301 adds r3, #1
800018a: b2da uxtb r2, r3
800018c: 4b09 ldr r3, [pc, #36] @ (80001b4 <HAL_SYSTICK_Callback+0x68>)
800018e: 701a strb r2, [r3, #0]
8000190: 4b08 ldr r3, [pc, #32] @ (80001b4 <HAL_SYSTICK_Callback+0x68>)
8000192: 781b ldrb r3, [r3, #0]
8000194: 2b09 cmp r3, #9
8000196: d907 bls.n 80001a8 <HAL_SYSTICK_Callback+0x5c>
c1s = 0;
8000198: 4b06 ldr r3, [pc, #24] @ (80001b4 <HAL_SYSTICK_Callback+0x68>)
800019a: 2200 movs r2, #0
800019c: 701a strb r2, [r3, #0]
HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
800019e: f44f 5100 mov.w r1, #8192 @ 0x2000
80001a2: 4805 ldr r0, [pc, #20] @ (80001b8 <HAL_SYSTICK_Callback+0x6c>)
80001a4: f001 fb56 bl 8001854 <HAL_GPIO_TogglePin>
}
}
}
}
80001a8: bf00 nop
80001aa: bd80 pop {r7, pc}
80001ac: 20000338 .word 0x20000338
80001b0: 20000339 .word 0x20000339
80001b4: 2000033a .word 0x2000033a
80001b8: 40011000 .word 0x40011000
080001bc <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80001bc: b580 push {r7, lr}
80001be: b09a sub sp, #104 @ 0x68
80001c0: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80001c2: f000 fe23 bl 8000e0c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80001c6: f000 f873 bl 80002b0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80001ca: f000 fbb5 bl 8000938 <MX_GPIO_Init>
MX_USB_DEVICE_Init();
80001ce: f008 fa85 bl 80086dc <MX_USB_DEVICE_Init>
MX_TIM2_Init();
80001d2: f000 f9c9 bl 8000568 <MX_TIM2_Init>
MX_TIM4_Init();
80001d6: f000 fb0d bl 80007f4 <MX_TIM4_Init>
MX_TIM3_Init();
80001da: f000 fa69 bl 80006b0 <MX_TIM3_Init>
MX_ADC1_Init();
80001de: f000 f8c5 bl 800036c <MX_ADC1_Init>
MX_TIM1_Init();
80001e2: f000 f901 bl 80003e8 <MX_TIM1_Init>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
80001e6: 2100 movs r1, #0
80001e8: 482b ldr r0, [pc, #172] @ (8000298 <main+0xdc>)
80001ea: f003 fde9 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2);
80001ee: 2104 movs r1, #4
80001f0: 4829 ldr r0, [pc, #164] @ (8000298 <main+0xdc>)
80001f2: f003 fde5 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);
80001f6: 2108 movs r1, #8
80001f8: 4827 ldr r0, [pc, #156] @ (8000298 <main+0xdc>)
80001fa: f003 fde1 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
80001fe: 2100 movs r1, #0
8000200: 4826 ldr r0, [pc, #152] @ (800029c <main+0xe0>)
8000202: f003 fddd bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
8000206: 2104 movs r1, #4
8000208: 4824 ldr r0, [pc, #144] @ (800029c <main+0xe0>)
800020a: f003 fdd9 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
800020e: 2108 movs r1, #8
8000210: 4822 ldr r0, [pc, #136] @ (800029c <main+0xe0>)
8000212: f003 fdd5 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
8000216: 210c movs r1, #12
8000218: 4820 ldr r0, [pc, #128] @ (800029c <main+0xe0>)
800021a: f003 fdd1 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
800021e: 2100 movs r1, #0
8000220: 481f ldr r0, [pc, #124] @ (80002a0 <main+0xe4>)
8000222: f003 fdcd bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2);
8000226: 2104 movs r1, #4
8000228: 481d ldr r0, [pc, #116] @ (80002a0 <main+0xe4>)
800022a: f003 fdc9 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_3);
800022e: 2108 movs r1, #8
8000230: 481b ldr r0, [pc, #108] @ (80002a0 <main+0xe4>)
8000232: f003 fdc5 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_4);
8000236: 210c movs r1, #12
8000238: 4819 ldr r0, [pc, #100] @ (80002a0 <main+0xe4>)
800023a: f003 fdc1 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_1);
800023e: 2100 movs r1, #0
8000240: 4818 ldr r0, [pc, #96] @ (80002a4 <main+0xe8>)
8000242: f003 fdbd bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2);
8000246: 2104 movs r1, #4
8000248: 4816 ldr r0, [pc, #88] @ (80002a4 <main+0xe8>)
800024a: f003 fdb9 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3);
800024e: 2108 movs r1, #8
8000250: 4814 ldr r0, [pc, #80] @ (80002a4 <main+0xe8>)
8000252: f003 fdb5 bl 8003dc0 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4);
8000256: 210c movs r1, #12
8000258: 4812 ldr r0, [pc, #72] @ (80002a4 <main+0xe8>)
800025a: f003 fdb1 bl 8003dc0 <HAL_TIM_PWM_Start>
/* USER CODE BEGIN 2 */
CDC_Transmit_FS((uint8_t*)"Start\r\n", 7);
800025e: 2107 movs r1, #7
8000260: 4811 ldr r0, [pc, #68] @ (80002a8 <main+0xec>)
8000262: f008 fb77 bl 8008954 <CDC_Transmit_FS>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1){
while (CDC_Available()) {
8000266: e011 b.n 800028c <main+0xd0>
int c = CDC_ReadByte();
8000268: f008 fab2 bl 80087d0 <CDC_ReadByte>
800026c: 6678 str r0, [r7, #100] @ 0x64
// uint8_t out = (uint8_t)c;
// if (out >= 'a' && out <= 'z') out -= 32; // to upper
unsigned char s[100];
sprintf((char*)s,"\nc=%03d",c);
800026e: 463b mov r3, r7
8000270: 6e7a ldr r2, [r7, #100] @ 0x64
8000272: 490e ldr r1, [pc, #56] @ (80002ac <main+0xf0>)
8000274: 4618 mov r0, r3
8000276: f008 ff4b bl 8009110 <siprintf>
while (CDC_Transmit_FS(s, 6) == USBD_BUSY) {
800027a: bf00 nop
800027c: 463b mov r3, r7
800027e: 2106 movs r1, #6
8000280: 4618 mov r0, r3
8000282: f008 fb67 bl 8008954 <CDC_Transmit_FS>
8000286: 4603 mov r3, r0
8000288: 2b01 cmp r3, #1
800028a: d0f7 beq.n 800027c <main+0xc0>
while (CDC_Available()) {
800028c: f008 fa8c bl 80087a8 <CDC_Available>
8000290: 4603 mov r3, r0
8000292: 2b00 cmp r3, #0
8000294: d1e8 bne.n 8000268 <main+0xac>
8000296: e7f9 b.n 800028c <main+0xd0>
8000298: 20000218 .word 0x20000218
800029c: 20000260 .word 0x20000260
80002a0: 200002a8 .word 0x200002a8
80002a4: 200002f0 .word 0x200002f0
80002a8: 08009a88 .word 0x08009a88
80002ac: 08009a90 .word 0x08009a90
080002b0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80002b0: b580 push {r7, lr}
80002b2: b094 sub sp, #80 @ 0x50
80002b4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80002b6: f107 0328 add.w r3, r7, #40 @ 0x28
80002ba: 2228 movs r2, #40 @ 0x28
80002bc: 2100 movs r1, #0
80002be: 4618 mov r0, r3
80002c0: f008 ff48 bl 8009154 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80002c4: f107 0314 add.w r3, r7, #20
80002c8: 2200 movs r2, #0
80002ca: 601a str r2, [r3, #0]
80002cc: 605a str r2, [r3, #4]
80002ce: 609a str r2, [r3, #8]
80002d0: 60da str r2, [r3, #12]
80002d2: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80002d4: 1d3b adds r3, r7, #4
80002d6: 2200 movs r2, #0
80002d8: 601a str r2, [r3, #0]
80002da: 605a str r2, [r3, #4]
80002dc: 609a str r2, [r3, #8]
80002de: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80002e0: 2301 movs r3, #1
80002e2: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80002e4: f44f 3380 mov.w r3, #65536 @ 0x10000
80002e8: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
80002ea: 2300 movs r3, #0
80002ec: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80002ee: 2301 movs r3, #1
80002f0: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80002f2: 2302 movs r3, #2
80002f4: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80002f6: f44f 3380 mov.w r3, #65536 @ 0x10000
80002fa: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
80002fc: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000
8000300: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000302: f107 0328 add.w r3, r7, #40 @ 0x28
8000306: 4618 mov r0, r3
8000308: f003 f81e bl 8003348 <HAL_RCC_OscConfig>
800030c: 4603 mov r3, r0
800030e: 2b00 cmp r3, #0
8000310: d001 beq.n 8000316 <SystemClock_Config+0x66>
{
Error_Handler();
8000312: f000 fb69 bl 80009e8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000316: 230f movs r3, #15
8000318: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800031a: 2302 movs r3, #2
800031c: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800031e: 2300 movs r3, #0
8000320: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000322: f44f 6380 mov.w r3, #1024 @ 0x400
8000326: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000328: 2300 movs r3, #0
800032a: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
800032c: f107 0314 add.w r3, r7, #20
8000330: 2102 movs r1, #2
8000332: 4618 mov r0, r3
8000334: f003 fa8a bl 800384c <HAL_RCC_ClockConfig>
8000338: 4603 mov r3, r0
800033a: 2b00 cmp r3, #0
800033c: d001 beq.n 8000342 <SystemClock_Config+0x92>
{
Error_Handler();
800033e: f000 fb53 bl 80009e8 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
8000342: 2312 movs r3, #18
8000344: 607b str r3, [r7, #4]
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
8000346: f44f 4300 mov.w r3, #32768 @ 0x8000
800034a: 60fb str r3, [r7, #12]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
800034c: 2300 movs r3, #0
800034e: 613b str r3, [r7, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000350: 1d3b adds r3, r7, #4
8000352: 4618 mov r0, r3
8000354: f003 fbd6 bl 8003b04 <HAL_RCCEx_PeriphCLKConfig>
8000358: 4603 mov r3, r0
800035a: 2b00 cmp r3, #0
800035c: d001 beq.n 8000362 <SystemClock_Config+0xb2>
{
Error_Handler();
800035e: f000 fb43 bl 80009e8 <Error_Handler>
}
}
8000362: bf00 nop
8000364: 3750 adds r7, #80 @ 0x50
8000366: 46bd mov sp, r7
8000368: bd80 pop {r7, pc}
...
0800036c <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
800036c: b580 push {r7, lr}
800036e: b084 sub sp, #16
8000370: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000372: 1d3b adds r3, r7, #4
8000374: 2200 movs r2, #0
8000376: 601a str r2, [r3, #0]
8000378: 605a str r2, [r3, #4]
800037a: 609a str r2, [r3, #8]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
800037c: 4b18 ldr r3, [pc, #96] @ (80003e0 <MX_ADC1_Init+0x74>)
800037e: 4a19 ldr r2, [pc, #100] @ (80003e4 <MX_ADC1_Init+0x78>)
8000380: 601a str r2, [r3, #0]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000382: 4b17 ldr r3, [pc, #92] @ (80003e0 <MX_ADC1_Init+0x74>)
8000384: 2200 movs r2, #0
8000386: 609a str r2, [r3, #8]
hadc1.Init.ContinuousConvMode = DISABLE;
8000388: 4b15 ldr r3, [pc, #84] @ (80003e0 <MX_ADC1_Init+0x74>)
800038a: 2200 movs r2, #0
800038c: 731a strb r2, [r3, #12]
hadc1.Init.DiscontinuousConvMode = DISABLE;
800038e: 4b14 ldr r3, [pc, #80] @ (80003e0 <MX_ADC1_Init+0x74>)
8000390: 2200 movs r2, #0
8000392: 751a strb r2, [r3, #20]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000394: 4b12 ldr r3, [pc, #72] @ (80003e0 <MX_ADC1_Init+0x74>)
8000396: f44f 2260 mov.w r2, #917504 @ 0xe0000
800039a: 61da str r2, [r3, #28]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800039c: 4b10 ldr r3, [pc, #64] @ (80003e0 <MX_ADC1_Init+0x74>)
800039e: 2200 movs r2, #0
80003a0: 605a str r2, [r3, #4]
hadc1.Init.NbrOfConversion = 1;
80003a2: 4b0f ldr r3, [pc, #60] @ (80003e0 <MX_ADC1_Init+0x74>)
80003a4: 2201 movs r2, #1
80003a6: 611a str r2, [r3, #16]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80003a8: 480d ldr r0, [pc, #52] @ (80003e0 <MX_ADC1_Init+0x74>)
80003aa: f000 fd91 bl 8000ed0 <HAL_ADC_Init>
80003ae: 4603 mov r3, r0
80003b0: 2b00 cmp r3, #0
80003b2: d001 beq.n 80003b8 <MX_ADC1_Init+0x4c>
{
Error_Handler();
80003b4: f000 fb18 bl 80009e8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
80003b8: 2304 movs r3, #4
80003ba: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80003bc: 2301 movs r3, #1
80003be: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80003c0: 2300 movs r3, #0
80003c2: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80003c4: 1d3b adds r3, r7, #4
80003c6: 4619 mov r1, r3
80003c8: 4805 ldr r0, [pc, #20] @ (80003e0 <MX_ADC1_Init+0x74>)
80003ca: f000 fe59 bl 8001080 <HAL_ADC_ConfigChannel>
80003ce: 4603 mov r3, r0
80003d0: 2b00 cmp r3, #0
80003d2: d001 beq.n 80003d8 <MX_ADC1_Init+0x6c>
{
Error_Handler();
80003d4: f000 fb08 bl 80009e8 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
80003d8: bf00 nop
80003da: 3710 adds r7, #16
80003dc: 46bd mov sp, r7
80003de: bd80 pop {r7, pc}
80003e0: 200001e8 .word 0x200001e8
80003e4: 40012400 .word 0x40012400
080003e8 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
80003e8: b580 push {r7, lr}
80003ea: b096 sub sp, #88 @ 0x58
80003ec: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80003ee: f107 0348 add.w r3, r7, #72 @ 0x48
80003f2: 2200 movs r2, #0
80003f4: 601a str r2, [r3, #0]
80003f6: 605a str r2, [r3, #4]
80003f8: 609a str r2, [r3, #8]
80003fa: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80003fc: f107 0340 add.w r3, r7, #64 @ 0x40
8000400: 2200 movs r2, #0
8000402: 601a str r2, [r3, #0]
8000404: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000406: f107 0324 add.w r3, r7, #36 @ 0x24
800040a: 2200 movs r2, #0
800040c: 601a str r2, [r3, #0]
800040e: 605a str r2, [r3, #4]
8000410: 609a str r2, [r3, #8]
8000412: 60da str r2, [r3, #12]
8000414: 611a str r2, [r3, #16]
8000416: 615a str r2, [r3, #20]
8000418: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
800041a: 1d3b adds r3, r7, #4
800041c: 2220 movs r2, #32
800041e: 2100 movs r1, #0
8000420: 4618 mov r0, r3
8000422: f008 fe97 bl 8009154 <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000426: 4b4e ldr r3, [pc, #312] @ (8000560 <MX_TIM1_Init+0x178>)
8000428: 4a4e ldr r2, [pc, #312] @ (8000564 <MX_TIM1_Init+0x17c>)
800042a: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
800042c: 4b4c ldr r3, [pc, #304] @ (8000560 <MX_TIM1_Init+0x178>)
800042e: 2200 movs r2, #0
8000430: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000432: 4b4b ldr r3, [pc, #300] @ (8000560 <MX_TIM1_Init+0x178>)
8000434: 2200 movs r2, #0
8000436: 609a str r2, [r3, #8]
htim1.Init.Period = 17999;
8000438: 4b49 ldr r3, [pc, #292] @ (8000560 <MX_TIM1_Init+0x178>)
800043a: f244 624f movw r2, #17999 @ 0x464f
800043e: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000440: 4b47 ldr r3, [pc, #284] @ (8000560 <MX_TIM1_Init+0x178>)
8000442: 2200 movs r2, #0
8000444: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8000446: 4b46 ldr r3, [pc, #280] @ (8000560 <MX_TIM1_Init+0x178>)
8000448: 2200 movs r2, #0
800044a: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800044c: 4b44 ldr r3, [pc, #272] @ (8000560 <MX_TIM1_Init+0x178>)
800044e: 2200 movs r2, #0
8000450: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8000452: 4843 ldr r0, [pc, #268] @ (8000560 <MX_TIM1_Init+0x178>)
8000454: f003 fc0c bl 8003c70 <HAL_TIM_Base_Init>
8000458: 4603 mov r3, r0
800045a: 2b00 cmp r3, #0
800045c: d001 beq.n 8000462 <MX_TIM1_Init+0x7a>
{
Error_Handler();
800045e: f000 fac3 bl 80009e8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000462: f44f 5380 mov.w r3, #4096 @ 0x1000
8000466: 64bb str r3, [r7, #72] @ 0x48
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8000468: f107 0348 add.w r3, r7, #72 @ 0x48
800046c: 4619 mov r1, r3
800046e: 483c ldr r0, [pc, #240] @ (8000560 <MX_TIM1_Init+0x178>)
8000470: f003 fe0a bl 8004088 <HAL_TIM_ConfigClockSource>
8000474: 4603 mov r3, r0
8000476: 2b00 cmp r3, #0
8000478: d001 beq.n 800047e <MX_TIM1_Init+0x96>
{
Error_Handler();
800047a: f000 fab5 bl 80009e8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
800047e: 4838 ldr r0, [pc, #224] @ (8000560 <MX_TIM1_Init+0x178>)
8000480: f003 fc45 bl 8003d0e <HAL_TIM_PWM_Init>
8000484: 4603 mov r3, r0
8000486: 2b00 cmp r3, #0
8000488: d001 beq.n 800048e <MX_TIM1_Init+0xa6>
{
Error_Handler();
800048a: f000 faad bl 80009e8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800048e: 2300 movs r3, #0
8000490: 643b str r3, [r7, #64] @ 0x40
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000492: 2300 movs r3, #0
8000494: 647b str r3, [r7, #68] @ 0x44
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000496: f107 0340 add.w r3, r7, #64 @ 0x40
800049a: 4619 mov r1, r3
800049c: 4830 ldr r0, [pc, #192] @ (8000560 <MX_TIM1_Init+0x178>)
800049e: f004 f96b bl 8004778 <HAL_TIMEx_MasterConfigSynchronization>
80004a2: 4603 mov r3, r0
80004a4: 2b00 cmp r3, #0
80004a6: d001 beq.n 80004ac <MX_TIM1_Init+0xc4>
{
Error_Handler();
80004a8: f000 fa9e bl 80009e8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80004ac: 2360 movs r3, #96 @ 0x60
80004ae: 627b str r3, [r7, #36] @ 0x24
sConfigOC.Pulse = 2400;
80004b0: f44f 6316 mov.w r3, #2400 @ 0x960
80004b4: 62bb str r3, [r7, #40] @ 0x28
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80004b6: 2300 movs r3, #0
80004b8: 62fb str r3, [r7, #44] @ 0x2c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80004ba: 2300 movs r3, #0
80004bc: 633b str r3, [r7, #48] @ 0x30
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
80004be: 2304 movs r3, #4
80004c0: 637b str r3, [r7, #52] @ 0x34
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80004c2: 2300 movs r3, #0
80004c4: 63bb str r3, [r7, #56] @ 0x38
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80004c6: 2300 movs r3, #0
80004c8: 63fb str r3, [r7, #60] @ 0x3c
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80004ca: f107 0324 add.w r3, r7, #36 @ 0x24
80004ce: 2200 movs r2, #0
80004d0: 4619 mov r1, r3
80004d2: 4823 ldr r0, [pc, #140] @ (8000560 <MX_TIM1_Init+0x178>)
80004d4: f003 fd16 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80004d8: 4603 mov r3, r0
80004da: 2b00 cmp r3, #0
80004dc: d001 beq.n 80004e2 <MX_TIM1_Init+0xfa>
{
Error_Handler();
80004de: f000 fa83 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 5500;
80004e2: f241 537c movw r3, #5500 @ 0x157c
80004e6: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80004e8: f107 0324 add.w r3, r7, #36 @ 0x24
80004ec: 2204 movs r2, #4
80004ee: 4619 mov r1, r3
80004f0: 481b ldr r0, [pc, #108] @ (8000560 <MX_TIM1_Init+0x178>)
80004f2: f003 fd07 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80004f6: 4603 mov r3, r0
80004f8: 2b00 cmp r3, #0
80004fa: d001 beq.n 8000500 <MX_TIM1_Init+0x118>
{
Error_Handler();
80004fc: f000 fa74 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 6500;
8000500: f641 1364 movw r3, #6500 @ 0x1964
8000504: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000506: f107 0324 add.w r3, r7, #36 @ 0x24
800050a: 2208 movs r2, #8
800050c: 4619 mov r1, r3
800050e: 4814 ldr r0, [pc, #80] @ (8000560 <MX_TIM1_Init+0x178>)
8000510: f003 fcf8 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
8000514: 4603 mov r3, r0
8000516: 2b00 cmp r3, #0
8000518: d001 beq.n 800051e <MX_TIM1_Init+0x136>
{
Error_Handler();
800051a: f000 fa65 bl 80009e8 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800051e: 2300 movs r3, #0
8000520: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8000522: 2300 movs r3, #0
8000524: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8000526: 2300 movs r3, #0
8000528: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
800052a: 2300 movs r3, #0
800052c: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
800052e: 2300 movs r3, #0
8000530: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000532: f44f 5300 mov.w r3, #8192 @ 0x2000
8000536: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8000538: 2300 movs r3, #0
800053a: 623b str r3, [r7, #32]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
800053c: 1d3b adds r3, r7, #4
800053e: 4619 mov r1, r3
8000540: 4807 ldr r0, [pc, #28] @ (8000560 <MX_TIM1_Init+0x178>)
8000542: f004 f977 bl 8004834 <HAL_TIMEx_ConfigBreakDeadTime>
8000546: 4603 mov r3, r0
8000548: 2b00 cmp r3, #0
800054a: d001 beq.n 8000550 <MX_TIM1_Init+0x168>
{
Error_Handler();
800054c: f000 fa4c bl 80009e8 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
8000550: 4803 ldr r0, [pc, #12] @ (8000560 <MX_TIM1_Init+0x178>)
8000552: f000 fb15 bl 8000b80 <HAL_TIM_MspPostInit>
}
8000556: bf00 nop
8000558: 3758 adds r7, #88 @ 0x58
800055a: 46bd mov sp, r7
800055c: bd80 pop {r7, pc}
800055e: bf00 nop
8000560: 20000218 .word 0x20000218
8000564: 40012c00 .word 0x40012c00
08000568 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8000568: b580 push {r7, lr}
800056a: b08e sub sp, #56 @ 0x38
800056c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800056e: f107 0328 add.w r3, r7, #40 @ 0x28
8000572: 2200 movs r2, #0
8000574: 601a str r2, [r3, #0]
8000576: 605a str r2, [r3, #4]
8000578: 609a str r2, [r3, #8]
800057a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800057c: f107 0320 add.w r3, r7, #32
8000580: 2200 movs r2, #0
8000582: 601a str r2, [r3, #0]
8000584: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000586: 1d3b adds r3, r7, #4
8000588: 2200 movs r2, #0
800058a: 601a str r2, [r3, #0]
800058c: 605a str r2, [r3, #4]
800058e: 609a str r2, [r3, #8]
8000590: 60da str r2, [r3, #12]
8000592: 611a str r2, [r3, #16]
8000594: 615a str r2, [r3, #20]
8000596: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000598: 4b44 ldr r3, [pc, #272] @ (80006ac <MX_TIM2_Init+0x144>)
800059a: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
800059e: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80005a0: 4b42 ldr r3, [pc, #264] @ (80006ac <MX_TIM2_Init+0x144>)
80005a2: 2200 movs r2, #0
80005a4: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
80005a6: 4b41 ldr r3, [pc, #260] @ (80006ac <MX_TIM2_Init+0x144>)
80005a8: 2200 movs r2, #0
80005aa: 609a str r2, [r3, #8]
htim2.Init.Period = 17999;
80005ac: 4b3f ldr r3, [pc, #252] @ (80006ac <MX_TIM2_Init+0x144>)
80005ae: f244 624f movw r2, #17999 @ 0x464f
80005b2: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80005b4: 4b3d ldr r3, [pc, #244] @ (80006ac <MX_TIM2_Init+0x144>)
80005b6: 2200 movs r2, #0
80005b8: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80005ba: 4b3c ldr r3, [pc, #240] @ (80006ac <MX_TIM2_Init+0x144>)
80005bc: 2200 movs r2, #0
80005be: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
80005c0: 483a ldr r0, [pc, #232] @ (80006ac <MX_TIM2_Init+0x144>)
80005c2: f003 fb55 bl 8003c70 <HAL_TIM_Base_Init>
80005c6: 4603 mov r3, r0
80005c8: 2b00 cmp r3, #0
80005ca: d001 beq.n 80005d0 <MX_TIM2_Init+0x68>
{
Error_Handler();
80005cc: f000 fa0c bl 80009e8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80005d0: f44f 5380 mov.w r3, #4096 @ 0x1000
80005d4: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
80005d6: f107 0328 add.w r3, r7, #40 @ 0x28
80005da: 4619 mov r1, r3
80005dc: 4833 ldr r0, [pc, #204] @ (80006ac <MX_TIM2_Init+0x144>)
80005de: f003 fd53 bl 8004088 <HAL_TIM_ConfigClockSource>
80005e2: 4603 mov r3, r0
80005e4: 2b00 cmp r3, #0
80005e6: d001 beq.n 80005ec <MX_TIM2_Init+0x84>
{
Error_Handler();
80005e8: f000 f9fe bl 80009e8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
80005ec: 482f ldr r0, [pc, #188] @ (80006ac <MX_TIM2_Init+0x144>)
80005ee: f003 fb8e bl 8003d0e <HAL_TIM_PWM_Init>
80005f2: 4603 mov r3, r0
80005f4: 2b00 cmp r3, #0
80005f6: d001 beq.n 80005fc <MX_TIM2_Init+0x94>
{
Error_Handler();
80005f8: f000 f9f6 bl 80009e8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80005fc: 2300 movs r3, #0
80005fe: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000600: 2300 movs r3, #0
8000602: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000604: f107 0320 add.w r3, r7, #32
8000608: 4619 mov r1, r3
800060a: 4828 ldr r0, [pc, #160] @ (80006ac <MX_TIM2_Init+0x144>)
800060c: f004 f8b4 bl 8004778 <HAL_TIMEx_MasterConfigSynchronization>
8000610: 4603 mov r3, r0
8000612: 2b00 cmp r3, #0
8000614: d001 beq.n 800061a <MX_TIM2_Init+0xb2>
{
Error_Handler();
8000616: f000 f9e7 bl 80009e8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800061a: 2360 movs r3, #96 @ 0x60
800061c: 607b str r3, [r7, #4]
sConfigOC.Pulse = 1000;
800061e: f44f 737a mov.w r3, #1000 @ 0x3e8
8000622: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000624: 2300 movs r3, #0
8000626: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8000628: 2304 movs r3, #4
800062a: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800062c: 1d3b adds r3, r7, #4
800062e: 2200 movs r2, #0
8000630: 4619 mov r1, r3
8000632: 481e ldr r0, [pc, #120] @ (80006ac <MX_TIM2_Init+0x144>)
8000634: f003 fc66 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
8000638: 4603 mov r3, r0
800063a: 2b00 cmp r3, #0
800063c: d001 beq.n 8000642 <MX_TIM2_Init+0xda>
{
Error_Handler();
800063e: f000 f9d3 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 2000;
8000642: f44f 63fa mov.w r3, #2000 @ 0x7d0
8000646: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000648: 1d3b adds r3, r7, #4
800064a: 2204 movs r2, #4
800064c: 4619 mov r1, r3
800064e: 4817 ldr r0, [pc, #92] @ (80006ac <MX_TIM2_Init+0x144>)
8000650: f003 fc58 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
8000654: 4603 mov r3, r0
8000656: 2b00 cmp r3, #0
8000658: d001 beq.n 800065e <MX_TIM2_Init+0xf6>
{
Error_Handler();
800065a: f000 f9c5 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 3000;
800065e: f640 33b8 movw r3, #3000 @ 0xbb8
8000662: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000664: 2300 movs r3, #0
8000666: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000668: 1d3b adds r3, r7, #4
800066a: 2208 movs r2, #8
800066c: 4619 mov r1, r3
800066e: 480f ldr r0, [pc, #60] @ (80006ac <MX_TIM2_Init+0x144>)
8000670: f003 fc48 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
8000674: 4603 mov r3, r0
8000676: 2b00 cmp r3, #0
8000678: d001 beq.n 800067e <MX_TIM2_Init+0x116>
{
Error_Handler();
800067a: f000 f9b5 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 4000;
800067e: f44f 637a mov.w r3, #4000 @ 0xfa0
8000682: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
8000684: 2304 movs r3, #4
8000686: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8000688: 1d3b adds r3, r7, #4
800068a: 220c movs r2, #12
800068c: 4619 mov r1, r3
800068e: 4807 ldr r0, [pc, #28] @ (80006ac <MX_TIM2_Init+0x144>)
8000690: f003 fc38 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
8000694: 4603 mov r3, r0
8000696: 2b00 cmp r3, #0
8000698: d001 beq.n 800069e <MX_TIM2_Init+0x136>
{
Error_Handler();
800069a: f000 f9a5 bl 80009e8 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
800069e: 4803 ldr r0, [pc, #12] @ (80006ac <MX_TIM2_Init+0x144>)
80006a0: f000 fa6e bl 8000b80 <HAL_TIM_MspPostInit>
}
80006a4: bf00 nop
80006a6: 3738 adds r7, #56 @ 0x38
80006a8: 46bd mov sp, r7
80006aa: bd80 pop {r7, pc}
80006ac: 20000260 .word 0x20000260
080006b0 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
80006b0: b580 push {r7, lr}
80006b2: b08e sub sp, #56 @ 0x38
80006b4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80006b6: f107 0328 add.w r3, r7, #40 @ 0x28
80006ba: 2200 movs r2, #0
80006bc: 601a str r2, [r3, #0]
80006be: 605a str r2, [r3, #4]
80006c0: 609a str r2, [r3, #8]
80006c2: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80006c4: f107 0320 add.w r3, r7, #32
80006c8: 2200 movs r2, #0
80006ca: 601a str r2, [r3, #0]
80006cc: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80006ce: 1d3b adds r3, r7, #4
80006d0: 2200 movs r2, #0
80006d2: 601a str r2, [r3, #0]
80006d4: 605a str r2, [r3, #4]
80006d6: 609a str r2, [r3, #8]
80006d8: 60da str r2, [r3, #12]
80006da: 611a str r2, [r3, #16]
80006dc: 615a str r2, [r3, #20]
80006de: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80006e0: 4b42 ldr r3, [pc, #264] @ (80007ec <MX_TIM3_Init+0x13c>)
80006e2: 4a43 ldr r2, [pc, #268] @ (80007f0 <MX_TIM3_Init+0x140>)
80006e4: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80006e6: 4b41 ldr r3, [pc, #260] @ (80007ec <MX_TIM3_Init+0x13c>)
80006e8: 2200 movs r2, #0
80006ea: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80006ec: 4b3f ldr r3, [pc, #252] @ (80007ec <MX_TIM3_Init+0x13c>)
80006ee: 2200 movs r2, #0
80006f0: 609a str r2, [r3, #8]
htim3.Init.Period = 17999;
80006f2: 4b3e ldr r3, [pc, #248] @ (80007ec <MX_TIM3_Init+0x13c>)
80006f4: f244 624f movw r2, #17999 @ 0x464f
80006f8: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80006fa: 4b3c ldr r3, [pc, #240] @ (80007ec <MX_TIM3_Init+0x13c>)
80006fc: 2200 movs r2, #0
80006fe: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000700: 4b3a ldr r3, [pc, #232] @ (80007ec <MX_TIM3_Init+0x13c>)
8000702: 2200 movs r2, #0
8000704: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8000706: 4839 ldr r0, [pc, #228] @ (80007ec <MX_TIM3_Init+0x13c>)
8000708: f003 fab2 bl 8003c70 <HAL_TIM_Base_Init>
800070c: 4603 mov r3, r0
800070e: 2b00 cmp r3, #0
8000710: d001 beq.n 8000716 <MX_TIM3_Init+0x66>
{
Error_Handler();
8000712: f000 f969 bl 80009e8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000716: f44f 5380 mov.w r3, #4096 @ 0x1000
800071a: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
800071c: f107 0328 add.w r3, r7, #40 @ 0x28
8000720: 4619 mov r1, r3
8000722: 4832 ldr r0, [pc, #200] @ (80007ec <MX_TIM3_Init+0x13c>)
8000724: f003 fcb0 bl 8004088 <HAL_TIM_ConfigClockSource>
8000728: 4603 mov r3, r0
800072a: 2b00 cmp r3, #0
800072c: d001 beq.n 8000732 <MX_TIM3_Init+0x82>
{
Error_Handler();
800072e: f000 f95b bl 80009e8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8000732: 482e ldr r0, [pc, #184] @ (80007ec <MX_TIM3_Init+0x13c>)
8000734: f003 faeb bl 8003d0e <HAL_TIM_PWM_Init>
8000738: 4603 mov r3, r0
800073a: 2b00 cmp r3, #0
800073c: d001 beq.n 8000742 <MX_TIM3_Init+0x92>
{
Error_Handler();
800073e: f000 f953 bl 80009e8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000742: 2300 movs r3, #0
8000744: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000746: 2300 movs r3, #0
8000748: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
800074a: f107 0320 add.w r3, r7, #32
800074e: 4619 mov r1, r3
8000750: 4826 ldr r0, [pc, #152] @ (80007ec <MX_TIM3_Init+0x13c>)
8000752: f004 f811 bl 8004778 <HAL_TIMEx_MasterConfigSynchronization>
8000756: 4603 mov r3, r0
8000758: 2b00 cmp r3, #0
800075a: d001 beq.n 8000760 <MX_TIM3_Init+0xb0>
{
Error_Handler();
800075c: f000 f944 bl 80009e8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000760: 2360 movs r3, #96 @ 0x60
8000762: 607b str r3, [r7, #4]
sConfigOC.Pulse = 9000;
8000764: f242 3328 movw r3, #9000 @ 0x2328
8000768: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800076a: 2300 movs r3, #0
800076c: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
800076e: 2304 movs r3, #4
8000770: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000772: 1d3b adds r3, r7, #4
8000774: 2200 movs r2, #0
8000776: 4619 mov r1, r3
8000778: 481c ldr r0, [pc, #112] @ (80007ec <MX_TIM3_Init+0x13c>)
800077a: f003 fbc3 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
800077e: 4603 mov r3, r0
8000780: 2b00 cmp r3, #0
8000782: d001 beq.n 8000788 <MX_TIM3_Init+0xd8>
{
Error_Handler();
8000784: f000 f930 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 10000;
8000788: f242 7310 movw r3, #10000 @ 0x2710
800078c: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
800078e: 1d3b adds r3, r7, #4
8000790: 2204 movs r2, #4
8000792: 4619 mov r1, r3
8000794: 4815 ldr r0, [pc, #84] @ (80007ec <MX_TIM3_Init+0x13c>)
8000796: f003 fbb5 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
800079a: 4603 mov r3, r0
800079c: 2b00 cmp r3, #0
800079e: d001 beq.n 80007a4 <MX_TIM3_Init+0xf4>
{
Error_Handler();
80007a0: f000 f922 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 11000;
80007a4: f642 23f8 movw r3, #11000 @ 0x2af8
80007a8: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80007aa: 1d3b adds r3, r7, #4
80007ac: 2208 movs r2, #8
80007ae: 4619 mov r1, r3
80007b0: 480e ldr r0, [pc, #56] @ (80007ec <MX_TIM3_Init+0x13c>)
80007b2: f003 fba7 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80007b6: 4603 mov r3, r0
80007b8: 2b00 cmp r3, #0
80007ba: d001 beq.n 80007c0 <MX_TIM3_Init+0x110>
{
Error_Handler();
80007bc: f000 f914 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 12000;
80007c0: f642 63e0 movw r3, #12000 @ 0x2ee0
80007c4: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
80007c6: 1d3b adds r3, r7, #4
80007c8: 220c movs r2, #12
80007ca: 4619 mov r1, r3
80007cc: 4807 ldr r0, [pc, #28] @ (80007ec <MX_TIM3_Init+0x13c>)
80007ce: f003 fb99 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80007d2: 4603 mov r3, r0
80007d4: 2b00 cmp r3, #0
80007d6: d001 beq.n 80007dc <MX_TIM3_Init+0x12c>
{
Error_Handler();
80007d8: f000 f906 bl 80009e8 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
80007dc: 4803 ldr r0, [pc, #12] @ (80007ec <MX_TIM3_Init+0x13c>)
80007de: f000 f9cf bl 8000b80 <HAL_TIM_MspPostInit>
}
80007e2: bf00 nop
80007e4: 3738 adds r7, #56 @ 0x38
80007e6: 46bd mov sp, r7
80007e8: bd80 pop {r7, pc}
80007ea: bf00 nop
80007ec: 200002a8 .word 0x200002a8
80007f0: 40000400 .word 0x40000400
080007f4 <MX_TIM4_Init>:
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
80007f4: b580 push {r7, lr}
80007f6: b08e sub sp, #56 @ 0x38
80007f8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80007fa: f107 0328 add.w r3, r7, #40 @ 0x28
80007fe: 2200 movs r2, #0
8000800: 601a str r2, [r3, #0]
8000802: 605a str r2, [r3, #4]
8000804: 609a str r2, [r3, #8]
8000806: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000808: f107 0320 add.w r3, r7, #32
800080c: 2200 movs r2, #0
800080e: 601a str r2, [r3, #0]
8000810: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000812: 1d3b adds r3, r7, #4
8000814: 2200 movs r2, #0
8000816: 601a str r2, [r3, #0]
8000818: 605a str r2, [r3, #4]
800081a: 609a str r2, [r3, #8]
800081c: 60da str r2, [r3, #12]
800081e: 611a str r2, [r3, #16]
8000820: 615a str r2, [r3, #20]
8000822: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
8000824: 4b42 ldr r3, [pc, #264] @ (8000930 <MX_TIM4_Init+0x13c>)
8000826: 4a43 ldr r2, [pc, #268] @ (8000934 <MX_TIM4_Init+0x140>)
8000828: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 0;
800082a: 4b41 ldr r3, [pc, #260] @ (8000930 <MX_TIM4_Init+0x13c>)
800082c: 2200 movs r2, #0
800082e: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
8000830: 4b3f ldr r3, [pc, #252] @ (8000930 <MX_TIM4_Init+0x13c>)
8000832: 2200 movs r2, #0
8000834: 609a str r2, [r3, #8]
htim4.Init.Period = 17999;
8000836: 4b3e ldr r3, [pc, #248] @ (8000930 <MX_TIM4_Init+0x13c>)
8000838: f244 624f movw r2, #17999 @ 0x464f
800083c: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800083e: 4b3c ldr r3, [pc, #240] @ (8000930 <MX_TIM4_Init+0x13c>)
8000840: 2200 movs r2, #0
8000842: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000844: 4b3a ldr r3, [pc, #232] @ (8000930 <MX_TIM4_Init+0x13c>)
8000846: 2200 movs r2, #0
8000848: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
800084a: 4839 ldr r0, [pc, #228] @ (8000930 <MX_TIM4_Init+0x13c>)
800084c: f003 fa10 bl 8003c70 <HAL_TIM_Base_Init>
8000850: 4603 mov r3, r0
8000852: 2b00 cmp r3, #0
8000854: d001 beq.n 800085a <MX_TIM4_Init+0x66>
{
Error_Handler();
8000856: f000 f8c7 bl 80009e8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800085a: f44f 5380 mov.w r3, #4096 @ 0x1000
800085e: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
8000860: f107 0328 add.w r3, r7, #40 @ 0x28
8000864: 4619 mov r1, r3
8000866: 4832 ldr r0, [pc, #200] @ (8000930 <MX_TIM4_Init+0x13c>)
8000868: f003 fc0e bl 8004088 <HAL_TIM_ConfigClockSource>
800086c: 4603 mov r3, r0
800086e: 2b00 cmp r3, #0
8000870: d001 beq.n 8000876 <MX_TIM4_Init+0x82>
{
Error_Handler();
8000872: f000 f8b9 bl 80009e8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
8000876: 482e ldr r0, [pc, #184] @ (8000930 <MX_TIM4_Init+0x13c>)
8000878: f003 fa49 bl 8003d0e <HAL_TIM_PWM_Init>
800087c: 4603 mov r3, r0
800087e: 2b00 cmp r3, #0
8000880: d001 beq.n 8000886 <MX_TIM4_Init+0x92>
{
Error_Handler();
8000882: f000 f8b1 bl 80009e8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000886: 2300 movs r3, #0
8000888: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800088a: 2300 movs r3, #0
800088c: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
800088e: f107 0320 add.w r3, r7, #32
8000892: 4619 mov r1, r3
8000894: 4826 ldr r0, [pc, #152] @ (8000930 <MX_TIM4_Init+0x13c>)
8000896: f003 ff6f bl 8004778 <HAL_TIMEx_MasterConfigSynchronization>
800089a: 4603 mov r3, r0
800089c: 2b00 cmp r3, #0
800089e: d001 beq.n 80008a4 <MX_TIM4_Init+0xb0>
{
Error_Handler();
80008a0: f000 f8a2 bl 80009e8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80008a4: 2360 movs r3, #96 @ 0x60
80008a6: 607b str r3, [r7, #4]
sConfigOC.Pulse = 5000;
80008a8: f241 3388 movw r3, #5000 @ 0x1388
80008ac: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80008ae: 2300 movs r3, #0
80008b0: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
80008b2: 2304 movs r3, #4
80008b4: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80008b6: 1d3b adds r3, r7, #4
80008b8: 2200 movs r2, #0
80008ba: 4619 mov r1, r3
80008bc: 481c ldr r0, [pc, #112] @ (8000930 <MX_TIM4_Init+0x13c>)
80008be: f003 fb21 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80008c2: 4603 mov r3, r0
80008c4: 2b00 cmp r3, #0
80008c6: d001 beq.n 80008cc <MX_TIM4_Init+0xd8>
{
Error_Handler();
80008c8: f000 f88e bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 6000;
80008cc: f241 7370 movw r3, #6000 @ 0x1770
80008d0: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80008d2: 1d3b adds r3, r7, #4
80008d4: 2204 movs r2, #4
80008d6: 4619 mov r1, r3
80008d8: 4815 ldr r0, [pc, #84] @ (8000930 <MX_TIM4_Init+0x13c>)
80008da: f003 fb13 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80008de: 4603 mov r3, r0
80008e0: 2b00 cmp r3, #0
80008e2: d001 beq.n 80008e8 <MX_TIM4_Init+0xf4>
{
Error_Handler();
80008e4: f000 f880 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 7000;
80008e8: f641 3358 movw r3, #7000 @ 0x1b58
80008ec: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80008ee: 1d3b adds r3, r7, #4
80008f0: 2208 movs r2, #8
80008f2: 4619 mov r1, r3
80008f4: 480e ldr r0, [pc, #56] @ (8000930 <MX_TIM4_Init+0x13c>)
80008f6: f003 fb05 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
80008fa: 4603 mov r3, r0
80008fc: 2b00 cmp r3, #0
80008fe: d001 beq.n 8000904 <MX_TIM4_Init+0x110>
{
Error_Handler();
8000900: f000 f872 bl 80009e8 <Error_Handler>
}
sConfigOC.Pulse = 8000;
8000904: f44f 53fa mov.w r3, #8000 @ 0x1f40
8000908: 60bb str r3, [r7, #8]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
800090a: 1d3b adds r3, r7, #4
800090c: 220c movs r2, #12
800090e: 4619 mov r1, r3
8000910: 4807 ldr r0, [pc, #28] @ (8000930 <MX_TIM4_Init+0x13c>)
8000912: f003 faf7 bl 8003f04 <HAL_TIM_PWM_ConfigChannel>
8000916: 4603 mov r3, r0
8000918: 2b00 cmp r3, #0
800091a: d001 beq.n 8000920 <MX_TIM4_Init+0x12c>
{
Error_Handler();
800091c: f000 f864 bl 80009e8 <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
8000920: 4803 ldr r0, [pc, #12] @ (8000930 <MX_TIM4_Init+0x13c>)
8000922: f000 f92d bl 8000b80 <HAL_TIM_MspPostInit>
}
8000926: bf00 nop
8000928: 3738 adds r7, #56 @ 0x38
800092a: 46bd mov sp, r7
800092c: bd80 pop {r7, pc}
800092e: bf00 nop
8000930: 200002f0 .word 0x200002f0
8000934: 40000800 .word 0x40000800
08000938 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000938: b580 push {r7, lr}
800093a: b088 sub sp, #32
800093c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800093e: f107 0310 add.w r3, r7, #16
8000942: 2200 movs r2, #0
8000944: 601a str r2, [r3, #0]
8000946: 605a str r2, [r3, #4]
8000948: 609a str r2, [r3, #8]
800094a: 60da str r2, [r3, #12]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
800094c: 4b24 ldr r3, [pc, #144] @ (80009e0 <MX_GPIO_Init+0xa8>)
800094e: 699b ldr r3, [r3, #24]
8000950: 4a23 ldr r2, [pc, #140] @ (80009e0 <MX_GPIO_Init+0xa8>)
8000952: f043 0310 orr.w r3, r3, #16
8000956: 6193 str r3, [r2, #24]
8000958: 4b21 ldr r3, [pc, #132] @ (80009e0 <MX_GPIO_Init+0xa8>)
800095a: 699b ldr r3, [r3, #24]
800095c: f003 0310 and.w r3, r3, #16
8000960: 60fb str r3, [r7, #12]
8000962: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000964: 4b1e ldr r3, [pc, #120] @ (80009e0 <MX_GPIO_Init+0xa8>)
8000966: 699b ldr r3, [r3, #24]
8000968: 4a1d ldr r2, [pc, #116] @ (80009e0 <MX_GPIO_Init+0xa8>)
800096a: f043 0320 orr.w r3, r3, #32
800096e: 6193 str r3, [r2, #24]
8000970: 4b1b ldr r3, [pc, #108] @ (80009e0 <MX_GPIO_Init+0xa8>)
8000972: 699b ldr r3, [r3, #24]
8000974: f003 0320 and.w r3, r3, #32
8000978: 60bb str r3, [r7, #8]
800097a: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800097c: 4b18 ldr r3, [pc, #96] @ (80009e0 <MX_GPIO_Init+0xa8>)
800097e: 699b ldr r3, [r3, #24]
8000980: 4a17 ldr r2, [pc, #92] @ (80009e0 <MX_GPIO_Init+0xa8>)
8000982: f043 0304 orr.w r3, r3, #4
8000986: 6193 str r3, [r2, #24]
8000988: 4b15 ldr r3, [pc, #84] @ (80009e0 <MX_GPIO_Init+0xa8>)
800098a: 699b ldr r3, [r3, #24]
800098c: f003 0304 and.w r3, r3, #4
8000990: 607b str r3, [r7, #4]
8000992: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000994: 4b12 ldr r3, [pc, #72] @ (80009e0 <MX_GPIO_Init+0xa8>)
8000996: 699b ldr r3, [r3, #24]
8000998: 4a11 ldr r2, [pc, #68] @ (80009e0 <MX_GPIO_Init+0xa8>)
800099a: f043 0308 orr.w r3, r3, #8
800099e: 6193 str r3, [r2, #24]
80009a0: 4b0f ldr r3, [pc, #60] @ (80009e0 <MX_GPIO_Init+0xa8>)
80009a2: 699b ldr r3, [r3, #24]
80009a4: f003 0308 and.w r3, r3, #8
80009a8: 603b str r3, [r7, #0]
80009aa: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
80009ac: 2200 movs r2, #0
80009ae: f44f 5100 mov.w r1, #8192 @ 0x2000
80009b2: 480c ldr r0, [pc, #48] @ (80009e4 <MX_GPIO_Init+0xac>)
80009b4: f000 ff36 bl 8001824 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PC13 */
GPIO_InitStruct.Pin = GPIO_PIN_13;
80009b8: f44f 5300 mov.w r3, #8192 @ 0x2000
80009bc: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80009be: 2301 movs r3, #1
80009c0: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009c2: 2300 movs r3, #0
80009c4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80009c6: 2302 movs r3, #2
80009c8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80009ca: f107 0310 add.w r3, r7, #16
80009ce: 4619 mov r1, r3
80009d0: 4804 ldr r0, [pc, #16] @ (80009e4 <MX_GPIO_Init+0xac>)
80009d2: f000 fda3 bl 800151c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80009d6: bf00 nop
80009d8: 3720 adds r7, #32
80009da: 46bd mov sp, r7
80009dc: bd80 pop {r7, pc}
80009de: bf00 nop
80009e0: 40021000 .word 0x40021000
80009e4: 40011000 .word 0x40011000
080009e8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80009e8: b480 push {r7}
80009ea: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80009ec: b672 cpsid i
}
80009ee: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80009f0: bf00 nop
80009f2: e7fd b.n 80009f0 <Error_Handler+0x8>
080009f4 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80009f4: b480 push {r7}
80009f6: b085 sub sp, #20
80009f8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
80009fa: 4b15 ldr r3, [pc, #84] @ (8000a50 <HAL_MspInit+0x5c>)
80009fc: 699b ldr r3, [r3, #24]
80009fe: 4a14 ldr r2, [pc, #80] @ (8000a50 <HAL_MspInit+0x5c>)
8000a00: f043 0301 orr.w r3, r3, #1
8000a04: 6193 str r3, [r2, #24]
8000a06: 4b12 ldr r3, [pc, #72] @ (8000a50 <HAL_MspInit+0x5c>)
8000a08: 699b ldr r3, [r3, #24]
8000a0a: f003 0301 and.w r3, r3, #1
8000a0e: 60bb str r3, [r7, #8]
8000a10: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8000a12: 4b0f ldr r3, [pc, #60] @ (8000a50 <HAL_MspInit+0x5c>)
8000a14: 69db ldr r3, [r3, #28]
8000a16: 4a0e ldr r2, [pc, #56] @ (8000a50 <HAL_MspInit+0x5c>)
8000a18: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000a1c: 61d3 str r3, [r2, #28]
8000a1e: 4b0c ldr r3, [pc, #48] @ (8000a50 <HAL_MspInit+0x5c>)
8000a20: 69db ldr r3, [r3, #28]
8000a22: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000a26: 607b str r3, [r7, #4]
8000a28: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** DISABLE: JTAG-DP Disabled and SW-DP Disabled
*/
__HAL_AFIO_REMAP_SWJ_DISABLE();
8000a2a: 4b0a ldr r3, [pc, #40] @ (8000a54 <HAL_MspInit+0x60>)
8000a2c: 685b ldr r3, [r3, #4]
8000a2e: 60fb str r3, [r7, #12]
8000a30: 68fb ldr r3, [r7, #12]
8000a32: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
8000a36: 60fb str r3, [r7, #12]
8000a38: 68fb ldr r3, [r7, #12]
8000a3a: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8000a3e: 60fb str r3, [r7, #12]
8000a40: 4a04 ldr r2, [pc, #16] @ (8000a54 <HAL_MspInit+0x60>)
8000a42: 68fb ldr r3, [r7, #12]
8000a44: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000a46: bf00 nop
8000a48: 3714 adds r7, #20
8000a4a: 46bd mov sp, r7
8000a4c: bc80 pop {r7}
8000a4e: 4770 bx lr
8000a50: 40021000 .word 0x40021000
8000a54: 40010000 .word 0x40010000
08000a58 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8000a58: b580 push {r7, lr}
8000a5a: b088 sub sp, #32
8000a5c: af00 add r7, sp, #0
8000a5e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000a60: f107 0310 add.w r3, r7, #16
8000a64: 2200 movs r2, #0
8000a66: 601a str r2, [r3, #0]
8000a68: 605a str r2, [r3, #4]
8000a6a: 609a str r2, [r3, #8]
8000a6c: 60da str r2, [r3, #12]
if(hadc->Instance==ADC1)
8000a6e: 687b ldr r3, [r7, #4]
8000a70: 681b ldr r3, [r3, #0]
8000a72: 4a14 ldr r2, [pc, #80] @ (8000ac4 <HAL_ADC_MspInit+0x6c>)
8000a74: 4293 cmp r3, r2
8000a76: d121 bne.n 8000abc <HAL_ADC_MspInit+0x64>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8000a78: 4b13 ldr r3, [pc, #76] @ (8000ac8 <HAL_ADC_MspInit+0x70>)
8000a7a: 699b ldr r3, [r3, #24]
8000a7c: 4a12 ldr r2, [pc, #72] @ (8000ac8 <HAL_ADC_MspInit+0x70>)
8000a7e: f443 7300 orr.w r3, r3, #512 @ 0x200
8000a82: 6193 str r3, [r2, #24]
8000a84: 4b10 ldr r3, [pc, #64] @ (8000ac8 <HAL_ADC_MspInit+0x70>)
8000a86: 699b ldr r3, [r3, #24]
8000a88: f403 7300 and.w r3, r3, #512 @ 0x200
8000a8c: 60fb str r3, [r7, #12]
8000a8e: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000a90: 4b0d ldr r3, [pc, #52] @ (8000ac8 <HAL_ADC_MspInit+0x70>)
8000a92: 699b ldr r3, [r3, #24]
8000a94: 4a0c ldr r2, [pc, #48] @ (8000ac8 <HAL_ADC_MspInit+0x70>)
8000a96: f043 0304 orr.w r3, r3, #4
8000a9a: 6193 str r3, [r2, #24]
8000a9c: 4b0a ldr r3, [pc, #40] @ (8000ac8 <HAL_ADC_MspInit+0x70>)
8000a9e: 699b ldr r3, [r3, #24]
8000aa0: f003 0304 and.w r3, r3, #4
8000aa4: 60bb str r3, [r7, #8]
8000aa6: 68bb ldr r3, [r7, #8]
/**ADC1 GPIO Configuration
PA4 ------> ADC1_IN4
PA5 ------> ADC1_IN5
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
8000aa8: 2330 movs r3, #48 @ 0x30
8000aaa: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000aac: 2303 movs r3, #3
8000aae: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ab0: f107 0310 add.w r3, r7, #16
8000ab4: 4619 mov r1, r3
8000ab6: 4805 ldr r0, [pc, #20] @ (8000acc <HAL_ADC_MspInit+0x74>)
8000ab8: f000 fd30 bl 800151c <HAL_GPIO_Init>
/* USER CODE END ADC1_MspInit 1 */
}
}
8000abc: bf00 nop
8000abe: 3720 adds r7, #32
8000ac0: 46bd mov sp, r7
8000ac2: bd80 pop {r7, pc}
8000ac4: 40012400 .word 0x40012400
8000ac8: 40021000 .word 0x40021000
8000acc: 40010800 .word 0x40010800
08000ad0 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000ad0: b480 push {r7}
8000ad2: b087 sub sp, #28
8000ad4: af00 add r7, sp, #0
8000ad6: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8000ad8: 687b ldr r3, [r7, #4]
8000ada: 681b ldr r3, [r3, #0]
8000adc: 4a24 ldr r2, [pc, #144] @ (8000b70 <HAL_TIM_Base_MspInit+0xa0>)
8000ade: 4293 cmp r3, r2
8000ae0: d10c bne.n 8000afc <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8000ae2: 4b24 ldr r3, [pc, #144] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000ae4: 699b ldr r3, [r3, #24]
8000ae6: 4a23 ldr r2, [pc, #140] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000ae8: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000aec: 6193 str r3, [r2, #24]
8000aee: 4b21 ldr r3, [pc, #132] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000af0: 699b ldr r3, [r3, #24]
8000af2: f403 6300 and.w r3, r3, #2048 @ 0x800
8000af6: 617b str r3, [r7, #20]
8000af8: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
8000afa: e034 b.n 8000b66 <HAL_TIM_Base_MspInit+0x96>
else if(htim_base->Instance==TIM2)
8000afc: 687b ldr r3, [r7, #4]
8000afe: 681b ldr r3, [r3, #0]
8000b00: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000b04: d10c bne.n 8000b20 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM2_CLK_ENABLE();
8000b06: 4b1b ldr r3, [pc, #108] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b08: 69db ldr r3, [r3, #28]
8000b0a: 4a1a ldr r2, [pc, #104] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b0c: f043 0301 orr.w r3, r3, #1
8000b10: 61d3 str r3, [r2, #28]
8000b12: 4b18 ldr r3, [pc, #96] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b14: 69db ldr r3, [r3, #28]
8000b16: f003 0301 and.w r3, r3, #1
8000b1a: 613b str r3, [r7, #16]
8000b1c: 693b ldr r3, [r7, #16]
}
8000b1e: e022 b.n 8000b66 <HAL_TIM_Base_MspInit+0x96>
else if(htim_base->Instance==TIM3)
8000b20: 687b ldr r3, [r7, #4]
8000b22: 681b ldr r3, [r3, #0]
8000b24: 4a14 ldr r2, [pc, #80] @ (8000b78 <HAL_TIM_Base_MspInit+0xa8>)
8000b26: 4293 cmp r3, r2
8000b28: d10c bne.n 8000b44 <HAL_TIM_Base_MspInit+0x74>
__HAL_RCC_TIM3_CLK_ENABLE();
8000b2a: 4b12 ldr r3, [pc, #72] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b2c: 69db ldr r3, [r3, #28]
8000b2e: 4a11 ldr r2, [pc, #68] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b30: f043 0302 orr.w r3, r3, #2
8000b34: 61d3 str r3, [r2, #28]
8000b36: 4b0f ldr r3, [pc, #60] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b38: 69db ldr r3, [r3, #28]
8000b3a: f003 0302 and.w r3, r3, #2
8000b3e: 60fb str r3, [r7, #12]
8000b40: 68fb ldr r3, [r7, #12]
}
8000b42: e010 b.n 8000b66 <HAL_TIM_Base_MspInit+0x96>
else if(htim_base->Instance==TIM4)
8000b44: 687b ldr r3, [r7, #4]
8000b46: 681b ldr r3, [r3, #0]
8000b48: 4a0c ldr r2, [pc, #48] @ (8000b7c <HAL_TIM_Base_MspInit+0xac>)
8000b4a: 4293 cmp r3, r2
8000b4c: d10b bne.n 8000b66 <HAL_TIM_Base_MspInit+0x96>
__HAL_RCC_TIM4_CLK_ENABLE();
8000b4e: 4b09 ldr r3, [pc, #36] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b50: 69db ldr r3, [r3, #28]
8000b52: 4a08 ldr r2, [pc, #32] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b54: f043 0304 orr.w r3, r3, #4
8000b58: 61d3 str r3, [r2, #28]
8000b5a: 4b06 ldr r3, [pc, #24] @ (8000b74 <HAL_TIM_Base_MspInit+0xa4>)
8000b5c: 69db ldr r3, [r3, #28]
8000b5e: f003 0304 and.w r3, r3, #4
8000b62: 60bb str r3, [r7, #8]
8000b64: 68bb ldr r3, [r7, #8]
}
8000b66: bf00 nop
8000b68: 371c adds r7, #28
8000b6a: 46bd mov sp, r7
8000b6c: bc80 pop {r7}
8000b6e: 4770 bx lr
8000b70: 40012c00 .word 0x40012c00
8000b74: 40021000 .word 0x40021000
8000b78: 40000400 .word 0x40000400
8000b7c: 40000800 .word 0x40000800
08000b80 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000b80: b580 push {r7, lr}
8000b82: b08c sub sp, #48 @ 0x30
8000b84: af00 add r7, sp, #0
8000b86: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000b88: f107 0320 add.w r3, r7, #32
8000b8c: 2200 movs r2, #0
8000b8e: 601a str r2, [r3, #0]
8000b90: 605a str r2, [r3, #4]
8000b92: 609a str r2, [r3, #8]
8000b94: 60da str r2, [r3, #12]
if(htim->Instance==TIM1)
8000b96: 687b ldr r3, [r7, #4]
8000b98: 681b ldr r3, [r3, #0]
8000b9a: 4a49 ldr r2, [pc, #292] @ (8000cc0 <HAL_TIM_MspPostInit+0x140>)
8000b9c: 4293 cmp r3, r2
8000b9e: d119 bne.n 8000bd4 <HAL_TIM_MspPostInit+0x54>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000ba0: 4b48 ldr r3, [pc, #288] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000ba2: 699b ldr r3, [r3, #24]
8000ba4: 4a47 ldr r2, [pc, #284] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000ba6: f043 0304 orr.w r3, r3, #4
8000baa: 6193 str r3, [r2, #24]
8000bac: 4b45 ldr r3, [pc, #276] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000bae: 699b ldr r3, [r3, #24]
8000bb0: f003 0304 and.w r3, r3, #4
8000bb4: 61fb str r3, [r7, #28]
8000bb6: 69fb ldr r3, [r7, #28]
/**TIM1 GPIO Configuration
PA8 ------> TIM1_CH1
PA9 ------> TIM1_CH2
PA10 ------> TIM1_CH3
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10;
8000bb8: f44f 63e0 mov.w r3, #1792 @ 0x700
8000bbc: 623b str r3, [r7, #32]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bbe: 2302 movs r3, #2
8000bc0: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bc2: 2302 movs r3, #2
8000bc4: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000bc6: f107 0320 add.w r3, r7, #32
8000bca: 4619 mov r1, r3
8000bcc: 483e ldr r0, [pc, #248] @ (8000cc8 <HAL_TIM_MspPostInit+0x148>)
8000bce: f000 fca5 bl 800151c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
8000bd2: e071 b.n 8000cb8 <HAL_TIM_MspPostInit+0x138>
else if(htim->Instance==TIM2)
8000bd4: 687b ldr r3, [r7, #4]
8000bd6: 681b ldr r3, [r3, #0]
8000bd8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000bdc: d118 bne.n 8000c10 <HAL_TIM_MspPostInit+0x90>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000bde: 4b39 ldr r3, [pc, #228] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000be0: 699b ldr r3, [r3, #24]
8000be2: 4a38 ldr r2, [pc, #224] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000be4: f043 0304 orr.w r3, r3, #4
8000be8: 6193 str r3, [r2, #24]
8000bea: 4b36 ldr r3, [pc, #216] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000bec: 699b ldr r3, [r3, #24]
8000bee: f003 0304 and.w r3, r3, #4
8000bf2: 61bb str r3, [r7, #24]
8000bf4: 69bb ldr r3, [r7, #24]
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
8000bf6: 230f movs r3, #15
8000bf8: 623b str r3, [r7, #32]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bfa: 2302 movs r3, #2
8000bfc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bfe: 2302 movs r3, #2
8000c00: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c02: f107 0320 add.w r3, r7, #32
8000c06: 4619 mov r1, r3
8000c08: 482f ldr r0, [pc, #188] @ (8000cc8 <HAL_TIM_MspPostInit+0x148>)
8000c0a: f000 fc87 bl 800151c <HAL_GPIO_Init>
}
8000c0e: e053 b.n 8000cb8 <HAL_TIM_MspPostInit+0x138>
else if(htim->Instance==TIM3)
8000c10: 687b ldr r3, [r7, #4]
8000c12: 681b ldr r3, [r3, #0]
8000c14: 4a2d ldr r2, [pc, #180] @ (8000ccc <HAL_TIM_MspPostInit+0x14c>)
8000c16: 4293 cmp r3, r2
8000c18: d130 bne.n 8000c7c <HAL_TIM_MspPostInit+0xfc>
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c1a: 4b2a ldr r3, [pc, #168] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c1c: 699b ldr r3, [r3, #24]
8000c1e: 4a29 ldr r2, [pc, #164] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c20: f043 0304 orr.w r3, r3, #4
8000c24: 6193 str r3, [r2, #24]
8000c26: 4b27 ldr r3, [pc, #156] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c28: 699b ldr r3, [r3, #24]
8000c2a: f003 0304 and.w r3, r3, #4
8000c2e: 617b str r3, [r7, #20]
8000c30: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000c32: 4b24 ldr r3, [pc, #144] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c34: 699b ldr r3, [r3, #24]
8000c36: 4a23 ldr r2, [pc, #140] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c38: f043 0308 orr.w r3, r3, #8
8000c3c: 6193 str r3, [r2, #24]
8000c3e: 4b21 ldr r3, [pc, #132] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c40: 699b ldr r3, [r3, #24]
8000c42: f003 0308 and.w r3, r3, #8
8000c46: 613b str r3, [r7, #16]
8000c48: 693b ldr r3, [r7, #16]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8000c4a: 23c0 movs r3, #192 @ 0xc0
8000c4c: 623b str r3, [r7, #32]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c4e: 2302 movs r3, #2
8000c50: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c52: 2302 movs r3, #2
8000c54: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c56: f107 0320 add.w r3, r7, #32
8000c5a: 4619 mov r1, r3
8000c5c: 481a ldr r0, [pc, #104] @ (8000cc8 <HAL_TIM_MspPostInit+0x148>)
8000c5e: f000 fc5d bl 800151c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
8000c62: 2303 movs r3, #3
8000c64: 623b str r3, [r7, #32]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c66: 2302 movs r3, #2
8000c68: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c6a: 2302 movs r3, #2
8000c6c: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000c6e: f107 0320 add.w r3, r7, #32
8000c72: 4619 mov r1, r3
8000c74: 4816 ldr r0, [pc, #88] @ (8000cd0 <HAL_TIM_MspPostInit+0x150>)
8000c76: f000 fc51 bl 800151c <HAL_GPIO_Init>
}
8000c7a: e01d b.n 8000cb8 <HAL_TIM_MspPostInit+0x138>
else if(htim->Instance==TIM4)
8000c7c: 687b ldr r3, [r7, #4]
8000c7e: 681b ldr r3, [r3, #0]
8000c80: 4a14 ldr r2, [pc, #80] @ (8000cd4 <HAL_TIM_MspPostInit+0x154>)
8000c82: 4293 cmp r3, r2
8000c84: d118 bne.n 8000cb8 <HAL_TIM_MspPostInit+0x138>
__HAL_RCC_GPIOB_CLK_ENABLE();
8000c86: 4b0f ldr r3, [pc, #60] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c88: 699b ldr r3, [r3, #24]
8000c8a: 4a0e ldr r2, [pc, #56] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c8c: f043 0308 orr.w r3, r3, #8
8000c90: 6193 str r3, [r2, #24]
8000c92: 4b0c ldr r3, [pc, #48] @ (8000cc4 <HAL_TIM_MspPostInit+0x144>)
8000c94: 699b ldr r3, [r3, #24]
8000c96: f003 0308 and.w r3, r3, #8
8000c9a: 60fb str r3, [r7, #12]
8000c9c: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
8000c9e: f44f 7370 mov.w r3, #960 @ 0x3c0
8000ca2: 623b str r3, [r7, #32]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ca4: 2302 movs r3, #2
8000ca6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ca8: 2302 movs r3, #2
8000caa: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000cac: f107 0320 add.w r3, r7, #32
8000cb0: 4619 mov r1, r3
8000cb2: 4807 ldr r0, [pc, #28] @ (8000cd0 <HAL_TIM_MspPostInit+0x150>)
8000cb4: f000 fc32 bl 800151c <HAL_GPIO_Init>
}
8000cb8: bf00 nop
8000cba: 3730 adds r7, #48 @ 0x30
8000cbc: 46bd mov sp, r7
8000cbe: bd80 pop {r7, pc}
8000cc0: 40012c00 .word 0x40012c00
8000cc4: 40021000 .word 0x40021000
8000cc8: 40010800 .word 0x40010800
8000ccc: 40000400 .word 0x40000400
8000cd0: 40010c00 .word 0x40010c00
8000cd4: 40000800 .word 0x40000800
08000cd8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000cd8: b480 push {r7}
8000cda: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000cdc: bf00 nop
8000cde: e7fd b.n 8000cdc <NMI_Handler+0x4>
08000ce0 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000ce0: b480 push {r7}
8000ce2: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000ce4: bf00 nop
8000ce6: e7fd b.n 8000ce4 <HardFault_Handler+0x4>
08000ce8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000ce8: b480 push {r7}
8000cea: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000cec: bf00 nop
8000cee: e7fd b.n 8000cec <MemManage_Handler+0x4>
08000cf0 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000cf0: b480 push {r7}
8000cf2: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000cf4: bf00 nop
8000cf6: e7fd b.n 8000cf4 <BusFault_Handler+0x4>
08000cf8 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000cf8: b480 push {r7}
8000cfa: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000cfc: bf00 nop
8000cfe: e7fd b.n 8000cfc <UsageFault_Handler+0x4>
08000d00 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000d00: b480 push {r7}
8000d02: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000d04: bf00 nop
8000d06: 46bd mov sp, r7
8000d08: bc80 pop {r7}
8000d0a: 4770 bx lr
08000d0c <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000d0c: b480 push {r7}
8000d0e: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000d10: bf00 nop
8000d12: 46bd mov sp, r7
8000d14: bc80 pop {r7}
8000d16: 4770 bx lr
08000d18 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000d18: b480 push {r7}
8000d1a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000d1c: bf00 nop
8000d1e: 46bd mov sp, r7
8000d20: bc80 pop {r7}
8000d22: 4770 bx lr
08000d24 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000d24: b580 push {r7, lr}
8000d26: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000d28: f000 f8b6 bl 8000e98 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
HAL_SYSTICK_IRQHandler();
8000d2c: f000 fbef bl 800150e <HAL_SYSTICK_IRQHandler>
/* USER CODE END SysTick_IRQn 1 */
}
8000d30: bf00 nop
8000d32: bd80 pop {r7, pc}
08000d34 <USB_LP_CAN1_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN RX0 interrupts.
*/
void USB_LP_CAN1_RX0_IRQHandler(void)
{
8000d34: b580 push {r7, lr}
8000d36: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_FS);
8000d38: 4802 ldr r0, [pc, #8] @ (8000d44 <USB_LP_CAN1_RX0_IRQHandler+0x10>)
8000d3a: f000 fec0 bl 8001abe <HAL_PCD_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
}
8000d3e: bf00 nop
8000d40: bd80 pop {r7, pc}
8000d42: bf00 nop
8000d44: 20001110 .word 0x20001110
08000d48 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8000d48: b580 push {r7, lr}
8000d4a: b086 sub sp, #24
8000d4c: af00 add r7, sp, #0
8000d4e: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8000d50: 4a14 ldr r2, [pc, #80] @ (8000da4 <_sbrk+0x5c>)
8000d52: 4b15 ldr r3, [pc, #84] @ (8000da8 <_sbrk+0x60>)
8000d54: 1ad3 subs r3, r2, r3
8000d56: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8000d58: 697b ldr r3, [r7, #20]
8000d5a: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8000d5c: 4b13 ldr r3, [pc, #76] @ (8000dac <_sbrk+0x64>)
8000d5e: 681b ldr r3, [r3, #0]
8000d60: 2b00 cmp r3, #0
8000d62: d102 bne.n 8000d6a <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8000d64: 4b11 ldr r3, [pc, #68] @ (8000dac <_sbrk+0x64>)
8000d66: 4a12 ldr r2, [pc, #72] @ (8000db0 <_sbrk+0x68>)
8000d68: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8000d6a: 4b10 ldr r3, [pc, #64] @ (8000dac <_sbrk+0x64>)
8000d6c: 681a ldr r2, [r3, #0]
8000d6e: 687b ldr r3, [r7, #4]
8000d70: 4413 add r3, r2
8000d72: 693a ldr r2, [r7, #16]
8000d74: 429a cmp r2, r3
8000d76: d207 bcs.n 8000d88 <_sbrk+0x40>
{
errno = ENOMEM;
8000d78: f008 f9f4 bl 8009164 <__errno>
8000d7c: 4603 mov r3, r0
8000d7e: 220c movs r2, #12
8000d80: 601a str r2, [r3, #0]
return (void *)-1;
8000d82: f04f 33ff mov.w r3, #4294967295
8000d86: e009 b.n 8000d9c <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8000d88: 4b08 ldr r3, [pc, #32] @ (8000dac <_sbrk+0x64>)
8000d8a: 681b ldr r3, [r3, #0]
8000d8c: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8000d8e: 4b07 ldr r3, [pc, #28] @ (8000dac <_sbrk+0x64>)
8000d90: 681a ldr r2, [r3, #0]
8000d92: 687b ldr r3, [r7, #4]
8000d94: 4413 add r3, r2
8000d96: 4a05 ldr r2, [pc, #20] @ (8000dac <_sbrk+0x64>)
8000d98: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8000d9a: 68fb ldr r3, [r7, #12]
}
8000d9c: 4618 mov r0, r3
8000d9e: 3718 adds r7, #24
8000da0: 46bd mov sp, r7
8000da2: bd80 pop {r7, pc}
8000da4: 20005000 .word 0x20005000
8000da8: 00000400 .word 0x00000400
8000dac: 2000033c .word 0x2000033c
8000db0: 20001750 .word 0x20001750
08000db4 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8000db4: b480 push {r7}
8000db6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000db8: bf00 nop
8000dba: 46bd mov sp, r7
8000dbc: bc80 pop {r7}
8000dbe: 4770 bx lr
08000dc0 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8000dc0: f7ff fff8 bl 8000db4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000dc4: 480b ldr r0, [pc, #44] @ (8000df4 <LoopFillZerobss+0xe>)
ldr r1, =_edata
8000dc6: 490c ldr r1, [pc, #48] @ (8000df8 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8000dc8: 4a0c ldr r2, [pc, #48] @ (8000dfc <LoopFillZerobss+0x16>)
movs r3, #0
8000dca: 2300 movs r3, #0
b LoopCopyDataInit
8000dcc: e002 b.n 8000dd4 <LoopCopyDataInit>
08000dce <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000dce: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000dd0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000dd2: 3304 adds r3, #4
08000dd4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000dd4: 18c4 adds r4, r0, r3
cmp r4, r1
8000dd6: 428c cmp r4, r1
bcc CopyDataInit
8000dd8: d3f9 bcc.n 8000dce <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000dda: 4a09 ldr r2, [pc, #36] @ (8000e00 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8000ddc: 4c09 ldr r4, [pc, #36] @ (8000e04 <LoopFillZerobss+0x1e>)
movs r3, #0
8000dde: 2300 movs r3, #0
b LoopFillZerobss
8000de0: e001 b.n 8000de6 <LoopFillZerobss>
08000de2 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000de2: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000de4: 3204 adds r2, #4
08000de6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000de6: 42a2 cmp r2, r4
bcc FillZerobss
8000de8: d3fb bcc.n 8000de2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000dea: f008 f9c1 bl 8009170 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000dee: f7ff f9e5 bl 80001bc <main>
bx lr
8000df2: 4770 bx lr
ldr r0, =_sdata
8000df4: 20000000 .word 0x20000000
ldr r1, =_edata
8000df8: 200001cc .word 0x200001cc
ldr r2, =_sidata
8000dfc: 08009b40 .word 0x08009b40
ldr r2, =_sbss
8000e00: 200001cc .word 0x200001cc
ldr r4, =_ebss
8000e04: 20001750 .word 0x20001750
08000e08 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000e08: e7fe b.n 8000e08 <ADC1_2_IRQHandler>
...
08000e0c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000e0c: b580 push {r7, lr}
8000e0e: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000e10: 4b08 ldr r3, [pc, #32] @ (8000e34 <HAL_Init+0x28>)
8000e12: 681b ldr r3, [r3, #0]
8000e14: 4a07 ldr r2, [pc, #28] @ (8000e34 <HAL_Init+0x28>)
8000e16: f043 0310 orr.w r3, r3, #16
8000e1a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000e1c: 2003 movs r0, #3
8000e1e: f000 fb35 bl 800148c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000e22: 200f movs r0, #15
8000e24: f000 f808 bl 8000e38 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000e28: f7ff fde4 bl 80009f4 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000e2c: 2300 movs r3, #0
}
8000e2e: 4618 mov r0, r3
8000e30: bd80 pop {r7, pc}
8000e32: bf00 nop
8000e34: 40022000 .word 0x40022000
08000e38 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000e38: b580 push {r7, lr}
8000e3a: b082 sub sp, #8
8000e3c: af00 add r7, sp, #0
8000e3e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000e40: 4b12 ldr r3, [pc, #72] @ (8000e8c <HAL_InitTick+0x54>)
8000e42: 681a ldr r2, [r3, #0]
8000e44: 4b12 ldr r3, [pc, #72] @ (8000e90 <HAL_InitTick+0x58>)
8000e46: 781b ldrb r3, [r3, #0]
8000e48: 4619 mov r1, r3
8000e4a: f44f 737a mov.w r3, #1000 @ 0x3e8
8000e4e: fbb3 f3f1 udiv r3, r3, r1
8000e52: fbb2 f3f3 udiv r3, r2, r3
8000e56: 4618 mov r0, r3
8000e58: f000 fb4d bl 80014f6 <HAL_SYSTICK_Config>
8000e5c: 4603 mov r3, r0
8000e5e: 2b00 cmp r3, #0
8000e60: d001 beq.n 8000e66 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000e62: 2301 movs r3, #1
8000e64: e00e b.n 8000e84 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000e66: 687b ldr r3, [r7, #4]
8000e68: 2b0f cmp r3, #15
8000e6a: d80a bhi.n 8000e82 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000e6c: 2200 movs r2, #0
8000e6e: 6879 ldr r1, [r7, #4]
8000e70: f04f 30ff mov.w r0, #4294967295
8000e74: f000 fb15 bl 80014a2 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000e78: 4a06 ldr r2, [pc, #24] @ (8000e94 <HAL_InitTick+0x5c>)
8000e7a: 687b ldr r3, [r7, #4]
8000e7c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000e7e: 2300 movs r3, #0
8000e80: e000 b.n 8000e84 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000e82: 2301 movs r3, #1
}
8000e84: 4618 mov r0, r3
8000e86: 3708 adds r7, #8
8000e88: 46bd mov sp, r7
8000e8a: bd80 pop {r7, pc}
8000e8c: 20000000 .word 0x20000000
8000e90: 20000008 .word 0x20000008
8000e94: 20000004 .word 0x20000004
08000e98 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000e98: b480 push {r7}
8000e9a: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000e9c: 4b05 ldr r3, [pc, #20] @ (8000eb4 <HAL_IncTick+0x1c>)
8000e9e: 781b ldrb r3, [r3, #0]
8000ea0: 461a mov r2, r3
8000ea2: 4b05 ldr r3, [pc, #20] @ (8000eb8 <HAL_IncTick+0x20>)
8000ea4: 681b ldr r3, [r3, #0]
8000ea6: 4413 add r3, r2
8000ea8: 4a03 ldr r2, [pc, #12] @ (8000eb8 <HAL_IncTick+0x20>)
8000eaa: 6013 str r3, [r2, #0]
}
8000eac: bf00 nop
8000eae: 46bd mov sp, r7
8000eb0: bc80 pop {r7}
8000eb2: 4770 bx lr
8000eb4: 20000008 .word 0x20000008
8000eb8: 20000340 .word 0x20000340
08000ebc <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000ebc: b480 push {r7}
8000ebe: af00 add r7, sp, #0
return uwTick;
8000ec0: 4b02 ldr r3, [pc, #8] @ (8000ecc <HAL_GetTick+0x10>)
8000ec2: 681b ldr r3, [r3, #0]
}
8000ec4: 4618 mov r0, r3
8000ec6: 46bd mov sp, r7
8000ec8: bc80 pop {r7}
8000eca: 4770 bx lr
8000ecc: 20000340 .word 0x20000340
08000ed0 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8000ed0: b580 push {r7, lr}
8000ed2: b086 sub sp, #24
8000ed4: af00 add r7, sp, #0
8000ed6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000ed8: 2300 movs r3, #0
8000eda: 75fb strb r3, [r7, #23]
uint32_t tmp_cr1 = 0U;
8000edc: 2300 movs r3, #0
8000ede: 613b str r3, [r7, #16]
uint32_t tmp_cr2 = 0U;
8000ee0: 2300 movs r3, #0
8000ee2: 60bb str r3, [r7, #8]
uint32_t tmp_sqr1 = 0U;
8000ee4: 2300 movs r3, #0
8000ee6: 60fb str r3, [r7, #12]
/* Check ADC handle */
if(hadc == NULL)
8000ee8: 687b ldr r3, [r7, #4]
8000eea: 2b00 cmp r3, #0
8000eec: d101 bne.n 8000ef2 <HAL_ADC_Init+0x22>
{
return HAL_ERROR;
8000eee: 2301 movs r3, #1
8000ef0: e0be b.n 8001070 <HAL_ADC_Init+0x1a0>
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8000ef2: 687b ldr r3, [r7, #4]
8000ef4: 689b ldr r3, [r3, #8]
8000ef6: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8000ef8: 687b ldr r3, [r7, #4]
8000efa: 6a9b ldr r3, [r3, #40] @ 0x28
8000efc: 2b00 cmp r3, #0
8000efe: d109 bne.n 8000f14 <HAL_ADC_Init+0x44>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8000f00: 687b ldr r3, [r7, #4]
8000f02: 2200 movs r2, #0
8000f04: 62da str r2, [r3, #44] @ 0x2c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8000f06: 687b ldr r3, [r7, #4]
8000f08: 2200 movs r2, #0
8000f0a: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8000f0e: 6878 ldr r0, [r7, #4]
8000f10: f7ff fda2 bl 8000a58 <HAL_ADC_MspInit>
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
/* Note: In case of ADC already enabled, precaution to not launch an */
/* unwanted conversion while modifying register CR2 by writing 1 to */
/* bit ADON. */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8000f14: 6878 ldr r0, [r7, #4]
8000f16: f000 f9ab bl 8001270 <ADC_ConversionStop_Disable>
8000f1a: 4603 mov r3, r0
8000f1c: 75fb strb r3, [r7, #23]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8000f1e: 687b ldr r3, [r7, #4]
8000f20: 6a9b ldr r3, [r3, #40] @ 0x28
8000f22: f003 0310 and.w r3, r3, #16
8000f26: 2b00 cmp r3, #0
8000f28: f040 8099 bne.w 800105e <HAL_ADC_Init+0x18e>
8000f2c: 7dfb ldrb r3, [r7, #23]
8000f2e: 2b00 cmp r3, #0
8000f30: f040 8095 bne.w 800105e <HAL_ADC_Init+0x18e>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000f34: 687b ldr r3, [r7, #4]
8000f36: 6a9b ldr r3, [r3, #40] @ 0x28
8000f38: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8000f3c: f023 0302 bic.w r3, r3, #2
8000f40: f043 0202 orr.w r2, r3, #2
8000f44: 687b ldr r3, [r7, #4]
8000f46: 629a str r2, [r3, #40] @ 0x28
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
/* HAL_ADC_Start_xxx functions because if set in this function, */
/* a conversion on injected group would start a conversion also on */
/* regular group after ADC enabling. */
tmp_cr2 |= (hadc->Init.DataAlign |
8000f48: 687b ldr r3, [r7, #4]
8000f4a: 685a ldr r2, [r3, #4]
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8000f4c: 687b ldr r3, [r7, #4]
8000f4e: 69db ldr r3, [r3, #28]
tmp_cr2 |= (hadc->Init.DataAlign |
8000f50: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8000f52: 687b ldr r3, [r7, #4]
8000f54: 7b1b ldrb r3, [r3, #12]
8000f56: 005b lsls r3, r3, #1
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
8000f58: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
8000f5a: 68ba ldr r2, [r7, #8]
8000f5c: 4313 orrs r3, r2
8000f5e: 60bb str r3, [r7, #8]
/* Configuration of ADC: */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
8000f60: 687b ldr r3, [r7, #4]
8000f62: 689b ldr r3, [r3, #8]
8000f64: f5b3 7f80 cmp.w r3, #256 @ 0x100
8000f68: d003 beq.n 8000f72 <HAL_ADC_Init+0xa2>
8000f6a: 687b ldr r3, [r7, #4]
8000f6c: 689b ldr r3, [r3, #8]
8000f6e: 2b01 cmp r3, #1
8000f70: d102 bne.n 8000f78 <HAL_ADC_Init+0xa8>
8000f72: f44f 7380 mov.w r3, #256 @ 0x100
8000f76: e000 b.n 8000f7a <HAL_ADC_Init+0xaa>
8000f78: 2300 movs r3, #0
8000f7a: 693a ldr r2, [r7, #16]
8000f7c: 4313 orrs r3, r2
8000f7e: 613b str r3, [r7, #16]
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but will have no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8000f80: 687b ldr r3, [r7, #4]
8000f82: 7d1b ldrb r3, [r3, #20]
8000f84: 2b01 cmp r3, #1
8000f86: d119 bne.n 8000fbc <HAL_ADC_Init+0xec>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8000f88: 687b ldr r3, [r7, #4]
8000f8a: 7b1b ldrb r3, [r3, #12]
8000f8c: 2b00 cmp r3, #0
8000f8e: d109 bne.n 8000fa4 <HAL_ADC_Init+0xd4>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8000f90: 687b ldr r3, [r7, #4]
8000f92: 699b ldr r3, [r3, #24]
8000f94: 3b01 subs r3, #1
8000f96: 035a lsls r2, r3, #13
8000f98: 693b ldr r3, [r7, #16]
8000f9a: 4313 orrs r3, r2
8000f9c: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000fa0: 613b str r3, [r7, #16]
8000fa2: e00b b.n 8000fbc <HAL_ADC_Init+0xec>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000fa4: 687b ldr r3, [r7, #4]
8000fa6: 6a9b ldr r3, [r3, #40] @ 0x28
8000fa8: f043 0220 orr.w r2, r3, #32
8000fac: 687b ldr r3, [r7, #4]
8000fae: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000fb0: 687b ldr r3, [r7, #4]
8000fb2: 6adb ldr r3, [r3, #44] @ 0x2c
8000fb4: f043 0201 orr.w r2, r3, #1
8000fb8: 687b ldr r3, [r7, #4]
8000fba: 62da str r2, [r3, #44] @ 0x2c
}
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
8000fbc: 687b ldr r3, [r7, #4]
8000fbe: 681b ldr r3, [r3, #0]
8000fc0: 685b ldr r3, [r3, #4]
8000fc2: f423 4169 bic.w r1, r3, #59648 @ 0xe900
8000fc6: 687b ldr r3, [r7, #4]
8000fc8: 681b ldr r3, [r3, #0]
8000fca: 693a ldr r2, [r7, #16]
8000fcc: 430a orrs r2, r1
8000fce: 605a str r2, [r3, #4]
ADC_CR1_DISCEN |
ADC_CR1_DISCNUM ,
tmp_cr1 );
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2,
8000fd0: 687b ldr r3, [r7, #4]
8000fd2: 681b ldr r3, [r3, #0]
8000fd4: 689a ldr r2, [r3, #8]
8000fd6: 4b28 ldr r3, [pc, #160] @ (8001078 <HAL_ADC_Init+0x1a8>)
8000fd8: 4013 ands r3, r2
8000fda: 687a ldr r2, [r7, #4]
8000fdc: 6812 ldr r2, [r2, #0]
8000fde: 68b9 ldr r1, [r7, #8]
8000fe0: 430b orrs r3, r1
8000fe2: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
8000fe4: 687b ldr r3, [r7, #4]
8000fe6: 689b ldr r3, [r3, #8]
8000fe8: f5b3 7f80 cmp.w r3, #256 @ 0x100
8000fec: d003 beq.n 8000ff6 <HAL_ADC_Init+0x126>
8000fee: 687b ldr r3, [r7, #4]
8000ff0: 689b ldr r3, [r3, #8]
8000ff2: 2b01 cmp r3, #1
8000ff4: d104 bne.n 8001000 <HAL_ADC_Init+0x130>
{
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
8000ff6: 687b ldr r3, [r7, #4]
8000ff8: 691b ldr r3, [r3, #16]
8000ffa: 3b01 subs r3, #1
8000ffc: 051b lsls r3, r3, #20
8000ffe: 60fb str r3, [r7, #12]
}
MODIFY_REG(hadc->Instance->SQR1,
8001000: 687b ldr r3, [r7, #4]
8001002: 681b ldr r3, [r3, #0]
8001004: 6adb ldr r3, [r3, #44] @ 0x2c
8001006: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
800100a: 687b ldr r3, [r7, #4]
800100c: 681b ldr r3, [r3, #0]
800100e: 68fa ldr r2, [r7, #12]
8001010: 430a orrs r2, r1
8001012: 62da str r2, [r3, #44] @ 0x2c
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding bits set in other functions: */
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
/* measurement path bit (TSVREFE). */
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
8001014: 687b ldr r3, [r7, #4]
8001016: 681b ldr r3, [r3, #0]
8001018: 689a ldr r2, [r3, #8]
800101a: 4b18 ldr r3, [pc, #96] @ (800107c <HAL_ADC_Init+0x1ac>)
800101c: 4013 ands r3, r2
800101e: 68ba ldr r2, [r7, #8]
8001020: 429a cmp r2, r3
8001022: d10b bne.n 800103c <HAL_ADC_Init+0x16c>
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
ADC_CR2_TSVREFE ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001024: 687b ldr r3, [r7, #4]
8001026: 2200 movs r2, #0
8001028: 62da str r2, [r3, #44] @ 0x2c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800102a: 687b ldr r3, [r7, #4]
800102c: 6a9b ldr r3, [r3, #40] @ 0x28
800102e: f023 0303 bic.w r3, r3, #3
8001032: f043 0201 orr.w r2, r3, #1
8001036: 687b ldr r3, [r7, #4]
8001038: 629a str r2, [r3, #40] @ 0x28
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800103a: e018 b.n 800106e <HAL_ADC_Init+0x19e>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
800103c: 687b ldr r3, [r7, #4]
800103e: 6a9b ldr r3, [r3, #40] @ 0x28
8001040: f023 0312 bic.w r3, r3, #18
8001044: f043 0210 orr.w r2, r3, #16
8001048: 687b ldr r3, [r7, #4]
800104a: 629a str r2, [r3, #40] @ 0x28
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800104c: 687b ldr r3, [r7, #4]
800104e: 6adb ldr r3, [r3, #44] @ 0x2c
8001050: f043 0201 orr.w r2, r3, #1
8001054: 687b ldr r3, [r7, #4]
8001056: 62da str r2, [r3, #44] @ 0x2c
tmp_hal_status = HAL_ERROR;
8001058: 2301 movs r3, #1
800105a: 75fb strb r3, [r7, #23]
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
800105c: e007 b.n 800106e <HAL_ADC_Init+0x19e>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800105e: 687b ldr r3, [r7, #4]
8001060: 6a9b ldr r3, [r3, #40] @ 0x28
8001062: f043 0210 orr.w r2, r3, #16
8001066: 687b ldr r3, [r7, #4]
8001068: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
800106a: 2301 movs r3, #1
800106c: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800106e: 7dfb ldrb r3, [r7, #23]
}
8001070: 4618 mov r0, r3
8001072: 3718 adds r7, #24
8001074: 46bd mov sp, r7
8001076: bd80 pop {r7, pc}
8001078: ffe1f7fd .word 0xffe1f7fd
800107c: ff1f0efe .word 0xff1f0efe
08001080 <HAL_ADC_ConfigChannel>:
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8001080: b480 push {r7}
8001082: b085 sub sp, #20
8001084: af00 add r7, sp, #0
8001086: 6078 str r0, [r7, #4]
8001088: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800108a: 2300 movs r3, #0
800108c: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0U;
800108e: 2300 movs r3, #0
8001090: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8001092: 687b ldr r3, [r7, #4]
8001094: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8001098: 2b01 cmp r3, #1
800109a: d101 bne.n 80010a0 <HAL_ADC_ConfigChannel+0x20>
800109c: 2302 movs r3, #2
800109e: e0dc b.n 800125a <HAL_ADC_ConfigChannel+0x1da>
80010a0: 687b ldr r3, [r7, #4]
80010a2: 2201 movs r2, #1
80010a4: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
80010a8: 683b ldr r3, [r7, #0]
80010aa: 685b ldr r3, [r3, #4]
80010ac: 2b06 cmp r3, #6
80010ae: d81c bhi.n 80010ea <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR3 ,
80010b0: 687b ldr r3, [r7, #4]
80010b2: 681b ldr r3, [r3, #0]
80010b4: 6b59 ldr r1, [r3, #52] @ 0x34
80010b6: 683b ldr r3, [r7, #0]
80010b8: 685a ldr r2, [r3, #4]
80010ba: 4613 mov r3, r2
80010bc: 009b lsls r3, r3, #2
80010be: 4413 add r3, r2
80010c0: 3b05 subs r3, #5
80010c2: 221f movs r2, #31
80010c4: fa02 f303 lsl.w r3, r2, r3
80010c8: 43db mvns r3, r3
80010ca: 4019 ands r1, r3
80010cc: 683b ldr r3, [r7, #0]
80010ce: 6818 ldr r0, [r3, #0]
80010d0: 683b ldr r3, [r7, #0]
80010d2: 685a ldr r2, [r3, #4]
80010d4: 4613 mov r3, r2
80010d6: 009b lsls r3, r3, #2
80010d8: 4413 add r3, r2
80010da: 3b05 subs r3, #5
80010dc: fa00 f203 lsl.w r2, r0, r3
80010e0: 687b ldr r3, [r7, #4]
80010e2: 681b ldr r3, [r3, #0]
80010e4: 430a orrs r2, r1
80010e6: 635a str r2, [r3, #52] @ 0x34
80010e8: e03c b.n 8001164 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
80010ea: 683b ldr r3, [r7, #0]
80010ec: 685b ldr r3, [r3, #4]
80010ee: 2b0c cmp r3, #12
80010f0: d81c bhi.n 800112c <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR2 ,
80010f2: 687b ldr r3, [r7, #4]
80010f4: 681b ldr r3, [r3, #0]
80010f6: 6b19 ldr r1, [r3, #48] @ 0x30
80010f8: 683b ldr r3, [r7, #0]
80010fa: 685a ldr r2, [r3, #4]
80010fc: 4613 mov r3, r2
80010fe: 009b lsls r3, r3, #2
8001100: 4413 add r3, r2
8001102: 3b23 subs r3, #35 @ 0x23
8001104: 221f movs r2, #31
8001106: fa02 f303 lsl.w r3, r2, r3
800110a: 43db mvns r3, r3
800110c: 4019 ands r1, r3
800110e: 683b ldr r3, [r7, #0]
8001110: 6818 ldr r0, [r3, #0]
8001112: 683b ldr r3, [r7, #0]
8001114: 685a ldr r2, [r3, #4]
8001116: 4613 mov r3, r2
8001118: 009b lsls r3, r3, #2
800111a: 4413 add r3, r2
800111c: 3b23 subs r3, #35 @ 0x23
800111e: fa00 f203 lsl.w r2, r0, r3
8001122: 687b ldr r3, [r7, #4]
8001124: 681b ldr r3, [r3, #0]
8001126: 430a orrs r2, r1
8001128: 631a str r2, [r3, #48] @ 0x30
800112a: e01b b.n 8001164 <HAL_ADC_ConfigChannel+0xe4>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 16 */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
800112c: 687b ldr r3, [r7, #4]
800112e: 681b ldr r3, [r3, #0]
8001130: 6ad9 ldr r1, [r3, #44] @ 0x2c
8001132: 683b ldr r3, [r7, #0]
8001134: 685a ldr r2, [r3, #4]
8001136: 4613 mov r3, r2
8001138: 009b lsls r3, r3, #2
800113a: 4413 add r3, r2
800113c: 3b41 subs r3, #65 @ 0x41
800113e: 221f movs r2, #31
8001140: fa02 f303 lsl.w r3, r2, r3
8001144: 43db mvns r3, r3
8001146: 4019 ands r1, r3
8001148: 683b ldr r3, [r7, #0]
800114a: 6818 ldr r0, [r3, #0]
800114c: 683b ldr r3, [r7, #0]
800114e: 685a ldr r2, [r3, #4]
8001150: 4613 mov r3, r2
8001152: 009b lsls r3, r3, #2
8001154: 4413 add r3, r2
8001156: 3b41 subs r3, #65 @ 0x41
8001158: fa00 f203 lsl.w r2, r0, r3
800115c: 687b ldr r3, [r7, #4]
800115e: 681b ldr r3, [r3, #0]
8001160: 430a orrs r2, r1
8001162: 62da str r2, [r3, #44] @ 0x2c
}
/* Channel sampling time configuration */
/* For channels 10 to 17 */
if (sConfig->Channel >= ADC_CHANNEL_10)
8001164: 683b ldr r3, [r7, #0]
8001166: 681b ldr r3, [r3, #0]
8001168: 2b09 cmp r3, #9
800116a: d91c bls.n 80011a6 <HAL_ADC_ConfigChannel+0x126>
{
MODIFY_REG(hadc->Instance->SMPR1 ,
800116c: 687b ldr r3, [r7, #4]
800116e: 681b ldr r3, [r3, #0]
8001170: 68d9 ldr r1, [r3, #12]
8001172: 683b ldr r3, [r7, #0]
8001174: 681a ldr r2, [r3, #0]
8001176: 4613 mov r3, r2
8001178: 005b lsls r3, r3, #1
800117a: 4413 add r3, r2
800117c: 3b1e subs r3, #30
800117e: 2207 movs r2, #7
8001180: fa02 f303 lsl.w r3, r2, r3
8001184: 43db mvns r3, r3
8001186: 4019 ands r1, r3
8001188: 683b ldr r3, [r7, #0]
800118a: 6898 ldr r0, [r3, #8]
800118c: 683b ldr r3, [r7, #0]
800118e: 681a ldr r2, [r3, #0]
8001190: 4613 mov r3, r2
8001192: 005b lsls r3, r3, #1
8001194: 4413 add r3, r2
8001196: 3b1e subs r3, #30
8001198: fa00 f203 lsl.w r2, r0, r3
800119c: 687b ldr r3, [r7, #4]
800119e: 681b ldr r3, [r3, #0]
80011a0: 430a orrs r2, r1
80011a2: 60da str r2, [r3, #12]
80011a4: e019 b.n 80011da <HAL_ADC_ConfigChannel+0x15a>
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 0 to 9 */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
80011a6: 687b ldr r3, [r7, #4]
80011a8: 681b ldr r3, [r3, #0]
80011aa: 6919 ldr r1, [r3, #16]
80011ac: 683b ldr r3, [r7, #0]
80011ae: 681a ldr r2, [r3, #0]
80011b0: 4613 mov r3, r2
80011b2: 005b lsls r3, r3, #1
80011b4: 4413 add r3, r2
80011b6: 2207 movs r2, #7
80011b8: fa02 f303 lsl.w r3, r2, r3
80011bc: 43db mvns r3, r3
80011be: 4019 ands r1, r3
80011c0: 683b ldr r3, [r7, #0]
80011c2: 6898 ldr r0, [r3, #8]
80011c4: 683b ldr r3, [r7, #0]
80011c6: 681a ldr r2, [r3, #0]
80011c8: 4613 mov r3, r2
80011ca: 005b lsls r3, r3, #1
80011cc: 4413 add r3, r2
80011ce: fa00 f203 lsl.w r2, r0, r3
80011d2: 687b ldr r3, [r7, #4]
80011d4: 681b ldr r3, [r3, #0]
80011d6: 430a orrs r2, r1
80011d8: 611a str r2, [r3, #16]
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80011da: 683b ldr r3, [r7, #0]
80011dc: 681b ldr r3, [r3, #0]
80011de: 2b10 cmp r3, #16
80011e0: d003 beq.n 80011ea <HAL_ADC_ConfigChannel+0x16a>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
80011e2: 683b ldr r3, [r7, #0]
80011e4: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
80011e6: 2b11 cmp r3, #17
80011e8: d132 bne.n 8001250 <HAL_ADC_ConfigChannel+0x1d0>
{
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
/* measurement channels (VrefInt/TempSensor). If these channels are */
/* intended to be set on other ADC instances, an error is reported. */
if (hadc->Instance == ADC1)
80011ea: 687b ldr r3, [r7, #4]
80011ec: 681b ldr r3, [r3, #0]
80011ee: 4a1d ldr r2, [pc, #116] @ (8001264 <HAL_ADC_ConfigChannel+0x1e4>)
80011f0: 4293 cmp r3, r2
80011f2: d125 bne.n 8001240 <HAL_ADC_ConfigChannel+0x1c0>
{
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
80011f4: 687b ldr r3, [r7, #4]
80011f6: 681b ldr r3, [r3, #0]
80011f8: 689b ldr r3, [r3, #8]
80011fa: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80011fe: 2b00 cmp r3, #0
8001200: d126 bne.n 8001250 <HAL_ADC_ConfigChannel+0x1d0>
{
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
8001202: 687b ldr r3, [r7, #4]
8001204: 681b ldr r3, [r3, #0]
8001206: 689a ldr r2, [r3, #8]
8001208: 687b ldr r3, [r7, #4]
800120a: 681b ldr r3, [r3, #0]
800120c: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8001210: 609a str r2, [r3, #8]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8001212: 683b ldr r3, [r7, #0]
8001214: 681b ldr r3, [r3, #0]
8001216: 2b10 cmp r3, #16
8001218: d11a bne.n 8001250 <HAL_ADC_ConfigChannel+0x1d0>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
800121a: 4b13 ldr r3, [pc, #76] @ (8001268 <HAL_ADC_ConfigChannel+0x1e8>)
800121c: 681b ldr r3, [r3, #0]
800121e: 4a13 ldr r2, [pc, #76] @ (800126c <HAL_ADC_ConfigChannel+0x1ec>)
8001220: fba2 2303 umull r2, r3, r2, r3
8001224: 0c9a lsrs r2, r3, #18
8001226: 4613 mov r3, r2
8001228: 009b lsls r3, r3, #2
800122a: 4413 add r3, r2
800122c: 005b lsls r3, r3, #1
800122e: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8001230: e002 b.n 8001238 <HAL_ADC_ConfigChannel+0x1b8>
{
wait_loop_index--;
8001232: 68bb ldr r3, [r7, #8]
8001234: 3b01 subs r3, #1
8001236: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8001238: 68bb ldr r3, [r7, #8]
800123a: 2b00 cmp r3, #0
800123c: d1f9 bne.n 8001232 <HAL_ADC_ConfigChannel+0x1b2>
800123e: e007 b.n 8001250 <HAL_ADC_ConfigChannel+0x1d0>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001240: 687b ldr r3, [r7, #4]
8001242: 6a9b ldr r3, [r3, #40] @ 0x28
8001244: f043 0220 orr.w r2, r3, #32
8001248: 687b ldr r3, [r7, #4]
800124a: 629a str r2, [r3, #40] @ 0x28
tmp_hal_status = HAL_ERROR;
800124c: 2301 movs r3, #1
800124e: 73fb strb r3, [r7, #15]
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8001250: 687b ldr r3, [r7, #4]
8001252: 2200 movs r2, #0
8001254: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Return function status */
return tmp_hal_status;
8001258: 7bfb ldrb r3, [r7, #15]
}
800125a: 4618 mov r0, r3
800125c: 3714 adds r7, #20
800125e: 46bd mov sp, r7
8001260: bc80 pop {r7}
8001262: 4770 bx lr
8001264: 40012400 .word 0x40012400
8001268: 20000000 .word 0x20000000
800126c: 431bde83 .word 0x431bde83
08001270 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc: ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
8001270: b580 push {r7, lr}
8001272: b084 sub sp, #16
8001274: af00 add r7, sp, #0
8001276: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8001278: 2300 movs r3, #0
800127a: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
800127c: 687b ldr r3, [r7, #4]
800127e: 681b ldr r3, [r3, #0]
8001280: 689b ldr r3, [r3, #8]
8001282: f003 0301 and.w r3, r3, #1
8001286: 2b01 cmp r3, #1
8001288: d12e bne.n 80012e8 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
800128a: 687b ldr r3, [r7, #4]
800128c: 681b ldr r3, [r3, #0]
800128e: 689a ldr r2, [r3, #8]
8001290: 687b ldr r3, [r7, #4]
8001292: 681b ldr r3, [r3, #0]
8001294: f022 0201 bic.w r2, r2, #1
8001298: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
800129a: f7ff fe0f bl 8000ebc <HAL_GetTick>
800129e: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
80012a0: e01b b.n 80012da <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
80012a2: f7ff fe0b bl 8000ebc <HAL_GetTick>
80012a6: 4602 mov r2, r0
80012a8: 68fb ldr r3, [r7, #12]
80012aa: 1ad3 subs r3, r2, r3
80012ac: 2b02 cmp r3, #2
80012ae: d914 bls.n 80012da <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
80012b0: 687b ldr r3, [r7, #4]
80012b2: 681b ldr r3, [r3, #0]
80012b4: 689b ldr r3, [r3, #8]
80012b6: f003 0301 and.w r3, r3, #1
80012ba: 2b01 cmp r3, #1
80012bc: d10d bne.n 80012da <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80012be: 687b ldr r3, [r7, #4]
80012c0: 6a9b ldr r3, [r3, #40] @ 0x28
80012c2: f043 0210 orr.w r2, r3, #16
80012c6: 687b ldr r3, [r7, #4]
80012c8: 629a str r2, [r3, #40] @ 0x28
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80012ca: 687b ldr r3, [r7, #4]
80012cc: 6adb ldr r3, [r3, #44] @ 0x2c
80012ce: f043 0201 orr.w r2, r3, #1
80012d2: 687b ldr r3, [r7, #4]
80012d4: 62da str r2, [r3, #44] @ 0x2c
return HAL_ERROR;
80012d6: 2301 movs r3, #1
80012d8: e007 b.n 80012ea <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
80012da: 687b ldr r3, [r7, #4]
80012dc: 681b ldr r3, [r3, #0]
80012de: 689b ldr r3, [r3, #8]
80012e0: f003 0301 and.w r3, r3, #1
80012e4: 2b01 cmp r3, #1
80012e6: d0dc beq.n 80012a2 <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
80012e8: 2300 movs r3, #0
}
80012ea: 4618 mov r0, r3
80012ec: 3710 adds r7, #16
80012ee: 46bd mov sp, r7
80012f0: bd80 pop {r7, pc}
...
080012f4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80012f4: b480 push {r7}
80012f6: b085 sub sp, #20
80012f8: af00 add r7, sp, #0
80012fa: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80012fc: 687b ldr r3, [r7, #4]
80012fe: f003 0307 and.w r3, r3, #7
8001302: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001304: 4b0c ldr r3, [pc, #48] @ (8001338 <__NVIC_SetPriorityGrouping+0x44>)
8001306: 68db ldr r3, [r3, #12]
8001308: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800130a: 68ba ldr r2, [r7, #8]
800130c: f64f 03ff movw r3, #63743 @ 0xf8ff
8001310: 4013 ands r3, r2
8001312: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001314: 68fb ldr r3, [r7, #12]
8001316: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001318: 68bb ldr r3, [r7, #8]
800131a: 4313 orrs r3, r2
reg_value = (reg_value |
800131c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8001320: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001324: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001326: 4a04 ldr r2, [pc, #16] @ (8001338 <__NVIC_SetPriorityGrouping+0x44>)
8001328: 68bb ldr r3, [r7, #8]
800132a: 60d3 str r3, [r2, #12]
}
800132c: bf00 nop
800132e: 3714 adds r7, #20
8001330: 46bd mov sp, r7
8001332: bc80 pop {r7}
8001334: 4770 bx lr
8001336: bf00 nop
8001338: e000ed00 .word 0xe000ed00
0800133c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800133c: b480 push {r7}
800133e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001340: 4b04 ldr r3, [pc, #16] @ (8001354 <__NVIC_GetPriorityGrouping+0x18>)
8001342: 68db ldr r3, [r3, #12]
8001344: 0a1b lsrs r3, r3, #8
8001346: f003 0307 and.w r3, r3, #7
}
800134a: 4618 mov r0, r3
800134c: 46bd mov sp, r7
800134e: bc80 pop {r7}
8001350: 4770 bx lr
8001352: bf00 nop
8001354: e000ed00 .word 0xe000ed00
08001358 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001358: b480 push {r7}
800135a: b083 sub sp, #12
800135c: af00 add r7, sp, #0
800135e: 4603 mov r3, r0
8001360: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001362: f997 3007 ldrsb.w r3, [r7, #7]
8001366: 2b00 cmp r3, #0
8001368: db0b blt.n 8001382 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800136a: 79fb ldrb r3, [r7, #7]
800136c: f003 021f and.w r2, r3, #31
8001370: 4906 ldr r1, [pc, #24] @ (800138c <__NVIC_EnableIRQ+0x34>)
8001372: f997 3007 ldrsb.w r3, [r7, #7]
8001376: 095b lsrs r3, r3, #5
8001378: 2001 movs r0, #1
800137a: fa00 f202 lsl.w r2, r0, r2
800137e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001382: bf00 nop
8001384: 370c adds r7, #12
8001386: 46bd mov sp, r7
8001388: bc80 pop {r7}
800138a: 4770 bx lr
800138c: e000e100 .word 0xe000e100
08001390 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001390: b480 push {r7}
8001392: b083 sub sp, #12
8001394: af00 add r7, sp, #0
8001396: 4603 mov r3, r0
8001398: 6039 str r1, [r7, #0]
800139a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800139c: f997 3007 ldrsb.w r3, [r7, #7]
80013a0: 2b00 cmp r3, #0
80013a2: db0a blt.n 80013ba <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80013a4: 683b ldr r3, [r7, #0]
80013a6: b2da uxtb r2, r3
80013a8: 490c ldr r1, [pc, #48] @ (80013dc <__NVIC_SetPriority+0x4c>)
80013aa: f997 3007 ldrsb.w r3, [r7, #7]
80013ae: 0112 lsls r2, r2, #4
80013b0: b2d2 uxtb r2, r2
80013b2: 440b add r3, r1
80013b4: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80013b8: e00a b.n 80013d0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80013ba: 683b ldr r3, [r7, #0]
80013bc: b2da uxtb r2, r3
80013be: 4908 ldr r1, [pc, #32] @ (80013e0 <__NVIC_SetPriority+0x50>)
80013c0: 79fb ldrb r3, [r7, #7]
80013c2: f003 030f and.w r3, r3, #15
80013c6: 3b04 subs r3, #4
80013c8: 0112 lsls r2, r2, #4
80013ca: b2d2 uxtb r2, r2
80013cc: 440b add r3, r1
80013ce: 761a strb r2, [r3, #24]
}
80013d0: bf00 nop
80013d2: 370c adds r7, #12
80013d4: 46bd mov sp, r7
80013d6: bc80 pop {r7}
80013d8: 4770 bx lr
80013da: bf00 nop
80013dc: e000e100 .word 0xe000e100
80013e0: e000ed00 .word 0xe000ed00
080013e4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80013e4: b480 push {r7}
80013e6: b089 sub sp, #36 @ 0x24
80013e8: af00 add r7, sp, #0
80013ea: 60f8 str r0, [r7, #12]
80013ec: 60b9 str r1, [r7, #8]
80013ee: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80013f0: 68fb ldr r3, [r7, #12]
80013f2: f003 0307 and.w r3, r3, #7
80013f6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80013f8: 69fb ldr r3, [r7, #28]
80013fa: f1c3 0307 rsb r3, r3, #7
80013fe: 2b04 cmp r3, #4
8001400: bf28 it cs
8001402: 2304 movcs r3, #4
8001404: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001406: 69fb ldr r3, [r7, #28]
8001408: 3304 adds r3, #4
800140a: 2b06 cmp r3, #6
800140c: d902 bls.n 8001414 <NVIC_EncodePriority+0x30>
800140e: 69fb ldr r3, [r7, #28]
8001410: 3b03 subs r3, #3
8001412: e000 b.n 8001416 <NVIC_EncodePriority+0x32>
8001414: 2300 movs r3, #0
8001416: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001418: f04f 32ff mov.w r2, #4294967295
800141c: 69bb ldr r3, [r7, #24]
800141e: fa02 f303 lsl.w r3, r2, r3
8001422: 43da mvns r2, r3
8001424: 68bb ldr r3, [r7, #8]
8001426: 401a ands r2, r3
8001428: 697b ldr r3, [r7, #20]
800142a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
800142c: f04f 31ff mov.w r1, #4294967295
8001430: 697b ldr r3, [r7, #20]
8001432: fa01 f303 lsl.w r3, r1, r3
8001436: 43d9 mvns r1, r3
8001438: 687b ldr r3, [r7, #4]
800143a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800143c: 4313 orrs r3, r2
);
}
800143e: 4618 mov r0, r3
8001440: 3724 adds r7, #36 @ 0x24
8001442: 46bd mov sp, r7
8001444: bc80 pop {r7}
8001446: 4770 bx lr
08001448 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001448: b580 push {r7, lr}
800144a: b082 sub sp, #8
800144c: af00 add r7, sp, #0
800144e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001450: 687b ldr r3, [r7, #4]
8001452: 3b01 subs r3, #1
8001454: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8001458: d301 bcc.n 800145e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800145a: 2301 movs r3, #1
800145c: e00f b.n 800147e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800145e: 4a0a ldr r2, [pc, #40] @ (8001488 <SysTick_Config+0x40>)
8001460: 687b ldr r3, [r7, #4]
8001462: 3b01 subs r3, #1
8001464: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001466: 210f movs r1, #15
8001468: f04f 30ff mov.w r0, #4294967295
800146c: f7ff ff90 bl 8001390 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001470: 4b05 ldr r3, [pc, #20] @ (8001488 <SysTick_Config+0x40>)
8001472: 2200 movs r2, #0
8001474: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001476: 4b04 ldr r3, [pc, #16] @ (8001488 <SysTick_Config+0x40>)
8001478: 2207 movs r2, #7
800147a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800147c: 2300 movs r3, #0
}
800147e: 4618 mov r0, r3
8001480: 3708 adds r7, #8
8001482: 46bd mov sp, r7
8001484: bd80 pop {r7, pc}
8001486: bf00 nop
8001488: e000e010 .word 0xe000e010
0800148c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800148c: b580 push {r7, lr}
800148e: b082 sub sp, #8
8001490: af00 add r7, sp, #0
8001492: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001494: 6878 ldr r0, [r7, #4]
8001496: f7ff ff2d bl 80012f4 <__NVIC_SetPriorityGrouping>
}
800149a: bf00 nop
800149c: 3708 adds r7, #8
800149e: 46bd mov sp, r7
80014a0: bd80 pop {r7, pc}
080014a2 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80014a2: b580 push {r7, lr}
80014a4: b086 sub sp, #24
80014a6: af00 add r7, sp, #0
80014a8: 4603 mov r3, r0
80014aa: 60b9 str r1, [r7, #8]
80014ac: 607a str r2, [r7, #4]
80014ae: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80014b0: 2300 movs r3, #0
80014b2: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80014b4: f7ff ff42 bl 800133c <__NVIC_GetPriorityGrouping>
80014b8: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80014ba: 687a ldr r2, [r7, #4]
80014bc: 68b9 ldr r1, [r7, #8]
80014be: 6978 ldr r0, [r7, #20]
80014c0: f7ff ff90 bl 80013e4 <NVIC_EncodePriority>
80014c4: 4602 mov r2, r0
80014c6: f997 300f ldrsb.w r3, [r7, #15]
80014ca: 4611 mov r1, r2
80014cc: 4618 mov r0, r3
80014ce: f7ff ff5f bl 8001390 <__NVIC_SetPriority>
}
80014d2: bf00 nop
80014d4: 3718 adds r7, #24
80014d6: 46bd mov sp, r7
80014d8: bd80 pop {r7, pc}
080014da <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80014da: b580 push {r7, lr}
80014dc: b082 sub sp, #8
80014de: af00 add r7, sp, #0
80014e0: 4603 mov r3, r0
80014e2: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80014e4: f997 3007 ldrsb.w r3, [r7, #7]
80014e8: 4618 mov r0, r3
80014ea: f7ff ff35 bl 8001358 <__NVIC_EnableIRQ>
}
80014ee: bf00 nop
80014f0: 3708 adds r7, #8
80014f2: 46bd mov sp, r7
80014f4: bd80 pop {r7, pc}
080014f6 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80014f6: b580 push {r7, lr}
80014f8: b082 sub sp, #8
80014fa: af00 add r7, sp, #0
80014fc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80014fe: 6878 ldr r0, [r7, #4]
8001500: f7ff ffa2 bl 8001448 <SysTick_Config>
8001504: 4603 mov r3, r0
}
8001506: 4618 mov r0, r3
8001508: 3708 adds r7, #8
800150a: 46bd mov sp, r7
800150c: bd80 pop {r7, pc}
0800150e <HAL_SYSTICK_IRQHandler>:
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
800150e: b580 push {r7, lr}
8001510: af00 add r7, sp, #0
HAL_SYSTICK_Callback();
8001512: f7fe fe1b bl 800014c <HAL_SYSTICK_Callback>
}
8001516: bf00 nop
8001518: bd80 pop {r7, pc}
...
0800151c <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800151c: b480 push {r7}
800151e: b08b sub sp, #44 @ 0x2c
8001520: af00 add r7, sp, #0
8001522: 6078 str r0, [r7, #4]
8001524: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001526: 2300 movs r3, #0
8001528: 627b str r3, [r7, #36] @ 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
800152a: 2300 movs r3, #0
800152c: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800152e: e169 b.n 8001804 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8001530: 2201 movs r2, #1
8001532: 6a7b ldr r3, [r7, #36] @ 0x24
8001534: fa02 f303 lsl.w r3, r2, r3
8001538: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800153a: 683b ldr r3, [r7, #0]
800153c: 681b ldr r3, [r3, #0]
800153e: 69fa ldr r2, [r7, #28]
8001540: 4013 ands r3, r2
8001542: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8001544: 69ba ldr r2, [r7, #24]
8001546: 69fb ldr r3, [r7, #28]
8001548: 429a cmp r2, r3
800154a: f040 8158 bne.w 80017fe <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
800154e: 683b ldr r3, [r7, #0]
8001550: 685b ldr r3, [r3, #4]
8001552: 4a9a ldr r2, [pc, #616] @ (80017bc <HAL_GPIO_Init+0x2a0>)
8001554: 4293 cmp r3, r2
8001556: d05e beq.n 8001616 <HAL_GPIO_Init+0xfa>
8001558: 4a98 ldr r2, [pc, #608] @ (80017bc <HAL_GPIO_Init+0x2a0>)
800155a: 4293 cmp r3, r2
800155c: d875 bhi.n 800164a <HAL_GPIO_Init+0x12e>
800155e: 4a98 ldr r2, [pc, #608] @ (80017c0 <HAL_GPIO_Init+0x2a4>)
8001560: 4293 cmp r3, r2
8001562: d058 beq.n 8001616 <HAL_GPIO_Init+0xfa>
8001564: 4a96 ldr r2, [pc, #600] @ (80017c0 <HAL_GPIO_Init+0x2a4>)
8001566: 4293 cmp r3, r2
8001568: d86f bhi.n 800164a <HAL_GPIO_Init+0x12e>
800156a: 4a96 ldr r2, [pc, #600] @ (80017c4 <HAL_GPIO_Init+0x2a8>)
800156c: 4293 cmp r3, r2
800156e: d052 beq.n 8001616 <HAL_GPIO_Init+0xfa>
8001570: 4a94 ldr r2, [pc, #592] @ (80017c4 <HAL_GPIO_Init+0x2a8>)
8001572: 4293 cmp r3, r2
8001574: d869 bhi.n 800164a <HAL_GPIO_Init+0x12e>
8001576: 4a94 ldr r2, [pc, #592] @ (80017c8 <HAL_GPIO_Init+0x2ac>)
8001578: 4293 cmp r3, r2
800157a: d04c beq.n 8001616 <HAL_GPIO_Init+0xfa>
800157c: 4a92 ldr r2, [pc, #584] @ (80017c8 <HAL_GPIO_Init+0x2ac>)
800157e: 4293 cmp r3, r2
8001580: d863 bhi.n 800164a <HAL_GPIO_Init+0x12e>
8001582: 4a92 ldr r2, [pc, #584] @ (80017cc <HAL_GPIO_Init+0x2b0>)
8001584: 4293 cmp r3, r2
8001586: d046 beq.n 8001616 <HAL_GPIO_Init+0xfa>
8001588: 4a90 ldr r2, [pc, #576] @ (80017cc <HAL_GPIO_Init+0x2b0>)
800158a: 4293 cmp r3, r2
800158c: d85d bhi.n 800164a <HAL_GPIO_Init+0x12e>
800158e: 2b12 cmp r3, #18
8001590: d82a bhi.n 80015e8 <HAL_GPIO_Init+0xcc>
8001592: 2b12 cmp r3, #18
8001594: d859 bhi.n 800164a <HAL_GPIO_Init+0x12e>
8001596: a201 add r2, pc, #4 @ (adr r2, 800159c <HAL_GPIO_Init+0x80>)
8001598: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800159c: 08001617 .word 0x08001617
80015a0: 080015f1 .word 0x080015f1
80015a4: 08001603 .word 0x08001603
80015a8: 08001645 .word 0x08001645
80015ac: 0800164b .word 0x0800164b
80015b0: 0800164b .word 0x0800164b
80015b4: 0800164b .word 0x0800164b
80015b8: 0800164b .word 0x0800164b
80015bc: 0800164b .word 0x0800164b
80015c0: 0800164b .word 0x0800164b
80015c4: 0800164b .word 0x0800164b
80015c8: 0800164b .word 0x0800164b
80015cc: 0800164b .word 0x0800164b
80015d0: 0800164b .word 0x0800164b
80015d4: 0800164b .word 0x0800164b
80015d8: 0800164b .word 0x0800164b
80015dc: 0800164b .word 0x0800164b
80015e0: 080015f9 .word 0x080015f9
80015e4: 0800160d .word 0x0800160d
80015e8: 4a79 ldr r2, [pc, #484] @ (80017d0 <HAL_GPIO_Init+0x2b4>)
80015ea: 4293 cmp r3, r2
80015ec: d013 beq.n 8001616 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
80015ee: e02c b.n 800164a <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
80015f0: 683b ldr r3, [r7, #0]
80015f2: 68db ldr r3, [r3, #12]
80015f4: 623b str r3, [r7, #32]
break;
80015f6: e029 b.n 800164c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
80015f8: 683b ldr r3, [r7, #0]
80015fa: 68db ldr r3, [r3, #12]
80015fc: 3304 adds r3, #4
80015fe: 623b str r3, [r7, #32]
break;
8001600: e024 b.n 800164c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8001602: 683b ldr r3, [r7, #0]
8001604: 68db ldr r3, [r3, #12]
8001606: 3308 adds r3, #8
8001608: 623b str r3, [r7, #32]
break;
800160a: e01f b.n 800164c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
800160c: 683b ldr r3, [r7, #0]
800160e: 68db ldr r3, [r3, #12]
8001610: 330c adds r3, #12
8001612: 623b str r3, [r7, #32]
break;
8001614: e01a b.n 800164c <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8001616: 683b ldr r3, [r7, #0]
8001618: 689b ldr r3, [r3, #8]
800161a: 2b00 cmp r3, #0
800161c: d102 bne.n 8001624 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800161e: 2304 movs r3, #4
8001620: 623b str r3, [r7, #32]
break;
8001622: e013 b.n 800164c <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8001624: 683b ldr r3, [r7, #0]
8001626: 689b ldr r3, [r3, #8]
8001628: 2b01 cmp r3, #1
800162a: d105 bne.n 8001638 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
800162c: 2308 movs r3, #8
800162e: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8001630: 687b ldr r3, [r7, #4]
8001632: 69fa ldr r2, [r7, #28]
8001634: 611a str r2, [r3, #16]
break;
8001636: e009 b.n 800164c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8001638: 2308 movs r3, #8
800163a: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
800163c: 687b ldr r3, [r7, #4]
800163e: 69fa ldr r2, [r7, #28]
8001640: 615a str r2, [r3, #20]
break;
8001642: e003 b.n 800164c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8001644: 2300 movs r3, #0
8001646: 623b str r3, [r7, #32]
break;
8001648: e000 b.n 800164c <HAL_GPIO_Init+0x130>
break;
800164a: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
800164c: 69bb ldr r3, [r7, #24]
800164e: 2bff cmp r3, #255 @ 0xff
8001650: d801 bhi.n 8001656 <HAL_GPIO_Init+0x13a>
8001652: 687b ldr r3, [r7, #4]
8001654: e001 b.n 800165a <HAL_GPIO_Init+0x13e>
8001656: 687b ldr r3, [r7, #4]
8001658: 3304 adds r3, #4
800165a: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
800165c: 69bb ldr r3, [r7, #24]
800165e: 2bff cmp r3, #255 @ 0xff
8001660: d802 bhi.n 8001668 <HAL_GPIO_Init+0x14c>
8001662: 6a7b ldr r3, [r7, #36] @ 0x24
8001664: 009b lsls r3, r3, #2
8001666: e002 b.n 800166e <HAL_GPIO_Init+0x152>
8001668: 6a7b ldr r3, [r7, #36] @ 0x24
800166a: 3b08 subs r3, #8
800166c: 009b lsls r3, r3, #2
800166e: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8001670: 697b ldr r3, [r7, #20]
8001672: 681a ldr r2, [r3, #0]
8001674: 210f movs r1, #15
8001676: 693b ldr r3, [r7, #16]
8001678: fa01 f303 lsl.w r3, r1, r3
800167c: 43db mvns r3, r3
800167e: 401a ands r2, r3
8001680: 6a39 ldr r1, [r7, #32]
8001682: 693b ldr r3, [r7, #16]
8001684: fa01 f303 lsl.w r3, r1, r3
8001688: 431a orrs r2, r3
800168a: 697b ldr r3, [r7, #20]
800168c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
800168e: 683b ldr r3, [r7, #0]
8001690: 685b ldr r3, [r3, #4]
8001692: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001696: 2b00 cmp r3, #0
8001698: f000 80b1 beq.w 80017fe <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
800169c: 4b4d ldr r3, [pc, #308] @ (80017d4 <HAL_GPIO_Init+0x2b8>)
800169e: 699b ldr r3, [r3, #24]
80016a0: 4a4c ldr r2, [pc, #304] @ (80017d4 <HAL_GPIO_Init+0x2b8>)
80016a2: f043 0301 orr.w r3, r3, #1
80016a6: 6193 str r3, [r2, #24]
80016a8: 4b4a ldr r3, [pc, #296] @ (80017d4 <HAL_GPIO_Init+0x2b8>)
80016aa: 699b ldr r3, [r3, #24]
80016ac: f003 0301 and.w r3, r3, #1
80016b0: 60bb str r3, [r7, #8]
80016b2: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
80016b4: 4a48 ldr r2, [pc, #288] @ (80017d8 <HAL_GPIO_Init+0x2bc>)
80016b6: 6a7b ldr r3, [r7, #36] @ 0x24
80016b8: 089b lsrs r3, r3, #2
80016ba: 3302 adds r3, #2
80016bc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80016c0: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
80016c2: 6a7b ldr r3, [r7, #36] @ 0x24
80016c4: f003 0303 and.w r3, r3, #3
80016c8: 009b lsls r3, r3, #2
80016ca: 220f movs r2, #15
80016cc: fa02 f303 lsl.w r3, r2, r3
80016d0: 43db mvns r3, r3
80016d2: 68fa ldr r2, [r7, #12]
80016d4: 4013 ands r3, r2
80016d6: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
80016d8: 687b ldr r3, [r7, #4]
80016da: 4a40 ldr r2, [pc, #256] @ (80017dc <HAL_GPIO_Init+0x2c0>)
80016dc: 4293 cmp r3, r2
80016de: d013 beq.n 8001708 <HAL_GPIO_Init+0x1ec>
80016e0: 687b ldr r3, [r7, #4]
80016e2: 4a3f ldr r2, [pc, #252] @ (80017e0 <HAL_GPIO_Init+0x2c4>)
80016e4: 4293 cmp r3, r2
80016e6: d00d beq.n 8001704 <HAL_GPIO_Init+0x1e8>
80016e8: 687b ldr r3, [r7, #4]
80016ea: 4a3e ldr r2, [pc, #248] @ (80017e4 <HAL_GPIO_Init+0x2c8>)
80016ec: 4293 cmp r3, r2
80016ee: d007 beq.n 8001700 <HAL_GPIO_Init+0x1e4>
80016f0: 687b ldr r3, [r7, #4]
80016f2: 4a3d ldr r2, [pc, #244] @ (80017e8 <HAL_GPIO_Init+0x2cc>)
80016f4: 4293 cmp r3, r2
80016f6: d101 bne.n 80016fc <HAL_GPIO_Init+0x1e0>
80016f8: 2303 movs r3, #3
80016fa: e006 b.n 800170a <HAL_GPIO_Init+0x1ee>
80016fc: 2304 movs r3, #4
80016fe: e004 b.n 800170a <HAL_GPIO_Init+0x1ee>
8001700: 2302 movs r3, #2
8001702: e002 b.n 800170a <HAL_GPIO_Init+0x1ee>
8001704: 2301 movs r3, #1
8001706: e000 b.n 800170a <HAL_GPIO_Init+0x1ee>
8001708: 2300 movs r3, #0
800170a: 6a7a ldr r2, [r7, #36] @ 0x24
800170c: f002 0203 and.w r2, r2, #3
8001710: 0092 lsls r2, r2, #2
8001712: 4093 lsls r3, r2
8001714: 68fa ldr r2, [r7, #12]
8001716: 4313 orrs r3, r2
8001718: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
800171a: 492f ldr r1, [pc, #188] @ (80017d8 <HAL_GPIO_Init+0x2bc>)
800171c: 6a7b ldr r3, [r7, #36] @ 0x24
800171e: 089b lsrs r3, r3, #2
8001720: 3302 adds r3, #2
8001722: 68fa ldr r2, [r7, #12]
8001724: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8001728: 683b ldr r3, [r7, #0]
800172a: 685b ldr r3, [r3, #4]
800172c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001730: 2b00 cmp r3, #0
8001732: d006 beq.n 8001742 <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->RTSR, iocurrent);
8001734: 4b2d ldr r3, [pc, #180] @ (80017ec <HAL_GPIO_Init+0x2d0>)
8001736: 689a ldr r2, [r3, #8]
8001738: 492c ldr r1, [pc, #176] @ (80017ec <HAL_GPIO_Init+0x2d0>)
800173a: 69bb ldr r3, [r7, #24]
800173c: 4313 orrs r3, r2
800173e: 608b str r3, [r1, #8]
8001740: e006 b.n 8001750 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8001742: 4b2a ldr r3, [pc, #168] @ (80017ec <HAL_GPIO_Init+0x2d0>)
8001744: 689a ldr r2, [r3, #8]
8001746: 69bb ldr r3, [r7, #24]
8001748: 43db mvns r3, r3
800174a: 4928 ldr r1, [pc, #160] @ (80017ec <HAL_GPIO_Init+0x2d0>)
800174c: 4013 ands r3, r2
800174e: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8001750: 683b ldr r3, [r7, #0]
8001752: 685b ldr r3, [r3, #4]
8001754: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001758: 2b00 cmp r3, #0
800175a: d006 beq.n 800176a <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->FTSR, iocurrent);
800175c: 4b23 ldr r3, [pc, #140] @ (80017ec <HAL_GPIO_Init+0x2d0>)
800175e: 68da ldr r2, [r3, #12]
8001760: 4922 ldr r1, [pc, #136] @ (80017ec <HAL_GPIO_Init+0x2d0>)
8001762: 69bb ldr r3, [r7, #24]
8001764: 4313 orrs r3, r2
8001766: 60cb str r3, [r1, #12]
8001768: e006 b.n 8001778 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
800176a: 4b20 ldr r3, [pc, #128] @ (80017ec <HAL_GPIO_Init+0x2d0>)
800176c: 68da ldr r2, [r3, #12]
800176e: 69bb ldr r3, [r7, #24]
8001770: 43db mvns r3, r3
8001772: 491e ldr r1, [pc, #120] @ (80017ec <HAL_GPIO_Init+0x2d0>)
8001774: 4013 ands r3, r2
8001776: 60cb str r3, [r1, #12]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8001778: 683b ldr r3, [r7, #0]
800177a: 685b ldr r3, [r3, #4]
800177c: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001780: 2b00 cmp r3, #0
8001782: d006 beq.n 8001792 <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->EMR, iocurrent);
8001784: 4b19 ldr r3, [pc, #100] @ (80017ec <HAL_GPIO_Init+0x2d0>)
8001786: 685a ldr r2, [r3, #4]
8001788: 4918 ldr r1, [pc, #96] @ (80017ec <HAL_GPIO_Init+0x2d0>)
800178a: 69bb ldr r3, [r7, #24]
800178c: 4313 orrs r3, r2
800178e: 604b str r3, [r1, #4]
8001790: e006 b.n 80017a0 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8001792: 4b16 ldr r3, [pc, #88] @ (80017ec <HAL_GPIO_Init+0x2d0>)
8001794: 685a ldr r2, [r3, #4]
8001796: 69bb ldr r3, [r7, #24]
8001798: 43db mvns r3, r3
800179a: 4914 ldr r1, [pc, #80] @ (80017ec <HAL_GPIO_Init+0x2d0>)
800179c: 4013 ands r3, r2
800179e: 604b str r3, [r1, #4]
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80017a0: 683b ldr r3, [r7, #0]
80017a2: 685b ldr r3, [r3, #4]
80017a4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80017a8: 2b00 cmp r3, #0
80017aa: d021 beq.n 80017f0 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->IMR, iocurrent);
80017ac: 4b0f ldr r3, [pc, #60] @ (80017ec <HAL_GPIO_Init+0x2d0>)
80017ae: 681a ldr r2, [r3, #0]
80017b0: 490e ldr r1, [pc, #56] @ (80017ec <HAL_GPIO_Init+0x2d0>)
80017b2: 69bb ldr r3, [r7, #24]
80017b4: 4313 orrs r3, r2
80017b6: 600b str r3, [r1, #0]
80017b8: e021 b.n 80017fe <HAL_GPIO_Init+0x2e2>
80017ba: bf00 nop
80017bc: 10320000 .word 0x10320000
80017c0: 10310000 .word 0x10310000
80017c4: 10220000 .word 0x10220000
80017c8: 10210000 .word 0x10210000
80017cc: 10120000 .word 0x10120000
80017d0: 10110000 .word 0x10110000
80017d4: 40021000 .word 0x40021000
80017d8: 40010000 .word 0x40010000
80017dc: 40010800 .word 0x40010800
80017e0: 40010c00 .word 0x40010c00
80017e4: 40011000 .word 0x40011000
80017e8: 40011400 .word 0x40011400
80017ec: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
80017f0: 4b0b ldr r3, [pc, #44] @ (8001820 <HAL_GPIO_Init+0x304>)
80017f2: 681a ldr r2, [r3, #0]
80017f4: 69bb ldr r3, [r7, #24]
80017f6: 43db mvns r3, r3
80017f8: 4909 ldr r1, [pc, #36] @ (8001820 <HAL_GPIO_Init+0x304>)
80017fa: 4013 ands r3, r2
80017fc: 600b str r3, [r1, #0]
}
}
}
position++;
80017fe: 6a7b ldr r3, [r7, #36] @ 0x24
8001800: 3301 adds r3, #1
8001802: 627b str r3, [r7, #36] @ 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001804: 683b ldr r3, [r7, #0]
8001806: 681a ldr r2, [r3, #0]
8001808: 6a7b ldr r3, [r7, #36] @ 0x24
800180a: fa22 f303 lsr.w r3, r2, r3
800180e: 2b00 cmp r3, #0
8001810: f47f ae8e bne.w 8001530 <HAL_GPIO_Init+0x14>
}
}
8001814: bf00 nop
8001816: bf00 nop
8001818: 372c adds r7, #44 @ 0x2c
800181a: 46bd mov sp, r7
800181c: bc80 pop {r7}
800181e: 4770 bx lr
8001820: 40010400 .word 0x40010400
08001824 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001824: b480 push {r7}
8001826: b083 sub sp, #12
8001828: af00 add r7, sp, #0
800182a: 6078 str r0, [r7, #4]
800182c: 460b mov r3, r1
800182e: 807b strh r3, [r7, #2]
8001830: 4613 mov r3, r2
8001832: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001834: 787b ldrb r3, [r7, #1]
8001836: 2b00 cmp r3, #0
8001838: d003 beq.n 8001842 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800183a: 887a ldrh r2, [r7, #2]
800183c: 687b ldr r3, [r7, #4]
800183e: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8001840: e003 b.n 800184a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8001842: 887b ldrh r3, [r7, #2]
8001844: 041a lsls r2, r3, #16
8001846: 687b ldr r3, [r7, #4]
8001848: 611a str r2, [r3, #16]
}
800184a: bf00 nop
800184c: 370c adds r7, #12
800184e: 46bd mov sp, r7
8001850: bc80 pop {r7}
8001852: 4770 bx lr
08001854 <HAL_GPIO_TogglePin>:
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8001854: b480 push {r7}
8001856: b085 sub sp, #20
8001858: af00 add r7, sp, #0
800185a: 6078 str r0, [r7, #4]
800185c: 460b mov r3, r1
800185e: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8001860: 687b ldr r3, [r7, #4]
8001862: 68db ldr r3, [r3, #12]
8001864: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8001866: 887a ldrh r2, [r7, #2]
8001868: 68fb ldr r3, [r7, #12]
800186a: 4013 ands r3, r2
800186c: 041a lsls r2, r3, #16
800186e: 68fb ldr r3, [r7, #12]
8001870: 43d9 mvns r1, r3
8001872: 887b ldrh r3, [r7, #2]
8001874: 400b ands r3, r1
8001876: 431a orrs r2, r3
8001878: 687b ldr r3, [r7, #4]
800187a: 611a str r2, [r3, #16]
}
800187c: bf00 nop
800187e: 3714 adds r7, #20
8001880: 46bd mov sp, r7
8001882: bc80 pop {r7}
8001884: 4770 bx lr
08001886 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8001886: b580 push {r7, lr}
8001888: b084 sub sp, #16
800188a: af00 add r7, sp, #0
800188c: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
800188e: 687b ldr r3, [r7, #4]
8001890: 2b00 cmp r3, #0
8001892: d101 bne.n 8001898 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8001894: 2301 movs r3, #1
8001896: e0e8 b.n 8001a6a <HAL_PCD_Init+0x1e4>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8001898: 687b ldr r3, [r7, #4]
800189a: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
800189e: b2db uxtb r3, r3
80018a0: 2b00 cmp r3, #0
80018a2: d106 bne.n 80018b2 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
80018a4: 687b ldr r3, [r7, #4]
80018a6: 2200 movs r2, #0
80018a8: f883 2290 strb.w r2, [r3, #656] @ 0x290
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
80018ac: 6878 ldr r0, [r7, #4]
80018ae: f007 f985 bl 8008bbc <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
80018b2: 687b ldr r3, [r7, #4]
80018b4: 2203 movs r2, #3
80018b6: f883 2291 strb.w r2, [r3, #657] @ 0x291
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
80018ba: 687b ldr r3, [r7, #4]
80018bc: 2200 movs r2, #0
80018be: 715a strb r2, [r3, #5]
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
80018c0: 687b ldr r3, [r7, #4]
80018c2: 681b ldr r3, [r3, #0]
80018c4: 4618 mov r0, r3
80018c6: f003 f829 bl 800491c <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
80018ca: 687b ldr r3, [r7, #4]
80018cc: 6818 ldr r0, [r3, #0]
80018ce: 687b ldr r3, [r7, #4]
80018d0: 3304 adds r3, #4
80018d2: cb0e ldmia r3, {r1, r2, r3}
80018d4: f002 ffff bl 80048d6 <USB_CoreInit>
80018d8: 4603 mov r3, r0
80018da: 2b00 cmp r3, #0
80018dc: d005 beq.n 80018ea <HAL_PCD_Init+0x64>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80018de: 687b ldr r3, [r7, #4]
80018e0: 2202 movs r2, #2
80018e2: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
80018e6: 2301 movs r3, #1
80018e8: e0bf b.n 8001a6a <HAL_PCD_Init+0x1e4>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
80018ea: 687b ldr r3, [r7, #4]
80018ec: 681b ldr r3, [r3, #0]
80018ee: 2100 movs r1, #0
80018f0: 4618 mov r0, r3
80018f2: f003 f82d bl 8004950 <USB_SetCurrentMode>
80018f6: 4603 mov r3, r0
80018f8: 2b00 cmp r3, #0
80018fa: d005 beq.n 8001908 <HAL_PCD_Init+0x82>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80018fc: 687b ldr r3, [r7, #4]
80018fe: 2202 movs r2, #2
8001900: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8001904: 2301 movs r3, #1
8001906: e0b0 b.n 8001a6a <HAL_PCD_Init+0x1e4>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001908: 2300 movs r3, #0
800190a: 73fb strb r3, [r7, #15]
800190c: e03e b.n 800198c <HAL_PCD_Init+0x106>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
800190e: 7bfa ldrb r2, [r7, #15]
8001910: 6879 ldr r1, [r7, #4]
8001912: 4613 mov r3, r2
8001914: 009b lsls r3, r3, #2
8001916: 4413 add r3, r2
8001918: 00db lsls r3, r3, #3
800191a: 440b add r3, r1
800191c: 3311 adds r3, #17
800191e: 2201 movs r2, #1
8001920: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8001922: 7bfa ldrb r2, [r7, #15]
8001924: 6879 ldr r1, [r7, #4]
8001926: 4613 mov r3, r2
8001928: 009b lsls r3, r3, #2
800192a: 4413 add r3, r2
800192c: 00db lsls r3, r3, #3
800192e: 440b add r3, r1
8001930: 3310 adds r3, #16
8001932: 7bfa ldrb r2, [r7, #15]
8001934: 701a strb r2, [r3, #0]
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8001936: 7bfa ldrb r2, [r7, #15]
8001938: 6879 ldr r1, [r7, #4]
800193a: 4613 mov r3, r2
800193c: 009b lsls r3, r3, #2
800193e: 4413 add r3, r2
8001940: 00db lsls r3, r3, #3
8001942: 440b add r3, r1
8001944: 3313 adds r3, #19
8001946: 2200 movs r2, #0
8001948: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
800194a: 7bfa ldrb r2, [r7, #15]
800194c: 6879 ldr r1, [r7, #4]
800194e: 4613 mov r3, r2
8001950: 009b lsls r3, r3, #2
8001952: 4413 add r3, r2
8001954: 00db lsls r3, r3, #3
8001956: 440b add r3, r1
8001958: 3320 adds r3, #32
800195a: 2200 movs r2, #0
800195c: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
800195e: 7bfa ldrb r2, [r7, #15]
8001960: 6879 ldr r1, [r7, #4]
8001962: 4613 mov r3, r2
8001964: 009b lsls r3, r3, #2
8001966: 4413 add r3, r2
8001968: 00db lsls r3, r3, #3
800196a: 440b add r3, r1
800196c: 3324 adds r3, #36 @ 0x24
800196e: 2200 movs r2, #0
8001970: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8001972: 7bfb ldrb r3, [r7, #15]
8001974: 6879 ldr r1, [r7, #4]
8001976: 1c5a adds r2, r3, #1
8001978: 4613 mov r3, r2
800197a: 009b lsls r3, r3, #2
800197c: 4413 add r3, r2
800197e: 00db lsls r3, r3, #3
8001980: 440b add r3, r1
8001982: 2200 movs r2, #0
8001984: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001986: 7bfb ldrb r3, [r7, #15]
8001988: 3301 adds r3, #1
800198a: 73fb strb r3, [r7, #15]
800198c: 687b ldr r3, [r7, #4]
800198e: 791b ldrb r3, [r3, #4]
8001990: 7bfa ldrb r2, [r7, #15]
8001992: 429a cmp r2, r3
8001994: d3bb bcc.n 800190e <HAL_PCD_Init+0x88>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001996: 2300 movs r3, #0
8001998: 73fb strb r3, [r7, #15]
800199a: e044 b.n 8001a26 <HAL_PCD_Init+0x1a0>
{
hpcd->OUT_ep[i].is_in = 0U;
800199c: 7bfa ldrb r2, [r7, #15]
800199e: 6879 ldr r1, [r7, #4]
80019a0: 4613 mov r3, r2
80019a2: 009b lsls r3, r3, #2
80019a4: 4413 add r3, r2
80019a6: 00db lsls r3, r3, #3
80019a8: 440b add r3, r1
80019aa: f203 1351 addw r3, r3, #337 @ 0x151
80019ae: 2200 movs r2, #0
80019b0: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
80019b2: 7bfa ldrb r2, [r7, #15]
80019b4: 6879 ldr r1, [r7, #4]
80019b6: 4613 mov r3, r2
80019b8: 009b lsls r3, r3, #2
80019ba: 4413 add r3, r2
80019bc: 00db lsls r3, r3, #3
80019be: 440b add r3, r1
80019c0: f503 73a8 add.w r3, r3, #336 @ 0x150
80019c4: 7bfa ldrb r2, [r7, #15]
80019c6: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
80019c8: 7bfa ldrb r2, [r7, #15]
80019ca: 6879 ldr r1, [r7, #4]
80019cc: 4613 mov r3, r2
80019ce: 009b lsls r3, r3, #2
80019d0: 4413 add r3, r2
80019d2: 00db lsls r3, r3, #3
80019d4: 440b add r3, r1
80019d6: f203 1353 addw r3, r3, #339 @ 0x153
80019da: 2200 movs r2, #0
80019dc: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
80019de: 7bfa ldrb r2, [r7, #15]
80019e0: 6879 ldr r1, [r7, #4]
80019e2: 4613 mov r3, r2
80019e4: 009b lsls r3, r3, #2
80019e6: 4413 add r3, r2
80019e8: 00db lsls r3, r3, #3
80019ea: 440b add r3, r1
80019ec: f503 73b0 add.w r3, r3, #352 @ 0x160
80019f0: 2200 movs r2, #0
80019f2: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
80019f4: 7bfa ldrb r2, [r7, #15]
80019f6: 6879 ldr r1, [r7, #4]
80019f8: 4613 mov r3, r2
80019fa: 009b lsls r3, r3, #2
80019fc: 4413 add r3, r2
80019fe: 00db lsls r3, r3, #3
8001a00: 440b add r3, r1
8001a02: f503 73b2 add.w r3, r3, #356 @ 0x164
8001a06: 2200 movs r2, #0
8001a08: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8001a0a: 7bfa ldrb r2, [r7, #15]
8001a0c: 6879 ldr r1, [r7, #4]
8001a0e: 4613 mov r3, r2
8001a10: 009b lsls r3, r3, #2
8001a12: 4413 add r3, r2
8001a14: 00db lsls r3, r3, #3
8001a16: 440b add r3, r1
8001a18: f503 73b4 add.w r3, r3, #360 @ 0x168
8001a1c: 2200 movs r2, #0
8001a1e: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001a20: 7bfb ldrb r3, [r7, #15]
8001a22: 3301 adds r3, #1
8001a24: 73fb strb r3, [r7, #15]
8001a26: 687b ldr r3, [r7, #4]
8001a28: 791b ldrb r3, [r3, #4]
8001a2a: 7bfa ldrb r2, [r7, #15]
8001a2c: 429a cmp r2, r3
8001a2e: d3b5 bcc.n 800199c <HAL_PCD_Init+0x116>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8001a30: 687b ldr r3, [r7, #4]
8001a32: 6818 ldr r0, [r3, #0]
8001a34: 687b ldr r3, [r7, #4]
8001a36: 3304 adds r3, #4
8001a38: cb0e ldmia r3, {r1, r2, r3}
8001a3a: f002 ff95 bl 8004968 <USB_DevInit>
8001a3e: 4603 mov r3, r0
8001a40: 2b00 cmp r3, #0
8001a42: d005 beq.n 8001a50 <HAL_PCD_Init+0x1ca>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8001a44: 687b ldr r3, [r7, #4]
8001a46: 2202 movs r2, #2
8001a48: f883 2291 strb.w r2, [r3, #657] @ 0x291
return HAL_ERROR;
8001a4c: 2301 movs r3, #1
8001a4e: e00c b.n 8001a6a <HAL_PCD_Init+0x1e4>
}
hpcd->USB_Address = 0U;
8001a50: 687b ldr r3, [r7, #4]
8001a52: 2200 movs r2, #0
8001a54: 735a strb r2, [r3, #13]
hpcd->State = HAL_PCD_STATE_READY;
8001a56: 687b ldr r3, [r7, #4]
8001a58: 2201 movs r2, #1
8001a5a: f883 2291 strb.w r2, [r3, #657] @ 0x291
(void)USB_DevDisconnect(hpcd->Instance);
8001a5e: 687b ldr r3, [r7, #4]
8001a60: 681b ldr r3, [r3, #0]
8001a62: 4618 mov r0, r3
8001a64: f005 fa15 bl 8006e92 <USB_DevDisconnect>
return HAL_OK;
8001a68: 2300 movs r3, #0
}
8001a6a: 4618 mov r0, r3
8001a6c: 3710 adds r7, #16
8001a6e: 46bd mov sp, r7
8001a70: bd80 pop {r7, pc}
08001a72 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
8001a72: b580 push {r7, lr}
8001a74: b082 sub sp, #8
8001a76: af00 add r7, sp, #0
8001a78: 6078 str r0, [r7, #4]
__HAL_LOCK(hpcd);
8001a7a: 687b ldr r3, [r7, #4]
8001a7c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8001a80: 2b01 cmp r3, #1
8001a82: d101 bne.n 8001a88 <HAL_PCD_Start+0x16>
8001a84: 2302 movs r3, #2
8001a86: e016 b.n 8001ab6 <HAL_PCD_Start+0x44>
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 2201 movs r2, #1
8001a8c: f883 2290 strb.w r2, [r3, #656] @ 0x290
__HAL_PCD_ENABLE(hpcd);
8001a90: 687b ldr r3, [r7, #4]
8001a92: 681b ldr r3, [r3, #0]
8001a94: 4618 mov r0, r3
8001a96: f002 ff2b bl 80048f0 <USB_EnableGlobalInt>
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
8001a9a: 2101 movs r1, #1
8001a9c: 6878 ldr r0, [r7, #4]
8001a9e: f007 fb00 bl 80090a2 <HAL_PCDEx_SetConnectionState>
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
8001aa2: 687b ldr r3, [r7, #4]
8001aa4: 681b ldr r3, [r3, #0]
8001aa6: 4618 mov r0, r3
8001aa8: f005 f9e9 bl 8006e7e <USB_DevConnect>
__HAL_UNLOCK(hpcd);
8001aac: 687b ldr r3, [r7, #4]
8001aae: 2200 movs r2, #0
8001ab0: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8001ab4: 2300 movs r3, #0
}
8001ab6: 4618 mov r0, r3
8001ab8: 3708 adds r7, #8
8001aba: 46bd mov sp, r7
8001abc: bd80 pop {r7, pc}
08001abe <HAL_PCD_IRQHandler>:
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
8001abe: b580 push {r7, lr}
8001ac0: b088 sub sp, #32
8001ac2: af00 add r7, sp, #0
8001ac4: 6078 str r0, [r7, #4]
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
8001ac6: 687b ldr r3, [r7, #4]
8001ac8: 681b ldr r3, [r3, #0]
8001aca: 4618 mov r0, r3
8001acc: f005 f9eb bl 8006ea6 <USB_ReadInterrupts>
8001ad0: 61b8 str r0, [r7, #24]
uint16_t store_ep[8];
uint8_t i;
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
8001ad2: 69bb ldr r3, [r7, #24]
8001ad4: f403 4300 and.w r3, r3, #32768 @ 0x8000
8001ad8: 2b00 cmp r3, #0
8001ada: d003 beq.n 8001ae4 <HAL_PCD_IRQHandler+0x26>
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
8001adc: 6878 ldr r0, [r7, #4]
8001ade: f000 fb1a bl 8002116 <PCD_EP_ISR_Handler>
return;
8001ae2: e119 b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
8001ae4: 69bb ldr r3, [r7, #24]
8001ae6: f403 6380 and.w r3, r3, #1024 @ 0x400
8001aea: 2b00 cmp r3, #0
8001aec: d013 beq.n 8001b16 <HAL_PCD_IRQHandler+0x58>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8001aee: 687b ldr r3, [r7, #4]
8001af0: 681b ldr r3, [r3, #0]
8001af2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001af6: b29a uxth r2, r3
8001af8: 687b ldr r3, [r7, #4]
8001afa: 681b ldr r3, [r3, #0]
8001afc: f422 6280 bic.w r2, r2, #1024 @ 0x400
8001b00: b292 uxth r2, r2
8001b02: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
8001b06: 6878 ldr r0, [r7, #4]
8001b08: f007 f8d3 bl 8008cb2 <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
8001b0c: 2100 movs r1, #0
8001b0e: 6878 ldr r0, [r7, #4]
8001b10: f000 f905 bl 8001d1e <HAL_PCD_SetAddress>
return;
8001b14: e100 b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
8001b16: 69bb ldr r3, [r7, #24]
8001b18: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001b1c: 2b00 cmp r3, #0
8001b1e: d00c beq.n 8001b3a <HAL_PCD_IRQHandler+0x7c>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
8001b20: 687b ldr r3, [r7, #4]
8001b22: 681b ldr r3, [r3, #0]
8001b24: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001b28: b29a uxth r2, r3
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 681b ldr r3, [r3, #0]
8001b2e: f422 4280 bic.w r2, r2, #16384 @ 0x4000
8001b32: b292 uxth r2, r2
8001b34: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8001b38: e0ee b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
8001b3a: 69bb ldr r3, [r7, #24]
8001b3c: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001b40: 2b00 cmp r3, #0
8001b42: d00c beq.n 8001b5e <HAL_PCD_IRQHandler+0xa0>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
8001b44: 687b ldr r3, [r7, #4]
8001b46: 681b ldr r3, [r3, #0]
8001b48: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001b4c: b29a uxth r2, r3
8001b4e: 687b ldr r3, [r7, #4]
8001b50: 681b ldr r3, [r3, #0]
8001b52: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8001b56: b292 uxth r2, r2
8001b58: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8001b5c: e0dc b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
8001b5e: 69bb ldr r3, [r7, #24]
8001b60: f403 5380 and.w r3, r3, #4096 @ 0x1000
8001b64: 2b00 cmp r3, #0
8001b66: d027 beq.n 8001bb8 <HAL_PCD_IRQHandler+0xfa>
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
8001b68: 687b ldr r3, [r7, #4]
8001b6a: 681b ldr r3, [r3, #0]
8001b6c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8001b70: b29a uxth r2, r3
8001b72: 687b ldr r3, [r7, #4]
8001b74: 681b ldr r3, [r3, #0]
8001b76: f022 0204 bic.w r2, r2, #4
8001b7a: b292 uxth r2, r2
8001b7c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
8001b80: 687b ldr r3, [r7, #4]
8001b82: 681b ldr r3, [r3, #0]
8001b84: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8001b88: b29a uxth r2, r3
8001b8a: 687b ldr r3, [r7, #4]
8001b8c: 681b ldr r3, [r3, #0]
8001b8e: f022 0208 bic.w r2, r2, #8
8001b92: b292 uxth r2, r2
8001b94: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
8001b98: 6878 ldr r0, [r7, #4]
8001b9a: f007 f8c3 bl 8008d24 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
8001b9e: 687b ldr r3, [r7, #4]
8001ba0: 681b ldr r3, [r3, #0]
8001ba2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001ba6: b29a uxth r2, r3
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 681b ldr r3, [r3, #0]
8001bac: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8001bb0: b292 uxth r2, r2
8001bb2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8001bb6: e0af b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
8001bb8: 69bb ldr r3, [r7, #24]
8001bba: f403 6300 and.w r3, r3, #2048 @ 0x800
8001bbe: 2b00 cmp r3, #0
8001bc0: f000 8083 beq.w 8001cca <HAL_PCD_IRQHandler+0x20c>
{
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint registers */
for (i = 0U; i < 8U; i++)
8001bc4: 2300 movs r3, #0
8001bc6: 77fb strb r3, [r7, #31]
8001bc8: e010 b.n 8001bec <HAL_PCD_IRQHandler+0x12e>
{
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
8001bca: 687b ldr r3, [r7, #4]
8001bcc: 681b ldr r3, [r3, #0]
8001bce: 461a mov r2, r3
8001bd0: 7ffb ldrb r3, [r7, #31]
8001bd2: 009b lsls r3, r3, #2
8001bd4: 441a add r2, r3
8001bd6: 7ffb ldrb r3, [r7, #31]
8001bd8: 8812 ldrh r2, [r2, #0]
8001bda: b292 uxth r2, r2
8001bdc: 005b lsls r3, r3, #1
8001bde: 3320 adds r3, #32
8001be0: 443b add r3, r7
8001be2: f823 2c18 strh.w r2, [r3, #-24]
for (i = 0U; i < 8U; i++)
8001be6: 7ffb ldrb r3, [r7, #31]
8001be8: 3301 adds r3, #1
8001bea: 77fb strb r3, [r7, #31]
8001bec: 7ffb ldrb r3, [r7, #31]
8001bee: 2b07 cmp r3, #7
8001bf0: d9eb bls.n 8001bca <HAL_PCD_IRQHandler+0x10c>
}
/* FORCE RESET */
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
8001bf2: 687b ldr r3, [r7, #4]
8001bf4: 681b ldr r3, [r3, #0]
8001bf6: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8001bfa: b29a uxth r2, r3
8001bfc: 687b ldr r3, [r7, #4]
8001bfe: 681b ldr r3, [r3, #0]
8001c00: f042 0201 orr.w r2, r2, #1
8001c04: b292 uxth r2, r2
8001c06: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CLEAR RESET */
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
8001c0a: 687b ldr r3, [r7, #4]
8001c0c: 681b ldr r3, [r3, #0]
8001c0e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8001c12: b29a uxth r2, r3
8001c14: 687b ldr r3, [r7, #4]
8001c16: 681b ldr r3, [r3, #0]
8001c18: f022 0201 bic.w r2, r2, #1
8001c1c: b292 uxth r2, r2
8001c1e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* wait for reset flag in ISTR */
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
8001c22: bf00 nop
8001c24: 687b ldr r3, [r7, #4]
8001c26: 681b ldr r3, [r3, #0]
8001c28: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001c2c: b29b uxth r3, r3
8001c2e: f403 6380 and.w r3, r3, #1024 @ 0x400
8001c32: 2b00 cmp r3, #0
8001c34: d0f6 beq.n 8001c24 <HAL_PCD_IRQHandler+0x166>
{
}
/* Clear Reset Flag */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8001c36: 687b ldr r3, [r7, #4]
8001c38: 681b ldr r3, [r3, #0]
8001c3a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001c3e: b29a uxth r2, r3
8001c40: 687b ldr r3, [r7, #4]
8001c42: 681b ldr r3, [r3, #0]
8001c44: f422 6280 bic.w r2, r2, #1024 @ 0x400
8001c48: b292 uxth r2, r2
8001c4a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Restore Registre */
for (i = 0U; i < 8U; i++)
8001c4e: 2300 movs r3, #0
8001c50: 77fb strb r3, [r7, #31]
8001c52: e00f b.n 8001c74 <HAL_PCD_IRQHandler+0x1b6>
{
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
8001c54: 7ffb ldrb r3, [r7, #31]
8001c56: 687a ldr r2, [r7, #4]
8001c58: 6812 ldr r2, [r2, #0]
8001c5a: 4611 mov r1, r2
8001c5c: 7ffa ldrb r2, [r7, #31]
8001c5e: 0092 lsls r2, r2, #2
8001c60: 440a add r2, r1
8001c62: 005b lsls r3, r3, #1
8001c64: 3320 adds r3, #32
8001c66: 443b add r3, r7
8001c68: f833 3c18 ldrh.w r3, [r3, #-24]
8001c6c: 8013 strh r3, [r2, #0]
for (i = 0U; i < 8U; i++)
8001c6e: 7ffb ldrb r3, [r7, #31]
8001c70: 3301 adds r3, #1
8001c72: 77fb strb r3, [r7, #31]
8001c74: 7ffb ldrb r3, [r7, #31]
8001c76: 2b07 cmp r3, #7
8001c78: d9ec bls.n 8001c54 <HAL_PCD_IRQHandler+0x196>
}
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
8001c7a: 687b ldr r3, [r7, #4]
8001c7c: 681b ldr r3, [r3, #0]
8001c7e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8001c82: b29a uxth r2, r3
8001c84: 687b ldr r3, [r7, #4]
8001c86: 681b ldr r3, [r3, #0]
8001c88: f042 0208 orr.w r2, r2, #8
8001c8c: b292 uxth r2, r2
8001c8e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
8001c92: 687b ldr r3, [r7, #4]
8001c94: 681b ldr r3, [r3, #0]
8001c96: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001c9a: b29a uxth r2, r3
8001c9c: 687b ldr r3, [r7, #4]
8001c9e: 681b ldr r3, [r3, #0]
8001ca0: f422 6200 bic.w r2, r2, #2048 @ 0x800
8001ca4: b292 uxth r2, r2
8001ca6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
8001caa: 687b ldr r3, [r7, #4]
8001cac: 681b ldr r3, [r3, #0]
8001cae: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8001cb2: b29a uxth r2, r3
8001cb4: 687b ldr r3, [r7, #4]
8001cb6: 681b ldr r3, [r3, #0]
8001cb8: f042 0204 orr.w r2, r2, #4
8001cbc: b292 uxth r2, r2
8001cbe: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
8001cc2: 6878 ldr r0, [r7, #4]
8001cc4: f007 f814 bl 8008cf0 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8001cc8: e026 b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
8001cca: 69bb ldr r3, [r7, #24]
8001ccc: f403 7300 and.w r3, r3, #512 @ 0x200
8001cd0: 2b00 cmp r3, #0
8001cd2: d00f beq.n 8001cf4 <HAL_PCD_IRQHandler+0x236>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
8001cd4: 687b ldr r3, [r7, #4]
8001cd6: 681b ldr r3, [r3, #0]
8001cd8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001cdc: b29a uxth r2, r3
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 681b ldr r3, [r3, #0]
8001ce2: f422 7200 bic.w r2, r2, #512 @ 0x200
8001ce6: b292 uxth r2, r2
8001ce8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
8001cec: 6878 ldr r0, [r7, #4]
8001cee: f006 ffd2 bl 8008c96 <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8001cf2: e011 b.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
}
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
8001cf4: 69bb ldr r3, [r7, #24]
8001cf6: f403 7380 and.w r3, r3, #256 @ 0x100
8001cfa: 2b00 cmp r3, #0
8001cfc: d00c beq.n 8001d18 <HAL_PCD_IRQHandler+0x25a>
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
8001cfe: 687b ldr r3, [r7, #4]
8001d00: 681b ldr r3, [r3, #0]
8001d02: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8001d06: b29a uxth r2, r3
8001d08: 687b ldr r3, [r7, #4]
8001d0a: 681b ldr r3, [r3, #0]
8001d0c: f422 7280 bic.w r2, r2, #256 @ 0x100
8001d10: b292 uxth r2, r2
8001d12: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8001d16: bf00 nop
}
}
8001d18: 3720 adds r7, #32
8001d1a: 46bd mov sp, r7
8001d1c: bd80 pop {r7, pc}
08001d1e <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
8001d1e: b580 push {r7, lr}
8001d20: b082 sub sp, #8
8001d22: af00 add r7, sp, #0
8001d24: 6078 str r0, [r7, #4]
8001d26: 460b mov r3, r1
8001d28: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
8001d2a: 687b ldr r3, [r7, #4]
8001d2c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8001d30: 2b01 cmp r3, #1
8001d32: d101 bne.n 8001d38 <HAL_PCD_SetAddress+0x1a>
8001d34: 2302 movs r3, #2
8001d36: e012 b.n 8001d5e <HAL_PCD_SetAddress+0x40>
8001d38: 687b ldr r3, [r7, #4]
8001d3a: 2201 movs r2, #1
8001d3c: f883 2290 strb.w r2, [r3, #656] @ 0x290
hpcd->USB_Address = address;
8001d40: 687b ldr r3, [r7, #4]
8001d42: 78fa ldrb r2, [r7, #3]
8001d44: 735a strb r2, [r3, #13]
(void)USB_SetDevAddress(hpcd->Instance, address);
8001d46: 687b ldr r3, [r7, #4]
8001d48: 681b ldr r3, [r3, #0]
8001d4a: 78fa ldrb r2, [r7, #3]
8001d4c: 4611 mov r1, r2
8001d4e: 4618 mov r0, r3
8001d50: f005 f882 bl 8006e58 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8001d54: 687b ldr r3, [r7, #4]
8001d56: 2200 movs r2, #0
8001d58: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8001d5c: 2300 movs r3, #0
}
8001d5e: 4618 mov r0, r3
8001d60: 3708 adds r7, #8
8001d62: 46bd mov sp, r7
8001d64: bd80 pop {r7, pc}
08001d66 <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
8001d66: b580 push {r7, lr}
8001d68: b084 sub sp, #16
8001d6a: af00 add r7, sp, #0
8001d6c: 6078 str r0, [r7, #4]
8001d6e: 4608 mov r0, r1
8001d70: 4611 mov r1, r2
8001d72: 461a mov r2, r3
8001d74: 4603 mov r3, r0
8001d76: 70fb strb r3, [r7, #3]
8001d78: 460b mov r3, r1
8001d7a: 803b strh r3, [r7, #0]
8001d7c: 4613 mov r3, r2
8001d7e: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8001d80: 2300 movs r3, #0
8001d82: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8001d84: f997 3003 ldrsb.w r3, [r7, #3]
8001d88: 2b00 cmp r3, #0
8001d8a: da0e bge.n 8001daa <HAL_PCD_EP_Open+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8001d8c: 78fb ldrb r3, [r7, #3]
8001d8e: f003 0207 and.w r2, r3, #7
8001d92: 4613 mov r3, r2
8001d94: 009b lsls r3, r3, #2
8001d96: 4413 add r3, r2
8001d98: 00db lsls r3, r3, #3
8001d9a: 3310 adds r3, #16
8001d9c: 687a ldr r2, [r7, #4]
8001d9e: 4413 add r3, r2
8001da0: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8001da2: 68fb ldr r3, [r7, #12]
8001da4: 2201 movs r2, #1
8001da6: 705a strb r2, [r3, #1]
8001da8: e00e b.n 8001dc8 <HAL_PCD_EP_Open+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8001daa: 78fb ldrb r3, [r7, #3]
8001dac: f003 0207 and.w r2, r3, #7
8001db0: 4613 mov r3, r2
8001db2: 009b lsls r3, r3, #2
8001db4: 4413 add r3, r2
8001db6: 00db lsls r3, r3, #3
8001db8: f503 73a8 add.w r3, r3, #336 @ 0x150
8001dbc: 687a ldr r2, [r7, #4]
8001dbe: 4413 add r3, r2
8001dc0: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8001dc2: 68fb ldr r3, [r7, #12]
8001dc4: 2200 movs r2, #0
8001dc6: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8001dc8: 78fb ldrb r3, [r7, #3]
8001dca: f003 0307 and.w r3, r3, #7
8001dce: b2da uxtb r2, r3
8001dd0: 68fb ldr r3, [r7, #12]
8001dd2: 701a strb r2, [r3, #0]
ep->maxpacket = ep_mps;
8001dd4: 883a ldrh r2, [r7, #0]
8001dd6: 68fb ldr r3, [r7, #12]
8001dd8: 611a str r2, [r3, #16]
ep->type = ep_type;
8001dda: 68fb ldr r3, [r7, #12]
8001ddc: 78ba ldrb r2, [r7, #2]
8001dde: 70da strb r2, [r3, #3]
ep->tx_fifo_num = ep->num;
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
8001de0: 78bb ldrb r3, [r7, #2]
8001de2: 2b02 cmp r3, #2
8001de4: d102 bne.n 8001dec <HAL_PCD_EP_Open+0x86>
{
ep->data_pid_start = 0U;
8001de6: 68fb ldr r3, [r7, #12]
8001de8: 2200 movs r2, #0
8001dea: 711a strb r2, [r3, #4]
}
__HAL_LOCK(hpcd);
8001dec: 687b ldr r3, [r7, #4]
8001dee: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8001df2: 2b01 cmp r3, #1
8001df4: d101 bne.n 8001dfa <HAL_PCD_EP_Open+0x94>
8001df6: 2302 movs r3, #2
8001df8: e00e b.n 8001e18 <HAL_PCD_EP_Open+0xb2>
8001dfa: 687b ldr r3, [r7, #4]
8001dfc: 2201 movs r2, #1
8001dfe: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
8001e02: 687b ldr r3, [r7, #4]
8001e04: 681b ldr r3, [r3, #0]
8001e06: 68f9 ldr r1, [r7, #12]
8001e08: 4618 mov r0, r3
8001e0a: f002 fdcb bl 80049a4 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
8001e0e: 687b ldr r3, [r7, #4]
8001e10: 2200 movs r2, #0
8001e12: f883 2290 strb.w r2, [r3, #656] @ 0x290
return ret;
8001e16: 7afb ldrb r3, [r7, #11]
}
8001e18: 4618 mov r0, r3
8001e1a: 3710 adds r7, #16
8001e1c: 46bd mov sp, r7
8001e1e: bd80 pop {r7, pc}
08001e20 <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8001e20: b580 push {r7, lr}
8001e22: b084 sub sp, #16
8001e24: af00 add r7, sp, #0
8001e26: 6078 str r0, [r7, #4]
8001e28: 460b mov r3, r1
8001e2a: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8001e2c: f997 3003 ldrsb.w r3, [r7, #3]
8001e30: 2b00 cmp r3, #0
8001e32: da0e bge.n 8001e52 <HAL_PCD_EP_Close+0x32>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8001e34: 78fb ldrb r3, [r7, #3]
8001e36: f003 0207 and.w r2, r3, #7
8001e3a: 4613 mov r3, r2
8001e3c: 009b lsls r3, r3, #2
8001e3e: 4413 add r3, r2
8001e40: 00db lsls r3, r3, #3
8001e42: 3310 adds r3, #16
8001e44: 687a ldr r2, [r7, #4]
8001e46: 4413 add r3, r2
8001e48: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8001e4a: 68fb ldr r3, [r7, #12]
8001e4c: 2201 movs r2, #1
8001e4e: 705a strb r2, [r3, #1]
8001e50: e00e b.n 8001e70 <HAL_PCD_EP_Close+0x50>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8001e52: 78fb ldrb r3, [r7, #3]
8001e54: f003 0207 and.w r2, r3, #7
8001e58: 4613 mov r3, r2
8001e5a: 009b lsls r3, r3, #2
8001e5c: 4413 add r3, r2
8001e5e: 00db lsls r3, r3, #3
8001e60: f503 73a8 add.w r3, r3, #336 @ 0x150
8001e64: 687a ldr r2, [r7, #4]
8001e66: 4413 add r3, r2
8001e68: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8001e6a: 68fb ldr r3, [r7, #12]
8001e6c: 2200 movs r2, #0
8001e6e: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
8001e70: 78fb ldrb r3, [r7, #3]
8001e72: f003 0307 and.w r3, r3, #7
8001e76: b2da uxtb r2, r3
8001e78: 68fb ldr r3, [r7, #12]
8001e7a: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8001e7c: 687b ldr r3, [r7, #4]
8001e7e: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8001e82: 2b01 cmp r3, #1
8001e84: d101 bne.n 8001e8a <HAL_PCD_EP_Close+0x6a>
8001e86: 2302 movs r3, #2
8001e88: e00e b.n 8001ea8 <HAL_PCD_EP_Close+0x88>
8001e8a: 687b ldr r3, [r7, #4]
8001e8c: 2201 movs r2, #1
8001e8e: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
8001e92: 687b ldr r3, [r7, #4]
8001e94: 681b ldr r3, [r3, #0]
8001e96: 68f9 ldr r1, [r7, #12]
8001e98: 4618 mov r0, r3
8001e9a: f003 f943 bl 8005124 <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
8001e9e: 687b ldr r3, [r7, #4]
8001ea0: 2200 movs r2, #0
8001ea2: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8001ea6: 2300 movs r3, #0
}
8001ea8: 4618 mov r0, r3
8001eaa: 3710 adds r7, #16
8001eac: 46bd mov sp, r7
8001eae: bd80 pop {r7, pc}
08001eb0 <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8001eb0: b580 push {r7, lr}
8001eb2: b086 sub sp, #24
8001eb4: af00 add r7, sp, #0
8001eb6: 60f8 str r0, [r7, #12]
8001eb8: 607a str r2, [r7, #4]
8001eba: 603b str r3, [r7, #0]
8001ebc: 460b mov r3, r1
8001ebe: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8001ec0: 7afb ldrb r3, [r7, #11]
8001ec2: f003 0207 and.w r2, r3, #7
8001ec6: 4613 mov r3, r2
8001ec8: 009b lsls r3, r3, #2
8001eca: 4413 add r3, r2
8001ecc: 00db lsls r3, r3, #3
8001ece: f503 73a8 add.w r3, r3, #336 @ 0x150
8001ed2: 68fa ldr r2, [r7, #12]
8001ed4: 4413 add r3, r2
8001ed6: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8001ed8: 697b ldr r3, [r7, #20]
8001eda: 687a ldr r2, [r7, #4]
8001edc: 615a str r2, [r3, #20]
ep->xfer_len = len;
8001ede: 697b ldr r3, [r7, #20]
8001ee0: 683a ldr r2, [r7, #0]
8001ee2: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
8001ee4: 697b ldr r3, [r7, #20]
8001ee6: 2200 movs r2, #0
8001ee8: 61da str r2, [r3, #28]
ep->is_in = 0U;
8001eea: 697b ldr r3, [r7, #20]
8001eec: 2200 movs r2, #0
8001eee: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8001ef0: 7afb ldrb r3, [r7, #11]
8001ef2: f003 0307 and.w r3, r3, #7
8001ef6: b2da uxtb r2, r3
8001ef8: 697b ldr r3, [r7, #20]
8001efa: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8001efc: 68fb ldr r3, [r7, #12]
8001efe: 681b ldr r3, [r3, #0]
8001f00: 6979 ldr r1, [r7, #20]
8001f02: 4618 mov r0, r3
8001f04: f003 fafa bl 80054fc <USB_EPStartXfer>
return HAL_OK;
8001f08: 2300 movs r3, #0
}
8001f0a: 4618 mov r0, r3
8001f0c: 3718 adds r7, #24
8001f0e: 46bd mov sp, r7
8001f10: bd80 pop {r7, pc}
08001f12 <HAL_PCD_EP_GetRxCount>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
8001f12: b480 push {r7}
8001f14: b083 sub sp, #12
8001f16: af00 add r7, sp, #0
8001f18: 6078 str r0, [r7, #4]
8001f1a: 460b mov r3, r1
8001f1c: 70fb strb r3, [r7, #3]
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
8001f1e: 78fb ldrb r3, [r7, #3]
8001f20: f003 0207 and.w r2, r3, #7
8001f24: 6879 ldr r1, [r7, #4]
8001f26: 4613 mov r3, r2
8001f28: 009b lsls r3, r3, #2
8001f2a: 4413 add r3, r2
8001f2c: 00db lsls r3, r3, #3
8001f2e: 440b add r3, r1
8001f30: f503 73b6 add.w r3, r3, #364 @ 0x16c
8001f34: 681b ldr r3, [r3, #0]
}
8001f36: 4618 mov r0, r3
8001f38: 370c adds r7, #12
8001f3a: 46bd mov sp, r7
8001f3c: bc80 pop {r7}
8001f3e: 4770 bx lr
08001f40 <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8001f40: b580 push {r7, lr}
8001f42: b086 sub sp, #24
8001f44: af00 add r7, sp, #0
8001f46: 60f8 str r0, [r7, #12]
8001f48: 607a str r2, [r7, #4]
8001f4a: 603b str r3, [r7, #0]
8001f4c: 460b mov r3, r1
8001f4e: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8001f50: 7afb ldrb r3, [r7, #11]
8001f52: f003 0207 and.w r2, r3, #7
8001f56: 4613 mov r3, r2
8001f58: 009b lsls r3, r3, #2
8001f5a: 4413 add r3, r2
8001f5c: 00db lsls r3, r3, #3
8001f5e: 3310 adds r3, #16
8001f60: 68fa ldr r2, [r7, #12]
8001f62: 4413 add r3, r2
8001f64: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8001f66: 697b ldr r3, [r7, #20]
8001f68: 687a ldr r2, [r7, #4]
8001f6a: 615a str r2, [r3, #20]
ep->xfer_len = len;
8001f6c: 697b ldr r3, [r7, #20]
8001f6e: 683a ldr r2, [r7, #0]
8001f70: 619a str r2, [r3, #24]
#if defined (USB)
ep->xfer_fill_db = 1U;
8001f72: 697b ldr r3, [r7, #20]
8001f74: 2201 movs r2, #1
8001f76: f883 2024 strb.w r2, [r3, #36] @ 0x24
ep->xfer_len_db = len;
8001f7a: 697b ldr r3, [r7, #20]
8001f7c: 683a ldr r2, [r7, #0]
8001f7e: 621a str r2, [r3, #32]
#endif /* defined (USB) */
ep->xfer_count = 0U;
8001f80: 697b ldr r3, [r7, #20]
8001f82: 2200 movs r2, #0
8001f84: 61da str r2, [r3, #28]
ep->is_in = 1U;
8001f86: 697b ldr r3, [r7, #20]
8001f88: 2201 movs r2, #1
8001f8a: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8001f8c: 7afb ldrb r3, [r7, #11]
8001f8e: f003 0307 and.w r3, r3, #7
8001f92: b2da uxtb r2, r3
8001f94: 697b ldr r3, [r7, #20]
8001f96: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8001f98: 68fb ldr r3, [r7, #12]
8001f9a: 681b ldr r3, [r3, #0]
8001f9c: 6979 ldr r1, [r7, #20]
8001f9e: 4618 mov r0, r3
8001fa0: f003 faac bl 80054fc <USB_EPStartXfer>
return HAL_OK;
8001fa4: 2300 movs r3, #0
}
8001fa6: 4618 mov r0, r3
8001fa8: 3718 adds r7, #24
8001faa: 46bd mov sp, r7
8001fac: bd80 pop {r7, pc}
08001fae <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8001fae: b580 push {r7, lr}
8001fb0: b084 sub sp, #16
8001fb2: af00 add r7, sp, #0
8001fb4: 6078 str r0, [r7, #4]
8001fb6: 460b mov r3, r1
8001fb8: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8001fba: 78fb ldrb r3, [r7, #3]
8001fbc: f003 0307 and.w r3, r3, #7
8001fc0: 687a ldr r2, [r7, #4]
8001fc2: 7912 ldrb r2, [r2, #4]
8001fc4: 4293 cmp r3, r2
8001fc6: d901 bls.n 8001fcc <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
8001fc8: 2301 movs r3, #1
8001fca: e04c b.n 8002066 <HAL_PCD_EP_SetStall+0xb8>
}
if ((0x80U & ep_addr) == 0x80U)
8001fcc: f997 3003 ldrsb.w r3, [r7, #3]
8001fd0: 2b00 cmp r3, #0
8001fd2: da0e bge.n 8001ff2 <HAL_PCD_EP_SetStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8001fd4: 78fb ldrb r3, [r7, #3]
8001fd6: f003 0207 and.w r2, r3, #7
8001fda: 4613 mov r3, r2
8001fdc: 009b lsls r3, r3, #2
8001fde: 4413 add r3, r2
8001fe0: 00db lsls r3, r3, #3
8001fe2: 3310 adds r3, #16
8001fe4: 687a ldr r2, [r7, #4]
8001fe6: 4413 add r3, r2
8001fe8: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8001fea: 68fb ldr r3, [r7, #12]
8001fec: 2201 movs r2, #1
8001fee: 705a strb r2, [r3, #1]
8001ff0: e00c b.n 800200c <HAL_PCD_EP_SetStall+0x5e>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8001ff2: 78fa ldrb r2, [r7, #3]
8001ff4: 4613 mov r3, r2
8001ff6: 009b lsls r3, r3, #2
8001ff8: 4413 add r3, r2
8001ffa: 00db lsls r3, r3, #3
8001ffc: f503 73a8 add.w r3, r3, #336 @ 0x150
8002000: 687a ldr r2, [r7, #4]
8002002: 4413 add r3, r2
8002004: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8002006: 68fb ldr r3, [r7, #12]
8002008: 2200 movs r2, #0
800200a: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
800200c: 68fb ldr r3, [r7, #12]
800200e: 2201 movs r2, #1
8002010: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8002012: 78fb ldrb r3, [r7, #3]
8002014: f003 0307 and.w r3, r3, #7
8002018: b2da uxtb r2, r3
800201a: 68fb ldr r3, [r7, #12]
800201c: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
800201e: 687b ldr r3, [r7, #4]
8002020: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8002024: 2b01 cmp r3, #1
8002026: d101 bne.n 800202c <HAL_PCD_EP_SetStall+0x7e>
8002028: 2302 movs r3, #2
800202a: e01c b.n 8002066 <HAL_PCD_EP_SetStall+0xb8>
800202c: 687b ldr r3, [r7, #4]
800202e: 2201 movs r2, #1
8002030: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPSetStall(hpcd->Instance, ep);
8002034: 687b ldr r3, [r7, #4]
8002036: 681b ldr r3, [r3, #0]
8002038: 68f9 ldr r1, [r7, #12]
800203a: 4618 mov r0, r3
800203c: f004 fe0f bl 8006c5e <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
8002040: 78fb ldrb r3, [r7, #3]
8002042: f003 0307 and.w r3, r3, #7
8002046: 2b00 cmp r3, #0
8002048: d108 bne.n 800205c <HAL_PCD_EP_SetStall+0xae>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
800204a: 687b ldr r3, [r7, #4]
800204c: 681a ldr r2, [r3, #0]
800204e: 687b ldr r3, [r7, #4]
8002050: f503 7326 add.w r3, r3, #664 @ 0x298
8002054: 4619 mov r1, r3
8002056: 4610 mov r0, r2
8002058: f004 ff34 bl 8006ec4 <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
800205c: 687b ldr r3, [r7, #4]
800205e: 2200 movs r2, #0
8002060: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8002064: 2300 movs r3, #0
}
8002066: 4618 mov r0, r3
8002068: 3710 adds r7, #16
800206a: 46bd mov sp, r7
800206c: bd80 pop {r7, pc}
0800206e <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
800206e: b580 push {r7, lr}
8002070: b084 sub sp, #16
8002072: af00 add r7, sp, #0
8002074: 6078 str r0, [r7, #4]
8002076: 460b mov r3, r1
8002078: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
800207a: 78fb ldrb r3, [r7, #3]
800207c: f003 030f and.w r3, r3, #15
8002080: 687a ldr r2, [r7, #4]
8002082: 7912 ldrb r2, [r2, #4]
8002084: 4293 cmp r3, r2
8002086: d901 bls.n 800208c <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
8002088: 2301 movs r3, #1
800208a: e040 b.n 800210e <HAL_PCD_EP_ClrStall+0xa0>
}
if ((0x80U & ep_addr) == 0x80U)
800208c: f997 3003 ldrsb.w r3, [r7, #3]
8002090: 2b00 cmp r3, #0
8002092: da0e bge.n 80020b2 <HAL_PCD_EP_ClrStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002094: 78fb ldrb r3, [r7, #3]
8002096: f003 0207 and.w r2, r3, #7
800209a: 4613 mov r3, r2
800209c: 009b lsls r3, r3, #2
800209e: 4413 add r3, r2
80020a0: 00db lsls r3, r3, #3
80020a2: 3310 adds r3, #16
80020a4: 687a ldr r2, [r7, #4]
80020a6: 4413 add r3, r2
80020a8: 60fb str r3, [r7, #12]
ep->is_in = 1U;
80020aa: 68fb ldr r3, [r7, #12]
80020ac: 2201 movs r2, #1
80020ae: 705a strb r2, [r3, #1]
80020b0: e00e b.n 80020d0 <HAL_PCD_EP_ClrStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
80020b2: 78fb ldrb r3, [r7, #3]
80020b4: f003 0207 and.w r2, r3, #7
80020b8: 4613 mov r3, r2
80020ba: 009b lsls r3, r3, #2
80020bc: 4413 add r3, r2
80020be: 00db lsls r3, r3, #3
80020c0: f503 73a8 add.w r3, r3, #336 @ 0x150
80020c4: 687a ldr r2, [r7, #4]
80020c6: 4413 add r3, r2
80020c8: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80020ca: 68fb ldr r3, [r7, #12]
80020cc: 2200 movs r2, #0
80020ce: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
80020d0: 68fb ldr r3, [r7, #12]
80020d2: 2200 movs r2, #0
80020d4: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
80020d6: 78fb ldrb r3, [r7, #3]
80020d8: f003 0307 and.w r3, r3, #7
80020dc: b2da uxtb r2, r3
80020de: 68fb ldr r3, [r7, #12]
80020e0: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80020e2: 687b ldr r3, [r7, #4]
80020e4: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
80020e8: 2b01 cmp r3, #1
80020ea: d101 bne.n 80020f0 <HAL_PCD_EP_ClrStall+0x82>
80020ec: 2302 movs r3, #2
80020ee: e00e b.n 800210e <HAL_PCD_EP_ClrStall+0xa0>
80020f0: 687b ldr r3, [r7, #4]
80020f2: 2201 movs r2, #1
80020f4: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPClearStall(hpcd->Instance, ep);
80020f8: 687b ldr r3, [r7, #4]
80020fa: 681b ldr r3, [r3, #0]
80020fc: 68f9 ldr r1, [r7, #12]
80020fe: 4618 mov r0, r3
8002100: f004 fdfd bl 8006cfe <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
8002104: 687b ldr r3, [r7, #4]
8002106: 2200 movs r2, #0
8002108: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
800210c: 2300 movs r3, #0
}
800210e: 4618 mov r0, r3
8002110: 3710 adds r7, #16
8002112: 46bd mov sp, r7
8002114: bd80 pop {r7, pc}
08002116 <PCD_EP_ISR_Handler>:
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
8002116: b580 push {r7, lr}
8002118: b096 sub sp, #88 @ 0x58
800211a: af00 add r7, sp, #0
800211c: 6078 str r0, [r7, #4]
#if (USE_USB_DOUBLE_BUFFER != 1U)
count = 0U;
#endif /* USE_USB_DOUBLE_BUFFER */
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
800211e: e3bb b.n 8002898 <PCD_EP_ISR_Handler+0x782>
{
wIstr = hpcd->Instance->ISTR;
8002120: 687b ldr r3, [r7, #4]
8002122: 681b ldr r3, [r3, #0]
8002124: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8002128: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
800212c: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8002130: b2db uxtb r3, r3
8002132: f003 030f and.w r3, r3, #15
8002136: f887 304d strb.w r3, [r7, #77] @ 0x4d
if (epindex == 0U)
800213a: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
800213e: 2b00 cmp r3, #0
8002140: f040 8175 bne.w 800242e <PCD_EP_ISR_Handler+0x318>
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
8002144: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8002148: f003 0310 and.w r3, r3, #16
800214c: 2b00 cmp r3, #0
800214e: d14e bne.n 80021ee <PCD_EP_ISR_Handler+0xd8>
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8002150: 687b ldr r3, [r7, #4]
8002152: 681b ldr r3, [r3, #0]
8002154: 881b ldrh r3, [r3, #0]
8002156: b29b uxth r3, r3
8002158: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
800215c: f023 0370 bic.w r3, r3, #112 @ 0x70
8002160: 81fb strh r3, [r7, #14]
8002162: 687b ldr r3, [r7, #4]
8002164: 681a ldr r2, [r3, #0]
8002166: 89fb ldrh r3, [r7, #14]
8002168: ea6f 4343 mvn.w r3, r3, lsl #17
800216c: ea6f 4353 mvn.w r3, r3, lsr #17
8002170: b29b uxth r3, r3
8002172: 8013 strh r3, [r2, #0]
ep = &hpcd->IN_ep[0];
8002174: 687b ldr r3, [r7, #4]
8002176: 3310 adds r3, #16
8002178: 657b str r3, [r7, #84] @ 0x54
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
800217a: 687b ldr r3, [r7, #4]
800217c: 681b ldr r3, [r3, #0]
800217e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002182: b29b uxth r3, r3
8002184: 461a mov r2, r3
8002186: 6d7b ldr r3, [r7, #84] @ 0x54
8002188: 781b ldrb r3, [r3, #0]
800218a: 00db lsls r3, r3, #3
800218c: 4413 add r3, r2
800218e: 3302 adds r3, #2
8002190: 005b lsls r3, r3, #1
8002192: 687a ldr r2, [r7, #4]
8002194: 6812 ldr r2, [r2, #0]
8002196: 4413 add r3, r2
8002198: f503 6380 add.w r3, r3, #1024 @ 0x400
800219c: 881b ldrh r3, [r3, #0]
800219e: f3c3 0209 ubfx r2, r3, #0, #10
80021a2: 6d7b ldr r3, [r7, #84] @ 0x54
80021a4: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
80021a6: 6d7b ldr r3, [r7, #84] @ 0x54
80021a8: 695a ldr r2, [r3, #20]
80021aa: 6d7b ldr r3, [r7, #84] @ 0x54
80021ac: 69db ldr r3, [r3, #28]
80021ae: 441a add r2, r3
80021b0: 6d7b ldr r3, [r7, #84] @ 0x54
80021b2: 615a str r2, [r3, #20]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
80021b4: 2100 movs r1, #0
80021b6: 6878 ldr r0, [r7, #4]
80021b8: f006 fd53 bl 8008c62 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
80021bc: 687b ldr r3, [r7, #4]
80021be: 7b5b ldrb r3, [r3, #13]
80021c0: b2db uxtb r3, r3
80021c2: 2b00 cmp r3, #0
80021c4: f000 8368 beq.w 8002898 <PCD_EP_ISR_Handler+0x782>
80021c8: 6d7b ldr r3, [r7, #84] @ 0x54
80021ca: 699b ldr r3, [r3, #24]
80021cc: 2b00 cmp r3, #0
80021ce: f040 8363 bne.w 8002898 <PCD_EP_ISR_Handler+0x782>
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
80021d2: 687b ldr r3, [r7, #4]
80021d4: 7b5b ldrb r3, [r3, #13]
80021d6: b2db uxtb r3, r3
80021d8: f063 037f orn r3, r3, #127 @ 0x7f
80021dc: b2da uxtb r2, r3
80021de: 687b ldr r3, [r7, #4]
80021e0: 681b ldr r3, [r3, #0]
80021e2: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
hpcd->USB_Address = 0U;
80021e6: 687b ldr r3, [r7, #4]
80021e8: 2200 movs r2, #0
80021ea: 735a strb r2, [r3, #13]
80021ec: e354 b.n 8002898 <PCD_EP_ISR_Handler+0x782>
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
80021ee: 687b ldr r3, [r7, #4]
80021f0: f503 73a8 add.w r3, r3, #336 @ 0x150
80021f4: 657b str r3, [r7, #84] @ 0x54
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
80021f6: 687b ldr r3, [r7, #4]
80021f8: 681b ldr r3, [r3, #0]
80021fa: 881b ldrh r3, [r3, #0]
80021fc: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_SETUP) != 0U)
8002200: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8002204: f403 6300 and.w r3, r3, #2048 @ 0x800
8002208: 2b00 cmp r3, #0
800220a: d034 beq.n 8002276 <PCD_EP_ISR_Handler+0x160>
{
/* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800220c: 687b ldr r3, [r7, #4]
800220e: 681b ldr r3, [r3, #0]
8002210: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002214: b29b uxth r3, r3
8002216: 461a mov r2, r3
8002218: 6d7b ldr r3, [r7, #84] @ 0x54
800221a: 781b ldrb r3, [r3, #0]
800221c: 00db lsls r3, r3, #3
800221e: 4413 add r3, r2
8002220: 3306 adds r3, #6
8002222: 005b lsls r3, r3, #1
8002224: 687a ldr r2, [r7, #4]
8002226: 6812 ldr r2, [r2, #0]
8002228: 4413 add r3, r2
800222a: f503 6380 add.w r3, r3, #1024 @ 0x400
800222e: 881b ldrh r3, [r3, #0]
8002230: f3c3 0209 ubfx r2, r3, #0, #10
8002234: 6d7b ldr r3, [r7, #84] @ 0x54
8002236: 61da str r2, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
8002238: 687b ldr r3, [r7, #4]
800223a: 6818 ldr r0, [r3, #0]
800223c: 687b ldr r3, [r7, #4]
800223e: f503 7126 add.w r1, r3, #664 @ 0x298
8002242: 6d7b ldr r3, [r7, #84] @ 0x54
8002244: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
8002246: 6d7b ldr r3, [r7, #84] @ 0x54
8002248: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
800224a: b29b uxth r3, r3
800224c: f004 fe8b bl 8006f66 <USB_ReadPMA>
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8002250: 687b ldr r3, [r7, #4]
8002252: 681b ldr r3, [r3, #0]
8002254: 881b ldrh r3, [r3, #0]
8002256: b29a uxth r2, r3
8002258: f640 738f movw r3, #3983 @ 0xf8f
800225c: 4013 ands r3, r2
800225e: 823b strh r3, [r7, #16]
8002260: 687b ldr r3, [r7, #4]
8002262: 681b ldr r3, [r3, #0]
8002264: 8a3a ldrh r2, [r7, #16]
8002266: f042 0280 orr.w r2, r2, #128 @ 0x80
800226a: b292 uxth r2, r2
800226c: 801a strh r2, [r3, #0]
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
800226e: 6878 ldr r0, [r7, #4]
8002270: f006 fcca bl 8008c08 <HAL_PCD_SetupStageCallback>
8002274: e310 b.n 8002898 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
8002276: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
800227a: 2b00 cmp r3, #0
800227c: f280 830c bge.w 8002898 <PCD_EP_ISR_Handler+0x782>
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8002280: 687b ldr r3, [r7, #4]
8002282: 681b ldr r3, [r3, #0]
8002284: 881b ldrh r3, [r3, #0]
8002286: b29a uxth r2, r3
8002288: f640 738f movw r3, #3983 @ 0xf8f
800228c: 4013 ands r3, r2
800228e: 83fb strh r3, [r7, #30]
8002290: 687b ldr r3, [r7, #4]
8002292: 681b ldr r3, [r3, #0]
8002294: 8bfa ldrh r2, [r7, #30]
8002296: f042 0280 orr.w r2, r2, #128 @ 0x80
800229a: b292 uxth r2, r2
800229c: 801a strh r2, [r3, #0]
/* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
800229e: 687b ldr r3, [r7, #4]
80022a0: 681b ldr r3, [r3, #0]
80022a2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80022a6: b29b uxth r3, r3
80022a8: 461a mov r2, r3
80022aa: 6d7b ldr r3, [r7, #84] @ 0x54
80022ac: 781b ldrb r3, [r3, #0]
80022ae: 00db lsls r3, r3, #3
80022b0: 4413 add r3, r2
80022b2: 3306 adds r3, #6
80022b4: 005b lsls r3, r3, #1
80022b6: 687a ldr r2, [r7, #4]
80022b8: 6812 ldr r2, [r2, #0]
80022ba: 4413 add r3, r2
80022bc: f503 6380 add.w r3, r3, #1024 @ 0x400
80022c0: 881b ldrh r3, [r3, #0]
80022c2: f3c3 0209 ubfx r2, r3, #0, #10
80022c6: 6d7b ldr r3, [r7, #84] @ 0x54
80022c8: 61da str r2, [r3, #28]
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
80022ca: 6d7b ldr r3, [r7, #84] @ 0x54
80022cc: 69db ldr r3, [r3, #28]
80022ce: 2b00 cmp r3, #0
80022d0: d019 beq.n 8002306 <PCD_EP_ISR_Handler+0x1f0>
80022d2: 6d7b ldr r3, [r7, #84] @ 0x54
80022d4: 695b ldr r3, [r3, #20]
80022d6: 2b00 cmp r3, #0
80022d8: d015 beq.n 8002306 <PCD_EP_ISR_Handler+0x1f0>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
80022da: 687b ldr r3, [r7, #4]
80022dc: 6818 ldr r0, [r3, #0]
80022de: 6d7b ldr r3, [r7, #84] @ 0x54
80022e0: 6959 ldr r1, [r3, #20]
80022e2: 6d7b ldr r3, [r7, #84] @ 0x54
80022e4: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
80022e6: 6d7b ldr r3, [r7, #84] @ 0x54
80022e8: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
80022ea: b29b uxth r3, r3
80022ec: f004 fe3b bl 8006f66 <USB_ReadPMA>
ep->xfer_buff += ep->xfer_count;
80022f0: 6d7b ldr r3, [r7, #84] @ 0x54
80022f2: 695a ldr r2, [r3, #20]
80022f4: 6d7b ldr r3, [r7, #84] @ 0x54
80022f6: 69db ldr r3, [r3, #28]
80022f8: 441a add r2, r3
80022fa: 6d7b ldr r3, [r7, #84] @ 0x54
80022fc: 615a str r2, [r3, #20]
/* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
80022fe: 2100 movs r1, #0
8002300: 6878 ldr r0, [r7, #4]
8002302: f006 fc93 bl 8008c2c <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
8002306: 687b ldr r3, [r7, #4]
8002308: 681b ldr r3, [r3, #0]
800230a: 881b ldrh r3, [r3, #0]
800230c: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
8002310: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8002314: f403 6300 and.w r3, r3, #2048 @ 0x800
8002318: 2b00 cmp r3, #0
800231a: f040 82bd bne.w 8002898 <PCD_EP_ISR_Handler+0x782>
800231e: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8002322: f403 5340 and.w r3, r3, #12288 @ 0x3000
8002326: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
800232a: f000 82b5 beq.w 8002898 <PCD_EP_ISR_Handler+0x782>
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
800232e: 687b ldr r3, [r7, #4]
8002330: 681b ldr r3, [r3, #0]
8002332: 61bb str r3, [r7, #24]
8002334: 687b ldr r3, [r7, #4]
8002336: 681b ldr r3, [r3, #0]
8002338: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800233c: b29b uxth r3, r3
800233e: 461a mov r2, r3
8002340: 69bb ldr r3, [r7, #24]
8002342: 4413 add r3, r2
8002344: 61bb str r3, [r7, #24]
8002346: 69bb ldr r3, [r7, #24]
8002348: f203 430c addw r3, r3, #1036 @ 0x40c
800234c: 617b str r3, [r7, #20]
800234e: 697b ldr r3, [r7, #20]
8002350: 881b ldrh r3, [r3, #0]
8002352: b29b uxth r3, r3
8002354: f3c3 0309 ubfx r3, r3, #0, #10
8002358: b29a uxth r2, r3
800235a: 697b ldr r3, [r7, #20]
800235c: 801a strh r2, [r3, #0]
800235e: 6d7b ldr r3, [r7, #84] @ 0x54
8002360: 691b ldr r3, [r3, #16]
8002362: 2b3e cmp r3, #62 @ 0x3e
8002364: d91d bls.n 80023a2 <PCD_EP_ISR_Handler+0x28c>
8002366: 6d7b ldr r3, [r7, #84] @ 0x54
8002368: 691b ldr r3, [r3, #16]
800236a: 095b lsrs r3, r3, #5
800236c: 647b str r3, [r7, #68] @ 0x44
800236e: 6d7b ldr r3, [r7, #84] @ 0x54
8002370: 691b ldr r3, [r3, #16]
8002372: f003 031f and.w r3, r3, #31
8002376: 2b00 cmp r3, #0
8002378: d102 bne.n 8002380 <PCD_EP_ISR_Handler+0x26a>
800237a: 6c7b ldr r3, [r7, #68] @ 0x44
800237c: 3b01 subs r3, #1
800237e: 647b str r3, [r7, #68] @ 0x44
8002380: 697b ldr r3, [r7, #20]
8002382: 881b ldrh r3, [r3, #0]
8002384: b29a uxth r2, r3
8002386: 6c7b ldr r3, [r7, #68] @ 0x44
8002388: b29b uxth r3, r3
800238a: 029b lsls r3, r3, #10
800238c: b29b uxth r3, r3
800238e: 4313 orrs r3, r2
8002390: b29b uxth r3, r3
8002392: ea6f 4343 mvn.w r3, r3, lsl #17
8002396: ea6f 4353 mvn.w r3, r3, lsr #17
800239a: b29a uxth r2, r3
800239c: 697b ldr r3, [r7, #20]
800239e: 801a strh r2, [r3, #0]
80023a0: e026 b.n 80023f0 <PCD_EP_ISR_Handler+0x2da>
80023a2: 6d7b ldr r3, [r7, #84] @ 0x54
80023a4: 691b ldr r3, [r3, #16]
80023a6: 2b00 cmp r3, #0
80023a8: d10a bne.n 80023c0 <PCD_EP_ISR_Handler+0x2aa>
80023aa: 697b ldr r3, [r7, #20]
80023ac: 881b ldrh r3, [r3, #0]
80023ae: b29b uxth r3, r3
80023b0: ea6f 4343 mvn.w r3, r3, lsl #17
80023b4: ea6f 4353 mvn.w r3, r3, lsr #17
80023b8: b29a uxth r2, r3
80023ba: 697b ldr r3, [r7, #20]
80023bc: 801a strh r2, [r3, #0]
80023be: e017 b.n 80023f0 <PCD_EP_ISR_Handler+0x2da>
80023c0: 6d7b ldr r3, [r7, #84] @ 0x54
80023c2: 691b ldr r3, [r3, #16]
80023c4: 085b lsrs r3, r3, #1
80023c6: 647b str r3, [r7, #68] @ 0x44
80023c8: 6d7b ldr r3, [r7, #84] @ 0x54
80023ca: 691b ldr r3, [r3, #16]
80023cc: f003 0301 and.w r3, r3, #1
80023d0: 2b00 cmp r3, #0
80023d2: d002 beq.n 80023da <PCD_EP_ISR_Handler+0x2c4>
80023d4: 6c7b ldr r3, [r7, #68] @ 0x44
80023d6: 3301 adds r3, #1
80023d8: 647b str r3, [r7, #68] @ 0x44
80023da: 697b ldr r3, [r7, #20]
80023dc: 881b ldrh r3, [r3, #0]
80023de: b29a uxth r2, r3
80023e0: 6c7b ldr r3, [r7, #68] @ 0x44
80023e2: b29b uxth r3, r3
80023e4: 029b lsls r3, r3, #10
80023e6: b29b uxth r3, r3
80023e8: 4313 orrs r3, r2
80023ea: b29a uxth r2, r3
80023ec: 697b ldr r3, [r7, #20]
80023ee: 801a strh r2, [r3, #0]
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
80023f0: 687b ldr r3, [r7, #4]
80023f2: 681b ldr r3, [r3, #0]
80023f4: 881b ldrh r3, [r3, #0]
80023f6: b29b uxth r3, r3
80023f8: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80023fc: f023 0370 bic.w r3, r3, #112 @ 0x70
8002400: 827b strh r3, [r7, #18]
8002402: 8a7b ldrh r3, [r7, #18]
8002404: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8002408: 827b strh r3, [r7, #18]
800240a: 8a7b ldrh r3, [r7, #18]
800240c: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8002410: 827b strh r3, [r7, #18]
8002412: 687b ldr r3, [r7, #4]
8002414: 681a ldr r2, [r3, #0]
8002416: 8a7b ldrh r3, [r7, #18]
8002418: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800241c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002420: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8002424: f043 0380 orr.w r3, r3, #128 @ 0x80
8002428: b29b uxth r3, r3
800242a: 8013 strh r3, [r2, #0]
800242c: e234 b.n 8002898 <PCD_EP_ISR_Handler+0x782>
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
800242e: 687b ldr r3, [r7, #4]
8002430: 681b ldr r3, [r3, #0]
8002432: 461a mov r2, r3
8002434: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8002438: 009b lsls r3, r3, #2
800243a: 4413 add r3, r2
800243c: 881b ldrh r3, [r3, #0]
800243e: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
if ((wEPVal & USB_EP_CTR_RX) != 0U)
8002442: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
8002446: 2b00 cmp r3, #0
8002448: f280 80fc bge.w 8002644 <PCD_EP_ISR_Handler+0x52e>
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
800244c: 687b ldr r3, [r7, #4]
800244e: 681b ldr r3, [r3, #0]
8002450: 461a mov r2, r3
8002452: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8002456: 009b lsls r3, r3, #2
8002458: 4413 add r3, r2
800245a: 881b ldrh r3, [r3, #0]
800245c: b29a uxth r2, r3
800245e: f640 738f movw r3, #3983 @ 0xf8f
8002462: 4013 ands r3, r2
8002464: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
8002468: 687b ldr r3, [r7, #4]
800246a: 681b ldr r3, [r3, #0]
800246c: 461a mov r2, r3
800246e: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8002472: 009b lsls r3, r3, #2
8002474: 4413 add r3, r2
8002476: f8b7 2048 ldrh.w r2, [r7, #72] @ 0x48
800247a: f042 0280 orr.w r2, r2, #128 @ 0x80
800247e: b292 uxth r2, r2
8002480: 801a strh r2, [r3, #0]
ep = &hpcd->OUT_ep[epindex];
8002482: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
8002486: 4613 mov r3, r2
8002488: 009b lsls r3, r3, #2
800248a: 4413 add r3, r2
800248c: 00db lsls r3, r3, #3
800248e: f503 73a8 add.w r3, r3, #336 @ 0x150
8002492: 687a ldr r2, [r7, #4]
8002494: 4413 add r3, r2
8002496: 657b str r3, [r7, #84] @ 0x54
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
8002498: 6d7b ldr r3, [r7, #84] @ 0x54
800249a: 7b1b ldrb r3, [r3, #12]
800249c: 2b00 cmp r3, #0
800249e: d125 bne.n 80024ec <PCD_EP_ISR_Handler+0x3d6>
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
80024a0: 687b ldr r3, [r7, #4]
80024a2: 681b ldr r3, [r3, #0]
80024a4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80024a8: b29b uxth r3, r3
80024aa: 461a mov r2, r3
80024ac: 6d7b ldr r3, [r7, #84] @ 0x54
80024ae: 781b ldrb r3, [r3, #0]
80024b0: 00db lsls r3, r3, #3
80024b2: 4413 add r3, r2
80024b4: 3306 adds r3, #6
80024b6: 005b lsls r3, r3, #1
80024b8: 687a ldr r2, [r7, #4]
80024ba: 6812 ldr r2, [r2, #0]
80024bc: 4413 add r3, r2
80024be: f503 6380 add.w r3, r3, #1024 @ 0x400
80024c2: 881b ldrh r3, [r3, #0]
80024c4: f3c3 0309 ubfx r3, r3, #0, #10
80024c8: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
80024cc: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80024d0: 2b00 cmp r3, #0
80024d2: f000 8092 beq.w 80025fa <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
80024d6: 687b ldr r3, [r7, #4]
80024d8: 6818 ldr r0, [r3, #0]
80024da: 6d7b ldr r3, [r7, #84] @ 0x54
80024dc: 6959 ldr r1, [r3, #20]
80024de: 6d7b ldr r3, [r7, #84] @ 0x54
80024e0: 88da ldrh r2, [r3, #6]
80024e2: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80024e6: f004 fd3e bl 8006f66 <USB_ReadPMA>
80024ea: e086 b.n 80025fa <PCD_EP_ISR_Handler+0x4e4>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
80024ec: 6d7b ldr r3, [r7, #84] @ 0x54
80024ee: 78db ldrb r3, [r3, #3]
80024f0: 2b02 cmp r3, #2
80024f2: d10a bne.n 800250a <PCD_EP_ISR_Handler+0x3f4>
{
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
80024f4: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80024f8: 461a mov r2, r3
80024fa: 6d79 ldr r1, [r7, #84] @ 0x54
80024fc: 6878 ldr r0, [r7, #4]
80024fe: f000 f9d9 bl 80028b4 <HAL_PCD_EP_DB_Receive>
8002502: 4603 mov r3, r0
8002504: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
8002508: e077 b.n 80025fa <PCD_EP_ISR_Handler+0x4e4>
}
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
800250a: 687b ldr r3, [r7, #4]
800250c: 681b ldr r3, [r3, #0]
800250e: 461a mov r2, r3
8002510: 6d7b ldr r3, [r7, #84] @ 0x54
8002512: 781b ldrb r3, [r3, #0]
8002514: 009b lsls r3, r3, #2
8002516: 4413 add r3, r2
8002518: 881b ldrh r3, [r3, #0]
800251a: b29b uxth r3, r3
800251c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002520: f023 0370 bic.w r3, r3, #112 @ 0x70
8002524: f8a7 3052 strh.w r3, [r7, #82] @ 0x52
8002528: 687b ldr r3, [r7, #4]
800252a: 681b ldr r3, [r3, #0]
800252c: 461a mov r2, r3
800252e: 6d7b ldr r3, [r7, #84] @ 0x54
8002530: 781b ldrb r3, [r3, #0]
8002532: 009b lsls r3, r3, #2
8002534: 441a add r2, r3
8002536: f8b7 3052 ldrh.w r3, [r7, #82] @ 0x52
800253a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800253e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002542: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8002546: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800254a: b29b uxth r3, r3
800254c: 8013 strh r3, [r2, #0]
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
800254e: 687b ldr r3, [r7, #4]
8002550: 681b ldr r3, [r3, #0]
8002552: 461a mov r2, r3
8002554: 6d7b ldr r3, [r7, #84] @ 0x54
8002556: 781b ldrb r3, [r3, #0]
8002558: 009b lsls r3, r3, #2
800255a: 4413 add r3, r2
800255c: 881b ldrh r3, [r3, #0]
800255e: b29b uxth r3, r3
8002560: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002564: 2b00 cmp r3, #0
8002566: d024 beq.n 80025b2 <PCD_EP_ISR_Handler+0x49c>
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8002568: 687b ldr r3, [r7, #4]
800256a: 681b ldr r3, [r3, #0]
800256c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002570: b29b uxth r3, r3
8002572: 461a mov r2, r3
8002574: 6d7b ldr r3, [r7, #84] @ 0x54
8002576: 781b ldrb r3, [r3, #0]
8002578: 00db lsls r3, r3, #3
800257a: 4413 add r3, r2
800257c: 3302 adds r3, #2
800257e: 005b lsls r3, r3, #1
8002580: 687a ldr r2, [r7, #4]
8002582: 6812 ldr r2, [r2, #0]
8002584: 4413 add r3, r2
8002586: f503 6380 add.w r3, r3, #1024 @ 0x400
800258a: 881b ldrh r3, [r3, #0]
800258c: f3c3 0309 ubfx r3, r3, #0, #10
8002590: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
8002594: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8002598: 2b00 cmp r3, #0
800259a: d02e beq.n 80025fa <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
800259c: 687b ldr r3, [r7, #4]
800259e: 6818 ldr r0, [r3, #0]
80025a0: 6d7b ldr r3, [r7, #84] @ 0x54
80025a2: 6959 ldr r1, [r3, #20]
80025a4: 6d7b ldr r3, [r7, #84] @ 0x54
80025a6: 891a ldrh r2, [r3, #8]
80025a8: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80025ac: f004 fcdb bl 8006f66 <USB_ReadPMA>
80025b0: e023 b.n 80025fa <PCD_EP_ISR_Handler+0x4e4>
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
80025b2: 687b ldr r3, [r7, #4]
80025b4: 681b ldr r3, [r3, #0]
80025b6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80025ba: b29b uxth r3, r3
80025bc: 461a mov r2, r3
80025be: 6d7b ldr r3, [r7, #84] @ 0x54
80025c0: 781b ldrb r3, [r3, #0]
80025c2: 00db lsls r3, r3, #3
80025c4: 4413 add r3, r2
80025c6: 3306 adds r3, #6
80025c8: 005b lsls r3, r3, #1
80025ca: 687a ldr r2, [r7, #4]
80025cc: 6812 ldr r2, [r2, #0]
80025ce: 4413 add r3, r2
80025d0: f503 6380 add.w r3, r3, #1024 @ 0x400
80025d4: 881b ldrh r3, [r3, #0]
80025d6: f3c3 0309 ubfx r3, r3, #0, #10
80025da: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
if (count != 0U)
80025de: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80025e2: 2b00 cmp r3, #0
80025e4: d009 beq.n 80025fa <PCD_EP_ISR_Handler+0x4e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
80025e6: 687b ldr r3, [r7, #4]
80025e8: 6818 ldr r0, [r3, #0]
80025ea: 6d7b ldr r3, [r7, #84] @ 0x54
80025ec: 6959 ldr r1, [r3, #20]
80025ee: 6d7b ldr r3, [r7, #84] @ 0x54
80025f0: 895a ldrh r2, [r3, #10]
80025f2: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
80025f6: f004 fcb6 bl 8006f66 <USB_ReadPMA>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
80025fa: 6d7b ldr r3, [r7, #84] @ 0x54
80025fc: 69da ldr r2, [r3, #28]
80025fe: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8002602: 441a add r2, r3
8002604: 6d7b ldr r3, [r7, #84] @ 0x54
8002606: 61da str r2, [r3, #28]
ep->xfer_buff += count;
8002608: 6d7b ldr r3, [r7, #84] @ 0x54
800260a: 695a ldr r2, [r3, #20]
800260c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
8002610: 441a add r2, r3
8002612: 6d7b ldr r3, [r7, #84] @ 0x54
8002614: 615a str r2, [r3, #20]
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
8002616: 6d7b ldr r3, [r7, #84] @ 0x54
8002618: 699b ldr r3, [r3, #24]
800261a: 2b00 cmp r3, #0
800261c: d005 beq.n 800262a <PCD_EP_ISR_Handler+0x514>
800261e: f8b7 2050 ldrh.w r2, [r7, #80] @ 0x50
8002622: 6d7b ldr r3, [r7, #84] @ 0x54
8002624: 691b ldr r3, [r3, #16]
8002626: 429a cmp r2, r3
8002628: d206 bcs.n 8002638 <PCD_EP_ISR_Handler+0x522>
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
800262a: 6d7b ldr r3, [r7, #84] @ 0x54
800262c: 781b ldrb r3, [r3, #0]
800262e: 4619 mov r1, r3
8002630: 6878 ldr r0, [r7, #4]
8002632: f006 fafb bl 8008c2c <HAL_PCD_DataOutStageCallback>
8002636: e005 b.n 8002644 <PCD_EP_ISR_Handler+0x52e>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
8002638: 687b ldr r3, [r7, #4]
800263a: 681b ldr r3, [r3, #0]
800263c: 6d79 ldr r1, [r7, #84] @ 0x54
800263e: 4618 mov r0, r3
8002640: f002 ff5c bl 80054fc <USB_EPStartXfer>
}
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
8002644: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8002648: f003 0380 and.w r3, r3, #128 @ 0x80
800264c: 2b00 cmp r3, #0
800264e: f000 8123 beq.w 8002898 <PCD_EP_ISR_Handler+0x782>
{
ep = &hpcd->IN_ep[epindex];
8002652: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
8002656: 4613 mov r3, r2
8002658: 009b lsls r3, r3, #2
800265a: 4413 add r3, r2
800265c: 00db lsls r3, r3, #3
800265e: 3310 adds r3, #16
8002660: 687a ldr r2, [r7, #4]
8002662: 4413 add r3, r2
8002664: 657b str r3, [r7, #84] @ 0x54
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
8002666: 687b ldr r3, [r7, #4]
8002668: 681b ldr r3, [r3, #0]
800266a: 461a mov r2, r3
800266c: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
8002670: 009b lsls r3, r3, #2
8002672: 4413 add r3, r2
8002674: 881b ldrh r3, [r3, #0]
8002676: b29b uxth r3, r3
8002678: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
800267c: f023 0370 bic.w r3, r3, #112 @ 0x70
8002680: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
8002684: 687b ldr r3, [r7, #4]
8002686: 681b ldr r3, [r3, #0]
8002688: 461a mov r2, r3
800268a: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
800268e: 009b lsls r3, r3, #2
8002690: 441a add r2, r3
8002692: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
8002696: ea6f 4343 mvn.w r3, r3, lsl #17
800269a: ea6f 4353 mvn.w r3, r3, lsr #17
800269e: b29b uxth r3, r3
80026a0: 8013 strh r3, [r2, #0]
if (ep->type == EP_TYPE_ISOC)
80026a2: 6d7b ldr r3, [r7, #84] @ 0x54
80026a4: 78db ldrb r3, [r3, #3]
80026a6: 2b01 cmp r3, #1
80026a8: f040 80a2 bne.w 80027f0 <PCD_EP_ISR_Handler+0x6da>
{
ep->xfer_len = 0U;
80026ac: 6d7b ldr r3, [r7, #84] @ 0x54
80026ae: 2200 movs r2, #0
80026b0: 619a str r2, [r3, #24]
#if (USE_USB_DOUBLE_BUFFER == 1U)
if (ep->doublebuffer != 0U)
80026b2: 6d7b ldr r3, [r7, #84] @ 0x54
80026b4: 7b1b ldrb r3, [r3, #12]
80026b6: 2b00 cmp r3, #0
80026b8: f000 8093 beq.w 80027e2 <PCD_EP_ISR_Handler+0x6cc>
{
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
80026bc: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80026c0: f003 0340 and.w r3, r3, #64 @ 0x40
80026c4: 2b00 cmp r3, #0
80026c6: d046 beq.n 8002756 <PCD_EP_ISR_Handler+0x640>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80026c8: 6d7b ldr r3, [r7, #84] @ 0x54
80026ca: 785b ldrb r3, [r3, #1]
80026cc: 2b00 cmp r3, #0
80026ce: d126 bne.n 800271e <PCD_EP_ISR_Handler+0x608>
80026d0: 687b ldr r3, [r7, #4]
80026d2: 681b ldr r3, [r3, #0]
80026d4: 627b str r3, [r7, #36] @ 0x24
80026d6: 687b ldr r3, [r7, #4]
80026d8: 681b ldr r3, [r3, #0]
80026da: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80026de: b29b uxth r3, r3
80026e0: 461a mov r2, r3
80026e2: 6a7b ldr r3, [r7, #36] @ 0x24
80026e4: 4413 add r3, r2
80026e6: 627b str r3, [r7, #36] @ 0x24
80026e8: 6d7b ldr r3, [r7, #84] @ 0x54
80026ea: 781b ldrb r3, [r3, #0]
80026ec: 011a lsls r2, r3, #4
80026ee: 6a7b ldr r3, [r7, #36] @ 0x24
80026f0: 4413 add r3, r2
80026f2: f203 4304 addw r3, r3, #1028 @ 0x404
80026f6: 623b str r3, [r7, #32]
80026f8: 6a3b ldr r3, [r7, #32]
80026fa: 881b ldrh r3, [r3, #0]
80026fc: b29b uxth r3, r3
80026fe: f3c3 0309 ubfx r3, r3, #0, #10
8002702: b29a uxth r2, r3
8002704: 6a3b ldr r3, [r7, #32]
8002706: 801a strh r2, [r3, #0]
8002708: 6a3b ldr r3, [r7, #32]
800270a: 881b ldrh r3, [r3, #0]
800270c: b29b uxth r3, r3
800270e: ea6f 4343 mvn.w r3, r3, lsl #17
8002712: ea6f 4353 mvn.w r3, r3, lsr #17
8002716: b29a uxth r2, r3
8002718: 6a3b ldr r3, [r7, #32]
800271a: 801a strh r2, [r3, #0]
800271c: e061 b.n 80027e2 <PCD_EP_ISR_Handler+0x6cc>
800271e: 6d7b ldr r3, [r7, #84] @ 0x54
8002720: 785b ldrb r3, [r3, #1]
8002722: 2b01 cmp r3, #1
8002724: d15d bne.n 80027e2 <PCD_EP_ISR_Handler+0x6cc>
8002726: 687b ldr r3, [r7, #4]
8002728: 681b ldr r3, [r3, #0]
800272a: 62fb str r3, [r7, #44] @ 0x2c
800272c: 687b ldr r3, [r7, #4]
800272e: 681b ldr r3, [r3, #0]
8002730: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002734: b29b uxth r3, r3
8002736: 461a mov r2, r3
8002738: 6afb ldr r3, [r7, #44] @ 0x2c
800273a: 4413 add r3, r2
800273c: 62fb str r3, [r7, #44] @ 0x2c
800273e: 6d7b ldr r3, [r7, #84] @ 0x54
8002740: 781b ldrb r3, [r3, #0]
8002742: 011a lsls r2, r3, #4
8002744: 6afb ldr r3, [r7, #44] @ 0x2c
8002746: 4413 add r3, r2
8002748: f203 4304 addw r3, r3, #1028 @ 0x404
800274c: 62bb str r3, [r7, #40] @ 0x28
800274e: 6abb ldr r3, [r7, #40] @ 0x28
8002750: 2200 movs r2, #0
8002752: 801a strh r2, [r3, #0]
8002754: e045 b.n 80027e2 <PCD_EP_ISR_Handler+0x6cc>
}
else
{
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8002756: 687b ldr r3, [r7, #4]
8002758: 681b ldr r3, [r3, #0]
800275a: 63fb str r3, [r7, #60] @ 0x3c
800275c: 6d7b ldr r3, [r7, #84] @ 0x54
800275e: 785b ldrb r3, [r3, #1]
8002760: 2b00 cmp r3, #0
8002762: d126 bne.n 80027b2 <PCD_EP_ISR_Handler+0x69c>
8002764: 687b ldr r3, [r7, #4]
8002766: 681b ldr r3, [r3, #0]
8002768: 637b str r3, [r7, #52] @ 0x34
800276a: 687b ldr r3, [r7, #4]
800276c: 681b ldr r3, [r3, #0]
800276e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002772: b29b uxth r3, r3
8002774: 461a mov r2, r3
8002776: 6b7b ldr r3, [r7, #52] @ 0x34
8002778: 4413 add r3, r2
800277a: 637b str r3, [r7, #52] @ 0x34
800277c: 6d7b ldr r3, [r7, #84] @ 0x54
800277e: 781b ldrb r3, [r3, #0]
8002780: 011a lsls r2, r3, #4
8002782: 6b7b ldr r3, [r7, #52] @ 0x34
8002784: 4413 add r3, r2
8002786: f203 430c addw r3, r3, #1036 @ 0x40c
800278a: 633b str r3, [r7, #48] @ 0x30
800278c: 6b3b ldr r3, [r7, #48] @ 0x30
800278e: 881b ldrh r3, [r3, #0]
8002790: b29b uxth r3, r3
8002792: f3c3 0309 ubfx r3, r3, #0, #10
8002796: b29a uxth r2, r3
8002798: 6b3b ldr r3, [r7, #48] @ 0x30
800279a: 801a strh r2, [r3, #0]
800279c: 6b3b ldr r3, [r7, #48] @ 0x30
800279e: 881b ldrh r3, [r3, #0]
80027a0: b29b uxth r3, r3
80027a2: ea6f 4343 mvn.w r3, r3, lsl #17
80027a6: ea6f 4353 mvn.w r3, r3, lsr #17
80027aa: b29a uxth r2, r3
80027ac: 6b3b ldr r3, [r7, #48] @ 0x30
80027ae: 801a strh r2, [r3, #0]
80027b0: e017 b.n 80027e2 <PCD_EP_ISR_Handler+0x6cc>
80027b2: 6d7b ldr r3, [r7, #84] @ 0x54
80027b4: 785b ldrb r3, [r3, #1]
80027b6: 2b01 cmp r3, #1
80027b8: d113 bne.n 80027e2 <PCD_EP_ISR_Handler+0x6cc>
80027ba: 687b ldr r3, [r7, #4]
80027bc: 681b ldr r3, [r3, #0]
80027be: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80027c2: b29b uxth r3, r3
80027c4: 461a mov r2, r3
80027c6: 6bfb ldr r3, [r7, #60] @ 0x3c
80027c8: 4413 add r3, r2
80027ca: 63fb str r3, [r7, #60] @ 0x3c
80027cc: 6d7b ldr r3, [r7, #84] @ 0x54
80027ce: 781b ldrb r3, [r3, #0]
80027d0: 011a lsls r2, r3, #4
80027d2: 6bfb ldr r3, [r7, #60] @ 0x3c
80027d4: 4413 add r3, r2
80027d6: f203 430c addw r3, r3, #1036 @ 0x40c
80027da: 63bb str r3, [r7, #56] @ 0x38
80027dc: 6bbb ldr r3, [r7, #56] @ 0x38
80027de: 2200 movs r2, #0
80027e0: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80027e2: 6d7b ldr r3, [r7, #84] @ 0x54
80027e4: 781b ldrb r3, [r3, #0]
80027e6: 4619 mov r1, r3
80027e8: 6878 ldr r0, [r7, #4]
80027ea: f006 fa3a bl 8008c62 <HAL_PCD_DataInStageCallback>
80027ee: e053 b.n 8002898 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
80027f0: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
80027f4: f403 7380 and.w r3, r3, #256 @ 0x100
80027f8: 2b00 cmp r3, #0
80027fa: d146 bne.n 800288a <PCD_EP_ISR_Handler+0x774>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
80027fc: 687b ldr r3, [r7, #4]
80027fe: 681b ldr r3, [r3, #0]
8002800: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002804: b29b uxth r3, r3
8002806: 461a mov r2, r3
8002808: 6d7b ldr r3, [r7, #84] @ 0x54
800280a: 781b ldrb r3, [r3, #0]
800280c: 00db lsls r3, r3, #3
800280e: 4413 add r3, r2
8002810: 3302 adds r3, #2
8002812: 005b lsls r3, r3, #1
8002814: 687a ldr r2, [r7, #4]
8002816: 6812 ldr r2, [r2, #0]
8002818: 4413 add r3, r2
800281a: f503 6380 add.w r3, r3, #1024 @ 0x400
800281e: 881b ldrh r3, [r3, #0]
8002820: f3c3 0309 ubfx r3, r3, #0, #10
8002824: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
if (ep->xfer_len > TxPctSize)
8002828: 6d7b ldr r3, [r7, #84] @ 0x54
800282a: 699a ldr r2, [r3, #24]
800282c: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8002830: 429a cmp r2, r3
8002832: d907 bls.n 8002844 <PCD_EP_ISR_Handler+0x72e>
{
ep->xfer_len -= TxPctSize;
8002834: 6d7b ldr r3, [r7, #84] @ 0x54
8002836: 699a ldr r2, [r3, #24]
8002838: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
800283c: 1ad2 subs r2, r2, r3
800283e: 6d7b ldr r3, [r7, #84] @ 0x54
8002840: 619a str r2, [r3, #24]
8002842: e002 b.n 800284a <PCD_EP_ISR_Handler+0x734>
}
else
{
ep->xfer_len = 0U;
8002844: 6d7b ldr r3, [r7, #84] @ 0x54
8002846: 2200 movs r2, #0
8002848: 619a str r2, [r3, #24]
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
800284a: 6d7b ldr r3, [r7, #84] @ 0x54
800284c: 699b ldr r3, [r3, #24]
800284e: 2b00 cmp r3, #0
8002850: d106 bne.n 8002860 <PCD_EP_ISR_Handler+0x74a>
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8002852: 6d7b ldr r3, [r7, #84] @ 0x54
8002854: 781b ldrb r3, [r3, #0]
8002856: 4619 mov r1, r3
8002858: 6878 ldr r0, [r7, #4]
800285a: f006 fa02 bl 8008c62 <HAL_PCD_DataInStageCallback>
800285e: e01b b.n 8002898 <PCD_EP_ISR_Handler+0x782>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxPctSize;
8002860: 6d7b ldr r3, [r7, #84] @ 0x54
8002862: 695a ldr r2, [r3, #20]
8002864: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8002868: 441a add r2, r3
800286a: 6d7b ldr r3, [r7, #84] @ 0x54
800286c: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
800286e: 6d7b ldr r3, [r7, #84] @ 0x54
8002870: 69da ldr r2, [r3, #28]
8002872: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8002876: 441a add r2, r3
8002878: 6d7b ldr r3, [r7, #84] @ 0x54
800287a: 61da str r2, [r3, #28]
(void)USB_EPStartXfer(hpcd->Instance, ep);
800287c: 687b ldr r3, [r7, #4]
800287e: 681b ldr r3, [r3, #0]
8002880: 6d79 ldr r1, [r7, #84] @ 0x54
8002882: 4618 mov r0, r3
8002884: f002 fe3a bl 80054fc <USB_EPStartXfer>
8002888: e006 b.n 8002898 <PCD_EP_ISR_Handler+0x782>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
800288a: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
800288e: 461a mov r2, r3
8002890: 6d79 ldr r1, [r7, #84] @ 0x54
8002892: 6878 ldr r0, [r7, #4]
8002894: f000 f91b bl 8002ace <HAL_PCD_EP_DB_Transmit>
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8002898: 687b ldr r3, [r7, #4]
800289a: 681b ldr r3, [r3, #0]
800289c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80028a0: b29b uxth r3, r3
80028a2: b21b sxth r3, r3
80028a4: 2b00 cmp r3, #0
80028a6: f6ff ac3b blt.w 8002120 <PCD_EP_ISR_Handler+0xa>
}
}
}
}
return HAL_OK;
80028aa: 2300 movs r3, #0
}
80028ac: 4618 mov r0, r3
80028ae: 3758 adds r7, #88 @ 0x58
80028b0: 46bd mov sp, r7
80028b2: bd80 pop {r7, pc}
080028b4 <HAL_PCD_EP_DB_Receive>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
80028b4: b580 push {r7, lr}
80028b6: b088 sub sp, #32
80028b8: af00 add r7, sp, #0
80028ba: 60f8 str r0, [r7, #12]
80028bc: 60b9 str r1, [r7, #8]
80028be: 4613 mov r3, r2
80028c0: 80fb strh r3, [r7, #6]
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
80028c2: 88fb ldrh r3, [r7, #6]
80028c4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80028c8: 2b00 cmp r3, #0
80028ca: d07e beq.n 80029ca <HAL_PCD_EP_DB_Receive+0x116>
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
80028cc: 68fb ldr r3, [r7, #12]
80028ce: 681b ldr r3, [r3, #0]
80028d0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80028d4: b29b uxth r3, r3
80028d6: 461a mov r2, r3
80028d8: 68bb ldr r3, [r7, #8]
80028da: 781b ldrb r3, [r3, #0]
80028dc: 00db lsls r3, r3, #3
80028de: 4413 add r3, r2
80028e0: 3302 adds r3, #2
80028e2: 005b lsls r3, r3, #1
80028e4: 68fa ldr r2, [r7, #12]
80028e6: 6812 ldr r2, [r2, #0]
80028e8: 4413 add r3, r2
80028ea: f503 6380 add.w r3, r3, #1024 @ 0x400
80028ee: 881b ldrh r3, [r3, #0]
80028f0: f3c3 0309 ubfx r3, r3, #0, #10
80028f4: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
80028f6: 68bb ldr r3, [r7, #8]
80028f8: 699a ldr r2, [r3, #24]
80028fa: 8b7b ldrh r3, [r7, #26]
80028fc: 429a cmp r2, r3
80028fe: d306 bcc.n 800290e <HAL_PCD_EP_DB_Receive+0x5a>
{
ep->xfer_len -= count;
8002900: 68bb ldr r3, [r7, #8]
8002902: 699a ldr r2, [r3, #24]
8002904: 8b7b ldrh r3, [r7, #26]
8002906: 1ad2 subs r2, r2, r3
8002908: 68bb ldr r3, [r7, #8]
800290a: 619a str r2, [r3, #24]
800290c: e002 b.n 8002914 <HAL_PCD_EP_DB_Receive+0x60>
}
else
{
ep->xfer_len = 0U;
800290e: 68bb ldr r3, [r7, #8]
8002910: 2200 movs r2, #0
8002912: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8002914: 68bb ldr r3, [r7, #8]
8002916: 699b ldr r3, [r3, #24]
8002918: 2b00 cmp r3, #0
800291a: d123 bne.n 8002964 <HAL_PCD_EP_DB_Receive+0xb0>
{
/* set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
800291c: 68fb ldr r3, [r7, #12]
800291e: 681b ldr r3, [r3, #0]
8002920: 461a mov r2, r3
8002922: 68bb ldr r3, [r7, #8]
8002924: 781b ldrb r3, [r3, #0]
8002926: 009b lsls r3, r3, #2
8002928: 4413 add r3, r2
800292a: 881b ldrh r3, [r3, #0]
800292c: b29b uxth r3, r3
800292e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8002932: f023 0370 bic.w r3, r3, #112 @ 0x70
8002936: 833b strh r3, [r7, #24]
8002938: 8b3b ldrh r3, [r7, #24]
800293a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800293e: 833b strh r3, [r7, #24]
8002940: 68fb ldr r3, [r7, #12]
8002942: 681b ldr r3, [r3, #0]
8002944: 461a mov r2, r3
8002946: 68bb ldr r3, [r7, #8]
8002948: 781b ldrb r3, [r3, #0]
800294a: 009b lsls r3, r3, #2
800294c: 441a add r2, r3
800294e: 8b3b ldrh r3, [r7, #24]
8002950: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8002954: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002958: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800295c: f043 0380 orr.w r3, r3, #128 @ 0x80
8002960: b29b uxth r3, r3
8002962: 8013 strh r3, [r2, #0]
}
/* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8002964: 88fb ldrh r3, [r7, #6]
8002966: f003 0340 and.w r3, r3, #64 @ 0x40
800296a: 2b00 cmp r3, #0
800296c: d01f beq.n 80029ae <HAL_PCD_EP_DB_Receive+0xfa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
800296e: 68fb ldr r3, [r7, #12]
8002970: 681b ldr r3, [r3, #0]
8002972: 461a mov r2, r3
8002974: 68bb ldr r3, [r7, #8]
8002976: 781b ldrb r3, [r3, #0]
8002978: 009b lsls r3, r3, #2
800297a: 4413 add r3, r2
800297c: 881b ldrh r3, [r3, #0]
800297e: b29b uxth r3, r3
8002980: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002984: f023 0370 bic.w r3, r3, #112 @ 0x70
8002988: 82fb strh r3, [r7, #22]
800298a: 68fb ldr r3, [r7, #12]
800298c: 681b ldr r3, [r3, #0]
800298e: 461a mov r2, r3
8002990: 68bb ldr r3, [r7, #8]
8002992: 781b ldrb r3, [r3, #0]
8002994: 009b lsls r3, r3, #2
8002996: 441a add r2, r3
8002998: 8afb ldrh r3, [r7, #22]
800299a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800299e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80029a2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80029a6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80029aa: b29b uxth r3, r3
80029ac: 8013 strh r3, [r2, #0]
}
if (count != 0U)
80029ae: 8b7b ldrh r3, [r7, #26]
80029b0: 2b00 cmp r3, #0
80029b2: f000 8087 beq.w 8002ac4 <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
80029b6: 68fb ldr r3, [r7, #12]
80029b8: 6818 ldr r0, [r3, #0]
80029ba: 68bb ldr r3, [r7, #8]
80029bc: 6959 ldr r1, [r3, #20]
80029be: 68bb ldr r3, [r7, #8]
80029c0: 891a ldrh r2, [r3, #8]
80029c2: 8b7b ldrh r3, [r7, #26]
80029c4: f004 facf bl 8006f66 <USB_ReadPMA>
80029c8: e07c b.n 8002ac4 <HAL_PCD_EP_DB_Receive+0x210>
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
80029ca: 68fb ldr r3, [r7, #12]
80029cc: 681b ldr r3, [r3, #0]
80029ce: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80029d2: b29b uxth r3, r3
80029d4: 461a mov r2, r3
80029d6: 68bb ldr r3, [r7, #8]
80029d8: 781b ldrb r3, [r3, #0]
80029da: 00db lsls r3, r3, #3
80029dc: 4413 add r3, r2
80029de: 3306 adds r3, #6
80029e0: 005b lsls r3, r3, #1
80029e2: 68fa ldr r2, [r7, #12]
80029e4: 6812 ldr r2, [r2, #0]
80029e6: 4413 add r3, r2
80029e8: f503 6380 add.w r3, r3, #1024 @ 0x400
80029ec: 881b ldrh r3, [r3, #0]
80029ee: f3c3 0309 ubfx r3, r3, #0, #10
80029f2: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
80029f4: 68bb ldr r3, [r7, #8]
80029f6: 699a ldr r2, [r3, #24]
80029f8: 8b7b ldrh r3, [r7, #26]
80029fa: 429a cmp r2, r3
80029fc: d306 bcc.n 8002a0c <HAL_PCD_EP_DB_Receive+0x158>
{
ep->xfer_len -= count;
80029fe: 68bb ldr r3, [r7, #8]
8002a00: 699a ldr r2, [r3, #24]
8002a02: 8b7b ldrh r3, [r7, #26]
8002a04: 1ad2 subs r2, r2, r3
8002a06: 68bb ldr r3, [r7, #8]
8002a08: 619a str r2, [r3, #24]
8002a0a: e002 b.n 8002a12 <HAL_PCD_EP_DB_Receive+0x15e>
}
else
{
ep->xfer_len = 0U;
8002a0c: 68bb ldr r3, [r7, #8]
8002a0e: 2200 movs r2, #0
8002a10: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8002a12: 68bb ldr r3, [r7, #8]
8002a14: 699b ldr r3, [r3, #24]
8002a16: 2b00 cmp r3, #0
8002a18: d123 bne.n 8002a62 <HAL_PCD_EP_DB_Receive+0x1ae>
{
/* set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
8002a1a: 68fb ldr r3, [r7, #12]
8002a1c: 681b ldr r3, [r3, #0]
8002a1e: 461a mov r2, r3
8002a20: 68bb ldr r3, [r7, #8]
8002a22: 781b ldrb r3, [r3, #0]
8002a24: 009b lsls r3, r3, #2
8002a26: 4413 add r3, r2
8002a28: 881b ldrh r3, [r3, #0]
8002a2a: b29b uxth r3, r3
8002a2c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8002a30: f023 0370 bic.w r3, r3, #112 @ 0x70
8002a34: 83fb strh r3, [r7, #30]
8002a36: 8bfb ldrh r3, [r7, #30]
8002a38: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8002a3c: 83fb strh r3, [r7, #30]
8002a3e: 68fb ldr r3, [r7, #12]
8002a40: 681b ldr r3, [r3, #0]
8002a42: 461a mov r2, r3
8002a44: 68bb ldr r3, [r7, #8]
8002a46: 781b ldrb r3, [r3, #0]
8002a48: 009b lsls r3, r3, #2
8002a4a: 441a add r2, r3
8002a4c: 8bfb ldrh r3, [r7, #30]
8002a4e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8002a52: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002a56: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8002a5a: f043 0380 orr.w r3, r3, #128 @ 0x80
8002a5e: b29b uxth r3, r3
8002a60: 8013 strh r3, [r2, #0]
}
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
8002a62: 88fb ldrh r3, [r7, #6]
8002a64: f003 0340 and.w r3, r3, #64 @ 0x40
8002a68: 2b00 cmp r3, #0
8002a6a: d11f bne.n 8002aac <HAL_PCD_EP_DB_Receive+0x1f8>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8002a6c: 68fb ldr r3, [r7, #12]
8002a6e: 681b ldr r3, [r3, #0]
8002a70: 461a mov r2, r3
8002a72: 68bb ldr r3, [r7, #8]
8002a74: 781b ldrb r3, [r3, #0]
8002a76: 009b lsls r3, r3, #2
8002a78: 4413 add r3, r2
8002a7a: 881b ldrh r3, [r3, #0]
8002a7c: b29b uxth r3, r3
8002a7e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002a82: f023 0370 bic.w r3, r3, #112 @ 0x70
8002a86: 83bb strh r3, [r7, #28]
8002a88: 68fb ldr r3, [r7, #12]
8002a8a: 681b ldr r3, [r3, #0]
8002a8c: 461a mov r2, r3
8002a8e: 68bb ldr r3, [r7, #8]
8002a90: 781b ldrb r3, [r3, #0]
8002a92: 009b lsls r3, r3, #2
8002a94: 441a add r2, r3
8002a96: 8bbb ldrh r3, [r7, #28]
8002a98: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8002a9c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002aa0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8002aa4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8002aa8: b29b uxth r3, r3
8002aaa: 8013 strh r3, [r2, #0]
}
if (count != 0U)
8002aac: 8b7b ldrh r3, [r7, #26]
8002aae: 2b00 cmp r3, #0
8002ab0: d008 beq.n 8002ac4 <HAL_PCD_EP_DB_Receive+0x210>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8002ab2: 68fb ldr r3, [r7, #12]
8002ab4: 6818 ldr r0, [r3, #0]
8002ab6: 68bb ldr r3, [r7, #8]
8002ab8: 6959 ldr r1, [r3, #20]
8002aba: 68bb ldr r3, [r7, #8]
8002abc: 895a ldrh r2, [r3, #10]
8002abe: 8b7b ldrh r3, [r7, #26]
8002ac0: f004 fa51 bl 8006f66 <USB_ReadPMA>
}
}
return count;
8002ac4: 8b7b ldrh r3, [r7, #26]
}
8002ac6: 4618 mov r0, r3
8002ac8: 3720 adds r7, #32
8002aca: 46bd mov sp, r7
8002acc: bd80 pop {r7, pc}
08002ace <HAL_PCD_EP_DB_Transmit>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8002ace: b580 push {r7, lr}
8002ad0: b0a4 sub sp, #144 @ 0x90
8002ad2: af00 add r7, sp, #0
8002ad4: 60f8 str r0, [r7, #12]
8002ad6: 60b9 str r1, [r7, #8]
8002ad8: 4613 mov r3, r2
8002ada: 80fb strh r3, [r7, #6]
uint32_t len;
uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8002adc: 88fb ldrh r3, [r7, #6]
8002ade: f003 0340 and.w r3, r3, #64 @ 0x40
8002ae2: 2b00 cmp r3, #0
8002ae4: f000 81dd beq.w 8002ea2 <HAL_PCD_EP_DB_Transmit+0x3d4>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8002ae8: 68fb ldr r3, [r7, #12]
8002aea: 681b ldr r3, [r3, #0]
8002aec: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002af0: b29b uxth r3, r3
8002af2: 461a mov r2, r3
8002af4: 68bb ldr r3, [r7, #8]
8002af6: 781b ldrb r3, [r3, #0]
8002af8: 00db lsls r3, r3, #3
8002afa: 4413 add r3, r2
8002afc: 3302 adds r3, #2
8002afe: 005b lsls r3, r3, #1
8002b00: 68fa ldr r2, [r7, #12]
8002b02: 6812 ldr r2, [r2, #0]
8002b04: 4413 add r3, r2
8002b06: f503 6380 add.w r3, r3, #1024 @ 0x400
8002b0a: 881b ldrh r3, [r3, #0]
8002b0c: f3c3 0309 ubfx r3, r3, #0, #10
8002b10: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len > TxPctSize)
8002b14: 68bb ldr r3, [r7, #8]
8002b16: 699a ldr r2, [r3, #24]
8002b18: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002b1c: 429a cmp r2, r3
8002b1e: d907 bls.n 8002b30 <HAL_PCD_EP_DB_Transmit+0x62>
{
ep->xfer_len -= TxPctSize;
8002b20: 68bb ldr r3, [r7, #8]
8002b22: 699a ldr r2, [r3, #24]
8002b24: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002b28: 1ad2 subs r2, r2, r3
8002b2a: 68bb ldr r3, [r7, #8]
8002b2c: 619a str r2, [r3, #24]
8002b2e: e002 b.n 8002b36 <HAL_PCD_EP_DB_Transmit+0x68>
}
else
{
ep->xfer_len = 0U;
8002b30: 68bb ldr r3, [r7, #8]
8002b32: 2200 movs r2, #0
8002b34: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8002b36: 68bb ldr r3, [r7, #8]
8002b38: 699b ldr r3, [r3, #24]
8002b3a: 2b00 cmp r3, #0
8002b3c: f040 80b9 bne.w 8002cb2 <HAL_PCD_EP_DB_Transmit+0x1e4>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8002b40: 68bb ldr r3, [r7, #8]
8002b42: 785b ldrb r3, [r3, #1]
8002b44: 2b00 cmp r3, #0
8002b46: d126 bne.n 8002b96 <HAL_PCD_EP_DB_Transmit+0xc8>
8002b48: 68fb ldr r3, [r7, #12]
8002b4a: 681b ldr r3, [r3, #0]
8002b4c: 62fb str r3, [r7, #44] @ 0x2c
8002b4e: 68fb ldr r3, [r7, #12]
8002b50: 681b ldr r3, [r3, #0]
8002b52: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002b56: b29b uxth r3, r3
8002b58: 461a mov r2, r3
8002b5a: 6afb ldr r3, [r7, #44] @ 0x2c
8002b5c: 4413 add r3, r2
8002b5e: 62fb str r3, [r7, #44] @ 0x2c
8002b60: 68bb ldr r3, [r7, #8]
8002b62: 781b ldrb r3, [r3, #0]
8002b64: 011a lsls r2, r3, #4
8002b66: 6afb ldr r3, [r7, #44] @ 0x2c
8002b68: 4413 add r3, r2
8002b6a: f203 4304 addw r3, r3, #1028 @ 0x404
8002b6e: 62bb str r3, [r7, #40] @ 0x28
8002b70: 6abb ldr r3, [r7, #40] @ 0x28
8002b72: 881b ldrh r3, [r3, #0]
8002b74: b29b uxth r3, r3
8002b76: f3c3 0309 ubfx r3, r3, #0, #10
8002b7a: b29a uxth r2, r3
8002b7c: 6abb ldr r3, [r7, #40] @ 0x28
8002b7e: 801a strh r2, [r3, #0]
8002b80: 6abb ldr r3, [r7, #40] @ 0x28
8002b82: 881b ldrh r3, [r3, #0]
8002b84: b29b uxth r3, r3
8002b86: ea6f 4343 mvn.w r3, r3, lsl #17
8002b8a: ea6f 4353 mvn.w r3, r3, lsr #17
8002b8e: b29a uxth r2, r3
8002b90: 6abb ldr r3, [r7, #40] @ 0x28
8002b92: 801a strh r2, [r3, #0]
8002b94: e01a b.n 8002bcc <HAL_PCD_EP_DB_Transmit+0xfe>
8002b96: 68bb ldr r3, [r7, #8]
8002b98: 785b ldrb r3, [r3, #1]
8002b9a: 2b01 cmp r3, #1
8002b9c: d116 bne.n 8002bcc <HAL_PCD_EP_DB_Transmit+0xfe>
8002b9e: 68fb ldr r3, [r7, #12]
8002ba0: 681b ldr r3, [r3, #0]
8002ba2: 637b str r3, [r7, #52] @ 0x34
8002ba4: 68fb ldr r3, [r7, #12]
8002ba6: 681b ldr r3, [r3, #0]
8002ba8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002bac: b29b uxth r3, r3
8002bae: 461a mov r2, r3
8002bb0: 6b7b ldr r3, [r7, #52] @ 0x34
8002bb2: 4413 add r3, r2
8002bb4: 637b str r3, [r7, #52] @ 0x34
8002bb6: 68bb ldr r3, [r7, #8]
8002bb8: 781b ldrb r3, [r3, #0]
8002bba: 011a lsls r2, r3, #4
8002bbc: 6b7b ldr r3, [r7, #52] @ 0x34
8002bbe: 4413 add r3, r2
8002bc0: f203 4304 addw r3, r3, #1028 @ 0x404
8002bc4: 633b str r3, [r7, #48] @ 0x30
8002bc6: 6b3b ldr r3, [r7, #48] @ 0x30
8002bc8: 2200 movs r2, #0
8002bca: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8002bcc: 68fb ldr r3, [r7, #12]
8002bce: 681b ldr r3, [r3, #0]
8002bd0: 627b str r3, [r7, #36] @ 0x24
8002bd2: 68bb ldr r3, [r7, #8]
8002bd4: 785b ldrb r3, [r3, #1]
8002bd6: 2b00 cmp r3, #0
8002bd8: d126 bne.n 8002c28 <HAL_PCD_EP_DB_Transmit+0x15a>
8002bda: 68fb ldr r3, [r7, #12]
8002bdc: 681b ldr r3, [r3, #0]
8002bde: 61fb str r3, [r7, #28]
8002be0: 68fb ldr r3, [r7, #12]
8002be2: 681b ldr r3, [r3, #0]
8002be4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002be8: b29b uxth r3, r3
8002bea: 461a mov r2, r3
8002bec: 69fb ldr r3, [r7, #28]
8002bee: 4413 add r3, r2
8002bf0: 61fb str r3, [r7, #28]
8002bf2: 68bb ldr r3, [r7, #8]
8002bf4: 781b ldrb r3, [r3, #0]
8002bf6: 011a lsls r2, r3, #4
8002bf8: 69fb ldr r3, [r7, #28]
8002bfa: 4413 add r3, r2
8002bfc: f203 430c addw r3, r3, #1036 @ 0x40c
8002c00: 61bb str r3, [r7, #24]
8002c02: 69bb ldr r3, [r7, #24]
8002c04: 881b ldrh r3, [r3, #0]
8002c06: b29b uxth r3, r3
8002c08: f3c3 0309 ubfx r3, r3, #0, #10
8002c0c: b29a uxth r2, r3
8002c0e: 69bb ldr r3, [r7, #24]
8002c10: 801a strh r2, [r3, #0]
8002c12: 69bb ldr r3, [r7, #24]
8002c14: 881b ldrh r3, [r3, #0]
8002c16: b29b uxth r3, r3
8002c18: ea6f 4343 mvn.w r3, r3, lsl #17
8002c1c: ea6f 4353 mvn.w r3, r3, lsr #17
8002c20: b29a uxth r2, r3
8002c22: 69bb ldr r3, [r7, #24]
8002c24: 801a strh r2, [r3, #0]
8002c26: e017 b.n 8002c58 <HAL_PCD_EP_DB_Transmit+0x18a>
8002c28: 68bb ldr r3, [r7, #8]
8002c2a: 785b ldrb r3, [r3, #1]
8002c2c: 2b01 cmp r3, #1
8002c2e: d113 bne.n 8002c58 <HAL_PCD_EP_DB_Transmit+0x18a>
8002c30: 68fb ldr r3, [r7, #12]
8002c32: 681b ldr r3, [r3, #0]
8002c34: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002c38: b29b uxth r3, r3
8002c3a: 461a mov r2, r3
8002c3c: 6a7b ldr r3, [r7, #36] @ 0x24
8002c3e: 4413 add r3, r2
8002c40: 627b str r3, [r7, #36] @ 0x24
8002c42: 68bb ldr r3, [r7, #8]
8002c44: 781b ldrb r3, [r3, #0]
8002c46: 011a lsls r2, r3, #4
8002c48: 6a7b ldr r3, [r7, #36] @ 0x24
8002c4a: 4413 add r3, r2
8002c4c: f203 430c addw r3, r3, #1036 @ 0x40c
8002c50: 623b str r3, [r7, #32]
8002c52: 6a3b ldr r3, [r7, #32]
8002c54: 2200 movs r2, #0
8002c56: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8002c58: 68bb ldr r3, [r7, #8]
8002c5a: 781b ldrb r3, [r3, #0]
8002c5c: 4619 mov r1, r3
8002c5e: 68f8 ldr r0, [r7, #12]
8002c60: f005 ffff bl 8008c62 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8002c64: 88fb ldrh r3, [r7, #6]
8002c66: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002c6a: 2b00 cmp r3, #0
8002c6c: f000 82fc beq.w 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8002c70: 68fb ldr r3, [r7, #12]
8002c72: 681b ldr r3, [r3, #0]
8002c74: 461a mov r2, r3
8002c76: 68bb ldr r3, [r7, #8]
8002c78: 781b ldrb r3, [r3, #0]
8002c7a: 009b lsls r3, r3, #2
8002c7c: 4413 add r3, r2
8002c7e: 881b ldrh r3, [r3, #0]
8002c80: b29b uxth r3, r3
8002c82: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002c86: f023 0370 bic.w r3, r3, #112 @ 0x70
8002c8a: 82fb strh r3, [r7, #22]
8002c8c: 68fb ldr r3, [r7, #12]
8002c8e: 681b ldr r3, [r3, #0]
8002c90: 461a mov r2, r3
8002c92: 68bb ldr r3, [r7, #8]
8002c94: 781b ldrb r3, [r3, #0]
8002c96: 009b lsls r3, r3, #2
8002c98: 441a add r2, r3
8002c9a: 8afb ldrh r3, [r7, #22]
8002c9c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8002ca0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002ca4: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8002ca8: f043 0380 orr.w r3, r3, #128 @ 0x80
8002cac: b29b uxth r3, r3
8002cae: 8013 strh r3, [r2, #0]
8002cb0: e2da b.n 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8002cb2: 88fb ldrh r3, [r7, #6]
8002cb4: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002cb8: 2b00 cmp r3, #0
8002cba: d021 beq.n 8002d00 <HAL_PCD_EP_DB_Transmit+0x232>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8002cbc: 68fb ldr r3, [r7, #12]
8002cbe: 681b ldr r3, [r3, #0]
8002cc0: 461a mov r2, r3
8002cc2: 68bb ldr r3, [r7, #8]
8002cc4: 781b ldrb r3, [r3, #0]
8002cc6: 009b lsls r3, r3, #2
8002cc8: 4413 add r3, r2
8002cca: 881b ldrh r3, [r3, #0]
8002ccc: b29b uxth r3, r3
8002cce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002cd2: f023 0370 bic.w r3, r3, #112 @ 0x70
8002cd6: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8002cda: 68fb ldr r3, [r7, #12]
8002cdc: 681b ldr r3, [r3, #0]
8002cde: 461a mov r2, r3
8002ce0: 68bb ldr r3, [r7, #8]
8002ce2: 781b ldrb r3, [r3, #0]
8002ce4: 009b lsls r3, r3, #2
8002ce6: 441a add r2, r3
8002ce8: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8002cec: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8002cf0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8002cf4: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8002cf8: f043 0380 orr.w r3, r3, #128 @ 0x80
8002cfc: b29b uxth r3, r3
8002cfe: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8002d00: 68bb ldr r3, [r7, #8]
8002d02: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8002d06: 2b01 cmp r3, #1
8002d08: f040 82ae bne.w 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
8002d0c: 68bb ldr r3, [r7, #8]
8002d0e: 695a ldr r2, [r3, #20]
8002d10: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002d14: 441a add r2, r3
8002d16: 68bb ldr r3, [r7, #8]
8002d18: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8002d1a: 68bb ldr r3, [r7, #8]
8002d1c: 69da ldr r2, [r3, #28]
8002d1e: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002d22: 441a add r2, r3
8002d24: 68bb ldr r3, [r7, #8]
8002d26: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
8002d28: 68bb ldr r3, [r7, #8]
8002d2a: 6a1a ldr r2, [r3, #32]
8002d2c: 68bb ldr r3, [r7, #8]
8002d2e: 691b ldr r3, [r3, #16]
8002d30: 429a cmp r2, r3
8002d32: d30b bcc.n 8002d4c <HAL_PCD_EP_DB_Transmit+0x27e>
{
len = ep->maxpacket;
8002d34: 68bb ldr r3, [r7, #8]
8002d36: 691b ldr r3, [r3, #16]
8002d38: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8002d3c: 68bb ldr r3, [r7, #8]
8002d3e: 6a1a ldr r2, [r3, #32]
8002d40: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002d44: 1ad2 subs r2, r2, r3
8002d46: 68bb ldr r3, [r7, #8]
8002d48: 621a str r2, [r3, #32]
8002d4a: e017 b.n 8002d7c <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else if (ep->xfer_len_db == 0U)
8002d4c: 68bb ldr r3, [r7, #8]
8002d4e: 6a1b ldr r3, [r3, #32]
8002d50: 2b00 cmp r3, #0
8002d52: d108 bne.n 8002d66 <HAL_PCD_EP_DB_Transmit+0x298>
{
len = TxPctSize;
8002d54: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002d58: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8002d5c: 68bb ldr r3, [r7, #8]
8002d5e: 2200 movs r2, #0
8002d60: f883 2024 strb.w r2, [r3, #36] @ 0x24
8002d64: e00a b.n 8002d7c <HAL_PCD_EP_DB_Transmit+0x2ae>
}
else
{
ep->xfer_fill_db = 0U;
8002d66: 68bb ldr r3, [r7, #8]
8002d68: 2200 movs r2, #0
8002d6a: f883 2024 strb.w r2, [r3, #36] @ 0x24
len = ep->xfer_len_db;
8002d6e: 68bb ldr r3, [r7, #8]
8002d70: 6a1b ldr r3, [r3, #32]
8002d72: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8002d76: 68bb ldr r3, [r7, #8]
8002d78: 2200 movs r2, #0
8002d7a: 621a str r2, [r3, #32]
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8002d7c: 68bb ldr r3, [r7, #8]
8002d7e: 785b ldrb r3, [r3, #1]
8002d80: 2b00 cmp r3, #0
8002d82: d165 bne.n 8002e50 <HAL_PCD_EP_DB_Transmit+0x382>
8002d84: 68fb ldr r3, [r7, #12]
8002d86: 681b ldr r3, [r3, #0]
8002d88: 63fb str r3, [r7, #60] @ 0x3c
8002d8a: 68fb ldr r3, [r7, #12]
8002d8c: 681b ldr r3, [r3, #0]
8002d8e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002d92: b29b uxth r3, r3
8002d94: 461a mov r2, r3
8002d96: 6bfb ldr r3, [r7, #60] @ 0x3c
8002d98: 4413 add r3, r2
8002d9a: 63fb str r3, [r7, #60] @ 0x3c
8002d9c: 68bb ldr r3, [r7, #8]
8002d9e: 781b ldrb r3, [r3, #0]
8002da0: 011a lsls r2, r3, #4
8002da2: 6bfb ldr r3, [r7, #60] @ 0x3c
8002da4: 4413 add r3, r2
8002da6: f203 4304 addw r3, r3, #1028 @ 0x404
8002daa: 63bb str r3, [r7, #56] @ 0x38
8002dac: 6bbb ldr r3, [r7, #56] @ 0x38
8002dae: 881b ldrh r3, [r3, #0]
8002db0: b29b uxth r3, r3
8002db2: f3c3 0309 ubfx r3, r3, #0, #10
8002db6: b29a uxth r2, r3
8002db8: 6bbb ldr r3, [r7, #56] @ 0x38
8002dba: 801a strh r2, [r3, #0]
8002dbc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002dc0: 2b3e cmp r3, #62 @ 0x3e
8002dc2: d91d bls.n 8002e00 <HAL_PCD_EP_DB_Transmit+0x332>
8002dc4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002dc8: 095b lsrs r3, r3, #5
8002dca: 64bb str r3, [r7, #72] @ 0x48
8002dcc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002dd0: f003 031f and.w r3, r3, #31
8002dd4: 2b00 cmp r3, #0
8002dd6: d102 bne.n 8002dde <HAL_PCD_EP_DB_Transmit+0x310>
8002dd8: 6cbb ldr r3, [r7, #72] @ 0x48
8002dda: 3b01 subs r3, #1
8002ddc: 64bb str r3, [r7, #72] @ 0x48
8002dde: 6bbb ldr r3, [r7, #56] @ 0x38
8002de0: 881b ldrh r3, [r3, #0]
8002de2: b29a uxth r2, r3
8002de4: 6cbb ldr r3, [r7, #72] @ 0x48
8002de6: b29b uxth r3, r3
8002de8: 029b lsls r3, r3, #10
8002dea: b29b uxth r3, r3
8002dec: 4313 orrs r3, r2
8002dee: b29b uxth r3, r3
8002df0: ea6f 4343 mvn.w r3, r3, lsl #17
8002df4: ea6f 4353 mvn.w r3, r3, lsr #17
8002df8: b29a uxth r2, r3
8002dfa: 6bbb ldr r3, [r7, #56] @ 0x38
8002dfc: 801a strh r2, [r3, #0]
8002dfe: e044 b.n 8002e8a <HAL_PCD_EP_DB_Transmit+0x3bc>
8002e00: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002e04: 2b00 cmp r3, #0
8002e06: d10a bne.n 8002e1e <HAL_PCD_EP_DB_Transmit+0x350>
8002e08: 6bbb ldr r3, [r7, #56] @ 0x38
8002e0a: 881b ldrh r3, [r3, #0]
8002e0c: b29b uxth r3, r3
8002e0e: ea6f 4343 mvn.w r3, r3, lsl #17
8002e12: ea6f 4353 mvn.w r3, r3, lsr #17
8002e16: b29a uxth r2, r3
8002e18: 6bbb ldr r3, [r7, #56] @ 0x38
8002e1a: 801a strh r2, [r3, #0]
8002e1c: e035 b.n 8002e8a <HAL_PCD_EP_DB_Transmit+0x3bc>
8002e1e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002e22: 085b lsrs r3, r3, #1
8002e24: 64bb str r3, [r7, #72] @ 0x48
8002e26: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002e2a: f003 0301 and.w r3, r3, #1
8002e2e: 2b00 cmp r3, #0
8002e30: d002 beq.n 8002e38 <HAL_PCD_EP_DB_Transmit+0x36a>
8002e32: 6cbb ldr r3, [r7, #72] @ 0x48
8002e34: 3301 adds r3, #1
8002e36: 64bb str r3, [r7, #72] @ 0x48
8002e38: 6bbb ldr r3, [r7, #56] @ 0x38
8002e3a: 881b ldrh r3, [r3, #0]
8002e3c: b29a uxth r2, r3
8002e3e: 6cbb ldr r3, [r7, #72] @ 0x48
8002e40: b29b uxth r3, r3
8002e42: 029b lsls r3, r3, #10
8002e44: b29b uxth r3, r3
8002e46: 4313 orrs r3, r2
8002e48: b29a uxth r2, r3
8002e4a: 6bbb ldr r3, [r7, #56] @ 0x38
8002e4c: 801a strh r2, [r3, #0]
8002e4e: e01c b.n 8002e8a <HAL_PCD_EP_DB_Transmit+0x3bc>
8002e50: 68bb ldr r3, [r7, #8]
8002e52: 785b ldrb r3, [r3, #1]
8002e54: 2b01 cmp r3, #1
8002e56: d118 bne.n 8002e8a <HAL_PCD_EP_DB_Transmit+0x3bc>
8002e58: 68fb ldr r3, [r7, #12]
8002e5a: 681b ldr r3, [r3, #0]
8002e5c: 647b str r3, [r7, #68] @ 0x44
8002e5e: 68fb ldr r3, [r7, #12]
8002e60: 681b ldr r3, [r3, #0]
8002e62: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002e66: b29b uxth r3, r3
8002e68: 461a mov r2, r3
8002e6a: 6c7b ldr r3, [r7, #68] @ 0x44
8002e6c: 4413 add r3, r2
8002e6e: 647b str r3, [r7, #68] @ 0x44
8002e70: 68bb ldr r3, [r7, #8]
8002e72: 781b ldrb r3, [r3, #0]
8002e74: 011a lsls r2, r3, #4
8002e76: 6c7b ldr r3, [r7, #68] @ 0x44
8002e78: 4413 add r3, r2
8002e7a: f203 4304 addw r3, r3, #1028 @ 0x404
8002e7e: 643b str r3, [r7, #64] @ 0x40
8002e80: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002e84: b29a uxth r2, r3
8002e86: 6c3b ldr r3, [r7, #64] @ 0x40
8002e88: 801a strh r2, [r3, #0]
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
8002e8a: 68fb ldr r3, [r7, #12]
8002e8c: 6818 ldr r0, [r3, #0]
8002e8e: 68bb ldr r3, [r7, #8]
8002e90: 6959 ldr r1, [r3, #20]
8002e92: 68bb ldr r3, [r7, #8]
8002e94: 891a ldrh r2, [r3, #8]
8002e96: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002e9a: b29b uxth r3, r3
8002e9c: f004 f81d bl 8006eda <USB_WritePMA>
8002ea0: e1e2 b.n 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8002ea2: 68fb ldr r3, [r7, #12]
8002ea4: 681b ldr r3, [r3, #0]
8002ea6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002eaa: b29b uxth r3, r3
8002eac: 461a mov r2, r3
8002eae: 68bb ldr r3, [r7, #8]
8002eb0: 781b ldrb r3, [r3, #0]
8002eb2: 00db lsls r3, r3, #3
8002eb4: 4413 add r3, r2
8002eb6: 3306 adds r3, #6
8002eb8: 005b lsls r3, r3, #1
8002eba: 68fa ldr r2, [r7, #12]
8002ebc: 6812 ldr r2, [r2, #0]
8002ebe: 4413 add r3, r2
8002ec0: f503 6380 add.w r3, r3, #1024 @ 0x400
8002ec4: 881b ldrh r3, [r3, #0]
8002ec6: f3c3 0309 ubfx r3, r3, #0, #10
8002eca: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
if (ep->xfer_len >= TxPctSize)
8002ece: 68bb ldr r3, [r7, #8]
8002ed0: 699a ldr r2, [r3, #24]
8002ed2: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002ed6: 429a cmp r2, r3
8002ed8: d307 bcc.n 8002eea <HAL_PCD_EP_DB_Transmit+0x41c>
{
ep->xfer_len -= TxPctSize;
8002eda: 68bb ldr r3, [r7, #8]
8002edc: 699a ldr r2, [r3, #24]
8002ede: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8002ee2: 1ad2 subs r2, r2, r3
8002ee4: 68bb ldr r3, [r7, #8]
8002ee6: 619a str r2, [r3, #24]
8002ee8: e002 b.n 8002ef0 <HAL_PCD_EP_DB_Transmit+0x422>
}
else
{
ep->xfer_len = 0U;
8002eea: 68bb ldr r3, [r7, #8]
8002eec: 2200 movs r2, #0
8002eee: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8002ef0: 68bb ldr r3, [r7, #8]
8002ef2: 699b ldr r3, [r3, #24]
8002ef4: 2b00 cmp r3, #0
8002ef6: f040 80c0 bne.w 800307a <HAL_PCD_EP_DB_Transmit+0x5ac>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8002efa: 68bb ldr r3, [r7, #8]
8002efc: 785b ldrb r3, [r3, #1]
8002efe: 2b00 cmp r3, #0
8002f00: d126 bne.n 8002f50 <HAL_PCD_EP_DB_Transmit+0x482>
8002f02: 68fb ldr r3, [r7, #12]
8002f04: 681b ldr r3, [r3, #0]
8002f06: 67fb str r3, [r7, #124] @ 0x7c
8002f08: 68fb ldr r3, [r7, #12]
8002f0a: 681b ldr r3, [r3, #0]
8002f0c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002f10: b29b uxth r3, r3
8002f12: 461a mov r2, r3
8002f14: 6ffb ldr r3, [r7, #124] @ 0x7c
8002f16: 4413 add r3, r2
8002f18: 67fb str r3, [r7, #124] @ 0x7c
8002f1a: 68bb ldr r3, [r7, #8]
8002f1c: 781b ldrb r3, [r3, #0]
8002f1e: 011a lsls r2, r3, #4
8002f20: 6ffb ldr r3, [r7, #124] @ 0x7c
8002f22: 4413 add r3, r2
8002f24: f203 4304 addw r3, r3, #1028 @ 0x404
8002f28: 67bb str r3, [r7, #120] @ 0x78
8002f2a: 6fbb ldr r3, [r7, #120] @ 0x78
8002f2c: 881b ldrh r3, [r3, #0]
8002f2e: b29b uxth r3, r3
8002f30: f3c3 0309 ubfx r3, r3, #0, #10
8002f34: b29a uxth r2, r3
8002f36: 6fbb ldr r3, [r7, #120] @ 0x78
8002f38: 801a strh r2, [r3, #0]
8002f3a: 6fbb ldr r3, [r7, #120] @ 0x78
8002f3c: 881b ldrh r3, [r3, #0]
8002f3e: b29b uxth r3, r3
8002f40: ea6f 4343 mvn.w r3, r3, lsl #17
8002f44: ea6f 4353 mvn.w r3, r3, lsr #17
8002f48: b29a uxth r2, r3
8002f4a: 6fbb ldr r3, [r7, #120] @ 0x78
8002f4c: 801a strh r2, [r3, #0]
8002f4e: e01a b.n 8002f86 <HAL_PCD_EP_DB_Transmit+0x4b8>
8002f50: 68bb ldr r3, [r7, #8]
8002f52: 785b ldrb r3, [r3, #1]
8002f54: 2b01 cmp r3, #1
8002f56: d116 bne.n 8002f86 <HAL_PCD_EP_DB_Transmit+0x4b8>
8002f58: 68fb ldr r3, [r7, #12]
8002f5a: 681b ldr r3, [r3, #0]
8002f5c: 667b str r3, [r7, #100] @ 0x64
8002f5e: 68fb ldr r3, [r7, #12]
8002f60: 681b ldr r3, [r3, #0]
8002f62: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002f66: b29b uxth r3, r3
8002f68: 461a mov r2, r3
8002f6a: 6e7b ldr r3, [r7, #100] @ 0x64
8002f6c: 4413 add r3, r2
8002f6e: 667b str r3, [r7, #100] @ 0x64
8002f70: 68bb ldr r3, [r7, #8]
8002f72: 781b ldrb r3, [r3, #0]
8002f74: 011a lsls r2, r3, #4
8002f76: 6e7b ldr r3, [r7, #100] @ 0x64
8002f78: 4413 add r3, r2
8002f7a: f203 4304 addw r3, r3, #1028 @ 0x404
8002f7e: 663b str r3, [r7, #96] @ 0x60
8002f80: 6e3b ldr r3, [r7, #96] @ 0x60
8002f82: 2200 movs r2, #0
8002f84: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8002f86: 68fb ldr r3, [r7, #12]
8002f88: 681b ldr r3, [r3, #0]
8002f8a: 677b str r3, [r7, #116] @ 0x74
8002f8c: 68bb ldr r3, [r7, #8]
8002f8e: 785b ldrb r3, [r3, #1]
8002f90: 2b00 cmp r3, #0
8002f92: d12b bne.n 8002fec <HAL_PCD_EP_DB_Transmit+0x51e>
8002f94: 68fb ldr r3, [r7, #12]
8002f96: 681b ldr r3, [r3, #0]
8002f98: 66fb str r3, [r7, #108] @ 0x6c
8002f9a: 68fb ldr r3, [r7, #12]
8002f9c: 681b ldr r3, [r3, #0]
8002f9e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002fa2: b29b uxth r3, r3
8002fa4: 461a mov r2, r3
8002fa6: 6efb ldr r3, [r7, #108] @ 0x6c
8002fa8: 4413 add r3, r2
8002faa: 66fb str r3, [r7, #108] @ 0x6c
8002fac: 68bb ldr r3, [r7, #8]
8002fae: 781b ldrb r3, [r3, #0]
8002fb0: 011a lsls r2, r3, #4
8002fb2: 6efb ldr r3, [r7, #108] @ 0x6c
8002fb4: 4413 add r3, r2
8002fb6: f203 430c addw r3, r3, #1036 @ 0x40c
8002fba: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8002fbe: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002fc2: 881b ldrh r3, [r3, #0]
8002fc4: b29b uxth r3, r3
8002fc6: f3c3 0309 ubfx r3, r3, #0, #10
8002fca: b29a uxth r2, r3
8002fcc: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002fd0: 801a strh r2, [r3, #0]
8002fd2: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002fd6: 881b ldrh r3, [r3, #0]
8002fd8: b29b uxth r3, r3
8002fda: ea6f 4343 mvn.w r3, r3, lsl #17
8002fde: ea6f 4353 mvn.w r3, r3, lsr #17
8002fe2: b29a uxth r2, r3
8002fe4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002fe8: 801a strh r2, [r3, #0]
8002fea: e017 b.n 800301c <HAL_PCD_EP_DB_Transmit+0x54e>
8002fec: 68bb ldr r3, [r7, #8]
8002fee: 785b ldrb r3, [r3, #1]
8002ff0: 2b01 cmp r3, #1
8002ff2: d113 bne.n 800301c <HAL_PCD_EP_DB_Transmit+0x54e>
8002ff4: 68fb ldr r3, [r7, #12]
8002ff6: 681b ldr r3, [r3, #0]
8002ff8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8002ffc: b29b uxth r3, r3
8002ffe: 461a mov r2, r3
8003000: 6f7b ldr r3, [r7, #116] @ 0x74
8003002: 4413 add r3, r2
8003004: 677b str r3, [r7, #116] @ 0x74
8003006: 68bb ldr r3, [r7, #8]
8003008: 781b ldrb r3, [r3, #0]
800300a: 011a lsls r2, r3, #4
800300c: 6f7b ldr r3, [r7, #116] @ 0x74
800300e: 4413 add r3, r2
8003010: f203 430c addw r3, r3, #1036 @ 0x40c
8003014: 673b str r3, [r7, #112] @ 0x70
8003016: 6f3b ldr r3, [r7, #112] @ 0x70
8003018: 2200 movs r2, #0
800301a: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
800301c: 68bb ldr r3, [r7, #8]
800301e: 781b ldrb r3, [r3, #0]
8003020: 4619 mov r1, r3
8003022: 68f8 ldr r0, [r7, #12]
8003024: f005 fe1d bl 8008c62 <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8003028: 88fb ldrh r3, [r7, #6]
800302a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800302e: 2b00 cmp r3, #0
8003030: f040 811a bne.w 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8003034: 68fb ldr r3, [r7, #12]
8003036: 681b ldr r3, [r3, #0]
8003038: 461a mov r2, r3
800303a: 68bb ldr r3, [r7, #8]
800303c: 781b ldrb r3, [r3, #0]
800303e: 009b lsls r3, r3, #2
8003040: 4413 add r3, r2
8003042: 881b ldrh r3, [r3, #0]
8003044: b29b uxth r3, r3
8003046: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800304a: f023 0370 bic.w r3, r3, #112 @ 0x70
800304e: f8a7 3088 strh.w r3, [r7, #136] @ 0x88
8003052: 68fb ldr r3, [r7, #12]
8003054: 681b ldr r3, [r3, #0]
8003056: 461a mov r2, r3
8003058: 68bb ldr r3, [r7, #8]
800305a: 781b ldrb r3, [r3, #0]
800305c: 009b lsls r3, r3, #2
800305e: 441a add r2, r3
8003060: f8b7 3088 ldrh.w r3, [r7, #136] @ 0x88
8003064: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8003068: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800306c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8003070: f043 0380 orr.w r3, r3, #128 @ 0x80
8003074: b29b uxth r3, r3
8003076: 8013 strh r3, [r2, #0]
8003078: e0f6 b.n 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
800307a: 88fb ldrh r3, [r7, #6]
800307c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8003080: 2b00 cmp r3, #0
8003082: d121 bne.n 80030c8 <HAL_PCD_EP_DB_Transmit+0x5fa>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8003084: 68fb ldr r3, [r7, #12]
8003086: 681b ldr r3, [r3, #0]
8003088: 461a mov r2, r3
800308a: 68bb ldr r3, [r7, #8]
800308c: 781b ldrb r3, [r3, #0]
800308e: 009b lsls r3, r3, #2
8003090: 4413 add r3, r2
8003092: 881b ldrh r3, [r3, #0]
8003094: b29b uxth r3, r3
8003096: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800309a: f023 0370 bic.w r3, r3, #112 @ 0x70
800309e: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
80030a2: 68fb ldr r3, [r7, #12]
80030a4: 681b ldr r3, [r3, #0]
80030a6: 461a mov r2, r3
80030a8: 68bb ldr r3, [r7, #8]
80030aa: 781b ldrb r3, [r3, #0]
80030ac: 009b lsls r3, r3, #2
80030ae: 441a add r2, r3
80030b0: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80030b4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80030b8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80030bc: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80030c0: f043 0380 orr.w r3, r3, #128 @ 0x80
80030c4: b29b uxth r3, r3
80030c6: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
80030c8: 68bb ldr r3, [r7, #8]
80030ca: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80030ce: 2b01 cmp r3, #1
80030d0: f040 80ca bne.w 8003268 <HAL_PCD_EP_DB_Transmit+0x79a>
{
ep->xfer_buff += TxPctSize;
80030d4: 68bb ldr r3, [r7, #8]
80030d6: 695a ldr r2, [r3, #20]
80030d8: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
80030dc: 441a add r2, r3
80030de: 68bb ldr r3, [r7, #8]
80030e0: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
80030e2: 68bb ldr r3, [r7, #8]
80030e4: 69da ldr r2, [r3, #28]
80030e6: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
80030ea: 441a add r2, r3
80030ec: 68bb ldr r3, [r7, #8]
80030ee: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
80030f0: 68bb ldr r3, [r7, #8]
80030f2: 6a1a ldr r2, [r3, #32]
80030f4: 68bb ldr r3, [r7, #8]
80030f6: 691b ldr r3, [r3, #16]
80030f8: 429a cmp r2, r3
80030fa: d30b bcc.n 8003114 <HAL_PCD_EP_DB_Transmit+0x646>
{
len = ep->maxpacket;
80030fc: 68bb ldr r3, [r7, #8]
80030fe: 691b ldr r3, [r3, #16]
8003100: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db -= len;
8003104: 68bb ldr r3, [r7, #8]
8003106: 6a1a ldr r2, [r3, #32]
8003108: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800310c: 1ad2 subs r2, r2, r3
800310e: 68bb ldr r3, [r7, #8]
8003110: 621a str r2, [r3, #32]
8003112: e017 b.n 8003144 <HAL_PCD_EP_DB_Transmit+0x676>
}
else if (ep->xfer_len_db == 0U)
8003114: 68bb ldr r3, [r7, #8]
8003116: 6a1b ldr r3, [r3, #32]
8003118: 2b00 cmp r3, #0
800311a: d108 bne.n 800312e <HAL_PCD_EP_DB_Transmit+0x660>
{
len = TxPctSize;
800311c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
8003120: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_fill_db = 0U;
8003124: 68bb ldr r3, [r7, #8]
8003126: 2200 movs r2, #0
8003128: f883 2024 strb.w r2, [r3, #36] @ 0x24
800312c: e00a b.n 8003144 <HAL_PCD_EP_DB_Transmit+0x676>
}
else
{
len = ep->xfer_len_db;
800312e: 68bb ldr r3, [r7, #8]
8003130: 6a1b ldr r3, [r3, #32]
8003132: f8c7 308c str.w r3, [r7, #140] @ 0x8c
ep->xfer_len_db = 0U;
8003136: 68bb ldr r3, [r7, #8]
8003138: 2200 movs r2, #0
800313a: 621a str r2, [r3, #32]
ep->xfer_fill_db = 0;
800313c: 68bb ldr r3, [r7, #8]
800313e: 2200 movs r2, #0
8003140: f883 2024 strb.w r2, [r3, #36] @ 0x24
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8003144: 68fb ldr r3, [r7, #12]
8003146: 681b ldr r3, [r3, #0]
8003148: 657b str r3, [r7, #84] @ 0x54
800314a: 68bb ldr r3, [r7, #8]
800314c: 785b ldrb r3, [r3, #1]
800314e: 2b00 cmp r3, #0
8003150: d165 bne.n 800321e <HAL_PCD_EP_DB_Transmit+0x750>
8003152: 68fb ldr r3, [r7, #12]
8003154: 681b ldr r3, [r3, #0]
8003156: 65fb str r3, [r7, #92] @ 0x5c
8003158: 68fb ldr r3, [r7, #12]
800315a: 681b ldr r3, [r3, #0]
800315c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8003160: b29b uxth r3, r3
8003162: 461a mov r2, r3
8003164: 6dfb ldr r3, [r7, #92] @ 0x5c
8003166: 4413 add r3, r2
8003168: 65fb str r3, [r7, #92] @ 0x5c
800316a: 68bb ldr r3, [r7, #8]
800316c: 781b ldrb r3, [r3, #0]
800316e: 011a lsls r2, r3, #4
8003170: 6dfb ldr r3, [r7, #92] @ 0x5c
8003172: 4413 add r3, r2
8003174: f203 430c addw r3, r3, #1036 @ 0x40c
8003178: 65bb str r3, [r7, #88] @ 0x58
800317a: 6dbb ldr r3, [r7, #88] @ 0x58
800317c: 881b ldrh r3, [r3, #0]
800317e: b29b uxth r3, r3
8003180: f3c3 0309 ubfx r3, r3, #0, #10
8003184: b29a uxth r2, r3
8003186: 6dbb ldr r3, [r7, #88] @ 0x58
8003188: 801a strh r2, [r3, #0]
800318a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800318e: 2b3e cmp r3, #62 @ 0x3e
8003190: d91d bls.n 80031ce <HAL_PCD_EP_DB_Transmit+0x700>
8003192: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8003196: 095b lsrs r3, r3, #5
8003198: 66bb str r3, [r7, #104] @ 0x68
800319a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800319e: f003 031f and.w r3, r3, #31
80031a2: 2b00 cmp r3, #0
80031a4: d102 bne.n 80031ac <HAL_PCD_EP_DB_Transmit+0x6de>
80031a6: 6ebb ldr r3, [r7, #104] @ 0x68
80031a8: 3b01 subs r3, #1
80031aa: 66bb str r3, [r7, #104] @ 0x68
80031ac: 6dbb ldr r3, [r7, #88] @ 0x58
80031ae: 881b ldrh r3, [r3, #0]
80031b0: b29a uxth r2, r3
80031b2: 6ebb ldr r3, [r7, #104] @ 0x68
80031b4: b29b uxth r3, r3
80031b6: 029b lsls r3, r3, #10
80031b8: b29b uxth r3, r3
80031ba: 4313 orrs r3, r2
80031bc: b29b uxth r3, r3
80031be: ea6f 4343 mvn.w r3, r3, lsl #17
80031c2: ea6f 4353 mvn.w r3, r3, lsr #17
80031c6: b29a uxth r2, r3
80031c8: 6dbb ldr r3, [r7, #88] @ 0x58
80031ca: 801a strh r2, [r3, #0]
80031cc: e041 b.n 8003252 <HAL_PCD_EP_DB_Transmit+0x784>
80031ce: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80031d2: 2b00 cmp r3, #0
80031d4: d10a bne.n 80031ec <HAL_PCD_EP_DB_Transmit+0x71e>
80031d6: 6dbb ldr r3, [r7, #88] @ 0x58
80031d8: 881b ldrh r3, [r3, #0]
80031da: b29b uxth r3, r3
80031dc: ea6f 4343 mvn.w r3, r3, lsl #17
80031e0: ea6f 4353 mvn.w r3, r3, lsr #17
80031e4: b29a uxth r2, r3
80031e6: 6dbb ldr r3, [r7, #88] @ 0x58
80031e8: 801a strh r2, [r3, #0]
80031ea: e032 b.n 8003252 <HAL_PCD_EP_DB_Transmit+0x784>
80031ec: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80031f0: 085b lsrs r3, r3, #1
80031f2: 66bb str r3, [r7, #104] @ 0x68
80031f4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80031f8: f003 0301 and.w r3, r3, #1
80031fc: 2b00 cmp r3, #0
80031fe: d002 beq.n 8003206 <HAL_PCD_EP_DB_Transmit+0x738>
8003200: 6ebb ldr r3, [r7, #104] @ 0x68
8003202: 3301 adds r3, #1
8003204: 66bb str r3, [r7, #104] @ 0x68
8003206: 6dbb ldr r3, [r7, #88] @ 0x58
8003208: 881b ldrh r3, [r3, #0]
800320a: b29a uxth r2, r3
800320c: 6ebb ldr r3, [r7, #104] @ 0x68
800320e: b29b uxth r3, r3
8003210: 029b lsls r3, r3, #10
8003212: b29b uxth r3, r3
8003214: 4313 orrs r3, r2
8003216: b29a uxth r2, r3
8003218: 6dbb ldr r3, [r7, #88] @ 0x58
800321a: 801a strh r2, [r3, #0]
800321c: e019 b.n 8003252 <HAL_PCD_EP_DB_Transmit+0x784>
800321e: 68bb ldr r3, [r7, #8]
8003220: 785b ldrb r3, [r3, #1]
8003222: 2b01 cmp r3, #1
8003224: d115 bne.n 8003252 <HAL_PCD_EP_DB_Transmit+0x784>
8003226: 68fb ldr r3, [r7, #12]
8003228: 681b ldr r3, [r3, #0]
800322a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800322e: b29b uxth r3, r3
8003230: 461a mov r2, r3
8003232: 6d7b ldr r3, [r7, #84] @ 0x54
8003234: 4413 add r3, r2
8003236: 657b str r3, [r7, #84] @ 0x54
8003238: 68bb ldr r3, [r7, #8]
800323a: 781b ldrb r3, [r3, #0]
800323c: 011a lsls r2, r3, #4
800323e: 6d7b ldr r3, [r7, #84] @ 0x54
8003240: 4413 add r3, r2
8003242: f203 430c addw r3, r3, #1036 @ 0x40c
8003246: 653b str r3, [r7, #80] @ 0x50
8003248: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800324c: b29a uxth r2, r3
800324e: 6d3b ldr r3, [r7, #80] @ 0x50
8003250: 801a strh r2, [r3, #0]
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
8003252: 68fb ldr r3, [r7, #12]
8003254: 6818 ldr r0, [r3, #0]
8003256: 68bb ldr r3, [r7, #8]
8003258: 6959 ldr r1, [r3, #20]
800325a: 68bb ldr r3, [r7, #8]
800325c: 895a ldrh r2, [r3, #10]
800325e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8003262: b29b uxth r3, r3
8003264: f003 fe39 bl 8006eda <USB_WritePMA>
}
}
}
/*enable endpoint IN*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
8003268: 68fb ldr r3, [r7, #12]
800326a: 681b ldr r3, [r3, #0]
800326c: 461a mov r2, r3
800326e: 68bb ldr r3, [r7, #8]
8003270: 781b ldrb r3, [r3, #0]
8003272: 009b lsls r3, r3, #2
8003274: 4413 add r3, r2
8003276: 881b ldrh r3, [r3, #0]
8003278: b29b uxth r3, r3
800327a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800327e: f023 0340 bic.w r3, r3, #64 @ 0x40
8003282: 82bb strh r3, [r7, #20]
8003284: 8abb ldrh r3, [r7, #20]
8003286: f083 0310 eor.w r3, r3, #16
800328a: 82bb strh r3, [r7, #20]
800328c: 8abb ldrh r3, [r7, #20]
800328e: f083 0320 eor.w r3, r3, #32
8003292: 82bb strh r3, [r7, #20]
8003294: 68fb ldr r3, [r7, #12]
8003296: 681b ldr r3, [r3, #0]
8003298: 461a mov r2, r3
800329a: 68bb ldr r3, [r7, #8]
800329c: 781b ldrb r3, [r3, #0]
800329e: 009b lsls r3, r3, #2
80032a0: 441a add r2, r3
80032a2: 8abb ldrh r3, [r7, #20]
80032a4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80032a8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80032ac: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80032b0: f043 0380 orr.w r3, r3, #128 @ 0x80
80032b4: b29b uxth r3, r3
80032b6: 8013 strh r3, [r2, #0]
return HAL_OK;
80032b8: 2300 movs r3, #0
}
80032ba: 4618 mov r0, r3
80032bc: 3790 adds r7, #144 @ 0x90
80032be: 46bd mov sp, r7
80032c0: bd80 pop {r7, pc}
080032c2 <HAL_PCDEx_PMAConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
80032c2: b480 push {r7}
80032c4: b087 sub sp, #28
80032c6: af00 add r7, sp, #0
80032c8: 60f8 str r0, [r7, #12]
80032ca: 607b str r3, [r7, #4]
80032cc: 460b mov r3, r1
80032ce: 817b strh r3, [r7, #10]
80032d0: 4613 mov r3, r2
80032d2: 813b strh r3, [r7, #8]
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
80032d4: 897b ldrh r3, [r7, #10]
80032d6: f003 0380 and.w r3, r3, #128 @ 0x80
80032da: b29b uxth r3, r3
80032dc: 2b00 cmp r3, #0
80032de: d00b beq.n 80032f8 <HAL_PCDEx_PMAConfig+0x36>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80032e0: 897b ldrh r3, [r7, #10]
80032e2: f003 0207 and.w r2, r3, #7
80032e6: 4613 mov r3, r2
80032e8: 009b lsls r3, r3, #2
80032ea: 4413 add r3, r2
80032ec: 00db lsls r3, r3, #3
80032ee: 3310 adds r3, #16
80032f0: 68fa ldr r2, [r7, #12]
80032f2: 4413 add r3, r2
80032f4: 617b str r3, [r7, #20]
80032f6: e009 b.n 800330c <HAL_PCDEx_PMAConfig+0x4a>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
80032f8: 897a ldrh r2, [r7, #10]
80032fa: 4613 mov r3, r2
80032fc: 009b lsls r3, r3, #2
80032fe: 4413 add r3, r2
8003300: 00db lsls r3, r3, #3
8003302: f503 73a8 add.w r3, r3, #336 @ 0x150
8003306: 68fa ldr r2, [r7, #12]
8003308: 4413 add r3, r2
800330a: 617b str r3, [r7, #20]
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
800330c: 893b ldrh r3, [r7, #8]
800330e: 2b00 cmp r3, #0
8003310: d107 bne.n 8003322 <HAL_PCDEx_PMAConfig+0x60>
{
/* Single Buffer */
ep->doublebuffer = 0U;
8003312: 697b ldr r3, [r7, #20]
8003314: 2200 movs r2, #0
8003316: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
8003318: 687b ldr r3, [r7, #4]
800331a: b29a uxth r2, r3
800331c: 697b ldr r3, [r7, #20]
800331e: 80da strh r2, [r3, #6]
8003320: e00b b.n 800333a <HAL_PCDEx_PMAConfig+0x78>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
8003322: 697b ldr r3, [r7, #20]
8003324: 2201 movs r2, #1
8003326: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
8003328: 687b ldr r3, [r7, #4]
800332a: b29a uxth r2, r3
800332c: 697b ldr r3, [r7, #20]
800332e: 811a strh r2, [r3, #8]
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
8003330: 687b ldr r3, [r7, #4]
8003332: 0c1b lsrs r3, r3, #16
8003334: b29a uxth r2, r3
8003336: 697b ldr r3, [r7, #20]
8003338: 815a strh r2, [r3, #10]
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
800333a: 2300 movs r3, #0
}
800333c: 4618 mov r0, r3
800333e: 371c adds r7, #28
8003340: 46bd mov sp, r7
8003342: bc80 pop {r7}
8003344: 4770 bx lr
...
08003348 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8003348: b580 push {r7, lr}
800334a: b086 sub sp, #24
800334c: af00 add r7, sp, #0
800334e: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8003350: 687b ldr r3, [r7, #4]
8003352: 2b00 cmp r3, #0
8003354: d101 bne.n 800335a <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8003356: 2301 movs r3, #1
8003358: e272 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800335a: 687b ldr r3, [r7, #4]
800335c: 681b ldr r3, [r3, #0]
800335e: f003 0301 and.w r3, r3, #1
8003362: 2b00 cmp r3, #0
8003364: f000 8087 beq.w 8003476 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8003368: 4b92 ldr r3, [pc, #584] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
800336a: 685b ldr r3, [r3, #4]
800336c: f003 030c and.w r3, r3, #12
8003370: 2b04 cmp r3, #4
8003372: d00c beq.n 800338e <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8003374: 4b8f ldr r3, [pc, #572] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003376: 685b ldr r3, [r3, #4]
8003378: f003 030c and.w r3, r3, #12
800337c: 2b08 cmp r3, #8
800337e: d112 bne.n 80033a6 <HAL_RCC_OscConfig+0x5e>
8003380: 4b8c ldr r3, [pc, #560] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003382: 685b ldr r3, [r3, #4]
8003384: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003388: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800338c: d10b bne.n 80033a6 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800338e: 4b89 ldr r3, [pc, #548] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003390: 681b ldr r3, [r3, #0]
8003392: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003396: 2b00 cmp r3, #0
8003398: d06c beq.n 8003474 <HAL_RCC_OscConfig+0x12c>
800339a: 687b ldr r3, [r7, #4]
800339c: 685b ldr r3, [r3, #4]
800339e: 2b00 cmp r3, #0
80033a0: d168 bne.n 8003474 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
80033a2: 2301 movs r3, #1
80033a4: e24c b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80033a6: 687b ldr r3, [r7, #4]
80033a8: 685b ldr r3, [r3, #4]
80033aa: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80033ae: d106 bne.n 80033be <HAL_RCC_OscConfig+0x76>
80033b0: 4b80 ldr r3, [pc, #512] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033b2: 681b ldr r3, [r3, #0]
80033b4: 4a7f ldr r2, [pc, #508] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033b6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80033ba: 6013 str r3, [r2, #0]
80033bc: e02e b.n 800341c <HAL_RCC_OscConfig+0xd4>
80033be: 687b ldr r3, [r7, #4]
80033c0: 685b ldr r3, [r3, #4]
80033c2: 2b00 cmp r3, #0
80033c4: d10c bne.n 80033e0 <HAL_RCC_OscConfig+0x98>
80033c6: 4b7b ldr r3, [pc, #492] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033c8: 681b ldr r3, [r3, #0]
80033ca: 4a7a ldr r2, [pc, #488] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033cc: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80033d0: 6013 str r3, [r2, #0]
80033d2: 4b78 ldr r3, [pc, #480] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033d4: 681b ldr r3, [r3, #0]
80033d6: 4a77 ldr r2, [pc, #476] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033d8: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80033dc: 6013 str r3, [r2, #0]
80033de: e01d b.n 800341c <HAL_RCC_OscConfig+0xd4>
80033e0: 687b ldr r3, [r7, #4]
80033e2: 685b ldr r3, [r3, #4]
80033e4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
80033e8: d10c bne.n 8003404 <HAL_RCC_OscConfig+0xbc>
80033ea: 4b72 ldr r3, [pc, #456] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033ec: 681b ldr r3, [r3, #0]
80033ee: 4a71 ldr r2, [pc, #452] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033f0: f443 2380 orr.w r3, r3, #262144 @ 0x40000
80033f4: 6013 str r3, [r2, #0]
80033f6: 4b6f ldr r3, [pc, #444] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033f8: 681b ldr r3, [r3, #0]
80033fa: 4a6e ldr r2, [pc, #440] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80033fc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003400: 6013 str r3, [r2, #0]
8003402: e00b b.n 800341c <HAL_RCC_OscConfig+0xd4>
8003404: 4b6b ldr r3, [pc, #428] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003406: 681b ldr r3, [r3, #0]
8003408: 4a6a ldr r2, [pc, #424] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
800340a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800340e: 6013 str r3, [r2, #0]
8003410: 4b68 ldr r3, [pc, #416] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003412: 681b ldr r3, [r3, #0]
8003414: 4a67 ldr r2, [pc, #412] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003416: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800341a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800341c: 687b ldr r3, [r7, #4]
800341e: 685b ldr r3, [r3, #4]
8003420: 2b00 cmp r3, #0
8003422: d013 beq.n 800344c <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8003424: f7fd fd4a bl 8000ebc <HAL_GetTick>
8003428: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800342a: e008 b.n 800343e <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800342c: f7fd fd46 bl 8000ebc <HAL_GetTick>
8003430: 4602 mov r2, r0
8003432: 693b ldr r3, [r7, #16]
8003434: 1ad3 subs r3, r2, r3
8003436: 2b64 cmp r3, #100 @ 0x64
8003438: d901 bls.n 800343e <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
800343a: 2303 movs r3, #3
800343c: e200 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800343e: 4b5d ldr r3, [pc, #372] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003440: 681b ldr r3, [r3, #0]
8003442: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003446: 2b00 cmp r3, #0
8003448: d0f0 beq.n 800342c <HAL_RCC_OscConfig+0xe4>
800344a: e014 b.n 8003476 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800344c: f7fd fd36 bl 8000ebc <HAL_GetTick>
8003450: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003452: e008 b.n 8003466 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8003454: f7fd fd32 bl 8000ebc <HAL_GetTick>
8003458: 4602 mov r2, r0
800345a: 693b ldr r3, [r7, #16]
800345c: 1ad3 subs r3, r2, r3
800345e: 2b64 cmp r3, #100 @ 0x64
8003460: d901 bls.n 8003466 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8003462: 2303 movs r3, #3
8003464: e1ec b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003466: 4b53 ldr r3, [pc, #332] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003468: 681b ldr r3, [r3, #0]
800346a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800346e: 2b00 cmp r3, #0
8003470: d1f0 bne.n 8003454 <HAL_RCC_OscConfig+0x10c>
8003472: e000 b.n 8003476 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003474: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003476: 687b ldr r3, [r7, #4]
8003478: 681b ldr r3, [r3, #0]
800347a: f003 0302 and.w r3, r3, #2
800347e: 2b00 cmp r3, #0
8003480: d063 beq.n 800354a <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8003482: 4b4c ldr r3, [pc, #304] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003484: 685b ldr r3, [r3, #4]
8003486: f003 030c and.w r3, r3, #12
800348a: 2b00 cmp r3, #0
800348c: d00b beq.n 80034a6 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
800348e: 4b49 ldr r3, [pc, #292] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003490: 685b ldr r3, [r3, #4]
8003492: f003 030c and.w r3, r3, #12
8003496: 2b08 cmp r3, #8
8003498: d11c bne.n 80034d4 <HAL_RCC_OscConfig+0x18c>
800349a: 4b46 ldr r3, [pc, #280] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
800349c: 685b ldr r3, [r3, #4]
800349e: f403 3380 and.w r3, r3, #65536 @ 0x10000
80034a2: 2b00 cmp r3, #0
80034a4: d116 bne.n 80034d4 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80034a6: 4b43 ldr r3, [pc, #268] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80034a8: 681b ldr r3, [r3, #0]
80034aa: f003 0302 and.w r3, r3, #2
80034ae: 2b00 cmp r3, #0
80034b0: d005 beq.n 80034be <HAL_RCC_OscConfig+0x176>
80034b2: 687b ldr r3, [r7, #4]
80034b4: 691b ldr r3, [r3, #16]
80034b6: 2b01 cmp r3, #1
80034b8: d001 beq.n 80034be <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
80034ba: 2301 movs r3, #1
80034bc: e1c0 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80034be: 4b3d ldr r3, [pc, #244] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80034c0: 681b ldr r3, [r3, #0]
80034c2: f023 02f8 bic.w r2, r3, #248 @ 0xf8
80034c6: 687b ldr r3, [r7, #4]
80034c8: 695b ldr r3, [r3, #20]
80034ca: 00db lsls r3, r3, #3
80034cc: 4939 ldr r1, [pc, #228] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80034ce: 4313 orrs r3, r2
80034d0: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80034d2: e03a b.n 800354a <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80034d4: 687b ldr r3, [r7, #4]
80034d6: 691b ldr r3, [r3, #16]
80034d8: 2b00 cmp r3, #0
80034da: d020 beq.n 800351e <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80034dc: 4b36 ldr r3, [pc, #216] @ (80035b8 <HAL_RCC_OscConfig+0x270>)
80034de: 2201 movs r2, #1
80034e0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80034e2: f7fd fceb bl 8000ebc <HAL_GetTick>
80034e6: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80034e8: e008 b.n 80034fc <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80034ea: f7fd fce7 bl 8000ebc <HAL_GetTick>
80034ee: 4602 mov r2, r0
80034f0: 693b ldr r3, [r7, #16]
80034f2: 1ad3 subs r3, r2, r3
80034f4: 2b02 cmp r3, #2
80034f6: d901 bls.n 80034fc <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
80034f8: 2303 movs r3, #3
80034fa: e1a1 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80034fc: 4b2d ldr r3, [pc, #180] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
80034fe: 681b ldr r3, [r3, #0]
8003500: f003 0302 and.w r3, r3, #2
8003504: 2b00 cmp r3, #0
8003506: d0f0 beq.n 80034ea <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003508: 4b2a ldr r3, [pc, #168] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
800350a: 681b ldr r3, [r3, #0]
800350c: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8003510: 687b ldr r3, [r7, #4]
8003512: 695b ldr r3, [r3, #20]
8003514: 00db lsls r3, r3, #3
8003516: 4927 ldr r1, [pc, #156] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003518: 4313 orrs r3, r2
800351a: 600b str r3, [r1, #0]
800351c: e015 b.n 800354a <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800351e: 4b26 ldr r3, [pc, #152] @ (80035b8 <HAL_RCC_OscConfig+0x270>)
8003520: 2200 movs r2, #0
8003522: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003524: f7fd fcca bl 8000ebc <HAL_GetTick>
8003528: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800352a: e008 b.n 800353e <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800352c: f7fd fcc6 bl 8000ebc <HAL_GetTick>
8003530: 4602 mov r2, r0
8003532: 693b ldr r3, [r7, #16]
8003534: 1ad3 subs r3, r2, r3
8003536: 2b02 cmp r3, #2
8003538: d901 bls.n 800353e <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
800353a: 2303 movs r3, #3
800353c: e180 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800353e: 4b1d ldr r3, [pc, #116] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003540: 681b ldr r3, [r3, #0]
8003542: f003 0302 and.w r3, r3, #2
8003546: 2b00 cmp r3, #0
8003548: d1f0 bne.n 800352c <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800354a: 687b ldr r3, [r7, #4]
800354c: 681b ldr r3, [r3, #0]
800354e: f003 0308 and.w r3, r3, #8
8003552: 2b00 cmp r3, #0
8003554: d03a beq.n 80035cc <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8003556: 687b ldr r3, [r7, #4]
8003558: 699b ldr r3, [r3, #24]
800355a: 2b00 cmp r3, #0
800355c: d019 beq.n 8003592 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800355e: 4b17 ldr r3, [pc, #92] @ (80035bc <HAL_RCC_OscConfig+0x274>)
8003560: 2201 movs r2, #1
8003562: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003564: f7fd fcaa bl 8000ebc <HAL_GetTick>
8003568: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800356a: e008 b.n 800357e <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800356c: f7fd fca6 bl 8000ebc <HAL_GetTick>
8003570: 4602 mov r2, r0
8003572: 693b ldr r3, [r7, #16]
8003574: 1ad3 subs r3, r2, r3
8003576: 2b02 cmp r3, #2
8003578: d901 bls.n 800357e <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
800357a: 2303 movs r3, #3
800357c: e160 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800357e: 4b0d ldr r3, [pc, #52] @ (80035b4 <HAL_RCC_OscConfig+0x26c>)
8003580: 6a5b ldr r3, [r3, #36] @ 0x24
8003582: f003 0302 and.w r3, r3, #2
8003586: 2b00 cmp r3, #0
8003588: d0f0 beq.n 800356c <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
800358a: 2001 movs r0, #1
800358c: f000 fa9c bl 8003ac8 <RCC_Delay>
8003590: e01c b.n 80035cc <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003592: 4b0a ldr r3, [pc, #40] @ (80035bc <HAL_RCC_OscConfig+0x274>)
8003594: 2200 movs r2, #0
8003596: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003598: f7fd fc90 bl 8000ebc <HAL_GetTick>
800359c: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800359e: e00f b.n 80035c0 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80035a0: f7fd fc8c bl 8000ebc <HAL_GetTick>
80035a4: 4602 mov r2, r0
80035a6: 693b ldr r3, [r7, #16]
80035a8: 1ad3 subs r3, r2, r3
80035aa: 2b02 cmp r3, #2
80035ac: d908 bls.n 80035c0 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
80035ae: 2303 movs r3, #3
80035b0: e146 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
80035b2: bf00 nop
80035b4: 40021000 .word 0x40021000
80035b8: 42420000 .word 0x42420000
80035bc: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80035c0: 4b92 ldr r3, [pc, #584] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80035c2: 6a5b ldr r3, [r3, #36] @ 0x24
80035c4: f003 0302 and.w r3, r3, #2
80035c8: 2b00 cmp r3, #0
80035ca: d1e9 bne.n 80035a0 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80035cc: 687b ldr r3, [r7, #4]
80035ce: 681b ldr r3, [r3, #0]
80035d0: f003 0304 and.w r3, r3, #4
80035d4: 2b00 cmp r3, #0
80035d6: f000 80a6 beq.w 8003726 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
80035da: 2300 movs r3, #0
80035dc: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80035de: 4b8b ldr r3, [pc, #556] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80035e0: 69db ldr r3, [r3, #28]
80035e2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80035e6: 2b00 cmp r3, #0
80035e8: d10d bne.n 8003606 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
80035ea: 4b88 ldr r3, [pc, #544] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80035ec: 69db ldr r3, [r3, #28]
80035ee: 4a87 ldr r2, [pc, #540] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80035f0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80035f4: 61d3 str r3, [r2, #28]
80035f6: 4b85 ldr r3, [pc, #532] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80035f8: 69db ldr r3, [r3, #28]
80035fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80035fe: 60bb str r3, [r7, #8]
8003600: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003602: 2301 movs r3, #1
8003604: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003606: 4b82 ldr r3, [pc, #520] @ (8003810 <HAL_RCC_OscConfig+0x4c8>)
8003608: 681b ldr r3, [r3, #0]
800360a: f403 7380 and.w r3, r3, #256 @ 0x100
800360e: 2b00 cmp r3, #0
8003610: d118 bne.n 8003644 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8003612: 4b7f ldr r3, [pc, #508] @ (8003810 <HAL_RCC_OscConfig+0x4c8>)
8003614: 681b ldr r3, [r3, #0]
8003616: 4a7e ldr r2, [pc, #504] @ (8003810 <HAL_RCC_OscConfig+0x4c8>)
8003618: f443 7380 orr.w r3, r3, #256 @ 0x100
800361c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800361e: f7fd fc4d bl 8000ebc <HAL_GetTick>
8003622: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003624: e008 b.n 8003638 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003626: f7fd fc49 bl 8000ebc <HAL_GetTick>
800362a: 4602 mov r2, r0
800362c: 693b ldr r3, [r7, #16]
800362e: 1ad3 subs r3, r2, r3
8003630: 2b64 cmp r3, #100 @ 0x64
8003632: d901 bls.n 8003638 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8003634: 2303 movs r3, #3
8003636: e103 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003638: 4b75 ldr r3, [pc, #468] @ (8003810 <HAL_RCC_OscConfig+0x4c8>)
800363a: 681b ldr r3, [r3, #0]
800363c: f403 7380 and.w r3, r3, #256 @ 0x100
8003640: 2b00 cmp r3, #0
8003642: d0f0 beq.n 8003626 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003644: 687b ldr r3, [r7, #4]
8003646: 68db ldr r3, [r3, #12]
8003648: 2b01 cmp r3, #1
800364a: d106 bne.n 800365a <HAL_RCC_OscConfig+0x312>
800364c: 4b6f ldr r3, [pc, #444] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
800364e: 6a1b ldr r3, [r3, #32]
8003650: 4a6e ldr r2, [pc, #440] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003652: f043 0301 orr.w r3, r3, #1
8003656: 6213 str r3, [r2, #32]
8003658: e02d b.n 80036b6 <HAL_RCC_OscConfig+0x36e>
800365a: 687b ldr r3, [r7, #4]
800365c: 68db ldr r3, [r3, #12]
800365e: 2b00 cmp r3, #0
8003660: d10c bne.n 800367c <HAL_RCC_OscConfig+0x334>
8003662: 4b6a ldr r3, [pc, #424] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003664: 6a1b ldr r3, [r3, #32]
8003666: 4a69 ldr r2, [pc, #420] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003668: f023 0301 bic.w r3, r3, #1
800366c: 6213 str r3, [r2, #32]
800366e: 4b67 ldr r3, [pc, #412] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003670: 6a1b ldr r3, [r3, #32]
8003672: 4a66 ldr r2, [pc, #408] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003674: f023 0304 bic.w r3, r3, #4
8003678: 6213 str r3, [r2, #32]
800367a: e01c b.n 80036b6 <HAL_RCC_OscConfig+0x36e>
800367c: 687b ldr r3, [r7, #4]
800367e: 68db ldr r3, [r3, #12]
8003680: 2b05 cmp r3, #5
8003682: d10c bne.n 800369e <HAL_RCC_OscConfig+0x356>
8003684: 4b61 ldr r3, [pc, #388] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003686: 6a1b ldr r3, [r3, #32]
8003688: 4a60 ldr r2, [pc, #384] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
800368a: f043 0304 orr.w r3, r3, #4
800368e: 6213 str r3, [r2, #32]
8003690: 4b5e ldr r3, [pc, #376] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003692: 6a1b ldr r3, [r3, #32]
8003694: 4a5d ldr r2, [pc, #372] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003696: f043 0301 orr.w r3, r3, #1
800369a: 6213 str r3, [r2, #32]
800369c: e00b b.n 80036b6 <HAL_RCC_OscConfig+0x36e>
800369e: 4b5b ldr r3, [pc, #364] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80036a0: 6a1b ldr r3, [r3, #32]
80036a2: 4a5a ldr r2, [pc, #360] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80036a4: f023 0301 bic.w r3, r3, #1
80036a8: 6213 str r3, [r2, #32]
80036aa: 4b58 ldr r3, [pc, #352] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80036ac: 6a1b ldr r3, [r3, #32]
80036ae: 4a57 ldr r2, [pc, #348] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80036b0: f023 0304 bic.w r3, r3, #4
80036b4: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80036b6: 687b ldr r3, [r7, #4]
80036b8: 68db ldr r3, [r3, #12]
80036ba: 2b00 cmp r3, #0
80036bc: d015 beq.n 80036ea <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80036be: f7fd fbfd bl 8000ebc <HAL_GetTick>
80036c2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80036c4: e00a b.n 80036dc <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80036c6: f7fd fbf9 bl 8000ebc <HAL_GetTick>
80036ca: 4602 mov r2, r0
80036cc: 693b ldr r3, [r7, #16]
80036ce: 1ad3 subs r3, r2, r3
80036d0: f241 3288 movw r2, #5000 @ 0x1388
80036d4: 4293 cmp r3, r2
80036d6: d901 bls.n 80036dc <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
80036d8: 2303 movs r3, #3
80036da: e0b1 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80036dc: 4b4b ldr r3, [pc, #300] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80036de: 6a1b ldr r3, [r3, #32]
80036e0: f003 0302 and.w r3, r3, #2
80036e4: 2b00 cmp r3, #0
80036e6: d0ee beq.n 80036c6 <HAL_RCC_OscConfig+0x37e>
80036e8: e014 b.n 8003714 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80036ea: f7fd fbe7 bl 8000ebc <HAL_GetTick>
80036ee: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80036f0: e00a b.n 8003708 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80036f2: f7fd fbe3 bl 8000ebc <HAL_GetTick>
80036f6: 4602 mov r2, r0
80036f8: 693b ldr r3, [r7, #16]
80036fa: 1ad3 subs r3, r2, r3
80036fc: f241 3288 movw r2, #5000 @ 0x1388
8003700: 4293 cmp r3, r2
8003702: d901 bls.n 8003708 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8003704: 2303 movs r3, #3
8003706: e09b b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003708: 4b40 ldr r3, [pc, #256] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
800370a: 6a1b ldr r3, [r3, #32]
800370c: f003 0302 and.w r3, r3, #2
8003710: 2b00 cmp r3, #0
8003712: d1ee bne.n 80036f2 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8003714: 7dfb ldrb r3, [r7, #23]
8003716: 2b01 cmp r3, #1
8003718: d105 bne.n 8003726 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
800371a: 4b3c ldr r3, [pc, #240] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
800371c: 69db ldr r3, [r3, #28]
800371e: 4a3b ldr r2, [pc, #236] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003720: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003724: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8003726: 687b ldr r3, [r7, #4]
8003728: 69db ldr r3, [r3, #28]
800372a: 2b00 cmp r3, #0
800372c: f000 8087 beq.w 800383e <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8003730: 4b36 ldr r3, [pc, #216] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003732: 685b ldr r3, [r3, #4]
8003734: f003 030c and.w r3, r3, #12
8003738: 2b08 cmp r3, #8
800373a: d061 beq.n 8003800 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800373c: 687b ldr r3, [r7, #4]
800373e: 69db ldr r3, [r3, #28]
8003740: 2b02 cmp r3, #2
8003742: d146 bne.n 80037d2 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003744: 4b33 ldr r3, [pc, #204] @ (8003814 <HAL_RCC_OscConfig+0x4cc>)
8003746: 2200 movs r2, #0
8003748: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800374a: f7fd fbb7 bl 8000ebc <HAL_GetTick>
800374e: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003750: e008 b.n 8003764 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003752: f7fd fbb3 bl 8000ebc <HAL_GetTick>
8003756: 4602 mov r2, r0
8003758: 693b ldr r3, [r7, #16]
800375a: 1ad3 subs r3, r2, r3
800375c: 2b02 cmp r3, #2
800375e: d901 bls.n 8003764 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8003760: 2303 movs r3, #3
8003762: e06d b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003764: 4b29 ldr r3, [pc, #164] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003766: 681b ldr r3, [r3, #0]
8003768: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800376c: 2b00 cmp r3, #0
800376e: d1f0 bne.n 8003752 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8003770: 687b ldr r3, [r7, #4]
8003772: 6a1b ldr r3, [r3, #32]
8003774: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003778: d108 bne.n 800378c <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
800377a: 4b24 ldr r3, [pc, #144] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
800377c: 685b ldr r3, [r3, #4]
800377e: f423 3200 bic.w r2, r3, #131072 @ 0x20000
8003782: 687b ldr r3, [r7, #4]
8003784: 689b ldr r3, [r3, #8]
8003786: 4921 ldr r1, [pc, #132] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
8003788: 4313 orrs r3, r2
800378a: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800378c: 4b1f ldr r3, [pc, #124] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
800378e: 685b ldr r3, [r3, #4]
8003790: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8003794: 687b ldr r3, [r7, #4]
8003796: 6a19 ldr r1, [r3, #32]
8003798: 687b ldr r3, [r7, #4]
800379a: 6a5b ldr r3, [r3, #36] @ 0x24
800379c: 430b orrs r3, r1
800379e: 491b ldr r1, [pc, #108] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80037a0: 4313 orrs r3, r2
80037a2: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80037a4: 4b1b ldr r3, [pc, #108] @ (8003814 <HAL_RCC_OscConfig+0x4cc>)
80037a6: 2201 movs r2, #1
80037a8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80037aa: f7fd fb87 bl 8000ebc <HAL_GetTick>
80037ae: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80037b0: e008 b.n 80037c4 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80037b2: f7fd fb83 bl 8000ebc <HAL_GetTick>
80037b6: 4602 mov r2, r0
80037b8: 693b ldr r3, [r7, #16]
80037ba: 1ad3 subs r3, r2, r3
80037bc: 2b02 cmp r3, #2
80037be: d901 bls.n 80037c4 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
80037c0: 2303 movs r3, #3
80037c2: e03d b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80037c4: 4b11 ldr r3, [pc, #68] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80037c6: 681b ldr r3, [r3, #0]
80037c8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80037cc: 2b00 cmp r3, #0
80037ce: d0f0 beq.n 80037b2 <HAL_RCC_OscConfig+0x46a>
80037d0: e035 b.n 800383e <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80037d2: 4b10 ldr r3, [pc, #64] @ (8003814 <HAL_RCC_OscConfig+0x4cc>)
80037d4: 2200 movs r2, #0
80037d6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80037d8: f7fd fb70 bl 8000ebc <HAL_GetTick>
80037dc: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80037de: e008 b.n 80037f2 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80037e0: f7fd fb6c bl 8000ebc <HAL_GetTick>
80037e4: 4602 mov r2, r0
80037e6: 693b ldr r3, [r7, #16]
80037e8: 1ad3 subs r3, r2, r3
80037ea: 2b02 cmp r3, #2
80037ec: d901 bls.n 80037f2 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
80037ee: 2303 movs r3, #3
80037f0: e026 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80037f2: 4b06 ldr r3, [pc, #24] @ (800380c <HAL_RCC_OscConfig+0x4c4>)
80037f4: 681b ldr r3, [r3, #0]
80037f6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80037fa: 2b00 cmp r3, #0
80037fc: d1f0 bne.n 80037e0 <HAL_RCC_OscConfig+0x498>
80037fe: e01e b.n 800383e <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003800: 687b ldr r3, [r7, #4]
8003802: 69db ldr r3, [r3, #28]
8003804: 2b01 cmp r3, #1
8003806: d107 bne.n 8003818 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8003808: 2301 movs r3, #1
800380a: e019 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
800380c: 40021000 .word 0x40021000
8003810: 40007000 .word 0x40007000
8003814: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8003818: 4b0b ldr r3, [pc, #44] @ (8003848 <HAL_RCC_OscConfig+0x500>)
800381a: 685b ldr r3, [r3, #4]
800381c: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800381e: 68fb ldr r3, [r7, #12]
8003820: f403 3280 and.w r2, r3, #65536 @ 0x10000
8003824: 687b ldr r3, [r7, #4]
8003826: 6a1b ldr r3, [r3, #32]
8003828: 429a cmp r2, r3
800382a: d106 bne.n 800383a <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
800382c: 68fb ldr r3, [r7, #12]
800382e: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8003832: 687b ldr r3, [r7, #4]
8003834: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003836: 429a cmp r2, r3
8003838: d001 beq.n 800383e <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
800383a: 2301 movs r3, #1
800383c: e000 b.n 8003840 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
800383e: 2300 movs r3, #0
}
8003840: 4618 mov r0, r3
8003842: 3718 adds r7, #24
8003844: 46bd mov sp, r7
8003846: bd80 pop {r7, pc}
8003848: 40021000 .word 0x40021000
0800384c <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
800384c: b580 push {r7, lr}
800384e: b084 sub sp, #16
8003850: af00 add r7, sp, #0
8003852: 6078 str r0, [r7, #4]
8003854: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8003856: 687b ldr r3, [r7, #4]
8003858: 2b00 cmp r3, #0
800385a: d101 bne.n 8003860 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
800385c: 2301 movs r3, #1
800385e: e0d0 b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8003860: 4b6a ldr r3, [pc, #424] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
8003862: 681b ldr r3, [r3, #0]
8003864: f003 0307 and.w r3, r3, #7
8003868: 683a ldr r2, [r7, #0]
800386a: 429a cmp r2, r3
800386c: d910 bls.n 8003890 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800386e: 4b67 ldr r3, [pc, #412] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
8003870: 681b ldr r3, [r3, #0]
8003872: f023 0207 bic.w r2, r3, #7
8003876: 4965 ldr r1, [pc, #404] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
8003878: 683b ldr r3, [r7, #0]
800387a: 4313 orrs r3, r2
800387c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800387e: 4b63 ldr r3, [pc, #396] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
8003880: 681b ldr r3, [r3, #0]
8003882: f003 0307 and.w r3, r3, #7
8003886: 683a ldr r2, [r7, #0]
8003888: 429a cmp r2, r3
800388a: d001 beq.n 8003890 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
800388c: 2301 movs r3, #1
800388e: e0b8 b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8003890: 687b ldr r3, [r7, #4]
8003892: 681b ldr r3, [r3, #0]
8003894: f003 0302 and.w r3, r3, #2
8003898: 2b00 cmp r3, #0
800389a: d020 beq.n 80038de <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800389c: 687b ldr r3, [r7, #4]
800389e: 681b ldr r3, [r3, #0]
80038a0: f003 0304 and.w r3, r3, #4
80038a4: 2b00 cmp r3, #0
80038a6: d005 beq.n 80038b4 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80038a8: 4b59 ldr r3, [pc, #356] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038aa: 685b ldr r3, [r3, #4]
80038ac: 4a58 ldr r2, [pc, #352] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038ae: f443 63e0 orr.w r3, r3, #1792 @ 0x700
80038b2: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80038b4: 687b ldr r3, [r7, #4]
80038b6: 681b ldr r3, [r3, #0]
80038b8: f003 0308 and.w r3, r3, #8
80038bc: 2b00 cmp r3, #0
80038be: d005 beq.n 80038cc <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80038c0: 4b53 ldr r3, [pc, #332] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038c2: 685b ldr r3, [r3, #4]
80038c4: 4a52 ldr r2, [pc, #328] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038c6: f443 5360 orr.w r3, r3, #14336 @ 0x3800
80038ca: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80038cc: 4b50 ldr r3, [pc, #320] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038ce: 685b ldr r3, [r3, #4]
80038d0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80038d4: 687b ldr r3, [r7, #4]
80038d6: 689b ldr r3, [r3, #8]
80038d8: 494d ldr r1, [pc, #308] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038da: 4313 orrs r3, r2
80038dc: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80038de: 687b ldr r3, [r7, #4]
80038e0: 681b ldr r3, [r3, #0]
80038e2: f003 0301 and.w r3, r3, #1
80038e6: 2b00 cmp r3, #0
80038e8: d040 beq.n 800396c <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80038ea: 687b ldr r3, [r7, #4]
80038ec: 685b ldr r3, [r3, #4]
80038ee: 2b01 cmp r3, #1
80038f0: d107 bne.n 8003902 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80038f2: 4b47 ldr r3, [pc, #284] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80038f4: 681b ldr r3, [r3, #0]
80038f6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80038fa: 2b00 cmp r3, #0
80038fc: d115 bne.n 800392a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80038fe: 2301 movs r3, #1
8003900: e07f b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003902: 687b ldr r3, [r7, #4]
8003904: 685b ldr r3, [r3, #4]
8003906: 2b02 cmp r3, #2
8003908: d107 bne.n 800391a <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800390a: 4b41 ldr r3, [pc, #260] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
800390c: 681b ldr r3, [r3, #0]
800390e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003912: 2b00 cmp r3, #0
8003914: d109 bne.n 800392a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003916: 2301 movs r3, #1
8003918: e073 b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800391a: 4b3d ldr r3, [pc, #244] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
800391c: 681b ldr r3, [r3, #0]
800391e: f003 0302 and.w r3, r3, #2
8003922: 2b00 cmp r3, #0
8003924: d101 bne.n 800392a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003926: 2301 movs r3, #1
8003928: e06b b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800392a: 4b39 ldr r3, [pc, #228] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
800392c: 685b ldr r3, [r3, #4]
800392e: f023 0203 bic.w r2, r3, #3
8003932: 687b ldr r3, [r7, #4]
8003934: 685b ldr r3, [r3, #4]
8003936: 4936 ldr r1, [pc, #216] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
8003938: 4313 orrs r3, r2
800393a: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
800393c: f7fd fabe bl 8000ebc <HAL_GetTick>
8003940: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003942: e00a b.n 800395a <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003944: f7fd faba bl 8000ebc <HAL_GetTick>
8003948: 4602 mov r2, r0
800394a: 68fb ldr r3, [r7, #12]
800394c: 1ad3 subs r3, r2, r3
800394e: f241 3288 movw r2, #5000 @ 0x1388
8003952: 4293 cmp r3, r2
8003954: d901 bls.n 800395a <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8003956: 2303 movs r3, #3
8003958: e053 b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800395a: 4b2d ldr r3, [pc, #180] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
800395c: 685b ldr r3, [r3, #4]
800395e: f003 020c and.w r2, r3, #12
8003962: 687b ldr r3, [r7, #4]
8003964: 685b ldr r3, [r3, #4]
8003966: 009b lsls r3, r3, #2
8003968: 429a cmp r2, r3
800396a: d1eb bne.n 8003944 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
800396c: 4b27 ldr r3, [pc, #156] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
800396e: 681b ldr r3, [r3, #0]
8003970: f003 0307 and.w r3, r3, #7
8003974: 683a ldr r2, [r7, #0]
8003976: 429a cmp r2, r3
8003978: d210 bcs.n 800399c <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800397a: 4b24 ldr r3, [pc, #144] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
800397c: 681b ldr r3, [r3, #0]
800397e: f023 0207 bic.w r2, r3, #7
8003982: 4922 ldr r1, [pc, #136] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
8003984: 683b ldr r3, [r7, #0]
8003986: 4313 orrs r3, r2
8003988: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800398a: 4b20 ldr r3, [pc, #128] @ (8003a0c <HAL_RCC_ClockConfig+0x1c0>)
800398c: 681b ldr r3, [r3, #0]
800398e: f003 0307 and.w r3, r3, #7
8003992: 683a ldr r2, [r7, #0]
8003994: 429a cmp r2, r3
8003996: d001 beq.n 800399c <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8003998: 2301 movs r3, #1
800399a: e032 b.n 8003a02 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800399c: 687b ldr r3, [r7, #4]
800399e: 681b ldr r3, [r3, #0]
80039a0: f003 0304 and.w r3, r3, #4
80039a4: 2b00 cmp r3, #0
80039a6: d008 beq.n 80039ba <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80039a8: 4b19 ldr r3, [pc, #100] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80039aa: 685b ldr r3, [r3, #4]
80039ac: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80039b0: 687b ldr r3, [r7, #4]
80039b2: 68db ldr r3, [r3, #12]
80039b4: 4916 ldr r1, [pc, #88] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80039b6: 4313 orrs r3, r2
80039b8: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80039ba: 687b ldr r3, [r7, #4]
80039bc: 681b ldr r3, [r3, #0]
80039be: f003 0308 and.w r3, r3, #8
80039c2: 2b00 cmp r3, #0
80039c4: d009 beq.n 80039da <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
80039c6: 4b12 ldr r3, [pc, #72] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80039c8: 685b ldr r3, [r3, #4]
80039ca: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80039ce: 687b ldr r3, [r7, #4]
80039d0: 691b ldr r3, [r3, #16]
80039d2: 00db lsls r3, r3, #3
80039d4: 490e ldr r1, [pc, #56] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80039d6: 4313 orrs r3, r2
80039d8: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80039da: f000 f821 bl 8003a20 <HAL_RCC_GetSysClockFreq>
80039de: 4602 mov r2, r0
80039e0: 4b0b ldr r3, [pc, #44] @ (8003a10 <HAL_RCC_ClockConfig+0x1c4>)
80039e2: 685b ldr r3, [r3, #4]
80039e4: 091b lsrs r3, r3, #4
80039e6: f003 030f and.w r3, r3, #15
80039ea: 490a ldr r1, [pc, #40] @ (8003a14 <HAL_RCC_ClockConfig+0x1c8>)
80039ec: 5ccb ldrb r3, [r1, r3]
80039ee: fa22 f303 lsr.w r3, r2, r3
80039f2: 4a09 ldr r2, [pc, #36] @ (8003a18 <HAL_RCC_ClockConfig+0x1cc>)
80039f4: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
80039f6: 4b09 ldr r3, [pc, #36] @ (8003a1c <HAL_RCC_ClockConfig+0x1d0>)
80039f8: 681b ldr r3, [r3, #0]
80039fa: 4618 mov r0, r3
80039fc: f7fd fa1c bl 8000e38 <HAL_InitTick>
return HAL_OK;
8003a00: 2300 movs r3, #0
}
8003a02: 4618 mov r0, r3
8003a04: 3710 adds r7, #16
8003a06: 46bd mov sp, r7
8003a08: bd80 pop {r7, pc}
8003a0a: bf00 nop
8003a0c: 40022000 .word 0x40022000
8003a10: 40021000 .word 0x40021000
8003a14: 08009ae0 .word 0x08009ae0
8003a18: 20000000 .word 0x20000000
8003a1c: 20000004 .word 0x20000004
08003a20 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003a20: b480 push {r7}
8003a22: b087 sub sp, #28
8003a24: af00 add r7, sp, #0
#else
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8003a26: 2300 movs r3, #0
8003a28: 60fb str r3, [r7, #12]
8003a2a: 2300 movs r3, #0
8003a2c: 60bb str r3, [r7, #8]
8003a2e: 2300 movs r3, #0
8003a30: 617b str r3, [r7, #20]
8003a32: 2300 movs r3, #0
8003a34: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
8003a36: 2300 movs r3, #0
8003a38: 613b str r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8003a3a: 4b1e ldr r3, [pc, #120] @ (8003ab4 <HAL_RCC_GetSysClockFreq+0x94>)
8003a3c: 685b ldr r3, [r3, #4]
8003a3e: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8003a40: 68fb ldr r3, [r7, #12]
8003a42: f003 030c and.w r3, r3, #12
8003a46: 2b04 cmp r3, #4
8003a48: d002 beq.n 8003a50 <HAL_RCC_GetSysClockFreq+0x30>
8003a4a: 2b08 cmp r3, #8
8003a4c: d003 beq.n 8003a56 <HAL_RCC_GetSysClockFreq+0x36>
8003a4e: e027 b.n 8003aa0 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8003a50: 4b19 ldr r3, [pc, #100] @ (8003ab8 <HAL_RCC_GetSysClockFreq+0x98>)
8003a52: 613b str r3, [r7, #16]
break;
8003a54: e027 b.n 8003aa6 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8003a56: 68fb ldr r3, [r7, #12]
8003a58: 0c9b lsrs r3, r3, #18
8003a5a: f003 030f and.w r3, r3, #15
8003a5e: 4a17 ldr r2, [pc, #92] @ (8003abc <HAL_RCC_GetSysClockFreq+0x9c>)
8003a60: 5cd3 ldrb r3, [r2, r3]
8003a62: 607b str r3, [r7, #4]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8003a64: 68fb ldr r3, [r7, #12]
8003a66: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003a6a: 2b00 cmp r3, #0
8003a6c: d010 beq.n 8003a90 <HAL_RCC_GetSysClockFreq+0x70>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8003a6e: 4b11 ldr r3, [pc, #68] @ (8003ab4 <HAL_RCC_GetSysClockFreq+0x94>)
8003a70: 685b ldr r3, [r3, #4]
8003a72: 0c5b lsrs r3, r3, #17
8003a74: f003 0301 and.w r3, r3, #1
8003a78: 4a11 ldr r2, [pc, #68] @ (8003ac0 <HAL_RCC_GetSysClockFreq+0xa0>)
8003a7a: 5cd3 ldrb r3, [r2, r3]
8003a7c: 60bb str r3, [r7, #8]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8003a7e: 687b ldr r3, [r7, #4]
8003a80: 4a0d ldr r2, [pc, #52] @ (8003ab8 <HAL_RCC_GetSysClockFreq+0x98>)
8003a82: fb03 f202 mul.w r2, r3, r2
8003a86: 68bb ldr r3, [r7, #8]
8003a88: fbb2 f3f3 udiv r3, r2, r3
8003a8c: 617b str r3, [r7, #20]
8003a8e: e004 b.n 8003a9a <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8003a90: 687b ldr r3, [r7, #4]
8003a92: 4a0c ldr r2, [pc, #48] @ (8003ac4 <HAL_RCC_GetSysClockFreq+0xa4>)
8003a94: fb02 f303 mul.w r3, r2, r3
8003a98: 617b str r3, [r7, #20]
}
sysclockfreq = pllclk;
8003a9a: 697b ldr r3, [r7, #20]
8003a9c: 613b str r3, [r7, #16]
break;
8003a9e: e002 b.n 8003aa6 <HAL_RCC_GetSysClockFreq+0x86>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8003aa0: 4b05 ldr r3, [pc, #20] @ (8003ab8 <HAL_RCC_GetSysClockFreq+0x98>)
8003aa2: 613b str r3, [r7, #16]
break;
8003aa4: bf00 nop
}
}
return sysclockfreq;
8003aa6: 693b ldr r3, [r7, #16]
}
8003aa8: 4618 mov r0, r3
8003aaa: 371c adds r7, #28
8003aac: 46bd mov sp, r7
8003aae: bc80 pop {r7}
8003ab0: 4770 bx lr
8003ab2: bf00 nop
8003ab4: 40021000 .word 0x40021000
8003ab8: 007a1200 .word 0x007a1200
8003abc: 08009af0 .word 0x08009af0
8003ac0: 08009b00 .word 0x08009b00
8003ac4: 003d0900 .word 0x003d0900
08003ac8 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8003ac8: b480 push {r7}
8003aca: b085 sub sp, #20
8003acc: af00 add r7, sp, #0
8003ace: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8003ad0: 4b0a ldr r3, [pc, #40] @ (8003afc <RCC_Delay+0x34>)
8003ad2: 681b ldr r3, [r3, #0]
8003ad4: 4a0a ldr r2, [pc, #40] @ (8003b00 <RCC_Delay+0x38>)
8003ad6: fba2 2303 umull r2, r3, r2, r3
8003ada: 0a5b lsrs r3, r3, #9
8003adc: 687a ldr r2, [r7, #4]
8003ade: fb02 f303 mul.w r3, r2, r3
8003ae2: 60fb str r3, [r7, #12]
do
{
__NOP();
8003ae4: bf00 nop
}
while (Delay --);
8003ae6: 68fb ldr r3, [r7, #12]
8003ae8: 1e5a subs r2, r3, #1
8003aea: 60fa str r2, [r7, #12]
8003aec: 2b00 cmp r3, #0
8003aee: d1f9 bne.n 8003ae4 <RCC_Delay+0x1c>
}
8003af0: bf00 nop
8003af2: bf00 nop
8003af4: 3714 adds r7, #20
8003af6: 46bd mov sp, r7
8003af8: bc80 pop {r7}
8003afa: 4770 bx lr
8003afc: 20000000 .word 0x20000000
8003b00: 10624dd3 .word 0x10624dd3
08003b04 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8003b04: b580 push {r7, lr}
8003b06: b086 sub sp, #24
8003b08: af00 add r7, sp, #0
8003b0a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8003b0c: 2300 movs r3, #0
8003b0e: 613b str r3, [r7, #16]
8003b10: 2300 movs r3, #0
8003b12: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8003b14: 687b ldr r3, [r7, #4]
8003b16: 681b ldr r3, [r3, #0]
8003b18: f003 0301 and.w r3, r3, #1
8003b1c: 2b00 cmp r3, #0
8003b1e: d07d beq.n 8003c1c <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8003b20: 2300 movs r3, #0
8003b22: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8003b24: 4b4f ldr r3, [pc, #316] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003b26: 69db ldr r3, [r3, #28]
8003b28: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003b2c: 2b00 cmp r3, #0
8003b2e: d10d bne.n 8003b4c <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003b30: 4b4c ldr r3, [pc, #304] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003b32: 69db ldr r3, [r3, #28]
8003b34: 4a4b ldr r2, [pc, #300] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003b36: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003b3a: 61d3 str r3, [r2, #28]
8003b3c: 4b49 ldr r3, [pc, #292] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003b3e: 69db ldr r3, [r3, #28]
8003b40: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003b44: 60bb str r3, [r7, #8]
8003b46: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003b48: 2301 movs r3, #1
8003b4a: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003b4c: 4b46 ldr r3, [pc, #280] @ (8003c68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8003b4e: 681b ldr r3, [r3, #0]
8003b50: f403 7380 and.w r3, r3, #256 @ 0x100
8003b54: 2b00 cmp r3, #0
8003b56: d118 bne.n 8003b8a <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8003b58: 4b43 ldr r3, [pc, #268] @ (8003c68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8003b5a: 681b ldr r3, [r3, #0]
8003b5c: 4a42 ldr r2, [pc, #264] @ (8003c68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8003b5e: f443 7380 orr.w r3, r3, #256 @ 0x100
8003b62: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003b64: f7fd f9aa bl 8000ebc <HAL_GetTick>
8003b68: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003b6a: e008 b.n 8003b7e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003b6c: f7fd f9a6 bl 8000ebc <HAL_GetTick>
8003b70: 4602 mov r2, r0
8003b72: 693b ldr r3, [r7, #16]
8003b74: 1ad3 subs r3, r2, r3
8003b76: 2b64 cmp r3, #100 @ 0x64
8003b78: d901 bls.n 8003b7e <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8003b7a: 2303 movs r3, #3
8003b7c: e06d b.n 8003c5a <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003b7e: 4b3a ldr r3, [pc, #232] @ (8003c68 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8003b80: 681b ldr r3, [r3, #0]
8003b82: f403 7380 and.w r3, r3, #256 @ 0x100
8003b86: 2b00 cmp r3, #0
8003b88: d0f0 beq.n 8003b6c <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8003b8a: 4b36 ldr r3, [pc, #216] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003b8c: 6a1b ldr r3, [r3, #32]
8003b8e: f403 7340 and.w r3, r3, #768 @ 0x300
8003b92: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8003b94: 68fb ldr r3, [r7, #12]
8003b96: 2b00 cmp r3, #0
8003b98: d02e beq.n 8003bf8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8003b9a: 687b ldr r3, [r7, #4]
8003b9c: 685b ldr r3, [r3, #4]
8003b9e: f403 7340 and.w r3, r3, #768 @ 0x300
8003ba2: 68fa ldr r2, [r7, #12]
8003ba4: 429a cmp r2, r3
8003ba6: d027 beq.n 8003bf8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8003ba8: 4b2e ldr r3, [pc, #184] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003baa: 6a1b ldr r3, [r3, #32]
8003bac: f423 7340 bic.w r3, r3, #768 @ 0x300
8003bb0: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8003bb2: 4b2e ldr r3, [pc, #184] @ (8003c6c <HAL_RCCEx_PeriphCLKConfig+0x168>)
8003bb4: 2201 movs r2, #1
8003bb6: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8003bb8: 4b2c ldr r3, [pc, #176] @ (8003c6c <HAL_RCCEx_PeriphCLKConfig+0x168>)
8003bba: 2200 movs r2, #0
8003bbc: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8003bbe: 4a29 ldr r2, [pc, #164] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003bc0: 68fb ldr r3, [r7, #12]
8003bc2: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8003bc4: 68fb ldr r3, [r7, #12]
8003bc6: f003 0301 and.w r3, r3, #1
8003bca: 2b00 cmp r3, #0
8003bcc: d014 beq.n 8003bf8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8003bce: f7fd f975 bl 8000ebc <HAL_GetTick>
8003bd2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003bd4: e00a b.n 8003bec <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003bd6: f7fd f971 bl 8000ebc <HAL_GetTick>
8003bda: 4602 mov r2, r0
8003bdc: 693b ldr r3, [r7, #16]
8003bde: 1ad3 subs r3, r2, r3
8003be0: f241 3288 movw r2, #5000 @ 0x1388
8003be4: 4293 cmp r3, r2
8003be6: d901 bls.n 8003bec <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8003be8: 2303 movs r3, #3
8003bea: e036 b.n 8003c5a <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003bec: 4b1d ldr r3, [pc, #116] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003bee: 6a1b ldr r3, [r3, #32]
8003bf0: f003 0302 and.w r3, r3, #2
8003bf4: 2b00 cmp r3, #0
8003bf6: d0ee beq.n 8003bd6 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003bf8: 4b1a ldr r3, [pc, #104] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003bfa: 6a1b ldr r3, [r3, #32]
8003bfc: f423 7240 bic.w r2, r3, #768 @ 0x300
8003c00: 687b ldr r3, [r7, #4]
8003c02: 685b ldr r3, [r3, #4]
8003c04: 4917 ldr r1, [pc, #92] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c06: 4313 orrs r3, r2
8003c08: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8003c0a: 7dfb ldrb r3, [r7, #23]
8003c0c: 2b01 cmp r3, #1
8003c0e: d105 bne.n 8003c1c <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003c10: 4b14 ldr r3, [pc, #80] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c12: 69db ldr r3, [r3, #28]
8003c14: 4a13 ldr r2, [pc, #76] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c16: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003c1a: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003c1c: 687b ldr r3, [r7, #4]
8003c1e: 681b ldr r3, [r3, #0]
8003c20: f003 0302 and.w r3, r3, #2
8003c24: 2b00 cmp r3, #0
8003c26: d008 beq.n 8003c3a <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8003c28: 4b0e ldr r3, [pc, #56] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c2a: 685b ldr r3, [r3, #4]
8003c2c: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8003c30: 687b ldr r3, [r7, #4]
8003c32: 689b ldr r3, [r3, #8]
8003c34: 490b ldr r1, [pc, #44] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c36: 4313 orrs r3, r2
8003c38: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8003c3a: 687b ldr r3, [r7, #4]
8003c3c: 681b ldr r3, [r3, #0]
8003c3e: f003 0310 and.w r3, r3, #16
8003c42: 2b00 cmp r3, #0
8003c44: d008 beq.n 8003c58 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8003c46: 4b07 ldr r3, [pc, #28] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c48: 685b ldr r3, [r3, #4]
8003c4a: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
8003c4e: 687b ldr r3, [r7, #4]
8003c50: 68db ldr r3, [r3, #12]
8003c52: 4904 ldr r1, [pc, #16] @ (8003c64 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003c54: 4313 orrs r3, r2
8003c56: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8003c58: 2300 movs r3, #0
}
8003c5a: 4618 mov r0, r3
8003c5c: 3718 adds r7, #24
8003c5e: 46bd mov sp, r7
8003c60: bd80 pop {r7, pc}
8003c62: bf00 nop
8003c64: 40021000 .word 0x40021000
8003c68: 40007000 .word 0x40007000
8003c6c: 42420440 .word 0x42420440
08003c70 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8003c70: b580 push {r7, lr}
8003c72: b082 sub sp, #8
8003c74: af00 add r7, sp, #0
8003c76: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003c78: 687b ldr r3, [r7, #4]
8003c7a: 2b00 cmp r3, #0
8003c7c: d101 bne.n 8003c82 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8003c7e: 2301 movs r3, #1
8003c80: e041 b.n 8003d06 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003c82: 687b ldr r3, [r7, #4]
8003c84: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003c88: b2db uxtb r3, r3
8003c8a: 2b00 cmp r3, #0
8003c8c: d106 bne.n 8003c9c <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003c8e: 687b ldr r3, [r7, #4]
8003c90: 2200 movs r2, #0
8003c92: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8003c96: 6878 ldr r0, [r7, #4]
8003c98: f7fc ff1a bl 8000ad0 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003c9c: 687b ldr r3, [r7, #4]
8003c9e: 2202 movs r2, #2
8003ca0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003ca4: 687b ldr r3, [r7, #4]
8003ca6: 681a ldr r2, [r3, #0]
8003ca8: 687b ldr r3, [r7, #4]
8003caa: 3304 adds r3, #4
8003cac: 4619 mov r1, r3
8003cae: 4610 mov r0, r2
8003cb0: f000 fab2 bl 8004218 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003cb4: 687b ldr r3, [r7, #4]
8003cb6: 2201 movs r2, #1
8003cb8: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003cbc: 687b ldr r3, [r7, #4]
8003cbe: 2201 movs r2, #1
8003cc0: f883 203e strb.w r2, [r3, #62] @ 0x3e
8003cc4: 687b ldr r3, [r7, #4]
8003cc6: 2201 movs r2, #1
8003cc8: f883 203f strb.w r2, [r3, #63] @ 0x3f
8003ccc: 687b ldr r3, [r7, #4]
8003cce: 2201 movs r2, #1
8003cd0: f883 2040 strb.w r2, [r3, #64] @ 0x40
8003cd4: 687b ldr r3, [r7, #4]
8003cd6: 2201 movs r2, #1
8003cd8: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003cdc: 687b ldr r3, [r7, #4]
8003cde: 2201 movs r2, #1
8003ce0: f883 2042 strb.w r2, [r3, #66] @ 0x42
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 2201 movs r2, #1
8003ce8: f883 2043 strb.w r2, [r3, #67] @ 0x43
8003cec: 687b ldr r3, [r7, #4]
8003cee: 2201 movs r2, #1
8003cf0: f883 2044 strb.w r2, [r3, #68] @ 0x44
8003cf4: 687b ldr r3, [r7, #4]
8003cf6: 2201 movs r2, #1
8003cf8: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003cfc: 687b ldr r3, [r7, #4]
8003cfe: 2201 movs r2, #1
8003d00: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8003d04: 2300 movs r3, #0
}
8003d06: 4618 mov r0, r3
8003d08: 3708 adds r7, #8
8003d0a: 46bd mov sp, r7
8003d0c: bd80 pop {r7, pc}
08003d0e <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8003d0e: b580 push {r7, lr}
8003d10: b082 sub sp, #8
8003d12: af00 add r7, sp, #0
8003d14: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003d16: 687b ldr r3, [r7, #4]
8003d18: 2b00 cmp r3, #0
8003d1a: d101 bne.n 8003d20 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8003d1c: 2301 movs r3, #1
8003d1e: e041 b.n 8003da4 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003d20: 687b ldr r3, [r7, #4]
8003d22: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003d26: b2db uxtb r3, r3
8003d28: 2b00 cmp r3, #0
8003d2a: d106 bne.n 8003d3a <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003d2c: 687b ldr r3, [r7, #4]
8003d2e: 2200 movs r2, #0
8003d30: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8003d34: 6878 ldr r0, [r7, #4]
8003d36: f000 f839 bl 8003dac <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003d3a: 687b ldr r3, [r7, #4]
8003d3c: 2202 movs r2, #2
8003d3e: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003d42: 687b ldr r3, [r7, #4]
8003d44: 681a ldr r2, [r3, #0]
8003d46: 687b ldr r3, [r7, #4]
8003d48: 3304 adds r3, #4
8003d4a: 4619 mov r1, r3
8003d4c: 4610 mov r0, r2
8003d4e: f000 fa63 bl 8004218 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003d52: 687b ldr r3, [r7, #4]
8003d54: 2201 movs r2, #1
8003d56: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003d5a: 687b ldr r3, [r7, #4]
8003d5c: 2201 movs r2, #1
8003d5e: f883 203e strb.w r2, [r3, #62] @ 0x3e
8003d62: 687b ldr r3, [r7, #4]
8003d64: 2201 movs r2, #1
8003d66: f883 203f strb.w r2, [r3, #63] @ 0x3f
8003d6a: 687b ldr r3, [r7, #4]
8003d6c: 2201 movs r2, #1
8003d6e: f883 2040 strb.w r2, [r3, #64] @ 0x40
8003d72: 687b ldr r3, [r7, #4]
8003d74: 2201 movs r2, #1
8003d76: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003d7a: 687b ldr r3, [r7, #4]
8003d7c: 2201 movs r2, #1
8003d7e: f883 2042 strb.w r2, [r3, #66] @ 0x42
8003d82: 687b ldr r3, [r7, #4]
8003d84: 2201 movs r2, #1
8003d86: f883 2043 strb.w r2, [r3, #67] @ 0x43
8003d8a: 687b ldr r3, [r7, #4]
8003d8c: 2201 movs r2, #1
8003d8e: f883 2044 strb.w r2, [r3, #68] @ 0x44
8003d92: 687b ldr r3, [r7, #4]
8003d94: 2201 movs r2, #1
8003d96: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003d9a: 687b ldr r3, [r7, #4]
8003d9c: 2201 movs r2, #1
8003d9e: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8003da2: 2300 movs r3, #0
}
8003da4: 4618 mov r0, r3
8003da6: 3708 adds r7, #8
8003da8: 46bd mov sp, r7
8003daa: bd80 pop {r7, pc}
08003dac <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8003dac: b480 push {r7}
8003dae: b083 sub sp, #12
8003db0: af00 add r7, sp, #0
8003db2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8003db4: bf00 nop
8003db6: 370c adds r7, #12
8003db8: 46bd mov sp, r7
8003dba: bc80 pop {r7}
8003dbc: 4770 bx lr
...
08003dc0 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8003dc0: b580 push {r7, lr}
8003dc2: b084 sub sp, #16
8003dc4: af00 add r7, sp, #0
8003dc6: 6078 str r0, [r7, #4]
8003dc8: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8003dca: 683b ldr r3, [r7, #0]
8003dcc: 2b00 cmp r3, #0
8003dce: d109 bne.n 8003de4 <HAL_TIM_PWM_Start+0x24>
8003dd0: 687b ldr r3, [r7, #4]
8003dd2: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8003dd6: b2db uxtb r3, r3
8003dd8: 2b01 cmp r3, #1
8003dda: bf14 ite ne
8003ddc: 2301 movne r3, #1
8003dde: 2300 moveq r3, #0
8003de0: b2db uxtb r3, r3
8003de2: e022 b.n 8003e2a <HAL_TIM_PWM_Start+0x6a>
8003de4: 683b ldr r3, [r7, #0]
8003de6: 2b04 cmp r3, #4
8003de8: d109 bne.n 8003dfe <HAL_TIM_PWM_Start+0x3e>
8003dea: 687b ldr r3, [r7, #4]
8003dec: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8003df0: b2db uxtb r3, r3
8003df2: 2b01 cmp r3, #1
8003df4: bf14 ite ne
8003df6: 2301 movne r3, #1
8003df8: 2300 moveq r3, #0
8003dfa: b2db uxtb r3, r3
8003dfc: e015 b.n 8003e2a <HAL_TIM_PWM_Start+0x6a>
8003dfe: 683b ldr r3, [r7, #0]
8003e00: 2b08 cmp r3, #8
8003e02: d109 bne.n 8003e18 <HAL_TIM_PWM_Start+0x58>
8003e04: 687b ldr r3, [r7, #4]
8003e06: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8003e0a: b2db uxtb r3, r3
8003e0c: 2b01 cmp r3, #1
8003e0e: bf14 ite ne
8003e10: 2301 movne r3, #1
8003e12: 2300 moveq r3, #0
8003e14: b2db uxtb r3, r3
8003e16: e008 b.n 8003e2a <HAL_TIM_PWM_Start+0x6a>
8003e18: 687b ldr r3, [r7, #4]
8003e1a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8003e1e: b2db uxtb r3, r3
8003e20: 2b01 cmp r3, #1
8003e22: bf14 ite ne
8003e24: 2301 movne r3, #1
8003e26: 2300 moveq r3, #0
8003e28: b2db uxtb r3, r3
8003e2a: 2b00 cmp r3, #0
8003e2c: d001 beq.n 8003e32 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8003e2e: 2301 movs r3, #1
8003e30: e05e b.n 8003ef0 <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8003e32: 683b ldr r3, [r7, #0]
8003e34: 2b00 cmp r3, #0
8003e36: d104 bne.n 8003e42 <HAL_TIM_PWM_Start+0x82>
8003e38: 687b ldr r3, [r7, #4]
8003e3a: 2202 movs r2, #2
8003e3c: f883 203e strb.w r2, [r3, #62] @ 0x3e
8003e40: e013 b.n 8003e6a <HAL_TIM_PWM_Start+0xaa>
8003e42: 683b ldr r3, [r7, #0]
8003e44: 2b04 cmp r3, #4
8003e46: d104 bne.n 8003e52 <HAL_TIM_PWM_Start+0x92>
8003e48: 687b ldr r3, [r7, #4]
8003e4a: 2202 movs r2, #2
8003e4c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8003e50: e00b b.n 8003e6a <HAL_TIM_PWM_Start+0xaa>
8003e52: 683b ldr r3, [r7, #0]
8003e54: 2b08 cmp r3, #8
8003e56: d104 bne.n 8003e62 <HAL_TIM_PWM_Start+0xa2>
8003e58: 687b ldr r3, [r7, #4]
8003e5a: 2202 movs r2, #2
8003e5c: f883 2040 strb.w r2, [r3, #64] @ 0x40
8003e60: e003 b.n 8003e6a <HAL_TIM_PWM_Start+0xaa>
8003e62: 687b ldr r3, [r7, #4]
8003e64: 2202 movs r2, #2
8003e66: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8003e6a: 687b ldr r3, [r7, #4]
8003e6c: 681b ldr r3, [r3, #0]
8003e6e: 2201 movs r2, #1
8003e70: 6839 ldr r1, [r7, #0]
8003e72: 4618 mov r0, r3
8003e74: f000 fc5c bl 8004730 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8003e78: 687b ldr r3, [r7, #4]
8003e7a: 681b ldr r3, [r3, #0]
8003e7c: 4a1e ldr r2, [pc, #120] @ (8003ef8 <HAL_TIM_PWM_Start+0x138>)
8003e7e: 4293 cmp r3, r2
8003e80: d107 bne.n 8003e92 <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8003e82: 687b ldr r3, [r7, #4]
8003e84: 681b ldr r3, [r3, #0]
8003e86: 6c5a ldr r2, [r3, #68] @ 0x44
8003e88: 687b ldr r3, [r7, #4]
8003e8a: 681b ldr r3, [r3, #0]
8003e8c: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003e90: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8003e92: 687b ldr r3, [r7, #4]
8003e94: 681b ldr r3, [r3, #0]
8003e96: 4a18 ldr r2, [pc, #96] @ (8003ef8 <HAL_TIM_PWM_Start+0x138>)
8003e98: 4293 cmp r3, r2
8003e9a: d00e beq.n 8003eba <HAL_TIM_PWM_Start+0xfa>
8003e9c: 687b ldr r3, [r7, #4]
8003e9e: 681b ldr r3, [r3, #0]
8003ea0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003ea4: d009 beq.n 8003eba <HAL_TIM_PWM_Start+0xfa>
8003ea6: 687b ldr r3, [r7, #4]
8003ea8: 681b ldr r3, [r3, #0]
8003eaa: 4a14 ldr r2, [pc, #80] @ (8003efc <HAL_TIM_PWM_Start+0x13c>)
8003eac: 4293 cmp r3, r2
8003eae: d004 beq.n 8003eba <HAL_TIM_PWM_Start+0xfa>
8003eb0: 687b ldr r3, [r7, #4]
8003eb2: 681b ldr r3, [r3, #0]
8003eb4: 4a12 ldr r2, [pc, #72] @ (8003f00 <HAL_TIM_PWM_Start+0x140>)
8003eb6: 4293 cmp r3, r2
8003eb8: d111 bne.n 8003ede <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003eba: 687b ldr r3, [r7, #4]
8003ebc: 681b ldr r3, [r3, #0]
8003ebe: 689b ldr r3, [r3, #8]
8003ec0: f003 0307 and.w r3, r3, #7
8003ec4: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003ec6: 68fb ldr r3, [r7, #12]
8003ec8: 2b06 cmp r3, #6
8003eca: d010 beq.n 8003eee <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
8003ecc: 687b ldr r3, [r7, #4]
8003ece: 681b ldr r3, [r3, #0]
8003ed0: 681a ldr r2, [r3, #0]
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 681b ldr r3, [r3, #0]
8003ed6: f042 0201 orr.w r2, r2, #1
8003eda: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003edc: e007 b.n 8003eee <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8003ede: 687b ldr r3, [r7, #4]
8003ee0: 681b ldr r3, [r3, #0]
8003ee2: 681a ldr r2, [r3, #0]
8003ee4: 687b ldr r3, [r7, #4]
8003ee6: 681b ldr r3, [r3, #0]
8003ee8: f042 0201 orr.w r2, r2, #1
8003eec: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8003eee: 2300 movs r3, #0
}
8003ef0: 4618 mov r0, r3
8003ef2: 3710 adds r7, #16
8003ef4: 46bd mov sp, r7
8003ef6: bd80 pop {r7, pc}
8003ef8: 40012c00 .word 0x40012c00
8003efc: 40000400 .word 0x40000400
8003f00: 40000800 .word 0x40000800
08003f04 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8003f04: b580 push {r7, lr}
8003f06: b086 sub sp, #24
8003f08: af00 add r7, sp, #0
8003f0a: 60f8 str r0, [r7, #12]
8003f0c: 60b9 str r1, [r7, #8]
8003f0e: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003f10: 2300 movs r3, #0
8003f12: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8003f14: 68fb ldr r3, [r7, #12]
8003f16: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8003f1a: 2b01 cmp r3, #1
8003f1c: d101 bne.n 8003f22 <HAL_TIM_PWM_ConfigChannel+0x1e>
8003f1e: 2302 movs r3, #2
8003f20: e0ae b.n 8004080 <HAL_TIM_PWM_ConfigChannel+0x17c>
8003f22: 68fb ldr r3, [r7, #12]
8003f24: 2201 movs r2, #1
8003f26: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8003f2a: 687b ldr r3, [r7, #4]
8003f2c: 2b0c cmp r3, #12
8003f2e: f200 809f bhi.w 8004070 <HAL_TIM_PWM_ConfigChannel+0x16c>
8003f32: a201 add r2, pc, #4 @ (adr r2, 8003f38 <HAL_TIM_PWM_ConfigChannel+0x34>)
8003f34: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003f38: 08003f6d .word 0x08003f6d
8003f3c: 08004071 .word 0x08004071
8003f40: 08004071 .word 0x08004071
8003f44: 08004071 .word 0x08004071
8003f48: 08003fad .word 0x08003fad
8003f4c: 08004071 .word 0x08004071
8003f50: 08004071 .word 0x08004071
8003f54: 08004071 .word 0x08004071
8003f58: 08003fef .word 0x08003fef
8003f5c: 08004071 .word 0x08004071
8003f60: 08004071 .word 0x08004071
8003f64: 08004071 .word 0x08004071
8003f68: 0800402f .word 0x0800402f
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8003f6c: 68fb ldr r3, [r7, #12]
8003f6e: 681b ldr r3, [r3, #0]
8003f70: 68b9 ldr r1, [r7, #8]
8003f72: 4618 mov r0, r3
8003f74: f000 f9be bl 80042f4 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8003f78: 68fb ldr r3, [r7, #12]
8003f7a: 681b ldr r3, [r3, #0]
8003f7c: 699a ldr r2, [r3, #24]
8003f7e: 68fb ldr r3, [r7, #12]
8003f80: 681b ldr r3, [r3, #0]
8003f82: f042 0208 orr.w r2, r2, #8
8003f86: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8003f88: 68fb ldr r3, [r7, #12]
8003f8a: 681b ldr r3, [r3, #0]
8003f8c: 699a ldr r2, [r3, #24]
8003f8e: 68fb ldr r3, [r7, #12]
8003f90: 681b ldr r3, [r3, #0]
8003f92: f022 0204 bic.w r2, r2, #4
8003f96: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8003f98: 68fb ldr r3, [r7, #12]
8003f9a: 681b ldr r3, [r3, #0]
8003f9c: 6999 ldr r1, [r3, #24]
8003f9e: 68bb ldr r3, [r7, #8]
8003fa0: 691a ldr r2, [r3, #16]
8003fa2: 68fb ldr r3, [r7, #12]
8003fa4: 681b ldr r3, [r3, #0]
8003fa6: 430a orrs r2, r1
8003fa8: 619a str r2, [r3, #24]
break;
8003faa: e064 b.n 8004076 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8003fac: 68fb ldr r3, [r7, #12]
8003fae: 681b ldr r3, [r3, #0]
8003fb0: 68b9 ldr r1, [r7, #8]
8003fb2: 4618 mov r0, r3
8003fb4: f000 fa04 bl 80043c0 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8003fb8: 68fb ldr r3, [r7, #12]
8003fba: 681b ldr r3, [r3, #0]
8003fbc: 699a ldr r2, [r3, #24]
8003fbe: 68fb ldr r3, [r7, #12]
8003fc0: 681b ldr r3, [r3, #0]
8003fc2: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003fc6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8003fc8: 68fb ldr r3, [r7, #12]
8003fca: 681b ldr r3, [r3, #0]
8003fcc: 699a ldr r2, [r3, #24]
8003fce: 68fb ldr r3, [r7, #12]
8003fd0: 681b ldr r3, [r3, #0]
8003fd2: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003fd6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8003fd8: 68fb ldr r3, [r7, #12]
8003fda: 681b ldr r3, [r3, #0]
8003fdc: 6999 ldr r1, [r3, #24]
8003fde: 68bb ldr r3, [r7, #8]
8003fe0: 691b ldr r3, [r3, #16]
8003fe2: 021a lsls r2, r3, #8
8003fe4: 68fb ldr r3, [r7, #12]
8003fe6: 681b ldr r3, [r3, #0]
8003fe8: 430a orrs r2, r1
8003fea: 619a str r2, [r3, #24]
break;
8003fec: e043 b.n 8004076 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8003fee: 68fb ldr r3, [r7, #12]
8003ff0: 681b ldr r3, [r3, #0]
8003ff2: 68b9 ldr r1, [r7, #8]
8003ff4: 4618 mov r0, r3
8003ff6: f000 fa4d bl 8004494 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8003ffa: 68fb ldr r3, [r7, #12]
8003ffc: 681b ldr r3, [r3, #0]
8003ffe: 69da ldr r2, [r3, #28]
8004000: 68fb ldr r3, [r7, #12]
8004002: 681b ldr r3, [r3, #0]
8004004: f042 0208 orr.w r2, r2, #8
8004008: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800400a: 68fb ldr r3, [r7, #12]
800400c: 681b ldr r3, [r3, #0]
800400e: 69da ldr r2, [r3, #28]
8004010: 68fb ldr r3, [r7, #12]
8004012: 681b ldr r3, [r3, #0]
8004014: f022 0204 bic.w r2, r2, #4
8004018: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800401a: 68fb ldr r3, [r7, #12]
800401c: 681b ldr r3, [r3, #0]
800401e: 69d9 ldr r1, [r3, #28]
8004020: 68bb ldr r3, [r7, #8]
8004022: 691a ldr r2, [r3, #16]
8004024: 68fb ldr r3, [r7, #12]
8004026: 681b ldr r3, [r3, #0]
8004028: 430a orrs r2, r1
800402a: 61da str r2, [r3, #28]
break;
800402c: e023 b.n 8004076 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800402e: 68fb ldr r3, [r7, #12]
8004030: 681b ldr r3, [r3, #0]
8004032: 68b9 ldr r1, [r7, #8]
8004034: 4618 mov r0, r3
8004036: f000 fa97 bl 8004568 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800403a: 68fb ldr r3, [r7, #12]
800403c: 681b ldr r3, [r3, #0]
800403e: 69da ldr r2, [r3, #28]
8004040: 68fb ldr r3, [r7, #12]
8004042: 681b ldr r3, [r3, #0]
8004044: f442 6200 orr.w r2, r2, #2048 @ 0x800
8004048: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800404a: 68fb ldr r3, [r7, #12]
800404c: 681b ldr r3, [r3, #0]
800404e: 69da ldr r2, [r3, #28]
8004050: 68fb ldr r3, [r7, #12]
8004052: 681b ldr r3, [r3, #0]
8004054: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004058: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800405a: 68fb ldr r3, [r7, #12]
800405c: 681b ldr r3, [r3, #0]
800405e: 69d9 ldr r1, [r3, #28]
8004060: 68bb ldr r3, [r7, #8]
8004062: 691b ldr r3, [r3, #16]
8004064: 021a lsls r2, r3, #8
8004066: 68fb ldr r3, [r7, #12]
8004068: 681b ldr r3, [r3, #0]
800406a: 430a orrs r2, r1
800406c: 61da str r2, [r3, #28]
break;
800406e: e002 b.n 8004076 <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8004070: 2301 movs r3, #1
8004072: 75fb strb r3, [r7, #23]
break;
8004074: bf00 nop
}
__HAL_UNLOCK(htim);
8004076: 68fb ldr r3, [r7, #12]
8004078: 2200 movs r2, #0
800407a: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
800407e: 7dfb ldrb r3, [r7, #23]
}
8004080: 4618 mov r0, r3
8004082: 3718 adds r7, #24
8004084: 46bd mov sp, r7
8004086: bd80 pop {r7, pc}
08004088 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8004088: b580 push {r7, lr}
800408a: b084 sub sp, #16
800408c: af00 add r7, sp, #0
800408e: 6078 str r0, [r7, #4]
8004090: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8004092: 2300 movs r3, #0
8004094: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8004096: 687b ldr r3, [r7, #4]
8004098: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800409c: 2b01 cmp r3, #1
800409e: d101 bne.n 80040a4 <HAL_TIM_ConfigClockSource+0x1c>
80040a0: 2302 movs r3, #2
80040a2: e0b4 b.n 800420e <HAL_TIM_ConfigClockSource+0x186>
80040a4: 687b ldr r3, [r7, #4]
80040a6: 2201 movs r2, #1
80040a8: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
80040ac: 687b ldr r3, [r7, #4]
80040ae: 2202 movs r2, #2
80040b0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80040b4: 687b ldr r3, [r7, #4]
80040b6: 681b ldr r3, [r3, #0]
80040b8: 689b ldr r3, [r3, #8]
80040ba: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80040bc: 68bb ldr r3, [r7, #8]
80040be: f023 0377 bic.w r3, r3, #119 @ 0x77
80040c2: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80040c4: 68bb ldr r3, [r7, #8]
80040c6: f423 437f bic.w r3, r3, #65280 @ 0xff00
80040ca: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80040cc: 687b ldr r3, [r7, #4]
80040ce: 681b ldr r3, [r3, #0]
80040d0: 68ba ldr r2, [r7, #8]
80040d2: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80040d4: 683b ldr r3, [r7, #0]
80040d6: 681b ldr r3, [r3, #0]
80040d8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80040dc: d03e beq.n 800415c <HAL_TIM_ConfigClockSource+0xd4>
80040de: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80040e2: f200 8087 bhi.w 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
80040e6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80040ea: f000 8086 beq.w 80041fa <HAL_TIM_ConfigClockSource+0x172>
80040ee: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80040f2: d87f bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
80040f4: 2b70 cmp r3, #112 @ 0x70
80040f6: d01a beq.n 800412e <HAL_TIM_ConfigClockSource+0xa6>
80040f8: 2b70 cmp r3, #112 @ 0x70
80040fa: d87b bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
80040fc: 2b60 cmp r3, #96 @ 0x60
80040fe: d050 beq.n 80041a2 <HAL_TIM_ConfigClockSource+0x11a>
8004100: 2b60 cmp r3, #96 @ 0x60
8004102: d877 bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
8004104: 2b50 cmp r3, #80 @ 0x50
8004106: d03c beq.n 8004182 <HAL_TIM_ConfigClockSource+0xfa>
8004108: 2b50 cmp r3, #80 @ 0x50
800410a: d873 bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
800410c: 2b40 cmp r3, #64 @ 0x40
800410e: d058 beq.n 80041c2 <HAL_TIM_ConfigClockSource+0x13a>
8004110: 2b40 cmp r3, #64 @ 0x40
8004112: d86f bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
8004114: 2b30 cmp r3, #48 @ 0x30
8004116: d064 beq.n 80041e2 <HAL_TIM_ConfigClockSource+0x15a>
8004118: 2b30 cmp r3, #48 @ 0x30
800411a: d86b bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
800411c: 2b20 cmp r3, #32
800411e: d060 beq.n 80041e2 <HAL_TIM_ConfigClockSource+0x15a>
8004120: 2b20 cmp r3, #32
8004122: d867 bhi.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
8004124: 2b00 cmp r3, #0
8004126: d05c beq.n 80041e2 <HAL_TIM_ConfigClockSource+0x15a>
8004128: 2b10 cmp r3, #16
800412a: d05a beq.n 80041e2 <HAL_TIM_ConfigClockSource+0x15a>
800412c: e062 b.n 80041f4 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
800412e: 687b ldr r3, [r7, #4]
8004130: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8004132: 683b ldr r3, [r7, #0]
8004134: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8004136: 683b ldr r3, [r7, #0]
8004138: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800413a: 683b ldr r3, [r7, #0]
800413c: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
800413e: f000 fad8 bl 80046f2 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8004142: 687b ldr r3, [r7, #4]
8004144: 681b ldr r3, [r3, #0]
8004146: 689b ldr r3, [r3, #8]
8004148: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800414a: 68bb ldr r3, [r7, #8]
800414c: f043 0377 orr.w r3, r3, #119 @ 0x77
8004150: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004152: 687b ldr r3, [r7, #4]
8004154: 681b ldr r3, [r3, #0]
8004156: 68ba ldr r2, [r7, #8]
8004158: 609a str r2, [r3, #8]
break;
800415a: e04f b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
800415c: 687b ldr r3, [r7, #4]
800415e: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8004160: 683b ldr r3, [r7, #0]
8004162: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8004164: 683b ldr r3, [r7, #0]
8004166: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8004168: 683b ldr r3, [r7, #0]
800416a: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
800416c: f000 fac1 bl 80046f2 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8004170: 687b ldr r3, [r7, #4]
8004172: 681b ldr r3, [r3, #0]
8004174: 689a ldr r2, [r3, #8]
8004176: 687b ldr r3, [r7, #4]
8004178: 681b ldr r3, [r3, #0]
800417a: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800417e: 609a str r2, [r3, #8]
break;
8004180: e03c b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8004182: 687b ldr r3, [r7, #4]
8004184: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8004186: 683b ldr r3, [r7, #0]
8004188: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800418a: 683b ldr r3, [r7, #0]
800418c: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
800418e: 461a mov r2, r3
8004190: f000 fa38 bl 8004604 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8004194: 687b ldr r3, [r7, #4]
8004196: 681b ldr r3, [r3, #0]
8004198: 2150 movs r1, #80 @ 0x50
800419a: 4618 mov r0, r3
800419c: f000 fa8f bl 80046be <TIM_ITRx_SetConfig>
break;
80041a0: e02c b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80041a2: 687b ldr r3, [r7, #4]
80041a4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80041a6: 683b ldr r3, [r7, #0]
80041a8: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80041aa: 683b ldr r3, [r7, #0]
80041ac: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
80041ae: 461a mov r2, r3
80041b0: f000 fa56 bl 8004660 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80041b4: 687b ldr r3, [r7, #4]
80041b6: 681b ldr r3, [r3, #0]
80041b8: 2160 movs r1, #96 @ 0x60
80041ba: 4618 mov r0, r3
80041bc: f000 fa7f bl 80046be <TIM_ITRx_SetConfig>
break;
80041c0: e01c b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80041c2: 687b ldr r3, [r7, #4]
80041c4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80041c6: 683b ldr r3, [r7, #0]
80041c8: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80041ca: 683b ldr r3, [r7, #0]
80041cc: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80041ce: 461a mov r2, r3
80041d0: f000 fa18 bl 8004604 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80041d4: 687b ldr r3, [r7, #4]
80041d6: 681b ldr r3, [r3, #0]
80041d8: 2140 movs r1, #64 @ 0x40
80041da: 4618 mov r0, r3
80041dc: f000 fa6f bl 80046be <TIM_ITRx_SetConfig>
break;
80041e0: e00c b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80041e2: 687b ldr r3, [r7, #4]
80041e4: 681a ldr r2, [r3, #0]
80041e6: 683b ldr r3, [r7, #0]
80041e8: 681b ldr r3, [r3, #0]
80041ea: 4619 mov r1, r3
80041ec: 4610 mov r0, r2
80041ee: f000 fa66 bl 80046be <TIM_ITRx_SetConfig>
break;
80041f2: e003 b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
80041f4: 2301 movs r3, #1
80041f6: 73fb strb r3, [r7, #15]
break;
80041f8: e000 b.n 80041fc <HAL_TIM_ConfigClockSource+0x174>
break;
80041fa: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
80041fc: 687b ldr r3, [r7, #4]
80041fe: 2201 movs r2, #1
8004200: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004204: 687b ldr r3, [r7, #4]
8004206: 2200 movs r2, #0
8004208: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
800420c: 7bfb ldrb r3, [r7, #15]
}
800420e: 4618 mov r0, r3
8004210: 3710 adds r7, #16
8004212: 46bd mov sp, r7
8004214: bd80 pop {r7, pc}
...
08004218 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8004218: b480 push {r7}
800421a: b085 sub sp, #20
800421c: af00 add r7, sp, #0
800421e: 6078 str r0, [r7, #4]
8004220: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8004222: 687b ldr r3, [r7, #4]
8004224: 681b ldr r3, [r3, #0]
8004226: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004228: 687b ldr r3, [r7, #4]
800422a: 4a2f ldr r2, [pc, #188] @ (80042e8 <TIM_Base_SetConfig+0xd0>)
800422c: 4293 cmp r3, r2
800422e: d00b beq.n 8004248 <TIM_Base_SetConfig+0x30>
8004230: 687b ldr r3, [r7, #4]
8004232: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004236: d007 beq.n 8004248 <TIM_Base_SetConfig+0x30>
8004238: 687b ldr r3, [r7, #4]
800423a: 4a2c ldr r2, [pc, #176] @ (80042ec <TIM_Base_SetConfig+0xd4>)
800423c: 4293 cmp r3, r2
800423e: d003 beq.n 8004248 <TIM_Base_SetConfig+0x30>
8004240: 687b ldr r3, [r7, #4]
8004242: 4a2b ldr r2, [pc, #172] @ (80042f0 <TIM_Base_SetConfig+0xd8>)
8004244: 4293 cmp r3, r2
8004246: d108 bne.n 800425a <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8004248: 68fb ldr r3, [r7, #12]
800424a: f023 0370 bic.w r3, r3, #112 @ 0x70
800424e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8004250: 683b ldr r3, [r7, #0]
8004252: 685b ldr r3, [r3, #4]
8004254: 68fa ldr r2, [r7, #12]
8004256: 4313 orrs r3, r2
8004258: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800425a: 687b ldr r3, [r7, #4]
800425c: 4a22 ldr r2, [pc, #136] @ (80042e8 <TIM_Base_SetConfig+0xd0>)
800425e: 4293 cmp r3, r2
8004260: d00b beq.n 800427a <TIM_Base_SetConfig+0x62>
8004262: 687b ldr r3, [r7, #4]
8004264: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004268: d007 beq.n 800427a <TIM_Base_SetConfig+0x62>
800426a: 687b ldr r3, [r7, #4]
800426c: 4a1f ldr r2, [pc, #124] @ (80042ec <TIM_Base_SetConfig+0xd4>)
800426e: 4293 cmp r3, r2
8004270: d003 beq.n 800427a <TIM_Base_SetConfig+0x62>
8004272: 687b ldr r3, [r7, #4]
8004274: 4a1e ldr r2, [pc, #120] @ (80042f0 <TIM_Base_SetConfig+0xd8>)
8004276: 4293 cmp r3, r2
8004278: d108 bne.n 800428c <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800427a: 68fb ldr r3, [r7, #12]
800427c: f423 7340 bic.w r3, r3, #768 @ 0x300
8004280: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004282: 683b ldr r3, [r7, #0]
8004284: 68db ldr r3, [r3, #12]
8004286: 68fa ldr r2, [r7, #12]
8004288: 4313 orrs r3, r2
800428a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800428c: 68fb ldr r3, [r7, #12]
800428e: f023 0280 bic.w r2, r3, #128 @ 0x80
8004292: 683b ldr r3, [r7, #0]
8004294: 695b ldr r3, [r3, #20]
8004296: 4313 orrs r3, r2
8004298: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800429a: 687b ldr r3, [r7, #4]
800429c: 68fa ldr r2, [r7, #12]
800429e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80042a0: 683b ldr r3, [r7, #0]
80042a2: 689a ldr r2, [r3, #8]
80042a4: 687b ldr r3, [r7, #4]
80042a6: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80042a8: 683b ldr r3, [r7, #0]
80042aa: 681a ldr r2, [r3, #0]
80042ac: 687b ldr r3, [r7, #4]
80042ae: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80042b0: 687b ldr r3, [r7, #4]
80042b2: 4a0d ldr r2, [pc, #52] @ (80042e8 <TIM_Base_SetConfig+0xd0>)
80042b4: 4293 cmp r3, r2
80042b6: d103 bne.n 80042c0 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80042b8: 683b ldr r3, [r7, #0]
80042ba: 691a ldr r2, [r3, #16]
80042bc: 687b ldr r3, [r7, #4]
80042be: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80042c0: 687b ldr r3, [r7, #4]
80042c2: 2201 movs r2, #1
80042c4: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
80042c6: 687b ldr r3, [r7, #4]
80042c8: 691b ldr r3, [r3, #16]
80042ca: f003 0301 and.w r3, r3, #1
80042ce: 2b00 cmp r3, #0
80042d0: d005 beq.n 80042de <TIM_Base_SetConfig+0xc6>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
80042d2: 687b ldr r3, [r7, #4]
80042d4: 691b ldr r3, [r3, #16]
80042d6: f023 0201 bic.w r2, r3, #1
80042da: 687b ldr r3, [r7, #4]
80042dc: 611a str r2, [r3, #16]
}
}
80042de: bf00 nop
80042e0: 3714 adds r7, #20
80042e2: 46bd mov sp, r7
80042e4: bc80 pop {r7}
80042e6: 4770 bx lr
80042e8: 40012c00 .word 0x40012c00
80042ec: 40000400 .word 0x40000400
80042f0: 40000800 .word 0x40000800
080042f4 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80042f4: b480 push {r7}
80042f6: b087 sub sp, #28
80042f8: af00 add r7, sp, #0
80042fa: 6078 str r0, [r7, #4]
80042fc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80042fe: 687b ldr r3, [r7, #4]
8004300: 6a1b ldr r3, [r3, #32]
8004302: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8004304: 687b ldr r3, [r7, #4]
8004306: 6a1b ldr r3, [r3, #32]
8004308: f023 0201 bic.w r2, r3, #1
800430c: 687b ldr r3, [r7, #4]
800430e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004310: 687b ldr r3, [r7, #4]
8004312: 685b ldr r3, [r3, #4]
8004314: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004316: 687b ldr r3, [r7, #4]
8004318: 699b ldr r3, [r3, #24]
800431a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800431c: 68fb ldr r3, [r7, #12]
800431e: f023 0370 bic.w r3, r3, #112 @ 0x70
8004322: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8004324: 68fb ldr r3, [r7, #12]
8004326: f023 0303 bic.w r3, r3, #3
800432a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800432c: 683b ldr r3, [r7, #0]
800432e: 681b ldr r3, [r3, #0]
8004330: 68fa ldr r2, [r7, #12]
8004332: 4313 orrs r3, r2
8004334: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8004336: 697b ldr r3, [r7, #20]
8004338: f023 0302 bic.w r3, r3, #2
800433c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800433e: 683b ldr r3, [r7, #0]
8004340: 689b ldr r3, [r3, #8]
8004342: 697a ldr r2, [r7, #20]
8004344: 4313 orrs r3, r2
8004346: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8004348: 687b ldr r3, [r7, #4]
800434a: 4a1c ldr r2, [pc, #112] @ (80043bc <TIM_OC1_SetConfig+0xc8>)
800434c: 4293 cmp r3, r2
800434e: d10c bne.n 800436a <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8004350: 697b ldr r3, [r7, #20]
8004352: f023 0308 bic.w r3, r3, #8
8004356: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8004358: 683b ldr r3, [r7, #0]
800435a: 68db ldr r3, [r3, #12]
800435c: 697a ldr r2, [r7, #20]
800435e: 4313 orrs r3, r2
8004360: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8004362: 697b ldr r3, [r7, #20]
8004364: f023 0304 bic.w r3, r3, #4
8004368: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800436a: 687b ldr r3, [r7, #4]
800436c: 4a13 ldr r2, [pc, #76] @ (80043bc <TIM_OC1_SetConfig+0xc8>)
800436e: 4293 cmp r3, r2
8004370: d111 bne.n 8004396 <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8004372: 693b ldr r3, [r7, #16]
8004374: f423 7380 bic.w r3, r3, #256 @ 0x100
8004378: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800437a: 693b ldr r3, [r7, #16]
800437c: f423 7300 bic.w r3, r3, #512 @ 0x200
8004380: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8004382: 683b ldr r3, [r7, #0]
8004384: 695b ldr r3, [r3, #20]
8004386: 693a ldr r2, [r7, #16]
8004388: 4313 orrs r3, r2
800438a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800438c: 683b ldr r3, [r7, #0]
800438e: 699b ldr r3, [r3, #24]
8004390: 693a ldr r2, [r7, #16]
8004392: 4313 orrs r3, r2
8004394: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004396: 687b ldr r3, [r7, #4]
8004398: 693a ldr r2, [r7, #16]
800439a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800439c: 687b ldr r3, [r7, #4]
800439e: 68fa ldr r2, [r7, #12]
80043a0: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80043a2: 683b ldr r3, [r7, #0]
80043a4: 685a ldr r2, [r3, #4]
80043a6: 687b ldr r3, [r7, #4]
80043a8: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80043aa: 687b ldr r3, [r7, #4]
80043ac: 697a ldr r2, [r7, #20]
80043ae: 621a str r2, [r3, #32]
}
80043b0: bf00 nop
80043b2: 371c adds r7, #28
80043b4: 46bd mov sp, r7
80043b6: bc80 pop {r7}
80043b8: 4770 bx lr
80043ba: bf00 nop
80043bc: 40012c00 .word 0x40012c00
080043c0 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80043c0: b480 push {r7}
80043c2: b087 sub sp, #28
80043c4: af00 add r7, sp, #0
80043c6: 6078 str r0, [r7, #4]
80043c8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80043ca: 687b ldr r3, [r7, #4]
80043cc: 6a1b ldr r3, [r3, #32]
80043ce: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
80043d0: 687b ldr r3, [r7, #4]
80043d2: 6a1b ldr r3, [r3, #32]
80043d4: f023 0210 bic.w r2, r3, #16
80043d8: 687b ldr r3, [r7, #4]
80043da: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80043dc: 687b ldr r3, [r7, #4]
80043de: 685b ldr r3, [r3, #4]
80043e0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80043e2: 687b ldr r3, [r7, #4]
80043e4: 699b ldr r3, [r3, #24]
80043e6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
80043e8: 68fb ldr r3, [r7, #12]
80043ea: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80043ee: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
80043f0: 68fb ldr r3, [r7, #12]
80043f2: f423 7340 bic.w r3, r3, #768 @ 0x300
80043f6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80043f8: 683b ldr r3, [r7, #0]
80043fa: 681b ldr r3, [r3, #0]
80043fc: 021b lsls r3, r3, #8
80043fe: 68fa ldr r2, [r7, #12]
8004400: 4313 orrs r3, r2
8004402: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8004404: 697b ldr r3, [r7, #20]
8004406: f023 0320 bic.w r3, r3, #32
800440a: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
800440c: 683b ldr r3, [r7, #0]
800440e: 689b ldr r3, [r3, #8]
8004410: 011b lsls r3, r3, #4
8004412: 697a ldr r2, [r7, #20]
8004414: 4313 orrs r3, r2
8004416: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8004418: 687b ldr r3, [r7, #4]
800441a: 4a1d ldr r2, [pc, #116] @ (8004490 <TIM_OC2_SetConfig+0xd0>)
800441c: 4293 cmp r3, r2
800441e: d10d bne.n 800443c <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8004420: 697b ldr r3, [r7, #20]
8004422: f023 0380 bic.w r3, r3, #128 @ 0x80
8004426: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8004428: 683b ldr r3, [r7, #0]
800442a: 68db ldr r3, [r3, #12]
800442c: 011b lsls r3, r3, #4
800442e: 697a ldr r2, [r7, #20]
8004430: 4313 orrs r3, r2
8004432: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8004434: 697b ldr r3, [r7, #20]
8004436: f023 0340 bic.w r3, r3, #64 @ 0x40
800443a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800443c: 687b ldr r3, [r7, #4]
800443e: 4a14 ldr r2, [pc, #80] @ (8004490 <TIM_OC2_SetConfig+0xd0>)
8004440: 4293 cmp r3, r2
8004442: d113 bne.n 800446c <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8004444: 693b ldr r3, [r7, #16]
8004446: f423 6380 bic.w r3, r3, #1024 @ 0x400
800444a: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800444c: 693b ldr r3, [r7, #16]
800444e: f423 6300 bic.w r3, r3, #2048 @ 0x800
8004452: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8004454: 683b ldr r3, [r7, #0]
8004456: 695b ldr r3, [r3, #20]
8004458: 009b lsls r3, r3, #2
800445a: 693a ldr r2, [r7, #16]
800445c: 4313 orrs r3, r2
800445e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8004460: 683b ldr r3, [r7, #0]
8004462: 699b ldr r3, [r3, #24]
8004464: 009b lsls r3, r3, #2
8004466: 693a ldr r2, [r7, #16]
8004468: 4313 orrs r3, r2
800446a: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800446c: 687b ldr r3, [r7, #4]
800446e: 693a ldr r2, [r7, #16]
8004470: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004472: 687b ldr r3, [r7, #4]
8004474: 68fa ldr r2, [r7, #12]
8004476: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8004478: 683b ldr r3, [r7, #0]
800447a: 685a ldr r2, [r3, #4]
800447c: 687b ldr r3, [r7, #4]
800447e: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004480: 687b ldr r3, [r7, #4]
8004482: 697a ldr r2, [r7, #20]
8004484: 621a str r2, [r3, #32]
}
8004486: bf00 nop
8004488: 371c adds r7, #28
800448a: 46bd mov sp, r7
800448c: bc80 pop {r7}
800448e: 4770 bx lr
8004490: 40012c00 .word 0x40012c00
08004494 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004494: b480 push {r7}
8004496: b087 sub sp, #28
8004498: af00 add r7, sp, #0
800449a: 6078 str r0, [r7, #4]
800449c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800449e: 687b ldr r3, [r7, #4]
80044a0: 6a1b ldr r3, [r3, #32]
80044a2: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
80044a4: 687b ldr r3, [r7, #4]
80044a6: 6a1b ldr r3, [r3, #32]
80044a8: f423 7280 bic.w r2, r3, #256 @ 0x100
80044ac: 687b ldr r3, [r7, #4]
80044ae: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80044b0: 687b ldr r3, [r7, #4]
80044b2: 685b ldr r3, [r3, #4]
80044b4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80044b6: 687b ldr r3, [r7, #4]
80044b8: 69db ldr r3, [r3, #28]
80044ba: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
80044bc: 68fb ldr r3, [r7, #12]
80044be: f023 0370 bic.w r3, r3, #112 @ 0x70
80044c2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80044c4: 68fb ldr r3, [r7, #12]
80044c6: f023 0303 bic.w r3, r3, #3
80044ca: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80044cc: 683b ldr r3, [r7, #0]
80044ce: 681b ldr r3, [r3, #0]
80044d0: 68fa ldr r2, [r7, #12]
80044d2: 4313 orrs r3, r2
80044d4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80044d6: 697b ldr r3, [r7, #20]
80044d8: f423 7300 bic.w r3, r3, #512 @ 0x200
80044dc: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80044de: 683b ldr r3, [r7, #0]
80044e0: 689b ldr r3, [r3, #8]
80044e2: 021b lsls r3, r3, #8
80044e4: 697a ldr r2, [r7, #20]
80044e6: 4313 orrs r3, r2
80044e8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
80044ea: 687b ldr r3, [r7, #4]
80044ec: 4a1d ldr r2, [pc, #116] @ (8004564 <TIM_OC3_SetConfig+0xd0>)
80044ee: 4293 cmp r3, r2
80044f0: d10d bne.n 800450e <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
80044f2: 697b ldr r3, [r7, #20]
80044f4: f423 6300 bic.w r3, r3, #2048 @ 0x800
80044f8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80044fa: 683b ldr r3, [r7, #0]
80044fc: 68db ldr r3, [r3, #12]
80044fe: 021b lsls r3, r3, #8
8004500: 697a ldr r2, [r7, #20]
8004502: 4313 orrs r3, r2
8004504: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8004506: 697b ldr r3, [r7, #20]
8004508: f423 6380 bic.w r3, r3, #1024 @ 0x400
800450c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800450e: 687b ldr r3, [r7, #4]
8004510: 4a14 ldr r2, [pc, #80] @ (8004564 <TIM_OC3_SetConfig+0xd0>)
8004512: 4293 cmp r3, r2
8004514: d113 bne.n 800453e <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8004516: 693b ldr r3, [r7, #16]
8004518: f423 5380 bic.w r3, r3, #4096 @ 0x1000
800451c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800451e: 693b ldr r3, [r7, #16]
8004520: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8004524: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8004526: 683b ldr r3, [r7, #0]
8004528: 695b ldr r3, [r3, #20]
800452a: 011b lsls r3, r3, #4
800452c: 693a ldr r2, [r7, #16]
800452e: 4313 orrs r3, r2
8004530: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8004532: 683b ldr r3, [r7, #0]
8004534: 699b ldr r3, [r3, #24]
8004536: 011b lsls r3, r3, #4
8004538: 693a ldr r2, [r7, #16]
800453a: 4313 orrs r3, r2
800453c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800453e: 687b ldr r3, [r7, #4]
8004540: 693a ldr r2, [r7, #16]
8004542: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8004544: 687b ldr r3, [r7, #4]
8004546: 68fa ldr r2, [r7, #12]
8004548: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800454a: 683b ldr r3, [r7, #0]
800454c: 685a ldr r2, [r3, #4]
800454e: 687b ldr r3, [r7, #4]
8004550: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004552: 687b ldr r3, [r7, #4]
8004554: 697a ldr r2, [r7, #20]
8004556: 621a str r2, [r3, #32]
}
8004558: bf00 nop
800455a: 371c adds r7, #28
800455c: 46bd mov sp, r7
800455e: bc80 pop {r7}
8004560: 4770 bx lr
8004562: bf00 nop
8004564: 40012c00 .word 0x40012c00
08004568 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004568: b480 push {r7}
800456a: b087 sub sp, #28
800456c: af00 add r7, sp, #0
800456e: 6078 str r0, [r7, #4]
8004570: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004572: 687b ldr r3, [r7, #4]
8004574: 6a1b ldr r3, [r3, #32]
8004576: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8004578: 687b ldr r3, [r7, #4]
800457a: 6a1b ldr r3, [r3, #32]
800457c: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8004580: 687b ldr r3, [r7, #4]
8004582: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004584: 687b ldr r3, [r7, #4]
8004586: 685b ldr r3, [r3, #4]
8004588: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800458a: 687b ldr r3, [r7, #4]
800458c: 69db ldr r3, [r3, #28]
800458e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8004590: 68fb ldr r3, [r7, #12]
8004592: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004596: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8004598: 68fb ldr r3, [r7, #12]
800459a: f423 7340 bic.w r3, r3, #768 @ 0x300
800459e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80045a0: 683b ldr r3, [r7, #0]
80045a2: 681b ldr r3, [r3, #0]
80045a4: 021b lsls r3, r3, #8
80045a6: 68fa ldr r2, [r7, #12]
80045a8: 4313 orrs r3, r2
80045aa: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80045ac: 693b ldr r3, [r7, #16]
80045ae: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80045b2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80045b4: 683b ldr r3, [r7, #0]
80045b6: 689b ldr r3, [r3, #8]
80045b8: 031b lsls r3, r3, #12
80045ba: 693a ldr r2, [r7, #16]
80045bc: 4313 orrs r3, r2
80045be: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80045c0: 687b ldr r3, [r7, #4]
80045c2: 4a0f ldr r2, [pc, #60] @ (8004600 <TIM_OC4_SetConfig+0x98>)
80045c4: 4293 cmp r3, r2
80045c6: d109 bne.n 80045dc <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80045c8: 697b ldr r3, [r7, #20]
80045ca: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80045ce: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80045d0: 683b ldr r3, [r7, #0]
80045d2: 695b ldr r3, [r3, #20]
80045d4: 019b lsls r3, r3, #6
80045d6: 697a ldr r2, [r7, #20]
80045d8: 4313 orrs r3, r2
80045da: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80045dc: 687b ldr r3, [r7, #4]
80045de: 697a ldr r2, [r7, #20]
80045e0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80045e2: 687b ldr r3, [r7, #4]
80045e4: 68fa ldr r2, [r7, #12]
80045e6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80045e8: 683b ldr r3, [r7, #0]
80045ea: 685a ldr r2, [r3, #4]
80045ec: 687b ldr r3, [r7, #4]
80045ee: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80045f0: 687b ldr r3, [r7, #4]
80045f2: 693a ldr r2, [r7, #16]
80045f4: 621a str r2, [r3, #32]
}
80045f6: bf00 nop
80045f8: 371c adds r7, #28
80045fa: 46bd mov sp, r7
80045fc: bc80 pop {r7}
80045fe: 4770 bx lr
8004600: 40012c00 .word 0x40012c00
08004604 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8004604: b480 push {r7}
8004606: b087 sub sp, #28
8004608: af00 add r7, sp, #0
800460a: 60f8 str r0, [r7, #12]
800460c: 60b9 str r1, [r7, #8]
800460e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8004610: 68fb ldr r3, [r7, #12]
8004612: 6a1b ldr r3, [r3, #32]
8004614: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8004616: 68fb ldr r3, [r7, #12]
8004618: 6a1b ldr r3, [r3, #32]
800461a: f023 0201 bic.w r2, r3, #1
800461e: 68fb ldr r3, [r7, #12]
8004620: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8004622: 68fb ldr r3, [r7, #12]
8004624: 699b ldr r3, [r3, #24]
8004626: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8004628: 693b ldr r3, [r7, #16]
800462a: f023 03f0 bic.w r3, r3, #240 @ 0xf0
800462e: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8004630: 687b ldr r3, [r7, #4]
8004632: 011b lsls r3, r3, #4
8004634: 693a ldr r2, [r7, #16]
8004636: 4313 orrs r3, r2
8004638: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800463a: 697b ldr r3, [r7, #20]
800463c: f023 030a bic.w r3, r3, #10
8004640: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8004642: 697a ldr r2, [r7, #20]
8004644: 68bb ldr r3, [r7, #8]
8004646: 4313 orrs r3, r2
8004648: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800464a: 68fb ldr r3, [r7, #12]
800464c: 693a ldr r2, [r7, #16]
800464e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8004650: 68fb ldr r3, [r7, #12]
8004652: 697a ldr r2, [r7, #20]
8004654: 621a str r2, [r3, #32]
}
8004656: bf00 nop
8004658: 371c adds r7, #28
800465a: 46bd mov sp, r7
800465c: bc80 pop {r7}
800465e: 4770 bx lr
08004660 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8004660: b480 push {r7}
8004662: b087 sub sp, #28
8004664: af00 add r7, sp, #0
8004666: 60f8 str r0, [r7, #12]
8004668: 60b9 str r1, [r7, #8]
800466a: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
800466c: 68fb ldr r3, [r7, #12]
800466e: 6a1b ldr r3, [r3, #32]
8004670: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8004672: 68fb ldr r3, [r7, #12]
8004674: 6a1b ldr r3, [r3, #32]
8004676: f023 0210 bic.w r2, r3, #16
800467a: 68fb ldr r3, [r7, #12]
800467c: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800467e: 68fb ldr r3, [r7, #12]
8004680: 699b ldr r3, [r3, #24]
8004682: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8004684: 693b ldr r3, [r7, #16]
8004686: f423 4370 bic.w r3, r3, #61440 @ 0xf000
800468a: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
800468c: 687b ldr r3, [r7, #4]
800468e: 031b lsls r3, r3, #12
8004690: 693a ldr r2, [r7, #16]
8004692: 4313 orrs r3, r2
8004694: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8004696: 697b ldr r3, [r7, #20]
8004698: f023 03a0 bic.w r3, r3, #160 @ 0xa0
800469c: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
800469e: 68bb ldr r3, [r7, #8]
80046a0: 011b lsls r3, r3, #4
80046a2: 697a ldr r2, [r7, #20]
80046a4: 4313 orrs r3, r2
80046a6: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80046a8: 68fb ldr r3, [r7, #12]
80046aa: 693a ldr r2, [r7, #16]
80046ac: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80046ae: 68fb ldr r3, [r7, #12]
80046b0: 697a ldr r2, [r7, #20]
80046b2: 621a str r2, [r3, #32]
}
80046b4: bf00 nop
80046b6: 371c adds r7, #28
80046b8: 46bd mov sp, r7
80046ba: bc80 pop {r7}
80046bc: 4770 bx lr
080046be <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80046be: b480 push {r7}
80046c0: b085 sub sp, #20
80046c2: af00 add r7, sp, #0
80046c4: 6078 str r0, [r7, #4]
80046c6: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80046c8: 687b ldr r3, [r7, #4]
80046ca: 689b ldr r3, [r3, #8]
80046cc: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80046ce: 68fb ldr r3, [r7, #12]
80046d0: f023 0370 bic.w r3, r3, #112 @ 0x70
80046d4: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80046d6: 683a ldr r2, [r7, #0]
80046d8: 68fb ldr r3, [r7, #12]
80046da: 4313 orrs r3, r2
80046dc: f043 0307 orr.w r3, r3, #7
80046e0: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80046e2: 687b ldr r3, [r7, #4]
80046e4: 68fa ldr r2, [r7, #12]
80046e6: 609a str r2, [r3, #8]
}
80046e8: bf00 nop
80046ea: 3714 adds r7, #20
80046ec: 46bd mov sp, r7
80046ee: bc80 pop {r7}
80046f0: 4770 bx lr
080046f2 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
80046f2: b480 push {r7}
80046f4: b087 sub sp, #28
80046f6: af00 add r7, sp, #0
80046f8: 60f8 str r0, [r7, #12]
80046fa: 60b9 str r1, [r7, #8]
80046fc: 607a str r2, [r7, #4]
80046fe: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8004700: 68fb ldr r3, [r7, #12]
8004702: 689b ldr r3, [r3, #8]
8004704: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004706: 697b ldr r3, [r7, #20]
8004708: f423 437f bic.w r3, r3, #65280 @ 0xff00
800470c: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
800470e: 683b ldr r3, [r7, #0]
8004710: 021a lsls r2, r3, #8
8004712: 687b ldr r3, [r7, #4]
8004714: 431a orrs r2, r3
8004716: 68bb ldr r3, [r7, #8]
8004718: 4313 orrs r3, r2
800471a: 697a ldr r2, [r7, #20]
800471c: 4313 orrs r3, r2
800471e: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8004720: 68fb ldr r3, [r7, #12]
8004722: 697a ldr r2, [r7, #20]
8004724: 609a str r2, [r3, #8]
}
8004726: bf00 nop
8004728: 371c adds r7, #28
800472a: 46bd mov sp, r7
800472c: bc80 pop {r7}
800472e: 4770 bx lr
08004730 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8004730: b480 push {r7}
8004732: b087 sub sp, #28
8004734: af00 add r7, sp, #0
8004736: 60f8 str r0, [r7, #12]
8004738: 60b9 str r1, [r7, #8]
800473a: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
800473c: 68bb ldr r3, [r7, #8]
800473e: f003 031f and.w r3, r3, #31
8004742: 2201 movs r2, #1
8004744: fa02 f303 lsl.w r3, r2, r3
8004748: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
800474a: 68fb ldr r3, [r7, #12]
800474c: 6a1a ldr r2, [r3, #32]
800474e: 697b ldr r3, [r7, #20]
8004750: 43db mvns r3, r3
8004752: 401a ands r2, r3
8004754: 68fb ldr r3, [r7, #12]
8004756: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8004758: 68fb ldr r3, [r7, #12]
800475a: 6a1a ldr r2, [r3, #32]
800475c: 68bb ldr r3, [r7, #8]
800475e: f003 031f and.w r3, r3, #31
8004762: 6879 ldr r1, [r7, #4]
8004764: fa01 f303 lsl.w r3, r1, r3
8004768: 431a orrs r2, r3
800476a: 68fb ldr r3, [r7, #12]
800476c: 621a str r2, [r3, #32]
}
800476e: bf00 nop
8004770: 371c adds r7, #28
8004772: 46bd mov sp, r7
8004774: bc80 pop {r7}
8004776: 4770 bx lr
08004778 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8004778: b480 push {r7}
800477a: b085 sub sp, #20
800477c: af00 add r7, sp, #0
800477e: 6078 str r0, [r7, #4]
8004780: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8004782: 687b ldr r3, [r7, #4]
8004784: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004788: 2b01 cmp r3, #1
800478a: d101 bne.n 8004790 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800478c: 2302 movs r3, #2
800478e: e046 b.n 800481e <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8004790: 687b ldr r3, [r7, #4]
8004792: 2201 movs r2, #1
8004794: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8004798: 687b ldr r3, [r7, #4]
800479a: 2202 movs r2, #2
800479c: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80047a0: 687b ldr r3, [r7, #4]
80047a2: 681b ldr r3, [r3, #0]
80047a4: 685b ldr r3, [r3, #4]
80047a6: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80047a8: 687b ldr r3, [r7, #4]
80047aa: 681b ldr r3, [r3, #0]
80047ac: 689b ldr r3, [r3, #8]
80047ae: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80047b0: 68fb ldr r3, [r7, #12]
80047b2: f023 0370 bic.w r3, r3, #112 @ 0x70
80047b6: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80047b8: 683b ldr r3, [r7, #0]
80047ba: 681b ldr r3, [r3, #0]
80047bc: 68fa ldr r2, [r7, #12]
80047be: 4313 orrs r3, r2
80047c0: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80047c2: 687b ldr r3, [r7, #4]
80047c4: 681b ldr r3, [r3, #0]
80047c6: 68fa ldr r2, [r7, #12]
80047c8: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80047ca: 687b ldr r3, [r7, #4]
80047cc: 681b ldr r3, [r3, #0]
80047ce: 4a16 ldr r2, [pc, #88] @ (8004828 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
80047d0: 4293 cmp r3, r2
80047d2: d00e beq.n 80047f2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80047d4: 687b ldr r3, [r7, #4]
80047d6: 681b ldr r3, [r3, #0]
80047d8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80047dc: d009 beq.n 80047f2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80047de: 687b ldr r3, [r7, #4]
80047e0: 681b ldr r3, [r3, #0]
80047e2: 4a12 ldr r2, [pc, #72] @ (800482c <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
80047e4: 4293 cmp r3, r2
80047e6: d004 beq.n 80047f2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
80047e8: 687b ldr r3, [r7, #4]
80047ea: 681b ldr r3, [r3, #0]
80047ec: 4a10 ldr r2, [pc, #64] @ (8004830 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
80047ee: 4293 cmp r3, r2
80047f0: d10c bne.n 800480c <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
80047f2: 68bb ldr r3, [r7, #8]
80047f4: f023 0380 bic.w r3, r3, #128 @ 0x80
80047f8: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
80047fa: 683b ldr r3, [r7, #0]
80047fc: 685b ldr r3, [r3, #4]
80047fe: 68ba ldr r2, [r7, #8]
8004800: 4313 orrs r3, r2
8004802: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004804: 687b ldr r3, [r7, #4]
8004806: 681b ldr r3, [r3, #0]
8004808: 68ba ldr r2, [r7, #8]
800480a: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800480c: 687b ldr r3, [r7, #4]
800480e: 2201 movs r2, #1
8004810: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004814: 687b ldr r3, [r7, #4]
8004816: 2200 movs r2, #0
8004818: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
800481c: 2300 movs r3, #0
}
800481e: 4618 mov r0, r3
8004820: 3714 adds r7, #20
8004822: 46bd mov sp, r7
8004824: bc80 pop {r7}
8004826: 4770 bx lr
8004828: 40012c00 .word 0x40012c00
800482c: 40000400 .word 0x40000400
8004830: 40000800 .word 0x40000800
08004834 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8004834: b480 push {r7}
8004836: b085 sub sp, #20
8004838: af00 add r7, sp, #0
800483a: 6078 str r0, [r7, #4]
800483c: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
800483e: 2300 movs r3, #0
8004840: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8004842: 687b ldr r3, [r7, #4]
8004844: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004848: 2b01 cmp r3, #1
800484a: d101 bne.n 8004850 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
800484c: 2302 movs r3, #2
800484e: e03d b.n 80048cc <HAL_TIMEx_ConfigBreakDeadTime+0x98>
8004850: 687b ldr r3, [r7, #4]
8004852: 2201 movs r2, #1
8004854: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8004858: 68fb ldr r3, [r7, #12]
800485a: f023 02ff bic.w r2, r3, #255 @ 0xff
800485e: 683b ldr r3, [r7, #0]
8004860: 68db ldr r3, [r3, #12]
8004862: 4313 orrs r3, r2
8004864: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8004866: 68fb ldr r3, [r7, #12]
8004868: f423 7240 bic.w r2, r3, #768 @ 0x300
800486c: 683b ldr r3, [r7, #0]
800486e: 689b ldr r3, [r3, #8]
8004870: 4313 orrs r3, r2
8004872: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8004874: 68fb ldr r3, [r7, #12]
8004876: f423 6280 bic.w r2, r3, #1024 @ 0x400
800487a: 683b ldr r3, [r7, #0]
800487c: 685b ldr r3, [r3, #4]
800487e: 4313 orrs r3, r2
8004880: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8004882: 68fb ldr r3, [r7, #12]
8004884: f423 6200 bic.w r2, r3, #2048 @ 0x800
8004888: 683b ldr r3, [r7, #0]
800488a: 681b ldr r3, [r3, #0]
800488c: 4313 orrs r3, r2
800488e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8004890: 68fb ldr r3, [r7, #12]
8004892: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8004896: 683b ldr r3, [r7, #0]
8004898: 691b ldr r3, [r3, #16]
800489a: 4313 orrs r3, r2
800489c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
800489e: 68fb ldr r3, [r7, #12]
80048a0: f423 5200 bic.w r2, r3, #8192 @ 0x2000
80048a4: 683b ldr r3, [r7, #0]
80048a6: 695b ldr r3, [r3, #20]
80048a8: 4313 orrs r3, r2
80048aa: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
80048ac: 68fb ldr r3, [r7, #12]
80048ae: f423 4280 bic.w r2, r3, #16384 @ 0x4000
80048b2: 683b ldr r3, [r7, #0]
80048b4: 69db ldr r3, [r3, #28]
80048b6: 4313 orrs r3, r2
80048b8: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
80048ba: 687b ldr r3, [r7, #4]
80048bc: 681b ldr r3, [r3, #0]
80048be: 68fa ldr r2, [r7, #12]
80048c0: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
80048c2: 687b ldr r3, [r7, #4]
80048c4: 2200 movs r2, #0
80048c6: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80048ca: 2300 movs r3, #0
}
80048cc: 4618 mov r0, r3
80048ce: 3714 adds r7, #20
80048d0: 46bd mov sp, r7
80048d2: bc80 pop {r7}
80048d4: 4770 bx lr
080048d6 <USB_CoreInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
80048d6: b480 push {r7}
80048d8: b085 sub sp, #20
80048da: af00 add r7, sp, #0
80048dc: 60f8 str r0, [r7, #12]
80048de: 4638 mov r0, r7
80048e0: e880 000e stmia.w r0, {r1, r2, r3}
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
80048e4: 2300 movs r3, #0
}
80048e6: 4618 mov r0, r3
80048e8: 3714 adds r7, #20
80048ea: 46bd mov sp, r7
80048ec: bc80 pop {r7}
80048ee: 4770 bx lr
080048f0 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
80048f0: b480 push {r7}
80048f2: b085 sub sp, #20
80048f4: af00 add r7, sp, #0
80048f6: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
80048f8: 687b ldr r3, [r7, #4]
80048fa: 2200 movs r2, #0
80048fc: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8004900: f44f 433f mov.w r3, #48896 @ 0xbf00
8004904: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR = (uint16_t)winterruptmask;
8004906: 68fb ldr r3, [r7, #12]
8004908: b29a uxth r2, r3
800490a: 687b ldr r3, [r7, #4]
800490c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8004910: 2300 movs r3, #0
}
8004912: 4618 mov r0, r3
8004914: 3714 adds r7, #20
8004916: 46bd mov sp, r7
8004918: bc80 pop {r7}
800491a: 4770 bx lr
0800491c <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
800491c: b480 push {r7}
800491e: b085 sub sp, #20
8004920: af00 add r7, sp, #0
8004922: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8004924: f44f 433f mov.w r3, #48896 @ 0xbf00
8004928: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= (uint16_t)(~winterruptmask);
800492a: 687b ldr r3, [r7, #4]
800492c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8004930: b29a uxth r2, r3
8004932: 68fb ldr r3, [r7, #12]
8004934: b29b uxth r3, r3
8004936: 43db mvns r3, r3
8004938: b29b uxth r3, r3
800493a: 4013 ands r3, r2
800493c: b29a uxth r2, r3
800493e: 687b ldr r3, [r7, #4]
8004940: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
8004944: 2300 movs r3, #0
}
8004946: 4618 mov r0, r3
8004948: 3714 adds r7, #20
800494a: 46bd mov sp, r7
800494c: bc80 pop {r7}
800494e: 4770 bx lr
08004950 <USB_SetCurrentMode>:
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
8004950: b480 push {r7}
8004952: b083 sub sp, #12
8004954: af00 add r7, sp, #0
8004956: 6078 str r0, [r7, #4]
8004958: 460b mov r3, r1
800495a: 70fb strb r3, [r7, #3]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
800495c: 2300 movs r3, #0
}
800495e: 4618 mov r0, r3
8004960: 370c adds r7, #12
8004962: 46bd mov sp, r7
8004964: bc80 pop {r7}
8004966: 4770 bx lr
08004968 <USB_DevInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8004968: b480 push {r7}
800496a: b085 sub sp, #20
800496c: af00 add r7, sp, #0
800496e: 60f8 str r0, [r7, #12]
8004970: 4638 mov r0, r7
8004972: e880 000e stmia.w r0, {r1, r2, r3}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
8004976: 68fb ldr r3, [r7, #12]
8004978: 2201 movs r2, #1
800497a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
800497e: 68fb ldr r3, [r7, #12]
8004980: 2200 movs r2, #0
8004982: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* Clear pending interrupts */
USBx->ISTR = 0U;
8004986: 68fb ldr r3, [r7, #12]
8004988: 2200 movs r2, #0
800498a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
800498e: 68fb ldr r3, [r7, #12]
8004990: 2200 movs r2, #0
8004992: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
return HAL_OK;
8004996: 2300 movs r3, #0
}
8004998: 4618 mov r0, r3
800499a: 3714 adds r7, #20
800499c: 46bd mov sp, r7
800499e: bc80 pop {r7}
80049a0: 4770 bx lr
...
080049a4 <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
80049a4: b480 push {r7}
80049a6: b09d sub sp, #116 @ 0x74
80049a8: af00 add r7, sp, #0
80049aa: 6078 str r0, [r7, #4]
80049ac: 6039 str r1, [r7, #0]
HAL_StatusTypeDef ret = HAL_OK;
80049ae: 2300 movs r3, #0
80049b0: f887 306f strb.w r3, [r7, #111] @ 0x6f
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
80049b4: 687a ldr r2, [r7, #4]
80049b6: 683b ldr r3, [r7, #0]
80049b8: 781b ldrb r3, [r3, #0]
80049ba: 009b lsls r3, r3, #2
80049bc: 4413 add r3, r2
80049be: 881b ldrh r3, [r3, #0]
80049c0: b29b uxth r3, r3
80049c2: f423 43ec bic.w r3, r3, #30208 @ 0x7600
80049c6: f023 0370 bic.w r3, r3, #112 @ 0x70
80049ca: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
/* initialize Endpoint */
switch (ep->type)
80049ce: 683b ldr r3, [r7, #0]
80049d0: 78db ldrb r3, [r3, #3]
80049d2: 2b03 cmp r3, #3
80049d4: d81f bhi.n 8004a16 <USB_ActivateEndpoint+0x72>
80049d6: a201 add r2, pc, #4 @ (adr r2, 80049dc <USB_ActivateEndpoint+0x38>)
80049d8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80049dc: 080049ed .word 0x080049ed
80049e0: 08004a09 .word 0x08004a09
80049e4: 08004a1f .word 0x08004a1f
80049e8: 080049fb .word 0x080049fb
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
80049ec: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
80049f0: f443 7300 orr.w r3, r3, #512 @ 0x200
80049f4: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
80049f8: e012 b.n 8004a20 <USB_ActivateEndpoint+0x7c>
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
80049fa: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
80049fe: f443 63c0 orr.w r3, r3, #1536 @ 0x600
8004a02: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8004a06: e00b b.n 8004a20 <USB_ActivateEndpoint+0x7c>
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
8004a08: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8004a0c: f443 6380 orr.w r3, r3, #1024 @ 0x400
8004a10: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
break;
8004a14: e004 b.n 8004a20 <USB_ActivateEndpoint+0x7c>
default:
ret = HAL_ERROR;
8004a16: 2301 movs r3, #1
8004a18: f887 306f strb.w r3, [r7, #111] @ 0x6f
break;
8004a1c: e000 b.n 8004a20 <USB_ActivateEndpoint+0x7c>
break;
8004a1e: bf00 nop
}
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
8004a20: 687a ldr r2, [r7, #4]
8004a22: 683b ldr r3, [r7, #0]
8004a24: 781b ldrb r3, [r3, #0]
8004a26: 009b lsls r3, r3, #2
8004a28: 441a add r2, r3
8004a2a: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8004a2e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004a32: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004a36: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004a3a: f043 0380 orr.w r3, r3, #128 @ 0x80
8004a3e: b29b uxth r3, r3
8004a40: 8013 strh r3, [r2, #0]
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
8004a42: 687a ldr r2, [r7, #4]
8004a44: 683b ldr r3, [r7, #0]
8004a46: 781b ldrb r3, [r3, #0]
8004a48: 009b lsls r3, r3, #2
8004a4a: 4413 add r3, r2
8004a4c: 881b ldrh r3, [r3, #0]
8004a4e: b29b uxth r3, r3
8004a50: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004a54: f023 0370 bic.w r3, r3, #112 @ 0x70
8004a58: b29b uxth r3, r3
8004a5a: 683a ldr r2, [r7, #0]
8004a5c: 7812 ldrb r2, [r2, #0]
8004a5e: 4313 orrs r3, r2
8004a60: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
8004a64: 687a ldr r2, [r7, #4]
8004a66: 683b ldr r3, [r7, #0]
8004a68: 781b ldrb r3, [r3, #0]
8004a6a: 009b lsls r3, r3, #2
8004a6c: 441a add r2, r3
8004a6e: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
8004a72: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004a76: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004a7a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004a7e: f043 0380 orr.w r3, r3, #128 @ 0x80
8004a82: b29b uxth r3, r3
8004a84: 8013 strh r3, [r2, #0]
if (ep->doublebuffer == 0U)
8004a86: 683b ldr r3, [r7, #0]
8004a88: 7b1b ldrb r3, [r3, #12]
8004a8a: 2b00 cmp r3, #0
8004a8c: f040 8178 bne.w 8004d80 <USB_ActivateEndpoint+0x3dc>
{
if (ep->is_in != 0U)
8004a90: 683b ldr r3, [r7, #0]
8004a92: 785b ldrb r3, [r3, #1]
8004a94: 2b00 cmp r3, #0
8004a96: f000 8084 beq.w 8004ba2 <USB_ActivateEndpoint+0x1fe>
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
8004a9a: 687b ldr r3, [r7, #4]
8004a9c: 61bb str r3, [r7, #24]
8004a9e: 687b ldr r3, [r7, #4]
8004aa0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004aa4: b29b uxth r3, r3
8004aa6: 461a mov r2, r3
8004aa8: 69bb ldr r3, [r7, #24]
8004aaa: 4413 add r3, r2
8004aac: 61bb str r3, [r7, #24]
8004aae: 683b ldr r3, [r7, #0]
8004ab0: 781b ldrb r3, [r3, #0]
8004ab2: 011a lsls r2, r3, #4
8004ab4: 69bb ldr r3, [r7, #24]
8004ab6: 4413 add r3, r2
8004ab8: f503 6380 add.w r3, r3, #1024 @ 0x400
8004abc: 617b str r3, [r7, #20]
8004abe: 683b ldr r3, [r7, #0]
8004ac0: 88db ldrh r3, [r3, #6]
8004ac2: 085b lsrs r3, r3, #1
8004ac4: b29b uxth r3, r3
8004ac6: 005b lsls r3, r3, #1
8004ac8: b29a uxth r2, r3
8004aca: 697b ldr r3, [r7, #20]
8004acc: 801a strh r2, [r3, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8004ace: 687a ldr r2, [r7, #4]
8004ad0: 683b ldr r3, [r7, #0]
8004ad2: 781b ldrb r3, [r3, #0]
8004ad4: 009b lsls r3, r3, #2
8004ad6: 4413 add r3, r2
8004ad8: 881b ldrh r3, [r3, #0]
8004ada: 827b strh r3, [r7, #18]
8004adc: 8a7b ldrh r3, [r7, #18]
8004ade: f003 0340 and.w r3, r3, #64 @ 0x40
8004ae2: 2b00 cmp r3, #0
8004ae4: d01b beq.n 8004b1e <USB_ActivateEndpoint+0x17a>
8004ae6: 687a ldr r2, [r7, #4]
8004ae8: 683b ldr r3, [r7, #0]
8004aea: 781b ldrb r3, [r3, #0]
8004aec: 009b lsls r3, r3, #2
8004aee: 4413 add r3, r2
8004af0: 881b ldrh r3, [r3, #0]
8004af2: b29b uxth r3, r3
8004af4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004af8: f023 0370 bic.w r3, r3, #112 @ 0x70
8004afc: 823b strh r3, [r7, #16]
8004afe: 687a ldr r2, [r7, #4]
8004b00: 683b ldr r3, [r7, #0]
8004b02: 781b ldrb r3, [r3, #0]
8004b04: 009b lsls r3, r3, #2
8004b06: 441a add r2, r3
8004b08: 8a3b ldrh r3, [r7, #16]
8004b0a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b0e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b12: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004b16: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8004b1a: b29b uxth r3, r3
8004b1c: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8004b1e: 683b ldr r3, [r7, #0]
8004b20: 78db ldrb r3, [r3, #3]
8004b22: 2b01 cmp r3, #1
8004b24: d020 beq.n 8004b68 <USB_ActivateEndpoint+0x1c4>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8004b26: 687a ldr r2, [r7, #4]
8004b28: 683b ldr r3, [r7, #0]
8004b2a: 781b ldrb r3, [r3, #0]
8004b2c: 009b lsls r3, r3, #2
8004b2e: 4413 add r3, r2
8004b30: 881b ldrh r3, [r3, #0]
8004b32: b29b uxth r3, r3
8004b34: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004b38: f023 0340 bic.w r3, r3, #64 @ 0x40
8004b3c: 81bb strh r3, [r7, #12]
8004b3e: 89bb ldrh r3, [r7, #12]
8004b40: f083 0320 eor.w r3, r3, #32
8004b44: 81bb strh r3, [r7, #12]
8004b46: 687a ldr r2, [r7, #4]
8004b48: 683b ldr r3, [r7, #0]
8004b4a: 781b ldrb r3, [r3, #0]
8004b4c: 009b lsls r3, r3, #2
8004b4e: 441a add r2, r3
8004b50: 89bb ldrh r3, [r7, #12]
8004b52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b5a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004b5e: f043 0380 orr.w r3, r3, #128 @ 0x80
8004b62: b29b uxth r3, r3
8004b64: 8013 strh r3, [r2, #0]
8004b66: e2d5 b.n 8005114 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8004b68: 687a ldr r2, [r7, #4]
8004b6a: 683b ldr r3, [r7, #0]
8004b6c: 781b ldrb r3, [r3, #0]
8004b6e: 009b lsls r3, r3, #2
8004b70: 4413 add r3, r2
8004b72: 881b ldrh r3, [r3, #0]
8004b74: b29b uxth r3, r3
8004b76: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004b7a: f023 0340 bic.w r3, r3, #64 @ 0x40
8004b7e: 81fb strh r3, [r7, #14]
8004b80: 687a ldr r2, [r7, #4]
8004b82: 683b ldr r3, [r7, #0]
8004b84: 781b ldrb r3, [r3, #0]
8004b86: 009b lsls r3, r3, #2
8004b88: 441a add r2, r3
8004b8a: 89fb ldrh r3, [r7, #14]
8004b8c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004b90: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004b94: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004b98: f043 0380 orr.w r3, r3, #128 @ 0x80
8004b9c: b29b uxth r3, r3
8004b9e: 8013 strh r3, [r2, #0]
8004ba0: e2b8 b.n 8005114 <USB_ActivateEndpoint+0x770>
}
}
else
{
/* Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
8004ba2: 687b ldr r3, [r7, #4]
8004ba4: 633b str r3, [r7, #48] @ 0x30
8004ba6: 687b ldr r3, [r7, #4]
8004ba8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004bac: b29b uxth r3, r3
8004bae: 461a mov r2, r3
8004bb0: 6b3b ldr r3, [r7, #48] @ 0x30
8004bb2: 4413 add r3, r2
8004bb4: 633b str r3, [r7, #48] @ 0x30
8004bb6: 683b ldr r3, [r7, #0]
8004bb8: 781b ldrb r3, [r3, #0]
8004bba: 011a lsls r2, r3, #4
8004bbc: 6b3b ldr r3, [r7, #48] @ 0x30
8004bbe: 4413 add r3, r2
8004bc0: f503 6381 add.w r3, r3, #1032 @ 0x408
8004bc4: 62fb str r3, [r7, #44] @ 0x2c
8004bc6: 683b ldr r3, [r7, #0]
8004bc8: 88db ldrh r3, [r3, #6]
8004bca: 085b lsrs r3, r3, #1
8004bcc: b29b uxth r3, r3
8004bce: 005b lsls r3, r3, #1
8004bd0: b29a uxth r2, r3
8004bd2: 6afb ldr r3, [r7, #44] @ 0x2c
8004bd4: 801a strh r2, [r3, #0]
/* Set the endpoint Receive buffer counter */
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
8004bd6: 687b ldr r3, [r7, #4]
8004bd8: 62bb str r3, [r7, #40] @ 0x28
8004bda: 687b ldr r3, [r7, #4]
8004bdc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004be0: b29b uxth r3, r3
8004be2: 461a mov r2, r3
8004be4: 6abb ldr r3, [r7, #40] @ 0x28
8004be6: 4413 add r3, r2
8004be8: 62bb str r3, [r7, #40] @ 0x28
8004bea: 683b ldr r3, [r7, #0]
8004bec: 781b ldrb r3, [r3, #0]
8004bee: 011a lsls r2, r3, #4
8004bf0: 6abb ldr r3, [r7, #40] @ 0x28
8004bf2: 4413 add r3, r2
8004bf4: f203 430c addw r3, r3, #1036 @ 0x40c
8004bf8: 627b str r3, [r7, #36] @ 0x24
8004bfa: 6a7b ldr r3, [r7, #36] @ 0x24
8004bfc: 881b ldrh r3, [r3, #0]
8004bfe: b29b uxth r3, r3
8004c00: f3c3 0309 ubfx r3, r3, #0, #10
8004c04: b29a uxth r2, r3
8004c06: 6a7b ldr r3, [r7, #36] @ 0x24
8004c08: 801a strh r2, [r3, #0]
8004c0a: 683b ldr r3, [r7, #0]
8004c0c: 691b ldr r3, [r3, #16]
8004c0e: 2b3e cmp r3, #62 @ 0x3e
8004c10: d91d bls.n 8004c4e <USB_ActivateEndpoint+0x2aa>
8004c12: 683b ldr r3, [r7, #0]
8004c14: 691b ldr r3, [r3, #16]
8004c16: 095b lsrs r3, r3, #5
8004c18: 66bb str r3, [r7, #104] @ 0x68
8004c1a: 683b ldr r3, [r7, #0]
8004c1c: 691b ldr r3, [r3, #16]
8004c1e: f003 031f and.w r3, r3, #31
8004c22: 2b00 cmp r3, #0
8004c24: d102 bne.n 8004c2c <USB_ActivateEndpoint+0x288>
8004c26: 6ebb ldr r3, [r7, #104] @ 0x68
8004c28: 3b01 subs r3, #1
8004c2a: 66bb str r3, [r7, #104] @ 0x68
8004c2c: 6a7b ldr r3, [r7, #36] @ 0x24
8004c2e: 881b ldrh r3, [r3, #0]
8004c30: b29a uxth r2, r3
8004c32: 6ebb ldr r3, [r7, #104] @ 0x68
8004c34: b29b uxth r3, r3
8004c36: 029b lsls r3, r3, #10
8004c38: b29b uxth r3, r3
8004c3a: 4313 orrs r3, r2
8004c3c: b29b uxth r3, r3
8004c3e: ea6f 4343 mvn.w r3, r3, lsl #17
8004c42: ea6f 4353 mvn.w r3, r3, lsr #17
8004c46: b29a uxth r2, r3
8004c48: 6a7b ldr r3, [r7, #36] @ 0x24
8004c4a: 801a strh r2, [r3, #0]
8004c4c: e026 b.n 8004c9c <USB_ActivateEndpoint+0x2f8>
8004c4e: 683b ldr r3, [r7, #0]
8004c50: 691b ldr r3, [r3, #16]
8004c52: 2b00 cmp r3, #0
8004c54: d10a bne.n 8004c6c <USB_ActivateEndpoint+0x2c8>
8004c56: 6a7b ldr r3, [r7, #36] @ 0x24
8004c58: 881b ldrh r3, [r3, #0]
8004c5a: b29b uxth r3, r3
8004c5c: ea6f 4343 mvn.w r3, r3, lsl #17
8004c60: ea6f 4353 mvn.w r3, r3, lsr #17
8004c64: b29a uxth r2, r3
8004c66: 6a7b ldr r3, [r7, #36] @ 0x24
8004c68: 801a strh r2, [r3, #0]
8004c6a: e017 b.n 8004c9c <USB_ActivateEndpoint+0x2f8>
8004c6c: 683b ldr r3, [r7, #0]
8004c6e: 691b ldr r3, [r3, #16]
8004c70: 085b lsrs r3, r3, #1
8004c72: 66bb str r3, [r7, #104] @ 0x68
8004c74: 683b ldr r3, [r7, #0]
8004c76: 691b ldr r3, [r3, #16]
8004c78: f003 0301 and.w r3, r3, #1
8004c7c: 2b00 cmp r3, #0
8004c7e: d002 beq.n 8004c86 <USB_ActivateEndpoint+0x2e2>
8004c80: 6ebb ldr r3, [r7, #104] @ 0x68
8004c82: 3301 adds r3, #1
8004c84: 66bb str r3, [r7, #104] @ 0x68
8004c86: 6a7b ldr r3, [r7, #36] @ 0x24
8004c88: 881b ldrh r3, [r3, #0]
8004c8a: b29a uxth r2, r3
8004c8c: 6ebb ldr r3, [r7, #104] @ 0x68
8004c8e: b29b uxth r3, r3
8004c90: 029b lsls r3, r3, #10
8004c92: b29b uxth r3, r3
8004c94: 4313 orrs r3, r2
8004c96: b29a uxth r2, r3
8004c98: 6a7b ldr r3, [r7, #36] @ 0x24
8004c9a: 801a strh r2, [r3, #0]
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8004c9c: 687a ldr r2, [r7, #4]
8004c9e: 683b ldr r3, [r7, #0]
8004ca0: 781b ldrb r3, [r3, #0]
8004ca2: 009b lsls r3, r3, #2
8004ca4: 4413 add r3, r2
8004ca6: 881b ldrh r3, [r3, #0]
8004ca8: 847b strh r3, [r7, #34] @ 0x22
8004caa: 8c7b ldrh r3, [r7, #34] @ 0x22
8004cac: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004cb0: 2b00 cmp r3, #0
8004cb2: d01b beq.n 8004cec <USB_ActivateEndpoint+0x348>
8004cb4: 687a ldr r2, [r7, #4]
8004cb6: 683b ldr r3, [r7, #0]
8004cb8: 781b ldrb r3, [r3, #0]
8004cba: 009b lsls r3, r3, #2
8004cbc: 4413 add r3, r2
8004cbe: 881b ldrh r3, [r3, #0]
8004cc0: b29b uxth r3, r3
8004cc2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004cc6: f023 0370 bic.w r3, r3, #112 @ 0x70
8004cca: 843b strh r3, [r7, #32]
8004ccc: 687a ldr r2, [r7, #4]
8004cce: 683b ldr r3, [r7, #0]
8004cd0: 781b ldrb r3, [r3, #0]
8004cd2: 009b lsls r3, r3, #2
8004cd4: 441a add r2, r3
8004cd6: 8c3b ldrh r3, [r7, #32]
8004cd8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004cdc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004ce0: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004ce4: f043 0380 orr.w r3, r3, #128 @ 0x80
8004ce8: b29b uxth r3, r3
8004cea: 8013 strh r3, [r2, #0]
if (ep->num == 0U)
8004cec: 683b ldr r3, [r7, #0]
8004cee: 781b ldrb r3, [r3, #0]
8004cf0: 2b00 cmp r3, #0
8004cf2: d124 bne.n 8004d3e <USB_ActivateEndpoint+0x39a>
{
/* Configure VALID status for EP0 */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8004cf4: 687a ldr r2, [r7, #4]
8004cf6: 683b ldr r3, [r7, #0]
8004cf8: 781b ldrb r3, [r3, #0]
8004cfa: 009b lsls r3, r3, #2
8004cfc: 4413 add r3, r2
8004cfe: 881b ldrh r3, [r3, #0]
8004d00: b29b uxth r3, r3
8004d02: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8004d06: f023 0370 bic.w r3, r3, #112 @ 0x70
8004d0a: 83bb strh r3, [r7, #28]
8004d0c: 8bbb ldrh r3, [r7, #28]
8004d0e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8004d12: 83bb strh r3, [r7, #28]
8004d14: 8bbb ldrh r3, [r7, #28]
8004d16: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8004d1a: 83bb strh r3, [r7, #28]
8004d1c: 687a ldr r2, [r7, #4]
8004d1e: 683b ldr r3, [r7, #0]
8004d20: 781b ldrb r3, [r3, #0]
8004d22: 009b lsls r3, r3, #2
8004d24: 441a add r2, r3
8004d26: 8bbb ldrh r3, [r7, #28]
8004d28: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004d2c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004d30: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004d34: f043 0380 orr.w r3, r3, #128 @ 0x80
8004d38: b29b uxth r3, r3
8004d3a: 8013 strh r3, [r2, #0]
8004d3c: e1ea b.n 8005114 <USB_ActivateEndpoint+0x770>
}
else
{
/* Configure NAK status for OUT Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
8004d3e: 687a ldr r2, [r7, #4]
8004d40: 683b ldr r3, [r7, #0]
8004d42: 781b ldrb r3, [r3, #0]
8004d44: 009b lsls r3, r3, #2
8004d46: 4413 add r3, r2
8004d48: 881b ldrh r3, [r3, #0]
8004d4a: b29b uxth r3, r3
8004d4c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8004d50: f023 0370 bic.w r3, r3, #112 @ 0x70
8004d54: 83fb strh r3, [r7, #30]
8004d56: 8bfb ldrh r3, [r7, #30]
8004d58: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8004d5c: 83fb strh r3, [r7, #30]
8004d5e: 687a ldr r2, [r7, #4]
8004d60: 683b ldr r3, [r7, #0]
8004d62: 781b ldrb r3, [r3, #0]
8004d64: 009b lsls r3, r3, #2
8004d66: 441a add r2, r3
8004d68: 8bfb ldrh r3, [r7, #30]
8004d6a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004d6e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004d72: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004d76: f043 0380 orr.w r3, r3, #128 @ 0x80
8004d7a: b29b uxth r3, r3
8004d7c: 8013 strh r3, [r2, #0]
8004d7e: e1c9 b.n 8005114 <USB_ActivateEndpoint+0x770>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->type == EP_TYPE_BULK)
8004d80: 683b ldr r3, [r7, #0]
8004d82: 78db ldrb r3, [r3, #3]
8004d84: 2b02 cmp r3, #2
8004d86: d11e bne.n 8004dc6 <USB_ActivateEndpoint+0x422>
{
/* Set bulk endpoint as double buffered */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
8004d88: 687a ldr r2, [r7, #4]
8004d8a: 683b ldr r3, [r7, #0]
8004d8c: 781b ldrb r3, [r3, #0]
8004d8e: 009b lsls r3, r3, #2
8004d90: 4413 add r3, r2
8004d92: 881b ldrh r3, [r3, #0]
8004d94: b29b uxth r3, r3
8004d96: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004d9a: f023 0370 bic.w r3, r3, #112 @ 0x70
8004d9e: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8004da2: 687a ldr r2, [r7, #4]
8004da4: 683b ldr r3, [r7, #0]
8004da6: 781b ldrb r3, [r3, #0]
8004da8: 009b lsls r3, r3, #2
8004daa: 441a add r2, r3
8004dac: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
8004db0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004db4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004db8: f443 4301 orr.w r3, r3, #33024 @ 0x8100
8004dbc: f043 0380 orr.w r3, r3, #128 @ 0x80
8004dc0: b29b uxth r3, r3
8004dc2: 8013 strh r3, [r2, #0]
8004dc4: e01d b.n 8004e02 <USB_ActivateEndpoint+0x45e>
}
else
{
/* Set the ISOC endpoint in double buffer mode */
PCD_CLEAR_EP_KIND(USBx, ep->num);
8004dc6: 687a ldr r2, [r7, #4]
8004dc8: 683b ldr r3, [r7, #0]
8004dca: 781b ldrb r3, [r3, #0]
8004dcc: 009b lsls r3, r3, #2
8004dce: 4413 add r3, r2
8004dd0: 881b ldrh r3, [r3, #0]
8004dd2: b29b uxth r3, r3
8004dd4: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8004dd8: f023 0370 bic.w r3, r3, #112 @ 0x70
8004ddc: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
8004de0: 687a ldr r2, [r7, #4]
8004de2: 683b ldr r3, [r7, #0]
8004de4: 781b ldrb r3, [r3, #0]
8004de6: 009b lsls r3, r3, #2
8004de8: 441a add r2, r3
8004dea: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
8004dee: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004df2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004df6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004dfa: f043 0380 orr.w r3, r3, #128 @ 0x80
8004dfe: b29b uxth r3, r3
8004e00: 8013 strh r3, [r2, #0]
}
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
8004e02: 687b ldr r3, [r7, #4]
8004e04: 65fb str r3, [r7, #92] @ 0x5c
8004e06: 687b ldr r3, [r7, #4]
8004e08: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e0c: b29b uxth r3, r3
8004e0e: 461a mov r2, r3
8004e10: 6dfb ldr r3, [r7, #92] @ 0x5c
8004e12: 4413 add r3, r2
8004e14: 65fb str r3, [r7, #92] @ 0x5c
8004e16: 683b ldr r3, [r7, #0]
8004e18: 781b ldrb r3, [r3, #0]
8004e1a: 011a lsls r2, r3, #4
8004e1c: 6dfb ldr r3, [r7, #92] @ 0x5c
8004e1e: 4413 add r3, r2
8004e20: f503 6380 add.w r3, r3, #1024 @ 0x400
8004e24: 65bb str r3, [r7, #88] @ 0x58
8004e26: 683b ldr r3, [r7, #0]
8004e28: 891b ldrh r3, [r3, #8]
8004e2a: 085b lsrs r3, r3, #1
8004e2c: b29b uxth r3, r3
8004e2e: 005b lsls r3, r3, #1
8004e30: b29a uxth r2, r3
8004e32: 6dbb ldr r3, [r7, #88] @ 0x58
8004e34: 801a strh r2, [r3, #0]
8004e36: 687b ldr r3, [r7, #4]
8004e38: 657b str r3, [r7, #84] @ 0x54
8004e3a: 687b ldr r3, [r7, #4]
8004e3c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8004e40: b29b uxth r3, r3
8004e42: 461a mov r2, r3
8004e44: 6d7b ldr r3, [r7, #84] @ 0x54
8004e46: 4413 add r3, r2
8004e48: 657b str r3, [r7, #84] @ 0x54
8004e4a: 683b ldr r3, [r7, #0]
8004e4c: 781b ldrb r3, [r3, #0]
8004e4e: 011a lsls r2, r3, #4
8004e50: 6d7b ldr r3, [r7, #84] @ 0x54
8004e52: 4413 add r3, r2
8004e54: f503 6381 add.w r3, r3, #1032 @ 0x408
8004e58: 653b str r3, [r7, #80] @ 0x50
8004e5a: 683b ldr r3, [r7, #0]
8004e5c: 895b ldrh r3, [r3, #10]
8004e5e: 085b lsrs r3, r3, #1
8004e60: b29b uxth r3, r3
8004e62: 005b lsls r3, r3, #1
8004e64: b29a uxth r2, r3
8004e66: 6d3b ldr r3, [r7, #80] @ 0x50
8004e68: 801a strh r2, [r3, #0]
if (ep->is_in == 0U)
8004e6a: 683b ldr r3, [r7, #0]
8004e6c: 785b ldrb r3, [r3, #1]
8004e6e: 2b00 cmp r3, #0
8004e70: f040 8093 bne.w 8004f9a <USB_ActivateEndpoint+0x5f6>
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8004e74: 687a ldr r2, [r7, #4]
8004e76: 683b ldr r3, [r7, #0]
8004e78: 781b ldrb r3, [r3, #0]
8004e7a: 009b lsls r3, r3, #2
8004e7c: 4413 add r3, r2
8004e7e: 881b ldrh r3, [r3, #0]
8004e80: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
8004e84: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
8004e88: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004e8c: 2b00 cmp r3, #0
8004e8e: d01b beq.n 8004ec8 <USB_ActivateEndpoint+0x524>
8004e90: 687a ldr r2, [r7, #4]
8004e92: 683b ldr r3, [r7, #0]
8004e94: 781b ldrb r3, [r3, #0]
8004e96: 009b lsls r3, r3, #2
8004e98: 4413 add r3, r2
8004e9a: 881b ldrh r3, [r3, #0]
8004e9c: b29b uxth r3, r3
8004e9e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004ea2: f023 0370 bic.w r3, r3, #112 @ 0x70
8004ea6: 87fb strh r3, [r7, #62] @ 0x3e
8004ea8: 687a ldr r2, [r7, #4]
8004eaa: 683b ldr r3, [r7, #0]
8004eac: 781b ldrb r3, [r3, #0]
8004eae: 009b lsls r3, r3, #2
8004eb0: 441a add r2, r3
8004eb2: 8ffb ldrh r3, [r7, #62] @ 0x3e
8004eb4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004eb8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004ebc: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004ec0: f043 0380 orr.w r3, r3, #128 @ 0x80
8004ec4: b29b uxth r3, r3
8004ec6: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8004ec8: 687a ldr r2, [r7, #4]
8004eca: 683b ldr r3, [r7, #0]
8004ecc: 781b ldrb r3, [r3, #0]
8004ece: 009b lsls r3, r3, #2
8004ed0: 4413 add r3, r2
8004ed2: 881b ldrh r3, [r3, #0]
8004ed4: 87bb strh r3, [r7, #60] @ 0x3c
8004ed6: 8fbb ldrh r3, [r7, #60] @ 0x3c
8004ed8: f003 0340 and.w r3, r3, #64 @ 0x40
8004edc: 2b00 cmp r3, #0
8004ede: d01b beq.n 8004f18 <USB_ActivateEndpoint+0x574>
8004ee0: 687a ldr r2, [r7, #4]
8004ee2: 683b ldr r3, [r7, #0]
8004ee4: 781b ldrb r3, [r3, #0]
8004ee6: 009b lsls r3, r3, #2
8004ee8: 4413 add r3, r2
8004eea: 881b ldrh r3, [r3, #0]
8004eec: b29b uxth r3, r3
8004eee: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004ef2: f023 0370 bic.w r3, r3, #112 @ 0x70
8004ef6: 877b strh r3, [r7, #58] @ 0x3a
8004ef8: 687a ldr r2, [r7, #4]
8004efa: 683b ldr r3, [r7, #0]
8004efc: 781b ldrb r3, [r3, #0]
8004efe: 009b lsls r3, r3, #2
8004f00: 441a add r2, r3
8004f02: 8f7b ldrh r3, [r7, #58] @ 0x3a
8004f04: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004f08: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004f0c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004f10: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8004f14: b29b uxth r3, r3
8004f16: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8004f18: 687a ldr r2, [r7, #4]
8004f1a: 683b ldr r3, [r7, #0]
8004f1c: 781b ldrb r3, [r3, #0]
8004f1e: 009b lsls r3, r3, #2
8004f20: 4413 add r3, r2
8004f22: 881b ldrh r3, [r3, #0]
8004f24: b29b uxth r3, r3
8004f26: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8004f2a: f023 0370 bic.w r3, r3, #112 @ 0x70
8004f2e: 873b strh r3, [r7, #56] @ 0x38
8004f30: 8f3b ldrh r3, [r7, #56] @ 0x38
8004f32: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8004f36: 873b strh r3, [r7, #56] @ 0x38
8004f38: 8f3b ldrh r3, [r7, #56] @ 0x38
8004f3a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8004f3e: 873b strh r3, [r7, #56] @ 0x38
8004f40: 687a ldr r2, [r7, #4]
8004f42: 683b ldr r3, [r7, #0]
8004f44: 781b ldrb r3, [r3, #0]
8004f46: 009b lsls r3, r3, #2
8004f48: 441a add r2, r3
8004f4a: 8f3b ldrh r3, [r7, #56] @ 0x38
8004f4c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004f50: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004f54: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004f58: f043 0380 orr.w r3, r3, #128 @ 0x80
8004f5c: b29b uxth r3, r3
8004f5e: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8004f60: 687a ldr r2, [r7, #4]
8004f62: 683b ldr r3, [r7, #0]
8004f64: 781b ldrb r3, [r3, #0]
8004f66: 009b lsls r3, r3, #2
8004f68: 4413 add r3, r2
8004f6a: 881b ldrh r3, [r3, #0]
8004f6c: b29b uxth r3, r3
8004f6e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004f72: f023 0340 bic.w r3, r3, #64 @ 0x40
8004f76: 86fb strh r3, [r7, #54] @ 0x36
8004f78: 687a ldr r2, [r7, #4]
8004f7a: 683b ldr r3, [r7, #0]
8004f7c: 781b ldrb r3, [r3, #0]
8004f7e: 009b lsls r3, r3, #2
8004f80: 441a add r2, r3
8004f82: 8efb ldrh r3, [r7, #54] @ 0x36
8004f84: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004f88: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004f8c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004f90: f043 0380 orr.w r3, r3, #128 @ 0x80
8004f94: b29b uxth r3, r3
8004f96: 8013 strh r3, [r2, #0]
8004f98: e0bc b.n 8005114 <USB_ActivateEndpoint+0x770>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8004f9a: 687a ldr r2, [r7, #4]
8004f9c: 683b ldr r3, [r7, #0]
8004f9e: 781b ldrb r3, [r3, #0]
8004fa0: 009b lsls r3, r3, #2
8004fa2: 4413 add r3, r2
8004fa4: 881b ldrh r3, [r3, #0]
8004fa6: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
8004faa: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8004fae: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004fb2: 2b00 cmp r3, #0
8004fb4: d01d beq.n 8004ff2 <USB_ActivateEndpoint+0x64e>
8004fb6: 687a ldr r2, [r7, #4]
8004fb8: 683b ldr r3, [r7, #0]
8004fba: 781b ldrb r3, [r3, #0]
8004fbc: 009b lsls r3, r3, #2
8004fbe: 4413 add r3, r2
8004fc0: 881b ldrh r3, [r3, #0]
8004fc2: b29b uxth r3, r3
8004fc4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004fc8: f023 0370 bic.w r3, r3, #112 @ 0x70
8004fcc: f8a7 304c strh.w r3, [r7, #76] @ 0x4c
8004fd0: 687a ldr r2, [r7, #4]
8004fd2: 683b ldr r3, [r7, #0]
8004fd4: 781b ldrb r3, [r3, #0]
8004fd6: 009b lsls r3, r3, #2
8004fd8: 441a add r2, r3
8004fda: f8b7 304c ldrh.w r3, [r7, #76] @ 0x4c
8004fde: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8004fe2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8004fe6: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8004fea: f043 0380 orr.w r3, r3, #128 @ 0x80
8004fee: b29b uxth r3, r3
8004ff0: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8004ff2: 687a ldr r2, [r7, #4]
8004ff4: 683b ldr r3, [r7, #0]
8004ff6: 781b ldrb r3, [r3, #0]
8004ff8: 009b lsls r3, r3, #2
8004ffa: 4413 add r3, r2
8004ffc: 881b ldrh r3, [r3, #0]
8004ffe: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
8005002: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
8005006: f003 0340 and.w r3, r3, #64 @ 0x40
800500a: 2b00 cmp r3, #0
800500c: d01d beq.n 800504a <USB_ActivateEndpoint+0x6a6>
800500e: 687a ldr r2, [r7, #4]
8005010: 683b ldr r3, [r7, #0]
8005012: 781b ldrb r3, [r3, #0]
8005014: 009b lsls r3, r3, #2
8005016: 4413 add r3, r2
8005018: 881b ldrh r3, [r3, #0]
800501a: b29b uxth r3, r3
800501c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005020: f023 0370 bic.w r3, r3, #112 @ 0x70
8005024: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
8005028: 687a ldr r2, [r7, #4]
800502a: 683b ldr r3, [r7, #0]
800502c: 781b ldrb r3, [r3, #0]
800502e: 009b lsls r3, r3, #2
8005030: 441a add r2, r3
8005032: f8b7 3048 ldrh.w r3, [r7, #72] @ 0x48
8005036: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800503a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800503e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005042: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8005046: b29b uxth r3, r3
8005048: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800504a: 683b ldr r3, [r7, #0]
800504c: 78db ldrb r3, [r3, #3]
800504e: 2b01 cmp r3, #1
8005050: d024 beq.n 800509c <USB_ActivateEndpoint+0x6f8>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8005052: 687a ldr r2, [r7, #4]
8005054: 683b ldr r3, [r7, #0]
8005056: 781b ldrb r3, [r3, #0]
8005058: 009b lsls r3, r3, #2
800505a: 4413 add r3, r2
800505c: 881b ldrh r3, [r3, #0]
800505e: b29b uxth r3, r3
8005060: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005064: f023 0340 bic.w r3, r3, #64 @ 0x40
8005068: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
800506c: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
8005070: f083 0320 eor.w r3, r3, #32
8005074: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
8005078: 687a ldr r2, [r7, #4]
800507a: 683b ldr r3, [r7, #0]
800507c: 781b ldrb r3, [r3, #0]
800507e: 009b lsls r3, r3, #2
8005080: 441a add r2, r3
8005082: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
8005086: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800508a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800508e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005092: f043 0380 orr.w r3, r3, #128 @ 0x80
8005096: b29b uxth r3, r3
8005098: 8013 strh r3, [r2, #0]
800509a: e01d b.n 80050d8 <USB_ActivateEndpoint+0x734>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800509c: 687a ldr r2, [r7, #4]
800509e: 683b ldr r3, [r7, #0]
80050a0: 781b ldrb r3, [r3, #0]
80050a2: 009b lsls r3, r3, #2
80050a4: 4413 add r3, r2
80050a6: 881b ldrh r3, [r3, #0]
80050a8: b29b uxth r3, r3
80050aa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80050ae: f023 0340 bic.w r3, r3, #64 @ 0x40
80050b2: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
80050b6: 687a ldr r2, [r7, #4]
80050b8: 683b ldr r3, [r7, #0]
80050ba: 781b ldrb r3, [r3, #0]
80050bc: 009b lsls r3, r3, #2
80050be: 441a add r2, r3
80050c0: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46
80050c4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80050c8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80050cc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80050d0: f043 0380 orr.w r3, r3, #128 @ 0x80
80050d4: b29b uxth r3, r3
80050d6: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80050d8: 687a ldr r2, [r7, #4]
80050da: 683b ldr r3, [r7, #0]
80050dc: 781b ldrb r3, [r3, #0]
80050de: 009b lsls r3, r3, #2
80050e0: 4413 add r3, r2
80050e2: 881b ldrh r3, [r3, #0]
80050e4: b29b uxth r3, r3
80050e6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80050ea: f023 0370 bic.w r3, r3, #112 @ 0x70
80050ee: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
80050f2: 687a ldr r2, [r7, #4]
80050f4: 683b ldr r3, [r7, #0]
80050f6: 781b ldrb r3, [r3, #0]
80050f8: 009b lsls r3, r3, #2
80050fa: 441a add r2, r3
80050fc: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
8005100: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005104: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005108: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800510c: f043 0380 orr.w r3, r3, #128 @ 0x80
8005110: b29b uxth r3, r3
8005112: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
8005114: f897 306f ldrb.w r3, [r7, #111] @ 0x6f
}
8005118: 4618 mov r0, r3
800511a: 3774 adds r7, #116 @ 0x74
800511c: 46bd mov sp, r7
800511e: bc80 pop {r7}
8005120: 4770 bx lr
8005122: bf00 nop
08005124 <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8005124: b480 push {r7}
8005126: b08d sub sp, #52 @ 0x34
8005128: af00 add r7, sp, #0
800512a: 6078 str r0, [r7, #4]
800512c: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
800512e: 683b ldr r3, [r7, #0]
8005130: 7b1b ldrb r3, [r3, #12]
8005132: 2b00 cmp r3, #0
8005134: f040 808e bne.w 8005254 <USB_DeactivateEndpoint+0x130>
{
if (ep->is_in != 0U)
8005138: 683b ldr r3, [r7, #0]
800513a: 785b ldrb r3, [r3, #1]
800513c: 2b00 cmp r3, #0
800513e: d044 beq.n 80051ca <USB_DeactivateEndpoint+0xa6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8005140: 687a ldr r2, [r7, #4]
8005142: 683b ldr r3, [r7, #0]
8005144: 781b ldrb r3, [r3, #0]
8005146: 009b lsls r3, r3, #2
8005148: 4413 add r3, r2
800514a: 881b ldrh r3, [r3, #0]
800514c: 81bb strh r3, [r7, #12]
800514e: 89bb ldrh r3, [r7, #12]
8005150: f003 0340 and.w r3, r3, #64 @ 0x40
8005154: 2b00 cmp r3, #0
8005156: d01b beq.n 8005190 <USB_DeactivateEndpoint+0x6c>
8005158: 687a ldr r2, [r7, #4]
800515a: 683b ldr r3, [r7, #0]
800515c: 781b ldrb r3, [r3, #0]
800515e: 009b lsls r3, r3, #2
8005160: 4413 add r3, r2
8005162: 881b ldrh r3, [r3, #0]
8005164: b29b uxth r3, r3
8005166: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800516a: f023 0370 bic.w r3, r3, #112 @ 0x70
800516e: 817b strh r3, [r7, #10]
8005170: 687a ldr r2, [r7, #4]
8005172: 683b ldr r3, [r7, #0]
8005174: 781b ldrb r3, [r3, #0]
8005176: 009b lsls r3, r3, #2
8005178: 441a add r2, r3
800517a: 897b ldrh r3, [r7, #10]
800517c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005180: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005184: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005188: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800518c: b29b uxth r3, r3
800518e: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8005190: 687a ldr r2, [r7, #4]
8005192: 683b ldr r3, [r7, #0]
8005194: 781b ldrb r3, [r3, #0]
8005196: 009b lsls r3, r3, #2
8005198: 4413 add r3, r2
800519a: 881b ldrh r3, [r3, #0]
800519c: b29b uxth r3, r3
800519e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80051a2: f023 0340 bic.w r3, r3, #64 @ 0x40
80051a6: 813b strh r3, [r7, #8]
80051a8: 687a ldr r2, [r7, #4]
80051aa: 683b ldr r3, [r7, #0]
80051ac: 781b ldrb r3, [r3, #0]
80051ae: 009b lsls r3, r3, #2
80051b0: 441a add r2, r3
80051b2: 893b ldrh r3, [r7, #8]
80051b4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80051b8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80051bc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80051c0: f043 0380 orr.w r3, r3, #128 @ 0x80
80051c4: b29b uxth r3, r3
80051c6: 8013 strh r3, [r2, #0]
80051c8: e192 b.n 80054f0 <USB_DeactivateEndpoint+0x3cc>
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80051ca: 687a ldr r2, [r7, #4]
80051cc: 683b ldr r3, [r7, #0]
80051ce: 781b ldrb r3, [r3, #0]
80051d0: 009b lsls r3, r3, #2
80051d2: 4413 add r3, r2
80051d4: 881b ldrh r3, [r3, #0]
80051d6: 827b strh r3, [r7, #18]
80051d8: 8a7b ldrh r3, [r7, #18]
80051da: f403 4380 and.w r3, r3, #16384 @ 0x4000
80051de: 2b00 cmp r3, #0
80051e0: d01b beq.n 800521a <USB_DeactivateEndpoint+0xf6>
80051e2: 687a ldr r2, [r7, #4]
80051e4: 683b ldr r3, [r7, #0]
80051e6: 781b ldrb r3, [r3, #0]
80051e8: 009b lsls r3, r3, #2
80051ea: 4413 add r3, r2
80051ec: 881b ldrh r3, [r3, #0]
80051ee: b29b uxth r3, r3
80051f0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80051f4: f023 0370 bic.w r3, r3, #112 @ 0x70
80051f8: 823b strh r3, [r7, #16]
80051fa: 687a ldr r2, [r7, #4]
80051fc: 683b ldr r3, [r7, #0]
80051fe: 781b ldrb r3, [r3, #0]
8005200: 009b lsls r3, r3, #2
8005202: 441a add r2, r3
8005204: 8a3b ldrh r3, [r7, #16]
8005206: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800520a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800520e: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8005212: f043 0380 orr.w r3, r3, #128 @ 0x80
8005216: b29b uxth r3, r3
8005218: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800521a: 687a ldr r2, [r7, #4]
800521c: 683b ldr r3, [r7, #0]
800521e: 781b ldrb r3, [r3, #0]
8005220: 009b lsls r3, r3, #2
8005222: 4413 add r3, r2
8005224: 881b ldrh r3, [r3, #0]
8005226: b29b uxth r3, r3
8005228: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800522c: f023 0370 bic.w r3, r3, #112 @ 0x70
8005230: 81fb strh r3, [r7, #14]
8005232: 687a ldr r2, [r7, #4]
8005234: 683b ldr r3, [r7, #0]
8005236: 781b ldrb r3, [r3, #0]
8005238: 009b lsls r3, r3, #2
800523a: 441a add r2, r3
800523c: 89fb ldrh r3, [r7, #14]
800523e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005242: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005246: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800524a: f043 0380 orr.w r3, r3, #128 @ 0x80
800524e: b29b uxth r3, r3
8005250: 8013 strh r3, [r2, #0]
8005252: e14d b.n 80054f0 <USB_DeactivateEndpoint+0x3cc>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->is_in == 0U)
8005254: 683b ldr r3, [r7, #0]
8005256: 785b ldrb r3, [r3, #1]
8005258: 2b00 cmp r3, #0
800525a: f040 80a5 bne.w 80053a8 <USB_DeactivateEndpoint+0x284>
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800525e: 687a ldr r2, [r7, #4]
8005260: 683b ldr r3, [r7, #0]
8005262: 781b ldrb r3, [r3, #0]
8005264: 009b lsls r3, r3, #2
8005266: 4413 add r3, r2
8005268: 881b ldrh r3, [r3, #0]
800526a: 843b strh r3, [r7, #32]
800526c: 8c3b ldrh r3, [r7, #32]
800526e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8005272: 2b00 cmp r3, #0
8005274: d01b beq.n 80052ae <USB_DeactivateEndpoint+0x18a>
8005276: 687a ldr r2, [r7, #4]
8005278: 683b ldr r3, [r7, #0]
800527a: 781b ldrb r3, [r3, #0]
800527c: 009b lsls r3, r3, #2
800527e: 4413 add r3, r2
8005280: 881b ldrh r3, [r3, #0]
8005282: b29b uxth r3, r3
8005284: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005288: f023 0370 bic.w r3, r3, #112 @ 0x70
800528c: 83fb strh r3, [r7, #30]
800528e: 687a ldr r2, [r7, #4]
8005290: 683b ldr r3, [r7, #0]
8005292: 781b ldrb r3, [r3, #0]
8005294: 009b lsls r3, r3, #2
8005296: 441a add r2, r3
8005298: 8bfb ldrh r3, [r7, #30]
800529a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800529e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80052a2: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80052a6: f043 0380 orr.w r3, r3, #128 @ 0x80
80052aa: b29b uxth r3, r3
80052ac: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80052ae: 687a ldr r2, [r7, #4]
80052b0: 683b ldr r3, [r7, #0]
80052b2: 781b ldrb r3, [r3, #0]
80052b4: 009b lsls r3, r3, #2
80052b6: 4413 add r3, r2
80052b8: 881b ldrh r3, [r3, #0]
80052ba: 83bb strh r3, [r7, #28]
80052bc: 8bbb ldrh r3, [r7, #28]
80052be: f003 0340 and.w r3, r3, #64 @ 0x40
80052c2: 2b00 cmp r3, #0
80052c4: d01b beq.n 80052fe <USB_DeactivateEndpoint+0x1da>
80052c6: 687a ldr r2, [r7, #4]
80052c8: 683b ldr r3, [r7, #0]
80052ca: 781b ldrb r3, [r3, #0]
80052cc: 009b lsls r3, r3, #2
80052ce: 4413 add r3, r2
80052d0: 881b ldrh r3, [r3, #0]
80052d2: b29b uxth r3, r3
80052d4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80052d8: f023 0370 bic.w r3, r3, #112 @ 0x70
80052dc: 837b strh r3, [r7, #26]
80052de: 687a ldr r2, [r7, #4]
80052e0: 683b ldr r3, [r7, #0]
80052e2: 781b ldrb r3, [r3, #0]
80052e4: 009b lsls r3, r3, #2
80052e6: 441a add r2, r3
80052e8: 8b7b ldrh r3, [r7, #26]
80052ea: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80052ee: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80052f2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80052f6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80052fa: b29b uxth r3, r3
80052fc: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
80052fe: 687a ldr r2, [r7, #4]
8005300: 683b ldr r3, [r7, #0]
8005302: 781b ldrb r3, [r3, #0]
8005304: 009b lsls r3, r3, #2
8005306: 4413 add r3, r2
8005308: 881b ldrh r3, [r3, #0]
800530a: b29b uxth r3, r3
800530c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005310: f023 0370 bic.w r3, r3, #112 @ 0x70
8005314: 833b strh r3, [r7, #24]
8005316: 687a ldr r2, [r7, #4]
8005318: 683b ldr r3, [r7, #0]
800531a: 781b ldrb r3, [r3, #0]
800531c: 009b lsls r3, r3, #2
800531e: 441a add r2, r3
8005320: 8b3b ldrh r3, [r7, #24]
8005322: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005326: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800532a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800532e: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8005332: b29b uxth r3, r3
8005334: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
8005336: 687a ldr r2, [r7, #4]
8005338: 683b ldr r3, [r7, #0]
800533a: 781b ldrb r3, [r3, #0]
800533c: 009b lsls r3, r3, #2
800533e: 4413 add r3, r2
8005340: 881b ldrh r3, [r3, #0]
8005342: b29b uxth r3, r3
8005344: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005348: f023 0370 bic.w r3, r3, #112 @ 0x70
800534c: 82fb strh r3, [r7, #22]
800534e: 687a ldr r2, [r7, #4]
8005350: 683b ldr r3, [r7, #0]
8005352: 781b ldrb r3, [r3, #0]
8005354: 009b lsls r3, r3, #2
8005356: 441a add r2, r3
8005358: 8afb ldrh r3, [r7, #22]
800535a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800535e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005362: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005366: f043 0380 orr.w r3, r3, #128 @ 0x80
800536a: b29b uxth r3, r3
800536c: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800536e: 687a ldr r2, [r7, #4]
8005370: 683b ldr r3, [r7, #0]
8005372: 781b ldrb r3, [r3, #0]
8005374: 009b lsls r3, r3, #2
8005376: 4413 add r3, r2
8005378: 881b ldrh r3, [r3, #0]
800537a: b29b uxth r3, r3
800537c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005380: f023 0340 bic.w r3, r3, #64 @ 0x40
8005384: 82bb strh r3, [r7, #20]
8005386: 687a ldr r2, [r7, #4]
8005388: 683b ldr r3, [r7, #0]
800538a: 781b ldrb r3, [r3, #0]
800538c: 009b lsls r3, r3, #2
800538e: 441a add r2, r3
8005390: 8abb ldrh r3, [r7, #20]
8005392: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005396: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800539a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800539e: f043 0380 orr.w r3, r3, #128 @ 0x80
80053a2: b29b uxth r3, r3
80053a4: 8013 strh r3, [r2, #0]
80053a6: e0a3 b.n 80054f0 <USB_DeactivateEndpoint+0x3cc>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80053a8: 687a ldr r2, [r7, #4]
80053aa: 683b ldr r3, [r7, #0]
80053ac: 781b ldrb r3, [r3, #0]
80053ae: 009b lsls r3, r3, #2
80053b0: 4413 add r3, r2
80053b2: 881b ldrh r3, [r3, #0]
80053b4: 85fb strh r3, [r7, #46] @ 0x2e
80053b6: 8dfb ldrh r3, [r7, #46] @ 0x2e
80053b8: f403 4380 and.w r3, r3, #16384 @ 0x4000
80053bc: 2b00 cmp r3, #0
80053be: d01b beq.n 80053f8 <USB_DeactivateEndpoint+0x2d4>
80053c0: 687a ldr r2, [r7, #4]
80053c2: 683b ldr r3, [r7, #0]
80053c4: 781b ldrb r3, [r3, #0]
80053c6: 009b lsls r3, r3, #2
80053c8: 4413 add r3, r2
80053ca: 881b ldrh r3, [r3, #0]
80053cc: b29b uxth r3, r3
80053ce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80053d2: f023 0370 bic.w r3, r3, #112 @ 0x70
80053d6: 85bb strh r3, [r7, #44] @ 0x2c
80053d8: 687a ldr r2, [r7, #4]
80053da: 683b ldr r3, [r7, #0]
80053dc: 781b ldrb r3, [r3, #0]
80053de: 009b lsls r3, r3, #2
80053e0: 441a add r2, r3
80053e2: 8dbb ldrh r3, [r7, #44] @ 0x2c
80053e4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80053e8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80053ec: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80053f0: f043 0380 orr.w r3, r3, #128 @ 0x80
80053f4: b29b uxth r3, r3
80053f6: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80053f8: 687a ldr r2, [r7, #4]
80053fa: 683b ldr r3, [r7, #0]
80053fc: 781b ldrb r3, [r3, #0]
80053fe: 009b lsls r3, r3, #2
8005400: 4413 add r3, r2
8005402: 881b ldrh r3, [r3, #0]
8005404: 857b strh r3, [r7, #42] @ 0x2a
8005406: 8d7b ldrh r3, [r7, #42] @ 0x2a
8005408: f003 0340 and.w r3, r3, #64 @ 0x40
800540c: 2b00 cmp r3, #0
800540e: d01b beq.n 8005448 <USB_DeactivateEndpoint+0x324>
8005410: 687a ldr r2, [r7, #4]
8005412: 683b ldr r3, [r7, #0]
8005414: 781b ldrb r3, [r3, #0]
8005416: 009b lsls r3, r3, #2
8005418: 4413 add r3, r2
800541a: 881b ldrh r3, [r3, #0]
800541c: b29b uxth r3, r3
800541e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005422: f023 0370 bic.w r3, r3, #112 @ 0x70
8005426: 853b strh r3, [r7, #40] @ 0x28
8005428: 687a ldr r2, [r7, #4]
800542a: 683b ldr r3, [r7, #0]
800542c: 781b ldrb r3, [r3, #0]
800542e: 009b lsls r3, r3, #2
8005430: 441a add r2, r3
8005432: 8d3b ldrh r3, [r7, #40] @ 0x28
8005434: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005438: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800543c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005440: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8005444: b29b uxth r3, r3
8005446: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
8005448: 687a ldr r2, [r7, #4]
800544a: 683b ldr r3, [r7, #0]
800544c: 781b ldrb r3, [r3, #0]
800544e: 009b lsls r3, r3, #2
8005450: 4413 add r3, r2
8005452: 881b ldrh r3, [r3, #0]
8005454: b29b uxth r3, r3
8005456: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800545a: f023 0370 bic.w r3, r3, #112 @ 0x70
800545e: 84fb strh r3, [r7, #38] @ 0x26
8005460: 687a ldr r2, [r7, #4]
8005462: 683b ldr r3, [r7, #0]
8005464: 781b ldrb r3, [r3, #0]
8005466: 009b lsls r3, r3, #2
8005468: 441a add r2, r3
800546a: 8cfb ldrh r3, [r7, #38] @ 0x26
800546c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005470: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005474: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8005478: f043 0380 orr.w r3, r3, #128 @ 0x80
800547c: b29b uxth r3, r3
800547e: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8005480: 687a ldr r2, [r7, #4]
8005482: 683b ldr r3, [r7, #0]
8005484: 781b ldrb r3, [r3, #0]
8005486: 009b lsls r3, r3, #2
8005488: 4413 add r3, r2
800548a: 881b ldrh r3, [r3, #0]
800548c: b29b uxth r3, r3
800548e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005492: f023 0340 bic.w r3, r3, #64 @ 0x40
8005496: 84bb strh r3, [r7, #36] @ 0x24
8005498: 687a ldr r2, [r7, #4]
800549a: 683b ldr r3, [r7, #0]
800549c: 781b ldrb r3, [r3, #0]
800549e: 009b lsls r3, r3, #2
80054a0: 441a add r2, r3
80054a2: 8cbb ldrh r3, [r7, #36] @ 0x24
80054a4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80054a8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80054ac: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80054b0: f043 0380 orr.w r3, r3, #128 @ 0x80
80054b4: b29b uxth r3, r3
80054b6: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80054b8: 687a ldr r2, [r7, #4]
80054ba: 683b ldr r3, [r7, #0]
80054bc: 781b ldrb r3, [r3, #0]
80054be: 009b lsls r3, r3, #2
80054c0: 4413 add r3, r2
80054c2: 881b ldrh r3, [r3, #0]
80054c4: b29b uxth r3, r3
80054c6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80054ca: f023 0370 bic.w r3, r3, #112 @ 0x70
80054ce: 847b strh r3, [r7, #34] @ 0x22
80054d0: 687a ldr r2, [r7, #4]
80054d2: 683b ldr r3, [r7, #0]
80054d4: 781b ldrb r3, [r3, #0]
80054d6: 009b lsls r3, r3, #2
80054d8: 441a add r2, r3
80054da: 8c7b ldrh r3, [r7, #34] @ 0x22
80054dc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80054e0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80054e4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80054e8: f043 0380 orr.w r3, r3, #128 @ 0x80
80054ec: b29b uxth r3, r3
80054ee: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
80054f0: 2300 movs r3, #0
}
80054f2: 4618 mov r0, r3
80054f4: 3734 adds r7, #52 @ 0x34
80054f6: 46bd mov sp, r7
80054f8: bc80 pop {r7}
80054fa: 4770 bx lr
080054fc <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
80054fc: b580 push {r7, lr}
80054fe: b0c2 sub sp, #264 @ 0x108
8005500: af00 add r7, sp, #0
8005502: f507 7384 add.w r3, r7, #264 @ 0x108
8005506: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800550a: 6018 str r0, [r3, #0]
800550c: f507 7384 add.w r3, r7, #264 @ 0x108
8005510: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005514: 6019 str r1, [r3, #0]
uint16_t pmabuffer;
uint16_t wEPVal;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
8005516: f507 7384 add.w r3, r7, #264 @ 0x108
800551a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800551e: 681b ldr r3, [r3, #0]
8005520: 785b ldrb r3, [r3, #1]
8005522: 2b01 cmp r3, #1
8005524: f040 86b7 bne.w 8006296 <USB_EPStartXfer+0xd9a>
{
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
8005528: f507 7384 add.w r3, r7, #264 @ 0x108
800552c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005530: 681b ldr r3, [r3, #0]
8005532: 699a ldr r2, [r3, #24]
8005534: f507 7384 add.w r3, r7, #264 @ 0x108
8005538: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800553c: 681b ldr r3, [r3, #0]
800553e: 691b ldr r3, [r3, #16]
8005540: 429a cmp r2, r3
8005542: d908 bls.n 8005556 <USB_EPStartXfer+0x5a>
{
len = ep->maxpacket;
8005544: f507 7384 add.w r3, r7, #264 @ 0x108
8005548: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800554c: 681b ldr r3, [r3, #0]
800554e: 691b ldr r3, [r3, #16]
8005550: f8c7 3104 str.w r3, [r7, #260] @ 0x104
8005554: e007 b.n 8005566 <USB_EPStartXfer+0x6a>
}
else
{
len = ep->xfer_len;
8005556: f507 7384 add.w r3, r7, #264 @ 0x108
800555a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800555e: 681b ldr r3, [r3, #0]
8005560: 699b ldr r3, [r3, #24]
8005562: f8c7 3104 str.w r3, [r7, #260] @ 0x104
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
8005566: f507 7384 add.w r3, r7, #264 @ 0x108
800556a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800556e: 681b ldr r3, [r3, #0]
8005570: 7b1b ldrb r3, [r3, #12]
8005572: 2b00 cmp r3, #0
8005574: d13a bne.n 80055ec <USB_EPStartXfer+0xf0>
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
8005576: f507 7384 add.w r3, r7, #264 @ 0x108
800557a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800557e: 681b ldr r3, [r3, #0]
8005580: 6959 ldr r1, [r3, #20]
8005582: f507 7384 add.w r3, r7, #264 @ 0x108
8005586: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800558a: 681b ldr r3, [r3, #0]
800558c: 88da ldrh r2, [r3, #6]
800558e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005592: b29b uxth r3, r3
8005594: f507 7084 add.w r0, r7, #264 @ 0x108
8005598: f5a0 7082 sub.w r0, r0, #260 @ 0x104
800559c: 6800 ldr r0, [r0, #0]
800559e: f001 fc9c bl 8006eda <USB_WritePMA>
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
80055a2: f507 7384 add.w r3, r7, #264 @ 0x108
80055a6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80055aa: 681b ldr r3, [r3, #0]
80055ac: 613b str r3, [r7, #16]
80055ae: f507 7384 add.w r3, r7, #264 @ 0x108
80055b2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80055b6: 681b ldr r3, [r3, #0]
80055b8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80055bc: b29b uxth r3, r3
80055be: 461a mov r2, r3
80055c0: 693b ldr r3, [r7, #16]
80055c2: 4413 add r3, r2
80055c4: 613b str r3, [r7, #16]
80055c6: f507 7384 add.w r3, r7, #264 @ 0x108
80055ca: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80055ce: 681b ldr r3, [r3, #0]
80055d0: 781b ldrb r3, [r3, #0]
80055d2: 011a lsls r2, r3, #4
80055d4: 693b ldr r3, [r7, #16]
80055d6: 4413 add r3, r2
80055d8: f203 4304 addw r3, r3, #1028 @ 0x404
80055dc: 60fb str r3, [r7, #12]
80055de: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80055e2: b29a uxth r2, r3
80055e4: 68fb ldr r3, [r7, #12]
80055e6: 801a strh r2, [r3, #0]
80055e8: f000 be1f b.w 800622a <USB_EPStartXfer+0xd2e>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
80055ec: f507 7384 add.w r3, r7, #264 @ 0x108
80055f0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80055f4: 681b ldr r3, [r3, #0]
80055f6: 78db ldrb r3, [r3, #3]
80055f8: 2b02 cmp r3, #2
80055fa: f040 8462 bne.w 8005ec2 <USB_EPStartXfer+0x9c6>
{
if (ep->xfer_len_db > ep->maxpacket)
80055fe: f507 7384 add.w r3, r7, #264 @ 0x108
8005602: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005606: 681b ldr r3, [r3, #0]
8005608: 6a1a ldr r2, [r3, #32]
800560a: f507 7384 add.w r3, r7, #264 @ 0x108
800560e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005612: 681b ldr r3, [r3, #0]
8005614: 691b ldr r3, [r3, #16]
8005616: 429a cmp r2, r3
8005618: f240 83df bls.w 8005dda <USB_EPStartXfer+0x8de>
{
/* enable double buffer */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
800561c: f507 7384 add.w r3, r7, #264 @ 0x108
8005620: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005624: 681a ldr r2, [r3, #0]
8005626: f507 7384 add.w r3, r7, #264 @ 0x108
800562a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800562e: 681b ldr r3, [r3, #0]
8005630: 781b ldrb r3, [r3, #0]
8005632: 009b lsls r3, r3, #2
8005634: 4413 add r3, r2
8005636: 881b ldrh r3, [r3, #0]
8005638: b29b uxth r3, r3
800563a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800563e: f023 0370 bic.w r3, r3, #112 @ 0x70
8005642: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
8005646: f507 7384 add.w r3, r7, #264 @ 0x108
800564a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800564e: 681a ldr r2, [r3, #0]
8005650: f507 7384 add.w r3, r7, #264 @ 0x108
8005654: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005658: 681b ldr r3, [r3, #0]
800565a: 781b ldrb r3, [r3, #0]
800565c: 009b lsls r3, r3, #2
800565e: 441a add r2, r3
8005660: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
8005664: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005668: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800566c: f443 4301 orr.w r3, r3, #33024 @ 0x8100
8005670: f043 0380 orr.w r3, r3, #128 @ 0x80
8005674: b29b uxth r3, r3
8005676: 8013 strh r3, [r2, #0]
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
8005678: f507 7384 add.w r3, r7, #264 @ 0x108
800567c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005680: 681b ldr r3, [r3, #0]
8005682: 6a1a ldr r2, [r3, #32]
8005684: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005688: 1ad2 subs r2, r2, r3
800568a: f507 7384 add.w r3, r7, #264 @ 0x108
800568e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005692: 681b ldr r3, [r3, #0]
8005694: 621a str r2, [r3, #32]
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8005696: f507 7384 add.w r3, r7, #264 @ 0x108
800569a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800569e: 681a ldr r2, [r3, #0]
80056a0: f507 7384 add.w r3, r7, #264 @ 0x108
80056a4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80056a8: 681b ldr r3, [r3, #0]
80056aa: 781b ldrb r3, [r3, #0]
80056ac: 009b lsls r3, r3, #2
80056ae: 4413 add r3, r2
80056b0: 881b ldrh r3, [r3, #0]
80056b2: b29b uxth r3, r3
80056b4: f003 0340 and.w r3, r3, #64 @ 0x40
80056b8: 2b00 cmp r3, #0
80056ba: f000 81c7 beq.w 8005a4c <USB_EPStartXfer+0x550>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
80056be: f507 7384 add.w r3, r7, #264 @ 0x108
80056c2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80056c6: 681b ldr r3, [r3, #0]
80056c8: 633b str r3, [r7, #48] @ 0x30
80056ca: f507 7384 add.w r3, r7, #264 @ 0x108
80056ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80056d2: 681b ldr r3, [r3, #0]
80056d4: 785b ldrb r3, [r3, #1]
80056d6: 2b00 cmp r3, #0
80056d8: d177 bne.n 80057ca <USB_EPStartXfer+0x2ce>
80056da: f507 7384 add.w r3, r7, #264 @ 0x108
80056de: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80056e2: 681b ldr r3, [r3, #0]
80056e4: 62bb str r3, [r7, #40] @ 0x28
80056e6: f507 7384 add.w r3, r7, #264 @ 0x108
80056ea: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80056ee: 681b ldr r3, [r3, #0]
80056f0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80056f4: b29b uxth r3, r3
80056f6: 461a mov r2, r3
80056f8: 6abb ldr r3, [r7, #40] @ 0x28
80056fa: 4413 add r3, r2
80056fc: 62bb str r3, [r7, #40] @ 0x28
80056fe: f507 7384 add.w r3, r7, #264 @ 0x108
8005702: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005706: 681b ldr r3, [r3, #0]
8005708: 781b ldrb r3, [r3, #0]
800570a: 011a lsls r2, r3, #4
800570c: 6abb ldr r3, [r7, #40] @ 0x28
800570e: 4413 add r3, r2
8005710: f203 430c addw r3, r3, #1036 @ 0x40c
8005714: 627b str r3, [r7, #36] @ 0x24
8005716: 6a7b ldr r3, [r7, #36] @ 0x24
8005718: 881b ldrh r3, [r3, #0]
800571a: b29b uxth r3, r3
800571c: f3c3 0309 ubfx r3, r3, #0, #10
8005720: b29a uxth r2, r3
8005722: 6a7b ldr r3, [r7, #36] @ 0x24
8005724: 801a strh r2, [r3, #0]
8005726: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800572a: 2b3e cmp r3, #62 @ 0x3e
800572c: d921 bls.n 8005772 <USB_EPStartXfer+0x276>
800572e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005732: 095b lsrs r3, r3, #5
8005734: f8c7 3100 str.w r3, [r7, #256] @ 0x100
8005738: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800573c: f003 031f and.w r3, r3, #31
8005740: 2b00 cmp r3, #0
8005742: d104 bne.n 800574e <USB_EPStartXfer+0x252>
8005744: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8005748: 3b01 subs r3, #1
800574a: f8c7 3100 str.w r3, [r7, #256] @ 0x100
800574e: 6a7b ldr r3, [r7, #36] @ 0x24
8005750: 881b ldrh r3, [r3, #0]
8005752: b29a uxth r2, r3
8005754: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
8005758: b29b uxth r3, r3
800575a: 029b lsls r3, r3, #10
800575c: b29b uxth r3, r3
800575e: 4313 orrs r3, r2
8005760: b29b uxth r3, r3
8005762: ea6f 4343 mvn.w r3, r3, lsl #17
8005766: ea6f 4353 mvn.w r3, r3, lsr #17
800576a: b29a uxth r2, r3
800576c: 6a7b ldr r3, [r7, #36] @ 0x24
800576e: 801a strh r2, [r3, #0]
8005770: e050 b.n 8005814 <USB_EPStartXfer+0x318>
8005772: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005776: 2b00 cmp r3, #0
8005778: d10a bne.n 8005790 <USB_EPStartXfer+0x294>
800577a: 6a7b ldr r3, [r7, #36] @ 0x24
800577c: 881b ldrh r3, [r3, #0]
800577e: b29b uxth r3, r3
8005780: ea6f 4343 mvn.w r3, r3, lsl #17
8005784: ea6f 4353 mvn.w r3, r3, lsr #17
8005788: b29a uxth r2, r3
800578a: 6a7b ldr r3, [r7, #36] @ 0x24
800578c: 801a strh r2, [r3, #0]
800578e: e041 b.n 8005814 <USB_EPStartXfer+0x318>
8005790: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005794: 085b lsrs r3, r3, #1
8005796: f8c7 3100 str.w r3, [r7, #256] @ 0x100
800579a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800579e: f003 0301 and.w r3, r3, #1
80057a2: 2b00 cmp r3, #0
80057a4: d004 beq.n 80057b0 <USB_EPStartXfer+0x2b4>
80057a6: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
80057aa: 3301 adds r3, #1
80057ac: f8c7 3100 str.w r3, [r7, #256] @ 0x100
80057b0: 6a7b ldr r3, [r7, #36] @ 0x24
80057b2: 881b ldrh r3, [r3, #0]
80057b4: b29a uxth r2, r3
80057b6: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
80057ba: b29b uxth r3, r3
80057bc: 029b lsls r3, r3, #10
80057be: b29b uxth r3, r3
80057c0: 4313 orrs r3, r2
80057c2: b29a uxth r2, r3
80057c4: 6a7b ldr r3, [r7, #36] @ 0x24
80057c6: 801a strh r2, [r3, #0]
80057c8: e024 b.n 8005814 <USB_EPStartXfer+0x318>
80057ca: f507 7384 add.w r3, r7, #264 @ 0x108
80057ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80057d2: 681b ldr r3, [r3, #0]
80057d4: 785b ldrb r3, [r3, #1]
80057d6: 2b01 cmp r3, #1
80057d8: d11c bne.n 8005814 <USB_EPStartXfer+0x318>
80057da: f507 7384 add.w r3, r7, #264 @ 0x108
80057de: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80057e2: 681b ldr r3, [r3, #0]
80057e4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80057e8: b29b uxth r3, r3
80057ea: 461a mov r2, r3
80057ec: 6b3b ldr r3, [r7, #48] @ 0x30
80057ee: 4413 add r3, r2
80057f0: 633b str r3, [r7, #48] @ 0x30
80057f2: f507 7384 add.w r3, r7, #264 @ 0x108
80057f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80057fa: 681b ldr r3, [r3, #0]
80057fc: 781b ldrb r3, [r3, #0]
80057fe: 011a lsls r2, r3, #4
8005800: 6b3b ldr r3, [r7, #48] @ 0x30
8005802: 4413 add r3, r2
8005804: f203 430c addw r3, r3, #1036 @ 0x40c
8005808: 62fb str r3, [r7, #44] @ 0x2c
800580a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800580e: b29a uxth r2, r3
8005810: 6afb ldr r3, [r7, #44] @ 0x2c
8005812: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8005814: f507 7384 add.w r3, r7, #264 @ 0x108
8005818: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800581c: 681b ldr r3, [r3, #0]
800581e: 895b ldrh r3, [r3, #10]
8005820: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8005824: f507 7384 add.w r3, r7, #264 @ 0x108
8005828: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800582c: 681b ldr r3, [r3, #0]
800582e: 6959 ldr r1, [r3, #20]
8005830: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005834: b29b uxth r3, r3
8005836: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800583a: f507 7084 add.w r0, r7, #264 @ 0x108
800583e: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8005842: 6800 ldr r0, [r0, #0]
8005844: f001 fb49 bl 8006eda <USB_WritePMA>
ep->xfer_buff += len;
8005848: f507 7384 add.w r3, r7, #264 @ 0x108
800584c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005850: 681b ldr r3, [r3, #0]
8005852: 695a ldr r2, [r3, #20]
8005854: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005858: 441a add r2, r3
800585a: f507 7384 add.w r3, r7, #264 @ 0x108
800585e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005862: 681b ldr r3, [r3, #0]
8005864: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8005866: f507 7384 add.w r3, r7, #264 @ 0x108
800586a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800586e: 681b ldr r3, [r3, #0]
8005870: 6a1a ldr r2, [r3, #32]
8005872: f507 7384 add.w r3, r7, #264 @ 0x108
8005876: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800587a: 681b ldr r3, [r3, #0]
800587c: 691b ldr r3, [r3, #16]
800587e: 429a cmp r2, r3
8005880: d90f bls.n 80058a2 <USB_EPStartXfer+0x3a6>
{
ep->xfer_len_db -= len;
8005882: f507 7384 add.w r3, r7, #264 @ 0x108
8005886: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800588a: 681b ldr r3, [r3, #0]
800588c: 6a1a ldr r2, [r3, #32]
800588e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005892: 1ad2 subs r2, r2, r3
8005894: f507 7384 add.w r3, r7, #264 @ 0x108
8005898: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800589c: 681b ldr r3, [r3, #0]
800589e: 621a str r2, [r3, #32]
80058a0: e00e b.n 80058c0 <USB_EPStartXfer+0x3c4>
}
else
{
len = ep->xfer_len_db;
80058a2: f507 7384 add.w r3, r7, #264 @ 0x108
80058a6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80058aa: 681b ldr r3, [r3, #0]
80058ac: 6a1b ldr r3, [r3, #32]
80058ae: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
80058b2: f507 7384 add.w r3, r7, #264 @ 0x108
80058b6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80058ba: 681b ldr r3, [r3, #0]
80058bc: 2200 movs r2, #0
80058be: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
80058c0: f507 7384 add.w r3, r7, #264 @ 0x108
80058c4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80058c8: 681b ldr r3, [r3, #0]
80058ca: 785b ldrb r3, [r3, #1]
80058cc: 2b00 cmp r3, #0
80058ce: d177 bne.n 80059c0 <USB_EPStartXfer+0x4c4>
80058d0: f507 7384 add.w r3, r7, #264 @ 0x108
80058d4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80058d8: 681b ldr r3, [r3, #0]
80058da: 61bb str r3, [r7, #24]
80058dc: f507 7384 add.w r3, r7, #264 @ 0x108
80058e0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80058e4: 681b ldr r3, [r3, #0]
80058e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80058ea: b29b uxth r3, r3
80058ec: 461a mov r2, r3
80058ee: 69bb ldr r3, [r7, #24]
80058f0: 4413 add r3, r2
80058f2: 61bb str r3, [r7, #24]
80058f4: f507 7384 add.w r3, r7, #264 @ 0x108
80058f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80058fc: 681b ldr r3, [r3, #0]
80058fe: 781b ldrb r3, [r3, #0]
8005900: 011a lsls r2, r3, #4
8005902: 69bb ldr r3, [r7, #24]
8005904: 4413 add r3, r2
8005906: f203 4304 addw r3, r3, #1028 @ 0x404
800590a: 617b str r3, [r7, #20]
800590c: 697b ldr r3, [r7, #20]
800590e: 881b ldrh r3, [r3, #0]
8005910: b29b uxth r3, r3
8005912: f3c3 0309 ubfx r3, r3, #0, #10
8005916: b29a uxth r2, r3
8005918: 697b ldr r3, [r7, #20]
800591a: 801a strh r2, [r3, #0]
800591c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005920: 2b3e cmp r3, #62 @ 0x3e
8005922: d921 bls.n 8005968 <USB_EPStartXfer+0x46c>
8005924: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005928: 095b lsrs r3, r3, #5
800592a: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
800592e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005932: f003 031f and.w r3, r3, #31
8005936: 2b00 cmp r3, #0
8005938: d104 bne.n 8005944 <USB_EPStartXfer+0x448>
800593a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
800593e: 3b01 subs r3, #1
8005940: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8005944: 697b ldr r3, [r7, #20]
8005946: 881b ldrh r3, [r3, #0]
8005948: b29a uxth r2, r3
800594a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
800594e: b29b uxth r3, r3
8005950: 029b lsls r3, r3, #10
8005952: b29b uxth r3, r3
8005954: 4313 orrs r3, r2
8005956: b29b uxth r3, r3
8005958: ea6f 4343 mvn.w r3, r3, lsl #17
800595c: ea6f 4353 mvn.w r3, r3, lsr #17
8005960: b29a uxth r2, r3
8005962: 697b ldr r3, [r7, #20]
8005964: 801a strh r2, [r3, #0]
8005966: e056 b.n 8005a16 <USB_EPStartXfer+0x51a>
8005968: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800596c: 2b00 cmp r3, #0
800596e: d10a bne.n 8005986 <USB_EPStartXfer+0x48a>
8005970: 697b ldr r3, [r7, #20]
8005972: 881b ldrh r3, [r3, #0]
8005974: b29b uxth r3, r3
8005976: ea6f 4343 mvn.w r3, r3, lsl #17
800597a: ea6f 4353 mvn.w r3, r3, lsr #17
800597e: b29a uxth r2, r3
8005980: 697b ldr r3, [r7, #20]
8005982: 801a strh r2, [r3, #0]
8005984: e047 b.n 8005a16 <USB_EPStartXfer+0x51a>
8005986: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800598a: 085b lsrs r3, r3, #1
800598c: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
8005990: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005994: f003 0301 and.w r3, r3, #1
8005998: 2b00 cmp r3, #0
800599a: d004 beq.n 80059a6 <USB_EPStartXfer+0x4aa>
800599c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
80059a0: 3301 adds r3, #1
80059a2: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
80059a6: 697b ldr r3, [r7, #20]
80059a8: 881b ldrh r3, [r3, #0]
80059aa: b29a uxth r2, r3
80059ac: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
80059b0: b29b uxth r3, r3
80059b2: 029b lsls r3, r3, #10
80059b4: b29b uxth r3, r3
80059b6: 4313 orrs r3, r2
80059b8: b29a uxth r2, r3
80059ba: 697b ldr r3, [r7, #20]
80059bc: 801a strh r2, [r3, #0]
80059be: e02a b.n 8005a16 <USB_EPStartXfer+0x51a>
80059c0: f507 7384 add.w r3, r7, #264 @ 0x108
80059c4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80059c8: 681b ldr r3, [r3, #0]
80059ca: 785b ldrb r3, [r3, #1]
80059cc: 2b01 cmp r3, #1
80059ce: d122 bne.n 8005a16 <USB_EPStartXfer+0x51a>
80059d0: f507 7384 add.w r3, r7, #264 @ 0x108
80059d4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80059d8: 681b ldr r3, [r3, #0]
80059da: 623b str r3, [r7, #32]
80059dc: f507 7384 add.w r3, r7, #264 @ 0x108
80059e0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80059e4: 681b ldr r3, [r3, #0]
80059e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80059ea: b29b uxth r3, r3
80059ec: 461a mov r2, r3
80059ee: 6a3b ldr r3, [r7, #32]
80059f0: 4413 add r3, r2
80059f2: 623b str r3, [r7, #32]
80059f4: f507 7384 add.w r3, r7, #264 @ 0x108
80059f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80059fc: 681b ldr r3, [r3, #0]
80059fe: 781b ldrb r3, [r3, #0]
8005a00: 011a lsls r2, r3, #4
8005a02: 6a3b ldr r3, [r7, #32]
8005a04: 4413 add r3, r2
8005a06: f203 4304 addw r3, r3, #1028 @ 0x404
8005a0a: 61fb str r3, [r7, #28]
8005a0c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005a10: b29a uxth r2, r3
8005a12: 69fb ldr r3, [r7, #28]
8005a14: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8005a16: f507 7384 add.w r3, r7, #264 @ 0x108
8005a1a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005a1e: 681b ldr r3, [r3, #0]
8005a20: 891b ldrh r3, [r3, #8]
8005a22: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8005a26: f507 7384 add.w r3, r7, #264 @ 0x108
8005a2a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005a2e: 681b ldr r3, [r3, #0]
8005a30: 6959 ldr r1, [r3, #20]
8005a32: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005a36: b29b uxth r3, r3
8005a38: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8005a3c: f507 7084 add.w r0, r7, #264 @ 0x108
8005a40: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8005a44: 6800 ldr r0, [r0, #0]
8005a46: f001 fa48 bl 8006eda <USB_WritePMA>
8005a4a: e3ee b.n 800622a <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8005a4c: f507 7384 add.w r3, r7, #264 @ 0x108
8005a50: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005a54: 681b ldr r3, [r3, #0]
8005a56: 785b ldrb r3, [r3, #1]
8005a58: 2b00 cmp r3, #0
8005a5a: d177 bne.n 8005b4c <USB_EPStartXfer+0x650>
8005a5c: f507 7384 add.w r3, r7, #264 @ 0x108
8005a60: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005a64: 681b ldr r3, [r3, #0]
8005a66: 64bb str r3, [r7, #72] @ 0x48
8005a68: f507 7384 add.w r3, r7, #264 @ 0x108
8005a6c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005a70: 681b ldr r3, [r3, #0]
8005a72: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005a76: b29b uxth r3, r3
8005a78: 461a mov r2, r3
8005a7a: 6cbb ldr r3, [r7, #72] @ 0x48
8005a7c: 4413 add r3, r2
8005a7e: 64bb str r3, [r7, #72] @ 0x48
8005a80: f507 7384 add.w r3, r7, #264 @ 0x108
8005a84: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005a88: 681b ldr r3, [r3, #0]
8005a8a: 781b ldrb r3, [r3, #0]
8005a8c: 011a lsls r2, r3, #4
8005a8e: 6cbb ldr r3, [r7, #72] @ 0x48
8005a90: 4413 add r3, r2
8005a92: f203 4304 addw r3, r3, #1028 @ 0x404
8005a96: 647b str r3, [r7, #68] @ 0x44
8005a98: 6c7b ldr r3, [r7, #68] @ 0x44
8005a9a: 881b ldrh r3, [r3, #0]
8005a9c: b29b uxth r3, r3
8005a9e: f3c3 0309 ubfx r3, r3, #0, #10
8005aa2: b29a uxth r2, r3
8005aa4: 6c7b ldr r3, [r7, #68] @ 0x44
8005aa6: 801a strh r2, [r3, #0]
8005aa8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005aac: 2b3e cmp r3, #62 @ 0x3e
8005aae: d921 bls.n 8005af4 <USB_EPStartXfer+0x5f8>
8005ab0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005ab4: 095b lsrs r3, r3, #5
8005ab6: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8005aba: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005abe: f003 031f and.w r3, r3, #31
8005ac2: 2b00 cmp r3, #0
8005ac4: d104 bne.n 8005ad0 <USB_EPStartXfer+0x5d4>
8005ac6: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8005aca: 3b01 subs r3, #1
8005acc: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8005ad0: 6c7b ldr r3, [r7, #68] @ 0x44
8005ad2: 881b ldrh r3, [r3, #0]
8005ad4: b29a uxth r2, r3
8005ad6: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8005ada: b29b uxth r3, r3
8005adc: 029b lsls r3, r3, #10
8005ade: b29b uxth r3, r3
8005ae0: 4313 orrs r3, r2
8005ae2: b29b uxth r3, r3
8005ae4: ea6f 4343 mvn.w r3, r3, lsl #17
8005ae8: ea6f 4353 mvn.w r3, r3, lsr #17
8005aec: b29a uxth r2, r3
8005aee: 6c7b ldr r3, [r7, #68] @ 0x44
8005af0: 801a strh r2, [r3, #0]
8005af2: e056 b.n 8005ba2 <USB_EPStartXfer+0x6a6>
8005af4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005af8: 2b00 cmp r3, #0
8005afa: d10a bne.n 8005b12 <USB_EPStartXfer+0x616>
8005afc: 6c7b ldr r3, [r7, #68] @ 0x44
8005afe: 881b ldrh r3, [r3, #0]
8005b00: b29b uxth r3, r3
8005b02: ea6f 4343 mvn.w r3, r3, lsl #17
8005b06: ea6f 4353 mvn.w r3, r3, lsr #17
8005b0a: b29a uxth r2, r3
8005b0c: 6c7b ldr r3, [r7, #68] @ 0x44
8005b0e: 801a strh r2, [r3, #0]
8005b10: e047 b.n 8005ba2 <USB_EPStartXfer+0x6a6>
8005b12: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005b16: 085b lsrs r3, r3, #1
8005b18: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8005b1c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005b20: f003 0301 and.w r3, r3, #1
8005b24: 2b00 cmp r3, #0
8005b26: d004 beq.n 8005b32 <USB_EPStartXfer+0x636>
8005b28: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8005b2c: 3301 adds r3, #1
8005b2e: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
8005b32: 6c7b ldr r3, [r7, #68] @ 0x44
8005b34: 881b ldrh r3, [r3, #0]
8005b36: b29a uxth r2, r3
8005b38: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8005b3c: b29b uxth r3, r3
8005b3e: 029b lsls r3, r3, #10
8005b40: b29b uxth r3, r3
8005b42: 4313 orrs r3, r2
8005b44: b29a uxth r2, r3
8005b46: 6c7b ldr r3, [r7, #68] @ 0x44
8005b48: 801a strh r2, [r3, #0]
8005b4a: e02a b.n 8005ba2 <USB_EPStartXfer+0x6a6>
8005b4c: f507 7384 add.w r3, r7, #264 @ 0x108
8005b50: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005b54: 681b ldr r3, [r3, #0]
8005b56: 785b ldrb r3, [r3, #1]
8005b58: 2b01 cmp r3, #1
8005b5a: d122 bne.n 8005ba2 <USB_EPStartXfer+0x6a6>
8005b5c: f507 7384 add.w r3, r7, #264 @ 0x108
8005b60: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005b64: 681b ldr r3, [r3, #0]
8005b66: 653b str r3, [r7, #80] @ 0x50
8005b68: f507 7384 add.w r3, r7, #264 @ 0x108
8005b6c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005b70: 681b ldr r3, [r3, #0]
8005b72: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005b76: b29b uxth r3, r3
8005b78: 461a mov r2, r3
8005b7a: 6d3b ldr r3, [r7, #80] @ 0x50
8005b7c: 4413 add r3, r2
8005b7e: 653b str r3, [r7, #80] @ 0x50
8005b80: f507 7384 add.w r3, r7, #264 @ 0x108
8005b84: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005b88: 681b ldr r3, [r3, #0]
8005b8a: 781b ldrb r3, [r3, #0]
8005b8c: 011a lsls r2, r3, #4
8005b8e: 6d3b ldr r3, [r7, #80] @ 0x50
8005b90: 4413 add r3, r2
8005b92: f203 4304 addw r3, r3, #1028 @ 0x404
8005b96: 64fb str r3, [r7, #76] @ 0x4c
8005b98: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005b9c: b29a uxth r2, r3
8005b9e: 6cfb ldr r3, [r7, #76] @ 0x4c
8005ba0: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8005ba2: f507 7384 add.w r3, r7, #264 @ 0x108
8005ba6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005baa: 681b ldr r3, [r3, #0]
8005bac: 891b ldrh r3, [r3, #8]
8005bae: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8005bb2: f507 7384 add.w r3, r7, #264 @ 0x108
8005bb6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005bba: 681b ldr r3, [r3, #0]
8005bbc: 6959 ldr r1, [r3, #20]
8005bbe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005bc2: b29b uxth r3, r3
8005bc4: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8005bc8: f507 7084 add.w r0, r7, #264 @ 0x108
8005bcc: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8005bd0: 6800 ldr r0, [r0, #0]
8005bd2: f001 f982 bl 8006eda <USB_WritePMA>
ep->xfer_buff += len;
8005bd6: f507 7384 add.w r3, r7, #264 @ 0x108
8005bda: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005bde: 681b ldr r3, [r3, #0]
8005be0: 695a ldr r2, [r3, #20]
8005be2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005be6: 441a add r2, r3
8005be8: f507 7384 add.w r3, r7, #264 @ 0x108
8005bec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005bf0: 681b ldr r3, [r3, #0]
8005bf2: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
8005bf4: f507 7384 add.w r3, r7, #264 @ 0x108
8005bf8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005bfc: 681b ldr r3, [r3, #0]
8005bfe: 6a1a ldr r2, [r3, #32]
8005c00: f507 7384 add.w r3, r7, #264 @ 0x108
8005c04: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c08: 681b ldr r3, [r3, #0]
8005c0a: 691b ldr r3, [r3, #16]
8005c0c: 429a cmp r2, r3
8005c0e: d90f bls.n 8005c30 <USB_EPStartXfer+0x734>
{
ep->xfer_len_db -= len;
8005c10: f507 7384 add.w r3, r7, #264 @ 0x108
8005c14: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c18: 681b ldr r3, [r3, #0]
8005c1a: 6a1a ldr r2, [r3, #32]
8005c1c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005c20: 1ad2 subs r2, r2, r3
8005c22: f507 7384 add.w r3, r7, #264 @ 0x108
8005c26: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c2a: 681b ldr r3, [r3, #0]
8005c2c: 621a str r2, [r3, #32]
8005c2e: e00e b.n 8005c4e <USB_EPStartXfer+0x752>
}
else
{
len = ep->xfer_len_db;
8005c30: f507 7384 add.w r3, r7, #264 @ 0x108
8005c34: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c38: 681b ldr r3, [r3, #0]
8005c3a: 6a1b ldr r3, [r3, #32]
8005c3c: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len_db = 0U;
8005c40: f507 7384 add.w r3, r7, #264 @ 0x108
8005c44: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c48: 681b ldr r3, [r3, #0]
8005c4a: 2200 movs r2, #0
8005c4c: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8005c4e: f507 7384 add.w r3, r7, #264 @ 0x108
8005c52: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005c56: 681b ldr r3, [r3, #0]
8005c58: 643b str r3, [r7, #64] @ 0x40
8005c5a: f507 7384 add.w r3, r7, #264 @ 0x108
8005c5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c62: 681b ldr r3, [r3, #0]
8005c64: 785b ldrb r3, [r3, #1]
8005c66: 2b00 cmp r3, #0
8005c68: d177 bne.n 8005d5a <USB_EPStartXfer+0x85e>
8005c6a: f507 7384 add.w r3, r7, #264 @ 0x108
8005c6e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005c72: 681b ldr r3, [r3, #0]
8005c74: 63bb str r3, [r7, #56] @ 0x38
8005c76: f507 7384 add.w r3, r7, #264 @ 0x108
8005c7a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005c7e: 681b ldr r3, [r3, #0]
8005c80: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005c84: b29b uxth r3, r3
8005c86: 461a mov r2, r3
8005c88: 6bbb ldr r3, [r7, #56] @ 0x38
8005c8a: 4413 add r3, r2
8005c8c: 63bb str r3, [r7, #56] @ 0x38
8005c8e: f507 7384 add.w r3, r7, #264 @ 0x108
8005c92: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005c96: 681b ldr r3, [r3, #0]
8005c98: 781b ldrb r3, [r3, #0]
8005c9a: 011a lsls r2, r3, #4
8005c9c: 6bbb ldr r3, [r7, #56] @ 0x38
8005c9e: 4413 add r3, r2
8005ca0: f203 430c addw r3, r3, #1036 @ 0x40c
8005ca4: 637b str r3, [r7, #52] @ 0x34
8005ca6: 6b7b ldr r3, [r7, #52] @ 0x34
8005ca8: 881b ldrh r3, [r3, #0]
8005caa: b29b uxth r3, r3
8005cac: f3c3 0309 ubfx r3, r3, #0, #10
8005cb0: b29a uxth r2, r3
8005cb2: 6b7b ldr r3, [r7, #52] @ 0x34
8005cb4: 801a strh r2, [r3, #0]
8005cb6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005cba: 2b3e cmp r3, #62 @ 0x3e
8005cbc: d921 bls.n 8005d02 <USB_EPStartXfer+0x806>
8005cbe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005cc2: 095b lsrs r3, r3, #5
8005cc4: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8005cc8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005ccc: f003 031f and.w r3, r3, #31
8005cd0: 2b00 cmp r3, #0
8005cd2: d104 bne.n 8005cde <USB_EPStartXfer+0x7e2>
8005cd4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005cd8: 3b01 subs r3, #1
8005cda: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8005cde: 6b7b ldr r3, [r7, #52] @ 0x34
8005ce0: 881b ldrh r3, [r3, #0]
8005ce2: b29a uxth r2, r3
8005ce4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005ce8: b29b uxth r3, r3
8005cea: 029b lsls r3, r3, #10
8005cec: b29b uxth r3, r3
8005cee: 4313 orrs r3, r2
8005cf0: b29b uxth r3, r3
8005cf2: ea6f 4343 mvn.w r3, r3, lsl #17
8005cf6: ea6f 4353 mvn.w r3, r3, lsr #17
8005cfa: b29a uxth r2, r3
8005cfc: 6b7b ldr r3, [r7, #52] @ 0x34
8005cfe: 801a strh r2, [r3, #0]
8005d00: e050 b.n 8005da4 <USB_EPStartXfer+0x8a8>
8005d02: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005d06: 2b00 cmp r3, #0
8005d08: d10a bne.n 8005d20 <USB_EPStartXfer+0x824>
8005d0a: 6b7b ldr r3, [r7, #52] @ 0x34
8005d0c: 881b ldrh r3, [r3, #0]
8005d0e: b29b uxth r3, r3
8005d10: ea6f 4343 mvn.w r3, r3, lsl #17
8005d14: ea6f 4353 mvn.w r3, r3, lsr #17
8005d18: b29a uxth r2, r3
8005d1a: 6b7b ldr r3, [r7, #52] @ 0x34
8005d1c: 801a strh r2, [r3, #0]
8005d1e: e041 b.n 8005da4 <USB_EPStartXfer+0x8a8>
8005d20: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005d24: 085b lsrs r3, r3, #1
8005d26: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8005d2a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005d2e: f003 0301 and.w r3, r3, #1
8005d32: 2b00 cmp r3, #0
8005d34: d004 beq.n 8005d40 <USB_EPStartXfer+0x844>
8005d36: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d3a: 3301 adds r3, #1
8005d3c: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
8005d40: 6b7b ldr r3, [r7, #52] @ 0x34
8005d42: 881b ldrh r3, [r3, #0]
8005d44: b29a uxth r2, r3
8005d46: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d4a: b29b uxth r3, r3
8005d4c: 029b lsls r3, r3, #10
8005d4e: b29b uxth r3, r3
8005d50: 4313 orrs r3, r2
8005d52: b29a uxth r2, r3
8005d54: 6b7b ldr r3, [r7, #52] @ 0x34
8005d56: 801a strh r2, [r3, #0]
8005d58: e024 b.n 8005da4 <USB_EPStartXfer+0x8a8>
8005d5a: f507 7384 add.w r3, r7, #264 @ 0x108
8005d5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005d62: 681b ldr r3, [r3, #0]
8005d64: 785b ldrb r3, [r3, #1]
8005d66: 2b01 cmp r3, #1
8005d68: d11c bne.n 8005da4 <USB_EPStartXfer+0x8a8>
8005d6a: f507 7384 add.w r3, r7, #264 @ 0x108
8005d6e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005d72: 681b ldr r3, [r3, #0]
8005d74: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005d78: b29b uxth r3, r3
8005d7a: 461a mov r2, r3
8005d7c: 6c3b ldr r3, [r7, #64] @ 0x40
8005d7e: 4413 add r3, r2
8005d80: 643b str r3, [r7, #64] @ 0x40
8005d82: f507 7384 add.w r3, r7, #264 @ 0x108
8005d86: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005d8a: 681b ldr r3, [r3, #0]
8005d8c: 781b ldrb r3, [r3, #0]
8005d8e: 011a lsls r2, r3, #4
8005d90: 6c3b ldr r3, [r7, #64] @ 0x40
8005d92: 4413 add r3, r2
8005d94: f203 430c addw r3, r3, #1036 @ 0x40c
8005d98: 63fb str r3, [r7, #60] @ 0x3c
8005d9a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005d9e: b29a uxth r2, r3
8005da0: 6bfb ldr r3, [r7, #60] @ 0x3c
8005da2: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
8005da4: f507 7384 add.w r3, r7, #264 @ 0x108
8005da8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005dac: 681b ldr r3, [r3, #0]
8005dae: 895b ldrh r3, [r3, #10]
8005db0: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8005db4: f507 7384 add.w r3, r7, #264 @ 0x108
8005db8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005dbc: 681b ldr r3, [r3, #0]
8005dbe: 6959 ldr r1, [r3, #20]
8005dc0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005dc4: b29b uxth r3, r3
8005dc6: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8005dca: f507 7084 add.w r0, r7, #264 @ 0x108
8005dce: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8005dd2: 6800 ldr r0, [r0, #0]
8005dd4: f001 f881 bl 8006eda <USB_WritePMA>
8005dd8: e227 b.n 800622a <USB_EPStartXfer+0xd2e>
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
8005dda: f507 7384 add.w r3, r7, #264 @ 0x108
8005dde: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005de2: 681b ldr r3, [r3, #0]
8005de4: 6a1b ldr r3, [r3, #32]
8005de6: f8c7 3104 str.w r3, [r7, #260] @ 0x104
/* disable double buffer mode for Bulk endpoint */
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
8005dea: f507 7384 add.w r3, r7, #264 @ 0x108
8005dee: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005df2: 681a ldr r2, [r3, #0]
8005df4: f507 7384 add.w r3, r7, #264 @ 0x108
8005df8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005dfc: 681b ldr r3, [r3, #0]
8005dfe: 781b ldrb r3, [r3, #0]
8005e00: 009b lsls r3, r3, #2
8005e02: 4413 add r3, r2
8005e04: 881b ldrh r3, [r3, #0]
8005e06: b29b uxth r3, r3
8005e08: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
8005e0c: f023 0370 bic.w r3, r3, #112 @ 0x70
8005e10: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
8005e14: f507 7384 add.w r3, r7, #264 @ 0x108
8005e18: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005e1c: 681a ldr r2, [r3, #0]
8005e1e: f507 7384 add.w r3, r7, #264 @ 0x108
8005e22: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005e26: 681b ldr r3, [r3, #0]
8005e28: 781b ldrb r3, [r3, #0]
8005e2a: 009b lsls r3, r3, #2
8005e2c: 441a add r2, r3
8005e2e: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
8005e32: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8005e36: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8005e3a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8005e3e: f043 0380 orr.w r3, r3, #128 @ 0x80
8005e42: b29b uxth r3, r3
8005e44: 8013 strh r3, [r2, #0]
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
8005e46: f507 7384 add.w r3, r7, #264 @ 0x108
8005e4a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005e4e: 681b ldr r3, [r3, #0]
8005e50: 65fb str r3, [r7, #92] @ 0x5c
8005e52: f507 7384 add.w r3, r7, #264 @ 0x108
8005e56: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005e5a: 681b ldr r3, [r3, #0]
8005e5c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005e60: b29b uxth r3, r3
8005e62: 461a mov r2, r3
8005e64: 6dfb ldr r3, [r7, #92] @ 0x5c
8005e66: 4413 add r3, r2
8005e68: 65fb str r3, [r7, #92] @ 0x5c
8005e6a: f507 7384 add.w r3, r7, #264 @ 0x108
8005e6e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005e72: 681b ldr r3, [r3, #0]
8005e74: 781b ldrb r3, [r3, #0]
8005e76: 011a lsls r2, r3, #4
8005e78: 6dfb ldr r3, [r7, #92] @ 0x5c
8005e7a: 4413 add r3, r2
8005e7c: f203 4304 addw r3, r3, #1028 @ 0x404
8005e80: 65bb str r3, [r7, #88] @ 0x58
8005e82: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005e86: b29a uxth r2, r3
8005e88: 6dbb ldr r3, [r7, #88] @ 0x58
8005e8a: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
8005e8c: f507 7384 add.w r3, r7, #264 @ 0x108
8005e90: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005e94: 681b ldr r3, [r3, #0]
8005e96: 891b ldrh r3, [r3, #8]
8005e98: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8005e9c: f507 7384 add.w r3, r7, #264 @ 0x108
8005ea0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005ea4: 681b ldr r3, [r3, #0]
8005ea6: 6959 ldr r1, [r3, #20]
8005ea8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005eac: b29b uxth r3, r3
8005eae: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8005eb2: f507 7084 add.w r0, r7, #264 @ 0x108
8005eb6: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8005eba: 6800 ldr r0, [r0, #0]
8005ebc: f001 f80d bl 8006eda <USB_WritePMA>
8005ec0: e1b3 b.n 800622a <USB_EPStartXfer+0xd2e>
}
}
else /* manage isochronous double buffer IN mode */
{
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
8005ec2: f507 7384 add.w r3, r7, #264 @ 0x108
8005ec6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005eca: 681b ldr r3, [r3, #0]
8005ecc: 6a1a ldr r2, [r3, #32]
8005ece: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005ed2: 1ad2 subs r2, r2, r3
8005ed4: f507 7384 add.w r3, r7, #264 @ 0x108
8005ed8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005edc: 681b ldr r3, [r3, #0]
8005ede: 621a str r2, [r3, #32]
/* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8005ee0: f507 7384 add.w r3, r7, #264 @ 0x108
8005ee4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005ee8: 681a ldr r2, [r3, #0]
8005eea: f507 7384 add.w r3, r7, #264 @ 0x108
8005eee: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005ef2: 681b ldr r3, [r3, #0]
8005ef4: 781b ldrb r3, [r3, #0]
8005ef6: 009b lsls r3, r3, #2
8005ef8: 4413 add r3, r2
8005efa: 881b ldrh r3, [r3, #0]
8005efc: b29b uxth r3, r3
8005efe: f003 0340 and.w r3, r3, #64 @ 0x40
8005f02: 2b00 cmp r3, #0
8005f04: f000 80c6 beq.w 8006094 <USB_EPStartXfer+0xb98>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
8005f08: f507 7384 add.w r3, r7, #264 @ 0x108
8005f0c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005f10: 681b ldr r3, [r3, #0]
8005f12: 673b str r3, [r7, #112] @ 0x70
8005f14: f507 7384 add.w r3, r7, #264 @ 0x108
8005f18: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005f1c: 681b ldr r3, [r3, #0]
8005f1e: 785b ldrb r3, [r3, #1]
8005f20: 2b00 cmp r3, #0
8005f22: d177 bne.n 8006014 <USB_EPStartXfer+0xb18>
8005f24: f507 7384 add.w r3, r7, #264 @ 0x108
8005f28: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005f2c: 681b ldr r3, [r3, #0]
8005f2e: 66bb str r3, [r7, #104] @ 0x68
8005f30: f507 7384 add.w r3, r7, #264 @ 0x108
8005f34: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8005f38: 681b ldr r3, [r3, #0]
8005f3a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8005f3e: b29b uxth r3, r3
8005f40: 461a mov r2, r3
8005f42: 6ebb ldr r3, [r7, #104] @ 0x68
8005f44: 4413 add r3, r2
8005f46: 66bb str r3, [r7, #104] @ 0x68
8005f48: f507 7384 add.w r3, r7, #264 @ 0x108
8005f4c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8005f50: 681b ldr r3, [r3, #0]
8005f52: 781b ldrb r3, [r3, #0]
8005f54: 011a lsls r2, r3, #4
8005f56: 6ebb ldr r3, [r7, #104] @ 0x68
8005f58: 4413 add r3, r2
8005f5a: f203 430c addw r3, r3, #1036 @ 0x40c
8005f5e: 667b str r3, [r7, #100] @ 0x64
8005f60: 6e7b ldr r3, [r7, #100] @ 0x64
8005f62: 881b ldrh r3, [r3, #0]
8005f64: b29b uxth r3, r3
8005f66: f3c3 0309 ubfx r3, r3, #0, #10
8005f6a: b29a uxth r2, r3
8005f6c: 6e7b ldr r3, [r7, #100] @ 0x64
8005f6e: 801a strh r2, [r3, #0]
8005f70: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005f74: 2b3e cmp r3, #62 @ 0x3e
8005f76: d921 bls.n 8005fbc <USB_EPStartXfer+0xac0>
8005f78: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005f7c: 095b lsrs r3, r3, #5
8005f7e: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8005f82: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005f86: f003 031f and.w r3, r3, #31
8005f8a: 2b00 cmp r3, #0
8005f8c: d104 bne.n 8005f98 <USB_EPStartXfer+0xa9c>
8005f8e: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8005f92: 3b01 subs r3, #1
8005f94: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8005f98: 6e7b ldr r3, [r7, #100] @ 0x64
8005f9a: 881b ldrh r3, [r3, #0]
8005f9c: b29a uxth r2, r3
8005f9e: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8005fa2: b29b uxth r3, r3
8005fa4: 029b lsls r3, r3, #10
8005fa6: b29b uxth r3, r3
8005fa8: 4313 orrs r3, r2
8005faa: b29b uxth r3, r3
8005fac: ea6f 4343 mvn.w r3, r3, lsl #17
8005fb0: ea6f 4353 mvn.w r3, r3, lsr #17
8005fb4: b29a uxth r2, r3
8005fb6: 6e7b ldr r3, [r7, #100] @ 0x64
8005fb8: 801a strh r2, [r3, #0]
8005fba: e050 b.n 800605e <USB_EPStartXfer+0xb62>
8005fbc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005fc0: 2b00 cmp r3, #0
8005fc2: d10a bne.n 8005fda <USB_EPStartXfer+0xade>
8005fc4: 6e7b ldr r3, [r7, #100] @ 0x64
8005fc6: 881b ldrh r3, [r3, #0]
8005fc8: b29b uxth r3, r3
8005fca: ea6f 4343 mvn.w r3, r3, lsl #17
8005fce: ea6f 4353 mvn.w r3, r3, lsr #17
8005fd2: b29a uxth r2, r3
8005fd4: 6e7b ldr r3, [r7, #100] @ 0x64
8005fd6: 801a strh r2, [r3, #0]
8005fd8: e041 b.n 800605e <USB_EPStartXfer+0xb62>
8005fda: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005fde: 085b lsrs r3, r3, #1
8005fe0: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8005fe4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8005fe8: f003 0301 and.w r3, r3, #1
8005fec: 2b00 cmp r3, #0
8005fee: d004 beq.n 8005ffa <USB_EPStartXfer+0xafe>
8005ff0: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8005ff4: 3301 adds r3, #1
8005ff6: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
8005ffa: 6e7b ldr r3, [r7, #100] @ 0x64
8005ffc: 881b ldrh r3, [r3, #0]
8005ffe: b29a uxth r2, r3
8006000: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
8006004: b29b uxth r3, r3
8006006: 029b lsls r3, r3, #10
8006008: b29b uxth r3, r3
800600a: 4313 orrs r3, r2
800600c: b29a uxth r2, r3
800600e: 6e7b ldr r3, [r7, #100] @ 0x64
8006010: 801a strh r2, [r3, #0]
8006012: e024 b.n 800605e <USB_EPStartXfer+0xb62>
8006014: f507 7384 add.w r3, r7, #264 @ 0x108
8006018: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800601c: 681b ldr r3, [r3, #0]
800601e: 785b ldrb r3, [r3, #1]
8006020: 2b01 cmp r3, #1
8006022: d11c bne.n 800605e <USB_EPStartXfer+0xb62>
8006024: f507 7384 add.w r3, r7, #264 @ 0x108
8006028: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800602c: 681b ldr r3, [r3, #0]
800602e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006032: b29b uxth r3, r3
8006034: 461a mov r2, r3
8006036: 6f3b ldr r3, [r7, #112] @ 0x70
8006038: 4413 add r3, r2
800603a: 673b str r3, [r7, #112] @ 0x70
800603c: f507 7384 add.w r3, r7, #264 @ 0x108
8006040: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006044: 681b ldr r3, [r3, #0]
8006046: 781b ldrb r3, [r3, #0]
8006048: 011a lsls r2, r3, #4
800604a: 6f3b ldr r3, [r7, #112] @ 0x70
800604c: 4413 add r3, r2
800604e: f203 430c addw r3, r3, #1036 @ 0x40c
8006052: 66fb str r3, [r7, #108] @ 0x6c
8006054: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006058: b29a uxth r2, r3
800605a: 6efb ldr r3, [r7, #108] @ 0x6c
800605c: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800605e: f507 7384 add.w r3, r7, #264 @ 0x108
8006062: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006066: 681b ldr r3, [r3, #0]
8006068: 895b ldrh r3, [r3, #10]
800606a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800606e: f507 7384 add.w r3, r7, #264 @ 0x108
8006072: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006076: 681b ldr r3, [r3, #0]
8006078: 6959 ldr r1, [r3, #20]
800607a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800607e: b29b uxth r3, r3
8006080: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
8006084: f507 7084 add.w r0, r7, #264 @ 0x108
8006088: f5a0 7082 sub.w r0, r0, #260 @ 0x104
800608c: 6800 ldr r0, [r0, #0]
800608e: f000 ff24 bl 8006eda <USB_WritePMA>
8006092: e0ca b.n 800622a <USB_EPStartXfer+0xd2e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8006094: f507 7384 add.w r3, r7, #264 @ 0x108
8006098: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800609c: 681b ldr r3, [r3, #0]
800609e: 785b ldrb r3, [r3, #1]
80060a0: 2b00 cmp r3, #0
80060a2: d177 bne.n 8006194 <USB_EPStartXfer+0xc98>
80060a4: f507 7384 add.w r3, r7, #264 @ 0x108
80060a8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80060ac: 681b ldr r3, [r3, #0]
80060ae: 67fb str r3, [r7, #124] @ 0x7c
80060b0: f507 7384 add.w r3, r7, #264 @ 0x108
80060b4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80060b8: 681b ldr r3, [r3, #0]
80060ba: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80060be: b29b uxth r3, r3
80060c0: 461a mov r2, r3
80060c2: 6ffb ldr r3, [r7, #124] @ 0x7c
80060c4: 4413 add r3, r2
80060c6: 67fb str r3, [r7, #124] @ 0x7c
80060c8: f507 7384 add.w r3, r7, #264 @ 0x108
80060cc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80060d0: 681b ldr r3, [r3, #0]
80060d2: 781b ldrb r3, [r3, #0]
80060d4: 011a lsls r2, r3, #4
80060d6: 6ffb ldr r3, [r7, #124] @ 0x7c
80060d8: 4413 add r3, r2
80060da: f203 4304 addw r3, r3, #1028 @ 0x404
80060de: 67bb str r3, [r7, #120] @ 0x78
80060e0: 6fbb ldr r3, [r7, #120] @ 0x78
80060e2: 881b ldrh r3, [r3, #0]
80060e4: b29b uxth r3, r3
80060e6: f3c3 0309 ubfx r3, r3, #0, #10
80060ea: b29a uxth r2, r3
80060ec: 6fbb ldr r3, [r7, #120] @ 0x78
80060ee: 801a strh r2, [r3, #0]
80060f0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80060f4: 2b3e cmp r3, #62 @ 0x3e
80060f6: d921 bls.n 800613c <USB_EPStartXfer+0xc40>
80060f8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80060fc: 095b lsrs r3, r3, #5
80060fe: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8006102: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006106: f003 031f and.w r3, r3, #31
800610a: 2b00 cmp r3, #0
800610c: d104 bne.n 8006118 <USB_EPStartXfer+0xc1c>
800610e: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8006112: 3b01 subs r3, #1
8006114: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8006118: 6fbb ldr r3, [r7, #120] @ 0x78
800611a: 881b ldrh r3, [r3, #0]
800611c: b29a uxth r2, r3
800611e: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8006122: b29b uxth r3, r3
8006124: 029b lsls r3, r3, #10
8006126: b29b uxth r3, r3
8006128: 4313 orrs r3, r2
800612a: b29b uxth r3, r3
800612c: ea6f 4343 mvn.w r3, r3, lsl #17
8006130: ea6f 4353 mvn.w r3, r3, lsr #17
8006134: b29a uxth r2, r3
8006136: 6fbb ldr r3, [r7, #120] @ 0x78
8006138: 801a strh r2, [r3, #0]
800613a: e05c b.n 80061f6 <USB_EPStartXfer+0xcfa>
800613c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006140: 2b00 cmp r3, #0
8006142: d10a bne.n 800615a <USB_EPStartXfer+0xc5e>
8006144: 6fbb ldr r3, [r7, #120] @ 0x78
8006146: 881b ldrh r3, [r3, #0]
8006148: b29b uxth r3, r3
800614a: ea6f 4343 mvn.w r3, r3, lsl #17
800614e: ea6f 4353 mvn.w r3, r3, lsr #17
8006152: b29a uxth r2, r3
8006154: 6fbb ldr r3, [r7, #120] @ 0x78
8006156: 801a strh r2, [r3, #0]
8006158: e04d b.n 80061f6 <USB_EPStartXfer+0xcfa>
800615a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800615e: 085b lsrs r3, r3, #1
8006160: f8c7 30ec str.w r3, [r7, #236] @ 0xec
8006164: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006168: f003 0301 and.w r3, r3, #1
800616c: 2b00 cmp r3, #0
800616e: d004 beq.n 800617a <USB_EPStartXfer+0xc7e>
8006170: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8006174: 3301 adds r3, #1
8006176: f8c7 30ec str.w r3, [r7, #236] @ 0xec
800617a: 6fbb ldr r3, [r7, #120] @ 0x78
800617c: 881b ldrh r3, [r3, #0]
800617e: b29a uxth r2, r3
8006180: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
8006184: b29b uxth r3, r3
8006186: 029b lsls r3, r3, #10
8006188: b29b uxth r3, r3
800618a: 4313 orrs r3, r2
800618c: b29a uxth r2, r3
800618e: 6fbb ldr r3, [r7, #120] @ 0x78
8006190: 801a strh r2, [r3, #0]
8006192: e030 b.n 80061f6 <USB_EPStartXfer+0xcfa>
8006194: f507 7384 add.w r3, r7, #264 @ 0x108
8006198: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800619c: 681b ldr r3, [r3, #0]
800619e: 785b ldrb r3, [r3, #1]
80061a0: 2b01 cmp r3, #1
80061a2: d128 bne.n 80061f6 <USB_EPStartXfer+0xcfa>
80061a4: f507 7384 add.w r3, r7, #264 @ 0x108
80061a8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80061ac: 681b ldr r3, [r3, #0]
80061ae: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80061b2: f507 7384 add.w r3, r7, #264 @ 0x108
80061b6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80061ba: 681b ldr r3, [r3, #0]
80061bc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80061c0: b29b uxth r3, r3
80061c2: 461a mov r2, r3
80061c4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
80061c8: 4413 add r3, r2
80061ca: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80061ce: f507 7384 add.w r3, r7, #264 @ 0x108
80061d2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80061d6: 681b ldr r3, [r3, #0]
80061d8: 781b ldrb r3, [r3, #0]
80061da: 011a lsls r2, r3, #4
80061dc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
80061e0: 4413 add r3, r2
80061e2: f203 4304 addw r3, r3, #1028 @ 0x404
80061e6: f8c7 3080 str.w r3, [r7, #128] @ 0x80
80061ea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80061ee: b29a uxth r2, r3
80061f0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80061f4: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
80061f6: f507 7384 add.w r3, r7, #264 @ 0x108
80061fa: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80061fe: 681b ldr r3, [r3, #0]
8006200: 891b ldrh r3, [r3, #8]
8006202: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8006206: f507 7384 add.w r3, r7, #264 @ 0x108
800620a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800620e: 681b ldr r3, [r3, #0]
8006210: 6959 ldr r1, [r3, #20]
8006212: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006216: b29b uxth r3, r3
8006218: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800621c: f507 7084 add.w r0, r7, #264 @ 0x108
8006220: f5a0 7082 sub.w r0, r0, #260 @ 0x104
8006224: 6800 ldr r0, [r0, #0]
8006226: f000 fe58 bl 8006eda <USB_WritePMA>
}
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
800622a: f507 7384 add.w r3, r7, #264 @ 0x108
800622e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006232: 681a ldr r2, [r3, #0]
8006234: f507 7384 add.w r3, r7, #264 @ 0x108
8006238: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800623c: 681b ldr r3, [r3, #0]
800623e: 781b ldrb r3, [r3, #0]
8006240: 009b lsls r3, r3, #2
8006242: 4413 add r3, r2
8006244: 881b ldrh r3, [r3, #0]
8006246: b29b uxth r3, r3
8006248: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800624c: f023 0340 bic.w r3, r3, #64 @ 0x40
8006250: 817b strh r3, [r7, #10]
8006252: 897b ldrh r3, [r7, #10]
8006254: f083 0310 eor.w r3, r3, #16
8006258: 817b strh r3, [r7, #10]
800625a: 897b ldrh r3, [r7, #10]
800625c: f083 0320 eor.w r3, r3, #32
8006260: 817b strh r3, [r7, #10]
8006262: f507 7384 add.w r3, r7, #264 @ 0x108
8006266: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800626a: 681a ldr r2, [r3, #0]
800626c: f507 7384 add.w r3, r7, #264 @ 0x108
8006270: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006274: 681b ldr r3, [r3, #0]
8006276: 781b ldrb r3, [r3, #0]
8006278: 009b lsls r3, r3, #2
800627a: 441a add r2, r3
800627c: 897b ldrh r3, [r7, #10]
800627e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006282: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006286: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800628a: f043 0380 orr.w r3, r3, #128 @ 0x80
800628e: b29b uxth r3, r3
8006290: 8013 strh r3, [r2, #0]
8006292: f000 bcde b.w 8006c52 <USB_EPStartXfer+0x1756>
}
else /* OUT endpoint */
{
if (ep->doublebuffer == 0U)
8006296: f507 7384 add.w r3, r7, #264 @ 0x108
800629a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800629e: 681b ldr r3, [r3, #0]
80062a0: 7b1b ldrb r3, [r3, #12]
80062a2: 2b00 cmp r3, #0
80062a4: f040 80bb bne.w 800641e <USB_EPStartXfer+0xf22>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
80062a8: f507 7384 add.w r3, r7, #264 @ 0x108
80062ac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80062b0: 681b ldr r3, [r3, #0]
80062b2: 699a ldr r2, [r3, #24]
80062b4: f507 7384 add.w r3, r7, #264 @ 0x108
80062b8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80062bc: 681b ldr r3, [r3, #0]
80062be: 691b ldr r3, [r3, #16]
80062c0: 429a cmp r2, r3
80062c2: d917 bls.n 80062f4 <USB_EPStartXfer+0xdf8>
{
len = ep->maxpacket;
80062c4: f507 7384 add.w r3, r7, #264 @ 0x108
80062c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80062cc: 681b ldr r3, [r3, #0]
80062ce: 691b ldr r3, [r3, #16]
80062d0: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
80062d4: f507 7384 add.w r3, r7, #264 @ 0x108
80062d8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80062dc: 681b ldr r3, [r3, #0]
80062de: 699a ldr r2, [r3, #24]
80062e0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80062e4: 1ad2 subs r2, r2, r3
80062e6: f507 7384 add.w r3, r7, #264 @ 0x108
80062ea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80062ee: 681b ldr r3, [r3, #0]
80062f0: 619a str r2, [r3, #24]
80062f2: e00e b.n 8006312 <USB_EPStartXfer+0xe16>
}
else
{
len = ep->xfer_len;
80062f4: f507 7384 add.w r3, r7, #264 @ 0x108
80062f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80062fc: 681b ldr r3, [r3, #0]
80062fe: 699b ldr r3, [r3, #24]
8006300: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
8006304: f507 7384 add.w r3, r7, #264 @ 0x108
8006308: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800630c: 681b ldr r3, [r3, #0]
800630e: 2200 movs r2, #0
8006310: 619a str r2, [r3, #24]
}
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
8006312: f507 7384 add.w r3, r7, #264 @ 0x108
8006316: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800631a: 681b ldr r3, [r3, #0]
800631c: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8006320: f507 7384 add.w r3, r7, #264 @ 0x108
8006324: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006328: 681b ldr r3, [r3, #0]
800632a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800632e: b29b uxth r3, r3
8006330: 461a mov r2, r3
8006332: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8006336: 4413 add r3, r2
8006338: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800633c: f507 7384 add.w r3, r7, #264 @ 0x108
8006340: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006344: 681b ldr r3, [r3, #0]
8006346: 781b ldrb r3, [r3, #0]
8006348: 011a lsls r2, r3, #4
800634a: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800634e: 4413 add r3, r2
8006350: f203 430c addw r3, r3, #1036 @ 0x40c
8006354: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8006358: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800635c: 881b ldrh r3, [r3, #0]
800635e: b29b uxth r3, r3
8006360: f3c3 0309 ubfx r3, r3, #0, #10
8006364: b29a uxth r2, r3
8006366: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800636a: 801a strh r2, [r3, #0]
800636c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006370: 2b3e cmp r3, #62 @ 0x3e
8006372: d924 bls.n 80063be <USB_EPStartXfer+0xec2>
8006374: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006378: 095b lsrs r3, r3, #5
800637a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
800637e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006382: f003 031f and.w r3, r3, #31
8006386: 2b00 cmp r3, #0
8006388: d104 bne.n 8006394 <USB_EPStartXfer+0xe98>
800638a: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
800638e: 3b01 subs r3, #1
8006390: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8006394: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006398: 881b ldrh r3, [r3, #0]
800639a: b29a uxth r2, r3
800639c: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80063a0: b29b uxth r3, r3
80063a2: 029b lsls r3, r3, #10
80063a4: b29b uxth r3, r3
80063a6: 4313 orrs r3, r2
80063a8: b29b uxth r3, r3
80063aa: ea6f 4343 mvn.w r3, r3, lsl #17
80063ae: ea6f 4353 mvn.w r3, r3, lsr #17
80063b2: b29a uxth r2, r3
80063b4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80063b8: 801a strh r2, [r3, #0]
80063ba: f000 bc10 b.w 8006bde <USB_EPStartXfer+0x16e2>
80063be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80063c2: 2b00 cmp r3, #0
80063c4: d10c bne.n 80063e0 <USB_EPStartXfer+0xee4>
80063c6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80063ca: 881b ldrh r3, [r3, #0]
80063cc: b29b uxth r3, r3
80063ce: ea6f 4343 mvn.w r3, r3, lsl #17
80063d2: ea6f 4353 mvn.w r3, r3, lsr #17
80063d6: b29a uxth r2, r3
80063d8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80063dc: 801a strh r2, [r3, #0]
80063de: e3fe b.n 8006bde <USB_EPStartXfer+0x16e2>
80063e0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80063e4: 085b lsrs r3, r3, #1
80063e6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
80063ea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80063ee: f003 0301 and.w r3, r3, #1
80063f2: 2b00 cmp r3, #0
80063f4: d004 beq.n 8006400 <USB_EPStartXfer+0xf04>
80063f6: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
80063fa: 3301 adds r3, #1
80063fc: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8006400: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006404: 881b ldrh r3, [r3, #0]
8006406: b29a uxth r2, r3
8006408: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
800640c: b29b uxth r3, r3
800640e: 029b lsls r3, r3, #10
8006410: b29b uxth r3, r3
8006412: 4313 orrs r3, r2
8006414: b29a uxth r2, r3
8006416: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800641a: 801a strh r2, [r3, #0]
800641c: e3df b.n 8006bde <USB_EPStartXfer+0x16e2>
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
800641e: f507 7384 add.w r3, r7, #264 @ 0x108
8006422: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006426: 681b ldr r3, [r3, #0]
8006428: 78db ldrb r3, [r3, #3]
800642a: 2b02 cmp r3, #2
800642c: f040 8218 bne.w 8006860 <USB_EPStartXfer+0x1364>
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
8006430: f507 7384 add.w r3, r7, #264 @ 0x108
8006434: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006438: 681b ldr r3, [r3, #0]
800643a: 785b ldrb r3, [r3, #1]
800643c: 2b00 cmp r3, #0
800643e: f040 809d bne.w 800657c <USB_EPStartXfer+0x1080>
8006442: f507 7384 add.w r3, r7, #264 @ 0x108
8006446: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800644a: 681b ldr r3, [r3, #0]
800644c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8006450: f507 7384 add.w r3, r7, #264 @ 0x108
8006454: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006458: 681b ldr r3, [r3, #0]
800645a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800645e: b29b uxth r3, r3
8006460: 461a mov r2, r3
8006462: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8006466: 4413 add r3, r2
8006468: f8c7 30ac str.w r3, [r7, #172] @ 0xac
800646c: f507 7384 add.w r3, r7, #264 @ 0x108
8006470: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006474: 681b ldr r3, [r3, #0]
8006476: 781b ldrb r3, [r3, #0]
8006478: 011a lsls r2, r3, #4
800647a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800647e: 4413 add r3, r2
8006480: f203 4304 addw r3, r3, #1028 @ 0x404
8006484: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
8006488: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800648c: 881b ldrh r3, [r3, #0]
800648e: b29b uxth r3, r3
8006490: f3c3 0309 ubfx r3, r3, #0, #10
8006494: b29a uxth r2, r3
8006496: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800649a: 801a strh r2, [r3, #0]
800649c: f507 7384 add.w r3, r7, #264 @ 0x108
80064a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80064a4: 681b ldr r3, [r3, #0]
80064a6: 691b ldr r3, [r3, #16]
80064a8: 2b3e cmp r3, #62 @ 0x3e
80064aa: d92b bls.n 8006504 <USB_EPStartXfer+0x1008>
80064ac: f507 7384 add.w r3, r7, #264 @ 0x108
80064b0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80064b4: 681b ldr r3, [r3, #0]
80064b6: 691b ldr r3, [r3, #16]
80064b8: 095b lsrs r3, r3, #5
80064ba: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80064be: f507 7384 add.w r3, r7, #264 @ 0x108
80064c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80064c6: 681b ldr r3, [r3, #0]
80064c8: 691b ldr r3, [r3, #16]
80064ca: f003 031f and.w r3, r3, #31
80064ce: 2b00 cmp r3, #0
80064d0: d104 bne.n 80064dc <USB_EPStartXfer+0xfe0>
80064d2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80064d6: 3b01 subs r3, #1
80064d8: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80064dc: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80064e0: 881b ldrh r3, [r3, #0]
80064e2: b29a uxth r2, r3
80064e4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80064e8: b29b uxth r3, r3
80064ea: 029b lsls r3, r3, #10
80064ec: b29b uxth r3, r3
80064ee: 4313 orrs r3, r2
80064f0: b29b uxth r3, r3
80064f2: ea6f 4343 mvn.w r3, r3, lsl #17
80064f6: ea6f 4353 mvn.w r3, r3, lsr #17
80064fa: b29a uxth r2, r3
80064fc: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8006500: 801a strh r2, [r3, #0]
8006502: e070 b.n 80065e6 <USB_EPStartXfer+0x10ea>
8006504: f507 7384 add.w r3, r7, #264 @ 0x108
8006508: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800650c: 681b ldr r3, [r3, #0]
800650e: 691b ldr r3, [r3, #16]
8006510: 2b00 cmp r3, #0
8006512: d10c bne.n 800652e <USB_EPStartXfer+0x1032>
8006514: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8006518: 881b ldrh r3, [r3, #0]
800651a: b29b uxth r3, r3
800651c: ea6f 4343 mvn.w r3, r3, lsl #17
8006520: ea6f 4353 mvn.w r3, r3, lsr #17
8006524: b29a uxth r2, r3
8006526: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800652a: 801a strh r2, [r3, #0]
800652c: e05b b.n 80065e6 <USB_EPStartXfer+0x10ea>
800652e: f507 7384 add.w r3, r7, #264 @ 0x108
8006532: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006536: 681b ldr r3, [r3, #0]
8006538: 691b ldr r3, [r3, #16]
800653a: 085b lsrs r3, r3, #1
800653c: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
8006540: f507 7384 add.w r3, r7, #264 @ 0x108
8006544: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006548: 681b ldr r3, [r3, #0]
800654a: 691b ldr r3, [r3, #16]
800654c: f003 0301 and.w r3, r3, #1
8006550: 2b00 cmp r3, #0
8006552: d004 beq.n 800655e <USB_EPStartXfer+0x1062>
8006554: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006558: 3301 adds r3, #1
800655a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
800655e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8006562: 881b ldrh r3, [r3, #0]
8006564: b29a uxth r2, r3
8006566: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800656a: b29b uxth r3, r3
800656c: 029b lsls r3, r3, #10
800656e: b29b uxth r3, r3
8006570: 4313 orrs r3, r2
8006572: b29a uxth r2, r3
8006574: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8006578: 801a strh r2, [r3, #0]
800657a: e034 b.n 80065e6 <USB_EPStartXfer+0x10ea>
800657c: f507 7384 add.w r3, r7, #264 @ 0x108
8006580: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006584: 681b ldr r3, [r3, #0]
8006586: 785b ldrb r3, [r3, #1]
8006588: 2b01 cmp r3, #1
800658a: d12c bne.n 80065e6 <USB_EPStartXfer+0x10ea>
800658c: f507 7384 add.w r3, r7, #264 @ 0x108
8006590: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006594: 681b ldr r3, [r3, #0]
8006596: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
800659a: f507 7384 add.w r3, r7, #264 @ 0x108
800659e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80065a2: 681b ldr r3, [r3, #0]
80065a4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80065a8: b29b uxth r3, r3
80065aa: 461a mov r2, r3
80065ac: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80065b0: 4413 add r3, r2
80065b2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80065b6: f507 7384 add.w r3, r7, #264 @ 0x108
80065ba: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80065be: 681b ldr r3, [r3, #0]
80065c0: 781b ldrb r3, [r3, #0]
80065c2: 011a lsls r2, r3, #4
80065c4: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80065c8: 4413 add r3, r2
80065ca: f203 4304 addw r3, r3, #1028 @ 0x404
80065ce: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
80065d2: f507 7384 add.w r3, r7, #264 @ 0x108
80065d6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80065da: 681b ldr r3, [r3, #0]
80065dc: 691b ldr r3, [r3, #16]
80065de: b29a uxth r2, r3
80065e0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
80065e4: 801a strh r2, [r3, #0]
80065e6: f507 7384 add.w r3, r7, #264 @ 0x108
80065ea: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80065ee: 681b ldr r3, [r3, #0]
80065f0: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
80065f4: f507 7384 add.w r3, r7, #264 @ 0x108
80065f8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80065fc: 681b ldr r3, [r3, #0]
80065fe: 785b ldrb r3, [r3, #1]
8006600: 2b00 cmp r3, #0
8006602: f040 809d bne.w 8006740 <USB_EPStartXfer+0x1244>
8006606: f507 7384 add.w r3, r7, #264 @ 0x108
800660a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800660e: 681b ldr r3, [r3, #0]
8006610: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8006614: f507 7384 add.w r3, r7, #264 @ 0x108
8006618: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800661c: 681b ldr r3, [r3, #0]
800661e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006622: b29b uxth r3, r3
8006624: 461a mov r2, r3
8006626: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800662a: 4413 add r3, r2
800662c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8006630: f507 7384 add.w r3, r7, #264 @ 0x108
8006634: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006638: 681b ldr r3, [r3, #0]
800663a: 781b ldrb r3, [r3, #0]
800663c: 011a lsls r2, r3, #4
800663e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8006642: 4413 add r3, r2
8006644: f203 430c addw r3, r3, #1036 @ 0x40c
8006648: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800664c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8006650: 881b ldrh r3, [r3, #0]
8006652: b29b uxth r3, r3
8006654: f3c3 0309 ubfx r3, r3, #0, #10
8006658: b29a uxth r2, r3
800665a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800665e: 801a strh r2, [r3, #0]
8006660: f507 7384 add.w r3, r7, #264 @ 0x108
8006664: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006668: 681b ldr r3, [r3, #0]
800666a: 691b ldr r3, [r3, #16]
800666c: 2b3e cmp r3, #62 @ 0x3e
800666e: d92b bls.n 80066c8 <USB_EPStartXfer+0x11cc>
8006670: f507 7384 add.w r3, r7, #264 @ 0x108
8006674: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006678: 681b ldr r3, [r3, #0]
800667a: 691b ldr r3, [r3, #16]
800667c: 095b lsrs r3, r3, #5
800667e: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8006682: f507 7384 add.w r3, r7, #264 @ 0x108
8006686: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800668a: 681b ldr r3, [r3, #0]
800668c: 691b ldr r3, [r3, #16]
800668e: f003 031f and.w r3, r3, #31
8006692: 2b00 cmp r3, #0
8006694: d104 bne.n 80066a0 <USB_EPStartXfer+0x11a4>
8006696: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800669a: 3b01 subs r3, #1
800669c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
80066a0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80066a4: 881b ldrh r3, [r3, #0]
80066a6: b29a uxth r2, r3
80066a8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80066ac: b29b uxth r3, r3
80066ae: 029b lsls r3, r3, #10
80066b0: b29b uxth r3, r3
80066b2: 4313 orrs r3, r2
80066b4: b29b uxth r3, r3
80066b6: ea6f 4343 mvn.w r3, r3, lsl #17
80066ba: ea6f 4353 mvn.w r3, r3, lsr #17
80066be: b29a uxth r2, r3
80066c0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80066c4: 801a strh r2, [r3, #0]
80066c6: e069 b.n 800679c <USB_EPStartXfer+0x12a0>
80066c8: f507 7384 add.w r3, r7, #264 @ 0x108
80066cc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80066d0: 681b ldr r3, [r3, #0]
80066d2: 691b ldr r3, [r3, #16]
80066d4: 2b00 cmp r3, #0
80066d6: d10c bne.n 80066f2 <USB_EPStartXfer+0x11f6>
80066d8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80066dc: 881b ldrh r3, [r3, #0]
80066de: b29b uxth r3, r3
80066e0: ea6f 4343 mvn.w r3, r3, lsl #17
80066e4: ea6f 4353 mvn.w r3, r3, lsr #17
80066e8: b29a uxth r2, r3
80066ea: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80066ee: 801a strh r2, [r3, #0]
80066f0: e054 b.n 800679c <USB_EPStartXfer+0x12a0>
80066f2: f507 7384 add.w r3, r7, #264 @ 0x108
80066f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80066fa: 681b ldr r3, [r3, #0]
80066fc: 691b ldr r3, [r3, #16]
80066fe: 085b lsrs r3, r3, #1
8006700: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8006704: f507 7384 add.w r3, r7, #264 @ 0x108
8006708: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800670c: 681b ldr r3, [r3, #0]
800670e: 691b ldr r3, [r3, #16]
8006710: f003 0301 and.w r3, r3, #1
8006714: 2b00 cmp r3, #0
8006716: d004 beq.n 8006722 <USB_EPStartXfer+0x1226>
8006718: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800671c: 3301 adds r3, #1
800671e: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8006722: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8006726: 881b ldrh r3, [r3, #0]
8006728: b29a uxth r2, r3
800672a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800672e: b29b uxth r3, r3
8006730: 029b lsls r3, r3, #10
8006732: b29b uxth r3, r3
8006734: 4313 orrs r3, r2
8006736: b29a uxth r2, r3
8006738: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800673c: 801a strh r2, [r3, #0]
800673e: e02d b.n 800679c <USB_EPStartXfer+0x12a0>
8006740: f507 7384 add.w r3, r7, #264 @ 0x108
8006744: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006748: 681b ldr r3, [r3, #0]
800674a: 785b ldrb r3, [r3, #1]
800674c: 2b01 cmp r3, #1
800674e: d125 bne.n 800679c <USB_EPStartXfer+0x12a0>
8006750: f507 7384 add.w r3, r7, #264 @ 0x108
8006754: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006758: 681b ldr r3, [r3, #0]
800675a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800675e: b29b uxth r3, r3
8006760: 461a mov r2, r3
8006762: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8006766: 4413 add r3, r2
8006768: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800676c: f507 7384 add.w r3, r7, #264 @ 0x108
8006770: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006774: 681b ldr r3, [r3, #0]
8006776: 781b ldrb r3, [r3, #0]
8006778: 011a lsls r2, r3, #4
800677a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800677e: 4413 add r3, r2
8006780: f203 430c addw r3, r3, #1036 @ 0x40c
8006784: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
8006788: f507 7384 add.w r3, r7, #264 @ 0x108
800678c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006790: 681b ldr r3, [r3, #0]
8006792: 691b ldr r3, [r3, #16]
8006794: b29a uxth r2, r3
8006796: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800679a: 801a strh r2, [r3, #0]
/* Coming from ISR */
if (ep->xfer_count != 0U)
800679c: f507 7384 add.w r3, r7, #264 @ 0x108
80067a0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80067a4: 681b ldr r3, [r3, #0]
80067a6: 69db ldr r3, [r3, #28]
80067a8: 2b00 cmp r3, #0
80067aa: f000 8218 beq.w 8006bde <USB_EPStartXfer+0x16e2>
{
/* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
80067ae: f507 7384 add.w r3, r7, #264 @ 0x108
80067b2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80067b6: 681a ldr r2, [r3, #0]
80067b8: f507 7384 add.w r3, r7, #264 @ 0x108
80067bc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80067c0: 681b ldr r3, [r3, #0]
80067c2: 781b ldrb r3, [r3, #0]
80067c4: 009b lsls r3, r3, #2
80067c6: 4413 add r3, r2
80067c8: 881b ldrh r3, [r3, #0]
80067ca: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
80067ce: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80067d2: f403 4380 and.w r3, r3, #16384 @ 0x4000
80067d6: 2b00 cmp r3, #0
80067d8: d005 beq.n 80067e6 <USB_EPStartXfer+0x12ea>
80067da: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80067de: f003 0340 and.w r3, r3, #64 @ 0x40
80067e2: 2b00 cmp r3, #0
80067e4: d10d bne.n 8006802 <USB_EPStartXfer+0x1306>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
80067e6: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80067ea: f403 4380 and.w r3, r3, #16384 @ 0x4000
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
80067ee: 2b00 cmp r3, #0
80067f0: f040 81f5 bne.w 8006bde <USB_EPStartXfer+0x16e2>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
80067f4: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80067f8: f003 0340 and.w r3, r3, #64 @ 0x40
80067fc: 2b00 cmp r3, #0
80067fe: f040 81ee bne.w 8006bde <USB_EPStartXfer+0x16e2>
{
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
8006802: f507 7384 add.w r3, r7, #264 @ 0x108
8006806: f5a3 7382 sub.w r3, r3, #260 @ 0x104
800680a: 681a ldr r2, [r3, #0]
800680c: f507 7384 add.w r3, r7, #264 @ 0x108
8006810: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006814: 681b ldr r3, [r3, #0]
8006816: 781b ldrb r3, [r3, #0]
8006818: 009b lsls r3, r3, #2
800681a: 4413 add r3, r2
800681c: 881b ldrh r3, [r3, #0]
800681e: b29b uxth r3, r3
8006820: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006824: f023 0370 bic.w r3, r3, #112 @ 0x70
8006828: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
800682c: f507 7384 add.w r3, r7, #264 @ 0x108
8006830: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006834: 681a ldr r2, [r3, #0]
8006836: f507 7384 add.w r3, r7, #264 @ 0x108
800683a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800683e: 681b ldr r3, [r3, #0]
8006840: 781b ldrb r3, [r3, #0]
8006842: 009b lsls r3, r3, #2
8006844: 441a add r2, r3
8006846: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800684a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800684e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006852: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006856: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800685a: b29b uxth r3, r3
800685c: 8013 strh r3, [r2, #0]
800685e: e1be b.n 8006bde <USB_EPStartXfer+0x16e2>
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
8006860: f507 7384 add.w r3, r7, #264 @ 0x108
8006864: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006868: 681b ldr r3, [r3, #0]
800686a: 78db ldrb r3, [r3, #3]
800686c: 2b01 cmp r3, #1
800686e: f040 81b4 bne.w 8006bda <USB_EPStartXfer+0x16de>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
8006872: f507 7384 add.w r3, r7, #264 @ 0x108
8006876: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800687a: 681b ldr r3, [r3, #0]
800687c: 699a ldr r2, [r3, #24]
800687e: f507 7384 add.w r3, r7, #264 @ 0x108
8006882: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006886: 681b ldr r3, [r3, #0]
8006888: 691b ldr r3, [r3, #16]
800688a: 429a cmp r2, r3
800688c: d917 bls.n 80068be <USB_EPStartXfer+0x13c2>
{
len = ep->maxpacket;
800688e: f507 7384 add.w r3, r7, #264 @ 0x108
8006892: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006896: 681b ldr r3, [r3, #0]
8006898: 691b ldr r3, [r3, #16]
800689a: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len -= len;
800689e: f507 7384 add.w r3, r7, #264 @ 0x108
80068a2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80068a6: 681b ldr r3, [r3, #0]
80068a8: 699a ldr r2, [r3, #24]
80068aa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80068ae: 1ad2 subs r2, r2, r3
80068b0: f507 7384 add.w r3, r7, #264 @ 0x108
80068b4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80068b8: 681b ldr r3, [r3, #0]
80068ba: 619a str r2, [r3, #24]
80068bc: e00e b.n 80068dc <USB_EPStartXfer+0x13e0>
}
else
{
len = ep->xfer_len;
80068be: f507 7384 add.w r3, r7, #264 @ 0x108
80068c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80068c6: 681b ldr r3, [r3, #0]
80068c8: 699b ldr r3, [r3, #24]
80068ca: f8c7 3104 str.w r3, [r7, #260] @ 0x104
ep->xfer_len = 0U;
80068ce: f507 7384 add.w r3, r7, #264 @ 0x108
80068d2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80068d6: 681b ldr r3, [r3, #0]
80068d8: 2200 movs r2, #0
80068da: 619a str r2, [r3, #24]
}
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
80068dc: f507 7384 add.w r3, r7, #264 @ 0x108
80068e0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80068e4: 681b ldr r3, [r3, #0]
80068e6: 785b ldrb r3, [r3, #1]
80068e8: 2b00 cmp r3, #0
80068ea: f040 8085 bne.w 80069f8 <USB_EPStartXfer+0x14fc>
80068ee: f507 7384 add.w r3, r7, #264 @ 0x108
80068f2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80068f6: 681b ldr r3, [r3, #0]
80068f8: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
80068fc: f507 7384 add.w r3, r7, #264 @ 0x108
8006900: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006904: 681b ldr r3, [r3, #0]
8006906: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800690a: b29b uxth r3, r3
800690c: 461a mov r2, r3
800690e: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8006912: 4413 add r3, r2
8006914: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8006918: f507 7384 add.w r3, r7, #264 @ 0x108
800691c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006920: 681b ldr r3, [r3, #0]
8006922: 781b ldrb r3, [r3, #0]
8006924: 011a lsls r2, r3, #4
8006926: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
800692a: 4413 add r3, r2
800692c: f203 4304 addw r3, r3, #1028 @ 0x404
8006930: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8006934: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8006938: 881b ldrh r3, [r3, #0]
800693a: b29b uxth r3, r3
800693c: f3c3 0309 ubfx r3, r3, #0, #10
8006940: b29a uxth r2, r3
8006942: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8006946: 801a strh r2, [r3, #0]
8006948: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800694c: 2b3e cmp r3, #62 @ 0x3e
800694e: d923 bls.n 8006998 <USB_EPStartXfer+0x149c>
8006950: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006954: 095b lsrs r3, r3, #5
8006956: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
800695a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800695e: f003 031f and.w r3, r3, #31
8006962: 2b00 cmp r3, #0
8006964: d104 bne.n 8006970 <USB_EPStartXfer+0x1474>
8006966: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
800696a: 3b01 subs r3, #1
800696c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
8006970: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8006974: 881b ldrh r3, [r3, #0]
8006976: b29a uxth r2, r3
8006978: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
800697c: b29b uxth r3, r3
800697e: 029b lsls r3, r3, #10
8006980: b29b uxth r3, r3
8006982: 4313 orrs r3, r2
8006984: b29b uxth r3, r3
8006986: ea6f 4343 mvn.w r3, r3, lsl #17
800698a: ea6f 4353 mvn.w r3, r3, lsr #17
800698e: b29a uxth r2, r3
8006990: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8006994: 801a strh r2, [r3, #0]
8006996: e060 b.n 8006a5a <USB_EPStartXfer+0x155e>
8006998: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
800699c: 2b00 cmp r3, #0
800699e: d10c bne.n 80069ba <USB_EPStartXfer+0x14be>
80069a0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80069a4: 881b ldrh r3, [r3, #0]
80069a6: b29b uxth r3, r3
80069a8: ea6f 4343 mvn.w r3, r3, lsl #17
80069ac: ea6f 4353 mvn.w r3, r3, lsr #17
80069b0: b29a uxth r2, r3
80069b2: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80069b6: 801a strh r2, [r3, #0]
80069b8: e04f b.n 8006a5a <USB_EPStartXfer+0x155e>
80069ba: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80069be: 085b lsrs r3, r3, #1
80069c0: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
80069c4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
80069c8: f003 0301 and.w r3, r3, #1
80069cc: 2b00 cmp r3, #0
80069ce: d004 beq.n 80069da <USB_EPStartXfer+0x14de>
80069d0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80069d4: 3301 adds r3, #1
80069d6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
80069da: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80069de: 881b ldrh r3, [r3, #0]
80069e0: b29a uxth r2, r3
80069e2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80069e6: b29b uxth r3, r3
80069e8: 029b lsls r3, r3, #10
80069ea: b29b uxth r3, r3
80069ec: 4313 orrs r3, r2
80069ee: b29a uxth r2, r3
80069f0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80069f4: 801a strh r2, [r3, #0]
80069f6: e030 b.n 8006a5a <USB_EPStartXfer+0x155e>
80069f8: f507 7384 add.w r3, r7, #264 @ 0x108
80069fc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006a00: 681b ldr r3, [r3, #0]
8006a02: 785b ldrb r3, [r3, #1]
8006a04: 2b01 cmp r3, #1
8006a06: d128 bne.n 8006a5a <USB_EPStartXfer+0x155e>
8006a08: f507 7384 add.w r3, r7, #264 @ 0x108
8006a0c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006a10: 681b ldr r3, [r3, #0]
8006a12: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8006a16: f507 7384 add.w r3, r7, #264 @ 0x108
8006a1a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006a1e: 681b ldr r3, [r3, #0]
8006a20: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006a24: b29b uxth r3, r3
8006a26: 461a mov r2, r3
8006a28: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8006a2c: 4413 add r3, r2
8006a2e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
8006a32: f507 7384 add.w r3, r7, #264 @ 0x108
8006a36: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006a3a: 681b ldr r3, [r3, #0]
8006a3c: 781b ldrb r3, [r3, #0]
8006a3e: 011a lsls r2, r3, #4
8006a40: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
8006a44: 4413 add r3, r2
8006a46: f203 4304 addw r3, r3, #1028 @ 0x404
8006a4a: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8006a4e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006a52: b29a uxth r2, r3
8006a54: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
8006a58: 801a strh r2, [r3, #0]
8006a5a: f507 7384 add.w r3, r7, #264 @ 0x108
8006a5e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006a62: 681b ldr r3, [r3, #0]
8006a64: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8006a68: f507 7384 add.w r3, r7, #264 @ 0x108
8006a6c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006a70: 681b ldr r3, [r3, #0]
8006a72: 785b ldrb r3, [r3, #1]
8006a74: 2b00 cmp r3, #0
8006a76: f040 8085 bne.w 8006b84 <USB_EPStartXfer+0x1688>
8006a7a: f507 7384 add.w r3, r7, #264 @ 0x108
8006a7e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006a82: 681b ldr r3, [r3, #0]
8006a84: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8006a88: f507 7384 add.w r3, r7, #264 @ 0x108
8006a8c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006a90: 681b ldr r3, [r3, #0]
8006a92: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006a96: b29b uxth r3, r3
8006a98: 461a mov r2, r3
8006a9a: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8006a9e: 4413 add r3, r2
8006aa0: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
8006aa4: f507 7384 add.w r3, r7, #264 @ 0x108
8006aa8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006aac: 681b ldr r3, [r3, #0]
8006aae: 781b ldrb r3, [r3, #0]
8006ab0: 011a lsls r2, r3, #4
8006ab2: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8006ab6: 4413 add r3, r2
8006ab8: f203 430c addw r3, r3, #1036 @ 0x40c
8006abc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8006ac0: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006ac4: 881b ldrh r3, [r3, #0]
8006ac6: b29b uxth r3, r3
8006ac8: f3c3 0309 ubfx r3, r3, #0, #10
8006acc: b29a uxth r2, r3
8006ace: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006ad2: 801a strh r2, [r3, #0]
8006ad4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006ad8: 2b3e cmp r3, #62 @ 0x3e
8006ada: d923 bls.n 8006b24 <USB_EPStartXfer+0x1628>
8006adc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006ae0: 095b lsrs r3, r3, #5
8006ae2: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8006ae6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006aea: f003 031f and.w r3, r3, #31
8006aee: 2b00 cmp r3, #0
8006af0: d104 bne.n 8006afc <USB_EPStartXfer+0x1600>
8006af2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8006af6: 3b01 subs r3, #1
8006af8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8006afc: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006b00: 881b ldrh r3, [r3, #0]
8006b02: b29a uxth r2, r3
8006b04: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8006b08: b29b uxth r3, r3
8006b0a: 029b lsls r3, r3, #10
8006b0c: b29b uxth r3, r3
8006b0e: 4313 orrs r3, r2
8006b10: b29b uxth r3, r3
8006b12: ea6f 4343 mvn.w r3, r3, lsl #17
8006b16: ea6f 4353 mvn.w r3, r3, lsr #17
8006b1a: b29a uxth r2, r3
8006b1c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006b20: 801a strh r2, [r3, #0]
8006b22: e05c b.n 8006bde <USB_EPStartXfer+0x16e2>
8006b24: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006b28: 2b00 cmp r3, #0
8006b2a: d10c bne.n 8006b46 <USB_EPStartXfer+0x164a>
8006b2c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006b30: 881b ldrh r3, [r3, #0]
8006b32: b29b uxth r3, r3
8006b34: ea6f 4343 mvn.w r3, r3, lsl #17
8006b38: ea6f 4353 mvn.w r3, r3, lsr #17
8006b3c: b29a uxth r2, r3
8006b3e: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006b42: 801a strh r2, [r3, #0]
8006b44: e04b b.n 8006bde <USB_EPStartXfer+0x16e2>
8006b46: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006b4a: 085b lsrs r3, r3, #1
8006b4c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8006b50: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006b54: f003 0301 and.w r3, r3, #1
8006b58: 2b00 cmp r3, #0
8006b5a: d004 beq.n 8006b66 <USB_EPStartXfer+0x166a>
8006b5c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8006b60: 3301 adds r3, #1
8006b62: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8006b66: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006b6a: 881b ldrh r3, [r3, #0]
8006b6c: b29a uxth r2, r3
8006b6e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8006b72: b29b uxth r3, r3
8006b74: 029b lsls r3, r3, #10
8006b76: b29b uxth r3, r3
8006b78: 4313 orrs r3, r2
8006b7a: b29a uxth r2, r3
8006b7c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006b80: 801a strh r2, [r3, #0]
8006b82: e02c b.n 8006bde <USB_EPStartXfer+0x16e2>
8006b84: f507 7384 add.w r3, r7, #264 @ 0x108
8006b88: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006b8c: 681b ldr r3, [r3, #0]
8006b8e: 785b ldrb r3, [r3, #1]
8006b90: 2b01 cmp r3, #1
8006b92: d124 bne.n 8006bde <USB_EPStartXfer+0x16e2>
8006b94: f507 7384 add.w r3, r7, #264 @ 0x108
8006b98: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006b9c: 681b ldr r3, [r3, #0]
8006b9e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8006ba2: b29b uxth r3, r3
8006ba4: 461a mov r2, r3
8006ba6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8006baa: 4413 add r3, r2
8006bac: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8006bb0: f507 7384 add.w r3, r7, #264 @ 0x108
8006bb4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006bb8: 681b ldr r3, [r3, #0]
8006bba: 781b ldrb r3, [r3, #0]
8006bbc: 011a lsls r2, r3, #4
8006bbe: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8006bc2: 4413 add r3, r2
8006bc4: f203 430c addw r3, r3, #1036 @ 0x40c
8006bc8: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8006bcc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
8006bd0: b29a uxth r2, r3
8006bd2: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8006bd6: 801a strh r2, [r3, #0]
8006bd8: e001 b.n 8006bde <USB_EPStartXfer+0x16e2>
}
else
{
return HAL_ERROR;
8006bda: 2301 movs r3, #1
8006bdc: e03a b.n 8006c54 <USB_EPStartXfer+0x1758>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8006bde: f507 7384 add.w r3, r7, #264 @ 0x108
8006be2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006be6: 681a ldr r2, [r3, #0]
8006be8: f507 7384 add.w r3, r7, #264 @ 0x108
8006bec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006bf0: 681b ldr r3, [r3, #0]
8006bf2: 781b ldrb r3, [r3, #0]
8006bf4: 009b lsls r3, r3, #2
8006bf6: 4413 add r3, r2
8006bf8: 881b ldrh r3, [r3, #0]
8006bfa: b29b uxth r3, r3
8006bfc: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006c00: f023 0370 bic.w r3, r3, #112 @ 0x70
8006c04: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8006c08: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8006c0c: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8006c10: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8006c14: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8006c18: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8006c1c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
8006c20: f507 7384 add.w r3, r7, #264 @ 0x108
8006c24: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8006c28: 681a ldr r2, [r3, #0]
8006c2a: f507 7384 add.w r3, r7, #264 @ 0x108
8006c2e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8006c32: 681b ldr r3, [r3, #0]
8006c34: 781b ldrb r3, [r3, #0]
8006c36: 009b lsls r3, r3, #2
8006c38: 441a add r2, r3
8006c3a: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8006c3e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006c42: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006c46: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006c4a: f043 0380 orr.w r3, r3, #128 @ 0x80
8006c4e: b29b uxth r3, r3
8006c50: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8006c52: 2300 movs r3, #0
}
8006c54: 4618 mov r0, r3
8006c56: f507 7784 add.w r7, r7, #264 @ 0x108
8006c5a: 46bd mov sp, r7
8006c5c: bd80 pop {r7, pc}
08006c5e <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8006c5e: b480 push {r7}
8006c60: b085 sub sp, #20
8006c62: af00 add r7, sp, #0
8006c64: 6078 str r0, [r7, #4]
8006c66: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
8006c68: 683b ldr r3, [r7, #0]
8006c6a: 785b ldrb r3, [r3, #1]
8006c6c: 2b00 cmp r3, #0
8006c6e: d020 beq.n 8006cb2 <USB_EPSetStall+0x54>
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
8006c70: 687a ldr r2, [r7, #4]
8006c72: 683b ldr r3, [r7, #0]
8006c74: 781b ldrb r3, [r3, #0]
8006c76: 009b lsls r3, r3, #2
8006c78: 4413 add r3, r2
8006c7a: 881b ldrh r3, [r3, #0]
8006c7c: b29b uxth r3, r3
8006c7e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006c82: f023 0340 bic.w r3, r3, #64 @ 0x40
8006c86: 81bb strh r3, [r7, #12]
8006c88: 89bb ldrh r3, [r7, #12]
8006c8a: f083 0310 eor.w r3, r3, #16
8006c8e: 81bb strh r3, [r7, #12]
8006c90: 687a ldr r2, [r7, #4]
8006c92: 683b ldr r3, [r7, #0]
8006c94: 781b ldrb r3, [r3, #0]
8006c96: 009b lsls r3, r3, #2
8006c98: 441a add r2, r3
8006c9a: 89bb ldrh r3, [r7, #12]
8006c9c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006ca0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006ca4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006ca8: f043 0380 orr.w r3, r3, #128 @ 0x80
8006cac: b29b uxth r3, r3
8006cae: 8013 strh r3, [r2, #0]
8006cb0: e01f b.n 8006cf2 <USB_EPSetStall+0x94>
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
8006cb2: 687a ldr r2, [r7, #4]
8006cb4: 683b ldr r3, [r7, #0]
8006cb6: 781b ldrb r3, [r3, #0]
8006cb8: 009b lsls r3, r3, #2
8006cba: 4413 add r3, r2
8006cbc: 881b ldrh r3, [r3, #0]
8006cbe: b29b uxth r3, r3
8006cc0: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006cc4: f023 0370 bic.w r3, r3, #112 @ 0x70
8006cc8: 81fb strh r3, [r7, #14]
8006cca: 89fb ldrh r3, [r7, #14]
8006ccc: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8006cd0: 81fb strh r3, [r7, #14]
8006cd2: 687a ldr r2, [r7, #4]
8006cd4: 683b ldr r3, [r7, #0]
8006cd6: 781b ldrb r3, [r3, #0]
8006cd8: 009b lsls r3, r3, #2
8006cda: 441a add r2, r3
8006cdc: 89fb ldrh r3, [r7, #14]
8006cde: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006ce2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006ce6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006cea: f043 0380 orr.w r3, r3, #128 @ 0x80
8006cee: b29b uxth r3, r3
8006cf0: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8006cf2: 2300 movs r3, #0
}
8006cf4: 4618 mov r0, r3
8006cf6: 3714 adds r7, #20
8006cf8: 46bd mov sp, r7
8006cfa: bc80 pop {r7}
8006cfc: 4770 bx lr
08006cfe <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8006cfe: b480 push {r7}
8006d00: b087 sub sp, #28
8006d02: af00 add r7, sp, #0
8006d04: 6078 str r0, [r7, #4]
8006d06: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
8006d08: 683b ldr r3, [r7, #0]
8006d0a: 7b1b ldrb r3, [r3, #12]
8006d0c: 2b00 cmp r3, #0
8006d0e: f040 809d bne.w 8006e4c <USB_EPClearStall+0x14e>
{
if (ep->is_in != 0U)
8006d12: 683b ldr r3, [r7, #0]
8006d14: 785b ldrb r3, [r3, #1]
8006d16: 2b00 cmp r3, #0
8006d18: d04c beq.n 8006db4 <USB_EPClearStall+0xb6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8006d1a: 687a ldr r2, [r7, #4]
8006d1c: 683b ldr r3, [r7, #0]
8006d1e: 781b ldrb r3, [r3, #0]
8006d20: 009b lsls r3, r3, #2
8006d22: 4413 add r3, r2
8006d24: 881b ldrh r3, [r3, #0]
8006d26: 823b strh r3, [r7, #16]
8006d28: 8a3b ldrh r3, [r7, #16]
8006d2a: f003 0340 and.w r3, r3, #64 @ 0x40
8006d2e: 2b00 cmp r3, #0
8006d30: d01b beq.n 8006d6a <USB_EPClearStall+0x6c>
8006d32: 687a ldr r2, [r7, #4]
8006d34: 683b ldr r3, [r7, #0]
8006d36: 781b ldrb r3, [r3, #0]
8006d38: 009b lsls r3, r3, #2
8006d3a: 4413 add r3, r2
8006d3c: 881b ldrh r3, [r3, #0]
8006d3e: b29b uxth r3, r3
8006d40: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006d44: f023 0370 bic.w r3, r3, #112 @ 0x70
8006d48: 81fb strh r3, [r7, #14]
8006d4a: 687a ldr r2, [r7, #4]
8006d4c: 683b ldr r3, [r7, #0]
8006d4e: 781b ldrb r3, [r3, #0]
8006d50: 009b lsls r3, r3, #2
8006d52: 441a add r2, r3
8006d54: 89fb ldrh r3, [r7, #14]
8006d56: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006d5a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006d5e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006d62: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8006d66: b29b uxth r3, r3
8006d68: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8006d6a: 683b ldr r3, [r7, #0]
8006d6c: 78db ldrb r3, [r3, #3]
8006d6e: 2b01 cmp r3, #1
8006d70: d06c beq.n 8006e4c <USB_EPClearStall+0x14e>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8006d72: 687a ldr r2, [r7, #4]
8006d74: 683b ldr r3, [r7, #0]
8006d76: 781b ldrb r3, [r3, #0]
8006d78: 009b lsls r3, r3, #2
8006d7a: 4413 add r3, r2
8006d7c: 881b ldrh r3, [r3, #0]
8006d7e: b29b uxth r3, r3
8006d80: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006d84: f023 0340 bic.w r3, r3, #64 @ 0x40
8006d88: 81bb strh r3, [r7, #12]
8006d8a: 89bb ldrh r3, [r7, #12]
8006d8c: f083 0320 eor.w r3, r3, #32
8006d90: 81bb strh r3, [r7, #12]
8006d92: 687a ldr r2, [r7, #4]
8006d94: 683b ldr r3, [r7, #0]
8006d96: 781b ldrb r3, [r3, #0]
8006d98: 009b lsls r3, r3, #2
8006d9a: 441a add r2, r3
8006d9c: 89bb ldrh r3, [r7, #12]
8006d9e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006da2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006da6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006daa: f043 0380 orr.w r3, r3, #128 @ 0x80
8006dae: b29b uxth r3, r3
8006db0: 8013 strh r3, [r2, #0]
8006db2: e04b b.n 8006e4c <USB_EPClearStall+0x14e>
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8006db4: 687a ldr r2, [r7, #4]
8006db6: 683b ldr r3, [r7, #0]
8006db8: 781b ldrb r3, [r3, #0]
8006dba: 009b lsls r3, r3, #2
8006dbc: 4413 add r3, r2
8006dbe: 881b ldrh r3, [r3, #0]
8006dc0: 82fb strh r3, [r7, #22]
8006dc2: 8afb ldrh r3, [r7, #22]
8006dc4: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006dc8: 2b00 cmp r3, #0
8006dca: d01b beq.n 8006e04 <USB_EPClearStall+0x106>
8006dcc: 687a ldr r2, [r7, #4]
8006dce: 683b ldr r3, [r7, #0]
8006dd0: 781b ldrb r3, [r3, #0]
8006dd2: 009b lsls r3, r3, #2
8006dd4: 4413 add r3, r2
8006dd6: 881b ldrh r3, [r3, #0]
8006dd8: b29b uxth r3, r3
8006dda: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8006dde: f023 0370 bic.w r3, r3, #112 @ 0x70
8006de2: 82bb strh r3, [r7, #20]
8006de4: 687a ldr r2, [r7, #4]
8006de6: 683b ldr r3, [r7, #0]
8006de8: 781b ldrb r3, [r3, #0]
8006dea: 009b lsls r3, r3, #2
8006dec: 441a add r2, r3
8006dee: 8abb ldrh r3, [r7, #20]
8006df0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006df4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006df8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8006dfc: f043 0380 orr.w r3, r3, #128 @ 0x80
8006e00: b29b uxth r3, r3
8006e02: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8006e04: 687a ldr r2, [r7, #4]
8006e06: 683b ldr r3, [r7, #0]
8006e08: 781b ldrb r3, [r3, #0]
8006e0a: 009b lsls r3, r3, #2
8006e0c: 4413 add r3, r2
8006e0e: 881b ldrh r3, [r3, #0]
8006e10: b29b uxth r3, r3
8006e12: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8006e16: f023 0370 bic.w r3, r3, #112 @ 0x70
8006e1a: 827b strh r3, [r7, #18]
8006e1c: 8a7b ldrh r3, [r7, #18]
8006e1e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
8006e22: 827b strh r3, [r7, #18]
8006e24: 8a7b ldrh r3, [r7, #18]
8006e26: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8006e2a: 827b strh r3, [r7, #18]
8006e2c: 687a ldr r2, [r7, #4]
8006e2e: 683b ldr r3, [r7, #0]
8006e30: 781b ldrb r3, [r3, #0]
8006e32: 009b lsls r3, r3, #2
8006e34: 441a add r2, r3
8006e36: 8a7b ldrh r3, [r7, #18]
8006e38: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8006e3c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8006e40: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006e44: f043 0380 orr.w r3, r3, #128 @ 0x80
8006e48: b29b uxth r3, r3
8006e4a: 8013 strh r3, [r2, #0]
}
}
return HAL_OK;
8006e4c: 2300 movs r3, #0
}
8006e4e: 4618 mov r0, r3
8006e50: 371c adds r7, #28
8006e52: 46bd mov sp, r7
8006e54: bc80 pop {r7}
8006e56: 4770 bx lr
08006e58 <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
8006e58: b480 push {r7}
8006e5a: b083 sub sp, #12
8006e5c: af00 add r7, sp, #0
8006e5e: 6078 str r0, [r7, #4]
8006e60: 460b mov r3, r1
8006e62: 70fb strb r3, [r7, #3]
if (address == 0U)
8006e64: 78fb ldrb r3, [r7, #3]
8006e66: 2b00 cmp r3, #0
8006e68: d103 bne.n 8006e72 <USB_SetDevAddress+0x1a>
{
/* set device address and enable function */
USBx->DADDR = (uint16_t)USB_DADDR_EF;
8006e6a: 687b ldr r3, [r7, #4]
8006e6c: 2280 movs r2, #128 @ 0x80
8006e6e: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
}
return HAL_OK;
8006e72: 2300 movs r3, #0
}
8006e74: 4618 mov r0, r3
8006e76: 370c adds r7, #12
8006e78: 46bd mov sp, r7
8006e7a: bc80 pop {r7}
8006e7c: 4770 bx lr
08006e7e <USB_DevConnect>:
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
8006e7e: b480 push {r7}
8006e80: b083 sub sp, #12
8006e82: af00 add r7, sp, #0
8006e84: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8006e86: 2300 movs r3, #0
}
8006e88: 4618 mov r0, r3
8006e8a: 370c adds r7, #12
8006e8c: 46bd mov sp, r7
8006e8e: bc80 pop {r7}
8006e90: 4770 bx lr
08006e92 <USB_DevDisconnect>:
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
8006e92: b480 push {r7}
8006e94: b083 sub sp, #12
8006e96: af00 add r7, sp, #0
8006e98: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8006e9a: 2300 movs r3, #0
}
8006e9c: 4618 mov r0, r3
8006e9e: 370c adds r7, #12
8006ea0: 46bd mov sp, r7
8006ea2: bc80 pop {r7}
8006ea4: 4770 bx lr
08006ea6 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
8006ea6: b480 push {r7}
8006ea8: b085 sub sp, #20
8006eaa: af00 add r7, sp, #0
8006eac: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->ISTR;
8006eae: 687b ldr r3, [r7, #4]
8006eb0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8006eb4: b29b uxth r3, r3
8006eb6: 60fb str r3, [r7, #12]
return tmpreg;
8006eb8: 68fb ldr r3, [r7, #12]
}
8006eba: 4618 mov r0, r3
8006ebc: 3714 adds r7, #20
8006ebe: 46bd mov sp, r7
8006ec0: bc80 pop {r7}
8006ec2: 4770 bx lr
08006ec4 <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
8006ec4: b480 push {r7}
8006ec6: b083 sub sp, #12
8006ec8: af00 add r7, sp, #0
8006eca: 6078 str r0, [r7, #4]
8006ecc: 6039 str r1, [r7, #0]
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8006ece: 2300 movs r3, #0
}
8006ed0: 4618 mov r0, r3
8006ed2: 370c adds r7, #12
8006ed4: 46bd mov sp, r7
8006ed6: bc80 pop {r7}
8006ed8: 4770 bx lr
08006eda <USB_WritePMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
8006eda: b480 push {r7}
8006edc: b08b sub sp, #44 @ 0x2c
8006ede: af00 add r7, sp, #0
8006ee0: 60f8 str r0, [r7, #12]
8006ee2: 60b9 str r1, [r7, #8]
8006ee4: 4611 mov r1, r2
8006ee6: 461a mov r2, r3
8006ee8: 460b mov r3, r1
8006eea: 80fb strh r3, [r7, #6]
8006eec: 4613 mov r3, r2
8006eee: 80bb strh r3, [r7, #4]
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
8006ef0: 88bb ldrh r3, [r7, #4]
8006ef2: 3301 adds r3, #1
8006ef4: 085b lsrs r3, r3, #1
8006ef6: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
8006ef8: 68fb ldr r3, [r7, #12]
8006efa: 617b str r3, [r7, #20]
uint32_t count;
uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
8006efc: 68bb ldr r3, [r7, #8]
8006efe: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
8006f00: 88fb ldrh r3, [r7, #6]
8006f02: 005a lsls r2, r3, #1
8006f04: 697b ldr r3, [r7, #20]
8006f06: 4413 add r3, r2
8006f08: f503 6380 add.w r3, r3, #1024 @ 0x400
8006f0c: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
8006f0e: 69bb ldr r3, [r7, #24]
8006f10: 627b str r3, [r7, #36] @ 0x24
8006f12: e01f b.n 8006f54 <USB_WritePMA+0x7a>
{
WrVal = pBuf[0];
8006f14: 69fb ldr r3, [r7, #28]
8006f16: 781b ldrb r3, [r3, #0]
8006f18: 827b strh r3, [r7, #18]
WrVal |= (uint16_t)pBuf[1] << 8;
8006f1a: 69fb ldr r3, [r7, #28]
8006f1c: 3301 adds r3, #1
8006f1e: 781b ldrb r3, [r3, #0]
8006f20: b21b sxth r3, r3
8006f22: 021b lsls r3, r3, #8
8006f24: b21a sxth r2, r3
8006f26: f9b7 3012 ldrsh.w r3, [r7, #18]
8006f2a: 4313 orrs r3, r2
8006f2c: b21b sxth r3, r3
8006f2e: 827b strh r3, [r7, #18]
*pdwVal = (WrVal & 0xFFFFU);
8006f30: 6a3b ldr r3, [r7, #32]
8006f32: 8a7a ldrh r2, [r7, #18]
8006f34: 801a strh r2, [r3, #0]
pdwVal++;
8006f36: 6a3b ldr r3, [r7, #32]
8006f38: 3302 adds r3, #2
8006f3a: 623b str r3, [r7, #32]
#if PMA_ACCESS > 1U
pdwVal++;
8006f3c: 6a3b ldr r3, [r7, #32]
8006f3e: 3302 adds r3, #2
8006f40: 623b str r3, [r7, #32]
#endif /* PMA_ACCESS */
pBuf++;
8006f42: 69fb ldr r3, [r7, #28]
8006f44: 3301 adds r3, #1
8006f46: 61fb str r3, [r7, #28]
pBuf++;
8006f48: 69fb ldr r3, [r7, #28]
8006f4a: 3301 adds r3, #1
8006f4c: 61fb str r3, [r7, #28]
for (count = n; count != 0U; count--)
8006f4e: 6a7b ldr r3, [r7, #36] @ 0x24
8006f50: 3b01 subs r3, #1
8006f52: 627b str r3, [r7, #36] @ 0x24
8006f54: 6a7b ldr r3, [r7, #36] @ 0x24
8006f56: 2b00 cmp r3, #0
8006f58: d1dc bne.n 8006f14 <USB_WritePMA+0x3a>
}
}
8006f5a: bf00 nop
8006f5c: bf00 nop
8006f5e: 372c adds r7, #44 @ 0x2c
8006f60: 46bd mov sp, r7
8006f62: bc80 pop {r7}
8006f64: 4770 bx lr
08006f66 <USB_ReadPMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
8006f66: b480 push {r7}
8006f68: b08b sub sp, #44 @ 0x2c
8006f6a: af00 add r7, sp, #0
8006f6c: 60f8 str r0, [r7, #12]
8006f6e: 60b9 str r1, [r7, #8]
8006f70: 4611 mov r1, r2
8006f72: 461a mov r2, r3
8006f74: 460b mov r3, r1
8006f76: 80fb strh r3, [r7, #6]
8006f78: 4613 mov r3, r2
8006f7a: 80bb strh r3, [r7, #4]
uint32_t n = (uint32_t)wNBytes >> 1;
8006f7c: 88bb ldrh r3, [r7, #4]
8006f7e: 085b lsrs r3, r3, #1
8006f80: b29b uxth r3, r3
8006f82: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
8006f84: 68fb ldr r3, [r7, #12]
8006f86: 617b str r3, [r7, #20]
uint32_t count;
uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
8006f88: 68bb ldr r3, [r7, #8]
8006f8a: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
8006f8c: 88fb ldrh r3, [r7, #6]
8006f8e: 005a lsls r2, r3, #1
8006f90: 697b ldr r3, [r7, #20]
8006f92: 4413 add r3, r2
8006f94: f503 6380 add.w r3, r3, #1024 @ 0x400
8006f98: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
8006f9a: 69bb ldr r3, [r7, #24]
8006f9c: 627b str r3, [r7, #36] @ 0x24
8006f9e: e01b b.n 8006fd8 <USB_ReadPMA+0x72>
{
RdVal = *(__IO uint16_t *)pdwVal;
8006fa0: 6a3b ldr r3, [r7, #32]
8006fa2: 881b ldrh r3, [r3, #0]
8006fa4: b29b uxth r3, r3
8006fa6: 613b str r3, [r7, #16]
pdwVal++;
8006fa8: 6a3b ldr r3, [r7, #32]
8006faa: 3302 adds r3, #2
8006fac: 623b str r3, [r7, #32]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
8006fae: 693b ldr r3, [r7, #16]
8006fb0: b2da uxtb r2, r3
8006fb2: 69fb ldr r3, [r7, #28]
8006fb4: 701a strb r2, [r3, #0]
pBuf++;
8006fb6: 69fb ldr r3, [r7, #28]
8006fb8: 3301 adds r3, #1
8006fba: 61fb str r3, [r7, #28]
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
8006fbc: 693b ldr r3, [r7, #16]
8006fbe: 0a1b lsrs r3, r3, #8
8006fc0: b2da uxtb r2, r3
8006fc2: 69fb ldr r3, [r7, #28]
8006fc4: 701a strb r2, [r3, #0]
pBuf++;
8006fc6: 69fb ldr r3, [r7, #28]
8006fc8: 3301 adds r3, #1
8006fca: 61fb str r3, [r7, #28]
#if PMA_ACCESS > 1U
pdwVal++;
8006fcc: 6a3b ldr r3, [r7, #32]
8006fce: 3302 adds r3, #2
8006fd0: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
8006fd2: 6a7b ldr r3, [r7, #36] @ 0x24
8006fd4: 3b01 subs r3, #1
8006fd6: 627b str r3, [r7, #36] @ 0x24
8006fd8: 6a7b ldr r3, [r7, #36] @ 0x24
8006fda: 2b00 cmp r3, #0
8006fdc: d1e0 bne.n 8006fa0 <USB_ReadPMA+0x3a>
#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
8006fde: 88bb ldrh r3, [r7, #4]
8006fe0: f003 0301 and.w r3, r3, #1
8006fe4: b29b uxth r3, r3
8006fe6: 2b00 cmp r3, #0
8006fe8: d007 beq.n 8006ffa <USB_ReadPMA+0x94>
{
RdVal = *pdwVal;
8006fea: 6a3b ldr r3, [r7, #32]
8006fec: 881b ldrh r3, [r3, #0]
8006fee: b29b uxth r3, r3
8006ff0: 613b str r3, [r7, #16]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
8006ff2: 693b ldr r3, [r7, #16]
8006ff4: b2da uxtb r2, r3
8006ff6: 69fb ldr r3, [r7, #28]
8006ff8: 701a strb r2, [r3, #0]
}
}
8006ffa: bf00 nop
8006ffc: 372c adds r7, #44 @ 0x2c
8006ffe: 46bd mov sp, r7
8007000: bc80 pop {r7}
8007002: 4770 bx lr
08007004 <USBD_CDC_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8007004: b580 push {r7, lr}
8007006: b084 sub sp, #16
8007008: af00 add r7, sp, #0
800700a: 6078 str r0, [r7, #4]
800700c: 460b mov r3, r1
800700e: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
8007010: 2300 movs r3, #0
8007012: 73fb strb r3, [r7, #15]
USBD_CDC_HandleTypeDef *hcdc;
if (pdev->dev_speed == USBD_SPEED_HIGH)
8007014: 687b ldr r3, [r7, #4]
8007016: 7c1b ldrb r3, [r3, #16]
8007018: 2b00 cmp r3, #0
800701a: d115 bne.n 8007048 <USBD_CDC_Init+0x44>
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
800701c: f44f 7300 mov.w r3, #512 @ 0x200
8007020: 2202 movs r2, #2
8007022: 2181 movs r1, #129 @ 0x81
8007024: 6878 ldr r0, [r7, #4]
8007026: f001 ff00 bl 8008e2a <USBD_LL_OpenEP>
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
800702a: 687b ldr r3, [r7, #4]
800702c: 2201 movs r2, #1
800702e: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
8007030: f44f 7300 mov.w r3, #512 @ 0x200
8007034: 2202 movs r2, #2
8007036: 2101 movs r1, #1
8007038: 6878 ldr r0, [r7, #4]
800703a: f001 fef6 bl 8008e2a <USBD_LL_OpenEP>
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
800703e: 687b ldr r3, [r7, #4]
8007040: 2201 movs r2, #1
8007042: f8c3 216c str.w r2, [r3, #364] @ 0x16c
8007046: e012 b.n 800706e <USBD_CDC_Init+0x6a>
}
else
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
8007048: 2340 movs r3, #64 @ 0x40
800704a: 2202 movs r2, #2
800704c: 2181 movs r1, #129 @ 0x81
800704e: 6878 ldr r0, [r7, #4]
8007050: f001 feeb bl 8008e2a <USBD_LL_OpenEP>
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
8007054: 687b ldr r3, [r7, #4]
8007056: 2201 movs r2, #1
8007058: 62da str r2, [r3, #44] @ 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
800705a: 2340 movs r3, #64 @ 0x40
800705c: 2202 movs r2, #2
800705e: 2101 movs r1, #1
8007060: 6878 ldr r0, [r7, #4]
8007062: f001 fee2 bl 8008e2a <USBD_LL_OpenEP>
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
8007066: 687b ldr r3, [r7, #4]
8007068: 2201 movs r2, #1
800706a: f8c3 216c str.w r2, [r3, #364] @ 0x16c
}
/* Open Command IN EP */
USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
800706e: 2308 movs r3, #8
8007070: 2203 movs r2, #3
8007072: 2182 movs r1, #130 @ 0x82
8007074: 6878 ldr r0, [r7, #4]
8007076: f001 fed8 bl 8008e2a <USBD_LL_OpenEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
800707a: 687b ldr r3, [r7, #4]
800707c: 2201 movs r2, #1
800707e: 641a str r2, [r3, #64] @ 0x40
pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
8007080: f44f 7007 mov.w r0, #540 @ 0x21c
8007084: f001 fff8 bl 8009078 <USBD_static_malloc>
8007088: 4602 mov r2, r0
800708a: 687b ldr r3, [r7, #4]
800708c: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClassData == NULL)
8007090: 687b ldr r3, [r7, #4]
8007092: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8007096: 2b00 cmp r3, #0
8007098: d102 bne.n 80070a0 <USBD_CDC_Init+0x9c>
{
ret = 1U;
800709a: 2301 movs r3, #1
800709c: 73fb strb r3, [r7, #15]
800709e: e026 b.n 80070ee <USBD_CDC_Init+0xea>
}
else
{
hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80070a0: 687b ldr r3, [r7, #4]
80070a2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80070a6: 60bb str r3, [r7, #8]
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
80070a8: 687b ldr r3, [r7, #4]
80070aa: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80070ae: 681b ldr r3, [r3, #0]
80070b0: 4798 blx r3
/* Init Xfer states */
hcdc->TxState = 0U;
80070b2: 68bb ldr r3, [r7, #8]
80070b4: 2200 movs r2, #0
80070b6: f8c3 2214 str.w r2, [r3, #532] @ 0x214
hcdc->RxState = 0U;
80070ba: 68bb ldr r3, [r7, #8]
80070bc: 2200 movs r2, #0
80070be: f8c3 2218 str.w r2, [r3, #536] @ 0x218
if (pdev->dev_speed == USBD_SPEED_HIGH)
80070c2: 687b ldr r3, [r7, #4]
80070c4: 7c1b ldrb r3, [r3, #16]
80070c6: 2b00 cmp r3, #0
80070c8: d109 bne.n 80070de <USBD_CDC_Init+0xda>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
80070ca: 68bb ldr r3, [r7, #8]
80070cc: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80070d0: f44f 7300 mov.w r3, #512 @ 0x200
80070d4: 2101 movs r1, #1
80070d6: 6878 ldr r0, [r7, #4]
80070d8: f001 ff97 bl 800900a <USBD_LL_PrepareReceive>
80070dc: e007 b.n 80070ee <USBD_CDC_Init+0xea>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
80070de: 68bb ldr r3, [r7, #8]
80070e0: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80070e4: 2340 movs r3, #64 @ 0x40
80070e6: 2101 movs r1, #1
80070e8: 6878 ldr r0, [r7, #4]
80070ea: f001 ff8e bl 800900a <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
}
return ret;
80070ee: 7bfb ldrb r3, [r7, #15]
}
80070f0: 4618 mov r0, r3
80070f2: 3710 adds r7, #16
80070f4: 46bd mov sp, r7
80070f6: bd80 pop {r7, pc}
080070f8 <USBD_CDC_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80070f8: b580 push {r7, lr}
80070fa: b084 sub sp, #16
80070fc: af00 add r7, sp, #0
80070fe: 6078 str r0, [r7, #4]
8007100: 460b mov r3, r1
8007102: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
8007104: 2300 movs r3, #0
8007106: 73fb strb r3, [r7, #15]
/* Close EP IN */
USBD_LL_CloseEP(pdev, CDC_IN_EP);
8007108: 2181 movs r1, #129 @ 0x81
800710a: 6878 ldr r0, [r7, #4]
800710c: f001 feb3 bl 8008e76 <USBD_LL_CloseEP>
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
8007110: 687b ldr r3, [r7, #4]
8007112: 2200 movs r2, #0
8007114: 62da str r2, [r3, #44] @ 0x2c
/* Close EP OUT */
USBD_LL_CloseEP(pdev, CDC_OUT_EP);
8007116: 2101 movs r1, #1
8007118: 6878 ldr r0, [r7, #4]
800711a: f001 feac bl 8008e76 <USBD_LL_CloseEP>
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
800711e: 687b ldr r3, [r7, #4]
8007120: 2200 movs r2, #0
8007122: f8c3 216c str.w r2, [r3, #364] @ 0x16c
/* Close Command IN EP */
USBD_LL_CloseEP(pdev, CDC_CMD_EP);
8007126: 2182 movs r1, #130 @ 0x82
8007128: 6878 ldr r0, [r7, #4]
800712a: f001 fea4 bl 8008e76 <USBD_LL_CloseEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
800712e: 687b ldr r3, [r7, #4]
8007130: 2200 movs r2, #0
8007132: 641a str r2, [r3, #64] @ 0x40
/* DeInit physical Interface components */
if (pdev->pClassData != NULL)
8007134: 687b ldr r3, [r7, #4]
8007136: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800713a: 2b00 cmp r3, #0
800713c: d00e beq.n 800715c <USBD_CDC_DeInit+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
800713e: 687b ldr r3, [r7, #4]
8007140: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8007144: 685b ldr r3, [r3, #4]
8007146: 4798 blx r3
USBD_free(pdev->pClassData);
8007148: 687b ldr r3, [r7, #4]
800714a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800714e: 4618 mov r0, r3
8007150: f001 ff9e bl 8009090 <USBD_static_free>
pdev->pClassData = NULL;
8007154: 687b ldr r3, [r7, #4]
8007156: 2200 movs r2, #0
8007158: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
}
return ret;
800715c: 7bfb ldrb r3, [r7, #15]
}
800715e: 4618 mov r0, r3
8007160: 3710 adds r7, #16
8007162: 46bd mov sp, r7
8007164: bd80 pop {r7, pc}
08007166 <USBD_CDC_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8007166: b580 push {r7, lr}
8007168: b086 sub sp, #24
800716a: af00 add r7, sp, #0
800716c: 6078 str r0, [r7, #4]
800716e: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8007170: 687b ldr r3, [r7, #4]
8007172: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8007176: 613b str r3, [r7, #16]
uint8_t ifalt = 0U;
8007178: 2300 movs r3, #0
800717a: 73fb strb r3, [r7, #15]
uint16_t status_info = 0U;
800717c: 2300 movs r3, #0
800717e: 81bb strh r3, [r7, #12]
uint8_t ret = USBD_OK;
8007180: 2300 movs r3, #0
8007182: 75fb strb r3, [r7, #23]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8007184: 683b ldr r3, [r7, #0]
8007186: 781b ldrb r3, [r3, #0]
8007188: f003 0360 and.w r3, r3, #96 @ 0x60
800718c: 2b00 cmp r3, #0
800718e: d039 beq.n 8007204 <USBD_CDC_Setup+0x9e>
8007190: 2b20 cmp r3, #32
8007192: d17f bne.n 8007294 <USBD_CDC_Setup+0x12e>
{
case USB_REQ_TYPE_CLASS :
if (req->wLength)
8007194: 683b ldr r3, [r7, #0]
8007196: 88db ldrh r3, [r3, #6]
8007198: 2b00 cmp r3, #0
800719a: d029 beq.n 80071f0 <USBD_CDC_Setup+0x8a>
{
if (req->bmRequest & 0x80U)
800719c: 683b ldr r3, [r7, #0]
800719e: 781b ldrb r3, [r3, #0]
80071a0: b25b sxtb r3, r3
80071a2: 2b00 cmp r3, #0
80071a4: da11 bge.n 80071ca <USBD_CDC_Setup+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80071a6: 687b ldr r3, [r7, #4]
80071a8: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80071ac: 689b ldr r3, [r3, #8]
80071ae: 683a ldr r2, [r7, #0]
80071b0: 7850 ldrb r0, [r2, #1]
(uint8_t *)(void *)hcdc->data,
80071b2: 6939 ldr r1, [r7, #16]
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80071b4: 683a ldr r2, [r7, #0]
80071b6: 88d2 ldrh r2, [r2, #6]
80071b8: 4798 blx r3
req->wLength);
USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
80071ba: 6939 ldr r1, [r7, #16]
80071bc: 683b ldr r3, [r7, #0]
80071be: 88db ldrh r3, [r3, #6]
80071c0: 461a mov r2, r3
80071c2: 6878 ldr r0, [r7, #4]
80071c4: f001 fa06 bl 80085d4 <USBD_CtlSendData>
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
(uint8_t *)(void *)req, 0U);
}
break;
80071c8: e06b b.n 80072a2 <USBD_CDC_Setup+0x13c>
hcdc->CmdOpCode = req->bRequest;
80071ca: 683b ldr r3, [r7, #0]
80071cc: 785a ldrb r2, [r3, #1]
80071ce: 693b ldr r3, [r7, #16]
80071d0: f883 2200 strb.w r2, [r3, #512] @ 0x200
hcdc->CmdLength = (uint8_t)req->wLength;
80071d4: 683b ldr r3, [r7, #0]
80071d6: 88db ldrh r3, [r3, #6]
80071d8: b2da uxtb r2, r3
80071da: 693b ldr r3, [r7, #16]
80071dc: f883 2201 strb.w r2, [r3, #513] @ 0x201
USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
80071e0: 6939 ldr r1, [r7, #16]
80071e2: 683b ldr r3, [r7, #0]
80071e4: 88db ldrh r3, [r3, #6]
80071e6: 461a mov r2, r3
80071e8: 6878 ldr r0, [r7, #4]
80071ea: f001 fa21 bl 8008630 <USBD_CtlPrepareRx>
break;
80071ee: e058 b.n 80072a2 <USBD_CDC_Setup+0x13c>
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80071f0: 687b ldr r3, [r7, #4]
80071f2: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80071f6: 689b ldr r3, [r3, #8]
80071f8: 683a ldr r2, [r7, #0]
80071fa: 7850 ldrb r0, [r2, #1]
80071fc: 2200 movs r2, #0
80071fe: 6839 ldr r1, [r7, #0]
8007200: 4798 blx r3
break;
8007202: e04e b.n 80072a2 <USBD_CDC_Setup+0x13c>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8007204: 683b ldr r3, [r7, #0]
8007206: 785b ldrb r3, [r3, #1]
8007208: 2b0b cmp r3, #11
800720a: d02e beq.n 800726a <USBD_CDC_Setup+0x104>
800720c: 2b0b cmp r3, #11
800720e: dc38 bgt.n 8007282 <USBD_CDC_Setup+0x11c>
8007210: 2b00 cmp r3, #0
8007212: d002 beq.n 800721a <USBD_CDC_Setup+0xb4>
8007214: 2b0a cmp r3, #10
8007216: d014 beq.n 8007242 <USBD_CDC_Setup+0xdc>
8007218: e033 b.n 8007282 <USBD_CDC_Setup+0x11c>
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800721a: 687b ldr r3, [r7, #4]
800721c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007220: 2b03 cmp r3, #3
8007222: d107 bne.n 8007234 <USBD_CDC_Setup+0xce>
{
USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
8007224: f107 030c add.w r3, r7, #12
8007228: 2202 movs r2, #2
800722a: 4619 mov r1, r3
800722c: 6878 ldr r0, [r7, #4]
800722e: f001 f9d1 bl 80085d4 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
8007232: e02e b.n 8007292 <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
8007234: 6839 ldr r1, [r7, #0]
8007236: 6878 ldr r0, [r7, #4]
8007238: f001 f962 bl 8008500 <USBD_CtlError>
ret = USBD_FAIL;
800723c: 2302 movs r3, #2
800723e: 75fb strb r3, [r7, #23]
break;
8007240: e027 b.n 8007292 <USBD_CDC_Setup+0x12c>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8007242: 687b ldr r3, [r7, #4]
8007244: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007248: 2b03 cmp r3, #3
800724a: d107 bne.n 800725c <USBD_CDC_Setup+0xf6>
{
USBD_CtlSendData(pdev, &ifalt, 1U);
800724c: f107 030f add.w r3, r7, #15
8007250: 2201 movs r2, #1
8007252: 4619 mov r1, r3
8007254: 6878 ldr r0, [r7, #4]
8007256: f001 f9bd bl 80085d4 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800725a: e01a b.n 8007292 <USBD_CDC_Setup+0x12c>
USBD_CtlError(pdev, req);
800725c: 6839 ldr r1, [r7, #0]
800725e: 6878 ldr r0, [r7, #4]
8007260: f001 f94e bl 8008500 <USBD_CtlError>
ret = USBD_FAIL;
8007264: 2302 movs r3, #2
8007266: 75fb strb r3, [r7, #23]
break;
8007268: e013 b.n 8007292 <USBD_CDC_Setup+0x12c>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
800726a: 687b ldr r3, [r7, #4]
800726c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007270: 2b03 cmp r3, #3
8007272: d00d beq.n 8007290 <USBD_CDC_Setup+0x12a>
{
USBD_CtlError(pdev, req);
8007274: 6839 ldr r1, [r7, #0]
8007276: 6878 ldr r0, [r7, #4]
8007278: f001 f942 bl 8008500 <USBD_CtlError>
ret = USBD_FAIL;
800727c: 2302 movs r3, #2
800727e: 75fb strb r3, [r7, #23]
}
break;
8007280: e006 b.n 8007290 <USBD_CDC_Setup+0x12a>
default:
USBD_CtlError(pdev, req);
8007282: 6839 ldr r1, [r7, #0]
8007284: 6878 ldr r0, [r7, #4]
8007286: f001 f93b bl 8008500 <USBD_CtlError>
ret = USBD_FAIL;
800728a: 2302 movs r3, #2
800728c: 75fb strb r3, [r7, #23]
break;
800728e: e000 b.n 8007292 <USBD_CDC_Setup+0x12c>
break;
8007290: bf00 nop
}
break;
8007292: e006 b.n 80072a2 <USBD_CDC_Setup+0x13c>
default:
USBD_CtlError(pdev, req);
8007294: 6839 ldr r1, [r7, #0]
8007296: 6878 ldr r0, [r7, #4]
8007298: f001 f932 bl 8008500 <USBD_CtlError>
ret = USBD_FAIL;
800729c: 2302 movs r3, #2
800729e: 75fb strb r3, [r7, #23]
break;
80072a0: bf00 nop
}
return ret;
80072a2: 7dfb ldrb r3, [r7, #23]
}
80072a4: 4618 mov r0, r3
80072a6: 3718 adds r7, #24
80072a8: 46bd mov sp, r7
80072aa: bd80 pop {r7, pc}
080072ac <USBD_CDC_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
80072ac: b580 push {r7, lr}
80072ae: b084 sub sp, #16
80072b0: af00 add r7, sp, #0
80072b2: 6078 str r0, [r7, #4]
80072b4: 460b mov r3, r1
80072b6: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
80072b8: 687b ldr r3, [r7, #4]
80072ba: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80072be: 60fb str r3, [r7, #12]
PCD_HandleTypeDef *hpcd = pdev->pData;
80072c0: 687b ldr r3, [r7, #4]
80072c2: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
80072c6: 60bb str r3, [r7, #8]
if (pdev->pClassData != NULL)
80072c8: 687b ldr r3, [r7, #4]
80072ca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80072ce: 2b00 cmp r3, #0
80072d0: d03a beq.n 8007348 <USBD_CDC_DataIn+0x9c>
{
if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
80072d2: 78fa ldrb r2, [r7, #3]
80072d4: 6879 ldr r1, [r7, #4]
80072d6: 4613 mov r3, r2
80072d8: 009b lsls r3, r3, #2
80072da: 4413 add r3, r2
80072dc: 009b lsls r3, r3, #2
80072de: 440b add r3, r1
80072e0: 331c adds r3, #28
80072e2: 681b ldr r3, [r3, #0]
80072e4: 2b00 cmp r3, #0
80072e6: d029 beq.n 800733c <USBD_CDC_DataIn+0x90>
80072e8: 78fa ldrb r2, [r7, #3]
80072ea: 6879 ldr r1, [r7, #4]
80072ec: 4613 mov r3, r2
80072ee: 009b lsls r3, r3, #2
80072f0: 4413 add r3, r2
80072f2: 009b lsls r3, r3, #2
80072f4: 440b add r3, r1
80072f6: 331c adds r3, #28
80072f8: 681a ldr r2, [r3, #0]
80072fa: 78f9 ldrb r1, [r7, #3]
80072fc: 68b8 ldr r0, [r7, #8]
80072fe: 460b mov r3, r1
8007300: 009b lsls r3, r3, #2
8007302: 440b add r3, r1
8007304: 00db lsls r3, r3, #3
8007306: 4403 add r3, r0
8007308: 3320 adds r3, #32
800730a: 681b ldr r3, [r3, #0]
800730c: fbb2 f1f3 udiv r1, r2, r3
8007310: fb01 f303 mul.w r3, r1, r3
8007314: 1ad3 subs r3, r2, r3
8007316: 2b00 cmp r3, #0
8007318: d110 bne.n 800733c <USBD_CDC_DataIn+0x90>
{
/* Update the packet total length */
pdev->ep_in[epnum].total_length = 0U;
800731a: 78fa ldrb r2, [r7, #3]
800731c: 6879 ldr r1, [r7, #4]
800731e: 4613 mov r3, r2
8007320: 009b lsls r3, r3, #2
8007322: 4413 add r3, r2
8007324: 009b lsls r3, r3, #2
8007326: 440b add r3, r1
8007328: 331c adds r3, #28
800732a: 2200 movs r2, #0
800732c: 601a str r2, [r3, #0]
/* Send ZLP */
USBD_LL_Transmit(pdev, epnum, NULL, 0U);
800732e: 78f9 ldrb r1, [r7, #3]
8007330: 2300 movs r3, #0
8007332: 2200 movs r2, #0
8007334: 6878 ldr r0, [r7, #4]
8007336: f001 fe45 bl 8008fc4 <USBD_LL_Transmit>
800733a: e003 b.n 8007344 <USBD_CDC_DataIn+0x98>
}
else
{
hcdc->TxState = 0U;
800733c: 68fb ldr r3, [r7, #12]
800733e: 2200 movs r2, #0
8007340: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
return USBD_OK;
8007344: 2300 movs r3, #0
8007346: e000 b.n 800734a <USBD_CDC_DataIn+0x9e>
}
else
{
return USBD_FAIL;
8007348: 2302 movs r3, #2
}
}
800734a: 4618 mov r0, r3
800734c: 3710 adds r7, #16
800734e: 46bd mov sp, r7
8007350: bd80 pop {r7, pc}
08007352 <USBD_CDC_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
8007352: b580 push {r7, lr}
8007354: b084 sub sp, #16
8007356: af00 add r7, sp, #0
8007358: 6078 str r0, [r7, #4]
800735a: 460b mov r3, r1
800735c: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800735e: 687b ldr r3, [r7, #4]
8007360: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8007364: 60fb str r3, [r7, #12]
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
8007366: 78fb ldrb r3, [r7, #3]
8007368: 4619 mov r1, r3
800736a: 6878 ldr r0, [r7, #4]
800736c: f001 fe70 bl 8009050 <USBD_LL_GetRxDataSize>
8007370: 4602 mov r2, r0
8007372: 68fb ldr r3, [r7, #12]
8007374: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
if (pdev->pClassData != NULL)
8007378: 687b ldr r3, [r7, #4]
800737a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800737e: 2b00 cmp r3, #0
8007380: d00d beq.n 800739e <USBD_CDC_DataOut+0x4c>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
8007382: 687b ldr r3, [r7, #4]
8007384: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8007388: 68db ldr r3, [r3, #12]
800738a: 68fa ldr r2, [r7, #12]
800738c: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
8007390: 68fa ldr r2, [r7, #12]
8007392: f502 7203 add.w r2, r2, #524 @ 0x20c
8007396: 4611 mov r1, r2
8007398: 4798 blx r3
return USBD_OK;
800739a: 2300 movs r3, #0
800739c: e000 b.n 80073a0 <USBD_CDC_DataOut+0x4e>
}
else
{
return USBD_FAIL;
800739e: 2302 movs r3, #2
}
}
80073a0: 4618 mov r0, r3
80073a2: 3710 adds r7, #16
80073a4: 46bd mov sp, r7
80073a6: bd80 pop {r7, pc}
080073a8 <USBD_CDC_EP0_RxReady>:
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
80073a8: b580 push {r7, lr}
80073aa: b084 sub sp, #16
80073ac: af00 add r7, sp, #0
80073ae: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80073b0: 687b ldr r3, [r7, #4]
80073b2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80073b6: 60fb str r3, [r7, #12]
if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
80073b8: 687b ldr r3, [r7, #4]
80073ba: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80073be: 2b00 cmp r3, #0
80073c0: d014 beq.n 80073ec <USBD_CDC_EP0_RxReady+0x44>
80073c2: 68fb ldr r3, [r7, #12]
80073c4: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
80073c8: 2bff cmp r3, #255 @ 0xff
80073ca: d00f beq.n 80073ec <USBD_CDC_EP0_RxReady+0x44>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
80073cc: 687b ldr r3, [r7, #4]
80073ce: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
80073d2: 689b ldr r3, [r3, #8]
80073d4: 68fa ldr r2, [r7, #12]
80073d6: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
(uint8_t *)(void *)hcdc->data,
80073da: 68f9 ldr r1, [r7, #12]
(uint16_t)hcdc->CmdLength);
80073dc: 68fa ldr r2, [r7, #12]
80073de: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
80073e2: 4798 blx r3
hcdc->CmdOpCode = 0xFFU;
80073e4: 68fb ldr r3, [r7, #12]
80073e6: 22ff movs r2, #255 @ 0xff
80073e8: f883 2200 strb.w r2, [r3, #512] @ 0x200
}
return USBD_OK;
80073ec: 2300 movs r3, #0
}
80073ee: 4618 mov r0, r3
80073f0: 3710 adds r7, #16
80073f2: 46bd mov sp, r7
80073f4: bd80 pop {r7, pc}
...
080073f8 <USBD_CDC_GetFSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
80073f8: b480 push {r7}
80073fa: b083 sub sp, #12
80073fc: af00 add r7, sp, #0
80073fe: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgFSDesc);
8007400: 687b ldr r3, [r7, #4]
8007402: 2243 movs r2, #67 @ 0x43
8007404: 801a strh r2, [r3, #0]
return USBD_CDC_CfgFSDesc;
8007406: 4b03 ldr r3, [pc, #12] @ (8007414 <USBD_CDC_GetFSCfgDesc+0x1c>)
}
8007408: 4618 mov r0, r3
800740a: 370c adds r7, #12
800740c: 46bd mov sp, r7
800740e: bc80 pop {r7}
8007410: 4770 bx lr
8007412: bf00 nop
8007414: 20000094 .word 0x20000094
08007418 <USBD_CDC_GetHSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
8007418: b480 push {r7}
800741a: b083 sub sp, #12
800741c: af00 add r7, sp, #0
800741e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgHSDesc);
8007420: 687b ldr r3, [r7, #4]
8007422: 2243 movs r2, #67 @ 0x43
8007424: 801a strh r2, [r3, #0]
return USBD_CDC_CfgHSDesc;
8007426: 4b03 ldr r3, [pc, #12] @ (8007434 <USBD_CDC_GetHSCfgDesc+0x1c>)
}
8007428: 4618 mov r0, r3
800742a: 370c adds r7, #12
800742c: 46bd mov sp, r7
800742e: bc80 pop {r7}
8007430: 4770 bx lr
8007432: bf00 nop
8007434: 20000050 .word 0x20000050
08007438 <USBD_CDC_GetOtherSpeedCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
8007438: b480 push {r7}
800743a: b083 sub sp, #12
800743c: af00 add r7, sp, #0
800743e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_OtherSpeedCfgDesc);
8007440: 687b ldr r3, [r7, #4]
8007442: 2243 movs r2, #67 @ 0x43
8007444: 801a strh r2, [r3, #0]
return USBD_CDC_OtherSpeedCfgDesc;
8007446: 4b03 ldr r3, [pc, #12] @ (8007454 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
}
8007448: 4618 mov r0, r3
800744a: 370c adds r7, #12
800744c: 46bd mov sp, r7
800744e: bc80 pop {r7}
8007450: 4770 bx lr
8007452: bf00 nop
8007454: 200000d8 .word 0x200000d8
08007458 <USBD_CDC_GetDeviceQualifierDescriptor>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
8007458: b480 push {r7}
800745a: b083 sub sp, #12
800745c: af00 add r7, sp, #0
800745e: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_DeviceQualifierDesc);
8007460: 687b ldr r3, [r7, #4]
8007462: 220a movs r2, #10
8007464: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceQualifierDesc;
8007466: 4b03 ldr r3, [pc, #12] @ (8007474 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
}
8007468: 4618 mov r0, r3
800746a: 370c adds r7, #12
800746c: 46bd mov sp, r7
800746e: bc80 pop {r7}
8007470: 4770 bx lr
8007472: bf00 nop
8007474: 2000000c .word 0x2000000c
08007478 <USBD_CDC_RegisterInterface>:
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
8007478: b480 push {r7}
800747a: b085 sub sp, #20
800747c: af00 add r7, sp, #0
800747e: 6078 str r0, [r7, #4]
8007480: 6039 str r1, [r7, #0]
uint8_t ret = USBD_FAIL;
8007482: 2302 movs r3, #2
8007484: 73fb strb r3, [r7, #15]
if (fops != NULL)
8007486: 683b ldr r3, [r7, #0]
8007488: 2b00 cmp r3, #0
800748a: d005 beq.n 8007498 <USBD_CDC_RegisterInterface+0x20>
{
pdev->pUserData = fops;
800748c: 687b ldr r3, [r7, #4]
800748e: 683a ldr r2, [r7, #0]
8007490: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
ret = USBD_OK;
8007494: 2300 movs r3, #0
8007496: 73fb strb r3, [r7, #15]
}
return ret;
8007498: 7bfb ldrb r3, [r7, #15]
}
800749a: 4618 mov r0, r3
800749c: 3714 adds r7, #20
800749e: 46bd mov sp, r7
80074a0: bc80 pop {r7}
80074a2: 4770 bx lr
080074a4 <USBD_CDC_SetTxBuffer>:
* @retval status
*/
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff,
uint16_t length)
{
80074a4: b480 push {r7}
80074a6: b087 sub sp, #28
80074a8: af00 add r7, sp, #0
80074aa: 60f8 str r0, [r7, #12]
80074ac: 60b9 str r1, [r7, #8]
80074ae: 4613 mov r3, r2
80074b0: 80fb strh r3, [r7, #6]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80074b2: 68fb ldr r3, [r7, #12]
80074b4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80074b8: 617b str r3, [r7, #20]
hcdc->TxBuffer = pbuff;
80074ba: 697b ldr r3, [r7, #20]
80074bc: 68ba ldr r2, [r7, #8]
80074be: f8c3 2208 str.w r2, [r3, #520] @ 0x208
hcdc->TxLength = length;
80074c2: 88fa ldrh r2, [r7, #6]
80074c4: 697b ldr r3, [r7, #20]
80074c6: f8c3 2210 str.w r2, [r3, #528] @ 0x210
return USBD_OK;
80074ca: 2300 movs r3, #0
}
80074cc: 4618 mov r0, r3
80074ce: 371c adds r7, #28
80074d0: 46bd mov sp, r7
80074d2: bc80 pop {r7}
80074d4: 4770 bx lr
080074d6 <USBD_CDC_SetRxBuffer>:
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff)
{
80074d6: b480 push {r7}
80074d8: b085 sub sp, #20
80074da: af00 add r7, sp, #0
80074dc: 6078 str r0, [r7, #4]
80074de: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80074e0: 687b ldr r3, [r7, #4]
80074e2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80074e6: 60fb str r3, [r7, #12]
hcdc->RxBuffer = pbuff;
80074e8: 68fb ldr r3, [r7, #12]
80074ea: 683a ldr r2, [r7, #0]
80074ec: f8c3 2204 str.w r2, [r3, #516] @ 0x204
return USBD_OK;
80074f0: 2300 movs r3, #0
}
80074f2: 4618 mov r0, r3
80074f4: 3714 adds r7, #20
80074f6: 46bd mov sp, r7
80074f8: bc80 pop {r7}
80074fa: 4770 bx lr
080074fc <USBD_CDC_TransmitPacket>:
* Transmit packet on IN endpoint
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
80074fc: b580 push {r7, lr}
80074fe: b084 sub sp, #16
8007500: af00 add r7, sp, #0
8007502: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8007504: 687b ldr r3, [r7, #4]
8007506: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800750a: 60fb str r3, [r7, #12]
if (pdev->pClassData != NULL)
800750c: 687b ldr r3, [r7, #4]
800750e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8007512: 2b00 cmp r3, #0
8007514: d01c beq.n 8007550 <USBD_CDC_TransmitPacket+0x54>
{
if (hcdc->TxState == 0U)
8007516: 68fb ldr r3, [r7, #12]
8007518: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800751c: 2b00 cmp r3, #0
800751e: d115 bne.n 800754c <USBD_CDC_TransmitPacket+0x50>
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
8007520: 68fb ldr r3, [r7, #12]
8007522: 2201 movs r2, #1
8007524: f8c3 2214 str.w r2, [r3, #532] @ 0x214
/* Update the packet total length */
pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
8007528: 68fb ldr r3, [r7, #12]
800752a: f8d3 2210 ldr.w r2, [r3, #528] @ 0x210
800752e: 687b ldr r3, [r7, #4]
8007530: 631a str r2, [r3, #48] @ 0x30
/* Transmit next packet */
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
8007532: 68fb ldr r3, [r7, #12]
8007534: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
(uint16_t)hcdc->TxLength);
8007538: 68fb ldr r3, [r7, #12]
800753a: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
800753e: b29b uxth r3, r3
8007540: 2181 movs r1, #129 @ 0x81
8007542: 6878 ldr r0, [r7, #4]
8007544: f001 fd3e bl 8008fc4 <USBD_LL_Transmit>
return USBD_OK;
8007548: 2300 movs r3, #0
800754a: e002 b.n 8007552 <USBD_CDC_TransmitPacket+0x56>
}
else
{
return USBD_BUSY;
800754c: 2301 movs r3, #1
800754e: e000 b.n 8007552 <USBD_CDC_TransmitPacket+0x56>
}
}
else
{
return USBD_FAIL;
8007550: 2302 movs r3, #2
}
}
8007552: 4618 mov r0, r3
8007554: 3710 adds r7, #16
8007556: 46bd mov sp, r7
8007558: bd80 pop {r7, pc}
0800755a <USBD_CDC_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
800755a: b580 push {r7, lr}
800755c: b084 sub sp, #16
800755e: af00 add r7, sp, #0
8007560: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8007562: 687b ldr r3, [r7, #4]
8007564: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8007568: 60fb str r3, [r7, #12]
/* Suspend or Resume USB Out process */
if (pdev->pClassData != NULL)
800756a: 687b ldr r3, [r7, #4]
800756c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8007570: 2b00 cmp r3, #0
8007572: d017 beq.n 80075a4 <USBD_CDC_ReceivePacket+0x4a>
{
if (pdev->dev_speed == USBD_SPEED_HIGH)
8007574: 687b ldr r3, [r7, #4]
8007576: 7c1b ldrb r3, [r3, #16]
8007578: 2b00 cmp r3, #0
800757a: d109 bne.n 8007590 <USBD_CDC_ReceivePacket+0x36>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
800757c: 68fb ldr r3, [r7, #12]
800757e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8007582: f44f 7300 mov.w r3, #512 @ 0x200
8007586: 2101 movs r1, #1
8007588: 6878 ldr r0, [r7, #4]
800758a: f001 fd3e bl 800900a <USBD_LL_PrepareReceive>
800758e: e007 b.n 80075a0 <USBD_CDC_ReceivePacket+0x46>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
8007590: 68fb ldr r3, [r7, #12]
8007592: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8007596: 2340 movs r3, #64 @ 0x40
8007598: 2101 movs r1, #1
800759a: 6878 ldr r0, [r7, #4]
800759c: f001 fd35 bl 800900a <USBD_LL_PrepareReceive>
CDC_OUT_EP,
hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return USBD_OK;
80075a0: 2300 movs r3, #0
80075a2: e000 b.n 80075a6 <USBD_CDC_ReceivePacket+0x4c>
}
else
{
return USBD_FAIL;
80075a4: 2302 movs r3, #2
}
}
80075a6: 4618 mov r0, r3
80075a8: 3710 adds r7, #16
80075aa: 46bd mov sp, r7
80075ac: bd80 pop {r7, pc}
080075ae <USBD_Init>:
* @param id: Low level core index
* @retval None
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
80075ae: b580 push {r7, lr}
80075b0: b084 sub sp, #16
80075b2: af00 add r7, sp, #0
80075b4: 60f8 str r0, [r7, #12]
80075b6: 60b9 str r1, [r7, #8]
80075b8: 4613 mov r3, r2
80075ba: 71fb strb r3, [r7, #7]
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
80075bc: 68fb ldr r3, [r7, #12]
80075be: 2b00 cmp r3, #0
80075c0: d101 bne.n 80075c6 <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif
return USBD_FAIL;
80075c2: 2302 movs r3, #2
80075c4: e01a b.n 80075fc <USBD_Init+0x4e>
}
/* Unlink previous class*/
if (pdev->pClass != NULL)
80075c6: 68fb ldr r3, [r7, #12]
80075c8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80075cc: 2b00 cmp r3, #0
80075ce: d003 beq.n 80075d8 <USBD_Init+0x2a>
{
pdev->pClass = NULL;
80075d0: 68fb ldr r3, [r7, #12]
80075d2: 2200 movs r2, #0
80075d4: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Assign USBD Descriptors */
if (pdesc != NULL)
80075d8: 68bb ldr r3, [r7, #8]
80075da: 2b00 cmp r3, #0
80075dc: d003 beq.n 80075e6 <USBD_Init+0x38>
{
pdev->pDesc = pdesc;
80075de: 68fb ldr r3, [r7, #12]
80075e0: 68ba ldr r2, [r7, #8]
80075e2: f8c3 22b0 str.w r2, [r3, #688] @ 0x2b0
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
80075e6: 68fb ldr r3, [r7, #12]
80075e8: 2201 movs r2, #1
80075ea: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
80075ee: 68fb ldr r3, [r7, #12]
80075f0: 79fa ldrb r2, [r7, #7]
80075f2: 701a strb r2, [r3, #0]
/* Initialize low level driver */
USBD_LL_Init(pdev);
80075f4: 68f8 ldr r0, [r7, #12]
80075f6: f001 fba3 bl 8008d40 <USBD_LL_Init>
return USBD_OK;
80075fa: 2300 movs r3, #0
}
80075fc: 4618 mov r0, r3
80075fe: 3710 adds r7, #16
8007600: 46bd mov sp, r7
8007602: bd80 pop {r7, pc}
08007604 <USBD_RegisterClass>:
* @param pDevice : Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
8007604: b480 push {r7}
8007606: b085 sub sp, #20
8007608: af00 add r7, sp, #0
800760a: 6078 str r0, [r7, #4]
800760c: 6039 str r1, [r7, #0]
USBD_StatusTypeDef status = USBD_OK;
800760e: 2300 movs r3, #0
8007610: 73fb strb r3, [r7, #15]
if (pclass != NULL)
8007612: 683b ldr r3, [r7, #0]
8007614: 2b00 cmp r3, #0
8007616: d006 beq.n 8007626 <USBD_RegisterClass+0x22>
{
/* link the class to the USB Device handle */
pdev->pClass = pclass;
8007618: 687b ldr r3, [r7, #4]
800761a: 683a ldr r2, [r7, #0]
800761c: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
status = USBD_OK;
8007620: 2300 movs r3, #0
8007622: 73fb strb r3, [r7, #15]
8007624: e001 b.n 800762a <USBD_RegisterClass+0x26>
else
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif
status = USBD_FAIL;
8007626: 2302 movs r3, #2
8007628: 73fb strb r3, [r7, #15]
}
return status;
800762a: 7bfb ldrb r3, [r7, #15]
}
800762c: 4618 mov r0, r3
800762e: 3714 adds r7, #20
8007630: 46bd mov sp, r7
8007632: bc80 pop {r7}
8007634: 4770 bx lr
08007636 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
8007636: b580 push {r7, lr}
8007638: b082 sub sp, #8
800763a: af00 add r7, sp, #0
800763c: 6078 str r0, [r7, #4]
/* Start the low level driver */
USBD_LL_Start(pdev);
800763e: 6878 ldr r0, [r7, #4]
8007640: f001 fbd8 bl 8008df4 <USBD_LL_Start>
return USBD_OK;
8007644: 2300 movs r3, #0
}
8007646: 4618 mov r0, r3
8007648: 3708 adds r7, #8
800764a: 46bd mov sp, r7
800764c: bd80 pop {r7, pc}
0800764e <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
800764e: b480 push {r7}
8007650: b083 sub sp, #12
8007652: af00 add r7, sp, #0
8007654: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
8007656: 2300 movs r3, #0
}
8007658: 4618 mov r0, r3
800765a: 370c adds r7, #12
800765c: 46bd mov sp, r7
800765e: bc80 pop {r7}
8007660: 4770 bx lr
08007662 <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
8007662: b580 push {r7, lr}
8007664: b084 sub sp, #16
8007666: af00 add r7, sp, #0
8007668: 6078 str r0, [r7, #4]
800766a: 460b mov r3, r1
800766c: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_FAIL;
800766e: 2302 movs r3, #2
8007670: 73fb strb r3, [r7, #15]
if (pdev->pClass != NULL)
8007672: 687b ldr r3, [r7, #4]
8007674: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007678: 2b00 cmp r3, #0
800767a: d00c beq.n 8007696 <USBD_SetClassConfig+0x34>
{
/* Set configuration and Start the Class*/
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
800767c: 687b ldr r3, [r7, #4]
800767e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007682: 681b ldr r3, [r3, #0]
8007684: 78fa ldrb r2, [r7, #3]
8007686: 4611 mov r1, r2
8007688: 6878 ldr r0, [r7, #4]
800768a: 4798 blx r3
800768c: 4603 mov r3, r0
800768e: 2b00 cmp r3, #0
8007690: d101 bne.n 8007696 <USBD_SetClassConfig+0x34>
{
ret = USBD_OK;
8007692: 2300 movs r3, #0
8007694: 73fb strb r3, [r7, #15]
}
}
return ret;
8007696: 7bfb ldrb r3, [r7, #15]
}
8007698: 4618 mov r0, r3
800769a: 3710 adds r7, #16
800769c: 46bd mov sp, r7
800769e: bd80 pop {r7, pc}
080076a0 <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status: USBD_StatusTypeDef
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80076a0: b580 push {r7, lr}
80076a2: b082 sub sp, #8
80076a4: af00 add r7, sp, #0
80076a6: 6078 str r0, [r7, #4]
80076a8: 460b mov r3, r1
80076aa: 70fb strb r3, [r7, #3]
/* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx);
80076ac: 687b ldr r3, [r7, #4]
80076ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80076b2: 685b ldr r3, [r3, #4]
80076b4: 78fa ldrb r2, [r7, #3]
80076b6: 4611 mov r1, r2
80076b8: 6878 ldr r0, [r7, #4]
80076ba: 4798 blx r3
return USBD_OK;
80076bc: 2300 movs r3, #0
}
80076be: 4618 mov r0, r3
80076c0: 3708 adds r7, #8
80076c2: 46bd mov sp, r7
80076c4: bd80 pop {r7, pc}
080076c6 <USBD_LL_SetupStage>:
* Handle the setup stage
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
80076c6: b580 push {r7, lr}
80076c8: b082 sub sp, #8
80076ca: af00 add r7, sp, #0
80076cc: 6078 str r0, [r7, #4]
80076ce: 6039 str r1, [r7, #0]
USBD_ParseSetupRequest(&pdev->request, psetup);
80076d0: 687b ldr r3, [r7, #4]
80076d2: f503 732a add.w r3, r3, #680 @ 0x2a8
80076d6: 6839 ldr r1, [r7, #0]
80076d8: 4618 mov r0, r3
80076da: f000 fed8 bl 800848e <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
80076de: 687b ldr r3, [r7, #4]
80076e0: 2201 movs r2, #1
80076e2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
80076e6: 687b ldr r3, [r7, #4]
80076e8: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
80076ec: 461a mov r2, r3
80076ee: 687b ldr r3, [r7, #4]
80076f0: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
80076f4: 687b ldr r3, [r7, #4]
80076f6: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
80076fa: f003 031f and.w r3, r3, #31
80076fe: 2b02 cmp r3, #2
8007700: d016 beq.n 8007730 <USBD_LL_SetupStage+0x6a>
8007702: 2b02 cmp r3, #2
8007704: d81c bhi.n 8007740 <USBD_LL_SetupStage+0x7a>
8007706: 2b00 cmp r3, #0
8007708: d002 beq.n 8007710 <USBD_LL_SetupStage+0x4a>
800770a: 2b01 cmp r3, #1
800770c: d008 beq.n 8007720 <USBD_LL_SetupStage+0x5a>
800770e: e017 b.n 8007740 <USBD_LL_SetupStage+0x7a>
{
case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq(pdev, &pdev->request);
8007710: 687b ldr r3, [r7, #4]
8007712: f503 732a add.w r3, r3, #680 @ 0x2a8
8007716: 4619 mov r1, r3
8007718: 6878 ldr r0, [r7, #4]
800771a: f000 f9cb bl 8007ab4 <USBD_StdDevReq>
break;
800771e: e01a b.n 8007756 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request);
8007720: 687b ldr r3, [r7, #4]
8007722: f503 732a add.w r3, r3, #680 @ 0x2a8
8007726: 4619 mov r1, r3
8007728: 6878 ldr r0, [r7, #4]
800772a: f000 fa2d bl 8007b88 <USBD_StdItfReq>
break;
800772e: e012 b.n 8007756 <USBD_LL_SetupStage+0x90>
case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request);
8007730: 687b ldr r3, [r7, #4]
8007732: f503 732a add.w r3, r3, #680 @ 0x2a8
8007736: 4619 mov r1, r3
8007738: 6878 ldr r0, [r7, #4]
800773a: f000 fa6d bl 8007c18 <USBD_StdEPReq>
break;
800773e: e00a b.n 8007756 <USBD_LL_SetupStage+0x90>
default:
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
8007740: 687b ldr r3, [r7, #4]
8007742: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
8007746: f023 037f bic.w r3, r3, #127 @ 0x7f
800774a: b2db uxtb r3, r3
800774c: 4619 mov r1, r3
800774e: 6878 ldr r0, [r7, #4]
8007750: f001 fbb0 bl 8008eb4 <USBD_LL_StallEP>
break;
8007754: bf00 nop
}
return USBD_OK;
8007756: 2300 movs r3, #0
}
8007758: 4618 mov r0, r3
800775a: 3708 adds r7, #8
800775c: 46bd mov sp, r7
800775e: bd80 pop {r7, pc}
08007760 <USBD_LL_DataOutStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8007760: b580 push {r7, lr}
8007762: b086 sub sp, #24
8007764: af00 add r7, sp, #0
8007766: 60f8 str r0, [r7, #12]
8007768: 460b mov r3, r1
800776a: 607a str r2, [r7, #4]
800776c: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
800776e: 7afb ldrb r3, [r7, #11]
8007770: 2b00 cmp r3, #0
8007772: d14b bne.n 800780c <USBD_LL_DataOutStage+0xac>
{
pep = &pdev->ep_out[0];
8007774: 68fb ldr r3, [r7, #12]
8007776: f503 73aa add.w r3, r3, #340 @ 0x154
800777a: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
800777c: 68fb ldr r3, [r7, #12]
800777e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8007782: 2b03 cmp r3, #3
8007784: d134 bne.n 80077f0 <USBD_LL_DataOutStage+0x90>
{
if (pep->rem_length > pep->maxpacket)
8007786: 697b ldr r3, [r7, #20]
8007788: 68da ldr r2, [r3, #12]
800778a: 697b ldr r3, [r7, #20]
800778c: 691b ldr r3, [r3, #16]
800778e: 429a cmp r2, r3
8007790: d919 bls.n 80077c6 <USBD_LL_DataOutStage+0x66>
{
pep->rem_length -= pep->maxpacket;
8007792: 697b ldr r3, [r7, #20]
8007794: 68da ldr r2, [r3, #12]
8007796: 697b ldr r3, [r7, #20]
8007798: 691b ldr r3, [r3, #16]
800779a: 1ad2 subs r2, r2, r3
800779c: 697b ldr r3, [r7, #20]
800779e: 60da str r2, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80077a0: 697b ldr r3, [r7, #20]
80077a2: 68da ldr r2, [r3, #12]
80077a4: 697b ldr r3, [r7, #20]
80077a6: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
80077a8: 429a cmp r2, r3
80077aa: d203 bcs.n 80077b4 <USBD_LL_DataOutStage+0x54>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80077ac: 697b ldr r3, [r7, #20]
80077ae: 68db ldr r3, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
80077b0: b29b uxth r3, r3
80077b2: e002 b.n 80077ba <USBD_LL_DataOutStage+0x5a>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
80077b4: 697b ldr r3, [r7, #20]
80077b6: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
80077b8: b29b uxth r3, r3
80077ba: 461a mov r2, r3
80077bc: 6879 ldr r1, [r7, #4]
80077be: 68f8 ldr r0, [r7, #12]
80077c0: f000 ff54 bl 800866c <USBD_CtlContinueRx>
80077c4: e038 b.n 8007838 <USBD_LL_DataOutStage+0xd8>
}
else
{
if ((pdev->pClass->EP0_RxReady != NULL) &&
80077c6: 68fb ldr r3, [r7, #12]
80077c8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80077cc: 691b ldr r3, [r3, #16]
80077ce: 2b00 cmp r3, #0
80077d0: d00a beq.n 80077e8 <USBD_LL_DataOutStage+0x88>
(pdev->dev_state == USBD_STATE_CONFIGURED))
80077d2: 68fb ldr r3, [r7, #12]
80077d4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_RxReady != NULL) &&
80077d8: 2b03 cmp r3, #3
80077da: d105 bne.n 80077e8 <USBD_LL_DataOutStage+0x88>
{
pdev->pClass->EP0_RxReady(pdev);
80077dc: 68fb ldr r3, [r7, #12]
80077de: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80077e2: 691b ldr r3, [r3, #16]
80077e4: 68f8 ldr r0, [r7, #12]
80077e6: 4798 blx r3
}
USBD_CtlSendStatus(pdev);
80077e8: 68f8 ldr r0, [r7, #12]
80077ea: f000 ff51 bl 8008690 <USBD_CtlSendStatus>
80077ee: e023 b.n 8007838 <USBD_LL_DataOutStage+0xd8>
}
}
else
{
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
80077f0: 68fb ldr r3, [r7, #12]
80077f2: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
80077f6: 2b05 cmp r3, #5
80077f8: d11e bne.n 8007838 <USBD_LL_DataOutStage+0xd8>
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
80077fa: 68fb ldr r3, [r7, #12]
80077fc: 2200 movs r2, #0
80077fe: f8c3 2294 str.w r2, [r3, #660] @ 0x294
USBD_LL_StallEP(pdev, 0U);
8007802: 2100 movs r1, #0
8007804: 68f8 ldr r0, [r7, #12]
8007806: f001 fb55 bl 8008eb4 <USBD_LL_StallEP>
800780a: e015 b.n 8007838 <USBD_LL_DataOutStage+0xd8>
}
}
}
else if ((pdev->pClass->DataOut != NULL) &&
800780c: 68fb ldr r3, [r7, #12]
800780e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007812: 699b ldr r3, [r3, #24]
8007814: 2b00 cmp r3, #0
8007816: d00d beq.n 8007834 <USBD_LL_DataOutStage+0xd4>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8007818: 68fb ldr r3, [r7, #12]
800781a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataOut != NULL) &&
800781e: 2b03 cmp r3, #3
8007820: d108 bne.n 8007834 <USBD_LL_DataOutStage+0xd4>
{
pdev->pClass->DataOut(pdev, epnum);
8007822: 68fb ldr r3, [r7, #12]
8007824: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007828: 699b ldr r3, [r3, #24]
800782a: 7afa ldrb r2, [r7, #11]
800782c: 4611 mov r1, r2
800782e: 68f8 ldr r0, [r7, #12]
8007830: 4798 blx r3
8007832: e001 b.n 8007838 <USBD_LL_DataOutStage+0xd8>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
8007834: 2302 movs r3, #2
8007836: e000 b.n 800783a <USBD_LL_DataOutStage+0xda>
}
return USBD_OK;
8007838: 2300 movs r3, #0
}
800783a: 4618 mov r0, r3
800783c: 3718 adds r7, #24
800783e: 46bd mov sp, r7
8007840: bd80 pop {r7, pc}
08007842 <USBD_LL_DataInStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8007842: b580 push {r7, lr}
8007844: b086 sub sp, #24
8007846: af00 add r7, sp, #0
8007848: 60f8 str r0, [r7, #12]
800784a: 460b mov r3, r1
800784c: 607a str r2, [r7, #4]
800784e: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
8007850: 7afb ldrb r3, [r7, #11]
8007852: 2b00 cmp r3, #0
8007854: d17f bne.n 8007956 <USBD_LL_DataInStage+0x114>
{
pep = &pdev->ep_in[0];
8007856: 68fb ldr r3, [r7, #12]
8007858: 3314 adds r3, #20
800785a: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
800785c: 68fb ldr r3, [r7, #12]
800785e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8007862: 2b02 cmp r3, #2
8007864: d15c bne.n 8007920 <USBD_LL_DataInStage+0xde>
{
if (pep->rem_length > pep->maxpacket)
8007866: 697b ldr r3, [r7, #20]
8007868: 68da ldr r2, [r3, #12]
800786a: 697b ldr r3, [r7, #20]
800786c: 691b ldr r3, [r3, #16]
800786e: 429a cmp r2, r3
8007870: d915 bls.n 800789e <USBD_LL_DataInStage+0x5c>
{
pep->rem_length -= pep->maxpacket;
8007872: 697b ldr r3, [r7, #20]
8007874: 68da ldr r2, [r3, #12]
8007876: 697b ldr r3, [r7, #20]
8007878: 691b ldr r3, [r3, #16]
800787a: 1ad2 subs r2, r2, r3
800787c: 697b ldr r3, [r7, #20]
800787e: 60da str r2, [r3, #12]
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
8007880: 697b ldr r3, [r7, #20]
8007882: 68db ldr r3, [r3, #12]
8007884: b29b uxth r3, r3
8007886: 461a mov r2, r3
8007888: 6879 ldr r1, [r7, #4]
800788a: 68f8 ldr r0, [r7, #12]
800788c: f000 febe bl 800860c <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8007890: 2300 movs r3, #0
8007892: 2200 movs r2, #0
8007894: 2100 movs r1, #0
8007896: 68f8 ldr r0, [r7, #12]
8007898: f001 fbb7 bl 800900a <USBD_LL_PrepareReceive>
800789c: e04e b.n 800793c <USBD_LL_DataInStage+0xfa>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->total_length % pep->maxpacket == 0U) &&
800789e: 697b ldr r3, [r7, #20]
80078a0: 689b ldr r3, [r3, #8]
80078a2: 697a ldr r2, [r7, #20]
80078a4: 6912 ldr r2, [r2, #16]
80078a6: fbb3 f1f2 udiv r1, r3, r2
80078aa: fb01 f202 mul.w r2, r1, r2
80078ae: 1a9b subs r3, r3, r2
80078b0: 2b00 cmp r3, #0
80078b2: d11c bne.n 80078ee <USBD_LL_DataInStage+0xac>
(pep->total_length >= pep->maxpacket) &&
80078b4: 697b ldr r3, [r7, #20]
80078b6: 689a ldr r2, [r3, #8]
80078b8: 697b ldr r3, [r7, #20]
80078ba: 691b ldr r3, [r3, #16]
if ((pep->total_length % pep->maxpacket == 0U) &&
80078bc: 429a cmp r2, r3
80078be: d316 bcc.n 80078ee <USBD_LL_DataInStage+0xac>
(pep->total_length < pdev->ep0_data_len))
80078c0: 697b ldr r3, [r7, #20]
80078c2: 689a ldr r2, [r3, #8]
80078c4: 68fb ldr r3, [r7, #12]
80078c6: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
80078ca: 429a cmp r2, r3
80078cc: d20f bcs.n 80078ee <USBD_LL_DataInStage+0xac>
{
USBD_CtlContinueSendData(pdev, NULL, 0U);
80078ce: 2200 movs r2, #0
80078d0: 2100 movs r1, #0
80078d2: 68f8 ldr r0, [r7, #12]
80078d4: f000 fe9a bl 800860c <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
80078d8: 68fb ldr r3, [r7, #12]
80078da: 2200 movs r2, #0
80078dc: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80078e0: 2300 movs r3, #0
80078e2: 2200 movs r2, #0
80078e4: 2100 movs r1, #0
80078e6: 68f8 ldr r0, [r7, #12]
80078e8: f001 fb8f bl 800900a <USBD_LL_PrepareReceive>
80078ec: e026 b.n 800793c <USBD_LL_DataInStage+0xfa>
}
else
{
if ((pdev->pClass->EP0_TxSent != NULL) &&
80078ee: 68fb ldr r3, [r7, #12]
80078f0: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80078f4: 68db ldr r3, [r3, #12]
80078f6: 2b00 cmp r3, #0
80078f8: d00a beq.n 8007910 <USBD_LL_DataInStage+0xce>
(pdev->dev_state == USBD_STATE_CONFIGURED))
80078fa: 68fb ldr r3, [r7, #12]
80078fc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
if ((pdev->pClass->EP0_TxSent != NULL) &&
8007900: 2b03 cmp r3, #3
8007902: d105 bne.n 8007910 <USBD_LL_DataInStage+0xce>
{
pdev->pClass->EP0_TxSent(pdev);
8007904: 68fb ldr r3, [r7, #12]
8007906: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800790a: 68db ldr r3, [r3, #12]
800790c: 68f8 ldr r0, [r7, #12]
800790e: 4798 blx r3
}
USBD_LL_StallEP(pdev, 0x80U);
8007910: 2180 movs r1, #128 @ 0x80
8007912: 68f8 ldr r0, [r7, #12]
8007914: f001 face bl 8008eb4 <USBD_LL_StallEP>
USBD_CtlReceiveStatus(pdev);
8007918: 68f8 ldr r0, [r7, #12]
800791a: f000 fecc bl 80086b6 <USBD_CtlReceiveStatus>
800791e: e00d b.n 800793c <USBD_LL_DataInStage+0xfa>
}
}
}
else
{
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
8007920: 68fb ldr r3, [r7, #12]
8007922: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8007926: 2b04 cmp r3, #4
8007928: d004 beq.n 8007934 <USBD_LL_DataInStage+0xf2>
(pdev->ep0_state == USBD_EP0_IDLE))
800792a: 68fb ldr r3, [r7, #12]
800792c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
8007930: 2b00 cmp r3, #0
8007932: d103 bne.n 800793c <USBD_LL_DataInStage+0xfa>
{
USBD_LL_StallEP(pdev, 0x80U);
8007934: 2180 movs r1, #128 @ 0x80
8007936: 68f8 ldr r0, [r7, #12]
8007938: f001 fabc bl 8008eb4 <USBD_LL_StallEP>
}
}
if (pdev->dev_test_mode == 1U)
800793c: 68fb ldr r3, [r7, #12]
800793e: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
8007942: 2b01 cmp r3, #1
8007944: d11d bne.n 8007982 <USBD_LL_DataInStage+0x140>
{
USBD_RunTestMode(pdev);
8007946: 68f8 ldr r0, [r7, #12]
8007948: f7ff fe81 bl 800764e <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
800794c: 68fb ldr r3, [r7, #12]
800794e: 2200 movs r2, #0
8007950: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
8007954: e015 b.n 8007982 <USBD_LL_DataInStage+0x140>
}
}
else if ((pdev->pClass->DataIn != NULL) &&
8007956: 68fb ldr r3, [r7, #12]
8007958: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
800795c: 695b ldr r3, [r3, #20]
800795e: 2b00 cmp r3, #0
8007960: d00d beq.n 800797e <USBD_LL_DataInStage+0x13c>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8007962: 68fb ldr r3, [r7, #12]
8007964: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
else if ((pdev->pClass->DataIn != NULL) &&
8007968: 2b03 cmp r3, #3
800796a: d108 bne.n 800797e <USBD_LL_DataInStage+0x13c>
{
pdev->pClass->DataIn(pdev, epnum);
800796c: 68fb ldr r3, [r7, #12]
800796e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007972: 695b ldr r3, [r3, #20]
8007974: 7afa ldrb r2, [r7, #11]
8007976: 4611 mov r1, r2
8007978: 68f8 ldr r0, [r7, #12]
800797a: 4798 blx r3
800797c: e001 b.n 8007982 <USBD_LL_DataInStage+0x140>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
800797e: 2302 movs r3, #2
8007980: e000 b.n 8007984 <USBD_LL_DataInStage+0x142>
}
return USBD_OK;
8007982: 2300 movs r3, #0
}
8007984: 4618 mov r0, r3
8007986: 3718 adds r7, #24
8007988: 46bd mov sp, r7
800798a: bd80 pop {r7, pc}
0800798c <USBD_LL_Reset>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
800798c: b580 push {r7, lr}
800798e: b082 sub sp, #8
8007990: af00 add r7, sp, #0
8007992: 6078 str r0, [r7, #4]
/* Open EP0 OUT */
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8007994: 2340 movs r3, #64 @ 0x40
8007996: 2200 movs r2, #0
8007998: 2100 movs r1, #0
800799a: 6878 ldr r0, [r7, #4]
800799c: f001 fa45 bl 8008e2a <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
80079a0: 687b ldr r3, [r7, #4]
80079a2: 2201 movs r2, #1
80079a4: f8c3 2158 str.w r2, [r3, #344] @ 0x158
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
80079a8: 687b ldr r3, [r7, #4]
80079aa: 2240 movs r2, #64 @ 0x40
80079ac: f8c3 2164 str.w r2, [r3, #356] @ 0x164
/* Open EP0 IN */
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
80079b0: 2340 movs r3, #64 @ 0x40
80079b2: 2200 movs r2, #0
80079b4: 2180 movs r1, #128 @ 0x80
80079b6: 6878 ldr r0, [r7, #4]
80079b8: f001 fa37 bl 8008e2a <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
80079bc: 687b ldr r3, [r7, #4]
80079be: 2201 movs r2, #1
80079c0: 619a str r2, [r3, #24]
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
80079c2: 687b ldr r3, [r7, #4]
80079c4: 2240 movs r2, #64 @ 0x40
80079c6: 625a str r2, [r3, #36] @ 0x24
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
80079c8: 687b ldr r3, [r7, #4]
80079ca: 2201 movs r2, #1
80079cc: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
80079d0: 687b ldr r3, [r7, #4]
80079d2: 2200 movs r2, #0
80079d4: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
80079d8: 687b ldr r3, [r7, #4]
80079da: 2200 movs r2, #0
80079dc: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
80079de: 687b ldr r3, [r7, #4]
80079e0: 2200 movs r2, #0
80079e2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
if (pdev->pClassData)
80079e6: 687b ldr r3, [r7, #4]
80079e8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80079ec: 2b00 cmp r3, #0
80079ee: d009 beq.n 8007a04 <USBD_LL_Reset+0x78>
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
80079f0: 687b ldr r3, [r7, #4]
80079f2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
80079f6: 685b ldr r3, [r3, #4]
80079f8: 687a ldr r2, [r7, #4]
80079fa: 6852 ldr r2, [r2, #4]
80079fc: b2d2 uxtb r2, r2
80079fe: 4611 mov r1, r2
8007a00: 6878 ldr r0, [r7, #4]
8007a02: 4798 blx r3
}
return USBD_OK;
8007a04: 2300 movs r3, #0
}
8007a06: 4618 mov r0, r3
8007a08: 3708 adds r7, #8
8007a0a: 46bd mov sp, r7
8007a0c: bd80 pop {r7, pc}
08007a0e <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8007a0e: b480 push {r7}
8007a10: b083 sub sp, #12
8007a12: af00 add r7, sp, #0
8007a14: 6078 str r0, [r7, #4]
8007a16: 460b mov r3, r1
8007a18: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
8007a1a: 687b ldr r3, [r7, #4]
8007a1c: 78fa ldrb r2, [r7, #3]
8007a1e: 741a strb r2, [r3, #16]
return USBD_OK;
8007a20: 2300 movs r3, #0
}
8007a22: 4618 mov r0, r3
8007a24: 370c adds r7, #12
8007a26: 46bd mov sp, r7
8007a28: bc80 pop {r7}
8007a2a: 4770 bx lr
08007a2c <USBD_LL_Suspend>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8007a2c: b480 push {r7}
8007a2e: b083 sub sp, #12
8007a30: af00 add r7, sp, #0
8007a32: 6078 str r0, [r7, #4]
pdev->dev_old_state = pdev->dev_state;
8007a34: 687b ldr r3, [r7, #4]
8007a36: f893 229c ldrb.w r2, [r3, #668] @ 0x29c
8007a3a: 687b ldr r3, [r7, #4]
8007a3c: f883 229d strb.w r2, [r3, #669] @ 0x29d
pdev->dev_state = USBD_STATE_SUSPENDED;
8007a40: 687b ldr r3, [r7, #4]
8007a42: 2204 movs r2, #4
8007a44: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
8007a48: 2300 movs r3, #0
}
8007a4a: 4618 mov r0, r3
8007a4c: 370c adds r7, #12
8007a4e: 46bd mov sp, r7
8007a50: bc80 pop {r7}
8007a52: 4770 bx lr
08007a54 <USBD_LL_Resume>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
8007a54: b480 push {r7}
8007a56: b083 sub sp, #12
8007a58: af00 add r7, sp, #0
8007a5a: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8007a5c: 687b ldr r3, [r7, #4]
8007a5e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007a62: 2b04 cmp r3, #4
8007a64: d105 bne.n 8007a72 <USBD_LL_Resume+0x1e>
{
pdev->dev_state = pdev->dev_old_state;
8007a66: 687b ldr r3, [r7, #4]
8007a68: f893 229d ldrb.w r2, [r3, #669] @ 0x29d
8007a6c: 687b ldr r3, [r7, #4]
8007a6e: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
8007a72: 2300 movs r3, #0
}
8007a74: 4618 mov r0, r3
8007a76: 370c adds r7, #12
8007a78: 46bd mov sp, r7
8007a7a: bc80 pop {r7}
8007a7c: 4770 bx lr
08007a7e <USBD_LL_SOF>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
8007a7e: b580 push {r7, lr}
8007a80: b082 sub sp, #8
8007a82: af00 add r7, sp, #0
8007a84: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8007a86: 687b ldr r3, [r7, #4]
8007a88: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007a8c: 2b03 cmp r3, #3
8007a8e: d10b bne.n 8007aa8 <USBD_LL_SOF+0x2a>
{
if (pdev->pClass->SOF != NULL)
8007a90: 687b ldr r3, [r7, #4]
8007a92: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007a96: 69db ldr r3, [r3, #28]
8007a98: 2b00 cmp r3, #0
8007a9a: d005 beq.n 8007aa8 <USBD_LL_SOF+0x2a>
{
pdev->pClass->SOF(pdev);
8007a9c: 687b ldr r3, [r7, #4]
8007a9e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007aa2: 69db ldr r3, [r3, #28]
8007aa4: 6878 ldr r0, [r7, #4]
8007aa6: 4798 blx r3
}
}
return USBD_OK;
8007aa8: 2300 movs r3, #0
}
8007aaa: 4618 mov r0, r3
8007aac: 3708 adds r7, #8
8007aae: 46bd mov sp, r7
8007ab0: bd80 pop {r7, pc}
...
08007ab4 <USBD_StdDevReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8007ab4: b580 push {r7, lr}
8007ab6: b084 sub sp, #16
8007ab8: af00 add r7, sp, #0
8007aba: 6078 str r0, [r7, #4]
8007abc: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8007abe: 2300 movs r3, #0
8007ac0: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8007ac2: 683b ldr r3, [r7, #0]
8007ac4: 781b ldrb r3, [r3, #0]
8007ac6: f003 0360 and.w r3, r3, #96 @ 0x60
8007aca: 2b40 cmp r3, #64 @ 0x40
8007acc: d005 beq.n 8007ada <USBD_StdDevReq+0x26>
8007ace: 2b40 cmp r3, #64 @ 0x40
8007ad0: d84f bhi.n 8007b72 <USBD_StdDevReq+0xbe>
8007ad2: 2b00 cmp r3, #0
8007ad4: d009 beq.n 8007aea <USBD_StdDevReq+0x36>
8007ad6: 2b20 cmp r3, #32
8007ad8: d14b bne.n 8007b72 <USBD_StdDevReq+0xbe>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8007ada: 687b ldr r3, [r7, #4]
8007adc: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007ae0: 689b ldr r3, [r3, #8]
8007ae2: 6839 ldr r1, [r7, #0]
8007ae4: 6878 ldr r0, [r7, #4]
8007ae6: 4798 blx r3
break;
8007ae8: e048 b.n 8007b7c <USBD_StdDevReq+0xc8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8007aea: 683b ldr r3, [r7, #0]
8007aec: 785b ldrb r3, [r3, #1]
8007aee: 2b09 cmp r3, #9
8007af0: d839 bhi.n 8007b66 <USBD_StdDevReq+0xb2>
8007af2: a201 add r2, pc, #4 @ (adr r2, 8007af8 <USBD_StdDevReq+0x44>)
8007af4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007af8: 08007b49 .word 0x08007b49
8007afc: 08007b5d .word 0x08007b5d
8007b00: 08007b67 .word 0x08007b67
8007b04: 08007b53 .word 0x08007b53
8007b08: 08007b67 .word 0x08007b67
8007b0c: 08007b2b .word 0x08007b2b
8007b10: 08007b21 .word 0x08007b21
8007b14: 08007b67 .word 0x08007b67
8007b18: 08007b3f .word 0x08007b3f
8007b1c: 08007b35 .word 0x08007b35
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
8007b20: 6839 ldr r1, [r7, #0]
8007b22: 6878 ldr r0, [r7, #4]
8007b24: f000 f9dc bl 8007ee0 <USBD_GetDescriptor>
break;
8007b28: e022 b.n 8007b70 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
8007b2a: 6839 ldr r1, [r7, #0]
8007b2c: 6878 ldr r0, [r7, #4]
8007b2e: f000 fb3f bl 80081b0 <USBD_SetAddress>
break;
8007b32: e01d b.n 8007b70 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_CONFIGURATION:
USBD_SetConfig(pdev, req);
8007b34: 6839 ldr r1, [r7, #0]
8007b36: 6878 ldr r0, [r7, #4]
8007b38: f000 fb7e bl 8008238 <USBD_SetConfig>
break;
8007b3c: e018 b.n 8007b70 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
8007b3e: 6839 ldr r1, [r7, #0]
8007b40: 6878 ldr r0, [r7, #4]
8007b42: f000 fc07 bl 8008354 <USBD_GetConfig>
break;
8007b46: e013 b.n 8007b70 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
8007b48: 6839 ldr r1, [r7, #0]
8007b4a: 6878 ldr r0, [r7, #4]
8007b4c: f000 fc37 bl 80083be <USBD_GetStatus>
break;
8007b50: e00e b.n 8007b70 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
8007b52: 6839 ldr r1, [r7, #0]
8007b54: 6878 ldr r0, [r7, #4]
8007b56: f000 fc65 bl 8008424 <USBD_SetFeature>
break;
8007b5a: e009 b.n 8007b70 <USBD_StdDevReq+0xbc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
8007b5c: 6839 ldr r1, [r7, #0]
8007b5e: 6878 ldr r0, [r7, #4]
8007b60: f000 fc74 bl 800844c <USBD_ClrFeature>
break;
8007b64: e004 b.n 8007b70 <USBD_StdDevReq+0xbc>
default:
USBD_CtlError(pdev, req);
8007b66: 6839 ldr r1, [r7, #0]
8007b68: 6878 ldr r0, [r7, #4]
8007b6a: f000 fcc9 bl 8008500 <USBD_CtlError>
break;
8007b6e: bf00 nop
}
break;
8007b70: e004 b.n 8007b7c <USBD_StdDevReq+0xc8>
default:
USBD_CtlError(pdev, req);
8007b72: 6839 ldr r1, [r7, #0]
8007b74: 6878 ldr r0, [r7, #4]
8007b76: f000 fcc3 bl 8008500 <USBD_CtlError>
break;
8007b7a: bf00 nop
}
return ret;
8007b7c: 7bfb ldrb r3, [r7, #15]
}
8007b7e: 4618 mov r0, r3
8007b80: 3710 adds r7, #16
8007b82: 46bd mov sp, r7
8007b84: bd80 pop {r7, pc}
8007b86: bf00 nop
08007b88 <USBD_StdItfReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8007b88: b580 push {r7, lr}
8007b8a: b084 sub sp, #16
8007b8c: af00 add r7, sp, #0
8007b8e: 6078 str r0, [r7, #4]
8007b90: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8007b92: 2300 movs r3, #0
8007b94: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8007b96: 683b ldr r3, [r7, #0]
8007b98: 781b ldrb r3, [r3, #0]
8007b9a: f003 0360 and.w r3, r3, #96 @ 0x60
8007b9e: 2b40 cmp r3, #64 @ 0x40
8007ba0: d005 beq.n 8007bae <USBD_StdItfReq+0x26>
8007ba2: 2b40 cmp r3, #64 @ 0x40
8007ba4: d82e bhi.n 8007c04 <USBD_StdItfReq+0x7c>
8007ba6: 2b00 cmp r3, #0
8007ba8: d001 beq.n 8007bae <USBD_StdItfReq+0x26>
8007baa: 2b20 cmp r3, #32
8007bac: d12a bne.n 8007c04 <USBD_StdItfReq+0x7c>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
8007bae: 687b ldr r3, [r7, #4]
8007bb0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007bb4: 3b01 subs r3, #1
8007bb6: 2b02 cmp r3, #2
8007bb8: d81d bhi.n 8007bf6 <USBD_StdItfReq+0x6e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
8007bba: 683b ldr r3, [r7, #0]
8007bbc: 889b ldrh r3, [r3, #4]
8007bbe: b2db uxtb r3, r3
8007bc0: 2b01 cmp r3, #1
8007bc2: d813 bhi.n 8007bec <USBD_StdItfReq+0x64>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8007bc4: 687b ldr r3, [r7, #4]
8007bc6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007bca: 689b ldr r3, [r3, #8]
8007bcc: 6839 ldr r1, [r7, #0]
8007bce: 6878 ldr r0, [r7, #4]
8007bd0: 4798 blx r3
8007bd2: 4603 mov r3, r0
8007bd4: 73fb strb r3, [r7, #15]
if ((req->wLength == 0U) && (ret == USBD_OK))
8007bd6: 683b ldr r3, [r7, #0]
8007bd8: 88db ldrh r3, [r3, #6]
8007bda: 2b00 cmp r3, #0
8007bdc: d110 bne.n 8007c00 <USBD_StdItfReq+0x78>
8007bde: 7bfb ldrb r3, [r7, #15]
8007be0: 2b00 cmp r3, #0
8007be2: d10d bne.n 8007c00 <USBD_StdItfReq+0x78>
{
USBD_CtlSendStatus(pdev);
8007be4: 6878 ldr r0, [r7, #4]
8007be6: f000 fd53 bl 8008690 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8007bea: e009 b.n 8007c00 <USBD_StdItfReq+0x78>
USBD_CtlError(pdev, req);
8007bec: 6839 ldr r1, [r7, #0]
8007bee: 6878 ldr r0, [r7, #4]
8007bf0: f000 fc86 bl 8008500 <USBD_CtlError>
break;
8007bf4: e004 b.n 8007c00 <USBD_StdItfReq+0x78>
default:
USBD_CtlError(pdev, req);
8007bf6: 6839 ldr r1, [r7, #0]
8007bf8: 6878 ldr r0, [r7, #4]
8007bfa: f000 fc81 bl 8008500 <USBD_CtlError>
break;
8007bfe: e000 b.n 8007c02 <USBD_StdItfReq+0x7a>
break;
8007c00: bf00 nop
}
break;
8007c02: e004 b.n 8007c0e <USBD_StdItfReq+0x86>
default:
USBD_CtlError(pdev, req);
8007c04: 6839 ldr r1, [r7, #0]
8007c06: 6878 ldr r0, [r7, #4]
8007c08: f000 fc7a bl 8008500 <USBD_CtlError>
break;
8007c0c: bf00 nop
}
return USBD_OK;
8007c0e: 2300 movs r3, #0
}
8007c10: 4618 mov r0, r3
8007c12: 3710 adds r7, #16
8007c14: 46bd mov sp, r7
8007c16: bd80 pop {r7, pc}
08007c18 <USBD_StdEPReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8007c18: b580 push {r7, lr}
8007c1a: b084 sub sp, #16
8007c1c: af00 add r7, sp, #0
8007c1e: 6078 str r0, [r7, #4]
8007c20: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
USBD_StatusTypeDef ret = USBD_OK;
8007c22: 2300 movs r3, #0
8007c24: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
8007c26: 683b ldr r3, [r7, #0]
8007c28: 889b ldrh r3, [r3, #4]
8007c2a: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8007c2c: 683b ldr r3, [r7, #0]
8007c2e: 781b ldrb r3, [r3, #0]
8007c30: f003 0360 and.w r3, r3, #96 @ 0x60
8007c34: 2b40 cmp r3, #64 @ 0x40
8007c36: d007 beq.n 8007c48 <USBD_StdEPReq+0x30>
8007c38: 2b40 cmp r3, #64 @ 0x40
8007c3a: f200 8146 bhi.w 8007eca <USBD_StdEPReq+0x2b2>
8007c3e: 2b00 cmp r3, #0
8007c40: d00a beq.n 8007c58 <USBD_StdEPReq+0x40>
8007c42: 2b20 cmp r3, #32
8007c44: f040 8141 bne.w 8007eca <USBD_StdEPReq+0x2b2>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8007c48: 687b ldr r3, [r7, #4]
8007c4a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007c4e: 689b ldr r3, [r3, #8]
8007c50: 6839 ldr r1, [r7, #0]
8007c52: 6878 ldr r0, [r7, #4]
8007c54: 4798 blx r3
break;
8007c56: e13d b.n 8007ed4 <USBD_StdEPReq+0x2bc>
case USB_REQ_TYPE_STANDARD:
/* Check if it is a class request */
if ((req->bmRequest & 0x60U) == 0x20U)
8007c58: 683b ldr r3, [r7, #0]
8007c5a: 781b ldrb r3, [r3, #0]
8007c5c: f003 0360 and.w r3, r3, #96 @ 0x60
8007c60: 2b20 cmp r3, #32
8007c62: d10a bne.n 8007c7a <USBD_StdEPReq+0x62>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8007c64: 687b ldr r3, [r7, #4]
8007c66: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007c6a: 689b ldr r3, [r3, #8]
8007c6c: 6839 ldr r1, [r7, #0]
8007c6e: 6878 ldr r0, [r7, #4]
8007c70: 4798 blx r3
8007c72: 4603 mov r3, r0
8007c74: 73fb strb r3, [r7, #15]
return ret;
8007c76: 7bfb ldrb r3, [r7, #15]
8007c78: e12d b.n 8007ed6 <USBD_StdEPReq+0x2be>
}
switch (req->bRequest)
8007c7a: 683b ldr r3, [r7, #0]
8007c7c: 785b ldrb r3, [r3, #1]
8007c7e: 2b03 cmp r3, #3
8007c80: d007 beq.n 8007c92 <USBD_StdEPReq+0x7a>
8007c82: 2b03 cmp r3, #3
8007c84: f300 811b bgt.w 8007ebe <USBD_StdEPReq+0x2a6>
8007c88: 2b00 cmp r3, #0
8007c8a: d072 beq.n 8007d72 <USBD_StdEPReq+0x15a>
8007c8c: 2b01 cmp r3, #1
8007c8e: d03a beq.n 8007d06 <USBD_StdEPReq+0xee>
8007c90: e115 b.n 8007ebe <USBD_StdEPReq+0x2a6>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
8007c92: 687b ldr r3, [r7, #4]
8007c94: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007c98: 2b02 cmp r3, #2
8007c9a: d002 beq.n 8007ca2 <USBD_StdEPReq+0x8a>
8007c9c: 2b03 cmp r3, #3
8007c9e: d015 beq.n 8007ccc <USBD_StdEPReq+0xb4>
8007ca0: e02b b.n 8007cfa <USBD_StdEPReq+0xe2>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8007ca2: 7bbb ldrb r3, [r7, #14]
8007ca4: 2b00 cmp r3, #0
8007ca6: d00c beq.n 8007cc2 <USBD_StdEPReq+0xaa>
8007ca8: 7bbb ldrb r3, [r7, #14]
8007caa: 2b80 cmp r3, #128 @ 0x80
8007cac: d009 beq.n 8007cc2 <USBD_StdEPReq+0xaa>
{
USBD_LL_StallEP(pdev, ep_addr);
8007cae: 7bbb ldrb r3, [r7, #14]
8007cb0: 4619 mov r1, r3
8007cb2: 6878 ldr r0, [r7, #4]
8007cb4: f001 f8fe bl 8008eb4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8007cb8: 2180 movs r1, #128 @ 0x80
8007cba: 6878 ldr r0, [r7, #4]
8007cbc: f001 f8fa bl 8008eb4 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8007cc0: e020 b.n 8007d04 <USBD_StdEPReq+0xec>
USBD_CtlError(pdev, req);
8007cc2: 6839 ldr r1, [r7, #0]
8007cc4: 6878 ldr r0, [r7, #4]
8007cc6: f000 fc1b bl 8008500 <USBD_CtlError>
break;
8007cca: e01b b.n 8007d04 <USBD_StdEPReq+0xec>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8007ccc: 683b ldr r3, [r7, #0]
8007cce: 885b ldrh r3, [r3, #2]
8007cd0: 2b00 cmp r3, #0
8007cd2: d10e bne.n 8007cf2 <USBD_StdEPReq+0xda>
{
if ((ep_addr != 0x00U) &&
8007cd4: 7bbb ldrb r3, [r7, #14]
8007cd6: 2b00 cmp r3, #0
8007cd8: d00b beq.n 8007cf2 <USBD_StdEPReq+0xda>
8007cda: 7bbb ldrb r3, [r7, #14]
8007cdc: 2b80 cmp r3, #128 @ 0x80
8007cde: d008 beq.n 8007cf2 <USBD_StdEPReq+0xda>
(ep_addr != 0x80U) && (req->wLength == 0x00U))
8007ce0: 683b ldr r3, [r7, #0]
8007ce2: 88db ldrh r3, [r3, #6]
8007ce4: 2b00 cmp r3, #0
8007ce6: d104 bne.n 8007cf2 <USBD_StdEPReq+0xda>
{
USBD_LL_StallEP(pdev, ep_addr);
8007ce8: 7bbb ldrb r3, [r7, #14]
8007cea: 4619 mov r1, r3
8007cec: 6878 ldr r0, [r7, #4]
8007cee: f001 f8e1 bl 8008eb4 <USBD_LL_StallEP>
}
}
USBD_CtlSendStatus(pdev);
8007cf2: 6878 ldr r0, [r7, #4]
8007cf4: f000 fccc bl 8008690 <USBD_CtlSendStatus>
break;
8007cf8: e004 b.n 8007d04 <USBD_StdEPReq+0xec>
default:
USBD_CtlError(pdev, req);
8007cfa: 6839 ldr r1, [r7, #0]
8007cfc: 6878 ldr r0, [r7, #4]
8007cfe: f000 fbff bl 8008500 <USBD_CtlError>
break;
8007d02: bf00 nop
}
break;
8007d04: e0e0 b.n 8007ec8 <USBD_StdEPReq+0x2b0>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
8007d06: 687b ldr r3, [r7, #4]
8007d08: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007d0c: 2b02 cmp r3, #2
8007d0e: d002 beq.n 8007d16 <USBD_StdEPReq+0xfe>
8007d10: 2b03 cmp r3, #3
8007d12: d015 beq.n 8007d40 <USBD_StdEPReq+0x128>
8007d14: e026 b.n 8007d64 <USBD_StdEPReq+0x14c>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8007d16: 7bbb ldrb r3, [r7, #14]
8007d18: 2b00 cmp r3, #0
8007d1a: d00c beq.n 8007d36 <USBD_StdEPReq+0x11e>
8007d1c: 7bbb ldrb r3, [r7, #14]
8007d1e: 2b80 cmp r3, #128 @ 0x80
8007d20: d009 beq.n 8007d36 <USBD_StdEPReq+0x11e>
{
USBD_LL_StallEP(pdev, ep_addr);
8007d22: 7bbb ldrb r3, [r7, #14]
8007d24: 4619 mov r1, r3
8007d26: 6878 ldr r0, [r7, #4]
8007d28: f001 f8c4 bl 8008eb4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8007d2c: 2180 movs r1, #128 @ 0x80
8007d2e: 6878 ldr r0, [r7, #4]
8007d30: f001 f8c0 bl 8008eb4 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8007d34: e01c b.n 8007d70 <USBD_StdEPReq+0x158>
USBD_CtlError(pdev, req);
8007d36: 6839 ldr r1, [r7, #0]
8007d38: 6878 ldr r0, [r7, #4]
8007d3a: f000 fbe1 bl 8008500 <USBD_CtlError>
break;
8007d3e: e017 b.n 8007d70 <USBD_StdEPReq+0x158>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8007d40: 683b ldr r3, [r7, #0]
8007d42: 885b ldrh r3, [r3, #2]
8007d44: 2b00 cmp r3, #0
8007d46: d112 bne.n 8007d6e <USBD_StdEPReq+0x156>
{
if ((ep_addr & 0x7FU) != 0x00U)
8007d48: 7bbb ldrb r3, [r7, #14]
8007d4a: f003 037f and.w r3, r3, #127 @ 0x7f
8007d4e: 2b00 cmp r3, #0
8007d50: d004 beq.n 8007d5c <USBD_StdEPReq+0x144>
{
USBD_LL_ClearStallEP(pdev, ep_addr);
8007d52: 7bbb ldrb r3, [r7, #14]
8007d54: 4619 mov r1, r3
8007d56: 6878 ldr r0, [r7, #4]
8007d58: f001 f8cb bl 8008ef2 <USBD_LL_ClearStallEP>
}
USBD_CtlSendStatus(pdev);
8007d5c: 6878 ldr r0, [r7, #4]
8007d5e: f000 fc97 bl 8008690 <USBD_CtlSendStatus>
}
break;
8007d62: e004 b.n 8007d6e <USBD_StdEPReq+0x156>
default:
USBD_CtlError(pdev, req);
8007d64: 6839 ldr r1, [r7, #0]
8007d66: 6878 ldr r0, [r7, #4]
8007d68: f000 fbca bl 8008500 <USBD_CtlError>
break;
8007d6c: e000 b.n 8007d70 <USBD_StdEPReq+0x158>
break;
8007d6e: bf00 nop
}
break;
8007d70: e0aa b.n 8007ec8 <USBD_StdEPReq+0x2b0>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
8007d72: 687b ldr r3, [r7, #4]
8007d74: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8007d78: 2b02 cmp r3, #2
8007d7a: d002 beq.n 8007d82 <USBD_StdEPReq+0x16a>
8007d7c: 2b03 cmp r3, #3
8007d7e: d032 beq.n 8007de6 <USBD_StdEPReq+0x1ce>
8007d80: e097 b.n 8007eb2 <USBD_StdEPReq+0x29a>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8007d82: 7bbb ldrb r3, [r7, #14]
8007d84: 2b00 cmp r3, #0
8007d86: d007 beq.n 8007d98 <USBD_StdEPReq+0x180>
8007d88: 7bbb ldrb r3, [r7, #14]
8007d8a: 2b80 cmp r3, #128 @ 0x80
8007d8c: d004 beq.n 8007d98 <USBD_StdEPReq+0x180>
{
USBD_CtlError(pdev, req);
8007d8e: 6839 ldr r1, [r7, #0]
8007d90: 6878 ldr r0, [r7, #4]
8007d92: f000 fbb5 bl 8008500 <USBD_CtlError>
break;
8007d96: e091 b.n 8007ebc <USBD_StdEPReq+0x2a4>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8007d98: f997 300e ldrsb.w r3, [r7, #14]
8007d9c: 2b00 cmp r3, #0
8007d9e: da0b bge.n 8007db8 <USBD_StdEPReq+0x1a0>
8007da0: 7bbb ldrb r3, [r7, #14]
8007da2: f003 027f and.w r2, r3, #127 @ 0x7f
8007da6: 4613 mov r3, r2
8007da8: 009b lsls r3, r3, #2
8007daa: 4413 add r3, r2
8007dac: 009b lsls r3, r3, #2
8007dae: 3310 adds r3, #16
8007db0: 687a ldr r2, [r7, #4]
8007db2: 4413 add r3, r2
8007db4: 3304 adds r3, #4
8007db6: e00b b.n 8007dd0 <USBD_StdEPReq+0x1b8>
&pdev->ep_out[ep_addr & 0x7FU];
8007db8: 7bbb ldrb r3, [r7, #14]
8007dba: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8007dbe: 4613 mov r3, r2
8007dc0: 009b lsls r3, r3, #2
8007dc2: 4413 add r3, r2
8007dc4: 009b lsls r3, r3, #2
8007dc6: f503 73a8 add.w r3, r3, #336 @ 0x150
8007dca: 687a ldr r2, [r7, #4]
8007dcc: 4413 add r3, r2
8007dce: 3304 adds r3, #4
8007dd0: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
8007dd2: 68bb ldr r3, [r7, #8]
8007dd4: 2200 movs r2, #0
8007dd6: 601a str r2, [r3, #0]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8007dd8: 68bb ldr r3, [r7, #8]
8007dda: 2202 movs r2, #2
8007ddc: 4619 mov r1, r3
8007dde: 6878 ldr r0, [r7, #4]
8007de0: f000 fbf8 bl 80085d4 <USBD_CtlSendData>
break;
8007de4: e06a b.n 8007ebc <USBD_StdEPReq+0x2a4>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
8007de6: f997 300e ldrsb.w r3, [r7, #14]
8007dea: 2b00 cmp r3, #0
8007dec: da11 bge.n 8007e12 <USBD_StdEPReq+0x1fa>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
8007dee: 7bbb ldrb r3, [r7, #14]
8007df0: f003 020f and.w r2, r3, #15
8007df4: 6879 ldr r1, [r7, #4]
8007df6: 4613 mov r3, r2
8007df8: 009b lsls r3, r3, #2
8007dfa: 4413 add r3, r2
8007dfc: 009b lsls r3, r3, #2
8007dfe: 440b add r3, r1
8007e00: 3318 adds r3, #24
8007e02: 681b ldr r3, [r3, #0]
8007e04: 2b00 cmp r3, #0
8007e06: d117 bne.n 8007e38 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
8007e08: 6839 ldr r1, [r7, #0]
8007e0a: 6878 ldr r0, [r7, #4]
8007e0c: f000 fb78 bl 8008500 <USBD_CtlError>
break;
8007e10: e054 b.n 8007ebc <USBD_StdEPReq+0x2a4>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
8007e12: 7bbb ldrb r3, [r7, #14]
8007e14: f003 020f and.w r2, r3, #15
8007e18: 6879 ldr r1, [r7, #4]
8007e1a: 4613 mov r3, r2
8007e1c: 009b lsls r3, r3, #2
8007e1e: 4413 add r3, r2
8007e20: 009b lsls r3, r3, #2
8007e22: 440b add r3, r1
8007e24: f503 73ac add.w r3, r3, #344 @ 0x158
8007e28: 681b ldr r3, [r3, #0]
8007e2a: 2b00 cmp r3, #0
8007e2c: d104 bne.n 8007e38 <USBD_StdEPReq+0x220>
{
USBD_CtlError(pdev, req);
8007e2e: 6839 ldr r1, [r7, #0]
8007e30: 6878 ldr r0, [r7, #4]
8007e32: f000 fb65 bl 8008500 <USBD_CtlError>
break;
8007e36: e041 b.n 8007ebc <USBD_StdEPReq+0x2a4>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8007e38: f997 300e ldrsb.w r3, [r7, #14]
8007e3c: 2b00 cmp r3, #0
8007e3e: da0b bge.n 8007e58 <USBD_StdEPReq+0x240>
8007e40: 7bbb ldrb r3, [r7, #14]
8007e42: f003 027f and.w r2, r3, #127 @ 0x7f
8007e46: 4613 mov r3, r2
8007e48: 009b lsls r3, r3, #2
8007e4a: 4413 add r3, r2
8007e4c: 009b lsls r3, r3, #2
8007e4e: 3310 adds r3, #16
8007e50: 687a ldr r2, [r7, #4]
8007e52: 4413 add r3, r2
8007e54: 3304 adds r3, #4
8007e56: e00b b.n 8007e70 <USBD_StdEPReq+0x258>
&pdev->ep_out[ep_addr & 0x7FU];
8007e58: 7bbb ldrb r3, [r7, #14]
8007e5a: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8007e5e: 4613 mov r3, r2
8007e60: 009b lsls r3, r3, #2
8007e62: 4413 add r3, r2
8007e64: 009b lsls r3, r3, #2
8007e66: f503 73a8 add.w r3, r3, #336 @ 0x150
8007e6a: 687a ldr r2, [r7, #4]
8007e6c: 4413 add r3, r2
8007e6e: 3304 adds r3, #4
8007e70: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
8007e72: 7bbb ldrb r3, [r7, #14]
8007e74: 2b00 cmp r3, #0
8007e76: d002 beq.n 8007e7e <USBD_StdEPReq+0x266>
8007e78: 7bbb ldrb r3, [r7, #14]
8007e7a: 2b80 cmp r3, #128 @ 0x80
8007e7c: d103 bne.n 8007e86 <USBD_StdEPReq+0x26e>
{
pep->status = 0x0000U;
8007e7e: 68bb ldr r3, [r7, #8]
8007e80: 2200 movs r2, #0
8007e82: 601a str r2, [r3, #0]
8007e84: e00e b.n 8007ea4 <USBD_StdEPReq+0x28c>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr))
8007e86: 7bbb ldrb r3, [r7, #14]
8007e88: 4619 mov r1, r3
8007e8a: 6878 ldr r0, [r7, #4]
8007e8c: f001 f850 bl 8008f30 <USBD_LL_IsStallEP>
8007e90: 4603 mov r3, r0
8007e92: 2b00 cmp r3, #0
8007e94: d003 beq.n 8007e9e <USBD_StdEPReq+0x286>
{
pep->status = 0x0001U;
8007e96: 68bb ldr r3, [r7, #8]
8007e98: 2201 movs r2, #1
8007e9a: 601a str r2, [r3, #0]
8007e9c: e002 b.n 8007ea4 <USBD_StdEPReq+0x28c>
}
else
{
pep->status = 0x0000U;
8007e9e: 68bb ldr r3, [r7, #8]
8007ea0: 2200 movs r2, #0
8007ea2: 601a str r2, [r3, #0]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8007ea4: 68bb ldr r3, [r7, #8]
8007ea6: 2202 movs r2, #2
8007ea8: 4619 mov r1, r3
8007eaa: 6878 ldr r0, [r7, #4]
8007eac: f000 fb92 bl 80085d4 <USBD_CtlSendData>
break;
8007eb0: e004 b.n 8007ebc <USBD_StdEPReq+0x2a4>
default:
USBD_CtlError(pdev, req);
8007eb2: 6839 ldr r1, [r7, #0]
8007eb4: 6878 ldr r0, [r7, #4]
8007eb6: f000 fb23 bl 8008500 <USBD_CtlError>
break;
8007eba: bf00 nop
}
break;
8007ebc: e004 b.n 8007ec8 <USBD_StdEPReq+0x2b0>
default:
USBD_CtlError(pdev, req);
8007ebe: 6839 ldr r1, [r7, #0]
8007ec0: 6878 ldr r0, [r7, #4]
8007ec2: f000 fb1d bl 8008500 <USBD_CtlError>
break;
8007ec6: bf00 nop
}
break;
8007ec8: e004 b.n 8007ed4 <USBD_StdEPReq+0x2bc>
default:
USBD_CtlError(pdev, req);
8007eca: 6839 ldr r1, [r7, #0]
8007ecc: 6878 ldr r0, [r7, #4]
8007ece: f000 fb17 bl 8008500 <USBD_CtlError>
break;
8007ed2: bf00 nop
}
return ret;
8007ed4: 7bfb ldrb r3, [r7, #15]
}
8007ed6: 4618 mov r0, r3
8007ed8: 3710 adds r7, #16
8007eda: 46bd mov sp, r7
8007edc: bd80 pop {r7, pc}
...
08007ee0 <USBD_GetDescriptor>:
* @param req: usb request
* @retval status
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8007ee0: b580 push {r7, lr}
8007ee2: b084 sub sp, #16
8007ee4: af00 add r7, sp, #0
8007ee6: 6078 str r0, [r7, #4]
8007ee8: 6039 str r1, [r7, #0]
uint16_t len = 0U;
8007eea: 2300 movs r3, #0
8007eec: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
8007eee: 2300 movs r3, #0
8007ef0: 60fb str r3, [r7, #12]
uint8_t err = 0U;
8007ef2: 2300 movs r3, #0
8007ef4: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
8007ef6: 683b ldr r3, [r7, #0]
8007ef8: 885b ldrh r3, [r3, #2]
8007efa: 0a1b lsrs r3, r3, #8
8007efc: b29b uxth r3, r3
8007efe: 3b01 subs r3, #1
8007f00: 2b06 cmp r3, #6
8007f02: f200 8128 bhi.w 8008156 <USBD_GetDescriptor+0x276>
8007f06: a201 add r2, pc, #4 @ (adr r2, 8007f0c <USBD_GetDescriptor+0x2c>)
8007f08: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007f0c: 08007f29 .word 0x08007f29
8007f10: 08007f41 .word 0x08007f41
8007f14: 08007f81 .word 0x08007f81
8007f18: 08008157 .word 0x08008157
8007f1c: 08008157 .word 0x08008157
8007f20: 080080f7 .word 0x080080f7
8007f24: 08008123 .word 0x08008123
err++;
}
break;
#endif
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
8007f28: 687b ldr r3, [r7, #4]
8007f2a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8007f2e: 681b ldr r3, [r3, #0]
8007f30: 687a ldr r2, [r7, #4]
8007f32: 7c12 ldrb r2, [r2, #16]
8007f34: f107 0108 add.w r1, r7, #8
8007f38: 4610 mov r0, r2
8007f3a: 4798 blx r3
8007f3c: 60f8 str r0, [r7, #12]
break;
8007f3e: e112 b.n 8008166 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8007f40: 687b ldr r3, [r7, #4]
8007f42: 7c1b ldrb r3, [r3, #16]
8007f44: 2b00 cmp r3, #0
8007f46: d10d bne.n 8007f64 <USBD_GetDescriptor+0x84>
{
pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
8007f48: 687b ldr r3, [r7, #4]
8007f4a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007f4e: 6a9b ldr r3, [r3, #40] @ 0x28
8007f50: f107 0208 add.w r2, r7, #8
8007f54: 4610 mov r0, r2
8007f56: 4798 blx r3
8007f58: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8007f5a: 68fb ldr r3, [r7, #12]
8007f5c: 3301 adds r3, #1
8007f5e: 2202 movs r2, #2
8007f60: 701a strb r2, [r3, #0]
else
{
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
8007f62: e100 b.n 8008166 <USBD_GetDescriptor+0x286>
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
8007f64: 687b ldr r3, [r7, #4]
8007f66: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8007f6a: 6adb ldr r3, [r3, #44] @ 0x2c
8007f6c: f107 0208 add.w r2, r7, #8
8007f70: 4610 mov r0, r2
8007f72: 4798 blx r3
8007f74: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8007f76: 68fb ldr r3, [r7, #12]
8007f78: 3301 adds r3, #1
8007f7a: 2202 movs r2, #2
8007f7c: 701a strb r2, [r3, #0]
break;
8007f7e: e0f2 b.n 8008166 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
8007f80: 683b ldr r3, [r7, #0]
8007f82: 885b ldrh r3, [r3, #2]
8007f84: b2db uxtb r3, r3
8007f86: 2b05 cmp r3, #5
8007f88: f200 80ac bhi.w 80080e4 <USBD_GetDescriptor+0x204>
8007f8c: a201 add r2, pc, #4 @ (adr r2, 8007f94 <USBD_GetDescriptor+0xb4>)
8007f8e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007f92: bf00 nop
8007f94: 08007fad .word 0x08007fad
8007f98: 08007fe1 .word 0x08007fe1
8007f9c: 08008015 .word 0x08008015
8007fa0: 08008049 .word 0x08008049
8007fa4: 0800807d .word 0x0800807d
8007fa8: 080080b1 .word 0x080080b1
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
8007fac: 687b ldr r3, [r7, #4]
8007fae: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8007fb2: 685b ldr r3, [r3, #4]
8007fb4: 2b00 cmp r3, #0
8007fb6: d00b beq.n 8007fd0 <USBD_GetDescriptor+0xf0>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
8007fb8: 687b ldr r3, [r7, #4]
8007fba: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8007fbe: 685b ldr r3, [r3, #4]
8007fc0: 687a ldr r2, [r7, #4]
8007fc2: 7c12 ldrb r2, [r2, #16]
8007fc4: f107 0108 add.w r1, r7, #8
8007fc8: 4610 mov r0, r2
8007fca: 4798 blx r3
8007fcc: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8007fce: e091 b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
8007fd0: 6839 ldr r1, [r7, #0]
8007fd2: 6878 ldr r0, [r7, #4]
8007fd4: f000 fa94 bl 8008500 <USBD_CtlError>
err++;
8007fd8: 7afb ldrb r3, [r7, #11]
8007fda: 3301 adds r3, #1
8007fdc: 72fb strb r3, [r7, #11]
break;
8007fde: e089 b.n 80080f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
8007fe0: 687b ldr r3, [r7, #4]
8007fe2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8007fe6: 689b ldr r3, [r3, #8]
8007fe8: 2b00 cmp r3, #0
8007fea: d00b beq.n 8008004 <USBD_GetDescriptor+0x124>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
8007fec: 687b ldr r3, [r7, #4]
8007fee: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8007ff2: 689b ldr r3, [r3, #8]
8007ff4: 687a ldr r2, [r7, #4]
8007ff6: 7c12 ldrb r2, [r2, #16]
8007ff8: f107 0108 add.w r1, r7, #8
8007ffc: 4610 mov r0, r2
8007ffe: 4798 blx r3
8008000: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8008002: e077 b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
8008004: 6839 ldr r1, [r7, #0]
8008006: 6878 ldr r0, [r7, #4]
8008008: f000 fa7a bl 8008500 <USBD_CtlError>
err++;
800800c: 7afb ldrb r3, [r7, #11]
800800e: 3301 adds r3, #1
8008010: 72fb strb r3, [r7, #11]
break;
8008012: e06f b.n 80080f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
8008014: 687b ldr r3, [r7, #4]
8008016: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800801a: 68db ldr r3, [r3, #12]
800801c: 2b00 cmp r3, #0
800801e: d00b beq.n 8008038 <USBD_GetDescriptor+0x158>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
8008020: 687b ldr r3, [r7, #4]
8008022: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8008026: 68db ldr r3, [r3, #12]
8008028: 687a ldr r2, [r7, #4]
800802a: 7c12 ldrb r2, [r2, #16]
800802c: f107 0108 add.w r1, r7, #8
8008030: 4610 mov r0, r2
8008032: 4798 blx r3
8008034: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8008036: e05d b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
8008038: 6839 ldr r1, [r7, #0]
800803a: 6878 ldr r0, [r7, #4]
800803c: f000 fa60 bl 8008500 <USBD_CtlError>
err++;
8008040: 7afb ldrb r3, [r7, #11]
8008042: 3301 adds r3, #1
8008044: 72fb strb r3, [r7, #11]
break;
8008046: e055 b.n 80080f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
8008048: 687b ldr r3, [r7, #4]
800804a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800804e: 691b ldr r3, [r3, #16]
8008050: 2b00 cmp r3, #0
8008052: d00b beq.n 800806c <USBD_GetDescriptor+0x18c>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
8008054: 687b ldr r3, [r7, #4]
8008056: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800805a: 691b ldr r3, [r3, #16]
800805c: 687a ldr r2, [r7, #4]
800805e: 7c12 ldrb r2, [r2, #16]
8008060: f107 0108 add.w r1, r7, #8
8008064: 4610 mov r0, r2
8008066: 4798 blx r3
8008068: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800806a: e043 b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800806c: 6839 ldr r1, [r7, #0]
800806e: 6878 ldr r0, [r7, #4]
8008070: f000 fa46 bl 8008500 <USBD_CtlError>
err++;
8008074: 7afb ldrb r3, [r7, #11]
8008076: 3301 adds r3, #1
8008078: 72fb strb r3, [r7, #11]
break;
800807a: e03b b.n 80080f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
800807c: 687b ldr r3, [r7, #4]
800807e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
8008082: 695b ldr r3, [r3, #20]
8008084: 2b00 cmp r3, #0
8008086: d00b beq.n 80080a0 <USBD_GetDescriptor+0x1c0>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
8008088: 687b ldr r3, [r7, #4]
800808a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
800808e: 695b ldr r3, [r3, #20]
8008090: 687a ldr r2, [r7, #4]
8008092: 7c12 ldrb r2, [r2, #16]
8008094: f107 0108 add.w r1, r7, #8
8008098: 4610 mov r0, r2
800809a: 4798 blx r3
800809c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800809e: e029 b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
80080a0: 6839 ldr r1, [r7, #0]
80080a2: 6878 ldr r0, [r7, #4]
80080a4: f000 fa2c bl 8008500 <USBD_CtlError>
err++;
80080a8: 7afb ldrb r3, [r7, #11]
80080aa: 3301 adds r3, #1
80080ac: 72fb strb r3, [r7, #11]
break;
80080ae: e021 b.n 80080f4 <USBD_GetDescriptor+0x214>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
80080b0: 687b ldr r3, [r7, #4]
80080b2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
80080b6: 699b ldr r3, [r3, #24]
80080b8: 2b00 cmp r3, #0
80080ba: d00b beq.n 80080d4 <USBD_GetDescriptor+0x1f4>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
80080bc: 687b ldr r3, [r7, #4]
80080be: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
80080c2: 699b ldr r3, [r3, #24]
80080c4: 687a ldr r2, [r7, #4]
80080c6: 7c12 ldrb r2, [r2, #16]
80080c8: f107 0108 add.w r1, r7, #8
80080cc: 4610 mov r0, r2
80080ce: 4798 blx r3
80080d0: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
80080d2: e00f b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
80080d4: 6839 ldr r1, [r7, #0]
80080d6: 6878 ldr r0, [r7, #4]
80080d8: f000 fa12 bl 8008500 <USBD_CtlError>
err++;
80080dc: 7afb ldrb r3, [r7, #11]
80080de: 3301 adds r3, #1
80080e0: 72fb strb r3, [r7, #11]
break;
80080e2: e007 b.n 80080f4 <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
err++;
}
break;
#else
USBD_CtlError(pdev, req);
80080e4: 6839 ldr r1, [r7, #0]
80080e6: 6878 ldr r0, [r7, #4]
80080e8: f000 fa0a bl 8008500 <USBD_CtlError>
err++;
80080ec: 7afb ldrb r3, [r7, #11]
80080ee: 3301 adds r3, #1
80080f0: 72fb strb r3, [r7, #11]
#endif
}
break;
80080f2: e038 b.n 8008166 <USBD_GetDescriptor+0x286>
80080f4: e037 b.n 8008166 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
80080f6: 687b ldr r3, [r7, #4]
80080f8: 7c1b ldrb r3, [r3, #16]
80080fa: 2b00 cmp r3, #0
80080fc: d109 bne.n 8008112 <USBD_GetDescriptor+0x232>
{
pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
80080fe: 687b ldr r3, [r7, #4]
8008100: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8008104: 6b5b ldr r3, [r3, #52] @ 0x34
8008106: f107 0208 add.w r2, r7, #8
800810a: 4610 mov r0, r2
800810c: 4798 blx r3
800810e: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8008110: e029 b.n 8008166 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
8008112: 6839 ldr r1, [r7, #0]
8008114: 6878 ldr r0, [r7, #4]
8008116: f000 f9f3 bl 8008500 <USBD_CtlError>
err++;
800811a: 7afb ldrb r3, [r7, #11]
800811c: 3301 adds r3, #1
800811e: 72fb strb r3, [r7, #11]
break;
8008120: e021 b.n 8008166 <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8008122: 687b ldr r3, [r7, #4]
8008124: 7c1b ldrb r3, [r3, #16]
8008126: 2b00 cmp r3, #0
8008128: d10d bne.n 8008146 <USBD_GetDescriptor+0x266>
{
pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
800812a: 687b ldr r3, [r7, #4]
800812c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8008130: 6b1b ldr r3, [r3, #48] @ 0x30
8008132: f107 0208 add.w r2, r7, #8
8008136: 4610 mov r0, r2
8008138: 4798 blx r3
800813a: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
800813c: 68fb ldr r3, [r7, #12]
800813e: 3301 adds r3, #1
8008140: 2207 movs r2, #7
8008142: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8008144: e00f b.n 8008166 <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
8008146: 6839 ldr r1, [r7, #0]
8008148: 6878 ldr r0, [r7, #4]
800814a: f000 f9d9 bl 8008500 <USBD_CtlError>
err++;
800814e: 7afb ldrb r3, [r7, #11]
8008150: 3301 adds r3, #1
8008152: 72fb strb r3, [r7, #11]
break;
8008154: e007 b.n 8008166 <USBD_GetDescriptor+0x286>
default:
USBD_CtlError(pdev, req);
8008156: 6839 ldr r1, [r7, #0]
8008158: 6878 ldr r0, [r7, #4]
800815a: f000 f9d1 bl 8008500 <USBD_CtlError>
err++;
800815e: 7afb ldrb r3, [r7, #11]
8008160: 3301 adds r3, #1
8008162: 72fb strb r3, [r7, #11]
break;
8008164: bf00 nop
}
if (err != 0U)
8008166: 7afb ldrb r3, [r7, #11]
8008168: 2b00 cmp r3, #0
800816a: d11c bne.n 80081a6 <USBD_GetDescriptor+0x2c6>
{
return;
}
else
{
if ((len != 0U) && (req->wLength != 0U))
800816c: 893b ldrh r3, [r7, #8]
800816e: 2b00 cmp r3, #0
8008170: d011 beq.n 8008196 <USBD_GetDescriptor+0x2b6>
8008172: 683b ldr r3, [r7, #0]
8008174: 88db ldrh r3, [r3, #6]
8008176: 2b00 cmp r3, #0
8008178: d00d beq.n 8008196 <USBD_GetDescriptor+0x2b6>
{
len = MIN(len, req->wLength);
800817a: 683b ldr r3, [r7, #0]
800817c: 88da ldrh r2, [r3, #6]
800817e: 893b ldrh r3, [r7, #8]
8008180: 4293 cmp r3, r2
8008182: bf28 it cs
8008184: 4613 movcs r3, r2
8008186: b29b uxth r3, r3
8008188: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
800818a: 893b ldrh r3, [r7, #8]
800818c: 461a mov r2, r3
800818e: 68f9 ldr r1, [r7, #12]
8008190: 6878 ldr r0, [r7, #4]
8008192: f000 fa1f bl 80085d4 <USBD_CtlSendData>
}
if (req->wLength == 0U)
8008196: 683b ldr r3, [r7, #0]
8008198: 88db ldrh r3, [r3, #6]
800819a: 2b00 cmp r3, #0
800819c: d104 bne.n 80081a8 <USBD_GetDescriptor+0x2c8>
{
(void)USBD_CtlSendStatus(pdev);
800819e: 6878 ldr r0, [r7, #4]
80081a0: f000 fa76 bl 8008690 <USBD_CtlSendStatus>
80081a4: e000 b.n 80081a8 <USBD_GetDescriptor+0x2c8>
return;
80081a6: bf00 nop
}
}
}
80081a8: 3710 adds r7, #16
80081aa: 46bd mov sp, r7
80081ac: bd80 pop {r7, pc}
80081ae: bf00 nop
080081b0 <USBD_SetAddress>:
* @param req: usb request
* @retval status
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
80081b0: b580 push {r7, lr}
80081b2: b084 sub sp, #16
80081b4: af00 add r7, sp, #0
80081b6: 6078 str r0, [r7, #4]
80081b8: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
80081ba: 683b ldr r3, [r7, #0]
80081bc: 889b ldrh r3, [r3, #4]
80081be: 2b00 cmp r3, #0
80081c0: d130 bne.n 8008224 <USBD_SetAddress+0x74>
80081c2: 683b ldr r3, [r7, #0]
80081c4: 88db ldrh r3, [r3, #6]
80081c6: 2b00 cmp r3, #0
80081c8: d12c bne.n 8008224 <USBD_SetAddress+0x74>
80081ca: 683b ldr r3, [r7, #0]
80081cc: 885b ldrh r3, [r3, #2]
80081ce: 2b7f cmp r3, #127 @ 0x7f
80081d0: d828 bhi.n 8008224 <USBD_SetAddress+0x74>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
80081d2: 683b ldr r3, [r7, #0]
80081d4: 885b ldrh r3, [r3, #2]
80081d6: b2db uxtb r3, r3
80081d8: f003 037f and.w r3, r3, #127 @ 0x7f
80081dc: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80081de: 687b ldr r3, [r7, #4]
80081e0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80081e4: 2b03 cmp r3, #3
80081e6: d104 bne.n 80081f2 <USBD_SetAddress+0x42>
{
USBD_CtlError(pdev, req);
80081e8: 6839 ldr r1, [r7, #0]
80081ea: 6878 ldr r0, [r7, #4]
80081ec: f000 f988 bl 8008500 <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80081f0: e01d b.n 800822e <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_address = dev_addr;
80081f2: 687b ldr r3, [r7, #4]
80081f4: 7bfa ldrb r2, [r7, #15]
80081f6: f883 229e strb.w r2, [r3, #670] @ 0x29e
USBD_LL_SetUSBAddress(pdev, dev_addr);
80081fa: 7bfb ldrb r3, [r7, #15]
80081fc: 4619 mov r1, r3
80081fe: 6878 ldr r0, [r7, #4]
8008200: f000 fec1 bl 8008f86 <USBD_LL_SetUSBAddress>
USBD_CtlSendStatus(pdev);
8008204: 6878 ldr r0, [r7, #4]
8008206: f000 fa43 bl 8008690 <USBD_CtlSendStatus>
if (dev_addr != 0U)
800820a: 7bfb ldrb r3, [r7, #15]
800820c: 2b00 cmp r3, #0
800820e: d004 beq.n 800821a <USBD_SetAddress+0x6a>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
8008210: 687b ldr r3, [r7, #4]
8008212: 2202 movs r2, #2
8008214: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8008218: e009 b.n 800822e <USBD_SetAddress+0x7e>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
800821a: 687b ldr r3, [r7, #4]
800821c: 2201 movs r2, #1
800821e: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8008222: e004 b.n 800822e <USBD_SetAddress+0x7e>
}
}
}
else
{
USBD_CtlError(pdev, req);
8008224: 6839 ldr r1, [r7, #0]
8008226: 6878 ldr r0, [r7, #4]
8008228: f000 f96a bl 8008500 <USBD_CtlError>
}
}
800822c: bf00 nop
800822e: bf00 nop
8008230: 3710 adds r7, #16
8008232: 46bd mov sp, r7
8008234: bd80 pop {r7, pc}
...
08008238 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8008238: b580 push {r7, lr}
800823a: b082 sub sp, #8
800823c: af00 add r7, sp, #0
800823e: 6078 str r0, [r7, #4]
8008240: 6039 str r1, [r7, #0]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
8008242: 683b ldr r3, [r7, #0]
8008244: 885b ldrh r3, [r3, #2]
8008246: b2da uxtb r2, r3
8008248: 4b41 ldr r3, [pc, #260] @ (8008350 <USBD_SetConfig+0x118>)
800824a: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
800824c: 4b40 ldr r3, [pc, #256] @ (8008350 <USBD_SetConfig+0x118>)
800824e: 781b ldrb r3, [r3, #0]
8008250: 2b01 cmp r3, #1
8008252: d904 bls.n 800825e <USBD_SetConfig+0x26>
{
USBD_CtlError(pdev, req);
8008254: 6839 ldr r1, [r7, #0]
8008256: 6878 ldr r0, [r7, #4]
8008258: f000 f952 bl 8008500 <USBD_CtlError>
800825c: e075 b.n 800834a <USBD_SetConfig+0x112>
}
else
{
switch (pdev->dev_state)
800825e: 687b ldr r3, [r7, #4]
8008260: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8008264: 2b02 cmp r3, #2
8008266: d002 beq.n 800826e <USBD_SetConfig+0x36>
8008268: 2b03 cmp r3, #3
800826a: d023 beq.n 80082b4 <USBD_SetConfig+0x7c>
800826c: e062 b.n 8008334 <USBD_SetConfig+0xfc>
{
case USBD_STATE_ADDRESSED:
if (cfgidx)
800826e: 4b38 ldr r3, [pc, #224] @ (8008350 <USBD_SetConfig+0x118>)
8008270: 781b ldrb r3, [r3, #0]
8008272: 2b00 cmp r3, #0
8008274: d01a beq.n 80082ac <USBD_SetConfig+0x74>
{
pdev->dev_config = cfgidx;
8008276: 4b36 ldr r3, [pc, #216] @ (8008350 <USBD_SetConfig+0x118>)
8008278: 781b ldrb r3, [r3, #0]
800827a: 461a mov r2, r3
800827c: 687b ldr r3, [r7, #4]
800827e: 605a str r2, [r3, #4]
pdev->dev_state = USBD_STATE_CONFIGURED;
8008280: 687b ldr r3, [r7, #4]
8008282: 2203 movs r2, #3
8008284: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
8008288: 4b31 ldr r3, [pc, #196] @ (8008350 <USBD_SetConfig+0x118>)
800828a: 781b ldrb r3, [r3, #0]
800828c: 4619 mov r1, r3
800828e: 6878 ldr r0, [r7, #4]
8008290: f7ff f9e7 bl 8007662 <USBD_SetClassConfig>
8008294: 4603 mov r3, r0
8008296: 2b02 cmp r3, #2
8008298: d104 bne.n 80082a4 <USBD_SetConfig+0x6c>
{
USBD_CtlError(pdev, req);
800829a: 6839 ldr r1, [r7, #0]
800829c: 6878 ldr r0, [r7, #4]
800829e: f000 f92f bl 8008500 <USBD_CtlError>
return;
80082a2: e052 b.n 800834a <USBD_SetConfig+0x112>
}
USBD_CtlSendStatus(pdev);
80082a4: 6878 ldr r0, [r7, #4]
80082a6: f000 f9f3 bl 8008690 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
80082aa: e04e b.n 800834a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
80082ac: 6878 ldr r0, [r7, #4]
80082ae: f000 f9ef bl 8008690 <USBD_CtlSendStatus>
break;
80082b2: e04a b.n 800834a <USBD_SetConfig+0x112>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
80082b4: 4b26 ldr r3, [pc, #152] @ (8008350 <USBD_SetConfig+0x118>)
80082b6: 781b ldrb r3, [r3, #0]
80082b8: 2b00 cmp r3, #0
80082ba: d112 bne.n 80082e2 <USBD_SetConfig+0xaa>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
80082bc: 687b ldr r3, [r7, #4]
80082be: 2202 movs r2, #2
80082c0: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
80082c4: 4b22 ldr r3, [pc, #136] @ (8008350 <USBD_SetConfig+0x118>)
80082c6: 781b ldrb r3, [r3, #0]
80082c8: 461a mov r2, r3
80082ca: 687b ldr r3, [r7, #4]
80082cc: 605a str r2, [r3, #4]
USBD_ClrClassConfig(pdev, cfgidx);
80082ce: 4b20 ldr r3, [pc, #128] @ (8008350 <USBD_SetConfig+0x118>)
80082d0: 781b ldrb r3, [r3, #0]
80082d2: 4619 mov r1, r3
80082d4: 6878 ldr r0, [r7, #4]
80082d6: f7ff f9e3 bl 80076a0 <USBD_ClrClassConfig>
USBD_CtlSendStatus(pdev);
80082da: 6878 ldr r0, [r7, #4]
80082dc: f000 f9d8 bl 8008690 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
80082e0: e033 b.n 800834a <USBD_SetConfig+0x112>
else if (cfgidx != pdev->dev_config)
80082e2: 4b1b ldr r3, [pc, #108] @ (8008350 <USBD_SetConfig+0x118>)
80082e4: 781b ldrb r3, [r3, #0]
80082e6: 461a mov r2, r3
80082e8: 687b ldr r3, [r7, #4]
80082ea: 685b ldr r3, [r3, #4]
80082ec: 429a cmp r2, r3
80082ee: d01d beq.n 800832c <USBD_SetConfig+0xf4>
USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
80082f0: 687b ldr r3, [r7, #4]
80082f2: 685b ldr r3, [r3, #4]
80082f4: b2db uxtb r3, r3
80082f6: 4619 mov r1, r3
80082f8: 6878 ldr r0, [r7, #4]
80082fa: f7ff f9d1 bl 80076a0 <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
80082fe: 4b14 ldr r3, [pc, #80] @ (8008350 <USBD_SetConfig+0x118>)
8008300: 781b ldrb r3, [r3, #0]
8008302: 461a mov r2, r3
8008304: 687b ldr r3, [r7, #4]
8008306: 605a str r2, [r3, #4]
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
8008308: 4b11 ldr r3, [pc, #68] @ (8008350 <USBD_SetConfig+0x118>)
800830a: 781b ldrb r3, [r3, #0]
800830c: 4619 mov r1, r3
800830e: 6878 ldr r0, [r7, #4]
8008310: f7ff f9a7 bl 8007662 <USBD_SetClassConfig>
8008314: 4603 mov r3, r0
8008316: 2b02 cmp r3, #2
8008318: d104 bne.n 8008324 <USBD_SetConfig+0xec>
USBD_CtlError(pdev, req);
800831a: 6839 ldr r1, [r7, #0]
800831c: 6878 ldr r0, [r7, #4]
800831e: f000 f8ef bl 8008500 <USBD_CtlError>
return;
8008322: e012 b.n 800834a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
8008324: 6878 ldr r0, [r7, #4]
8008326: f000 f9b3 bl 8008690 <USBD_CtlSendStatus>
break;
800832a: e00e b.n 800834a <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
800832c: 6878 ldr r0, [r7, #4]
800832e: f000 f9af bl 8008690 <USBD_CtlSendStatus>
break;
8008332: e00a b.n 800834a <USBD_SetConfig+0x112>
default:
USBD_CtlError(pdev, req);
8008334: 6839 ldr r1, [r7, #0]
8008336: 6878 ldr r0, [r7, #4]
8008338: f000 f8e2 bl 8008500 <USBD_CtlError>
USBD_ClrClassConfig(pdev, cfgidx);
800833c: 4b04 ldr r3, [pc, #16] @ (8008350 <USBD_SetConfig+0x118>)
800833e: 781b ldrb r3, [r3, #0]
8008340: 4619 mov r1, r3
8008342: 6878 ldr r0, [r7, #4]
8008344: f7ff f9ac bl 80076a0 <USBD_ClrClassConfig>
break;
8008348: bf00 nop
}
}
}
800834a: 3708 adds r7, #8
800834c: 46bd mov sp, r7
800834e: bd80 pop {r7, pc}
8008350: 20000344 .word 0x20000344
08008354 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8008354: b580 push {r7, lr}
8008356: b082 sub sp, #8
8008358: af00 add r7, sp, #0
800835a: 6078 str r0, [r7, #4]
800835c: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
800835e: 683b ldr r3, [r7, #0]
8008360: 88db ldrh r3, [r3, #6]
8008362: 2b01 cmp r3, #1
8008364: d004 beq.n 8008370 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
8008366: 6839 ldr r1, [r7, #0]
8008368: 6878 ldr r0, [r7, #4]
800836a: f000 f8c9 bl 8008500 <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
800836e: e022 b.n 80083b6 <USBD_GetConfig+0x62>
switch (pdev->dev_state)
8008370: 687b ldr r3, [r7, #4]
8008372: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8008376: 2b02 cmp r3, #2
8008378: dc02 bgt.n 8008380 <USBD_GetConfig+0x2c>
800837a: 2b00 cmp r3, #0
800837c: dc03 bgt.n 8008386 <USBD_GetConfig+0x32>
800837e: e015 b.n 80083ac <USBD_GetConfig+0x58>
8008380: 2b03 cmp r3, #3
8008382: d00b beq.n 800839c <USBD_GetConfig+0x48>
8008384: e012 b.n 80083ac <USBD_GetConfig+0x58>
pdev->dev_default_config = 0U;
8008386: 687b ldr r3, [r7, #4]
8008388: 2200 movs r2, #0
800838a: 609a str r2, [r3, #8]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
800838c: 687b ldr r3, [r7, #4]
800838e: 3308 adds r3, #8
8008390: 2201 movs r2, #1
8008392: 4619 mov r1, r3
8008394: 6878 ldr r0, [r7, #4]
8008396: f000 f91d bl 80085d4 <USBD_CtlSendData>
break;
800839a: e00c b.n 80083b6 <USBD_GetConfig+0x62>
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
800839c: 687b ldr r3, [r7, #4]
800839e: 3304 adds r3, #4
80083a0: 2201 movs r2, #1
80083a2: 4619 mov r1, r3
80083a4: 6878 ldr r0, [r7, #4]
80083a6: f000 f915 bl 80085d4 <USBD_CtlSendData>
break;
80083aa: e004 b.n 80083b6 <USBD_GetConfig+0x62>
USBD_CtlError(pdev, req);
80083ac: 6839 ldr r1, [r7, #0]
80083ae: 6878 ldr r0, [r7, #4]
80083b0: f000 f8a6 bl 8008500 <USBD_CtlError>
break;
80083b4: bf00 nop
}
80083b6: bf00 nop
80083b8: 3708 adds r7, #8
80083ba: 46bd mov sp, r7
80083bc: bd80 pop {r7, pc}
080083be <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80083be: b580 push {r7, lr}
80083c0: b082 sub sp, #8
80083c2: af00 add r7, sp, #0
80083c4: 6078 str r0, [r7, #4]
80083c6: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
80083c8: 687b ldr r3, [r7, #4]
80083ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80083ce: 3b01 subs r3, #1
80083d0: 2b02 cmp r3, #2
80083d2: d81e bhi.n 8008412 <USBD_GetStatus+0x54>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
80083d4: 683b ldr r3, [r7, #0]
80083d6: 88db ldrh r3, [r3, #6]
80083d8: 2b02 cmp r3, #2
80083da: d004 beq.n 80083e6 <USBD_GetStatus+0x28>
{
USBD_CtlError(pdev, req);
80083dc: 6839 ldr r1, [r7, #0]
80083de: 6878 ldr r0, [r7, #4]
80083e0: f000 f88e bl 8008500 <USBD_CtlError>
break;
80083e4: e01a b.n 800841c <USBD_GetStatus+0x5e>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
80083e6: 687b ldr r3, [r7, #4]
80083e8: 2201 movs r2, #1
80083ea: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif
if (pdev->dev_remote_wakeup)
80083ec: 687b ldr r3, [r7, #4]
80083ee: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
80083f2: 2b00 cmp r3, #0
80083f4: d005 beq.n 8008402 <USBD_GetStatus+0x44>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
80083f6: 687b ldr r3, [r7, #4]
80083f8: 68db ldr r3, [r3, #12]
80083fa: f043 0202 orr.w r2, r3, #2
80083fe: 687b ldr r3, [r7, #4]
8008400: 60da str r2, [r3, #12]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
8008402: 687b ldr r3, [r7, #4]
8008404: 330c adds r3, #12
8008406: 2202 movs r2, #2
8008408: 4619 mov r1, r3
800840a: 6878 ldr r0, [r7, #4]
800840c: f000 f8e2 bl 80085d4 <USBD_CtlSendData>
break;
8008410: e004 b.n 800841c <USBD_GetStatus+0x5e>
default:
USBD_CtlError(pdev, req);
8008412: 6839 ldr r1, [r7, #0]
8008414: 6878 ldr r0, [r7, #4]
8008416: f000 f873 bl 8008500 <USBD_CtlError>
break;
800841a: bf00 nop
}
}
800841c: bf00 nop
800841e: 3708 adds r7, #8
8008420: 46bd mov sp, r7
8008422: bd80 pop {r7, pc}
08008424 <USBD_SetFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8008424: b580 push {r7, lr}
8008426: b082 sub sp, #8
8008428: af00 add r7, sp, #0
800842a: 6078 str r0, [r7, #4]
800842c: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
800842e: 683b ldr r3, [r7, #0]
8008430: 885b ldrh r3, [r3, #2]
8008432: 2b01 cmp r3, #1
8008434: d106 bne.n 8008444 <USBD_SetFeature+0x20>
{
pdev->dev_remote_wakeup = 1U;
8008436: 687b ldr r3, [r7, #4]
8008438: 2201 movs r2, #1
800843a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
800843e: 6878 ldr r0, [r7, #4]
8008440: f000 f926 bl 8008690 <USBD_CtlSendStatus>
}
}
8008444: bf00 nop
8008446: 3708 adds r7, #8
8008448: 46bd mov sp, r7
800844a: bd80 pop {r7, pc}
0800844c <USBD_ClrFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800844c: b580 push {r7, lr}
800844e: b082 sub sp, #8
8008450: af00 add r7, sp, #0
8008452: 6078 str r0, [r7, #4]
8008454: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
8008456: 687b ldr r3, [r7, #4]
8008458: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800845c: 3b01 subs r3, #1
800845e: 2b02 cmp r3, #2
8008460: d80b bhi.n 800847a <USBD_ClrFeature+0x2e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
8008462: 683b ldr r3, [r7, #0]
8008464: 885b ldrh r3, [r3, #2]
8008466: 2b01 cmp r3, #1
8008468: d10c bne.n 8008484 <USBD_ClrFeature+0x38>
{
pdev->dev_remote_wakeup = 0U;
800846a: 687b ldr r3, [r7, #4]
800846c: 2200 movs r2, #0
800846e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
USBD_CtlSendStatus(pdev);
8008472: 6878 ldr r0, [r7, #4]
8008474: f000 f90c bl 8008690 <USBD_CtlSendStatus>
}
break;
8008478: e004 b.n 8008484 <USBD_ClrFeature+0x38>
default:
USBD_CtlError(pdev, req);
800847a: 6839 ldr r1, [r7, #0]
800847c: 6878 ldr r0, [r7, #4]
800847e: f000 f83f bl 8008500 <USBD_CtlError>
break;
8008482: e000 b.n 8008486 <USBD_ClrFeature+0x3a>
break;
8008484: bf00 nop
}
}
8008486: bf00 nop
8008488: 3708 adds r7, #8
800848a: 46bd mov sp, r7
800848c: bd80 pop {r7, pc}
0800848e <USBD_ParseSetupRequest>:
* @param req: usb request
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
800848e: b480 push {r7}
8008490: b083 sub sp, #12
8008492: af00 add r7, sp, #0
8008494: 6078 str r0, [r7, #4]
8008496: 6039 str r1, [r7, #0]
req->bmRequest = *(uint8_t *)(pdata);
8008498: 683b ldr r3, [r7, #0]
800849a: 781a ldrb r2, [r3, #0]
800849c: 687b ldr r3, [r7, #4]
800849e: 701a strb r2, [r3, #0]
req->bRequest = *(uint8_t *)(pdata + 1U);
80084a0: 683b ldr r3, [r7, #0]
80084a2: 785a ldrb r2, [r3, #1]
80084a4: 687b ldr r3, [r7, #4]
80084a6: 705a strb r2, [r3, #1]
req->wValue = SWAPBYTE(pdata + 2U);
80084a8: 683b ldr r3, [r7, #0]
80084aa: 3302 adds r3, #2
80084ac: 781b ldrb r3, [r3, #0]
80084ae: 461a mov r2, r3
80084b0: 683b ldr r3, [r7, #0]
80084b2: 3303 adds r3, #3
80084b4: 781b ldrb r3, [r3, #0]
80084b6: 021b lsls r3, r3, #8
80084b8: b29b uxth r3, r3
80084ba: 4413 add r3, r2
80084bc: b29a uxth r2, r3
80084be: 687b ldr r3, [r7, #4]
80084c0: 805a strh r2, [r3, #2]
req->wIndex = SWAPBYTE(pdata + 4U);
80084c2: 683b ldr r3, [r7, #0]
80084c4: 3304 adds r3, #4
80084c6: 781b ldrb r3, [r3, #0]
80084c8: 461a mov r2, r3
80084ca: 683b ldr r3, [r7, #0]
80084cc: 3305 adds r3, #5
80084ce: 781b ldrb r3, [r3, #0]
80084d0: 021b lsls r3, r3, #8
80084d2: b29b uxth r3, r3
80084d4: 4413 add r3, r2
80084d6: b29a uxth r2, r3
80084d8: 687b ldr r3, [r7, #4]
80084da: 809a strh r2, [r3, #4]
req->wLength = SWAPBYTE(pdata + 6U);
80084dc: 683b ldr r3, [r7, #0]
80084de: 3306 adds r3, #6
80084e0: 781b ldrb r3, [r3, #0]
80084e2: 461a mov r2, r3
80084e4: 683b ldr r3, [r7, #0]
80084e6: 3307 adds r3, #7
80084e8: 781b ldrb r3, [r3, #0]
80084ea: 021b lsls r3, r3, #8
80084ec: b29b uxth r3, r3
80084ee: 4413 add r3, r2
80084f0: b29a uxth r2, r3
80084f2: 687b ldr r3, [r7, #4]
80084f4: 80da strh r2, [r3, #6]
}
80084f6: bf00 nop
80084f8: 370c adds r7, #12
80084fa: 46bd mov sp, r7
80084fc: bc80 pop {r7}
80084fe: 4770 bx lr
08008500 <USBD_CtlError>:
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8008500: b580 push {r7, lr}
8008502: b082 sub sp, #8
8008504: af00 add r7, sp, #0
8008506: 6078 str r0, [r7, #4]
8008508: 6039 str r1, [r7, #0]
USBD_LL_StallEP(pdev, 0x80U);
800850a: 2180 movs r1, #128 @ 0x80
800850c: 6878 ldr r0, [r7, #4]
800850e: f000 fcd1 bl 8008eb4 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0U);
8008512: 2100 movs r1, #0
8008514: 6878 ldr r0, [r7, #4]
8008516: f000 fccd bl 8008eb4 <USBD_LL_StallEP>
}
800851a: bf00 nop
800851c: 3708 adds r7, #8
800851e: 46bd mov sp, r7
8008520: bd80 pop {r7, pc}
08008522 <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
8008522: b580 push {r7, lr}
8008524: b086 sub sp, #24
8008526: af00 add r7, sp, #0
8008528: 60f8 str r0, [r7, #12]
800852a: 60b9 str r1, [r7, #8]
800852c: 607a str r2, [r7, #4]
uint8_t idx = 0U;
800852e: 2300 movs r3, #0
8008530: 75fb strb r3, [r7, #23]
if (desc != NULL)
8008532: 68fb ldr r3, [r7, #12]
8008534: 2b00 cmp r3, #0
8008536: d032 beq.n 800859e <USBD_GetString+0x7c>
{
*len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
8008538: 68f8 ldr r0, [r7, #12]
800853a: f000 f834 bl 80085a6 <USBD_GetLen>
800853e: 4603 mov r3, r0
8008540: 3301 adds r3, #1
8008542: b29b uxth r3, r3
8008544: 005b lsls r3, r3, #1
8008546: b29a uxth r2, r3
8008548: 687b ldr r3, [r7, #4]
800854a: 801a strh r2, [r3, #0]
unicode[idx++] = *(uint8_t *)(void *)len;
800854c: 7dfb ldrb r3, [r7, #23]
800854e: 1c5a adds r2, r3, #1
8008550: 75fa strb r2, [r7, #23]
8008552: 461a mov r2, r3
8008554: 68bb ldr r3, [r7, #8]
8008556: 4413 add r3, r2
8008558: 687a ldr r2, [r7, #4]
800855a: 7812 ldrb r2, [r2, #0]
800855c: 701a strb r2, [r3, #0]
unicode[idx++] = USB_DESC_TYPE_STRING;
800855e: 7dfb ldrb r3, [r7, #23]
8008560: 1c5a adds r2, r3, #1
8008562: 75fa strb r2, [r7, #23]
8008564: 461a mov r2, r3
8008566: 68bb ldr r3, [r7, #8]
8008568: 4413 add r3, r2
800856a: 2203 movs r2, #3
800856c: 701a strb r2, [r3, #0]
while (*desc != '\0')
800856e: e012 b.n 8008596 <USBD_GetString+0x74>
{
unicode[idx++] = *desc++;
8008570: 68fb ldr r3, [r7, #12]
8008572: 1c5a adds r2, r3, #1
8008574: 60fa str r2, [r7, #12]
8008576: 7dfa ldrb r2, [r7, #23]
8008578: 1c51 adds r1, r2, #1
800857a: 75f9 strb r1, [r7, #23]
800857c: 4611 mov r1, r2
800857e: 68ba ldr r2, [r7, #8]
8008580: 440a add r2, r1
8008582: 781b ldrb r3, [r3, #0]
8008584: 7013 strb r3, [r2, #0]
unicode[idx++] = 0U;
8008586: 7dfb ldrb r3, [r7, #23]
8008588: 1c5a adds r2, r3, #1
800858a: 75fa strb r2, [r7, #23]
800858c: 461a mov r2, r3
800858e: 68bb ldr r3, [r7, #8]
8008590: 4413 add r3, r2
8008592: 2200 movs r2, #0
8008594: 701a strb r2, [r3, #0]
while (*desc != '\0')
8008596: 68fb ldr r3, [r7, #12]
8008598: 781b ldrb r3, [r3, #0]
800859a: 2b00 cmp r3, #0
800859c: d1e8 bne.n 8008570 <USBD_GetString+0x4e>
}
}
}
800859e: bf00 nop
80085a0: 3718 adds r7, #24
80085a2: 46bd mov sp, r7
80085a4: bd80 pop {r7, pc}
080085a6 <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
80085a6: b480 push {r7}
80085a8: b085 sub sp, #20
80085aa: af00 add r7, sp, #0
80085ac: 6078 str r0, [r7, #4]
uint8_t len = 0U;
80085ae: 2300 movs r3, #0
80085b0: 73fb strb r3, [r7, #15]
while (*buf != '\0')
80085b2: e005 b.n 80085c0 <USBD_GetLen+0x1a>
{
len++;
80085b4: 7bfb ldrb r3, [r7, #15]
80085b6: 3301 adds r3, #1
80085b8: 73fb strb r3, [r7, #15]
buf++;
80085ba: 687b ldr r3, [r7, #4]
80085bc: 3301 adds r3, #1
80085be: 607b str r3, [r7, #4]
while (*buf != '\0')
80085c0: 687b ldr r3, [r7, #4]
80085c2: 781b ldrb r3, [r3, #0]
80085c4: 2b00 cmp r3, #0
80085c6: d1f5 bne.n 80085b4 <USBD_GetLen+0xe>
}
return len;
80085c8: 7bfb ldrb r3, [r7, #15]
}
80085ca: 4618 mov r0, r3
80085cc: 3714 adds r7, #20
80085ce: 46bd mov sp, r7
80085d0: bc80 pop {r7}
80085d2: 4770 bx lr
080085d4 <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
80085d4: b580 push {r7, lr}
80085d6: b084 sub sp, #16
80085d8: af00 add r7, sp, #0
80085da: 60f8 str r0, [r7, #12]
80085dc: 60b9 str r1, [r7, #8]
80085de: 4613 mov r3, r2
80085e0: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
80085e2: 68fb ldr r3, [r7, #12]
80085e4: 2202 movs r2, #2
80085e6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
80085ea: 88fa ldrh r2, [r7, #6]
80085ec: 68fb ldr r3, [r7, #12]
80085ee: 61da str r2, [r3, #28]
pdev->ep_in[0].rem_length = len;
80085f0: 88fa ldrh r2, [r7, #6]
80085f2: 68fb ldr r3, [r7, #12]
80085f4: 621a str r2, [r3, #32]
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
80085f6: 88fb ldrh r3, [r7, #6]
80085f8: 68ba ldr r2, [r7, #8]
80085fa: 2100 movs r1, #0
80085fc: 68f8 ldr r0, [r7, #12]
80085fe: f000 fce1 bl 8008fc4 <USBD_LL_Transmit>
return USBD_OK;
8008602: 2300 movs r3, #0
}
8008604: 4618 mov r0, r3
8008606: 3710 adds r7, #16
8008608: 46bd mov sp, r7
800860a: bd80 pop {r7, pc}
0800860c <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800860c: b580 push {r7, lr}
800860e: b084 sub sp, #16
8008610: af00 add r7, sp, #0
8008612: 60f8 str r0, [r7, #12]
8008614: 60b9 str r1, [r7, #8]
8008616: 4613 mov r3, r2
8008618: 80fb strh r3, [r7, #6]
/* Start the next transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800861a: 88fb ldrh r3, [r7, #6]
800861c: 68ba ldr r2, [r7, #8]
800861e: 2100 movs r1, #0
8008620: 68f8 ldr r0, [r7, #12]
8008622: f000 fccf bl 8008fc4 <USBD_LL_Transmit>
return USBD_OK;
8008626: 2300 movs r3, #0
}
8008628: 4618 mov r0, r3
800862a: 3710 adds r7, #16
800862c: 46bd mov sp, r7
800862e: bd80 pop {r7, pc}
08008630 <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
8008630: b580 push {r7, lr}
8008632: b084 sub sp, #16
8008634: af00 add r7, sp, #0
8008636: 60f8 str r0, [r7, #12]
8008638: 60b9 str r1, [r7, #8]
800863a: 4613 mov r3, r2
800863c: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
800863e: 68fb ldr r3, [r7, #12]
8008640: 2203 movs r2, #3
8008642: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_out[0].total_length = len;
8008646: 88fa ldrh r2, [r7, #6]
8008648: 68fb ldr r3, [r7, #12]
800864a: f8c3 215c str.w r2, [r3, #348] @ 0x15c
pdev->ep_out[0].rem_length = len;
800864e: 88fa ldrh r2, [r7, #6]
8008650: 68fb ldr r3, [r7, #12]
8008652: f8c3 2160 str.w r2, [r3, #352] @ 0x160
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
8008656: 88fb ldrh r3, [r7, #6]
8008658: 68ba ldr r2, [r7, #8]
800865a: 2100 movs r1, #0
800865c: 68f8 ldr r0, [r7, #12]
800865e: f000 fcd4 bl 800900a <USBD_LL_PrepareReceive>
return USBD_OK;
8008662: 2300 movs r3, #0
}
8008664: 4618 mov r0, r3
8008666: 3710 adds r7, #16
8008668: 46bd mov sp, r7
800866a: bd80 pop {r7, pc}
0800866c <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800866c: b580 push {r7, lr}
800866e: b084 sub sp, #16
8008670: af00 add r7, sp, #0
8008672: 60f8 str r0, [r7, #12]
8008674: 60b9 str r1, [r7, #8]
8008676: 4613 mov r3, r2
8008678: 80fb strh r3, [r7, #6]
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
800867a: 88fb ldrh r3, [r7, #6]
800867c: 68ba ldr r2, [r7, #8]
800867e: 2100 movs r1, #0
8008680: 68f8 ldr r0, [r7, #12]
8008682: f000 fcc2 bl 800900a <USBD_LL_PrepareReceive>
return USBD_OK;
8008686: 2300 movs r3, #0
}
8008688: 4618 mov r0, r3
800868a: 3710 adds r7, #16
800868c: 46bd mov sp, r7
800868e: bd80 pop {r7, pc}
08008690 <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
8008690: b580 push {r7, lr}
8008692: b082 sub sp, #8
8008694: af00 add r7, sp, #0
8008696: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
8008698: 687b ldr r3, [r7, #4]
800869a: 2204 movs r2, #4
800869c: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
80086a0: 2300 movs r3, #0
80086a2: 2200 movs r2, #0
80086a4: 2100 movs r1, #0
80086a6: 6878 ldr r0, [r7, #4]
80086a8: f000 fc8c bl 8008fc4 <USBD_LL_Transmit>
return USBD_OK;
80086ac: 2300 movs r3, #0
}
80086ae: 4618 mov r0, r3
80086b0: 3708 adds r7, #8
80086b2: 46bd mov sp, r7
80086b4: bd80 pop {r7, pc}
080086b6 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
80086b6: b580 push {r7, lr}
80086b8: b082 sub sp, #8
80086ba: af00 add r7, sp, #0
80086bc: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
80086be: 687b ldr r3, [r7, #4]
80086c0: 2205 movs r2, #5
80086c2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80086c6: 2300 movs r3, #0
80086c8: 2200 movs r2, #0
80086ca: 2100 movs r1, #0
80086cc: 6878 ldr r0, [r7, #4]
80086ce: f000 fc9c bl 800900a <USBD_LL_PrepareReceive>
return USBD_OK;
80086d2: 2300 movs r3, #0
}
80086d4: 4618 mov r0, r3
80086d6: 3708 adds r7, #8
80086d8: 46bd mov sp, r7
80086da: bd80 pop {r7, pc}
080086dc <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
80086dc: b580 push {r7, lr}
80086de: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
80086e0: 2200 movs r2, #0
80086e2: 4912 ldr r1, [pc, #72] @ (800872c <MX_USB_DEVICE_Init+0x50>)
80086e4: 4812 ldr r0, [pc, #72] @ (8008730 <MX_USB_DEVICE_Init+0x54>)
80086e6: f7fe ff62 bl 80075ae <USBD_Init>
80086ea: 4603 mov r3, r0
80086ec: 2b00 cmp r3, #0
80086ee: d001 beq.n 80086f4 <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
80086f0: f7f8 f97a bl 80009e8 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
80086f4: 490f ldr r1, [pc, #60] @ (8008734 <MX_USB_DEVICE_Init+0x58>)
80086f6: 480e ldr r0, [pc, #56] @ (8008730 <MX_USB_DEVICE_Init+0x54>)
80086f8: f7fe ff84 bl 8007604 <USBD_RegisterClass>
80086fc: 4603 mov r3, r0
80086fe: 2b00 cmp r3, #0
8008700: d001 beq.n 8008706 <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
8008702: f7f8 f971 bl 80009e8 <Error_Handler>
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
8008706: 490c ldr r1, [pc, #48] @ (8008738 <MX_USB_DEVICE_Init+0x5c>)
8008708: 4809 ldr r0, [pc, #36] @ (8008730 <MX_USB_DEVICE_Init+0x54>)
800870a: f7fe feb5 bl 8007478 <USBD_CDC_RegisterInterface>
800870e: 4603 mov r3, r0
8008710: 2b00 cmp r3, #0
8008712: d001 beq.n 8008718 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
8008714: f7f8 f968 bl 80009e8 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
8008718: 4805 ldr r0, [pc, #20] @ (8008730 <MX_USB_DEVICE_Init+0x54>)
800871a: f7fe ff8c bl 8007636 <USBD_Start>
800871e: 4603 mov r3, r0
8008720: 2b00 cmp r3, #0
8008722: d001 beq.n 8008728 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
8008724: f7f8 f960 bl 80009e8 <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
8008728: bf00 nop
800872a: bd80 pop {r7, pc}
800872c: 2000012c .word 0x2000012c
8008730: 20000348 .word 0x20000348
8008734: 20000018 .word 0x20000018
8008738: 2000011c .word 0x2000011c
0800873c <fifo_push>:
/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
#define RX_FIFO_SZ 256
static uint8_t rx_fifo[RX_FIFO_SZ];
static volatile uint16_t rx_head = 0, rx_tail = 0;
static void fifo_push(const uint8_t* data, uint32_t len) {
800873c: b480 push {r7}
800873e: b085 sub sp, #20
8008740: af00 add r7, sp, #0
8008742: 6078 str r0, [r7, #4]
8008744: 6039 str r1, [r7, #0]
while (len--) {
8008746: e01e b.n 8008786 <fifo_push+0x4a>
uint16_t next = (rx_head + 1u) & (RX_FIFO_SZ - 1u);
8008748: 4b14 ldr r3, [pc, #80] @ (800879c <fifo_push+0x60>)
800874a: 881b ldrh r3, [r3, #0]
800874c: b29b uxth r3, r3
800874e: 3301 adds r3, #1
8008750: b29b uxth r3, r3
8008752: b2db uxtb r3, r3
8008754: 81fb strh r3, [r7, #14]
if (next == (rx_tail & (RX_FIFO_SZ - 1u))) {
8008756: 89fa ldrh r2, [r7, #14]
8008758: 4b11 ldr r3, [pc, #68] @ (80087a0 <fifo_push+0x64>)
800875a: 881b ldrh r3, [r3, #0]
800875c: b29b uxth r3, r3
800875e: b2db uxtb r3, r3
8008760: 429a cmp r2, r3
8008762: d103 bne.n 800876c <fifo_push+0x30>
/* overflow — drop byte (or set a flag) */
data++;
8008764: 687b ldr r3, [r7, #4]
8008766: 3301 adds r3, #1
8008768: 607b str r3, [r7, #4]
continue;
800876a: e00c b.n 8008786 <fifo_push+0x4a>
}
rx_fifo[rx_head & (RX_FIFO_SZ - 1u)] = *data++;
800876c: 687b ldr r3, [r7, #4]
800876e: 1c5a adds r2, r3, #1
8008770: 607a str r2, [r7, #4]
8008772: 4a0a ldr r2, [pc, #40] @ (800879c <fifo_push+0x60>)
8008774: 8812 ldrh r2, [r2, #0]
8008776: b292 uxth r2, r2
8008778: b2d2 uxtb r2, r2
800877a: 7819 ldrb r1, [r3, #0]
800877c: 4b09 ldr r3, [pc, #36] @ (80087a4 <fifo_push+0x68>)
800877e: 5499 strb r1, [r3, r2]
rx_head = next;
8008780: 4a06 ldr r2, [pc, #24] @ (800879c <fifo_push+0x60>)
8008782: 89fb ldrh r3, [r7, #14]
8008784: 8013 strh r3, [r2, #0]
while (len--) {
8008786: 683b ldr r3, [r7, #0]
8008788: 1e5a subs r2, r3, #1
800878a: 603a str r2, [r7, #0]
800878c: 2b00 cmp r3, #0
800878e: d1db bne.n 8008748 <fifo_push+0xc>
}
}
8008790: bf00 nop
8008792: bf00 nop
8008794: 3714 adds r7, #20
8008796: 46bd mov sp, r7
8008798: bc80 pop {r7}
800879a: 4770 bx lr
800879c: 20000f0c .word 0x20000f0c
80087a0: 20000f0e .word 0x20000f0e
80087a4: 20000e0c .word 0x20000e0c
080087a8 <CDC_Available>:
uint32_t CDC_Available(void) {
80087a8: b480 push {r7}
80087aa: af00 add r7, sp, #0
return (uint16_t)((rx_head - rx_tail) & (RX_FIFO_SZ - 1u));
80087ac: 4b06 ldr r3, [pc, #24] @ (80087c8 <CDC_Available+0x20>)
80087ae: 881b ldrh r3, [r3, #0]
80087b0: b29a uxth r2, r3
80087b2: 4b06 ldr r3, [pc, #24] @ (80087cc <CDC_Available+0x24>)
80087b4: 881b ldrh r3, [r3, #0]
80087b6: b29b uxth r3, r3
80087b8: 1ad3 subs r3, r2, r3
80087ba: b29b uxth r3, r3
80087bc: b2db uxtb r3, r3
}
80087be: 4618 mov r0, r3
80087c0: 46bd mov sp, r7
80087c2: bc80 pop {r7}
80087c4: 4770 bx lr
80087c6: bf00 nop
80087c8: 20000f0c .word 0x20000f0c
80087cc: 20000f0e .word 0x20000f0e
080087d0 <CDC_ReadByte>:
int CDC_ReadByte(void) {
80087d0: b480 push {r7}
80087d2: b083 sub sp, #12
80087d4: af00 add r7, sp, #0
if (rx_tail == rx_head) return -1;
80087d6: 4b10 ldr r3, [pc, #64] @ (8008818 <CDC_ReadByte+0x48>)
80087d8: 881b ldrh r3, [r3, #0]
80087da: b29a uxth r2, r3
80087dc: 4b0f ldr r3, [pc, #60] @ (800881c <CDC_ReadByte+0x4c>)
80087de: 881b ldrh r3, [r3, #0]
80087e0: b29b uxth r3, r3
80087e2: 429a cmp r2, r3
80087e4: d102 bne.n 80087ec <CDC_ReadByte+0x1c>
80087e6: f04f 33ff mov.w r3, #4294967295
80087ea: e010 b.n 800880e <CDC_ReadByte+0x3e>
int b = rx_fifo[rx_tail & (RX_FIFO_SZ - 1u)];
80087ec: 4b0a ldr r3, [pc, #40] @ (8008818 <CDC_ReadByte+0x48>)
80087ee: 881b ldrh r3, [r3, #0]
80087f0: b29b uxth r3, r3
80087f2: b2db uxtb r3, r3
80087f4: 4a0a ldr r2, [pc, #40] @ (8008820 <CDC_ReadByte+0x50>)
80087f6: 5cd3 ldrb r3, [r2, r3]
80087f8: 607b str r3, [r7, #4]
rx_tail = (rx_tail + 1u) & (RX_FIFO_SZ - 1u);
80087fa: 4b07 ldr r3, [pc, #28] @ (8008818 <CDC_ReadByte+0x48>)
80087fc: 881b ldrh r3, [r3, #0]
80087fe: b29b uxth r3, r3
8008800: 3301 adds r3, #1
8008802: b29b uxth r3, r3
8008804: b2db uxtb r3, r3
8008806: b29a uxth r2, r3
8008808: 4b03 ldr r3, [pc, #12] @ (8008818 <CDC_ReadByte+0x48>)
800880a: 801a strh r2, [r3, #0]
return b;
800880c: 687b ldr r3, [r7, #4]
}
800880e: 4618 mov r0, r3
8008810: 370c adds r7, #12
8008812: 46bd mov sp, r7
8008814: bc80 pop {r7}
8008816: 4770 bx lr
8008818: 20000f0e .word 0x20000f0e
800881c: 20000f0c .word 0x20000f0c
8008820: 20000e0c .word 0x20000e0c
08008824 <CDC_Init_FS>:
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
8008824: b580 push {r7, lr}
8008826: af00 add r7, sp, #0
/* USER CODE BEGIN 3 */
/* Set Application Buffers */
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
8008828: 2200 movs r2, #0
800882a: 4905 ldr r1, [pc, #20] @ (8008840 <CDC_Init_FS+0x1c>)
800882c: 4805 ldr r0, [pc, #20] @ (8008844 <CDC_Init_FS+0x20>)
800882e: f7fe fe39 bl 80074a4 <USBD_CDC_SetTxBuffer>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
8008832: 4905 ldr r1, [pc, #20] @ (8008848 <CDC_Init_FS+0x24>)
8008834: 4803 ldr r0, [pc, #12] @ (8008844 <CDC_Init_FS+0x20>)
8008836: f7fe fe4e bl 80074d6 <USBD_CDC_SetRxBuffer>
return (USBD_OK);
800883a: 2300 movs r3, #0
/* USER CODE END 3 */
}
800883c: 4618 mov r0, r3
800883e: bd80 pop {r7, pc}
8008840: 20000a0c .word 0x20000a0c
8008844: 20000348 .word 0x20000348
8008848: 2000060c .word 0x2000060c
0800884c <CDC_DeInit_FS>:
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
800884c: b480 push {r7}
800884e: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
8008850: 2300 movs r3, #0
/* USER CODE END 4 */
}
8008852: 4618 mov r0, r3
8008854: 46bd mov sp, r7
8008856: bc80 pop {r7}
8008858: 4770 bx lr
...
0800885c <CDC_Control_FS>:
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
800885c: b480 push {r7}
800885e: b083 sub sp, #12
8008860: af00 add r7, sp, #0
8008862: 4603 mov r3, r0
8008864: 6039 str r1, [r7, #0]
8008866: 71fb strb r3, [r7, #7]
8008868: 4613 mov r3, r2
800886a: 80bb strh r3, [r7, #4]
/* USER CODE BEGIN 5 */
switch(cmd)
800886c: 79fb ldrb r3, [r7, #7]
800886e: 2b23 cmp r3, #35 @ 0x23
8008870: d84a bhi.n 8008908 <CDC_Control_FS+0xac>
8008872: a201 add r2, pc, #4 @ (adr r2, 8008878 <CDC_Control_FS+0x1c>)
8008874: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8008878: 08008909 .word 0x08008909
800887c: 08008909 .word 0x08008909
8008880: 08008909 .word 0x08008909
8008884: 08008909 .word 0x08008909
8008888: 08008909 .word 0x08008909
800888c: 08008909 .word 0x08008909
8008890: 08008909 .word 0x08008909
8008894: 08008909 .word 0x08008909
8008898: 08008909 .word 0x08008909
800889c: 08008909 .word 0x08008909
80088a0: 08008909 .word 0x08008909
80088a4: 08008909 .word 0x08008909
80088a8: 08008909 .word 0x08008909
80088ac: 08008909 .word 0x08008909
80088b0: 08008909 .word 0x08008909
80088b4: 08008909 .word 0x08008909
80088b8: 08008909 .word 0x08008909
80088bc: 08008909 .word 0x08008909
80088c0: 08008909 .word 0x08008909
80088c4: 08008909 .word 0x08008909
80088c8: 08008909 .word 0x08008909
80088cc: 08008909 .word 0x08008909
80088d0: 08008909 .word 0x08008909
80088d4: 08008909 .word 0x08008909
80088d8: 08008909 .word 0x08008909
80088dc: 08008909 .word 0x08008909
80088e0: 08008909 .word 0x08008909
80088e4: 08008909 .word 0x08008909
80088e8: 08008909 .word 0x08008909
80088ec: 08008909 .word 0x08008909
80088f0: 08008909 .word 0x08008909
80088f4: 08008909 .word 0x08008909
80088f8: 08008909 .word 0x08008909
80088fc: 08008909 .word 0x08008909
8008900: 08008909 .word 0x08008909
8008904: 08008909 .word 0x08008909
case CDC_SEND_BREAK:
break;
default:
break;
8008908: bf00 nop
}
return (USBD_OK);
800890a: 2300 movs r3, #0
/* USER CODE END 5 */
}
800890c: 4618 mov r0, r3
800890e: 370c adds r7, #12
8008910: 46bd mov sp, r7
8008912: bc80 pop {r7}
8008914: 4770 bx lr
8008916: bf00 nop
08008918 <CDC_Receive_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
8008918: b580 push {r7, lr}
800891a: b082 sub sp, #8
800891c: af00 add r7, sp, #0
800891e: 6078 str r0, [r7, #4]
8008920: 6039 str r1, [r7, #0]
/* USER CODE BEGIN 6 */
if (*Len) fifo_push(Buf, *Len);
8008922: 683b ldr r3, [r7, #0]
8008924: 681b ldr r3, [r3, #0]
8008926: 2b00 cmp r3, #0
8008928: d005 beq.n 8008936 <CDC_Receive_FS+0x1e>
800892a: 683b ldr r3, [r7, #0]
800892c: 681b ldr r3, [r3, #0]
800892e: 4619 mov r1, r3
8008930: 6878 ldr r0, [r7, #4]
8008932: f7ff ff03 bl 800873c <fifo_push>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
8008936: 6879 ldr r1, [r7, #4]
8008938: 4805 ldr r0, [pc, #20] @ (8008950 <CDC_Receive_FS+0x38>)
800893a: f7fe fdcc bl 80074d6 <USBD_CDC_SetRxBuffer>
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
800893e: 4804 ldr r0, [pc, #16] @ (8008950 <CDC_Receive_FS+0x38>)
8008940: f7fe fe0b bl 800755a <USBD_CDC_ReceivePacket>
return (USBD_OK);
8008944: 2300 movs r3, #0
/* USER CODE END 6 */
}
8008946: 4618 mov r0, r3
8008948: 3708 adds r7, #8
800894a: 46bd mov sp, r7
800894c: bd80 pop {r7, pc}
800894e: bf00 nop
8008950: 20000348 .word 0x20000348
08008954 <CDC_Transmit_FS>:
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
8008954: b580 push {r7, lr}
8008956: b084 sub sp, #16
8008958: af00 add r7, sp, #0
800895a: 6078 str r0, [r7, #4]
800895c: 460b mov r3, r1
800895e: 807b strh r3, [r7, #2]
uint8_t result = USBD_OK;
8008960: 2300 movs r3, #0
8008962: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
8008964: 4b0d ldr r3, [pc, #52] @ (800899c <CDC_Transmit_FS+0x48>)
8008966: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800896a: 60bb str r3, [r7, #8]
if (hcdc->TxState != 0){
800896c: 68bb ldr r3, [r7, #8]
800896e: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
8008972: 2b00 cmp r3, #0
8008974: d001 beq.n 800897a <CDC_Transmit_FS+0x26>
return USBD_BUSY;
8008976: 2301 movs r3, #1
8008978: e00b b.n 8008992 <CDC_Transmit_FS+0x3e>
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
800897a: 887b ldrh r3, [r7, #2]
800897c: 461a mov r2, r3
800897e: 6879 ldr r1, [r7, #4]
8008980: 4806 ldr r0, [pc, #24] @ (800899c <CDC_Transmit_FS+0x48>)
8008982: f7fe fd8f bl 80074a4 <USBD_CDC_SetTxBuffer>
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
8008986: 4805 ldr r0, [pc, #20] @ (800899c <CDC_Transmit_FS+0x48>)
8008988: f7fe fdb8 bl 80074fc <USBD_CDC_TransmitPacket>
800898c: 4603 mov r3, r0
800898e: 73fb strb r3, [r7, #15]
/* USER CODE END 7 */
return result;
8008990: 7bfb ldrb r3, [r7, #15]
}
8008992: 4618 mov r0, r3
8008994: 3710 adds r7, #16
8008996: 46bd mov sp, r7
8008998: bd80 pop {r7, pc}
800899a: bf00 nop
800899c: 20000348 .word 0x20000348
080089a0 <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80089a0: b480 push {r7}
80089a2: b083 sub sp, #12
80089a4: af00 add r7, sp, #0
80089a6: 4603 mov r3, r0
80089a8: 6039 str r1, [r7, #0]
80089aa: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
80089ac: 683b ldr r3, [r7, #0]
80089ae: 2212 movs r2, #18
80089b0: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
80089b2: 4b03 ldr r3, [pc, #12] @ (80089c0 <USBD_FS_DeviceDescriptor+0x20>)
}
80089b4: 4618 mov r0, r3
80089b6: 370c adds r7, #12
80089b8: 46bd mov sp, r7
80089ba: bc80 pop {r7}
80089bc: 4770 bx lr
80089be: bf00 nop
80089c0: 20000148 .word 0x20000148
080089c4 <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80089c4: b480 push {r7}
80089c6: b083 sub sp, #12
80089c8: af00 add r7, sp, #0
80089ca: 4603 mov r3, r0
80089cc: 6039 str r1, [r7, #0]
80089ce: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
80089d0: 683b ldr r3, [r7, #0]
80089d2: 2204 movs r2, #4
80089d4: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
80089d6: 4b03 ldr r3, [pc, #12] @ (80089e4 <USBD_FS_LangIDStrDescriptor+0x20>)
}
80089d8: 4618 mov r0, r3
80089da: 370c adds r7, #12
80089dc: 46bd mov sp, r7
80089de: bc80 pop {r7}
80089e0: 4770 bx lr
80089e2: bf00 nop
80089e4: 2000015c .word 0x2000015c
080089e8 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80089e8: b580 push {r7, lr}
80089ea: b082 sub sp, #8
80089ec: af00 add r7, sp, #0
80089ee: 4603 mov r3, r0
80089f0: 6039 str r1, [r7, #0]
80089f2: 71fb strb r3, [r7, #7]
if(speed == 0)
80089f4: 79fb ldrb r3, [r7, #7]
80089f6: 2b00 cmp r3, #0
80089f8: d105 bne.n 8008a06 <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
80089fa: 683a ldr r2, [r7, #0]
80089fc: 4907 ldr r1, [pc, #28] @ (8008a1c <USBD_FS_ProductStrDescriptor+0x34>)
80089fe: 4808 ldr r0, [pc, #32] @ (8008a20 <USBD_FS_ProductStrDescriptor+0x38>)
8008a00: f7ff fd8f bl 8008522 <USBD_GetString>
8008a04: e004 b.n 8008a10 <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
8008a06: 683a ldr r2, [r7, #0]
8008a08: 4904 ldr r1, [pc, #16] @ (8008a1c <USBD_FS_ProductStrDescriptor+0x34>)
8008a0a: 4805 ldr r0, [pc, #20] @ (8008a20 <USBD_FS_ProductStrDescriptor+0x38>)
8008a0c: f7ff fd89 bl 8008522 <USBD_GetString>
}
return USBD_StrDesc;
8008a10: 4b02 ldr r3, [pc, #8] @ (8008a1c <USBD_FS_ProductStrDescriptor+0x34>)
}
8008a12: 4618 mov r0, r3
8008a14: 3708 adds r7, #8
8008a16: 46bd mov sp, r7
8008a18: bd80 pop {r7, pc}
8008a1a: bf00 nop
8008a1c: 20000f10 .word 0x20000f10
8008a20: 08009a98 .word 0x08009a98
08008a24 <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8008a24: b580 push {r7, lr}
8008a26: b082 sub sp, #8
8008a28: af00 add r7, sp, #0
8008a2a: 4603 mov r3, r0
8008a2c: 6039 str r1, [r7, #0]
8008a2e: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
8008a30: 683a ldr r2, [r7, #0]
8008a32: 4904 ldr r1, [pc, #16] @ (8008a44 <USBD_FS_ManufacturerStrDescriptor+0x20>)
8008a34: 4804 ldr r0, [pc, #16] @ (8008a48 <USBD_FS_ManufacturerStrDescriptor+0x24>)
8008a36: f7ff fd74 bl 8008522 <USBD_GetString>
return USBD_StrDesc;
8008a3a: 4b02 ldr r3, [pc, #8] @ (8008a44 <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
8008a3c: 4618 mov r0, r3
8008a3e: 3708 adds r7, #8
8008a40: 46bd mov sp, r7
8008a42: bd80 pop {r7, pc}
8008a44: 20000f10 .word 0x20000f10
8008a48: 08009ab0 .word 0x08009ab0
08008a4c <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8008a4c: b580 push {r7, lr}
8008a4e: b082 sub sp, #8
8008a50: af00 add r7, sp, #0
8008a52: 4603 mov r3, r0
8008a54: 6039 str r1, [r7, #0]
8008a56: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
8008a58: 683b ldr r3, [r7, #0]
8008a5a: 221a movs r2, #26
8008a5c: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
8008a5e: f000 f843 bl 8008ae8 <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
8008a62: 4b02 ldr r3, [pc, #8] @ (8008a6c <USBD_FS_SerialStrDescriptor+0x20>)
}
8008a64: 4618 mov r0, r3
8008a66: 3708 adds r7, #8
8008a68: 46bd mov sp, r7
8008a6a: bd80 pop {r7, pc}
8008a6c: 20000160 .word 0x20000160
08008a70 <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8008a70: b580 push {r7, lr}
8008a72: b082 sub sp, #8
8008a74: af00 add r7, sp, #0
8008a76: 4603 mov r3, r0
8008a78: 6039 str r1, [r7, #0]
8008a7a: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
8008a7c: 79fb ldrb r3, [r7, #7]
8008a7e: 2b00 cmp r3, #0
8008a80: d105 bne.n 8008a8e <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
8008a82: 683a ldr r2, [r7, #0]
8008a84: 4907 ldr r1, [pc, #28] @ (8008aa4 <USBD_FS_ConfigStrDescriptor+0x34>)
8008a86: 4808 ldr r0, [pc, #32] @ (8008aa8 <USBD_FS_ConfigStrDescriptor+0x38>)
8008a88: f7ff fd4b bl 8008522 <USBD_GetString>
8008a8c: e004 b.n 8008a98 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
8008a8e: 683a ldr r2, [r7, #0]
8008a90: 4904 ldr r1, [pc, #16] @ (8008aa4 <USBD_FS_ConfigStrDescriptor+0x34>)
8008a92: 4805 ldr r0, [pc, #20] @ (8008aa8 <USBD_FS_ConfigStrDescriptor+0x38>)
8008a94: f7ff fd45 bl 8008522 <USBD_GetString>
}
return USBD_StrDesc;
8008a98: 4b02 ldr r3, [pc, #8] @ (8008aa4 <USBD_FS_ConfigStrDescriptor+0x34>)
}
8008a9a: 4618 mov r0, r3
8008a9c: 3708 adds r7, #8
8008a9e: 46bd mov sp, r7
8008aa0: bd80 pop {r7, pc}
8008aa2: bf00 nop
8008aa4: 20000f10 .word 0x20000f10
8008aa8: 08009ac4 .word 0x08009ac4
08008aac <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8008aac: b580 push {r7, lr}
8008aae: b082 sub sp, #8
8008ab0: af00 add r7, sp, #0
8008ab2: 4603 mov r3, r0
8008ab4: 6039 str r1, [r7, #0]
8008ab6: 71fb strb r3, [r7, #7]
if(speed == 0)
8008ab8: 79fb ldrb r3, [r7, #7]
8008aba: 2b00 cmp r3, #0
8008abc: d105 bne.n 8008aca <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
8008abe: 683a ldr r2, [r7, #0]
8008ac0: 4907 ldr r1, [pc, #28] @ (8008ae0 <USBD_FS_InterfaceStrDescriptor+0x34>)
8008ac2: 4808 ldr r0, [pc, #32] @ (8008ae4 <USBD_FS_InterfaceStrDescriptor+0x38>)
8008ac4: f7ff fd2d bl 8008522 <USBD_GetString>
8008ac8: e004 b.n 8008ad4 <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
8008aca: 683a ldr r2, [r7, #0]
8008acc: 4904 ldr r1, [pc, #16] @ (8008ae0 <USBD_FS_InterfaceStrDescriptor+0x34>)
8008ace: 4805 ldr r0, [pc, #20] @ (8008ae4 <USBD_FS_InterfaceStrDescriptor+0x38>)
8008ad0: f7ff fd27 bl 8008522 <USBD_GetString>
}
return USBD_StrDesc;
8008ad4: 4b02 ldr r3, [pc, #8] @ (8008ae0 <USBD_FS_InterfaceStrDescriptor+0x34>)
}
8008ad6: 4618 mov r0, r3
8008ad8: 3708 adds r7, #8
8008ada: 46bd mov sp, r7
8008adc: bd80 pop {r7, pc}
8008ade: bf00 nop
8008ae0: 20000f10 .word 0x20000f10
8008ae4: 08009ad0 .word 0x08009ad0
08008ae8 <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
8008ae8: b580 push {r7, lr}
8008aea: b084 sub sp, #16
8008aec: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
8008aee: 4b0f ldr r3, [pc, #60] @ (8008b2c <Get_SerialNum+0x44>)
8008af0: 681b ldr r3, [r3, #0]
8008af2: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
8008af4: 4b0e ldr r3, [pc, #56] @ (8008b30 <Get_SerialNum+0x48>)
8008af6: 681b ldr r3, [r3, #0]
8008af8: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
8008afa: 4b0e ldr r3, [pc, #56] @ (8008b34 <Get_SerialNum+0x4c>)
8008afc: 681b ldr r3, [r3, #0]
8008afe: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
8008b00: 68fa ldr r2, [r7, #12]
8008b02: 687b ldr r3, [r7, #4]
8008b04: 4413 add r3, r2
8008b06: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
8008b08: 68fb ldr r3, [r7, #12]
8008b0a: 2b00 cmp r3, #0
8008b0c: d009 beq.n 8008b22 <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
8008b0e: 2208 movs r2, #8
8008b10: 4909 ldr r1, [pc, #36] @ (8008b38 <Get_SerialNum+0x50>)
8008b12: 68f8 ldr r0, [r7, #12]
8008b14: f000 f814 bl 8008b40 <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
8008b18: 2204 movs r2, #4
8008b1a: 4908 ldr r1, [pc, #32] @ (8008b3c <Get_SerialNum+0x54>)
8008b1c: 68b8 ldr r0, [r7, #8]
8008b1e: f000 f80f bl 8008b40 <IntToUnicode>
}
}
8008b22: bf00 nop
8008b24: 3710 adds r7, #16
8008b26: 46bd mov sp, r7
8008b28: bd80 pop {r7, pc}
8008b2a: bf00 nop
8008b2c: 1ffff7e8 .word 0x1ffff7e8
8008b30: 1ffff7ec .word 0x1ffff7ec
8008b34: 1ffff7f0 .word 0x1ffff7f0
8008b38: 20000162 .word 0x20000162
8008b3c: 20000172 .word 0x20000172
08008b40 <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
8008b40: b480 push {r7}
8008b42: b087 sub sp, #28
8008b44: af00 add r7, sp, #0
8008b46: 60f8 str r0, [r7, #12]
8008b48: 60b9 str r1, [r7, #8]
8008b4a: 4613 mov r3, r2
8008b4c: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
8008b4e: 2300 movs r3, #0
8008b50: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
8008b52: 2300 movs r3, #0
8008b54: 75fb strb r3, [r7, #23]
8008b56: e027 b.n 8008ba8 <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
8008b58: 68fb ldr r3, [r7, #12]
8008b5a: 0f1b lsrs r3, r3, #28
8008b5c: 2b09 cmp r3, #9
8008b5e: d80b bhi.n 8008b78 <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
8008b60: 68fb ldr r3, [r7, #12]
8008b62: 0f1b lsrs r3, r3, #28
8008b64: b2da uxtb r2, r3
8008b66: 7dfb ldrb r3, [r7, #23]
8008b68: 005b lsls r3, r3, #1
8008b6a: 4619 mov r1, r3
8008b6c: 68bb ldr r3, [r7, #8]
8008b6e: 440b add r3, r1
8008b70: 3230 adds r2, #48 @ 0x30
8008b72: b2d2 uxtb r2, r2
8008b74: 701a strb r2, [r3, #0]
8008b76: e00a b.n 8008b8e <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
8008b78: 68fb ldr r3, [r7, #12]
8008b7a: 0f1b lsrs r3, r3, #28
8008b7c: b2da uxtb r2, r3
8008b7e: 7dfb ldrb r3, [r7, #23]
8008b80: 005b lsls r3, r3, #1
8008b82: 4619 mov r1, r3
8008b84: 68bb ldr r3, [r7, #8]
8008b86: 440b add r3, r1
8008b88: 3237 adds r2, #55 @ 0x37
8008b8a: b2d2 uxtb r2, r2
8008b8c: 701a strb r2, [r3, #0]
}
value = value << 4;
8008b8e: 68fb ldr r3, [r7, #12]
8008b90: 011b lsls r3, r3, #4
8008b92: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
8008b94: 7dfb ldrb r3, [r7, #23]
8008b96: 005b lsls r3, r3, #1
8008b98: 3301 adds r3, #1
8008b9a: 68ba ldr r2, [r7, #8]
8008b9c: 4413 add r3, r2
8008b9e: 2200 movs r2, #0
8008ba0: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
8008ba2: 7dfb ldrb r3, [r7, #23]
8008ba4: 3301 adds r3, #1
8008ba6: 75fb strb r3, [r7, #23]
8008ba8: 7dfa ldrb r2, [r7, #23]
8008baa: 79fb ldrb r3, [r7, #7]
8008bac: 429a cmp r2, r3
8008bae: d3d3 bcc.n 8008b58 <IntToUnicode+0x18>
}
}
8008bb0: bf00 nop
8008bb2: bf00 nop
8008bb4: 371c adds r7, #28
8008bb6: 46bd mov sp, r7
8008bb8: bc80 pop {r7}
8008bba: 4770 bx lr
08008bbc <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
8008bbc: b580 push {r7, lr}
8008bbe: b084 sub sp, #16
8008bc0: af00 add r7, sp, #0
8008bc2: 6078 str r0, [r7, #4]
if(pcdHandle->Instance==USB)
8008bc4: 687b ldr r3, [r7, #4]
8008bc6: 681b ldr r3, [r3, #0]
8008bc8: 4a0d ldr r2, [pc, #52] @ (8008c00 <HAL_PCD_MspInit+0x44>)
8008bca: 4293 cmp r3, r2
8008bcc: d113 bne.n 8008bf6 <HAL_PCD_MspInit+0x3a>
{
/* USER CODE BEGIN USB_MspInit 0 */
/* USER CODE END USB_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
8008bce: 4b0d ldr r3, [pc, #52] @ (8008c04 <HAL_PCD_MspInit+0x48>)
8008bd0: 69db ldr r3, [r3, #28]
8008bd2: 4a0c ldr r2, [pc, #48] @ (8008c04 <HAL_PCD_MspInit+0x48>)
8008bd4: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8008bd8: 61d3 str r3, [r2, #28]
8008bda: 4b0a ldr r3, [pc, #40] @ (8008c04 <HAL_PCD_MspInit+0x48>)
8008bdc: 69db ldr r3, [r3, #28]
8008bde: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8008be2: 60fb str r3, [r7, #12]
8008be4: 68fb ldr r3, [r7, #12]
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
8008be6: 2200 movs r2, #0
8008be8: 2100 movs r1, #0
8008bea: 2014 movs r0, #20
8008bec: f7f8 fc59 bl 80014a2 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
8008bf0: 2014 movs r0, #20
8008bf2: f7f8 fc72 bl 80014da <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
8008bf6: bf00 nop
8008bf8: 3710 adds r7, #16
8008bfa: 46bd mov sp, r7
8008bfc: bd80 pop {r7, pc}
8008bfe: bf00 nop
8008c00: 40005c00 .word 0x40005c00
8008c04: 40021000 .word 0x40021000
08008c08 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008c08: b580 push {r7, lr}
8008c0a: b082 sub sp, #8
8008c0c: af00 add r7, sp, #0
8008c0e: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
8008c10: 687b ldr r3, [r7, #4]
8008c12: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8008c16: 687b ldr r3, [r7, #4]
8008c18: f503 7326 add.w r3, r3, #664 @ 0x298
8008c1c: 4619 mov r1, r3
8008c1e: 4610 mov r0, r2
8008c20: f7fe fd51 bl 80076c6 <USBD_LL_SetupStage>
}
8008c24: bf00 nop
8008c26: 3708 adds r7, #8
8008c28: 46bd mov sp, r7
8008c2a: bd80 pop {r7, pc}
08008c2c <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008c2c: b580 push {r7, lr}
8008c2e: b082 sub sp, #8
8008c30: af00 add r7, sp, #0
8008c32: 6078 str r0, [r7, #4]
8008c34: 460b mov r3, r1
8008c36: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
8008c38: 687b ldr r3, [r7, #4]
8008c3a: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
8008c3e: 78fa ldrb r2, [r7, #3]
8008c40: 6879 ldr r1, [r7, #4]
8008c42: 4613 mov r3, r2
8008c44: 009b lsls r3, r3, #2
8008c46: 4413 add r3, r2
8008c48: 00db lsls r3, r3, #3
8008c4a: 440b add r3, r1
8008c4c: f503 73b2 add.w r3, r3, #356 @ 0x164
8008c50: 681a ldr r2, [r3, #0]
8008c52: 78fb ldrb r3, [r7, #3]
8008c54: 4619 mov r1, r3
8008c56: f7fe fd83 bl 8007760 <USBD_LL_DataOutStage>
}
8008c5a: bf00 nop
8008c5c: 3708 adds r7, #8
8008c5e: 46bd mov sp, r7
8008c60: bd80 pop {r7, pc}
08008c62 <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008c62: b580 push {r7, lr}
8008c64: b082 sub sp, #8
8008c66: af00 add r7, sp, #0
8008c68: 6078 str r0, [r7, #4]
8008c6a: 460b mov r3, r1
8008c6c: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
8008c6e: 687b ldr r3, [r7, #4]
8008c70: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
8008c74: 78fa ldrb r2, [r7, #3]
8008c76: 6879 ldr r1, [r7, #4]
8008c78: 4613 mov r3, r2
8008c7a: 009b lsls r3, r3, #2
8008c7c: 4413 add r3, r2
8008c7e: 00db lsls r3, r3, #3
8008c80: 440b add r3, r1
8008c82: 3324 adds r3, #36 @ 0x24
8008c84: 681a ldr r2, [r3, #0]
8008c86: 78fb ldrb r3, [r7, #3]
8008c88: 4619 mov r1, r3
8008c8a: f7fe fdda bl 8007842 <USBD_LL_DataInStage>
}
8008c8e: bf00 nop
8008c90: 3708 adds r7, #8
8008c92: 46bd mov sp, r7
8008c94: bd80 pop {r7, pc}
08008c96 <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008c96: b580 push {r7, lr}
8008c98: b082 sub sp, #8
8008c9a: af00 add r7, sp, #0
8008c9c: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
8008c9e: 687b ldr r3, [r7, #4]
8008ca0: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8008ca4: 4618 mov r0, r3
8008ca6: f7fe feea bl 8007a7e <USBD_LL_SOF>
}
8008caa: bf00 nop
8008cac: 3708 adds r7, #8
8008cae: 46bd mov sp, r7
8008cb0: bd80 pop {r7, pc}
08008cb2 <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008cb2: b580 push {r7, lr}
8008cb4: b084 sub sp, #16
8008cb6: af00 add r7, sp, #0
8008cb8: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
8008cba: 2301 movs r3, #1
8008cbc: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
8008cbe: 687b ldr r3, [r7, #4]
8008cc0: 799b ldrb r3, [r3, #6]
8008cc2: 2b02 cmp r3, #2
8008cc4: d001 beq.n 8008cca <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
8008cc6: f7f7 fe8f bl 80009e8 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
8008cca: 687b ldr r3, [r7, #4]
8008ccc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8008cd0: 7bfa ldrb r2, [r7, #15]
8008cd2: 4611 mov r1, r2
8008cd4: 4618 mov r0, r3
8008cd6: f7fe fe9a bl 8007a0e <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
8008cda: 687b ldr r3, [r7, #4]
8008cdc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8008ce0: 4618 mov r0, r3
8008ce2: f7fe fe53 bl 800798c <USBD_LL_Reset>
}
8008ce6: bf00 nop
8008ce8: 3710 adds r7, #16
8008cea: 46bd mov sp, r7
8008cec: bd80 pop {r7, pc}
...
08008cf0 <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008cf0: b580 push {r7, lr}
8008cf2: b082 sub sp, #8
8008cf4: af00 add r7, sp, #0
8008cf6: 6078 str r0, [r7, #4]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
8008cf8: 687b ldr r3, [r7, #4]
8008cfa: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8008cfe: 4618 mov r0, r3
8008d00: f7fe fe94 bl 8007a2c <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
8008d04: 687b ldr r3, [r7, #4]
8008d06: 7a9b ldrb r3, [r3, #10]
8008d08: 2b00 cmp r3, #0
8008d0a: d005 beq.n 8008d18 <HAL_PCD_SuspendCallback+0x28>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8008d0c: 4b04 ldr r3, [pc, #16] @ (8008d20 <HAL_PCD_SuspendCallback+0x30>)
8008d0e: 691b ldr r3, [r3, #16]
8008d10: 4a03 ldr r2, [pc, #12] @ (8008d20 <HAL_PCD_SuspendCallback+0x30>)
8008d12: f043 0306 orr.w r3, r3, #6
8008d16: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
8008d18: bf00 nop
8008d1a: 3708 adds r7, #8
8008d1c: 46bd mov sp, r7
8008d1e: bd80 pop {r7, pc}
8008d20: e000ed00 .word 0xe000ed00
08008d24 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8008d24: b580 push {r7, lr}
8008d26: b082 sub sp, #8
8008d28: af00 add r7, sp, #0
8008d2a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
8008d2c: 687b ldr r3, [r7, #4]
8008d2e: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
8008d32: 4618 mov r0, r3
8008d34: f7fe fe8e bl 8007a54 <USBD_LL_Resume>
}
8008d38: bf00 nop
8008d3a: 3708 adds r7, #8
8008d3c: 46bd mov sp, r7
8008d3e: bd80 pop {r7, pc}
08008d40 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
8008d40: b580 push {r7, lr}
8008d42: b082 sub sp, #8
8008d44: af00 add r7, sp, #0
8008d46: 6078 str r0, [r7, #4]
/* Init USB Ip. */
/* Link the driver to the stack. */
hpcd_USB_FS.pData = pdev;
8008d48: 4a28 ldr r2, [pc, #160] @ (8008dec <USBD_LL_Init+0xac>)
8008d4a: 687b ldr r3, [r7, #4]
8008d4c: f8c2 32d4 str.w r3, [r2, #724] @ 0x2d4
pdev->pData = &hpcd_USB_FS;
8008d50: 687b ldr r3, [r7, #4]
8008d52: 4a26 ldr r2, [pc, #152] @ (8008dec <USBD_LL_Init+0xac>)
8008d54: f8c3 22c0 str.w r2, [r3, #704] @ 0x2c0
hpcd_USB_FS.Instance = USB;
8008d58: 4b24 ldr r3, [pc, #144] @ (8008dec <USBD_LL_Init+0xac>)
8008d5a: 4a25 ldr r2, [pc, #148] @ (8008df0 <USBD_LL_Init+0xb0>)
8008d5c: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
8008d5e: 4b23 ldr r3, [pc, #140] @ (8008dec <USBD_LL_Init+0xac>)
8008d60: 2208 movs r2, #8
8008d62: 711a strb r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
8008d64: 4b21 ldr r3, [pc, #132] @ (8008dec <USBD_LL_Init+0xac>)
8008d66: 2202 movs r2, #2
8008d68: 719a strb r2, [r3, #6]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
8008d6a: 4b20 ldr r3, [pc, #128] @ (8008dec <USBD_LL_Init+0xac>)
8008d6c: 2200 movs r2, #0
8008d6e: 729a strb r2, [r3, #10]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
8008d70: 4b1e ldr r3, [pc, #120] @ (8008dec <USBD_LL_Init+0xac>)
8008d72: 2200 movs r2, #0
8008d74: 72da strb r2, [r3, #11]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
8008d76: 4b1d ldr r3, [pc, #116] @ (8008dec <USBD_LL_Init+0xac>)
8008d78: 2200 movs r2, #0
8008d7a: 731a strb r2, [r3, #12]
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
8008d7c: 481b ldr r0, [pc, #108] @ (8008dec <USBD_LL_Init+0xac>)
8008d7e: f7f8 fd82 bl 8001886 <HAL_PCD_Init>
8008d82: 4603 mov r3, r0
8008d84: 2b00 cmp r3, #0
8008d86: d001 beq.n 8008d8c <USBD_LL_Init+0x4c>
{
Error_Handler( );
8008d88: f7f7 fe2e bl 80009e8 <Error_Handler>
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
8008d8c: 687b ldr r3, [r7, #4]
8008d8e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008d92: 2318 movs r3, #24
8008d94: 2200 movs r2, #0
8008d96: 2100 movs r1, #0
8008d98: f7fa fa93 bl 80032c2 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
8008d9c: 687b ldr r3, [r7, #4]
8008d9e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008da2: 2358 movs r3, #88 @ 0x58
8008da4: 2200 movs r2, #0
8008da6: 2180 movs r1, #128 @ 0x80
8008da8: f7fa fa8b bl 80032c2 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
8008dac: 687b ldr r3, [r7, #4]
8008dae: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008db2: 23c0 movs r3, #192 @ 0xc0
8008db4: 2200 movs r2, #0
8008db6: 2181 movs r1, #129 @ 0x81
8008db8: f7fa fa83 bl 80032c2 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
8008dbc: 687b ldr r3, [r7, #4]
8008dbe: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008dc2: f44f 7388 mov.w r3, #272 @ 0x110
8008dc6: 2200 movs r2, #0
8008dc8: 2101 movs r1, #1
8008dca: f7fa fa7a bl 80032c2 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
8008dce: 687b ldr r3, [r7, #4]
8008dd0: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008dd4: f44f 7380 mov.w r3, #256 @ 0x100
8008dd8: 2200 movs r2, #0
8008dda: 2182 movs r1, #130 @ 0x82
8008ddc: f7fa fa71 bl 80032c2 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK;
8008de0: 2300 movs r3, #0
}
8008de2: 4618 mov r0, r3
8008de4: 3708 adds r7, #8
8008de6: 46bd mov sp, r7
8008de8: bd80 pop {r7, pc}
8008dea: bf00 nop
8008dec: 20001110 .word 0x20001110
8008df0: 40005c00 .word 0x40005c00
08008df4 <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
8008df4: b580 push {r7, lr}
8008df6: b084 sub sp, #16
8008df8: af00 add r7, sp, #0
8008dfa: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
8008dfc: 2300 movs r3, #0
8008dfe: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8008e00: 2300 movs r3, #0
8008e02: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_Start(pdev->pData);
8008e04: 687b ldr r3, [r7, #4]
8008e06: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8008e0a: 4618 mov r0, r3
8008e0c: f7f8 fe31 bl 8001a72 <HAL_PCD_Start>
8008e10: 4603 mov r3, r0
8008e12: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8008e14: 7bfb ldrb r3, [r7, #15]
8008e16: 4618 mov r0, r3
8008e18: f000 f94e bl 80090b8 <USBD_Get_USB_Status>
8008e1c: 4603 mov r3, r0
8008e1e: 73bb strb r3, [r7, #14]
return usb_status;
8008e20: 7bbb ldrb r3, [r7, #14]
}
8008e22: 4618 mov r0, r3
8008e24: 3710 adds r7, #16
8008e26: 46bd mov sp, r7
8008e28: bd80 pop {r7, pc}
08008e2a <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
8008e2a: b580 push {r7, lr}
8008e2c: b084 sub sp, #16
8008e2e: af00 add r7, sp, #0
8008e30: 6078 str r0, [r7, #4]
8008e32: 4608 mov r0, r1
8008e34: 4611 mov r1, r2
8008e36: 461a mov r2, r3
8008e38: 4603 mov r3, r0
8008e3a: 70fb strb r3, [r7, #3]
8008e3c: 460b mov r3, r1
8008e3e: 70bb strb r3, [r7, #2]
8008e40: 4613 mov r3, r2
8008e42: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
8008e44: 2300 movs r3, #0
8008e46: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8008e48: 2300 movs r3, #0
8008e4a: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
8008e4c: 687b ldr r3, [r7, #4]
8008e4e: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008e52: 78bb ldrb r3, [r7, #2]
8008e54: 883a ldrh r2, [r7, #0]
8008e56: 78f9 ldrb r1, [r7, #3]
8008e58: f7f8 ff85 bl 8001d66 <HAL_PCD_EP_Open>
8008e5c: 4603 mov r3, r0
8008e5e: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8008e60: 7bfb ldrb r3, [r7, #15]
8008e62: 4618 mov r0, r3
8008e64: f000 f928 bl 80090b8 <USBD_Get_USB_Status>
8008e68: 4603 mov r3, r0
8008e6a: 73bb strb r3, [r7, #14]
return usb_status;
8008e6c: 7bbb ldrb r3, [r7, #14]
}
8008e6e: 4618 mov r0, r3
8008e70: 3710 adds r7, #16
8008e72: 46bd mov sp, r7
8008e74: bd80 pop {r7, pc}
08008e76 <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8008e76: b580 push {r7, lr}
8008e78: b084 sub sp, #16
8008e7a: af00 add r7, sp, #0
8008e7c: 6078 str r0, [r7, #4]
8008e7e: 460b mov r3, r1
8008e80: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8008e82: 2300 movs r3, #0
8008e84: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8008e86: 2300 movs r3, #0
8008e88: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
8008e8a: 687b ldr r3, [r7, #4]
8008e8c: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8008e90: 78fa ldrb r2, [r7, #3]
8008e92: 4611 mov r1, r2
8008e94: 4618 mov r0, r3
8008e96: f7f8 ffc3 bl 8001e20 <HAL_PCD_EP_Close>
8008e9a: 4603 mov r3, r0
8008e9c: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8008e9e: 7bfb ldrb r3, [r7, #15]
8008ea0: 4618 mov r0, r3
8008ea2: f000 f909 bl 80090b8 <USBD_Get_USB_Status>
8008ea6: 4603 mov r3, r0
8008ea8: 73bb strb r3, [r7, #14]
return usb_status;
8008eaa: 7bbb ldrb r3, [r7, #14]
}
8008eac: 4618 mov r0, r3
8008eae: 3710 adds r7, #16
8008eb0: 46bd mov sp, r7
8008eb2: bd80 pop {r7, pc}
08008eb4 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8008eb4: b580 push {r7, lr}
8008eb6: b084 sub sp, #16
8008eb8: af00 add r7, sp, #0
8008eba: 6078 str r0, [r7, #4]
8008ebc: 460b mov r3, r1
8008ebe: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8008ec0: 2300 movs r3, #0
8008ec2: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8008ec4: 2300 movs r3, #0
8008ec6: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
8008ec8: 687b ldr r3, [r7, #4]
8008eca: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8008ece: 78fa ldrb r2, [r7, #3]
8008ed0: 4611 mov r1, r2
8008ed2: 4618 mov r0, r3
8008ed4: f7f9 f86b bl 8001fae <HAL_PCD_EP_SetStall>
8008ed8: 4603 mov r3, r0
8008eda: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8008edc: 7bfb ldrb r3, [r7, #15]
8008ede: 4618 mov r0, r3
8008ee0: f000 f8ea bl 80090b8 <USBD_Get_USB_Status>
8008ee4: 4603 mov r3, r0
8008ee6: 73bb strb r3, [r7, #14]
return usb_status;
8008ee8: 7bbb ldrb r3, [r7, #14]
}
8008eea: 4618 mov r0, r3
8008eec: 3710 adds r7, #16
8008eee: 46bd mov sp, r7
8008ef0: bd80 pop {r7, pc}
08008ef2 <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8008ef2: b580 push {r7, lr}
8008ef4: b084 sub sp, #16
8008ef6: af00 add r7, sp, #0
8008ef8: 6078 str r0, [r7, #4]
8008efa: 460b mov r3, r1
8008efc: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8008efe: 2300 movs r3, #0
8008f00: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8008f02: 2300 movs r3, #0
8008f04: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
8008f06: 687b ldr r3, [r7, #4]
8008f08: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8008f0c: 78fa ldrb r2, [r7, #3]
8008f0e: 4611 mov r1, r2
8008f10: 4618 mov r0, r3
8008f12: f7f9 f8ac bl 800206e <HAL_PCD_EP_ClrStall>
8008f16: 4603 mov r3, r0
8008f18: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8008f1a: 7bfb ldrb r3, [r7, #15]
8008f1c: 4618 mov r0, r3
8008f1e: f000 f8cb bl 80090b8 <USBD_Get_USB_Status>
8008f22: 4603 mov r3, r0
8008f24: 73bb strb r3, [r7, #14]
return usb_status;
8008f26: 7bbb ldrb r3, [r7, #14]
}
8008f28: 4618 mov r0, r3
8008f2a: 3710 adds r7, #16
8008f2c: 46bd mov sp, r7
8008f2e: bd80 pop {r7, pc}
08008f30 <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8008f30: b480 push {r7}
8008f32: b085 sub sp, #20
8008f34: af00 add r7, sp, #0
8008f36: 6078 str r0, [r7, #4]
8008f38: 460b mov r3, r1
8008f3a: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
8008f3c: 687b ldr r3, [r7, #4]
8008f3e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8008f42: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
8008f44: f997 3003 ldrsb.w r3, [r7, #3]
8008f48: 2b00 cmp r3, #0
8008f4a: da0b bge.n 8008f64 <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
8008f4c: 78fb ldrb r3, [r7, #3]
8008f4e: f003 027f and.w r2, r3, #127 @ 0x7f
8008f52: 68f9 ldr r1, [r7, #12]
8008f54: 4613 mov r3, r2
8008f56: 009b lsls r3, r3, #2
8008f58: 4413 add r3, r2
8008f5a: 00db lsls r3, r3, #3
8008f5c: 440b add r3, r1
8008f5e: 3312 adds r3, #18
8008f60: 781b ldrb r3, [r3, #0]
8008f62: e00b b.n 8008f7c <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
8008f64: 78fb ldrb r3, [r7, #3]
8008f66: f003 027f and.w r2, r3, #127 @ 0x7f
8008f6a: 68f9 ldr r1, [r7, #12]
8008f6c: 4613 mov r3, r2
8008f6e: 009b lsls r3, r3, #2
8008f70: 4413 add r3, r2
8008f72: 00db lsls r3, r3, #3
8008f74: 440b add r3, r1
8008f76: f503 73a9 add.w r3, r3, #338 @ 0x152
8008f7a: 781b ldrb r3, [r3, #0]
}
}
8008f7c: 4618 mov r0, r3
8008f7e: 3714 adds r7, #20
8008f80: 46bd mov sp, r7
8008f82: bc80 pop {r7}
8008f84: 4770 bx lr
08008f86 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
8008f86: b580 push {r7, lr}
8008f88: b084 sub sp, #16
8008f8a: af00 add r7, sp, #0
8008f8c: 6078 str r0, [r7, #4]
8008f8e: 460b mov r3, r1
8008f90: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8008f92: 2300 movs r3, #0
8008f94: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8008f96: 2300 movs r3, #0
8008f98: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
8008f9a: 687b ldr r3, [r7, #4]
8008f9c: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8008fa0: 78fa ldrb r2, [r7, #3]
8008fa2: 4611 mov r1, r2
8008fa4: 4618 mov r0, r3
8008fa6: f7f8 feba bl 8001d1e <HAL_PCD_SetAddress>
8008faa: 4603 mov r3, r0
8008fac: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8008fae: 7bfb ldrb r3, [r7, #15]
8008fb0: 4618 mov r0, r3
8008fb2: f000 f881 bl 80090b8 <USBD_Get_USB_Status>
8008fb6: 4603 mov r3, r0
8008fb8: 73bb strb r3, [r7, #14]
return usb_status;
8008fba: 7bbb ldrb r3, [r7, #14]
}
8008fbc: 4618 mov r0, r3
8008fbe: 3710 adds r7, #16
8008fc0: 46bd mov sp, r7
8008fc2: bd80 pop {r7, pc}
08008fc4 <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
8008fc4: b580 push {r7, lr}
8008fc6: b086 sub sp, #24
8008fc8: af00 add r7, sp, #0
8008fca: 60f8 str r0, [r7, #12]
8008fcc: 607a str r2, [r7, #4]
8008fce: 461a mov r2, r3
8008fd0: 460b mov r3, r1
8008fd2: 72fb strb r3, [r7, #11]
8008fd4: 4613 mov r3, r2
8008fd6: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
8008fd8: 2300 movs r3, #0
8008fda: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
8008fdc: 2300 movs r3, #0
8008fde: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
8008fe0: 68fb ldr r3, [r7, #12]
8008fe2: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
8008fe6: 893b ldrh r3, [r7, #8]
8008fe8: 7af9 ldrb r1, [r7, #11]
8008fea: 687a ldr r2, [r7, #4]
8008fec: f7f8 ffa8 bl 8001f40 <HAL_PCD_EP_Transmit>
8008ff0: 4603 mov r3, r0
8008ff2: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
8008ff4: 7dfb ldrb r3, [r7, #23]
8008ff6: 4618 mov r0, r3
8008ff8: f000 f85e bl 80090b8 <USBD_Get_USB_Status>
8008ffc: 4603 mov r3, r0
8008ffe: 75bb strb r3, [r7, #22]
return usb_status;
8009000: 7dbb ldrb r3, [r7, #22]
}
8009002: 4618 mov r0, r3
8009004: 3718 adds r7, #24
8009006: 46bd mov sp, r7
8009008: bd80 pop {r7, pc}
0800900a <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
800900a: b580 push {r7, lr}
800900c: b086 sub sp, #24
800900e: af00 add r7, sp, #0
8009010: 60f8 str r0, [r7, #12]
8009012: 607a str r2, [r7, #4]
8009014: 461a mov r2, r3
8009016: 460b mov r3, r1
8009018: 72fb strb r3, [r7, #11]
800901a: 4613 mov r3, r2
800901c: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
800901e: 2300 movs r3, #0
8009020: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
8009022: 2300 movs r3, #0
8009024: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
8009026: 68fb ldr r3, [r7, #12]
8009028: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
800902c: 893b ldrh r3, [r7, #8]
800902e: 7af9 ldrb r1, [r7, #11]
8009030: 687a ldr r2, [r7, #4]
8009032: f7f8 ff3d bl 8001eb0 <HAL_PCD_EP_Receive>
8009036: 4603 mov r3, r0
8009038: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
800903a: 7dfb ldrb r3, [r7, #23]
800903c: 4618 mov r0, r3
800903e: f000 f83b bl 80090b8 <USBD_Get_USB_Status>
8009042: 4603 mov r3, r0
8009044: 75bb strb r3, [r7, #22]
return usb_status;
8009046: 7dbb ldrb r3, [r7, #22]
}
8009048: 4618 mov r0, r3
800904a: 3718 adds r7, #24
800904c: 46bd mov sp, r7
800904e: bd80 pop {r7, pc}
08009050 <USBD_LL_GetRxDataSize>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Received Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8009050: b580 push {r7, lr}
8009052: b082 sub sp, #8
8009054: af00 add r7, sp, #0
8009056: 6078 str r0, [r7, #4]
8009058: 460b mov r3, r1
800905a: 70fb strb r3, [r7, #3]
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
800905c: 687b ldr r3, [r7, #4]
800905e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
8009062: 78fa ldrb r2, [r7, #3]
8009064: 4611 mov r1, r2
8009066: 4618 mov r0, r3
8009068: f7f8 ff53 bl 8001f12 <HAL_PCD_EP_GetRxCount>
800906c: 4603 mov r3, r0
}
800906e: 4618 mov r0, r3
8009070: 3708 adds r7, #8
8009072: 46bd mov sp, r7
8009074: bd80 pop {r7, pc}
...
08009078 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
8009078: b480 push {r7}
800907a: b083 sub sp, #12
800907c: af00 add r7, sp, #0
800907e: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
return mem;
8009080: 4b02 ldr r3, [pc, #8] @ (800908c <USBD_static_malloc+0x14>)
}
8009082: 4618 mov r0, r3
8009084: 370c adds r7, #12
8009086: 46bd mov sp, r7
8009088: bc80 pop {r7}
800908a: 4770 bx lr
800908c: 200013e8 .word 0x200013e8
08009090 <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
8009090: b480 push {r7}
8009092: b083 sub sp, #12
8009094: af00 add r7, sp, #0
8009096: 6078 str r0, [r7, #4]
}
8009098: bf00 nop
800909a: 370c adds r7, #12
800909c: 46bd mov sp, r7
800909e: bc80 pop {r7}
80090a0: 4770 bx lr
080090a2 <HAL_PCDEx_SetConnectionState>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80090a2: b480 push {r7}
80090a4: b083 sub sp, #12
80090a6: af00 add r7, sp, #0
80090a8: 6078 str r0, [r7, #4]
80090aa: 460b mov r3, r1
80090ac: 70fb strb r3, [r7, #3]
{
/* Configure High connection state. */
}
/* USER CODE END 6 */
}
80090ae: bf00 nop
80090b0: 370c adds r7, #12
80090b2: 46bd mov sp, r7
80090b4: bc80 pop {r7}
80090b6: 4770 bx lr
080090b8 <USBD_Get_USB_Status>:
* @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
80090b8: b480 push {r7}
80090ba: b085 sub sp, #20
80090bc: af00 add r7, sp, #0
80090be: 4603 mov r3, r0
80090c0: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef usb_status = USBD_OK;
80090c2: 2300 movs r3, #0
80090c4: 73fb strb r3, [r7, #15]
switch (hal_status)
80090c6: 79fb ldrb r3, [r7, #7]
80090c8: 2b03 cmp r3, #3
80090ca: d817 bhi.n 80090fc <USBD_Get_USB_Status+0x44>
80090cc: a201 add r2, pc, #4 @ (adr r2, 80090d4 <USBD_Get_USB_Status+0x1c>)
80090ce: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80090d2: bf00 nop
80090d4: 080090e5 .word 0x080090e5
80090d8: 080090eb .word 0x080090eb
80090dc: 080090f1 .word 0x080090f1
80090e0: 080090f7 .word 0x080090f7
{
case HAL_OK :
usb_status = USBD_OK;
80090e4: 2300 movs r3, #0
80090e6: 73fb strb r3, [r7, #15]
break;
80090e8: e00b b.n 8009102 <USBD_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBD_FAIL;
80090ea: 2302 movs r3, #2
80090ec: 73fb strb r3, [r7, #15]
break;
80090ee: e008 b.n 8009102 <USBD_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBD_BUSY;
80090f0: 2301 movs r3, #1
80090f2: 73fb strb r3, [r7, #15]
break;
80090f4: e005 b.n 8009102 <USBD_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
80090f6: 2302 movs r3, #2
80090f8: 73fb strb r3, [r7, #15]
break;
80090fa: e002 b.n 8009102 <USBD_Get_USB_Status+0x4a>
default :
usb_status = USBD_FAIL;
80090fc: 2302 movs r3, #2
80090fe: 73fb strb r3, [r7, #15]
break;
8009100: bf00 nop
}
return usb_status;
8009102: 7bfb ldrb r3, [r7, #15]
}
8009104: 4618 mov r0, r3
8009106: 3714 adds r7, #20
8009108: 46bd mov sp, r7
800910a: bc80 pop {r7}
800910c: 4770 bx lr
800910e: bf00 nop
08009110 <siprintf>:
8009110: b40e push {r1, r2, r3}
8009112: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
8009116: b510 push {r4, lr}
8009118: 2400 movs r4, #0
800911a: b09d sub sp, #116 @ 0x74
800911c: ab1f add r3, sp, #124 @ 0x7c
800911e: 9002 str r0, [sp, #8]
8009120: 9006 str r0, [sp, #24]
8009122: 9107 str r1, [sp, #28]
8009124: 9104 str r1, [sp, #16]
8009126: 4809 ldr r0, [pc, #36] @ (800914c <siprintf+0x3c>)
8009128: 4909 ldr r1, [pc, #36] @ (8009150 <siprintf+0x40>)
800912a: f853 2b04 ldr.w r2, [r3], #4
800912e: 9105 str r1, [sp, #20]
8009130: 6800 ldr r0, [r0, #0]
8009132: a902 add r1, sp, #8
8009134: 9301 str r3, [sp, #4]
8009136: 941b str r4, [sp, #108] @ 0x6c
8009138: f000 f992 bl 8009460 <_svfiprintf_r>
800913c: 9b02 ldr r3, [sp, #8]
800913e: 701c strb r4, [r3, #0]
8009140: b01d add sp, #116 @ 0x74
8009142: e8bd 4010 ldmia.w sp!, {r4, lr}
8009146: b003 add sp, #12
8009148: 4770 bx lr
800914a: bf00 nop
800914c: 2000017c .word 0x2000017c
8009150: ffff0208 .word 0xffff0208
08009154 <memset>:
8009154: 4603 mov r3, r0
8009156: 4402 add r2, r0
8009158: 4293 cmp r3, r2
800915a: d100 bne.n 800915e <memset+0xa>
800915c: 4770 bx lr
800915e: f803 1b01 strb.w r1, [r3], #1
8009162: e7f9 b.n 8009158 <memset+0x4>
08009164 <__errno>:
8009164: 4b01 ldr r3, [pc, #4] @ (800916c <__errno+0x8>)
8009166: 6818 ldr r0, [r3, #0]
8009168: 4770 bx lr
800916a: bf00 nop
800916c: 2000017c .word 0x2000017c
08009170 <__libc_init_array>:
8009170: b570 push {r4, r5, r6, lr}
8009172: 2600 movs r6, #0
8009174: 4d0c ldr r5, [pc, #48] @ (80091a8 <__libc_init_array+0x38>)
8009176: 4c0d ldr r4, [pc, #52] @ (80091ac <__libc_init_array+0x3c>)
8009178: 1b64 subs r4, r4, r5
800917a: 10a4 asrs r4, r4, #2
800917c: 42a6 cmp r6, r4
800917e: d109 bne.n 8009194 <__libc_init_array+0x24>
8009180: f000 fc76 bl 8009a70 <_init>
8009184: 2600 movs r6, #0
8009186: 4d0a ldr r5, [pc, #40] @ (80091b0 <__libc_init_array+0x40>)
8009188: 4c0a ldr r4, [pc, #40] @ (80091b4 <__libc_init_array+0x44>)
800918a: 1b64 subs r4, r4, r5
800918c: 10a4 asrs r4, r4, #2
800918e: 42a6 cmp r6, r4
8009190: d105 bne.n 800919e <__libc_init_array+0x2e>
8009192: bd70 pop {r4, r5, r6, pc}
8009194: f855 3b04 ldr.w r3, [r5], #4
8009198: 4798 blx r3
800919a: 3601 adds r6, #1
800919c: e7ee b.n 800917c <__libc_init_array+0xc>
800919e: f855 3b04 ldr.w r3, [r5], #4
80091a2: 4798 blx r3
80091a4: 3601 adds r6, #1
80091a6: e7f2 b.n 800918e <__libc_init_array+0x1e>
80091a8: 08009b38 .word 0x08009b38
80091ac: 08009b38 .word 0x08009b38
80091b0: 08009b38 .word 0x08009b38
80091b4: 08009b3c .word 0x08009b3c
080091b8 <__retarget_lock_acquire_recursive>:
80091b8: 4770 bx lr
080091ba <__retarget_lock_release_recursive>:
80091ba: 4770 bx lr
080091bc <_free_r>:
80091bc: b538 push {r3, r4, r5, lr}
80091be: 4605 mov r5, r0
80091c0: 2900 cmp r1, #0
80091c2: d040 beq.n 8009246 <_free_r+0x8a>
80091c4: f851 3c04 ldr.w r3, [r1, #-4]
80091c8: 1f0c subs r4, r1, #4
80091ca: 2b00 cmp r3, #0
80091cc: bfb8 it lt
80091ce: 18e4 addlt r4, r4, r3
80091d0: f000 f8de bl 8009390 <__malloc_lock>
80091d4: 4a1c ldr r2, [pc, #112] @ (8009248 <_free_r+0x8c>)
80091d6: 6813 ldr r3, [r2, #0]
80091d8: b933 cbnz r3, 80091e8 <_free_r+0x2c>
80091da: 6063 str r3, [r4, #4]
80091dc: 6014 str r4, [r2, #0]
80091de: 4628 mov r0, r5
80091e0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
80091e4: f000 b8da b.w 800939c <__malloc_unlock>
80091e8: 42a3 cmp r3, r4
80091ea: d908 bls.n 80091fe <_free_r+0x42>
80091ec: 6820 ldr r0, [r4, #0]
80091ee: 1821 adds r1, r4, r0
80091f0: 428b cmp r3, r1
80091f2: bf01 itttt eq
80091f4: 6819 ldreq r1, [r3, #0]
80091f6: 685b ldreq r3, [r3, #4]
80091f8: 1809 addeq r1, r1, r0
80091fa: 6021 streq r1, [r4, #0]
80091fc: e7ed b.n 80091da <_free_r+0x1e>
80091fe: 461a mov r2, r3
8009200: 685b ldr r3, [r3, #4]
8009202: b10b cbz r3, 8009208 <_free_r+0x4c>
8009204: 42a3 cmp r3, r4
8009206: d9fa bls.n 80091fe <_free_r+0x42>
8009208: 6811 ldr r1, [r2, #0]
800920a: 1850 adds r0, r2, r1
800920c: 42a0 cmp r0, r4
800920e: d10b bne.n 8009228 <_free_r+0x6c>
8009210: 6820 ldr r0, [r4, #0]
8009212: 4401 add r1, r0
8009214: 1850 adds r0, r2, r1
8009216: 4283 cmp r3, r0
8009218: 6011 str r1, [r2, #0]
800921a: d1e0 bne.n 80091de <_free_r+0x22>
800921c: 6818 ldr r0, [r3, #0]
800921e: 685b ldr r3, [r3, #4]
8009220: 4408 add r0, r1
8009222: 6010 str r0, [r2, #0]
8009224: 6053 str r3, [r2, #4]
8009226: e7da b.n 80091de <_free_r+0x22>
8009228: d902 bls.n 8009230 <_free_r+0x74>
800922a: 230c movs r3, #12
800922c: 602b str r3, [r5, #0]
800922e: e7d6 b.n 80091de <_free_r+0x22>
8009230: 6820 ldr r0, [r4, #0]
8009232: 1821 adds r1, r4, r0
8009234: 428b cmp r3, r1
8009236: bf01 itttt eq
8009238: 6819 ldreq r1, [r3, #0]
800923a: 685b ldreq r3, [r3, #4]
800923c: 1809 addeq r1, r1, r0
800923e: 6021 streq r1, [r4, #0]
8009240: 6063 str r3, [r4, #4]
8009242: 6054 str r4, [r2, #4]
8009244: e7cb b.n 80091de <_free_r+0x22>
8009246: bd38 pop {r3, r4, r5, pc}
8009248: 2000174c .word 0x2000174c
0800924c <sbrk_aligned>:
800924c: b570 push {r4, r5, r6, lr}
800924e: 4e0f ldr r6, [pc, #60] @ (800928c <sbrk_aligned+0x40>)
8009250: 460c mov r4, r1
8009252: 6831 ldr r1, [r6, #0]
8009254: 4605 mov r5, r0
8009256: b911 cbnz r1, 800925e <sbrk_aligned+0x12>
8009258: f000 fba8 bl 80099ac <_sbrk_r>
800925c: 6030 str r0, [r6, #0]
800925e: 4621 mov r1, r4
8009260: 4628 mov r0, r5
8009262: f000 fba3 bl 80099ac <_sbrk_r>
8009266: 1c43 adds r3, r0, #1
8009268: d103 bne.n 8009272 <sbrk_aligned+0x26>
800926a: f04f 34ff mov.w r4, #4294967295
800926e: 4620 mov r0, r4
8009270: bd70 pop {r4, r5, r6, pc}
8009272: 1cc4 adds r4, r0, #3
8009274: f024 0403 bic.w r4, r4, #3
8009278: 42a0 cmp r0, r4
800927a: d0f8 beq.n 800926e <sbrk_aligned+0x22>
800927c: 1a21 subs r1, r4, r0
800927e: 4628 mov r0, r5
8009280: f000 fb94 bl 80099ac <_sbrk_r>
8009284: 3001 adds r0, #1
8009286: d1f2 bne.n 800926e <sbrk_aligned+0x22>
8009288: e7ef b.n 800926a <sbrk_aligned+0x1e>
800928a: bf00 nop
800928c: 20001748 .word 0x20001748
08009290 <_malloc_r>:
8009290: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8009294: 1ccd adds r5, r1, #3
8009296: f025 0503 bic.w r5, r5, #3
800929a: 3508 adds r5, #8
800929c: 2d0c cmp r5, #12
800929e: bf38 it cc
80092a0: 250c movcc r5, #12
80092a2: 2d00 cmp r5, #0
80092a4: 4606 mov r6, r0
80092a6: db01 blt.n 80092ac <_malloc_r+0x1c>
80092a8: 42a9 cmp r1, r5
80092aa: d904 bls.n 80092b6 <_malloc_r+0x26>
80092ac: 230c movs r3, #12
80092ae: 6033 str r3, [r6, #0]
80092b0: 2000 movs r0, #0
80092b2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
80092b6: f8df 80d4 ldr.w r8, [pc, #212] @ 800938c <_malloc_r+0xfc>
80092ba: f000 f869 bl 8009390 <__malloc_lock>
80092be: f8d8 3000 ldr.w r3, [r8]
80092c2: 461c mov r4, r3
80092c4: bb44 cbnz r4, 8009318 <_malloc_r+0x88>
80092c6: 4629 mov r1, r5
80092c8: 4630 mov r0, r6
80092ca: f7ff ffbf bl 800924c <sbrk_aligned>
80092ce: 1c43 adds r3, r0, #1
80092d0: 4604 mov r4, r0
80092d2: d158 bne.n 8009386 <_malloc_r+0xf6>
80092d4: f8d8 4000 ldr.w r4, [r8]
80092d8: 4627 mov r7, r4
80092da: 2f00 cmp r7, #0
80092dc: d143 bne.n 8009366 <_malloc_r+0xd6>
80092de: 2c00 cmp r4, #0
80092e0: d04b beq.n 800937a <_malloc_r+0xea>
80092e2: 6823 ldr r3, [r4, #0]
80092e4: 4639 mov r1, r7
80092e6: 4630 mov r0, r6
80092e8: eb04 0903 add.w r9, r4, r3
80092ec: f000 fb5e bl 80099ac <_sbrk_r>
80092f0: 4581 cmp r9, r0
80092f2: d142 bne.n 800937a <_malloc_r+0xea>
80092f4: 6821 ldr r1, [r4, #0]
80092f6: 4630 mov r0, r6
80092f8: 1a6d subs r5, r5, r1
80092fa: 4629 mov r1, r5
80092fc: f7ff ffa6 bl 800924c <sbrk_aligned>
8009300: 3001 adds r0, #1
8009302: d03a beq.n 800937a <_malloc_r+0xea>
8009304: 6823 ldr r3, [r4, #0]
8009306: 442b add r3, r5
8009308: 6023 str r3, [r4, #0]
800930a: f8d8 3000 ldr.w r3, [r8]
800930e: 685a ldr r2, [r3, #4]
8009310: bb62 cbnz r2, 800936c <_malloc_r+0xdc>
8009312: f8c8 7000 str.w r7, [r8]
8009316: e00f b.n 8009338 <_malloc_r+0xa8>
8009318: 6822 ldr r2, [r4, #0]
800931a: 1b52 subs r2, r2, r5
800931c: d420 bmi.n 8009360 <_malloc_r+0xd0>
800931e: 2a0b cmp r2, #11
8009320: d917 bls.n 8009352 <_malloc_r+0xc2>
8009322: 1961 adds r1, r4, r5
8009324: 42a3 cmp r3, r4
8009326: 6025 str r5, [r4, #0]
8009328: bf18 it ne
800932a: 6059 strne r1, [r3, #4]
800932c: 6863 ldr r3, [r4, #4]
800932e: bf08 it eq
8009330: f8c8 1000 streq.w r1, [r8]
8009334: 5162 str r2, [r4, r5]
8009336: 604b str r3, [r1, #4]
8009338: 4630 mov r0, r6
800933a: f000 f82f bl 800939c <__malloc_unlock>
800933e: f104 000b add.w r0, r4, #11
8009342: 1d23 adds r3, r4, #4
8009344: f020 0007 bic.w r0, r0, #7
8009348: 1ac2 subs r2, r0, r3
800934a: bf1c itt ne
800934c: 1a1b subne r3, r3, r0
800934e: 50a3 strne r3, [r4, r2]
8009350: e7af b.n 80092b2 <_malloc_r+0x22>
8009352: 6862 ldr r2, [r4, #4]
8009354: 42a3 cmp r3, r4
8009356: bf0c ite eq
8009358: f8c8 2000 streq.w r2, [r8]
800935c: 605a strne r2, [r3, #4]
800935e: e7eb b.n 8009338 <_malloc_r+0xa8>
8009360: 4623 mov r3, r4
8009362: 6864 ldr r4, [r4, #4]
8009364: e7ae b.n 80092c4 <_malloc_r+0x34>
8009366: 463c mov r4, r7
8009368: 687f ldr r7, [r7, #4]
800936a: e7b6 b.n 80092da <_malloc_r+0x4a>
800936c: 461a mov r2, r3
800936e: 685b ldr r3, [r3, #4]
8009370: 42a3 cmp r3, r4
8009372: d1fb bne.n 800936c <_malloc_r+0xdc>
8009374: 2300 movs r3, #0
8009376: 6053 str r3, [r2, #4]
8009378: e7de b.n 8009338 <_malloc_r+0xa8>
800937a: 230c movs r3, #12
800937c: 4630 mov r0, r6
800937e: 6033 str r3, [r6, #0]
8009380: f000 f80c bl 800939c <__malloc_unlock>
8009384: e794 b.n 80092b0 <_malloc_r+0x20>
8009386: 6005 str r5, [r0, #0]
8009388: e7d6 b.n 8009338 <_malloc_r+0xa8>
800938a: bf00 nop
800938c: 2000174c .word 0x2000174c
08009390 <__malloc_lock>:
8009390: 4801 ldr r0, [pc, #4] @ (8009398 <__malloc_lock+0x8>)
8009392: f7ff bf11 b.w 80091b8 <__retarget_lock_acquire_recursive>
8009396: bf00 nop
8009398: 20001744 .word 0x20001744
0800939c <__malloc_unlock>:
800939c: 4801 ldr r0, [pc, #4] @ (80093a4 <__malloc_unlock+0x8>)
800939e: f7ff bf0c b.w 80091ba <__retarget_lock_release_recursive>
80093a2: bf00 nop
80093a4: 20001744 .word 0x20001744
080093a8 <__ssputs_r>:
80093a8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80093ac: 461f mov r7, r3
80093ae: 688e ldr r6, [r1, #8]
80093b0: 4682 mov sl, r0
80093b2: 42be cmp r6, r7
80093b4: 460c mov r4, r1
80093b6: 4690 mov r8, r2
80093b8: 680b ldr r3, [r1, #0]
80093ba: d82d bhi.n 8009418 <__ssputs_r+0x70>
80093bc: f9b1 200c ldrsh.w r2, [r1, #12]
80093c0: f412 6f90 tst.w r2, #1152 @ 0x480
80093c4: d026 beq.n 8009414 <__ssputs_r+0x6c>
80093c6: 6965 ldr r5, [r4, #20]
80093c8: 6909 ldr r1, [r1, #16]
80093ca: eb05 0545 add.w r5, r5, r5, lsl #1
80093ce: eba3 0901 sub.w r9, r3, r1
80093d2: eb05 75d5 add.w r5, r5, r5, lsr #31
80093d6: 1c7b adds r3, r7, #1
80093d8: 444b add r3, r9
80093da: 106d asrs r5, r5, #1
80093dc: 429d cmp r5, r3
80093de: bf38 it cc
80093e0: 461d movcc r5, r3
80093e2: 0553 lsls r3, r2, #21
80093e4: d527 bpl.n 8009436 <__ssputs_r+0x8e>
80093e6: 4629 mov r1, r5
80093e8: f7ff ff52 bl 8009290 <_malloc_r>
80093ec: 4606 mov r6, r0
80093ee: b360 cbz r0, 800944a <__ssputs_r+0xa2>
80093f0: 464a mov r2, r9
80093f2: 6921 ldr r1, [r4, #16]
80093f4: f000 faf8 bl 80099e8 <memcpy>
80093f8: 89a3 ldrh r3, [r4, #12]
80093fa: f423 6390 bic.w r3, r3, #1152 @ 0x480
80093fe: f043 0380 orr.w r3, r3, #128 @ 0x80
8009402: 81a3 strh r3, [r4, #12]
8009404: 6126 str r6, [r4, #16]
8009406: 444e add r6, r9
8009408: 6026 str r6, [r4, #0]
800940a: 463e mov r6, r7
800940c: 6165 str r5, [r4, #20]
800940e: eba5 0509 sub.w r5, r5, r9
8009412: 60a5 str r5, [r4, #8]
8009414: 42be cmp r6, r7
8009416: d900 bls.n 800941a <__ssputs_r+0x72>
8009418: 463e mov r6, r7
800941a: 4632 mov r2, r6
800941c: 4641 mov r1, r8
800941e: 6820 ldr r0, [r4, #0]
8009420: f000 faaa bl 8009978 <memmove>
8009424: 2000 movs r0, #0
8009426: 68a3 ldr r3, [r4, #8]
8009428: 1b9b subs r3, r3, r6
800942a: 60a3 str r3, [r4, #8]
800942c: 6823 ldr r3, [r4, #0]
800942e: 4433 add r3, r6
8009430: 6023 str r3, [r4, #0]
8009432: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8009436: 462a mov r2, r5
8009438: f000 fae4 bl 8009a04 <_realloc_r>
800943c: 4606 mov r6, r0
800943e: 2800 cmp r0, #0
8009440: d1e0 bne.n 8009404 <__ssputs_r+0x5c>
8009442: 4650 mov r0, sl
8009444: 6921 ldr r1, [r4, #16]
8009446: f7ff feb9 bl 80091bc <_free_r>
800944a: 230c movs r3, #12
800944c: f8ca 3000 str.w r3, [sl]
8009450: 89a3 ldrh r3, [r4, #12]
8009452: f04f 30ff mov.w r0, #4294967295
8009456: f043 0340 orr.w r3, r3, #64 @ 0x40
800945a: 81a3 strh r3, [r4, #12]
800945c: e7e9 b.n 8009432 <__ssputs_r+0x8a>
...
08009460 <_svfiprintf_r>:
8009460: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8009464: 4698 mov r8, r3
8009466: 898b ldrh r3, [r1, #12]
8009468: 4607 mov r7, r0
800946a: 061b lsls r3, r3, #24
800946c: 460d mov r5, r1
800946e: 4614 mov r4, r2
8009470: b09d sub sp, #116 @ 0x74
8009472: d510 bpl.n 8009496 <_svfiprintf_r+0x36>
8009474: 690b ldr r3, [r1, #16]
8009476: b973 cbnz r3, 8009496 <_svfiprintf_r+0x36>
8009478: 2140 movs r1, #64 @ 0x40
800947a: f7ff ff09 bl 8009290 <_malloc_r>
800947e: 6028 str r0, [r5, #0]
8009480: 6128 str r0, [r5, #16]
8009482: b930 cbnz r0, 8009492 <_svfiprintf_r+0x32>
8009484: 230c movs r3, #12
8009486: 603b str r3, [r7, #0]
8009488: f04f 30ff mov.w r0, #4294967295
800948c: b01d add sp, #116 @ 0x74
800948e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8009492: 2340 movs r3, #64 @ 0x40
8009494: 616b str r3, [r5, #20]
8009496: 2300 movs r3, #0
8009498: 9309 str r3, [sp, #36] @ 0x24
800949a: 2320 movs r3, #32
800949c: f88d 3029 strb.w r3, [sp, #41] @ 0x29
80094a0: 2330 movs r3, #48 @ 0x30
80094a2: f04f 0901 mov.w r9, #1
80094a6: f8cd 800c str.w r8, [sp, #12]
80094aa: f8df 8198 ldr.w r8, [pc, #408] @ 8009644 <_svfiprintf_r+0x1e4>
80094ae: f88d 302a strb.w r3, [sp, #42] @ 0x2a
80094b2: 4623 mov r3, r4
80094b4: 469a mov sl, r3
80094b6: f813 2b01 ldrb.w r2, [r3], #1
80094ba: b10a cbz r2, 80094c0 <_svfiprintf_r+0x60>
80094bc: 2a25 cmp r2, #37 @ 0x25
80094be: d1f9 bne.n 80094b4 <_svfiprintf_r+0x54>
80094c0: ebba 0b04 subs.w fp, sl, r4
80094c4: d00b beq.n 80094de <_svfiprintf_r+0x7e>
80094c6: 465b mov r3, fp
80094c8: 4622 mov r2, r4
80094ca: 4629 mov r1, r5
80094cc: 4638 mov r0, r7
80094ce: f7ff ff6b bl 80093a8 <__ssputs_r>
80094d2: 3001 adds r0, #1
80094d4: f000 80a7 beq.w 8009626 <_svfiprintf_r+0x1c6>
80094d8: 9a09 ldr r2, [sp, #36] @ 0x24
80094da: 445a add r2, fp
80094dc: 9209 str r2, [sp, #36] @ 0x24
80094de: f89a 3000 ldrb.w r3, [sl]
80094e2: 2b00 cmp r3, #0
80094e4: f000 809f beq.w 8009626 <_svfiprintf_r+0x1c6>
80094e8: 2300 movs r3, #0
80094ea: f04f 32ff mov.w r2, #4294967295
80094ee: e9cd 2305 strd r2, r3, [sp, #20]
80094f2: f10a 0a01 add.w sl, sl, #1
80094f6: 9304 str r3, [sp, #16]
80094f8: 9307 str r3, [sp, #28]
80094fa: f88d 3053 strb.w r3, [sp, #83] @ 0x53
80094fe: 931a str r3, [sp, #104] @ 0x68
8009500: 4654 mov r4, sl
8009502: 2205 movs r2, #5
8009504: f814 1b01 ldrb.w r1, [r4], #1
8009508: 484e ldr r0, [pc, #312] @ (8009644 <_svfiprintf_r+0x1e4>)
800950a: f000 fa5f bl 80099cc <memchr>
800950e: 9a04 ldr r2, [sp, #16]
8009510: b9d8 cbnz r0, 800954a <_svfiprintf_r+0xea>
8009512: 06d0 lsls r0, r2, #27
8009514: bf44 itt mi
8009516: 2320 movmi r3, #32
8009518: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800951c: 0711 lsls r1, r2, #28
800951e: bf44 itt mi
8009520: 232b movmi r3, #43 @ 0x2b
8009522: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8009526: f89a 3000 ldrb.w r3, [sl]
800952a: 2b2a cmp r3, #42 @ 0x2a
800952c: d015 beq.n 800955a <_svfiprintf_r+0xfa>
800952e: 4654 mov r4, sl
8009530: 2000 movs r0, #0
8009532: f04f 0c0a mov.w ip, #10
8009536: 9a07 ldr r2, [sp, #28]
8009538: 4621 mov r1, r4
800953a: f811 3b01 ldrb.w r3, [r1], #1
800953e: 3b30 subs r3, #48 @ 0x30
8009540: 2b09 cmp r3, #9
8009542: d94b bls.n 80095dc <_svfiprintf_r+0x17c>
8009544: b1b0 cbz r0, 8009574 <_svfiprintf_r+0x114>
8009546: 9207 str r2, [sp, #28]
8009548: e014 b.n 8009574 <_svfiprintf_r+0x114>
800954a: eba0 0308 sub.w r3, r0, r8
800954e: fa09 f303 lsl.w r3, r9, r3
8009552: 4313 orrs r3, r2
8009554: 46a2 mov sl, r4
8009556: 9304 str r3, [sp, #16]
8009558: e7d2 b.n 8009500 <_svfiprintf_r+0xa0>
800955a: 9b03 ldr r3, [sp, #12]
800955c: 1d19 adds r1, r3, #4
800955e: 681b ldr r3, [r3, #0]
8009560: 9103 str r1, [sp, #12]
8009562: 2b00 cmp r3, #0
8009564: bfbb ittet lt
8009566: 425b neglt r3, r3
8009568: f042 0202 orrlt.w r2, r2, #2
800956c: 9307 strge r3, [sp, #28]
800956e: 9307 strlt r3, [sp, #28]
8009570: bfb8 it lt
8009572: 9204 strlt r2, [sp, #16]
8009574: 7823 ldrb r3, [r4, #0]
8009576: 2b2e cmp r3, #46 @ 0x2e
8009578: d10a bne.n 8009590 <_svfiprintf_r+0x130>
800957a: 7863 ldrb r3, [r4, #1]
800957c: 2b2a cmp r3, #42 @ 0x2a
800957e: d132 bne.n 80095e6 <_svfiprintf_r+0x186>
8009580: 9b03 ldr r3, [sp, #12]
8009582: 3402 adds r4, #2
8009584: 1d1a adds r2, r3, #4
8009586: 681b ldr r3, [r3, #0]
8009588: 9203 str r2, [sp, #12]
800958a: ea43 73e3 orr.w r3, r3, r3, asr #31
800958e: 9305 str r3, [sp, #20]
8009590: f8df a0b4 ldr.w sl, [pc, #180] @ 8009648 <_svfiprintf_r+0x1e8>
8009594: 2203 movs r2, #3
8009596: 4650 mov r0, sl
8009598: 7821 ldrb r1, [r4, #0]
800959a: f000 fa17 bl 80099cc <memchr>
800959e: b138 cbz r0, 80095b0 <_svfiprintf_r+0x150>
80095a0: 2240 movs r2, #64 @ 0x40
80095a2: 9b04 ldr r3, [sp, #16]
80095a4: eba0 000a sub.w r0, r0, sl
80095a8: 4082 lsls r2, r0
80095aa: 4313 orrs r3, r2
80095ac: 3401 adds r4, #1
80095ae: 9304 str r3, [sp, #16]
80095b0: f814 1b01 ldrb.w r1, [r4], #1
80095b4: 2206 movs r2, #6
80095b6: 4825 ldr r0, [pc, #148] @ (800964c <_svfiprintf_r+0x1ec>)
80095b8: f88d 1028 strb.w r1, [sp, #40] @ 0x28
80095bc: f000 fa06 bl 80099cc <memchr>
80095c0: 2800 cmp r0, #0
80095c2: d036 beq.n 8009632 <_svfiprintf_r+0x1d2>
80095c4: 4b22 ldr r3, [pc, #136] @ (8009650 <_svfiprintf_r+0x1f0>)
80095c6: bb1b cbnz r3, 8009610 <_svfiprintf_r+0x1b0>
80095c8: 9b03 ldr r3, [sp, #12]
80095ca: 3307 adds r3, #7
80095cc: f023 0307 bic.w r3, r3, #7
80095d0: 3308 adds r3, #8
80095d2: 9303 str r3, [sp, #12]
80095d4: 9b09 ldr r3, [sp, #36] @ 0x24
80095d6: 4433 add r3, r6
80095d8: 9309 str r3, [sp, #36] @ 0x24
80095da: e76a b.n 80094b2 <_svfiprintf_r+0x52>
80095dc: 460c mov r4, r1
80095de: 2001 movs r0, #1
80095e0: fb0c 3202 mla r2, ip, r2, r3
80095e4: e7a8 b.n 8009538 <_svfiprintf_r+0xd8>
80095e6: 2300 movs r3, #0
80095e8: f04f 0c0a mov.w ip, #10
80095ec: 4619 mov r1, r3
80095ee: 3401 adds r4, #1
80095f0: 9305 str r3, [sp, #20]
80095f2: 4620 mov r0, r4
80095f4: f810 2b01 ldrb.w r2, [r0], #1
80095f8: 3a30 subs r2, #48 @ 0x30
80095fa: 2a09 cmp r2, #9
80095fc: d903 bls.n 8009606 <_svfiprintf_r+0x1a6>
80095fe: 2b00 cmp r3, #0
8009600: d0c6 beq.n 8009590 <_svfiprintf_r+0x130>
8009602: 9105 str r1, [sp, #20]
8009604: e7c4 b.n 8009590 <_svfiprintf_r+0x130>
8009606: 4604 mov r4, r0
8009608: 2301 movs r3, #1
800960a: fb0c 2101 mla r1, ip, r1, r2
800960e: e7f0 b.n 80095f2 <_svfiprintf_r+0x192>
8009610: ab03 add r3, sp, #12
8009612: 9300 str r3, [sp, #0]
8009614: 462a mov r2, r5
8009616: 4638 mov r0, r7
8009618: 4b0e ldr r3, [pc, #56] @ (8009654 <_svfiprintf_r+0x1f4>)
800961a: a904 add r1, sp, #16
800961c: f3af 8000 nop.w
8009620: 1c42 adds r2, r0, #1
8009622: 4606 mov r6, r0
8009624: d1d6 bne.n 80095d4 <_svfiprintf_r+0x174>
8009626: 89ab ldrh r3, [r5, #12]
8009628: 065b lsls r3, r3, #25
800962a: f53f af2d bmi.w 8009488 <_svfiprintf_r+0x28>
800962e: 9809 ldr r0, [sp, #36] @ 0x24
8009630: e72c b.n 800948c <_svfiprintf_r+0x2c>
8009632: ab03 add r3, sp, #12
8009634: 9300 str r3, [sp, #0]
8009636: 462a mov r2, r5
8009638: 4638 mov r0, r7
800963a: 4b06 ldr r3, [pc, #24] @ (8009654 <_svfiprintf_r+0x1f4>)
800963c: a904 add r1, sp, #16
800963e: f000 f87d bl 800973c <_printf_i>
8009642: e7ed b.n 8009620 <_svfiprintf_r+0x1c0>
8009644: 08009b02 .word 0x08009b02
8009648: 08009b08 .word 0x08009b08
800964c: 08009b0c .word 0x08009b0c
8009650: 00000000 .word 0x00000000
8009654: 080093a9 .word 0x080093a9
08009658 <_printf_common>:
8009658: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800965c: 4616 mov r6, r2
800965e: 4698 mov r8, r3
8009660: 688a ldr r2, [r1, #8]
8009662: 690b ldr r3, [r1, #16]
8009664: 4607 mov r7, r0
8009666: 4293 cmp r3, r2
8009668: bfb8 it lt
800966a: 4613 movlt r3, r2
800966c: 6033 str r3, [r6, #0]
800966e: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
8009672: 460c mov r4, r1
8009674: f8dd 9020 ldr.w r9, [sp, #32]
8009678: b10a cbz r2, 800967e <_printf_common+0x26>
800967a: 3301 adds r3, #1
800967c: 6033 str r3, [r6, #0]
800967e: 6823 ldr r3, [r4, #0]
8009680: 0699 lsls r1, r3, #26
8009682: bf42 ittt mi
8009684: 6833 ldrmi r3, [r6, #0]
8009686: 3302 addmi r3, #2
8009688: 6033 strmi r3, [r6, #0]
800968a: 6825 ldr r5, [r4, #0]
800968c: f015 0506 ands.w r5, r5, #6
8009690: d106 bne.n 80096a0 <_printf_common+0x48>
8009692: f104 0a19 add.w sl, r4, #25
8009696: 68e3 ldr r3, [r4, #12]
8009698: 6832 ldr r2, [r6, #0]
800969a: 1a9b subs r3, r3, r2
800969c: 42ab cmp r3, r5
800969e: dc2b bgt.n 80096f8 <_printf_common+0xa0>
80096a0: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
80096a4: 6822 ldr r2, [r4, #0]
80096a6: 3b00 subs r3, #0
80096a8: bf18 it ne
80096aa: 2301 movne r3, #1
80096ac: 0692 lsls r2, r2, #26
80096ae: d430 bmi.n 8009712 <_printf_common+0xba>
80096b0: 4641 mov r1, r8
80096b2: 4638 mov r0, r7
80096b4: f104 0243 add.w r2, r4, #67 @ 0x43
80096b8: 47c8 blx r9
80096ba: 3001 adds r0, #1
80096bc: d023 beq.n 8009706 <_printf_common+0xae>
80096be: 6823 ldr r3, [r4, #0]
80096c0: 6922 ldr r2, [r4, #16]
80096c2: f003 0306 and.w r3, r3, #6
80096c6: 2b04 cmp r3, #4
80096c8: bf14 ite ne
80096ca: 2500 movne r5, #0
80096cc: 6833 ldreq r3, [r6, #0]
80096ce: f04f 0600 mov.w r6, #0
80096d2: bf08 it eq
80096d4: 68e5 ldreq r5, [r4, #12]
80096d6: f104 041a add.w r4, r4, #26
80096da: bf08 it eq
80096dc: 1aed subeq r5, r5, r3
80096de: f854 3c12 ldr.w r3, [r4, #-18]
80096e2: bf08 it eq
80096e4: ea25 75e5 biceq.w r5, r5, r5, asr #31
80096e8: 4293 cmp r3, r2
80096ea: bfc4 itt gt
80096ec: 1a9b subgt r3, r3, r2
80096ee: 18ed addgt r5, r5, r3
80096f0: 42b5 cmp r5, r6
80096f2: d11a bne.n 800972a <_printf_common+0xd2>
80096f4: 2000 movs r0, #0
80096f6: e008 b.n 800970a <_printf_common+0xb2>
80096f8: 2301 movs r3, #1
80096fa: 4652 mov r2, sl
80096fc: 4641 mov r1, r8
80096fe: 4638 mov r0, r7
8009700: 47c8 blx r9
8009702: 3001 adds r0, #1
8009704: d103 bne.n 800970e <_printf_common+0xb6>
8009706: f04f 30ff mov.w r0, #4294967295
800970a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800970e: 3501 adds r5, #1
8009710: e7c1 b.n 8009696 <_printf_common+0x3e>
8009712: 2030 movs r0, #48 @ 0x30
8009714: 18e1 adds r1, r4, r3
8009716: f881 0043 strb.w r0, [r1, #67] @ 0x43
800971a: 1c5a adds r2, r3, #1
800971c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
8009720: 4422 add r2, r4
8009722: 3302 adds r3, #2
8009724: f882 1043 strb.w r1, [r2, #67] @ 0x43
8009728: e7c2 b.n 80096b0 <_printf_common+0x58>
800972a: 2301 movs r3, #1
800972c: 4622 mov r2, r4
800972e: 4641 mov r1, r8
8009730: 4638 mov r0, r7
8009732: 47c8 blx r9
8009734: 3001 adds r0, #1
8009736: d0e6 beq.n 8009706 <_printf_common+0xae>
8009738: 3601 adds r6, #1
800973a: e7d9 b.n 80096f0 <_printf_common+0x98>
0800973c <_printf_i>:
800973c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
8009740: 7e0f ldrb r7, [r1, #24]
8009742: 4691 mov r9, r2
8009744: 2f78 cmp r7, #120 @ 0x78
8009746: 4680 mov r8, r0
8009748: 460c mov r4, r1
800974a: 469a mov sl, r3
800974c: 9e0c ldr r6, [sp, #48] @ 0x30
800974e: f101 0243 add.w r2, r1, #67 @ 0x43
8009752: d807 bhi.n 8009764 <_printf_i+0x28>
8009754: 2f62 cmp r7, #98 @ 0x62
8009756: d80a bhi.n 800976e <_printf_i+0x32>
8009758: 2f00 cmp r7, #0
800975a: f000 80d1 beq.w 8009900 <_printf_i+0x1c4>
800975e: 2f58 cmp r7, #88 @ 0x58
8009760: f000 80b8 beq.w 80098d4 <_printf_i+0x198>
8009764: f104 0642 add.w r6, r4, #66 @ 0x42
8009768: f884 7042 strb.w r7, [r4, #66] @ 0x42
800976c: e03a b.n 80097e4 <_printf_i+0xa8>
800976e: f1a7 0363 sub.w r3, r7, #99 @ 0x63
8009772: 2b15 cmp r3, #21
8009774: d8f6 bhi.n 8009764 <_printf_i+0x28>
8009776: a101 add r1, pc, #4 @ (adr r1, 800977c <_printf_i+0x40>)
8009778: f851 f023 ldr.w pc, [r1, r3, lsl #2]
800977c: 080097d5 .word 0x080097d5
8009780: 080097e9 .word 0x080097e9
8009784: 08009765 .word 0x08009765
8009788: 08009765 .word 0x08009765
800978c: 08009765 .word 0x08009765
8009790: 08009765 .word 0x08009765
8009794: 080097e9 .word 0x080097e9
8009798: 08009765 .word 0x08009765
800979c: 08009765 .word 0x08009765
80097a0: 08009765 .word 0x08009765
80097a4: 08009765 .word 0x08009765
80097a8: 080098e7 .word 0x080098e7
80097ac: 08009813 .word 0x08009813
80097b0: 080098a1 .word 0x080098a1
80097b4: 08009765 .word 0x08009765
80097b8: 08009765 .word 0x08009765
80097bc: 08009909 .word 0x08009909
80097c0: 08009765 .word 0x08009765
80097c4: 08009813 .word 0x08009813
80097c8: 08009765 .word 0x08009765
80097cc: 08009765 .word 0x08009765
80097d0: 080098a9 .word 0x080098a9
80097d4: 6833 ldr r3, [r6, #0]
80097d6: 1d1a adds r2, r3, #4
80097d8: 681b ldr r3, [r3, #0]
80097da: 6032 str r2, [r6, #0]
80097dc: f104 0642 add.w r6, r4, #66 @ 0x42
80097e0: f884 3042 strb.w r3, [r4, #66] @ 0x42
80097e4: 2301 movs r3, #1
80097e6: e09c b.n 8009922 <_printf_i+0x1e6>
80097e8: 6833 ldr r3, [r6, #0]
80097ea: 6820 ldr r0, [r4, #0]
80097ec: 1d19 adds r1, r3, #4
80097ee: 6031 str r1, [r6, #0]
80097f0: 0606 lsls r6, r0, #24
80097f2: d501 bpl.n 80097f8 <_printf_i+0xbc>
80097f4: 681d ldr r5, [r3, #0]
80097f6: e003 b.n 8009800 <_printf_i+0xc4>
80097f8: 0645 lsls r5, r0, #25
80097fa: d5fb bpl.n 80097f4 <_printf_i+0xb8>
80097fc: f9b3 5000 ldrsh.w r5, [r3]
8009800: 2d00 cmp r5, #0
8009802: da03 bge.n 800980c <_printf_i+0xd0>
8009804: 232d movs r3, #45 @ 0x2d
8009806: 426d negs r5, r5
8009808: f884 3043 strb.w r3, [r4, #67] @ 0x43
800980c: 230a movs r3, #10
800980e: 4858 ldr r0, [pc, #352] @ (8009970 <_printf_i+0x234>)
8009810: e011 b.n 8009836 <_printf_i+0xfa>
8009812: 6821 ldr r1, [r4, #0]
8009814: 6833 ldr r3, [r6, #0]
8009816: 0608 lsls r0, r1, #24
8009818: f853 5b04 ldr.w r5, [r3], #4
800981c: d402 bmi.n 8009824 <_printf_i+0xe8>
800981e: 0649 lsls r1, r1, #25
8009820: bf48 it mi
8009822: b2ad uxthmi r5, r5
8009824: 2f6f cmp r7, #111 @ 0x6f
8009826: 6033 str r3, [r6, #0]
8009828: bf14 ite ne
800982a: 230a movne r3, #10
800982c: 2308 moveq r3, #8
800982e: 4850 ldr r0, [pc, #320] @ (8009970 <_printf_i+0x234>)
8009830: 2100 movs r1, #0
8009832: f884 1043 strb.w r1, [r4, #67] @ 0x43
8009836: 6866 ldr r6, [r4, #4]
8009838: 2e00 cmp r6, #0
800983a: 60a6 str r6, [r4, #8]
800983c: db05 blt.n 800984a <_printf_i+0x10e>
800983e: 6821 ldr r1, [r4, #0]
8009840: 432e orrs r6, r5
8009842: f021 0104 bic.w r1, r1, #4
8009846: 6021 str r1, [r4, #0]
8009848: d04b beq.n 80098e2 <_printf_i+0x1a6>
800984a: 4616 mov r6, r2
800984c: fbb5 f1f3 udiv r1, r5, r3
8009850: fb03 5711 mls r7, r3, r1, r5
8009854: 5dc7 ldrb r7, [r0, r7]
8009856: f806 7d01 strb.w r7, [r6, #-1]!
800985a: 462f mov r7, r5
800985c: 42bb cmp r3, r7
800985e: 460d mov r5, r1
8009860: d9f4 bls.n 800984c <_printf_i+0x110>
8009862: 2b08 cmp r3, #8
8009864: d10b bne.n 800987e <_printf_i+0x142>
8009866: 6823 ldr r3, [r4, #0]
8009868: 07df lsls r7, r3, #31
800986a: d508 bpl.n 800987e <_printf_i+0x142>
800986c: 6923 ldr r3, [r4, #16]
800986e: 6861 ldr r1, [r4, #4]
8009870: 4299 cmp r1, r3
8009872: bfde ittt le
8009874: 2330 movle r3, #48 @ 0x30
8009876: f806 3c01 strble.w r3, [r6, #-1]
800987a: f106 36ff addle.w r6, r6, #4294967295
800987e: 1b92 subs r2, r2, r6
8009880: 6122 str r2, [r4, #16]
8009882: 464b mov r3, r9
8009884: 4621 mov r1, r4
8009886: 4640 mov r0, r8
8009888: f8cd a000 str.w sl, [sp]
800988c: aa03 add r2, sp, #12
800988e: f7ff fee3 bl 8009658 <_printf_common>
8009892: 3001 adds r0, #1
8009894: d14a bne.n 800992c <_printf_i+0x1f0>
8009896: f04f 30ff mov.w r0, #4294967295
800989a: b004 add sp, #16
800989c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80098a0: 6823 ldr r3, [r4, #0]
80098a2: f043 0320 orr.w r3, r3, #32
80098a6: 6023 str r3, [r4, #0]
80098a8: 2778 movs r7, #120 @ 0x78
80098aa: 4832 ldr r0, [pc, #200] @ (8009974 <_printf_i+0x238>)
80098ac: f884 7045 strb.w r7, [r4, #69] @ 0x45
80098b0: 6823 ldr r3, [r4, #0]
80098b2: 6831 ldr r1, [r6, #0]
80098b4: 061f lsls r7, r3, #24
80098b6: f851 5b04 ldr.w r5, [r1], #4
80098ba: d402 bmi.n 80098c2 <_printf_i+0x186>
80098bc: 065f lsls r7, r3, #25
80098be: bf48 it mi
80098c0: b2ad uxthmi r5, r5
80098c2: 6031 str r1, [r6, #0]
80098c4: 07d9 lsls r1, r3, #31
80098c6: bf44 itt mi
80098c8: f043 0320 orrmi.w r3, r3, #32
80098cc: 6023 strmi r3, [r4, #0]
80098ce: b11d cbz r5, 80098d8 <_printf_i+0x19c>
80098d0: 2310 movs r3, #16
80098d2: e7ad b.n 8009830 <_printf_i+0xf4>
80098d4: 4826 ldr r0, [pc, #152] @ (8009970 <_printf_i+0x234>)
80098d6: e7e9 b.n 80098ac <_printf_i+0x170>
80098d8: 6823 ldr r3, [r4, #0]
80098da: f023 0320 bic.w r3, r3, #32
80098de: 6023 str r3, [r4, #0]
80098e0: e7f6 b.n 80098d0 <_printf_i+0x194>
80098e2: 4616 mov r6, r2
80098e4: e7bd b.n 8009862 <_printf_i+0x126>
80098e6: 6833 ldr r3, [r6, #0]
80098e8: 6825 ldr r5, [r4, #0]
80098ea: 1d18 adds r0, r3, #4
80098ec: 6961 ldr r1, [r4, #20]
80098ee: 6030 str r0, [r6, #0]
80098f0: 062e lsls r6, r5, #24
80098f2: 681b ldr r3, [r3, #0]
80098f4: d501 bpl.n 80098fa <_printf_i+0x1be>
80098f6: 6019 str r1, [r3, #0]
80098f8: e002 b.n 8009900 <_printf_i+0x1c4>
80098fa: 0668 lsls r0, r5, #25
80098fc: d5fb bpl.n 80098f6 <_printf_i+0x1ba>
80098fe: 8019 strh r1, [r3, #0]
8009900: 2300 movs r3, #0
8009902: 4616 mov r6, r2
8009904: 6123 str r3, [r4, #16]
8009906: e7bc b.n 8009882 <_printf_i+0x146>
8009908: 6833 ldr r3, [r6, #0]
800990a: 2100 movs r1, #0
800990c: 1d1a adds r2, r3, #4
800990e: 6032 str r2, [r6, #0]
8009910: 681e ldr r6, [r3, #0]
8009912: 6862 ldr r2, [r4, #4]
8009914: 4630 mov r0, r6
8009916: f000 f859 bl 80099cc <memchr>
800991a: b108 cbz r0, 8009920 <_printf_i+0x1e4>
800991c: 1b80 subs r0, r0, r6
800991e: 6060 str r0, [r4, #4]
8009920: 6863 ldr r3, [r4, #4]
8009922: 6123 str r3, [r4, #16]
8009924: 2300 movs r3, #0
8009926: f884 3043 strb.w r3, [r4, #67] @ 0x43
800992a: e7aa b.n 8009882 <_printf_i+0x146>
800992c: 4632 mov r2, r6
800992e: 4649 mov r1, r9
8009930: 4640 mov r0, r8
8009932: 6923 ldr r3, [r4, #16]
8009934: 47d0 blx sl
8009936: 3001 adds r0, #1
8009938: d0ad beq.n 8009896 <_printf_i+0x15a>
800993a: 6823 ldr r3, [r4, #0]
800993c: 079b lsls r3, r3, #30
800993e: d413 bmi.n 8009968 <_printf_i+0x22c>
8009940: 68e0 ldr r0, [r4, #12]
8009942: 9b03 ldr r3, [sp, #12]
8009944: 4298 cmp r0, r3
8009946: bfb8 it lt
8009948: 4618 movlt r0, r3
800994a: e7a6 b.n 800989a <_printf_i+0x15e>
800994c: 2301 movs r3, #1
800994e: 4632 mov r2, r6
8009950: 4649 mov r1, r9
8009952: 4640 mov r0, r8
8009954: 47d0 blx sl
8009956: 3001 adds r0, #1
8009958: d09d beq.n 8009896 <_printf_i+0x15a>
800995a: 3501 adds r5, #1
800995c: 68e3 ldr r3, [r4, #12]
800995e: 9903 ldr r1, [sp, #12]
8009960: 1a5b subs r3, r3, r1
8009962: 42ab cmp r3, r5
8009964: dcf2 bgt.n 800994c <_printf_i+0x210>
8009966: e7eb b.n 8009940 <_printf_i+0x204>
8009968: 2500 movs r5, #0
800996a: f104 0619 add.w r6, r4, #25
800996e: e7f5 b.n 800995c <_printf_i+0x220>
8009970: 08009b13 .word 0x08009b13
8009974: 08009b24 .word 0x08009b24
08009978 <memmove>:
8009978: 4288 cmp r0, r1
800997a: b510 push {r4, lr}
800997c: eb01 0402 add.w r4, r1, r2
8009980: d902 bls.n 8009988 <memmove+0x10>
8009982: 4284 cmp r4, r0
8009984: 4623 mov r3, r4
8009986: d807 bhi.n 8009998 <memmove+0x20>
8009988: 1e43 subs r3, r0, #1
800998a: 42a1 cmp r1, r4
800998c: d008 beq.n 80099a0 <memmove+0x28>
800998e: f811 2b01 ldrb.w r2, [r1], #1
8009992: f803 2f01 strb.w r2, [r3, #1]!
8009996: e7f8 b.n 800998a <memmove+0x12>
8009998: 4601 mov r1, r0
800999a: 4402 add r2, r0
800999c: 428a cmp r2, r1
800999e: d100 bne.n 80099a2 <memmove+0x2a>
80099a0: bd10 pop {r4, pc}
80099a2: f813 4d01 ldrb.w r4, [r3, #-1]!
80099a6: f802 4d01 strb.w r4, [r2, #-1]!
80099aa: e7f7 b.n 800999c <memmove+0x24>
080099ac <_sbrk_r>:
80099ac: b538 push {r3, r4, r5, lr}
80099ae: 2300 movs r3, #0
80099b0: 4d05 ldr r5, [pc, #20] @ (80099c8 <_sbrk_r+0x1c>)
80099b2: 4604 mov r4, r0
80099b4: 4608 mov r0, r1
80099b6: 602b str r3, [r5, #0]
80099b8: f7f7 f9c6 bl 8000d48 <_sbrk>
80099bc: 1c43 adds r3, r0, #1
80099be: d102 bne.n 80099c6 <_sbrk_r+0x1a>
80099c0: 682b ldr r3, [r5, #0]
80099c2: b103 cbz r3, 80099c6 <_sbrk_r+0x1a>
80099c4: 6023 str r3, [r4, #0]
80099c6: bd38 pop {r3, r4, r5, pc}
80099c8: 20001740 .word 0x20001740
080099cc <memchr>:
80099cc: 4603 mov r3, r0
80099ce: b510 push {r4, lr}
80099d0: b2c9 uxtb r1, r1
80099d2: 4402 add r2, r0
80099d4: 4293 cmp r3, r2
80099d6: 4618 mov r0, r3
80099d8: d101 bne.n 80099de <memchr+0x12>
80099da: 2000 movs r0, #0
80099dc: e003 b.n 80099e6 <memchr+0x1a>
80099de: 7804 ldrb r4, [r0, #0]
80099e0: 3301 adds r3, #1
80099e2: 428c cmp r4, r1
80099e4: d1f6 bne.n 80099d4 <memchr+0x8>
80099e6: bd10 pop {r4, pc}
080099e8 <memcpy>:
80099e8: 440a add r2, r1
80099ea: 4291 cmp r1, r2
80099ec: f100 33ff add.w r3, r0, #4294967295
80099f0: d100 bne.n 80099f4 <memcpy+0xc>
80099f2: 4770 bx lr
80099f4: b510 push {r4, lr}
80099f6: f811 4b01 ldrb.w r4, [r1], #1
80099fa: 4291 cmp r1, r2
80099fc: f803 4f01 strb.w r4, [r3, #1]!
8009a00: d1f9 bne.n 80099f6 <memcpy+0xe>
8009a02: bd10 pop {r4, pc}
08009a04 <_realloc_r>:
8009a04: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8009a08: 4607 mov r7, r0
8009a0a: 4614 mov r4, r2
8009a0c: 460d mov r5, r1
8009a0e: b921 cbnz r1, 8009a1a <_realloc_r+0x16>
8009a10: 4611 mov r1, r2
8009a12: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
8009a16: f7ff bc3b b.w 8009290 <_malloc_r>
8009a1a: b92a cbnz r2, 8009a28 <_realloc_r+0x24>
8009a1c: f7ff fbce bl 80091bc <_free_r>
8009a20: 4625 mov r5, r4
8009a22: 4628 mov r0, r5
8009a24: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8009a28: f000 f81a bl 8009a60 <_malloc_usable_size_r>
8009a2c: 4284 cmp r4, r0
8009a2e: 4606 mov r6, r0
8009a30: d802 bhi.n 8009a38 <_realloc_r+0x34>
8009a32: ebb4 0f50 cmp.w r4, r0, lsr #1
8009a36: d8f4 bhi.n 8009a22 <_realloc_r+0x1e>
8009a38: 4621 mov r1, r4
8009a3a: 4638 mov r0, r7
8009a3c: f7ff fc28 bl 8009290 <_malloc_r>
8009a40: 4680 mov r8, r0
8009a42: b908 cbnz r0, 8009a48 <_realloc_r+0x44>
8009a44: 4645 mov r5, r8
8009a46: e7ec b.n 8009a22 <_realloc_r+0x1e>
8009a48: 42b4 cmp r4, r6
8009a4a: 4622 mov r2, r4
8009a4c: 4629 mov r1, r5
8009a4e: bf28 it cs
8009a50: 4632 movcs r2, r6
8009a52: f7ff ffc9 bl 80099e8 <memcpy>
8009a56: 4629 mov r1, r5
8009a58: 4638 mov r0, r7
8009a5a: f7ff fbaf bl 80091bc <_free_r>
8009a5e: e7f1 b.n 8009a44 <_realloc_r+0x40>
08009a60 <_malloc_usable_size_r>:
8009a60: f851 3c04 ldr.w r3, [r1, #-4]
8009a64: 1f18 subs r0, r3, #4
8009a66: 2b00 cmp r3, #0
8009a68: bfbc itt lt
8009a6a: 580b ldrlt r3, [r1, r0]
8009a6c: 18c0 addlt r0, r0, r3
8009a6e: 4770 bx lr
08009a70 <_init>:
8009a70: b5f8 push {r3, r4, r5, r6, r7, lr}
8009a72: bf00 nop
8009a74: bcf8 pop {r3, r4, r5, r6, r7}
8009a76: bc08 pop {r3}
8009a78: 469e mov lr, r3
8009a7a: 4770 bx lr
08009a7c <_fini>:
8009a7c: b5f8 push {r3, r4, r5, r6, r7, lr}
8009a7e: bf00 nop
8009a80: bcf8 pop {r3, r4, r5, r6, r7}
8009a82: bc08 pop {r3}
8009a84: 469e mov lr, r3
8009a86: 4770 bx lr
Reference in New Issue View Git Blame Copy Permalink