24949 lines
932 KiB
Plaintext
24949 lines
932 KiB
Plaintext
|
|
AUTOM10.elf: file format elf32-littlearm
|
|
|
|
Sections:
|
|
Idx Name Size VMA LMA File off Algn
|
|
0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
1 .text 0000a1e0 0800010c 0800010c 0000110c 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
|
2 .rodata 0000015c 0800a2ec 0800a2ec 0000b2ec 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
3 .ARM.extab 00000000 0800a448 0800a448 0000c1cc 2**0
|
|
CONTENTS, READONLY
|
|
4 .ARM 00000008 0800a448 0800a448 0000b448 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
5 .preinit_array 00000000 0800a450 0800a450 0000c1cc 2**0
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
6 .init_array 00000004 0800a450 0800a450 0000b450 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
7 .fini_array 00000004 0800a454 0800a454 0000b454 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
8 .data 000001cc 20000000 0800a458 0000c000 2**2
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
9 .bss 000015ec 200001cc 0800a624 0000c1cc 2**2
|
|
ALLOC
|
|
10 ._user_heap_stack 00000600 200017b8 0800a624 0000c7b8 2**0
|
|
ALLOC
|
|
11 .ARM.attributes 00000029 00000000 00000000 0000c1cc 2**0
|
|
CONTENTS, READONLY
|
|
12 .debug_info 000163a1 00000000 00000000 0000c1f5 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
13 .debug_abbrev 00003a44 00000000 00000000 00022596 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
14 .debug_aranges 00001398 00000000 00000000 00025fe0 2**3
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
15 .debug_rnglists 00000f03 00000000 00000000 00027378 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
16 .debug_macro 0001bc58 00000000 00000000 0002827b 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
17 .debug_line 00019141 00000000 00000000 00043ed3 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
18 .debug_str 00094b2f 00000000 00000000 0005d014 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
19 .comment 00000043 00000000 00000000 000f1b43 2**0
|
|
CONTENTS, READONLY
|
|
20 .debug_frame 000055d8 00000000 00000000 000f1b88 2**2
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
21 .debug_line_str 00000052 00000000 00000000 000f7160 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
|
|
Disassembly of section .text:
|
|
|
|
0800010c <__do_global_dtors_aux>:
|
|
800010c: b510 push {r4, lr}
|
|
800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
|
|
8000110: 7823 ldrb r3, [r4, #0]
|
|
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
|
|
8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
|
|
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
|
|
8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
|
|
800011a: f3af 8000 nop.w
|
|
800011e: 2301 movs r3, #1
|
|
8000120: 7023 strb r3, [r4, #0]
|
|
8000122: bd10 pop {r4, pc}
|
|
8000124: 200001cc .word 0x200001cc
|
|
8000128: 00000000 .word 0x00000000
|
|
800012c: 0800a2d4 .word 0x0800a2d4
|
|
|
|
08000130 <frame_dummy>:
|
|
8000130: b508 push {r3, lr}
|
|
8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
|
|
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
|
|
8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
|
|
8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
|
|
800013a: f3af 8000 nop.w
|
|
800013e: bd08 pop {r3, pc}
|
|
8000140: 00000000 .word 0x00000000
|
|
8000144: 200001d0 .word 0x200001d0
|
|
8000148: 0800a2d4 .word 0x0800a2d4
|
|
|
|
0800014c <strlen>:
|
|
800014c: 4603 mov r3, r0
|
|
800014e: f813 2b01 ldrb.w r2, [r3], #1
|
|
8000152: 2a00 cmp r2, #0
|
|
8000154: d1fb bne.n 800014e <strlen+0x2>
|
|
8000156: 1a18 subs r0, r3, r0
|
|
8000158: 3801 subs r0, #1
|
|
800015a: 4770 bx lr
|
|
|
|
0800015c <manageCDC>:
|
|
extern TIM_HandleTypeDef htim1;
|
|
extern TIM_HandleTypeDef htim2;
|
|
extern TIM_HandleTypeDef htim3;
|
|
extern TIM_HandleTypeDef htim4;
|
|
|
|
void manageCDC(void){
|
|
800015c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
|
|
8000160: b0a7 sub sp, #156 @ 0x9c
|
|
8000162: af06 add r7, sp, #24
|
|
static uint8_t rxidx=0;
|
|
unsigned char s[100];
|
|
uint8_t mot,dir,dm,m,c,d,u;
|
|
uint16_t val;
|
|
|
|
if (CDC_Available()) {
|
|
8000164: f008 ff52 bl 800900c <CDC_Available>
|
|
8000168: 4603 mov r3, r0
|
|
800016a: 2b00 cmp r3, #0
|
|
800016c: f000 821a beq.w 80005a4 <manageCDC+0x448>
|
|
int rx = CDC_ReadByte();
|
|
8000170: f008 ff60 bl 8009034 <CDC_ReadByte>
|
|
8000174: 67b8 str r0, [r7, #120] @ 0x78
|
|
if (rx < 0) return;
|
|
8000176: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8000178: 2b00 cmp r3, #0
|
|
800017a: f2c0 8212 blt.w 80005a2 <manageCDC+0x446>
|
|
//uint8_t out = (uint8_t)c;
|
|
//if (out >= 'a' && out <= 'z') out -= 32; // to upper
|
|
rxbuf[rxidx]=rx;
|
|
800017e: 4b7f ldr r3, [pc, #508] @ (800037c <manageCDC+0x220>)
|
|
8000180: 781b ldrb r3, [r3, #0]
|
|
8000182: 461a mov r2, r3
|
|
8000184: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8000186: b2d9 uxtb r1, r3
|
|
8000188: 4b7d ldr r3, [pc, #500] @ (8000380 <manageCDC+0x224>)
|
|
800018a: 5499 strb r1, [r3, r2]
|
|
while (CDC_Transmit_FS(&rxbuf[rxidx], 1) == USBD_BUSY);//echo
|
|
800018c: bf00 nop
|
|
800018e: 4b7b ldr r3, [pc, #492] @ (800037c <manageCDC+0x220>)
|
|
8000190: 781b ldrb r3, [r3, #0]
|
|
8000192: 461a mov r2, r3
|
|
8000194: 4b7a ldr r3, [pc, #488] @ (8000380 <manageCDC+0x224>)
|
|
8000196: 4413 add r3, r2
|
|
8000198: 2101 movs r1, #1
|
|
800019a: 4618 mov r0, r3
|
|
800019c: f009 f80c bl 80091b8 <CDC_Transmit_FS>
|
|
80001a0: 4603 mov r3, r0
|
|
80001a2: 2b01 cmp r3, #1
|
|
80001a4: d0f3 beq.n 800018e <manageCDC+0x32>
|
|
if((rx==0x0d)||(rx==0x0a)){
|
|
80001a6: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80001a8: 2b0d cmp r3, #13
|
|
80001aa: d003 beq.n 80001b4 <manageCDC+0x58>
|
|
80001ac: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80001ae: 2b0a cmp r3, #10
|
|
80001b0: f040 81f0 bne.w 8000594 <manageCDC+0x438>
|
|
if(rxidx){
|
|
80001b4: 4b71 ldr r3, [pc, #452] @ (800037c <manageCDC+0x220>)
|
|
80001b6: 781b ldrb r3, [r3, #0]
|
|
80001b8: 2b00 cmp r3, #0
|
|
80001ba: f000 81e7 beq.w 800058c <manageCDC+0x430>
|
|
switch(rxbuf[0]){
|
|
80001be: 4b70 ldr r3, [pc, #448] @ (8000380 <manageCDC+0x224>)
|
|
80001c0: 781b ldrb r3, [r3, #0]
|
|
80001c2: 2b69 cmp r3, #105 @ 0x69
|
|
80001c4: d003 beq.n 80001ce <manageCDC+0x72>
|
|
80001c6: 2b6d cmp r3, #109 @ 0x6d
|
|
80001c8: f000 809d beq.w 8000306 <manageCDC+0x1aa>
|
|
80001cc: e1cd b.n 800056a <manageCDC+0x40e>
|
|
case 'i':
|
|
sprintf((char*)s,"\ninfo");
|
|
80001ce: f107 030c add.w r3, r7, #12
|
|
80001d2: 496c ldr r1, [pc, #432] @ (8000384 <manageCDC+0x228>)
|
|
80001d4: 4618 mov r0, r3
|
|
80001d6: f009 fbcd bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, 5) == USBD_BUSY);
|
|
80001da: bf00 nop
|
|
80001dc: f107 030c add.w r3, r7, #12
|
|
80001e0: 2105 movs r1, #5
|
|
80001e2: 4618 mov r0, r3
|
|
80001e4: f008 ffe8 bl 80091b8 <CDC_Transmit_FS>
|
|
80001e8: 4603 mov r3, r0
|
|
80001ea: 2b01 cmp r3, #1
|
|
80001ec: d0f6 beq.n 80001dc <manageCDC+0x80>
|
|
sprintf((char*)s,"\npwm %d%d%d%d%d%d%d%d",IsPwmRunning(timMot1,FWMot1),IsPwmRunning(timMot1,BWMot1),IsPwmRunning(timMot2,FWMot2),IsPwmRunning(timMot2,BWMot2),IsPwmRunning(timMot3,FWMot3),IsPwmRunning(timMot3,BWMot3),IsPwmRunning(timMot4,FWMot4),IsPwmRunning(timMot4,BWMot4));
|
|
80001ee: 2100 movs r1, #0
|
|
80001f0: 4865 ldr r0, [pc, #404] @ (8000388 <manageCDC+0x22c>)
|
|
80001f2: f000 fd1b bl 8000c2c <IsPwmRunning>
|
|
80001f6: 4603 mov r3, r0
|
|
80001f8: 4698 mov r8, r3
|
|
80001fa: 2104 movs r1, #4
|
|
80001fc: 4862 ldr r0, [pc, #392] @ (8000388 <manageCDC+0x22c>)
|
|
80001fe: f000 fd15 bl 8000c2c <IsPwmRunning>
|
|
8000202: 4603 mov r3, r0
|
|
8000204: 4699 mov r9, r3
|
|
8000206: 2108 movs r1, #8
|
|
8000208: 485f ldr r0, [pc, #380] @ (8000388 <manageCDC+0x22c>)
|
|
800020a: f000 fd0f bl 8000c2c <IsPwmRunning>
|
|
800020e: 4603 mov r3, r0
|
|
8000210: 461c mov r4, r3
|
|
8000212: 210c movs r1, #12
|
|
8000214: 485c ldr r0, [pc, #368] @ (8000388 <manageCDC+0x22c>)
|
|
8000216: f000 fd09 bl 8000c2c <IsPwmRunning>
|
|
800021a: 4603 mov r3, r0
|
|
800021c: 461d mov r5, r3
|
|
800021e: 2100 movs r1, #0
|
|
8000220: 485a ldr r0, [pc, #360] @ (800038c <manageCDC+0x230>)
|
|
8000222: f000 fd03 bl 8000c2c <IsPwmRunning>
|
|
8000226: 4603 mov r3, r0
|
|
8000228: 461e mov r6, r3
|
|
800022a: 2104 movs r1, #4
|
|
800022c: 4857 ldr r0, [pc, #348] @ (800038c <manageCDC+0x230>)
|
|
800022e: f000 fcfd bl 8000c2c <IsPwmRunning>
|
|
8000232: 4603 mov r3, r0
|
|
8000234: 607b str r3, [r7, #4]
|
|
8000236: 2108 movs r1, #8
|
|
8000238: 4854 ldr r0, [pc, #336] @ (800038c <manageCDC+0x230>)
|
|
800023a: f000 fcf7 bl 8000c2c <IsPwmRunning>
|
|
800023e: 4603 mov r3, r0
|
|
8000240: 603b str r3, [r7, #0]
|
|
8000242: 210c movs r1, #12
|
|
8000244: 4851 ldr r0, [pc, #324] @ (800038c <manageCDC+0x230>)
|
|
8000246: f000 fcf1 bl 8000c2c <IsPwmRunning>
|
|
800024a: 4603 mov r3, r0
|
|
800024c: f107 000c add.w r0, r7, #12
|
|
8000250: 9305 str r3, [sp, #20]
|
|
8000252: 683a ldr r2, [r7, #0]
|
|
8000254: 9204 str r2, [sp, #16]
|
|
8000256: 687b ldr r3, [r7, #4]
|
|
8000258: 9303 str r3, [sp, #12]
|
|
800025a: 9602 str r6, [sp, #8]
|
|
800025c: 9501 str r5, [sp, #4]
|
|
800025e: 9400 str r4, [sp, #0]
|
|
8000260: 464b mov r3, r9
|
|
8000262: 4642 mov r2, r8
|
|
8000264: 494a ldr r1, [pc, #296] @ (8000390 <manageCDC+0x234>)
|
|
8000266: f009 fb85 bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
|
|
800026a: bf00 nop
|
|
800026c: f107 030c add.w r3, r7, #12
|
|
8000270: 4618 mov r0, r3
|
|
8000272: f7ff ff6b bl 800014c <strlen>
|
|
8000276: 4603 mov r3, r0
|
|
8000278: b29a uxth r2, r3
|
|
800027a: f107 030c add.w r3, r7, #12
|
|
800027e: 4611 mov r1, r2
|
|
8000280: 4618 mov r0, r3
|
|
8000282: f008 ff99 bl 80091b8 <CDC_Transmit_FS>
|
|
8000286: 4603 mov r3, r0
|
|
8000288: 2b01 cmp r3, #1
|
|
800028a: d0ef beq.n 800026c <manageCDC+0x110>
|
|
__HAL_TIM_GET_COMPARE(&htim3, TIM_CHANNEL_1);
|
|
800028c: 4b41 ldr r3, [pc, #260] @ (8000394 <manageCDC+0x238>)
|
|
800028e: 681b ldr r3, [r3, #0]
|
|
8000290: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
sprintf((char*)s,"\n0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx",(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,FWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot1,BWMot1),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,FWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot2,BWMot2),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,FWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot3,BWMot3),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,FWMot4),(uint32_t)__HAL_TIM_GET_COMPARE(timMot4,BWMot4));
|
|
8000292: 4b3d ldr r3, [pc, #244] @ (8000388 <manageCDC+0x22c>)
|
|
8000294: 681b ldr r3, [r3, #0]
|
|
8000296: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8000298: 607b str r3, [r7, #4]
|
|
800029a: 4b3b ldr r3, [pc, #236] @ (8000388 <manageCDC+0x22c>)
|
|
800029c: 681b ldr r3, [r3, #0]
|
|
800029e: 6b99 ldr r1, [r3, #56] @ 0x38
|
|
80002a0: 6039 str r1, [r7, #0]
|
|
80002a2: 4b39 ldr r3, [pc, #228] @ (8000388 <manageCDC+0x22c>)
|
|
80002a4: 681b ldr r3, [r3, #0]
|
|
80002a6: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80002a8: 4a37 ldr r2, [pc, #220] @ (8000388 <manageCDC+0x22c>)
|
|
80002aa: 6812 ldr r2, [r2, #0]
|
|
80002ac: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
80002ae: 4937 ldr r1, [pc, #220] @ (800038c <manageCDC+0x230>)
|
|
80002b0: 6809 ldr r1, [r1, #0]
|
|
80002b2: 6b49 ldr r1, [r1, #52] @ 0x34
|
|
80002b4: 4835 ldr r0, [pc, #212] @ (800038c <manageCDC+0x230>)
|
|
80002b6: 6800 ldr r0, [r0, #0]
|
|
80002b8: 6b80 ldr r0, [r0, #56] @ 0x38
|
|
80002ba: 4c34 ldr r4, [pc, #208] @ (800038c <manageCDC+0x230>)
|
|
80002bc: 6824 ldr r4, [r4, #0]
|
|
80002be: 6be4 ldr r4, [r4, #60] @ 0x3c
|
|
80002c0: 4d32 ldr r5, [pc, #200] @ (800038c <manageCDC+0x230>)
|
|
80002c2: 682d ldr r5, [r5, #0]
|
|
80002c4: 6c2d ldr r5, [r5, #64] @ 0x40
|
|
80002c6: f107 060c add.w r6, r7, #12
|
|
80002ca: 9505 str r5, [sp, #20]
|
|
80002cc: 9404 str r4, [sp, #16]
|
|
80002ce: 9003 str r0, [sp, #12]
|
|
80002d0: 9102 str r1, [sp, #8]
|
|
80002d2: 9201 str r2, [sp, #4]
|
|
80002d4: 9300 str r3, [sp, #0]
|
|
80002d6: 683b ldr r3, [r7, #0]
|
|
80002d8: 687a ldr r2, [r7, #4]
|
|
80002da: 492f ldr r1, [pc, #188] @ (8000398 <manageCDC+0x23c>)
|
|
80002dc: 4630 mov r0, r6
|
|
80002de: f009 fb49 bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, strlen((char*)s)) == USBD_BUSY);
|
|
80002e2: bf00 nop
|
|
80002e4: f107 030c add.w r3, r7, #12
|
|
80002e8: 4618 mov r0, r3
|
|
80002ea: f7ff ff2f bl 800014c <strlen>
|
|
80002ee: 4603 mov r3, r0
|
|
80002f0: b29a uxth r2, r3
|
|
80002f2: f107 030c add.w r3, r7, #12
|
|
80002f6: 4611 mov r1, r2
|
|
80002f8: 4618 mov r0, r3
|
|
80002fa: f008 ff5d bl 80091b8 <CDC_Transmit_FS>
|
|
80002fe: 4603 mov r3, r0
|
|
8000300: 2b01 cmp r3, #1
|
|
8000302: d0ef beq.n 80002e4 <manageCDC+0x188>
|
|
break;
|
|
8000304: e142 b.n 800058c <manageCDC+0x430>
|
|
case 'm':
|
|
if(rxidx==8){
|
|
8000306: 4b1d ldr r3, [pc, #116] @ (800037c <manageCDC+0x220>)
|
|
8000308: 781b ldrb r3, [r3, #0]
|
|
800030a: 2b08 cmp r3, #8
|
|
800030c: f040 811b bne.w 8000546 <manageCDC+0x3ea>
|
|
if((rxbuf[1]>='1')&&(rxbuf[1]<='4')){
|
|
8000310: 4b1b ldr r3, [pc, #108] @ (8000380 <manageCDC+0x224>)
|
|
8000312: 785b ldrb r3, [r3, #1]
|
|
8000314: 2b30 cmp r3, #48 @ 0x30
|
|
8000316: f240 8105 bls.w 8000524 <manageCDC+0x3c8>
|
|
800031a: 4b19 ldr r3, [pc, #100] @ (8000380 <manageCDC+0x224>)
|
|
800031c: 785b ldrb r3, [r3, #1]
|
|
800031e: 2b34 cmp r3, #52 @ 0x34
|
|
8000320: f200 8100 bhi.w 8000524 <manageCDC+0x3c8>
|
|
mot=rxbuf[1]-='0';
|
|
8000324: 4b16 ldr r3, [pc, #88] @ (8000380 <manageCDC+0x224>)
|
|
8000326: 785b ldrb r3, [r3, #1]
|
|
8000328: 3b30 subs r3, #48 @ 0x30
|
|
800032a: b2da uxtb r2, r3
|
|
800032c: 4b14 ldr r3, [pc, #80] @ (8000380 <manageCDC+0x224>)
|
|
800032e: 705a strb r2, [r3, #1]
|
|
8000330: 4b13 ldr r3, [pc, #76] @ (8000380 <manageCDC+0x224>)
|
|
8000332: 785b ldrb r3, [r3, #1]
|
|
8000334: f887 3077 strb.w r3, [r7, #119] @ 0x77
|
|
if(rxbuf[2]=='f'){
|
|
8000338: 4b11 ldr r3, [pc, #68] @ (8000380 <manageCDC+0x224>)
|
|
800033a: 789b ldrb r3, [r3, #2]
|
|
800033c: 2b66 cmp r3, #102 @ 0x66
|
|
800033e: d103 bne.n 8000348 <manageCDC+0x1ec>
|
|
dir=FW;
|
|
8000340: 2300 movs r3, #0
|
|
8000342: f887 307f strb.w r3, [r7, #127] @ 0x7f
|
|
8000346: e02b b.n 80003a0 <manageCDC+0x244>
|
|
}else if(rxbuf[2]=='b'){
|
|
8000348: 4b0d ldr r3, [pc, #52] @ (8000380 <manageCDC+0x224>)
|
|
800034a: 789b ldrb r3, [r3, #2]
|
|
800034c: 2b62 cmp r3, #98 @ 0x62
|
|
800034e: d103 bne.n 8000358 <manageCDC+0x1fc>
|
|
dir=BW;
|
|
8000350: 2301 movs r3, #1
|
|
8000352: f887 307f strb.w r3, [r7, #127] @ 0x7f
|
|
8000356: e023 b.n 80003a0 <manageCDC+0x244>
|
|
}else{
|
|
sprintf((char*)s,"\n?mnsvvvvv s=f|b");//m nmotore senso valore
|
|
8000358: f107 030c add.w r3, r7, #12
|
|
800035c: 490f ldr r1, [pc, #60] @ (800039c <manageCDC+0x240>)
|
|
800035e: 4618 mov r0, r3
|
|
8000360: f009 fb08 bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, 16) == USBD_BUSY);
|
|
8000364: bf00 nop
|
|
8000366: f107 030c add.w r3, r7, #12
|
|
800036a: 2110 movs r1, #16
|
|
800036c: 4618 mov r0, r3
|
|
800036e: f008 ff23 bl 80091b8 <CDC_Transmit_FS>
|
|
8000372: 4603 mov r3, r0
|
|
8000374: 2b01 cmp r3, #1
|
|
8000376: d0f6 beq.n 8000366 <manageCDC+0x20a>
|
|
break;
|
|
8000378: e108 b.n 800058c <manageCDC+0x430>
|
|
800037a: bf00 nop
|
|
800037c: 200001e8 .word 0x200001e8
|
|
8000380: 200001ec .word 0x200001ec
|
|
8000384: 0800a2ec .word 0x0800a2ec
|
|
8000388: 20000280 .word 0x20000280
|
|
800038c: 200002c8 .word 0x200002c8
|
|
8000390: 0800a2f4 .word 0x0800a2f4
|
|
8000394: 20000358 .word 0x20000358
|
|
8000398: 0800a30c .word 0x0800a30c
|
|
800039c: 0800a340 .word 0x0800a340
|
|
}
|
|
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
|
|
80003a0: 4b82 ldr r3, [pc, #520] @ (80005ac <manageCDC+0x450>)
|
|
80003a2: 78db ldrb r3, [r3, #3]
|
|
80003a4: 2b2f cmp r3, #47 @ 0x2f
|
|
80003a6: f240 80ac bls.w 8000502 <manageCDC+0x3a6>
|
|
80003aa: 4b80 ldr r3, [pc, #512] @ (80005ac <manageCDC+0x450>)
|
|
80003ac: 78db ldrb r3, [r3, #3]
|
|
80003ae: 2b39 cmp r3, #57 @ 0x39
|
|
80003b0: f200 80a7 bhi.w 8000502 <manageCDC+0x3a6>
|
|
80003b4: 4b7d ldr r3, [pc, #500] @ (80005ac <manageCDC+0x450>)
|
|
80003b6: 791b ldrb r3, [r3, #4]
|
|
80003b8: 2b2f cmp r3, #47 @ 0x2f
|
|
80003ba: f240 80a2 bls.w 8000502 <manageCDC+0x3a6>
|
|
80003be: 4b7b ldr r3, [pc, #492] @ (80005ac <manageCDC+0x450>)
|
|
80003c0: 791b ldrb r3, [r3, #4]
|
|
80003c2: 2b39 cmp r3, #57 @ 0x39
|
|
80003c4: f200 809d bhi.w 8000502 <manageCDC+0x3a6>
|
|
80003c8: 4b78 ldr r3, [pc, #480] @ (80005ac <manageCDC+0x450>)
|
|
80003ca: 795b ldrb r3, [r3, #5]
|
|
80003cc: 2b2f cmp r3, #47 @ 0x2f
|
|
80003ce: f240 8098 bls.w 8000502 <manageCDC+0x3a6>
|
|
80003d2: 4b76 ldr r3, [pc, #472] @ (80005ac <manageCDC+0x450>)
|
|
80003d4: 795b ldrb r3, [r3, #5]
|
|
80003d6: 2b39 cmp r3, #57 @ 0x39
|
|
80003d8: f200 8093 bhi.w 8000502 <manageCDC+0x3a6>
|
|
80003dc: 4b73 ldr r3, [pc, #460] @ (80005ac <manageCDC+0x450>)
|
|
80003de: 799b ldrb r3, [r3, #6]
|
|
80003e0: 2b2f cmp r3, #47 @ 0x2f
|
|
80003e2: f240 808e bls.w 8000502 <manageCDC+0x3a6>
|
|
80003e6: 4b71 ldr r3, [pc, #452] @ (80005ac <manageCDC+0x450>)
|
|
80003e8: 799b ldrb r3, [r3, #6]
|
|
80003ea: 2b39 cmp r3, #57 @ 0x39
|
|
80003ec: f200 8089 bhi.w 8000502 <manageCDC+0x3a6>
|
|
80003f0: 4b6e ldr r3, [pc, #440] @ (80005ac <manageCDC+0x450>)
|
|
80003f2: 79db ldrb r3, [r3, #7]
|
|
80003f4: 2b2f cmp r3, #47 @ 0x2f
|
|
80003f6: f240 8084 bls.w 8000502 <manageCDC+0x3a6>
|
|
80003fa: 4b6c ldr r3, [pc, #432] @ (80005ac <manageCDC+0x450>)
|
|
80003fc: 79db ldrb r3, [r3, #7]
|
|
80003fe: 2b39 cmp r3, #57 @ 0x39
|
|
8000400: d87f bhi.n 8000502 <manageCDC+0x3a6>
|
|
dm=rxbuf[3]-='0';
|
|
8000402: 4b6a ldr r3, [pc, #424] @ (80005ac <manageCDC+0x450>)
|
|
8000404: 78db ldrb r3, [r3, #3]
|
|
8000406: 3b30 subs r3, #48 @ 0x30
|
|
8000408: b2da uxtb r2, r3
|
|
800040a: 4b68 ldr r3, [pc, #416] @ (80005ac <manageCDC+0x450>)
|
|
800040c: 70da strb r2, [r3, #3]
|
|
800040e: 4b67 ldr r3, [pc, #412] @ (80005ac <manageCDC+0x450>)
|
|
8000410: 78db ldrb r3, [r3, #3]
|
|
8000412: f887 3076 strb.w r3, [r7, #118] @ 0x76
|
|
m=rxbuf[4]-='0';
|
|
8000416: 4b65 ldr r3, [pc, #404] @ (80005ac <manageCDC+0x450>)
|
|
8000418: 791b ldrb r3, [r3, #4]
|
|
800041a: 3b30 subs r3, #48 @ 0x30
|
|
800041c: b2da uxtb r2, r3
|
|
800041e: 4b63 ldr r3, [pc, #396] @ (80005ac <manageCDC+0x450>)
|
|
8000420: 711a strb r2, [r3, #4]
|
|
8000422: 4b62 ldr r3, [pc, #392] @ (80005ac <manageCDC+0x450>)
|
|
8000424: 791b ldrb r3, [r3, #4]
|
|
8000426: f887 3075 strb.w r3, [r7, #117] @ 0x75
|
|
c=rxbuf[5]-='0';
|
|
800042a: 4b60 ldr r3, [pc, #384] @ (80005ac <manageCDC+0x450>)
|
|
800042c: 795b ldrb r3, [r3, #5]
|
|
800042e: 3b30 subs r3, #48 @ 0x30
|
|
8000430: b2da uxtb r2, r3
|
|
8000432: 4b5e ldr r3, [pc, #376] @ (80005ac <manageCDC+0x450>)
|
|
8000434: 715a strb r2, [r3, #5]
|
|
8000436: 4b5d ldr r3, [pc, #372] @ (80005ac <manageCDC+0x450>)
|
|
8000438: 795b ldrb r3, [r3, #5]
|
|
800043a: f887 3074 strb.w r3, [r7, #116] @ 0x74
|
|
d=rxbuf[6]-='0';
|
|
800043e: 4b5b ldr r3, [pc, #364] @ (80005ac <manageCDC+0x450>)
|
|
8000440: 799b ldrb r3, [r3, #6]
|
|
8000442: 3b30 subs r3, #48 @ 0x30
|
|
8000444: b2da uxtb r2, r3
|
|
8000446: 4b59 ldr r3, [pc, #356] @ (80005ac <manageCDC+0x450>)
|
|
8000448: 719a strb r2, [r3, #6]
|
|
800044a: 4b58 ldr r3, [pc, #352] @ (80005ac <manageCDC+0x450>)
|
|
800044c: 799b ldrb r3, [r3, #6]
|
|
800044e: f887 3073 strb.w r3, [r7, #115] @ 0x73
|
|
u=rxbuf[7]-='0';
|
|
8000452: 4b56 ldr r3, [pc, #344] @ (80005ac <manageCDC+0x450>)
|
|
8000454: 79db ldrb r3, [r3, #7]
|
|
8000456: 3b30 subs r3, #48 @ 0x30
|
|
8000458: b2da uxtb r2, r3
|
|
800045a: 4b54 ldr r3, [pc, #336] @ (80005ac <manageCDC+0x450>)
|
|
800045c: 71da strb r2, [r3, #7]
|
|
800045e: 4b53 ldr r3, [pc, #332] @ (80005ac <manageCDC+0x450>)
|
|
8000460: 79db ldrb r3, [r3, #7]
|
|
8000462: f887 3072 strb.w r3, [r7, #114] @ 0x72
|
|
val=dm;
|
|
8000466: f897 3076 ldrb.w r3, [r7, #118] @ 0x76
|
|
800046a: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val*=10;
|
|
800046e: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
8000472: 461a mov r2, r3
|
|
8000474: 0092 lsls r2, r2, #2
|
|
8000476: 4413 add r3, r2
|
|
8000478: 005b lsls r3, r3, #1
|
|
800047a: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val+=m;
|
|
800047e: f897 3075 ldrb.w r3, [r7, #117] @ 0x75
|
|
8000482: b29a uxth r2, r3
|
|
8000484: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
8000488: 4413 add r3, r2
|
|
800048a: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val*=10;
|
|
800048e: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
8000492: 461a mov r2, r3
|
|
8000494: 0092 lsls r2, r2, #2
|
|
8000496: 4413 add r3, r2
|
|
8000498: 005b lsls r3, r3, #1
|
|
800049a: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val+=c;
|
|
800049e: f897 3074 ldrb.w r3, [r7, #116] @ 0x74
|
|
80004a2: b29a uxth r2, r3
|
|
80004a4: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
80004a8: 4413 add r3, r2
|
|
80004aa: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val*=10;
|
|
80004ae: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
80004b2: 461a mov r2, r3
|
|
80004b4: 0092 lsls r2, r2, #2
|
|
80004b6: 4413 add r3, r2
|
|
80004b8: 005b lsls r3, r3, #1
|
|
80004ba: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val+=d;
|
|
80004be: f897 3073 ldrb.w r3, [r7, #115] @ 0x73
|
|
80004c2: b29a uxth r2, r3
|
|
80004c4: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
80004c8: 4413 add r3, r2
|
|
80004ca: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val*=10;
|
|
80004ce: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
80004d2: 461a mov r2, r3
|
|
80004d4: 0092 lsls r2, r2, #2
|
|
80004d6: 4413 add r3, r2
|
|
80004d8: 005b lsls r3, r3, #1
|
|
80004da: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
val+=u;
|
|
80004de: f897 3072 ldrb.w r3, [r7, #114] @ 0x72
|
|
80004e2: b29a uxth r2, r3
|
|
80004e4: f8b7 3070 ldrh.w r3, [r7, #112] @ 0x70
|
|
80004e8: 4413 add r3, r2
|
|
80004ea: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
SetMot(mot,dir,val);
|
|
80004ee: f8b7 2070 ldrh.w r2, [r7, #112] @ 0x70
|
|
80004f2: f897 107f ldrb.w r1, [r7, #127] @ 0x7f
|
|
80004f6: f897 3077 ldrb.w r3, [r7, #119] @ 0x77
|
|
80004fa: 4618 mov r0, r3
|
|
80004fc: f000 fc0c bl 8000d18 <SetMot>
|
|
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
|
|
8000500: e032 b.n 8000568 <manageCDC+0x40c>
|
|
}else{
|
|
sprintf((char*)s,"\n?mnsvvvvv 00000>=vvvvv<=99999");//m nmotore senso valore
|
|
8000502: f107 030c add.w r3, r7, #12
|
|
8000506: 492a ldr r1, [pc, #168] @ (80005b0 <manageCDC+0x454>)
|
|
8000508: 4618 mov r0, r3
|
|
800050a: f009 fa33 bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
|
|
800050e: bf00 nop
|
|
8000510: f107 030c add.w r3, r7, #12
|
|
8000514: 2113 movs r1, #19
|
|
8000516: 4618 mov r0, r3
|
|
8000518: f008 fe4e bl 80091b8 <CDC_Transmit_FS>
|
|
800051c: 4603 mov r3, r0
|
|
800051e: 2b01 cmp r3, #1
|
|
8000520: d0f6 beq.n 8000510 <manageCDC+0x3b4>
|
|
if(((rxbuf[3]>='0')&&(rxbuf[3]<='9'))&&((rxbuf[4]>='0')&&(rxbuf[4]<='9'))&&((rxbuf[5]>='0')&&(rxbuf[5]<='9'))&&((rxbuf[6]>='0')&&(rxbuf[6]<='9'))&&((rxbuf[7]>='0')&&(rxbuf[7]<='9'))){
|
|
8000522: e021 b.n 8000568 <manageCDC+0x40c>
|
|
}
|
|
|
|
}else{
|
|
sprintf((char*)s,"\n?mnsvvvvv 1>=m<=4");//m nmotore senso valore
|
|
8000524: f107 030c add.w r3, r7, #12
|
|
8000528: 4922 ldr r1, [pc, #136] @ (80005b4 <manageCDC+0x458>)
|
|
800052a: 4618 mov r0, r3
|
|
800052c: f009 fa22 bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, 19) == USBD_BUSY);
|
|
8000530: bf00 nop
|
|
8000532: f107 030c add.w r3, r7, #12
|
|
8000536: 2113 movs r1, #19
|
|
8000538: 4618 mov r0, r3
|
|
800053a: f008 fe3d bl 80091b8 <CDC_Transmit_FS>
|
|
800053e: 4603 mov r3, r0
|
|
8000540: 2b01 cmp r3, #1
|
|
8000542: d0f6 beq.n 8000532 <manageCDC+0x3d6>
|
|
}
|
|
}else{
|
|
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
|
|
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
|
|
}
|
|
break;
|
|
8000544: e022 b.n 800058c <manageCDC+0x430>
|
|
sprintf((char*)s,"\n?mnsvvvvv");//m nmotore senso valore
|
|
8000546: f107 030c add.w r3, r7, #12
|
|
800054a: 491b ldr r1, [pc, #108] @ (80005b8 <manageCDC+0x45c>)
|
|
800054c: 4618 mov r0, r3
|
|
800054e: f009 fa11 bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, 10) == USBD_BUSY);
|
|
8000552: bf00 nop
|
|
8000554: f107 030c add.w r3, r7, #12
|
|
8000558: 210a movs r1, #10
|
|
800055a: 4618 mov r0, r3
|
|
800055c: f008 fe2c bl 80091b8 <CDC_Transmit_FS>
|
|
8000560: 4603 mov r3, r0
|
|
8000562: 2b01 cmp r3, #1
|
|
8000564: d0f6 beq.n 8000554 <manageCDC+0x3f8>
|
|
break;
|
|
8000566: e011 b.n 800058c <manageCDC+0x430>
|
|
8000568: e010 b.n 800058c <manageCDC+0x430>
|
|
default:
|
|
sprintf((char*)s,"\n?");
|
|
800056a: f107 030c add.w r3, r7, #12
|
|
800056e: 4913 ldr r1, [pc, #76] @ (80005bc <manageCDC+0x460>)
|
|
8000570: 4618 mov r0, r3
|
|
8000572: f009 f9ff bl 8009974 <siprintf>
|
|
while (CDC_Transmit_FS(s, 2) == USBD_BUSY);
|
|
8000576: bf00 nop
|
|
8000578: f107 030c add.w r3, r7, #12
|
|
800057c: 2102 movs r1, #2
|
|
800057e: 4618 mov r0, r3
|
|
8000580: f008 fe1a bl 80091b8 <CDC_Transmit_FS>
|
|
8000584: 4603 mov r3, r0
|
|
8000586: 2b01 cmp r3, #1
|
|
8000588: d0f6 beq.n 8000578 <manageCDC+0x41c>
|
|
break;
|
|
800058a: bf00 nop
|
|
}
|
|
}
|
|
rxidx=0;
|
|
800058c: 4b0c ldr r3, [pc, #48] @ (80005c0 <manageCDC+0x464>)
|
|
800058e: 2200 movs r2, #0
|
|
8000590: 701a strb r2, [r3, #0]
|
|
8000592: e007 b.n 80005a4 <manageCDC+0x448>
|
|
}else rxidx++;
|
|
8000594: 4b0a ldr r3, [pc, #40] @ (80005c0 <manageCDC+0x464>)
|
|
8000596: 781b ldrb r3, [r3, #0]
|
|
8000598: 3301 adds r3, #1
|
|
800059a: b2da uxtb r2, r3
|
|
800059c: 4b08 ldr r3, [pc, #32] @ (80005c0 <manageCDC+0x464>)
|
|
800059e: 701a strb r2, [r3, #0]
|
|
80005a0: e000 b.n 80005a4 <manageCDC+0x448>
|
|
if (rx < 0) return;
|
|
80005a2: bf00 nop
|
|
// tiny spin or yield
|
|
}
|
|
|
|
}
|
|
80005a4: 3784 adds r7, #132 @ 0x84
|
|
80005a6: 46bd mov sp, r7
|
|
80005a8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
80005ac: 200001ec .word 0x200001ec
|
|
80005b0: 0800a354 .word 0x0800a354
|
|
80005b4: 0800a374 .word 0x0800a374
|
|
80005b8: 0800a388 .word 0x0800a388
|
|
80005bc: 0800a394 .word 0x0800a394
|
|
80005c0: 200001e8 .word 0x200001e8
|
|
|
|
080005c4 <HAL_SYSTICK_Callback>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Private user code ---------------------------------------------------------*/
|
|
/* USER CODE BEGIN 0 */
|
|
void HAL_SYSTICK_Callback(void){
|
|
80005c4: b580 push {r7, lr}
|
|
80005c6: af00 add r7, sp, #0
|
|
static unsigned char c10ms = 0;
|
|
|
|
static uint8_t c100ms = 0;
|
|
static uint8_t c1s = 0;
|
|
if (++c10ms >= 10) { // 10 ms
|
|
80005c8: 4b16 ldr r3, [pc, #88] @ (8000624 <HAL_SYSTICK_Callback+0x60>)
|
|
80005ca: 781b ldrb r3, [r3, #0]
|
|
80005cc: 3301 adds r3, #1
|
|
80005ce: b2da uxtb r2, r3
|
|
80005d0: 4b14 ldr r3, [pc, #80] @ (8000624 <HAL_SYSTICK_Callback+0x60>)
|
|
80005d2: 701a strb r2, [r3, #0]
|
|
80005d4: 4b13 ldr r3, [pc, #76] @ (8000624 <HAL_SYSTICK_Callback+0x60>)
|
|
80005d6: 781b ldrb r3, [r3, #0]
|
|
80005d8: 2b09 cmp r3, #9
|
|
80005da: d921 bls.n 8000620 <HAL_SYSTICK_Callback+0x5c>
|
|
c10ms = 0;
|
|
80005dc: 4b11 ldr r3, [pc, #68] @ (8000624 <HAL_SYSTICK_Callback+0x60>)
|
|
80005de: 2200 movs r2, #0
|
|
80005e0: 701a strb r2, [r3, #0]
|
|
if (++c100ms >= 10) { // 10 ms
|
|
80005e2: 4b11 ldr r3, [pc, #68] @ (8000628 <HAL_SYSTICK_Callback+0x64>)
|
|
80005e4: 781b ldrb r3, [r3, #0]
|
|
80005e6: 3301 adds r3, #1
|
|
80005e8: b2da uxtb r2, r3
|
|
80005ea: 4b0f ldr r3, [pc, #60] @ (8000628 <HAL_SYSTICK_Callback+0x64>)
|
|
80005ec: 701a strb r2, [r3, #0]
|
|
80005ee: 4b0e ldr r3, [pc, #56] @ (8000628 <HAL_SYSTICK_Callback+0x64>)
|
|
80005f0: 781b ldrb r3, [r3, #0]
|
|
80005f2: 2b09 cmp r3, #9
|
|
80005f4: d914 bls.n 8000620 <HAL_SYSTICK_Callback+0x5c>
|
|
c100ms = 0; //flag_10ms = 1; // set a flag; do real work in main loop
|
|
80005f6: 4b0c ldr r3, [pc, #48] @ (8000628 <HAL_SYSTICK_Callback+0x64>)
|
|
80005f8: 2200 movs r2, #0
|
|
80005fa: 701a strb r2, [r3, #0]
|
|
if (++c1s >= 10) { // 10 ms
|
|
80005fc: 4b0b ldr r3, [pc, #44] @ (800062c <HAL_SYSTICK_Callback+0x68>)
|
|
80005fe: 781b ldrb r3, [r3, #0]
|
|
8000600: 3301 adds r3, #1
|
|
8000602: b2da uxtb r2, r3
|
|
8000604: 4b09 ldr r3, [pc, #36] @ (800062c <HAL_SYSTICK_Callback+0x68>)
|
|
8000606: 701a strb r2, [r3, #0]
|
|
8000608: 4b08 ldr r3, [pc, #32] @ (800062c <HAL_SYSTICK_Callback+0x68>)
|
|
800060a: 781b ldrb r3, [r3, #0]
|
|
800060c: 2b09 cmp r3, #9
|
|
800060e: d907 bls.n 8000620 <HAL_SYSTICK_Callback+0x5c>
|
|
c1s = 0;
|
|
8000610: 4b06 ldr r3, [pc, #24] @ (800062c <HAL_SYSTICK_Callback+0x68>)
|
|
8000612: 2200 movs r2, #0
|
|
8000614: 701a strb r2, [r3, #0]
|
|
HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
|
|
8000616: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
800061a: 4805 ldr r0, [pc, #20] @ (8000630 <HAL_SYSTICK_Callback+0x6c>)
|
|
800061c: f001 fc02 bl 8001e24 <HAL_GPIO_TogglePin>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8000620: bf00 nop
|
|
8000622: bd80 pop {r7, pc}
|
|
8000624: 200003a0 .word 0x200003a0
|
|
8000628: 200003a1 .word 0x200003a1
|
|
800062c: 200003a2 .word 0x200003a2
|
|
8000630: 40011000 .word 0x40011000
|
|
|
|
08000634 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000634: b580 push {r7, lr}
|
|
8000636: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000638: f000 fed0 bl 80013dc <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800063c: f000 f83a bl 80006b4 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000640: f000 fa44 bl 8000acc <MX_GPIO_Init>
|
|
MX_USB_DEVICE_Init();
|
|
8000644: f008 fc7c bl 8008f40 <MX_USB_DEVICE_Init>
|
|
MX_TIM2_Init();
|
|
8000648: f000 f8d0 bl 80007ec <MX_TIM2_Init>
|
|
MX_TIM4_Init();
|
|
800064c: f000 f972 bl 8000934 <MX_TIM4_Init>
|
|
MX_ADC1_Init();
|
|
8000650: f000 f88e bl 8000770 <MX_ADC1_Init>
|
|
MX_USART1_UART_Init();
|
|
8000654: f000 fa10 bl 8000a78 <MX_USART1_UART_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
StopMot(timMot1,FWMot1);
|
|
8000658: 2100 movs r1, #0
|
|
800065a: 4813 ldr r0, [pc, #76] @ (80006a8 <main+0x74>)
|
|
800065c: f000 fafb bl 8000c56 <StopMot>
|
|
StopMot(timMot1,BWMot1);
|
|
8000660: 2104 movs r1, #4
|
|
8000662: 4811 ldr r0, [pc, #68] @ (80006a8 <main+0x74>)
|
|
8000664: f000 faf7 bl 8000c56 <StopMot>
|
|
StopMot(timMot2,FWMot2);
|
|
8000668: 2108 movs r1, #8
|
|
800066a: 480f ldr r0, [pc, #60] @ (80006a8 <main+0x74>)
|
|
800066c: f000 faf3 bl 8000c56 <StopMot>
|
|
StopMot(timMot2,BWMot2);
|
|
8000670: 210c movs r1, #12
|
|
8000672: 480d ldr r0, [pc, #52] @ (80006a8 <main+0x74>)
|
|
8000674: f000 faef bl 8000c56 <StopMot>
|
|
StopMot(timMot3,FWMot3);
|
|
8000678: 2100 movs r1, #0
|
|
800067a: 480c ldr r0, [pc, #48] @ (80006ac <main+0x78>)
|
|
800067c: f000 faeb bl 8000c56 <StopMot>
|
|
StopMot(timMot3,BWMot3);
|
|
8000680: 2104 movs r1, #4
|
|
8000682: 480a ldr r0, [pc, #40] @ (80006ac <main+0x78>)
|
|
8000684: f000 fae7 bl 8000c56 <StopMot>
|
|
StopMot(timMot4,FWMot4);
|
|
8000688: 2108 movs r1, #8
|
|
800068a: 4808 ldr r0, [pc, #32] @ (80006ac <main+0x78>)
|
|
800068c: f000 fae3 bl 8000c56 <StopMot>
|
|
StopMot(timMot4,BWMot4);
|
|
8000690: 210c movs r1, #12
|
|
8000692: 4806 ldr r0, [pc, #24] @ (80006ac <main+0x78>)
|
|
8000694: f000 fadf bl 8000c56 <StopMot>
|
|
CDC_Transmit_FS((uint8_t*)"Start\r\n", 7);
|
|
8000698: 2107 movs r1, #7
|
|
800069a: 4805 ldr r0, [pc, #20] @ (80006b0 <main+0x7c>)
|
|
800069c: f008 fd8c bl 80091b8 <CDC_Transmit_FS>
|
|
/* USER CODE END 2 */
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1){
|
|
manageCDC();
|
|
80006a0: f7ff fd5c bl 800015c <manageCDC>
|
|
80006a4: e7fc b.n 80006a0 <main+0x6c>
|
|
80006a6: bf00 nop
|
|
80006a8: 20000280 .word 0x20000280
|
|
80006ac: 200002c8 .word 0x200002c8
|
|
80006b0: 0800a398 .word 0x0800a398
|
|
|
|
080006b4 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
80006b4: b580 push {r7, lr}
|
|
80006b6: b094 sub sp, #80 @ 0x50
|
|
80006b8: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
80006ba: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
80006be: 2228 movs r2, #40 @ 0x28
|
|
80006c0: 2100 movs r1, #0
|
|
80006c2: 4618 mov r0, r3
|
|
80006c4: f009 f978 bl 80099b8 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80006c8: f107 0314 add.w r3, r7, #20
|
|
80006cc: 2200 movs r2, #0
|
|
80006ce: 601a str r2, [r3, #0]
|
|
80006d0: 605a str r2, [r3, #4]
|
|
80006d2: 609a str r2, [r3, #8]
|
|
80006d4: 60da str r2, [r3, #12]
|
|
80006d6: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
80006d8: 1d3b adds r3, r7, #4
|
|
80006da: 2200 movs r2, #0
|
|
80006dc: 601a str r2, [r3, #0]
|
|
80006de: 605a str r2, [r3, #4]
|
|
80006e0: 609a str r2, [r3, #8]
|
|
80006e2: 60da str r2, [r3, #12]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
80006e4: 2301 movs r3, #1
|
|
80006e6: 62bb str r3, [r7, #40] @ 0x28
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
80006e8: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80006ec: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
|
|
80006ee: 2300 movs r3, #0
|
|
80006f0: 633b str r3, [r7, #48] @ 0x30
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80006f2: 2301 movs r3, #1
|
|
80006f4: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80006f6: 2302 movs r3, #2
|
|
80006f8: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
80006fa: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80006fe: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
|
|
8000700: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000
|
|
8000704: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000706: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
800070a: 4618 mov r0, r3
|
|
800070c: f003 f904 bl 8003918 <HAL_RCC_OscConfig>
|
|
8000710: 4603 mov r3, r0
|
|
8000712: 2b00 cmp r3, #0
|
|
8000714: d001 beq.n 800071a <SystemClock_Config+0x66>
|
|
{
|
|
Error_Handler();
|
|
8000716: f000 fa83 bl 8000c20 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
800071a: 230f movs r3, #15
|
|
800071c: 617b str r3, [r7, #20]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
800071e: 2302 movs r3, #2
|
|
8000720: 61bb str r3, [r7, #24]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8000722: 2300 movs r3, #0
|
|
8000724: 61fb str r3, [r7, #28]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
8000726: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
800072a: 623b str r3, [r7, #32]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
800072c: 2300 movs r3, #0
|
|
800072e: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
|
8000730: f107 0314 add.w r3, r7, #20
|
|
8000734: 2102 movs r1, #2
|
|
8000736: 4618 mov r0, r3
|
|
8000738: f003 fb70 bl 8003e1c <HAL_RCC_ClockConfig>
|
|
800073c: 4603 mov r3, r0
|
|
800073e: 2b00 cmp r3, #0
|
|
8000740: d001 beq.n 8000746 <SystemClock_Config+0x92>
|
|
{
|
|
Error_Handler();
|
|
8000742: f000 fa6d bl 8000c20 <Error_Handler>
|
|
}
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
|
|
8000746: 2312 movs r3, #18
|
|
8000748: 607b str r3, [r7, #4]
|
|
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
|
|
800074a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800074e: 60fb str r3, [r7, #12]
|
|
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
|
|
8000750: 2300 movs r3, #0
|
|
8000752: 613b str r3, [r7, #16]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8000754: 1d3b adds r3, r7, #4
|
|
8000756: 4618 mov r0, r3
|
|
8000758: f003 fcee bl 8004138 <HAL_RCCEx_PeriphCLKConfig>
|
|
800075c: 4603 mov r3, r0
|
|
800075e: 2b00 cmp r3, #0
|
|
8000760: d001 beq.n 8000766 <SystemClock_Config+0xb2>
|
|
{
|
|
Error_Handler();
|
|
8000762: f000 fa5d bl 8000c20 <Error_Handler>
|
|
}
|
|
}
|
|
8000766: bf00 nop
|
|
8000768: 3750 adds r7, #80 @ 0x50
|
|
800076a: 46bd mov sp, r7
|
|
800076c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000770 <MX_ADC1_Init>:
|
|
* @brief ADC1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC1_Init(void)
|
|
{
|
|
8000770: b580 push {r7, lr}
|
|
8000772: b084 sub sp, #16
|
|
8000774: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC1_Init 0 */
|
|
|
|
/* USER CODE END ADC1_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8000776: 1d3b adds r3, r7, #4
|
|
8000778: 2200 movs r2, #0
|
|
800077a: 601a str r2, [r3, #0]
|
|
800077c: 605a str r2, [r3, #4]
|
|
800077e: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE END ADC1_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc1.Instance = ADC1;
|
|
8000780: 4b18 ldr r3, [pc, #96] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
8000782: 4a19 ldr r2, [pc, #100] @ (80007e8 <MX_ADC1_Init+0x78>)
|
|
8000784: 601a str r2, [r3, #0]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
8000786: 4b17 ldr r3, [pc, #92] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
8000788: 2200 movs r2, #0
|
|
800078a: 609a str r2, [r3, #8]
|
|
hadc1.Init.ContinuousConvMode = DISABLE;
|
|
800078c: 4b15 ldr r3, [pc, #84] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
800078e: 2200 movs r2, #0
|
|
8000790: 731a strb r2, [r3, #12]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
8000792: 4b14 ldr r3, [pc, #80] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
8000794: 2200 movs r2, #0
|
|
8000796: 751a strb r2, [r3, #20]
|
|
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
8000798: 4b12 ldr r3, [pc, #72] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
800079a: f44f 2260 mov.w r2, #917504 @ 0xe0000
|
|
800079e: 61da str r2, [r3, #28]
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
80007a0: 4b10 ldr r3, [pc, #64] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
80007a2: 2200 movs r2, #0
|
|
80007a4: 605a str r2, [r3, #4]
|
|
hadc1.Init.NbrOfConversion = 1;
|
|
80007a6: 4b0f ldr r3, [pc, #60] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
80007a8: 2201 movs r2, #1
|
|
80007aa: 611a str r2, [r3, #16]
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
80007ac: 480d ldr r0, [pc, #52] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
80007ae: f000 fe77 bl 80014a0 <HAL_ADC_Init>
|
|
80007b2: 4603 mov r3, r0
|
|
80007b4: 2b00 cmp r3, #0
|
|
80007b6: d001 beq.n 80007bc <MX_ADC1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
80007b8: f000 fa32 bl 8000c20 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_4;
|
|
80007bc: 2304 movs r3, #4
|
|
80007be: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
80007c0: 2301 movs r3, #1
|
|
80007c2: 60bb str r3, [r7, #8]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
|
80007c4: 2300 movs r3, #0
|
|
80007c6: 60fb str r3, [r7, #12]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80007c8: 1d3b adds r3, r7, #4
|
|
80007ca: 4619 mov r1, r3
|
|
80007cc: 4805 ldr r0, [pc, #20] @ (80007e4 <MX_ADC1_Init+0x74>)
|
|
80007ce: f000 ff3f bl 8001650 <HAL_ADC_ConfigChannel>
|
|
80007d2: 4603 mov r3, r0
|
|
80007d4: 2b00 cmp r3, #0
|
|
80007d6: d001 beq.n 80007dc <MX_ADC1_Init+0x6c>
|
|
{
|
|
Error_Handler();
|
|
80007d8: f000 fa22 bl 8000c20 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC1_Init 2 */
|
|
|
|
/* USER CODE END ADC1_Init 2 */
|
|
|
|
}
|
|
80007dc: bf00 nop
|
|
80007de: 3710 adds r7, #16
|
|
80007e0: 46bd mov sp, r7
|
|
80007e2: bd80 pop {r7, pc}
|
|
80007e4: 20000250 .word 0x20000250
|
|
80007e8: 40012400 .word 0x40012400
|
|
|
|
080007ec <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
80007ec: b580 push {r7, lr}
|
|
80007ee: b08e sub sp, #56 @ 0x38
|
|
80007f0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
80007f2: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
80007f6: 2200 movs r2, #0
|
|
80007f8: 601a str r2, [r3, #0]
|
|
80007fa: 605a str r2, [r3, #4]
|
|
80007fc: 609a str r2, [r3, #8]
|
|
80007fe: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000800: f107 0320 add.w r3, r7, #32
|
|
8000804: 2200 movs r2, #0
|
|
8000806: 601a str r2, [r3, #0]
|
|
8000808: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
800080a: 1d3b adds r3, r7, #4
|
|
800080c: 2200 movs r2, #0
|
|
800080e: 601a str r2, [r3, #0]
|
|
8000810: 605a str r2, [r3, #4]
|
|
8000812: 609a str r2, [r3, #8]
|
|
8000814: 60da str r2, [r3, #12]
|
|
8000816: 611a str r2, [r3, #16]
|
|
8000818: 615a str r2, [r3, #20]
|
|
800081a: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
800081c: 4b44 ldr r3, [pc, #272] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
800081e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8000822: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
8000824: 4b42 ldr r3, [pc, #264] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000826: 2200 movs r2, #0
|
|
8000828: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800082a: 4b41 ldr r3, [pc, #260] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
800082c: 2200 movs r2, #0
|
|
800082e: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 17999;
|
|
8000830: 4b3f ldr r3, [pc, #252] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000832: f244 624f movw r2, #17999 @ 0x464f
|
|
8000836: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000838: 4b3d ldr r3, [pc, #244] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
800083a: 2200 movs r2, #0
|
|
800083c: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
800083e: 4b3c ldr r3, [pc, #240] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000840: 2200 movs r2, #0
|
|
8000842: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
|
|
8000844: 483a ldr r0, [pc, #232] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000846: f003 fd2d bl 80042a4 <HAL_TIM_Base_Init>
|
|
800084a: 4603 mov r3, r0
|
|
800084c: 2b00 cmp r3, #0
|
|
800084e: d001 beq.n 8000854 <MX_TIM2_Init+0x68>
|
|
{
|
|
Error_Handler();
|
|
8000850: f000 f9e6 bl 8000c20 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8000854: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000858: 62bb str r3, [r7, #40] @ 0x28
|
|
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
|
|
800085a: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
800085e: 4619 mov r1, r3
|
|
8000860: 4833 ldr r0, [pc, #204] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000862: f003 ff8f bl 8004784 <HAL_TIM_ConfigClockSource>
|
|
8000866: 4603 mov r3, r0
|
|
8000868: 2b00 cmp r3, #0
|
|
800086a: d001 beq.n 8000870 <MX_TIM2_Init+0x84>
|
|
{
|
|
Error_Handler();
|
|
800086c: f000 f9d8 bl 8000c20 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
|
|
8000870: 482f ldr r0, [pc, #188] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000872: f003 fd66 bl 8004342 <HAL_TIM_PWM_Init>
|
|
8000876: 4603 mov r3, r0
|
|
8000878: 2b00 cmp r3, #0
|
|
800087a: d001 beq.n 8000880 <MX_TIM2_Init+0x94>
|
|
{
|
|
Error_Handler();
|
|
800087c: f000 f9d0 bl 8000c20 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000880: 2300 movs r3, #0
|
|
8000882: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8000884: 2300 movs r3, #0
|
|
8000886: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
8000888: f107 0320 add.w r3, r7, #32
|
|
800088c: 4619 mov r1, r3
|
|
800088e: 4828 ldr r0, [pc, #160] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000890: f004 fb18 bl 8004ec4 <HAL_TIMEx_MasterConfigSynchronization>
|
|
8000894: 4603 mov r3, r0
|
|
8000896: 2b00 cmp r3, #0
|
|
8000898: d001 beq.n 800089e <MX_TIM2_Init+0xb2>
|
|
{
|
|
Error_Handler();
|
|
800089a: f000 f9c1 bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
800089e: 2360 movs r3, #96 @ 0x60
|
|
80008a0: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 1000;
|
|
80008a2: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80008a6: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80008a8: 2300 movs r3, #0
|
|
80008aa: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
|
|
80008ac: 2304 movs r3, #4
|
|
80008ae: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
80008b0: 1d3b adds r3, r7, #4
|
|
80008b2: 2200 movs r2, #0
|
|
80008b4: 4619 mov r1, r3
|
|
80008b6: 481e ldr r0, [pc, #120] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
80008b8: f003 fea2 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
80008bc: 4603 mov r3, r0
|
|
80008be: 2b00 cmp r3, #0
|
|
80008c0: d001 beq.n 80008c6 <MX_TIM2_Init+0xda>
|
|
{
|
|
Error_Handler();
|
|
80008c2: f000 f9ad bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.Pulse = 2000;
|
|
80008c6: f44f 63fa mov.w r3, #2000 @ 0x7d0
|
|
80008ca: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
|
80008cc: 1d3b adds r3, r7, #4
|
|
80008ce: 2204 movs r2, #4
|
|
80008d0: 4619 mov r1, r3
|
|
80008d2: 4817 ldr r0, [pc, #92] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
80008d4: f003 fe94 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
80008d8: 4603 mov r3, r0
|
|
80008da: 2b00 cmp r3, #0
|
|
80008dc: d001 beq.n 80008e2 <MX_TIM2_Init+0xf6>
|
|
{
|
|
Error_Handler();
|
|
80008de: f000 f99f bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.Pulse = 3000;
|
|
80008e2: f640 33b8 movw r3, #3000 @ 0xbb8
|
|
80008e6: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
80008e8: 2300 movs r3, #0
|
|
80008ea: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
|
80008ec: 1d3b adds r3, r7, #4
|
|
80008ee: 2208 movs r2, #8
|
|
80008f0: 4619 mov r1, r3
|
|
80008f2: 480f ldr r0, [pc, #60] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
80008f4: f003 fe84 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
80008f8: 4603 mov r3, r0
|
|
80008fa: 2b00 cmp r3, #0
|
|
80008fc: d001 beq.n 8000902 <MX_TIM2_Init+0x116>
|
|
{
|
|
Error_Handler();
|
|
80008fe: f000 f98f bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.Pulse = 4000;
|
|
8000902: f44f 637a mov.w r3, #4000 @ 0xfa0
|
|
8000906: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
|
|
8000908: 2304 movs r3, #4
|
|
800090a: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
|
|
800090c: 1d3b adds r3, r7, #4
|
|
800090e: 220c movs r2, #12
|
|
8000910: 4619 mov r1, r3
|
|
8000912: 4807 ldr r0, [pc, #28] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000914: f003 fe74 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
8000918: 4603 mov r3, r0
|
|
800091a: 2b00 cmp r3, #0
|
|
800091c: d001 beq.n 8000922 <MX_TIM2_Init+0x136>
|
|
{
|
|
Error_Handler();
|
|
800091e: f000 f97f bl 8000c20 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
8000922: 4803 ldr r0, [pc, #12] @ (8000930 <MX_TIM2_Init+0x144>)
|
|
8000924: f000 fc20 bl 8001168 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000928: bf00 nop
|
|
800092a: 3738 adds r7, #56 @ 0x38
|
|
800092c: 46bd mov sp, r7
|
|
800092e: bd80 pop {r7, pc}
|
|
8000930: 20000280 .word 0x20000280
|
|
|
|
08000934 <MX_TIM4_Init>:
|
|
* @brief TIM4 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM4_Init(void)
|
|
{
|
|
8000934: b580 push {r7, lr}
|
|
8000936: b08e sub sp, #56 @ 0x38
|
|
8000938: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM4_Init 0 */
|
|
|
|
/* USER CODE END TIM4_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
800093a: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
800093e: 2200 movs r2, #0
|
|
8000940: 601a str r2, [r3, #0]
|
|
8000942: 605a str r2, [r3, #4]
|
|
8000944: 609a str r2, [r3, #8]
|
|
8000946: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000948: f107 0320 add.w r3, r7, #32
|
|
800094c: 2200 movs r2, #0
|
|
800094e: 601a str r2, [r3, #0]
|
|
8000950: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8000952: 1d3b adds r3, r7, #4
|
|
8000954: 2200 movs r2, #0
|
|
8000956: 601a str r2, [r3, #0]
|
|
8000958: 605a str r2, [r3, #4]
|
|
800095a: 609a str r2, [r3, #8]
|
|
800095c: 60da str r2, [r3, #12]
|
|
800095e: 611a str r2, [r3, #16]
|
|
8000960: 615a str r2, [r3, #20]
|
|
8000962: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM4_Init 1 */
|
|
|
|
/* USER CODE END TIM4_Init 1 */
|
|
htim4.Instance = TIM4;
|
|
8000964: 4b42 ldr r3, [pc, #264] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000966: 4a43 ldr r2, [pc, #268] @ (8000a74 <MX_TIM4_Init+0x140>)
|
|
8000968: 601a str r2, [r3, #0]
|
|
htim4.Init.Prescaler = 0;
|
|
800096a: 4b41 ldr r3, [pc, #260] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
800096c: 2200 movs r2, #0
|
|
800096e: 605a str r2, [r3, #4]
|
|
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000970: 4b3f ldr r3, [pc, #252] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000972: 2200 movs r2, #0
|
|
8000974: 609a str r2, [r3, #8]
|
|
htim4.Init.Period = 17999;
|
|
8000976: 4b3e ldr r3, [pc, #248] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000978: f244 624f movw r2, #17999 @ 0x464f
|
|
800097c: 60da str r2, [r3, #12]
|
|
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800097e: 4b3c ldr r3, [pc, #240] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000980: 2200 movs r2, #0
|
|
8000982: 611a str r2, [r3, #16]
|
|
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000984: 4b3a ldr r3, [pc, #232] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000986: 2200 movs r2, #0
|
|
8000988: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
|
|
800098a: 4839 ldr r0, [pc, #228] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
800098c: f003 fc8a bl 80042a4 <HAL_TIM_Base_Init>
|
|
8000990: 4603 mov r3, r0
|
|
8000992: 2b00 cmp r3, #0
|
|
8000994: d001 beq.n 800099a <MX_TIM4_Init+0x66>
|
|
{
|
|
Error_Handler();
|
|
8000996: f000 f943 bl 8000c20 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
800099a: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
800099e: 62bb str r3, [r7, #40] @ 0x28
|
|
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
|
|
80009a0: f107 0328 add.w r3, r7, #40 @ 0x28
|
|
80009a4: 4619 mov r1, r3
|
|
80009a6: 4832 ldr r0, [pc, #200] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
80009a8: f003 feec bl 8004784 <HAL_TIM_ConfigClockSource>
|
|
80009ac: 4603 mov r3, r0
|
|
80009ae: 2b00 cmp r3, #0
|
|
80009b0: d001 beq.n 80009b6 <MX_TIM4_Init+0x82>
|
|
{
|
|
Error_Handler();
|
|
80009b2: f000 f935 bl 8000c20 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
|
|
80009b6: 482e ldr r0, [pc, #184] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
80009b8: f003 fcc3 bl 8004342 <HAL_TIM_PWM_Init>
|
|
80009bc: 4603 mov r3, r0
|
|
80009be: 2b00 cmp r3, #0
|
|
80009c0: d001 beq.n 80009c6 <MX_TIM4_Init+0x92>
|
|
{
|
|
Error_Handler();
|
|
80009c2: f000 f92d bl 8000c20 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80009c6: 2300 movs r3, #0
|
|
80009c8: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80009ca: 2300 movs r3, #0
|
|
80009cc: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
|
|
80009ce: f107 0320 add.w r3, r7, #32
|
|
80009d2: 4619 mov r1, r3
|
|
80009d4: 4826 ldr r0, [pc, #152] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
80009d6: f004 fa75 bl 8004ec4 <HAL_TIMEx_MasterConfigSynchronization>
|
|
80009da: 4603 mov r3, r0
|
|
80009dc: 2b00 cmp r3, #0
|
|
80009de: d001 beq.n 80009e4 <MX_TIM4_Init+0xb0>
|
|
{
|
|
Error_Handler();
|
|
80009e0: f000 f91e bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
80009e4: 2360 movs r3, #96 @ 0x60
|
|
80009e6: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 5000;
|
|
80009e8: f241 3388 movw r3, #5000 @ 0x1388
|
|
80009ec: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80009ee: 2300 movs r3, #0
|
|
80009f0: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
|
|
80009f2: 2304 movs r3, #4
|
|
80009f4: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
80009f6: 1d3b adds r3, r7, #4
|
|
80009f8: 2200 movs r2, #0
|
|
80009fa: 4619 mov r1, r3
|
|
80009fc: 481c ldr r0, [pc, #112] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
80009fe: f003 fdff bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
8000a02: 4603 mov r3, r0
|
|
8000a04: 2b00 cmp r3, #0
|
|
8000a06: d001 beq.n 8000a0c <MX_TIM4_Init+0xd8>
|
|
{
|
|
Error_Handler();
|
|
8000a08: f000 f90a bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.Pulse = 6000;
|
|
8000a0c: f241 7370 movw r3, #6000 @ 0x1770
|
|
8000a10: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
|
8000a12: 1d3b adds r3, r7, #4
|
|
8000a14: 2204 movs r2, #4
|
|
8000a16: 4619 mov r1, r3
|
|
8000a18: 4815 ldr r0, [pc, #84] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000a1a: f003 fdf1 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
8000a1e: 4603 mov r3, r0
|
|
8000a20: 2b00 cmp r3, #0
|
|
8000a22: d001 beq.n 8000a28 <MX_TIM4_Init+0xf4>
|
|
{
|
|
Error_Handler();
|
|
8000a24: f000 f8fc bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.Pulse = 7000;
|
|
8000a28: f641 3358 movw r3, #7000 @ 0x1b58
|
|
8000a2c: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
|
8000a2e: 1d3b adds r3, r7, #4
|
|
8000a30: 2208 movs r2, #8
|
|
8000a32: 4619 mov r1, r3
|
|
8000a34: 480e ldr r0, [pc, #56] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000a36: f003 fde3 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
8000a3a: 4603 mov r3, r0
|
|
8000a3c: 2b00 cmp r3, #0
|
|
8000a3e: d001 beq.n 8000a44 <MX_TIM4_Init+0x110>
|
|
{
|
|
Error_Handler();
|
|
8000a40: f000 f8ee bl 8000c20 <Error_Handler>
|
|
}
|
|
sConfigOC.Pulse = 8000;
|
|
8000a44: f44f 53fa mov.w r3, #8000 @ 0x1f40
|
|
8000a48: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
|
|
8000a4a: 1d3b adds r3, r7, #4
|
|
8000a4c: 220c movs r2, #12
|
|
8000a4e: 4619 mov r1, r3
|
|
8000a50: 4807 ldr r0, [pc, #28] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000a52: f003 fdd5 bl 8004600 <HAL_TIM_PWM_ConfigChannel>
|
|
8000a56: 4603 mov r3, r0
|
|
8000a58: 2b00 cmp r3, #0
|
|
8000a5a: d001 beq.n 8000a60 <MX_TIM4_Init+0x12c>
|
|
{
|
|
Error_Handler();
|
|
8000a5c: f000 f8e0 bl 8000c20 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM4_Init 2 */
|
|
|
|
/* USER CODE END TIM4_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim4);
|
|
8000a60: 4803 ldr r0, [pc, #12] @ (8000a70 <MX_TIM4_Init+0x13c>)
|
|
8000a62: f000 fb81 bl 8001168 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000a66: bf00 nop
|
|
8000a68: 3738 adds r7, #56 @ 0x38
|
|
8000a6a: 46bd mov sp, r7
|
|
8000a6c: bd80 pop {r7, pc}
|
|
8000a6e: bf00 nop
|
|
8000a70: 200002c8 .word 0x200002c8
|
|
8000a74: 40000800 .word 0x40000800
|
|
|
|
08000a78 <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
8000a78: b580 push {r7, lr}
|
|
8000a7a: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8000a7c: 4b11 ldr r3, [pc, #68] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000a7e: 4a12 ldr r2, [pc, #72] @ (8000ac8 <MX_USART1_UART_Init+0x50>)
|
|
8000a80: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8000a82: 4b10 ldr r3, [pc, #64] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000a84: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000a88: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000a8a: 4b0e ldr r3, [pc, #56] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000a8c: 2200 movs r2, #0
|
|
8000a8e: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8000a90: 4b0c ldr r3, [pc, #48] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000a92: 2200 movs r2, #0
|
|
8000a94: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8000a96: 4b0b ldr r3, [pc, #44] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000a98: 2200 movs r2, #0
|
|
8000a9a: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8000a9c: 4b09 ldr r3, [pc, #36] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000a9e: 220c movs r2, #12
|
|
8000aa0: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000aa2: 4b08 ldr r3, [pc, #32] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000aa4: 2200 movs r2, #0
|
|
8000aa6: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000aa8: 4b06 ldr r3, [pc, #24] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000aaa: 2200 movs r2, #0
|
|
8000aac: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8000aae: 4805 ldr r0, [pc, #20] @ (8000ac4 <MX_USART1_UART_Init+0x4c>)
|
|
8000ab0: f004 fa66 bl 8004f80 <HAL_UART_Init>
|
|
8000ab4: 4603 mov r3, r0
|
|
8000ab6: 2b00 cmp r3, #0
|
|
8000ab8: d001 beq.n 8000abe <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000aba: f000 f8b1 bl 8000c20 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8000abe: bf00 nop
|
|
8000ac0: bd80 pop {r7, pc}
|
|
8000ac2: bf00 nop
|
|
8000ac4: 20000310 .word 0x20000310
|
|
8000ac8: 40013800 .word 0x40013800
|
|
|
|
08000acc <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000acc: b580 push {r7, lr}
|
|
8000ace: b088 sub sp, #32
|
|
8000ad0: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000ad2: f107 0310 add.w r3, r7, #16
|
|
8000ad6: 2200 movs r2, #0
|
|
8000ad8: 601a str r2, [r3, #0]
|
|
8000ada: 605a str r2, [r3, #4]
|
|
8000adc: 609a str r2, [r3, #8]
|
|
8000ade: 60da str r2, [r3, #12]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000ae0: 4b4b ldr r3, [pc, #300] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000ae2: 699b ldr r3, [r3, #24]
|
|
8000ae4: 4a4a ldr r2, [pc, #296] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000ae6: f043 0310 orr.w r3, r3, #16
|
|
8000aea: 6193 str r3, [r2, #24]
|
|
8000aec: 4b48 ldr r3, [pc, #288] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000aee: 699b ldr r3, [r3, #24]
|
|
8000af0: f003 0310 and.w r3, r3, #16
|
|
8000af4: 60fb str r3, [r7, #12]
|
|
8000af6: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000af8: 4b45 ldr r3, [pc, #276] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000afa: 699b ldr r3, [r3, #24]
|
|
8000afc: 4a44 ldr r2, [pc, #272] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000afe: f043 0320 orr.w r3, r3, #32
|
|
8000b02: 6193 str r3, [r2, #24]
|
|
8000b04: 4b42 ldr r3, [pc, #264] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b06: 699b ldr r3, [r3, #24]
|
|
8000b08: f003 0320 and.w r3, r3, #32
|
|
8000b0c: 60bb str r3, [r7, #8]
|
|
8000b0e: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000b10: 4b3f ldr r3, [pc, #252] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b12: 699b ldr r3, [r3, #24]
|
|
8000b14: 4a3e ldr r2, [pc, #248] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b16: f043 0304 orr.w r3, r3, #4
|
|
8000b1a: 6193 str r3, [r2, #24]
|
|
8000b1c: 4b3c ldr r3, [pc, #240] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b1e: 699b ldr r3, [r3, #24]
|
|
8000b20: f003 0304 and.w r3, r3, #4
|
|
8000b24: 607b str r3, [r7, #4]
|
|
8000b26: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000b28: 4b39 ldr r3, [pc, #228] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b2a: 699b ldr r3, [r3, #24]
|
|
8000b2c: 4a38 ldr r2, [pc, #224] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b2e: f043 0308 orr.w r3, r3, #8
|
|
8000b32: 6193 str r3, [r2, #24]
|
|
8000b34: 4b36 ldr r3, [pc, #216] @ (8000c10 <MX_GPIO_Init+0x144>)
|
|
8000b36: 699b ldr r3, [r3, #24]
|
|
8000b38: f003 0308 and.w r3, r3, #8
|
|
8000b3c: 603b str r3, [r7, #0]
|
|
8000b3e: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
|
|
8000b40: 2200 movs r2, #0
|
|
8000b42: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8000b46: 4833 ldr r0, [pc, #204] @ (8000c14 <MX_GPIO_Init+0x148>)
|
|
8000b48: f001 f954 bl 8001df4 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
|
|
8000b4c: 2200 movs r2, #0
|
|
8000b4e: f640 413e movw r1, #3134 @ 0xc3e
|
|
8000b52: 4831 ldr r0, [pc, #196] @ (8000c18 <MX_GPIO_Init+0x14c>)
|
|
8000b54: f001 f94e bl 8001df4 <HAL_GPIO_WritePin>
|
|
|EXP1_Pin|EXP2_Pin|EXP3_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, BUZ_Pin|LED1_Pin, GPIO_PIN_RESET);
|
|
8000b58: 2200 movs r2, #0
|
|
8000b5a: f44f 4101 mov.w r1, #33024 @ 0x8100
|
|
8000b5e: 482f ldr r0, [pc, #188] @ (8000c1c <MX_GPIO_Init+0x150>)
|
|
8000b60: f001 f948 bl 8001df4 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : LED2_Pin */
|
|
GPIO_InitStruct.Pin = LED2_Pin;
|
|
8000b64: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8000b68: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000b6a: 2301 movs r3, #1
|
|
8000b6c: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000b6e: 2300 movs r3, #0
|
|
8000b70: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000b72: 2302 movs r3, #2
|
|
8000b74: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct);
|
|
8000b76: f107 0310 add.w r3, r7, #16
|
|
8000b7a: 4619 mov r1, r3
|
|
8000b7c: 4825 ldr r0, [pc, #148] @ (8000c14 <MX_GPIO_Init+0x148>)
|
|
8000b7e: f000 ffb5 bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : P1_Pin P2_Pin */
|
|
GPIO_InitStruct.Pin = P1_Pin|P2_Pin;
|
|
8000b82: f44f 4340 mov.w r3, #49152 @ 0xc000
|
|
8000b86: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000b88: 2300 movs r3, #0
|
|
8000b8a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000b8c: 2300 movs r3, #0
|
|
8000b8e: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000b90: f107 0310 add.w r3, r7, #16
|
|
8000b94: 4619 mov r1, r3
|
|
8000b96: 481f ldr r0, [pc, #124] @ (8000c14 <MX_GPIO_Init+0x148>)
|
|
8000b98: f000 ffa8 bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : AIN1_Pin */
|
|
GPIO_InitStruct.Pin = AIN1_Pin;
|
|
8000b9c: 2310 movs r3, #16
|
|
8000b9e: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8000ba0: 2303 movs r3, #3
|
|
8000ba2: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(AIN1_GPIO_Port, &GPIO_InitStruct);
|
|
8000ba4: f107 0310 add.w r3, r7, #16
|
|
8000ba8: 4619 mov r1, r3
|
|
8000baa: 481c ldr r0, [pc, #112] @ (8000c1c <MX_GPIO_Init+0x150>)
|
|
8000bac: f000 ff9e bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : INH1_Pin INH2_Pin INH3_Pin INH4_Pin
|
|
EXP1_Pin EXP2_Pin EXP3_Pin */
|
|
GPIO_InitStruct.Pin = INH1_Pin|INH2_Pin|INH3_Pin|INH4_Pin
|
|
8000bb0: f640 433e movw r3, #3134 @ 0xc3e
|
|
8000bb4: 613b str r3, [r7, #16]
|
|
|EXP1_Pin|EXP2_Pin|EXP3_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000bb6: 2301 movs r3, #1
|
|
8000bb8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000bba: 2300 movs r3, #0
|
|
8000bbc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000bbe: 2302 movs r3, #2
|
|
8000bc0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000bc2: f107 0310 add.w r3, r7, #16
|
|
8000bc6: 4619 mov r1, r3
|
|
8000bc8: 4813 ldr r0, [pc, #76] @ (8000c18 <MX_GPIO_Init+0x14c>)
|
|
8000bca: f000 ff8f bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : CH1_Pin CH2_Pin CH3_Pin CH4_Pin */
|
|
GPIO_InitStruct.Pin = CH1_Pin|CH2_Pin|CH3_Pin|CH4_Pin;
|
|
8000bce: f44f 4370 mov.w r3, #61440 @ 0xf000
|
|
8000bd2: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000bd4: 2300 movs r3, #0
|
|
8000bd6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000bd8: 2300 movs r3, #0
|
|
8000bda: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000bdc: f107 0310 add.w r3, r7, #16
|
|
8000be0: 4619 mov r1, r3
|
|
8000be2: 480d ldr r0, [pc, #52] @ (8000c18 <MX_GPIO_Init+0x14c>)
|
|
8000be4: f000 ff82 bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : BUZ_Pin LED1_Pin */
|
|
GPIO_InitStruct.Pin = BUZ_Pin|LED1_Pin;
|
|
8000be8: f44f 4301 mov.w r3, #33024 @ 0x8100
|
|
8000bec: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000bee: 2301 movs r3, #1
|
|
8000bf0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000bf2: 2300 movs r3, #0
|
|
8000bf4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000bf6: 2302 movs r3, #2
|
|
8000bf8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000bfa: f107 0310 add.w r3, r7, #16
|
|
8000bfe: 4619 mov r1, r3
|
|
8000c00: 4806 ldr r0, [pc, #24] @ (8000c1c <MX_GPIO_Init+0x150>)
|
|
8000c02: f000 ff73 bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000c06: bf00 nop
|
|
8000c08: 3720 adds r7, #32
|
|
8000c0a: 46bd mov sp, r7
|
|
8000c0c: bd80 pop {r7, pc}
|
|
8000c0e: bf00 nop
|
|
8000c10: 40021000 .word 0x40021000
|
|
8000c14: 40011000 .word 0x40011000
|
|
8000c18: 40010c00 .word 0x40010c00
|
|
8000c1c: 40010800 .word 0x40010800
|
|
|
|
08000c20 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000c20: b480 push {r7}
|
|
8000c22: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000c24: b672 cpsid i
|
|
}
|
|
8000c26: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000c28: bf00 nop
|
|
8000c2a: e7fd b.n 8000c28 <Error_Handler+0x8>
|
|
|
|
08000c2c <IsPwmRunning>:
|
|
extern TIM_HandleTypeDef htim2;
|
|
extern TIM_HandleTypeDef htim3;
|
|
extern TIM_HandleTypeDef htim4;
|
|
|
|
bool IsPwmRunning(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
8000c2c: b580 push {r7, lr}
|
|
8000c2e: b084 sub sp, #16
|
|
8000c30: af00 add r7, sp, #0
|
|
8000c32: 6078 str r0, [r7, #4]
|
|
8000c34: 6039 str r1, [r7, #0]
|
|
HAL_TIM_ChannelStateTypeDef chState = HAL_TIM_GetChannelState(htim, Channel);
|
|
8000c36: 6839 ldr r1, [r7, #0]
|
|
8000c38: 6878 ldr r0, [r7, #4]
|
|
8000c3a: f003 fe6a bl 8004912 <HAL_TIM_GetChannelState>
|
|
8000c3e: 4603 mov r3, r0
|
|
8000c40: 73fb strb r3, [r7, #15]
|
|
|
|
return (chState == HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8000c42: 7bfb ldrb r3, [r7, #15]
|
|
8000c44: 2b02 cmp r3, #2
|
|
8000c46: bf0c ite eq
|
|
8000c48: 2301 moveq r3, #1
|
|
8000c4a: 2300 movne r3, #0
|
|
8000c4c: b2db uxtb r3, r3
|
|
}
|
|
8000c4e: 4618 mov r0, r3
|
|
8000c50: 3710 adds r7, #16
|
|
8000c52: 46bd mov sp, r7
|
|
8000c54: bd80 pop {r7, pc}
|
|
|
|
08000c56 <StopMot>:
|
|
|
|
void StopMot(TIM_HandleTypeDef *htim,uint32_t Channel){
|
|
8000c56: b580 push {r7, lr}
|
|
8000c58: b082 sub sp, #8
|
|
8000c5a: af00 add r7, sp, #0
|
|
8000c5c: 6078 str r0, [r7, #4]
|
|
8000c5e: 6039 str r1, [r7, #0]
|
|
HAL_TIM_PWM_Stop(htim, Channel);
|
|
8000c60: 6839 ldr r1, [r7, #0]
|
|
8000c62: 6878 ldr r0, [r7, #4]
|
|
8000c64: f003 fc68 bl 8004538 <HAL_TIM_PWM_Stop>
|
|
}
|
|
8000c68: bf00 nop
|
|
8000c6a: 3708 adds r7, #8
|
|
8000c6c: 46bd mov sp, r7
|
|
8000c6e: bd80 pop {r7, pc}
|
|
|
|
08000c70 <StartMot>:
|
|
|
|
void StartMot(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
|
|
8000c70: b580 push {r7, lr}
|
|
8000c72: b084 sub sp, #16
|
|
8000c74: af00 add r7, sp, #0
|
|
8000c76: 60f8 str r0, [r7, #12]
|
|
8000c78: 60b9 str r1, [r7, #8]
|
|
8000c7a: 4613 mov r3, r2
|
|
8000c7c: 80fb strh r3, [r7, #6]
|
|
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
|
|
8000c7e: 68bb ldr r3, [r7, #8]
|
|
8000c80: 2b00 cmp r3, #0
|
|
8000c82: d104 bne.n 8000c8e <StartMot+0x1e>
|
|
8000c84: 68fb ldr r3, [r7, #12]
|
|
8000c86: 681b ldr r3, [r3, #0]
|
|
8000c88: 88fa ldrh r2, [r7, #6]
|
|
8000c8a: 635a str r2, [r3, #52] @ 0x34
|
|
8000c8c: e013 b.n 8000cb6 <StartMot+0x46>
|
|
8000c8e: 68bb ldr r3, [r7, #8]
|
|
8000c90: 2b04 cmp r3, #4
|
|
8000c92: d104 bne.n 8000c9e <StartMot+0x2e>
|
|
8000c94: 68fb ldr r3, [r7, #12]
|
|
8000c96: 681a ldr r2, [r3, #0]
|
|
8000c98: 88fb ldrh r3, [r7, #6]
|
|
8000c9a: 6393 str r3, [r2, #56] @ 0x38
|
|
8000c9c: e00b b.n 8000cb6 <StartMot+0x46>
|
|
8000c9e: 68bb ldr r3, [r7, #8]
|
|
8000ca0: 2b08 cmp r3, #8
|
|
8000ca2: d104 bne.n 8000cae <StartMot+0x3e>
|
|
8000ca4: 68fb ldr r3, [r7, #12]
|
|
8000ca6: 681a ldr r2, [r3, #0]
|
|
8000ca8: 88fb ldrh r3, [r7, #6]
|
|
8000caa: 63d3 str r3, [r2, #60] @ 0x3c
|
|
8000cac: e003 b.n 8000cb6 <StartMot+0x46>
|
|
8000cae: 68fb ldr r3, [r7, #12]
|
|
8000cb0: 681a ldr r2, [r3, #0]
|
|
8000cb2: 88fb ldrh r3, [r7, #6]
|
|
8000cb4: 6413 str r3, [r2, #64] @ 0x40
|
|
HAL_TIM_PWM_Start(htim, Channel);
|
|
8000cb6: 68b9 ldr r1, [r7, #8]
|
|
8000cb8: 68f8 ldr r0, [r7, #12]
|
|
8000cba: f003 fb9b bl 80043f4 <HAL_TIM_PWM_Start>
|
|
}
|
|
8000cbe: bf00 nop
|
|
8000cc0: 3710 adds r7, #16
|
|
8000cc2: 46bd mov sp, r7
|
|
8000cc4: bd80 pop {r7, pc}
|
|
|
|
08000cc6 <SetMotPwm>:
|
|
|
|
void SetMotPwm(TIM_HandleTypeDef *htim,uint32_t Channel,uint16_t pwmval){
|
|
8000cc6: b480 push {r7}
|
|
8000cc8: b085 sub sp, #20
|
|
8000cca: af00 add r7, sp, #0
|
|
8000ccc: 60f8 str r0, [r7, #12]
|
|
8000cce: 60b9 str r1, [r7, #8]
|
|
8000cd0: 4613 mov r3, r2
|
|
8000cd2: 80fb strh r3, [r7, #6]
|
|
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
|
|
8000cd4: 68bb ldr r3, [r7, #8]
|
|
8000cd6: 2b00 cmp r3, #0
|
|
8000cd8: d104 bne.n 8000ce4 <SetMotPwm+0x1e>
|
|
8000cda: 68fb ldr r3, [r7, #12]
|
|
8000cdc: 681b ldr r3, [r3, #0]
|
|
8000cde: 88fa ldrh r2, [r7, #6]
|
|
8000ce0: 635a str r2, [r3, #52] @ 0x34
|
|
}
|
|
8000ce2: e013 b.n 8000d0c <SetMotPwm+0x46>
|
|
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
|
|
8000ce4: 68bb ldr r3, [r7, #8]
|
|
8000ce6: 2b04 cmp r3, #4
|
|
8000ce8: d104 bne.n 8000cf4 <SetMotPwm+0x2e>
|
|
8000cea: 68fb ldr r3, [r7, #12]
|
|
8000cec: 681a ldr r2, [r3, #0]
|
|
8000cee: 88fb ldrh r3, [r7, #6]
|
|
8000cf0: 6393 str r3, [r2, #56] @ 0x38
|
|
}
|
|
8000cf2: e00b b.n 8000d0c <SetMotPwm+0x46>
|
|
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
|
|
8000cf4: 68bb ldr r3, [r7, #8]
|
|
8000cf6: 2b08 cmp r3, #8
|
|
8000cf8: d104 bne.n 8000d04 <SetMotPwm+0x3e>
|
|
8000cfa: 68fb ldr r3, [r7, #12]
|
|
8000cfc: 681a ldr r2, [r3, #0]
|
|
8000cfe: 88fb ldrh r3, [r7, #6]
|
|
8000d00: 63d3 str r3, [r2, #60] @ 0x3c
|
|
}
|
|
8000d02: e003 b.n 8000d0c <SetMotPwm+0x46>
|
|
__HAL_TIM_SET_COMPARE(htim, Channel, pwmval);
|
|
8000d04: 68fb ldr r3, [r7, #12]
|
|
8000d06: 681a ldr r2, [r3, #0]
|
|
8000d08: 88fb ldrh r3, [r7, #6]
|
|
8000d0a: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
8000d0c: bf00 nop
|
|
8000d0e: 3714 adds r7, #20
|
|
8000d10: 46bd mov sp, r7
|
|
8000d12: bc80 pop {r7}
|
|
8000d14: 4770 bx lr
|
|
...
|
|
|
|
08000d18 <SetMot>:
|
|
|
|
void SetMot(uint8_t mot,uint8_t dir,uint16_t pwmval){
|
|
8000d18: b580 push {r7, lr}
|
|
8000d1a: b082 sub sp, #8
|
|
8000d1c: af00 add r7, sp, #0
|
|
8000d1e: 4603 mov r3, r0
|
|
8000d20: 71fb strb r3, [r7, #7]
|
|
8000d22: 460b mov r3, r1
|
|
8000d24: 71bb strb r3, [r7, #6]
|
|
8000d26: 4613 mov r3, r2
|
|
8000d28: 80bb strh r3, [r7, #4]
|
|
switch(mot){
|
|
8000d2a: 79fb ldrb r3, [r7, #7]
|
|
8000d2c: 3b01 subs r3, #1
|
|
8000d2e: 2b03 cmp r3, #3
|
|
8000d30: f200 8158 bhi.w 8000fe4 <SetMot+0x2cc>
|
|
8000d34: a201 add r2, pc, #4 @ (adr r2, 8000d3c <SetMot+0x24>)
|
|
8000d36: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8000d3a: bf00 nop
|
|
8000d3c: 08000d4d .word 0x08000d4d
|
|
8000d40: 08000def .word 0x08000def
|
|
8000d44: 08000e91 .word 0x08000e91
|
|
8000d48: 08000f3b .word 0x08000f3b
|
|
case 1:
|
|
if(dir==FW){
|
|
8000d4c: 79bb ldrb r3, [r7, #6]
|
|
8000d4e: 2b00 cmp r3, #0
|
|
8000d50: d126 bne.n 8000da0 <SetMot+0x88>
|
|
if(pwmval==0){
|
|
8000d52: 88bb ldrh r3, [r7, #4]
|
|
8000d54: 2b00 cmp r3, #0
|
|
8000d56: d109 bne.n 8000d6c <SetMot+0x54>
|
|
StopMot(timMot1,FWMot1);
|
|
8000d58: 2100 movs r1, #0
|
|
8000d5a: 48a5 ldr r0, [pc, #660] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000d5c: f7ff ff7b bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
|
|
8000d60: 2200 movs r2, #0
|
|
8000d62: 2102 movs r1, #2
|
|
8000d64: 48a3 ldr r0, [pc, #652] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000d66: f001 f845 bl 8001df4 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
|
|
StartMot(timMot1,BWMot1,pwmval);
|
|
|
|
}
|
|
}
|
|
break;
|
|
8000d6a: e13c b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot1, FWMot1)){
|
|
8000d6c: 2100 movs r1, #0
|
|
8000d6e: 48a0 ldr r0, [pc, #640] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000d70: f7ff ff5c bl 8000c2c <IsPwmRunning>
|
|
8000d74: 4603 mov r3, r0
|
|
8000d76: 2b00 cmp r3, #0
|
|
8000d78: d006 beq.n 8000d88 <SetMot+0x70>
|
|
SetMotPwm(timMot1,FWMot1,pwmval);
|
|
8000d7a: 88bb ldrh r3, [r7, #4]
|
|
8000d7c: 461a mov r2, r3
|
|
8000d7e: 2100 movs r1, #0
|
|
8000d80: 489b ldr r0, [pc, #620] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000d82: f7ff ffa0 bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000d86: e12e b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
|
|
8000d88: 2201 movs r2, #1
|
|
8000d8a: 2102 movs r1, #2
|
|
8000d8c: 4899 ldr r0, [pc, #612] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000d8e: f001 f831 bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot1,FWMot1,pwmval);
|
|
8000d92: 88bb ldrh r3, [r7, #4]
|
|
8000d94: 461a mov r2, r3
|
|
8000d96: 2100 movs r1, #0
|
|
8000d98: 4895 ldr r0, [pc, #596] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000d9a: f7ff ff69 bl 8000c70 <StartMot>
|
|
break;
|
|
8000d9e: e122 b.n 8000fe6 <SetMot+0x2ce>
|
|
if(pwmval==0){
|
|
8000da0: 88bb ldrh r3, [r7, #4]
|
|
8000da2: 2b00 cmp r3, #0
|
|
8000da4: d109 bne.n 8000dba <SetMot+0xa2>
|
|
StopMot(timMot1,BWMot1);
|
|
8000da6: 2104 movs r1, #4
|
|
8000da8: 4891 ldr r0, [pc, #580] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000daa: f7ff ff54 bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_RESET);
|
|
8000dae: 2200 movs r2, #0
|
|
8000db0: 2102 movs r1, #2
|
|
8000db2: 4890 ldr r0, [pc, #576] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000db4: f001 f81e bl 8001df4 <HAL_GPIO_WritePin>
|
|
break;
|
|
8000db8: e115 b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot1, BWMot1)){
|
|
8000dba: 2104 movs r1, #4
|
|
8000dbc: 488c ldr r0, [pc, #560] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000dbe: f7ff ff35 bl 8000c2c <IsPwmRunning>
|
|
8000dc2: 4603 mov r3, r0
|
|
8000dc4: 2b00 cmp r3, #0
|
|
8000dc6: d006 beq.n 8000dd6 <SetMot+0xbe>
|
|
SetMotPwm(timMot1,BWMot1,pwmval);
|
|
8000dc8: 88bb ldrh r3, [r7, #4]
|
|
8000dca: 461a mov r2, r3
|
|
8000dcc: 2104 movs r1, #4
|
|
8000dce: 4888 ldr r0, [pc, #544] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000dd0: f7ff ff79 bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000dd4: e107 b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH1_GPIO_Port, INH1_Pin, GPIO_PIN_SET);
|
|
8000dd6: 2201 movs r2, #1
|
|
8000dd8: 2102 movs r1, #2
|
|
8000dda: 4886 ldr r0, [pc, #536] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000ddc: f001 f80a bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot1,BWMot1,pwmval);
|
|
8000de0: 88bb ldrh r3, [r7, #4]
|
|
8000de2: 461a mov r2, r3
|
|
8000de4: 2104 movs r1, #4
|
|
8000de6: 4882 ldr r0, [pc, #520] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000de8: f7ff ff42 bl 8000c70 <StartMot>
|
|
break;
|
|
8000dec: e0fb b.n 8000fe6 <SetMot+0x2ce>
|
|
case 2:
|
|
if(dir==FW){
|
|
8000dee: 79bb ldrb r3, [r7, #6]
|
|
8000df0: 2b00 cmp r3, #0
|
|
8000df2: d126 bne.n 8000e42 <SetMot+0x12a>
|
|
if(pwmval==0){
|
|
8000df4: 88bb ldrh r3, [r7, #4]
|
|
8000df6: 2b00 cmp r3, #0
|
|
8000df8: d109 bne.n 8000e0e <SetMot+0xf6>
|
|
StopMot(timMot2,FWMot2);
|
|
8000dfa: 2108 movs r1, #8
|
|
8000dfc: 487c ldr r0, [pc, #496] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000dfe: f7ff ff2a bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
|
|
8000e02: 2200 movs r2, #0
|
|
8000e04: 2104 movs r1, #4
|
|
8000e06: 487b ldr r0, [pc, #492] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000e08: f000 fff4 bl 8001df4 <HAL_GPIO_WritePin>
|
|
}else{
|
|
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
|
|
StartMot(timMot2,BWMot2,pwmval);
|
|
}
|
|
}
|
|
break;
|
|
8000e0c: e0eb b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot2, FWMot2)){
|
|
8000e0e: 2108 movs r1, #8
|
|
8000e10: 4877 ldr r0, [pc, #476] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e12: f7ff ff0b bl 8000c2c <IsPwmRunning>
|
|
8000e16: 4603 mov r3, r0
|
|
8000e18: 2b00 cmp r3, #0
|
|
8000e1a: d006 beq.n 8000e2a <SetMot+0x112>
|
|
SetMotPwm(timMot2,FWMot2,pwmval);
|
|
8000e1c: 88bb ldrh r3, [r7, #4]
|
|
8000e1e: 461a mov r2, r3
|
|
8000e20: 2108 movs r1, #8
|
|
8000e22: 4873 ldr r0, [pc, #460] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e24: f7ff ff4f bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000e28: e0dd b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
|
|
8000e2a: 2201 movs r2, #1
|
|
8000e2c: 2104 movs r1, #4
|
|
8000e2e: 4871 ldr r0, [pc, #452] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000e30: f000 ffe0 bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot2,FWMot2,pwmval);
|
|
8000e34: 88bb ldrh r3, [r7, #4]
|
|
8000e36: 461a mov r2, r3
|
|
8000e38: 2108 movs r1, #8
|
|
8000e3a: 486d ldr r0, [pc, #436] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e3c: f7ff ff18 bl 8000c70 <StartMot>
|
|
break;
|
|
8000e40: e0d1 b.n 8000fe6 <SetMot+0x2ce>
|
|
if(pwmval==0){
|
|
8000e42: 88bb ldrh r3, [r7, #4]
|
|
8000e44: 2b00 cmp r3, #0
|
|
8000e46: d109 bne.n 8000e5c <SetMot+0x144>
|
|
StopMot(timMot2,BWMot2);
|
|
8000e48: 210c movs r1, #12
|
|
8000e4a: 4869 ldr r0, [pc, #420] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e4c: f7ff ff03 bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_RESET);
|
|
8000e50: 2200 movs r2, #0
|
|
8000e52: 2104 movs r1, #4
|
|
8000e54: 4867 ldr r0, [pc, #412] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000e56: f000 ffcd bl 8001df4 <HAL_GPIO_WritePin>
|
|
break;
|
|
8000e5a: e0c4 b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot2, BWMot2)){
|
|
8000e5c: 210c movs r1, #12
|
|
8000e5e: 4864 ldr r0, [pc, #400] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e60: f7ff fee4 bl 8000c2c <IsPwmRunning>
|
|
8000e64: 4603 mov r3, r0
|
|
8000e66: 2b00 cmp r3, #0
|
|
8000e68: d006 beq.n 8000e78 <SetMot+0x160>
|
|
SetMotPwm(timMot2,BWMot2,pwmval);
|
|
8000e6a: 88bb ldrh r3, [r7, #4]
|
|
8000e6c: 461a mov r2, r3
|
|
8000e6e: 210c movs r1, #12
|
|
8000e70: 485f ldr r0, [pc, #380] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e72: f7ff ff28 bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000e76: e0b6 b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH2_GPIO_Port, INH2_Pin, GPIO_PIN_SET);
|
|
8000e78: 2201 movs r2, #1
|
|
8000e7a: 2104 movs r1, #4
|
|
8000e7c: 485d ldr r0, [pc, #372] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000e7e: f000 ffb9 bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot2,BWMot2,pwmval);
|
|
8000e82: 88bb ldrh r3, [r7, #4]
|
|
8000e84: 461a mov r2, r3
|
|
8000e86: 210c movs r1, #12
|
|
8000e88: 4859 ldr r0, [pc, #356] @ (8000ff0 <SetMot+0x2d8>)
|
|
8000e8a: f7ff fef1 bl 8000c70 <StartMot>
|
|
break;
|
|
8000e8e: e0aa b.n 8000fe6 <SetMot+0x2ce>
|
|
case 3:
|
|
if(dir==FW){
|
|
8000e90: 79bb ldrb r3, [r7, #6]
|
|
8000e92: 2b00 cmp r3, #0
|
|
8000e94: d128 bne.n 8000ee8 <SetMot+0x1d0>
|
|
if(pwmval==0){
|
|
8000e96: 88bb ldrh r3, [r7, #4]
|
|
8000e98: 2b00 cmp r3, #0
|
|
8000e9a: d10a bne.n 8000eb2 <SetMot+0x19a>
|
|
StopMot(timMot3,FWMot3);
|
|
8000e9c: 2100 movs r1, #0
|
|
8000e9e: 4856 ldr r0, [pc, #344] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000ea0: f7ff fed9 bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
|
|
8000ea4: 2200 movs r2, #0
|
|
8000ea6: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8000eaa: 4852 ldr r0, [pc, #328] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000eac: f000 ffa2 bl 8001df4 <HAL_GPIO_WritePin>
|
|
}else{
|
|
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
|
|
StartMot(timMot3,BWMot3,pwmval);
|
|
}
|
|
}
|
|
break;
|
|
8000eb0: e099 b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot3, FWMot3)){
|
|
8000eb2: 2100 movs r1, #0
|
|
8000eb4: 4850 ldr r0, [pc, #320] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000eb6: f7ff feb9 bl 8000c2c <IsPwmRunning>
|
|
8000eba: 4603 mov r3, r0
|
|
8000ebc: 2b00 cmp r3, #0
|
|
8000ebe: d006 beq.n 8000ece <SetMot+0x1b6>
|
|
SetMotPwm(timMot3,FWMot3,pwmval);
|
|
8000ec0: 88bb ldrh r3, [r7, #4]
|
|
8000ec2: 461a mov r2, r3
|
|
8000ec4: 2100 movs r1, #0
|
|
8000ec6: 484c ldr r0, [pc, #304] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000ec8: f7ff fefd bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000ecc: e08b b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
|
|
8000ece: 2201 movs r2, #1
|
|
8000ed0: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8000ed4: 4847 ldr r0, [pc, #284] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000ed6: f000 ff8d bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot3,FWMot3,pwmval);
|
|
8000eda: 88bb ldrh r3, [r7, #4]
|
|
8000edc: 461a mov r2, r3
|
|
8000ede: 2100 movs r1, #0
|
|
8000ee0: 4845 ldr r0, [pc, #276] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000ee2: f7ff fec5 bl 8000c70 <StartMot>
|
|
break;
|
|
8000ee6: e07e b.n 8000fe6 <SetMot+0x2ce>
|
|
if(pwmval==0){
|
|
8000ee8: 88bb ldrh r3, [r7, #4]
|
|
8000eea: 2b00 cmp r3, #0
|
|
8000eec: d10a bne.n 8000f04 <SetMot+0x1ec>
|
|
StopMot(timMot3,BWMot3);
|
|
8000eee: 2104 movs r1, #4
|
|
8000ef0: 4841 ldr r0, [pc, #260] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000ef2: f7ff feb0 bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_RESET);
|
|
8000ef6: 2200 movs r2, #0
|
|
8000ef8: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8000efc: 483d ldr r0, [pc, #244] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000efe: f000 ff79 bl 8001df4 <HAL_GPIO_WritePin>
|
|
break;
|
|
8000f02: e070 b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot3, BWMot3)){
|
|
8000f04: 2104 movs r1, #4
|
|
8000f06: 483c ldr r0, [pc, #240] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f08: f7ff fe90 bl 8000c2c <IsPwmRunning>
|
|
8000f0c: 4603 mov r3, r0
|
|
8000f0e: 2b00 cmp r3, #0
|
|
8000f10: d006 beq.n 8000f20 <SetMot+0x208>
|
|
SetMotPwm(timMot3,BWMot3,pwmval);
|
|
8000f12: 88bb ldrh r3, [r7, #4]
|
|
8000f14: 461a mov r2, r3
|
|
8000f16: 2104 movs r1, #4
|
|
8000f18: 4837 ldr r0, [pc, #220] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f1a: f7ff fed4 bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000f1e: e062 b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH3_GPIO_Port, INH3_Pin, GPIO_PIN_SET);
|
|
8000f20: 2201 movs r2, #1
|
|
8000f22: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8000f26: 4833 ldr r0, [pc, #204] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000f28: f000 ff64 bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot3,BWMot3,pwmval);
|
|
8000f2c: 88bb ldrh r3, [r7, #4]
|
|
8000f2e: 461a mov r2, r3
|
|
8000f30: 2104 movs r1, #4
|
|
8000f32: 4831 ldr r0, [pc, #196] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f34: f7ff fe9c bl 8000c70 <StartMot>
|
|
break;
|
|
8000f38: e055 b.n 8000fe6 <SetMot+0x2ce>
|
|
case 4:
|
|
if(dir==FW){
|
|
8000f3a: 79bb ldrb r3, [r7, #6]
|
|
8000f3c: 2b00 cmp r3, #0
|
|
8000f3e: d128 bne.n 8000f92 <SetMot+0x27a>
|
|
if(pwmval==0){
|
|
8000f40: 88bb ldrh r3, [r7, #4]
|
|
8000f42: 2b00 cmp r3, #0
|
|
8000f44: d10a bne.n 8000f5c <SetMot+0x244>
|
|
StopMot(timMot4,FWMot4);
|
|
8000f46: 2108 movs r1, #8
|
|
8000f48: 482b ldr r0, [pc, #172] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f4a: f7ff fe84 bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
|
|
8000f4e: 2200 movs r2, #0
|
|
8000f50: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8000f54: 4827 ldr r0, [pc, #156] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000f56: f000 ff4d bl 8001df4 <HAL_GPIO_WritePin>
|
|
}else{
|
|
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
|
|
StartMot(timMot4,BWMot4,pwmval);
|
|
}
|
|
}
|
|
break;
|
|
8000f5a: e044 b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot4, FWMot4)){
|
|
8000f5c: 2108 movs r1, #8
|
|
8000f5e: 4826 ldr r0, [pc, #152] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f60: f7ff fe64 bl 8000c2c <IsPwmRunning>
|
|
8000f64: 4603 mov r3, r0
|
|
8000f66: 2b00 cmp r3, #0
|
|
8000f68: d006 beq.n 8000f78 <SetMot+0x260>
|
|
SetMotPwm(timMot4,FWMot4,pwmval);
|
|
8000f6a: 88bb ldrh r3, [r7, #4]
|
|
8000f6c: 461a mov r2, r3
|
|
8000f6e: 2108 movs r1, #8
|
|
8000f70: 4821 ldr r0, [pc, #132] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f72: f7ff fea8 bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000f76: e036 b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
|
|
8000f78: 2201 movs r2, #1
|
|
8000f7a: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8000f7e: 481d ldr r0, [pc, #116] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000f80: f000 ff38 bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot4,FWMot4,pwmval);
|
|
8000f84: 88bb ldrh r3, [r7, #4]
|
|
8000f86: 461a mov r2, r3
|
|
8000f88: 2108 movs r1, #8
|
|
8000f8a: 481b ldr r0, [pc, #108] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f8c: f7ff fe70 bl 8000c70 <StartMot>
|
|
break;
|
|
8000f90: e029 b.n 8000fe6 <SetMot+0x2ce>
|
|
if(pwmval==0){
|
|
8000f92: 88bb ldrh r3, [r7, #4]
|
|
8000f94: 2b00 cmp r3, #0
|
|
8000f96: d10a bne.n 8000fae <SetMot+0x296>
|
|
StopMot(timMot4,BWMot4);
|
|
8000f98: 210c movs r1, #12
|
|
8000f9a: 4817 ldr r0, [pc, #92] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000f9c: f7ff fe5b bl 8000c56 <StopMot>
|
|
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_RESET);
|
|
8000fa0: 2200 movs r2, #0
|
|
8000fa2: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8000fa6: 4813 ldr r0, [pc, #76] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000fa8: f000 ff24 bl 8001df4 <HAL_GPIO_WritePin>
|
|
break;
|
|
8000fac: e01b b.n 8000fe6 <SetMot+0x2ce>
|
|
}else if(IsPwmRunning(timMot4, BWMot4)){
|
|
8000fae: 210c movs r1, #12
|
|
8000fb0: 4811 ldr r0, [pc, #68] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000fb2: f7ff fe3b bl 8000c2c <IsPwmRunning>
|
|
8000fb6: 4603 mov r3, r0
|
|
8000fb8: 2b00 cmp r3, #0
|
|
8000fba: d006 beq.n 8000fca <SetMot+0x2b2>
|
|
SetMotPwm(timMot4,BWMot4,pwmval);
|
|
8000fbc: 88bb ldrh r3, [r7, #4]
|
|
8000fbe: 461a mov r2, r3
|
|
8000fc0: 210c movs r1, #12
|
|
8000fc2: 480d ldr r0, [pc, #52] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000fc4: f7ff fe7f bl 8000cc6 <SetMotPwm>
|
|
break;
|
|
8000fc8: e00d b.n 8000fe6 <SetMot+0x2ce>
|
|
HAL_GPIO_WritePin(INH4_GPIO_Port, INH4_Pin, GPIO_PIN_SET);
|
|
8000fca: 2201 movs r2, #1
|
|
8000fcc: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8000fd0: 4808 ldr r0, [pc, #32] @ (8000ff4 <SetMot+0x2dc>)
|
|
8000fd2: f000 ff0f bl 8001df4 <HAL_GPIO_WritePin>
|
|
StartMot(timMot4,BWMot4,pwmval);
|
|
8000fd6: 88bb ldrh r3, [r7, #4]
|
|
8000fd8: 461a mov r2, r3
|
|
8000fda: 210c movs r1, #12
|
|
8000fdc: 4806 ldr r0, [pc, #24] @ (8000ff8 <SetMot+0x2e0>)
|
|
8000fde: f7ff fe47 bl 8000c70 <StartMot>
|
|
break;
|
|
8000fe2: e000 b.n 8000fe6 <SetMot+0x2ce>
|
|
default:
|
|
break;
|
|
8000fe4: bf00 nop
|
|
}
|
|
|
|
}
|
|
8000fe6: bf00 nop
|
|
8000fe8: 3708 adds r7, #8
|
|
8000fea: 46bd mov sp, r7
|
|
8000fec: bd80 pop {r7, pc}
|
|
8000fee: bf00 nop
|
|
8000ff0: 20000280 .word 0x20000280
|
|
8000ff4: 40010c00 .word 0x40010c00
|
|
8000ff8: 200002c8 .word 0x200002c8
|
|
|
|
08000ffc <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000ffc: b480 push {r7}
|
|
8000ffe: b085 sub sp, #20
|
|
8001000: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
8001002: 4b15 ldr r3, [pc, #84] @ (8001058 <HAL_MspInit+0x5c>)
|
|
8001004: 699b ldr r3, [r3, #24]
|
|
8001006: 4a14 ldr r2, [pc, #80] @ (8001058 <HAL_MspInit+0x5c>)
|
|
8001008: f043 0301 orr.w r3, r3, #1
|
|
800100c: 6193 str r3, [r2, #24]
|
|
800100e: 4b12 ldr r3, [pc, #72] @ (8001058 <HAL_MspInit+0x5c>)
|
|
8001010: 699b ldr r3, [r3, #24]
|
|
8001012: f003 0301 and.w r3, r3, #1
|
|
8001016: 60bb str r3, [r7, #8]
|
|
8001018: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800101a: 4b0f ldr r3, [pc, #60] @ (8001058 <HAL_MspInit+0x5c>)
|
|
800101c: 69db ldr r3, [r3, #28]
|
|
800101e: 4a0e ldr r2, [pc, #56] @ (8001058 <HAL_MspInit+0x5c>)
|
|
8001020: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001024: 61d3 str r3, [r2, #28]
|
|
8001026: 4b0c ldr r3, [pc, #48] @ (8001058 <HAL_MspInit+0x5c>)
|
|
8001028: 69db ldr r3, [r3, #28]
|
|
800102a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800102e: 607b str r3, [r7, #4]
|
|
8001030: 687b ldr r3, [r7, #4]
|
|
|
|
/* System interrupt init*/
|
|
|
|
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
|
*/
|
|
__HAL_AFIO_REMAP_SWJ_NOJTAG();
|
|
8001032: 4b0a ldr r3, [pc, #40] @ (800105c <HAL_MspInit+0x60>)
|
|
8001034: 685b ldr r3, [r3, #4]
|
|
8001036: 60fb str r3, [r7, #12]
|
|
8001038: 68fb ldr r3, [r7, #12]
|
|
800103a: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
|
|
800103e: 60fb str r3, [r7, #12]
|
|
8001040: 68fb ldr r3, [r7, #12]
|
|
8001042: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8001046: 60fb str r3, [r7, #12]
|
|
8001048: 4a04 ldr r2, [pc, #16] @ (800105c <HAL_MspInit+0x60>)
|
|
800104a: 68fb ldr r3, [r7, #12]
|
|
800104c: 6053 str r3, [r2, #4]
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
800104e: bf00 nop
|
|
8001050: 3714 adds r7, #20
|
|
8001052: 46bd mov sp, r7
|
|
8001054: bc80 pop {r7}
|
|
8001056: 4770 bx lr
|
|
8001058: 40021000 .word 0x40021000
|
|
800105c: 40010000 .word 0x40010000
|
|
|
|
08001060 <HAL_ADC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8001060: b580 push {r7, lr}
|
|
8001062: b08a sub sp, #40 @ 0x28
|
|
8001064: af00 add r7, sp, #0
|
|
8001066: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001068: f107 0318 add.w r3, r7, #24
|
|
800106c: 2200 movs r2, #0
|
|
800106e: 601a str r2, [r3, #0]
|
|
8001070: 605a str r2, [r3, #4]
|
|
8001072: 609a str r2, [r3, #8]
|
|
8001074: 60da str r2, [r3, #12]
|
|
if(hadc->Instance==ADC1)
|
|
8001076: 687b ldr r3, [r7, #4]
|
|
8001078: 681b ldr r3, [r3, #0]
|
|
800107a: 4a1f ldr r2, [pc, #124] @ (80010f8 <HAL_ADC_MspInit+0x98>)
|
|
800107c: 4293 cmp r3, r2
|
|
800107e: d137 bne.n 80010f0 <HAL_ADC_MspInit+0x90>
|
|
{
|
|
/* USER CODE BEGIN ADC1_MspInit 0 */
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_ADC1_CLK_ENABLE();
|
|
8001080: 4b1e ldr r3, [pc, #120] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
8001082: 699b ldr r3, [r3, #24]
|
|
8001084: 4a1d ldr r2, [pc, #116] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
8001086: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800108a: 6193 str r3, [r2, #24]
|
|
800108c: 4b1b ldr r3, [pc, #108] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
800108e: 699b ldr r3, [r3, #24]
|
|
8001090: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001094: 617b str r3, [r7, #20]
|
|
8001096: 697b ldr r3, [r7, #20]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001098: 4b18 ldr r3, [pc, #96] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
800109a: 699b ldr r3, [r3, #24]
|
|
800109c: 4a17 ldr r2, [pc, #92] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
800109e: f043 0304 orr.w r3, r3, #4
|
|
80010a2: 6193 str r3, [r2, #24]
|
|
80010a4: 4b15 ldr r3, [pc, #84] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
80010a6: 699b ldr r3, [r3, #24]
|
|
80010a8: f003 0304 and.w r3, r3, #4
|
|
80010ac: 613b str r3, [r7, #16]
|
|
80010ae: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80010b0: 4b12 ldr r3, [pc, #72] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
80010b2: 699b ldr r3, [r3, #24]
|
|
80010b4: 4a11 ldr r2, [pc, #68] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
80010b6: f043 0308 orr.w r3, r3, #8
|
|
80010ba: 6193 str r3, [r2, #24]
|
|
80010bc: 4b0f ldr r3, [pc, #60] @ (80010fc <HAL_ADC_MspInit+0x9c>)
|
|
80010be: 699b ldr r3, [r3, #24]
|
|
80010c0: f003 0308 and.w r3, r3, #8
|
|
80010c4: 60fb str r3, [r7, #12]
|
|
80010c6: 68fb ldr r3, [r7, #12]
|
|
PA5 ------> ADC1_IN5
|
|
PA6 ------> ADC1_IN6
|
|
PA7 ------> ADC1_IN7
|
|
PB0 ------> ADC1_IN8
|
|
*/
|
|
GPIO_InitStruct.Pin = AIN1_Pin|AIN2_Pin|AIN3_Pin|AIN4_Pin;
|
|
80010c8: 23f0 movs r3, #240 @ 0xf0
|
|
80010ca: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80010cc: 2303 movs r3, #3
|
|
80010ce: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80010d0: f107 0318 add.w r3, r7, #24
|
|
80010d4: 4619 mov r1, r3
|
|
80010d6: 480a ldr r0, [pc, #40] @ (8001100 <HAL_ADC_MspInit+0xa0>)
|
|
80010d8: f000 fd08 bl 8001aec <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = ANEM_Pin;
|
|
80010dc: 2301 movs r3, #1
|
|
80010de: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80010e0: 2303 movs r3, #3
|
|
80010e2: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(ANEM_GPIO_Port, &GPIO_InitStruct);
|
|
80010e4: f107 0318 add.w r3, r7, #24
|
|
80010e8: 4619 mov r1, r3
|
|
80010ea: 4806 ldr r0, [pc, #24] @ (8001104 <HAL_ADC_MspInit+0xa4>)
|
|
80010ec: f000 fcfe bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END ADC1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80010f0: bf00 nop
|
|
80010f2: 3728 adds r7, #40 @ 0x28
|
|
80010f4: 46bd mov sp, r7
|
|
80010f6: bd80 pop {r7, pc}
|
|
80010f8: 40012400 .word 0x40012400
|
|
80010fc: 40021000 .word 0x40021000
|
|
8001100: 40010800 .word 0x40010800
|
|
8001104: 40010c00 .word 0x40010c00
|
|
|
|
08001108 <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
8001108: b480 push {r7}
|
|
800110a: b085 sub sp, #20
|
|
800110c: af00 add r7, sp, #0
|
|
800110e: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM2)
|
|
8001110: 687b ldr r3, [r7, #4]
|
|
8001112: 681b ldr r3, [r3, #0]
|
|
8001114: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8001118: d10c bne.n 8001134 <HAL_TIM_Base_MspInit+0x2c>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
800111a: 4b11 ldr r3, [pc, #68] @ (8001160 <HAL_TIM_Base_MspInit+0x58>)
|
|
800111c: 69db ldr r3, [r3, #28]
|
|
800111e: 4a10 ldr r2, [pc, #64] @ (8001160 <HAL_TIM_Base_MspInit+0x58>)
|
|
8001120: f043 0301 orr.w r3, r3, #1
|
|
8001124: 61d3 str r3, [r2, #28]
|
|
8001126: 4b0e ldr r3, [pc, #56] @ (8001160 <HAL_TIM_Base_MspInit+0x58>)
|
|
8001128: 69db ldr r3, [r3, #28]
|
|
800112a: f003 0301 and.w r3, r3, #1
|
|
800112e: 60fb str r3, [r7, #12]
|
|
8001130: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN TIM4_MspInit 1 */
|
|
|
|
/* USER CODE END TIM4_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001132: e010 b.n 8001156 <HAL_TIM_Base_MspInit+0x4e>
|
|
else if(htim_base->Instance==TIM4)
|
|
8001134: 687b ldr r3, [r7, #4]
|
|
8001136: 681b ldr r3, [r3, #0]
|
|
8001138: 4a0a ldr r2, [pc, #40] @ (8001164 <HAL_TIM_Base_MspInit+0x5c>)
|
|
800113a: 4293 cmp r3, r2
|
|
800113c: d10b bne.n 8001156 <HAL_TIM_Base_MspInit+0x4e>
|
|
__HAL_RCC_TIM4_CLK_ENABLE();
|
|
800113e: 4b08 ldr r3, [pc, #32] @ (8001160 <HAL_TIM_Base_MspInit+0x58>)
|
|
8001140: 69db ldr r3, [r3, #28]
|
|
8001142: 4a07 ldr r2, [pc, #28] @ (8001160 <HAL_TIM_Base_MspInit+0x58>)
|
|
8001144: f043 0304 orr.w r3, r3, #4
|
|
8001148: 61d3 str r3, [r2, #28]
|
|
800114a: 4b05 ldr r3, [pc, #20] @ (8001160 <HAL_TIM_Base_MspInit+0x58>)
|
|
800114c: 69db ldr r3, [r3, #28]
|
|
800114e: f003 0304 and.w r3, r3, #4
|
|
8001152: 60bb str r3, [r7, #8]
|
|
8001154: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8001156: bf00 nop
|
|
8001158: 3714 adds r7, #20
|
|
800115a: 46bd mov sp, r7
|
|
800115c: bc80 pop {r7}
|
|
800115e: 4770 bx lr
|
|
8001160: 40021000 .word 0x40021000
|
|
8001164: 40000800 .word 0x40000800
|
|
|
|
08001168 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8001168: b580 push {r7, lr}
|
|
800116a: b088 sub sp, #32
|
|
800116c: af00 add r7, sp, #0
|
|
800116e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001170: f107 0310 add.w r3, r7, #16
|
|
8001174: 2200 movs r2, #0
|
|
8001176: 601a str r2, [r3, #0]
|
|
8001178: 605a str r2, [r3, #4]
|
|
800117a: 609a str r2, [r3, #8]
|
|
800117c: 60da str r2, [r3, #12]
|
|
if(htim->Instance==TIM2)
|
|
800117e: 687b ldr r3, [r7, #4]
|
|
8001180: 681b ldr r3, [r3, #0]
|
|
8001182: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8001186: d118 bne.n 80011ba <HAL_TIM_MspPostInit+0x52>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001188: 4b1d ldr r3, [pc, #116] @ (8001200 <HAL_TIM_MspPostInit+0x98>)
|
|
800118a: 699b ldr r3, [r3, #24]
|
|
800118c: 4a1c ldr r2, [pc, #112] @ (8001200 <HAL_TIM_MspPostInit+0x98>)
|
|
800118e: f043 0304 orr.w r3, r3, #4
|
|
8001192: 6193 str r3, [r2, #24]
|
|
8001194: 4b1a ldr r3, [pc, #104] @ (8001200 <HAL_TIM_MspPostInit+0x98>)
|
|
8001196: 699b ldr r3, [r3, #24]
|
|
8001198: f003 0304 and.w r3, r3, #4
|
|
800119c: 60fb str r3, [r7, #12]
|
|
800119e: 68fb ldr r3, [r7, #12]
|
|
PA0-WKUP ------> TIM2_CH1
|
|
PA1 ------> TIM2_CH2
|
|
PA2 ------> TIM2_CH3
|
|
PA3 ------> TIM2_CH4
|
|
*/
|
|
GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|IN3_Pin|IN4_Pin;
|
|
80011a0: 230f movs r3, #15
|
|
80011a2: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011a4: 2302 movs r3, #2
|
|
80011a6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80011a8: 2302 movs r3, #2
|
|
80011aa: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80011ac: f107 0310 add.w r3, r7, #16
|
|
80011b0: 4619 mov r1, r3
|
|
80011b2: 4814 ldr r0, [pc, #80] @ (8001204 <HAL_TIM_MspPostInit+0x9c>)
|
|
80011b4: f000 fc9a bl 8001aec <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM4_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM4_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80011b8: e01d b.n 80011f6 <HAL_TIM_MspPostInit+0x8e>
|
|
else if(htim->Instance==TIM4)
|
|
80011ba: 687b ldr r3, [r7, #4]
|
|
80011bc: 681b ldr r3, [r3, #0]
|
|
80011be: 4a12 ldr r2, [pc, #72] @ (8001208 <HAL_TIM_MspPostInit+0xa0>)
|
|
80011c0: 4293 cmp r3, r2
|
|
80011c2: d118 bne.n 80011f6 <HAL_TIM_MspPostInit+0x8e>
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80011c4: 4b0e ldr r3, [pc, #56] @ (8001200 <HAL_TIM_MspPostInit+0x98>)
|
|
80011c6: 699b ldr r3, [r3, #24]
|
|
80011c8: 4a0d ldr r2, [pc, #52] @ (8001200 <HAL_TIM_MspPostInit+0x98>)
|
|
80011ca: f043 0308 orr.w r3, r3, #8
|
|
80011ce: 6193 str r3, [r2, #24]
|
|
80011d0: 4b0b ldr r3, [pc, #44] @ (8001200 <HAL_TIM_MspPostInit+0x98>)
|
|
80011d2: 699b ldr r3, [r3, #24]
|
|
80011d4: f003 0308 and.w r3, r3, #8
|
|
80011d8: 60bb str r3, [r7, #8]
|
|
80011da: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = IN5_Pin|IN6_Pin|IN7_Pin|IN8_Pin;
|
|
80011dc: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
80011e0: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011e2: 2302 movs r3, #2
|
|
80011e4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80011e6: 2302 movs r3, #2
|
|
80011e8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80011ea: f107 0310 add.w r3, r7, #16
|
|
80011ee: 4619 mov r1, r3
|
|
80011f0: 4806 ldr r0, [pc, #24] @ (800120c <HAL_TIM_MspPostInit+0xa4>)
|
|
80011f2: f000 fc7b bl 8001aec <HAL_GPIO_Init>
|
|
}
|
|
80011f6: bf00 nop
|
|
80011f8: 3720 adds r7, #32
|
|
80011fa: 46bd mov sp, r7
|
|
80011fc: bd80 pop {r7, pc}
|
|
80011fe: bf00 nop
|
|
8001200: 40021000 .word 0x40021000
|
|
8001204: 40010800 .word 0x40010800
|
|
8001208: 40000800 .word 0x40000800
|
|
800120c: 40010c00 .word 0x40010c00
|
|
|
|
08001210 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8001210: b580 push {r7, lr}
|
|
8001212: b088 sub sp, #32
|
|
8001214: af00 add r7, sp, #0
|
|
8001216: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001218: f107 0310 add.w r3, r7, #16
|
|
800121c: 2200 movs r2, #0
|
|
800121e: 601a str r2, [r3, #0]
|
|
8001220: 605a str r2, [r3, #4]
|
|
8001222: 609a str r2, [r3, #8]
|
|
8001224: 60da str r2, [r3, #12]
|
|
if(huart->Instance==USART1)
|
|
8001226: 687b ldr r3, [r7, #4]
|
|
8001228: 681b ldr r3, [r3, #0]
|
|
800122a: 4a1c ldr r2, [pc, #112] @ (800129c <HAL_UART_MspInit+0x8c>)
|
|
800122c: 4293 cmp r3, r2
|
|
800122e: d131 bne.n 8001294 <HAL_UART_MspInit+0x84>
|
|
{
|
|
/* USER CODE BEGIN USART1_MspInit 0 */
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8001230: 4b1b ldr r3, [pc, #108] @ (80012a0 <HAL_UART_MspInit+0x90>)
|
|
8001232: 699b ldr r3, [r3, #24]
|
|
8001234: 4a1a ldr r2, [pc, #104] @ (80012a0 <HAL_UART_MspInit+0x90>)
|
|
8001236: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800123a: 6193 str r3, [r2, #24]
|
|
800123c: 4b18 ldr r3, [pc, #96] @ (80012a0 <HAL_UART_MspInit+0x90>)
|
|
800123e: 699b ldr r3, [r3, #24]
|
|
8001240: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001244: 60fb str r3, [r7, #12]
|
|
8001246: 68fb ldr r3, [r7, #12]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001248: 4b15 ldr r3, [pc, #84] @ (80012a0 <HAL_UART_MspInit+0x90>)
|
|
800124a: 699b ldr r3, [r3, #24]
|
|
800124c: 4a14 ldr r2, [pc, #80] @ (80012a0 <HAL_UART_MspInit+0x90>)
|
|
800124e: f043 0304 orr.w r3, r3, #4
|
|
8001252: 6193 str r3, [r2, #24]
|
|
8001254: 4b12 ldr r3, [pc, #72] @ (80012a0 <HAL_UART_MspInit+0x90>)
|
|
8001256: 699b ldr r3, [r3, #24]
|
|
8001258: f003 0304 and.w r3, r3, #4
|
|
800125c: 60bb str r3, [r7, #8]
|
|
800125e: 68bb ldr r3, [r7, #8]
|
|
/**USART1 GPIO Configuration
|
|
PA9 ------> USART1_TX
|
|
PA10 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9;
|
|
8001260: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8001264: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001266: 2302 movs r3, #2
|
|
8001268: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
800126a: 2303 movs r3, #3
|
|
800126c: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800126e: f107 0310 add.w r3, r7, #16
|
|
8001272: 4619 mov r1, r3
|
|
8001274: 480b ldr r0, [pc, #44] @ (80012a4 <HAL_UART_MspInit+0x94>)
|
|
8001276: f000 fc39 bl 8001aec <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10;
|
|
800127a: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
800127e: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001280: 2300 movs r3, #0
|
|
8001282: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001284: 2300 movs r3, #0
|
|
8001286: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001288: f107 0310 add.w r3, r7, #16
|
|
800128c: 4619 mov r1, r3
|
|
800128e: 4805 ldr r0, [pc, #20] @ (80012a4 <HAL_UART_MspInit+0x94>)
|
|
8001290: f000 fc2c bl 8001aec <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001294: bf00 nop
|
|
8001296: 3720 adds r7, #32
|
|
8001298: 46bd mov sp, r7
|
|
800129a: bd80 pop {r7, pc}
|
|
800129c: 40013800 .word 0x40013800
|
|
80012a0: 40021000 .word 0x40021000
|
|
80012a4: 40010800 .word 0x40010800
|
|
|
|
080012a8 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80012a8: b480 push {r7}
|
|
80012aa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80012ac: bf00 nop
|
|
80012ae: e7fd b.n 80012ac <NMI_Handler+0x4>
|
|
|
|
080012b0 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80012b0: b480 push {r7}
|
|
80012b2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80012b4: bf00 nop
|
|
80012b6: e7fd b.n 80012b4 <HardFault_Handler+0x4>
|
|
|
|
080012b8 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80012b8: b480 push {r7}
|
|
80012ba: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80012bc: bf00 nop
|
|
80012be: e7fd b.n 80012bc <MemManage_Handler+0x4>
|
|
|
|
080012c0 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
80012c0: b480 push {r7}
|
|
80012c2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
80012c4: bf00 nop
|
|
80012c6: e7fd b.n 80012c4 <BusFault_Handler+0x4>
|
|
|
|
080012c8 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
80012c8: b480 push {r7}
|
|
80012ca: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
80012cc: bf00 nop
|
|
80012ce: e7fd b.n 80012cc <UsageFault_Handler+0x4>
|
|
|
|
080012d0 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
80012d0: b480 push {r7}
|
|
80012d2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
80012d4: bf00 nop
|
|
80012d6: 46bd mov sp, r7
|
|
80012d8: bc80 pop {r7}
|
|
80012da: 4770 bx lr
|
|
|
|
080012dc <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
80012dc: b480 push {r7}
|
|
80012de: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
80012e0: bf00 nop
|
|
80012e2: 46bd mov sp, r7
|
|
80012e4: bc80 pop {r7}
|
|
80012e6: 4770 bx lr
|
|
|
|
080012e8 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
80012e8: b480 push {r7}
|
|
80012ea: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
80012ec: bf00 nop
|
|
80012ee: 46bd mov sp, r7
|
|
80012f0: bc80 pop {r7}
|
|
80012f2: 4770 bx lr
|
|
|
|
080012f4 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
80012f4: b580 push {r7, lr}
|
|
80012f6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
80012f8: f000 f8b6 bl 8001468 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
HAL_SYSTICK_IRQHandler();
|
|
80012fc: f000 fbef bl 8001ade <HAL_SYSTICK_IRQHandler>
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8001300: bf00 nop
|
|
8001302: bd80 pop {r7, pc}
|
|
|
|
08001304 <USB_LP_CAN1_RX0_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB low priority or CAN RX0 interrupts.
|
|
*/
|
|
void USB_LP_CAN1_RX0_IRQHandler(void)
|
|
{
|
|
8001304: b580 push {r7, lr}
|
|
8001306: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
|
|
|
|
/* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_FS);
|
|
8001308: 4802 ldr r0, [pc, #8] @ (8001314 <USB_LP_CAN1_RX0_IRQHandler+0x10>)
|
|
800130a: f000 fec0 bl 800208e <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
|
|
|
|
/* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
|
|
}
|
|
800130e: bf00 nop
|
|
8001310: bd80 pop {r7, pc}
|
|
8001312: bf00 nop
|
|
8001314: 20001178 .word 0x20001178
|
|
|
|
08001318 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
8001318: b580 push {r7, lr}
|
|
800131a: b086 sub sp, #24
|
|
800131c: af00 add r7, sp, #0
|
|
800131e: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8001320: 4a14 ldr r2, [pc, #80] @ (8001374 <_sbrk+0x5c>)
|
|
8001322: 4b15 ldr r3, [pc, #84] @ (8001378 <_sbrk+0x60>)
|
|
8001324: 1ad3 subs r3, r2, r3
|
|
8001326: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
8001328: 697b ldr r3, [r7, #20]
|
|
800132a: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
800132c: 4b13 ldr r3, [pc, #76] @ (800137c <_sbrk+0x64>)
|
|
800132e: 681b ldr r3, [r3, #0]
|
|
8001330: 2b00 cmp r3, #0
|
|
8001332: d102 bne.n 800133a <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
8001334: 4b11 ldr r3, [pc, #68] @ (800137c <_sbrk+0x64>)
|
|
8001336: 4a12 ldr r2, [pc, #72] @ (8001380 <_sbrk+0x68>)
|
|
8001338: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
800133a: 4b10 ldr r3, [pc, #64] @ (800137c <_sbrk+0x64>)
|
|
800133c: 681a ldr r2, [r3, #0]
|
|
800133e: 687b ldr r3, [r7, #4]
|
|
8001340: 4413 add r3, r2
|
|
8001342: 693a ldr r2, [r7, #16]
|
|
8001344: 429a cmp r2, r3
|
|
8001346: d207 bcs.n 8001358 <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
8001348: f008 fb3e bl 80099c8 <__errno>
|
|
800134c: 4603 mov r3, r0
|
|
800134e: 220c movs r2, #12
|
|
8001350: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
8001352: f04f 33ff mov.w r3, #4294967295
|
|
8001356: e009 b.n 800136c <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
8001358: 4b08 ldr r3, [pc, #32] @ (800137c <_sbrk+0x64>)
|
|
800135a: 681b ldr r3, [r3, #0]
|
|
800135c: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
800135e: 4b07 ldr r3, [pc, #28] @ (800137c <_sbrk+0x64>)
|
|
8001360: 681a ldr r2, [r3, #0]
|
|
8001362: 687b ldr r3, [r7, #4]
|
|
8001364: 4413 add r3, r2
|
|
8001366: 4a05 ldr r2, [pc, #20] @ (800137c <_sbrk+0x64>)
|
|
8001368: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
800136a: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800136c: 4618 mov r0, r3
|
|
800136e: 3718 adds r7, #24
|
|
8001370: 46bd mov sp, r7
|
|
8001372: bd80 pop {r7, pc}
|
|
8001374: 20005000 .word 0x20005000
|
|
8001378: 00000400 .word 0x00000400
|
|
800137c: 200003a4 .word 0x200003a4
|
|
8001380: 200017b8 .word 0x200017b8
|
|
|
|
08001384 <SystemInit>:
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit (void)
|
|
{
|
|
8001384: b480 push {r7}
|
|
8001386: af00 add r7, sp, #0
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8001388: bf00 nop
|
|
800138a: 46bd mov sp, r7
|
|
800138c: bc80 pop {r7}
|
|
800138e: 4770 bx lr
|
|
|
|
08001390 <Reset_Handler>:
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001390: f7ff fff8 bl 8001384 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001394: 480b ldr r0, [pc, #44] @ (80013c4 <LoopFillZerobss+0xe>)
|
|
ldr r1, =_edata
|
|
8001396: 490c ldr r1, [pc, #48] @ (80013c8 <LoopFillZerobss+0x12>)
|
|
ldr r2, =_sidata
|
|
8001398: 4a0c ldr r2, [pc, #48] @ (80013cc <LoopFillZerobss+0x16>)
|
|
movs r3, #0
|
|
800139a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800139c: e002 b.n 80013a4 <LoopCopyDataInit>
|
|
|
|
0800139e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800139e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
80013a0: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
80013a2: 3304 adds r3, #4
|
|
|
|
080013a4 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
80013a4: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
80013a6: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
80013a8: d3f9 bcc.n 800139e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
80013aa: 4a09 ldr r2, [pc, #36] @ (80013d0 <LoopFillZerobss+0x1a>)
|
|
ldr r4, =_ebss
|
|
80013ac: 4c09 ldr r4, [pc, #36] @ (80013d4 <LoopFillZerobss+0x1e>)
|
|
movs r3, #0
|
|
80013ae: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
80013b0: e001 b.n 80013b6 <LoopFillZerobss>
|
|
|
|
080013b2 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
80013b2: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
80013b4: 3204 adds r2, #4
|
|
|
|
080013b6 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
80013b6: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
80013b8: d3fb bcc.n 80013b2 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80013ba: f008 fb0b bl 80099d4 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
80013be: f7ff f939 bl 8000634 <main>
|
|
bx lr
|
|
80013c2: 4770 bx lr
|
|
ldr r0, =_sdata
|
|
80013c4: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80013c8: 200001cc .word 0x200001cc
|
|
ldr r2, =_sidata
|
|
80013cc: 0800a458 .word 0x0800a458
|
|
ldr r2, =_sbss
|
|
80013d0: 200001cc .word 0x200001cc
|
|
ldr r4, =_ebss
|
|
80013d4: 200017b8 .word 0x200017b8
|
|
|
|
080013d8 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80013d8: e7fe b.n 80013d8 <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
080013dc <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80013dc: b580 push {r7, lr}
|
|
80013de: af00 add r7, sp, #0
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
80013e0: 4b08 ldr r3, [pc, #32] @ (8001404 <HAL_Init+0x28>)
|
|
80013e2: 681b ldr r3, [r3, #0]
|
|
80013e4: 4a07 ldr r2, [pc, #28] @ (8001404 <HAL_Init+0x28>)
|
|
80013e6: f043 0310 orr.w r3, r3, #16
|
|
80013ea: 6013 str r3, [r2, #0]
|
|
#endif
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80013ec: 2003 movs r0, #3
|
|
80013ee: f000 fb35 bl 8001a5c <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
80013f2: 200f movs r0, #15
|
|
80013f4: f000 f808 bl 8001408 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80013f8: f7ff fe00 bl 8000ffc <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80013fc: 2300 movs r3, #0
|
|
}
|
|
80013fe: 4618 mov r0, r3
|
|
8001400: bd80 pop {r7, pc}
|
|
8001402: bf00 nop
|
|
8001404: 40022000 .word 0x40022000
|
|
|
|
08001408 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001408: b580 push {r7, lr}
|
|
800140a: b082 sub sp, #8
|
|
800140c: af00 add r7, sp, #0
|
|
800140e: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8001410: 4b12 ldr r3, [pc, #72] @ (800145c <HAL_InitTick+0x54>)
|
|
8001412: 681a ldr r2, [r3, #0]
|
|
8001414: 4b12 ldr r3, [pc, #72] @ (8001460 <HAL_InitTick+0x58>)
|
|
8001416: 781b ldrb r3, [r3, #0]
|
|
8001418: 4619 mov r1, r3
|
|
800141a: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
800141e: fbb3 f3f1 udiv r3, r3, r1
|
|
8001422: fbb2 f3f3 udiv r3, r2, r3
|
|
8001426: 4618 mov r0, r3
|
|
8001428: f000 fb4d bl 8001ac6 <HAL_SYSTICK_Config>
|
|
800142c: 4603 mov r3, r0
|
|
800142e: 2b00 cmp r3, #0
|
|
8001430: d001 beq.n 8001436 <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
8001432: 2301 movs r3, #1
|
|
8001434: e00e b.n 8001454 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001436: 687b ldr r3, [r7, #4]
|
|
8001438: 2b0f cmp r3, #15
|
|
800143a: d80a bhi.n 8001452 <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
800143c: 2200 movs r2, #0
|
|
800143e: 6879 ldr r1, [r7, #4]
|
|
8001440: f04f 30ff mov.w r0, #4294967295
|
|
8001444: f000 fb15 bl 8001a72 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001448: 4a06 ldr r2, [pc, #24] @ (8001464 <HAL_InitTick+0x5c>)
|
|
800144a: 687b ldr r3, [r7, #4]
|
|
800144c: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800144e: 2300 movs r3, #0
|
|
8001450: e000 b.n 8001454 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
8001452: 2301 movs r3, #1
|
|
}
|
|
8001454: 4618 mov r0, r3
|
|
8001456: 3708 adds r7, #8
|
|
8001458: 46bd mov sp, r7
|
|
800145a: bd80 pop {r7, pc}
|
|
800145c: 20000000 .word 0x20000000
|
|
8001460: 20000008 .word 0x20000008
|
|
8001464: 20000004 .word 0x20000004
|
|
|
|
08001468 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8001468: b480 push {r7}
|
|
800146a: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
800146c: 4b05 ldr r3, [pc, #20] @ (8001484 <HAL_IncTick+0x1c>)
|
|
800146e: 781b ldrb r3, [r3, #0]
|
|
8001470: 461a mov r2, r3
|
|
8001472: 4b05 ldr r3, [pc, #20] @ (8001488 <HAL_IncTick+0x20>)
|
|
8001474: 681b ldr r3, [r3, #0]
|
|
8001476: 4413 add r3, r2
|
|
8001478: 4a03 ldr r2, [pc, #12] @ (8001488 <HAL_IncTick+0x20>)
|
|
800147a: 6013 str r3, [r2, #0]
|
|
}
|
|
800147c: bf00 nop
|
|
800147e: 46bd mov sp, r7
|
|
8001480: bc80 pop {r7}
|
|
8001482: 4770 bx lr
|
|
8001484: 20000008 .word 0x20000008
|
|
8001488: 200003a8 .word 0x200003a8
|
|
|
|
0800148c <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
800148c: b480 push {r7}
|
|
800148e: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8001490: 4b02 ldr r3, [pc, #8] @ (800149c <HAL_GetTick+0x10>)
|
|
8001492: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001494: 4618 mov r0, r3
|
|
8001496: 46bd mov sp, r7
|
|
8001498: bc80 pop {r7}
|
|
800149a: 4770 bx lr
|
|
800149c: 200003a8 .word 0x200003a8
|
|
|
|
080014a0 <HAL_ADC_Init>:
|
|
* of structure "ADC_InitTypeDef".
|
|
* @param hadc: ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
|
{
|
|
80014a0: b580 push {r7, lr}
|
|
80014a2: b086 sub sp, #24
|
|
80014a4: af00 add r7, sp, #0
|
|
80014a6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
80014a8: 2300 movs r3, #0
|
|
80014aa: 75fb strb r3, [r7, #23]
|
|
uint32_t tmp_cr1 = 0U;
|
|
80014ac: 2300 movs r3, #0
|
|
80014ae: 613b str r3, [r7, #16]
|
|
uint32_t tmp_cr2 = 0U;
|
|
80014b0: 2300 movs r3, #0
|
|
80014b2: 60bb str r3, [r7, #8]
|
|
uint32_t tmp_sqr1 = 0U;
|
|
80014b4: 2300 movs r3, #0
|
|
80014b6: 60fb str r3, [r7, #12]
|
|
|
|
/* Check ADC handle */
|
|
if(hadc == NULL)
|
|
80014b8: 687b ldr r3, [r7, #4]
|
|
80014ba: 2b00 cmp r3, #0
|
|
80014bc: d101 bne.n 80014c2 <HAL_ADC_Init+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80014be: 2301 movs r3, #1
|
|
80014c0: e0be b.n 8001640 <HAL_ADC_Init+0x1a0>
|
|
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
|
|
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
|
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
|
|
|
|
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
|
80014c2: 687b ldr r3, [r7, #4]
|
|
80014c4: 689b ldr r3, [r3, #8]
|
|
80014c6: 2b00 cmp r3, #0
|
|
/* Refer to header of this file for more details on clock enabling */
|
|
/* procedure. */
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
80014c8: 687b ldr r3, [r7, #4]
|
|
80014ca: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80014cc: 2b00 cmp r3, #0
|
|
80014ce: d109 bne.n 80014e4 <HAL_ADC_Init+0x44>
|
|
{
|
|
/* Initialize ADC error code */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
80014d0: 687b ldr r3, [r7, #4]
|
|
80014d2: 2200 movs r2, #0
|
|
80014d4: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
80014d6: 687b ldr r3, [r7, #4]
|
|
80014d8: 2200 movs r2, #0
|
|
80014da: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
80014de: 6878 ldr r0, [r7, #4]
|
|
80014e0: f7ff fdbe bl 8001060 <HAL_ADC_MspInit>
|
|
/* Stop potential conversion on going, on regular and injected groups */
|
|
/* Disable ADC peripheral */
|
|
/* Note: In case of ADC already enabled, precaution to not launch an */
|
|
/* unwanted conversion while modifying register CR2 by writing 1 to */
|
|
/* bit ADON. */
|
|
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
|
|
80014e4: 6878 ldr r0, [r7, #4]
|
|
80014e6: f000 f9ab bl 8001840 <ADC_ConversionStop_Disable>
|
|
80014ea: 4603 mov r3, r0
|
|
80014ec: 75fb strb r3, [r7, #23]
|
|
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed. */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
|
|
80014ee: 687b ldr r3, [r7, #4]
|
|
80014f0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80014f2: f003 0310 and.w r3, r3, #16
|
|
80014f6: 2b00 cmp r3, #0
|
|
80014f8: f040 8099 bne.w 800162e <HAL_ADC_Init+0x18e>
|
|
80014fc: 7dfb ldrb r3, [r7, #23]
|
|
80014fe: 2b00 cmp r3, #0
|
|
8001500: f040 8095 bne.w 800162e <HAL_ADC_Init+0x18e>
|
|
(tmp_hal_status == HAL_OK) )
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8001504: 687b ldr r3, [r7, #4]
|
|
8001506: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001508: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
800150c: f023 0302 bic.w r3, r3, #2
|
|
8001510: f043 0202 orr.w r2, r3, #2
|
|
8001514: 687b ldr r3, [r7, #4]
|
|
8001516: 629a str r2, [r3, #40] @ 0x28
|
|
/* - continuous conversion mode */
|
|
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
|
|
/* HAL_ADC_Start_xxx functions because if set in this function, */
|
|
/* a conversion on injected group would start a conversion also on */
|
|
/* regular group after ADC enabling. */
|
|
tmp_cr2 |= (hadc->Init.DataAlign |
|
|
8001518: 687b ldr r3, [r7, #4]
|
|
800151a: 685a ldr r2, [r3, #4]
|
|
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
|
|
800151c: 687b ldr r3, [r7, #4]
|
|
800151e: 69db ldr r3, [r3, #28]
|
|
tmp_cr2 |= (hadc->Init.DataAlign |
|
|
8001520: 431a orrs r2, r3
|
|
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
|
|
8001522: 687b ldr r3, [r7, #4]
|
|
8001524: 7b1b ldrb r3, [r3, #12]
|
|
8001526: 005b lsls r3, r3, #1
|
|
ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
|
|
8001528: 4313 orrs r3, r2
|
|
tmp_cr2 |= (hadc->Init.DataAlign |
|
|
800152a: 68ba ldr r2, [r7, #8]
|
|
800152c: 4313 orrs r3, r2
|
|
800152e: 60bb str r3, [r7, #8]
|
|
|
|
/* Configuration of ADC: */
|
|
/* - scan mode */
|
|
/* - discontinuous mode disable/enable */
|
|
/* - discontinuous mode number of conversions */
|
|
tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
|
|
8001530: 687b ldr r3, [r7, #4]
|
|
8001532: 689b ldr r3, [r3, #8]
|
|
8001534: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8001538: d003 beq.n 8001542 <HAL_ADC_Init+0xa2>
|
|
800153a: 687b ldr r3, [r7, #4]
|
|
800153c: 689b ldr r3, [r3, #8]
|
|
800153e: 2b01 cmp r3, #1
|
|
8001540: d102 bne.n 8001548 <HAL_ADC_Init+0xa8>
|
|
8001542: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8001546: e000 b.n 800154a <HAL_ADC_Init+0xaa>
|
|
8001548: 2300 movs r3, #0
|
|
800154a: 693a ldr r2, [r7, #16]
|
|
800154c: 4313 orrs r3, r2
|
|
800154e: 613b str r3, [r7, #16]
|
|
|
|
/* Enable discontinuous mode only if continuous mode is disabled */
|
|
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
|
|
/* discontinuous is set anyway, but will have no effect on ADC HW. */
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
8001550: 687b ldr r3, [r7, #4]
|
|
8001552: 7d1b ldrb r3, [r3, #20]
|
|
8001554: 2b01 cmp r3, #1
|
|
8001556: d119 bne.n 800158c <HAL_ADC_Init+0xec>
|
|
{
|
|
if (hadc->Init.ContinuousConvMode == DISABLE)
|
|
8001558: 687b ldr r3, [r7, #4]
|
|
800155a: 7b1b ldrb r3, [r3, #12]
|
|
800155c: 2b00 cmp r3, #0
|
|
800155e: d109 bne.n 8001574 <HAL_ADC_Init+0xd4>
|
|
{
|
|
/* Enable the selected ADC regular discontinuous mode */
|
|
/* Set the number of channels to be converted in discontinuous mode */
|
|
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
|
|
8001560: 687b ldr r3, [r7, #4]
|
|
8001562: 699b ldr r3, [r3, #24]
|
|
8001564: 3b01 subs r3, #1
|
|
8001566: 035a lsls r2, r3, #13
|
|
8001568: 693b ldr r3, [r7, #16]
|
|
800156a: 4313 orrs r3, r2
|
|
800156c: f443 6300 orr.w r3, r3, #2048 @ 0x800
|
|
8001570: 613b str r3, [r7, #16]
|
|
8001572: e00b b.n 800158c <HAL_ADC_Init+0xec>
|
|
{
|
|
/* ADC regular group settings continuous and sequencer discontinuous*/
|
|
/* cannot be enabled simultaneously. */
|
|
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8001574: 687b ldr r3, [r7, #4]
|
|
8001576: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001578: f043 0220 orr.w r2, r3, #32
|
|
800157c: 687b ldr r3, [r7, #4]
|
|
800157e: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8001580: 687b ldr r3, [r7, #4]
|
|
8001582: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8001584: f043 0201 orr.w r2, r3, #1
|
|
8001588: 687b ldr r3, [r7, #4]
|
|
800158a: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
}
|
|
|
|
/* Update ADC configuration register CR1 with previous settings */
|
|
MODIFY_REG(hadc->Instance->CR1,
|
|
800158c: 687b ldr r3, [r7, #4]
|
|
800158e: 681b ldr r3, [r3, #0]
|
|
8001590: 685b ldr r3, [r3, #4]
|
|
8001592: f423 4169 bic.w r1, r3, #59648 @ 0xe900
|
|
8001596: 687b ldr r3, [r7, #4]
|
|
8001598: 681b ldr r3, [r3, #0]
|
|
800159a: 693a ldr r2, [r7, #16]
|
|
800159c: 430a orrs r2, r1
|
|
800159e: 605a str r2, [r3, #4]
|
|
ADC_CR1_DISCEN |
|
|
ADC_CR1_DISCNUM ,
|
|
tmp_cr1 );
|
|
|
|
/* Update ADC configuration register CR2 with previous settings */
|
|
MODIFY_REG(hadc->Instance->CR2,
|
|
80015a0: 687b ldr r3, [r7, #4]
|
|
80015a2: 681b ldr r3, [r3, #0]
|
|
80015a4: 689a ldr r2, [r3, #8]
|
|
80015a6: 4b28 ldr r3, [pc, #160] @ (8001648 <HAL_ADC_Init+0x1a8>)
|
|
80015a8: 4013 ands r3, r2
|
|
80015aa: 687a ldr r2, [r7, #4]
|
|
80015ac: 6812 ldr r2, [r2, #0]
|
|
80015ae: 68b9 ldr r1, [r7, #8]
|
|
80015b0: 430b orrs r3, r1
|
|
80015b2: 6093 str r3, [r2, #8]
|
|
/* Note: Scan mode is present by hardware on this device and, if */
|
|
/* disabled, discards automatically nb of conversions. Anyway, nb of */
|
|
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
|
|
/* - if scan mode is enabled, regular channels sequence length is set to */
|
|
/* parameter "NbrOfConversion" */
|
|
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
|
|
80015b4: 687b ldr r3, [r7, #4]
|
|
80015b6: 689b ldr r3, [r3, #8]
|
|
80015b8: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80015bc: d003 beq.n 80015c6 <HAL_ADC_Init+0x126>
|
|
80015be: 687b ldr r3, [r7, #4]
|
|
80015c0: 689b ldr r3, [r3, #8]
|
|
80015c2: 2b01 cmp r3, #1
|
|
80015c4: d104 bne.n 80015d0 <HAL_ADC_Init+0x130>
|
|
{
|
|
tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
|
|
80015c6: 687b ldr r3, [r7, #4]
|
|
80015c8: 691b ldr r3, [r3, #16]
|
|
80015ca: 3b01 subs r3, #1
|
|
80015cc: 051b lsls r3, r3, #20
|
|
80015ce: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
MODIFY_REG(hadc->Instance->SQR1,
|
|
80015d0: 687b ldr r3, [r7, #4]
|
|
80015d2: 681b ldr r3, [r3, #0]
|
|
80015d4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80015d6: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000
|
|
80015da: 687b ldr r3, [r7, #4]
|
|
80015dc: 681b ldr r3, [r3, #0]
|
|
80015de: 68fa ldr r2, [r7, #12]
|
|
80015e0: 430a orrs r2, r1
|
|
80015e2: 62da str r2, [r3, #44] @ 0x2c
|
|
/* ensure of no potential problem of ADC core IP clocking. */
|
|
/* Check through register CR2 (excluding bits set in other functions: */
|
|
/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
|
|
/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
|
|
/* measurement path bit (TSVREFE). */
|
|
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
|
|
80015e4: 687b ldr r3, [r7, #4]
|
|
80015e6: 681b ldr r3, [r3, #0]
|
|
80015e8: 689a ldr r2, [r3, #8]
|
|
80015ea: 4b18 ldr r3, [pc, #96] @ (800164c <HAL_ADC_Init+0x1ac>)
|
|
80015ec: 4013 ands r3, r2
|
|
80015ee: 68ba ldr r2, [r7, #8]
|
|
80015f0: 429a cmp r2, r3
|
|
80015f2: d10b bne.n 800160c <HAL_ADC_Init+0x16c>
|
|
ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
|
|
ADC_CR2_TSVREFE ))
|
|
== tmp_cr2)
|
|
{
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
80015f4: 687b ldr r3, [r7, #4]
|
|
80015f6: 2200 movs r2, #0
|
|
80015f8: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80015fa: 687b ldr r3, [r7, #4]
|
|
80015fc: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80015fe: f023 0303 bic.w r3, r3, #3
|
|
8001602: f043 0201 orr.w r2, r3, #1
|
|
8001606: 687b ldr r3, [r7, #4]
|
|
8001608: 629a str r2, [r3, #40] @ 0x28
|
|
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
|
|
800160a: e018 b.n 800163e <HAL_ADC_Init+0x19e>
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800160c: 687b ldr r3, [r7, #4]
|
|
800160e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001610: f023 0312 bic.w r3, r3, #18
|
|
8001614: f043 0210 orr.w r2, r3, #16
|
|
8001618: 687b ldr r3, [r7, #4]
|
|
800161a: 629a str r2, [r3, #40] @ 0x28
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800161c: 687b ldr r3, [r7, #4]
|
|
800161e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8001620: f043 0201 orr.w r2, r3, #1
|
|
8001624: 687b ldr r3, [r7, #4]
|
|
8001626: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8001628: 2301 movs r3, #1
|
|
800162a: 75fb strb r3, [r7, #23]
|
|
if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
|
|
800162c: e007 b.n 800163e <HAL_ADC_Init+0x19e>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
800162e: 687b ldr r3, [r7, #4]
|
|
8001630: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001632: f043 0210 orr.w r2, r3, #16
|
|
8001636: 687b ldr r3, [r7, #4]
|
|
8001638: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
800163a: 2301 movs r3, #1
|
|
800163c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
800163e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8001640: 4618 mov r0, r3
|
|
8001642: 3718 adds r7, #24
|
|
8001644: 46bd mov sp, r7
|
|
8001646: bd80 pop {r7, pc}
|
|
8001648: ffe1f7fd .word 0xffe1f7fd
|
|
800164c: ff1f0efe .word 0xff1f0efe
|
|
|
|
08001650 <HAL_ADC_ConfigChannel>:
|
|
* @param hadc: ADC handle
|
|
* @param sConfig: Structure of ADC channel for regular group.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
|
{
|
|
8001650: b480 push {r7}
|
|
8001652: b085 sub sp, #20
|
|
8001654: af00 add r7, sp, #0
|
|
8001656: 6078 str r0, [r7, #4]
|
|
8001658: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
800165a: 2300 movs r3, #0
|
|
800165c: 73fb strb r3, [r7, #15]
|
|
__IO uint32_t wait_loop_index = 0U;
|
|
800165e: 2300 movs r3, #0
|
|
8001660: 60bb str r3, [r7, #8]
|
|
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
|
|
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
|
|
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8001662: 687b ldr r3, [r7, #4]
|
|
8001664: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8001668: 2b01 cmp r3, #1
|
|
800166a: d101 bne.n 8001670 <HAL_ADC_ConfigChannel+0x20>
|
|
800166c: 2302 movs r3, #2
|
|
800166e: e0dc b.n 800182a <HAL_ADC_ConfigChannel+0x1da>
|
|
8001670: 687b ldr r3, [r7, #4]
|
|
8001672: 2201 movs r2, #1
|
|
8001674: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
|
|
/* Regular sequence configuration */
|
|
/* For Rank 1 to 6 */
|
|
if (sConfig->Rank < 7U)
|
|
8001678: 683b ldr r3, [r7, #0]
|
|
800167a: 685b ldr r3, [r3, #4]
|
|
800167c: 2b06 cmp r3, #6
|
|
800167e: d81c bhi.n 80016ba <HAL_ADC_ConfigChannel+0x6a>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR3 ,
|
|
8001680: 687b ldr r3, [r7, #4]
|
|
8001682: 681b ldr r3, [r3, #0]
|
|
8001684: 6b59 ldr r1, [r3, #52] @ 0x34
|
|
8001686: 683b ldr r3, [r7, #0]
|
|
8001688: 685a ldr r2, [r3, #4]
|
|
800168a: 4613 mov r3, r2
|
|
800168c: 009b lsls r3, r3, #2
|
|
800168e: 4413 add r3, r2
|
|
8001690: 3b05 subs r3, #5
|
|
8001692: 221f movs r2, #31
|
|
8001694: fa02 f303 lsl.w r3, r2, r3
|
|
8001698: 43db mvns r3, r3
|
|
800169a: 4019 ands r1, r3
|
|
800169c: 683b ldr r3, [r7, #0]
|
|
800169e: 6818 ldr r0, [r3, #0]
|
|
80016a0: 683b ldr r3, [r7, #0]
|
|
80016a2: 685a ldr r2, [r3, #4]
|
|
80016a4: 4613 mov r3, r2
|
|
80016a6: 009b lsls r3, r3, #2
|
|
80016a8: 4413 add r3, r2
|
|
80016aa: 3b05 subs r3, #5
|
|
80016ac: fa00 f203 lsl.w r2, r0, r3
|
|
80016b0: 687b ldr r3, [r7, #4]
|
|
80016b2: 681b ldr r3, [r3, #0]
|
|
80016b4: 430a orrs r2, r1
|
|
80016b6: 635a str r2, [r3, #52] @ 0x34
|
|
80016b8: e03c b.n 8001734 <HAL_ADC_ConfigChannel+0xe4>
|
|
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
|
|
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 7 to 12 */
|
|
else if (sConfig->Rank < 13U)
|
|
80016ba: 683b ldr r3, [r7, #0]
|
|
80016bc: 685b ldr r3, [r3, #4]
|
|
80016be: 2b0c cmp r3, #12
|
|
80016c0: d81c bhi.n 80016fc <HAL_ADC_ConfigChannel+0xac>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR2 ,
|
|
80016c2: 687b ldr r3, [r7, #4]
|
|
80016c4: 681b ldr r3, [r3, #0]
|
|
80016c6: 6b19 ldr r1, [r3, #48] @ 0x30
|
|
80016c8: 683b ldr r3, [r7, #0]
|
|
80016ca: 685a ldr r2, [r3, #4]
|
|
80016cc: 4613 mov r3, r2
|
|
80016ce: 009b lsls r3, r3, #2
|
|
80016d0: 4413 add r3, r2
|
|
80016d2: 3b23 subs r3, #35 @ 0x23
|
|
80016d4: 221f movs r2, #31
|
|
80016d6: fa02 f303 lsl.w r3, r2, r3
|
|
80016da: 43db mvns r3, r3
|
|
80016dc: 4019 ands r1, r3
|
|
80016de: 683b ldr r3, [r7, #0]
|
|
80016e0: 6818 ldr r0, [r3, #0]
|
|
80016e2: 683b ldr r3, [r7, #0]
|
|
80016e4: 685a ldr r2, [r3, #4]
|
|
80016e6: 4613 mov r3, r2
|
|
80016e8: 009b lsls r3, r3, #2
|
|
80016ea: 4413 add r3, r2
|
|
80016ec: 3b23 subs r3, #35 @ 0x23
|
|
80016ee: fa00 f203 lsl.w r2, r0, r3
|
|
80016f2: 687b ldr r3, [r7, #4]
|
|
80016f4: 681b ldr r3, [r3, #0]
|
|
80016f6: 430a orrs r2, r1
|
|
80016f8: 631a str r2, [r3, #48] @ 0x30
|
|
80016fa: e01b b.n 8001734 <HAL_ADC_ConfigChannel+0xe4>
|
|
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 13 to 16 */
|
|
else
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR1 ,
|
|
80016fc: 687b ldr r3, [r7, #4]
|
|
80016fe: 681b ldr r3, [r3, #0]
|
|
8001700: 6ad9 ldr r1, [r3, #44] @ 0x2c
|
|
8001702: 683b ldr r3, [r7, #0]
|
|
8001704: 685a ldr r2, [r3, #4]
|
|
8001706: 4613 mov r3, r2
|
|
8001708: 009b lsls r3, r3, #2
|
|
800170a: 4413 add r3, r2
|
|
800170c: 3b41 subs r3, #65 @ 0x41
|
|
800170e: 221f movs r2, #31
|
|
8001710: fa02 f303 lsl.w r3, r2, r3
|
|
8001714: 43db mvns r3, r3
|
|
8001716: 4019 ands r1, r3
|
|
8001718: 683b ldr r3, [r7, #0]
|
|
800171a: 6818 ldr r0, [r3, #0]
|
|
800171c: 683b ldr r3, [r7, #0]
|
|
800171e: 685a ldr r2, [r3, #4]
|
|
8001720: 4613 mov r3, r2
|
|
8001722: 009b lsls r3, r3, #2
|
|
8001724: 4413 add r3, r2
|
|
8001726: 3b41 subs r3, #65 @ 0x41
|
|
8001728: fa00 f203 lsl.w r2, r0, r3
|
|
800172c: 687b ldr r3, [r7, #4]
|
|
800172e: 681b ldr r3, [r3, #0]
|
|
8001730: 430a orrs r2, r1
|
|
8001732: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
|
|
/* Channel sampling time configuration */
|
|
/* For channels 10 to 17 */
|
|
if (sConfig->Channel >= ADC_CHANNEL_10)
|
|
8001734: 683b ldr r3, [r7, #0]
|
|
8001736: 681b ldr r3, [r3, #0]
|
|
8001738: 2b09 cmp r3, #9
|
|
800173a: d91c bls.n 8001776 <HAL_ADC_ConfigChannel+0x126>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR1 ,
|
|
800173c: 687b ldr r3, [r7, #4]
|
|
800173e: 681b ldr r3, [r3, #0]
|
|
8001740: 68d9 ldr r1, [r3, #12]
|
|
8001742: 683b ldr r3, [r7, #0]
|
|
8001744: 681a ldr r2, [r3, #0]
|
|
8001746: 4613 mov r3, r2
|
|
8001748: 005b lsls r3, r3, #1
|
|
800174a: 4413 add r3, r2
|
|
800174c: 3b1e subs r3, #30
|
|
800174e: 2207 movs r2, #7
|
|
8001750: fa02 f303 lsl.w r3, r2, r3
|
|
8001754: 43db mvns r3, r3
|
|
8001756: 4019 ands r1, r3
|
|
8001758: 683b ldr r3, [r7, #0]
|
|
800175a: 6898 ldr r0, [r3, #8]
|
|
800175c: 683b ldr r3, [r7, #0]
|
|
800175e: 681a ldr r2, [r3, #0]
|
|
8001760: 4613 mov r3, r2
|
|
8001762: 005b lsls r3, r3, #1
|
|
8001764: 4413 add r3, r2
|
|
8001766: 3b1e subs r3, #30
|
|
8001768: fa00 f203 lsl.w r2, r0, r3
|
|
800176c: 687b ldr r3, [r7, #4]
|
|
800176e: 681b ldr r3, [r3, #0]
|
|
8001770: 430a orrs r2, r1
|
|
8001772: 60da str r2, [r3, #12]
|
|
8001774: e019 b.n 80017aa <HAL_ADC_ConfigChannel+0x15a>
|
|
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
|
|
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
|
|
}
|
|
else /* For channels 0 to 9 */
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR2 ,
|
|
8001776: 687b ldr r3, [r7, #4]
|
|
8001778: 681b ldr r3, [r3, #0]
|
|
800177a: 6919 ldr r1, [r3, #16]
|
|
800177c: 683b ldr r3, [r7, #0]
|
|
800177e: 681a ldr r2, [r3, #0]
|
|
8001780: 4613 mov r3, r2
|
|
8001782: 005b lsls r3, r3, #1
|
|
8001784: 4413 add r3, r2
|
|
8001786: 2207 movs r2, #7
|
|
8001788: fa02 f303 lsl.w r3, r2, r3
|
|
800178c: 43db mvns r3, r3
|
|
800178e: 4019 ands r1, r3
|
|
8001790: 683b ldr r3, [r7, #0]
|
|
8001792: 6898 ldr r0, [r3, #8]
|
|
8001794: 683b ldr r3, [r7, #0]
|
|
8001796: 681a ldr r2, [r3, #0]
|
|
8001798: 4613 mov r3, r2
|
|
800179a: 005b lsls r3, r3, #1
|
|
800179c: 4413 add r3, r2
|
|
800179e: fa00 f203 lsl.w r2, r0, r3
|
|
80017a2: 687b ldr r3, [r7, #4]
|
|
80017a4: 681b ldr r3, [r3, #0]
|
|
80017a6: 430a orrs r2, r1
|
|
80017a8: 611a str r2, [r3, #16]
|
|
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
|
|
}
|
|
|
|
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
|
|
/* and VREFINT measurement path. */
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
|
|
80017aa: 683b ldr r3, [r7, #0]
|
|
80017ac: 681b ldr r3, [r3, #0]
|
|
80017ae: 2b10 cmp r3, #16
|
|
80017b0: d003 beq.n 80017ba <HAL_ADC_ConfigChannel+0x16a>
|
|
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
|
|
80017b2: 683b ldr r3, [r7, #0]
|
|
80017b4: 681b ldr r3, [r3, #0]
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
|
|
80017b6: 2b11 cmp r3, #17
|
|
80017b8: d132 bne.n 8001820 <HAL_ADC_ConfigChannel+0x1d0>
|
|
{
|
|
/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
|
|
/* measurement channels (VrefInt/TempSensor). If these channels are */
|
|
/* intended to be set on other ADC instances, an error is reported. */
|
|
if (hadc->Instance == ADC1)
|
|
80017ba: 687b ldr r3, [r7, #4]
|
|
80017bc: 681b ldr r3, [r3, #0]
|
|
80017be: 4a1d ldr r2, [pc, #116] @ (8001834 <HAL_ADC_ConfigChannel+0x1e4>)
|
|
80017c0: 4293 cmp r3, r2
|
|
80017c2: d125 bne.n 8001810 <HAL_ADC_ConfigChannel+0x1c0>
|
|
{
|
|
if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
|
|
80017c4: 687b ldr r3, [r7, #4]
|
|
80017c6: 681b ldr r3, [r3, #0]
|
|
80017c8: 689b ldr r3, [r3, #8]
|
|
80017ca: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80017ce: 2b00 cmp r3, #0
|
|
80017d0: d126 bne.n 8001820 <HAL_ADC_ConfigChannel+0x1d0>
|
|
{
|
|
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
|
|
80017d2: 687b ldr r3, [r7, #4]
|
|
80017d4: 681b ldr r3, [r3, #0]
|
|
80017d6: 689a ldr r2, [r3, #8]
|
|
80017d8: 687b ldr r3, [r7, #4]
|
|
80017da: 681b ldr r3, [r3, #0]
|
|
80017dc: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
|
|
80017e0: 609a str r2, [r3, #8]
|
|
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
80017e2: 683b ldr r3, [r7, #0]
|
|
80017e4: 681b ldr r3, [r3, #0]
|
|
80017e6: 2b10 cmp r3, #16
|
|
80017e8: d11a bne.n 8001820 <HAL_ADC_ConfigChannel+0x1d0>
|
|
{
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Compute number of CPU cycles to wait for */
|
|
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
|
|
80017ea: 4b13 ldr r3, [pc, #76] @ (8001838 <HAL_ADC_ConfigChannel+0x1e8>)
|
|
80017ec: 681b ldr r3, [r3, #0]
|
|
80017ee: 4a13 ldr r2, [pc, #76] @ (800183c <HAL_ADC_ConfigChannel+0x1ec>)
|
|
80017f0: fba2 2303 umull r2, r3, r2, r3
|
|
80017f4: 0c9a lsrs r2, r3, #18
|
|
80017f6: 4613 mov r3, r2
|
|
80017f8: 009b lsls r3, r3, #2
|
|
80017fa: 4413 add r3, r2
|
|
80017fc: 005b lsls r3, r3, #1
|
|
80017fe: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
8001800: e002 b.n 8001808 <HAL_ADC_ConfigChannel+0x1b8>
|
|
{
|
|
wait_loop_index--;
|
|
8001802: 68bb ldr r3, [r7, #8]
|
|
8001804: 3b01 subs r3, #1
|
|
8001806: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
8001808: 68bb ldr r3, [r7, #8]
|
|
800180a: 2b00 cmp r3, #0
|
|
800180c: d1f9 bne.n 8001802 <HAL_ADC_ConfigChannel+0x1b2>
|
|
800180e: e007 b.n 8001820 <HAL_ADC_ConfigChannel+0x1d0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8001810: 687b ldr r3, [r7, #4]
|
|
8001812: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001814: f043 0220 orr.w r2, r3, #32
|
|
8001818: 687b ldr r3, [r7, #4]
|
|
800181a: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
800181c: 2301 movs r3, #1
|
|
800181e: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8001820: 687b ldr r3, [r7, #4]
|
|
8001822: 2200 movs r2, #0
|
|
8001824: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8001828: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800182a: 4618 mov r0, r3
|
|
800182c: 3714 adds r7, #20
|
|
800182e: 46bd mov sp, r7
|
|
8001830: bc80 pop {r7}
|
|
8001832: 4770 bx lr
|
|
8001834: 40012400 .word 0x40012400
|
|
8001838: 20000000 .word 0x20000000
|
|
800183c: 431bde83 .word 0x431bde83
|
|
|
|
08001840 <ADC_ConversionStop_Disable>:
|
|
* stopped to disable the ADC.
|
|
* @param hadc: ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8001840: b580 push {r7, lr}
|
|
8001842: b084 sub sp, #16
|
|
8001844: af00 add r7, sp, #0
|
|
8001846: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8001848: 2300 movs r3, #0
|
|
800184a: 60fb str r3, [r7, #12]
|
|
|
|
/* Verification if ADC is not already disabled */
|
|
if (ADC_IS_ENABLE(hadc) != RESET)
|
|
800184c: 687b ldr r3, [r7, #4]
|
|
800184e: 681b ldr r3, [r3, #0]
|
|
8001850: 689b ldr r3, [r3, #8]
|
|
8001852: f003 0301 and.w r3, r3, #1
|
|
8001856: 2b01 cmp r3, #1
|
|
8001858: d12e bne.n 80018b8 <ADC_ConversionStop_Disable+0x78>
|
|
{
|
|
/* Disable the ADC peripheral */
|
|
__HAL_ADC_DISABLE(hadc);
|
|
800185a: 687b ldr r3, [r7, #4]
|
|
800185c: 681b ldr r3, [r3, #0]
|
|
800185e: 689a ldr r2, [r3, #8]
|
|
8001860: 687b ldr r3, [r7, #4]
|
|
8001862: 681b ldr r3, [r3, #0]
|
|
8001864: f022 0201 bic.w r2, r2, #1
|
|
8001868: 609a str r2, [r3, #8]
|
|
|
|
/* Get tick count */
|
|
tickstart = HAL_GetTick();
|
|
800186a: f7ff fe0f bl 800148c <HAL_GetTick>
|
|
800186e: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait for ADC effectively disabled */
|
|
while(ADC_IS_ENABLE(hadc) != RESET)
|
|
8001870: e01b b.n 80018aa <ADC_ConversionStop_Disable+0x6a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
|
|
8001872: f7ff fe0b bl 800148c <HAL_GetTick>
|
|
8001876: 4602 mov r2, r0
|
|
8001878: 68fb ldr r3, [r7, #12]
|
|
800187a: 1ad3 subs r3, r2, r3
|
|
800187c: 2b02 cmp r3, #2
|
|
800187e: d914 bls.n 80018aa <ADC_ConversionStop_Disable+0x6a>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if(ADC_IS_ENABLE(hadc) != RESET)
|
|
8001880: 687b ldr r3, [r7, #4]
|
|
8001882: 681b ldr r3, [r3, #0]
|
|
8001884: 689b ldr r3, [r3, #8]
|
|
8001886: f003 0301 and.w r3, r3, #1
|
|
800188a: 2b01 cmp r3, #1
|
|
800188c: d10d bne.n 80018aa <ADC_ConversionStop_Disable+0x6a>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
800188e: 687b ldr r3, [r7, #4]
|
|
8001890: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001892: f043 0210 orr.w r2, r3, #16
|
|
8001896: 687b ldr r3, [r7, #4]
|
|
8001898: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800189a: 687b ldr r3, [r7, #4]
|
|
800189c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800189e: f043 0201 orr.w r2, r3, #1
|
|
80018a2: 687b ldr r3, [r7, #4]
|
|
80018a4: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_ERROR;
|
|
80018a6: 2301 movs r3, #1
|
|
80018a8: e007 b.n 80018ba <ADC_ConversionStop_Disable+0x7a>
|
|
while(ADC_IS_ENABLE(hadc) != RESET)
|
|
80018aa: 687b ldr r3, [r7, #4]
|
|
80018ac: 681b ldr r3, [r3, #0]
|
|
80018ae: 689b ldr r3, [r3, #8]
|
|
80018b0: f003 0301 and.w r3, r3, #1
|
|
80018b4: 2b01 cmp r3, #1
|
|
80018b6: d0dc beq.n 8001872 <ADC_ConversionStop_Disable+0x32>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
80018b8: 2300 movs r3, #0
|
|
}
|
|
80018ba: 4618 mov r0, r3
|
|
80018bc: 3710 adds r7, #16
|
|
80018be: 46bd mov sp, r7
|
|
80018c0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080018c4 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80018c4: b480 push {r7}
|
|
80018c6: b085 sub sp, #20
|
|
80018c8: af00 add r7, sp, #0
|
|
80018ca: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80018cc: 687b ldr r3, [r7, #4]
|
|
80018ce: f003 0307 and.w r3, r3, #7
|
|
80018d2: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80018d4: 4b0c ldr r3, [pc, #48] @ (8001908 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80018d6: 68db ldr r3, [r3, #12]
|
|
80018d8: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80018da: 68ba ldr r2, [r7, #8]
|
|
80018dc: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80018e0: 4013 ands r3, r2
|
|
80018e2: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80018e4: 68fb ldr r3, [r7, #12]
|
|
80018e6: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80018e8: 68bb ldr r3, [r7, #8]
|
|
80018ea: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80018ec: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80018f0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80018f4: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80018f6: 4a04 ldr r2, [pc, #16] @ (8001908 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80018f8: 68bb ldr r3, [r7, #8]
|
|
80018fa: 60d3 str r3, [r2, #12]
|
|
}
|
|
80018fc: bf00 nop
|
|
80018fe: 3714 adds r7, #20
|
|
8001900: 46bd mov sp, r7
|
|
8001902: bc80 pop {r7}
|
|
8001904: 4770 bx lr
|
|
8001906: bf00 nop
|
|
8001908: e000ed00 .word 0xe000ed00
|
|
|
|
0800190c <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
800190c: b480 push {r7}
|
|
800190e: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8001910: 4b04 ldr r3, [pc, #16] @ (8001924 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8001912: 68db ldr r3, [r3, #12]
|
|
8001914: 0a1b lsrs r3, r3, #8
|
|
8001916: f003 0307 and.w r3, r3, #7
|
|
}
|
|
800191a: 4618 mov r0, r3
|
|
800191c: 46bd mov sp, r7
|
|
800191e: bc80 pop {r7}
|
|
8001920: 4770 bx lr
|
|
8001922: bf00 nop
|
|
8001924: e000ed00 .word 0xe000ed00
|
|
|
|
08001928 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001928: b480 push {r7}
|
|
800192a: b083 sub sp, #12
|
|
800192c: af00 add r7, sp, #0
|
|
800192e: 4603 mov r3, r0
|
|
8001930: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001932: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001936: 2b00 cmp r3, #0
|
|
8001938: db0b blt.n 8001952 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
800193a: 79fb ldrb r3, [r7, #7]
|
|
800193c: f003 021f and.w r2, r3, #31
|
|
8001940: 4906 ldr r1, [pc, #24] @ (800195c <__NVIC_EnableIRQ+0x34>)
|
|
8001942: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001946: 095b lsrs r3, r3, #5
|
|
8001948: 2001 movs r0, #1
|
|
800194a: fa00 f202 lsl.w r2, r0, r2
|
|
800194e: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
}
|
|
8001952: bf00 nop
|
|
8001954: 370c adds r7, #12
|
|
8001956: 46bd mov sp, r7
|
|
8001958: bc80 pop {r7}
|
|
800195a: 4770 bx lr
|
|
800195c: e000e100 .word 0xe000e100
|
|
|
|
08001960 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001960: b480 push {r7}
|
|
8001962: b083 sub sp, #12
|
|
8001964: af00 add r7, sp, #0
|
|
8001966: 4603 mov r3, r0
|
|
8001968: 6039 str r1, [r7, #0]
|
|
800196a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800196c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001970: 2b00 cmp r3, #0
|
|
8001972: db0a blt.n 800198a <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001974: 683b ldr r3, [r7, #0]
|
|
8001976: b2da uxtb r2, r3
|
|
8001978: 490c ldr r1, [pc, #48] @ (80019ac <__NVIC_SetPriority+0x4c>)
|
|
800197a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800197e: 0112 lsls r2, r2, #4
|
|
8001980: b2d2 uxtb r2, r2
|
|
8001982: 440b add r3, r1
|
|
8001984: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001988: e00a b.n 80019a0 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800198a: 683b ldr r3, [r7, #0]
|
|
800198c: b2da uxtb r2, r3
|
|
800198e: 4908 ldr r1, [pc, #32] @ (80019b0 <__NVIC_SetPriority+0x50>)
|
|
8001990: 79fb ldrb r3, [r7, #7]
|
|
8001992: f003 030f and.w r3, r3, #15
|
|
8001996: 3b04 subs r3, #4
|
|
8001998: 0112 lsls r2, r2, #4
|
|
800199a: b2d2 uxtb r2, r2
|
|
800199c: 440b add r3, r1
|
|
800199e: 761a strb r2, [r3, #24]
|
|
}
|
|
80019a0: bf00 nop
|
|
80019a2: 370c adds r7, #12
|
|
80019a4: 46bd mov sp, r7
|
|
80019a6: bc80 pop {r7}
|
|
80019a8: 4770 bx lr
|
|
80019aa: bf00 nop
|
|
80019ac: e000e100 .word 0xe000e100
|
|
80019b0: e000ed00 .word 0xe000ed00
|
|
|
|
080019b4 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80019b4: b480 push {r7}
|
|
80019b6: b089 sub sp, #36 @ 0x24
|
|
80019b8: af00 add r7, sp, #0
|
|
80019ba: 60f8 str r0, [r7, #12]
|
|
80019bc: 60b9 str r1, [r7, #8]
|
|
80019be: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80019c0: 68fb ldr r3, [r7, #12]
|
|
80019c2: f003 0307 and.w r3, r3, #7
|
|
80019c6: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80019c8: 69fb ldr r3, [r7, #28]
|
|
80019ca: f1c3 0307 rsb r3, r3, #7
|
|
80019ce: 2b04 cmp r3, #4
|
|
80019d0: bf28 it cs
|
|
80019d2: 2304 movcs r3, #4
|
|
80019d4: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80019d6: 69fb ldr r3, [r7, #28]
|
|
80019d8: 3304 adds r3, #4
|
|
80019da: 2b06 cmp r3, #6
|
|
80019dc: d902 bls.n 80019e4 <NVIC_EncodePriority+0x30>
|
|
80019de: 69fb ldr r3, [r7, #28]
|
|
80019e0: 3b03 subs r3, #3
|
|
80019e2: e000 b.n 80019e6 <NVIC_EncodePriority+0x32>
|
|
80019e4: 2300 movs r3, #0
|
|
80019e6: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80019e8: f04f 32ff mov.w r2, #4294967295
|
|
80019ec: 69bb ldr r3, [r7, #24]
|
|
80019ee: fa02 f303 lsl.w r3, r2, r3
|
|
80019f2: 43da mvns r2, r3
|
|
80019f4: 68bb ldr r3, [r7, #8]
|
|
80019f6: 401a ands r2, r3
|
|
80019f8: 697b ldr r3, [r7, #20]
|
|
80019fa: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80019fc: f04f 31ff mov.w r1, #4294967295
|
|
8001a00: 697b ldr r3, [r7, #20]
|
|
8001a02: fa01 f303 lsl.w r3, r1, r3
|
|
8001a06: 43d9 mvns r1, r3
|
|
8001a08: 687b ldr r3, [r7, #4]
|
|
8001a0a: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001a0c: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8001a0e: 4618 mov r0, r3
|
|
8001a10: 3724 adds r7, #36 @ 0x24
|
|
8001a12: 46bd mov sp, r7
|
|
8001a14: bc80 pop {r7}
|
|
8001a16: 4770 bx lr
|
|
|
|
08001a18 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8001a18: b580 push {r7, lr}
|
|
8001a1a: b082 sub sp, #8
|
|
8001a1c: af00 add r7, sp, #0
|
|
8001a1e: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8001a20: 687b ldr r3, [r7, #4]
|
|
8001a22: 3b01 subs r3, #1
|
|
8001a24: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8001a28: d301 bcc.n 8001a2e <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8001a2a: 2301 movs r3, #1
|
|
8001a2c: e00f b.n 8001a4e <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8001a2e: 4a0a ldr r2, [pc, #40] @ (8001a58 <SysTick_Config+0x40>)
|
|
8001a30: 687b ldr r3, [r7, #4]
|
|
8001a32: 3b01 subs r3, #1
|
|
8001a34: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8001a36: 210f movs r1, #15
|
|
8001a38: f04f 30ff mov.w r0, #4294967295
|
|
8001a3c: f7ff ff90 bl 8001960 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001a40: 4b05 ldr r3, [pc, #20] @ (8001a58 <SysTick_Config+0x40>)
|
|
8001a42: 2200 movs r2, #0
|
|
8001a44: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001a46: 4b04 ldr r3, [pc, #16] @ (8001a58 <SysTick_Config+0x40>)
|
|
8001a48: 2207 movs r2, #7
|
|
8001a4a: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001a4c: 2300 movs r3, #0
|
|
}
|
|
8001a4e: 4618 mov r0, r3
|
|
8001a50: 3708 adds r7, #8
|
|
8001a52: 46bd mov sp, r7
|
|
8001a54: bd80 pop {r7, pc}
|
|
8001a56: bf00 nop
|
|
8001a58: e000e010 .word 0xe000e010
|
|
|
|
08001a5c <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001a5c: b580 push {r7, lr}
|
|
8001a5e: b082 sub sp, #8
|
|
8001a60: af00 add r7, sp, #0
|
|
8001a62: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001a64: 6878 ldr r0, [r7, #4]
|
|
8001a66: f7ff ff2d bl 80018c4 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001a6a: bf00 nop
|
|
8001a6c: 3708 adds r7, #8
|
|
8001a6e: 46bd mov sp, r7
|
|
8001a70: bd80 pop {r7, pc}
|
|
|
|
08001a72 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001a72: b580 push {r7, lr}
|
|
8001a74: b086 sub sp, #24
|
|
8001a76: af00 add r7, sp, #0
|
|
8001a78: 4603 mov r3, r0
|
|
8001a7a: 60b9 str r1, [r7, #8]
|
|
8001a7c: 607a str r2, [r7, #4]
|
|
8001a7e: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8001a80: 2300 movs r3, #0
|
|
8001a82: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001a84: f7ff ff42 bl 800190c <__NVIC_GetPriorityGrouping>
|
|
8001a88: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8001a8a: 687a ldr r2, [r7, #4]
|
|
8001a8c: 68b9 ldr r1, [r7, #8]
|
|
8001a8e: 6978 ldr r0, [r7, #20]
|
|
8001a90: f7ff ff90 bl 80019b4 <NVIC_EncodePriority>
|
|
8001a94: 4602 mov r2, r0
|
|
8001a96: f997 300f ldrsb.w r3, [r7, #15]
|
|
8001a9a: 4611 mov r1, r2
|
|
8001a9c: 4618 mov r0, r3
|
|
8001a9e: f7ff ff5f bl 8001960 <__NVIC_SetPriority>
|
|
}
|
|
8001aa2: bf00 nop
|
|
8001aa4: 3718 adds r7, #24
|
|
8001aa6: 46bd mov sp, r7
|
|
8001aa8: bd80 pop {r7, pc}
|
|
|
|
08001aaa <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001aaa: b580 push {r7, lr}
|
|
8001aac: b082 sub sp, #8
|
|
8001aae: af00 add r7, sp, #0
|
|
8001ab0: 4603 mov r3, r0
|
|
8001ab2: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001ab4: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001ab8: 4618 mov r0, r3
|
|
8001aba: f7ff ff35 bl 8001928 <__NVIC_EnableIRQ>
|
|
}
|
|
8001abe: bf00 nop
|
|
8001ac0: 3708 adds r7, #8
|
|
8001ac2: 46bd mov sp, r7
|
|
8001ac4: bd80 pop {r7, pc}
|
|
|
|
08001ac6 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8001ac6: b580 push {r7, lr}
|
|
8001ac8: b082 sub sp, #8
|
|
8001aca: af00 add r7, sp, #0
|
|
8001acc: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8001ace: 6878 ldr r0, [r7, #4]
|
|
8001ad0: f7ff ffa2 bl 8001a18 <SysTick_Config>
|
|
8001ad4: 4603 mov r3, r0
|
|
}
|
|
8001ad6: 4618 mov r0, r3
|
|
8001ad8: 3708 adds r7, #8
|
|
8001ada: 46bd mov sp, r7
|
|
8001adc: bd80 pop {r7, pc}
|
|
|
|
08001ade <HAL_SYSTICK_IRQHandler>:
|
|
/**
|
|
* @brief This function handles SYSTICK interrupt request.
|
|
* @retval None
|
|
*/
|
|
void HAL_SYSTICK_IRQHandler(void)
|
|
{
|
|
8001ade: b580 push {r7, lr}
|
|
8001ae0: af00 add r7, sp, #0
|
|
HAL_SYSTICK_Callback();
|
|
8001ae2: f7fe fd6f bl 80005c4 <HAL_SYSTICK_Callback>
|
|
}
|
|
8001ae6: bf00 nop
|
|
8001ae8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001aec <HAL_GPIO_Init>:
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8001aec: b480 push {r7}
|
|
8001aee: b08b sub sp, #44 @ 0x2c
|
|
8001af0: af00 add r7, sp, #0
|
|
8001af2: 6078 str r0, [r7, #4]
|
|
8001af4: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8001af6: 2300 movs r3, #0
|
|
8001af8: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t ioposition;
|
|
uint32_t iocurrent;
|
|
uint32_t temp;
|
|
uint32_t config = 0x00u;
|
|
8001afa: 2300 movs r3, #0
|
|
8001afc: 623b str r3, [r7, #32]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8001afe: e169 b.n 8001dd4 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = (0x01uL << position);
|
|
8001b00: 2201 movs r2, #1
|
|
8001b02: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001b04: fa02 f303 lsl.w r3, r2, r3
|
|
8001b08: 61fb str r3, [r7, #28]
|
|
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8001b0a: 683b ldr r3, [r7, #0]
|
|
8001b0c: 681b ldr r3, [r3, #0]
|
|
8001b0e: 69fa ldr r2, [r7, #28]
|
|
8001b10: 4013 ands r3, r2
|
|
8001b12: 61bb str r3, [r7, #24]
|
|
|
|
if (iocurrent == ioposition)
|
|
8001b14: 69ba ldr r2, [r7, #24]
|
|
8001b16: 69fb ldr r3, [r7, #28]
|
|
8001b18: 429a cmp r2, r3
|
|
8001b1a: f040 8158 bne.w 8001dce <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
switch (GPIO_Init->Mode)
|
|
8001b1e: 683b ldr r3, [r7, #0]
|
|
8001b20: 685b ldr r3, [r3, #4]
|
|
8001b22: 4a9a ldr r2, [pc, #616] @ (8001d8c <HAL_GPIO_Init+0x2a0>)
|
|
8001b24: 4293 cmp r3, r2
|
|
8001b26: d05e beq.n 8001be6 <HAL_GPIO_Init+0xfa>
|
|
8001b28: 4a98 ldr r2, [pc, #608] @ (8001d8c <HAL_GPIO_Init+0x2a0>)
|
|
8001b2a: 4293 cmp r3, r2
|
|
8001b2c: d875 bhi.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
8001b2e: 4a98 ldr r2, [pc, #608] @ (8001d90 <HAL_GPIO_Init+0x2a4>)
|
|
8001b30: 4293 cmp r3, r2
|
|
8001b32: d058 beq.n 8001be6 <HAL_GPIO_Init+0xfa>
|
|
8001b34: 4a96 ldr r2, [pc, #600] @ (8001d90 <HAL_GPIO_Init+0x2a4>)
|
|
8001b36: 4293 cmp r3, r2
|
|
8001b38: d86f bhi.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
8001b3a: 4a96 ldr r2, [pc, #600] @ (8001d94 <HAL_GPIO_Init+0x2a8>)
|
|
8001b3c: 4293 cmp r3, r2
|
|
8001b3e: d052 beq.n 8001be6 <HAL_GPIO_Init+0xfa>
|
|
8001b40: 4a94 ldr r2, [pc, #592] @ (8001d94 <HAL_GPIO_Init+0x2a8>)
|
|
8001b42: 4293 cmp r3, r2
|
|
8001b44: d869 bhi.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
8001b46: 4a94 ldr r2, [pc, #592] @ (8001d98 <HAL_GPIO_Init+0x2ac>)
|
|
8001b48: 4293 cmp r3, r2
|
|
8001b4a: d04c beq.n 8001be6 <HAL_GPIO_Init+0xfa>
|
|
8001b4c: 4a92 ldr r2, [pc, #584] @ (8001d98 <HAL_GPIO_Init+0x2ac>)
|
|
8001b4e: 4293 cmp r3, r2
|
|
8001b50: d863 bhi.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
8001b52: 4a92 ldr r2, [pc, #584] @ (8001d9c <HAL_GPIO_Init+0x2b0>)
|
|
8001b54: 4293 cmp r3, r2
|
|
8001b56: d046 beq.n 8001be6 <HAL_GPIO_Init+0xfa>
|
|
8001b58: 4a90 ldr r2, [pc, #576] @ (8001d9c <HAL_GPIO_Init+0x2b0>)
|
|
8001b5a: 4293 cmp r3, r2
|
|
8001b5c: d85d bhi.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
8001b5e: 2b12 cmp r3, #18
|
|
8001b60: d82a bhi.n 8001bb8 <HAL_GPIO_Init+0xcc>
|
|
8001b62: 2b12 cmp r3, #18
|
|
8001b64: d859 bhi.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
8001b66: a201 add r2, pc, #4 @ (adr r2, 8001b6c <HAL_GPIO_Init+0x80>)
|
|
8001b68: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001b6c: 08001be7 .word 0x08001be7
|
|
8001b70: 08001bc1 .word 0x08001bc1
|
|
8001b74: 08001bd3 .word 0x08001bd3
|
|
8001b78: 08001c15 .word 0x08001c15
|
|
8001b7c: 08001c1b .word 0x08001c1b
|
|
8001b80: 08001c1b .word 0x08001c1b
|
|
8001b84: 08001c1b .word 0x08001c1b
|
|
8001b88: 08001c1b .word 0x08001c1b
|
|
8001b8c: 08001c1b .word 0x08001c1b
|
|
8001b90: 08001c1b .word 0x08001c1b
|
|
8001b94: 08001c1b .word 0x08001c1b
|
|
8001b98: 08001c1b .word 0x08001c1b
|
|
8001b9c: 08001c1b .word 0x08001c1b
|
|
8001ba0: 08001c1b .word 0x08001c1b
|
|
8001ba4: 08001c1b .word 0x08001c1b
|
|
8001ba8: 08001c1b .word 0x08001c1b
|
|
8001bac: 08001c1b .word 0x08001c1b
|
|
8001bb0: 08001bc9 .word 0x08001bc9
|
|
8001bb4: 08001bdd .word 0x08001bdd
|
|
8001bb8: 4a79 ldr r2, [pc, #484] @ (8001da0 <HAL_GPIO_Init+0x2b4>)
|
|
8001bba: 4293 cmp r3, r2
|
|
8001bbc: d013 beq.n 8001be6 <HAL_GPIO_Init+0xfa>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
break;
|
|
|
|
/* Parameters are checked with assert_param */
|
|
default:
|
|
break;
|
|
8001bbe: e02c b.n 8001c1a <HAL_GPIO_Init+0x12e>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
8001bc0: 683b ldr r3, [r7, #0]
|
|
8001bc2: 68db ldr r3, [r3, #12]
|
|
8001bc4: 623b str r3, [r7, #32]
|
|
break;
|
|
8001bc6: e029 b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
8001bc8: 683b ldr r3, [r7, #0]
|
|
8001bca: 68db ldr r3, [r3, #12]
|
|
8001bcc: 3304 adds r3, #4
|
|
8001bce: 623b str r3, [r7, #32]
|
|
break;
|
|
8001bd0: e024 b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
8001bd2: 683b ldr r3, [r7, #0]
|
|
8001bd4: 68db ldr r3, [r3, #12]
|
|
8001bd6: 3308 adds r3, #8
|
|
8001bd8: 623b str r3, [r7, #32]
|
|
break;
|
|
8001bda: e01f b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
8001bdc: 683b ldr r3, [r7, #0]
|
|
8001bde: 68db ldr r3, [r3, #12]
|
|
8001be0: 330c adds r3, #12
|
|
8001be2: 623b str r3, [r7, #32]
|
|
break;
|
|
8001be4: e01a b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
8001be6: 683b ldr r3, [r7, #0]
|
|
8001be8: 689b ldr r3, [r3, #8]
|
|
8001bea: 2b00 cmp r3, #0
|
|
8001bec: d102 bne.n 8001bf4 <HAL_GPIO_Init+0x108>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
8001bee: 2304 movs r3, #4
|
|
8001bf0: 623b str r3, [r7, #32]
|
|
break;
|
|
8001bf2: e013 b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
8001bf4: 683b ldr r3, [r7, #0]
|
|
8001bf6: 689b ldr r3, [r3, #8]
|
|
8001bf8: 2b01 cmp r3, #1
|
|
8001bfa: d105 bne.n 8001c08 <HAL_GPIO_Init+0x11c>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8001bfc: 2308 movs r3, #8
|
|
8001bfe: 623b str r3, [r7, #32]
|
|
GPIOx->BSRR = ioposition;
|
|
8001c00: 687b ldr r3, [r7, #4]
|
|
8001c02: 69fa ldr r2, [r7, #28]
|
|
8001c04: 611a str r2, [r3, #16]
|
|
break;
|
|
8001c06: e009 b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8001c08: 2308 movs r3, #8
|
|
8001c0a: 623b str r3, [r7, #32]
|
|
GPIOx->BRR = ioposition;
|
|
8001c0c: 687b ldr r3, [r7, #4]
|
|
8001c0e: 69fa ldr r2, [r7, #28]
|
|
8001c10: 615a str r2, [r3, #20]
|
|
break;
|
|
8001c12: e003 b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
8001c14: 2300 movs r3, #0
|
|
8001c16: 623b str r3, [r7, #32]
|
|
break;
|
|
8001c18: e000 b.n 8001c1c <HAL_GPIO_Init+0x130>
|
|
break;
|
|
8001c1a: bf00 nop
|
|
}
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
in order to address CRH or CRL register*/
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
8001c1c: 69bb ldr r3, [r7, #24]
|
|
8001c1e: 2bff cmp r3, #255 @ 0xff
|
|
8001c20: d801 bhi.n 8001c26 <HAL_GPIO_Init+0x13a>
|
|
8001c22: 687b ldr r3, [r7, #4]
|
|
8001c24: e001 b.n 8001c2a <HAL_GPIO_Init+0x13e>
|
|
8001c26: 687b ldr r3, [r7, #4]
|
|
8001c28: 3304 adds r3, #4
|
|
8001c2a: 617b str r3, [r7, #20]
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
8001c2c: 69bb ldr r3, [r7, #24]
|
|
8001c2e: 2bff cmp r3, #255 @ 0xff
|
|
8001c30: d802 bhi.n 8001c38 <HAL_GPIO_Init+0x14c>
|
|
8001c32: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001c34: 009b lsls r3, r3, #2
|
|
8001c36: e002 b.n 8001c3e <HAL_GPIO_Init+0x152>
|
|
8001c38: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001c3a: 3b08 subs r3, #8
|
|
8001c3c: 009b lsls r3, r3, #2
|
|
8001c3e: 613b str r3, [r7, #16]
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
8001c40: 697b ldr r3, [r7, #20]
|
|
8001c42: 681a ldr r2, [r3, #0]
|
|
8001c44: 210f movs r1, #15
|
|
8001c46: 693b ldr r3, [r7, #16]
|
|
8001c48: fa01 f303 lsl.w r3, r1, r3
|
|
8001c4c: 43db mvns r3, r3
|
|
8001c4e: 401a ands r2, r3
|
|
8001c50: 6a39 ldr r1, [r7, #32]
|
|
8001c52: 693b ldr r3, [r7, #16]
|
|
8001c54: fa01 f303 lsl.w r3, r1, r3
|
|
8001c58: 431a orrs r2, r3
|
|
8001c5a: 697b ldr r3, [r7, #20]
|
|
8001c5c: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
8001c5e: 683b ldr r3, [r7, #0]
|
|
8001c60: 685b ldr r3, [r3, #4]
|
|
8001c62: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001c66: 2b00 cmp r3, #0
|
|
8001c68: f000 80b1 beq.w 8001dce <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable AFIO Clock */
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
8001c6c: 4b4d ldr r3, [pc, #308] @ (8001da4 <HAL_GPIO_Init+0x2b8>)
|
|
8001c6e: 699b ldr r3, [r3, #24]
|
|
8001c70: 4a4c ldr r2, [pc, #304] @ (8001da4 <HAL_GPIO_Init+0x2b8>)
|
|
8001c72: f043 0301 orr.w r3, r3, #1
|
|
8001c76: 6193 str r3, [r2, #24]
|
|
8001c78: 4b4a ldr r3, [pc, #296] @ (8001da4 <HAL_GPIO_Init+0x2b8>)
|
|
8001c7a: 699b ldr r3, [r3, #24]
|
|
8001c7c: f003 0301 and.w r3, r3, #1
|
|
8001c80: 60bb str r3, [r7, #8]
|
|
8001c82: 68bb ldr r3, [r7, #8]
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
8001c84: 4a48 ldr r2, [pc, #288] @ (8001da8 <HAL_GPIO_Init+0x2bc>)
|
|
8001c86: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001c88: 089b lsrs r3, r3, #2
|
|
8001c8a: 3302 adds r3, #2
|
|
8001c8c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001c90: 60fb str r3, [r7, #12]
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
8001c92: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001c94: f003 0303 and.w r3, r3, #3
|
|
8001c98: 009b lsls r3, r3, #2
|
|
8001c9a: 220f movs r2, #15
|
|
8001c9c: fa02 f303 lsl.w r3, r2, r3
|
|
8001ca0: 43db mvns r3, r3
|
|
8001ca2: 68fa ldr r2, [r7, #12]
|
|
8001ca4: 4013 ands r3, r2
|
|
8001ca6: 60fb str r3, [r7, #12]
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
8001ca8: 687b ldr r3, [r7, #4]
|
|
8001caa: 4a40 ldr r2, [pc, #256] @ (8001dac <HAL_GPIO_Init+0x2c0>)
|
|
8001cac: 4293 cmp r3, r2
|
|
8001cae: d013 beq.n 8001cd8 <HAL_GPIO_Init+0x1ec>
|
|
8001cb0: 687b ldr r3, [r7, #4]
|
|
8001cb2: 4a3f ldr r2, [pc, #252] @ (8001db0 <HAL_GPIO_Init+0x2c4>)
|
|
8001cb4: 4293 cmp r3, r2
|
|
8001cb6: d00d beq.n 8001cd4 <HAL_GPIO_Init+0x1e8>
|
|
8001cb8: 687b ldr r3, [r7, #4]
|
|
8001cba: 4a3e ldr r2, [pc, #248] @ (8001db4 <HAL_GPIO_Init+0x2c8>)
|
|
8001cbc: 4293 cmp r3, r2
|
|
8001cbe: d007 beq.n 8001cd0 <HAL_GPIO_Init+0x1e4>
|
|
8001cc0: 687b ldr r3, [r7, #4]
|
|
8001cc2: 4a3d ldr r2, [pc, #244] @ (8001db8 <HAL_GPIO_Init+0x2cc>)
|
|
8001cc4: 4293 cmp r3, r2
|
|
8001cc6: d101 bne.n 8001ccc <HAL_GPIO_Init+0x1e0>
|
|
8001cc8: 2303 movs r3, #3
|
|
8001cca: e006 b.n 8001cda <HAL_GPIO_Init+0x1ee>
|
|
8001ccc: 2304 movs r3, #4
|
|
8001cce: e004 b.n 8001cda <HAL_GPIO_Init+0x1ee>
|
|
8001cd0: 2302 movs r3, #2
|
|
8001cd2: e002 b.n 8001cda <HAL_GPIO_Init+0x1ee>
|
|
8001cd4: 2301 movs r3, #1
|
|
8001cd6: e000 b.n 8001cda <HAL_GPIO_Init+0x1ee>
|
|
8001cd8: 2300 movs r3, #0
|
|
8001cda: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001cdc: f002 0203 and.w r2, r2, #3
|
|
8001ce0: 0092 lsls r2, r2, #2
|
|
8001ce2: 4093 lsls r3, r2
|
|
8001ce4: 68fa ldr r2, [r7, #12]
|
|
8001ce6: 4313 orrs r3, r2
|
|
8001ce8: 60fb str r3, [r7, #12]
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
8001cea: 492f ldr r1, [pc, #188] @ (8001da8 <HAL_GPIO_Init+0x2bc>)
|
|
8001cec: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001cee: 089b lsrs r3, r3, #2
|
|
8001cf0: 3302 adds r3, #2
|
|
8001cf2: 68fa ldr r2, [r7, #12]
|
|
8001cf4: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
/* Enable or disable the rising trigger */
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
8001cf8: 683b ldr r3, [r7, #0]
|
|
8001cfa: 685b ldr r3, [r3, #4]
|
|
8001cfc: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001d00: 2b00 cmp r3, #0
|
|
8001d02: d006 beq.n 8001d12 <HAL_GPIO_Init+0x226>
|
|
{
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
8001d04: 4b2d ldr r3, [pc, #180] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d06: 689a ldr r2, [r3, #8]
|
|
8001d08: 492c ldr r1, [pc, #176] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d0a: 69bb ldr r3, [r7, #24]
|
|
8001d0c: 4313 orrs r3, r2
|
|
8001d0e: 608b str r3, [r1, #8]
|
|
8001d10: e006 b.n 8001d20 <HAL_GPIO_Init+0x234>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
8001d12: 4b2a ldr r3, [pc, #168] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d14: 689a ldr r2, [r3, #8]
|
|
8001d16: 69bb ldr r3, [r7, #24]
|
|
8001d18: 43db mvns r3, r3
|
|
8001d1a: 4928 ldr r1, [pc, #160] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d1c: 4013 ands r3, r2
|
|
8001d1e: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Enable or disable the falling trigger */
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
8001d20: 683b ldr r3, [r7, #0]
|
|
8001d22: 685b ldr r3, [r3, #4]
|
|
8001d24: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001d28: 2b00 cmp r3, #0
|
|
8001d2a: d006 beq.n 8001d3a <HAL_GPIO_Init+0x24e>
|
|
{
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
8001d2c: 4b23 ldr r3, [pc, #140] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d2e: 68da ldr r2, [r3, #12]
|
|
8001d30: 4922 ldr r1, [pc, #136] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d32: 69bb ldr r3, [r7, #24]
|
|
8001d34: 4313 orrs r3, r2
|
|
8001d36: 60cb str r3, [r1, #12]
|
|
8001d38: e006 b.n 8001d48 <HAL_GPIO_Init+0x25c>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
8001d3a: 4b20 ldr r3, [pc, #128] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d3c: 68da ldr r2, [r3, #12]
|
|
8001d3e: 69bb ldr r3, [r7, #24]
|
|
8001d40: 43db mvns r3, r3
|
|
8001d42: 491e ldr r1, [pc, #120] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d44: 4013 ands r3, r2
|
|
8001d46: 60cb str r3, [r1, #12]
|
|
}
|
|
|
|
/* Configure the event mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8001d48: 683b ldr r3, [r7, #0]
|
|
8001d4a: 685b ldr r3, [r3, #4]
|
|
8001d4c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001d50: 2b00 cmp r3, #0
|
|
8001d52: d006 beq.n 8001d62 <HAL_GPIO_Init+0x276>
|
|
{
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
8001d54: 4b19 ldr r3, [pc, #100] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d56: 685a ldr r2, [r3, #4]
|
|
8001d58: 4918 ldr r1, [pc, #96] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d5a: 69bb ldr r3, [r7, #24]
|
|
8001d5c: 4313 orrs r3, r2
|
|
8001d5e: 604b str r3, [r1, #4]
|
|
8001d60: e006 b.n 8001d70 <HAL_GPIO_Init+0x284>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
8001d62: 4b16 ldr r3, [pc, #88] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d64: 685a ldr r2, [r3, #4]
|
|
8001d66: 69bb ldr r3, [r7, #24]
|
|
8001d68: 43db mvns r3, r3
|
|
8001d6a: 4914 ldr r1, [pc, #80] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d6c: 4013 ands r3, r2
|
|
8001d6e: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the interrupt mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
8001d70: 683b ldr r3, [r7, #0]
|
|
8001d72: 685b ldr r3, [r3, #4]
|
|
8001d74: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001d78: 2b00 cmp r3, #0
|
|
8001d7a: d021 beq.n 8001dc0 <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
8001d7c: 4b0f ldr r3, [pc, #60] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d7e: 681a ldr r2, [r3, #0]
|
|
8001d80: 490e ldr r1, [pc, #56] @ (8001dbc <HAL_GPIO_Init+0x2d0>)
|
|
8001d82: 69bb ldr r3, [r7, #24]
|
|
8001d84: 4313 orrs r3, r2
|
|
8001d86: 600b str r3, [r1, #0]
|
|
8001d88: e021 b.n 8001dce <HAL_GPIO_Init+0x2e2>
|
|
8001d8a: bf00 nop
|
|
8001d8c: 10320000 .word 0x10320000
|
|
8001d90: 10310000 .word 0x10310000
|
|
8001d94: 10220000 .word 0x10220000
|
|
8001d98: 10210000 .word 0x10210000
|
|
8001d9c: 10120000 .word 0x10120000
|
|
8001da0: 10110000 .word 0x10110000
|
|
8001da4: 40021000 .word 0x40021000
|
|
8001da8: 40010000 .word 0x40010000
|
|
8001dac: 40010800 .word 0x40010800
|
|
8001db0: 40010c00 .word 0x40010c00
|
|
8001db4: 40011000 .word 0x40011000
|
|
8001db8: 40011400 .word 0x40011400
|
|
8001dbc: 40010400 .word 0x40010400
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
8001dc0: 4b0b ldr r3, [pc, #44] @ (8001df0 <HAL_GPIO_Init+0x304>)
|
|
8001dc2: 681a ldr r2, [r3, #0]
|
|
8001dc4: 69bb ldr r3, [r7, #24]
|
|
8001dc6: 43db mvns r3, r3
|
|
8001dc8: 4909 ldr r1, [pc, #36] @ (8001df0 <HAL_GPIO_Init+0x304>)
|
|
8001dca: 4013 ands r3, r2
|
|
8001dcc: 600b str r3, [r1, #0]
|
|
}
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8001dce: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001dd0: 3301 adds r3, #1
|
|
8001dd2: 627b str r3, [r7, #36] @ 0x24
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8001dd4: 683b ldr r3, [r7, #0]
|
|
8001dd6: 681a ldr r2, [r3, #0]
|
|
8001dd8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001dda: fa22 f303 lsr.w r3, r2, r3
|
|
8001dde: 2b00 cmp r3, #0
|
|
8001de0: f47f ae8e bne.w 8001b00 <HAL_GPIO_Init+0x14>
|
|
}
|
|
}
|
|
8001de4: bf00 nop
|
|
8001de6: bf00 nop
|
|
8001de8: 372c adds r7, #44 @ 0x2c
|
|
8001dea: 46bd mov sp, r7
|
|
8001dec: bc80 pop {r7}
|
|
8001dee: 4770 bx lr
|
|
8001df0: 40010400 .word 0x40010400
|
|
|
|
08001df4 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8001df4: b480 push {r7}
|
|
8001df6: b083 sub sp, #12
|
|
8001df8: af00 add r7, sp, #0
|
|
8001dfa: 6078 str r0, [r7, #4]
|
|
8001dfc: 460b mov r3, r1
|
|
8001dfe: 807b strh r3, [r7, #2]
|
|
8001e00: 4613 mov r3, r2
|
|
8001e02: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8001e04: 787b ldrb r3, [r7, #1]
|
|
8001e06: 2b00 cmp r3, #0
|
|
8001e08: d003 beq.n 8001e12 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8001e0a: 887a ldrh r2, [r7, #2]
|
|
8001e0c: 687b ldr r3, [r7, #4]
|
|
8001e0e: 611a str r2, [r3, #16]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
}
|
|
}
|
|
8001e10: e003 b.n 8001e1a <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
8001e12: 887b ldrh r3, [r7, #2]
|
|
8001e14: 041a lsls r2, r3, #16
|
|
8001e16: 687b ldr r3, [r7, #4]
|
|
8001e18: 611a str r2, [r3, #16]
|
|
}
|
|
8001e1a: bf00 nop
|
|
8001e1c: 370c adds r7, #12
|
|
8001e1e: 46bd mov sp, r7
|
|
8001e20: bc80 pop {r7}
|
|
8001e22: 4770 bx lr
|
|
|
|
08001e24 <HAL_GPIO_TogglePin>:
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
|
* @param GPIO_Pin: Specifies the pins to be toggled.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8001e24: b480 push {r7}
|
|
8001e26: b085 sub sp, #20
|
|
8001e28: af00 add r7, sp, #0
|
|
8001e2a: 6078 str r0, [r7, #4]
|
|
8001e2c: 460b mov r3, r1
|
|
8001e2e: 807b strh r3, [r7, #2]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* get current Output Data Register value */
|
|
odr = GPIOx->ODR;
|
|
8001e30: 687b ldr r3, [r7, #4]
|
|
8001e32: 68db ldr r3, [r3, #12]
|
|
8001e34: 60fb str r3, [r7, #12]
|
|
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
|
8001e36: 887a ldrh r2, [r7, #2]
|
|
8001e38: 68fb ldr r3, [r7, #12]
|
|
8001e3a: 4013 ands r3, r2
|
|
8001e3c: 041a lsls r2, r3, #16
|
|
8001e3e: 68fb ldr r3, [r7, #12]
|
|
8001e40: 43d9 mvns r1, r3
|
|
8001e42: 887b ldrh r3, [r7, #2]
|
|
8001e44: 400b ands r3, r1
|
|
8001e46: 431a orrs r2, r3
|
|
8001e48: 687b ldr r3, [r7, #4]
|
|
8001e4a: 611a str r2, [r3, #16]
|
|
}
|
|
8001e4c: bf00 nop
|
|
8001e4e: 3714 adds r7, #20
|
|
8001e50: 46bd mov sp, r7
|
|
8001e52: bc80 pop {r7}
|
|
8001e54: 4770 bx lr
|
|
|
|
08001e56 <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8001e56: b580 push {r7, lr}
|
|
8001e58: b084 sub sp, #16
|
|
8001e5a: af00 add r7, sp, #0
|
|
8001e5c: 6078 str r0, [r7, #4]
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
8001e5e: 687b ldr r3, [r7, #4]
|
|
8001e60: 2b00 cmp r3, #0
|
|
8001e62: d101 bne.n 8001e68 <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001e64: 2301 movs r3, #1
|
|
8001e66: e0e8 b.n 800203a <HAL_PCD_Init+0x1e4>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
8001e68: 687b ldr r3, [r7, #4]
|
|
8001e6a: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
|
|
8001e6e: b2db uxtb r3, r3
|
|
8001e70: 2b00 cmp r3, #0
|
|
8001e72: d106 bne.n 8001e82 <HAL_PCD_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
8001e74: 687b ldr r3, [r7, #4]
|
|
8001e76: 2200 movs r2, #0
|
|
8001e78: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
8001e7c: 6878 ldr r0, [r7, #4]
|
|
8001e7e: f007 facf bl 8009420 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
8001e82: 687b ldr r3, [r7, #4]
|
|
8001e84: 2203 movs r2, #3
|
|
8001e86: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
|
|
/* Disable DMA mode for FS instance */
|
|
hpcd->Init.dma_enable = 0U;
|
|
8001e8a: 687b ldr r3, [r7, #4]
|
|
8001e8c: 2200 movs r2, #0
|
|
8001e8e: 715a strb r2, [r3, #5]
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
8001e90: 687b ldr r3, [r7, #4]
|
|
8001e92: 681b ldr r3, [r3, #0]
|
|
8001e94: 4618 mov r0, r3
|
|
8001e96: f003 f974 bl 8005182 <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8001e9a: 687b ldr r3, [r7, #4]
|
|
8001e9c: 6818 ldr r0, [r3, #0]
|
|
8001e9e: 687b ldr r3, [r7, #4]
|
|
8001ea0: 3304 adds r3, #4
|
|
8001ea2: cb0e ldmia r3, {r1, r2, r3}
|
|
8001ea4: f003 f94a bl 800513c <USB_CoreInit>
|
|
8001ea8: 4603 mov r3, r0
|
|
8001eaa: 2b00 cmp r3, #0
|
|
8001eac: d005 beq.n 8001eba <HAL_PCD_Init+0x64>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001eae: 687b ldr r3, [r7, #4]
|
|
8001eb0: 2202 movs r2, #2
|
|
8001eb2: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
return HAL_ERROR;
|
|
8001eb6: 2301 movs r3, #1
|
|
8001eb8: e0bf b.n 800203a <HAL_PCD_Init+0x1e4>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8001eba: 687b ldr r3, [r7, #4]
|
|
8001ebc: 681b ldr r3, [r3, #0]
|
|
8001ebe: 2100 movs r1, #0
|
|
8001ec0: 4618 mov r0, r3
|
|
8001ec2: f003 f978 bl 80051b6 <USB_SetCurrentMode>
|
|
8001ec6: 4603 mov r3, r0
|
|
8001ec8: 2b00 cmp r3, #0
|
|
8001eca: d005 beq.n 8001ed8 <HAL_PCD_Init+0x82>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001ecc: 687b ldr r3, [r7, #4]
|
|
8001ece: 2202 movs r2, #2
|
|
8001ed0: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
return HAL_ERROR;
|
|
8001ed4: 2301 movs r3, #1
|
|
8001ed6: e0b0 b.n 800203a <HAL_PCD_Init+0x1e4>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001ed8: 2300 movs r3, #0
|
|
8001eda: 73fb strb r3, [r7, #15]
|
|
8001edc: e03e b.n 8001f5c <HAL_PCD_Init+0x106>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8001ede: 7bfa ldrb r2, [r7, #15]
|
|
8001ee0: 6879 ldr r1, [r7, #4]
|
|
8001ee2: 4613 mov r3, r2
|
|
8001ee4: 009b lsls r3, r3, #2
|
|
8001ee6: 4413 add r3, r2
|
|
8001ee8: 00db lsls r3, r3, #3
|
|
8001eea: 440b add r3, r1
|
|
8001eec: 3311 adds r3, #17
|
|
8001eee: 2201 movs r2, #1
|
|
8001ef0: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8001ef2: 7bfa ldrb r2, [r7, #15]
|
|
8001ef4: 6879 ldr r1, [r7, #4]
|
|
8001ef6: 4613 mov r3, r2
|
|
8001ef8: 009b lsls r3, r3, #2
|
|
8001efa: 4413 add r3, r2
|
|
8001efc: 00db lsls r3, r3, #3
|
|
8001efe: 440b add r3, r1
|
|
8001f00: 3310 adds r3, #16
|
|
8001f02: 7bfa ldrb r2, [r7, #15]
|
|
8001f04: 701a strb r2, [r3, #0]
|
|
#if defined (USB_OTG_FS)
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8001f06: 7bfa ldrb r2, [r7, #15]
|
|
8001f08: 6879 ldr r1, [r7, #4]
|
|
8001f0a: 4613 mov r3, r2
|
|
8001f0c: 009b lsls r3, r3, #2
|
|
8001f0e: 4413 add r3, r2
|
|
8001f10: 00db lsls r3, r3, #3
|
|
8001f12: 440b add r3, r1
|
|
8001f14: 3313 adds r3, #19
|
|
8001f16: 2200 movs r2, #0
|
|
8001f18: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8001f1a: 7bfa ldrb r2, [r7, #15]
|
|
8001f1c: 6879 ldr r1, [r7, #4]
|
|
8001f1e: 4613 mov r3, r2
|
|
8001f20: 009b lsls r3, r3, #2
|
|
8001f22: 4413 add r3, r2
|
|
8001f24: 00db lsls r3, r3, #3
|
|
8001f26: 440b add r3, r1
|
|
8001f28: 3320 adds r3, #32
|
|
8001f2a: 2200 movs r2, #0
|
|
8001f2c: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8001f2e: 7bfa ldrb r2, [r7, #15]
|
|
8001f30: 6879 ldr r1, [r7, #4]
|
|
8001f32: 4613 mov r3, r2
|
|
8001f34: 009b lsls r3, r3, #2
|
|
8001f36: 4413 add r3, r2
|
|
8001f38: 00db lsls r3, r3, #3
|
|
8001f3a: 440b add r3, r1
|
|
8001f3c: 3324 adds r3, #36 @ 0x24
|
|
8001f3e: 2200 movs r2, #0
|
|
8001f40: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8001f42: 7bfb ldrb r3, [r7, #15]
|
|
8001f44: 6879 ldr r1, [r7, #4]
|
|
8001f46: 1c5a adds r2, r3, #1
|
|
8001f48: 4613 mov r3, r2
|
|
8001f4a: 009b lsls r3, r3, #2
|
|
8001f4c: 4413 add r3, r2
|
|
8001f4e: 00db lsls r3, r3, #3
|
|
8001f50: 440b add r3, r1
|
|
8001f52: 2200 movs r2, #0
|
|
8001f54: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001f56: 7bfb ldrb r3, [r7, #15]
|
|
8001f58: 3301 adds r3, #1
|
|
8001f5a: 73fb strb r3, [r7, #15]
|
|
8001f5c: 687b ldr r3, [r7, #4]
|
|
8001f5e: 791b ldrb r3, [r3, #4]
|
|
8001f60: 7bfa ldrb r2, [r7, #15]
|
|
8001f62: 429a cmp r2, r3
|
|
8001f64: d3bb bcc.n 8001ede <HAL_PCD_Init+0x88>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001f66: 2300 movs r3, #0
|
|
8001f68: 73fb strb r3, [r7, #15]
|
|
8001f6a: e044 b.n 8001ff6 <HAL_PCD_Init+0x1a0>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8001f6c: 7bfa ldrb r2, [r7, #15]
|
|
8001f6e: 6879 ldr r1, [r7, #4]
|
|
8001f70: 4613 mov r3, r2
|
|
8001f72: 009b lsls r3, r3, #2
|
|
8001f74: 4413 add r3, r2
|
|
8001f76: 00db lsls r3, r3, #3
|
|
8001f78: 440b add r3, r1
|
|
8001f7a: f203 1351 addw r3, r3, #337 @ 0x151
|
|
8001f7e: 2200 movs r2, #0
|
|
8001f80: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8001f82: 7bfa ldrb r2, [r7, #15]
|
|
8001f84: 6879 ldr r1, [r7, #4]
|
|
8001f86: 4613 mov r3, r2
|
|
8001f88: 009b lsls r3, r3, #2
|
|
8001f8a: 4413 add r3, r2
|
|
8001f8c: 00db lsls r3, r3, #3
|
|
8001f8e: 440b add r3, r1
|
|
8001f90: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8001f94: 7bfa ldrb r2, [r7, #15]
|
|
8001f96: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
8001f98: 7bfa ldrb r2, [r7, #15]
|
|
8001f9a: 6879 ldr r1, [r7, #4]
|
|
8001f9c: 4613 mov r3, r2
|
|
8001f9e: 009b lsls r3, r3, #2
|
|
8001fa0: 4413 add r3, r2
|
|
8001fa2: 00db lsls r3, r3, #3
|
|
8001fa4: 440b add r3, r1
|
|
8001fa6: f203 1353 addw r3, r3, #339 @ 0x153
|
|
8001faa: 2200 movs r2, #0
|
|
8001fac: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8001fae: 7bfa ldrb r2, [r7, #15]
|
|
8001fb0: 6879 ldr r1, [r7, #4]
|
|
8001fb2: 4613 mov r3, r2
|
|
8001fb4: 009b lsls r3, r3, #2
|
|
8001fb6: 4413 add r3, r2
|
|
8001fb8: 00db lsls r3, r3, #3
|
|
8001fba: 440b add r3, r1
|
|
8001fbc: f503 73b0 add.w r3, r3, #352 @ 0x160
|
|
8001fc0: 2200 movs r2, #0
|
|
8001fc2: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8001fc4: 7bfa ldrb r2, [r7, #15]
|
|
8001fc6: 6879 ldr r1, [r7, #4]
|
|
8001fc8: 4613 mov r3, r2
|
|
8001fca: 009b lsls r3, r3, #2
|
|
8001fcc: 4413 add r3, r2
|
|
8001fce: 00db lsls r3, r3, #3
|
|
8001fd0: 440b add r3, r1
|
|
8001fd2: f503 73b2 add.w r3, r3, #356 @ 0x164
|
|
8001fd6: 2200 movs r2, #0
|
|
8001fd8: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
8001fda: 7bfa ldrb r2, [r7, #15]
|
|
8001fdc: 6879 ldr r1, [r7, #4]
|
|
8001fde: 4613 mov r3, r2
|
|
8001fe0: 009b lsls r3, r3, #2
|
|
8001fe2: 4413 add r3, r2
|
|
8001fe4: 00db lsls r3, r3, #3
|
|
8001fe6: 440b add r3, r1
|
|
8001fe8: f503 73b4 add.w r3, r3, #360 @ 0x168
|
|
8001fec: 2200 movs r2, #0
|
|
8001fee: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001ff0: 7bfb ldrb r3, [r7, #15]
|
|
8001ff2: 3301 adds r3, #1
|
|
8001ff4: 73fb strb r3, [r7, #15]
|
|
8001ff6: 687b ldr r3, [r7, #4]
|
|
8001ff8: 791b ldrb r3, [r3, #4]
|
|
8001ffa: 7bfa ldrb r2, [r7, #15]
|
|
8001ffc: 429a cmp r2, r3
|
|
8001ffe: d3b5 bcc.n 8001f6c <HAL_PCD_Init+0x116>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8002000: 687b ldr r3, [r7, #4]
|
|
8002002: 6818 ldr r0, [r3, #0]
|
|
8002004: 687b ldr r3, [r7, #4]
|
|
8002006: 3304 adds r3, #4
|
|
8002008: cb0e ldmia r3, {r1, r2, r3}
|
|
800200a: f003 f8e0 bl 80051ce <USB_DevInit>
|
|
800200e: 4603 mov r3, r0
|
|
8002010: 2b00 cmp r3, #0
|
|
8002012: d005 beq.n 8002020 <HAL_PCD_Init+0x1ca>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8002014: 687b ldr r3, [r7, #4]
|
|
8002016: 2202 movs r2, #2
|
|
8002018: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
return HAL_ERROR;
|
|
800201c: 2301 movs r3, #1
|
|
800201e: e00c b.n 800203a <HAL_PCD_Init+0x1e4>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8002020: 687b ldr r3, [r7, #4]
|
|
8002022: 2200 movs r2, #0
|
|
8002024: 735a strb r2, [r3, #13]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
8002026: 687b ldr r3, [r7, #4]
|
|
8002028: 2201 movs r2, #1
|
|
800202a: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
800202e: 687b ldr r3, [r7, #4]
|
|
8002030: 681b ldr r3, [r3, #0]
|
|
8002032: 4618 mov r0, r3
|
|
8002034: f005 fb5f bl 80076f6 <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
8002038: 2300 movs r3, #0
|
|
}
|
|
800203a: 4618 mov r0, r3
|
|
800203c: 3710 adds r7, #16
|
|
800203e: 46bd mov sp, r7
|
|
8002040: bd80 pop {r7, pc}
|
|
|
|
08002042 <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002042: b580 push {r7, lr}
|
|
8002044: b082 sub sp, #8
|
|
8002046: af00 add r7, sp, #0
|
|
8002048: 6078 str r0, [r7, #4]
|
|
__HAL_LOCK(hpcd);
|
|
800204a: 687b ldr r3, [r7, #4]
|
|
800204c: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8002050: 2b01 cmp r3, #1
|
|
8002052: d101 bne.n 8002058 <HAL_PCD_Start+0x16>
|
|
8002054: 2302 movs r3, #2
|
|
8002056: e016 b.n 8002086 <HAL_PCD_Start+0x44>
|
|
8002058: 687b ldr r3, [r7, #4]
|
|
800205a: 2201 movs r2, #1
|
|
800205c: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
8002060: 687b ldr r3, [r7, #4]
|
|
8002062: 681b ldr r3, [r3, #0]
|
|
8002064: 4618 mov r0, r3
|
|
8002066: f003 f876 bl 8005156 <USB_EnableGlobalInt>
|
|
|
|
#if defined (USB)
|
|
HAL_PCDEx_SetConnectionState(hpcd, 1U);
|
|
800206a: 2101 movs r1, #1
|
|
800206c: 6878 ldr r0, [r7, #4]
|
|
800206e: f007 fc4a bl 8009906 <HAL_PCDEx_SetConnectionState>
|
|
#endif /* defined (USB) */
|
|
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
8002072: 687b ldr r3, [r7, #4]
|
|
8002074: 681b ldr r3, [r3, #0]
|
|
8002076: 4618 mov r0, r3
|
|
8002078: f005 fb33 bl 80076e2 <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
800207c: 687b ldr r3, [r7, #4]
|
|
800207e: 2200 movs r2, #0
|
|
8002080: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
8002084: 2300 movs r3, #0
|
|
}
|
|
8002086: 4618 mov r0, r3
|
|
8002088: 3708 adds r7, #8
|
|
800208a: 46bd mov sp, r7
|
|
800208c: bd80 pop {r7, pc}
|
|
|
|
0800208e <HAL_PCD_IRQHandler>:
|
|
* @brief This function handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
800208e: b580 push {r7, lr}
|
|
8002090: b088 sub sp, #32
|
|
8002092: af00 add r7, sp, #0
|
|
8002094: 6078 str r0, [r7, #4]
|
|
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
|
|
8002096: 687b ldr r3, [r7, #4]
|
|
8002098: 681b ldr r3, [r3, #0]
|
|
800209a: 4618 mov r0, r3
|
|
800209c: f005 fb35 bl 800770a <USB_ReadInterrupts>
|
|
80020a0: 61b8 str r0, [r7, #24]
|
|
uint16_t store_ep[8];
|
|
uint8_t i;
|
|
|
|
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
|
|
80020a2: 69bb ldr r3, [r7, #24]
|
|
80020a4: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80020a8: 2b00 cmp r3, #0
|
|
80020aa: d003 beq.n 80020b4 <HAL_PCD_IRQHandler+0x26>
|
|
{
|
|
/* servicing of the endpoint correct transfer interrupt */
|
|
/* clear of the CTR flag into the sub */
|
|
(void)PCD_EP_ISR_Handler(hpcd);
|
|
80020ac: 6878 ldr r0, [r7, #4]
|
|
80020ae: f000 fb1a bl 80026e6 <PCD_EP_ISR_Handler>
|
|
|
|
return;
|
|
80020b2: e119 b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
|
|
80020b4: 69bb ldr r3, [r7, #24]
|
|
80020b6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80020ba: 2b00 cmp r3, #0
|
|
80020bc: d013 beq.n 80020e6 <HAL_PCD_IRQHandler+0x58>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
|
|
80020be: 687b ldr r3, [r7, #4]
|
|
80020c0: 681b ldr r3, [r3, #0]
|
|
80020c2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80020c6: b29a uxth r2, r3
|
|
80020c8: 687b ldr r3, [r7, #4]
|
|
80020ca: 681b ldr r3, [r3, #0]
|
|
80020cc: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
80020d0: b292 uxth r2, r2
|
|
80020d2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
80020d6: 6878 ldr r0, [r7, #4]
|
|
80020d8: f007 fa1d bl 8009516 <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
(void)HAL_PCD_SetAddress(hpcd, 0U);
|
|
80020dc: 2100 movs r1, #0
|
|
80020de: 6878 ldr r0, [r7, #4]
|
|
80020e0: f000 f905 bl 80022ee <HAL_PCD_SetAddress>
|
|
|
|
return;
|
|
80020e4: e100 b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
|
|
80020e6: 69bb ldr r3, [r7, #24]
|
|
80020e8: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80020ec: 2b00 cmp r3, #0
|
|
80020ee: d00c beq.n 800210a <HAL_PCD_IRQHandler+0x7c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
|
|
80020f0: 687b ldr r3, [r7, #4]
|
|
80020f2: 681b ldr r3, [r3, #0]
|
|
80020f4: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80020f8: b29a uxth r2, r3
|
|
80020fa: 687b ldr r3, [r7, #4]
|
|
80020fc: 681b ldr r3, [r3, #0]
|
|
80020fe: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
8002102: b292 uxth r2, r2
|
|
8002104: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
8002108: e0ee b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
|
|
800210a: 69bb ldr r3, [r7, #24]
|
|
800210c: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8002110: 2b00 cmp r3, #0
|
|
8002112: d00c beq.n 800212e <HAL_PCD_IRQHandler+0xa0>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
|
|
8002114: 687b ldr r3, [r7, #4]
|
|
8002116: 681b ldr r3, [r3, #0]
|
|
8002118: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800211c: b29a uxth r2, r3
|
|
800211e: 687b ldr r3, [r7, #4]
|
|
8002120: 681b ldr r3, [r3, #0]
|
|
8002122: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8002126: b292 uxth r2, r2
|
|
8002128: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
800212c: e0dc b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
|
|
800212e: 69bb ldr r3, [r7, #24]
|
|
8002130: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8002134: 2b00 cmp r3, #0
|
|
8002136: d027 beq.n 8002188 <HAL_PCD_IRQHandler+0xfa>
|
|
{
|
|
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
|
|
8002138: 687b ldr r3, [r7, #4]
|
|
800213a: 681b ldr r3, [r3, #0]
|
|
800213c: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8002140: b29a uxth r2, r3
|
|
8002142: 687b ldr r3, [r7, #4]
|
|
8002144: 681b ldr r3, [r3, #0]
|
|
8002146: f022 0204 bic.w r2, r2, #4
|
|
800214a: b292 uxth r2, r2
|
|
800214c: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
|
|
8002150: 687b ldr r3, [r7, #4]
|
|
8002152: 681b ldr r3, [r3, #0]
|
|
8002154: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8002158: b29a uxth r2, r3
|
|
800215a: 687b ldr r3, [r7, #4]
|
|
800215c: 681b ldr r3, [r3, #0]
|
|
800215e: f022 0208 bic.w r2, r2, #8
|
|
8002162: b292 uxth r2, r2
|
|
8002164: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
8002168: 6878 ldr r0, [r7, #4]
|
|
800216a: f007 fa0d bl 8009588 <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
|
|
800216e: 687b ldr r3, [r7, #4]
|
|
8002170: 681b ldr r3, [r3, #0]
|
|
8002172: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
8002176: b29a uxth r2, r3
|
|
8002178: 687b ldr r3, [r7, #4]
|
|
800217a: 681b ldr r3, [r3, #0]
|
|
800217c: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8002180: b292 uxth r2, r2
|
|
8002182: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
8002186: e0af b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
|
|
8002188: 69bb ldr r3, [r7, #24]
|
|
800218a: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800218e: 2b00 cmp r3, #0
|
|
8002190: f000 8083 beq.w 800229a <HAL_PCD_IRQHandler+0x20c>
|
|
{
|
|
/* WA: To Clear Wakeup flag if raised with suspend signal */
|
|
|
|
/* Store Endpoint registers */
|
|
for (i = 0U; i < 8U; i++)
|
|
8002194: 2300 movs r3, #0
|
|
8002196: 77fb strb r3, [r7, #31]
|
|
8002198: e010 b.n 80021bc <HAL_PCD_IRQHandler+0x12e>
|
|
{
|
|
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
|
|
800219a: 687b ldr r3, [r7, #4]
|
|
800219c: 681b ldr r3, [r3, #0]
|
|
800219e: 461a mov r2, r3
|
|
80021a0: 7ffb ldrb r3, [r7, #31]
|
|
80021a2: 009b lsls r3, r3, #2
|
|
80021a4: 441a add r2, r3
|
|
80021a6: 7ffb ldrb r3, [r7, #31]
|
|
80021a8: 8812 ldrh r2, [r2, #0]
|
|
80021aa: b292 uxth r2, r2
|
|
80021ac: 005b lsls r3, r3, #1
|
|
80021ae: 3320 adds r3, #32
|
|
80021b0: 443b add r3, r7
|
|
80021b2: f823 2c18 strh.w r2, [r3, #-24]
|
|
for (i = 0U; i < 8U; i++)
|
|
80021b6: 7ffb ldrb r3, [r7, #31]
|
|
80021b8: 3301 adds r3, #1
|
|
80021ba: 77fb strb r3, [r7, #31]
|
|
80021bc: 7ffb ldrb r3, [r7, #31]
|
|
80021be: 2b07 cmp r3, #7
|
|
80021c0: d9eb bls.n 800219a <HAL_PCD_IRQHandler+0x10c>
|
|
}
|
|
|
|
/* FORCE RESET */
|
|
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
|
|
80021c2: 687b ldr r3, [r7, #4]
|
|
80021c4: 681b ldr r3, [r3, #0]
|
|
80021c6: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
80021ca: b29a uxth r2, r3
|
|
80021cc: 687b ldr r3, [r7, #4]
|
|
80021ce: 681b ldr r3, [r3, #0]
|
|
80021d0: f042 0201 orr.w r2, r2, #1
|
|
80021d4: b292 uxth r2, r2
|
|
80021d6: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* CLEAR RESET */
|
|
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
|
|
80021da: 687b ldr r3, [r7, #4]
|
|
80021dc: 681b ldr r3, [r3, #0]
|
|
80021de: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
80021e2: b29a uxth r2, r3
|
|
80021e4: 687b ldr r3, [r7, #4]
|
|
80021e6: 681b ldr r3, [r3, #0]
|
|
80021e8: f022 0201 bic.w r2, r2, #1
|
|
80021ec: b292 uxth r2, r2
|
|
80021ee: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* wait for reset flag in ISTR */
|
|
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
|
|
80021f2: bf00 nop
|
|
80021f4: 687b ldr r3, [r7, #4]
|
|
80021f6: 681b ldr r3, [r3, #0]
|
|
80021f8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80021fc: b29b uxth r3, r3
|
|
80021fe: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002202: 2b00 cmp r3, #0
|
|
8002204: d0f6 beq.n 80021f4 <HAL_PCD_IRQHandler+0x166>
|
|
{
|
|
}
|
|
|
|
/* Clear Reset Flag */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
|
|
8002206: 687b ldr r3, [r7, #4]
|
|
8002208: 681b ldr r3, [r3, #0]
|
|
800220a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800220e: b29a uxth r2, r3
|
|
8002210: 687b ldr r3, [r7, #4]
|
|
8002212: 681b ldr r3, [r3, #0]
|
|
8002214: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8002218: b292 uxth r2, r2
|
|
800221a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore Registre */
|
|
for (i = 0U; i < 8U; i++)
|
|
800221e: 2300 movs r3, #0
|
|
8002220: 77fb strb r3, [r7, #31]
|
|
8002222: e00f b.n 8002244 <HAL_PCD_IRQHandler+0x1b6>
|
|
{
|
|
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
|
|
8002224: 7ffb ldrb r3, [r7, #31]
|
|
8002226: 687a ldr r2, [r7, #4]
|
|
8002228: 6812 ldr r2, [r2, #0]
|
|
800222a: 4611 mov r1, r2
|
|
800222c: 7ffa ldrb r2, [r7, #31]
|
|
800222e: 0092 lsls r2, r2, #2
|
|
8002230: 440a add r2, r1
|
|
8002232: 005b lsls r3, r3, #1
|
|
8002234: 3320 adds r3, #32
|
|
8002236: 443b add r3, r7
|
|
8002238: f833 3c18 ldrh.w r3, [r3, #-24]
|
|
800223c: 8013 strh r3, [r2, #0]
|
|
for (i = 0U; i < 8U; i++)
|
|
800223e: 7ffb ldrb r3, [r7, #31]
|
|
8002240: 3301 adds r3, #1
|
|
8002242: 77fb strb r3, [r7, #31]
|
|
8002244: 7ffb ldrb r3, [r7, #31]
|
|
8002246: 2b07 cmp r3, #7
|
|
8002248: d9ec bls.n 8002224 <HAL_PCD_IRQHandler+0x196>
|
|
}
|
|
|
|
/* Force low-power mode in the macrocell */
|
|
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
|
|
800224a: 687b ldr r3, [r7, #4]
|
|
800224c: 681b ldr r3, [r3, #0]
|
|
800224e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8002252: b29a uxth r2, r3
|
|
8002254: 687b ldr r3, [r7, #4]
|
|
8002256: 681b ldr r3, [r3, #0]
|
|
8002258: f042 0208 orr.w r2, r2, #8
|
|
800225c: b292 uxth r2, r2
|
|
800225e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
|
|
8002262: 687b ldr r3, [r7, #4]
|
|
8002264: 681b ldr r3, [r3, #0]
|
|
8002266: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800226a: b29a uxth r2, r3
|
|
800226c: 687b ldr r3, [r7, #4]
|
|
800226e: 681b ldr r3, [r3, #0]
|
|
8002270: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8002274: b292 uxth r2, r2
|
|
8002276: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
|
|
800227a: 687b ldr r3, [r7, #4]
|
|
800227c: 681b ldr r3, [r3, #0]
|
|
800227e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8002282: b29a uxth r2, r3
|
|
8002284: 687b ldr r3, [r7, #4]
|
|
8002286: 681b ldr r3, [r3, #0]
|
|
8002288: f042 0204 orr.w r2, r2, #4
|
|
800228c: b292 uxth r2, r2
|
|
800228e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
8002292: 6878 ldr r0, [r7, #4]
|
|
8002294: f007 f95e bl 8009554 <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
return;
|
|
8002298: e026 b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
|
|
800229a: 69bb ldr r3, [r7, #24]
|
|
800229c: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80022a0: 2b00 cmp r3, #0
|
|
80022a2: d00f beq.n 80022c4 <HAL_PCD_IRQHandler+0x236>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
|
|
80022a4: 687b ldr r3, [r7, #4]
|
|
80022a6: 681b ldr r3, [r3, #0]
|
|
80022a8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80022ac: b29a uxth r2, r3
|
|
80022ae: 687b ldr r3, [r7, #4]
|
|
80022b0: 681b ldr r3, [r3, #0]
|
|
80022b2: f422 7200 bic.w r2, r2, #512 @ 0x200
|
|
80022b6: b292 uxth r2, r2
|
|
80022b8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
80022bc: 6878 ldr r0, [r7, #4]
|
|
80022be: f007 f91c bl 80094fa <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
return;
|
|
80022c2: e011 b.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
|
|
80022c4: 69bb ldr r3, [r7, #24]
|
|
80022c6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80022ca: 2b00 cmp r3, #0
|
|
80022cc: d00c beq.n 80022e8 <HAL_PCD_IRQHandler+0x25a>
|
|
{
|
|
/* clear ESOF flag in ISTR */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
|
|
80022ce: 687b ldr r3, [r7, #4]
|
|
80022d0: 681b ldr r3, [r3, #0]
|
|
80022d2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80022d6: b29a uxth r2, r3
|
|
80022d8: 687b ldr r3, [r7, #4]
|
|
80022da: 681b ldr r3, [r3, #0]
|
|
80022dc: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
80022e0: b292 uxth r2, r2
|
|
80022e2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
80022e6: bf00 nop
|
|
}
|
|
}
|
|
80022e8: 3720 adds r7, #32
|
|
80022ea: 46bd mov sp, r7
|
|
80022ec: bd80 pop {r7, pc}
|
|
|
|
080022ee <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
80022ee: b580 push {r7, lr}
|
|
80022f0: b082 sub sp, #8
|
|
80022f2: af00 add r7, sp, #0
|
|
80022f4: 6078 str r0, [r7, #4]
|
|
80022f6: 460b mov r3, r1
|
|
80022f8: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
80022fa: 687b ldr r3, [r7, #4]
|
|
80022fc: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8002300: 2b01 cmp r3, #1
|
|
8002302: d101 bne.n 8002308 <HAL_PCD_SetAddress+0x1a>
|
|
8002304: 2302 movs r3, #2
|
|
8002306: e012 b.n 800232e <HAL_PCD_SetAddress+0x40>
|
|
8002308: 687b ldr r3, [r7, #4]
|
|
800230a: 2201 movs r2, #1
|
|
800230c: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
hpcd->USB_Address = address;
|
|
8002310: 687b ldr r3, [r7, #4]
|
|
8002312: 78fa ldrb r2, [r7, #3]
|
|
8002314: 735a strb r2, [r3, #13]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
8002316: 687b ldr r3, [r7, #4]
|
|
8002318: 681b ldr r3, [r3, #0]
|
|
800231a: 78fa ldrb r2, [r7, #3]
|
|
800231c: 4611 mov r1, r2
|
|
800231e: 4618 mov r0, r3
|
|
8002320: f005 f9cc bl 80076bc <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002324: 687b ldr r3, [r7, #4]
|
|
8002326: 2200 movs r2, #0
|
|
8002328: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
800232c: 2300 movs r3, #0
|
|
}
|
|
800232e: 4618 mov r0, r3
|
|
8002330: 3708 adds r7, #8
|
|
8002332: 46bd mov sp, r7
|
|
8002334: bd80 pop {r7, pc}
|
|
|
|
08002336 <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
8002336: b580 push {r7, lr}
|
|
8002338: b084 sub sp, #16
|
|
800233a: af00 add r7, sp, #0
|
|
800233c: 6078 str r0, [r7, #4]
|
|
800233e: 4608 mov r0, r1
|
|
8002340: 4611 mov r1, r2
|
|
8002342: 461a mov r2, r3
|
|
8002344: 4603 mov r3, r0
|
|
8002346: 70fb strb r3, [r7, #3]
|
|
8002348: 460b mov r3, r1
|
|
800234a: 803b strh r3, [r7, #0]
|
|
800234c: 4613 mov r3, r2
|
|
800234e: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8002350: 2300 movs r3, #0
|
|
8002352: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8002354: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002358: 2b00 cmp r3, #0
|
|
800235a: da0e bge.n 800237a <HAL_PCD_EP_Open+0x44>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
800235c: 78fb ldrb r3, [r7, #3]
|
|
800235e: f003 0207 and.w r2, r3, #7
|
|
8002362: 4613 mov r3, r2
|
|
8002364: 009b lsls r3, r3, #2
|
|
8002366: 4413 add r3, r2
|
|
8002368: 00db lsls r3, r3, #3
|
|
800236a: 3310 adds r3, #16
|
|
800236c: 687a ldr r2, [r7, #4]
|
|
800236e: 4413 add r3, r2
|
|
8002370: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002372: 68fb ldr r3, [r7, #12]
|
|
8002374: 2201 movs r2, #1
|
|
8002376: 705a strb r2, [r3, #1]
|
|
8002378: e00e b.n 8002398 <HAL_PCD_EP_Open+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
800237a: 78fb ldrb r3, [r7, #3]
|
|
800237c: f003 0207 and.w r2, r3, #7
|
|
8002380: 4613 mov r3, r2
|
|
8002382: 009b lsls r3, r3, #2
|
|
8002384: 4413 add r3, r2
|
|
8002386: 00db lsls r3, r3, #3
|
|
8002388: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
800238c: 687a ldr r2, [r7, #4]
|
|
800238e: 4413 add r3, r2
|
|
8002390: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002392: 68fb ldr r3, [r7, #12]
|
|
8002394: 2200 movs r2, #0
|
|
8002396: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002398: 78fb ldrb r3, [r7, #3]
|
|
800239a: f003 0307 and.w r3, r3, #7
|
|
800239e: b2da uxtb r2, r3
|
|
80023a0: 68fb ldr r3, [r7, #12]
|
|
80023a2: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = ep_mps;
|
|
80023a4: 883a ldrh r2, [r7, #0]
|
|
80023a6: 68fb ldr r3, [r7, #12]
|
|
80023a8: 611a str r2, [r3, #16]
|
|
ep->type = ep_type;
|
|
80023aa: 68fb ldr r3, [r7, #12]
|
|
80023ac: 78ba ldrb r2, [r7, #2]
|
|
80023ae: 70da strb r2, [r3, #3]
|
|
ep->tx_fifo_num = ep->num;
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
80023b0: 78bb ldrb r3, [r7, #2]
|
|
80023b2: 2b02 cmp r3, #2
|
|
80023b4: d102 bne.n 80023bc <HAL_PCD_EP_Open+0x86>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
80023b6: 68fb ldr r3, [r7, #12]
|
|
80023b8: 2200 movs r2, #0
|
|
80023ba: 711a strb r2, [r3, #4]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80023bc: 687b ldr r3, [r7, #4]
|
|
80023be: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
80023c2: 2b01 cmp r3, #1
|
|
80023c4: d101 bne.n 80023ca <HAL_PCD_EP_Open+0x94>
|
|
80023c6: 2302 movs r3, #2
|
|
80023c8: e00e b.n 80023e8 <HAL_PCD_EP_Open+0xb2>
|
|
80023ca: 687b ldr r3, [r7, #4]
|
|
80023cc: 2201 movs r2, #1
|
|
80023ce: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
80023d2: 687b ldr r3, [r7, #4]
|
|
80023d4: 681b ldr r3, [r3, #0]
|
|
80023d6: 68f9 ldr r1, [r7, #12]
|
|
80023d8: 4618 mov r0, r3
|
|
80023da: f002 ff15 bl 8005208 <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
80023de: 687b ldr r3, [r7, #4]
|
|
80023e0: 2200 movs r2, #0
|
|
80023e2: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return ret;
|
|
80023e6: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80023e8: 4618 mov r0, r3
|
|
80023ea: 3710 adds r7, #16
|
|
80023ec: 46bd mov sp, r7
|
|
80023ee: bd80 pop {r7, pc}
|
|
|
|
080023f0 <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
80023f0: b580 push {r7, lr}
|
|
80023f2: b084 sub sp, #16
|
|
80023f4: af00 add r7, sp, #0
|
|
80023f6: 6078 str r0, [r7, #4]
|
|
80023f8: 460b mov r3, r1
|
|
80023fa: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
80023fc: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002400: 2b00 cmp r3, #0
|
|
8002402: da0e bge.n 8002422 <HAL_PCD_EP_Close+0x32>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002404: 78fb ldrb r3, [r7, #3]
|
|
8002406: f003 0207 and.w r2, r3, #7
|
|
800240a: 4613 mov r3, r2
|
|
800240c: 009b lsls r3, r3, #2
|
|
800240e: 4413 add r3, r2
|
|
8002410: 00db lsls r3, r3, #3
|
|
8002412: 3310 adds r3, #16
|
|
8002414: 687a ldr r2, [r7, #4]
|
|
8002416: 4413 add r3, r2
|
|
8002418: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
800241a: 68fb ldr r3, [r7, #12]
|
|
800241c: 2201 movs r2, #1
|
|
800241e: 705a strb r2, [r3, #1]
|
|
8002420: e00e b.n 8002440 <HAL_PCD_EP_Close+0x50>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002422: 78fb ldrb r3, [r7, #3]
|
|
8002424: f003 0207 and.w r2, r3, #7
|
|
8002428: 4613 mov r3, r2
|
|
800242a: 009b lsls r3, r3, #2
|
|
800242c: 4413 add r3, r2
|
|
800242e: 00db lsls r3, r3, #3
|
|
8002430: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8002434: 687a ldr r2, [r7, #4]
|
|
8002436: 4413 add r3, r2
|
|
8002438: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
800243a: 68fb ldr r3, [r7, #12]
|
|
800243c: 2200 movs r2, #0
|
|
800243e: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002440: 78fb ldrb r3, [r7, #3]
|
|
8002442: f003 0307 and.w r3, r3, #7
|
|
8002446: b2da uxtb r2, r3
|
|
8002448: 68fb ldr r3, [r7, #12]
|
|
800244a: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
800244c: 687b ldr r3, [r7, #4]
|
|
800244e: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8002452: 2b01 cmp r3, #1
|
|
8002454: d101 bne.n 800245a <HAL_PCD_EP_Close+0x6a>
|
|
8002456: 2302 movs r3, #2
|
|
8002458: e00e b.n 8002478 <HAL_PCD_EP_Close+0x88>
|
|
800245a: 687b ldr r3, [r7, #4]
|
|
800245c: 2201 movs r2, #1
|
|
800245e: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8002462: 687b ldr r3, [r7, #4]
|
|
8002464: 681b ldr r3, [r3, #0]
|
|
8002466: 68f9 ldr r1, [r7, #12]
|
|
8002468: 4618 mov r0, r3
|
|
800246a: f003 fa8d bl 8005988 <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
800246e: 687b ldr r3, [r7, #4]
|
|
8002470: 2200 movs r2, #0
|
|
8002472: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
return HAL_OK;
|
|
8002476: 2300 movs r3, #0
|
|
}
|
|
8002478: 4618 mov r0, r3
|
|
800247a: 3710 adds r7, #16
|
|
800247c: 46bd mov sp, r7
|
|
800247e: bd80 pop {r7, pc}
|
|
|
|
08002480 <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8002480: b580 push {r7, lr}
|
|
8002482: b086 sub sp, #24
|
|
8002484: af00 add r7, sp, #0
|
|
8002486: 60f8 str r0, [r7, #12]
|
|
8002488: 607a str r2, [r7, #4]
|
|
800248a: 603b str r3, [r7, #0]
|
|
800248c: 460b mov r3, r1
|
|
800248e: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002490: 7afb ldrb r3, [r7, #11]
|
|
8002492: f003 0207 and.w r2, r3, #7
|
|
8002496: 4613 mov r3, r2
|
|
8002498: 009b lsls r3, r3, #2
|
|
800249a: 4413 add r3, r2
|
|
800249c: 00db lsls r3, r3, #3
|
|
800249e: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80024a2: 68fa ldr r2, [r7, #12]
|
|
80024a4: 4413 add r3, r2
|
|
80024a6: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
80024a8: 697b ldr r3, [r7, #20]
|
|
80024aa: 687a ldr r2, [r7, #4]
|
|
80024ac: 615a str r2, [r3, #20]
|
|
ep->xfer_len = len;
|
|
80024ae: 697b ldr r3, [r7, #20]
|
|
80024b0: 683a ldr r2, [r7, #0]
|
|
80024b2: 619a str r2, [r3, #24]
|
|
ep->xfer_count = 0U;
|
|
80024b4: 697b ldr r3, [r7, #20]
|
|
80024b6: 2200 movs r2, #0
|
|
80024b8: 61da str r2, [r3, #28]
|
|
ep->is_in = 0U;
|
|
80024ba: 697b ldr r3, [r7, #20]
|
|
80024bc: 2200 movs r2, #0
|
|
80024be: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80024c0: 7afb ldrb r3, [r7, #11]
|
|
80024c2: f003 0307 and.w r3, r3, #7
|
|
80024c6: b2da uxtb r2, r3
|
|
80024c8: 697b ldr r3, [r7, #20]
|
|
80024ca: 701a strb r2, [r3, #0]
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
80024cc: 68fb ldr r3, [r7, #12]
|
|
80024ce: 681b ldr r3, [r3, #0]
|
|
80024d0: 6979 ldr r1, [r7, #20]
|
|
80024d2: 4618 mov r0, r3
|
|
80024d4: f003 fc44 bl 8005d60 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
80024d8: 2300 movs r3, #0
|
|
}
|
|
80024da: 4618 mov r0, r3
|
|
80024dc: 3718 adds r7, #24
|
|
80024de: 46bd mov sp, r7
|
|
80024e0: bd80 pop {r7, pc}
|
|
|
|
080024e2 <HAL_PCD_EP_GetRxCount>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval Data Size
|
|
*/
|
|
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
|
|
{
|
|
80024e2: b480 push {r7}
|
|
80024e4: b083 sub sp, #12
|
|
80024e6: af00 add r7, sp, #0
|
|
80024e8: 6078 str r0, [r7, #4]
|
|
80024ea: 460b mov r3, r1
|
|
80024ec: 70fb strb r3, [r7, #3]
|
|
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
|
|
80024ee: 78fb ldrb r3, [r7, #3]
|
|
80024f0: f003 0207 and.w r2, r3, #7
|
|
80024f4: 6879 ldr r1, [r7, #4]
|
|
80024f6: 4613 mov r3, r2
|
|
80024f8: 009b lsls r3, r3, #2
|
|
80024fa: 4413 add r3, r2
|
|
80024fc: 00db lsls r3, r3, #3
|
|
80024fe: 440b add r3, r1
|
|
8002500: f503 73b6 add.w r3, r3, #364 @ 0x16c
|
|
8002504: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002506: 4618 mov r0, r3
|
|
8002508: 370c adds r7, #12
|
|
800250a: 46bd mov sp, r7
|
|
800250c: bc80 pop {r7}
|
|
800250e: 4770 bx lr
|
|
|
|
08002510 <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8002510: b580 push {r7, lr}
|
|
8002512: b086 sub sp, #24
|
|
8002514: af00 add r7, sp, #0
|
|
8002516: 60f8 str r0, [r7, #12]
|
|
8002518: 607a str r2, [r7, #4]
|
|
800251a: 603b str r3, [r7, #0]
|
|
800251c: 460b mov r3, r1
|
|
800251e: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002520: 7afb ldrb r3, [r7, #11]
|
|
8002522: f003 0207 and.w r2, r3, #7
|
|
8002526: 4613 mov r3, r2
|
|
8002528: 009b lsls r3, r3, #2
|
|
800252a: 4413 add r3, r2
|
|
800252c: 00db lsls r3, r3, #3
|
|
800252e: 3310 adds r3, #16
|
|
8002530: 68fa ldr r2, [r7, #12]
|
|
8002532: 4413 add r3, r2
|
|
8002534: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8002536: 697b ldr r3, [r7, #20]
|
|
8002538: 687a ldr r2, [r7, #4]
|
|
800253a: 615a str r2, [r3, #20]
|
|
ep->xfer_len = len;
|
|
800253c: 697b ldr r3, [r7, #20]
|
|
800253e: 683a ldr r2, [r7, #0]
|
|
8002540: 619a str r2, [r3, #24]
|
|
#if defined (USB)
|
|
ep->xfer_fill_db = 1U;
|
|
8002542: 697b ldr r3, [r7, #20]
|
|
8002544: 2201 movs r2, #1
|
|
8002546: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
ep->xfer_len_db = len;
|
|
800254a: 697b ldr r3, [r7, #20]
|
|
800254c: 683a ldr r2, [r7, #0]
|
|
800254e: 621a str r2, [r3, #32]
|
|
#endif /* defined (USB) */
|
|
ep->xfer_count = 0U;
|
|
8002550: 697b ldr r3, [r7, #20]
|
|
8002552: 2200 movs r2, #0
|
|
8002554: 61da str r2, [r3, #28]
|
|
ep->is_in = 1U;
|
|
8002556: 697b ldr r3, [r7, #20]
|
|
8002558: 2201 movs r2, #1
|
|
800255a: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
800255c: 7afb ldrb r3, [r7, #11]
|
|
800255e: f003 0307 and.w r3, r3, #7
|
|
8002562: b2da uxtb r2, r3
|
|
8002564: 697b ldr r3, [r7, #20]
|
|
8002566: 701a strb r2, [r3, #0]
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
8002568: 68fb ldr r3, [r7, #12]
|
|
800256a: 681b ldr r3, [r3, #0]
|
|
800256c: 6979 ldr r1, [r7, #20]
|
|
800256e: 4618 mov r0, r3
|
|
8002570: f003 fbf6 bl 8005d60 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8002574: 2300 movs r3, #0
|
|
}
|
|
8002576: 4618 mov r0, r3
|
|
8002578: 3718 adds r7, #24
|
|
800257a: 46bd mov sp, r7
|
|
800257c: bd80 pop {r7, pc}
|
|
|
|
0800257e <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
800257e: b580 push {r7, lr}
|
|
8002580: b084 sub sp, #16
|
|
8002582: af00 add r7, sp, #0
|
|
8002584: 6078 str r0, [r7, #4]
|
|
8002586: 460b mov r3, r1
|
|
8002588: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
800258a: 78fb ldrb r3, [r7, #3]
|
|
800258c: f003 0307 and.w r3, r3, #7
|
|
8002590: 687a ldr r2, [r7, #4]
|
|
8002592: 7912 ldrb r2, [r2, #4]
|
|
8002594: 4293 cmp r3, r2
|
|
8002596: d901 bls.n 800259c <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002598: 2301 movs r3, #1
|
|
800259a: e04c b.n 8002636 <HAL_PCD_EP_SetStall+0xb8>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
800259c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
80025a0: 2b00 cmp r3, #0
|
|
80025a2: da0e bge.n 80025c2 <HAL_PCD_EP_SetStall+0x44>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
80025a4: 78fb ldrb r3, [r7, #3]
|
|
80025a6: f003 0207 and.w r2, r3, #7
|
|
80025aa: 4613 mov r3, r2
|
|
80025ac: 009b lsls r3, r3, #2
|
|
80025ae: 4413 add r3, r2
|
|
80025b0: 00db lsls r3, r3, #3
|
|
80025b2: 3310 adds r3, #16
|
|
80025b4: 687a ldr r2, [r7, #4]
|
|
80025b6: 4413 add r3, r2
|
|
80025b8: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
80025ba: 68fb ldr r3, [r7, #12]
|
|
80025bc: 2201 movs r2, #1
|
|
80025be: 705a strb r2, [r3, #1]
|
|
80025c0: e00c b.n 80025dc <HAL_PCD_EP_SetStall+0x5e>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
80025c2: 78fa ldrb r2, [r7, #3]
|
|
80025c4: 4613 mov r3, r2
|
|
80025c6: 009b lsls r3, r3, #2
|
|
80025c8: 4413 add r3, r2
|
|
80025ca: 00db lsls r3, r3, #3
|
|
80025cc: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80025d0: 687a ldr r2, [r7, #4]
|
|
80025d2: 4413 add r3, r2
|
|
80025d4: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
80025d6: 68fb ldr r3, [r7, #12]
|
|
80025d8: 2200 movs r2, #0
|
|
80025da: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
80025dc: 68fb ldr r3, [r7, #12]
|
|
80025de: 2201 movs r2, #1
|
|
80025e0: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80025e2: 78fb ldrb r3, [r7, #3]
|
|
80025e4: f003 0307 and.w r3, r3, #7
|
|
80025e8: b2da uxtb r2, r3
|
|
80025ea: 68fb ldr r3, [r7, #12]
|
|
80025ec: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80025ee: 687b ldr r3, [r7, #4]
|
|
80025f0: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
80025f4: 2b01 cmp r3, #1
|
|
80025f6: d101 bne.n 80025fc <HAL_PCD_EP_SetStall+0x7e>
|
|
80025f8: 2302 movs r3, #2
|
|
80025fa: e01c b.n 8002636 <HAL_PCD_EP_SetStall+0xb8>
|
|
80025fc: 687b ldr r3, [r7, #4]
|
|
80025fe: 2201 movs r2, #1
|
|
8002600: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
8002604: 687b ldr r3, [r7, #4]
|
|
8002606: 681b ldr r3, [r3, #0]
|
|
8002608: 68f9 ldr r1, [r7, #12]
|
|
800260a: 4618 mov r0, r3
|
|
800260c: f004 ff59 bl 80074c2 <USB_EPSetStall>
|
|
|
|
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
|
8002610: 78fb ldrb r3, [r7, #3]
|
|
8002612: f003 0307 and.w r3, r3, #7
|
|
8002616: 2b00 cmp r3, #0
|
|
8002618: d108 bne.n 800262c <HAL_PCD_EP_SetStall+0xae>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
|
|
800261a: 687b ldr r3, [r7, #4]
|
|
800261c: 681a ldr r2, [r3, #0]
|
|
800261e: 687b ldr r3, [r7, #4]
|
|
8002620: f503 7326 add.w r3, r3, #664 @ 0x298
|
|
8002624: 4619 mov r1, r3
|
|
8002626: 4610 mov r0, r2
|
|
8002628: f005 f87e bl 8007728 <USB_EP0_OutStart>
|
|
}
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
800262c: 687b ldr r3, [r7, #4]
|
|
800262e: 2200 movs r2, #0
|
|
8002630: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
8002634: 2300 movs r3, #0
|
|
}
|
|
8002636: 4618 mov r0, r3
|
|
8002638: 3710 adds r7, #16
|
|
800263a: 46bd mov sp, r7
|
|
800263c: bd80 pop {r7, pc}
|
|
|
|
0800263e <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
800263e: b580 push {r7, lr}
|
|
8002640: b084 sub sp, #16
|
|
8002642: af00 add r7, sp, #0
|
|
8002644: 6078 str r0, [r7, #4]
|
|
8002646: 460b mov r3, r1
|
|
8002648: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
800264a: 78fb ldrb r3, [r7, #3]
|
|
800264c: f003 030f and.w r3, r3, #15
|
|
8002650: 687a ldr r2, [r7, #4]
|
|
8002652: 7912 ldrb r2, [r2, #4]
|
|
8002654: 4293 cmp r3, r2
|
|
8002656: d901 bls.n 800265c <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002658: 2301 movs r3, #1
|
|
800265a: e040 b.n 80026de <HAL_PCD_EP_ClrStall+0xa0>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
800265c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002660: 2b00 cmp r3, #0
|
|
8002662: da0e bge.n 8002682 <HAL_PCD_EP_ClrStall+0x44>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002664: 78fb ldrb r3, [r7, #3]
|
|
8002666: f003 0207 and.w r2, r3, #7
|
|
800266a: 4613 mov r3, r2
|
|
800266c: 009b lsls r3, r3, #2
|
|
800266e: 4413 add r3, r2
|
|
8002670: 00db lsls r3, r3, #3
|
|
8002672: 3310 adds r3, #16
|
|
8002674: 687a ldr r2, [r7, #4]
|
|
8002676: 4413 add r3, r2
|
|
8002678: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
800267a: 68fb ldr r3, [r7, #12]
|
|
800267c: 2201 movs r2, #1
|
|
800267e: 705a strb r2, [r3, #1]
|
|
8002680: e00e b.n 80026a0 <HAL_PCD_EP_ClrStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002682: 78fb ldrb r3, [r7, #3]
|
|
8002684: f003 0207 and.w r2, r3, #7
|
|
8002688: 4613 mov r3, r2
|
|
800268a: 009b lsls r3, r3, #2
|
|
800268c: 4413 add r3, r2
|
|
800268e: 00db lsls r3, r3, #3
|
|
8002690: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8002694: 687a ldr r2, [r7, #4]
|
|
8002696: 4413 add r3, r2
|
|
8002698: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
800269a: 68fb ldr r3, [r7, #12]
|
|
800269c: 2200 movs r2, #0
|
|
800269e: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
80026a0: 68fb ldr r3, [r7, #12]
|
|
80026a2: 2200 movs r2, #0
|
|
80026a4: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80026a6: 78fb ldrb r3, [r7, #3]
|
|
80026a8: f003 0307 and.w r3, r3, #7
|
|
80026ac: b2da uxtb r2, r3
|
|
80026ae: 68fb ldr r3, [r7, #12]
|
|
80026b0: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80026b2: 687b ldr r3, [r7, #4]
|
|
80026b4: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
80026b8: 2b01 cmp r3, #1
|
|
80026ba: d101 bne.n 80026c0 <HAL_PCD_EP_ClrStall+0x82>
|
|
80026bc: 2302 movs r3, #2
|
|
80026be: e00e b.n 80026de <HAL_PCD_EP_ClrStall+0xa0>
|
|
80026c0: 687b ldr r3, [r7, #4]
|
|
80026c2: 2201 movs r2, #1
|
|
80026c4: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
80026c8: 687b ldr r3, [r7, #4]
|
|
80026ca: 681b ldr r3, [r3, #0]
|
|
80026cc: 68f9 ldr r1, [r7, #12]
|
|
80026ce: 4618 mov r0, r3
|
|
80026d0: f004 ff47 bl 8007562 <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
80026d4: 687b ldr r3, [r7, #4]
|
|
80026d6: 2200 movs r2, #0
|
|
80026d8: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
80026dc: 2300 movs r3, #0
|
|
}
|
|
80026de: 4618 mov r0, r3
|
|
80026e0: 3710 adds r7, #16
|
|
80026e2: 46bd mov sp, r7
|
|
80026e4: bd80 pop {r7, pc}
|
|
|
|
080026e6 <PCD_EP_ISR_Handler>:
|
|
* @brief This function handles PCD Endpoint interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80026e6: b580 push {r7, lr}
|
|
80026e8: b096 sub sp, #88 @ 0x58
|
|
80026ea: af00 add r7, sp, #0
|
|
80026ec: 6078 str r0, [r7, #4]
|
|
#if (USE_USB_DOUBLE_BUFFER != 1U)
|
|
count = 0U;
|
|
#endif /* USE_USB_DOUBLE_BUFFER */
|
|
|
|
/* stay in loop while pending interrupts */
|
|
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
|
|
80026ee: e3bb b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
{
|
|
wIstr = hpcd->Instance->ISTR;
|
|
80026f0: 687b ldr r3, [r7, #4]
|
|
80026f2: 681b ldr r3, [r3, #0]
|
|
80026f4: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80026f8: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
|
|
/* extract highest priority endpoint number */
|
|
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
|
|
80026fc: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
8002700: b2db uxtb r3, r3
|
|
8002702: f003 030f and.w r3, r3, #15
|
|
8002706: f887 304d strb.w r3, [r7, #77] @ 0x4d
|
|
|
|
if (epindex == 0U)
|
|
800270a: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
800270e: 2b00 cmp r3, #0
|
|
8002710: f040 8175 bne.w 80029fe <PCD_EP_ISR_Handler+0x318>
|
|
{
|
|
/* Decode and service control endpoint interrupt */
|
|
|
|
/* DIR bit = origin of the interrupt */
|
|
if ((wIstr & USB_ISTR_DIR) == 0U)
|
|
8002714: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
8002718: f003 0310 and.w r3, r3, #16
|
|
800271c: 2b00 cmp r3, #0
|
|
800271e: d14e bne.n 80027be <PCD_EP_ISR_Handler+0xd8>
|
|
{
|
|
/* DIR = 0 */
|
|
|
|
/* DIR = 0 => IN int */
|
|
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
|
|
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8002720: 687b ldr r3, [r7, #4]
|
|
8002722: 681b ldr r3, [r3, #0]
|
|
8002724: 881b ldrh r3, [r3, #0]
|
|
8002726: b29b uxth r3, r3
|
|
8002728: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
|
|
800272c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8002730: 81fb strh r3, [r7, #14]
|
|
8002732: 687b ldr r3, [r7, #4]
|
|
8002734: 681a ldr r2, [r3, #0]
|
|
8002736: 89fb ldrh r3, [r7, #14]
|
|
8002738: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800273c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8002740: b29b uxth r3, r3
|
|
8002742: 8013 strh r3, [r2, #0]
|
|
ep = &hpcd->IN_ep[0];
|
|
8002744: 687b ldr r3, [r7, #4]
|
|
8002746: 3310 adds r3, #16
|
|
8002748: 657b str r3, [r7, #84] @ 0x54
|
|
|
|
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
|
800274a: 687b ldr r3, [r7, #4]
|
|
800274c: 681b ldr r3, [r3, #0]
|
|
800274e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002752: b29b uxth r3, r3
|
|
8002754: 461a mov r2, r3
|
|
8002756: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002758: 781b ldrb r3, [r3, #0]
|
|
800275a: 00db lsls r3, r3, #3
|
|
800275c: 4413 add r3, r2
|
|
800275e: 3302 adds r3, #2
|
|
8002760: 005b lsls r3, r3, #1
|
|
8002762: 687a ldr r2, [r7, #4]
|
|
8002764: 6812 ldr r2, [r2, #0]
|
|
8002766: 4413 add r3, r2
|
|
8002768: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800276c: 881b ldrh r3, [r3, #0]
|
|
800276e: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8002772: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002774: 61da str r2, [r3, #28]
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8002776: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002778: 695a ldr r2, [r3, #20]
|
|
800277a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800277c: 69db ldr r3, [r3, #28]
|
|
800277e: 441a add r2, r3
|
|
8002780: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002782: 615a str r2, [r3, #20]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, 0U);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, 0U);
|
|
8002784: 2100 movs r1, #0
|
|
8002786: 6878 ldr r0, [r7, #4]
|
|
8002788: f006 fe9d bl 80094c6 <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
|
|
800278c: 687b ldr r3, [r7, #4]
|
|
800278e: 7b5b ldrb r3, [r3, #13]
|
|
8002790: b2db uxtb r3, r3
|
|
8002792: 2b00 cmp r3, #0
|
|
8002794: f000 8368 beq.w 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
8002798: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800279a: 699b ldr r3, [r3, #24]
|
|
800279c: 2b00 cmp r3, #0
|
|
800279e: f040 8363 bne.w 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
{
|
|
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
|
|
80027a2: 687b ldr r3, [r7, #4]
|
|
80027a4: 7b5b ldrb r3, [r3, #13]
|
|
80027a6: b2db uxtb r3, r3
|
|
80027a8: f063 037f orn r3, r3, #127 @ 0x7f
|
|
80027ac: b2da uxtb r2, r3
|
|
80027ae: 687b ldr r3, [r7, #4]
|
|
80027b0: 681b ldr r3, [r3, #0]
|
|
80027b2: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
|
|
hpcd->USB_Address = 0U;
|
|
80027b6: 687b ldr r3, [r7, #4]
|
|
80027b8: 2200 movs r2, #0
|
|
80027ba: 735a strb r2, [r3, #13]
|
|
80027bc: e354 b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
{
|
|
/* DIR = 1 */
|
|
|
|
/* DIR = 1 & CTR_RX => SETUP or OUT int */
|
|
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
|
|
ep = &hpcd->OUT_ep[0];
|
|
80027be: 687b ldr r3, [r7, #4]
|
|
80027c0: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80027c4: 657b str r3, [r7, #84] @ 0x54
|
|
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
|
|
80027c6: 687b ldr r3, [r7, #4]
|
|
80027c8: 681b ldr r3, [r3, #0]
|
|
80027ca: 881b ldrh r3, [r3, #0]
|
|
80027cc: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
|
|
|
|
if ((wEPVal & USB_EP_SETUP) != 0U)
|
|
80027d0: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
80027d4: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80027d8: 2b00 cmp r3, #0
|
|
80027da: d034 beq.n 8002846 <PCD_EP_ISR_Handler+0x160>
|
|
{
|
|
/* Get SETUP Packet */
|
|
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
|
80027dc: 687b ldr r3, [r7, #4]
|
|
80027de: 681b ldr r3, [r3, #0]
|
|
80027e0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80027e4: b29b uxth r3, r3
|
|
80027e6: 461a mov r2, r3
|
|
80027e8: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80027ea: 781b ldrb r3, [r3, #0]
|
|
80027ec: 00db lsls r3, r3, #3
|
|
80027ee: 4413 add r3, r2
|
|
80027f0: 3306 adds r3, #6
|
|
80027f2: 005b lsls r3, r3, #1
|
|
80027f4: 687a ldr r2, [r7, #4]
|
|
80027f6: 6812 ldr r2, [r2, #0]
|
|
80027f8: 4413 add r3, r2
|
|
80027fa: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80027fe: 881b ldrh r3, [r3, #0]
|
|
8002800: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8002804: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002806: 61da str r2, [r3, #28]
|
|
|
|
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
|
|
8002808: 687b ldr r3, [r7, #4]
|
|
800280a: 6818 ldr r0, [r3, #0]
|
|
800280c: 687b ldr r3, [r7, #4]
|
|
800280e: f503 7126 add.w r1, r3, #664 @ 0x298
|
|
8002812: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002814: 88da ldrh r2, [r3, #6]
|
|
ep->pmaadress, (uint16_t)ep->xfer_count);
|
|
8002816: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002818: 69db ldr r3, [r3, #28]
|
|
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
|
|
800281a: b29b uxth r3, r3
|
|
800281c: f004 ffd5 bl 80077ca <USB_ReadPMA>
|
|
|
|
/* SETUP bit kept frozen while CTR_RX = 1 */
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8002820: 687b ldr r3, [r7, #4]
|
|
8002822: 681b ldr r3, [r3, #0]
|
|
8002824: 881b ldrh r3, [r3, #0]
|
|
8002826: b29a uxth r2, r3
|
|
8002828: f640 738f movw r3, #3983 @ 0xf8f
|
|
800282c: 4013 ands r3, r2
|
|
800282e: 823b strh r3, [r7, #16]
|
|
8002830: 687b ldr r3, [r7, #4]
|
|
8002832: 681b ldr r3, [r3, #0]
|
|
8002834: 8a3a ldrh r2, [r7, #16]
|
|
8002836: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
800283a: b292 uxth r2, r2
|
|
800283c: 801a strh r2, [r3, #0]
|
|
|
|
/* Process SETUP Packet*/
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
800283e: 6878 ldr r0, [r7, #4]
|
|
8002840: f006 fe14 bl 800946c <HAL_PCD_SetupStageCallback>
|
|
8002844: e310 b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
|
|
8002846: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
|
|
800284a: 2b00 cmp r3, #0
|
|
800284c: f280 830c bge.w 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
{
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8002850: 687b ldr r3, [r7, #4]
|
|
8002852: 681b ldr r3, [r3, #0]
|
|
8002854: 881b ldrh r3, [r3, #0]
|
|
8002856: b29a uxth r2, r3
|
|
8002858: f640 738f movw r3, #3983 @ 0xf8f
|
|
800285c: 4013 ands r3, r2
|
|
800285e: 83fb strh r3, [r7, #30]
|
|
8002860: 687b ldr r3, [r7, #4]
|
|
8002862: 681b ldr r3, [r3, #0]
|
|
8002864: 8bfa ldrh r2, [r7, #30]
|
|
8002866: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
800286a: b292 uxth r2, r2
|
|
800286c: 801a strh r2, [r3, #0]
|
|
|
|
/* Get Control Data OUT Packet */
|
|
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
|
800286e: 687b ldr r3, [r7, #4]
|
|
8002870: 681b ldr r3, [r3, #0]
|
|
8002872: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002876: b29b uxth r3, r3
|
|
8002878: 461a mov r2, r3
|
|
800287a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800287c: 781b ldrb r3, [r3, #0]
|
|
800287e: 00db lsls r3, r3, #3
|
|
8002880: 4413 add r3, r2
|
|
8002882: 3306 adds r3, #6
|
|
8002884: 005b lsls r3, r3, #1
|
|
8002886: 687a ldr r2, [r7, #4]
|
|
8002888: 6812 ldr r2, [r2, #0]
|
|
800288a: 4413 add r3, r2
|
|
800288c: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002890: 881b ldrh r3, [r3, #0]
|
|
8002892: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8002896: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002898: 61da str r2, [r3, #28]
|
|
|
|
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
|
|
800289a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800289c: 69db ldr r3, [r3, #28]
|
|
800289e: 2b00 cmp r3, #0
|
|
80028a0: d019 beq.n 80028d6 <PCD_EP_ISR_Handler+0x1f0>
|
|
80028a2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028a4: 695b ldr r3, [r3, #20]
|
|
80028a6: 2b00 cmp r3, #0
|
|
80028a8: d015 beq.n 80028d6 <PCD_EP_ISR_Handler+0x1f0>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
|
|
80028aa: 687b ldr r3, [r7, #4]
|
|
80028ac: 6818 ldr r0, [r3, #0]
|
|
80028ae: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028b0: 6959 ldr r1, [r3, #20]
|
|
80028b2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028b4: 88da ldrh r2, [r3, #6]
|
|
ep->pmaadress, (uint16_t)ep->xfer_count);
|
|
80028b6: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028b8: 69db ldr r3, [r3, #28]
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
|
|
80028ba: b29b uxth r3, r3
|
|
80028bc: f004 ff85 bl 80077ca <USB_ReadPMA>
|
|
|
|
ep->xfer_buff += ep->xfer_count;
|
|
80028c0: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028c2: 695a ldr r2, [r3, #20]
|
|
80028c4: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028c6: 69db ldr r3, [r3, #28]
|
|
80028c8: 441a add r2, r3
|
|
80028ca: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80028cc: 615a str r2, [r3, #20]
|
|
|
|
/* Process Control Data OUT Packet */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, 0U);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, 0U);
|
|
80028ce: 2100 movs r1, #0
|
|
80028d0: 6878 ldr r0, [r7, #4]
|
|
80028d2: f006 fddd bl 8009490 <HAL_PCD_DataOutStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
|
|
80028d6: 687b ldr r3, [r7, #4]
|
|
80028d8: 681b ldr r3, [r3, #0]
|
|
80028da: 881b ldrh r3, [r3, #0]
|
|
80028dc: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
|
|
|
|
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
|
|
80028e0: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
80028e4: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80028e8: 2b00 cmp r3, #0
|
|
80028ea: f040 82bd bne.w 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
80028ee: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
80028f2: f403 5340 and.w r3, r3, #12288 @ 0x3000
|
|
80028f6: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
|
|
80028fa: f000 82b5 beq.w 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
{
|
|
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
|
|
80028fe: 687b ldr r3, [r7, #4]
|
|
8002900: 681b ldr r3, [r3, #0]
|
|
8002902: 61bb str r3, [r7, #24]
|
|
8002904: 687b ldr r3, [r7, #4]
|
|
8002906: 681b ldr r3, [r3, #0]
|
|
8002908: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800290c: b29b uxth r3, r3
|
|
800290e: 461a mov r2, r3
|
|
8002910: 69bb ldr r3, [r7, #24]
|
|
8002912: 4413 add r3, r2
|
|
8002914: 61bb str r3, [r7, #24]
|
|
8002916: 69bb ldr r3, [r7, #24]
|
|
8002918: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
800291c: 617b str r3, [r7, #20]
|
|
800291e: 697b ldr r3, [r7, #20]
|
|
8002920: 881b ldrh r3, [r3, #0]
|
|
8002922: b29b uxth r3, r3
|
|
8002924: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002928: b29a uxth r2, r3
|
|
800292a: 697b ldr r3, [r7, #20]
|
|
800292c: 801a strh r2, [r3, #0]
|
|
800292e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002930: 691b ldr r3, [r3, #16]
|
|
8002932: 2b3e cmp r3, #62 @ 0x3e
|
|
8002934: d91d bls.n 8002972 <PCD_EP_ISR_Handler+0x28c>
|
|
8002936: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002938: 691b ldr r3, [r3, #16]
|
|
800293a: 095b lsrs r3, r3, #5
|
|
800293c: 647b str r3, [r7, #68] @ 0x44
|
|
800293e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002940: 691b ldr r3, [r3, #16]
|
|
8002942: f003 031f and.w r3, r3, #31
|
|
8002946: 2b00 cmp r3, #0
|
|
8002948: d102 bne.n 8002950 <PCD_EP_ISR_Handler+0x26a>
|
|
800294a: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800294c: 3b01 subs r3, #1
|
|
800294e: 647b str r3, [r7, #68] @ 0x44
|
|
8002950: 697b ldr r3, [r7, #20]
|
|
8002952: 881b ldrh r3, [r3, #0]
|
|
8002954: b29a uxth r2, r3
|
|
8002956: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8002958: b29b uxth r3, r3
|
|
800295a: 029b lsls r3, r3, #10
|
|
800295c: b29b uxth r3, r3
|
|
800295e: 4313 orrs r3, r2
|
|
8002960: b29b uxth r3, r3
|
|
8002962: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8002966: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800296a: b29a uxth r2, r3
|
|
800296c: 697b ldr r3, [r7, #20]
|
|
800296e: 801a strh r2, [r3, #0]
|
|
8002970: e026 b.n 80029c0 <PCD_EP_ISR_Handler+0x2da>
|
|
8002972: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002974: 691b ldr r3, [r3, #16]
|
|
8002976: 2b00 cmp r3, #0
|
|
8002978: d10a bne.n 8002990 <PCD_EP_ISR_Handler+0x2aa>
|
|
800297a: 697b ldr r3, [r7, #20]
|
|
800297c: 881b ldrh r3, [r3, #0]
|
|
800297e: b29b uxth r3, r3
|
|
8002980: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8002984: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8002988: b29a uxth r2, r3
|
|
800298a: 697b ldr r3, [r7, #20]
|
|
800298c: 801a strh r2, [r3, #0]
|
|
800298e: e017 b.n 80029c0 <PCD_EP_ISR_Handler+0x2da>
|
|
8002990: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002992: 691b ldr r3, [r3, #16]
|
|
8002994: 085b lsrs r3, r3, #1
|
|
8002996: 647b str r3, [r7, #68] @ 0x44
|
|
8002998: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800299a: 691b ldr r3, [r3, #16]
|
|
800299c: f003 0301 and.w r3, r3, #1
|
|
80029a0: 2b00 cmp r3, #0
|
|
80029a2: d002 beq.n 80029aa <PCD_EP_ISR_Handler+0x2c4>
|
|
80029a4: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80029a6: 3301 adds r3, #1
|
|
80029a8: 647b str r3, [r7, #68] @ 0x44
|
|
80029aa: 697b ldr r3, [r7, #20]
|
|
80029ac: 881b ldrh r3, [r3, #0]
|
|
80029ae: b29a uxth r2, r3
|
|
80029b0: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80029b2: b29b uxth r3, r3
|
|
80029b4: 029b lsls r3, r3, #10
|
|
80029b6: b29b uxth r3, r3
|
|
80029b8: 4313 orrs r3, r2
|
|
80029ba: b29a uxth r2, r3
|
|
80029bc: 697b ldr r3, [r7, #20]
|
|
80029be: 801a strh r2, [r3, #0]
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
|
|
80029c0: 687b ldr r3, [r7, #4]
|
|
80029c2: 681b ldr r3, [r3, #0]
|
|
80029c4: 881b ldrh r3, [r3, #0]
|
|
80029c6: b29b uxth r3, r3
|
|
80029c8: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80029cc: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80029d0: 827b strh r3, [r7, #18]
|
|
80029d2: 8a7b ldrh r3, [r7, #18]
|
|
80029d4: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
80029d8: 827b strh r3, [r7, #18]
|
|
80029da: 8a7b ldrh r3, [r7, #18]
|
|
80029dc: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
80029e0: 827b strh r3, [r7, #18]
|
|
80029e2: 687b ldr r3, [r7, #4]
|
|
80029e4: 681a ldr r2, [r3, #0]
|
|
80029e6: 8a7b ldrh r3, [r7, #18]
|
|
80029e8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80029ec: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80029f0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80029f4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80029f8: b29b uxth r3, r3
|
|
80029fa: 8013 strh r3, [r2, #0]
|
|
80029fc: e234 b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
}
|
|
else
|
|
{
|
|
/* Decode and service non control endpoints interrupt */
|
|
/* process related endpoint register */
|
|
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
|
|
80029fe: 687b ldr r3, [r7, #4]
|
|
8002a00: 681b ldr r3, [r3, #0]
|
|
8002a02: 461a mov r2, r3
|
|
8002a04: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
8002a08: 009b lsls r3, r3, #2
|
|
8002a0a: 4413 add r3, r2
|
|
8002a0c: 881b ldrh r3, [r3, #0]
|
|
8002a0e: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
|
|
|
|
if ((wEPVal & USB_EP_CTR_RX) != 0U)
|
|
8002a12: f9b7 304a ldrsh.w r3, [r7, #74] @ 0x4a
|
|
8002a16: 2b00 cmp r3, #0
|
|
8002a18: f280 80fc bge.w 8002c14 <PCD_EP_ISR_Handler+0x52e>
|
|
{
|
|
/* clear int flag */
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
|
|
8002a1c: 687b ldr r3, [r7, #4]
|
|
8002a1e: 681b ldr r3, [r3, #0]
|
|
8002a20: 461a mov r2, r3
|
|
8002a22: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
8002a26: 009b lsls r3, r3, #2
|
|
8002a28: 4413 add r3, r2
|
|
8002a2a: 881b ldrh r3, [r3, #0]
|
|
8002a2c: b29a uxth r2, r3
|
|
8002a2e: f640 738f movw r3, #3983 @ 0xf8f
|
|
8002a32: 4013 ands r3, r2
|
|
8002a34: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
|
|
8002a38: 687b ldr r3, [r7, #4]
|
|
8002a3a: 681b ldr r3, [r3, #0]
|
|
8002a3c: 461a mov r2, r3
|
|
8002a3e: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
8002a42: 009b lsls r3, r3, #2
|
|
8002a44: 4413 add r3, r2
|
|
8002a46: f8b7 2048 ldrh.w r2, [r7, #72] @ 0x48
|
|
8002a4a: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8002a4e: b292 uxth r2, r2
|
|
8002a50: 801a strh r2, [r3, #0]
|
|
ep = &hpcd->OUT_ep[epindex];
|
|
8002a52: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
|
|
8002a56: 4613 mov r3, r2
|
|
8002a58: 009b lsls r3, r3, #2
|
|
8002a5a: 4413 add r3, r2
|
|
8002a5c: 00db lsls r3, r3, #3
|
|
8002a5e: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8002a62: 687a ldr r2, [r7, #4]
|
|
8002a64: 4413 add r3, r2
|
|
8002a66: 657b str r3, [r7, #84] @ 0x54
|
|
|
|
/* OUT Single Buffering */
|
|
if (ep->doublebuffer == 0U)
|
|
8002a68: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002a6a: 7b1b ldrb r3, [r3, #12]
|
|
8002a6c: 2b00 cmp r3, #0
|
|
8002a6e: d125 bne.n 8002abc <PCD_EP_ISR_Handler+0x3d6>
|
|
{
|
|
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
|
8002a70: 687b ldr r3, [r7, #4]
|
|
8002a72: 681b ldr r3, [r3, #0]
|
|
8002a74: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002a78: b29b uxth r3, r3
|
|
8002a7a: 461a mov r2, r3
|
|
8002a7c: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002a7e: 781b ldrb r3, [r3, #0]
|
|
8002a80: 00db lsls r3, r3, #3
|
|
8002a82: 4413 add r3, r2
|
|
8002a84: 3306 adds r3, #6
|
|
8002a86: 005b lsls r3, r3, #1
|
|
8002a88: 687a ldr r2, [r7, #4]
|
|
8002a8a: 6812 ldr r2, [r2, #0]
|
|
8002a8c: 4413 add r3, r2
|
|
8002a8e: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002a92: 881b ldrh r3, [r3, #0]
|
|
8002a94: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002a98: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
|
|
|
|
if (count != 0U)
|
|
8002a9c: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002aa0: 2b00 cmp r3, #0
|
|
8002aa2: f000 8092 beq.w 8002bca <PCD_EP_ISR_Handler+0x4e4>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
|
|
8002aa6: 687b ldr r3, [r7, #4]
|
|
8002aa8: 6818 ldr r0, [r3, #0]
|
|
8002aaa: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002aac: 6959 ldr r1, [r3, #20]
|
|
8002aae: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002ab0: 88da ldrh r2, [r3, #6]
|
|
8002ab2: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002ab6: f004 fe88 bl 80077ca <USB_ReadPMA>
|
|
8002aba: e086 b.n 8002bca <PCD_EP_ISR_Handler+0x4e4>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else
|
|
{
|
|
/* manage double buffer bulk out */
|
|
if (ep->type == EP_TYPE_BULK)
|
|
8002abc: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002abe: 78db ldrb r3, [r3, #3]
|
|
8002ac0: 2b02 cmp r3, #2
|
|
8002ac2: d10a bne.n 8002ada <PCD_EP_ISR_Handler+0x3f4>
|
|
{
|
|
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
|
|
8002ac4: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
8002ac8: 461a mov r2, r3
|
|
8002aca: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8002acc: 6878 ldr r0, [r7, #4]
|
|
8002ace: f000 f9d9 bl 8002e84 <HAL_PCD_EP_DB_Receive>
|
|
8002ad2: 4603 mov r3, r0
|
|
8002ad4: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
|
|
8002ad8: e077 b.n 8002bca <PCD_EP_ISR_Handler+0x4e4>
|
|
}
|
|
else /* manage double buffer iso out */
|
|
{
|
|
/* free EP OUT Buffer */
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
|
|
8002ada: 687b ldr r3, [r7, #4]
|
|
8002adc: 681b ldr r3, [r3, #0]
|
|
8002ade: 461a mov r2, r3
|
|
8002ae0: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002ae2: 781b ldrb r3, [r3, #0]
|
|
8002ae4: 009b lsls r3, r3, #2
|
|
8002ae6: 4413 add r3, r2
|
|
8002ae8: 881b ldrh r3, [r3, #0]
|
|
8002aea: b29b uxth r3, r3
|
|
8002aec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8002af0: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8002af4: f8a7 3052 strh.w r3, [r7, #82] @ 0x52
|
|
8002af8: 687b ldr r3, [r7, #4]
|
|
8002afa: 681b ldr r3, [r3, #0]
|
|
8002afc: 461a mov r2, r3
|
|
8002afe: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002b00: 781b ldrb r3, [r3, #0]
|
|
8002b02: 009b lsls r3, r3, #2
|
|
8002b04: 441a add r2, r3
|
|
8002b06: f8b7 3052 ldrh.w r3, [r7, #82] @ 0x52
|
|
8002b0a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8002b0e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8002b12: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8002b16: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8002b1a: b29b uxth r3, r3
|
|
8002b1c: 8013 strh r3, [r2, #0]
|
|
|
|
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
|
|
8002b1e: 687b ldr r3, [r7, #4]
|
|
8002b20: 681b ldr r3, [r3, #0]
|
|
8002b22: 461a mov r2, r3
|
|
8002b24: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002b26: 781b ldrb r3, [r3, #0]
|
|
8002b28: 009b lsls r3, r3, #2
|
|
8002b2a: 4413 add r3, r2
|
|
8002b2c: 881b ldrh r3, [r3, #0]
|
|
8002b2e: b29b uxth r3, r3
|
|
8002b30: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002b34: 2b00 cmp r3, #0
|
|
8002b36: d024 beq.n 8002b82 <PCD_EP_ISR_Handler+0x49c>
|
|
{
|
|
/* read from endpoint BUF0Addr buffer */
|
|
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
|
8002b38: 687b ldr r3, [r7, #4]
|
|
8002b3a: 681b ldr r3, [r3, #0]
|
|
8002b3c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002b40: b29b uxth r3, r3
|
|
8002b42: 461a mov r2, r3
|
|
8002b44: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002b46: 781b ldrb r3, [r3, #0]
|
|
8002b48: 00db lsls r3, r3, #3
|
|
8002b4a: 4413 add r3, r2
|
|
8002b4c: 3302 adds r3, #2
|
|
8002b4e: 005b lsls r3, r3, #1
|
|
8002b50: 687a ldr r2, [r7, #4]
|
|
8002b52: 6812 ldr r2, [r2, #0]
|
|
8002b54: 4413 add r3, r2
|
|
8002b56: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002b5a: 881b ldrh r3, [r3, #0]
|
|
8002b5c: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002b60: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
|
|
|
|
if (count != 0U)
|
|
8002b64: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002b68: 2b00 cmp r3, #0
|
|
8002b6a: d02e beq.n 8002bca <PCD_EP_ISR_Handler+0x4e4>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
|
8002b6c: 687b ldr r3, [r7, #4]
|
|
8002b6e: 6818 ldr r0, [r3, #0]
|
|
8002b70: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002b72: 6959 ldr r1, [r3, #20]
|
|
8002b74: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002b76: 891a ldrh r2, [r3, #8]
|
|
8002b78: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002b7c: f004 fe25 bl 80077ca <USB_ReadPMA>
|
|
8002b80: e023 b.n 8002bca <PCD_EP_ISR_Handler+0x4e4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* read from endpoint BUF1Addr buffer */
|
|
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
|
8002b82: 687b ldr r3, [r7, #4]
|
|
8002b84: 681b ldr r3, [r3, #0]
|
|
8002b86: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002b8a: b29b uxth r3, r3
|
|
8002b8c: 461a mov r2, r3
|
|
8002b8e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002b90: 781b ldrb r3, [r3, #0]
|
|
8002b92: 00db lsls r3, r3, #3
|
|
8002b94: 4413 add r3, r2
|
|
8002b96: 3306 adds r3, #6
|
|
8002b98: 005b lsls r3, r3, #1
|
|
8002b9a: 687a ldr r2, [r7, #4]
|
|
8002b9c: 6812 ldr r2, [r2, #0]
|
|
8002b9e: 4413 add r3, r2
|
|
8002ba0: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002ba4: 881b ldrh r3, [r3, #0]
|
|
8002ba6: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002baa: f8a7 3050 strh.w r3, [r7, #80] @ 0x50
|
|
|
|
if (count != 0U)
|
|
8002bae: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002bb2: 2b00 cmp r3, #0
|
|
8002bb4: d009 beq.n 8002bca <PCD_EP_ISR_Handler+0x4e4>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
|
8002bb6: 687b ldr r3, [r7, #4]
|
|
8002bb8: 6818 ldr r0, [r3, #0]
|
|
8002bba: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bbc: 6959 ldr r1, [r3, #20]
|
|
8002bbe: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bc0: 895a ldrh r2, [r3, #10]
|
|
8002bc2: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002bc6: f004 fe00 bl 80077ca <USB_ReadPMA>
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
/* multi-packet on the NON control OUT endpoint */
|
|
ep->xfer_count += count;
|
|
8002bca: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bcc: 69da ldr r2, [r3, #28]
|
|
8002bce: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002bd2: 441a add r2, r3
|
|
8002bd4: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bd6: 61da str r2, [r3, #28]
|
|
ep->xfer_buff += count;
|
|
8002bd8: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bda: 695a ldr r2, [r3, #20]
|
|
8002bdc: f8b7 3050 ldrh.w r3, [r7, #80] @ 0x50
|
|
8002be0: 441a add r2, r3
|
|
8002be2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002be4: 615a str r2, [r3, #20]
|
|
|
|
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
|
|
8002be6: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002be8: 699b ldr r3, [r3, #24]
|
|
8002bea: 2b00 cmp r3, #0
|
|
8002bec: d005 beq.n 8002bfa <PCD_EP_ISR_Handler+0x514>
|
|
8002bee: f8b7 2050 ldrh.w r2, [r7, #80] @ 0x50
|
|
8002bf2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bf4: 691b ldr r3, [r3, #16]
|
|
8002bf6: 429a cmp r2, r3
|
|
8002bf8: d206 bcs.n 8002c08 <PCD_EP_ISR_Handler+0x522>
|
|
{
|
|
/* RX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
|
|
8002bfa: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002bfc: 781b ldrb r3, [r3, #0]
|
|
8002bfe: 4619 mov r1, r3
|
|
8002c00: 6878 ldr r0, [r7, #4]
|
|
8002c02: f006 fc45 bl 8009490 <HAL_PCD_DataOutStageCallback>
|
|
8002c06: e005 b.n 8002c14 <PCD_EP_ISR_Handler+0x52e>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
8002c08: 687b ldr r3, [r7, #4]
|
|
8002c0a: 681b ldr r3, [r3, #0]
|
|
8002c0c: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8002c0e: 4618 mov r0, r3
|
|
8002c10: f003 f8a6 bl 8005d60 <USB_EPStartXfer>
|
|
}
|
|
}
|
|
|
|
if ((wEPVal & USB_EP_CTR_TX) != 0U)
|
|
8002c14: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
8002c18: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002c1c: 2b00 cmp r3, #0
|
|
8002c1e: f000 8123 beq.w 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
{
|
|
ep = &hpcd->IN_ep[epindex];
|
|
8002c22: f897 204d ldrb.w r2, [r7, #77] @ 0x4d
|
|
8002c26: 4613 mov r3, r2
|
|
8002c28: 009b lsls r3, r3, #2
|
|
8002c2a: 4413 add r3, r2
|
|
8002c2c: 00db lsls r3, r3, #3
|
|
8002c2e: 3310 adds r3, #16
|
|
8002c30: 687a ldr r2, [r7, #4]
|
|
8002c32: 4413 add r3, r2
|
|
8002c34: 657b str r3, [r7, #84] @ 0x54
|
|
|
|
/* clear int flag */
|
|
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
|
|
8002c36: 687b ldr r3, [r7, #4]
|
|
8002c38: 681b ldr r3, [r3, #0]
|
|
8002c3a: 461a mov r2, r3
|
|
8002c3c: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
8002c40: 009b lsls r3, r3, #2
|
|
8002c42: 4413 add r3, r2
|
|
8002c44: 881b ldrh r3, [r3, #0]
|
|
8002c46: b29b uxth r3, r3
|
|
8002c48: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
|
|
8002c4c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8002c50: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
|
|
8002c54: 687b ldr r3, [r7, #4]
|
|
8002c56: 681b ldr r3, [r3, #0]
|
|
8002c58: 461a mov r2, r3
|
|
8002c5a: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
8002c5e: 009b lsls r3, r3, #2
|
|
8002c60: 441a add r2, r3
|
|
8002c62: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
|
|
8002c66: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8002c6a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8002c6e: b29b uxth r3, r3
|
|
8002c70: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8002c72: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002c74: 78db ldrb r3, [r3, #3]
|
|
8002c76: 2b01 cmp r3, #1
|
|
8002c78: f040 80a2 bne.w 8002dc0 <PCD_EP_ISR_Handler+0x6da>
|
|
{
|
|
ep->xfer_len = 0U;
|
|
8002c7c: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002c7e: 2200 movs r2, #0
|
|
8002c80: 619a str r2, [r3, #24]
|
|
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
if (ep->doublebuffer != 0U)
|
|
8002c82: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002c84: 7b1b ldrb r3, [r3, #12]
|
|
8002c86: 2b00 cmp r3, #0
|
|
8002c88: f000 8093 beq.w 8002db2 <PCD_EP_ISR_Handler+0x6cc>
|
|
{
|
|
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
|
8002c8c: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
8002c90: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002c94: 2b00 cmp r3, #0
|
|
8002c96: d046 beq.n 8002d26 <PCD_EP_ISR_Handler+0x640>
|
|
{
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
8002c98: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002c9a: 785b ldrb r3, [r3, #1]
|
|
8002c9c: 2b00 cmp r3, #0
|
|
8002c9e: d126 bne.n 8002cee <PCD_EP_ISR_Handler+0x608>
|
|
8002ca0: 687b ldr r3, [r7, #4]
|
|
8002ca2: 681b ldr r3, [r3, #0]
|
|
8002ca4: 627b str r3, [r7, #36] @ 0x24
|
|
8002ca6: 687b ldr r3, [r7, #4]
|
|
8002ca8: 681b ldr r3, [r3, #0]
|
|
8002caa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002cae: b29b uxth r3, r3
|
|
8002cb0: 461a mov r2, r3
|
|
8002cb2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002cb4: 4413 add r3, r2
|
|
8002cb6: 627b str r3, [r7, #36] @ 0x24
|
|
8002cb8: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002cba: 781b ldrb r3, [r3, #0]
|
|
8002cbc: 011a lsls r2, r3, #4
|
|
8002cbe: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002cc0: 4413 add r3, r2
|
|
8002cc2: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8002cc6: 623b str r3, [r7, #32]
|
|
8002cc8: 6a3b ldr r3, [r7, #32]
|
|
8002cca: 881b ldrh r3, [r3, #0]
|
|
8002ccc: b29b uxth r3, r3
|
|
8002cce: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002cd2: b29a uxth r2, r3
|
|
8002cd4: 6a3b ldr r3, [r7, #32]
|
|
8002cd6: 801a strh r2, [r3, #0]
|
|
8002cd8: 6a3b ldr r3, [r7, #32]
|
|
8002cda: 881b ldrh r3, [r3, #0]
|
|
8002cdc: b29b uxth r3, r3
|
|
8002cde: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8002ce2: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8002ce6: b29a uxth r2, r3
|
|
8002ce8: 6a3b ldr r3, [r7, #32]
|
|
8002cea: 801a strh r2, [r3, #0]
|
|
8002cec: e061 b.n 8002db2 <PCD_EP_ISR_Handler+0x6cc>
|
|
8002cee: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002cf0: 785b ldrb r3, [r3, #1]
|
|
8002cf2: 2b01 cmp r3, #1
|
|
8002cf4: d15d bne.n 8002db2 <PCD_EP_ISR_Handler+0x6cc>
|
|
8002cf6: 687b ldr r3, [r7, #4]
|
|
8002cf8: 681b ldr r3, [r3, #0]
|
|
8002cfa: 62fb str r3, [r7, #44] @ 0x2c
|
|
8002cfc: 687b ldr r3, [r7, #4]
|
|
8002cfe: 681b ldr r3, [r3, #0]
|
|
8002d00: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002d04: b29b uxth r3, r3
|
|
8002d06: 461a mov r2, r3
|
|
8002d08: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002d0a: 4413 add r3, r2
|
|
8002d0c: 62fb str r3, [r7, #44] @ 0x2c
|
|
8002d0e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002d10: 781b ldrb r3, [r3, #0]
|
|
8002d12: 011a lsls r2, r3, #4
|
|
8002d14: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002d16: 4413 add r3, r2
|
|
8002d18: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8002d1c: 62bb str r3, [r7, #40] @ 0x28
|
|
8002d1e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002d20: 2200 movs r2, #0
|
|
8002d22: 801a strh r2, [r3, #0]
|
|
8002d24: e045 b.n 8002db2 <PCD_EP_ISR_Handler+0x6cc>
|
|
}
|
|
else
|
|
{
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
8002d26: 687b ldr r3, [r7, #4]
|
|
8002d28: 681b ldr r3, [r3, #0]
|
|
8002d2a: 63fb str r3, [r7, #60] @ 0x3c
|
|
8002d2c: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002d2e: 785b ldrb r3, [r3, #1]
|
|
8002d30: 2b00 cmp r3, #0
|
|
8002d32: d126 bne.n 8002d82 <PCD_EP_ISR_Handler+0x69c>
|
|
8002d34: 687b ldr r3, [r7, #4]
|
|
8002d36: 681b ldr r3, [r3, #0]
|
|
8002d38: 637b str r3, [r7, #52] @ 0x34
|
|
8002d3a: 687b ldr r3, [r7, #4]
|
|
8002d3c: 681b ldr r3, [r3, #0]
|
|
8002d3e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002d42: b29b uxth r3, r3
|
|
8002d44: 461a mov r2, r3
|
|
8002d46: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8002d48: 4413 add r3, r2
|
|
8002d4a: 637b str r3, [r7, #52] @ 0x34
|
|
8002d4c: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002d4e: 781b ldrb r3, [r3, #0]
|
|
8002d50: 011a lsls r2, r3, #4
|
|
8002d52: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8002d54: 4413 add r3, r2
|
|
8002d56: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8002d5a: 633b str r3, [r7, #48] @ 0x30
|
|
8002d5c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8002d5e: 881b ldrh r3, [r3, #0]
|
|
8002d60: b29b uxth r3, r3
|
|
8002d62: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002d66: b29a uxth r2, r3
|
|
8002d68: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8002d6a: 801a strh r2, [r3, #0]
|
|
8002d6c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8002d6e: 881b ldrh r3, [r3, #0]
|
|
8002d70: b29b uxth r3, r3
|
|
8002d72: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8002d76: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8002d7a: b29a uxth r2, r3
|
|
8002d7c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8002d7e: 801a strh r2, [r3, #0]
|
|
8002d80: e017 b.n 8002db2 <PCD_EP_ISR_Handler+0x6cc>
|
|
8002d82: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002d84: 785b ldrb r3, [r3, #1]
|
|
8002d86: 2b01 cmp r3, #1
|
|
8002d88: d113 bne.n 8002db2 <PCD_EP_ISR_Handler+0x6cc>
|
|
8002d8a: 687b ldr r3, [r7, #4]
|
|
8002d8c: 681b ldr r3, [r3, #0]
|
|
8002d8e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002d92: b29b uxth r3, r3
|
|
8002d94: 461a mov r2, r3
|
|
8002d96: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8002d98: 4413 add r3, r2
|
|
8002d9a: 63fb str r3, [r7, #60] @ 0x3c
|
|
8002d9c: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002d9e: 781b ldrb r3, [r3, #0]
|
|
8002da0: 011a lsls r2, r3, #4
|
|
8002da2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8002da4: 4413 add r3, r2
|
|
8002da6: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8002daa: 63bb str r3, [r7, #56] @ 0x38
|
|
8002dac: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8002dae: 2200 movs r2, #0
|
|
8002db0: 801a strh r2, [r3, #0]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
8002db2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002db4: 781b ldrb r3, [r3, #0]
|
|
8002db6: 4619 mov r1, r3
|
|
8002db8: 6878 ldr r0, [r7, #4]
|
|
8002dba: f006 fb84 bl 80094c6 <HAL_PCD_DataInStageCallback>
|
|
8002dbe: e053 b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
/* Manage Single Buffer Transaction */
|
|
if ((wEPVal & USB_EP_KIND) == 0U)
|
|
8002dc0: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
8002dc4: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002dc8: 2b00 cmp r3, #0
|
|
8002dca: d146 bne.n 8002e5a <PCD_EP_ISR_Handler+0x774>
|
|
{
|
|
/* multi-packet on the NON control IN endpoint */
|
|
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
|
8002dcc: 687b ldr r3, [r7, #4]
|
|
8002dce: 681b ldr r3, [r3, #0]
|
|
8002dd0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002dd4: b29b uxth r3, r3
|
|
8002dd6: 461a mov r2, r3
|
|
8002dd8: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002dda: 781b ldrb r3, [r3, #0]
|
|
8002ddc: 00db lsls r3, r3, #3
|
|
8002dde: 4413 add r3, r2
|
|
8002de0: 3302 adds r3, #2
|
|
8002de2: 005b lsls r3, r3, #1
|
|
8002de4: 687a ldr r2, [r7, #4]
|
|
8002de6: 6812 ldr r2, [r2, #0]
|
|
8002de8: 4413 add r3, r2
|
|
8002dea: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002dee: 881b ldrh r3, [r3, #0]
|
|
8002df0: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002df4: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
|
|
|
|
if (ep->xfer_len > TxPctSize)
|
|
8002df8: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002dfa: 699a ldr r2, [r3, #24]
|
|
8002dfc: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
|
|
8002e00: 429a cmp r2, r3
|
|
8002e02: d907 bls.n 8002e14 <PCD_EP_ISR_Handler+0x72e>
|
|
{
|
|
ep->xfer_len -= TxPctSize;
|
|
8002e04: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e06: 699a ldr r2, [r3, #24]
|
|
8002e08: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
|
|
8002e0c: 1ad2 subs r2, r2, r3
|
|
8002e0e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e10: 619a str r2, [r3, #24]
|
|
8002e12: e002 b.n 8002e1a <PCD_EP_ISR_Handler+0x734>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
8002e14: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e16: 2200 movs r2, #0
|
|
8002e18: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
8002e1a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e1c: 699b ldr r3, [r3, #24]
|
|
8002e1e: 2b00 cmp r3, #0
|
|
8002e20: d106 bne.n 8002e30 <PCD_EP_ISR_Handler+0x74a>
|
|
{
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
8002e22: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e24: 781b ldrb r3, [r3, #0]
|
|
8002e26: 4619 mov r1, r3
|
|
8002e28: 6878 ldr r0, [r7, #4]
|
|
8002e2a: f006 fb4c bl 80094c6 <HAL_PCD_DataInStageCallback>
|
|
8002e2e: e01b b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
/* Transfer is not yet Done */
|
|
ep->xfer_buff += TxPctSize;
|
|
8002e30: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e32: 695a ldr r2, [r3, #20]
|
|
8002e34: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
|
|
8002e38: 441a add r2, r3
|
|
8002e3a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e3c: 615a str r2, [r3, #20]
|
|
ep->xfer_count += TxPctSize;
|
|
8002e3e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e40: 69da ldr r2, [r3, #28]
|
|
8002e42: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
|
|
8002e46: 441a add r2, r3
|
|
8002e48: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002e4a: 61da str r2, [r3, #28]
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
8002e4c: 687b ldr r3, [r7, #4]
|
|
8002e4e: 681b ldr r3, [r3, #0]
|
|
8002e50: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8002e52: 4618 mov r0, r3
|
|
8002e54: f002 ff84 bl 8005d60 <USB_EPStartXfer>
|
|
8002e58: e006 b.n 8002e68 <PCD_EP_ISR_Handler+0x782>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
|
|
else
|
|
{
|
|
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
|
|
8002e5a: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
8002e5e: 461a mov r2, r3
|
|
8002e60: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8002e62: 6878 ldr r0, [r7, #4]
|
|
8002e64: f000 f91b bl 800309e <HAL_PCD_EP_DB_Transmit>
|
|
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
|
|
8002e68: 687b ldr r3, [r7, #4]
|
|
8002e6a: 681b ldr r3, [r3, #0]
|
|
8002e6c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
8002e70: b29b uxth r3, r3
|
|
8002e72: b21b sxth r3, r3
|
|
8002e74: 2b00 cmp r3, #0
|
|
8002e76: f6ff ac3b blt.w 80026f0 <PCD_EP_ISR_Handler+0xa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002e7a: 2300 movs r3, #0
|
|
}
|
|
8002e7c: 4618 mov r0, r3
|
|
8002e7e: 3758 adds r7, #88 @ 0x58
|
|
8002e80: 46bd mov sp, r7
|
|
8002e82: bd80 pop {r7, pc}
|
|
|
|
08002e84 <HAL_PCD_EP_DB_Receive>:
|
|
* @param wEPVal Last snapshot of EPRx register value taken in ISR
|
|
* @retval HAL status
|
|
*/
|
|
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
|
|
PCD_EPTypeDef *ep, uint16_t wEPVal)
|
|
{
|
|
8002e84: b580 push {r7, lr}
|
|
8002e86: b088 sub sp, #32
|
|
8002e88: af00 add r7, sp, #0
|
|
8002e8a: 60f8 str r0, [r7, #12]
|
|
8002e8c: 60b9 str r1, [r7, #8]
|
|
8002e8e: 4613 mov r3, r2
|
|
8002e90: 80fb strh r3, [r7, #6]
|
|
uint16_t count;
|
|
|
|
/* Manage Buffer0 OUT */
|
|
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
|
8002e92: 88fb ldrh r3, [r7, #6]
|
|
8002e94: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002e98: 2b00 cmp r3, #0
|
|
8002e9a: d07e beq.n 8002f9a <HAL_PCD_EP_DB_Receive+0x116>
|
|
{
|
|
/* Get count of received Data on buffer0 */
|
|
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
|
8002e9c: 68fb ldr r3, [r7, #12]
|
|
8002e9e: 681b ldr r3, [r3, #0]
|
|
8002ea0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002ea4: b29b uxth r3, r3
|
|
8002ea6: 461a mov r2, r3
|
|
8002ea8: 68bb ldr r3, [r7, #8]
|
|
8002eaa: 781b ldrb r3, [r3, #0]
|
|
8002eac: 00db lsls r3, r3, #3
|
|
8002eae: 4413 add r3, r2
|
|
8002eb0: 3302 adds r3, #2
|
|
8002eb2: 005b lsls r3, r3, #1
|
|
8002eb4: 68fa ldr r2, [r7, #12]
|
|
8002eb6: 6812 ldr r2, [r2, #0]
|
|
8002eb8: 4413 add r3, r2
|
|
8002eba: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002ebe: 881b ldrh r3, [r3, #0]
|
|
8002ec0: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002ec4: 837b strh r3, [r7, #26]
|
|
|
|
if (ep->xfer_len >= count)
|
|
8002ec6: 68bb ldr r3, [r7, #8]
|
|
8002ec8: 699a ldr r2, [r3, #24]
|
|
8002eca: 8b7b ldrh r3, [r7, #26]
|
|
8002ecc: 429a cmp r2, r3
|
|
8002ece: d306 bcc.n 8002ede <HAL_PCD_EP_DB_Receive+0x5a>
|
|
{
|
|
ep->xfer_len -= count;
|
|
8002ed0: 68bb ldr r3, [r7, #8]
|
|
8002ed2: 699a ldr r2, [r3, #24]
|
|
8002ed4: 8b7b ldrh r3, [r7, #26]
|
|
8002ed6: 1ad2 subs r2, r2, r3
|
|
8002ed8: 68bb ldr r3, [r7, #8]
|
|
8002eda: 619a str r2, [r3, #24]
|
|
8002edc: e002 b.n 8002ee4 <HAL_PCD_EP_DB_Receive+0x60>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
8002ede: 68bb ldr r3, [r7, #8]
|
|
8002ee0: 2200 movs r2, #0
|
|
8002ee2: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (ep->xfer_len == 0U)
|
|
8002ee4: 68bb ldr r3, [r7, #8]
|
|
8002ee6: 699b ldr r3, [r3, #24]
|
|
8002ee8: 2b00 cmp r3, #0
|
|
8002eea: d123 bne.n 8002f34 <HAL_PCD_EP_DB_Receive+0xb0>
|
|
{
|
|
/* set NAK to OUT endpoint since double buffer is enabled */
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
|
8002eec: 68fb ldr r3, [r7, #12]
|
|
8002eee: 681b ldr r3, [r3, #0]
|
|
8002ef0: 461a mov r2, r3
|
|
8002ef2: 68bb ldr r3, [r7, #8]
|
|
8002ef4: 781b ldrb r3, [r3, #0]
|
|
8002ef6: 009b lsls r3, r3, #2
|
|
8002ef8: 4413 add r3, r2
|
|
8002efa: 881b ldrh r3, [r3, #0]
|
|
8002efc: b29b uxth r3, r3
|
|
8002efe: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8002f02: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8002f06: 833b strh r3, [r7, #24]
|
|
8002f08: 8b3b ldrh r3, [r7, #24]
|
|
8002f0a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
8002f0e: 833b strh r3, [r7, #24]
|
|
8002f10: 68fb ldr r3, [r7, #12]
|
|
8002f12: 681b ldr r3, [r3, #0]
|
|
8002f14: 461a mov r2, r3
|
|
8002f16: 68bb ldr r3, [r7, #8]
|
|
8002f18: 781b ldrb r3, [r3, #0]
|
|
8002f1a: 009b lsls r3, r3, #2
|
|
8002f1c: 441a add r2, r3
|
|
8002f1e: 8b3b ldrh r3, [r7, #24]
|
|
8002f20: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8002f24: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8002f28: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8002f2c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8002f30: b29b uxth r3, r3
|
|
8002f32: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Check if Buffer1 is in blocked state which requires to toggle */
|
|
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
|
8002f34: 88fb ldrh r3, [r7, #6]
|
|
8002f36: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002f3a: 2b00 cmp r3, #0
|
|
8002f3c: d01f beq.n 8002f7e <HAL_PCD_EP_DB_Receive+0xfa>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
|
|
8002f3e: 68fb ldr r3, [r7, #12]
|
|
8002f40: 681b ldr r3, [r3, #0]
|
|
8002f42: 461a mov r2, r3
|
|
8002f44: 68bb ldr r3, [r7, #8]
|
|
8002f46: 781b ldrb r3, [r3, #0]
|
|
8002f48: 009b lsls r3, r3, #2
|
|
8002f4a: 4413 add r3, r2
|
|
8002f4c: 881b ldrh r3, [r3, #0]
|
|
8002f4e: b29b uxth r3, r3
|
|
8002f50: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8002f54: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8002f58: 82fb strh r3, [r7, #22]
|
|
8002f5a: 68fb ldr r3, [r7, #12]
|
|
8002f5c: 681b ldr r3, [r3, #0]
|
|
8002f5e: 461a mov r2, r3
|
|
8002f60: 68bb ldr r3, [r7, #8]
|
|
8002f62: 781b ldrb r3, [r3, #0]
|
|
8002f64: 009b lsls r3, r3, #2
|
|
8002f66: 441a add r2, r3
|
|
8002f68: 8afb ldrh r3, [r7, #22]
|
|
8002f6a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8002f6e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8002f72: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8002f76: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8002f7a: b29b uxth r3, r3
|
|
8002f7c: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
if (count != 0U)
|
|
8002f7e: 8b7b ldrh r3, [r7, #26]
|
|
8002f80: 2b00 cmp r3, #0
|
|
8002f82: f000 8087 beq.w 8003094 <HAL_PCD_EP_DB_Receive+0x210>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
|
8002f86: 68fb ldr r3, [r7, #12]
|
|
8002f88: 6818 ldr r0, [r3, #0]
|
|
8002f8a: 68bb ldr r3, [r7, #8]
|
|
8002f8c: 6959 ldr r1, [r3, #20]
|
|
8002f8e: 68bb ldr r3, [r7, #8]
|
|
8002f90: 891a ldrh r2, [r3, #8]
|
|
8002f92: 8b7b ldrh r3, [r7, #26]
|
|
8002f94: f004 fc19 bl 80077ca <USB_ReadPMA>
|
|
8002f98: e07c b.n 8003094 <HAL_PCD_EP_DB_Receive+0x210>
|
|
}
|
|
/* Manage Buffer 1 DTOG_RX=0 */
|
|
else
|
|
{
|
|
/* Get count of received data */
|
|
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
|
8002f9a: 68fb ldr r3, [r7, #12]
|
|
8002f9c: 681b ldr r3, [r3, #0]
|
|
8002f9e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8002fa2: b29b uxth r3, r3
|
|
8002fa4: 461a mov r2, r3
|
|
8002fa6: 68bb ldr r3, [r7, #8]
|
|
8002fa8: 781b ldrb r3, [r3, #0]
|
|
8002faa: 00db lsls r3, r3, #3
|
|
8002fac: 4413 add r3, r2
|
|
8002fae: 3306 adds r3, #6
|
|
8002fb0: 005b lsls r3, r3, #1
|
|
8002fb2: 68fa ldr r2, [r7, #12]
|
|
8002fb4: 6812 ldr r2, [r2, #0]
|
|
8002fb6: 4413 add r3, r2
|
|
8002fb8: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8002fbc: 881b ldrh r3, [r3, #0]
|
|
8002fbe: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8002fc2: 837b strh r3, [r7, #26]
|
|
|
|
if (ep->xfer_len >= count)
|
|
8002fc4: 68bb ldr r3, [r7, #8]
|
|
8002fc6: 699a ldr r2, [r3, #24]
|
|
8002fc8: 8b7b ldrh r3, [r7, #26]
|
|
8002fca: 429a cmp r2, r3
|
|
8002fcc: d306 bcc.n 8002fdc <HAL_PCD_EP_DB_Receive+0x158>
|
|
{
|
|
ep->xfer_len -= count;
|
|
8002fce: 68bb ldr r3, [r7, #8]
|
|
8002fd0: 699a ldr r2, [r3, #24]
|
|
8002fd2: 8b7b ldrh r3, [r7, #26]
|
|
8002fd4: 1ad2 subs r2, r2, r3
|
|
8002fd6: 68bb ldr r3, [r7, #8]
|
|
8002fd8: 619a str r2, [r3, #24]
|
|
8002fda: e002 b.n 8002fe2 <HAL_PCD_EP_DB_Receive+0x15e>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
8002fdc: 68bb ldr r3, [r7, #8]
|
|
8002fde: 2200 movs r2, #0
|
|
8002fe0: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (ep->xfer_len == 0U)
|
|
8002fe2: 68bb ldr r3, [r7, #8]
|
|
8002fe4: 699b ldr r3, [r3, #24]
|
|
8002fe6: 2b00 cmp r3, #0
|
|
8002fe8: d123 bne.n 8003032 <HAL_PCD_EP_DB_Receive+0x1ae>
|
|
{
|
|
/* set NAK on the current endpoint */
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
|
8002fea: 68fb ldr r3, [r7, #12]
|
|
8002fec: 681b ldr r3, [r3, #0]
|
|
8002fee: 461a mov r2, r3
|
|
8002ff0: 68bb ldr r3, [r7, #8]
|
|
8002ff2: 781b ldrb r3, [r3, #0]
|
|
8002ff4: 009b lsls r3, r3, #2
|
|
8002ff6: 4413 add r3, r2
|
|
8002ff8: 881b ldrh r3, [r3, #0]
|
|
8002ffa: b29b uxth r3, r3
|
|
8002ffc: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8003000: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8003004: 83fb strh r3, [r7, #30]
|
|
8003006: 8bfb ldrh r3, [r7, #30]
|
|
8003008: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800300c: 83fb strh r3, [r7, #30]
|
|
800300e: 68fb ldr r3, [r7, #12]
|
|
8003010: 681b ldr r3, [r3, #0]
|
|
8003012: 461a mov r2, r3
|
|
8003014: 68bb ldr r3, [r7, #8]
|
|
8003016: 781b ldrb r3, [r3, #0]
|
|
8003018: 009b lsls r3, r3, #2
|
|
800301a: 441a add r2, r3
|
|
800301c: 8bfb ldrh r3, [r7, #30]
|
|
800301e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8003022: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8003026: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800302a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800302e: b29b uxth r3, r3
|
|
8003030: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/*Need to FreeUser Buffer*/
|
|
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
|
|
8003032: 88fb ldrh r3, [r7, #6]
|
|
8003034: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003038: 2b00 cmp r3, #0
|
|
800303a: d11f bne.n 800307c <HAL_PCD_EP_DB_Receive+0x1f8>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
|
|
800303c: 68fb ldr r3, [r7, #12]
|
|
800303e: 681b ldr r3, [r3, #0]
|
|
8003040: 461a mov r2, r3
|
|
8003042: 68bb ldr r3, [r7, #8]
|
|
8003044: 781b ldrb r3, [r3, #0]
|
|
8003046: 009b lsls r3, r3, #2
|
|
8003048: 4413 add r3, r2
|
|
800304a: 881b ldrh r3, [r3, #0]
|
|
800304c: b29b uxth r3, r3
|
|
800304e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8003052: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8003056: 83bb strh r3, [r7, #28]
|
|
8003058: 68fb ldr r3, [r7, #12]
|
|
800305a: 681b ldr r3, [r3, #0]
|
|
800305c: 461a mov r2, r3
|
|
800305e: 68bb ldr r3, [r7, #8]
|
|
8003060: 781b ldrb r3, [r3, #0]
|
|
8003062: 009b lsls r3, r3, #2
|
|
8003064: 441a add r2, r3
|
|
8003066: 8bbb ldrh r3, [r7, #28]
|
|
8003068: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800306c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8003070: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8003074: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8003078: b29b uxth r3, r3
|
|
800307a: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
if (count != 0U)
|
|
800307c: 8b7b ldrh r3, [r7, #26]
|
|
800307e: 2b00 cmp r3, #0
|
|
8003080: d008 beq.n 8003094 <HAL_PCD_EP_DB_Receive+0x210>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
|
8003082: 68fb ldr r3, [r7, #12]
|
|
8003084: 6818 ldr r0, [r3, #0]
|
|
8003086: 68bb ldr r3, [r7, #8]
|
|
8003088: 6959 ldr r1, [r3, #20]
|
|
800308a: 68bb ldr r3, [r7, #8]
|
|
800308c: 895a ldrh r2, [r3, #10]
|
|
800308e: 8b7b ldrh r3, [r7, #26]
|
|
8003090: f004 fb9b bl 80077ca <USB_ReadPMA>
|
|
}
|
|
}
|
|
|
|
return count;
|
|
8003094: 8b7b ldrh r3, [r7, #26]
|
|
}
|
|
8003096: 4618 mov r0, r3
|
|
8003098: 3720 adds r7, #32
|
|
800309a: 46bd mov sp, r7
|
|
800309c: bd80 pop {r7, pc}
|
|
|
|
0800309e <HAL_PCD_EP_DB_Transmit>:
|
|
* @param wEPVal Last snapshot of EPRx register value taken in ISR
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
|
PCD_EPTypeDef *ep, uint16_t wEPVal)
|
|
{
|
|
800309e: b580 push {r7, lr}
|
|
80030a0: b0a4 sub sp, #144 @ 0x90
|
|
80030a2: af00 add r7, sp, #0
|
|
80030a4: 60f8 str r0, [r7, #12]
|
|
80030a6: 60b9 str r1, [r7, #8]
|
|
80030a8: 4613 mov r3, r2
|
|
80030aa: 80fb strh r3, [r7, #6]
|
|
uint32_t len;
|
|
uint16_t TxPctSize;
|
|
|
|
/* Data Buffer0 ACK received */
|
|
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
|
80030ac: 88fb ldrh r3, [r7, #6]
|
|
80030ae: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80030b2: 2b00 cmp r3, #0
|
|
80030b4: f000 81dd beq.w 8003472 <HAL_PCD_EP_DB_Transmit+0x3d4>
|
|
{
|
|
/* multi-packet on the NON control IN endpoint */
|
|
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
|
80030b8: 68fb ldr r3, [r7, #12]
|
|
80030ba: 681b ldr r3, [r3, #0]
|
|
80030bc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80030c0: b29b uxth r3, r3
|
|
80030c2: 461a mov r2, r3
|
|
80030c4: 68bb ldr r3, [r7, #8]
|
|
80030c6: 781b ldrb r3, [r3, #0]
|
|
80030c8: 00db lsls r3, r3, #3
|
|
80030ca: 4413 add r3, r2
|
|
80030cc: 3302 adds r3, #2
|
|
80030ce: 005b lsls r3, r3, #1
|
|
80030d0: 68fa ldr r2, [r7, #12]
|
|
80030d2: 6812 ldr r2, [r2, #0]
|
|
80030d4: 4413 add r3, r2
|
|
80030d6: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80030da: 881b ldrh r3, [r3, #0]
|
|
80030dc: f3c3 0309 ubfx r3, r3, #0, #10
|
|
80030e0: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
|
|
|
|
if (ep->xfer_len > TxPctSize)
|
|
80030e4: 68bb ldr r3, [r7, #8]
|
|
80030e6: 699a ldr r2, [r3, #24]
|
|
80030e8: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80030ec: 429a cmp r2, r3
|
|
80030ee: d907 bls.n 8003100 <HAL_PCD_EP_DB_Transmit+0x62>
|
|
{
|
|
ep->xfer_len -= TxPctSize;
|
|
80030f0: 68bb ldr r3, [r7, #8]
|
|
80030f2: 699a ldr r2, [r3, #24]
|
|
80030f4: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80030f8: 1ad2 subs r2, r2, r3
|
|
80030fa: 68bb ldr r3, [r7, #8]
|
|
80030fc: 619a str r2, [r3, #24]
|
|
80030fe: e002 b.n 8003106 <HAL_PCD_EP_DB_Transmit+0x68>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
8003100: 68bb ldr r3, [r7, #8]
|
|
8003102: 2200 movs r2, #0
|
|
8003104: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Transfer is completed */
|
|
if (ep->xfer_len == 0U)
|
|
8003106: 68bb ldr r3, [r7, #8]
|
|
8003108: 699b ldr r3, [r3, #24]
|
|
800310a: 2b00 cmp r3, #0
|
|
800310c: f040 80b9 bne.w 8003282 <HAL_PCD_EP_DB_Transmit+0x1e4>
|
|
{
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
8003110: 68bb ldr r3, [r7, #8]
|
|
8003112: 785b ldrb r3, [r3, #1]
|
|
8003114: 2b00 cmp r3, #0
|
|
8003116: d126 bne.n 8003166 <HAL_PCD_EP_DB_Transmit+0xc8>
|
|
8003118: 68fb ldr r3, [r7, #12]
|
|
800311a: 681b ldr r3, [r3, #0]
|
|
800311c: 62fb str r3, [r7, #44] @ 0x2c
|
|
800311e: 68fb ldr r3, [r7, #12]
|
|
8003120: 681b ldr r3, [r3, #0]
|
|
8003122: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003126: b29b uxth r3, r3
|
|
8003128: 461a mov r2, r3
|
|
800312a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800312c: 4413 add r3, r2
|
|
800312e: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003130: 68bb ldr r3, [r7, #8]
|
|
8003132: 781b ldrb r3, [r3, #0]
|
|
8003134: 011a lsls r2, r3, #4
|
|
8003136: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003138: 4413 add r3, r2
|
|
800313a: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800313e: 62bb str r3, [r7, #40] @ 0x28
|
|
8003140: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003142: 881b ldrh r3, [r3, #0]
|
|
8003144: b29b uxth r3, r3
|
|
8003146: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800314a: b29a uxth r2, r3
|
|
800314c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800314e: 801a strh r2, [r3, #0]
|
|
8003150: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003152: 881b ldrh r3, [r3, #0]
|
|
8003154: b29b uxth r3, r3
|
|
8003156: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800315a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800315e: b29a uxth r2, r3
|
|
8003160: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003162: 801a strh r2, [r3, #0]
|
|
8003164: e01a b.n 800319c <HAL_PCD_EP_DB_Transmit+0xfe>
|
|
8003166: 68bb ldr r3, [r7, #8]
|
|
8003168: 785b ldrb r3, [r3, #1]
|
|
800316a: 2b01 cmp r3, #1
|
|
800316c: d116 bne.n 800319c <HAL_PCD_EP_DB_Transmit+0xfe>
|
|
800316e: 68fb ldr r3, [r7, #12]
|
|
8003170: 681b ldr r3, [r3, #0]
|
|
8003172: 637b str r3, [r7, #52] @ 0x34
|
|
8003174: 68fb ldr r3, [r7, #12]
|
|
8003176: 681b ldr r3, [r3, #0]
|
|
8003178: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800317c: b29b uxth r3, r3
|
|
800317e: 461a mov r2, r3
|
|
8003180: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8003182: 4413 add r3, r2
|
|
8003184: 637b str r3, [r7, #52] @ 0x34
|
|
8003186: 68bb ldr r3, [r7, #8]
|
|
8003188: 781b ldrb r3, [r3, #0]
|
|
800318a: 011a lsls r2, r3, #4
|
|
800318c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800318e: 4413 add r3, r2
|
|
8003190: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8003194: 633b str r3, [r7, #48] @ 0x30
|
|
8003196: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8003198: 2200 movs r2, #0
|
|
800319a: 801a strh r2, [r3, #0]
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800319c: 68fb ldr r3, [r7, #12]
|
|
800319e: 681b ldr r3, [r3, #0]
|
|
80031a0: 627b str r3, [r7, #36] @ 0x24
|
|
80031a2: 68bb ldr r3, [r7, #8]
|
|
80031a4: 785b ldrb r3, [r3, #1]
|
|
80031a6: 2b00 cmp r3, #0
|
|
80031a8: d126 bne.n 80031f8 <HAL_PCD_EP_DB_Transmit+0x15a>
|
|
80031aa: 68fb ldr r3, [r7, #12]
|
|
80031ac: 681b ldr r3, [r3, #0]
|
|
80031ae: 61fb str r3, [r7, #28]
|
|
80031b0: 68fb ldr r3, [r7, #12]
|
|
80031b2: 681b ldr r3, [r3, #0]
|
|
80031b4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80031b8: b29b uxth r3, r3
|
|
80031ba: 461a mov r2, r3
|
|
80031bc: 69fb ldr r3, [r7, #28]
|
|
80031be: 4413 add r3, r2
|
|
80031c0: 61fb str r3, [r7, #28]
|
|
80031c2: 68bb ldr r3, [r7, #8]
|
|
80031c4: 781b ldrb r3, [r3, #0]
|
|
80031c6: 011a lsls r2, r3, #4
|
|
80031c8: 69fb ldr r3, [r7, #28]
|
|
80031ca: 4413 add r3, r2
|
|
80031cc: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
80031d0: 61bb str r3, [r7, #24]
|
|
80031d2: 69bb ldr r3, [r7, #24]
|
|
80031d4: 881b ldrh r3, [r3, #0]
|
|
80031d6: b29b uxth r3, r3
|
|
80031d8: f3c3 0309 ubfx r3, r3, #0, #10
|
|
80031dc: b29a uxth r2, r3
|
|
80031de: 69bb ldr r3, [r7, #24]
|
|
80031e0: 801a strh r2, [r3, #0]
|
|
80031e2: 69bb ldr r3, [r7, #24]
|
|
80031e4: 881b ldrh r3, [r3, #0]
|
|
80031e6: b29b uxth r3, r3
|
|
80031e8: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80031ec: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80031f0: b29a uxth r2, r3
|
|
80031f2: 69bb ldr r3, [r7, #24]
|
|
80031f4: 801a strh r2, [r3, #0]
|
|
80031f6: e017 b.n 8003228 <HAL_PCD_EP_DB_Transmit+0x18a>
|
|
80031f8: 68bb ldr r3, [r7, #8]
|
|
80031fa: 785b ldrb r3, [r3, #1]
|
|
80031fc: 2b01 cmp r3, #1
|
|
80031fe: d113 bne.n 8003228 <HAL_PCD_EP_DB_Transmit+0x18a>
|
|
8003200: 68fb ldr r3, [r7, #12]
|
|
8003202: 681b ldr r3, [r3, #0]
|
|
8003204: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003208: b29b uxth r3, r3
|
|
800320a: 461a mov r2, r3
|
|
800320c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800320e: 4413 add r3, r2
|
|
8003210: 627b str r3, [r7, #36] @ 0x24
|
|
8003212: 68bb ldr r3, [r7, #8]
|
|
8003214: 781b ldrb r3, [r3, #0]
|
|
8003216: 011a lsls r2, r3, #4
|
|
8003218: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800321a: 4413 add r3, r2
|
|
800321c: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8003220: 623b str r3, [r7, #32]
|
|
8003222: 6a3b ldr r3, [r7, #32]
|
|
8003224: 2200 movs r2, #0
|
|
8003226: 801a strh r2, [r3, #0]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
8003228: 68bb ldr r3, [r7, #8]
|
|
800322a: 781b ldrb r3, [r3, #0]
|
|
800322c: 4619 mov r1, r3
|
|
800322e: 68f8 ldr r0, [r7, #12]
|
|
8003230: f006 f949 bl 80094c6 <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
|
8003234: 88fb ldrh r3, [r7, #6]
|
|
8003236: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800323a: 2b00 cmp r3, #0
|
|
800323c: f000 82fc beq.w 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
8003240: 68fb ldr r3, [r7, #12]
|
|
8003242: 681b ldr r3, [r3, #0]
|
|
8003244: 461a mov r2, r3
|
|
8003246: 68bb ldr r3, [r7, #8]
|
|
8003248: 781b ldrb r3, [r3, #0]
|
|
800324a: 009b lsls r3, r3, #2
|
|
800324c: 4413 add r3, r2
|
|
800324e: 881b ldrh r3, [r3, #0]
|
|
8003250: b29b uxth r3, r3
|
|
8003252: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8003256: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800325a: 82fb strh r3, [r7, #22]
|
|
800325c: 68fb ldr r3, [r7, #12]
|
|
800325e: 681b ldr r3, [r3, #0]
|
|
8003260: 461a mov r2, r3
|
|
8003262: 68bb ldr r3, [r7, #8]
|
|
8003264: 781b ldrb r3, [r3, #0]
|
|
8003266: 009b lsls r3, r3, #2
|
|
8003268: 441a add r2, r3
|
|
800326a: 8afb ldrh r3, [r7, #22]
|
|
800326c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8003270: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8003274: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8003278: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800327c: b29b uxth r3, r3
|
|
800327e: 8013 strh r3, [r2, #0]
|
|
8003280: e2da b.n 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
}
|
|
}
|
|
else /* Transfer is not yet Done */
|
|
{
|
|
/* need to Free USB Buff */
|
|
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
|
8003282: 88fb ldrh r3, [r7, #6]
|
|
8003284: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8003288: 2b00 cmp r3, #0
|
|
800328a: d021 beq.n 80032d0 <HAL_PCD_EP_DB_Transmit+0x232>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
800328c: 68fb ldr r3, [r7, #12]
|
|
800328e: 681b ldr r3, [r3, #0]
|
|
8003290: 461a mov r2, r3
|
|
8003292: 68bb ldr r3, [r7, #8]
|
|
8003294: 781b ldrb r3, [r3, #0]
|
|
8003296: 009b lsls r3, r3, #2
|
|
8003298: 4413 add r3, r2
|
|
800329a: 881b ldrh r3, [r3, #0]
|
|
800329c: b29b uxth r3, r3
|
|
800329e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80032a2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80032a6: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
80032aa: 68fb ldr r3, [r7, #12]
|
|
80032ac: 681b ldr r3, [r3, #0]
|
|
80032ae: 461a mov r2, r3
|
|
80032b0: 68bb ldr r3, [r7, #8]
|
|
80032b2: 781b ldrb r3, [r3, #0]
|
|
80032b4: 009b lsls r3, r3, #2
|
|
80032b6: 441a add r2, r3
|
|
80032b8: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
80032bc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80032c0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80032c4: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
80032c8: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80032cc: b29b uxth r3, r3
|
|
80032ce: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Still there is data to Fill in the next Buffer */
|
|
if (ep->xfer_fill_db == 1U)
|
|
80032d0: 68bb ldr r3, [r7, #8]
|
|
80032d2: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
80032d6: 2b01 cmp r3, #1
|
|
80032d8: f040 82ae bne.w 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
{
|
|
ep->xfer_buff += TxPctSize;
|
|
80032dc: 68bb ldr r3, [r7, #8]
|
|
80032de: 695a ldr r2, [r3, #20]
|
|
80032e0: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80032e4: 441a add r2, r3
|
|
80032e6: 68bb ldr r3, [r7, #8]
|
|
80032e8: 615a str r2, [r3, #20]
|
|
ep->xfer_count += TxPctSize;
|
|
80032ea: 68bb ldr r3, [r7, #8]
|
|
80032ec: 69da ldr r2, [r3, #28]
|
|
80032ee: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80032f2: 441a add r2, r3
|
|
80032f4: 68bb ldr r3, [r7, #8]
|
|
80032f6: 61da str r2, [r3, #28]
|
|
|
|
/* Calculate the len of the new buffer to fill */
|
|
if (ep->xfer_len_db >= ep->maxpacket)
|
|
80032f8: 68bb ldr r3, [r7, #8]
|
|
80032fa: 6a1a ldr r2, [r3, #32]
|
|
80032fc: 68bb ldr r3, [r7, #8]
|
|
80032fe: 691b ldr r3, [r3, #16]
|
|
8003300: 429a cmp r2, r3
|
|
8003302: d30b bcc.n 800331c <HAL_PCD_EP_DB_Transmit+0x27e>
|
|
{
|
|
len = ep->maxpacket;
|
|
8003304: 68bb ldr r3, [r7, #8]
|
|
8003306: 691b ldr r3, [r3, #16]
|
|
8003308: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
ep->xfer_len_db -= len;
|
|
800330c: 68bb ldr r3, [r7, #8]
|
|
800330e: 6a1a ldr r2, [r3, #32]
|
|
8003310: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003314: 1ad2 subs r2, r2, r3
|
|
8003316: 68bb ldr r3, [r7, #8]
|
|
8003318: 621a str r2, [r3, #32]
|
|
800331a: e017 b.n 800334c <HAL_PCD_EP_DB_Transmit+0x2ae>
|
|
}
|
|
else if (ep->xfer_len_db == 0U)
|
|
800331c: 68bb ldr r3, [r7, #8]
|
|
800331e: 6a1b ldr r3, [r3, #32]
|
|
8003320: 2b00 cmp r3, #0
|
|
8003322: d108 bne.n 8003336 <HAL_PCD_EP_DB_Transmit+0x298>
|
|
{
|
|
len = TxPctSize;
|
|
8003324: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
8003328: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
ep->xfer_fill_db = 0U;
|
|
800332c: 68bb ldr r3, [r7, #8]
|
|
800332e: 2200 movs r2, #0
|
|
8003330: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
8003334: e00a b.n 800334c <HAL_PCD_EP_DB_Transmit+0x2ae>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_fill_db = 0U;
|
|
8003336: 68bb ldr r3, [r7, #8]
|
|
8003338: 2200 movs r2, #0
|
|
800333a: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
len = ep->xfer_len_db;
|
|
800333e: 68bb ldr r3, [r7, #8]
|
|
8003340: 6a1b ldr r3, [r3, #32]
|
|
8003342: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
ep->xfer_len_db = 0U;
|
|
8003346: 68bb ldr r3, [r7, #8]
|
|
8003348: 2200 movs r2, #0
|
|
800334a: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
/* Write remaining Data to Buffer */
|
|
/* Set the Double buffer counter for pma buffer1 */
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
|
800334c: 68bb ldr r3, [r7, #8]
|
|
800334e: 785b ldrb r3, [r3, #1]
|
|
8003350: 2b00 cmp r3, #0
|
|
8003352: d165 bne.n 8003420 <HAL_PCD_EP_DB_Transmit+0x382>
|
|
8003354: 68fb ldr r3, [r7, #12]
|
|
8003356: 681b ldr r3, [r3, #0]
|
|
8003358: 63fb str r3, [r7, #60] @ 0x3c
|
|
800335a: 68fb ldr r3, [r7, #12]
|
|
800335c: 681b ldr r3, [r3, #0]
|
|
800335e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003362: b29b uxth r3, r3
|
|
8003364: 461a mov r2, r3
|
|
8003366: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8003368: 4413 add r3, r2
|
|
800336a: 63fb str r3, [r7, #60] @ 0x3c
|
|
800336c: 68bb ldr r3, [r7, #8]
|
|
800336e: 781b ldrb r3, [r3, #0]
|
|
8003370: 011a lsls r2, r3, #4
|
|
8003372: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8003374: 4413 add r3, r2
|
|
8003376: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800337a: 63bb str r3, [r7, #56] @ 0x38
|
|
800337c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800337e: 881b ldrh r3, [r3, #0]
|
|
8003380: b29b uxth r3, r3
|
|
8003382: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8003386: b29a uxth r2, r3
|
|
8003388: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800338a: 801a strh r2, [r3, #0]
|
|
800338c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003390: 2b3e cmp r3, #62 @ 0x3e
|
|
8003392: d91d bls.n 80033d0 <HAL_PCD_EP_DB_Transmit+0x332>
|
|
8003394: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003398: 095b lsrs r3, r3, #5
|
|
800339a: 64bb str r3, [r7, #72] @ 0x48
|
|
800339c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80033a0: f003 031f and.w r3, r3, #31
|
|
80033a4: 2b00 cmp r3, #0
|
|
80033a6: d102 bne.n 80033ae <HAL_PCD_EP_DB_Transmit+0x310>
|
|
80033a8: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80033aa: 3b01 subs r3, #1
|
|
80033ac: 64bb str r3, [r7, #72] @ 0x48
|
|
80033ae: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80033b0: 881b ldrh r3, [r3, #0]
|
|
80033b2: b29a uxth r2, r3
|
|
80033b4: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80033b6: b29b uxth r3, r3
|
|
80033b8: 029b lsls r3, r3, #10
|
|
80033ba: b29b uxth r3, r3
|
|
80033bc: 4313 orrs r3, r2
|
|
80033be: b29b uxth r3, r3
|
|
80033c0: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80033c4: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80033c8: b29a uxth r2, r3
|
|
80033ca: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80033cc: 801a strh r2, [r3, #0]
|
|
80033ce: e044 b.n 800345a <HAL_PCD_EP_DB_Transmit+0x3bc>
|
|
80033d0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80033d4: 2b00 cmp r3, #0
|
|
80033d6: d10a bne.n 80033ee <HAL_PCD_EP_DB_Transmit+0x350>
|
|
80033d8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80033da: 881b ldrh r3, [r3, #0]
|
|
80033dc: b29b uxth r3, r3
|
|
80033de: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80033e2: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80033e6: b29a uxth r2, r3
|
|
80033e8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80033ea: 801a strh r2, [r3, #0]
|
|
80033ec: e035 b.n 800345a <HAL_PCD_EP_DB_Transmit+0x3bc>
|
|
80033ee: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80033f2: 085b lsrs r3, r3, #1
|
|
80033f4: 64bb str r3, [r7, #72] @ 0x48
|
|
80033f6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80033fa: f003 0301 and.w r3, r3, #1
|
|
80033fe: 2b00 cmp r3, #0
|
|
8003400: d002 beq.n 8003408 <HAL_PCD_EP_DB_Transmit+0x36a>
|
|
8003402: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8003404: 3301 adds r3, #1
|
|
8003406: 64bb str r3, [r7, #72] @ 0x48
|
|
8003408: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800340a: 881b ldrh r3, [r3, #0]
|
|
800340c: b29a uxth r2, r3
|
|
800340e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8003410: b29b uxth r3, r3
|
|
8003412: 029b lsls r3, r3, #10
|
|
8003414: b29b uxth r3, r3
|
|
8003416: 4313 orrs r3, r2
|
|
8003418: b29a uxth r2, r3
|
|
800341a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800341c: 801a strh r2, [r3, #0]
|
|
800341e: e01c b.n 800345a <HAL_PCD_EP_DB_Transmit+0x3bc>
|
|
8003420: 68bb ldr r3, [r7, #8]
|
|
8003422: 785b ldrb r3, [r3, #1]
|
|
8003424: 2b01 cmp r3, #1
|
|
8003426: d118 bne.n 800345a <HAL_PCD_EP_DB_Transmit+0x3bc>
|
|
8003428: 68fb ldr r3, [r7, #12]
|
|
800342a: 681b ldr r3, [r3, #0]
|
|
800342c: 647b str r3, [r7, #68] @ 0x44
|
|
800342e: 68fb ldr r3, [r7, #12]
|
|
8003430: 681b ldr r3, [r3, #0]
|
|
8003432: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003436: b29b uxth r3, r3
|
|
8003438: 461a mov r2, r3
|
|
800343a: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800343c: 4413 add r3, r2
|
|
800343e: 647b str r3, [r7, #68] @ 0x44
|
|
8003440: 68bb ldr r3, [r7, #8]
|
|
8003442: 781b ldrb r3, [r3, #0]
|
|
8003444: 011a lsls r2, r3, #4
|
|
8003446: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8003448: 4413 add r3, r2
|
|
800344a: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800344e: 643b str r3, [r7, #64] @ 0x40
|
|
8003450: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003454: b29a uxth r2, r3
|
|
8003456: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8003458: 801a strh r2, [r3, #0]
|
|
|
|
/* Copy user buffer to USB PMA */
|
|
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
|
|
800345a: 68fb ldr r3, [r7, #12]
|
|
800345c: 6818 ldr r0, [r3, #0]
|
|
800345e: 68bb ldr r3, [r7, #8]
|
|
8003460: 6959 ldr r1, [r3, #20]
|
|
8003462: 68bb ldr r3, [r7, #8]
|
|
8003464: 891a ldrh r2, [r3, #8]
|
|
8003466: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800346a: b29b uxth r3, r3
|
|
800346c: f004 f967 bl 800773e <USB_WritePMA>
|
|
8003470: e1e2 b.n 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
}
|
|
}
|
|
else /* Data Buffer1 ACK received */
|
|
{
|
|
/* multi-packet on the NON control IN endpoint */
|
|
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
|
8003472: 68fb ldr r3, [r7, #12]
|
|
8003474: 681b ldr r3, [r3, #0]
|
|
8003476: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800347a: b29b uxth r3, r3
|
|
800347c: 461a mov r2, r3
|
|
800347e: 68bb ldr r3, [r7, #8]
|
|
8003480: 781b ldrb r3, [r3, #0]
|
|
8003482: 00db lsls r3, r3, #3
|
|
8003484: 4413 add r3, r2
|
|
8003486: 3306 adds r3, #6
|
|
8003488: 005b lsls r3, r3, #1
|
|
800348a: 68fa ldr r2, [r7, #12]
|
|
800348c: 6812 ldr r2, [r2, #0]
|
|
800348e: 4413 add r3, r2
|
|
8003490: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8003494: 881b ldrh r3, [r3, #0]
|
|
8003496: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800349a: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
|
|
|
|
if (ep->xfer_len >= TxPctSize)
|
|
800349e: 68bb ldr r3, [r7, #8]
|
|
80034a0: 699a ldr r2, [r3, #24]
|
|
80034a2: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80034a6: 429a cmp r2, r3
|
|
80034a8: d307 bcc.n 80034ba <HAL_PCD_EP_DB_Transmit+0x41c>
|
|
{
|
|
ep->xfer_len -= TxPctSize;
|
|
80034aa: 68bb ldr r3, [r7, #8]
|
|
80034ac: 699a ldr r2, [r3, #24]
|
|
80034ae: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80034b2: 1ad2 subs r2, r2, r3
|
|
80034b4: 68bb ldr r3, [r7, #8]
|
|
80034b6: 619a str r2, [r3, #24]
|
|
80034b8: e002 b.n 80034c0 <HAL_PCD_EP_DB_Transmit+0x422>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
80034ba: 68bb ldr r3, [r7, #8]
|
|
80034bc: 2200 movs r2, #0
|
|
80034be: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Transfer is completed */
|
|
if (ep->xfer_len == 0U)
|
|
80034c0: 68bb ldr r3, [r7, #8]
|
|
80034c2: 699b ldr r3, [r3, #24]
|
|
80034c4: 2b00 cmp r3, #0
|
|
80034c6: f040 80c0 bne.w 800364a <HAL_PCD_EP_DB_Transmit+0x5ac>
|
|
{
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
80034ca: 68bb ldr r3, [r7, #8]
|
|
80034cc: 785b ldrb r3, [r3, #1]
|
|
80034ce: 2b00 cmp r3, #0
|
|
80034d0: d126 bne.n 8003520 <HAL_PCD_EP_DB_Transmit+0x482>
|
|
80034d2: 68fb ldr r3, [r7, #12]
|
|
80034d4: 681b ldr r3, [r3, #0]
|
|
80034d6: 67fb str r3, [r7, #124] @ 0x7c
|
|
80034d8: 68fb ldr r3, [r7, #12]
|
|
80034da: 681b ldr r3, [r3, #0]
|
|
80034dc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80034e0: b29b uxth r3, r3
|
|
80034e2: 461a mov r2, r3
|
|
80034e4: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
80034e6: 4413 add r3, r2
|
|
80034e8: 67fb str r3, [r7, #124] @ 0x7c
|
|
80034ea: 68bb ldr r3, [r7, #8]
|
|
80034ec: 781b ldrb r3, [r3, #0]
|
|
80034ee: 011a lsls r2, r3, #4
|
|
80034f0: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
80034f2: 4413 add r3, r2
|
|
80034f4: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
80034f8: 67bb str r3, [r7, #120] @ 0x78
|
|
80034fa: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80034fc: 881b ldrh r3, [r3, #0]
|
|
80034fe: b29b uxth r3, r3
|
|
8003500: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8003504: b29a uxth r2, r3
|
|
8003506: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8003508: 801a strh r2, [r3, #0]
|
|
800350a: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800350c: 881b ldrh r3, [r3, #0]
|
|
800350e: b29b uxth r3, r3
|
|
8003510: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8003514: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8003518: b29a uxth r2, r3
|
|
800351a: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800351c: 801a strh r2, [r3, #0]
|
|
800351e: e01a b.n 8003556 <HAL_PCD_EP_DB_Transmit+0x4b8>
|
|
8003520: 68bb ldr r3, [r7, #8]
|
|
8003522: 785b ldrb r3, [r3, #1]
|
|
8003524: 2b01 cmp r3, #1
|
|
8003526: d116 bne.n 8003556 <HAL_PCD_EP_DB_Transmit+0x4b8>
|
|
8003528: 68fb ldr r3, [r7, #12]
|
|
800352a: 681b ldr r3, [r3, #0]
|
|
800352c: 667b str r3, [r7, #100] @ 0x64
|
|
800352e: 68fb ldr r3, [r7, #12]
|
|
8003530: 681b ldr r3, [r3, #0]
|
|
8003532: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003536: b29b uxth r3, r3
|
|
8003538: 461a mov r2, r3
|
|
800353a: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800353c: 4413 add r3, r2
|
|
800353e: 667b str r3, [r7, #100] @ 0x64
|
|
8003540: 68bb ldr r3, [r7, #8]
|
|
8003542: 781b ldrb r3, [r3, #0]
|
|
8003544: 011a lsls r2, r3, #4
|
|
8003546: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8003548: 4413 add r3, r2
|
|
800354a: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800354e: 663b str r3, [r7, #96] @ 0x60
|
|
8003550: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8003552: 2200 movs r2, #0
|
|
8003554: 801a strh r2, [r3, #0]
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
8003556: 68fb ldr r3, [r7, #12]
|
|
8003558: 681b ldr r3, [r3, #0]
|
|
800355a: 677b str r3, [r7, #116] @ 0x74
|
|
800355c: 68bb ldr r3, [r7, #8]
|
|
800355e: 785b ldrb r3, [r3, #1]
|
|
8003560: 2b00 cmp r3, #0
|
|
8003562: d12b bne.n 80035bc <HAL_PCD_EP_DB_Transmit+0x51e>
|
|
8003564: 68fb ldr r3, [r7, #12]
|
|
8003566: 681b ldr r3, [r3, #0]
|
|
8003568: 66fb str r3, [r7, #108] @ 0x6c
|
|
800356a: 68fb ldr r3, [r7, #12]
|
|
800356c: 681b ldr r3, [r3, #0]
|
|
800356e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003572: b29b uxth r3, r3
|
|
8003574: 461a mov r2, r3
|
|
8003576: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8003578: 4413 add r3, r2
|
|
800357a: 66fb str r3, [r7, #108] @ 0x6c
|
|
800357c: 68bb ldr r3, [r7, #8]
|
|
800357e: 781b ldrb r3, [r3, #0]
|
|
8003580: 011a lsls r2, r3, #4
|
|
8003582: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8003584: 4413 add r3, r2
|
|
8003586: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
800358a: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
800358e: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8003592: 881b ldrh r3, [r3, #0]
|
|
8003594: b29b uxth r3, r3
|
|
8003596: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800359a: b29a uxth r2, r3
|
|
800359c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80035a0: 801a strh r2, [r3, #0]
|
|
80035a2: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80035a6: 881b ldrh r3, [r3, #0]
|
|
80035a8: b29b uxth r3, r3
|
|
80035aa: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80035ae: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80035b2: b29a uxth r2, r3
|
|
80035b4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80035b8: 801a strh r2, [r3, #0]
|
|
80035ba: e017 b.n 80035ec <HAL_PCD_EP_DB_Transmit+0x54e>
|
|
80035bc: 68bb ldr r3, [r7, #8]
|
|
80035be: 785b ldrb r3, [r3, #1]
|
|
80035c0: 2b01 cmp r3, #1
|
|
80035c2: d113 bne.n 80035ec <HAL_PCD_EP_DB_Transmit+0x54e>
|
|
80035c4: 68fb ldr r3, [r7, #12]
|
|
80035c6: 681b ldr r3, [r3, #0]
|
|
80035c8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80035cc: b29b uxth r3, r3
|
|
80035ce: 461a mov r2, r3
|
|
80035d0: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80035d2: 4413 add r3, r2
|
|
80035d4: 677b str r3, [r7, #116] @ 0x74
|
|
80035d6: 68bb ldr r3, [r7, #8]
|
|
80035d8: 781b ldrb r3, [r3, #0]
|
|
80035da: 011a lsls r2, r3, #4
|
|
80035dc: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80035de: 4413 add r3, r2
|
|
80035e0: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
80035e4: 673b str r3, [r7, #112] @ 0x70
|
|
80035e6: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80035e8: 2200 movs r2, #0
|
|
80035ea: 801a strh r2, [r3, #0]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
80035ec: 68bb ldr r3, [r7, #8]
|
|
80035ee: 781b ldrb r3, [r3, #0]
|
|
80035f0: 4619 mov r1, r3
|
|
80035f2: 68f8 ldr r0, [r7, #12]
|
|
80035f4: f005 ff67 bl 80094c6 <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
/* need to Free USB Buff */
|
|
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
|
80035f8: 88fb ldrh r3, [r7, #6]
|
|
80035fa: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80035fe: 2b00 cmp r3, #0
|
|
8003600: f040 811a bne.w 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
8003604: 68fb ldr r3, [r7, #12]
|
|
8003606: 681b ldr r3, [r3, #0]
|
|
8003608: 461a mov r2, r3
|
|
800360a: 68bb ldr r3, [r7, #8]
|
|
800360c: 781b ldrb r3, [r3, #0]
|
|
800360e: 009b lsls r3, r3, #2
|
|
8003610: 4413 add r3, r2
|
|
8003612: 881b ldrh r3, [r3, #0]
|
|
8003614: b29b uxth r3, r3
|
|
8003616: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800361a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800361e: f8a7 3088 strh.w r3, [r7, #136] @ 0x88
|
|
8003622: 68fb ldr r3, [r7, #12]
|
|
8003624: 681b ldr r3, [r3, #0]
|
|
8003626: 461a mov r2, r3
|
|
8003628: 68bb ldr r3, [r7, #8]
|
|
800362a: 781b ldrb r3, [r3, #0]
|
|
800362c: 009b lsls r3, r3, #2
|
|
800362e: 441a add r2, r3
|
|
8003630: f8b7 3088 ldrh.w r3, [r7, #136] @ 0x88
|
|
8003634: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8003638: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800363c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8003640: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8003644: b29b uxth r3, r3
|
|
8003646: 8013 strh r3, [r2, #0]
|
|
8003648: e0f6 b.n 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
}
|
|
}
|
|
else /* Transfer is not yet Done */
|
|
{
|
|
/* need to Free USB Buff */
|
|
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
|
800364a: 88fb ldrh r3, [r7, #6]
|
|
800364c: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8003650: 2b00 cmp r3, #0
|
|
8003652: d121 bne.n 8003698 <HAL_PCD_EP_DB_Transmit+0x5fa>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
8003654: 68fb ldr r3, [r7, #12]
|
|
8003656: 681b ldr r3, [r3, #0]
|
|
8003658: 461a mov r2, r3
|
|
800365a: 68bb ldr r3, [r7, #8]
|
|
800365c: 781b ldrb r3, [r3, #0]
|
|
800365e: 009b lsls r3, r3, #2
|
|
8003660: 4413 add r3, r2
|
|
8003662: 881b ldrh r3, [r3, #0]
|
|
8003664: b29b uxth r3, r3
|
|
8003666: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800366a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800366e: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
8003672: 68fb ldr r3, [r7, #12]
|
|
8003674: 681b ldr r3, [r3, #0]
|
|
8003676: 461a mov r2, r3
|
|
8003678: 68bb ldr r3, [r7, #8]
|
|
800367a: 781b ldrb r3, [r3, #0]
|
|
800367c: 009b lsls r3, r3, #2
|
|
800367e: 441a add r2, r3
|
|
8003680: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
8003684: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8003688: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800368c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8003690: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8003694: b29b uxth r3, r3
|
|
8003696: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Still there is data to Fill in the next Buffer */
|
|
if (ep->xfer_fill_db == 1U)
|
|
8003698: 68bb ldr r3, [r7, #8]
|
|
800369a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
800369e: 2b01 cmp r3, #1
|
|
80036a0: f040 80ca bne.w 8003838 <HAL_PCD_EP_DB_Transmit+0x79a>
|
|
{
|
|
ep->xfer_buff += TxPctSize;
|
|
80036a4: 68bb ldr r3, [r7, #8]
|
|
80036a6: 695a ldr r2, [r3, #20]
|
|
80036a8: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80036ac: 441a add r2, r3
|
|
80036ae: 68bb ldr r3, [r7, #8]
|
|
80036b0: 615a str r2, [r3, #20]
|
|
ep->xfer_count += TxPctSize;
|
|
80036b2: 68bb ldr r3, [r7, #8]
|
|
80036b4: 69da ldr r2, [r3, #28]
|
|
80036b6: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80036ba: 441a add r2, r3
|
|
80036bc: 68bb ldr r3, [r7, #8]
|
|
80036be: 61da str r2, [r3, #28]
|
|
|
|
/* Calculate the len of the new buffer to fill */
|
|
if (ep->xfer_len_db >= ep->maxpacket)
|
|
80036c0: 68bb ldr r3, [r7, #8]
|
|
80036c2: 6a1a ldr r2, [r3, #32]
|
|
80036c4: 68bb ldr r3, [r7, #8]
|
|
80036c6: 691b ldr r3, [r3, #16]
|
|
80036c8: 429a cmp r2, r3
|
|
80036ca: d30b bcc.n 80036e4 <HAL_PCD_EP_DB_Transmit+0x646>
|
|
{
|
|
len = ep->maxpacket;
|
|
80036cc: 68bb ldr r3, [r7, #8]
|
|
80036ce: 691b ldr r3, [r3, #16]
|
|
80036d0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
ep->xfer_len_db -= len;
|
|
80036d4: 68bb ldr r3, [r7, #8]
|
|
80036d6: 6a1a ldr r2, [r3, #32]
|
|
80036d8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80036dc: 1ad2 subs r2, r2, r3
|
|
80036de: 68bb ldr r3, [r7, #8]
|
|
80036e0: 621a str r2, [r3, #32]
|
|
80036e2: e017 b.n 8003714 <HAL_PCD_EP_DB_Transmit+0x676>
|
|
}
|
|
else if (ep->xfer_len_db == 0U)
|
|
80036e4: 68bb ldr r3, [r7, #8]
|
|
80036e6: 6a1b ldr r3, [r3, #32]
|
|
80036e8: 2b00 cmp r3, #0
|
|
80036ea: d108 bne.n 80036fe <HAL_PCD_EP_DB_Transmit+0x660>
|
|
{
|
|
len = TxPctSize;
|
|
80036ec: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
80036f0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
ep->xfer_fill_db = 0U;
|
|
80036f4: 68bb ldr r3, [r7, #8]
|
|
80036f6: 2200 movs r2, #0
|
|
80036f8: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
80036fc: e00a b.n 8003714 <HAL_PCD_EP_DB_Transmit+0x676>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
80036fe: 68bb ldr r3, [r7, #8]
|
|
8003700: 6a1b ldr r3, [r3, #32]
|
|
8003702: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
ep->xfer_len_db = 0U;
|
|
8003706: 68bb ldr r3, [r7, #8]
|
|
8003708: 2200 movs r2, #0
|
|
800370a: 621a str r2, [r3, #32]
|
|
ep->xfer_fill_db = 0;
|
|
800370c: 68bb ldr r3, [r7, #8]
|
|
800370e: 2200 movs r2, #0
|
|
8003710: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
}
|
|
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
|
8003714: 68fb ldr r3, [r7, #12]
|
|
8003716: 681b ldr r3, [r3, #0]
|
|
8003718: 657b str r3, [r7, #84] @ 0x54
|
|
800371a: 68bb ldr r3, [r7, #8]
|
|
800371c: 785b ldrb r3, [r3, #1]
|
|
800371e: 2b00 cmp r3, #0
|
|
8003720: d165 bne.n 80037ee <HAL_PCD_EP_DB_Transmit+0x750>
|
|
8003722: 68fb ldr r3, [r7, #12]
|
|
8003724: 681b ldr r3, [r3, #0]
|
|
8003726: 65fb str r3, [r7, #92] @ 0x5c
|
|
8003728: 68fb ldr r3, [r7, #12]
|
|
800372a: 681b ldr r3, [r3, #0]
|
|
800372c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8003730: b29b uxth r3, r3
|
|
8003732: 461a mov r2, r3
|
|
8003734: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8003736: 4413 add r3, r2
|
|
8003738: 65fb str r3, [r7, #92] @ 0x5c
|
|
800373a: 68bb ldr r3, [r7, #8]
|
|
800373c: 781b ldrb r3, [r3, #0]
|
|
800373e: 011a lsls r2, r3, #4
|
|
8003740: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8003742: 4413 add r3, r2
|
|
8003744: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8003748: 65bb str r3, [r7, #88] @ 0x58
|
|
800374a: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800374c: 881b ldrh r3, [r3, #0]
|
|
800374e: b29b uxth r3, r3
|
|
8003750: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8003754: b29a uxth r2, r3
|
|
8003756: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8003758: 801a strh r2, [r3, #0]
|
|
800375a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800375e: 2b3e cmp r3, #62 @ 0x3e
|
|
8003760: d91d bls.n 800379e <HAL_PCD_EP_DB_Transmit+0x700>
|
|
8003762: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003766: 095b lsrs r3, r3, #5
|
|
8003768: 66bb str r3, [r7, #104] @ 0x68
|
|
800376a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800376e: f003 031f and.w r3, r3, #31
|
|
8003772: 2b00 cmp r3, #0
|
|
8003774: d102 bne.n 800377c <HAL_PCD_EP_DB_Transmit+0x6de>
|
|
8003776: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8003778: 3b01 subs r3, #1
|
|
800377a: 66bb str r3, [r7, #104] @ 0x68
|
|
800377c: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800377e: 881b ldrh r3, [r3, #0]
|
|
8003780: b29a uxth r2, r3
|
|
8003782: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8003784: b29b uxth r3, r3
|
|
8003786: 029b lsls r3, r3, #10
|
|
8003788: b29b uxth r3, r3
|
|
800378a: 4313 orrs r3, r2
|
|
800378c: b29b uxth r3, r3
|
|
800378e: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8003792: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8003796: b29a uxth r2, r3
|
|
8003798: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800379a: 801a strh r2, [r3, #0]
|
|
800379c: e041 b.n 8003822 <HAL_PCD_EP_DB_Transmit+0x784>
|
|
800379e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80037a2: 2b00 cmp r3, #0
|
|
80037a4: d10a bne.n 80037bc <HAL_PCD_EP_DB_Transmit+0x71e>
|
|
80037a6: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80037a8: 881b ldrh r3, [r3, #0]
|
|
80037aa: b29b uxth r3, r3
|
|
80037ac: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80037b0: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80037b4: b29a uxth r2, r3
|
|
80037b6: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80037b8: 801a strh r2, [r3, #0]
|
|
80037ba: e032 b.n 8003822 <HAL_PCD_EP_DB_Transmit+0x784>
|
|
80037bc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80037c0: 085b lsrs r3, r3, #1
|
|
80037c2: 66bb str r3, [r7, #104] @ 0x68
|
|
80037c4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80037c8: f003 0301 and.w r3, r3, #1
|
|
80037cc: 2b00 cmp r3, #0
|
|
80037ce: d002 beq.n 80037d6 <HAL_PCD_EP_DB_Transmit+0x738>
|
|
80037d0: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80037d2: 3301 adds r3, #1
|
|
80037d4: 66bb str r3, [r7, #104] @ 0x68
|
|
80037d6: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80037d8: 881b ldrh r3, [r3, #0]
|
|
80037da: b29a uxth r2, r3
|
|
80037dc: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80037de: b29b uxth r3, r3
|
|
80037e0: 029b lsls r3, r3, #10
|
|
80037e2: b29b uxth r3, r3
|
|
80037e4: 4313 orrs r3, r2
|
|
80037e6: b29a uxth r2, r3
|
|
80037e8: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80037ea: 801a strh r2, [r3, #0]
|
|
80037ec: e019 b.n 8003822 <HAL_PCD_EP_DB_Transmit+0x784>
|
|
80037ee: 68bb ldr r3, [r7, #8]
|
|
80037f0: 785b ldrb r3, [r3, #1]
|
|
80037f2: 2b01 cmp r3, #1
|
|
80037f4: d115 bne.n 8003822 <HAL_PCD_EP_DB_Transmit+0x784>
|
|
80037f6: 68fb ldr r3, [r7, #12]
|
|
80037f8: 681b ldr r3, [r3, #0]
|
|
80037fa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80037fe: b29b uxth r3, r3
|
|
8003800: 461a mov r2, r3
|
|
8003802: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8003804: 4413 add r3, r2
|
|
8003806: 657b str r3, [r7, #84] @ 0x54
|
|
8003808: 68bb ldr r3, [r7, #8]
|
|
800380a: 781b ldrb r3, [r3, #0]
|
|
800380c: 011a lsls r2, r3, #4
|
|
800380e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8003810: 4413 add r3, r2
|
|
8003812: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8003816: 653b str r3, [r7, #80] @ 0x50
|
|
8003818: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800381c: b29a uxth r2, r3
|
|
800381e: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8003820: 801a strh r2, [r3, #0]
|
|
|
|
/* Copy the user buffer to USB PMA */
|
|
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
|
|
8003822: 68fb ldr r3, [r7, #12]
|
|
8003824: 6818 ldr r0, [r3, #0]
|
|
8003826: 68bb ldr r3, [r7, #8]
|
|
8003828: 6959 ldr r1, [r3, #20]
|
|
800382a: 68bb ldr r3, [r7, #8]
|
|
800382c: 895a ldrh r2, [r3, #10]
|
|
800382e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003832: b29b uxth r3, r3
|
|
8003834: f003 ff83 bl 800773e <USB_WritePMA>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*enable endpoint IN*/
|
|
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
|
|
8003838: 68fb ldr r3, [r7, #12]
|
|
800383a: 681b ldr r3, [r3, #0]
|
|
800383c: 461a mov r2, r3
|
|
800383e: 68bb ldr r3, [r7, #8]
|
|
8003840: 781b ldrb r3, [r3, #0]
|
|
8003842: 009b lsls r3, r3, #2
|
|
8003844: 4413 add r3, r2
|
|
8003846: 881b ldrh r3, [r3, #0]
|
|
8003848: b29b uxth r3, r3
|
|
800384a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800384e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8003852: 82bb strh r3, [r7, #20]
|
|
8003854: 8abb ldrh r3, [r7, #20]
|
|
8003856: f083 0310 eor.w r3, r3, #16
|
|
800385a: 82bb strh r3, [r7, #20]
|
|
800385c: 8abb ldrh r3, [r7, #20]
|
|
800385e: f083 0320 eor.w r3, r3, #32
|
|
8003862: 82bb strh r3, [r7, #20]
|
|
8003864: 68fb ldr r3, [r7, #12]
|
|
8003866: 681b ldr r3, [r3, #0]
|
|
8003868: 461a mov r2, r3
|
|
800386a: 68bb ldr r3, [r7, #8]
|
|
800386c: 781b ldrb r3, [r3, #0]
|
|
800386e: 009b lsls r3, r3, #2
|
|
8003870: 441a add r2, r3
|
|
8003872: 8abb ldrh r3, [r7, #20]
|
|
8003874: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8003878: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800387c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8003880: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8003884: b29b uxth r3, r3
|
|
8003886: 8013 strh r3, [r2, #0]
|
|
|
|
return HAL_OK;
|
|
8003888: 2300 movs r3, #0
|
|
}
|
|
800388a: 4618 mov r0, r3
|
|
800388c: 3790 adds r7, #144 @ 0x90
|
|
800388e: 46bd mov sp, r7
|
|
8003890: bd80 pop {r7, pc}
|
|
|
|
08003892 <HAL_PCDEx_PMAConfig>:
|
|
* @retval HAL status
|
|
*/
|
|
|
|
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
|
uint16_t ep_kind, uint32_t pmaadress)
|
|
{
|
|
8003892: b480 push {r7}
|
|
8003894: b087 sub sp, #28
|
|
8003896: af00 add r7, sp, #0
|
|
8003898: 60f8 str r0, [r7, #12]
|
|
800389a: 607b str r3, [r7, #4]
|
|
800389c: 460b mov r3, r1
|
|
800389e: 817b strh r3, [r7, #10]
|
|
80038a0: 4613 mov r3, r2
|
|
80038a2: 813b strh r3, [r7, #8]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
/* initialize ep structure*/
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
80038a4: 897b ldrh r3, [r7, #10]
|
|
80038a6: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80038aa: b29b uxth r3, r3
|
|
80038ac: 2b00 cmp r3, #0
|
|
80038ae: d00b beq.n 80038c8 <HAL_PCDEx_PMAConfig+0x36>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
80038b0: 897b ldrh r3, [r7, #10]
|
|
80038b2: f003 0207 and.w r2, r3, #7
|
|
80038b6: 4613 mov r3, r2
|
|
80038b8: 009b lsls r3, r3, #2
|
|
80038ba: 4413 add r3, r2
|
|
80038bc: 00db lsls r3, r3, #3
|
|
80038be: 3310 adds r3, #16
|
|
80038c0: 68fa ldr r2, [r7, #12]
|
|
80038c2: 4413 add r3, r2
|
|
80038c4: 617b str r3, [r7, #20]
|
|
80038c6: e009 b.n 80038dc <HAL_PCDEx_PMAConfig+0x4a>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
80038c8: 897a ldrh r2, [r7, #10]
|
|
80038ca: 4613 mov r3, r2
|
|
80038cc: 009b lsls r3, r3, #2
|
|
80038ce: 4413 add r3, r2
|
|
80038d0: 00db lsls r3, r3, #3
|
|
80038d2: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80038d6: 68fa ldr r2, [r7, #12]
|
|
80038d8: 4413 add r3, r2
|
|
80038da: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Here we check if the endpoint is single or double Buffer*/
|
|
if (ep_kind == PCD_SNG_BUF)
|
|
80038dc: 893b ldrh r3, [r7, #8]
|
|
80038de: 2b00 cmp r3, #0
|
|
80038e0: d107 bne.n 80038f2 <HAL_PCDEx_PMAConfig+0x60>
|
|
{
|
|
/* Single Buffer */
|
|
ep->doublebuffer = 0U;
|
|
80038e2: 697b ldr r3, [r7, #20]
|
|
80038e4: 2200 movs r2, #0
|
|
80038e6: 731a strb r2, [r3, #12]
|
|
/* Configure the PMA */
|
|
ep->pmaadress = (uint16_t)pmaadress;
|
|
80038e8: 687b ldr r3, [r7, #4]
|
|
80038ea: b29a uxth r2, r3
|
|
80038ec: 697b ldr r3, [r7, #20]
|
|
80038ee: 80da strh r2, [r3, #6]
|
|
80038f0: e00b b.n 800390a <HAL_PCDEx_PMAConfig+0x78>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else /* USB_DBL_BUF */
|
|
{
|
|
/* Double Buffer Endpoint */
|
|
ep->doublebuffer = 1U;
|
|
80038f2: 697b ldr r3, [r7, #20]
|
|
80038f4: 2201 movs r2, #1
|
|
80038f6: 731a strb r2, [r3, #12]
|
|
/* Configure the PMA */
|
|
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
|
|
80038f8: 687b ldr r3, [r7, #4]
|
|
80038fa: b29a uxth r2, r3
|
|
80038fc: 697b ldr r3, [r7, #20]
|
|
80038fe: 811a strh r2, [r3, #8]
|
|
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
|
|
8003900: 687b ldr r3, [r7, #4]
|
|
8003902: 0c1b lsrs r3, r3, #16
|
|
8003904: b29a uxth r2, r3
|
|
8003906: 697b ldr r3, [r7, #20]
|
|
8003908: 815a strh r2, [r3, #10]
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
return HAL_OK;
|
|
800390a: 2300 movs r3, #0
|
|
}
|
|
800390c: 4618 mov r0, r3
|
|
800390e: 371c adds r7, #28
|
|
8003910: 46bd mov sp, r7
|
|
8003912: bc80 pop {r7}
|
|
8003914: 4770 bx lr
|
|
...
|
|
|
|
08003918 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8003918: b580 push {r7, lr}
|
|
800391a: b086 sub sp, #24
|
|
800391c: af00 add r7, sp, #0
|
|
800391e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8003920: 687b ldr r3, [r7, #4]
|
|
8003922: 2b00 cmp r3, #0
|
|
8003924: d101 bne.n 800392a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003926: 2301 movs r3, #1
|
|
8003928: e272 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800392a: 687b ldr r3, [r7, #4]
|
|
800392c: 681b ldr r3, [r3, #0]
|
|
800392e: f003 0301 and.w r3, r3, #1
|
|
8003932: 2b00 cmp r3, #0
|
|
8003934: f000 8087 beq.w 8003a46 <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8003938: 4b92 ldr r3, [pc, #584] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
800393a: 685b ldr r3, [r3, #4]
|
|
800393c: f003 030c and.w r3, r3, #12
|
|
8003940: 2b04 cmp r3, #4
|
|
8003942: d00c beq.n 800395e <HAL_RCC_OscConfig+0x46>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8003944: 4b8f ldr r3, [pc, #572] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003946: 685b ldr r3, [r3, #4]
|
|
8003948: f003 030c and.w r3, r3, #12
|
|
800394c: 2b08 cmp r3, #8
|
|
800394e: d112 bne.n 8003976 <HAL_RCC_OscConfig+0x5e>
|
|
8003950: 4b8c ldr r3, [pc, #560] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003952: 685b ldr r3, [r3, #4]
|
|
8003954: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8003958: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800395c: d10b bne.n 8003976 <HAL_RCC_OscConfig+0x5e>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
800395e: 4b89 ldr r3, [pc, #548] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003960: 681b ldr r3, [r3, #0]
|
|
8003962: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003966: 2b00 cmp r3, #0
|
|
8003968: d06c beq.n 8003a44 <HAL_RCC_OscConfig+0x12c>
|
|
800396a: 687b ldr r3, [r7, #4]
|
|
800396c: 685b ldr r3, [r3, #4]
|
|
800396e: 2b00 cmp r3, #0
|
|
8003970: d168 bne.n 8003a44 <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003972: 2301 movs r3, #1
|
|
8003974: e24c b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8003976: 687b ldr r3, [r7, #4]
|
|
8003978: 685b ldr r3, [r3, #4]
|
|
800397a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800397e: d106 bne.n 800398e <HAL_RCC_OscConfig+0x76>
|
|
8003980: 4b80 ldr r3, [pc, #512] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003982: 681b ldr r3, [r3, #0]
|
|
8003984: 4a7f ldr r2, [pc, #508] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003986: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800398a: 6013 str r3, [r2, #0]
|
|
800398c: e02e b.n 80039ec <HAL_RCC_OscConfig+0xd4>
|
|
800398e: 687b ldr r3, [r7, #4]
|
|
8003990: 685b ldr r3, [r3, #4]
|
|
8003992: 2b00 cmp r3, #0
|
|
8003994: d10c bne.n 80039b0 <HAL_RCC_OscConfig+0x98>
|
|
8003996: 4b7b ldr r3, [pc, #492] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003998: 681b ldr r3, [r3, #0]
|
|
800399a: 4a7a ldr r2, [pc, #488] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
800399c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80039a0: 6013 str r3, [r2, #0]
|
|
80039a2: 4b78 ldr r3, [pc, #480] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039a4: 681b ldr r3, [r3, #0]
|
|
80039a6: 4a77 ldr r2, [pc, #476] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039a8: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80039ac: 6013 str r3, [r2, #0]
|
|
80039ae: e01d b.n 80039ec <HAL_RCC_OscConfig+0xd4>
|
|
80039b0: 687b ldr r3, [r7, #4]
|
|
80039b2: 685b ldr r3, [r3, #4]
|
|
80039b4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
80039b8: d10c bne.n 80039d4 <HAL_RCC_OscConfig+0xbc>
|
|
80039ba: 4b72 ldr r3, [pc, #456] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039bc: 681b ldr r3, [r3, #0]
|
|
80039be: 4a71 ldr r2, [pc, #452] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039c0: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
80039c4: 6013 str r3, [r2, #0]
|
|
80039c6: 4b6f ldr r3, [pc, #444] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039c8: 681b ldr r3, [r3, #0]
|
|
80039ca: 4a6e ldr r2, [pc, #440] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039cc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80039d0: 6013 str r3, [r2, #0]
|
|
80039d2: e00b b.n 80039ec <HAL_RCC_OscConfig+0xd4>
|
|
80039d4: 4b6b ldr r3, [pc, #428] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039d6: 681b ldr r3, [r3, #0]
|
|
80039d8: 4a6a ldr r2, [pc, #424] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039da: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80039de: 6013 str r3, [r2, #0]
|
|
80039e0: 4b68 ldr r3, [pc, #416] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039e2: 681b ldr r3, [r3, #0]
|
|
80039e4: 4a67 ldr r2, [pc, #412] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
80039e6: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80039ea: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
80039ec: 687b ldr r3, [r7, #4]
|
|
80039ee: 685b ldr r3, [r3, #4]
|
|
80039f0: 2b00 cmp r3, #0
|
|
80039f2: d013 beq.n 8003a1c <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80039f4: f7fd fd4a bl 800148c <HAL_GetTick>
|
|
80039f8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
80039fa: e008 b.n 8003a0e <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80039fc: f7fd fd46 bl 800148c <HAL_GetTick>
|
|
8003a00: 4602 mov r2, r0
|
|
8003a02: 693b ldr r3, [r7, #16]
|
|
8003a04: 1ad3 subs r3, r2, r3
|
|
8003a06: 2b64 cmp r3, #100 @ 0x64
|
|
8003a08: d901 bls.n 8003a0e <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003a0a: 2303 movs r3, #3
|
|
8003a0c: e200 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8003a0e: 4b5d ldr r3, [pc, #372] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a10: 681b ldr r3, [r3, #0]
|
|
8003a12: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003a16: 2b00 cmp r3, #0
|
|
8003a18: d0f0 beq.n 80039fc <HAL_RCC_OscConfig+0xe4>
|
|
8003a1a: e014 b.n 8003a46 <HAL_RCC_OscConfig+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003a1c: f7fd fd36 bl 800148c <HAL_GetTick>
|
|
8003a20: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8003a22: e008 b.n 8003a36 <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003a24: f7fd fd32 bl 800148c <HAL_GetTick>
|
|
8003a28: 4602 mov r2, r0
|
|
8003a2a: 693b ldr r3, [r7, #16]
|
|
8003a2c: 1ad3 subs r3, r2, r3
|
|
8003a2e: 2b64 cmp r3, #100 @ 0x64
|
|
8003a30: d901 bls.n 8003a36 <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003a32: 2303 movs r3, #3
|
|
8003a34: e1ec b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8003a36: 4b53 ldr r3, [pc, #332] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a38: 681b ldr r3, [r3, #0]
|
|
8003a3a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003a3e: 2b00 cmp r3, #0
|
|
8003a40: d1f0 bne.n 8003a24 <HAL_RCC_OscConfig+0x10c>
|
|
8003a42: e000 b.n 8003a46 <HAL_RCC_OscConfig+0x12e>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8003a44: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8003a46: 687b ldr r3, [r7, #4]
|
|
8003a48: 681b ldr r3, [r3, #0]
|
|
8003a4a: f003 0302 and.w r3, r3, #2
|
|
8003a4e: 2b00 cmp r3, #0
|
|
8003a50: d063 beq.n 8003b1a <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8003a52: 4b4c ldr r3, [pc, #304] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a54: 685b ldr r3, [r3, #4]
|
|
8003a56: f003 030c and.w r3, r3, #12
|
|
8003a5a: 2b00 cmp r3, #0
|
|
8003a5c: d00b beq.n 8003a76 <HAL_RCC_OscConfig+0x15e>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
8003a5e: 4b49 ldr r3, [pc, #292] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a60: 685b ldr r3, [r3, #4]
|
|
8003a62: f003 030c and.w r3, r3, #12
|
|
8003a66: 2b08 cmp r3, #8
|
|
8003a68: d11c bne.n 8003aa4 <HAL_RCC_OscConfig+0x18c>
|
|
8003a6a: 4b46 ldr r3, [pc, #280] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a6c: 685b ldr r3, [r3, #4]
|
|
8003a6e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8003a72: 2b00 cmp r3, #0
|
|
8003a74: d116 bne.n 8003aa4 <HAL_RCC_OscConfig+0x18c>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8003a76: 4b43 ldr r3, [pc, #268] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a78: 681b ldr r3, [r3, #0]
|
|
8003a7a: f003 0302 and.w r3, r3, #2
|
|
8003a7e: 2b00 cmp r3, #0
|
|
8003a80: d005 beq.n 8003a8e <HAL_RCC_OscConfig+0x176>
|
|
8003a82: 687b ldr r3, [r7, #4]
|
|
8003a84: 691b ldr r3, [r3, #16]
|
|
8003a86: 2b01 cmp r3, #1
|
|
8003a88: d001 beq.n 8003a8e <HAL_RCC_OscConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8003a8a: 2301 movs r3, #1
|
|
8003a8c: e1c0 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003a8e: 4b3d ldr r3, [pc, #244] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a90: 681b ldr r3, [r3, #0]
|
|
8003a92: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8003a96: 687b ldr r3, [r7, #4]
|
|
8003a98: 695b ldr r3, [r3, #20]
|
|
8003a9a: 00db lsls r3, r3, #3
|
|
8003a9c: 4939 ldr r1, [pc, #228] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003a9e: 4313 orrs r3, r2
|
|
8003aa0: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8003aa2: e03a b.n 8003b1a <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8003aa4: 687b ldr r3, [r7, #4]
|
|
8003aa6: 691b ldr r3, [r3, #16]
|
|
8003aa8: 2b00 cmp r3, #0
|
|
8003aaa: d020 beq.n 8003aee <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8003aac: 4b36 ldr r3, [pc, #216] @ (8003b88 <HAL_RCC_OscConfig+0x270>)
|
|
8003aae: 2201 movs r2, #1
|
|
8003ab0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003ab2: f7fd fceb bl 800148c <HAL_GetTick>
|
|
8003ab6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8003ab8: e008 b.n 8003acc <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003aba: f7fd fce7 bl 800148c <HAL_GetTick>
|
|
8003abe: 4602 mov r2, r0
|
|
8003ac0: 693b ldr r3, [r7, #16]
|
|
8003ac2: 1ad3 subs r3, r2, r3
|
|
8003ac4: 2b02 cmp r3, #2
|
|
8003ac6: d901 bls.n 8003acc <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ac8: 2303 movs r3, #3
|
|
8003aca: e1a1 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8003acc: 4b2d ldr r3, [pc, #180] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003ace: 681b ldr r3, [r3, #0]
|
|
8003ad0: f003 0302 and.w r3, r3, #2
|
|
8003ad4: 2b00 cmp r3, #0
|
|
8003ad6: d0f0 beq.n 8003aba <HAL_RCC_OscConfig+0x1a2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003ad8: 4b2a ldr r3, [pc, #168] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003ada: 681b ldr r3, [r3, #0]
|
|
8003adc: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8003ae0: 687b ldr r3, [r7, #4]
|
|
8003ae2: 695b ldr r3, [r3, #20]
|
|
8003ae4: 00db lsls r3, r3, #3
|
|
8003ae6: 4927 ldr r1, [pc, #156] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003ae8: 4313 orrs r3, r2
|
|
8003aea: 600b str r3, [r1, #0]
|
|
8003aec: e015 b.n 8003b1a <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8003aee: 4b26 ldr r3, [pc, #152] @ (8003b88 <HAL_RCC_OscConfig+0x270>)
|
|
8003af0: 2200 movs r2, #0
|
|
8003af2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003af4: f7fd fcca bl 800148c <HAL_GetTick>
|
|
8003af8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8003afa: e008 b.n 8003b0e <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003afc: f7fd fcc6 bl 800148c <HAL_GetTick>
|
|
8003b00: 4602 mov r2, r0
|
|
8003b02: 693b ldr r3, [r7, #16]
|
|
8003b04: 1ad3 subs r3, r2, r3
|
|
8003b06: 2b02 cmp r3, #2
|
|
8003b08: d901 bls.n 8003b0e <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b0a: 2303 movs r3, #3
|
|
8003b0c: e180 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8003b0e: 4b1d ldr r3, [pc, #116] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003b10: 681b ldr r3, [r3, #0]
|
|
8003b12: f003 0302 and.w r3, r3, #2
|
|
8003b16: 2b00 cmp r3, #0
|
|
8003b18: d1f0 bne.n 8003afc <HAL_RCC_OscConfig+0x1e4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8003b1a: 687b ldr r3, [r7, #4]
|
|
8003b1c: 681b ldr r3, [r3, #0]
|
|
8003b1e: f003 0308 and.w r3, r3, #8
|
|
8003b22: 2b00 cmp r3, #0
|
|
8003b24: d03a beq.n 8003b9c <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8003b26: 687b ldr r3, [r7, #4]
|
|
8003b28: 699b ldr r3, [r3, #24]
|
|
8003b2a: 2b00 cmp r3, #0
|
|
8003b2c: d019 beq.n 8003b62 <HAL_RCC_OscConfig+0x24a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003b2e: 4b17 ldr r3, [pc, #92] @ (8003b8c <HAL_RCC_OscConfig+0x274>)
|
|
8003b30: 2201 movs r2, #1
|
|
8003b32: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003b34: f7fd fcaa bl 800148c <HAL_GetTick>
|
|
8003b38: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8003b3a: e008 b.n 8003b4e <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003b3c: f7fd fca6 bl 800148c <HAL_GetTick>
|
|
8003b40: 4602 mov r2, r0
|
|
8003b42: 693b ldr r3, [r7, #16]
|
|
8003b44: 1ad3 subs r3, r2, r3
|
|
8003b46: 2b02 cmp r3, #2
|
|
8003b48: d901 bls.n 8003b4e <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b4a: 2303 movs r3, #3
|
|
8003b4c: e160 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8003b4e: 4b0d ldr r3, [pc, #52] @ (8003b84 <HAL_RCC_OscConfig+0x26c>)
|
|
8003b50: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003b52: f003 0302 and.w r3, r3, #2
|
|
8003b56: 2b00 cmp r3, #0
|
|
8003b58: d0f0 beq.n 8003b3c <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
}
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
should be added.*/
|
|
RCC_Delay(1);
|
|
8003b5a: 2001 movs r0, #1
|
|
8003b5c: f000 face bl 80040fc <RCC_Delay>
|
|
8003b60: e01c b.n 8003b9c <HAL_RCC_OscConfig+0x284>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8003b62: 4b0a ldr r3, [pc, #40] @ (8003b8c <HAL_RCC_OscConfig+0x274>)
|
|
8003b64: 2200 movs r2, #0
|
|
8003b66: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003b68: f7fd fc90 bl 800148c <HAL_GetTick>
|
|
8003b6c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8003b6e: e00f b.n 8003b90 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003b70: f7fd fc8c bl 800148c <HAL_GetTick>
|
|
8003b74: 4602 mov r2, r0
|
|
8003b76: 693b ldr r3, [r7, #16]
|
|
8003b78: 1ad3 subs r3, r2, r3
|
|
8003b7a: 2b02 cmp r3, #2
|
|
8003b7c: d908 bls.n 8003b90 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b7e: 2303 movs r3, #3
|
|
8003b80: e146 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
8003b82: bf00 nop
|
|
8003b84: 40021000 .word 0x40021000
|
|
8003b88: 42420000 .word 0x42420000
|
|
8003b8c: 42420480 .word 0x42420480
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8003b90: 4b92 ldr r3, [pc, #584] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003b92: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003b94: f003 0302 and.w r3, r3, #2
|
|
8003b98: 2b00 cmp r3, #0
|
|
8003b9a: d1e9 bne.n 8003b70 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8003b9c: 687b ldr r3, [r7, #4]
|
|
8003b9e: 681b ldr r3, [r3, #0]
|
|
8003ba0: f003 0304 and.w r3, r3, #4
|
|
8003ba4: 2b00 cmp r3, #0
|
|
8003ba6: f000 80a6 beq.w 8003cf6 <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003baa: 2300 movs r3, #0
|
|
8003bac: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8003bae: 4b8b ldr r3, [pc, #556] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003bb0: 69db ldr r3, [r3, #28]
|
|
8003bb2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003bb6: 2b00 cmp r3, #0
|
|
8003bb8: d10d bne.n 8003bd6 <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003bba: 4b88 ldr r3, [pc, #544] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003bbc: 69db ldr r3, [r3, #28]
|
|
8003bbe: 4a87 ldr r2, [pc, #540] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003bc0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003bc4: 61d3 str r3, [r2, #28]
|
|
8003bc6: 4b85 ldr r3, [pc, #532] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003bc8: 69db ldr r3, [r3, #28]
|
|
8003bca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003bce: 60bb str r3, [r7, #8]
|
|
8003bd0: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8003bd2: 2301 movs r3, #1
|
|
8003bd4: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8003bd6: 4b82 ldr r3, [pc, #520] @ (8003de0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8003bd8: 681b ldr r3, [r3, #0]
|
|
8003bda: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003bde: 2b00 cmp r3, #0
|
|
8003be0: d118 bne.n 8003c14 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8003be2: 4b7f ldr r3, [pc, #508] @ (8003de0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8003be4: 681b ldr r3, [r3, #0]
|
|
8003be6: 4a7e ldr r2, [pc, #504] @ (8003de0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8003be8: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003bec: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8003bee: f7fd fc4d bl 800148c <HAL_GetTick>
|
|
8003bf2: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8003bf4: e008 b.n 8003c08 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8003bf6: f7fd fc49 bl 800148c <HAL_GetTick>
|
|
8003bfa: 4602 mov r2, r0
|
|
8003bfc: 693b ldr r3, [r7, #16]
|
|
8003bfe: 1ad3 subs r3, r2, r3
|
|
8003c00: 2b64 cmp r3, #100 @ 0x64
|
|
8003c02: d901 bls.n 8003c08 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c04: 2303 movs r3, #3
|
|
8003c06: e103 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8003c08: 4b75 ldr r3, [pc, #468] @ (8003de0 <HAL_RCC_OscConfig+0x4c8>)
|
|
8003c0a: 681b ldr r3, [r3, #0]
|
|
8003c0c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003c10: 2b00 cmp r3, #0
|
|
8003c12: d0f0 beq.n 8003bf6 <HAL_RCC_OscConfig+0x2de>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8003c14: 687b ldr r3, [r7, #4]
|
|
8003c16: 68db ldr r3, [r3, #12]
|
|
8003c18: 2b01 cmp r3, #1
|
|
8003c1a: d106 bne.n 8003c2a <HAL_RCC_OscConfig+0x312>
|
|
8003c1c: 4b6f ldr r3, [pc, #444] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c1e: 6a1b ldr r3, [r3, #32]
|
|
8003c20: 4a6e ldr r2, [pc, #440] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c22: f043 0301 orr.w r3, r3, #1
|
|
8003c26: 6213 str r3, [r2, #32]
|
|
8003c28: e02d b.n 8003c86 <HAL_RCC_OscConfig+0x36e>
|
|
8003c2a: 687b ldr r3, [r7, #4]
|
|
8003c2c: 68db ldr r3, [r3, #12]
|
|
8003c2e: 2b00 cmp r3, #0
|
|
8003c30: d10c bne.n 8003c4c <HAL_RCC_OscConfig+0x334>
|
|
8003c32: 4b6a ldr r3, [pc, #424] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c34: 6a1b ldr r3, [r3, #32]
|
|
8003c36: 4a69 ldr r2, [pc, #420] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c38: f023 0301 bic.w r3, r3, #1
|
|
8003c3c: 6213 str r3, [r2, #32]
|
|
8003c3e: 4b67 ldr r3, [pc, #412] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c40: 6a1b ldr r3, [r3, #32]
|
|
8003c42: 4a66 ldr r2, [pc, #408] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c44: f023 0304 bic.w r3, r3, #4
|
|
8003c48: 6213 str r3, [r2, #32]
|
|
8003c4a: e01c b.n 8003c86 <HAL_RCC_OscConfig+0x36e>
|
|
8003c4c: 687b ldr r3, [r7, #4]
|
|
8003c4e: 68db ldr r3, [r3, #12]
|
|
8003c50: 2b05 cmp r3, #5
|
|
8003c52: d10c bne.n 8003c6e <HAL_RCC_OscConfig+0x356>
|
|
8003c54: 4b61 ldr r3, [pc, #388] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c56: 6a1b ldr r3, [r3, #32]
|
|
8003c58: 4a60 ldr r2, [pc, #384] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c5a: f043 0304 orr.w r3, r3, #4
|
|
8003c5e: 6213 str r3, [r2, #32]
|
|
8003c60: 4b5e ldr r3, [pc, #376] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c62: 6a1b ldr r3, [r3, #32]
|
|
8003c64: 4a5d ldr r2, [pc, #372] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c66: f043 0301 orr.w r3, r3, #1
|
|
8003c6a: 6213 str r3, [r2, #32]
|
|
8003c6c: e00b b.n 8003c86 <HAL_RCC_OscConfig+0x36e>
|
|
8003c6e: 4b5b ldr r3, [pc, #364] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c70: 6a1b ldr r3, [r3, #32]
|
|
8003c72: 4a5a ldr r2, [pc, #360] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c74: f023 0301 bic.w r3, r3, #1
|
|
8003c78: 6213 str r3, [r2, #32]
|
|
8003c7a: 4b58 ldr r3, [pc, #352] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c7c: 6a1b ldr r3, [r3, #32]
|
|
8003c7e: 4a57 ldr r2, [pc, #348] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003c80: f023 0304 bic.w r3, r3, #4
|
|
8003c84: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8003c86: 687b ldr r3, [r7, #4]
|
|
8003c88: 68db ldr r3, [r3, #12]
|
|
8003c8a: 2b00 cmp r3, #0
|
|
8003c8c: d015 beq.n 8003cba <HAL_RCC_OscConfig+0x3a2>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003c8e: f7fd fbfd bl 800148c <HAL_GetTick>
|
|
8003c92: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8003c94: e00a b.n 8003cac <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003c96: f7fd fbf9 bl 800148c <HAL_GetTick>
|
|
8003c9a: 4602 mov r2, r0
|
|
8003c9c: 693b ldr r3, [r7, #16]
|
|
8003c9e: 1ad3 subs r3, r2, r3
|
|
8003ca0: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003ca4: 4293 cmp r3, r2
|
|
8003ca6: d901 bls.n 8003cac <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ca8: 2303 movs r3, #3
|
|
8003caa: e0b1 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8003cac: 4b4b ldr r3, [pc, #300] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003cae: 6a1b ldr r3, [r3, #32]
|
|
8003cb0: f003 0302 and.w r3, r3, #2
|
|
8003cb4: 2b00 cmp r3, #0
|
|
8003cb6: d0ee beq.n 8003c96 <HAL_RCC_OscConfig+0x37e>
|
|
8003cb8: e014 b.n 8003ce4 <HAL_RCC_OscConfig+0x3cc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003cba: f7fd fbe7 bl 800148c <HAL_GetTick>
|
|
8003cbe: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8003cc0: e00a b.n 8003cd8 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003cc2: f7fd fbe3 bl 800148c <HAL_GetTick>
|
|
8003cc6: 4602 mov r2, r0
|
|
8003cc8: 693b ldr r3, [r7, #16]
|
|
8003cca: 1ad3 subs r3, r2, r3
|
|
8003ccc: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003cd0: 4293 cmp r3, r2
|
|
8003cd2: d901 bls.n 8003cd8 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003cd4: 2303 movs r3, #3
|
|
8003cd6: e09b b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8003cd8: 4b40 ldr r3, [pc, #256] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003cda: 6a1b ldr r3, [r3, #32]
|
|
8003cdc: f003 0302 and.w r3, r3, #2
|
|
8003ce0: 2b00 cmp r3, #0
|
|
8003ce2: d1ee bne.n 8003cc2 <HAL_RCC_OscConfig+0x3aa>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
8003ce4: 7dfb ldrb r3, [r7, #23]
|
|
8003ce6: 2b01 cmp r3, #1
|
|
8003ce8: d105 bne.n 8003cf6 <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8003cea: 4b3c ldr r3, [pc, #240] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003cec: 69db ldr r3, [r3, #28]
|
|
8003cee: 4a3b ldr r2, [pc, #236] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003cf0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003cf4: 61d3 str r3, [r2, #28]
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8003cf6: 687b ldr r3, [r7, #4]
|
|
8003cf8: 69db ldr r3, [r3, #28]
|
|
8003cfa: 2b00 cmp r3, #0
|
|
8003cfc: f000 8087 beq.w 8003e0e <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8003d00: 4b36 ldr r3, [pc, #216] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d02: 685b ldr r3, [r3, #4]
|
|
8003d04: f003 030c and.w r3, r3, #12
|
|
8003d08: 2b08 cmp r3, #8
|
|
8003d0a: d061 beq.n 8003dd0 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8003d0c: 687b ldr r3, [r7, #4]
|
|
8003d0e: 69db ldr r3, [r3, #28]
|
|
8003d10: 2b02 cmp r3, #2
|
|
8003d12: d146 bne.n 8003da2 <HAL_RCC_OscConfig+0x48a>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003d14: 4b33 ldr r3, [pc, #204] @ (8003de4 <HAL_RCC_OscConfig+0x4cc>)
|
|
8003d16: 2200 movs r2, #0
|
|
8003d18: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003d1a: f7fd fbb7 bl 800148c <HAL_GetTick>
|
|
8003d1e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8003d20: e008 b.n 8003d34 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003d22: f7fd fbb3 bl 800148c <HAL_GetTick>
|
|
8003d26: 4602 mov r2, r0
|
|
8003d28: 693b ldr r3, [r7, #16]
|
|
8003d2a: 1ad3 subs r3, r2, r3
|
|
8003d2c: 2b02 cmp r3, #2
|
|
8003d2e: d901 bls.n 8003d34 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d30: 2303 movs r3, #3
|
|
8003d32: e06d b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8003d34: 4b29 ldr r3, [pc, #164] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d36: 681b ldr r3, [r3, #0]
|
|
8003d38: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003d3c: 2b00 cmp r3, #0
|
|
8003d3e: d1f0 bne.n 8003d22 <HAL_RCC_OscConfig+0x40a>
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
8003d40: 687b ldr r3, [r7, #4]
|
|
8003d42: 6a1b ldr r3, [r3, #32]
|
|
8003d44: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8003d48: d108 bne.n 8003d5c <HAL_RCC_OscConfig+0x444>
|
|
/* Set PREDIV1 source */
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Set PREDIV1 Value */
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8003d4a: 4b24 ldr r3, [pc, #144] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d4c: 685b ldr r3, [r3, #4]
|
|
8003d4e: f423 3200 bic.w r2, r3, #131072 @ 0x20000
|
|
8003d52: 687b ldr r3, [r7, #4]
|
|
8003d54: 689b ldr r3, [r3, #8]
|
|
8003d56: 4921 ldr r1, [pc, #132] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d58: 4313 orrs r3, r2
|
|
8003d5a: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8003d5c: 4b1f ldr r3, [pc, #124] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d5e: 685b ldr r3, [r3, #4]
|
|
8003d60: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
|
|
8003d64: 687b ldr r3, [r7, #4]
|
|
8003d66: 6a19 ldr r1, [r3, #32]
|
|
8003d68: 687b ldr r3, [r7, #4]
|
|
8003d6a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003d6c: 430b orrs r3, r1
|
|
8003d6e: 491b ldr r1, [pc, #108] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d70: 4313 orrs r3, r2
|
|
8003d72: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8003d74: 4b1b ldr r3, [pc, #108] @ (8003de4 <HAL_RCC_OscConfig+0x4cc>)
|
|
8003d76: 2201 movs r2, #1
|
|
8003d78: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003d7a: f7fd fb87 bl 800148c <HAL_GetTick>
|
|
8003d7e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8003d80: e008 b.n 8003d94 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003d82: f7fd fb83 bl 800148c <HAL_GetTick>
|
|
8003d86: 4602 mov r2, r0
|
|
8003d88: 693b ldr r3, [r7, #16]
|
|
8003d8a: 1ad3 subs r3, r2, r3
|
|
8003d8c: 2b02 cmp r3, #2
|
|
8003d8e: d901 bls.n 8003d94 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d90: 2303 movs r3, #3
|
|
8003d92: e03d b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8003d94: 4b11 ldr r3, [pc, #68] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003d96: 681b ldr r3, [r3, #0]
|
|
8003d98: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003d9c: 2b00 cmp r3, #0
|
|
8003d9e: d0f0 beq.n 8003d82 <HAL_RCC_OscConfig+0x46a>
|
|
8003da0: e035 b.n 8003e0e <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003da2: 4b10 ldr r3, [pc, #64] @ (8003de4 <HAL_RCC_OscConfig+0x4cc>)
|
|
8003da4: 2200 movs r2, #0
|
|
8003da6: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003da8: f7fd fb70 bl 800148c <HAL_GetTick>
|
|
8003dac: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8003dae: e008 b.n 8003dc2 <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003db0: f7fd fb6c bl 800148c <HAL_GetTick>
|
|
8003db4: 4602 mov r2, r0
|
|
8003db6: 693b ldr r3, [r7, #16]
|
|
8003db8: 1ad3 subs r3, r2, r3
|
|
8003dba: 2b02 cmp r3, #2
|
|
8003dbc: d901 bls.n 8003dc2 <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003dbe: 2303 movs r3, #3
|
|
8003dc0: e026 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8003dc2: 4b06 ldr r3, [pc, #24] @ (8003ddc <HAL_RCC_OscConfig+0x4c4>)
|
|
8003dc4: 681b ldr r3, [r3, #0]
|
|
8003dc6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003dca: 2b00 cmp r3, #0
|
|
8003dcc: d1f0 bne.n 8003db0 <HAL_RCC_OscConfig+0x498>
|
|
8003dce: e01e b.n 8003e0e <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8003dd0: 687b ldr r3, [r7, #4]
|
|
8003dd2: 69db ldr r3, [r3, #28]
|
|
8003dd4: 2b01 cmp r3, #1
|
|
8003dd6: d107 bne.n 8003de8 <HAL_RCC_OscConfig+0x4d0>
|
|
{
|
|
return HAL_ERROR;
|
|
8003dd8: 2301 movs r3, #1
|
|
8003dda: e019 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
8003ddc: 40021000 .word 0x40021000
|
|
8003de0: 40007000 .word 0x40007000
|
|
8003de4: 42420060 .word 0x42420060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8003de8: 4b0b ldr r3, [pc, #44] @ (8003e18 <HAL_RCC_OscConfig+0x500>)
|
|
8003dea: 685b ldr r3, [r3, #4]
|
|
8003dec: 60fb str r3, [r7, #12]
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003dee: 68fb ldr r3, [r7, #12]
|
|
8003df0: f403 3280 and.w r2, r3, #65536 @ 0x10000
|
|
8003df4: 687b ldr r3, [r7, #4]
|
|
8003df6: 6a1b ldr r3, [r3, #32]
|
|
8003df8: 429a cmp r2, r3
|
|
8003dfa: d106 bne.n 8003e0a <HAL_RCC_OscConfig+0x4f2>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8003dfc: 68fb ldr r3, [r7, #12]
|
|
8003dfe: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
|
|
8003e02: 687b ldr r3, [r7, #4]
|
|
8003e04: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003e06: 429a cmp r2, r3
|
|
8003e08: d001 beq.n 8003e0e <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e0a: 2301 movs r3, #1
|
|
8003e0c: e000 b.n 8003e10 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003e0e: 2300 movs r3, #0
|
|
}
|
|
8003e10: 4618 mov r0, r3
|
|
8003e12: 3718 adds r7, #24
|
|
8003e14: 46bd mov sp, r7
|
|
8003e16: bd80 pop {r7, pc}
|
|
8003e18: 40021000 .word 0x40021000
|
|
|
|
08003e1c <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8003e1c: b580 push {r7, lr}
|
|
8003e1e: b084 sub sp, #16
|
|
8003e20: af00 add r7, sp, #0
|
|
8003e22: 6078 str r0, [r7, #4]
|
|
8003e24: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8003e26: 687b ldr r3, [r7, #4]
|
|
8003e28: 2b00 cmp r3, #0
|
|
8003e2a: d101 bne.n 8003e30 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e2c: 2301 movs r3, #1
|
|
8003e2e: e0d0 b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8003e30: 4b6a ldr r3, [pc, #424] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003e32: 681b ldr r3, [r3, #0]
|
|
8003e34: f003 0307 and.w r3, r3, #7
|
|
8003e38: 683a ldr r2, [r7, #0]
|
|
8003e3a: 429a cmp r2, r3
|
|
8003e3c: d910 bls.n 8003e60 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003e3e: 4b67 ldr r3, [pc, #412] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003e40: 681b ldr r3, [r3, #0]
|
|
8003e42: f023 0207 bic.w r2, r3, #7
|
|
8003e46: 4965 ldr r1, [pc, #404] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003e48: 683b ldr r3, [r7, #0]
|
|
8003e4a: 4313 orrs r3, r2
|
|
8003e4c: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003e4e: 4b63 ldr r3, [pc, #396] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003e50: 681b ldr r3, [r3, #0]
|
|
8003e52: f003 0307 and.w r3, r3, #7
|
|
8003e56: 683a ldr r2, [r7, #0]
|
|
8003e58: 429a cmp r2, r3
|
|
8003e5a: d001 beq.n 8003e60 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e5c: 2301 movs r3, #1
|
|
8003e5e: e0b8 b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003e60: 687b ldr r3, [r7, #4]
|
|
8003e62: 681b ldr r3, [r3, #0]
|
|
8003e64: f003 0302 and.w r3, r3, #2
|
|
8003e68: 2b00 cmp r3, #0
|
|
8003e6a: d020 beq.n 8003eae <HAL_RCC_ClockConfig+0x92>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003e6c: 687b ldr r3, [r7, #4]
|
|
8003e6e: 681b ldr r3, [r3, #0]
|
|
8003e70: f003 0304 and.w r3, r3, #4
|
|
8003e74: 2b00 cmp r3, #0
|
|
8003e76: d005 beq.n 8003e84 <HAL_RCC_ClockConfig+0x68>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8003e78: 4b59 ldr r3, [pc, #356] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003e7a: 685b ldr r3, [r3, #4]
|
|
8003e7c: 4a58 ldr r2, [pc, #352] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003e7e: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
8003e82: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8003e84: 687b ldr r3, [r7, #4]
|
|
8003e86: 681b ldr r3, [r3, #0]
|
|
8003e88: f003 0308 and.w r3, r3, #8
|
|
8003e8c: 2b00 cmp r3, #0
|
|
8003e8e: d005 beq.n 8003e9c <HAL_RCC_ClockConfig+0x80>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8003e90: 4b53 ldr r3, [pc, #332] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003e92: 685b ldr r3, [r3, #4]
|
|
8003e94: 4a52 ldr r2, [pc, #328] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003e96: f443 5360 orr.w r3, r3, #14336 @ 0x3800
|
|
8003e9a: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8003e9c: 4b50 ldr r3, [pc, #320] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003e9e: 685b ldr r3, [r3, #4]
|
|
8003ea0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8003ea4: 687b ldr r3, [r7, #4]
|
|
8003ea6: 689b ldr r3, [r3, #8]
|
|
8003ea8: 494d ldr r1, [pc, #308] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003eaa: 4313 orrs r3, r2
|
|
8003eac: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003eae: 687b ldr r3, [r7, #4]
|
|
8003eb0: 681b ldr r3, [r3, #0]
|
|
8003eb2: f003 0301 and.w r3, r3, #1
|
|
8003eb6: 2b00 cmp r3, #0
|
|
8003eb8: d040 beq.n 8003f3c <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8003eba: 687b ldr r3, [r7, #4]
|
|
8003ebc: 685b ldr r3, [r3, #4]
|
|
8003ebe: 2b01 cmp r3, #1
|
|
8003ec0: d107 bne.n 8003ed2 <HAL_RCC_ClockConfig+0xb6>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8003ec2: 4b47 ldr r3, [pc, #284] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003ec4: 681b ldr r3, [r3, #0]
|
|
8003ec6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003eca: 2b00 cmp r3, #0
|
|
8003ecc: d115 bne.n 8003efa <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ece: 2301 movs r3, #1
|
|
8003ed0: e07f b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8003ed2: 687b ldr r3, [r7, #4]
|
|
8003ed4: 685b ldr r3, [r3, #4]
|
|
8003ed6: 2b02 cmp r3, #2
|
|
8003ed8: d107 bne.n 8003eea <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8003eda: 4b41 ldr r3, [pc, #260] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003edc: 681b ldr r3, [r3, #0]
|
|
8003ede: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003ee2: 2b00 cmp r3, #0
|
|
8003ee4: d109 bne.n 8003efa <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ee6: 2301 movs r3, #1
|
|
8003ee8: e073 b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8003eea: 4b3d ldr r3, [pc, #244] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003eec: 681b ldr r3, [r3, #0]
|
|
8003eee: f003 0302 and.w r3, r3, #2
|
|
8003ef2: 2b00 cmp r3, #0
|
|
8003ef4: d101 bne.n 8003efa <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ef6: 2301 movs r3, #1
|
|
8003ef8: e06b b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8003efa: 4b39 ldr r3, [pc, #228] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003efc: 685b ldr r3, [r3, #4]
|
|
8003efe: f023 0203 bic.w r2, r3, #3
|
|
8003f02: 687b ldr r3, [r7, #4]
|
|
8003f04: 685b ldr r3, [r3, #4]
|
|
8003f06: 4936 ldr r1, [pc, #216] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003f08: 4313 orrs r3, r2
|
|
8003f0a: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8003f0c: f7fd fabe bl 800148c <HAL_GetTick>
|
|
8003f10: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8003f12: e00a b.n 8003f2a <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8003f14: f7fd faba bl 800148c <HAL_GetTick>
|
|
8003f18: 4602 mov r2, r0
|
|
8003f1a: 68fb ldr r3, [r7, #12]
|
|
8003f1c: 1ad3 subs r3, r2, r3
|
|
8003f1e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003f22: 4293 cmp r3, r2
|
|
8003f24: d901 bls.n 8003f2a <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003f26: 2303 movs r3, #3
|
|
8003f28: e053 b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8003f2a: 4b2d ldr r3, [pc, #180] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003f2c: 685b ldr r3, [r3, #4]
|
|
8003f2e: f003 020c and.w r2, r3, #12
|
|
8003f32: 687b ldr r3, [r7, #4]
|
|
8003f34: 685b ldr r3, [r3, #4]
|
|
8003f36: 009b lsls r3, r3, #2
|
|
8003f38: 429a cmp r2, r3
|
|
8003f3a: d1eb bne.n 8003f14 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8003f3c: 4b27 ldr r3, [pc, #156] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003f3e: 681b ldr r3, [r3, #0]
|
|
8003f40: f003 0307 and.w r3, r3, #7
|
|
8003f44: 683a ldr r2, [r7, #0]
|
|
8003f46: 429a cmp r2, r3
|
|
8003f48: d210 bcs.n 8003f6c <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003f4a: 4b24 ldr r3, [pc, #144] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003f4c: 681b ldr r3, [r3, #0]
|
|
8003f4e: f023 0207 bic.w r2, r3, #7
|
|
8003f52: 4922 ldr r1, [pc, #136] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003f54: 683b ldr r3, [r7, #0]
|
|
8003f56: 4313 orrs r3, r2
|
|
8003f58: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003f5a: 4b20 ldr r3, [pc, #128] @ (8003fdc <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003f5c: 681b ldr r3, [r3, #0]
|
|
8003f5e: f003 0307 and.w r3, r3, #7
|
|
8003f62: 683a ldr r2, [r7, #0]
|
|
8003f64: 429a cmp r2, r3
|
|
8003f66: d001 beq.n 8003f6c <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f68: 2301 movs r3, #1
|
|
8003f6a: e032 b.n 8003fd2 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003f6c: 687b ldr r3, [r7, #4]
|
|
8003f6e: 681b ldr r3, [r3, #0]
|
|
8003f70: f003 0304 and.w r3, r3, #4
|
|
8003f74: 2b00 cmp r3, #0
|
|
8003f76: d008 beq.n 8003f8a <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8003f78: 4b19 ldr r3, [pc, #100] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003f7a: 685b ldr r3, [r3, #4]
|
|
8003f7c: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
8003f80: 687b ldr r3, [r7, #4]
|
|
8003f82: 68db ldr r3, [r3, #12]
|
|
8003f84: 4916 ldr r1, [pc, #88] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003f86: 4313 orrs r3, r2
|
|
8003f88: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8003f8a: 687b ldr r3, [r7, #4]
|
|
8003f8c: 681b ldr r3, [r3, #0]
|
|
8003f8e: f003 0308 and.w r3, r3, #8
|
|
8003f92: 2b00 cmp r3, #0
|
|
8003f94: d009 beq.n 8003faa <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
8003f96: 4b12 ldr r3, [pc, #72] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003f98: 685b ldr r3, [r3, #4]
|
|
8003f9a: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
8003f9e: 687b ldr r3, [r7, #4]
|
|
8003fa0: 691b ldr r3, [r3, #16]
|
|
8003fa2: 00db lsls r3, r3, #3
|
|
8003fa4: 490e ldr r1, [pc, #56] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003fa6: 4313 orrs r3, r2
|
|
8003fa8: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8003faa: f000 f821 bl 8003ff0 <HAL_RCC_GetSysClockFreq>
|
|
8003fae: 4602 mov r2, r0
|
|
8003fb0: 4b0b ldr r3, [pc, #44] @ (8003fe0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003fb2: 685b ldr r3, [r3, #4]
|
|
8003fb4: 091b lsrs r3, r3, #4
|
|
8003fb6: f003 030f and.w r3, r3, #15
|
|
8003fba: 490a ldr r1, [pc, #40] @ (8003fe4 <HAL_RCC_ClockConfig+0x1c8>)
|
|
8003fbc: 5ccb ldrb r3, [r1, r3]
|
|
8003fbe: fa22 f303 lsr.w r3, r2, r3
|
|
8003fc2: 4a09 ldr r2, [pc, #36] @ (8003fe8 <HAL_RCC_ClockConfig+0x1cc>)
|
|
8003fc4: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick(uwTickPrio);
|
|
8003fc6: 4b09 ldr r3, [pc, #36] @ (8003fec <HAL_RCC_ClockConfig+0x1d0>)
|
|
8003fc8: 681b ldr r3, [r3, #0]
|
|
8003fca: 4618 mov r0, r3
|
|
8003fcc: f7fd fa1c bl 8001408 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8003fd0: 2300 movs r3, #0
|
|
}
|
|
8003fd2: 4618 mov r0, r3
|
|
8003fd4: 3710 adds r7, #16
|
|
8003fd6: 46bd mov sp, r7
|
|
8003fd8: bd80 pop {r7, pc}
|
|
8003fda: bf00 nop
|
|
8003fdc: 40022000 .word 0x40022000
|
|
8003fe0: 40021000 .word 0x40021000
|
|
8003fe4: 0800a3e8 .word 0x0800a3e8
|
|
8003fe8: 20000000 .word 0x20000000
|
|
8003fec: 20000004 .word 0x20000004
|
|
|
|
08003ff0 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8003ff0: b480 push {r7}
|
|
8003ff2: b087 sub sp, #28
|
|
8003ff4: af00 add r7, sp, #0
|
|
#else
|
|
static const uint8_t aPredivFactorTable[2U] = {1, 2};
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
#endif
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
8003ff6: 2300 movs r3, #0
|
|
8003ff8: 60fb str r3, [r7, #12]
|
|
8003ffa: 2300 movs r3, #0
|
|
8003ffc: 60bb str r3, [r7, #8]
|
|
8003ffe: 2300 movs r3, #0
|
|
8004000: 617b str r3, [r7, #20]
|
|
8004002: 2300 movs r3, #0
|
|
8004004: 607b str r3, [r7, #4]
|
|
uint32_t sysclockfreq = 0U;
|
|
8004006: 2300 movs r3, #0
|
|
8004008: 613b str r3, [r7, #16]
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
tmpreg = RCC->CFGR;
|
|
800400a: 4b1e ldr r3, [pc, #120] @ (8004084 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
800400c: 685b ldr r3, [r3, #4]
|
|
800400e: 60fb str r3, [r7, #12]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8004010: 68fb ldr r3, [r7, #12]
|
|
8004012: f003 030c and.w r3, r3, #12
|
|
8004016: 2b04 cmp r3, #4
|
|
8004018: d002 beq.n 8004020 <HAL_RCC_GetSysClockFreq+0x30>
|
|
800401a: 2b08 cmp r3, #8
|
|
800401c: d003 beq.n 8004026 <HAL_RCC_GetSysClockFreq+0x36>
|
|
800401e: e027 b.n 8004070 <HAL_RCC_GetSysClockFreq+0x80>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8004020: 4b19 ldr r3, [pc, #100] @ (8004088 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8004022: 613b str r3, [r7, #16]
|
|
break;
|
|
8004024: e027 b.n 8004076 <HAL_RCC_GetSysClockFreq+0x86>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
8004026: 68fb ldr r3, [r7, #12]
|
|
8004028: 0c9b lsrs r3, r3, #18
|
|
800402a: f003 030f and.w r3, r3, #15
|
|
800402e: 4a17 ldr r2, [pc, #92] @ (800408c <HAL_RCC_GetSysClockFreq+0x9c>)
|
|
8004030: 5cd3 ldrb r3, [r2, r3]
|
|
8004032: 607b str r3, [r7, #4]
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
8004034: 68fb ldr r3, [r7, #12]
|
|
8004036: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
800403a: 2b00 cmp r3, #0
|
|
800403c: d010 beq.n 8004060 <HAL_RCC_GetSysClockFreq+0x70>
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
800403e: 4b11 ldr r3, [pc, #68] @ (8004084 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
8004040: 685b ldr r3, [r3, #4]
|
|
8004042: 0c5b lsrs r3, r3, #17
|
|
8004044: f003 0301 and.w r3, r3, #1
|
|
8004048: 4a11 ldr r2, [pc, #68] @ (8004090 <HAL_RCC_GetSysClockFreq+0xa0>)
|
|
800404a: 5cd3 ldrb r3, [r2, r3]
|
|
800404c: 60bb str r3, [r7, #8]
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
800404e: 687b ldr r3, [r7, #4]
|
|
8004050: 4a0d ldr r2, [pc, #52] @ (8004088 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8004052: fb03 f202 mul.w r2, r3, r2
|
|
8004056: 68bb ldr r3, [r7, #8]
|
|
8004058: fbb2 f3f3 udiv r3, r2, r3
|
|
800405c: 617b str r3, [r7, #20]
|
|
800405e: e004 b.n 800406a <HAL_RCC_GetSysClockFreq+0x7a>
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
8004060: 687b ldr r3, [r7, #4]
|
|
8004062: 4a0c ldr r2, [pc, #48] @ (8004094 <HAL_RCC_GetSysClockFreq+0xa4>)
|
|
8004064: fb02 f303 mul.w r3, r2, r3
|
|
8004068: 617b str r3, [r7, #20]
|
|
}
|
|
sysclockfreq = pllclk;
|
|
800406a: 697b ldr r3, [r7, #20]
|
|
800406c: 613b str r3, [r7, #16]
|
|
break;
|
|
800406e: e002 b.n 8004076 <HAL_RCC_GetSysClockFreq+0x86>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004070: 4b05 ldr r3, [pc, #20] @ (8004088 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8004072: 613b str r3, [r7, #16]
|
|
break;
|
|
8004074: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8004076: 693b ldr r3, [r7, #16]
|
|
}
|
|
8004078: 4618 mov r0, r3
|
|
800407a: 371c adds r7, #28
|
|
800407c: 46bd mov sp, r7
|
|
800407e: bc80 pop {r7}
|
|
8004080: 4770 bx lr
|
|
8004082: bf00 nop
|
|
8004084: 40021000 .word 0x40021000
|
|
8004088: 007a1200 .word 0x007a1200
|
|
800408c: 0800a400 .word 0x0800a400
|
|
8004090: 0800a410 .word 0x0800a410
|
|
8004094: 003d0900 .word 0x003d0900
|
|
|
|
08004098 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8004098: b480 push {r7}
|
|
800409a: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
800409c: 4b02 ldr r3, [pc, #8] @ (80040a8 <HAL_RCC_GetHCLKFreq+0x10>)
|
|
800409e: 681b ldr r3, [r3, #0]
|
|
}
|
|
80040a0: 4618 mov r0, r3
|
|
80040a2: 46bd mov sp, r7
|
|
80040a4: bc80 pop {r7}
|
|
80040a6: 4770 bx lr
|
|
80040a8: 20000000 .word 0x20000000
|
|
|
|
080040ac <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80040ac: b580 push {r7, lr}
|
|
80040ae: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
80040b0: f7ff fff2 bl 8004098 <HAL_RCC_GetHCLKFreq>
|
|
80040b4: 4602 mov r2, r0
|
|
80040b6: 4b05 ldr r3, [pc, #20] @ (80040cc <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80040b8: 685b ldr r3, [r3, #4]
|
|
80040ba: 0a1b lsrs r3, r3, #8
|
|
80040bc: f003 0307 and.w r3, r3, #7
|
|
80040c0: 4903 ldr r1, [pc, #12] @ (80040d0 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80040c2: 5ccb ldrb r3, [r1, r3]
|
|
80040c4: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80040c8: 4618 mov r0, r3
|
|
80040ca: bd80 pop {r7, pc}
|
|
80040cc: 40021000 .word 0x40021000
|
|
80040d0: 0800a3f8 .word 0x0800a3f8
|
|
|
|
080040d4 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80040d4: b580 push {r7, lr}
|
|
80040d6: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80040d8: f7ff ffde bl 8004098 <HAL_RCC_GetHCLKFreq>
|
|
80040dc: 4602 mov r2, r0
|
|
80040de: 4b05 ldr r3, [pc, #20] @ (80040f4 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80040e0: 685b ldr r3, [r3, #4]
|
|
80040e2: 0adb lsrs r3, r3, #11
|
|
80040e4: f003 0307 and.w r3, r3, #7
|
|
80040e8: 4903 ldr r1, [pc, #12] @ (80040f8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80040ea: 5ccb ldrb r3, [r1, r3]
|
|
80040ec: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80040f0: 4618 mov r0, r3
|
|
80040f2: bd80 pop {r7, pc}
|
|
80040f4: 40021000 .word 0x40021000
|
|
80040f8: 0800a3f8 .word 0x0800a3f8
|
|
|
|
080040fc <RCC_Delay>:
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
{
|
|
80040fc: b480 push {r7}
|
|
80040fe: b085 sub sp, #20
|
|
8004100: af00 add r7, sp, #0
|
|
8004102: 6078 str r0, [r7, #4]
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
8004104: 4b0a ldr r3, [pc, #40] @ (8004130 <RCC_Delay+0x34>)
|
|
8004106: 681b ldr r3, [r3, #0]
|
|
8004108: 4a0a ldr r2, [pc, #40] @ (8004134 <RCC_Delay+0x38>)
|
|
800410a: fba2 2303 umull r2, r3, r2, r3
|
|
800410e: 0a5b lsrs r3, r3, #9
|
|
8004110: 687a ldr r2, [r7, #4]
|
|
8004112: fb02 f303 mul.w r3, r2, r3
|
|
8004116: 60fb str r3, [r7, #12]
|
|
do
|
|
{
|
|
__NOP();
|
|
8004118: bf00 nop
|
|
}
|
|
while (Delay --);
|
|
800411a: 68fb ldr r3, [r7, #12]
|
|
800411c: 1e5a subs r2, r3, #1
|
|
800411e: 60fa str r2, [r7, #12]
|
|
8004120: 2b00 cmp r3, #0
|
|
8004122: d1f9 bne.n 8004118 <RCC_Delay+0x1c>
|
|
}
|
|
8004124: bf00 nop
|
|
8004126: bf00 nop
|
|
8004128: 3714 adds r7, #20
|
|
800412a: 46bd mov sp, r7
|
|
800412c: bc80 pop {r7}
|
|
800412e: 4770 bx lr
|
|
8004130: 20000000 .word 0x20000000
|
|
8004134: 10624dd3 .word 0x10624dd3
|
|
|
|
08004138 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* manually disable it.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8004138: b580 push {r7, lr}
|
|
800413a: b086 sub sp, #24
|
|
800413c: af00 add r7, sp, #0
|
|
800413e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U, temp_reg = 0U;
|
|
8004140: 2300 movs r3, #0
|
|
8004142: 613b str r3, [r7, #16]
|
|
8004144: 2300 movs r3, #0
|
|
8004146: 60fb str r3, [r7, #12]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------------- RTC/LCD Configuration ------------------------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
|
8004148: 687b ldr r3, [r7, #4]
|
|
800414a: 681b ldr r3, [r3, #0]
|
|
800414c: f003 0301 and.w r3, r3, #1
|
|
8004150: 2b00 cmp r3, #0
|
|
8004152: d07d beq.n 8004250 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8004154: 2300 movs r3, #0
|
|
8004156: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
|
power domain is done. */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8004158: 4b4f ldr r3, [pc, #316] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800415a: 69db ldr r3, [r3, #28]
|
|
800415c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004160: 2b00 cmp r3, #0
|
|
8004162: d10d bne.n 8004180 <HAL_RCCEx_PeriphCLKConfig+0x48>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8004164: 4b4c ldr r3, [pc, #304] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8004166: 69db ldr r3, [r3, #28]
|
|
8004168: 4a4b ldr r2, [pc, #300] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800416a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800416e: 61d3 str r3, [r2, #28]
|
|
8004170: 4b49 ldr r3, [pc, #292] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8004172: 69db ldr r3, [r3, #28]
|
|
8004174: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004178: 60bb str r3, [r7, #8]
|
|
800417a: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
800417c: 2301 movs r3, #1
|
|
800417e: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004180: 4b46 ldr r3, [pc, #280] @ (800429c <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8004182: 681b ldr r3, [r3, #0]
|
|
8004184: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004188: 2b00 cmp r3, #0
|
|
800418a: d118 bne.n 80041be <HAL_RCCEx_PeriphCLKConfig+0x86>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
800418c: 4b43 ldr r3, [pc, #268] @ (800429c <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
800418e: 681b ldr r3, [r3, #0]
|
|
8004190: 4a42 ldr r2, [pc, #264] @ (800429c <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8004192: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004196: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8004198: f7fd f978 bl 800148c <HAL_GetTick>
|
|
800419c: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800419e: e008 b.n 80041b2 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80041a0: f7fd f974 bl 800148c <HAL_GetTick>
|
|
80041a4: 4602 mov r2, r0
|
|
80041a6: 693b ldr r3, [r7, #16]
|
|
80041a8: 1ad3 subs r3, r2, r3
|
|
80041aa: 2b64 cmp r3, #100 @ 0x64
|
|
80041ac: d901 bls.n 80041b2 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80041ae: 2303 movs r3, #3
|
|
80041b0: e06d b.n 800428e <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80041b2: 4b3a ldr r3, [pc, #232] @ (800429c <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
80041b4: 681b ldr r3, [r3, #0]
|
|
80041b6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80041ba: 2b00 cmp r3, #0
|
|
80041bc: d0f0 beq.n 80041a0 <HAL_RCCEx_PeriphCLKConfig+0x68>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
80041be: 4b36 ldr r3, [pc, #216] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80041c0: 6a1b ldr r3, [r3, #32]
|
|
80041c2: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80041c6: 60fb str r3, [r7, #12]
|
|
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
80041c8: 68fb ldr r3, [r7, #12]
|
|
80041ca: 2b00 cmp r3, #0
|
|
80041cc: d02e beq.n 800422c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
80041ce: 687b ldr r3, [r7, #4]
|
|
80041d0: 685b ldr r3, [r3, #4]
|
|
80041d2: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80041d6: 68fa ldr r2, [r7, #12]
|
|
80041d8: 429a cmp r2, r3
|
|
80041da: d027 beq.n 800422c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
80041dc: 4b2e ldr r3, [pc, #184] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80041de: 6a1b ldr r3, [r3, #32]
|
|
80041e0: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80041e4: 60fb str r3, [r7, #12]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80041e6: 4b2e ldr r3, [pc, #184] @ (80042a0 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
80041e8: 2201 movs r2, #1
|
|
80041ea: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
80041ec: 4b2c ldr r3, [pc, #176] @ (80042a0 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
80041ee: 2200 movs r2, #0
|
|
80041f0: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = temp_reg;
|
|
80041f2: 4a29 ldr r2, [pc, #164] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80041f4: 68fb ldr r3, [r7, #12]
|
|
80041f6: 6213 str r3, [r2, #32]
|
|
|
|
/* Wait for LSERDY if LSE was enabled */
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
|
80041f8: 68fb ldr r3, [r7, #12]
|
|
80041fa: f003 0301 and.w r3, r3, #1
|
|
80041fe: 2b00 cmp r3, #0
|
|
8004200: d014 beq.n 800422c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004202: f7fd f943 bl 800148c <HAL_GetTick>
|
|
8004206: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004208: e00a b.n 8004220 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800420a: f7fd f93f bl 800148c <HAL_GetTick>
|
|
800420e: 4602 mov r2, r0
|
|
8004210: 693b ldr r3, [r7, #16]
|
|
8004212: 1ad3 subs r3, r2, r3
|
|
8004214: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004218: 4293 cmp r3, r2
|
|
800421a: d901 bls.n 8004220 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800421c: 2303 movs r3, #3
|
|
800421e: e036 b.n 800428e <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004220: 4b1d ldr r3, [pc, #116] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8004222: 6a1b ldr r3, [r3, #32]
|
|
8004224: f003 0302 and.w r3, r3, #2
|
|
8004228: 2b00 cmp r3, #0
|
|
800422a: d0ee beq.n 800420a <HAL_RCCEx_PeriphCLKConfig+0xd2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
800422c: 4b1a ldr r3, [pc, #104] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800422e: 6a1b ldr r3, [r3, #32]
|
|
8004230: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8004234: 687b ldr r3, [r7, #4]
|
|
8004236: 685b ldr r3, [r3, #4]
|
|
8004238: 4917 ldr r1, [pc, #92] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800423a: 4313 orrs r3, r2
|
|
800423c: 620b str r3, [r1, #32]
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
800423e: 7dfb ldrb r3, [r7, #23]
|
|
8004240: 2b01 cmp r3, #1
|
|
8004242: d105 bne.n 8004250 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8004244: 4b14 ldr r3, [pc, #80] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8004246: 69db ldr r3, [r3, #28]
|
|
8004248: 4a13 ldr r2, [pc, #76] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800424a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800424e: 61d3 str r3, [r2, #28]
|
|
}
|
|
}
|
|
|
|
/*------------------------------ ADC clock Configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8004250: 687b ldr r3, [r7, #4]
|
|
8004252: 681b ldr r3, [r3, #0]
|
|
8004254: f003 0302 and.w r3, r3, #2
|
|
8004258: 2b00 cmp r3, #0
|
|
800425a: d008 beq.n 800426e <HAL_RCCEx_PeriphCLKConfig+0x136>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
800425c: 4b0e ldr r3, [pc, #56] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800425e: 685b ldr r3, [r3, #4]
|
|
8004260: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
8004264: 687b ldr r3, [r7, #4]
|
|
8004266: 689b ldr r3, [r3, #8]
|
|
8004268: 490b ldr r1, [pc, #44] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800426a: 4313 orrs r3, r2
|
|
800426c: 604b str r3, [r1, #4]
|
|
|
|
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
|
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
|
|| defined(STM32F105xC) || defined(STM32F107xC)
|
|
/*------------------------------ USB clock Configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
|
800426e: 687b ldr r3, [r7, #4]
|
|
8004270: 681b ldr r3, [r3, #0]
|
|
8004272: f003 0310 and.w r3, r3, #16
|
|
8004276: 2b00 cmp r3, #0
|
|
8004278: d008 beq.n 800428c <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
|
|
|
|
/* Configure the USB clock source */
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
800427a: 4b07 ldr r3, [pc, #28] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800427c: 685b ldr r3, [r3, #4]
|
|
800427e: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
|
|
8004282: 687b ldr r3, [r7, #4]
|
|
8004284: 68db ldr r3, [r3, #12]
|
|
8004286: 4904 ldr r1, [pc, #16] @ (8004298 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8004288: 4313 orrs r3, r2
|
|
800428a: 604b str r3, [r1, #4]
|
|
}
|
|
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
|
|
|
return HAL_OK;
|
|
800428c: 2300 movs r3, #0
|
|
}
|
|
800428e: 4618 mov r0, r3
|
|
8004290: 3718 adds r7, #24
|
|
8004292: 46bd mov sp, r7
|
|
8004294: bd80 pop {r7, pc}
|
|
8004296: bf00 nop
|
|
8004298: 40021000 .word 0x40021000
|
|
800429c: 40007000 .word 0x40007000
|
|
80042a0: 42420440 .word 0x42420440
|
|
|
|
080042a4 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80042a4: b580 push {r7, lr}
|
|
80042a6: b082 sub sp, #8
|
|
80042a8: af00 add r7, sp, #0
|
|
80042aa: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80042ac: 687b ldr r3, [r7, #4]
|
|
80042ae: 2b00 cmp r3, #0
|
|
80042b0: d101 bne.n 80042b6 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80042b2: 2301 movs r3, #1
|
|
80042b4: e041 b.n 800433a <HAL_TIM_Base_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80042b6: 687b ldr r3, [r7, #4]
|
|
80042b8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80042bc: b2db uxtb r3, r3
|
|
80042be: 2b00 cmp r3, #0
|
|
80042c0: d106 bne.n 80042d0 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80042c2: 687b ldr r3, [r7, #4]
|
|
80042c4: 2200 movs r2, #0
|
|
80042c6: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
80042ca: 6878 ldr r0, [r7, #4]
|
|
80042cc: f7fc ff1c bl 8001108 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80042d0: 687b ldr r3, [r7, #4]
|
|
80042d2: 2202 movs r2, #2
|
|
80042d4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80042d8: 687b ldr r3, [r7, #4]
|
|
80042da: 681a ldr r2, [r3, #0]
|
|
80042dc: 687b ldr r3, [r7, #4]
|
|
80042de: 3304 adds r3, #4
|
|
80042e0: 4619 mov r1, r3
|
|
80042e2: 4610 mov r0, r2
|
|
80042e4: f000 fb3e bl 8004964 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80042e8: 687b ldr r3, [r7, #4]
|
|
80042ea: 2201 movs r2, #1
|
|
80042ec: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80042f0: 687b ldr r3, [r7, #4]
|
|
80042f2: 2201 movs r2, #1
|
|
80042f4: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
80042f8: 687b ldr r3, [r7, #4]
|
|
80042fa: 2201 movs r2, #1
|
|
80042fc: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8004300: 687b ldr r3, [r7, #4]
|
|
8004302: 2201 movs r2, #1
|
|
8004304: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8004308: 687b ldr r3, [r7, #4]
|
|
800430a: 2201 movs r2, #1
|
|
800430c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004310: 687b ldr r3, [r7, #4]
|
|
8004312: 2201 movs r2, #1
|
|
8004314: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8004318: 687b ldr r3, [r7, #4]
|
|
800431a: 2201 movs r2, #1
|
|
800431c: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8004320: 687b ldr r3, [r7, #4]
|
|
8004322: 2201 movs r2, #1
|
|
8004324: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8004328: 687b ldr r3, [r7, #4]
|
|
800432a: 2201 movs r2, #1
|
|
800432c: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004330: 687b ldr r3, [r7, #4]
|
|
8004332: 2201 movs r2, #1
|
|
8004334: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8004338: 2300 movs r3, #0
|
|
}
|
|
800433a: 4618 mov r0, r3
|
|
800433c: 3708 adds r7, #8
|
|
800433e: 46bd mov sp, r7
|
|
8004340: bd80 pop {r7, pc}
|
|
|
|
08004342 <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004342: b580 push {r7, lr}
|
|
8004344: b082 sub sp, #8
|
|
8004346: af00 add r7, sp, #0
|
|
8004348: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800434a: 687b ldr r3, [r7, #4]
|
|
800434c: 2b00 cmp r3, #0
|
|
800434e: d101 bne.n 8004354 <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004350: 2301 movs r3, #1
|
|
8004352: e041 b.n 80043d8 <HAL_TIM_PWM_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8004354: 687b ldr r3, [r7, #4]
|
|
8004356: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800435a: b2db uxtb r3, r3
|
|
800435c: 2b00 cmp r3, #0
|
|
800435e: d106 bne.n 800436e <HAL_TIM_PWM_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8004360: 687b ldr r3, [r7, #4]
|
|
8004362: 2200 movs r2, #0
|
|
8004364: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
8004368: 6878 ldr r0, [r7, #4]
|
|
800436a: f000 f839 bl 80043e0 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800436e: 687b ldr r3, [r7, #4]
|
|
8004370: 2202 movs r2, #2
|
|
8004372: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8004376: 687b ldr r3, [r7, #4]
|
|
8004378: 681a ldr r2, [r3, #0]
|
|
800437a: 687b ldr r3, [r7, #4]
|
|
800437c: 3304 adds r3, #4
|
|
800437e: 4619 mov r1, r3
|
|
8004380: 4610 mov r0, r2
|
|
8004382: f000 faef bl 8004964 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8004386: 687b ldr r3, [r7, #4]
|
|
8004388: 2201 movs r2, #1
|
|
800438a: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800438e: 687b ldr r3, [r7, #4]
|
|
8004390: 2201 movs r2, #1
|
|
8004392: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8004396: 687b ldr r3, [r7, #4]
|
|
8004398: 2201 movs r2, #1
|
|
800439a: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
800439e: 687b ldr r3, [r7, #4]
|
|
80043a0: 2201 movs r2, #1
|
|
80043a2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80043a6: 687b ldr r3, [r7, #4]
|
|
80043a8: 2201 movs r2, #1
|
|
80043aa: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80043ae: 687b ldr r3, [r7, #4]
|
|
80043b0: 2201 movs r2, #1
|
|
80043b2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80043b6: 687b ldr r3, [r7, #4]
|
|
80043b8: 2201 movs r2, #1
|
|
80043ba: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
80043be: 687b ldr r3, [r7, #4]
|
|
80043c0: 2201 movs r2, #1
|
|
80043c2: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
80043c6: 687b ldr r3, [r7, #4]
|
|
80043c8: 2201 movs r2, #1
|
|
80043ca: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80043ce: 687b ldr r3, [r7, #4]
|
|
80043d0: 2201 movs r2, #1
|
|
80043d2: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80043d6: 2300 movs r3, #0
|
|
}
|
|
80043d8: 4618 mov r0, r3
|
|
80043da: 3708 adds r7, #8
|
|
80043dc: 46bd mov sp, r7
|
|
80043de: bd80 pop {r7, pc}
|
|
|
|
080043e0 <HAL_TIM_PWM_MspInit>:
|
|
* @brief Initializes the TIM PWM MSP.
|
|
* @param htim TIM PWM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
80043e0: b480 push {r7}
|
|
80043e2: b083 sub sp, #12
|
|
80043e4: af00 add r7, sp, #0
|
|
80043e6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
80043e8: bf00 nop
|
|
80043ea: 370c adds r7, #12
|
|
80043ec: 46bd mov sp, r7
|
|
80043ee: bc80 pop {r7}
|
|
80043f0: 4770 bx lr
|
|
...
|
|
|
|
080043f4 <HAL_TIM_PWM_Start>:
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
80043f4: b580 push {r7, lr}
|
|
80043f6: b084 sub sp, #16
|
|
80043f8: af00 add r7, sp, #0
|
|
80043fa: 6078 str r0, [r7, #4]
|
|
80043fc: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Check the TIM channel state */
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
80043fe: 683b ldr r3, [r7, #0]
|
|
8004400: 2b00 cmp r3, #0
|
|
8004402: d109 bne.n 8004418 <HAL_TIM_PWM_Start+0x24>
|
|
8004404: 687b ldr r3, [r7, #4]
|
|
8004406: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
|
|
800440a: b2db uxtb r3, r3
|
|
800440c: 2b01 cmp r3, #1
|
|
800440e: bf14 ite ne
|
|
8004410: 2301 movne r3, #1
|
|
8004412: 2300 moveq r3, #0
|
|
8004414: b2db uxtb r3, r3
|
|
8004416: e022 b.n 800445e <HAL_TIM_PWM_Start+0x6a>
|
|
8004418: 683b ldr r3, [r7, #0]
|
|
800441a: 2b04 cmp r3, #4
|
|
800441c: d109 bne.n 8004432 <HAL_TIM_PWM_Start+0x3e>
|
|
800441e: 687b ldr r3, [r7, #4]
|
|
8004420: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
|
|
8004424: b2db uxtb r3, r3
|
|
8004426: 2b01 cmp r3, #1
|
|
8004428: bf14 ite ne
|
|
800442a: 2301 movne r3, #1
|
|
800442c: 2300 moveq r3, #0
|
|
800442e: b2db uxtb r3, r3
|
|
8004430: e015 b.n 800445e <HAL_TIM_PWM_Start+0x6a>
|
|
8004432: 683b ldr r3, [r7, #0]
|
|
8004434: 2b08 cmp r3, #8
|
|
8004436: d109 bne.n 800444c <HAL_TIM_PWM_Start+0x58>
|
|
8004438: 687b ldr r3, [r7, #4]
|
|
800443a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800443e: b2db uxtb r3, r3
|
|
8004440: 2b01 cmp r3, #1
|
|
8004442: bf14 ite ne
|
|
8004444: 2301 movne r3, #1
|
|
8004446: 2300 moveq r3, #0
|
|
8004448: b2db uxtb r3, r3
|
|
800444a: e008 b.n 800445e <HAL_TIM_PWM_Start+0x6a>
|
|
800444c: 687b ldr r3, [r7, #4]
|
|
800444e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004452: b2db uxtb r3, r3
|
|
8004454: 2b01 cmp r3, #1
|
|
8004456: bf14 ite ne
|
|
8004458: 2301 movne r3, #1
|
|
800445a: 2300 moveq r3, #0
|
|
800445c: b2db uxtb r3, r3
|
|
800445e: 2b00 cmp r3, #0
|
|
8004460: d001 beq.n 8004466 <HAL_TIM_PWM_Start+0x72>
|
|
{
|
|
return HAL_ERROR;
|
|
8004462: 2301 movs r3, #1
|
|
8004464: e05e b.n 8004524 <HAL_TIM_PWM_Start+0x130>
|
|
}
|
|
|
|
/* Set the TIM channel state */
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8004466: 683b ldr r3, [r7, #0]
|
|
8004468: 2b00 cmp r3, #0
|
|
800446a: d104 bne.n 8004476 <HAL_TIM_PWM_Start+0x82>
|
|
800446c: 687b ldr r3, [r7, #4]
|
|
800446e: 2202 movs r2, #2
|
|
8004470: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8004474: e013 b.n 800449e <HAL_TIM_PWM_Start+0xaa>
|
|
8004476: 683b ldr r3, [r7, #0]
|
|
8004478: 2b04 cmp r3, #4
|
|
800447a: d104 bne.n 8004486 <HAL_TIM_PWM_Start+0x92>
|
|
800447c: 687b ldr r3, [r7, #4]
|
|
800447e: 2202 movs r2, #2
|
|
8004480: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8004484: e00b b.n 800449e <HAL_TIM_PWM_Start+0xaa>
|
|
8004486: 683b ldr r3, [r7, #0]
|
|
8004488: 2b08 cmp r3, #8
|
|
800448a: d104 bne.n 8004496 <HAL_TIM_PWM_Start+0xa2>
|
|
800448c: 687b ldr r3, [r7, #4]
|
|
800448e: 2202 movs r2, #2
|
|
8004490: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8004494: e003 b.n 800449e <HAL_TIM_PWM_Start+0xaa>
|
|
8004496: 687b ldr r3, [r7, #4]
|
|
8004498: 2202 movs r2, #2
|
|
800449a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Enable the Capture compare channel */
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
800449e: 687b ldr r3, [r7, #4]
|
|
80044a0: 681b ldr r3, [r3, #0]
|
|
80044a2: 2201 movs r2, #1
|
|
80044a4: 6839 ldr r1, [r7, #0]
|
|
80044a6: 4618 mov r0, r3
|
|
80044a8: f000 fce8 bl 8004e7c <TIM_CCxChannelCmd>
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
80044ac: 687b ldr r3, [r7, #4]
|
|
80044ae: 681b ldr r3, [r3, #0]
|
|
80044b0: 4a1e ldr r2, [pc, #120] @ (800452c <HAL_TIM_PWM_Start+0x138>)
|
|
80044b2: 4293 cmp r3, r2
|
|
80044b4: d107 bne.n 80044c6 <HAL_TIM_PWM_Start+0xd2>
|
|
{
|
|
/* Enable the main output */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
80044b6: 687b ldr r3, [r7, #4]
|
|
80044b8: 681b ldr r3, [r3, #0]
|
|
80044ba: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
80044bc: 687b ldr r3, [r7, #4]
|
|
80044be: 681b ldr r3, [r3, #0]
|
|
80044c0: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
80044c4: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
80044c6: 687b ldr r3, [r7, #4]
|
|
80044c8: 681b ldr r3, [r3, #0]
|
|
80044ca: 4a18 ldr r2, [pc, #96] @ (800452c <HAL_TIM_PWM_Start+0x138>)
|
|
80044cc: 4293 cmp r3, r2
|
|
80044ce: d00e beq.n 80044ee <HAL_TIM_PWM_Start+0xfa>
|
|
80044d0: 687b ldr r3, [r7, #4]
|
|
80044d2: 681b ldr r3, [r3, #0]
|
|
80044d4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80044d8: d009 beq.n 80044ee <HAL_TIM_PWM_Start+0xfa>
|
|
80044da: 687b ldr r3, [r7, #4]
|
|
80044dc: 681b ldr r3, [r3, #0]
|
|
80044de: 4a14 ldr r2, [pc, #80] @ (8004530 <HAL_TIM_PWM_Start+0x13c>)
|
|
80044e0: 4293 cmp r3, r2
|
|
80044e2: d004 beq.n 80044ee <HAL_TIM_PWM_Start+0xfa>
|
|
80044e4: 687b ldr r3, [r7, #4]
|
|
80044e6: 681b ldr r3, [r3, #0]
|
|
80044e8: 4a12 ldr r2, [pc, #72] @ (8004534 <HAL_TIM_PWM_Start+0x140>)
|
|
80044ea: 4293 cmp r3, r2
|
|
80044ec: d111 bne.n 8004512 <HAL_TIM_PWM_Start+0x11e>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
80044ee: 687b ldr r3, [r7, #4]
|
|
80044f0: 681b ldr r3, [r3, #0]
|
|
80044f2: 689b ldr r3, [r3, #8]
|
|
80044f4: f003 0307 and.w r3, r3, #7
|
|
80044f8: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
80044fa: 68fb ldr r3, [r7, #12]
|
|
80044fc: 2b06 cmp r3, #6
|
|
80044fe: d010 beq.n 8004522 <HAL_TIM_PWM_Start+0x12e>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8004500: 687b ldr r3, [r7, #4]
|
|
8004502: 681b ldr r3, [r3, #0]
|
|
8004504: 681a ldr r2, [r3, #0]
|
|
8004506: 687b ldr r3, [r7, #4]
|
|
8004508: 681b ldr r3, [r3, #0]
|
|
800450a: f042 0201 orr.w r2, r2, #1
|
|
800450e: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8004510: e007 b.n 8004522 <HAL_TIM_PWM_Start+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8004512: 687b ldr r3, [r7, #4]
|
|
8004514: 681b ldr r3, [r3, #0]
|
|
8004516: 681a ldr r2, [r3, #0]
|
|
8004518: 687b ldr r3, [r7, #4]
|
|
800451a: 681b ldr r3, [r3, #0]
|
|
800451c: f042 0201 orr.w r2, r2, #1
|
|
8004520: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8004522: 2300 movs r3, #0
|
|
}
|
|
8004524: 4618 mov r0, r3
|
|
8004526: 3710 adds r7, #16
|
|
8004528: 46bd mov sp, r7
|
|
800452a: bd80 pop {r7, pc}
|
|
800452c: 40012c00 .word 0x40012c00
|
|
8004530: 40000400 .word 0x40000400
|
|
8004534: 40000800 .word 0x40000800
|
|
|
|
08004538 <HAL_TIM_PWM_Stop>:
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
8004538: b580 push {r7, lr}
|
|
800453a: b082 sub sp, #8
|
|
800453c: af00 add r7, sp, #0
|
|
800453e: 6078 str r0, [r7, #4]
|
|
8004540: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Disable the Capture compare channel */
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
8004542: 687b ldr r3, [r7, #4]
|
|
8004544: 681b ldr r3, [r3, #0]
|
|
8004546: 2200 movs r2, #0
|
|
8004548: 6839 ldr r1, [r7, #0]
|
|
800454a: 4618 mov r0, r3
|
|
800454c: f000 fc96 bl 8004e7c <TIM_CCxChannelCmd>
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
8004550: 687b ldr r3, [r7, #4]
|
|
8004552: 681b ldr r3, [r3, #0]
|
|
8004554: 4a29 ldr r2, [pc, #164] @ (80045fc <HAL_TIM_PWM_Stop+0xc4>)
|
|
8004556: 4293 cmp r3, r2
|
|
8004558: d117 bne.n 800458a <HAL_TIM_PWM_Stop+0x52>
|
|
{
|
|
/* Disable the Main Output */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
800455a: 687b ldr r3, [r7, #4]
|
|
800455c: 681b ldr r3, [r3, #0]
|
|
800455e: 6a1a ldr r2, [r3, #32]
|
|
8004560: f241 1311 movw r3, #4369 @ 0x1111
|
|
8004564: 4013 ands r3, r2
|
|
8004566: 2b00 cmp r3, #0
|
|
8004568: d10f bne.n 800458a <HAL_TIM_PWM_Stop+0x52>
|
|
800456a: 687b ldr r3, [r7, #4]
|
|
800456c: 681b ldr r3, [r3, #0]
|
|
800456e: 6a1a ldr r2, [r3, #32]
|
|
8004570: f240 4344 movw r3, #1092 @ 0x444
|
|
8004574: 4013 ands r3, r2
|
|
8004576: 2b00 cmp r3, #0
|
|
8004578: d107 bne.n 800458a <HAL_TIM_PWM_Stop+0x52>
|
|
800457a: 687b ldr r3, [r7, #4]
|
|
800457c: 681b ldr r3, [r3, #0]
|
|
800457e: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8004580: 687b ldr r3, [r7, #4]
|
|
8004582: 681b ldr r3, [r3, #0]
|
|
8004584: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8004588: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
800458a: 687b ldr r3, [r7, #4]
|
|
800458c: 681b ldr r3, [r3, #0]
|
|
800458e: 6a1a ldr r2, [r3, #32]
|
|
8004590: f241 1311 movw r3, #4369 @ 0x1111
|
|
8004594: 4013 ands r3, r2
|
|
8004596: 2b00 cmp r3, #0
|
|
8004598: d10f bne.n 80045ba <HAL_TIM_PWM_Stop+0x82>
|
|
800459a: 687b ldr r3, [r7, #4]
|
|
800459c: 681b ldr r3, [r3, #0]
|
|
800459e: 6a1a ldr r2, [r3, #32]
|
|
80045a0: f240 4344 movw r3, #1092 @ 0x444
|
|
80045a4: 4013 ands r3, r2
|
|
80045a6: 2b00 cmp r3, #0
|
|
80045a8: d107 bne.n 80045ba <HAL_TIM_PWM_Stop+0x82>
|
|
80045aa: 687b ldr r3, [r7, #4]
|
|
80045ac: 681b ldr r3, [r3, #0]
|
|
80045ae: 681a ldr r2, [r3, #0]
|
|
80045b0: 687b ldr r3, [r7, #4]
|
|
80045b2: 681b ldr r3, [r3, #0]
|
|
80045b4: f022 0201 bic.w r2, r2, #1
|
|
80045b8: 601a str r2, [r3, #0]
|
|
|
|
/* Set the TIM channel state */
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
|
|
80045ba: 683b ldr r3, [r7, #0]
|
|
80045bc: 2b00 cmp r3, #0
|
|
80045be: d104 bne.n 80045ca <HAL_TIM_PWM_Stop+0x92>
|
|
80045c0: 687b ldr r3, [r7, #4]
|
|
80045c2: 2201 movs r2, #1
|
|
80045c4: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
80045c8: e013 b.n 80045f2 <HAL_TIM_PWM_Stop+0xba>
|
|
80045ca: 683b ldr r3, [r7, #0]
|
|
80045cc: 2b04 cmp r3, #4
|
|
80045ce: d104 bne.n 80045da <HAL_TIM_PWM_Stop+0xa2>
|
|
80045d0: 687b ldr r3, [r7, #4]
|
|
80045d2: 2201 movs r2, #1
|
|
80045d4: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
80045d8: e00b b.n 80045f2 <HAL_TIM_PWM_Stop+0xba>
|
|
80045da: 683b ldr r3, [r7, #0]
|
|
80045dc: 2b08 cmp r3, #8
|
|
80045de: d104 bne.n 80045ea <HAL_TIM_PWM_Stop+0xb2>
|
|
80045e0: 687b ldr r3, [r7, #4]
|
|
80045e2: 2201 movs r2, #1
|
|
80045e4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80045e8: e003 b.n 80045f2 <HAL_TIM_PWM_Stop+0xba>
|
|
80045ea: 687b ldr r3, [r7, #4]
|
|
80045ec: 2201 movs r2, #1
|
|
80045ee: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80045f2: 2300 movs r3, #0
|
|
}
|
|
80045f4: 4618 mov r0, r3
|
|
80045f6: 3708 adds r7, #8
|
|
80045f8: 46bd mov sp, r7
|
|
80045fa: bd80 pop {r7, pc}
|
|
80045fc: 40012c00 .word 0x40012c00
|
|
|
|
08004600 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
8004600: b580 push {r7, lr}
|
|
8004602: b086 sub sp, #24
|
|
8004604: af00 add r7, sp, #0
|
|
8004606: 60f8 str r0, [r7, #12]
|
|
8004608: 60b9 str r1, [r7, #8]
|
|
800460a: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800460c: 2300 movs r3, #0
|
|
800460e: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8004610: 68fb ldr r3, [r7, #12]
|
|
8004612: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004616: 2b01 cmp r3, #1
|
|
8004618: d101 bne.n 800461e <HAL_TIM_PWM_ConfigChannel+0x1e>
|
|
800461a: 2302 movs r3, #2
|
|
800461c: e0ae b.n 800477c <HAL_TIM_PWM_ConfigChannel+0x17c>
|
|
800461e: 68fb ldr r3, [r7, #12]
|
|
8004620: 2201 movs r2, #1
|
|
8004622: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
8004626: 687b ldr r3, [r7, #4]
|
|
8004628: 2b0c cmp r3, #12
|
|
800462a: f200 809f bhi.w 800476c <HAL_TIM_PWM_ConfigChannel+0x16c>
|
|
800462e: a201 add r2, pc, #4 @ (adr r2, 8004634 <HAL_TIM_PWM_ConfigChannel+0x34>)
|
|
8004630: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8004634: 08004669 .word 0x08004669
|
|
8004638: 0800476d .word 0x0800476d
|
|
800463c: 0800476d .word 0x0800476d
|
|
8004640: 0800476d .word 0x0800476d
|
|
8004644: 080046a9 .word 0x080046a9
|
|
8004648: 0800476d .word 0x0800476d
|
|
800464c: 0800476d .word 0x0800476d
|
|
8004650: 0800476d .word 0x0800476d
|
|
8004654: 080046eb .word 0x080046eb
|
|
8004658: 0800476d .word 0x0800476d
|
|
800465c: 0800476d .word 0x0800476d
|
|
8004660: 0800476d .word 0x0800476d
|
|
8004664: 0800472b .word 0x0800472b
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8004668: 68fb ldr r3, [r7, #12]
|
|
800466a: 681b ldr r3, [r3, #0]
|
|
800466c: 68b9 ldr r1, [r7, #8]
|
|
800466e: 4618 mov r0, r3
|
|
8004670: f000 f9e6 bl 8004a40 <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
8004674: 68fb ldr r3, [r7, #12]
|
|
8004676: 681b ldr r3, [r3, #0]
|
|
8004678: 699a ldr r2, [r3, #24]
|
|
800467a: 68fb ldr r3, [r7, #12]
|
|
800467c: 681b ldr r3, [r3, #0]
|
|
800467e: f042 0208 orr.w r2, r2, #8
|
|
8004682: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
8004684: 68fb ldr r3, [r7, #12]
|
|
8004686: 681b ldr r3, [r3, #0]
|
|
8004688: 699a ldr r2, [r3, #24]
|
|
800468a: 68fb ldr r3, [r7, #12]
|
|
800468c: 681b ldr r3, [r3, #0]
|
|
800468e: f022 0204 bic.w r2, r2, #4
|
|
8004692: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
8004694: 68fb ldr r3, [r7, #12]
|
|
8004696: 681b ldr r3, [r3, #0]
|
|
8004698: 6999 ldr r1, [r3, #24]
|
|
800469a: 68bb ldr r3, [r7, #8]
|
|
800469c: 691a ldr r2, [r3, #16]
|
|
800469e: 68fb ldr r3, [r7, #12]
|
|
80046a0: 681b ldr r3, [r3, #0]
|
|
80046a2: 430a orrs r2, r1
|
|
80046a4: 619a str r2, [r3, #24]
|
|
break;
|
|
80046a6: e064 b.n 8004772 <HAL_TIM_PWM_ConfigChannel+0x172>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
80046a8: 68fb ldr r3, [r7, #12]
|
|
80046aa: 681b ldr r3, [r3, #0]
|
|
80046ac: 68b9 ldr r1, [r7, #8]
|
|
80046ae: 4618 mov r0, r3
|
|
80046b0: f000 fa2c bl 8004b0c <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
80046b4: 68fb ldr r3, [r7, #12]
|
|
80046b6: 681b ldr r3, [r3, #0]
|
|
80046b8: 699a ldr r2, [r3, #24]
|
|
80046ba: 68fb ldr r3, [r7, #12]
|
|
80046bc: 681b ldr r3, [r3, #0]
|
|
80046be: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
80046c2: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
80046c4: 68fb ldr r3, [r7, #12]
|
|
80046c6: 681b ldr r3, [r3, #0]
|
|
80046c8: 699a ldr r2, [r3, #24]
|
|
80046ca: 68fb ldr r3, [r7, #12]
|
|
80046cc: 681b ldr r3, [r3, #0]
|
|
80046ce: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
80046d2: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
80046d4: 68fb ldr r3, [r7, #12]
|
|
80046d6: 681b ldr r3, [r3, #0]
|
|
80046d8: 6999 ldr r1, [r3, #24]
|
|
80046da: 68bb ldr r3, [r7, #8]
|
|
80046dc: 691b ldr r3, [r3, #16]
|
|
80046de: 021a lsls r2, r3, #8
|
|
80046e0: 68fb ldr r3, [r7, #12]
|
|
80046e2: 681b ldr r3, [r3, #0]
|
|
80046e4: 430a orrs r2, r1
|
|
80046e6: 619a str r2, [r3, #24]
|
|
break;
|
|
80046e8: e043 b.n 8004772 <HAL_TIM_PWM_ConfigChannel+0x172>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
80046ea: 68fb ldr r3, [r7, #12]
|
|
80046ec: 681b ldr r3, [r3, #0]
|
|
80046ee: 68b9 ldr r1, [r7, #8]
|
|
80046f0: 4618 mov r0, r3
|
|
80046f2: f000 fa75 bl 8004be0 <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
80046f6: 68fb ldr r3, [r7, #12]
|
|
80046f8: 681b ldr r3, [r3, #0]
|
|
80046fa: 69da ldr r2, [r3, #28]
|
|
80046fc: 68fb ldr r3, [r7, #12]
|
|
80046fe: 681b ldr r3, [r3, #0]
|
|
8004700: f042 0208 orr.w r2, r2, #8
|
|
8004704: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
8004706: 68fb ldr r3, [r7, #12]
|
|
8004708: 681b ldr r3, [r3, #0]
|
|
800470a: 69da ldr r2, [r3, #28]
|
|
800470c: 68fb ldr r3, [r7, #12]
|
|
800470e: 681b ldr r3, [r3, #0]
|
|
8004710: f022 0204 bic.w r2, r2, #4
|
|
8004714: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
8004716: 68fb ldr r3, [r7, #12]
|
|
8004718: 681b ldr r3, [r3, #0]
|
|
800471a: 69d9 ldr r1, [r3, #28]
|
|
800471c: 68bb ldr r3, [r7, #8]
|
|
800471e: 691a ldr r2, [r3, #16]
|
|
8004720: 68fb ldr r3, [r7, #12]
|
|
8004722: 681b ldr r3, [r3, #0]
|
|
8004724: 430a orrs r2, r1
|
|
8004726: 61da str r2, [r3, #28]
|
|
break;
|
|
8004728: e023 b.n 8004772 <HAL_TIM_PWM_ConfigChannel+0x172>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
800472a: 68fb ldr r3, [r7, #12]
|
|
800472c: 681b ldr r3, [r3, #0]
|
|
800472e: 68b9 ldr r1, [r7, #8]
|
|
8004730: 4618 mov r0, r3
|
|
8004732: f000 fabf bl 8004cb4 <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
8004736: 68fb ldr r3, [r7, #12]
|
|
8004738: 681b ldr r3, [r3, #0]
|
|
800473a: 69da ldr r2, [r3, #28]
|
|
800473c: 68fb ldr r3, [r7, #12]
|
|
800473e: 681b ldr r3, [r3, #0]
|
|
8004740: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8004744: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
8004746: 68fb ldr r3, [r7, #12]
|
|
8004748: 681b ldr r3, [r3, #0]
|
|
800474a: 69da ldr r2, [r3, #28]
|
|
800474c: 68fb ldr r3, [r7, #12]
|
|
800474e: 681b ldr r3, [r3, #0]
|
|
8004750: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8004754: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
8004756: 68fb ldr r3, [r7, #12]
|
|
8004758: 681b ldr r3, [r3, #0]
|
|
800475a: 69d9 ldr r1, [r3, #28]
|
|
800475c: 68bb ldr r3, [r7, #8]
|
|
800475e: 691b ldr r3, [r3, #16]
|
|
8004760: 021a lsls r2, r3, #8
|
|
8004762: 68fb ldr r3, [r7, #12]
|
|
8004764: 681b ldr r3, [r3, #0]
|
|
8004766: 430a orrs r2, r1
|
|
8004768: 61da str r2, [r3, #28]
|
|
break;
|
|
800476a: e002 b.n 8004772 <HAL_TIM_PWM_ConfigChannel+0x172>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
800476c: 2301 movs r3, #1
|
|
800476e: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8004770: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004772: 68fb ldr r3, [r7, #12]
|
|
8004774: 2200 movs r2, #0
|
|
8004776: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
800477a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800477c: 4618 mov r0, r3
|
|
800477e: 3718 adds r7, #24
|
|
8004780: 46bd mov sp, r7
|
|
8004782: bd80 pop {r7, pc}
|
|
|
|
08004784 <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
8004784: b580 push {r7, lr}
|
|
8004786: b084 sub sp, #16
|
|
8004788: af00 add r7, sp, #0
|
|
800478a: 6078 str r0, [r7, #4]
|
|
800478c: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800478e: 2300 movs r3, #0
|
|
8004790: 73fb strb r3, [r7, #15]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8004792: 687b ldr r3, [r7, #4]
|
|
8004794: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004798: 2b01 cmp r3, #1
|
|
800479a: d101 bne.n 80047a0 <HAL_TIM_ConfigClockSource+0x1c>
|
|
800479c: 2302 movs r3, #2
|
|
800479e: e0b4 b.n 800490a <HAL_TIM_ConfigClockSource+0x186>
|
|
80047a0: 687b ldr r3, [r7, #4]
|
|
80047a2: 2201 movs r2, #1
|
|
80047a4: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80047a8: 687b ldr r3, [r7, #4]
|
|
80047aa: 2202 movs r2, #2
|
|
80047ac: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80047b0: 687b ldr r3, [r7, #4]
|
|
80047b2: 681b ldr r3, [r3, #0]
|
|
80047b4: 689b ldr r3, [r3, #8]
|
|
80047b6: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
80047b8: 68bb ldr r3, [r7, #8]
|
|
80047ba: f023 0377 bic.w r3, r3, #119 @ 0x77
|
|
80047be: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
80047c0: 68bb ldr r3, [r7, #8]
|
|
80047c2: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
80047c6: 60bb str r3, [r7, #8]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80047c8: 687b ldr r3, [r7, #4]
|
|
80047ca: 681b ldr r3, [r3, #0]
|
|
80047cc: 68ba ldr r2, [r7, #8]
|
|
80047ce: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
80047d0: 683b ldr r3, [r7, #0]
|
|
80047d2: 681b ldr r3, [r3, #0]
|
|
80047d4: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
80047d8: d03e beq.n 8004858 <HAL_TIM_ConfigClockSource+0xd4>
|
|
80047da: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
80047de: f200 8087 bhi.w 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
80047e2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80047e6: f000 8086 beq.w 80048f6 <HAL_TIM_ConfigClockSource+0x172>
|
|
80047ea: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80047ee: d87f bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
80047f0: 2b70 cmp r3, #112 @ 0x70
|
|
80047f2: d01a beq.n 800482a <HAL_TIM_ConfigClockSource+0xa6>
|
|
80047f4: 2b70 cmp r3, #112 @ 0x70
|
|
80047f6: d87b bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
80047f8: 2b60 cmp r3, #96 @ 0x60
|
|
80047fa: d050 beq.n 800489e <HAL_TIM_ConfigClockSource+0x11a>
|
|
80047fc: 2b60 cmp r3, #96 @ 0x60
|
|
80047fe: d877 bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8004800: 2b50 cmp r3, #80 @ 0x50
|
|
8004802: d03c beq.n 800487e <HAL_TIM_ConfigClockSource+0xfa>
|
|
8004804: 2b50 cmp r3, #80 @ 0x50
|
|
8004806: d873 bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8004808: 2b40 cmp r3, #64 @ 0x40
|
|
800480a: d058 beq.n 80048be <HAL_TIM_ConfigClockSource+0x13a>
|
|
800480c: 2b40 cmp r3, #64 @ 0x40
|
|
800480e: d86f bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8004810: 2b30 cmp r3, #48 @ 0x30
|
|
8004812: d064 beq.n 80048de <HAL_TIM_ConfigClockSource+0x15a>
|
|
8004814: 2b30 cmp r3, #48 @ 0x30
|
|
8004816: d86b bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8004818: 2b20 cmp r3, #32
|
|
800481a: d060 beq.n 80048de <HAL_TIM_ConfigClockSource+0x15a>
|
|
800481c: 2b20 cmp r3, #32
|
|
800481e: d867 bhi.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8004820: 2b00 cmp r3, #0
|
|
8004822: d05c beq.n 80048de <HAL_TIM_ConfigClockSource+0x15a>
|
|
8004824: 2b10 cmp r3, #16
|
|
8004826: d05a beq.n 80048de <HAL_TIM_ConfigClockSource+0x15a>
|
|
8004828: e062 b.n 80048f0 <HAL_TIM_ConfigClockSource+0x16c>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800482a: 687b ldr r3, [r7, #4]
|
|
800482c: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
800482e: 683b ldr r3, [r7, #0]
|
|
8004830: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8004832: 683b ldr r3, [r7, #0]
|
|
8004834: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8004836: 683b ldr r3, [r7, #0]
|
|
8004838: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800483a: f000 fb00 bl 8004e3e <TIM_ETR_SetConfig>
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800483e: 687b ldr r3, [r7, #4]
|
|
8004840: 681b ldr r3, [r3, #0]
|
|
8004842: 689b ldr r3, [r3, #8]
|
|
8004844: 60bb str r3, [r7, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
8004846: 68bb ldr r3, [r7, #8]
|
|
8004848: f043 0377 orr.w r3, r3, #119 @ 0x77
|
|
800484c: 60bb str r3, [r7, #8]
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800484e: 687b ldr r3, [r7, #4]
|
|
8004850: 681b ldr r3, [r3, #0]
|
|
8004852: 68ba ldr r2, [r7, #8]
|
|
8004854: 609a str r2, [r3, #8]
|
|
break;
|
|
8004856: e04f b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
800485a: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
800485c: 683b ldr r3, [r7, #0]
|
|
800485e: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8004860: 683b ldr r3, [r7, #0]
|
|
8004862: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8004864: 683b ldr r3, [r7, #0]
|
|
8004866: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8004868: f000 fae9 bl 8004e3e <TIM_ETR_SetConfig>
|
|
/* Enable the External clock mode2 */
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
800486c: 687b ldr r3, [r7, #4]
|
|
800486e: 681b ldr r3, [r3, #0]
|
|
8004870: 689a ldr r2, [r3, #8]
|
|
8004872: 687b ldr r3, [r7, #4]
|
|
8004874: 681b ldr r3, [r3, #0]
|
|
8004876: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800487a: 609a str r2, [r3, #8]
|
|
break;
|
|
800487c: e03c b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800487e: 687b ldr r3, [r7, #4]
|
|
8004880: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8004882: 683b ldr r3, [r7, #0]
|
|
8004884: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8004886: 683b ldr r3, [r7, #0]
|
|
8004888: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800488a: 461a mov r2, r3
|
|
800488c: f000 fa60 bl 8004d50 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
8004890: 687b ldr r3, [r7, #4]
|
|
8004892: 681b ldr r3, [r3, #0]
|
|
8004894: 2150 movs r1, #80 @ 0x50
|
|
8004896: 4618 mov r0, r3
|
|
8004898: f000 fab7 bl 8004e0a <TIM_ITRx_SetConfig>
|
|
break;
|
|
800489c: e02c b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
800489e: 687b ldr r3, [r7, #4]
|
|
80048a0: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80048a2: 683b ldr r3, [r7, #0]
|
|
80048a4: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80048a6: 683b ldr r3, [r7, #0]
|
|
80048a8: 68db ldr r3, [r3, #12]
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
80048aa: 461a mov r2, r3
|
|
80048ac: f000 fa7e bl 8004dac <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
80048b0: 687b ldr r3, [r7, #4]
|
|
80048b2: 681b ldr r3, [r3, #0]
|
|
80048b4: 2160 movs r1, #96 @ 0x60
|
|
80048b6: 4618 mov r0, r3
|
|
80048b8: f000 faa7 bl 8004e0a <TIM_ITRx_SetConfig>
|
|
break;
|
|
80048bc: e01c b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80048be: 687b ldr r3, [r7, #4]
|
|
80048c0: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80048c2: 683b ldr r3, [r7, #0]
|
|
80048c4: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80048c6: 683b ldr r3, [r7, #0]
|
|
80048c8: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80048ca: 461a mov r2, r3
|
|
80048cc: f000 fa40 bl 8004d50 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
80048d0: 687b ldr r3, [r7, #4]
|
|
80048d2: 681b ldr r3, [r3, #0]
|
|
80048d4: 2140 movs r1, #64 @ 0x40
|
|
80048d6: 4618 mov r0, r3
|
|
80048d8: f000 fa97 bl 8004e0a <TIM_ITRx_SetConfig>
|
|
break;
|
|
80048dc: e00c b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
case TIM_CLOCKSOURCE_ITR3:
|
|
{
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
80048de: 687b ldr r3, [r7, #4]
|
|
80048e0: 681a ldr r2, [r3, #0]
|
|
80048e2: 683b ldr r3, [r7, #0]
|
|
80048e4: 681b ldr r3, [r3, #0]
|
|
80048e6: 4619 mov r1, r3
|
|
80048e8: 4610 mov r0, r2
|
|
80048ea: f000 fa8e bl 8004e0a <TIM_ITRx_SetConfig>
|
|
break;
|
|
80048ee: e003 b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
80048f0: 2301 movs r3, #1
|
|
80048f2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80048f4: e000 b.n 80048f8 <HAL_TIM_ConfigClockSource+0x174>
|
|
break;
|
|
80048f6: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80048f8: 687b ldr r3, [r7, #4]
|
|
80048fa: 2201 movs r2, #1
|
|
80048fc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004900: 687b ldr r3, [r7, #4]
|
|
8004902: 2200 movs r2, #0
|
|
8004904: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8004908: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800490a: 4618 mov r0, r3
|
|
800490c: 3710 adds r7, #16
|
|
800490e: 46bd mov sp, r7
|
|
8004910: bd80 pop {r7, pc}
|
|
|
|
08004912 <HAL_TIM_GetChannelState>:
|
|
* @arg TIM_CHANNEL_5: TIM Channel 5
|
|
* @arg TIM_CHANNEL_6: TIM Channel 6
|
|
* @retval TIM Channel state
|
|
*/
|
|
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
8004912: b480 push {r7}
|
|
8004914: b085 sub sp, #20
|
|
8004916: af00 add r7, sp, #0
|
|
8004918: 6078 str r0, [r7, #4]
|
|
800491a: 6039 str r1, [r7, #0]
|
|
HAL_TIM_ChannelStateTypeDef channel_state;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
|
|
800491c: 683b ldr r3, [r7, #0]
|
|
800491e: 2b00 cmp r3, #0
|
|
8004920: d104 bne.n 800492c <HAL_TIM_GetChannelState+0x1a>
|
|
8004922: 687b ldr r3, [r7, #4]
|
|
8004924: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
|
|
8004928: b2db uxtb r3, r3
|
|
800492a: e013 b.n 8004954 <HAL_TIM_GetChannelState+0x42>
|
|
800492c: 683b ldr r3, [r7, #0]
|
|
800492e: 2b04 cmp r3, #4
|
|
8004930: d104 bne.n 800493c <HAL_TIM_GetChannelState+0x2a>
|
|
8004932: 687b ldr r3, [r7, #4]
|
|
8004934: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
|
|
8004938: b2db uxtb r3, r3
|
|
800493a: e00b b.n 8004954 <HAL_TIM_GetChannelState+0x42>
|
|
800493c: 683b ldr r3, [r7, #0]
|
|
800493e: 2b08 cmp r3, #8
|
|
8004940: d104 bne.n 800494c <HAL_TIM_GetChannelState+0x3a>
|
|
8004942: 687b ldr r3, [r7, #4]
|
|
8004944: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8004948: b2db uxtb r3, r3
|
|
800494a: e003 b.n 8004954 <HAL_TIM_GetChannelState+0x42>
|
|
800494c: 687b ldr r3, [r7, #4]
|
|
800494e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004952: b2db uxtb r3, r3
|
|
8004954: 73fb strb r3, [r7, #15]
|
|
|
|
return channel_state;
|
|
8004956: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004958: 4618 mov r0, r3
|
|
800495a: 3714 adds r7, #20
|
|
800495c: 46bd mov sp, r7
|
|
800495e: bc80 pop {r7}
|
|
8004960: 4770 bx lr
|
|
...
|
|
|
|
08004964 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8004964: b480 push {r7}
|
|
8004966: b085 sub sp, #20
|
|
8004968: af00 add r7, sp, #0
|
|
800496a: 6078 str r0, [r7, #4]
|
|
800496c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800496e: 687b ldr r3, [r7, #4]
|
|
8004970: 681b ldr r3, [r3, #0]
|
|
8004972: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8004974: 687b ldr r3, [r7, #4]
|
|
8004976: 4a2f ldr r2, [pc, #188] @ (8004a34 <TIM_Base_SetConfig+0xd0>)
|
|
8004978: 4293 cmp r3, r2
|
|
800497a: d00b beq.n 8004994 <TIM_Base_SetConfig+0x30>
|
|
800497c: 687b ldr r3, [r7, #4]
|
|
800497e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8004982: d007 beq.n 8004994 <TIM_Base_SetConfig+0x30>
|
|
8004984: 687b ldr r3, [r7, #4]
|
|
8004986: 4a2c ldr r2, [pc, #176] @ (8004a38 <TIM_Base_SetConfig+0xd4>)
|
|
8004988: 4293 cmp r3, r2
|
|
800498a: d003 beq.n 8004994 <TIM_Base_SetConfig+0x30>
|
|
800498c: 687b ldr r3, [r7, #4]
|
|
800498e: 4a2b ldr r2, [pc, #172] @ (8004a3c <TIM_Base_SetConfig+0xd8>)
|
|
8004990: 4293 cmp r3, r2
|
|
8004992: d108 bne.n 80049a6 <TIM_Base_SetConfig+0x42>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8004994: 68fb ldr r3, [r7, #12]
|
|
8004996: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800499a: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
800499c: 683b ldr r3, [r7, #0]
|
|
800499e: 685b ldr r3, [r3, #4]
|
|
80049a0: 68fa ldr r2, [r7, #12]
|
|
80049a2: 4313 orrs r3, r2
|
|
80049a4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80049a6: 687b ldr r3, [r7, #4]
|
|
80049a8: 4a22 ldr r2, [pc, #136] @ (8004a34 <TIM_Base_SetConfig+0xd0>)
|
|
80049aa: 4293 cmp r3, r2
|
|
80049ac: d00b beq.n 80049c6 <TIM_Base_SetConfig+0x62>
|
|
80049ae: 687b ldr r3, [r7, #4]
|
|
80049b0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80049b4: d007 beq.n 80049c6 <TIM_Base_SetConfig+0x62>
|
|
80049b6: 687b ldr r3, [r7, #4]
|
|
80049b8: 4a1f ldr r2, [pc, #124] @ (8004a38 <TIM_Base_SetConfig+0xd4>)
|
|
80049ba: 4293 cmp r3, r2
|
|
80049bc: d003 beq.n 80049c6 <TIM_Base_SetConfig+0x62>
|
|
80049be: 687b ldr r3, [r7, #4]
|
|
80049c0: 4a1e ldr r2, [pc, #120] @ (8004a3c <TIM_Base_SetConfig+0xd8>)
|
|
80049c2: 4293 cmp r3, r2
|
|
80049c4: d108 bne.n 80049d8 <TIM_Base_SetConfig+0x74>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
80049c6: 68fb ldr r3, [r7, #12]
|
|
80049c8: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80049cc: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
80049ce: 683b ldr r3, [r7, #0]
|
|
80049d0: 68db ldr r3, [r3, #12]
|
|
80049d2: 68fa ldr r2, [r7, #12]
|
|
80049d4: 4313 orrs r3, r2
|
|
80049d6: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
80049d8: 68fb ldr r3, [r7, #12]
|
|
80049da: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80049de: 683b ldr r3, [r7, #0]
|
|
80049e0: 695b ldr r3, [r3, #20]
|
|
80049e2: 4313 orrs r3, r2
|
|
80049e4: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
80049e6: 687b ldr r3, [r7, #4]
|
|
80049e8: 68fa ldr r2, [r7, #12]
|
|
80049ea: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
80049ec: 683b ldr r3, [r7, #0]
|
|
80049ee: 689a ldr r2, [r3, #8]
|
|
80049f0: 687b ldr r3, [r7, #4]
|
|
80049f2: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
80049f4: 683b ldr r3, [r7, #0]
|
|
80049f6: 681a ldr r2, [r3, #0]
|
|
80049f8: 687b ldr r3, [r7, #4]
|
|
80049fa: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
80049fc: 687b ldr r3, [r7, #4]
|
|
80049fe: 4a0d ldr r2, [pc, #52] @ (8004a34 <TIM_Base_SetConfig+0xd0>)
|
|
8004a00: 4293 cmp r3, r2
|
|
8004a02: d103 bne.n 8004a0c <TIM_Base_SetConfig+0xa8>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8004a04: 683b ldr r3, [r7, #0]
|
|
8004a06: 691a ldr r2, [r3, #16]
|
|
8004a08: 687b ldr r3, [r7, #4]
|
|
8004a0a: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8004a0c: 687b ldr r3, [r7, #4]
|
|
8004a0e: 2201 movs r2, #1
|
|
8004a10: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
8004a12: 687b ldr r3, [r7, #4]
|
|
8004a14: 691b ldr r3, [r3, #16]
|
|
8004a16: f003 0301 and.w r3, r3, #1
|
|
8004a1a: 2b00 cmp r3, #0
|
|
8004a1c: d005 beq.n 8004a2a <TIM_Base_SetConfig+0xc6>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
8004a1e: 687b ldr r3, [r7, #4]
|
|
8004a20: 691b ldr r3, [r3, #16]
|
|
8004a22: f023 0201 bic.w r2, r3, #1
|
|
8004a26: 687b ldr r3, [r7, #4]
|
|
8004a28: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
8004a2a: bf00 nop
|
|
8004a2c: 3714 adds r7, #20
|
|
8004a2e: 46bd mov sp, r7
|
|
8004a30: bc80 pop {r7}
|
|
8004a32: 4770 bx lr
|
|
8004a34: 40012c00 .word 0x40012c00
|
|
8004a38: 40000400 .word 0x40000400
|
|
8004a3c: 40000800 .word 0x40000800
|
|
|
|
08004a40 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004a40: b480 push {r7}
|
|
8004a42: b087 sub sp, #28
|
|
8004a44: af00 add r7, sp, #0
|
|
8004a46: 6078 str r0, [r7, #4]
|
|
8004a48: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004a4a: 687b ldr r3, [r7, #4]
|
|
8004a4c: 6a1b ldr r3, [r3, #32]
|
|
8004a4e: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8004a50: 687b ldr r3, [r7, #4]
|
|
8004a52: 6a1b ldr r3, [r3, #32]
|
|
8004a54: f023 0201 bic.w r2, r3, #1
|
|
8004a58: 687b ldr r3, [r7, #4]
|
|
8004a5a: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004a5c: 687b ldr r3, [r7, #4]
|
|
8004a5e: 685b ldr r3, [r3, #4]
|
|
8004a60: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8004a62: 687b ldr r3, [r7, #4]
|
|
8004a64: 699b ldr r3, [r3, #24]
|
|
8004a66: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8004a68: 68fb ldr r3, [r7, #12]
|
|
8004a6a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004a6e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8004a70: 68fb ldr r3, [r7, #12]
|
|
8004a72: f023 0303 bic.w r3, r3, #3
|
|
8004a76: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004a78: 683b ldr r3, [r7, #0]
|
|
8004a7a: 681b ldr r3, [r3, #0]
|
|
8004a7c: 68fa ldr r2, [r7, #12]
|
|
8004a7e: 4313 orrs r3, r2
|
|
8004a80: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8004a82: 697b ldr r3, [r7, #20]
|
|
8004a84: f023 0302 bic.w r3, r3, #2
|
|
8004a88: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8004a8a: 683b ldr r3, [r7, #0]
|
|
8004a8c: 689b ldr r3, [r3, #8]
|
|
8004a8e: 697a ldr r2, [r7, #20]
|
|
8004a90: 4313 orrs r3, r2
|
|
8004a92: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8004a94: 687b ldr r3, [r7, #4]
|
|
8004a96: 4a1c ldr r2, [pc, #112] @ (8004b08 <TIM_OC1_SetConfig+0xc8>)
|
|
8004a98: 4293 cmp r3, r2
|
|
8004a9a: d10c bne.n 8004ab6 <TIM_OC1_SetConfig+0x76>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8004a9c: 697b ldr r3, [r7, #20]
|
|
8004a9e: f023 0308 bic.w r3, r3, #8
|
|
8004aa2: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8004aa4: 683b ldr r3, [r7, #0]
|
|
8004aa6: 68db ldr r3, [r3, #12]
|
|
8004aa8: 697a ldr r2, [r7, #20]
|
|
8004aaa: 4313 orrs r3, r2
|
|
8004aac: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8004aae: 697b ldr r3, [r7, #20]
|
|
8004ab0: f023 0304 bic.w r3, r3, #4
|
|
8004ab4: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004ab6: 687b ldr r3, [r7, #4]
|
|
8004ab8: 4a13 ldr r2, [pc, #76] @ (8004b08 <TIM_OC1_SetConfig+0xc8>)
|
|
8004aba: 4293 cmp r3, r2
|
|
8004abc: d111 bne.n 8004ae2 <TIM_OC1_SetConfig+0xa2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8004abe: 693b ldr r3, [r7, #16]
|
|
8004ac0: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8004ac4: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8004ac6: 693b ldr r3, [r7, #16]
|
|
8004ac8: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004acc: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8004ace: 683b ldr r3, [r7, #0]
|
|
8004ad0: 695b ldr r3, [r3, #20]
|
|
8004ad2: 693a ldr r2, [r7, #16]
|
|
8004ad4: 4313 orrs r3, r2
|
|
8004ad6: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8004ad8: 683b ldr r3, [r7, #0]
|
|
8004ada: 699b ldr r3, [r3, #24]
|
|
8004adc: 693a ldr r2, [r7, #16]
|
|
8004ade: 4313 orrs r3, r2
|
|
8004ae0: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004ae2: 687b ldr r3, [r7, #4]
|
|
8004ae4: 693a ldr r2, [r7, #16]
|
|
8004ae6: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004ae8: 687b ldr r3, [r7, #4]
|
|
8004aea: 68fa ldr r2, [r7, #12]
|
|
8004aec: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8004aee: 683b ldr r3, [r7, #0]
|
|
8004af0: 685a ldr r2, [r3, #4]
|
|
8004af2: 687b ldr r3, [r7, #4]
|
|
8004af4: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004af6: 687b ldr r3, [r7, #4]
|
|
8004af8: 697a ldr r2, [r7, #20]
|
|
8004afa: 621a str r2, [r3, #32]
|
|
}
|
|
8004afc: bf00 nop
|
|
8004afe: 371c adds r7, #28
|
|
8004b00: 46bd mov sp, r7
|
|
8004b02: bc80 pop {r7}
|
|
8004b04: 4770 bx lr
|
|
8004b06: bf00 nop
|
|
8004b08: 40012c00 .word 0x40012c00
|
|
|
|
08004b0c <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004b0c: b480 push {r7}
|
|
8004b0e: b087 sub sp, #28
|
|
8004b10: af00 add r7, sp, #0
|
|
8004b12: 6078 str r0, [r7, #4]
|
|
8004b14: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004b16: 687b ldr r3, [r7, #4]
|
|
8004b18: 6a1b ldr r3, [r3, #32]
|
|
8004b1a: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8004b1c: 687b ldr r3, [r7, #4]
|
|
8004b1e: 6a1b ldr r3, [r3, #32]
|
|
8004b20: f023 0210 bic.w r2, r3, #16
|
|
8004b24: 687b ldr r3, [r7, #4]
|
|
8004b26: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004b28: 687b ldr r3, [r7, #4]
|
|
8004b2a: 685b ldr r3, [r3, #4]
|
|
8004b2c: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8004b2e: 687b ldr r3, [r7, #4]
|
|
8004b30: 699b ldr r3, [r3, #24]
|
|
8004b32: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
8004b34: 68fb ldr r3, [r7, #12]
|
|
8004b36: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8004b3a: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8004b3c: 68fb ldr r3, [r7, #12]
|
|
8004b3e: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004b42: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8004b44: 683b ldr r3, [r7, #0]
|
|
8004b46: 681b ldr r3, [r3, #0]
|
|
8004b48: 021b lsls r3, r3, #8
|
|
8004b4a: 68fa ldr r2, [r7, #12]
|
|
8004b4c: 4313 orrs r3, r2
|
|
8004b4e: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8004b50: 697b ldr r3, [r7, #20]
|
|
8004b52: f023 0320 bic.w r3, r3, #32
|
|
8004b56: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8004b58: 683b ldr r3, [r7, #0]
|
|
8004b5a: 689b ldr r3, [r3, #8]
|
|
8004b5c: 011b lsls r3, r3, #4
|
|
8004b5e: 697a ldr r2, [r7, #20]
|
|
8004b60: 4313 orrs r3, r2
|
|
8004b62: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
8004b64: 687b ldr r3, [r7, #4]
|
|
8004b66: 4a1d ldr r2, [pc, #116] @ (8004bdc <TIM_OC2_SetConfig+0xd0>)
|
|
8004b68: 4293 cmp r3, r2
|
|
8004b6a: d10d bne.n 8004b88 <TIM_OC2_SetConfig+0x7c>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8004b6c: 697b ldr r3, [r7, #20]
|
|
8004b6e: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004b72: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8004b74: 683b ldr r3, [r7, #0]
|
|
8004b76: 68db ldr r3, [r3, #12]
|
|
8004b78: 011b lsls r3, r3, #4
|
|
8004b7a: 697a ldr r2, [r7, #20]
|
|
8004b7c: 4313 orrs r3, r2
|
|
8004b7e: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8004b80: 697b ldr r3, [r7, #20]
|
|
8004b82: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8004b86: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004b88: 687b ldr r3, [r7, #4]
|
|
8004b8a: 4a14 ldr r2, [pc, #80] @ (8004bdc <TIM_OC2_SetConfig+0xd0>)
|
|
8004b8c: 4293 cmp r3, r2
|
|
8004b8e: d113 bne.n 8004bb8 <TIM_OC2_SetConfig+0xac>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8004b90: 693b ldr r3, [r7, #16]
|
|
8004b92: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004b96: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8004b98: 693b ldr r3, [r7, #16]
|
|
8004b9a: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8004b9e: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8004ba0: 683b ldr r3, [r7, #0]
|
|
8004ba2: 695b ldr r3, [r3, #20]
|
|
8004ba4: 009b lsls r3, r3, #2
|
|
8004ba6: 693a ldr r2, [r7, #16]
|
|
8004ba8: 4313 orrs r3, r2
|
|
8004baa: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8004bac: 683b ldr r3, [r7, #0]
|
|
8004bae: 699b ldr r3, [r3, #24]
|
|
8004bb0: 009b lsls r3, r3, #2
|
|
8004bb2: 693a ldr r2, [r7, #16]
|
|
8004bb4: 4313 orrs r3, r2
|
|
8004bb6: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004bb8: 687b ldr r3, [r7, #4]
|
|
8004bba: 693a ldr r2, [r7, #16]
|
|
8004bbc: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004bbe: 687b ldr r3, [r7, #4]
|
|
8004bc0: 68fa ldr r2, [r7, #12]
|
|
8004bc2: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8004bc4: 683b ldr r3, [r7, #0]
|
|
8004bc6: 685a ldr r2, [r3, #4]
|
|
8004bc8: 687b ldr r3, [r7, #4]
|
|
8004bca: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004bcc: 687b ldr r3, [r7, #4]
|
|
8004bce: 697a ldr r2, [r7, #20]
|
|
8004bd0: 621a str r2, [r3, #32]
|
|
}
|
|
8004bd2: bf00 nop
|
|
8004bd4: 371c adds r7, #28
|
|
8004bd6: 46bd mov sp, r7
|
|
8004bd8: bc80 pop {r7}
|
|
8004bda: 4770 bx lr
|
|
8004bdc: 40012c00 .word 0x40012c00
|
|
|
|
08004be0 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004be0: b480 push {r7}
|
|
8004be2: b087 sub sp, #28
|
|
8004be4: af00 add r7, sp, #0
|
|
8004be6: 6078 str r0, [r7, #4]
|
|
8004be8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004bea: 687b ldr r3, [r7, #4]
|
|
8004bec: 6a1b ldr r3, [r3, #32]
|
|
8004bee: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8004bf0: 687b ldr r3, [r7, #4]
|
|
8004bf2: 6a1b ldr r3, [r3, #32]
|
|
8004bf4: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8004bf8: 687b ldr r3, [r7, #4]
|
|
8004bfa: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004bfc: 687b ldr r3, [r7, #4]
|
|
8004bfe: 685b ldr r3, [r3, #4]
|
|
8004c00: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004c02: 687b ldr r3, [r7, #4]
|
|
8004c04: 69db ldr r3, [r3, #28]
|
|
8004c06: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8004c08: 68fb ldr r3, [r7, #12]
|
|
8004c0a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004c0e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
8004c10: 68fb ldr r3, [r7, #12]
|
|
8004c12: f023 0303 bic.w r3, r3, #3
|
|
8004c16: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004c18: 683b ldr r3, [r7, #0]
|
|
8004c1a: 681b ldr r3, [r3, #0]
|
|
8004c1c: 68fa ldr r2, [r7, #12]
|
|
8004c1e: 4313 orrs r3, r2
|
|
8004c20: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8004c22: 697b ldr r3, [r7, #20]
|
|
8004c24: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004c28: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8004c2a: 683b ldr r3, [r7, #0]
|
|
8004c2c: 689b ldr r3, [r3, #8]
|
|
8004c2e: 021b lsls r3, r3, #8
|
|
8004c30: 697a ldr r2, [r7, #20]
|
|
8004c32: 4313 orrs r3, r2
|
|
8004c34: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8004c36: 687b ldr r3, [r7, #4]
|
|
8004c38: 4a1d ldr r2, [pc, #116] @ (8004cb0 <TIM_OC3_SetConfig+0xd0>)
|
|
8004c3a: 4293 cmp r3, r2
|
|
8004c3c: d10d bne.n 8004c5a <TIM_OC3_SetConfig+0x7a>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8004c3e: 697b ldr r3, [r7, #20]
|
|
8004c40: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8004c44: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8004c46: 683b ldr r3, [r7, #0]
|
|
8004c48: 68db ldr r3, [r3, #12]
|
|
8004c4a: 021b lsls r3, r3, #8
|
|
8004c4c: 697a ldr r2, [r7, #20]
|
|
8004c4e: 4313 orrs r3, r2
|
|
8004c50: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8004c52: 697b ldr r3, [r7, #20]
|
|
8004c54: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004c58: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004c5a: 687b ldr r3, [r7, #4]
|
|
8004c5c: 4a14 ldr r2, [pc, #80] @ (8004cb0 <TIM_OC3_SetConfig+0xd0>)
|
|
8004c5e: 4293 cmp r3, r2
|
|
8004c60: d113 bne.n 8004c8a <TIM_OC3_SetConfig+0xaa>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8004c62: 693b ldr r3, [r7, #16]
|
|
8004c64: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8004c68: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8004c6a: 693b ldr r3, [r7, #16]
|
|
8004c6c: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004c70: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8004c72: 683b ldr r3, [r7, #0]
|
|
8004c74: 695b ldr r3, [r3, #20]
|
|
8004c76: 011b lsls r3, r3, #4
|
|
8004c78: 693a ldr r2, [r7, #16]
|
|
8004c7a: 4313 orrs r3, r2
|
|
8004c7c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8004c7e: 683b ldr r3, [r7, #0]
|
|
8004c80: 699b ldr r3, [r3, #24]
|
|
8004c82: 011b lsls r3, r3, #4
|
|
8004c84: 693a ldr r2, [r7, #16]
|
|
8004c86: 4313 orrs r3, r2
|
|
8004c88: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004c8a: 687b ldr r3, [r7, #4]
|
|
8004c8c: 693a ldr r2, [r7, #16]
|
|
8004c8e: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004c90: 687b ldr r3, [r7, #4]
|
|
8004c92: 68fa ldr r2, [r7, #12]
|
|
8004c94: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8004c96: 683b ldr r3, [r7, #0]
|
|
8004c98: 685a ldr r2, [r3, #4]
|
|
8004c9a: 687b ldr r3, [r7, #4]
|
|
8004c9c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004c9e: 687b ldr r3, [r7, #4]
|
|
8004ca0: 697a ldr r2, [r7, #20]
|
|
8004ca2: 621a str r2, [r3, #32]
|
|
}
|
|
8004ca4: bf00 nop
|
|
8004ca6: 371c adds r7, #28
|
|
8004ca8: 46bd mov sp, r7
|
|
8004caa: bc80 pop {r7}
|
|
8004cac: 4770 bx lr
|
|
8004cae: bf00 nop
|
|
8004cb0: 40012c00 .word 0x40012c00
|
|
|
|
08004cb4 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004cb4: b480 push {r7}
|
|
8004cb6: b087 sub sp, #28
|
|
8004cb8: af00 add r7, sp, #0
|
|
8004cba: 6078 str r0, [r7, #4]
|
|
8004cbc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004cbe: 687b ldr r3, [r7, #4]
|
|
8004cc0: 6a1b ldr r3, [r3, #32]
|
|
8004cc2: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8004cc4: 687b ldr r3, [r7, #4]
|
|
8004cc6: 6a1b ldr r3, [r3, #32]
|
|
8004cc8: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8004ccc: 687b ldr r3, [r7, #4]
|
|
8004cce: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004cd0: 687b ldr r3, [r7, #4]
|
|
8004cd2: 685b ldr r3, [r3, #4]
|
|
8004cd4: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004cd6: 687b ldr r3, [r7, #4]
|
|
8004cd8: 69db ldr r3, [r3, #28]
|
|
8004cda: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8004cdc: 68fb ldr r3, [r7, #12]
|
|
8004cde: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8004ce2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8004ce4: 68fb ldr r3, [r7, #12]
|
|
8004ce6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004cea: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8004cec: 683b ldr r3, [r7, #0]
|
|
8004cee: 681b ldr r3, [r3, #0]
|
|
8004cf0: 021b lsls r3, r3, #8
|
|
8004cf2: 68fa ldr r2, [r7, #12]
|
|
8004cf4: 4313 orrs r3, r2
|
|
8004cf6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8004cf8: 693b ldr r3, [r7, #16]
|
|
8004cfa: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004cfe: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8004d00: 683b ldr r3, [r7, #0]
|
|
8004d02: 689b ldr r3, [r3, #8]
|
|
8004d04: 031b lsls r3, r3, #12
|
|
8004d06: 693a ldr r2, [r7, #16]
|
|
8004d08: 4313 orrs r3, r2
|
|
8004d0a: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004d0c: 687b ldr r3, [r7, #4]
|
|
8004d0e: 4a0f ldr r2, [pc, #60] @ (8004d4c <TIM_OC4_SetConfig+0x98>)
|
|
8004d10: 4293 cmp r3, r2
|
|
8004d12: d109 bne.n 8004d28 <TIM_OC4_SetConfig+0x74>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8004d14: 697b ldr r3, [r7, #20]
|
|
8004d16: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8004d1a: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8004d1c: 683b ldr r3, [r7, #0]
|
|
8004d1e: 695b ldr r3, [r3, #20]
|
|
8004d20: 019b lsls r3, r3, #6
|
|
8004d22: 697a ldr r2, [r7, #20]
|
|
8004d24: 4313 orrs r3, r2
|
|
8004d26: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004d28: 687b ldr r3, [r7, #4]
|
|
8004d2a: 697a ldr r2, [r7, #20]
|
|
8004d2c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004d2e: 687b ldr r3, [r7, #4]
|
|
8004d30: 68fa ldr r2, [r7, #12]
|
|
8004d32: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8004d34: 683b ldr r3, [r7, #0]
|
|
8004d36: 685a ldr r2, [r3, #4]
|
|
8004d38: 687b ldr r3, [r7, #4]
|
|
8004d3a: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004d3c: 687b ldr r3, [r7, #4]
|
|
8004d3e: 693a ldr r2, [r7, #16]
|
|
8004d40: 621a str r2, [r3, #32]
|
|
}
|
|
8004d42: bf00 nop
|
|
8004d44: 371c adds r7, #28
|
|
8004d46: 46bd mov sp, r7
|
|
8004d48: bc80 pop {r7}
|
|
8004d4a: 4770 bx lr
|
|
8004d4c: 40012c00 .word 0x40012c00
|
|
|
|
08004d50 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8004d50: b480 push {r7}
|
|
8004d52: b087 sub sp, #28
|
|
8004d54: af00 add r7, sp, #0
|
|
8004d56: 60f8 str r0, [r7, #12]
|
|
8004d58: 60b9 str r1, [r7, #8]
|
|
8004d5a: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8004d5c: 68fb ldr r3, [r7, #12]
|
|
8004d5e: 6a1b ldr r3, [r3, #32]
|
|
8004d60: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8004d62: 68fb ldr r3, [r7, #12]
|
|
8004d64: 6a1b ldr r3, [r3, #32]
|
|
8004d66: f023 0201 bic.w r2, r3, #1
|
|
8004d6a: 68fb ldr r3, [r7, #12]
|
|
8004d6c: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8004d6e: 68fb ldr r3, [r7, #12]
|
|
8004d70: 699b ldr r3, [r3, #24]
|
|
8004d72: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
8004d74: 693b ldr r3, [r7, #16]
|
|
8004d76: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
8004d7a: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8004d7c: 687b ldr r3, [r7, #4]
|
|
8004d7e: 011b lsls r3, r3, #4
|
|
8004d80: 693a ldr r2, [r7, #16]
|
|
8004d82: 4313 orrs r3, r2
|
|
8004d84: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
8004d86: 697b ldr r3, [r7, #20]
|
|
8004d88: f023 030a bic.w r3, r3, #10
|
|
8004d8c: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
8004d8e: 697a ldr r2, [r7, #20]
|
|
8004d90: 68bb ldr r3, [r7, #8]
|
|
8004d92: 4313 orrs r3, r2
|
|
8004d94: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
8004d96: 68fb ldr r3, [r7, #12]
|
|
8004d98: 693a ldr r2, [r7, #16]
|
|
8004d9a: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8004d9c: 68fb ldr r3, [r7, #12]
|
|
8004d9e: 697a ldr r2, [r7, #20]
|
|
8004da0: 621a str r2, [r3, #32]
|
|
}
|
|
8004da2: bf00 nop
|
|
8004da4: 371c adds r7, #28
|
|
8004da6: 46bd mov sp, r7
|
|
8004da8: bc80 pop {r7}
|
|
8004daa: 4770 bx lr
|
|
|
|
08004dac <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8004dac: b480 push {r7}
|
|
8004dae: b087 sub sp, #28
|
|
8004db0: af00 add r7, sp, #0
|
|
8004db2: 60f8 str r0, [r7, #12]
|
|
8004db4: 60b9 str r1, [r7, #8]
|
|
8004db6: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8004db8: 68fb ldr r3, [r7, #12]
|
|
8004dba: 6a1b ldr r3, [r3, #32]
|
|
8004dbc: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8004dbe: 68fb ldr r3, [r7, #12]
|
|
8004dc0: 6a1b ldr r3, [r3, #32]
|
|
8004dc2: f023 0210 bic.w r2, r3, #16
|
|
8004dc6: 68fb ldr r3, [r7, #12]
|
|
8004dc8: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8004dca: 68fb ldr r3, [r7, #12]
|
|
8004dcc: 699b ldr r3, [r3, #24]
|
|
8004dce: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
8004dd0: 693b ldr r3, [r7, #16]
|
|
8004dd2: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
8004dd6: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
8004dd8: 687b ldr r3, [r7, #4]
|
|
8004dda: 031b lsls r3, r3, #12
|
|
8004ddc: 693a ldr r2, [r7, #16]
|
|
8004dde: 4313 orrs r3, r2
|
|
8004de0: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
8004de2: 697b ldr r3, [r7, #20]
|
|
8004de4: f023 03a0 bic.w r3, r3, #160 @ 0xa0
|
|
8004de8: 617b str r3, [r7, #20]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8004dea: 68bb ldr r3, [r7, #8]
|
|
8004dec: 011b lsls r3, r3, #4
|
|
8004dee: 697a ldr r2, [r7, #20]
|
|
8004df0: 4313 orrs r3, r2
|
|
8004df2: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
8004df4: 68fb ldr r3, [r7, #12]
|
|
8004df6: 693a ldr r2, [r7, #16]
|
|
8004df8: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8004dfa: 68fb ldr r3, [r7, #12]
|
|
8004dfc: 697a ldr r2, [r7, #20]
|
|
8004dfe: 621a str r2, [r3, #32]
|
|
}
|
|
8004e00: bf00 nop
|
|
8004e02: 371c adds r7, #28
|
|
8004e04: 46bd mov sp, r7
|
|
8004e06: bc80 pop {r7}
|
|
8004e08: 4770 bx lr
|
|
|
|
08004e0a <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
8004e0a: b480 push {r7}
|
|
8004e0c: b085 sub sp, #20
|
|
8004e0e: af00 add r7, sp, #0
|
|
8004e10: 6078 str r0, [r7, #4]
|
|
8004e12: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
8004e14: 687b ldr r3, [r7, #4]
|
|
8004e16: 689b ldr r3, [r3, #8]
|
|
8004e18: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8004e1a: 68fb ldr r3, [r7, #12]
|
|
8004e1c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004e20: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8004e22: 683a ldr r2, [r7, #0]
|
|
8004e24: 68fb ldr r3, [r7, #12]
|
|
8004e26: 4313 orrs r3, r2
|
|
8004e28: f043 0307 orr.w r3, r3, #7
|
|
8004e2c: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8004e2e: 687b ldr r3, [r7, #4]
|
|
8004e30: 68fa ldr r2, [r7, #12]
|
|
8004e32: 609a str r2, [r3, #8]
|
|
}
|
|
8004e34: bf00 nop
|
|
8004e36: 3714 adds r7, #20
|
|
8004e38: 46bd mov sp, r7
|
|
8004e3a: bc80 pop {r7}
|
|
8004e3c: 4770 bx lr
|
|
|
|
08004e3e <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
8004e3e: b480 push {r7}
|
|
8004e40: b087 sub sp, #28
|
|
8004e42: af00 add r7, sp, #0
|
|
8004e44: 60f8 str r0, [r7, #12]
|
|
8004e46: 60b9 str r1, [r7, #8]
|
|
8004e48: 607a str r2, [r7, #4]
|
|
8004e4a: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
8004e4c: 68fb ldr r3, [r7, #12]
|
|
8004e4e: 689b ldr r3, [r3, #8]
|
|
8004e50: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8004e52: 697b ldr r3, [r7, #20]
|
|
8004e54: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
8004e58: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
8004e5a: 683b ldr r3, [r7, #0]
|
|
8004e5c: 021a lsls r2, r3, #8
|
|
8004e5e: 687b ldr r3, [r7, #4]
|
|
8004e60: 431a orrs r2, r3
|
|
8004e62: 68bb ldr r3, [r7, #8]
|
|
8004e64: 4313 orrs r3, r2
|
|
8004e66: 697a ldr r2, [r7, #20]
|
|
8004e68: 4313 orrs r3, r2
|
|
8004e6a: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8004e6c: 68fb ldr r3, [r7, #12]
|
|
8004e6e: 697a ldr r2, [r7, #20]
|
|
8004e70: 609a str r2, [r3, #8]
|
|
}
|
|
8004e72: bf00 nop
|
|
8004e74: 371c adds r7, #28
|
|
8004e76: 46bd mov sp, r7
|
|
8004e78: bc80 pop {r7}
|
|
8004e7a: 4770 bx lr
|
|
|
|
08004e7c <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8004e7c: b480 push {r7}
|
|
8004e7e: b087 sub sp, #28
|
|
8004e80: af00 add r7, sp, #0
|
|
8004e82: 60f8 str r0, [r7, #12]
|
|
8004e84: 60b9 str r1, [r7, #8]
|
|
8004e86: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8004e88: 68bb ldr r3, [r7, #8]
|
|
8004e8a: f003 031f and.w r3, r3, #31
|
|
8004e8e: 2201 movs r2, #1
|
|
8004e90: fa02 f303 lsl.w r3, r2, r3
|
|
8004e94: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8004e96: 68fb ldr r3, [r7, #12]
|
|
8004e98: 6a1a ldr r2, [r3, #32]
|
|
8004e9a: 697b ldr r3, [r7, #20]
|
|
8004e9c: 43db mvns r3, r3
|
|
8004e9e: 401a ands r2, r3
|
|
8004ea0: 68fb ldr r3, [r7, #12]
|
|
8004ea2: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8004ea4: 68fb ldr r3, [r7, #12]
|
|
8004ea6: 6a1a ldr r2, [r3, #32]
|
|
8004ea8: 68bb ldr r3, [r7, #8]
|
|
8004eaa: f003 031f and.w r3, r3, #31
|
|
8004eae: 6879 ldr r1, [r7, #4]
|
|
8004eb0: fa01 f303 lsl.w r3, r1, r3
|
|
8004eb4: 431a orrs r2, r3
|
|
8004eb6: 68fb ldr r3, [r7, #12]
|
|
8004eb8: 621a str r2, [r3, #32]
|
|
}
|
|
8004eba: bf00 nop
|
|
8004ebc: 371c adds r7, #28
|
|
8004ebe: 46bd mov sp, r7
|
|
8004ec0: bc80 pop {r7}
|
|
8004ec2: 4770 bx lr
|
|
|
|
08004ec4 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8004ec4: b480 push {r7}
|
|
8004ec6: b085 sub sp, #20
|
|
8004ec8: af00 add r7, sp, #0
|
|
8004eca: 6078 str r0, [r7, #4]
|
|
8004ecc: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8004ece: 687b ldr r3, [r7, #4]
|
|
8004ed0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004ed4: 2b01 cmp r3, #1
|
|
8004ed6: d101 bne.n 8004edc <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8004ed8: 2302 movs r3, #2
|
|
8004eda: e046 b.n 8004f6a <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
8004edc: 687b ldr r3, [r7, #4]
|
|
8004ede: 2201 movs r2, #1
|
|
8004ee0: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004ee4: 687b ldr r3, [r7, #4]
|
|
8004ee6: 2202 movs r2, #2
|
|
8004ee8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8004eec: 687b ldr r3, [r7, #4]
|
|
8004eee: 681b ldr r3, [r3, #0]
|
|
8004ef0: 685b ldr r3, [r3, #4]
|
|
8004ef2: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004ef4: 687b ldr r3, [r7, #4]
|
|
8004ef6: 681b ldr r3, [r3, #0]
|
|
8004ef8: 689b ldr r3, [r3, #8]
|
|
8004efa: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8004efc: 68fb ldr r3, [r7, #12]
|
|
8004efe: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004f02: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8004f04: 683b ldr r3, [r7, #0]
|
|
8004f06: 681b ldr r3, [r3, #0]
|
|
8004f08: 68fa ldr r2, [r7, #12]
|
|
8004f0a: 4313 orrs r3, r2
|
|
8004f0c: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8004f0e: 687b ldr r3, [r7, #4]
|
|
8004f10: 681b ldr r3, [r3, #0]
|
|
8004f12: 68fa ldr r2, [r7, #12]
|
|
8004f14: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004f16: 687b ldr r3, [r7, #4]
|
|
8004f18: 681b ldr r3, [r3, #0]
|
|
8004f1a: 4a16 ldr r2, [pc, #88] @ (8004f74 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
|
|
8004f1c: 4293 cmp r3, r2
|
|
8004f1e: d00e beq.n 8004f3e <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8004f20: 687b ldr r3, [r7, #4]
|
|
8004f22: 681b ldr r3, [r3, #0]
|
|
8004f24: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8004f28: d009 beq.n 8004f3e <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8004f2a: 687b ldr r3, [r7, #4]
|
|
8004f2c: 681b ldr r3, [r3, #0]
|
|
8004f2e: 4a12 ldr r2, [pc, #72] @ (8004f78 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
|
|
8004f30: 4293 cmp r3, r2
|
|
8004f32: d004 beq.n 8004f3e <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8004f34: 687b ldr r3, [r7, #4]
|
|
8004f36: 681b ldr r3, [r3, #0]
|
|
8004f38: 4a10 ldr r2, [pc, #64] @ (8004f7c <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
8004f3a: 4293 cmp r3, r2
|
|
8004f3c: d10c bne.n 8004f58 <HAL_TIMEx_MasterConfigSynchronization+0x94>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8004f3e: 68bb ldr r3, [r7, #8]
|
|
8004f40: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004f44: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8004f46: 683b ldr r3, [r7, #0]
|
|
8004f48: 685b ldr r3, [r3, #4]
|
|
8004f4a: 68ba ldr r2, [r7, #8]
|
|
8004f4c: 4313 orrs r3, r2
|
|
8004f4e: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004f50: 687b ldr r3, [r7, #4]
|
|
8004f52: 681b ldr r3, [r3, #0]
|
|
8004f54: 68ba ldr r2, [r7, #8]
|
|
8004f56: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004f58: 687b ldr r3, [r7, #4]
|
|
8004f5a: 2201 movs r2, #1
|
|
8004f5c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004f60: 687b ldr r3, [r7, #4]
|
|
8004f62: 2200 movs r2, #0
|
|
8004f64: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8004f68: 2300 movs r3, #0
|
|
}
|
|
8004f6a: 4618 mov r0, r3
|
|
8004f6c: 3714 adds r7, #20
|
|
8004f6e: 46bd mov sp, r7
|
|
8004f70: bc80 pop {r7}
|
|
8004f72: 4770 bx lr
|
|
8004f74: 40012c00 .word 0x40012c00
|
|
8004f78: 40000400 .word 0x40000400
|
|
8004f7c: 40000800 .word 0x40000800
|
|
|
|
08004f80 <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8004f80: b580 push {r7, lr}
|
|
8004f82: b082 sub sp, #8
|
|
8004f84: af00 add r7, sp, #0
|
|
8004f86: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8004f88: 687b ldr r3, [r7, #4]
|
|
8004f8a: 2b00 cmp r3, #0
|
|
8004f8c: d101 bne.n 8004f92 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f8e: 2301 movs r3, #1
|
|
8004f90: e042 b.n 8005018 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
#if defined(USART_CR1_OVER8)
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8004f92: 687b ldr r3, [r7, #4]
|
|
8004f94: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004f98: b2db uxtb r3, r3
|
|
8004f9a: 2b00 cmp r3, #0
|
|
8004f9c: d106 bne.n 8004fac <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8004f9e: 687b ldr r3, [r7, #4]
|
|
8004fa0: 2200 movs r2, #0
|
|
8004fa2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8004fa6: 6878 ldr r0, [r7, #4]
|
|
8004fa8: f7fc f932 bl 8001210 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004fac: 687b ldr r3, [r7, #4]
|
|
8004fae: 2224 movs r2, #36 @ 0x24
|
|
8004fb0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8004fb4: 687b ldr r3, [r7, #4]
|
|
8004fb6: 681b ldr r3, [r3, #0]
|
|
8004fb8: 68da ldr r2, [r3, #12]
|
|
8004fba: 687b ldr r3, [r7, #4]
|
|
8004fbc: 681b ldr r3, [r3, #0]
|
|
8004fbe: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8004fc2: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8004fc4: 6878 ldr r0, [r7, #4]
|
|
8004fc6: f000 f82b bl 8005020 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004fca: 687b ldr r3, [r7, #4]
|
|
8004fcc: 681b ldr r3, [r3, #0]
|
|
8004fce: 691a ldr r2, [r3, #16]
|
|
8004fd0: 687b ldr r3, [r7, #4]
|
|
8004fd2: 681b ldr r3, [r3, #0]
|
|
8004fd4: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8004fd8: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8004fda: 687b ldr r3, [r7, #4]
|
|
8004fdc: 681b ldr r3, [r3, #0]
|
|
8004fde: 695a ldr r2, [r3, #20]
|
|
8004fe0: 687b ldr r3, [r7, #4]
|
|
8004fe2: 681b ldr r3, [r3, #0]
|
|
8004fe4: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8004fe8: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8004fea: 687b ldr r3, [r7, #4]
|
|
8004fec: 681b ldr r3, [r3, #0]
|
|
8004fee: 68da ldr r2, [r3, #12]
|
|
8004ff0: 687b ldr r3, [r7, #4]
|
|
8004ff2: 681b ldr r3, [r3, #0]
|
|
8004ff4: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8004ff8: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004ffa: 687b ldr r3, [r7, #4]
|
|
8004ffc: 2200 movs r2, #0
|
|
8004ffe: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005000: 687b ldr r3, [r7, #4]
|
|
8005002: 2220 movs r2, #32
|
|
8005004: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005008: 687b ldr r3, [r7, #4]
|
|
800500a: 2220 movs r2, #32
|
|
800500c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005010: 687b ldr r3, [r7, #4]
|
|
8005012: 2200 movs r2, #0
|
|
8005014: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8005016: 2300 movs r3, #0
|
|
}
|
|
8005018: 4618 mov r0, r3
|
|
800501a: 3708 adds r7, #8
|
|
800501c: 46bd mov sp, r7
|
|
800501e: bd80 pop {r7, pc}
|
|
|
|
08005020 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005020: b580 push {r7, lr}
|
|
8005022: b084 sub sp, #16
|
|
8005024: af00 add r7, sp, #0
|
|
8005026: 6078 str r0, [r7, #4]
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8005028: 687b ldr r3, [r7, #4]
|
|
800502a: 681b ldr r3, [r3, #0]
|
|
800502c: 691b ldr r3, [r3, #16]
|
|
800502e: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
8005032: 687b ldr r3, [r7, #4]
|
|
8005034: 68da ldr r2, [r3, #12]
|
|
8005036: 687b ldr r3, [r7, #4]
|
|
8005038: 681b ldr r3, [r3, #0]
|
|
800503a: 430a orrs r2, r1
|
|
800503c: 611a str r2, [r3, #16]
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
#else
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
|
|
800503e: 687b ldr r3, [r7, #4]
|
|
8005040: 689a ldr r2, [r3, #8]
|
|
8005042: 687b ldr r3, [r7, #4]
|
|
8005044: 691b ldr r3, [r3, #16]
|
|
8005046: 431a orrs r2, r3
|
|
8005048: 687b ldr r3, [r7, #4]
|
|
800504a: 695b ldr r3, [r3, #20]
|
|
800504c: 4313 orrs r3, r2
|
|
800504e: 60bb str r3, [r7, #8]
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
8005050: 687b ldr r3, [r7, #4]
|
|
8005052: 681b ldr r3, [r3, #0]
|
|
8005054: 68db ldr r3, [r3, #12]
|
|
8005056: f423 53b0 bic.w r3, r3, #5632 @ 0x1600
|
|
800505a: f023 030c bic.w r3, r3, #12
|
|
800505e: 687a ldr r2, [r7, #4]
|
|
8005060: 6812 ldr r2, [r2, #0]
|
|
8005062: 68b9 ldr r1, [r7, #8]
|
|
8005064: 430b orrs r3, r1
|
|
8005066: 60d3 str r3, [r2, #12]
|
|
tmpreg);
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8005068: 687b ldr r3, [r7, #4]
|
|
800506a: 681b ldr r3, [r3, #0]
|
|
800506c: 695b ldr r3, [r3, #20]
|
|
800506e: f423 7140 bic.w r1, r3, #768 @ 0x300
|
|
8005072: 687b ldr r3, [r7, #4]
|
|
8005074: 699a ldr r2, [r3, #24]
|
|
8005076: 687b ldr r3, [r7, #4]
|
|
8005078: 681b ldr r3, [r3, #0]
|
|
800507a: 430a orrs r2, r1
|
|
800507c: 615a str r2, [r3, #20]
|
|
|
|
|
|
if(huart->Instance == USART1)
|
|
800507e: 687b ldr r3, [r7, #4]
|
|
8005080: 681b ldr r3, [r3, #0]
|
|
8005082: 4a2c ldr r2, [pc, #176] @ (8005134 <UART_SetConfig+0x114>)
|
|
8005084: 4293 cmp r3, r2
|
|
8005086: d103 bne.n 8005090 <UART_SetConfig+0x70>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005088: f7ff f824 bl 80040d4 <HAL_RCC_GetPCLK2Freq>
|
|
800508c: 60f8 str r0, [r7, #12]
|
|
800508e: e002 b.n 8005096 <UART_SetConfig+0x76>
|
|
}
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005090: f7ff f80c bl 80040ac <HAL_RCC_GetPCLK1Freq>
|
|
8005094: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
#else
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8005096: 68fa ldr r2, [r7, #12]
|
|
8005098: 4613 mov r3, r2
|
|
800509a: 009b lsls r3, r3, #2
|
|
800509c: 4413 add r3, r2
|
|
800509e: 009a lsls r2, r3, #2
|
|
80050a0: 441a add r2, r3
|
|
80050a2: 687b ldr r3, [r7, #4]
|
|
80050a4: 685b ldr r3, [r3, #4]
|
|
80050a6: 009b lsls r3, r3, #2
|
|
80050a8: fbb2 f3f3 udiv r3, r2, r3
|
|
80050ac: 4a22 ldr r2, [pc, #136] @ (8005138 <UART_SetConfig+0x118>)
|
|
80050ae: fba2 2303 umull r2, r3, r2, r3
|
|
80050b2: 095b lsrs r3, r3, #5
|
|
80050b4: 0119 lsls r1, r3, #4
|
|
80050b6: 68fa ldr r2, [r7, #12]
|
|
80050b8: 4613 mov r3, r2
|
|
80050ba: 009b lsls r3, r3, #2
|
|
80050bc: 4413 add r3, r2
|
|
80050be: 009a lsls r2, r3, #2
|
|
80050c0: 441a add r2, r3
|
|
80050c2: 687b ldr r3, [r7, #4]
|
|
80050c4: 685b ldr r3, [r3, #4]
|
|
80050c6: 009b lsls r3, r3, #2
|
|
80050c8: fbb2 f2f3 udiv r2, r2, r3
|
|
80050cc: 4b1a ldr r3, [pc, #104] @ (8005138 <UART_SetConfig+0x118>)
|
|
80050ce: fba3 0302 umull r0, r3, r3, r2
|
|
80050d2: 095b lsrs r3, r3, #5
|
|
80050d4: 2064 movs r0, #100 @ 0x64
|
|
80050d6: fb00 f303 mul.w r3, r0, r3
|
|
80050da: 1ad3 subs r3, r2, r3
|
|
80050dc: 011b lsls r3, r3, #4
|
|
80050de: 3332 adds r3, #50 @ 0x32
|
|
80050e0: 4a15 ldr r2, [pc, #84] @ (8005138 <UART_SetConfig+0x118>)
|
|
80050e2: fba2 2303 umull r2, r3, r2, r3
|
|
80050e6: 095b lsrs r3, r3, #5
|
|
80050e8: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80050ec: 4419 add r1, r3
|
|
80050ee: 68fa ldr r2, [r7, #12]
|
|
80050f0: 4613 mov r3, r2
|
|
80050f2: 009b lsls r3, r3, #2
|
|
80050f4: 4413 add r3, r2
|
|
80050f6: 009a lsls r2, r3, #2
|
|
80050f8: 441a add r2, r3
|
|
80050fa: 687b ldr r3, [r7, #4]
|
|
80050fc: 685b ldr r3, [r3, #4]
|
|
80050fe: 009b lsls r3, r3, #2
|
|
8005100: fbb2 f2f3 udiv r2, r2, r3
|
|
8005104: 4b0c ldr r3, [pc, #48] @ (8005138 <UART_SetConfig+0x118>)
|
|
8005106: fba3 0302 umull r0, r3, r3, r2
|
|
800510a: 095b lsrs r3, r3, #5
|
|
800510c: 2064 movs r0, #100 @ 0x64
|
|
800510e: fb00 f303 mul.w r3, r0, r3
|
|
8005112: 1ad3 subs r3, r2, r3
|
|
8005114: 011b lsls r3, r3, #4
|
|
8005116: 3332 adds r3, #50 @ 0x32
|
|
8005118: 4a07 ldr r2, [pc, #28] @ (8005138 <UART_SetConfig+0x118>)
|
|
800511a: fba2 2303 umull r2, r3, r2, r3
|
|
800511e: 095b lsrs r3, r3, #5
|
|
8005120: f003 020f and.w r2, r3, #15
|
|
8005124: 687b ldr r3, [r7, #4]
|
|
8005126: 681b ldr r3, [r3, #0]
|
|
8005128: 440a add r2, r1
|
|
800512a: 609a str r2, [r3, #8]
|
|
#endif /* USART_CR1_OVER8 */
|
|
}
|
|
800512c: bf00 nop
|
|
800512e: 3710 adds r7, #16
|
|
8005130: 46bd mov sp, r7
|
|
8005132: bd80 pop {r7, pc}
|
|
8005134: 40013800 .word 0x40013800
|
|
8005138: 51eb851f .word 0x51eb851f
|
|
|
|
0800513c <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
|
|
{
|
|
800513c: b480 push {r7}
|
|
800513e: b085 sub sp, #20
|
|
8005140: af00 add r7, sp, #0
|
|
8005142: 60f8 str r0, [r7, #12]
|
|
8005144: 4638 mov r0, r7
|
|
8005146: e880 000e stmia.w r0, {r1, r2, r3}
|
|
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
|
only by USB OTG FS peripheral.
|
|
- This function is added to ensure compatibility across platforms.
|
|
*/
|
|
|
|
return HAL_OK;
|
|
800514a: 2300 movs r3, #0
|
|
}
|
|
800514c: 4618 mov r0, r3
|
|
800514e: 3714 adds r7, #20
|
|
8005150: 46bd mov sp, r7
|
|
8005152: bc80 pop {r7}
|
|
8005154: 4770 bx lr
|
|
|
|
08005156 <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
|
|
{
|
|
8005156: b480 push {r7}
|
|
8005158: b085 sub sp, #20
|
|
800515a: af00 add r7, sp, #0
|
|
800515c: 6078 str r0, [r7, #4]
|
|
uint32_t winterruptmask;
|
|
|
|
/* Clear pending interrupts */
|
|
USBx->ISTR = 0U;
|
|
800515e: 687b ldr r3, [r7, #4]
|
|
8005160: 2200 movs r2, #0
|
|
8005162: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
/* Set winterruptmask variable */
|
|
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
|
|
8005166: f44f 433f mov.w r3, #48896 @ 0xbf00
|
|
800516a: 60fb str r3, [r7, #12]
|
|
USB_CNTR_SUSPM | USB_CNTR_ERRM |
|
|
USB_CNTR_SOFM | USB_CNTR_ESOFM |
|
|
USB_CNTR_RESETM;
|
|
|
|
/* Set interrupt mask */
|
|
USBx->CNTR = (uint16_t)winterruptmask;
|
|
800516c: 68fb ldr r3, [r7, #12]
|
|
800516e: b29a uxth r2, r3
|
|
8005170: 687b ldr r3, [r7, #4]
|
|
8005172: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8005176: 2300 movs r3, #0
|
|
}
|
|
8005178: 4618 mov r0, r3
|
|
800517a: 3714 adds r7, #20
|
|
800517c: 46bd mov sp, r7
|
|
800517e: bc80 pop {r7}
|
|
8005180: 4770 bx lr
|
|
|
|
08005182 <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
|
|
{
|
|
8005182: b480 push {r7}
|
|
8005184: b085 sub sp, #20
|
|
8005186: af00 add r7, sp, #0
|
|
8005188: 6078 str r0, [r7, #4]
|
|
uint32_t winterruptmask;
|
|
|
|
/* Set winterruptmask variable */
|
|
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
|
|
800518a: f44f 433f mov.w r3, #48896 @ 0xbf00
|
|
800518e: 60fb str r3, [r7, #12]
|
|
USB_CNTR_SUSPM | USB_CNTR_ERRM |
|
|
USB_CNTR_SOFM | USB_CNTR_ESOFM |
|
|
USB_CNTR_RESETM;
|
|
|
|
/* Clear interrupt mask */
|
|
USBx->CNTR &= (uint16_t)(~winterruptmask);
|
|
8005190: 687b ldr r3, [r7, #4]
|
|
8005192: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8005196: b29a uxth r2, r3
|
|
8005198: 68fb ldr r3, [r7, #12]
|
|
800519a: b29b uxth r3, r3
|
|
800519c: 43db mvns r3, r3
|
|
800519e: b29b uxth r3, r3
|
|
80051a0: 4013 ands r3, r2
|
|
80051a2: b29a uxth r2, r3
|
|
80051a4: 687b ldr r3, [r7, #4]
|
|
80051a6: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
80051aa: 2300 movs r3, #0
|
|
}
|
|
80051ac: 4618 mov r0, r3
|
|
80051ae: 3714 adds r7, #20
|
|
80051b0: 46bd mov sp, r7
|
|
80051b2: bc80 pop {r7}
|
|
80051b4: 4770 bx lr
|
|
|
|
080051b6 <USB_SetCurrentMode>:
|
|
* This parameter can be one of the these values:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
|
|
{
|
|
80051b6: b480 push {r7}
|
|
80051b8: b083 sub sp, #12
|
|
80051ba: af00 add r7, sp, #0
|
|
80051bc: 6078 str r0, [r7, #4]
|
|
80051be: 460b mov r3, r1
|
|
80051c0: 70fb strb r3, [r7, #3]
|
|
|
|
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
|
only by USB OTG FS peripheral.
|
|
- This function is added to ensure compatibility across platforms.
|
|
*/
|
|
return HAL_OK;
|
|
80051c2: 2300 movs r3, #0
|
|
}
|
|
80051c4: 4618 mov r0, r3
|
|
80051c6: 370c adds r7, #12
|
|
80051c8: 46bd mov sp, r7
|
|
80051ca: bc80 pop {r7}
|
|
80051cc: 4770 bx lr
|
|
|
|
080051ce <USB_DevInit>:
|
|
* @param cfg pointer to a USB_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
|
|
{
|
|
80051ce: b480 push {r7}
|
|
80051d0: b085 sub sp, #20
|
|
80051d2: af00 add r7, sp, #0
|
|
80051d4: 60f8 str r0, [r7, #12]
|
|
80051d6: 4638 mov r0, r7
|
|
80051d8: e880 000e stmia.w r0, {r1, r2, r3}
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(cfg);
|
|
|
|
/* Init Device */
|
|
/* CNTR_FRES = 1 */
|
|
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
|
|
80051dc: 68fb ldr r3, [r7, #12]
|
|
80051de: 2201 movs r2, #1
|
|
80051e0: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* CNTR_FRES = 0 */
|
|
USBx->CNTR = 0U;
|
|
80051e4: 68fb ldr r3, [r7, #12]
|
|
80051e6: 2200 movs r2, #0
|
|
80051e8: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Clear pending interrupts */
|
|
USBx->ISTR = 0U;
|
|
80051ec: 68fb ldr r3, [r7, #12]
|
|
80051ee: 2200 movs r2, #0
|
|
80051f0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
/*Set Btable Address*/
|
|
USBx->BTABLE = BTABLE_ADDRESS;
|
|
80051f4: 68fb ldr r3, [r7, #12]
|
|
80051f6: 2200 movs r2, #0
|
|
80051f8: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
|
|
|
|
return HAL_OK;
|
|
80051fc: 2300 movs r3, #0
|
|
}
|
|
80051fe: 4618 mov r0, r3
|
|
8005200: 3714 adds r7, #20
|
|
8005202: 46bd mov sp, r7
|
|
8005204: bc80 pop {r7}
|
|
8005206: 4770 bx lr
|
|
|
|
08005208 <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8005208: b480 push {r7}
|
|
800520a: b09d sub sp, #116 @ 0x74
|
|
800520c: af00 add r7, sp, #0
|
|
800520e: 6078 str r0, [r7, #4]
|
|
8005210: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8005212: 2300 movs r3, #0
|
|
8005214: f887 306f strb.w r3, [r7, #111] @ 0x6f
|
|
uint16_t wEpRegVal;
|
|
|
|
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
|
|
8005218: 687a ldr r2, [r7, #4]
|
|
800521a: 683b ldr r3, [r7, #0]
|
|
800521c: 781b ldrb r3, [r3, #0]
|
|
800521e: 009b lsls r3, r3, #2
|
|
8005220: 4413 add r3, r2
|
|
8005222: 881b ldrh r3, [r3, #0]
|
|
8005224: b29b uxth r3, r3
|
|
8005226: f423 43ec bic.w r3, r3, #30208 @ 0x7600
|
|
800522a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800522e: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
|
|
/* initialize Endpoint */
|
|
switch (ep->type)
|
|
8005232: 683b ldr r3, [r7, #0]
|
|
8005234: 78db ldrb r3, [r3, #3]
|
|
8005236: 2b03 cmp r3, #3
|
|
8005238: d81f bhi.n 800527a <USB_ActivateEndpoint+0x72>
|
|
800523a: a201 add r2, pc, #4 @ (adr r2, 8005240 <USB_ActivateEndpoint+0x38>)
|
|
800523c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005240: 08005251 .word 0x08005251
|
|
8005244: 0800526d .word 0x0800526d
|
|
8005248: 08005283 .word 0x08005283
|
|
800524c: 0800525f .word 0x0800525f
|
|
{
|
|
case EP_TYPE_CTRL:
|
|
wEpRegVal |= USB_EP_CONTROL;
|
|
8005250: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
8005254: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8005258: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
break;
|
|
800525c: e012 b.n 8005284 <USB_ActivateEndpoint+0x7c>
|
|
case EP_TYPE_BULK:
|
|
wEpRegVal |= USB_EP_BULK;
|
|
break;
|
|
|
|
case EP_TYPE_INTR:
|
|
wEpRegVal |= USB_EP_INTERRUPT;
|
|
800525e: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
8005262: f443 63c0 orr.w r3, r3, #1536 @ 0x600
|
|
8005266: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
break;
|
|
800526a: e00b b.n 8005284 <USB_ActivateEndpoint+0x7c>
|
|
|
|
case EP_TYPE_ISOC:
|
|
wEpRegVal |= USB_EP_ISOCHRONOUS;
|
|
800526c: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
8005270: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8005274: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
break;
|
|
8005278: e004 b.n 8005284 <USB_ActivateEndpoint+0x7c>
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800527a: 2301 movs r3, #1
|
|
800527c: f887 306f strb.w r3, [r7, #111] @ 0x6f
|
|
break;
|
|
8005280: e000 b.n 8005284 <USB_ActivateEndpoint+0x7c>
|
|
break;
|
|
8005282: bf00 nop
|
|
}
|
|
|
|
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
|
|
8005284: 687a ldr r2, [r7, #4]
|
|
8005286: 683b ldr r3, [r7, #0]
|
|
8005288: 781b ldrb r3, [r3, #0]
|
|
800528a: 009b lsls r3, r3, #2
|
|
800528c: 441a add r2, r3
|
|
800528e: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
8005292: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005296: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800529a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800529e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80052a2: b29b uxth r3, r3
|
|
80052a4: 8013 strh r3, [r2, #0]
|
|
|
|
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
|
|
80052a6: 687a ldr r2, [r7, #4]
|
|
80052a8: 683b ldr r3, [r7, #0]
|
|
80052aa: 781b ldrb r3, [r3, #0]
|
|
80052ac: 009b lsls r3, r3, #2
|
|
80052ae: 4413 add r3, r2
|
|
80052b0: 881b ldrh r3, [r3, #0]
|
|
80052b2: b29b uxth r3, r3
|
|
80052b4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80052b8: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80052bc: b29b uxth r3, r3
|
|
80052be: 683a ldr r2, [r7, #0]
|
|
80052c0: 7812 ldrb r2, [r2, #0]
|
|
80052c2: 4313 orrs r3, r2
|
|
80052c4: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
|
|
80052c8: 687a ldr r2, [r7, #4]
|
|
80052ca: 683b ldr r3, [r7, #0]
|
|
80052cc: 781b ldrb r3, [r3, #0]
|
|
80052ce: 009b lsls r3, r3, #2
|
|
80052d0: 441a add r2, r3
|
|
80052d2: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
|
|
80052d6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80052da: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80052de: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80052e2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80052e6: b29b uxth r3, r3
|
|
80052e8: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->doublebuffer == 0U)
|
|
80052ea: 683b ldr r3, [r7, #0]
|
|
80052ec: 7b1b ldrb r3, [r3, #12]
|
|
80052ee: 2b00 cmp r3, #0
|
|
80052f0: f040 8178 bne.w 80055e4 <USB_ActivateEndpoint+0x3dc>
|
|
{
|
|
if (ep->is_in != 0U)
|
|
80052f4: 683b ldr r3, [r7, #0]
|
|
80052f6: 785b ldrb r3, [r3, #1]
|
|
80052f8: 2b00 cmp r3, #0
|
|
80052fa: f000 8084 beq.w 8005406 <USB_ActivateEndpoint+0x1fe>
|
|
{
|
|
/*Set the endpoint Transmit buffer address */
|
|
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
|
|
80052fe: 687b ldr r3, [r7, #4]
|
|
8005300: 61bb str r3, [r7, #24]
|
|
8005302: 687b ldr r3, [r7, #4]
|
|
8005304: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8005308: b29b uxth r3, r3
|
|
800530a: 461a mov r2, r3
|
|
800530c: 69bb ldr r3, [r7, #24]
|
|
800530e: 4413 add r3, r2
|
|
8005310: 61bb str r3, [r7, #24]
|
|
8005312: 683b ldr r3, [r7, #0]
|
|
8005314: 781b ldrb r3, [r3, #0]
|
|
8005316: 011a lsls r2, r3, #4
|
|
8005318: 69bb ldr r3, [r7, #24]
|
|
800531a: 4413 add r3, r2
|
|
800531c: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8005320: 617b str r3, [r7, #20]
|
|
8005322: 683b ldr r3, [r7, #0]
|
|
8005324: 88db ldrh r3, [r3, #6]
|
|
8005326: 085b lsrs r3, r3, #1
|
|
8005328: b29b uxth r3, r3
|
|
800532a: 005b lsls r3, r3, #1
|
|
800532c: b29a uxth r2, r3
|
|
800532e: 697b ldr r3, [r7, #20]
|
|
8005330: 801a strh r2, [r3, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
8005332: 687a ldr r2, [r7, #4]
|
|
8005334: 683b ldr r3, [r7, #0]
|
|
8005336: 781b ldrb r3, [r3, #0]
|
|
8005338: 009b lsls r3, r3, #2
|
|
800533a: 4413 add r3, r2
|
|
800533c: 881b ldrh r3, [r3, #0]
|
|
800533e: 827b strh r3, [r7, #18]
|
|
8005340: 8a7b ldrh r3, [r7, #18]
|
|
8005342: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005346: 2b00 cmp r3, #0
|
|
8005348: d01b beq.n 8005382 <USB_ActivateEndpoint+0x17a>
|
|
800534a: 687a ldr r2, [r7, #4]
|
|
800534c: 683b ldr r3, [r7, #0]
|
|
800534e: 781b ldrb r3, [r3, #0]
|
|
8005350: 009b lsls r3, r3, #2
|
|
8005352: 4413 add r3, r2
|
|
8005354: 881b ldrh r3, [r3, #0]
|
|
8005356: b29b uxth r3, r3
|
|
8005358: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800535c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005360: 823b strh r3, [r7, #16]
|
|
8005362: 687a ldr r2, [r7, #4]
|
|
8005364: 683b ldr r3, [r7, #0]
|
|
8005366: 781b ldrb r3, [r3, #0]
|
|
8005368: 009b lsls r3, r3, #2
|
|
800536a: 441a add r2, r3
|
|
800536c: 8a3b ldrh r3, [r7, #16]
|
|
800536e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005372: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005376: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800537a: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800537e: b29b uxth r3, r3
|
|
8005380: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
8005382: 683b ldr r3, [r7, #0]
|
|
8005384: 78db ldrb r3, [r3, #3]
|
|
8005386: 2b01 cmp r3, #1
|
|
8005388: d020 beq.n 80053cc <USB_ActivateEndpoint+0x1c4>
|
|
{
|
|
/* Configure NAK status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
|
800538a: 687a ldr r2, [r7, #4]
|
|
800538c: 683b ldr r3, [r7, #0]
|
|
800538e: 781b ldrb r3, [r3, #0]
|
|
8005390: 009b lsls r3, r3, #2
|
|
8005392: 4413 add r3, r2
|
|
8005394: 881b ldrh r3, [r3, #0]
|
|
8005396: b29b uxth r3, r3
|
|
8005398: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800539c: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80053a0: 81bb strh r3, [r7, #12]
|
|
80053a2: 89bb ldrh r3, [r7, #12]
|
|
80053a4: f083 0320 eor.w r3, r3, #32
|
|
80053a8: 81bb strh r3, [r7, #12]
|
|
80053aa: 687a ldr r2, [r7, #4]
|
|
80053ac: 683b ldr r3, [r7, #0]
|
|
80053ae: 781b ldrb r3, [r3, #0]
|
|
80053b0: 009b lsls r3, r3, #2
|
|
80053b2: 441a add r2, r3
|
|
80053b4: 89bb ldrh r3, [r7, #12]
|
|
80053b6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80053ba: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80053be: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80053c2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80053c6: b29b uxth r3, r3
|
|
80053c8: 8013 strh r3, [r2, #0]
|
|
80053ca: e2d5 b.n 8005978 <USB_ActivateEndpoint+0x770>
|
|
}
|
|
else
|
|
{
|
|
/* Configure TX Endpoint to disabled state */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
80053cc: 687a ldr r2, [r7, #4]
|
|
80053ce: 683b ldr r3, [r7, #0]
|
|
80053d0: 781b ldrb r3, [r3, #0]
|
|
80053d2: 009b lsls r3, r3, #2
|
|
80053d4: 4413 add r3, r2
|
|
80053d6: 881b ldrh r3, [r3, #0]
|
|
80053d8: b29b uxth r3, r3
|
|
80053da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80053de: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80053e2: 81fb strh r3, [r7, #14]
|
|
80053e4: 687a ldr r2, [r7, #4]
|
|
80053e6: 683b ldr r3, [r7, #0]
|
|
80053e8: 781b ldrb r3, [r3, #0]
|
|
80053ea: 009b lsls r3, r3, #2
|
|
80053ec: 441a add r2, r3
|
|
80053ee: 89fb ldrh r3, [r7, #14]
|
|
80053f0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80053f4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80053f8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80053fc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005400: b29b uxth r3, r3
|
|
8005402: 8013 strh r3, [r2, #0]
|
|
8005404: e2b8 b.n 8005978 <USB_ActivateEndpoint+0x770>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the endpoint Receive buffer address */
|
|
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
|
|
8005406: 687b ldr r3, [r7, #4]
|
|
8005408: 633b str r3, [r7, #48] @ 0x30
|
|
800540a: 687b ldr r3, [r7, #4]
|
|
800540c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8005410: b29b uxth r3, r3
|
|
8005412: 461a mov r2, r3
|
|
8005414: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8005416: 4413 add r3, r2
|
|
8005418: 633b str r3, [r7, #48] @ 0x30
|
|
800541a: 683b ldr r3, [r7, #0]
|
|
800541c: 781b ldrb r3, [r3, #0]
|
|
800541e: 011a lsls r2, r3, #4
|
|
8005420: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8005422: 4413 add r3, r2
|
|
8005424: f503 6381 add.w r3, r3, #1032 @ 0x408
|
|
8005428: 62fb str r3, [r7, #44] @ 0x2c
|
|
800542a: 683b ldr r3, [r7, #0]
|
|
800542c: 88db ldrh r3, [r3, #6]
|
|
800542e: 085b lsrs r3, r3, #1
|
|
8005430: b29b uxth r3, r3
|
|
8005432: 005b lsls r3, r3, #1
|
|
8005434: b29a uxth r2, r3
|
|
8005436: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8005438: 801a strh r2, [r3, #0]
|
|
|
|
/* Set the endpoint Receive buffer counter */
|
|
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
|
|
800543a: 687b ldr r3, [r7, #4]
|
|
800543c: 62bb str r3, [r7, #40] @ 0x28
|
|
800543e: 687b ldr r3, [r7, #4]
|
|
8005440: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8005444: b29b uxth r3, r3
|
|
8005446: 461a mov r2, r3
|
|
8005448: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800544a: 4413 add r3, r2
|
|
800544c: 62bb str r3, [r7, #40] @ 0x28
|
|
800544e: 683b ldr r3, [r7, #0]
|
|
8005450: 781b ldrb r3, [r3, #0]
|
|
8005452: 011a lsls r2, r3, #4
|
|
8005454: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005456: 4413 add r3, r2
|
|
8005458: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
800545c: 627b str r3, [r7, #36] @ 0x24
|
|
800545e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005460: 881b ldrh r3, [r3, #0]
|
|
8005462: b29b uxth r3, r3
|
|
8005464: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8005468: b29a uxth r2, r3
|
|
800546a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800546c: 801a strh r2, [r3, #0]
|
|
800546e: 683b ldr r3, [r7, #0]
|
|
8005470: 691b ldr r3, [r3, #16]
|
|
8005472: 2b3e cmp r3, #62 @ 0x3e
|
|
8005474: d91d bls.n 80054b2 <USB_ActivateEndpoint+0x2aa>
|
|
8005476: 683b ldr r3, [r7, #0]
|
|
8005478: 691b ldr r3, [r3, #16]
|
|
800547a: 095b lsrs r3, r3, #5
|
|
800547c: 66bb str r3, [r7, #104] @ 0x68
|
|
800547e: 683b ldr r3, [r7, #0]
|
|
8005480: 691b ldr r3, [r3, #16]
|
|
8005482: f003 031f and.w r3, r3, #31
|
|
8005486: 2b00 cmp r3, #0
|
|
8005488: d102 bne.n 8005490 <USB_ActivateEndpoint+0x288>
|
|
800548a: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800548c: 3b01 subs r3, #1
|
|
800548e: 66bb str r3, [r7, #104] @ 0x68
|
|
8005490: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005492: 881b ldrh r3, [r3, #0]
|
|
8005494: b29a uxth r2, r3
|
|
8005496: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8005498: b29b uxth r3, r3
|
|
800549a: 029b lsls r3, r3, #10
|
|
800549c: b29b uxth r3, r3
|
|
800549e: 4313 orrs r3, r2
|
|
80054a0: b29b uxth r3, r3
|
|
80054a2: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80054a6: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80054aa: b29a uxth r2, r3
|
|
80054ac: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80054ae: 801a strh r2, [r3, #0]
|
|
80054b0: e026 b.n 8005500 <USB_ActivateEndpoint+0x2f8>
|
|
80054b2: 683b ldr r3, [r7, #0]
|
|
80054b4: 691b ldr r3, [r3, #16]
|
|
80054b6: 2b00 cmp r3, #0
|
|
80054b8: d10a bne.n 80054d0 <USB_ActivateEndpoint+0x2c8>
|
|
80054ba: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80054bc: 881b ldrh r3, [r3, #0]
|
|
80054be: b29b uxth r3, r3
|
|
80054c0: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80054c4: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80054c8: b29a uxth r2, r3
|
|
80054ca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80054cc: 801a strh r2, [r3, #0]
|
|
80054ce: e017 b.n 8005500 <USB_ActivateEndpoint+0x2f8>
|
|
80054d0: 683b ldr r3, [r7, #0]
|
|
80054d2: 691b ldr r3, [r3, #16]
|
|
80054d4: 085b lsrs r3, r3, #1
|
|
80054d6: 66bb str r3, [r7, #104] @ 0x68
|
|
80054d8: 683b ldr r3, [r7, #0]
|
|
80054da: 691b ldr r3, [r3, #16]
|
|
80054dc: f003 0301 and.w r3, r3, #1
|
|
80054e0: 2b00 cmp r3, #0
|
|
80054e2: d002 beq.n 80054ea <USB_ActivateEndpoint+0x2e2>
|
|
80054e4: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80054e6: 3301 adds r3, #1
|
|
80054e8: 66bb str r3, [r7, #104] @ 0x68
|
|
80054ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80054ec: 881b ldrh r3, [r3, #0]
|
|
80054ee: b29a uxth r2, r3
|
|
80054f0: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80054f2: b29b uxth r3, r3
|
|
80054f4: 029b lsls r3, r3, #10
|
|
80054f6: b29b uxth r3, r3
|
|
80054f8: 4313 orrs r3, r2
|
|
80054fa: b29a uxth r2, r3
|
|
80054fc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80054fe: 801a strh r2, [r3, #0]
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
8005500: 687a ldr r2, [r7, #4]
|
|
8005502: 683b ldr r3, [r7, #0]
|
|
8005504: 781b ldrb r3, [r3, #0]
|
|
8005506: 009b lsls r3, r3, #2
|
|
8005508: 4413 add r3, r2
|
|
800550a: 881b ldrh r3, [r3, #0]
|
|
800550c: 847b strh r3, [r7, #34] @ 0x22
|
|
800550e: 8c7b ldrh r3, [r7, #34] @ 0x22
|
|
8005510: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8005514: 2b00 cmp r3, #0
|
|
8005516: d01b beq.n 8005550 <USB_ActivateEndpoint+0x348>
|
|
8005518: 687a ldr r2, [r7, #4]
|
|
800551a: 683b ldr r3, [r7, #0]
|
|
800551c: 781b ldrb r3, [r3, #0]
|
|
800551e: 009b lsls r3, r3, #2
|
|
8005520: 4413 add r3, r2
|
|
8005522: 881b ldrh r3, [r3, #0]
|
|
8005524: b29b uxth r3, r3
|
|
8005526: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800552a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800552e: 843b strh r3, [r7, #32]
|
|
8005530: 687a ldr r2, [r7, #4]
|
|
8005532: 683b ldr r3, [r7, #0]
|
|
8005534: 781b ldrb r3, [r3, #0]
|
|
8005536: 009b lsls r3, r3, #2
|
|
8005538: 441a add r2, r3
|
|
800553a: 8c3b ldrh r3, [r7, #32]
|
|
800553c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005540: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005544: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8005548: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800554c: b29b uxth r3, r3
|
|
800554e: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->num == 0U)
|
|
8005550: 683b ldr r3, [r7, #0]
|
|
8005552: 781b ldrb r3, [r3, #0]
|
|
8005554: 2b00 cmp r3, #0
|
|
8005556: d124 bne.n 80055a2 <USB_ActivateEndpoint+0x39a>
|
|
{
|
|
/* Configure VALID status for EP0 */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
8005558: 687a ldr r2, [r7, #4]
|
|
800555a: 683b ldr r3, [r7, #0]
|
|
800555c: 781b ldrb r3, [r3, #0]
|
|
800555e: 009b lsls r3, r3, #2
|
|
8005560: 4413 add r3, r2
|
|
8005562: 881b ldrh r3, [r3, #0]
|
|
8005564: b29b uxth r3, r3
|
|
8005566: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800556a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800556e: 83bb strh r3, [r7, #28]
|
|
8005570: 8bbb ldrh r3, [r7, #28]
|
|
8005572: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8005576: 83bb strh r3, [r7, #28]
|
|
8005578: 8bbb ldrh r3, [r7, #28]
|
|
800557a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800557e: 83bb strh r3, [r7, #28]
|
|
8005580: 687a ldr r2, [r7, #4]
|
|
8005582: 683b ldr r3, [r7, #0]
|
|
8005584: 781b ldrb r3, [r3, #0]
|
|
8005586: 009b lsls r3, r3, #2
|
|
8005588: 441a add r2, r3
|
|
800558a: 8bbb ldrh r3, [r7, #28]
|
|
800558c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005590: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005594: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005598: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800559c: b29b uxth r3, r3
|
|
800559e: 8013 strh r3, [r2, #0]
|
|
80055a0: e1ea b.n 8005978 <USB_ActivateEndpoint+0x770>
|
|
}
|
|
else
|
|
{
|
|
/* Configure NAK status for OUT Endpoint */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
|
|
80055a2: 687a ldr r2, [r7, #4]
|
|
80055a4: 683b ldr r3, [r7, #0]
|
|
80055a6: 781b ldrb r3, [r3, #0]
|
|
80055a8: 009b lsls r3, r3, #2
|
|
80055aa: 4413 add r3, r2
|
|
80055ac: 881b ldrh r3, [r3, #0]
|
|
80055ae: b29b uxth r3, r3
|
|
80055b0: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80055b4: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80055b8: 83fb strh r3, [r7, #30]
|
|
80055ba: 8bfb ldrh r3, [r7, #30]
|
|
80055bc: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
80055c0: 83fb strh r3, [r7, #30]
|
|
80055c2: 687a ldr r2, [r7, #4]
|
|
80055c4: 683b ldr r3, [r7, #0]
|
|
80055c6: 781b ldrb r3, [r3, #0]
|
|
80055c8: 009b lsls r3, r3, #2
|
|
80055ca: 441a add r2, r3
|
|
80055cc: 8bfb ldrh r3, [r7, #30]
|
|
80055ce: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80055d2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80055d6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80055da: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80055de: b29b uxth r3, r3
|
|
80055e0: 8013 strh r3, [r2, #0]
|
|
80055e2: e1c9 b.n 8005978 <USB_ActivateEndpoint+0x770>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
/* Double Buffer */
|
|
else
|
|
{
|
|
if (ep->type == EP_TYPE_BULK)
|
|
80055e4: 683b ldr r3, [r7, #0]
|
|
80055e6: 78db ldrb r3, [r3, #3]
|
|
80055e8: 2b02 cmp r3, #2
|
|
80055ea: d11e bne.n 800562a <USB_ActivateEndpoint+0x422>
|
|
{
|
|
/* Set bulk endpoint as double buffered */
|
|
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
|
|
80055ec: 687a ldr r2, [r7, #4]
|
|
80055ee: 683b ldr r3, [r7, #0]
|
|
80055f0: 781b ldrb r3, [r3, #0]
|
|
80055f2: 009b lsls r3, r3, #2
|
|
80055f4: 4413 add r3, r2
|
|
80055f6: 881b ldrh r3, [r3, #0]
|
|
80055f8: b29b uxth r3, r3
|
|
80055fa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80055fe: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005602: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
|
|
8005606: 687a ldr r2, [r7, #4]
|
|
8005608: 683b ldr r3, [r7, #0]
|
|
800560a: 781b ldrb r3, [r3, #0]
|
|
800560c: 009b lsls r3, r3, #2
|
|
800560e: 441a add r2, r3
|
|
8005610: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
|
|
8005614: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005618: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800561c: f443 4301 orr.w r3, r3, #33024 @ 0x8100
|
|
8005620: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005624: b29b uxth r3, r3
|
|
8005626: 8013 strh r3, [r2, #0]
|
|
8005628: e01d b.n 8005666 <USB_ActivateEndpoint+0x45e>
|
|
}
|
|
else
|
|
{
|
|
/* Set the ISOC endpoint in double buffer mode */
|
|
PCD_CLEAR_EP_KIND(USBx, ep->num);
|
|
800562a: 687a ldr r2, [r7, #4]
|
|
800562c: 683b ldr r3, [r7, #0]
|
|
800562e: 781b ldrb r3, [r3, #0]
|
|
8005630: 009b lsls r3, r3, #2
|
|
8005632: 4413 add r3, r2
|
|
8005634: 881b ldrh r3, [r3, #0]
|
|
8005636: b29b uxth r3, r3
|
|
8005638: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
|
|
800563c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005640: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
|
|
8005644: 687a ldr r2, [r7, #4]
|
|
8005646: 683b ldr r3, [r7, #0]
|
|
8005648: 781b ldrb r3, [r3, #0]
|
|
800564a: 009b lsls r3, r3, #2
|
|
800564c: 441a add r2, r3
|
|
800564e: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
|
|
8005652: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005656: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800565a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800565e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005662: b29b uxth r3, r3
|
|
8005664: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Set buffer address for double buffered mode */
|
|
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
|
|
8005666: 687b ldr r3, [r7, #4]
|
|
8005668: 65fb str r3, [r7, #92] @ 0x5c
|
|
800566a: 687b ldr r3, [r7, #4]
|
|
800566c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8005670: b29b uxth r3, r3
|
|
8005672: 461a mov r2, r3
|
|
8005674: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8005676: 4413 add r3, r2
|
|
8005678: 65fb str r3, [r7, #92] @ 0x5c
|
|
800567a: 683b ldr r3, [r7, #0]
|
|
800567c: 781b ldrb r3, [r3, #0]
|
|
800567e: 011a lsls r2, r3, #4
|
|
8005680: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8005682: 4413 add r3, r2
|
|
8005684: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8005688: 65bb str r3, [r7, #88] @ 0x58
|
|
800568a: 683b ldr r3, [r7, #0]
|
|
800568c: 891b ldrh r3, [r3, #8]
|
|
800568e: 085b lsrs r3, r3, #1
|
|
8005690: b29b uxth r3, r3
|
|
8005692: 005b lsls r3, r3, #1
|
|
8005694: b29a uxth r2, r3
|
|
8005696: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8005698: 801a strh r2, [r3, #0]
|
|
800569a: 687b ldr r3, [r7, #4]
|
|
800569c: 657b str r3, [r7, #84] @ 0x54
|
|
800569e: 687b ldr r3, [r7, #4]
|
|
80056a0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80056a4: b29b uxth r3, r3
|
|
80056a6: 461a mov r2, r3
|
|
80056a8: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80056aa: 4413 add r3, r2
|
|
80056ac: 657b str r3, [r7, #84] @ 0x54
|
|
80056ae: 683b ldr r3, [r7, #0]
|
|
80056b0: 781b ldrb r3, [r3, #0]
|
|
80056b2: 011a lsls r2, r3, #4
|
|
80056b4: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80056b6: 4413 add r3, r2
|
|
80056b8: f503 6381 add.w r3, r3, #1032 @ 0x408
|
|
80056bc: 653b str r3, [r7, #80] @ 0x50
|
|
80056be: 683b ldr r3, [r7, #0]
|
|
80056c0: 895b ldrh r3, [r3, #10]
|
|
80056c2: 085b lsrs r3, r3, #1
|
|
80056c4: b29b uxth r3, r3
|
|
80056c6: 005b lsls r3, r3, #1
|
|
80056c8: b29a uxth r2, r3
|
|
80056ca: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80056cc: 801a strh r2, [r3, #0]
|
|
|
|
if (ep->is_in == 0U)
|
|
80056ce: 683b ldr r3, [r7, #0]
|
|
80056d0: 785b ldrb r3, [r3, #1]
|
|
80056d2: 2b00 cmp r3, #0
|
|
80056d4: f040 8093 bne.w 80057fe <USB_ActivateEndpoint+0x5f6>
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT */
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
80056d8: 687a ldr r2, [r7, #4]
|
|
80056da: 683b ldr r3, [r7, #0]
|
|
80056dc: 781b ldrb r3, [r3, #0]
|
|
80056de: 009b lsls r3, r3, #2
|
|
80056e0: 4413 add r3, r2
|
|
80056e2: 881b ldrh r3, [r3, #0]
|
|
80056e4: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
|
|
80056e8: f8b7 3040 ldrh.w r3, [r7, #64] @ 0x40
|
|
80056ec: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80056f0: 2b00 cmp r3, #0
|
|
80056f2: d01b beq.n 800572c <USB_ActivateEndpoint+0x524>
|
|
80056f4: 687a ldr r2, [r7, #4]
|
|
80056f6: 683b ldr r3, [r7, #0]
|
|
80056f8: 781b ldrb r3, [r3, #0]
|
|
80056fa: 009b lsls r3, r3, #2
|
|
80056fc: 4413 add r3, r2
|
|
80056fe: 881b ldrh r3, [r3, #0]
|
|
8005700: b29b uxth r3, r3
|
|
8005702: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005706: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800570a: 87fb strh r3, [r7, #62] @ 0x3e
|
|
800570c: 687a ldr r2, [r7, #4]
|
|
800570e: 683b ldr r3, [r7, #0]
|
|
8005710: 781b ldrb r3, [r3, #0]
|
|
8005712: 009b lsls r3, r3, #2
|
|
8005714: 441a add r2, r3
|
|
8005716: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
8005718: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800571c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005720: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8005724: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005728: b29b uxth r3, r3
|
|
800572a: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800572c: 687a ldr r2, [r7, #4]
|
|
800572e: 683b ldr r3, [r7, #0]
|
|
8005730: 781b ldrb r3, [r3, #0]
|
|
8005732: 009b lsls r3, r3, #2
|
|
8005734: 4413 add r3, r2
|
|
8005736: 881b ldrh r3, [r3, #0]
|
|
8005738: 87bb strh r3, [r7, #60] @ 0x3c
|
|
800573a: 8fbb ldrh r3, [r7, #60] @ 0x3c
|
|
800573c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005740: 2b00 cmp r3, #0
|
|
8005742: d01b beq.n 800577c <USB_ActivateEndpoint+0x574>
|
|
8005744: 687a ldr r2, [r7, #4]
|
|
8005746: 683b ldr r3, [r7, #0]
|
|
8005748: 781b ldrb r3, [r3, #0]
|
|
800574a: 009b lsls r3, r3, #2
|
|
800574c: 4413 add r3, r2
|
|
800574e: 881b ldrh r3, [r3, #0]
|
|
8005750: b29b uxth r3, r3
|
|
8005752: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005756: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800575a: 877b strh r3, [r7, #58] @ 0x3a
|
|
800575c: 687a ldr r2, [r7, #4]
|
|
800575e: 683b ldr r3, [r7, #0]
|
|
8005760: 781b ldrb r3, [r3, #0]
|
|
8005762: 009b lsls r3, r3, #2
|
|
8005764: 441a add r2, r3
|
|
8005766: 8f7b ldrh r3, [r7, #58] @ 0x3a
|
|
8005768: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800576c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005770: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005774: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8005778: b29b uxth r3, r3
|
|
800577a: 8013 strh r3, [r2, #0]
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
800577c: 687a ldr r2, [r7, #4]
|
|
800577e: 683b ldr r3, [r7, #0]
|
|
8005780: 781b ldrb r3, [r3, #0]
|
|
8005782: 009b lsls r3, r3, #2
|
|
8005784: 4413 add r3, r2
|
|
8005786: 881b ldrh r3, [r3, #0]
|
|
8005788: b29b uxth r3, r3
|
|
800578a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800578e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005792: 873b strh r3, [r7, #56] @ 0x38
|
|
8005794: 8f3b ldrh r3, [r7, #56] @ 0x38
|
|
8005796: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
800579a: 873b strh r3, [r7, #56] @ 0x38
|
|
800579c: 8f3b ldrh r3, [r7, #56] @ 0x38
|
|
800579e: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
80057a2: 873b strh r3, [r7, #56] @ 0x38
|
|
80057a4: 687a ldr r2, [r7, #4]
|
|
80057a6: 683b ldr r3, [r7, #0]
|
|
80057a8: 781b ldrb r3, [r3, #0]
|
|
80057aa: 009b lsls r3, r3, #2
|
|
80057ac: 441a add r2, r3
|
|
80057ae: 8f3b ldrh r3, [r7, #56] @ 0x38
|
|
80057b0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80057b4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80057b8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80057bc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80057c0: b29b uxth r3, r3
|
|
80057c2: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
80057c4: 687a ldr r2, [r7, #4]
|
|
80057c6: 683b ldr r3, [r7, #0]
|
|
80057c8: 781b ldrb r3, [r3, #0]
|
|
80057ca: 009b lsls r3, r3, #2
|
|
80057cc: 4413 add r3, r2
|
|
80057ce: 881b ldrh r3, [r3, #0]
|
|
80057d0: b29b uxth r3, r3
|
|
80057d2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80057d6: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80057da: 86fb strh r3, [r7, #54] @ 0x36
|
|
80057dc: 687a ldr r2, [r7, #4]
|
|
80057de: 683b ldr r3, [r7, #0]
|
|
80057e0: 781b ldrb r3, [r3, #0]
|
|
80057e2: 009b lsls r3, r3, #2
|
|
80057e4: 441a add r2, r3
|
|
80057e6: 8efb ldrh r3, [r7, #54] @ 0x36
|
|
80057e8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80057ec: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80057f0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80057f4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80057f8: b29b uxth r3, r3
|
|
80057fa: 8013 strh r3, [r2, #0]
|
|
80057fc: e0bc b.n 8005978 <USB_ActivateEndpoint+0x770>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT */
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
80057fe: 687a ldr r2, [r7, #4]
|
|
8005800: 683b ldr r3, [r7, #0]
|
|
8005802: 781b ldrb r3, [r3, #0]
|
|
8005804: 009b lsls r3, r3, #2
|
|
8005806: 4413 add r3, r2
|
|
8005808: 881b ldrh r3, [r3, #0]
|
|
800580a: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
800580e: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
8005812: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8005816: 2b00 cmp r3, #0
|
|
8005818: d01d beq.n 8005856 <USB_ActivateEndpoint+0x64e>
|
|
800581a: 687a ldr r2, [r7, #4]
|
|
800581c: 683b ldr r3, [r7, #0]
|
|
800581e: 781b ldrb r3, [r3, #0]
|
|
8005820: 009b lsls r3, r3, #2
|
|
8005822: 4413 add r3, r2
|
|
8005824: 881b ldrh r3, [r3, #0]
|
|
8005826: b29b uxth r3, r3
|
|
8005828: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800582c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005830: f8a7 304c strh.w r3, [r7, #76] @ 0x4c
|
|
8005834: 687a ldr r2, [r7, #4]
|
|
8005836: 683b ldr r3, [r7, #0]
|
|
8005838: 781b ldrb r3, [r3, #0]
|
|
800583a: 009b lsls r3, r3, #2
|
|
800583c: 441a add r2, r3
|
|
800583e: f8b7 304c ldrh.w r3, [r7, #76] @ 0x4c
|
|
8005842: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005846: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800584a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800584e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005852: b29b uxth r3, r3
|
|
8005854: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
8005856: 687a ldr r2, [r7, #4]
|
|
8005858: 683b ldr r3, [r7, #0]
|
|
800585a: 781b ldrb r3, [r3, #0]
|
|
800585c: 009b lsls r3, r3, #2
|
|
800585e: 4413 add r3, r2
|
|
8005860: 881b ldrh r3, [r3, #0]
|
|
8005862: f8a7 304a strh.w r3, [r7, #74] @ 0x4a
|
|
8005866: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a
|
|
800586a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800586e: 2b00 cmp r3, #0
|
|
8005870: d01d beq.n 80058ae <USB_ActivateEndpoint+0x6a6>
|
|
8005872: 687a ldr r2, [r7, #4]
|
|
8005874: 683b ldr r3, [r7, #0]
|
|
8005876: 781b ldrb r3, [r3, #0]
|
|
8005878: 009b lsls r3, r3, #2
|
|
800587a: 4413 add r3, r2
|
|
800587c: 881b ldrh r3, [r3, #0]
|
|
800587e: b29b uxth r3, r3
|
|
8005880: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005884: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005888: f8a7 3048 strh.w r3, [r7, #72] @ 0x48
|
|
800588c: 687a ldr r2, [r7, #4]
|
|
800588e: 683b ldr r3, [r7, #0]
|
|
8005890: 781b ldrb r3, [r3, #0]
|
|
8005892: 009b lsls r3, r3, #2
|
|
8005894: 441a add r2, r3
|
|
8005896: f8b7 3048 ldrh.w r3, [r7, #72] @ 0x48
|
|
800589a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800589e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80058a2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80058a6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
80058aa: b29b uxth r3, r3
|
|
80058ac: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
80058ae: 683b ldr r3, [r7, #0]
|
|
80058b0: 78db ldrb r3, [r3, #3]
|
|
80058b2: 2b01 cmp r3, #1
|
|
80058b4: d024 beq.n 8005900 <USB_ActivateEndpoint+0x6f8>
|
|
{
|
|
/* Configure NAK status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
|
80058b6: 687a ldr r2, [r7, #4]
|
|
80058b8: 683b ldr r3, [r7, #0]
|
|
80058ba: 781b ldrb r3, [r3, #0]
|
|
80058bc: 009b lsls r3, r3, #2
|
|
80058be: 4413 add r3, r2
|
|
80058c0: 881b ldrh r3, [r3, #0]
|
|
80058c2: b29b uxth r3, r3
|
|
80058c4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80058c8: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80058cc: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
|
|
80058d0: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
|
|
80058d4: f083 0320 eor.w r3, r3, #32
|
|
80058d8: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
|
|
80058dc: 687a ldr r2, [r7, #4]
|
|
80058de: 683b ldr r3, [r7, #0]
|
|
80058e0: 781b ldrb r3, [r3, #0]
|
|
80058e2: 009b lsls r3, r3, #2
|
|
80058e4: 441a add r2, r3
|
|
80058e6: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
|
|
80058ea: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80058ee: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80058f2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80058f6: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80058fa: b29b uxth r3, r3
|
|
80058fc: 8013 strh r3, [r2, #0]
|
|
80058fe: e01d b.n 800593c <USB_ActivateEndpoint+0x734>
|
|
}
|
|
else
|
|
{
|
|
/* Configure TX Endpoint to disabled state */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
8005900: 687a ldr r2, [r7, #4]
|
|
8005902: 683b ldr r3, [r7, #0]
|
|
8005904: 781b ldrb r3, [r3, #0]
|
|
8005906: 009b lsls r3, r3, #2
|
|
8005908: 4413 add r3, r2
|
|
800590a: 881b ldrh r3, [r3, #0]
|
|
800590c: b29b uxth r3, r3
|
|
800590e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005912: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005916: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
|
|
800591a: 687a ldr r2, [r7, #4]
|
|
800591c: 683b ldr r3, [r7, #0]
|
|
800591e: 781b ldrb r3, [r3, #0]
|
|
8005920: 009b lsls r3, r3, #2
|
|
8005922: 441a add r2, r3
|
|
8005924: f8b7 3046 ldrh.w r3, [r7, #70] @ 0x46
|
|
8005928: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800592c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005930: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005934: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005938: b29b uxth r3, r3
|
|
800593a: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
800593c: 687a ldr r2, [r7, #4]
|
|
800593e: 683b ldr r3, [r7, #0]
|
|
8005940: 781b ldrb r3, [r3, #0]
|
|
8005942: 009b lsls r3, r3, #2
|
|
8005944: 4413 add r3, r2
|
|
8005946: 881b ldrh r3, [r3, #0]
|
|
8005948: b29b uxth r3, r3
|
|
800594a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800594e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005952: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
|
|
8005956: 687a ldr r2, [r7, #4]
|
|
8005958: 683b ldr r3, [r7, #0]
|
|
800595a: 781b ldrb r3, [r3, #0]
|
|
800595c: 009b lsls r3, r3, #2
|
|
800595e: 441a add r2, r3
|
|
8005960: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
|
|
8005964: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005968: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800596c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005970: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005974: b29b uxth r3, r3
|
|
8005976: 8013 strh r3, [r2, #0]
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
return ret;
|
|
8005978: f897 306f ldrb.w r3, [r7, #111] @ 0x6f
|
|
}
|
|
800597c: 4618 mov r0, r3
|
|
800597e: 3774 adds r7, #116 @ 0x74
|
|
8005980: 46bd mov sp, r7
|
|
8005982: bc80 pop {r7}
|
|
8005984: 4770 bx lr
|
|
8005986: bf00 nop
|
|
|
|
08005988 <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8005988: b480 push {r7}
|
|
800598a: b08d sub sp, #52 @ 0x34
|
|
800598c: af00 add r7, sp, #0
|
|
800598e: 6078 str r0, [r7, #4]
|
|
8005990: 6039 str r1, [r7, #0]
|
|
if (ep->doublebuffer == 0U)
|
|
8005992: 683b ldr r3, [r7, #0]
|
|
8005994: 7b1b ldrb r3, [r3, #12]
|
|
8005996: 2b00 cmp r3, #0
|
|
8005998: f040 808e bne.w 8005ab8 <USB_DeactivateEndpoint+0x130>
|
|
{
|
|
if (ep->is_in != 0U)
|
|
800599c: 683b ldr r3, [r7, #0]
|
|
800599e: 785b ldrb r3, [r3, #1]
|
|
80059a0: 2b00 cmp r3, #0
|
|
80059a2: d044 beq.n 8005a2e <USB_DeactivateEndpoint+0xa6>
|
|
{
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
80059a4: 687a ldr r2, [r7, #4]
|
|
80059a6: 683b ldr r3, [r7, #0]
|
|
80059a8: 781b ldrb r3, [r3, #0]
|
|
80059aa: 009b lsls r3, r3, #2
|
|
80059ac: 4413 add r3, r2
|
|
80059ae: 881b ldrh r3, [r3, #0]
|
|
80059b0: 81bb strh r3, [r7, #12]
|
|
80059b2: 89bb ldrh r3, [r7, #12]
|
|
80059b4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80059b8: 2b00 cmp r3, #0
|
|
80059ba: d01b beq.n 80059f4 <USB_DeactivateEndpoint+0x6c>
|
|
80059bc: 687a ldr r2, [r7, #4]
|
|
80059be: 683b ldr r3, [r7, #0]
|
|
80059c0: 781b ldrb r3, [r3, #0]
|
|
80059c2: 009b lsls r3, r3, #2
|
|
80059c4: 4413 add r3, r2
|
|
80059c6: 881b ldrh r3, [r3, #0]
|
|
80059c8: b29b uxth r3, r3
|
|
80059ca: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80059ce: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80059d2: 817b strh r3, [r7, #10]
|
|
80059d4: 687a ldr r2, [r7, #4]
|
|
80059d6: 683b ldr r3, [r7, #0]
|
|
80059d8: 781b ldrb r3, [r3, #0]
|
|
80059da: 009b lsls r3, r3, #2
|
|
80059dc: 441a add r2, r3
|
|
80059de: 897b ldrh r3, [r7, #10]
|
|
80059e0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80059e4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80059e8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80059ec: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
80059f0: b29b uxth r3, r3
|
|
80059f2: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure DISABLE status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
80059f4: 687a ldr r2, [r7, #4]
|
|
80059f6: 683b ldr r3, [r7, #0]
|
|
80059f8: 781b ldrb r3, [r3, #0]
|
|
80059fa: 009b lsls r3, r3, #2
|
|
80059fc: 4413 add r3, r2
|
|
80059fe: 881b ldrh r3, [r3, #0]
|
|
8005a00: b29b uxth r3, r3
|
|
8005a02: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005a06: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005a0a: 813b strh r3, [r7, #8]
|
|
8005a0c: 687a ldr r2, [r7, #4]
|
|
8005a0e: 683b ldr r3, [r7, #0]
|
|
8005a10: 781b ldrb r3, [r3, #0]
|
|
8005a12: 009b lsls r3, r3, #2
|
|
8005a14: 441a add r2, r3
|
|
8005a16: 893b ldrh r3, [r7, #8]
|
|
8005a18: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005a1c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005a20: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005a24: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005a28: b29b uxth r3, r3
|
|
8005a2a: 8013 strh r3, [r2, #0]
|
|
8005a2c: e192 b.n 8005d54 <USB_DeactivateEndpoint+0x3cc>
|
|
}
|
|
|
|
else
|
|
{
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
8005a2e: 687a ldr r2, [r7, #4]
|
|
8005a30: 683b ldr r3, [r7, #0]
|
|
8005a32: 781b ldrb r3, [r3, #0]
|
|
8005a34: 009b lsls r3, r3, #2
|
|
8005a36: 4413 add r3, r2
|
|
8005a38: 881b ldrh r3, [r3, #0]
|
|
8005a3a: 827b strh r3, [r7, #18]
|
|
8005a3c: 8a7b ldrh r3, [r7, #18]
|
|
8005a3e: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8005a42: 2b00 cmp r3, #0
|
|
8005a44: d01b beq.n 8005a7e <USB_DeactivateEndpoint+0xf6>
|
|
8005a46: 687a ldr r2, [r7, #4]
|
|
8005a48: 683b ldr r3, [r7, #0]
|
|
8005a4a: 781b ldrb r3, [r3, #0]
|
|
8005a4c: 009b lsls r3, r3, #2
|
|
8005a4e: 4413 add r3, r2
|
|
8005a50: 881b ldrh r3, [r3, #0]
|
|
8005a52: b29b uxth r3, r3
|
|
8005a54: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005a58: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005a5c: 823b strh r3, [r7, #16]
|
|
8005a5e: 687a ldr r2, [r7, #4]
|
|
8005a60: 683b ldr r3, [r7, #0]
|
|
8005a62: 781b ldrb r3, [r3, #0]
|
|
8005a64: 009b lsls r3, r3, #2
|
|
8005a66: 441a add r2, r3
|
|
8005a68: 8a3b ldrh r3, [r7, #16]
|
|
8005a6a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005a6e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005a72: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8005a76: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005a7a: b29b uxth r3, r3
|
|
8005a7c: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure DISABLE status for the Endpoint */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
8005a7e: 687a ldr r2, [r7, #4]
|
|
8005a80: 683b ldr r3, [r7, #0]
|
|
8005a82: 781b ldrb r3, [r3, #0]
|
|
8005a84: 009b lsls r3, r3, #2
|
|
8005a86: 4413 add r3, r2
|
|
8005a88: 881b ldrh r3, [r3, #0]
|
|
8005a8a: b29b uxth r3, r3
|
|
8005a8c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8005a90: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005a94: 81fb strh r3, [r7, #14]
|
|
8005a96: 687a ldr r2, [r7, #4]
|
|
8005a98: 683b ldr r3, [r7, #0]
|
|
8005a9a: 781b ldrb r3, [r3, #0]
|
|
8005a9c: 009b lsls r3, r3, #2
|
|
8005a9e: 441a add r2, r3
|
|
8005aa0: 89fb ldrh r3, [r7, #14]
|
|
8005aa2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005aa6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005aaa: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005aae: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005ab2: b29b uxth r3, r3
|
|
8005ab4: 8013 strh r3, [r2, #0]
|
|
8005ab6: e14d b.n 8005d54 <USB_DeactivateEndpoint+0x3cc>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
/* Double Buffer */
|
|
else
|
|
{
|
|
if (ep->is_in == 0U)
|
|
8005ab8: 683b ldr r3, [r7, #0]
|
|
8005aba: 785b ldrb r3, [r3, #1]
|
|
8005abc: 2b00 cmp r3, #0
|
|
8005abe: f040 80a5 bne.w 8005c0c <USB_DeactivateEndpoint+0x284>
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
8005ac2: 687a ldr r2, [r7, #4]
|
|
8005ac4: 683b ldr r3, [r7, #0]
|
|
8005ac6: 781b ldrb r3, [r3, #0]
|
|
8005ac8: 009b lsls r3, r3, #2
|
|
8005aca: 4413 add r3, r2
|
|
8005acc: 881b ldrh r3, [r3, #0]
|
|
8005ace: 843b strh r3, [r7, #32]
|
|
8005ad0: 8c3b ldrh r3, [r7, #32]
|
|
8005ad2: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8005ad6: 2b00 cmp r3, #0
|
|
8005ad8: d01b beq.n 8005b12 <USB_DeactivateEndpoint+0x18a>
|
|
8005ada: 687a ldr r2, [r7, #4]
|
|
8005adc: 683b ldr r3, [r7, #0]
|
|
8005ade: 781b ldrb r3, [r3, #0]
|
|
8005ae0: 009b lsls r3, r3, #2
|
|
8005ae2: 4413 add r3, r2
|
|
8005ae4: 881b ldrh r3, [r3, #0]
|
|
8005ae6: b29b uxth r3, r3
|
|
8005ae8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005aec: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005af0: 83fb strh r3, [r7, #30]
|
|
8005af2: 687a ldr r2, [r7, #4]
|
|
8005af4: 683b ldr r3, [r7, #0]
|
|
8005af6: 781b ldrb r3, [r3, #0]
|
|
8005af8: 009b lsls r3, r3, #2
|
|
8005afa: 441a add r2, r3
|
|
8005afc: 8bfb ldrh r3, [r7, #30]
|
|
8005afe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005b02: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005b06: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8005b0a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005b0e: b29b uxth r3, r3
|
|
8005b10: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
8005b12: 687a ldr r2, [r7, #4]
|
|
8005b14: 683b ldr r3, [r7, #0]
|
|
8005b16: 781b ldrb r3, [r3, #0]
|
|
8005b18: 009b lsls r3, r3, #2
|
|
8005b1a: 4413 add r3, r2
|
|
8005b1c: 881b ldrh r3, [r3, #0]
|
|
8005b1e: 83bb strh r3, [r7, #28]
|
|
8005b20: 8bbb ldrh r3, [r7, #28]
|
|
8005b22: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005b26: 2b00 cmp r3, #0
|
|
8005b28: d01b beq.n 8005b62 <USB_DeactivateEndpoint+0x1da>
|
|
8005b2a: 687a ldr r2, [r7, #4]
|
|
8005b2c: 683b ldr r3, [r7, #0]
|
|
8005b2e: 781b ldrb r3, [r3, #0]
|
|
8005b30: 009b lsls r3, r3, #2
|
|
8005b32: 4413 add r3, r2
|
|
8005b34: 881b ldrh r3, [r3, #0]
|
|
8005b36: b29b uxth r3, r3
|
|
8005b38: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005b3c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005b40: 837b strh r3, [r7, #26]
|
|
8005b42: 687a ldr r2, [r7, #4]
|
|
8005b44: 683b ldr r3, [r7, #0]
|
|
8005b46: 781b ldrb r3, [r3, #0]
|
|
8005b48: 009b lsls r3, r3, #2
|
|
8005b4a: 441a add r2, r3
|
|
8005b4c: 8b7b ldrh r3, [r7, #26]
|
|
8005b4e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005b52: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005b56: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005b5a: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8005b5e: b29b uxth r3, r3
|
|
8005b60: 8013 strh r3, [r2, #0]
|
|
|
|
/* Reset value of the data toggle bits for the endpoint out*/
|
|
PCD_TX_DTOG(USBx, ep->num);
|
|
8005b62: 687a ldr r2, [r7, #4]
|
|
8005b64: 683b ldr r3, [r7, #0]
|
|
8005b66: 781b ldrb r3, [r3, #0]
|
|
8005b68: 009b lsls r3, r3, #2
|
|
8005b6a: 4413 add r3, r2
|
|
8005b6c: 881b ldrh r3, [r3, #0]
|
|
8005b6e: b29b uxth r3, r3
|
|
8005b70: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005b74: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005b78: 833b strh r3, [r7, #24]
|
|
8005b7a: 687a ldr r2, [r7, #4]
|
|
8005b7c: 683b ldr r3, [r7, #0]
|
|
8005b7e: 781b ldrb r3, [r3, #0]
|
|
8005b80: 009b lsls r3, r3, #2
|
|
8005b82: 441a add r2, r3
|
|
8005b84: 8b3b ldrh r3, [r7, #24]
|
|
8005b86: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005b8a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005b8e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005b92: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8005b96: b29b uxth r3, r3
|
|
8005b98: 8013 strh r3, [r2, #0]
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
8005b9a: 687a ldr r2, [r7, #4]
|
|
8005b9c: 683b ldr r3, [r7, #0]
|
|
8005b9e: 781b ldrb r3, [r3, #0]
|
|
8005ba0: 009b lsls r3, r3, #2
|
|
8005ba2: 4413 add r3, r2
|
|
8005ba4: 881b ldrh r3, [r3, #0]
|
|
8005ba6: b29b uxth r3, r3
|
|
8005ba8: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8005bac: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005bb0: 82fb strh r3, [r7, #22]
|
|
8005bb2: 687a ldr r2, [r7, #4]
|
|
8005bb4: 683b ldr r3, [r7, #0]
|
|
8005bb6: 781b ldrb r3, [r3, #0]
|
|
8005bb8: 009b lsls r3, r3, #2
|
|
8005bba: 441a add r2, r3
|
|
8005bbc: 8afb ldrh r3, [r7, #22]
|
|
8005bbe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005bc2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005bc6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005bca: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005bce: b29b uxth r3, r3
|
|
8005bd0: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
8005bd2: 687a ldr r2, [r7, #4]
|
|
8005bd4: 683b ldr r3, [r7, #0]
|
|
8005bd6: 781b ldrb r3, [r3, #0]
|
|
8005bd8: 009b lsls r3, r3, #2
|
|
8005bda: 4413 add r3, r2
|
|
8005bdc: 881b ldrh r3, [r3, #0]
|
|
8005bde: b29b uxth r3, r3
|
|
8005be0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005be4: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005be8: 82bb strh r3, [r7, #20]
|
|
8005bea: 687a ldr r2, [r7, #4]
|
|
8005bec: 683b ldr r3, [r7, #0]
|
|
8005bee: 781b ldrb r3, [r3, #0]
|
|
8005bf0: 009b lsls r3, r3, #2
|
|
8005bf2: 441a add r2, r3
|
|
8005bf4: 8abb ldrh r3, [r7, #20]
|
|
8005bf6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005bfa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005bfe: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005c02: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005c06: b29b uxth r3, r3
|
|
8005c08: 8013 strh r3, [r2, #0]
|
|
8005c0a: e0a3 b.n 8005d54 <USB_DeactivateEndpoint+0x3cc>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
8005c0c: 687a ldr r2, [r7, #4]
|
|
8005c0e: 683b ldr r3, [r7, #0]
|
|
8005c10: 781b ldrb r3, [r3, #0]
|
|
8005c12: 009b lsls r3, r3, #2
|
|
8005c14: 4413 add r3, r2
|
|
8005c16: 881b ldrh r3, [r3, #0]
|
|
8005c18: 85fb strh r3, [r7, #46] @ 0x2e
|
|
8005c1a: 8dfb ldrh r3, [r7, #46] @ 0x2e
|
|
8005c1c: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8005c20: 2b00 cmp r3, #0
|
|
8005c22: d01b beq.n 8005c5c <USB_DeactivateEndpoint+0x2d4>
|
|
8005c24: 687a ldr r2, [r7, #4]
|
|
8005c26: 683b ldr r3, [r7, #0]
|
|
8005c28: 781b ldrb r3, [r3, #0]
|
|
8005c2a: 009b lsls r3, r3, #2
|
|
8005c2c: 4413 add r3, r2
|
|
8005c2e: 881b ldrh r3, [r3, #0]
|
|
8005c30: b29b uxth r3, r3
|
|
8005c32: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005c36: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005c3a: 85bb strh r3, [r7, #44] @ 0x2c
|
|
8005c3c: 687a ldr r2, [r7, #4]
|
|
8005c3e: 683b ldr r3, [r7, #0]
|
|
8005c40: 781b ldrb r3, [r3, #0]
|
|
8005c42: 009b lsls r3, r3, #2
|
|
8005c44: 441a add r2, r3
|
|
8005c46: 8dbb ldrh r3, [r7, #44] @ 0x2c
|
|
8005c48: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005c4c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005c50: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8005c54: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005c58: b29b uxth r3, r3
|
|
8005c5a: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
8005c5c: 687a ldr r2, [r7, #4]
|
|
8005c5e: 683b ldr r3, [r7, #0]
|
|
8005c60: 781b ldrb r3, [r3, #0]
|
|
8005c62: 009b lsls r3, r3, #2
|
|
8005c64: 4413 add r3, r2
|
|
8005c66: 881b ldrh r3, [r3, #0]
|
|
8005c68: 857b strh r3, [r7, #42] @ 0x2a
|
|
8005c6a: 8d7b ldrh r3, [r7, #42] @ 0x2a
|
|
8005c6c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005c70: 2b00 cmp r3, #0
|
|
8005c72: d01b beq.n 8005cac <USB_DeactivateEndpoint+0x324>
|
|
8005c74: 687a ldr r2, [r7, #4]
|
|
8005c76: 683b ldr r3, [r7, #0]
|
|
8005c78: 781b ldrb r3, [r3, #0]
|
|
8005c7a: 009b lsls r3, r3, #2
|
|
8005c7c: 4413 add r3, r2
|
|
8005c7e: 881b ldrh r3, [r3, #0]
|
|
8005c80: b29b uxth r3, r3
|
|
8005c82: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005c86: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005c8a: 853b strh r3, [r7, #40] @ 0x28
|
|
8005c8c: 687a ldr r2, [r7, #4]
|
|
8005c8e: 683b ldr r3, [r7, #0]
|
|
8005c90: 781b ldrb r3, [r3, #0]
|
|
8005c92: 009b lsls r3, r3, #2
|
|
8005c94: 441a add r2, r3
|
|
8005c96: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
8005c98: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005c9c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005ca0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005ca4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8005ca8: b29b uxth r3, r3
|
|
8005caa: 8013 strh r3, [r2, #0]
|
|
PCD_RX_DTOG(USBx, ep->num);
|
|
8005cac: 687a ldr r2, [r7, #4]
|
|
8005cae: 683b ldr r3, [r7, #0]
|
|
8005cb0: 781b ldrb r3, [r3, #0]
|
|
8005cb2: 009b lsls r3, r3, #2
|
|
8005cb4: 4413 add r3, r2
|
|
8005cb6: 881b ldrh r3, [r3, #0]
|
|
8005cb8: b29b uxth r3, r3
|
|
8005cba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005cbe: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005cc2: 84fb strh r3, [r7, #38] @ 0x26
|
|
8005cc4: 687a ldr r2, [r7, #4]
|
|
8005cc6: 683b ldr r3, [r7, #0]
|
|
8005cc8: 781b ldrb r3, [r3, #0]
|
|
8005cca: 009b lsls r3, r3, #2
|
|
8005ccc: 441a add r2, r3
|
|
8005cce: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
8005cd0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005cd4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005cd8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8005cdc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005ce0: b29b uxth r3, r3
|
|
8005ce2: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure DISABLE status for the Endpoint*/
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
8005ce4: 687a ldr r2, [r7, #4]
|
|
8005ce6: 683b ldr r3, [r7, #0]
|
|
8005ce8: 781b ldrb r3, [r3, #0]
|
|
8005cea: 009b lsls r3, r3, #2
|
|
8005cec: 4413 add r3, r2
|
|
8005cee: 881b ldrh r3, [r3, #0]
|
|
8005cf0: b29b uxth r3, r3
|
|
8005cf2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005cf6: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005cfa: 84bb strh r3, [r7, #36] @ 0x24
|
|
8005cfc: 687a ldr r2, [r7, #4]
|
|
8005cfe: 683b ldr r3, [r7, #0]
|
|
8005d00: 781b ldrb r3, [r3, #0]
|
|
8005d02: 009b lsls r3, r3, #2
|
|
8005d04: 441a add r2, r3
|
|
8005d06: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8005d08: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005d0c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005d10: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005d14: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005d18: b29b uxth r3, r3
|
|
8005d1a: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
8005d1c: 687a ldr r2, [r7, #4]
|
|
8005d1e: 683b ldr r3, [r7, #0]
|
|
8005d20: 781b ldrb r3, [r3, #0]
|
|
8005d22: 009b lsls r3, r3, #2
|
|
8005d24: 4413 add r3, r2
|
|
8005d26: 881b ldrh r3, [r3, #0]
|
|
8005d28: b29b uxth r3, r3
|
|
8005d2a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8005d2e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005d32: 847b strh r3, [r7, #34] @ 0x22
|
|
8005d34: 687a ldr r2, [r7, #4]
|
|
8005d36: 683b ldr r3, [r7, #0]
|
|
8005d38: 781b ldrb r3, [r3, #0]
|
|
8005d3a: 009b lsls r3, r3, #2
|
|
8005d3c: 441a add r2, r3
|
|
8005d3e: 8c7b ldrh r3, [r7, #34] @ 0x22
|
|
8005d40: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005d44: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005d48: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005d4c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005d50: b29b uxth r3, r3
|
|
8005d52: 8013 strh r3, [r2, #0]
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
return HAL_OK;
|
|
8005d54: 2300 movs r3, #0
|
|
}
|
|
8005d56: 4618 mov r0, r3
|
|
8005d58: 3734 adds r7, #52 @ 0x34
|
|
8005d5a: 46bd mov sp, r7
|
|
8005d5c: bc80 pop {r7}
|
|
8005d5e: 4770 bx lr
|
|
|
|
08005d60 <USB_EPStartXfer>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8005d60: b580 push {r7, lr}
|
|
8005d62: b0c2 sub sp, #264 @ 0x108
|
|
8005d64: af00 add r7, sp, #0
|
|
8005d66: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005d6a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005d6e: 6018 str r0, [r3, #0]
|
|
8005d70: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005d74: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005d78: 6019 str r1, [r3, #0]
|
|
uint16_t pmabuffer;
|
|
uint16_t wEPVal;
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
8005d7a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005d7e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005d82: 681b ldr r3, [r3, #0]
|
|
8005d84: 785b ldrb r3, [r3, #1]
|
|
8005d86: 2b01 cmp r3, #1
|
|
8005d88: f040 86b7 bne.w 8006afa <USB_EPStartXfer+0xd9a>
|
|
{
|
|
/*Multi packet transfer*/
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
8005d8c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005d90: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005d94: 681b ldr r3, [r3, #0]
|
|
8005d96: 699a ldr r2, [r3, #24]
|
|
8005d98: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005d9c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005da0: 681b ldr r3, [r3, #0]
|
|
8005da2: 691b ldr r3, [r3, #16]
|
|
8005da4: 429a cmp r2, r3
|
|
8005da6: d908 bls.n 8005dba <USB_EPStartXfer+0x5a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8005da8: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005dac: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005db0: 681b ldr r3, [r3, #0]
|
|
8005db2: 691b ldr r3, [r3, #16]
|
|
8005db4: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
8005db8: e007 b.n 8005dca <USB_EPStartXfer+0x6a>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len;
|
|
8005dba: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005dbe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005dc2: 681b ldr r3, [r3, #0]
|
|
8005dc4: 699b ldr r3, [r3, #24]
|
|
8005dc6: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
}
|
|
|
|
/* configure and validate Tx endpoint */
|
|
if (ep->doublebuffer == 0U)
|
|
8005dca: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005dce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005dd2: 681b ldr r3, [r3, #0]
|
|
8005dd4: 7b1b ldrb r3, [r3, #12]
|
|
8005dd6: 2b00 cmp r3, #0
|
|
8005dd8: d13a bne.n 8005e50 <USB_EPStartXfer+0xf0>
|
|
{
|
|
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
|
|
8005dda: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005dde: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005de2: 681b ldr r3, [r3, #0]
|
|
8005de4: 6959 ldr r1, [r3, #20]
|
|
8005de6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005dea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005dee: 681b ldr r3, [r3, #0]
|
|
8005df0: 88da ldrh r2, [r3, #6]
|
|
8005df2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005df6: b29b uxth r3, r3
|
|
8005df8: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
8005dfc: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
8005e00: 6800 ldr r0, [r0, #0]
|
|
8005e02: f001 fc9c bl 800773e <USB_WritePMA>
|
|
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
|
|
8005e06: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e0a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005e0e: 681b ldr r3, [r3, #0]
|
|
8005e10: 613b str r3, [r7, #16]
|
|
8005e12: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e16: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005e1a: 681b ldr r3, [r3, #0]
|
|
8005e1c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8005e20: b29b uxth r3, r3
|
|
8005e22: 461a mov r2, r3
|
|
8005e24: 693b ldr r3, [r7, #16]
|
|
8005e26: 4413 add r3, r2
|
|
8005e28: 613b str r3, [r7, #16]
|
|
8005e2a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e2e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005e32: 681b ldr r3, [r3, #0]
|
|
8005e34: 781b ldrb r3, [r3, #0]
|
|
8005e36: 011a lsls r2, r3, #4
|
|
8005e38: 693b ldr r3, [r7, #16]
|
|
8005e3a: 4413 add r3, r2
|
|
8005e3c: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8005e40: 60fb str r3, [r7, #12]
|
|
8005e42: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005e46: b29a uxth r2, r3
|
|
8005e48: 68fb ldr r3, [r7, #12]
|
|
8005e4a: 801a strh r2, [r3, #0]
|
|
8005e4c: f000 be1f b.w 8006a8e <USB_EPStartXfer+0xd2e>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else
|
|
{
|
|
/* double buffer bulk management */
|
|
if (ep->type == EP_TYPE_BULK)
|
|
8005e50: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e54: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005e58: 681b ldr r3, [r3, #0]
|
|
8005e5a: 78db ldrb r3, [r3, #3]
|
|
8005e5c: 2b02 cmp r3, #2
|
|
8005e5e: f040 8462 bne.w 8006726 <USB_EPStartXfer+0x9c6>
|
|
{
|
|
if (ep->xfer_len_db > ep->maxpacket)
|
|
8005e62: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e66: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005e6a: 681b ldr r3, [r3, #0]
|
|
8005e6c: 6a1a ldr r2, [r3, #32]
|
|
8005e6e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e72: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005e76: 681b ldr r3, [r3, #0]
|
|
8005e78: 691b ldr r3, [r3, #16]
|
|
8005e7a: 429a cmp r2, r3
|
|
8005e7c: f240 83df bls.w 800663e <USB_EPStartXfer+0x8de>
|
|
{
|
|
/* enable double buffer */
|
|
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
|
|
8005e80: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e84: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005e88: 681a ldr r2, [r3, #0]
|
|
8005e8a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005e8e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005e92: 681b ldr r3, [r3, #0]
|
|
8005e94: 781b ldrb r3, [r3, #0]
|
|
8005e96: 009b lsls r3, r3, #2
|
|
8005e98: 4413 add r3, r2
|
|
8005e9a: 881b ldrh r3, [r3, #0]
|
|
8005e9c: b29b uxth r3, r3
|
|
8005e9e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005ea2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005ea6: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
|
|
8005eaa: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005eae: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005eb2: 681a ldr r2, [r3, #0]
|
|
8005eb4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005eb8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005ebc: 681b ldr r3, [r3, #0]
|
|
8005ebe: 781b ldrb r3, [r3, #0]
|
|
8005ec0: 009b lsls r3, r3, #2
|
|
8005ec2: 441a add r2, r3
|
|
8005ec4: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
|
|
8005ec8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8005ecc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8005ed0: f443 4301 orr.w r3, r3, #33024 @ 0x8100
|
|
8005ed4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005ed8: b29b uxth r3, r3
|
|
8005eda: 8013 strh r3, [r2, #0]
|
|
|
|
/* each Time to write in PMA xfer_len_db will */
|
|
ep->xfer_len_db -= len;
|
|
8005edc: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005ee0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005ee4: 681b ldr r3, [r3, #0]
|
|
8005ee6: 6a1a ldr r2, [r3, #32]
|
|
8005ee8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005eec: 1ad2 subs r2, r2, r3
|
|
8005eee: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005ef2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005ef6: 681b ldr r3, [r3, #0]
|
|
8005ef8: 621a str r2, [r3, #32]
|
|
|
|
/* Fill the two first buffer in the Buffer0 & Buffer1 */
|
|
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
|
|
8005efa: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005efe: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005f02: 681a ldr r2, [r3, #0]
|
|
8005f04: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005f08: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005f0c: 681b ldr r3, [r3, #0]
|
|
8005f0e: 781b ldrb r3, [r3, #0]
|
|
8005f10: 009b lsls r3, r3, #2
|
|
8005f12: 4413 add r3, r2
|
|
8005f14: 881b ldrh r3, [r3, #0]
|
|
8005f16: b29b uxth r3, r3
|
|
8005f18: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005f1c: 2b00 cmp r3, #0
|
|
8005f1e: f000 81c7 beq.w 80062b0 <USB_EPStartXfer+0x550>
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
|
8005f22: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005f26: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005f2a: 681b ldr r3, [r3, #0]
|
|
8005f2c: 633b str r3, [r7, #48] @ 0x30
|
|
8005f2e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005f32: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005f36: 681b ldr r3, [r3, #0]
|
|
8005f38: 785b ldrb r3, [r3, #1]
|
|
8005f3a: 2b00 cmp r3, #0
|
|
8005f3c: d177 bne.n 800602e <USB_EPStartXfer+0x2ce>
|
|
8005f3e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005f42: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005f46: 681b ldr r3, [r3, #0]
|
|
8005f48: 62bb str r3, [r7, #40] @ 0x28
|
|
8005f4a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005f4e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8005f52: 681b ldr r3, [r3, #0]
|
|
8005f54: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8005f58: b29b uxth r3, r3
|
|
8005f5a: 461a mov r2, r3
|
|
8005f5c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005f5e: 4413 add r3, r2
|
|
8005f60: 62bb str r3, [r7, #40] @ 0x28
|
|
8005f62: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8005f66: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005f6a: 681b ldr r3, [r3, #0]
|
|
8005f6c: 781b ldrb r3, [r3, #0]
|
|
8005f6e: 011a lsls r2, r3, #4
|
|
8005f70: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005f72: 4413 add r3, r2
|
|
8005f74: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8005f78: 627b str r3, [r7, #36] @ 0x24
|
|
8005f7a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f7c: 881b ldrh r3, [r3, #0]
|
|
8005f7e: b29b uxth r3, r3
|
|
8005f80: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8005f84: b29a uxth r2, r3
|
|
8005f86: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f88: 801a strh r2, [r3, #0]
|
|
8005f8a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005f8e: 2b3e cmp r3, #62 @ 0x3e
|
|
8005f90: d921 bls.n 8005fd6 <USB_EPStartXfer+0x276>
|
|
8005f92: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005f96: 095b lsrs r3, r3, #5
|
|
8005f98: f8c7 3100 str.w r3, [r7, #256] @ 0x100
|
|
8005f9c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005fa0: f003 031f and.w r3, r3, #31
|
|
8005fa4: 2b00 cmp r3, #0
|
|
8005fa6: d104 bne.n 8005fb2 <USB_EPStartXfer+0x252>
|
|
8005fa8: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
|
|
8005fac: 3b01 subs r3, #1
|
|
8005fae: f8c7 3100 str.w r3, [r7, #256] @ 0x100
|
|
8005fb2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005fb4: 881b ldrh r3, [r3, #0]
|
|
8005fb6: b29a uxth r2, r3
|
|
8005fb8: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
|
|
8005fbc: b29b uxth r3, r3
|
|
8005fbe: 029b lsls r3, r3, #10
|
|
8005fc0: b29b uxth r3, r3
|
|
8005fc2: 4313 orrs r3, r2
|
|
8005fc4: b29b uxth r3, r3
|
|
8005fc6: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8005fca: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8005fce: b29a uxth r2, r3
|
|
8005fd0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005fd2: 801a strh r2, [r3, #0]
|
|
8005fd4: e050 b.n 8006078 <USB_EPStartXfer+0x318>
|
|
8005fd6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005fda: 2b00 cmp r3, #0
|
|
8005fdc: d10a bne.n 8005ff4 <USB_EPStartXfer+0x294>
|
|
8005fde: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005fe0: 881b ldrh r3, [r3, #0]
|
|
8005fe2: b29b uxth r3, r3
|
|
8005fe4: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8005fe8: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8005fec: b29a uxth r2, r3
|
|
8005fee: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005ff0: 801a strh r2, [r3, #0]
|
|
8005ff2: e041 b.n 8006078 <USB_EPStartXfer+0x318>
|
|
8005ff4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8005ff8: 085b lsrs r3, r3, #1
|
|
8005ffa: f8c7 3100 str.w r3, [r7, #256] @ 0x100
|
|
8005ffe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006002: f003 0301 and.w r3, r3, #1
|
|
8006006: 2b00 cmp r3, #0
|
|
8006008: d004 beq.n 8006014 <USB_EPStartXfer+0x2b4>
|
|
800600a: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
|
|
800600e: 3301 adds r3, #1
|
|
8006010: f8c7 3100 str.w r3, [r7, #256] @ 0x100
|
|
8006014: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006016: 881b ldrh r3, [r3, #0]
|
|
8006018: b29a uxth r2, r3
|
|
800601a: f8d7 3100 ldr.w r3, [r7, #256] @ 0x100
|
|
800601e: b29b uxth r3, r3
|
|
8006020: 029b lsls r3, r3, #10
|
|
8006022: b29b uxth r3, r3
|
|
8006024: 4313 orrs r3, r2
|
|
8006026: b29a uxth r2, r3
|
|
8006028: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800602a: 801a strh r2, [r3, #0]
|
|
800602c: e024 b.n 8006078 <USB_EPStartXfer+0x318>
|
|
800602e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006032: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006036: 681b ldr r3, [r3, #0]
|
|
8006038: 785b ldrb r3, [r3, #1]
|
|
800603a: 2b01 cmp r3, #1
|
|
800603c: d11c bne.n 8006078 <USB_EPStartXfer+0x318>
|
|
800603e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006042: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006046: 681b ldr r3, [r3, #0]
|
|
8006048: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800604c: b29b uxth r3, r3
|
|
800604e: 461a mov r2, r3
|
|
8006050: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006052: 4413 add r3, r2
|
|
8006054: 633b str r3, [r7, #48] @ 0x30
|
|
8006056: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800605a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800605e: 681b ldr r3, [r3, #0]
|
|
8006060: 781b ldrb r3, [r3, #0]
|
|
8006062: 011a lsls r2, r3, #4
|
|
8006064: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006066: 4413 add r3, r2
|
|
8006068: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
800606c: 62fb str r3, [r7, #44] @ 0x2c
|
|
800606e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006072: b29a uxth r2, r3
|
|
8006074: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006076: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr1;
|
|
8006078: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800607c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006080: 681b ldr r3, [r3, #0]
|
|
8006082: 895b ldrh r3, [r3, #10]
|
|
8006084: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8006088: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800608c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006090: 681b ldr r3, [r3, #0]
|
|
8006092: 6959 ldr r1, [r3, #20]
|
|
8006094: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006098: b29b uxth r3, r3
|
|
800609a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
800609e: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
80060a2: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
80060a6: 6800 ldr r0, [r0, #0]
|
|
80060a8: f001 fb49 bl 800773e <USB_WritePMA>
|
|
ep->xfer_buff += len;
|
|
80060ac: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80060b0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80060b4: 681b ldr r3, [r3, #0]
|
|
80060b6: 695a ldr r2, [r3, #20]
|
|
80060b8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80060bc: 441a add r2, r3
|
|
80060be: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80060c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80060c6: 681b ldr r3, [r3, #0]
|
|
80060c8: 615a str r2, [r3, #20]
|
|
|
|
if (ep->xfer_len_db > ep->maxpacket)
|
|
80060ca: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80060ce: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80060d2: 681b ldr r3, [r3, #0]
|
|
80060d4: 6a1a ldr r2, [r3, #32]
|
|
80060d6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80060da: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80060de: 681b ldr r3, [r3, #0]
|
|
80060e0: 691b ldr r3, [r3, #16]
|
|
80060e2: 429a cmp r2, r3
|
|
80060e4: d90f bls.n 8006106 <USB_EPStartXfer+0x3a6>
|
|
{
|
|
ep->xfer_len_db -= len;
|
|
80060e6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80060ea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80060ee: 681b ldr r3, [r3, #0]
|
|
80060f0: 6a1a ldr r2, [r3, #32]
|
|
80060f2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80060f6: 1ad2 subs r2, r2, r3
|
|
80060f8: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80060fc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006100: 681b ldr r3, [r3, #0]
|
|
8006102: 621a str r2, [r3, #32]
|
|
8006104: e00e b.n 8006124 <USB_EPStartXfer+0x3c4>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
8006106: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800610a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800610e: 681b ldr r3, [r3, #0]
|
|
8006110: 6a1b ldr r3, [r3, #32]
|
|
8006112: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
ep->xfer_len_db = 0U;
|
|
8006116: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800611a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800611e: 681b ldr r3, [r3, #0]
|
|
8006120: 2200 movs r2, #0
|
|
8006122: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
/* Set the Double buffer counter for pmabuffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
|
8006124: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006128: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800612c: 681b ldr r3, [r3, #0]
|
|
800612e: 785b ldrb r3, [r3, #1]
|
|
8006130: 2b00 cmp r3, #0
|
|
8006132: d177 bne.n 8006224 <USB_EPStartXfer+0x4c4>
|
|
8006134: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006138: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800613c: 681b ldr r3, [r3, #0]
|
|
800613e: 61bb str r3, [r7, #24]
|
|
8006140: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006144: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006148: 681b ldr r3, [r3, #0]
|
|
800614a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800614e: b29b uxth r3, r3
|
|
8006150: 461a mov r2, r3
|
|
8006152: 69bb ldr r3, [r7, #24]
|
|
8006154: 4413 add r3, r2
|
|
8006156: 61bb str r3, [r7, #24]
|
|
8006158: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800615c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006160: 681b ldr r3, [r3, #0]
|
|
8006162: 781b ldrb r3, [r3, #0]
|
|
8006164: 011a lsls r2, r3, #4
|
|
8006166: 69bb ldr r3, [r7, #24]
|
|
8006168: 4413 add r3, r2
|
|
800616a: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800616e: 617b str r3, [r7, #20]
|
|
8006170: 697b ldr r3, [r7, #20]
|
|
8006172: 881b ldrh r3, [r3, #0]
|
|
8006174: b29b uxth r3, r3
|
|
8006176: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800617a: b29a uxth r2, r3
|
|
800617c: 697b ldr r3, [r7, #20]
|
|
800617e: 801a strh r2, [r3, #0]
|
|
8006180: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006184: 2b3e cmp r3, #62 @ 0x3e
|
|
8006186: d921 bls.n 80061cc <USB_EPStartXfer+0x46c>
|
|
8006188: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800618c: 095b lsrs r3, r3, #5
|
|
800618e: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
|
|
8006192: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006196: f003 031f and.w r3, r3, #31
|
|
800619a: 2b00 cmp r3, #0
|
|
800619c: d104 bne.n 80061a8 <USB_EPStartXfer+0x448>
|
|
800619e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80061a2: 3b01 subs r3, #1
|
|
80061a4: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
|
|
80061a8: 697b ldr r3, [r7, #20]
|
|
80061aa: 881b ldrh r3, [r3, #0]
|
|
80061ac: b29a uxth r2, r3
|
|
80061ae: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80061b2: b29b uxth r3, r3
|
|
80061b4: 029b lsls r3, r3, #10
|
|
80061b6: b29b uxth r3, r3
|
|
80061b8: 4313 orrs r3, r2
|
|
80061ba: b29b uxth r3, r3
|
|
80061bc: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80061c0: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80061c4: b29a uxth r2, r3
|
|
80061c6: 697b ldr r3, [r7, #20]
|
|
80061c8: 801a strh r2, [r3, #0]
|
|
80061ca: e056 b.n 800627a <USB_EPStartXfer+0x51a>
|
|
80061cc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80061d0: 2b00 cmp r3, #0
|
|
80061d2: d10a bne.n 80061ea <USB_EPStartXfer+0x48a>
|
|
80061d4: 697b ldr r3, [r7, #20]
|
|
80061d6: 881b ldrh r3, [r3, #0]
|
|
80061d8: b29b uxth r3, r3
|
|
80061da: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80061de: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80061e2: b29a uxth r2, r3
|
|
80061e4: 697b ldr r3, [r7, #20]
|
|
80061e6: 801a strh r2, [r3, #0]
|
|
80061e8: e047 b.n 800627a <USB_EPStartXfer+0x51a>
|
|
80061ea: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80061ee: 085b lsrs r3, r3, #1
|
|
80061f0: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
|
|
80061f4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80061f8: f003 0301 and.w r3, r3, #1
|
|
80061fc: 2b00 cmp r3, #0
|
|
80061fe: d004 beq.n 800620a <USB_EPStartXfer+0x4aa>
|
|
8006200: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006204: 3301 adds r3, #1
|
|
8006206: f8c7 30fc str.w r3, [r7, #252] @ 0xfc
|
|
800620a: 697b ldr r3, [r7, #20]
|
|
800620c: 881b ldrh r3, [r3, #0]
|
|
800620e: b29a uxth r2, r3
|
|
8006210: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006214: b29b uxth r3, r3
|
|
8006216: 029b lsls r3, r3, #10
|
|
8006218: b29b uxth r3, r3
|
|
800621a: 4313 orrs r3, r2
|
|
800621c: b29a uxth r2, r3
|
|
800621e: 697b ldr r3, [r7, #20]
|
|
8006220: 801a strh r2, [r3, #0]
|
|
8006222: e02a b.n 800627a <USB_EPStartXfer+0x51a>
|
|
8006224: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006228: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800622c: 681b ldr r3, [r3, #0]
|
|
800622e: 785b ldrb r3, [r3, #1]
|
|
8006230: 2b01 cmp r3, #1
|
|
8006232: d122 bne.n 800627a <USB_EPStartXfer+0x51a>
|
|
8006234: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006238: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800623c: 681b ldr r3, [r3, #0]
|
|
800623e: 623b str r3, [r7, #32]
|
|
8006240: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006244: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006248: 681b ldr r3, [r3, #0]
|
|
800624a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800624e: b29b uxth r3, r3
|
|
8006250: 461a mov r2, r3
|
|
8006252: 6a3b ldr r3, [r7, #32]
|
|
8006254: 4413 add r3, r2
|
|
8006256: 623b str r3, [r7, #32]
|
|
8006258: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800625c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006260: 681b ldr r3, [r3, #0]
|
|
8006262: 781b ldrb r3, [r3, #0]
|
|
8006264: 011a lsls r2, r3, #4
|
|
8006266: 6a3b ldr r3, [r7, #32]
|
|
8006268: 4413 add r3, r2
|
|
800626a: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800626e: 61fb str r3, [r7, #28]
|
|
8006270: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006274: b29a uxth r2, r3
|
|
8006276: 69fb ldr r3, [r7, #28]
|
|
8006278: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
800627a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800627e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006282: 681b ldr r3, [r3, #0]
|
|
8006284: 891b ldrh r3, [r3, #8]
|
|
8006286: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
800628a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800628e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006292: 681b ldr r3, [r3, #0]
|
|
8006294: 6959 ldr r1, [r3, #20]
|
|
8006296: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800629a: b29b uxth r3, r3
|
|
800629c: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
80062a0: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
80062a4: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
80062a8: 6800 ldr r0, [r0, #0]
|
|
80062aa: f001 fa48 bl 800773e <USB_WritePMA>
|
|
80062ae: e3ee b.n 8006a8e <USB_EPStartXfer+0xd2e>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
|
80062b0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80062b4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80062b8: 681b ldr r3, [r3, #0]
|
|
80062ba: 785b ldrb r3, [r3, #1]
|
|
80062bc: 2b00 cmp r3, #0
|
|
80062be: d177 bne.n 80063b0 <USB_EPStartXfer+0x650>
|
|
80062c0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80062c4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80062c8: 681b ldr r3, [r3, #0]
|
|
80062ca: 64bb str r3, [r7, #72] @ 0x48
|
|
80062cc: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80062d0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80062d4: 681b ldr r3, [r3, #0]
|
|
80062d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80062da: b29b uxth r3, r3
|
|
80062dc: 461a mov r2, r3
|
|
80062de: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80062e0: 4413 add r3, r2
|
|
80062e2: 64bb str r3, [r7, #72] @ 0x48
|
|
80062e4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80062e8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80062ec: 681b ldr r3, [r3, #0]
|
|
80062ee: 781b ldrb r3, [r3, #0]
|
|
80062f0: 011a lsls r2, r3, #4
|
|
80062f2: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80062f4: 4413 add r3, r2
|
|
80062f6: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
80062fa: 647b str r3, [r7, #68] @ 0x44
|
|
80062fc: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80062fe: 881b ldrh r3, [r3, #0]
|
|
8006300: b29b uxth r3, r3
|
|
8006302: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8006306: b29a uxth r2, r3
|
|
8006308: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800630a: 801a strh r2, [r3, #0]
|
|
800630c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006310: 2b3e cmp r3, #62 @ 0x3e
|
|
8006312: d921 bls.n 8006358 <USB_EPStartXfer+0x5f8>
|
|
8006314: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006318: 095b lsrs r3, r3, #5
|
|
800631a: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
800631e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006322: f003 031f and.w r3, r3, #31
|
|
8006326: 2b00 cmp r3, #0
|
|
8006328: d104 bne.n 8006334 <USB_EPStartXfer+0x5d4>
|
|
800632a: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
800632e: 3b01 subs r3, #1
|
|
8006330: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
8006334: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006336: 881b ldrh r3, [r3, #0]
|
|
8006338: b29a uxth r2, r3
|
|
800633a: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
800633e: b29b uxth r3, r3
|
|
8006340: 029b lsls r3, r3, #10
|
|
8006342: b29b uxth r3, r3
|
|
8006344: 4313 orrs r3, r2
|
|
8006346: b29b uxth r3, r3
|
|
8006348: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800634c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006350: b29a uxth r2, r3
|
|
8006352: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006354: 801a strh r2, [r3, #0]
|
|
8006356: e056 b.n 8006406 <USB_EPStartXfer+0x6a6>
|
|
8006358: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800635c: 2b00 cmp r3, #0
|
|
800635e: d10a bne.n 8006376 <USB_EPStartXfer+0x616>
|
|
8006360: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006362: 881b ldrh r3, [r3, #0]
|
|
8006364: b29b uxth r3, r3
|
|
8006366: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800636a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800636e: b29a uxth r2, r3
|
|
8006370: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006372: 801a strh r2, [r3, #0]
|
|
8006374: e047 b.n 8006406 <USB_EPStartXfer+0x6a6>
|
|
8006376: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800637a: 085b lsrs r3, r3, #1
|
|
800637c: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
8006380: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006384: f003 0301 and.w r3, r3, #1
|
|
8006388: 2b00 cmp r3, #0
|
|
800638a: d004 beq.n 8006396 <USB_EPStartXfer+0x636>
|
|
800638c: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
8006390: 3301 adds r3, #1
|
|
8006392: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
8006396: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006398: 881b ldrh r3, [r3, #0]
|
|
800639a: b29a uxth r2, r3
|
|
800639c: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
80063a0: b29b uxth r3, r3
|
|
80063a2: 029b lsls r3, r3, #10
|
|
80063a4: b29b uxth r3, r3
|
|
80063a6: 4313 orrs r3, r2
|
|
80063a8: b29a uxth r2, r3
|
|
80063aa: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80063ac: 801a strh r2, [r3, #0]
|
|
80063ae: e02a b.n 8006406 <USB_EPStartXfer+0x6a6>
|
|
80063b0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80063b4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80063b8: 681b ldr r3, [r3, #0]
|
|
80063ba: 785b ldrb r3, [r3, #1]
|
|
80063bc: 2b01 cmp r3, #1
|
|
80063be: d122 bne.n 8006406 <USB_EPStartXfer+0x6a6>
|
|
80063c0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80063c4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80063c8: 681b ldr r3, [r3, #0]
|
|
80063ca: 653b str r3, [r7, #80] @ 0x50
|
|
80063cc: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80063d0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80063d4: 681b ldr r3, [r3, #0]
|
|
80063d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80063da: b29b uxth r3, r3
|
|
80063dc: 461a mov r2, r3
|
|
80063de: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80063e0: 4413 add r3, r2
|
|
80063e2: 653b str r3, [r7, #80] @ 0x50
|
|
80063e4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80063e8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80063ec: 681b ldr r3, [r3, #0]
|
|
80063ee: 781b ldrb r3, [r3, #0]
|
|
80063f0: 011a lsls r2, r3, #4
|
|
80063f2: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80063f4: 4413 add r3, r2
|
|
80063f6: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
80063fa: 64fb str r3, [r7, #76] @ 0x4c
|
|
80063fc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006400: b29a uxth r2, r3
|
|
8006402: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006404: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
8006406: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800640a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800640e: 681b ldr r3, [r3, #0]
|
|
8006410: 891b ldrh r3, [r3, #8]
|
|
8006412: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8006416: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800641a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800641e: 681b ldr r3, [r3, #0]
|
|
8006420: 6959 ldr r1, [r3, #20]
|
|
8006422: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006426: b29b uxth r3, r3
|
|
8006428: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
800642c: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
8006430: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
8006434: 6800 ldr r0, [r0, #0]
|
|
8006436: f001 f982 bl 800773e <USB_WritePMA>
|
|
ep->xfer_buff += len;
|
|
800643a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800643e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006442: 681b ldr r3, [r3, #0]
|
|
8006444: 695a ldr r2, [r3, #20]
|
|
8006446: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800644a: 441a add r2, r3
|
|
800644c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006450: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006454: 681b ldr r3, [r3, #0]
|
|
8006456: 615a str r2, [r3, #20]
|
|
|
|
if (ep->xfer_len_db > ep->maxpacket)
|
|
8006458: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800645c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006460: 681b ldr r3, [r3, #0]
|
|
8006462: 6a1a ldr r2, [r3, #32]
|
|
8006464: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006468: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800646c: 681b ldr r3, [r3, #0]
|
|
800646e: 691b ldr r3, [r3, #16]
|
|
8006470: 429a cmp r2, r3
|
|
8006472: d90f bls.n 8006494 <USB_EPStartXfer+0x734>
|
|
{
|
|
ep->xfer_len_db -= len;
|
|
8006474: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006478: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800647c: 681b ldr r3, [r3, #0]
|
|
800647e: 6a1a ldr r2, [r3, #32]
|
|
8006480: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006484: 1ad2 subs r2, r2, r3
|
|
8006486: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800648a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800648e: 681b ldr r3, [r3, #0]
|
|
8006490: 621a str r2, [r3, #32]
|
|
8006492: e00e b.n 80064b2 <USB_EPStartXfer+0x752>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
8006494: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006498: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800649c: 681b ldr r3, [r3, #0]
|
|
800649e: 6a1b ldr r3, [r3, #32]
|
|
80064a0: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
ep->xfer_len_db = 0U;
|
|
80064a4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80064a8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80064ac: 681b ldr r3, [r3, #0]
|
|
80064ae: 2200 movs r2, #0
|
|
80064b0: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
|
80064b2: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80064b6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80064ba: 681b ldr r3, [r3, #0]
|
|
80064bc: 643b str r3, [r7, #64] @ 0x40
|
|
80064be: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80064c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80064c6: 681b ldr r3, [r3, #0]
|
|
80064c8: 785b ldrb r3, [r3, #1]
|
|
80064ca: 2b00 cmp r3, #0
|
|
80064cc: d177 bne.n 80065be <USB_EPStartXfer+0x85e>
|
|
80064ce: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80064d2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80064d6: 681b ldr r3, [r3, #0]
|
|
80064d8: 63bb str r3, [r7, #56] @ 0x38
|
|
80064da: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80064de: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80064e2: 681b ldr r3, [r3, #0]
|
|
80064e4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80064e8: b29b uxth r3, r3
|
|
80064ea: 461a mov r2, r3
|
|
80064ec: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80064ee: 4413 add r3, r2
|
|
80064f0: 63bb str r3, [r7, #56] @ 0x38
|
|
80064f2: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80064f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80064fa: 681b ldr r3, [r3, #0]
|
|
80064fc: 781b ldrb r3, [r3, #0]
|
|
80064fe: 011a lsls r2, r3, #4
|
|
8006500: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006502: 4413 add r3, r2
|
|
8006504: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8006508: 637b str r3, [r7, #52] @ 0x34
|
|
800650a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800650c: 881b ldrh r3, [r3, #0]
|
|
800650e: b29b uxth r3, r3
|
|
8006510: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8006514: b29a uxth r2, r3
|
|
8006516: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006518: 801a strh r2, [r3, #0]
|
|
800651a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800651e: 2b3e cmp r3, #62 @ 0x3e
|
|
8006520: d921 bls.n 8006566 <USB_EPStartXfer+0x806>
|
|
8006522: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006526: 095b lsrs r3, r3, #5
|
|
8006528: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
|
|
800652c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006530: f003 031f and.w r3, r3, #31
|
|
8006534: 2b00 cmp r3, #0
|
|
8006536: d104 bne.n 8006542 <USB_EPStartXfer+0x7e2>
|
|
8006538: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800653c: 3b01 subs r3, #1
|
|
800653e: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
|
|
8006542: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006544: 881b ldrh r3, [r3, #0]
|
|
8006546: b29a uxth r2, r3
|
|
8006548: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800654c: b29b uxth r3, r3
|
|
800654e: 029b lsls r3, r3, #10
|
|
8006550: b29b uxth r3, r3
|
|
8006552: 4313 orrs r3, r2
|
|
8006554: b29b uxth r3, r3
|
|
8006556: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800655a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800655e: b29a uxth r2, r3
|
|
8006560: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006562: 801a strh r2, [r3, #0]
|
|
8006564: e050 b.n 8006608 <USB_EPStartXfer+0x8a8>
|
|
8006566: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800656a: 2b00 cmp r3, #0
|
|
800656c: d10a bne.n 8006584 <USB_EPStartXfer+0x824>
|
|
800656e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006570: 881b ldrh r3, [r3, #0]
|
|
8006572: b29b uxth r3, r3
|
|
8006574: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006578: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800657c: b29a uxth r2, r3
|
|
800657e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006580: 801a strh r2, [r3, #0]
|
|
8006582: e041 b.n 8006608 <USB_EPStartXfer+0x8a8>
|
|
8006584: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006588: 085b lsrs r3, r3, #1
|
|
800658a: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
|
|
800658e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006592: f003 0301 and.w r3, r3, #1
|
|
8006596: 2b00 cmp r3, #0
|
|
8006598: d004 beq.n 80065a4 <USB_EPStartXfer+0x844>
|
|
800659a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800659e: 3301 adds r3, #1
|
|
80065a0: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4
|
|
80065a4: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80065a6: 881b ldrh r3, [r3, #0]
|
|
80065a8: b29a uxth r2, r3
|
|
80065aa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80065ae: b29b uxth r3, r3
|
|
80065b0: 029b lsls r3, r3, #10
|
|
80065b2: b29b uxth r3, r3
|
|
80065b4: 4313 orrs r3, r2
|
|
80065b6: b29a uxth r2, r3
|
|
80065b8: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80065ba: 801a strh r2, [r3, #0]
|
|
80065bc: e024 b.n 8006608 <USB_EPStartXfer+0x8a8>
|
|
80065be: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80065c2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80065c6: 681b ldr r3, [r3, #0]
|
|
80065c8: 785b ldrb r3, [r3, #1]
|
|
80065ca: 2b01 cmp r3, #1
|
|
80065cc: d11c bne.n 8006608 <USB_EPStartXfer+0x8a8>
|
|
80065ce: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80065d2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80065d6: 681b ldr r3, [r3, #0]
|
|
80065d8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80065dc: b29b uxth r3, r3
|
|
80065de: 461a mov r2, r3
|
|
80065e0: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80065e2: 4413 add r3, r2
|
|
80065e4: 643b str r3, [r7, #64] @ 0x40
|
|
80065e6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80065ea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80065ee: 681b ldr r3, [r3, #0]
|
|
80065f0: 781b ldrb r3, [r3, #0]
|
|
80065f2: 011a lsls r2, r3, #4
|
|
80065f4: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80065f6: 4413 add r3, r2
|
|
80065f8: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
80065fc: 63fb str r3, [r7, #60] @ 0x3c
|
|
80065fe: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006602: b29a uxth r2, r3
|
|
8006604: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006606: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr1;
|
|
8006608: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800660c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006610: 681b ldr r3, [r3, #0]
|
|
8006612: 895b ldrh r3, [r3, #10]
|
|
8006614: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8006618: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800661c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006620: 681b ldr r3, [r3, #0]
|
|
8006622: 6959 ldr r1, [r3, #20]
|
|
8006624: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006628: b29b uxth r3, r3
|
|
800662a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
800662e: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
8006632: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
8006636: 6800 ldr r0, [r0, #0]
|
|
8006638: f001 f881 bl 800773e <USB_WritePMA>
|
|
800663c: e227 b.n 8006a8e <USB_EPStartXfer+0xd2e>
|
|
}
|
|
}
|
|
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
800663e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006642: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006646: 681b ldr r3, [r3, #0]
|
|
8006648: 6a1b ldr r3, [r3, #32]
|
|
800664a: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
|
|
/* disable double buffer mode for Bulk endpoint */
|
|
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
|
|
800664e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006652: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006656: 681a ldr r2, [r3, #0]
|
|
8006658: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800665c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006660: 681b ldr r3, [r3, #0]
|
|
8006662: 781b ldrb r3, [r3, #0]
|
|
8006664: 009b lsls r3, r3, #2
|
|
8006666: 4413 add r3, r2
|
|
8006668: 881b ldrh r3, [r3, #0]
|
|
800666a: b29b uxth r3, r3
|
|
800666c: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
|
|
8006670: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8006674: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
|
|
8006678: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800667c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006680: 681a ldr r2, [r3, #0]
|
|
8006682: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006686: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800668a: 681b ldr r3, [r3, #0]
|
|
800668c: 781b ldrb r3, [r3, #0]
|
|
800668e: 009b lsls r3, r3, #2
|
|
8006690: 441a add r2, r3
|
|
8006692: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
|
|
8006696: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800669a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800669e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80066a2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80066a6: b29b uxth r3, r3
|
|
80066a8: 8013 strh r3, [r2, #0]
|
|
|
|
/* Set Tx count with nbre of byte to be transmitted */
|
|
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
|
|
80066aa: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80066ae: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80066b2: 681b ldr r3, [r3, #0]
|
|
80066b4: 65fb str r3, [r7, #92] @ 0x5c
|
|
80066b6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80066ba: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80066be: 681b ldr r3, [r3, #0]
|
|
80066c0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80066c4: b29b uxth r3, r3
|
|
80066c6: 461a mov r2, r3
|
|
80066c8: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80066ca: 4413 add r3, r2
|
|
80066cc: 65fb str r3, [r7, #92] @ 0x5c
|
|
80066ce: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80066d2: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80066d6: 681b ldr r3, [r3, #0]
|
|
80066d8: 781b ldrb r3, [r3, #0]
|
|
80066da: 011a lsls r2, r3, #4
|
|
80066dc: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80066de: 4413 add r3, r2
|
|
80066e0: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
80066e4: 65bb str r3, [r7, #88] @ 0x58
|
|
80066e6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80066ea: b29a uxth r2, r3
|
|
80066ec: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80066ee: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
80066f0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80066f4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80066f8: 681b ldr r3, [r3, #0]
|
|
80066fa: 891b ldrh r3, [r3, #8]
|
|
80066fc: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8006700: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006704: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006708: 681b ldr r3, [r3, #0]
|
|
800670a: 6959 ldr r1, [r3, #20]
|
|
800670c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006710: b29b uxth r3, r3
|
|
8006712: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
8006716: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
800671a: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
800671e: 6800 ldr r0, [r0, #0]
|
|
8006720: f001 f80d bl 800773e <USB_WritePMA>
|
|
8006724: e1b3 b.n 8006a8e <USB_EPStartXfer+0xd2e>
|
|
}
|
|
}
|
|
else /* manage isochronous double buffer IN mode */
|
|
{
|
|
/* each Time to write in PMA xfer_len_db will */
|
|
ep->xfer_len_db -= len;
|
|
8006726: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800672a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800672e: 681b ldr r3, [r3, #0]
|
|
8006730: 6a1a ldr r2, [r3, #32]
|
|
8006732: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006736: 1ad2 subs r2, r2, r3
|
|
8006738: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800673c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006740: 681b ldr r3, [r3, #0]
|
|
8006742: 621a str r2, [r3, #32]
|
|
|
|
/* Fill the data buffer */
|
|
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
|
|
8006744: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006748: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800674c: 681a ldr r2, [r3, #0]
|
|
800674e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006752: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006756: 681b ldr r3, [r3, #0]
|
|
8006758: 781b ldrb r3, [r3, #0]
|
|
800675a: 009b lsls r3, r3, #2
|
|
800675c: 4413 add r3, r2
|
|
800675e: 881b ldrh r3, [r3, #0]
|
|
8006760: b29b uxth r3, r3
|
|
8006762: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006766: 2b00 cmp r3, #0
|
|
8006768: f000 80c6 beq.w 80068f8 <USB_EPStartXfer+0xb98>
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
|
800676c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006770: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006774: 681b ldr r3, [r3, #0]
|
|
8006776: 673b str r3, [r7, #112] @ 0x70
|
|
8006778: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800677c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006780: 681b ldr r3, [r3, #0]
|
|
8006782: 785b ldrb r3, [r3, #1]
|
|
8006784: 2b00 cmp r3, #0
|
|
8006786: d177 bne.n 8006878 <USB_EPStartXfer+0xb18>
|
|
8006788: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800678c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006790: 681b ldr r3, [r3, #0]
|
|
8006792: 66bb str r3, [r7, #104] @ 0x68
|
|
8006794: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006798: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800679c: 681b ldr r3, [r3, #0]
|
|
800679e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80067a2: b29b uxth r3, r3
|
|
80067a4: 461a mov r2, r3
|
|
80067a6: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80067a8: 4413 add r3, r2
|
|
80067aa: 66bb str r3, [r7, #104] @ 0x68
|
|
80067ac: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80067b0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80067b4: 681b ldr r3, [r3, #0]
|
|
80067b6: 781b ldrb r3, [r3, #0]
|
|
80067b8: 011a lsls r2, r3, #4
|
|
80067ba: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80067bc: 4413 add r3, r2
|
|
80067be: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
80067c2: 667b str r3, [r7, #100] @ 0x64
|
|
80067c4: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80067c6: 881b ldrh r3, [r3, #0]
|
|
80067c8: b29b uxth r3, r3
|
|
80067ca: f3c3 0309 ubfx r3, r3, #0, #10
|
|
80067ce: b29a uxth r2, r3
|
|
80067d0: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80067d2: 801a strh r2, [r3, #0]
|
|
80067d4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80067d8: 2b3e cmp r3, #62 @ 0x3e
|
|
80067da: d921 bls.n 8006820 <USB_EPStartXfer+0xac0>
|
|
80067dc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80067e0: 095b lsrs r3, r3, #5
|
|
80067e2: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
|
|
80067e6: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80067ea: f003 031f and.w r3, r3, #31
|
|
80067ee: 2b00 cmp r3, #0
|
|
80067f0: d104 bne.n 80067fc <USB_EPStartXfer+0xa9c>
|
|
80067f2: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
|
|
80067f6: 3b01 subs r3, #1
|
|
80067f8: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
|
|
80067fc: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80067fe: 881b ldrh r3, [r3, #0]
|
|
8006800: b29a uxth r2, r3
|
|
8006802: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
|
|
8006806: b29b uxth r3, r3
|
|
8006808: 029b lsls r3, r3, #10
|
|
800680a: b29b uxth r3, r3
|
|
800680c: 4313 orrs r3, r2
|
|
800680e: b29b uxth r3, r3
|
|
8006810: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006814: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006818: b29a uxth r2, r3
|
|
800681a: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800681c: 801a strh r2, [r3, #0]
|
|
800681e: e050 b.n 80068c2 <USB_EPStartXfer+0xb62>
|
|
8006820: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006824: 2b00 cmp r3, #0
|
|
8006826: d10a bne.n 800683e <USB_EPStartXfer+0xade>
|
|
8006828: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800682a: 881b ldrh r3, [r3, #0]
|
|
800682c: b29b uxth r3, r3
|
|
800682e: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006832: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006836: b29a uxth r2, r3
|
|
8006838: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800683a: 801a strh r2, [r3, #0]
|
|
800683c: e041 b.n 80068c2 <USB_EPStartXfer+0xb62>
|
|
800683e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006842: 085b lsrs r3, r3, #1
|
|
8006844: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
|
|
8006848: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800684c: f003 0301 and.w r3, r3, #1
|
|
8006850: 2b00 cmp r3, #0
|
|
8006852: d004 beq.n 800685e <USB_EPStartXfer+0xafe>
|
|
8006854: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
|
|
8006858: 3301 adds r3, #1
|
|
800685a: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0
|
|
800685e: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8006860: 881b ldrh r3, [r3, #0]
|
|
8006862: b29a uxth r2, r3
|
|
8006864: f8d7 30f0 ldr.w r3, [r7, #240] @ 0xf0
|
|
8006868: b29b uxth r3, r3
|
|
800686a: 029b lsls r3, r3, #10
|
|
800686c: b29b uxth r3, r3
|
|
800686e: 4313 orrs r3, r2
|
|
8006870: b29a uxth r2, r3
|
|
8006872: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8006874: 801a strh r2, [r3, #0]
|
|
8006876: e024 b.n 80068c2 <USB_EPStartXfer+0xb62>
|
|
8006878: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800687c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006880: 681b ldr r3, [r3, #0]
|
|
8006882: 785b ldrb r3, [r3, #1]
|
|
8006884: 2b01 cmp r3, #1
|
|
8006886: d11c bne.n 80068c2 <USB_EPStartXfer+0xb62>
|
|
8006888: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800688c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006890: 681b ldr r3, [r3, #0]
|
|
8006892: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006896: b29b uxth r3, r3
|
|
8006898: 461a mov r2, r3
|
|
800689a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800689c: 4413 add r3, r2
|
|
800689e: 673b str r3, [r7, #112] @ 0x70
|
|
80068a0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80068a4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80068a8: 681b ldr r3, [r3, #0]
|
|
80068aa: 781b ldrb r3, [r3, #0]
|
|
80068ac: 011a lsls r2, r3, #4
|
|
80068ae: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80068b0: 4413 add r3, r2
|
|
80068b2: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
80068b6: 66fb str r3, [r7, #108] @ 0x6c
|
|
80068b8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80068bc: b29a uxth r2, r3
|
|
80068be: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80068c0: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr1;
|
|
80068c2: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80068c6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80068ca: 681b ldr r3, [r3, #0]
|
|
80068cc: 895b ldrh r3, [r3, #10]
|
|
80068ce: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
80068d2: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80068d6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80068da: 681b ldr r3, [r3, #0]
|
|
80068dc: 6959 ldr r1, [r3, #20]
|
|
80068de: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80068e2: b29b uxth r3, r3
|
|
80068e4: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
80068e8: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
80068ec: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
80068f0: 6800 ldr r0, [r0, #0]
|
|
80068f2: f000 ff24 bl 800773e <USB_WritePMA>
|
|
80068f6: e0ca b.n 8006a8e <USB_EPStartXfer+0xd2e>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
|
80068f8: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80068fc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006900: 681b ldr r3, [r3, #0]
|
|
8006902: 785b ldrb r3, [r3, #1]
|
|
8006904: 2b00 cmp r3, #0
|
|
8006906: d177 bne.n 80069f8 <USB_EPStartXfer+0xc98>
|
|
8006908: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800690c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006910: 681b ldr r3, [r3, #0]
|
|
8006912: 67fb str r3, [r7, #124] @ 0x7c
|
|
8006914: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006918: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800691c: 681b ldr r3, [r3, #0]
|
|
800691e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006922: b29b uxth r3, r3
|
|
8006924: 461a mov r2, r3
|
|
8006926: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
8006928: 4413 add r3, r2
|
|
800692a: 67fb str r3, [r7, #124] @ 0x7c
|
|
800692c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006930: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006934: 681b ldr r3, [r3, #0]
|
|
8006936: 781b ldrb r3, [r3, #0]
|
|
8006938: 011a lsls r2, r3, #4
|
|
800693a: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
800693c: 4413 add r3, r2
|
|
800693e: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8006942: 67bb str r3, [r7, #120] @ 0x78
|
|
8006944: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8006946: 881b ldrh r3, [r3, #0]
|
|
8006948: b29b uxth r3, r3
|
|
800694a: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800694e: b29a uxth r2, r3
|
|
8006950: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8006952: 801a strh r2, [r3, #0]
|
|
8006954: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006958: 2b3e cmp r3, #62 @ 0x3e
|
|
800695a: d921 bls.n 80069a0 <USB_EPStartXfer+0xc40>
|
|
800695c: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006960: 095b lsrs r3, r3, #5
|
|
8006962: f8c7 30ec str.w r3, [r7, #236] @ 0xec
|
|
8006966: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800696a: f003 031f and.w r3, r3, #31
|
|
800696e: 2b00 cmp r3, #0
|
|
8006970: d104 bne.n 800697c <USB_EPStartXfer+0xc1c>
|
|
8006972: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
|
|
8006976: 3b01 subs r3, #1
|
|
8006978: f8c7 30ec str.w r3, [r7, #236] @ 0xec
|
|
800697c: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800697e: 881b ldrh r3, [r3, #0]
|
|
8006980: b29a uxth r2, r3
|
|
8006982: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
|
|
8006986: b29b uxth r3, r3
|
|
8006988: 029b lsls r3, r3, #10
|
|
800698a: b29b uxth r3, r3
|
|
800698c: 4313 orrs r3, r2
|
|
800698e: b29b uxth r3, r3
|
|
8006990: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006994: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006998: b29a uxth r2, r3
|
|
800699a: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800699c: 801a strh r2, [r3, #0]
|
|
800699e: e05c b.n 8006a5a <USB_EPStartXfer+0xcfa>
|
|
80069a0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80069a4: 2b00 cmp r3, #0
|
|
80069a6: d10a bne.n 80069be <USB_EPStartXfer+0xc5e>
|
|
80069a8: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80069aa: 881b ldrh r3, [r3, #0]
|
|
80069ac: b29b uxth r3, r3
|
|
80069ae: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80069b2: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80069b6: b29a uxth r2, r3
|
|
80069b8: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80069ba: 801a strh r2, [r3, #0]
|
|
80069bc: e04d b.n 8006a5a <USB_EPStartXfer+0xcfa>
|
|
80069be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80069c2: 085b lsrs r3, r3, #1
|
|
80069c4: f8c7 30ec str.w r3, [r7, #236] @ 0xec
|
|
80069c8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80069cc: f003 0301 and.w r3, r3, #1
|
|
80069d0: 2b00 cmp r3, #0
|
|
80069d2: d004 beq.n 80069de <USB_EPStartXfer+0xc7e>
|
|
80069d4: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
|
|
80069d8: 3301 adds r3, #1
|
|
80069da: f8c7 30ec str.w r3, [r7, #236] @ 0xec
|
|
80069de: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80069e0: 881b ldrh r3, [r3, #0]
|
|
80069e2: b29a uxth r2, r3
|
|
80069e4: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec
|
|
80069e8: b29b uxth r3, r3
|
|
80069ea: 029b lsls r3, r3, #10
|
|
80069ec: b29b uxth r3, r3
|
|
80069ee: 4313 orrs r3, r2
|
|
80069f0: b29a uxth r2, r3
|
|
80069f2: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80069f4: 801a strh r2, [r3, #0]
|
|
80069f6: e030 b.n 8006a5a <USB_EPStartXfer+0xcfa>
|
|
80069f8: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80069fc: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006a00: 681b ldr r3, [r3, #0]
|
|
8006a02: 785b ldrb r3, [r3, #1]
|
|
8006a04: 2b01 cmp r3, #1
|
|
8006a06: d128 bne.n 8006a5a <USB_EPStartXfer+0xcfa>
|
|
8006a08: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a0c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006a10: 681b ldr r3, [r3, #0]
|
|
8006a12: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8006a16: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a1a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006a1e: 681b ldr r3, [r3, #0]
|
|
8006a20: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006a24: b29b uxth r3, r3
|
|
8006a26: 461a mov r2, r3
|
|
8006a28: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8006a2c: 4413 add r3, r2
|
|
8006a2e: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8006a32: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a36: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006a3a: 681b ldr r3, [r3, #0]
|
|
8006a3c: 781b ldrb r3, [r3, #0]
|
|
8006a3e: 011a lsls r2, r3, #4
|
|
8006a40: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8006a44: 4413 add r3, r2
|
|
8006a46: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8006a4a: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8006a4e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006a52: b29a uxth r2, r3
|
|
8006a54: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8006a58: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
8006a5a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a5e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006a62: 681b ldr r3, [r3, #0]
|
|
8006a64: 891b ldrh r3, [r3, #8]
|
|
8006a66: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8006a6a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a6e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006a72: 681b ldr r3, [r3, #0]
|
|
8006a74: 6959 ldr r1, [r3, #20]
|
|
8006a76: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006a7a: b29b uxth r3, r3
|
|
8006a7c: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
8006a80: f507 7084 add.w r0, r7, #264 @ 0x108
|
|
8006a84: f5a0 7082 sub.w r0, r0, #260 @ 0x104
|
|
8006a88: 6800 ldr r0, [r0, #0]
|
|
8006a8a: f000 fe58 bl 800773e <USB_WritePMA>
|
|
}
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
|
|
8006a8e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a92: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006a96: 681a ldr r2, [r3, #0]
|
|
8006a98: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006a9c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006aa0: 681b ldr r3, [r3, #0]
|
|
8006aa2: 781b ldrb r3, [r3, #0]
|
|
8006aa4: 009b lsls r3, r3, #2
|
|
8006aa6: 4413 add r3, r2
|
|
8006aa8: 881b ldrh r3, [r3, #0]
|
|
8006aaa: b29b uxth r3, r3
|
|
8006aac: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8006ab0: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8006ab4: 817b strh r3, [r7, #10]
|
|
8006ab6: 897b ldrh r3, [r7, #10]
|
|
8006ab8: f083 0310 eor.w r3, r3, #16
|
|
8006abc: 817b strh r3, [r7, #10]
|
|
8006abe: 897b ldrh r3, [r7, #10]
|
|
8006ac0: f083 0320 eor.w r3, r3, #32
|
|
8006ac4: 817b strh r3, [r7, #10]
|
|
8006ac6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006aca: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006ace: 681a ldr r2, [r3, #0]
|
|
8006ad0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006ad4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006ad8: 681b ldr r3, [r3, #0]
|
|
8006ada: 781b ldrb r3, [r3, #0]
|
|
8006adc: 009b lsls r3, r3, #2
|
|
8006ade: 441a add r2, r3
|
|
8006ae0: 897b ldrh r3, [r7, #10]
|
|
8006ae2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8006ae6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8006aea: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8006aee: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8006af2: b29b uxth r3, r3
|
|
8006af4: 8013 strh r3, [r2, #0]
|
|
8006af6: f000 bcde b.w 80074b6 <USB_EPStartXfer+0x1756>
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (ep->doublebuffer == 0U)
|
|
8006afa: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006afe: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b02: 681b ldr r3, [r3, #0]
|
|
8006b04: 7b1b ldrb r3, [r3, #12]
|
|
8006b06: 2b00 cmp r3, #0
|
|
8006b08: f040 80bb bne.w 8006c82 <USB_EPStartXfer+0xf22>
|
|
{
|
|
/* Multi packet transfer */
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
8006b0c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b10: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b14: 681b ldr r3, [r3, #0]
|
|
8006b16: 699a ldr r2, [r3, #24]
|
|
8006b18: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b1c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b20: 681b ldr r3, [r3, #0]
|
|
8006b22: 691b ldr r3, [r3, #16]
|
|
8006b24: 429a cmp r2, r3
|
|
8006b26: d917 bls.n 8006b58 <USB_EPStartXfer+0xdf8>
|
|
{
|
|
len = ep->maxpacket;
|
|
8006b28: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b2c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b30: 681b ldr r3, [r3, #0]
|
|
8006b32: 691b ldr r3, [r3, #16]
|
|
8006b34: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
ep->xfer_len -= len;
|
|
8006b38: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b3c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b40: 681b ldr r3, [r3, #0]
|
|
8006b42: 699a ldr r2, [r3, #24]
|
|
8006b44: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006b48: 1ad2 subs r2, r2, r3
|
|
8006b4a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b4e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b52: 681b ldr r3, [r3, #0]
|
|
8006b54: 619a str r2, [r3, #24]
|
|
8006b56: e00e b.n 8006b76 <USB_EPStartXfer+0xe16>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len;
|
|
8006b58: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b5c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b60: 681b ldr r3, [r3, #0]
|
|
8006b62: 699b ldr r3, [r3, #24]
|
|
8006b64: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
ep->xfer_len = 0U;
|
|
8006b68: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b6c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006b70: 681b ldr r3, [r3, #0]
|
|
8006b72: 2200 movs r2, #0
|
|
8006b74: 619a str r2, [r3, #24]
|
|
}
|
|
/* configure and validate Rx endpoint */
|
|
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
|
|
8006b76: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b7a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006b7e: 681b ldr r3, [r3, #0]
|
|
8006b80: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8006b84: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006b88: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006b8c: 681b ldr r3, [r3, #0]
|
|
8006b8e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006b92: b29b uxth r3, r3
|
|
8006b94: 461a mov r2, r3
|
|
8006b96: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8006b9a: 4413 add r3, r2
|
|
8006b9c: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8006ba0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006ba4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006ba8: 681b ldr r3, [r3, #0]
|
|
8006baa: 781b ldrb r3, [r3, #0]
|
|
8006bac: 011a lsls r2, r3, #4
|
|
8006bae: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8006bb2: 4413 add r3, r2
|
|
8006bb4: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8006bb8: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
8006bbc: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006bc0: 881b ldrh r3, [r3, #0]
|
|
8006bc2: b29b uxth r3, r3
|
|
8006bc4: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8006bc8: b29a uxth r2, r3
|
|
8006bca: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006bce: 801a strh r2, [r3, #0]
|
|
8006bd0: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006bd4: 2b3e cmp r3, #62 @ 0x3e
|
|
8006bd6: d924 bls.n 8006c22 <USB_EPStartXfer+0xec2>
|
|
8006bd8: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006bdc: 095b lsrs r3, r3, #5
|
|
8006bde: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006be2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006be6: f003 031f and.w r3, r3, #31
|
|
8006bea: 2b00 cmp r3, #0
|
|
8006bec: d104 bne.n 8006bf8 <USB_EPStartXfer+0xe98>
|
|
8006bee: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
|
|
8006bf2: 3b01 subs r3, #1
|
|
8006bf4: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006bf8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006bfc: 881b ldrh r3, [r3, #0]
|
|
8006bfe: b29a uxth r2, r3
|
|
8006c00: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
|
|
8006c04: b29b uxth r3, r3
|
|
8006c06: 029b lsls r3, r3, #10
|
|
8006c08: b29b uxth r3, r3
|
|
8006c0a: 4313 orrs r3, r2
|
|
8006c0c: b29b uxth r3, r3
|
|
8006c0e: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006c12: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006c16: b29a uxth r2, r3
|
|
8006c18: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006c1c: 801a strh r2, [r3, #0]
|
|
8006c1e: f000 bc10 b.w 8007442 <USB_EPStartXfer+0x16e2>
|
|
8006c22: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006c26: 2b00 cmp r3, #0
|
|
8006c28: d10c bne.n 8006c44 <USB_EPStartXfer+0xee4>
|
|
8006c2a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006c2e: 881b ldrh r3, [r3, #0]
|
|
8006c30: b29b uxth r3, r3
|
|
8006c32: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006c36: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006c3a: b29a uxth r2, r3
|
|
8006c3c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006c40: 801a strh r2, [r3, #0]
|
|
8006c42: e3fe b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
8006c44: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006c48: 085b lsrs r3, r3, #1
|
|
8006c4a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006c4e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8006c52: f003 0301 and.w r3, r3, #1
|
|
8006c56: 2b00 cmp r3, #0
|
|
8006c58: d004 beq.n 8006c64 <USB_EPStartXfer+0xf04>
|
|
8006c5a: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
|
|
8006c5e: 3301 adds r3, #1
|
|
8006c60: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006c64: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006c68: 881b ldrh r3, [r3, #0]
|
|
8006c6a: b29a uxth r2, r3
|
|
8006c6c: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8
|
|
8006c70: b29b uxth r3, r3
|
|
8006c72: 029b lsls r3, r3, #10
|
|
8006c74: b29b uxth r3, r3
|
|
8006c76: 4313 orrs r3, r2
|
|
8006c78: b29a uxth r2, r3
|
|
8006c7a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006c7e: 801a strh r2, [r3, #0]
|
|
8006c80: e3df b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else
|
|
{
|
|
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
|
|
/* Set the Double buffer counter */
|
|
if (ep->type == EP_TYPE_BULK)
|
|
8006c82: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006c86: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006c8a: 681b ldr r3, [r3, #0]
|
|
8006c8c: 78db ldrb r3, [r3, #3]
|
|
8006c8e: 2b02 cmp r3, #2
|
|
8006c90: f040 8218 bne.w 80070c4 <USB_EPStartXfer+0x1364>
|
|
{
|
|
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
|
|
8006c94: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006c98: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006c9c: 681b ldr r3, [r3, #0]
|
|
8006c9e: 785b ldrb r3, [r3, #1]
|
|
8006ca0: 2b00 cmp r3, #0
|
|
8006ca2: f040 809d bne.w 8006de0 <USB_EPStartXfer+0x1080>
|
|
8006ca6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006caa: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006cae: 681b ldr r3, [r3, #0]
|
|
8006cb0: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
8006cb4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006cb8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006cbc: 681b ldr r3, [r3, #0]
|
|
8006cbe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006cc2: b29b uxth r3, r3
|
|
8006cc4: 461a mov r2, r3
|
|
8006cc6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006cca: 4413 add r3, r2
|
|
8006ccc: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
8006cd0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006cd4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006cd8: 681b ldr r3, [r3, #0]
|
|
8006cda: 781b ldrb r3, [r3, #0]
|
|
8006cdc: 011a lsls r2, r3, #4
|
|
8006cde: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8006ce2: 4413 add r3, r2
|
|
8006ce4: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8006ce8: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8006cec: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006cf0: 881b ldrh r3, [r3, #0]
|
|
8006cf2: b29b uxth r3, r3
|
|
8006cf4: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8006cf8: b29a uxth r2, r3
|
|
8006cfa: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006cfe: 801a strh r2, [r3, #0]
|
|
8006d00: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006d04: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006d08: 681b ldr r3, [r3, #0]
|
|
8006d0a: 691b ldr r3, [r3, #16]
|
|
8006d0c: 2b3e cmp r3, #62 @ 0x3e
|
|
8006d0e: d92b bls.n 8006d68 <USB_EPStartXfer+0x1008>
|
|
8006d10: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006d14: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006d18: 681b ldr r3, [r3, #0]
|
|
8006d1a: 691b ldr r3, [r3, #16]
|
|
8006d1c: 095b lsrs r3, r3, #5
|
|
8006d1e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8006d22: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006d26: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006d2a: 681b ldr r3, [r3, #0]
|
|
8006d2c: 691b ldr r3, [r3, #16]
|
|
8006d2e: f003 031f and.w r3, r3, #31
|
|
8006d32: 2b00 cmp r3, #0
|
|
8006d34: d104 bne.n 8006d40 <USB_EPStartXfer+0xfe0>
|
|
8006d36: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006d3a: 3b01 subs r3, #1
|
|
8006d3c: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8006d40: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006d44: 881b ldrh r3, [r3, #0]
|
|
8006d46: b29a uxth r2, r3
|
|
8006d48: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006d4c: b29b uxth r3, r3
|
|
8006d4e: 029b lsls r3, r3, #10
|
|
8006d50: b29b uxth r3, r3
|
|
8006d52: 4313 orrs r3, r2
|
|
8006d54: b29b uxth r3, r3
|
|
8006d56: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006d5a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006d5e: b29a uxth r2, r3
|
|
8006d60: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006d64: 801a strh r2, [r3, #0]
|
|
8006d66: e070 b.n 8006e4a <USB_EPStartXfer+0x10ea>
|
|
8006d68: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006d6c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006d70: 681b ldr r3, [r3, #0]
|
|
8006d72: 691b ldr r3, [r3, #16]
|
|
8006d74: 2b00 cmp r3, #0
|
|
8006d76: d10c bne.n 8006d92 <USB_EPStartXfer+0x1032>
|
|
8006d78: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006d7c: 881b ldrh r3, [r3, #0]
|
|
8006d7e: b29b uxth r3, r3
|
|
8006d80: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006d84: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006d88: b29a uxth r2, r3
|
|
8006d8a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006d8e: 801a strh r2, [r3, #0]
|
|
8006d90: e05b b.n 8006e4a <USB_EPStartXfer+0x10ea>
|
|
8006d92: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006d96: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006d9a: 681b ldr r3, [r3, #0]
|
|
8006d9c: 691b ldr r3, [r3, #16]
|
|
8006d9e: 085b lsrs r3, r3, #1
|
|
8006da0: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8006da4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006da8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006dac: 681b ldr r3, [r3, #0]
|
|
8006dae: 691b ldr r3, [r3, #16]
|
|
8006db0: f003 0301 and.w r3, r3, #1
|
|
8006db4: 2b00 cmp r3, #0
|
|
8006db6: d004 beq.n 8006dc2 <USB_EPStartXfer+0x1062>
|
|
8006db8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006dbc: 3301 adds r3, #1
|
|
8006dbe: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8006dc2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006dc6: 881b ldrh r3, [r3, #0]
|
|
8006dc8: b29a uxth r2, r3
|
|
8006dca: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006dce: b29b uxth r3, r3
|
|
8006dd0: 029b lsls r3, r3, #10
|
|
8006dd2: b29b uxth r3, r3
|
|
8006dd4: 4313 orrs r3, r2
|
|
8006dd6: b29a uxth r2, r3
|
|
8006dd8: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8006ddc: 801a strh r2, [r3, #0]
|
|
8006dde: e034 b.n 8006e4a <USB_EPStartXfer+0x10ea>
|
|
8006de0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006de4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006de8: 681b ldr r3, [r3, #0]
|
|
8006dea: 785b ldrb r3, [r3, #1]
|
|
8006dec: 2b01 cmp r3, #1
|
|
8006dee: d12c bne.n 8006e4a <USB_EPStartXfer+0x10ea>
|
|
8006df0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006df4: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006df8: 681b ldr r3, [r3, #0]
|
|
8006dfa: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8006dfe: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e02: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006e06: 681b ldr r3, [r3, #0]
|
|
8006e08: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006e0c: b29b uxth r3, r3
|
|
8006e0e: 461a mov r2, r3
|
|
8006e10: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8006e14: 4413 add r3, r2
|
|
8006e16: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8006e1a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e1e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006e22: 681b ldr r3, [r3, #0]
|
|
8006e24: 781b ldrb r3, [r3, #0]
|
|
8006e26: 011a lsls r2, r3, #4
|
|
8006e28: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8006e2c: 4413 add r3, r2
|
|
8006e2e: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8006e32: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8006e36: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e3a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006e3e: 681b ldr r3, [r3, #0]
|
|
8006e40: 691b ldr r3, [r3, #16]
|
|
8006e42: b29a uxth r2, r3
|
|
8006e44: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
8006e48: 801a strh r2, [r3, #0]
|
|
8006e4a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e4e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006e52: 681b ldr r3, [r3, #0]
|
|
8006e54: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
8006e58: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e5c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006e60: 681b ldr r3, [r3, #0]
|
|
8006e62: 785b ldrb r3, [r3, #1]
|
|
8006e64: 2b00 cmp r3, #0
|
|
8006e66: f040 809d bne.w 8006fa4 <USB_EPStartXfer+0x1244>
|
|
8006e6a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e6e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006e72: 681b ldr r3, [r3, #0]
|
|
8006e74: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8006e78: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e7c: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006e80: 681b ldr r3, [r3, #0]
|
|
8006e82: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006e86: b29b uxth r3, r3
|
|
8006e88: 461a mov r2, r3
|
|
8006e8a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8006e8e: 4413 add r3, r2
|
|
8006e90: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8006e94: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006e98: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006e9c: 681b ldr r3, [r3, #0]
|
|
8006e9e: 781b ldrb r3, [r3, #0]
|
|
8006ea0: 011a lsls r2, r3, #4
|
|
8006ea2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8006ea6: 4413 add r3, r2
|
|
8006ea8: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8006eac: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8006eb0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006eb4: 881b ldrh r3, [r3, #0]
|
|
8006eb6: b29b uxth r3, r3
|
|
8006eb8: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8006ebc: b29a uxth r2, r3
|
|
8006ebe: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006ec2: 801a strh r2, [r3, #0]
|
|
8006ec4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006ec8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006ecc: 681b ldr r3, [r3, #0]
|
|
8006ece: 691b ldr r3, [r3, #16]
|
|
8006ed0: 2b3e cmp r3, #62 @ 0x3e
|
|
8006ed2: d92b bls.n 8006f2c <USB_EPStartXfer+0x11cc>
|
|
8006ed4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006ed8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006edc: 681b ldr r3, [r3, #0]
|
|
8006ede: 691b ldr r3, [r3, #16]
|
|
8006ee0: 095b lsrs r3, r3, #5
|
|
8006ee2: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8006ee6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006eea: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006eee: 681b ldr r3, [r3, #0]
|
|
8006ef0: 691b ldr r3, [r3, #16]
|
|
8006ef2: f003 031f and.w r3, r3, #31
|
|
8006ef6: 2b00 cmp r3, #0
|
|
8006ef8: d104 bne.n 8006f04 <USB_EPStartXfer+0x11a4>
|
|
8006efa: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006efe: 3b01 subs r3, #1
|
|
8006f00: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8006f04: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006f08: 881b ldrh r3, [r3, #0]
|
|
8006f0a: b29a uxth r2, r3
|
|
8006f0c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006f10: b29b uxth r3, r3
|
|
8006f12: 029b lsls r3, r3, #10
|
|
8006f14: b29b uxth r3, r3
|
|
8006f16: 4313 orrs r3, r2
|
|
8006f18: b29b uxth r3, r3
|
|
8006f1a: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006f1e: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006f22: b29a uxth r2, r3
|
|
8006f24: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006f28: 801a strh r2, [r3, #0]
|
|
8006f2a: e069 b.n 8007000 <USB_EPStartXfer+0x12a0>
|
|
8006f2c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006f30: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006f34: 681b ldr r3, [r3, #0]
|
|
8006f36: 691b ldr r3, [r3, #16]
|
|
8006f38: 2b00 cmp r3, #0
|
|
8006f3a: d10c bne.n 8006f56 <USB_EPStartXfer+0x11f6>
|
|
8006f3c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006f40: 881b ldrh r3, [r3, #0]
|
|
8006f42: b29b uxth r3, r3
|
|
8006f44: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8006f48: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8006f4c: b29a uxth r2, r3
|
|
8006f4e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006f52: 801a strh r2, [r3, #0]
|
|
8006f54: e054 b.n 8007000 <USB_EPStartXfer+0x12a0>
|
|
8006f56: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006f5a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006f5e: 681b ldr r3, [r3, #0]
|
|
8006f60: 691b ldr r3, [r3, #16]
|
|
8006f62: 085b lsrs r3, r3, #1
|
|
8006f64: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8006f68: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006f6c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006f70: 681b ldr r3, [r3, #0]
|
|
8006f72: 691b ldr r3, [r3, #16]
|
|
8006f74: f003 0301 and.w r3, r3, #1
|
|
8006f78: 2b00 cmp r3, #0
|
|
8006f7a: d004 beq.n 8006f86 <USB_EPStartXfer+0x1226>
|
|
8006f7c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006f80: 3301 adds r3, #1
|
|
8006f82: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8006f86: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006f8a: 881b ldrh r3, [r3, #0]
|
|
8006f8c: b29a uxth r2, r3
|
|
8006f8e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006f92: b29b uxth r3, r3
|
|
8006f94: 029b lsls r3, r3, #10
|
|
8006f96: b29b uxth r3, r3
|
|
8006f98: 4313 orrs r3, r2
|
|
8006f9a: b29a uxth r2, r3
|
|
8006f9c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8006fa0: 801a strh r2, [r3, #0]
|
|
8006fa2: e02d b.n 8007000 <USB_EPStartXfer+0x12a0>
|
|
8006fa4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006fa8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006fac: 681b ldr r3, [r3, #0]
|
|
8006fae: 785b ldrb r3, [r3, #1]
|
|
8006fb0: 2b01 cmp r3, #1
|
|
8006fb2: d125 bne.n 8007000 <USB_EPStartXfer+0x12a0>
|
|
8006fb4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006fb8: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8006fbc: 681b ldr r3, [r3, #0]
|
|
8006fbe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8006fc2: b29b uxth r3, r3
|
|
8006fc4: 461a mov r2, r3
|
|
8006fc6: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8006fca: 4413 add r3, r2
|
|
8006fcc: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
8006fd0: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006fd4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006fd8: 681b ldr r3, [r3, #0]
|
|
8006fda: 781b ldrb r3, [r3, #0]
|
|
8006fdc: 011a lsls r2, r3, #4
|
|
8006fde: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8006fe2: 4413 add r3, r2
|
|
8006fe4: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8006fe8: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8006fec: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8006ff0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8006ff4: 681b ldr r3, [r3, #0]
|
|
8006ff6: 691b ldr r3, [r3, #16]
|
|
8006ff8: b29a uxth r2, r3
|
|
8006ffa: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8006ffe: 801a strh r2, [r3, #0]
|
|
|
|
/* Coming from ISR */
|
|
if (ep->xfer_count != 0U)
|
|
8007000: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007004: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007008: 681b ldr r3, [r3, #0]
|
|
800700a: 69db ldr r3, [r3, #28]
|
|
800700c: 2b00 cmp r3, #0
|
|
800700e: f000 8218 beq.w 8007442 <USB_EPStartXfer+0x16e2>
|
|
{
|
|
/* update last value to check if there is blocking state */
|
|
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
|
|
8007012: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007016: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800701a: 681a ldr r2, [r3, #0]
|
|
800701c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007020: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007024: 681b ldr r3, [r3, #0]
|
|
8007026: 781b ldrb r3, [r3, #0]
|
|
8007028: 009b lsls r3, r3, #2
|
|
800702a: 4413 add r3, r2
|
|
800702c: 881b ldrh r3, [r3, #0]
|
|
800702e: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
|
|
|
|
/*Blocking State */
|
|
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
|
|
8007032: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
8007036: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800703a: 2b00 cmp r3, #0
|
|
800703c: d005 beq.n 800704a <USB_EPStartXfer+0x12ea>
|
|
800703e: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
8007042: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8007046: 2b00 cmp r3, #0
|
|
8007048: d10d bne.n 8007066 <USB_EPStartXfer+0x1306>
|
|
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
|
|
800704a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800704e: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
|
|
8007052: 2b00 cmp r3, #0
|
|
8007054: f040 81f5 bne.w 8007442 <USB_EPStartXfer+0x16e2>
|
|
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
|
|
8007058: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800705c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8007060: 2b00 cmp r3, #0
|
|
8007062: f040 81ee bne.w 8007442 <USB_EPStartXfer+0x16e2>
|
|
{
|
|
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
|
|
8007066: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800706a: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800706e: 681a ldr r2, [r3, #0]
|
|
8007070: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007074: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007078: 681b ldr r3, [r3, #0]
|
|
800707a: 781b ldrb r3, [r3, #0]
|
|
800707c: 009b lsls r3, r3, #2
|
|
800707e: 4413 add r3, r2
|
|
8007080: 881b ldrh r3, [r3, #0]
|
|
8007082: b29b uxth r3, r3
|
|
8007084: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8007088: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800708c: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
8007090: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007094: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8007098: 681a ldr r2, [r3, #0]
|
|
800709a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800709e: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80070a2: 681b ldr r3, [r3, #0]
|
|
80070a4: 781b ldrb r3, [r3, #0]
|
|
80070a6: 009b lsls r3, r3, #2
|
|
80070a8: 441a add r2, r3
|
|
80070aa: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
80070ae: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80070b2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80070b6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80070ba: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
80070be: b29b uxth r3, r3
|
|
80070c0: 8013 strh r3, [r2, #0]
|
|
80070c2: e1be b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
}
|
|
}
|
|
}
|
|
/* iso out double */
|
|
else if (ep->type == EP_TYPE_ISOC)
|
|
80070c4: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80070c8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80070cc: 681b ldr r3, [r3, #0]
|
|
80070ce: 78db ldrb r3, [r3, #3]
|
|
80070d0: 2b01 cmp r3, #1
|
|
80070d2: f040 81b4 bne.w 800743e <USB_EPStartXfer+0x16de>
|
|
{
|
|
/* Multi packet transfer */
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
80070d6: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80070da: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80070de: 681b ldr r3, [r3, #0]
|
|
80070e0: 699a ldr r2, [r3, #24]
|
|
80070e2: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80070e6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80070ea: 681b ldr r3, [r3, #0]
|
|
80070ec: 691b ldr r3, [r3, #16]
|
|
80070ee: 429a cmp r2, r3
|
|
80070f0: d917 bls.n 8007122 <USB_EPStartXfer+0x13c2>
|
|
{
|
|
len = ep->maxpacket;
|
|
80070f2: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80070f6: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80070fa: 681b ldr r3, [r3, #0]
|
|
80070fc: 691b ldr r3, [r3, #16]
|
|
80070fe: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
ep->xfer_len -= len;
|
|
8007102: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007106: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800710a: 681b ldr r3, [r3, #0]
|
|
800710c: 699a ldr r2, [r3, #24]
|
|
800710e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8007112: 1ad2 subs r2, r2, r3
|
|
8007114: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007118: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800711c: 681b ldr r3, [r3, #0]
|
|
800711e: 619a str r2, [r3, #24]
|
|
8007120: e00e b.n 8007140 <USB_EPStartXfer+0x13e0>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len;
|
|
8007122: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007126: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800712a: 681b ldr r3, [r3, #0]
|
|
800712c: 699b ldr r3, [r3, #24]
|
|
800712e: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
ep->xfer_len = 0U;
|
|
8007132: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007136: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800713a: 681b ldr r3, [r3, #0]
|
|
800713c: 2200 movs r2, #0
|
|
800713e: 619a str r2, [r3, #24]
|
|
}
|
|
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
|
|
8007140: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007144: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007148: 681b ldr r3, [r3, #0]
|
|
800714a: 785b ldrb r3, [r3, #1]
|
|
800714c: 2b00 cmp r3, #0
|
|
800714e: f040 8085 bne.w 800725c <USB_EPStartXfer+0x14fc>
|
|
8007152: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007156: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800715a: 681b ldr r3, [r3, #0]
|
|
800715c: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8007160: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007164: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8007168: 681b ldr r3, [r3, #0]
|
|
800716a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800716e: b29b uxth r3, r3
|
|
8007170: 461a mov r2, r3
|
|
8007172: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
|
|
8007176: 4413 add r3, r2
|
|
8007178: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
800717c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007180: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007184: 681b ldr r3, [r3, #0]
|
|
8007186: 781b ldrb r3, [r3, #0]
|
|
8007188: 011a lsls r2, r3, #4
|
|
800718a: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
|
|
800718e: 4413 add r3, r2
|
|
8007190: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
8007194: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8007198: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
800719c: 881b ldrh r3, [r3, #0]
|
|
800719e: b29b uxth r3, r3
|
|
80071a0: f3c3 0309 ubfx r3, r3, #0, #10
|
|
80071a4: b29a uxth r2, r3
|
|
80071a6: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
80071aa: 801a strh r2, [r3, #0]
|
|
80071ac: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80071b0: 2b3e cmp r3, #62 @ 0x3e
|
|
80071b2: d923 bls.n 80071fc <USB_EPStartXfer+0x149c>
|
|
80071b4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80071b8: 095b lsrs r3, r3, #5
|
|
80071ba: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
80071be: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80071c2: f003 031f and.w r3, r3, #31
|
|
80071c6: 2b00 cmp r3, #0
|
|
80071c8: d104 bne.n 80071d4 <USB_EPStartXfer+0x1474>
|
|
80071ca: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80071ce: 3b01 subs r3, #1
|
|
80071d0: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
80071d4: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
80071d8: 881b ldrh r3, [r3, #0]
|
|
80071da: b29a uxth r2, r3
|
|
80071dc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80071e0: b29b uxth r3, r3
|
|
80071e2: 029b lsls r3, r3, #10
|
|
80071e4: b29b uxth r3, r3
|
|
80071e6: 4313 orrs r3, r2
|
|
80071e8: b29b uxth r3, r3
|
|
80071ea: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80071ee: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80071f2: b29a uxth r2, r3
|
|
80071f4: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
80071f8: 801a strh r2, [r3, #0]
|
|
80071fa: e060 b.n 80072be <USB_EPStartXfer+0x155e>
|
|
80071fc: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8007200: 2b00 cmp r3, #0
|
|
8007202: d10c bne.n 800721e <USB_EPStartXfer+0x14be>
|
|
8007204: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8007208: 881b ldrh r3, [r3, #0]
|
|
800720a: b29b uxth r3, r3
|
|
800720c: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8007210: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8007214: b29a uxth r2, r3
|
|
8007216: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
800721a: 801a strh r2, [r3, #0]
|
|
800721c: e04f b.n 80072be <USB_EPStartXfer+0x155e>
|
|
800721e: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8007222: 085b lsrs r3, r3, #1
|
|
8007224: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
8007228: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800722c: f003 0301 and.w r3, r3, #1
|
|
8007230: 2b00 cmp r3, #0
|
|
8007232: d004 beq.n 800723e <USB_EPStartXfer+0x14de>
|
|
8007234: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8007238: 3301 adds r3, #1
|
|
800723a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
800723e: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8007242: 881b ldrh r3, [r3, #0]
|
|
8007244: b29a uxth r2, r3
|
|
8007246: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
800724a: b29b uxth r3, r3
|
|
800724c: 029b lsls r3, r3, #10
|
|
800724e: b29b uxth r3, r3
|
|
8007250: 4313 orrs r3, r2
|
|
8007252: b29a uxth r2, r3
|
|
8007254: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8007258: 801a strh r2, [r3, #0]
|
|
800725a: e030 b.n 80072be <USB_EPStartXfer+0x155e>
|
|
800725c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007260: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007264: 681b ldr r3, [r3, #0]
|
|
8007266: 785b ldrb r3, [r3, #1]
|
|
8007268: 2b01 cmp r3, #1
|
|
800726a: d128 bne.n 80072be <USB_EPStartXfer+0x155e>
|
|
800726c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007270: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8007274: 681b ldr r3, [r3, #0]
|
|
8007276: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
800727a: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800727e: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8007282: 681b ldr r3, [r3, #0]
|
|
8007284: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8007288: b29b uxth r3, r3
|
|
800728a: 461a mov r2, r3
|
|
800728c: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
8007290: 4413 add r3, r2
|
|
8007292: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
8007296: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800729a: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800729e: 681b ldr r3, [r3, #0]
|
|
80072a0: 781b ldrb r3, [r3, #0]
|
|
80072a2: 011a lsls r2, r3, #4
|
|
80072a4: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
80072a8: 4413 add r3, r2
|
|
80072aa: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
80072ae: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80072b2: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80072b6: b29a uxth r2, r3
|
|
80072b8: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
|
|
80072bc: 801a strh r2, [r3, #0]
|
|
80072be: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80072c2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80072c6: 681b ldr r3, [r3, #0]
|
|
80072c8: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
80072cc: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80072d0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80072d4: 681b ldr r3, [r3, #0]
|
|
80072d6: 785b ldrb r3, [r3, #1]
|
|
80072d8: 2b00 cmp r3, #0
|
|
80072da: f040 8085 bne.w 80073e8 <USB_EPStartXfer+0x1688>
|
|
80072de: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80072e2: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80072e6: 681b ldr r3, [r3, #0]
|
|
80072e8: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
|
|
80072ec: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80072f0: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
80072f4: 681b ldr r3, [r3, #0]
|
|
80072f6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80072fa: b29b uxth r3, r3
|
|
80072fc: 461a mov r2, r3
|
|
80072fe: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
|
|
8007302: 4413 add r3, r2
|
|
8007304: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
|
|
8007308: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
800730c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007310: 681b ldr r3, [r3, #0]
|
|
8007312: 781b ldrb r3, [r3, #0]
|
|
8007314: 011a lsls r2, r3, #4
|
|
8007316: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
|
|
800731a: 4413 add r3, r2
|
|
800731c: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
8007320: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8007324: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
8007328: 881b ldrh r3, [r3, #0]
|
|
800732a: b29b uxth r3, r3
|
|
800732c: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8007330: b29a uxth r2, r3
|
|
8007332: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
8007336: 801a strh r2, [r3, #0]
|
|
8007338: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800733c: 2b3e cmp r3, #62 @ 0x3e
|
|
800733e: d923 bls.n 8007388 <USB_EPStartXfer+0x1628>
|
|
8007340: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8007344: 095b lsrs r3, r3, #5
|
|
8007346: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
800734a: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800734e: f003 031f and.w r3, r3, #31
|
|
8007352: 2b00 cmp r3, #0
|
|
8007354: d104 bne.n 8007360 <USB_EPStartXfer+0x1600>
|
|
8007356: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
800735a: 3b01 subs r3, #1
|
|
800735c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
8007360: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
8007364: 881b ldrh r3, [r3, #0]
|
|
8007366: b29a uxth r2, r3
|
|
8007368: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
800736c: b29b uxth r3, r3
|
|
800736e: 029b lsls r3, r3, #10
|
|
8007370: b29b uxth r3, r3
|
|
8007372: 4313 orrs r3, r2
|
|
8007374: b29b uxth r3, r3
|
|
8007376: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800737a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800737e: b29a uxth r2, r3
|
|
8007380: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
8007384: 801a strh r2, [r3, #0]
|
|
8007386: e05c b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
8007388: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
800738c: 2b00 cmp r3, #0
|
|
800738e: d10c bne.n 80073aa <USB_EPStartXfer+0x164a>
|
|
8007390: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
8007394: 881b ldrh r3, [r3, #0]
|
|
8007396: b29b uxth r3, r3
|
|
8007398: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800739c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80073a0: b29a uxth r2, r3
|
|
80073a2: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80073a6: 801a strh r2, [r3, #0]
|
|
80073a8: e04b b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
80073aa: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80073ae: 085b lsrs r3, r3, #1
|
|
80073b0: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
80073b4: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
80073b8: f003 0301 and.w r3, r3, #1
|
|
80073bc: 2b00 cmp r3, #0
|
|
80073be: d004 beq.n 80073ca <USB_EPStartXfer+0x166a>
|
|
80073c0: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80073c4: 3301 adds r3, #1
|
|
80073c6: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
80073ca: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80073ce: 881b ldrh r3, [r3, #0]
|
|
80073d0: b29a uxth r2, r3
|
|
80073d2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80073d6: b29b uxth r3, r3
|
|
80073d8: 029b lsls r3, r3, #10
|
|
80073da: b29b uxth r3, r3
|
|
80073dc: 4313 orrs r3, r2
|
|
80073de: b29a uxth r2, r3
|
|
80073e0: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80073e4: 801a strh r2, [r3, #0]
|
|
80073e6: e02c b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
80073e8: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80073ec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
80073f0: 681b ldr r3, [r3, #0]
|
|
80073f2: 785b ldrb r3, [r3, #1]
|
|
80073f4: 2b01 cmp r3, #1
|
|
80073f6: d124 bne.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
80073f8: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
80073fc: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
8007400: 681b ldr r3, [r3, #0]
|
|
8007402: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8007406: b29b uxth r3, r3
|
|
8007408: 461a mov r2, r3
|
|
800740a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
800740e: 4413 add r3, r2
|
|
8007410: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
8007414: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007418: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
800741c: 681b ldr r3, [r3, #0]
|
|
800741e: 781b ldrb r3, [r3, #0]
|
|
8007420: 011a lsls r2, r3, #4
|
|
8007422: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8007426: 4413 add r3, r2
|
|
8007428: f203 430c addw r3, r3, #1036 @ 0x40c
|
|
800742c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8007430: f8d7 3104 ldr.w r3, [r7, #260] @ 0x104
|
|
8007434: b29a uxth r2, r3
|
|
8007436: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
800743a: 801a strh r2, [r3, #0]
|
|
800743c: e001 b.n 8007442 <USB_EPStartXfer+0x16e2>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
800743e: 2301 movs r3, #1
|
|
8007440: e03a b.n 80074b8 <USB_EPStartXfer+0x1758>
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
8007442: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007446: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800744a: 681a ldr r2, [r3, #0]
|
|
800744c: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007450: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007454: 681b ldr r3, [r3, #0]
|
|
8007456: 781b ldrb r3, [r3, #0]
|
|
8007458: 009b lsls r3, r3, #2
|
|
800745a: 4413 add r3, r2
|
|
800745c: 881b ldrh r3, [r3, #0]
|
|
800745e: b29b uxth r3, r3
|
|
8007460: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8007464: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8007468: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
800746c: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
8007470: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8007474: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
8007478: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
800747c: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
8007480: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
8007484: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007488: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800748c: 681a ldr r2, [r3, #0]
|
|
800748e: f507 7384 add.w r3, r7, #264 @ 0x108
|
|
8007492: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8007496: 681b ldr r3, [r3, #0]
|
|
8007498: 781b ldrb r3, [r3, #0]
|
|
800749a: 009b lsls r3, r3, #2
|
|
800749c: 441a add r2, r3
|
|
800749e: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
80074a2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80074a6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80074aa: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80074ae: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80074b2: b29b uxth r3, r3
|
|
80074b4: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
80074b6: 2300 movs r3, #0
|
|
}
|
|
80074b8: 4618 mov r0, r3
|
|
80074ba: f507 7784 add.w r7, r7, #264 @ 0x108
|
|
80074be: 46bd mov sp, r7
|
|
80074c0: bd80 pop {r7, pc}
|
|
|
|
080074c2 <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
80074c2: b480 push {r7}
|
|
80074c4: b085 sub sp, #20
|
|
80074c6: af00 add r7, sp, #0
|
|
80074c8: 6078 str r0, [r7, #4]
|
|
80074ca: 6039 str r1, [r7, #0]
|
|
if (ep->is_in != 0U)
|
|
80074cc: 683b ldr r3, [r7, #0]
|
|
80074ce: 785b ldrb r3, [r3, #1]
|
|
80074d0: 2b00 cmp r3, #0
|
|
80074d2: d020 beq.n 8007516 <USB_EPSetStall+0x54>
|
|
{
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
|
|
80074d4: 687a ldr r2, [r7, #4]
|
|
80074d6: 683b ldr r3, [r7, #0]
|
|
80074d8: 781b ldrb r3, [r3, #0]
|
|
80074da: 009b lsls r3, r3, #2
|
|
80074dc: 4413 add r3, r2
|
|
80074de: 881b ldrh r3, [r3, #0]
|
|
80074e0: b29b uxth r3, r3
|
|
80074e2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80074e6: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80074ea: 81bb strh r3, [r7, #12]
|
|
80074ec: 89bb ldrh r3, [r7, #12]
|
|
80074ee: f083 0310 eor.w r3, r3, #16
|
|
80074f2: 81bb strh r3, [r7, #12]
|
|
80074f4: 687a ldr r2, [r7, #4]
|
|
80074f6: 683b ldr r3, [r7, #0]
|
|
80074f8: 781b ldrb r3, [r3, #0]
|
|
80074fa: 009b lsls r3, r3, #2
|
|
80074fc: 441a add r2, r3
|
|
80074fe: 89bb ldrh r3, [r7, #12]
|
|
8007500: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8007504: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8007508: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800750c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8007510: b29b uxth r3, r3
|
|
8007512: 8013 strh r3, [r2, #0]
|
|
8007514: e01f b.n 8007556 <USB_EPSetStall+0x94>
|
|
}
|
|
else
|
|
{
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
|
|
8007516: 687a ldr r2, [r7, #4]
|
|
8007518: 683b ldr r3, [r7, #0]
|
|
800751a: 781b ldrb r3, [r3, #0]
|
|
800751c: 009b lsls r3, r3, #2
|
|
800751e: 4413 add r3, r2
|
|
8007520: 881b ldrh r3, [r3, #0]
|
|
8007522: b29b uxth r3, r3
|
|
8007524: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8007528: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800752c: 81fb strh r3, [r7, #14]
|
|
800752e: 89fb ldrh r3, [r7, #14]
|
|
8007530: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8007534: 81fb strh r3, [r7, #14]
|
|
8007536: 687a ldr r2, [r7, #4]
|
|
8007538: 683b ldr r3, [r7, #0]
|
|
800753a: 781b ldrb r3, [r3, #0]
|
|
800753c: 009b lsls r3, r3, #2
|
|
800753e: 441a add r2, r3
|
|
8007540: 89fb ldrh r3, [r7, #14]
|
|
8007542: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8007546: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800754a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800754e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8007552: b29b uxth r3, r3
|
|
8007554: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007556: 2300 movs r3, #0
|
|
}
|
|
8007558: 4618 mov r0, r3
|
|
800755a: 3714 adds r7, #20
|
|
800755c: 46bd mov sp, r7
|
|
800755e: bc80 pop {r7}
|
|
8007560: 4770 bx lr
|
|
|
|
08007562 <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8007562: b480 push {r7}
|
|
8007564: b087 sub sp, #28
|
|
8007566: af00 add r7, sp, #0
|
|
8007568: 6078 str r0, [r7, #4]
|
|
800756a: 6039 str r1, [r7, #0]
|
|
if (ep->doublebuffer == 0U)
|
|
800756c: 683b ldr r3, [r7, #0]
|
|
800756e: 7b1b ldrb r3, [r3, #12]
|
|
8007570: 2b00 cmp r3, #0
|
|
8007572: f040 809d bne.w 80076b0 <USB_EPClearStall+0x14e>
|
|
{
|
|
if (ep->is_in != 0U)
|
|
8007576: 683b ldr r3, [r7, #0]
|
|
8007578: 785b ldrb r3, [r3, #1]
|
|
800757a: 2b00 cmp r3, #0
|
|
800757c: d04c beq.n 8007618 <USB_EPClearStall+0xb6>
|
|
{
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800757e: 687a ldr r2, [r7, #4]
|
|
8007580: 683b ldr r3, [r7, #0]
|
|
8007582: 781b ldrb r3, [r3, #0]
|
|
8007584: 009b lsls r3, r3, #2
|
|
8007586: 4413 add r3, r2
|
|
8007588: 881b ldrh r3, [r3, #0]
|
|
800758a: 823b strh r3, [r7, #16]
|
|
800758c: 8a3b ldrh r3, [r7, #16]
|
|
800758e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8007592: 2b00 cmp r3, #0
|
|
8007594: d01b beq.n 80075ce <USB_EPClearStall+0x6c>
|
|
8007596: 687a ldr r2, [r7, #4]
|
|
8007598: 683b ldr r3, [r7, #0]
|
|
800759a: 781b ldrb r3, [r3, #0]
|
|
800759c: 009b lsls r3, r3, #2
|
|
800759e: 4413 add r3, r2
|
|
80075a0: 881b ldrh r3, [r3, #0]
|
|
80075a2: b29b uxth r3, r3
|
|
80075a4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80075a8: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80075ac: 81fb strh r3, [r7, #14]
|
|
80075ae: 687a ldr r2, [r7, #4]
|
|
80075b0: 683b ldr r3, [r7, #0]
|
|
80075b2: 781b ldrb r3, [r3, #0]
|
|
80075b4: 009b lsls r3, r3, #2
|
|
80075b6: 441a add r2, r3
|
|
80075b8: 89fb ldrh r3, [r7, #14]
|
|
80075ba: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80075be: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80075c2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80075c6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
80075ca: b29b uxth r3, r3
|
|
80075cc: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
80075ce: 683b ldr r3, [r7, #0]
|
|
80075d0: 78db ldrb r3, [r3, #3]
|
|
80075d2: 2b01 cmp r3, #1
|
|
80075d4: d06c beq.n 80076b0 <USB_EPClearStall+0x14e>
|
|
{
|
|
/* Configure NAK status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
|
80075d6: 687a ldr r2, [r7, #4]
|
|
80075d8: 683b ldr r3, [r7, #0]
|
|
80075da: 781b ldrb r3, [r3, #0]
|
|
80075dc: 009b lsls r3, r3, #2
|
|
80075de: 4413 add r3, r2
|
|
80075e0: 881b ldrh r3, [r3, #0]
|
|
80075e2: b29b uxth r3, r3
|
|
80075e4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80075e8: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80075ec: 81bb strh r3, [r7, #12]
|
|
80075ee: 89bb ldrh r3, [r7, #12]
|
|
80075f0: f083 0320 eor.w r3, r3, #32
|
|
80075f4: 81bb strh r3, [r7, #12]
|
|
80075f6: 687a ldr r2, [r7, #4]
|
|
80075f8: 683b ldr r3, [r7, #0]
|
|
80075fa: 781b ldrb r3, [r3, #0]
|
|
80075fc: 009b lsls r3, r3, #2
|
|
80075fe: 441a add r2, r3
|
|
8007600: 89bb ldrh r3, [r7, #12]
|
|
8007602: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8007606: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800760a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800760e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8007612: b29b uxth r3, r3
|
|
8007614: 8013 strh r3, [r2, #0]
|
|
8007616: e04b b.n 80076b0 <USB_EPClearStall+0x14e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
8007618: 687a ldr r2, [r7, #4]
|
|
800761a: 683b ldr r3, [r7, #0]
|
|
800761c: 781b ldrb r3, [r3, #0]
|
|
800761e: 009b lsls r3, r3, #2
|
|
8007620: 4413 add r3, r2
|
|
8007622: 881b ldrh r3, [r3, #0]
|
|
8007624: 82fb strh r3, [r7, #22]
|
|
8007626: 8afb ldrh r3, [r7, #22]
|
|
8007628: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800762c: 2b00 cmp r3, #0
|
|
800762e: d01b beq.n 8007668 <USB_EPClearStall+0x106>
|
|
8007630: 687a ldr r2, [r7, #4]
|
|
8007632: 683b ldr r3, [r7, #0]
|
|
8007634: 781b ldrb r3, [r3, #0]
|
|
8007636: 009b lsls r3, r3, #2
|
|
8007638: 4413 add r3, r2
|
|
800763a: 881b ldrh r3, [r3, #0]
|
|
800763c: b29b uxth r3, r3
|
|
800763e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8007642: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8007646: 82bb strh r3, [r7, #20]
|
|
8007648: 687a ldr r2, [r7, #4]
|
|
800764a: 683b ldr r3, [r7, #0]
|
|
800764c: 781b ldrb r3, [r3, #0]
|
|
800764e: 009b lsls r3, r3, #2
|
|
8007650: 441a add r2, r3
|
|
8007652: 8abb ldrh r3, [r7, #20]
|
|
8007654: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8007658: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800765c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8007660: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8007664: b29b uxth r3, r3
|
|
8007666: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure VALID status for the Endpoint */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
8007668: 687a ldr r2, [r7, #4]
|
|
800766a: 683b ldr r3, [r7, #0]
|
|
800766c: 781b ldrb r3, [r3, #0]
|
|
800766e: 009b lsls r3, r3, #2
|
|
8007670: 4413 add r3, r2
|
|
8007672: 881b ldrh r3, [r3, #0]
|
|
8007674: b29b uxth r3, r3
|
|
8007676: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800767a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800767e: 827b strh r3, [r7, #18]
|
|
8007680: 8a7b ldrh r3, [r7, #18]
|
|
8007682: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8007686: 827b strh r3, [r7, #18]
|
|
8007688: 8a7b ldrh r3, [r7, #18]
|
|
800768a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800768e: 827b strh r3, [r7, #18]
|
|
8007690: 687a ldr r2, [r7, #4]
|
|
8007692: 683b ldr r3, [r7, #0]
|
|
8007694: 781b ldrb r3, [r3, #0]
|
|
8007696: 009b lsls r3, r3, #2
|
|
8007698: 441a add r2, r3
|
|
800769a: 8a7b ldrh r3, [r7, #18]
|
|
800769c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80076a0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80076a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80076a8: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80076ac: b29b uxth r3, r3
|
|
80076ae: 8013 strh r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80076b0: 2300 movs r3, #0
|
|
}
|
|
80076b2: 4618 mov r0, r3
|
|
80076b4: 371c adds r7, #28
|
|
80076b6: 46bd mov sp, r7
|
|
80076b8: bc80 pop {r7}
|
|
80076ba: 4770 bx lr
|
|
|
|
080076bc <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
|
|
{
|
|
80076bc: b480 push {r7}
|
|
80076be: b083 sub sp, #12
|
|
80076c0: af00 add r7, sp, #0
|
|
80076c2: 6078 str r0, [r7, #4]
|
|
80076c4: 460b mov r3, r1
|
|
80076c6: 70fb strb r3, [r7, #3]
|
|
if (address == 0U)
|
|
80076c8: 78fb ldrb r3, [r7, #3]
|
|
80076ca: 2b00 cmp r3, #0
|
|
80076cc: d103 bne.n 80076d6 <USB_SetDevAddress+0x1a>
|
|
{
|
|
/* set device address and enable function */
|
|
USBx->DADDR = (uint16_t)USB_DADDR_EF;
|
|
80076ce: 687b ldr r3, [r7, #4]
|
|
80076d0: 2280 movs r2, #128 @ 0x80
|
|
80076d2: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
|
|
}
|
|
|
|
return HAL_OK;
|
|
80076d6: 2300 movs r3, #0
|
|
}
|
|
80076d8: 4618 mov r0, r3
|
|
80076da: 370c adds r7, #12
|
|
80076dc: 46bd mov sp, r7
|
|
80076de: bc80 pop {r7}
|
|
80076e0: 4770 bx lr
|
|
|
|
080076e2 <USB_DevConnect>:
|
|
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
|
|
{
|
|
80076e2: b480 push {r7}
|
|
80076e4: b083 sub sp, #12
|
|
80076e6: af00 add r7, sp, #0
|
|
80076e8: 6078 str r0, [r7, #4]
|
|
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
|
only by USB OTG FS peripheral.
|
|
- This function is added to ensure compatibility across platforms.
|
|
*/
|
|
|
|
return HAL_OK;
|
|
80076ea: 2300 movs r3, #0
|
|
}
|
|
80076ec: 4618 mov r0, r3
|
|
80076ee: 370c adds r7, #12
|
|
80076f0: 46bd mov sp, r7
|
|
80076f2: bc80 pop {r7}
|
|
80076f4: 4770 bx lr
|
|
|
|
080076f6 <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
|
|
{
|
|
80076f6: b480 push {r7}
|
|
80076f8: b083 sub sp, #12
|
|
80076fa: af00 add r7, sp, #0
|
|
80076fc: 6078 str r0, [r7, #4]
|
|
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
|
only by USB OTG FS peripheral.
|
|
- This function is added to ensure compatibility across platforms.
|
|
*/
|
|
|
|
return HAL_OK;
|
|
80076fe: 2300 movs r3, #0
|
|
}
|
|
8007700: 4618 mov r0, r3
|
|
8007702: 370c adds r7, #12
|
|
8007704: 46bd mov sp, r7
|
|
8007706: bc80 pop {r7}
|
|
8007708: 4770 bx lr
|
|
|
|
0800770a <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
|
|
{
|
|
800770a: b480 push {r7}
|
|
800770c: b085 sub sp, #20
|
|
800770e: af00 add r7, sp, #0
|
|
8007710: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->ISTR;
|
|
8007712: 687b ldr r3, [r7, #4]
|
|
8007714: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
8007718: b29b uxth r3, r3
|
|
800771a: 60fb str r3, [r7, #12]
|
|
return tmpreg;
|
|
800771c: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800771e: 4618 mov r0, r3
|
|
8007720: 3714 adds r7, #20
|
|
8007722: 46bd mov sp, r7
|
|
8007724: bc80 pop {r7}
|
|
8007726: 4770 bx lr
|
|
|
|
08007728 <USB_EP0_OutStart>:
|
|
* @param USBx Selected device
|
|
* @param psetup pointer to setup packet
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
|
|
{
|
|
8007728: b480 push {r7}
|
|
800772a: b083 sub sp, #12
|
|
800772c: af00 add r7, sp, #0
|
|
800772e: 6078 str r0, [r7, #4]
|
|
8007730: 6039 str r1, [r7, #0]
|
|
UNUSED(psetup);
|
|
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
|
only by USB OTG FS peripheral.
|
|
- This function is added to ensure compatibility across platforms.
|
|
*/
|
|
return HAL_OK;
|
|
8007732: 2300 movs r3, #0
|
|
}
|
|
8007734: 4618 mov r0, r3
|
|
8007736: 370c adds r7, #12
|
|
8007738: 46bd mov sp, r7
|
|
800773a: bc80 pop {r7}
|
|
800773c: 4770 bx lr
|
|
|
|
0800773e <USB_WritePMA>:
|
|
* @param wPMABufAddr address into PMA.
|
|
* @param wNBytes no. of bytes to be copied.
|
|
* @retval None
|
|
*/
|
|
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
|
{
|
|
800773e: b480 push {r7}
|
|
8007740: b08b sub sp, #44 @ 0x2c
|
|
8007742: af00 add r7, sp, #0
|
|
8007744: 60f8 str r0, [r7, #12]
|
|
8007746: 60b9 str r1, [r7, #8]
|
|
8007748: 4611 mov r1, r2
|
|
800774a: 461a mov r2, r3
|
|
800774c: 460b mov r3, r1
|
|
800774e: 80fb strh r3, [r7, #6]
|
|
8007750: 4613 mov r3, r2
|
|
8007752: 80bb strh r3, [r7, #4]
|
|
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
|
|
8007754: 88bb ldrh r3, [r7, #4]
|
|
8007756: 3301 adds r3, #1
|
|
8007758: 085b lsrs r3, r3, #1
|
|
800775a: 61bb str r3, [r7, #24]
|
|
uint32_t BaseAddr = (uint32_t)USBx;
|
|
800775c: 68fb ldr r3, [r7, #12]
|
|
800775e: 617b str r3, [r7, #20]
|
|
uint32_t count;
|
|
uint16_t WrVal;
|
|
__IO uint16_t *pdwVal;
|
|
uint8_t *pBuf = pbUsrBuf;
|
|
8007760: 68bb ldr r3, [r7, #8]
|
|
8007762: 61fb str r3, [r7, #28]
|
|
|
|
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
|
8007764: 88fb ldrh r3, [r7, #6]
|
|
8007766: 005a lsls r2, r3, #1
|
|
8007768: 697b ldr r3, [r7, #20]
|
|
800776a: 4413 add r3, r2
|
|
800776c: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007770: 623b str r3, [r7, #32]
|
|
|
|
for (count = n; count != 0U; count--)
|
|
8007772: 69bb ldr r3, [r7, #24]
|
|
8007774: 627b str r3, [r7, #36] @ 0x24
|
|
8007776: e01f b.n 80077b8 <USB_WritePMA+0x7a>
|
|
{
|
|
WrVal = pBuf[0];
|
|
8007778: 69fb ldr r3, [r7, #28]
|
|
800777a: 781b ldrb r3, [r3, #0]
|
|
800777c: 827b strh r3, [r7, #18]
|
|
WrVal |= (uint16_t)pBuf[1] << 8;
|
|
800777e: 69fb ldr r3, [r7, #28]
|
|
8007780: 3301 adds r3, #1
|
|
8007782: 781b ldrb r3, [r3, #0]
|
|
8007784: b21b sxth r3, r3
|
|
8007786: 021b lsls r3, r3, #8
|
|
8007788: b21a sxth r2, r3
|
|
800778a: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
800778e: 4313 orrs r3, r2
|
|
8007790: b21b sxth r3, r3
|
|
8007792: 827b strh r3, [r7, #18]
|
|
*pdwVal = (WrVal & 0xFFFFU);
|
|
8007794: 6a3b ldr r3, [r7, #32]
|
|
8007796: 8a7a ldrh r2, [r7, #18]
|
|
8007798: 801a strh r2, [r3, #0]
|
|
pdwVal++;
|
|
800779a: 6a3b ldr r3, [r7, #32]
|
|
800779c: 3302 adds r3, #2
|
|
800779e: 623b str r3, [r7, #32]
|
|
|
|
#if PMA_ACCESS > 1U
|
|
pdwVal++;
|
|
80077a0: 6a3b ldr r3, [r7, #32]
|
|
80077a2: 3302 adds r3, #2
|
|
80077a4: 623b str r3, [r7, #32]
|
|
#endif /* PMA_ACCESS */
|
|
|
|
pBuf++;
|
|
80077a6: 69fb ldr r3, [r7, #28]
|
|
80077a8: 3301 adds r3, #1
|
|
80077aa: 61fb str r3, [r7, #28]
|
|
pBuf++;
|
|
80077ac: 69fb ldr r3, [r7, #28]
|
|
80077ae: 3301 adds r3, #1
|
|
80077b0: 61fb str r3, [r7, #28]
|
|
for (count = n; count != 0U; count--)
|
|
80077b2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80077b4: 3b01 subs r3, #1
|
|
80077b6: 627b str r3, [r7, #36] @ 0x24
|
|
80077b8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80077ba: 2b00 cmp r3, #0
|
|
80077bc: d1dc bne.n 8007778 <USB_WritePMA+0x3a>
|
|
}
|
|
}
|
|
80077be: bf00 nop
|
|
80077c0: bf00 nop
|
|
80077c2: 372c adds r7, #44 @ 0x2c
|
|
80077c4: 46bd mov sp, r7
|
|
80077c6: bc80 pop {r7}
|
|
80077c8: 4770 bx lr
|
|
|
|
080077ca <USB_ReadPMA>:
|
|
* @param wPMABufAddr address into PMA.
|
|
* @param wNBytes no. of bytes to be copied.
|
|
* @retval None
|
|
*/
|
|
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
|
{
|
|
80077ca: b480 push {r7}
|
|
80077cc: b08b sub sp, #44 @ 0x2c
|
|
80077ce: af00 add r7, sp, #0
|
|
80077d0: 60f8 str r0, [r7, #12]
|
|
80077d2: 60b9 str r1, [r7, #8]
|
|
80077d4: 4611 mov r1, r2
|
|
80077d6: 461a mov r2, r3
|
|
80077d8: 460b mov r3, r1
|
|
80077da: 80fb strh r3, [r7, #6]
|
|
80077dc: 4613 mov r3, r2
|
|
80077de: 80bb strh r3, [r7, #4]
|
|
uint32_t n = (uint32_t)wNBytes >> 1;
|
|
80077e0: 88bb ldrh r3, [r7, #4]
|
|
80077e2: 085b lsrs r3, r3, #1
|
|
80077e4: b29b uxth r3, r3
|
|
80077e6: 61bb str r3, [r7, #24]
|
|
uint32_t BaseAddr = (uint32_t)USBx;
|
|
80077e8: 68fb ldr r3, [r7, #12]
|
|
80077ea: 617b str r3, [r7, #20]
|
|
uint32_t count;
|
|
uint32_t RdVal;
|
|
__IO uint16_t *pdwVal;
|
|
uint8_t *pBuf = pbUsrBuf;
|
|
80077ec: 68bb ldr r3, [r7, #8]
|
|
80077ee: 61fb str r3, [r7, #28]
|
|
|
|
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
|
80077f0: 88fb ldrh r3, [r7, #6]
|
|
80077f2: 005a lsls r2, r3, #1
|
|
80077f4: 697b ldr r3, [r7, #20]
|
|
80077f6: 4413 add r3, r2
|
|
80077f8: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80077fc: 623b str r3, [r7, #32]
|
|
|
|
for (count = n; count != 0U; count--)
|
|
80077fe: 69bb ldr r3, [r7, #24]
|
|
8007800: 627b str r3, [r7, #36] @ 0x24
|
|
8007802: e01b b.n 800783c <USB_ReadPMA+0x72>
|
|
{
|
|
RdVal = *(__IO uint16_t *)pdwVal;
|
|
8007804: 6a3b ldr r3, [r7, #32]
|
|
8007806: 881b ldrh r3, [r3, #0]
|
|
8007808: b29b uxth r3, r3
|
|
800780a: 613b str r3, [r7, #16]
|
|
pdwVal++;
|
|
800780c: 6a3b ldr r3, [r7, #32]
|
|
800780e: 3302 adds r3, #2
|
|
8007810: 623b str r3, [r7, #32]
|
|
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
|
|
8007812: 693b ldr r3, [r7, #16]
|
|
8007814: b2da uxtb r2, r3
|
|
8007816: 69fb ldr r3, [r7, #28]
|
|
8007818: 701a strb r2, [r3, #0]
|
|
pBuf++;
|
|
800781a: 69fb ldr r3, [r7, #28]
|
|
800781c: 3301 adds r3, #1
|
|
800781e: 61fb str r3, [r7, #28]
|
|
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
|
|
8007820: 693b ldr r3, [r7, #16]
|
|
8007822: 0a1b lsrs r3, r3, #8
|
|
8007824: b2da uxtb r2, r3
|
|
8007826: 69fb ldr r3, [r7, #28]
|
|
8007828: 701a strb r2, [r3, #0]
|
|
pBuf++;
|
|
800782a: 69fb ldr r3, [r7, #28]
|
|
800782c: 3301 adds r3, #1
|
|
800782e: 61fb str r3, [r7, #28]
|
|
|
|
#if PMA_ACCESS > 1U
|
|
pdwVal++;
|
|
8007830: 6a3b ldr r3, [r7, #32]
|
|
8007832: 3302 adds r3, #2
|
|
8007834: 623b str r3, [r7, #32]
|
|
for (count = n; count != 0U; count--)
|
|
8007836: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007838: 3b01 subs r3, #1
|
|
800783a: 627b str r3, [r7, #36] @ 0x24
|
|
800783c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800783e: 2b00 cmp r3, #0
|
|
8007840: d1e0 bne.n 8007804 <USB_ReadPMA+0x3a>
|
|
#endif /* PMA_ACCESS */
|
|
}
|
|
|
|
if ((wNBytes % 2U) != 0U)
|
|
8007842: 88bb ldrh r3, [r7, #4]
|
|
8007844: f003 0301 and.w r3, r3, #1
|
|
8007848: b29b uxth r3, r3
|
|
800784a: 2b00 cmp r3, #0
|
|
800784c: d007 beq.n 800785e <USB_ReadPMA+0x94>
|
|
{
|
|
RdVal = *pdwVal;
|
|
800784e: 6a3b ldr r3, [r7, #32]
|
|
8007850: 881b ldrh r3, [r3, #0]
|
|
8007852: b29b uxth r3, r3
|
|
8007854: 613b str r3, [r7, #16]
|
|
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
|
|
8007856: 693b ldr r3, [r7, #16]
|
|
8007858: b2da uxtb r2, r3
|
|
800785a: 69fb ldr r3, [r7, #28]
|
|
800785c: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
800785e: bf00 nop
|
|
8007860: 372c adds r7, #44 @ 0x2c
|
|
8007862: 46bd mov sp, r7
|
|
8007864: bc80 pop {r7}
|
|
8007866: 4770 bx lr
|
|
|
|
08007868 <USBD_CDC_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8007868: b580 push {r7, lr}
|
|
800786a: b084 sub sp, #16
|
|
800786c: af00 add r7, sp, #0
|
|
800786e: 6078 str r0, [r7, #4]
|
|
8007870: 460b mov r3, r1
|
|
8007872: 70fb strb r3, [r7, #3]
|
|
uint8_t ret = 0U;
|
|
8007874: 2300 movs r3, #0
|
|
8007876: 73fb strb r3, [r7, #15]
|
|
USBD_CDC_HandleTypeDef *hcdc;
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8007878: 687b ldr r3, [r7, #4]
|
|
800787a: 7c1b ldrb r3, [r3, #16]
|
|
800787c: 2b00 cmp r3, #0
|
|
800787e: d115 bne.n 80078ac <USBD_CDC_Init+0x44>
|
|
{
|
|
/* Open EP IN */
|
|
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
|
|
8007880: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8007884: 2202 movs r2, #2
|
|
8007886: 2181 movs r1, #129 @ 0x81
|
|
8007888: 6878 ldr r0, [r7, #4]
|
|
800788a: f001 ff00 bl 800968e <USBD_LL_OpenEP>
|
|
CDC_DATA_HS_IN_PACKET_SIZE);
|
|
|
|
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
|
|
800788e: 687b ldr r3, [r7, #4]
|
|
8007890: 2201 movs r2, #1
|
|
8007892: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Open EP OUT */
|
|
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
|
|
8007894: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8007898: 2202 movs r2, #2
|
|
800789a: 2101 movs r1, #1
|
|
800789c: 6878 ldr r0, [r7, #4]
|
|
800789e: f001 fef6 bl 800968e <USBD_LL_OpenEP>
|
|
CDC_DATA_HS_OUT_PACKET_SIZE);
|
|
|
|
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
|
|
80078a2: 687b ldr r3, [r7, #4]
|
|
80078a4: 2201 movs r2, #1
|
|
80078a6: f8c3 216c str.w r2, [r3, #364] @ 0x16c
|
|
80078aa: e012 b.n 80078d2 <USBD_CDC_Init+0x6a>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Open EP IN */
|
|
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
|
|
80078ac: 2340 movs r3, #64 @ 0x40
|
|
80078ae: 2202 movs r2, #2
|
|
80078b0: 2181 movs r1, #129 @ 0x81
|
|
80078b2: 6878 ldr r0, [r7, #4]
|
|
80078b4: f001 feeb bl 800968e <USBD_LL_OpenEP>
|
|
CDC_DATA_FS_IN_PACKET_SIZE);
|
|
|
|
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
|
|
80078b8: 687b ldr r3, [r7, #4]
|
|
80078ba: 2201 movs r2, #1
|
|
80078bc: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Open EP OUT */
|
|
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
|
|
80078be: 2340 movs r3, #64 @ 0x40
|
|
80078c0: 2202 movs r2, #2
|
|
80078c2: 2101 movs r1, #1
|
|
80078c4: 6878 ldr r0, [r7, #4]
|
|
80078c6: f001 fee2 bl 800968e <USBD_LL_OpenEP>
|
|
CDC_DATA_FS_OUT_PACKET_SIZE);
|
|
|
|
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
|
|
80078ca: 687b ldr r3, [r7, #4]
|
|
80078cc: 2201 movs r2, #1
|
|
80078ce: f8c3 216c str.w r2, [r3, #364] @ 0x16c
|
|
}
|
|
/* Open Command IN EP */
|
|
USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
|
|
80078d2: 2308 movs r3, #8
|
|
80078d4: 2203 movs r2, #3
|
|
80078d6: 2182 movs r1, #130 @ 0x82
|
|
80078d8: 6878 ldr r0, [r7, #4]
|
|
80078da: f001 fed8 bl 800968e <USBD_LL_OpenEP>
|
|
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
|
|
80078de: 687b ldr r3, [r7, #4]
|
|
80078e0: 2201 movs r2, #1
|
|
80078e2: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
|
|
80078e4: f44f 7007 mov.w r0, #540 @ 0x21c
|
|
80078e8: f001 fff8 bl 80098dc <USBD_static_malloc>
|
|
80078ec: 4602 mov r2, r0
|
|
80078ee: 687b ldr r3, [r7, #4]
|
|
80078f0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
|
|
if (pdev->pClassData == NULL)
|
|
80078f4: 687b ldr r3, [r7, #4]
|
|
80078f6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80078fa: 2b00 cmp r3, #0
|
|
80078fc: d102 bne.n 8007904 <USBD_CDC_Init+0x9c>
|
|
{
|
|
ret = 1U;
|
|
80078fe: 2301 movs r3, #1
|
|
8007900: 73fb strb r3, [r7, #15]
|
|
8007902: e026 b.n 8007952 <USBD_CDC_Init+0xea>
|
|
}
|
|
else
|
|
{
|
|
hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007904: 687b ldr r3, [r7, #4]
|
|
8007906: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
800790a: 60bb str r3, [r7, #8]
|
|
|
|
/* Init physical Interface components */
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
|
|
800790c: 687b ldr r3, [r7, #4]
|
|
800790e: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8007912: 681b ldr r3, [r3, #0]
|
|
8007914: 4798 blx r3
|
|
|
|
/* Init Xfer states */
|
|
hcdc->TxState = 0U;
|
|
8007916: 68bb ldr r3, [r7, #8]
|
|
8007918: 2200 movs r2, #0
|
|
800791a: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
hcdc->RxState = 0U;
|
|
800791e: 68bb ldr r3, [r7, #8]
|
|
8007920: 2200 movs r2, #0
|
|
8007922: f8c3 2218 str.w r2, [r3, #536] @ 0x218
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8007926: 687b ldr r3, [r7, #4]
|
|
8007928: 7c1b ldrb r3, [r3, #16]
|
|
800792a: 2b00 cmp r3, #0
|
|
800792c: d109 bne.n 8007942 <USBD_CDC_Init+0xda>
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
|
|
800792e: 68bb ldr r3, [r7, #8]
|
|
8007930: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
8007934: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8007938: 2101 movs r1, #1
|
|
800793a: 6878 ldr r0, [r7, #4]
|
|
800793c: f001 ff97 bl 800986e <USBD_LL_PrepareReceive>
|
|
8007940: e007 b.n 8007952 <USBD_CDC_Init+0xea>
|
|
CDC_DATA_HS_OUT_PACKET_SIZE);
|
|
}
|
|
else
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
|
|
8007942: 68bb ldr r3, [r7, #8]
|
|
8007944: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
8007948: 2340 movs r3, #64 @ 0x40
|
|
800794a: 2101 movs r1, #1
|
|
800794c: 6878 ldr r0, [r7, #4]
|
|
800794e: f001 ff8e bl 800986e <USBD_LL_PrepareReceive>
|
|
CDC_DATA_FS_OUT_PACKET_SIZE);
|
|
}
|
|
}
|
|
return ret;
|
|
8007952: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007954: 4618 mov r0, r3
|
|
8007956: 3710 adds r7, #16
|
|
8007958: 46bd mov sp, r7
|
|
800795a: bd80 pop {r7, pc}
|
|
|
|
0800795c <USBD_CDC_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
800795c: b580 push {r7, lr}
|
|
800795e: b084 sub sp, #16
|
|
8007960: af00 add r7, sp, #0
|
|
8007962: 6078 str r0, [r7, #4]
|
|
8007964: 460b mov r3, r1
|
|
8007966: 70fb strb r3, [r7, #3]
|
|
uint8_t ret = 0U;
|
|
8007968: 2300 movs r3, #0
|
|
800796a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Close EP IN */
|
|
USBD_LL_CloseEP(pdev, CDC_IN_EP);
|
|
800796c: 2181 movs r1, #129 @ 0x81
|
|
800796e: 6878 ldr r0, [r7, #4]
|
|
8007970: f001 feb3 bl 80096da <USBD_LL_CloseEP>
|
|
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
|
|
8007974: 687b ldr r3, [r7, #4]
|
|
8007976: 2200 movs r2, #0
|
|
8007978: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Close EP OUT */
|
|
USBD_LL_CloseEP(pdev, CDC_OUT_EP);
|
|
800797a: 2101 movs r1, #1
|
|
800797c: 6878 ldr r0, [r7, #4]
|
|
800797e: f001 feac bl 80096da <USBD_LL_CloseEP>
|
|
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
|
|
8007982: 687b ldr r3, [r7, #4]
|
|
8007984: 2200 movs r2, #0
|
|
8007986: f8c3 216c str.w r2, [r3, #364] @ 0x16c
|
|
|
|
/* Close Command IN EP */
|
|
USBD_LL_CloseEP(pdev, CDC_CMD_EP);
|
|
800798a: 2182 movs r1, #130 @ 0x82
|
|
800798c: 6878 ldr r0, [r7, #4]
|
|
800798e: f001 fea4 bl 80096da <USBD_LL_CloseEP>
|
|
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
|
|
8007992: 687b ldr r3, [r7, #4]
|
|
8007994: 2200 movs r2, #0
|
|
8007996: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* DeInit physical Interface components */
|
|
if (pdev->pClassData != NULL)
|
|
8007998: 687b ldr r3, [r7, #4]
|
|
800799a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
800799e: 2b00 cmp r3, #0
|
|
80079a0: d00e beq.n 80079c0 <USBD_CDC_DeInit+0x64>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
|
|
80079a2: 687b ldr r3, [r7, #4]
|
|
80079a4: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
80079a8: 685b ldr r3, [r3, #4]
|
|
80079aa: 4798 blx r3
|
|
USBD_free(pdev->pClassData);
|
|
80079ac: 687b ldr r3, [r7, #4]
|
|
80079ae: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80079b2: 4618 mov r0, r3
|
|
80079b4: f001 ff9e bl 80098f4 <USBD_static_free>
|
|
pdev->pClassData = NULL;
|
|
80079b8: 687b ldr r3, [r7, #4]
|
|
80079ba: 2200 movs r2, #0
|
|
80079bc: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
}
|
|
|
|
return ret;
|
|
80079c0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80079c2: 4618 mov r0, r3
|
|
80079c4: 3710 adds r7, #16
|
|
80079c6: 46bd mov sp, r7
|
|
80079c8: bd80 pop {r7, pc}
|
|
|
|
080079ca <USBD_CDC_Setup>:
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
80079ca: b580 push {r7, lr}
|
|
80079cc: b086 sub sp, #24
|
|
80079ce: af00 add r7, sp, #0
|
|
80079d0: 6078 str r0, [r7, #4]
|
|
80079d2: 6039 str r1, [r7, #0]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
80079d4: 687b ldr r3, [r7, #4]
|
|
80079d6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80079da: 613b str r3, [r7, #16]
|
|
uint8_t ifalt = 0U;
|
|
80079dc: 2300 movs r3, #0
|
|
80079de: 73fb strb r3, [r7, #15]
|
|
uint16_t status_info = 0U;
|
|
80079e0: 2300 movs r3, #0
|
|
80079e2: 81bb strh r3, [r7, #12]
|
|
uint8_t ret = USBD_OK;
|
|
80079e4: 2300 movs r3, #0
|
|
80079e6: 75fb strb r3, [r7, #23]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
80079e8: 683b ldr r3, [r7, #0]
|
|
80079ea: 781b ldrb r3, [r3, #0]
|
|
80079ec: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
80079f0: 2b00 cmp r3, #0
|
|
80079f2: d039 beq.n 8007a68 <USBD_CDC_Setup+0x9e>
|
|
80079f4: 2b20 cmp r3, #32
|
|
80079f6: d17f bne.n 8007af8 <USBD_CDC_Setup+0x12e>
|
|
{
|
|
case USB_REQ_TYPE_CLASS :
|
|
if (req->wLength)
|
|
80079f8: 683b ldr r3, [r7, #0]
|
|
80079fa: 88db ldrh r3, [r3, #6]
|
|
80079fc: 2b00 cmp r3, #0
|
|
80079fe: d029 beq.n 8007a54 <USBD_CDC_Setup+0x8a>
|
|
{
|
|
if (req->bmRequest & 0x80U)
|
|
8007a00: 683b ldr r3, [r7, #0]
|
|
8007a02: 781b ldrb r3, [r3, #0]
|
|
8007a04: b25b sxtb r3, r3
|
|
8007a06: 2b00 cmp r3, #0
|
|
8007a08: da11 bge.n 8007a2e <USBD_CDC_Setup+0x64>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
|
|
8007a0a: 687b ldr r3, [r7, #4]
|
|
8007a0c: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8007a10: 689b ldr r3, [r3, #8]
|
|
8007a12: 683a ldr r2, [r7, #0]
|
|
8007a14: 7850 ldrb r0, [r2, #1]
|
|
(uint8_t *)(void *)hcdc->data,
|
|
8007a16: 6939 ldr r1, [r7, #16]
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
|
|
8007a18: 683a ldr r2, [r7, #0]
|
|
8007a1a: 88d2 ldrh r2, [r2, #6]
|
|
8007a1c: 4798 blx r3
|
|
req->wLength);
|
|
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
|
|
8007a1e: 6939 ldr r1, [r7, #16]
|
|
8007a20: 683b ldr r3, [r7, #0]
|
|
8007a22: 88db ldrh r3, [r3, #6]
|
|
8007a24: 461a mov r2, r3
|
|
8007a26: 6878 ldr r0, [r7, #4]
|
|
8007a28: f001 fa06 bl 8008e38 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
|
|
(uint8_t *)(void *)req, 0U);
|
|
}
|
|
break;
|
|
8007a2c: e06b b.n 8007b06 <USBD_CDC_Setup+0x13c>
|
|
hcdc->CmdOpCode = req->bRequest;
|
|
8007a2e: 683b ldr r3, [r7, #0]
|
|
8007a30: 785a ldrb r2, [r3, #1]
|
|
8007a32: 693b ldr r3, [r7, #16]
|
|
8007a34: f883 2200 strb.w r2, [r3, #512] @ 0x200
|
|
hcdc->CmdLength = (uint8_t)req->wLength;
|
|
8007a38: 683b ldr r3, [r7, #0]
|
|
8007a3a: 88db ldrh r3, [r3, #6]
|
|
8007a3c: b2da uxtb r2, r3
|
|
8007a3e: 693b ldr r3, [r7, #16]
|
|
8007a40: f883 2201 strb.w r2, [r3, #513] @ 0x201
|
|
USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
|
|
8007a44: 6939 ldr r1, [r7, #16]
|
|
8007a46: 683b ldr r3, [r7, #0]
|
|
8007a48: 88db ldrh r3, [r3, #6]
|
|
8007a4a: 461a mov r2, r3
|
|
8007a4c: 6878 ldr r0, [r7, #4]
|
|
8007a4e: f001 fa21 bl 8008e94 <USBD_CtlPrepareRx>
|
|
break;
|
|
8007a52: e058 b.n 8007b06 <USBD_CDC_Setup+0x13c>
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
|
|
8007a54: 687b ldr r3, [r7, #4]
|
|
8007a56: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8007a5a: 689b ldr r3, [r3, #8]
|
|
8007a5c: 683a ldr r2, [r7, #0]
|
|
8007a5e: 7850 ldrb r0, [r2, #1]
|
|
8007a60: 2200 movs r2, #0
|
|
8007a62: 6839 ldr r1, [r7, #0]
|
|
8007a64: 4798 blx r3
|
|
break;
|
|
8007a66: e04e b.n 8007b06 <USBD_CDC_Setup+0x13c>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8007a68: 683b ldr r3, [r7, #0]
|
|
8007a6a: 785b ldrb r3, [r3, #1]
|
|
8007a6c: 2b0b cmp r3, #11
|
|
8007a6e: d02e beq.n 8007ace <USBD_CDC_Setup+0x104>
|
|
8007a70: 2b0b cmp r3, #11
|
|
8007a72: dc38 bgt.n 8007ae6 <USBD_CDC_Setup+0x11c>
|
|
8007a74: 2b00 cmp r3, #0
|
|
8007a76: d002 beq.n 8007a7e <USBD_CDC_Setup+0xb4>
|
|
8007a78: 2b0a cmp r3, #10
|
|
8007a7a: d014 beq.n 8007aa6 <USBD_CDC_Setup+0xdc>
|
|
8007a7c: e033 b.n 8007ae6 <USBD_CDC_Setup+0x11c>
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a7e: 687b ldr r3, [r7, #4]
|
|
8007a80: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007a84: 2b03 cmp r3, #3
|
|
8007a86: d107 bne.n 8007a98 <USBD_CDC_Setup+0xce>
|
|
{
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
|
|
8007a88: f107 030c add.w r3, r7, #12
|
|
8007a8c: 2202 movs r2, #2
|
|
8007a8e: 4619 mov r1, r3
|
|
8007a90: 6878 ldr r0, [r7, #4]
|
|
8007a92: f001 f9d1 bl 8008e38 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8007a96: e02e b.n 8007af6 <USBD_CDC_Setup+0x12c>
|
|
USBD_CtlError(pdev, req);
|
|
8007a98: 6839 ldr r1, [r7, #0]
|
|
8007a9a: 6878 ldr r0, [r7, #4]
|
|
8007a9c: f001 f962 bl 8008d64 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007aa0: 2302 movs r3, #2
|
|
8007aa2: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007aa4: e027 b.n 8007af6 <USBD_CDC_Setup+0x12c>
|
|
|
|
case USB_REQ_GET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007aa6: 687b ldr r3, [r7, #4]
|
|
8007aa8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007aac: 2b03 cmp r3, #3
|
|
8007aae: d107 bne.n 8007ac0 <USBD_CDC_Setup+0xf6>
|
|
{
|
|
USBD_CtlSendData(pdev, &ifalt, 1U);
|
|
8007ab0: f107 030f add.w r3, r7, #15
|
|
8007ab4: 2201 movs r2, #1
|
|
8007ab6: 4619 mov r1, r3
|
|
8007ab8: 6878 ldr r0, [r7, #4]
|
|
8007aba: f001 f9bd bl 8008e38 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8007abe: e01a b.n 8007af6 <USBD_CDC_Setup+0x12c>
|
|
USBD_CtlError(pdev, req);
|
|
8007ac0: 6839 ldr r1, [r7, #0]
|
|
8007ac2: 6878 ldr r0, [r7, #4]
|
|
8007ac4: f001 f94e bl 8008d64 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007ac8: 2302 movs r3, #2
|
|
8007aca: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007acc: e013 b.n 8007af6 <USBD_CDC_Setup+0x12c>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state != USBD_STATE_CONFIGURED)
|
|
8007ace: 687b ldr r3, [r7, #4]
|
|
8007ad0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007ad4: 2b03 cmp r3, #3
|
|
8007ad6: d00d beq.n 8007af4 <USBD_CDC_Setup+0x12a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007ad8: 6839 ldr r1, [r7, #0]
|
|
8007ada: 6878 ldr r0, [r7, #4]
|
|
8007adc: f001 f942 bl 8008d64 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007ae0: 2302 movs r3, #2
|
|
8007ae2: 75fb strb r3, [r7, #23]
|
|
}
|
|
break;
|
|
8007ae4: e006 b.n 8007af4 <USBD_CDC_Setup+0x12a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007ae6: 6839 ldr r1, [r7, #0]
|
|
8007ae8: 6878 ldr r0, [r7, #4]
|
|
8007aea: f001 f93b bl 8008d64 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007aee: 2302 movs r3, #2
|
|
8007af0: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007af2: e000 b.n 8007af6 <USBD_CDC_Setup+0x12c>
|
|
break;
|
|
8007af4: bf00 nop
|
|
}
|
|
break;
|
|
8007af6: e006 b.n 8007b06 <USBD_CDC_Setup+0x13c>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007af8: 6839 ldr r1, [r7, #0]
|
|
8007afa: 6878 ldr r0, [r7, #4]
|
|
8007afc: f001 f932 bl 8008d64 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007b00: 2302 movs r3, #2
|
|
8007b02: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007b04: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8007b06: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8007b08: 4618 mov r0, r3
|
|
8007b0a: 3718 adds r7, #24
|
|
8007b0c: 46bd mov sp, r7
|
|
8007b0e: bd80 pop {r7, pc}
|
|
|
|
08007b10 <USBD_CDC_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint number
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
8007b10: b580 push {r7, lr}
|
|
8007b12: b084 sub sp, #16
|
|
8007b14: af00 add r7, sp, #0
|
|
8007b16: 6078 str r0, [r7, #4]
|
|
8007b18: 460b mov r3, r1
|
|
8007b1a: 70fb strb r3, [r7, #3]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
|
|
8007b1c: 687b ldr r3, [r7, #4]
|
|
8007b1e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b22: 60fb str r3, [r7, #12]
|
|
PCD_HandleTypeDef *hpcd = pdev->pData;
|
|
8007b24: 687b ldr r3, [r7, #4]
|
|
8007b26: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
8007b2a: 60bb str r3, [r7, #8]
|
|
|
|
if (pdev->pClassData != NULL)
|
|
8007b2c: 687b ldr r3, [r7, #4]
|
|
8007b2e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b32: 2b00 cmp r3, #0
|
|
8007b34: d03a beq.n 8007bac <USBD_CDC_DataIn+0x9c>
|
|
{
|
|
if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
|
|
8007b36: 78fa ldrb r2, [r7, #3]
|
|
8007b38: 6879 ldr r1, [r7, #4]
|
|
8007b3a: 4613 mov r3, r2
|
|
8007b3c: 009b lsls r3, r3, #2
|
|
8007b3e: 4413 add r3, r2
|
|
8007b40: 009b lsls r3, r3, #2
|
|
8007b42: 440b add r3, r1
|
|
8007b44: 331c adds r3, #28
|
|
8007b46: 681b ldr r3, [r3, #0]
|
|
8007b48: 2b00 cmp r3, #0
|
|
8007b4a: d029 beq.n 8007ba0 <USBD_CDC_DataIn+0x90>
|
|
8007b4c: 78fa ldrb r2, [r7, #3]
|
|
8007b4e: 6879 ldr r1, [r7, #4]
|
|
8007b50: 4613 mov r3, r2
|
|
8007b52: 009b lsls r3, r3, #2
|
|
8007b54: 4413 add r3, r2
|
|
8007b56: 009b lsls r3, r3, #2
|
|
8007b58: 440b add r3, r1
|
|
8007b5a: 331c adds r3, #28
|
|
8007b5c: 681a ldr r2, [r3, #0]
|
|
8007b5e: 78f9 ldrb r1, [r7, #3]
|
|
8007b60: 68b8 ldr r0, [r7, #8]
|
|
8007b62: 460b mov r3, r1
|
|
8007b64: 009b lsls r3, r3, #2
|
|
8007b66: 440b add r3, r1
|
|
8007b68: 00db lsls r3, r3, #3
|
|
8007b6a: 4403 add r3, r0
|
|
8007b6c: 3320 adds r3, #32
|
|
8007b6e: 681b ldr r3, [r3, #0]
|
|
8007b70: fbb2 f1f3 udiv r1, r2, r3
|
|
8007b74: fb01 f303 mul.w r3, r1, r3
|
|
8007b78: 1ad3 subs r3, r2, r3
|
|
8007b7a: 2b00 cmp r3, #0
|
|
8007b7c: d110 bne.n 8007ba0 <USBD_CDC_DataIn+0x90>
|
|
{
|
|
/* Update the packet total length */
|
|
pdev->ep_in[epnum].total_length = 0U;
|
|
8007b7e: 78fa ldrb r2, [r7, #3]
|
|
8007b80: 6879 ldr r1, [r7, #4]
|
|
8007b82: 4613 mov r3, r2
|
|
8007b84: 009b lsls r3, r3, #2
|
|
8007b86: 4413 add r3, r2
|
|
8007b88: 009b lsls r3, r3, #2
|
|
8007b8a: 440b add r3, r1
|
|
8007b8c: 331c adds r3, #28
|
|
8007b8e: 2200 movs r2, #0
|
|
8007b90: 601a str r2, [r3, #0]
|
|
|
|
/* Send ZLP */
|
|
USBD_LL_Transmit(pdev, epnum, NULL, 0U);
|
|
8007b92: 78f9 ldrb r1, [r7, #3]
|
|
8007b94: 2300 movs r3, #0
|
|
8007b96: 2200 movs r2, #0
|
|
8007b98: 6878 ldr r0, [r7, #4]
|
|
8007b9a: f001 fe45 bl 8009828 <USBD_LL_Transmit>
|
|
8007b9e: e003 b.n 8007ba8 <USBD_CDC_DataIn+0x98>
|
|
}
|
|
else
|
|
{
|
|
hcdc->TxState = 0U;
|
|
8007ba0: 68fb ldr r3, [r7, #12]
|
|
8007ba2: 2200 movs r2, #0
|
|
8007ba4: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
}
|
|
return USBD_OK;
|
|
8007ba8: 2300 movs r3, #0
|
|
8007baa: e000 b.n 8007bae <USBD_CDC_DataIn+0x9e>
|
|
}
|
|
else
|
|
{
|
|
return USBD_FAIL;
|
|
8007bac: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007bae: 4618 mov r0, r3
|
|
8007bb0: 3710 adds r7, #16
|
|
8007bb2: 46bd mov sp, r7
|
|
8007bb4: bd80 pop {r7, pc}
|
|
|
|
08007bb6 <USBD_CDC_DataOut>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint number
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
8007bb6: b580 push {r7, lr}
|
|
8007bb8: b084 sub sp, #16
|
|
8007bba: af00 add r7, sp, #0
|
|
8007bbc: 6078 str r0, [r7, #4]
|
|
8007bbe: 460b mov r3, r1
|
|
8007bc0: 70fb strb r3, [r7, #3]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007bc2: 687b ldr r3, [r7, #4]
|
|
8007bc4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007bc8: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the received data length */
|
|
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
|
|
8007bca: 78fb ldrb r3, [r7, #3]
|
|
8007bcc: 4619 mov r1, r3
|
|
8007bce: 6878 ldr r0, [r7, #4]
|
|
8007bd0: f001 fe70 bl 80098b4 <USBD_LL_GetRxDataSize>
|
|
8007bd4: 4602 mov r2, r0
|
|
8007bd6: 68fb ldr r3, [r7, #12]
|
|
8007bd8: f8c3 220c str.w r2, [r3, #524] @ 0x20c
|
|
|
|
/* USB data will be immediately processed, this allow next USB traffic being
|
|
NAKed till the end of the application Xfer */
|
|
if (pdev->pClassData != NULL)
|
|
8007bdc: 687b ldr r3, [r7, #4]
|
|
8007bde: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007be2: 2b00 cmp r3, #0
|
|
8007be4: d00d beq.n 8007c02 <USBD_CDC_DataOut+0x4c>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
|
|
8007be6: 687b ldr r3, [r7, #4]
|
|
8007be8: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8007bec: 68db ldr r3, [r3, #12]
|
|
8007bee: 68fa ldr r2, [r7, #12]
|
|
8007bf0: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
|
|
8007bf4: 68fa ldr r2, [r7, #12]
|
|
8007bf6: f502 7203 add.w r2, r2, #524 @ 0x20c
|
|
8007bfa: 4611 mov r1, r2
|
|
8007bfc: 4798 blx r3
|
|
|
|
return USBD_OK;
|
|
8007bfe: 2300 movs r3, #0
|
|
8007c00: e000 b.n 8007c04 <USBD_CDC_DataOut+0x4e>
|
|
}
|
|
else
|
|
{
|
|
return USBD_FAIL;
|
|
8007c02: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007c04: 4618 mov r0, r3
|
|
8007c06: 3710 adds r7, #16
|
|
8007c08: 46bd mov sp, r7
|
|
8007c0a: bd80 pop {r7, pc}
|
|
|
|
08007c0c <USBD_CDC_EP0_RxReady>:
|
|
* Handle EP0 Rx Ready event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007c0c: b580 push {r7, lr}
|
|
8007c0e: b084 sub sp, #16
|
|
8007c10: af00 add r7, sp, #0
|
|
8007c12: 6078 str r0, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007c14: 687b ldr r3, [r7, #4]
|
|
8007c16: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c1a: 60fb str r3, [r7, #12]
|
|
|
|
if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
|
|
8007c1c: 687b ldr r3, [r7, #4]
|
|
8007c1e: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8007c22: 2b00 cmp r3, #0
|
|
8007c24: d014 beq.n 8007c50 <USBD_CDC_EP0_RxReady+0x44>
|
|
8007c26: 68fb ldr r3, [r7, #12]
|
|
8007c28: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
|
|
8007c2c: 2bff cmp r3, #255 @ 0xff
|
|
8007c2e: d00f beq.n 8007c50 <USBD_CDC_EP0_RxReady+0x44>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
|
|
8007c30: 687b ldr r3, [r7, #4]
|
|
8007c32: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8007c36: 689b ldr r3, [r3, #8]
|
|
8007c38: 68fa ldr r2, [r7, #12]
|
|
8007c3a: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
|
|
(uint8_t *)(void *)hcdc->data,
|
|
8007c3e: 68f9 ldr r1, [r7, #12]
|
|
(uint16_t)hcdc->CmdLength);
|
|
8007c40: 68fa ldr r2, [r7, #12]
|
|
8007c42: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
|
|
8007c46: 4798 blx r3
|
|
hcdc->CmdOpCode = 0xFFU;
|
|
8007c48: 68fb ldr r3, [r7, #12]
|
|
8007c4a: 22ff movs r2, #255 @ 0xff
|
|
8007c4c: f883 2200 strb.w r2, [r3, #512] @ 0x200
|
|
|
|
}
|
|
return USBD_OK;
|
|
8007c50: 2300 movs r3, #0
|
|
}
|
|
8007c52: 4618 mov r0, r3
|
|
8007c54: 3710 adds r7, #16
|
|
8007c56: 46bd mov sp, r7
|
|
8007c58: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007c5c <USBD_CDC_GetFSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8007c5c: b480 push {r7}
|
|
8007c5e: b083 sub sp, #12
|
|
8007c60: af00 add r7, sp, #0
|
|
8007c62: 6078 str r0, [r7, #4]
|
|
*length = sizeof(USBD_CDC_CfgFSDesc);
|
|
8007c64: 687b ldr r3, [r7, #4]
|
|
8007c66: 2243 movs r2, #67 @ 0x43
|
|
8007c68: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_CfgFSDesc;
|
|
8007c6a: 4b03 ldr r3, [pc, #12] @ (8007c78 <USBD_CDC_GetFSCfgDesc+0x1c>)
|
|
}
|
|
8007c6c: 4618 mov r0, r3
|
|
8007c6e: 370c adds r7, #12
|
|
8007c70: 46bd mov sp, r7
|
|
8007c72: bc80 pop {r7}
|
|
8007c74: 4770 bx lr
|
|
8007c76: bf00 nop
|
|
8007c78: 20000094 .word 0x20000094
|
|
|
|
08007c7c <USBD_CDC_GetHSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
8007c7c: b480 push {r7}
|
|
8007c7e: b083 sub sp, #12
|
|
8007c80: af00 add r7, sp, #0
|
|
8007c82: 6078 str r0, [r7, #4]
|
|
*length = sizeof(USBD_CDC_CfgHSDesc);
|
|
8007c84: 687b ldr r3, [r7, #4]
|
|
8007c86: 2243 movs r2, #67 @ 0x43
|
|
8007c88: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_CfgHSDesc;
|
|
8007c8a: 4b03 ldr r3, [pc, #12] @ (8007c98 <USBD_CDC_GetHSCfgDesc+0x1c>)
|
|
}
|
|
8007c8c: 4618 mov r0, r3
|
|
8007c8e: 370c adds r7, #12
|
|
8007c90: 46bd mov sp, r7
|
|
8007c92: bc80 pop {r7}
|
|
8007c94: 4770 bx lr
|
|
8007c96: bf00 nop
|
|
8007c98: 20000050 .word 0x20000050
|
|
|
|
08007c9c <USBD_CDC_GetOtherSpeedCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
8007c9c: b480 push {r7}
|
|
8007c9e: b083 sub sp, #12
|
|
8007ca0: af00 add r7, sp, #0
|
|
8007ca2: 6078 str r0, [r7, #4]
|
|
*length = sizeof(USBD_CDC_OtherSpeedCfgDesc);
|
|
8007ca4: 687b ldr r3, [r7, #4]
|
|
8007ca6: 2243 movs r2, #67 @ 0x43
|
|
8007ca8: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_OtherSpeedCfgDesc;
|
|
8007caa: 4b03 ldr r3, [pc, #12] @ (8007cb8 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
|
|
}
|
|
8007cac: 4618 mov r0, r3
|
|
8007cae: 370c adds r7, #12
|
|
8007cb0: 46bd mov sp, r7
|
|
8007cb2: bc80 pop {r7}
|
|
8007cb4: 4770 bx lr
|
|
8007cb6: bf00 nop
|
|
8007cb8: 200000d8 .word 0x200000d8
|
|
|
|
08007cbc <USBD_CDC_GetDeviceQualifierDescriptor>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
|
|
{
|
|
8007cbc: b480 push {r7}
|
|
8007cbe: b083 sub sp, #12
|
|
8007cc0: af00 add r7, sp, #0
|
|
8007cc2: 6078 str r0, [r7, #4]
|
|
*length = sizeof(USBD_CDC_DeviceQualifierDesc);
|
|
8007cc4: 687b ldr r3, [r7, #4]
|
|
8007cc6: 220a movs r2, #10
|
|
8007cc8: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_DeviceQualifierDesc;
|
|
8007cca: 4b03 ldr r3, [pc, #12] @ (8007cd8 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
|
|
}
|
|
8007ccc: 4618 mov r0, r3
|
|
8007cce: 370c adds r7, #12
|
|
8007cd0: 46bd mov sp, r7
|
|
8007cd2: bc80 pop {r7}
|
|
8007cd4: 4770 bx lr
|
|
8007cd6: bf00 nop
|
|
8007cd8: 2000000c .word 0x2000000c
|
|
|
|
08007cdc <USBD_CDC_RegisterInterface>:
|
|
* @param fops: CD Interface callback
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
|
|
USBD_CDC_ItfTypeDef *fops)
|
|
{
|
|
8007cdc: b480 push {r7}
|
|
8007cde: b085 sub sp, #20
|
|
8007ce0: af00 add r7, sp, #0
|
|
8007ce2: 6078 str r0, [r7, #4]
|
|
8007ce4: 6039 str r1, [r7, #0]
|
|
uint8_t ret = USBD_FAIL;
|
|
8007ce6: 2302 movs r3, #2
|
|
8007ce8: 73fb strb r3, [r7, #15]
|
|
|
|
if (fops != NULL)
|
|
8007cea: 683b ldr r3, [r7, #0]
|
|
8007cec: 2b00 cmp r3, #0
|
|
8007cee: d005 beq.n 8007cfc <USBD_CDC_RegisterInterface+0x20>
|
|
{
|
|
pdev->pUserData = fops;
|
|
8007cf0: 687b ldr r3, [r7, #4]
|
|
8007cf2: 683a ldr r2, [r7, #0]
|
|
8007cf4: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
ret = USBD_OK;
|
|
8007cf8: 2300 movs r3, #0
|
|
8007cfa: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return ret;
|
|
8007cfc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007cfe: 4618 mov r0, r3
|
|
8007d00: 3714 adds r7, #20
|
|
8007d02: 46bd mov sp, r7
|
|
8007d04: bc80 pop {r7}
|
|
8007d06: 4770 bx lr
|
|
|
|
08007d08 <USBD_CDC_SetTxBuffer>:
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuff,
|
|
uint16_t length)
|
|
{
|
|
8007d08: b480 push {r7}
|
|
8007d0a: b087 sub sp, #28
|
|
8007d0c: af00 add r7, sp, #0
|
|
8007d0e: 60f8 str r0, [r7, #12]
|
|
8007d10: 60b9 str r1, [r7, #8]
|
|
8007d12: 4613 mov r3, r2
|
|
8007d14: 80fb strh r3, [r7, #6]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007d16: 68fb ldr r3, [r7, #12]
|
|
8007d18: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d1c: 617b str r3, [r7, #20]
|
|
|
|
hcdc->TxBuffer = pbuff;
|
|
8007d1e: 697b ldr r3, [r7, #20]
|
|
8007d20: 68ba ldr r2, [r7, #8]
|
|
8007d22: f8c3 2208 str.w r2, [r3, #520] @ 0x208
|
|
hcdc->TxLength = length;
|
|
8007d26: 88fa ldrh r2, [r7, #6]
|
|
8007d28: 697b ldr r3, [r7, #20]
|
|
8007d2a: f8c3 2210 str.w r2, [r3, #528] @ 0x210
|
|
|
|
return USBD_OK;
|
|
8007d2e: 2300 movs r3, #0
|
|
}
|
|
8007d30: 4618 mov r0, r3
|
|
8007d32: 371c adds r7, #28
|
|
8007d34: 46bd mov sp, r7
|
|
8007d36: bc80 pop {r7}
|
|
8007d38: 4770 bx lr
|
|
|
|
08007d3a <USBD_CDC_SetRxBuffer>:
|
|
* @param pbuff: Rx Buffer
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuff)
|
|
{
|
|
8007d3a: b480 push {r7}
|
|
8007d3c: b085 sub sp, #20
|
|
8007d3e: af00 add r7, sp, #0
|
|
8007d40: 6078 str r0, [r7, #4]
|
|
8007d42: 6039 str r1, [r7, #0]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007d44: 687b ldr r3, [r7, #4]
|
|
8007d46: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d4a: 60fb str r3, [r7, #12]
|
|
|
|
hcdc->RxBuffer = pbuff;
|
|
8007d4c: 68fb ldr r3, [r7, #12]
|
|
8007d4e: 683a ldr r2, [r7, #0]
|
|
8007d50: f8c3 2204 str.w r2, [r3, #516] @ 0x204
|
|
|
|
return USBD_OK;
|
|
8007d54: 2300 movs r3, #0
|
|
}
|
|
8007d56: 4618 mov r0, r3
|
|
8007d58: 3714 adds r7, #20
|
|
8007d5a: 46bd mov sp, r7
|
|
8007d5c: bc80 pop {r7}
|
|
8007d5e: 4770 bx lr
|
|
|
|
08007d60 <USBD_CDC_TransmitPacket>:
|
|
* Transmit packet on IN endpoint
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007d60: b580 push {r7, lr}
|
|
8007d62: b084 sub sp, #16
|
|
8007d64: af00 add r7, sp, #0
|
|
8007d66: 6078 str r0, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007d68: 687b ldr r3, [r7, #4]
|
|
8007d6a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d6e: 60fb str r3, [r7, #12]
|
|
|
|
if (pdev->pClassData != NULL)
|
|
8007d70: 687b ldr r3, [r7, #4]
|
|
8007d72: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d76: 2b00 cmp r3, #0
|
|
8007d78: d01c beq.n 8007db4 <USBD_CDC_TransmitPacket+0x54>
|
|
{
|
|
if (hcdc->TxState == 0U)
|
|
8007d7a: 68fb ldr r3, [r7, #12]
|
|
8007d7c: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
|
|
8007d80: 2b00 cmp r3, #0
|
|
8007d82: d115 bne.n 8007db0 <USBD_CDC_TransmitPacket+0x50>
|
|
{
|
|
/* Tx Transfer in progress */
|
|
hcdc->TxState = 1U;
|
|
8007d84: 68fb ldr r3, [r7, #12]
|
|
8007d86: 2201 movs r2, #1
|
|
8007d88: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
|
|
/* Update the packet total length */
|
|
pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
|
|
8007d8c: 68fb ldr r3, [r7, #12]
|
|
8007d8e: f8d3 2210 ldr.w r2, [r3, #528] @ 0x210
|
|
8007d92: 687b ldr r3, [r7, #4]
|
|
8007d94: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Transmit next packet */
|
|
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
|
|
8007d96: 68fb ldr r3, [r7, #12]
|
|
8007d98: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
|
|
(uint16_t)hcdc->TxLength);
|
|
8007d9c: 68fb ldr r3, [r7, #12]
|
|
8007d9e: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
|
|
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
|
|
8007da2: b29b uxth r3, r3
|
|
8007da4: 2181 movs r1, #129 @ 0x81
|
|
8007da6: 6878 ldr r0, [r7, #4]
|
|
8007da8: f001 fd3e bl 8009828 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8007dac: 2300 movs r3, #0
|
|
8007dae: e002 b.n 8007db6 <USBD_CDC_TransmitPacket+0x56>
|
|
}
|
|
else
|
|
{
|
|
return USBD_BUSY;
|
|
8007db0: 2301 movs r3, #1
|
|
8007db2: e000 b.n 8007db6 <USBD_CDC_TransmitPacket+0x56>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return USBD_FAIL;
|
|
8007db4: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007db6: 4618 mov r0, r3
|
|
8007db8: 3710 adds r7, #16
|
|
8007dba: 46bd mov sp, r7
|
|
8007dbc: bd80 pop {r7, pc}
|
|
|
|
08007dbe <USBD_CDC_ReceivePacket>:
|
|
* prepare OUT Endpoint for reception
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007dbe: b580 push {r7, lr}
|
|
8007dc0: b084 sub sp, #16
|
|
8007dc2: af00 add r7, sp, #0
|
|
8007dc4: 6078 str r0, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
|
|
8007dc6: 687b ldr r3, [r7, #4]
|
|
8007dc8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007dcc: 60fb str r3, [r7, #12]
|
|
|
|
/* Suspend or Resume USB Out process */
|
|
if (pdev->pClassData != NULL)
|
|
8007dce: 687b ldr r3, [r7, #4]
|
|
8007dd0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007dd4: 2b00 cmp r3, #0
|
|
8007dd6: d017 beq.n 8007e08 <USBD_CDC_ReceivePacket+0x4a>
|
|
{
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8007dd8: 687b ldr r3, [r7, #4]
|
|
8007dda: 7c1b ldrb r3, [r3, #16]
|
|
8007ddc: 2b00 cmp r3, #0
|
|
8007dde: d109 bne.n 8007df4 <USBD_CDC_ReceivePacket+0x36>
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
USBD_LL_PrepareReceive(pdev,
|
|
8007de0: 68fb ldr r3, [r7, #12]
|
|
8007de2: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
8007de6: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8007dea: 2101 movs r1, #1
|
|
8007dec: 6878 ldr r0, [r7, #4]
|
|
8007dee: f001 fd3e bl 800986e <USBD_LL_PrepareReceive>
|
|
8007df2: e007 b.n 8007e04 <USBD_CDC_ReceivePacket+0x46>
|
|
CDC_DATA_HS_OUT_PACKET_SIZE);
|
|
}
|
|
else
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
USBD_LL_PrepareReceive(pdev,
|
|
8007df4: 68fb ldr r3, [r7, #12]
|
|
8007df6: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
8007dfa: 2340 movs r3, #64 @ 0x40
|
|
8007dfc: 2101 movs r1, #1
|
|
8007dfe: 6878 ldr r0, [r7, #4]
|
|
8007e00: f001 fd35 bl 800986e <USBD_LL_PrepareReceive>
|
|
CDC_OUT_EP,
|
|
hcdc->RxBuffer,
|
|
CDC_DATA_FS_OUT_PACKET_SIZE);
|
|
}
|
|
return USBD_OK;
|
|
8007e04: 2300 movs r3, #0
|
|
8007e06: e000 b.n 8007e0a <USBD_CDC_ReceivePacket+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return USBD_FAIL;
|
|
8007e08: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007e0a: 4618 mov r0, r3
|
|
8007e0c: 3710 adds r7, #16
|
|
8007e0e: 46bd mov sp, r7
|
|
8007e10: bd80 pop {r7, pc}
|
|
|
|
08007e12 <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval None
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
8007e12: b580 push {r7, lr}
|
|
8007e14: b084 sub sp, #16
|
|
8007e16: af00 add r7, sp, #0
|
|
8007e18: 60f8 str r0, [r7, #12]
|
|
8007e1a: 60b9 str r1, [r7, #8]
|
|
8007e1c: 4613 mov r3, r2
|
|
8007e1e: 71fb strb r3, [r7, #7]
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
8007e20: 68fb ldr r3, [r7, #12]
|
|
8007e22: 2b00 cmp r3, #0
|
|
8007e24: d101 bne.n 8007e2a <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif
|
|
return USBD_FAIL;
|
|
8007e26: 2302 movs r3, #2
|
|
8007e28: e01a b.n 8007e60 <USBD_Init+0x4e>
|
|
}
|
|
|
|
/* Unlink previous class*/
|
|
if (pdev->pClass != NULL)
|
|
8007e2a: 68fb ldr r3, [r7, #12]
|
|
8007e2c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007e30: 2b00 cmp r3, #0
|
|
8007e32: d003 beq.n 8007e3c <USBD_Init+0x2a>
|
|
{
|
|
pdev->pClass = NULL;
|
|
8007e34: 68fb ldr r3, [r7, #12]
|
|
8007e36: 2200 movs r2, #0
|
|
8007e38: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
8007e3c: 68bb ldr r3, [r7, #8]
|
|
8007e3e: 2b00 cmp r3, #0
|
|
8007e40: d003 beq.n 8007e4a <USBD_Init+0x38>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
8007e42: 68fb ldr r3, [r7, #12]
|
|
8007e44: 68ba ldr r2, [r7, #8]
|
|
8007e46: f8c3 22b0 str.w r2, [r3, #688] @ 0x2b0
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007e4a: 68fb ldr r3, [r7, #12]
|
|
8007e4c: 2201 movs r2, #1
|
|
8007e4e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
8007e52: 68fb ldr r3, [r7, #12]
|
|
8007e54: 79fa ldrb r2, [r7, #7]
|
|
8007e56: 701a strb r2, [r3, #0]
|
|
/* Initialize low level driver */
|
|
USBD_LL_Init(pdev);
|
|
8007e58: 68f8 ldr r0, [r7, #12]
|
|
8007e5a: f001 fba3 bl 80095a4 <USBD_LL_Init>
|
|
|
|
return USBD_OK;
|
|
8007e5e: 2300 movs r3, #0
|
|
}
|
|
8007e60: 4618 mov r0, r3
|
|
8007e62: 3710 adds r7, #16
|
|
8007e64: 46bd mov sp, r7
|
|
8007e66: bd80 pop {r7, pc}
|
|
|
|
08007e68 <USBD_RegisterClass>:
|
|
* @param pDevice : Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
8007e68: b480 push {r7}
|
|
8007e6a: b085 sub sp, #20
|
|
8007e6c: af00 add r7, sp, #0
|
|
8007e6e: 6078 str r0, [r7, #4]
|
|
8007e70: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef status = USBD_OK;
|
|
8007e72: 2300 movs r3, #0
|
|
8007e74: 73fb strb r3, [r7, #15]
|
|
if (pclass != NULL)
|
|
8007e76: 683b ldr r3, [r7, #0]
|
|
8007e78: 2b00 cmp r3, #0
|
|
8007e7a: d006 beq.n 8007e8a <USBD_RegisterClass+0x22>
|
|
{
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass = pclass;
|
|
8007e7c: 687b ldr r3, [r7, #4]
|
|
8007e7e: 683a ldr r2, [r7, #0]
|
|
8007e80: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
status = USBD_OK;
|
|
8007e84: 2300 movs r3, #0
|
|
8007e86: 73fb strb r3, [r7, #15]
|
|
8007e88: e001 b.n 8007e8e <USBD_RegisterClass+0x26>
|
|
else
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif
|
|
status = USBD_FAIL;
|
|
8007e8a: 2302 movs r3, #2
|
|
8007e8c: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return status;
|
|
8007e8e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007e90: 4618 mov r0, r3
|
|
8007e92: 3714 adds r7, #20
|
|
8007e94: 46bd mov sp, r7
|
|
8007e96: bc80 pop {r7}
|
|
8007e98: 4770 bx lr
|
|
|
|
08007e9a <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007e9a: b580 push {r7, lr}
|
|
8007e9c: b082 sub sp, #8
|
|
8007e9e: af00 add r7, sp, #0
|
|
8007ea0: 6078 str r0, [r7, #4]
|
|
/* Start the low level driver */
|
|
USBD_LL_Start(pdev);
|
|
8007ea2: 6878 ldr r0, [r7, #4]
|
|
8007ea4: f001 fbd8 bl 8009658 <USBD_LL_Start>
|
|
|
|
return USBD_OK;
|
|
8007ea8: 2300 movs r3, #0
|
|
}
|
|
8007eaa: 4618 mov r0, r3
|
|
8007eac: 3708 adds r7, #8
|
|
8007eae: 46bd mov sp, r7
|
|
8007eb0: bd80 pop {r7, pc}
|
|
|
|
08007eb2 <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007eb2: b480 push {r7}
|
|
8007eb4: b083 sub sp, #12
|
|
8007eb6: af00 add r7, sp, #0
|
|
8007eb8: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8007eba: 2300 movs r3, #0
|
|
}
|
|
8007ebc: 4618 mov r0, r3
|
|
8007ebe: 370c adds r7, #12
|
|
8007ec0: 46bd mov sp, r7
|
|
8007ec2: bc80 pop {r7}
|
|
8007ec4: 4770 bx lr
|
|
|
|
08007ec6 <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8007ec6: b580 push {r7, lr}
|
|
8007ec8: b084 sub sp, #16
|
|
8007eca: af00 add r7, sp, #0
|
|
8007ecc: 6078 str r0, [r7, #4]
|
|
8007ece: 460b mov r3, r1
|
|
8007ed0: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_FAIL;
|
|
8007ed2: 2302 movs r3, #2
|
|
8007ed4: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->pClass != NULL)
|
|
8007ed6: 687b ldr r3, [r7, #4]
|
|
8007ed8: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007edc: 2b00 cmp r3, #0
|
|
8007ede: d00c beq.n 8007efa <USBD_SetClassConfig+0x34>
|
|
{
|
|
/* Set configuration and Start the Class*/
|
|
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
|
|
8007ee0: 687b ldr r3, [r7, #4]
|
|
8007ee2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007ee6: 681b ldr r3, [r3, #0]
|
|
8007ee8: 78fa ldrb r2, [r7, #3]
|
|
8007eea: 4611 mov r1, r2
|
|
8007eec: 6878 ldr r0, [r7, #4]
|
|
8007eee: 4798 blx r3
|
|
8007ef0: 4603 mov r3, r0
|
|
8007ef2: 2b00 cmp r3, #0
|
|
8007ef4: d101 bne.n 8007efa <USBD_SetClassConfig+0x34>
|
|
{
|
|
ret = USBD_OK;
|
|
8007ef6: 2300 movs r3, #0
|
|
8007ef8: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
8007efa: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007efc: 4618 mov r0, r3
|
|
8007efe: 3710 adds r7, #16
|
|
8007f00: 46bd mov sp, r7
|
|
8007f02: bd80 pop {r7, pc}
|
|
|
|
08007f04 <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status: USBD_StatusTypeDef
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8007f04: b580 push {r7, lr}
|
|
8007f06: b082 sub sp, #8
|
|
8007f08: af00 add r7, sp, #0
|
|
8007f0a: 6078 str r0, [r7, #4]
|
|
8007f0c: 460b mov r3, r1
|
|
8007f0e: 70fb strb r3, [r7, #3]
|
|
/* Clear configuration and De-initialize the Class process*/
|
|
pdev->pClass->DeInit(pdev, cfgidx);
|
|
8007f10: 687b ldr r3, [r7, #4]
|
|
8007f12: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007f16: 685b ldr r3, [r3, #4]
|
|
8007f18: 78fa ldrb r2, [r7, #3]
|
|
8007f1a: 4611 mov r1, r2
|
|
8007f1c: 6878 ldr r0, [r7, #4]
|
|
8007f1e: 4798 blx r3
|
|
|
|
return USBD_OK;
|
|
8007f20: 2300 movs r3, #0
|
|
}
|
|
8007f22: 4618 mov r0, r3
|
|
8007f24: 3708 adds r7, #8
|
|
8007f26: 46bd mov sp, r7
|
|
8007f28: bd80 pop {r7, pc}
|
|
|
|
08007f2a <USBD_LL_SetupStage>:
|
|
* Handle the setup stage
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
8007f2a: b580 push {r7, lr}
|
|
8007f2c: b082 sub sp, #8
|
|
8007f2e: af00 add r7, sp, #0
|
|
8007f30: 6078 str r0, [r7, #4]
|
|
8007f32: 6039 str r1, [r7, #0]
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
8007f34: 687b ldr r3, [r7, #4]
|
|
8007f36: f503 732a add.w r3, r3, #680 @ 0x2a8
|
|
8007f3a: 6839 ldr r1, [r7, #0]
|
|
8007f3c: 4618 mov r0, r3
|
|
8007f3e: f000 fed8 bl 8008cf2 <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
8007f42: 687b ldr r3, [r7, #4]
|
|
8007f44: 2201 movs r2, #1
|
|
8007f46: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
8007f4a: 687b ldr r3, [r7, #4]
|
|
8007f4c: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8007f50: 461a mov r2, r3
|
|
8007f52: 687b ldr r3, [r7, #4]
|
|
8007f54: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8007f58: 687b ldr r3, [r7, #4]
|
|
8007f5a: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
|
|
8007f5e: f003 031f and.w r3, r3, #31
|
|
8007f62: 2b02 cmp r3, #2
|
|
8007f64: d016 beq.n 8007f94 <USBD_LL_SetupStage+0x6a>
|
|
8007f66: 2b02 cmp r3, #2
|
|
8007f68: d81c bhi.n 8007fa4 <USBD_LL_SetupStage+0x7a>
|
|
8007f6a: 2b00 cmp r3, #0
|
|
8007f6c: d002 beq.n 8007f74 <USBD_LL_SetupStage+0x4a>
|
|
8007f6e: 2b01 cmp r3, #1
|
|
8007f70: d008 beq.n 8007f84 <USBD_LL_SetupStage+0x5a>
|
|
8007f72: e017 b.n 8007fa4 <USBD_LL_SetupStage+0x7a>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
USBD_StdDevReq(pdev, &pdev->request);
|
|
8007f74: 687b ldr r3, [r7, #4]
|
|
8007f76: f503 732a add.w r3, r3, #680 @ 0x2a8
|
|
8007f7a: 4619 mov r1, r3
|
|
8007f7c: 6878 ldr r0, [r7, #4]
|
|
8007f7e: f000 f9cb bl 8008318 <USBD_StdDevReq>
|
|
break;
|
|
8007f82: e01a b.n 8007fba <USBD_LL_SetupStage+0x90>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
USBD_StdItfReq(pdev, &pdev->request);
|
|
8007f84: 687b ldr r3, [r7, #4]
|
|
8007f86: f503 732a add.w r3, r3, #680 @ 0x2a8
|
|
8007f8a: 4619 mov r1, r3
|
|
8007f8c: 6878 ldr r0, [r7, #4]
|
|
8007f8e: f000 fa2d bl 80083ec <USBD_StdItfReq>
|
|
break;
|
|
8007f92: e012 b.n 8007fba <USBD_LL_SetupStage+0x90>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
USBD_StdEPReq(pdev, &pdev->request);
|
|
8007f94: 687b ldr r3, [r7, #4]
|
|
8007f96: f503 732a add.w r3, r3, #680 @ 0x2a8
|
|
8007f9a: 4619 mov r1, r3
|
|
8007f9c: 6878 ldr r0, [r7, #4]
|
|
8007f9e: f000 fa6d bl 800847c <USBD_StdEPReq>
|
|
break;
|
|
8007fa2: e00a b.n 8007fba <USBD_LL_SetupStage+0x90>
|
|
|
|
default:
|
|
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
8007fa4: 687b ldr r3, [r7, #4]
|
|
8007fa6: f893 32a8 ldrb.w r3, [r3, #680] @ 0x2a8
|
|
8007faa: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8007fae: b2db uxtb r3, r3
|
|
8007fb0: 4619 mov r1, r3
|
|
8007fb2: 6878 ldr r0, [r7, #4]
|
|
8007fb4: f001 fbb0 bl 8009718 <USBD_LL_StallEP>
|
|
break;
|
|
8007fb8: bf00 nop
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007fba: 2300 movs r3, #0
|
|
}
|
|
8007fbc: 4618 mov r0, r3
|
|
8007fbe: 3708 adds r7, #8
|
|
8007fc0: 46bd mov sp, r7
|
|
8007fc2: bd80 pop {r7, pc}
|
|
|
|
08007fc4 <USBD_LL_DataOutStage>:
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8007fc4: b580 push {r7, lr}
|
|
8007fc6: b086 sub sp, #24
|
|
8007fc8: af00 add r7, sp, #0
|
|
8007fca: 60f8 str r0, [r7, #12]
|
|
8007fcc: 460b mov r3, r1
|
|
8007fce: 607a str r2, [r7, #4]
|
|
8007fd0: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
|
|
if (epnum == 0U)
|
|
8007fd2: 7afb ldrb r3, [r7, #11]
|
|
8007fd4: 2b00 cmp r3, #0
|
|
8007fd6: d14b bne.n 8008070 <USBD_LL_DataOutStage+0xac>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
8007fd8: 68fb ldr r3, [r7, #12]
|
|
8007fda: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
8007fde: 617b str r3, [r7, #20]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
8007fe0: 68fb ldr r3, [r7, #12]
|
|
8007fe2: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8007fe6: 2b03 cmp r3, #3
|
|
8007fe8: d134 bne.n 8008054 <USBD_LL_DataOutStage+0x90>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8007fea: 697b ldr r3, [r7, #20]
|
|
8007fec: 68da ldr r2, [r3, #12]
|
|
8007fee: 697b ldr r3, [r7, #20]
|
|
8007ff0: 691b ldr r3, [r3, #16]
|
|
8007ff2: 429a cmp r2, r3
|
|
8007ff4: d919 bls.n 800802a <USBD_LL_DataOutStage+0x66>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8007ff6: 697b ldr r3, [r7, #20]
|
|
8007ff8: 68da ldr r2, [r3, #12]
|
|
8007ffa: 697b ldr r3, [r7, #20]
|
|
8007ffc: 691b ldr r3, [r3, #16]
|
|
8007ffe: 1ad2 subs r2, r2, r3
|
|
8008000: 697b ldr r3, [r7, #20]
|
|
8008002: 60da str r2, [r3, #12]
|
|
|
|
USBD_CtlContinueRx(pdev, pdata,
|
|
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
|
|
8008004: 697b ldr r3, [r7, #20]
|
|
8008006: 68da ldr r2, [r3, #12]
|
|
8008008: 697b ldr r3, [r7, #20]
|
|
800800a: 691b ldr r3, [r3, #16]
|
|
USBD_CtlContinueRx(pdev, pdata,
|
|
800800c: 429a cmp r2, r3
|
|
800800e: d203 bcs.n 8008018 <USBD_LL_DataOutStage+0x54>
|
|
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
|
|
8008010: 697b ldr r3, [r7, #20]
|
|
8008012: 68db ldr r3, [r3, #12]
|
|
USBD_CtlContinueRx(pdev, pdata,
|
|
8008014: b29b uxth r3, r3
|
|
8008016: e002 b.n 800801e <USBD_LL_DataOutStage+0x5a>
|
|
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
|
|
8008018: 697b ldr r3, [r7, #20]
|
|
800801a: 691b ldr r3, [r3, #16]
|
|
USBD_CtlContinueRx(pdev, pdata,
|
|
800801c: b29b uxth r3, r3
|
|
800801e: 461a mov r2, r3
|
|
8008020: 6879 ldr r1, [r7, #4]
|
|
8008022: 68f8 ldr r0, [r7, #12]
|
|
8008024: f000 ff54 bl 8008ed0 <USBD_CtlContinueRx>
|
|
8008028: e038 b.n 800809c <USBD_LL_DataOutStage+0xd8>
|
|
}
|
|
else
|
|
{
|
|
if ((pdev->pClass->EP0_RxReady != NULL) &&
|
|
800802a: 68fb ldr r3, [r7, #12]
|
|
800802c: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008030: 691b ldr r3, [r3, #16]
|
|
8008032: 2b00 cmp r3, #0
|
|
8008034: d00a beq.n 800804c <USBD_LL_DataOutStage+0x88>
|
|
(pdev->dev_state == USBD_STATE_CONFIGURED))
|
|
8008036: 68fb ldr r3, [r7, #12]
|
|
8008038: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
if ((pdev->pClass->EP0_RxReady != NULL) &&
|
|
800803c: 2b03 cmp r3, #3
|
|
800803e: d105 bne.n 800804c <USBD_LL_DataOutStage+0x88>
|
|
{
|
|
pdev->pClass->EP0_RxReady(pdev);
|
|
8008040: 68fb ldr r3, [r7, #12]
|
|
8008042: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008046: 691b ldr r3, [r3, #16]
|
|
8008048: 68f8 ldr r0, [r7, #12]
|
|
800804a: 4798 blx r3
|
|
}
|
|
USBD_CtlSendStatus(pdev);
|
|
800804c: 68f8 ldr r0, [r7, #12]
|
|
800804e: f000 ff51 bl 8008ef4 <USBD_CtlSendStatus>
|
|
8008052: e023 b.n 800809c <USBD_LL_DataOutStage+0xd8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
|
|
8008054: 68fb ldr r3, [r7, #12]
|
|
8008056: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
800805a: 2b05 cmp r3, #5
|
|
800805c: d11e bne.n 800809c <USBD_LL_DataOutStage+0xd8>
|
|
{
|
|
/*
|
|
* STATUS PHASE completed, update ep0_state to idle
|
|
*/
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
800805e: 68fb ldr r3, [r7, #12]
|
|
8008060: 2200 movs r2, #0
|
|
8008062: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
USBD_LL_StallEP(pdev, 0U);
|
|
8008066: 2100 movs r1, #0
|
|
8008068: 68f8 ldr r0, [r7, #12]
|
|
800806a: f001 fb55 bl 8009718 <USBD_LL_StallEP>
|
|
800806e: e015 b.n 800809c <USBD_LL_DataOutStage+0xd8>
|
|
}
|
|
}
|
|
}
|
|
else if ((pdev->pClass->DataOut != NULL) &&
|
|
8008070: 68fb ldr r3, [r7, #12]
|
|
8008072: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008076: 699b ldr r3, [r3, #24]
|
|
8008078: 2b00 cmp r3, #0
|
|
800807a: d00d beq.n 8008098 <USBD_LL_DataOutStage+0xd4>
|
|
(pdev->dev_state == USBD_STATE_CONFIGURED))
|
|
800807c: 68fb ldr r3, [r7, #12]
|
|
800807e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
else if ((pdev->pClass->DataOut != NULL) &&
|
|
8008082: 2b03 cmp r3, #3
|
|
8008084: d108 bne.n 8008098 <USBD_LL_DataOutStage+0xd4>
|
|
{
|
|
pdev->pClass->DataOut(pdev, epnum);
|
|
8008086: 68fb ldr r3, [r7, #12]
|
|
8008088: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800808c: 699b ldr r3, [r3, #24]
|
|
800808e: 7afa ldrb r2, [r7, #11]
|
|
8008090: 4611 mov r1, r2
|
|
8008092: 68f8 ldr r0, [r7, #12]
|
|
8008094: 4798 blx r3
|
|
8008096: e001 b.n 800809c <USBD_LL_DataOutStage+0xd8>
|
|
}
|
|
else
|
|
{
|
|
/* should never be in this condition */
|
|
return USBD_FAIL;
|
|
8008098: 2302 movs r3, #2
|
|
800809a: e000 b.n 800809e <USBD_LL_DataOutStage+0xda>
|
|
}
|
|
|
|
return USBD_OK;
|
|
800809c: 2300 movs r3, #0
|
|
}
|
|
800809e: 4618 mov r0, r3
|
|
80080a0: 3718 adds r7, #24
|
|
80080a2: 46bd mov sp, r7
|
|
80080a4: bd80 pop {r7, pc}
|
|
|
|
080080a6 <USBD_LL_DataInStage>:
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
80080a6: b580 push {r7, lr}
|
|
80080a8: b086 sub sp, #24
|
|
80080aa: af00 add r7, sp, #0
|
|
80080ac: 60f8 str r0, [r7, #12]
|
|
80080ae: 460b mov r3, r1
|
|
80080b0: 607a str r2, [r7, #4]
|
|
80080b2: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
|
|
if (epnum == 0U)
|
|
80080b4: 7afb ldrb r3, [r7, #11]
|
|
80080b6: 2b00 cmp r3, #0
|
|
80080b8: d17f bne.n 80081ba <USBD_LL_DataInStage+0x114>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
80080ba: 68fb ldr r3, [r7, #12]
|
|
80080bc: 3314 adds r3, #20
|
|
80080be: 617b str r3, [r7, #20]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
80080c0: 68fb ldr r3, [r7, #12]
|
|
80080c2: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
80080c6: 2b02 cmp r3, #2
|
|
80080c8: d15c bne.n 8008184 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
80080ca: 697b ldr r3, [r7, #20]
|
|
80080cc: 68da ldr r2, [r3, #12]
|
|
80080ce: 697b ldr r3, [r7, #20]
|
|
80080d0: 691b ldr r3, [r3, #16]
|
|
80080d2: 429a cmp r2, r3
|
|
80080d4: d915 bls.n 8008102 <USBD_LL_DataInStage+0x5c>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
80080d6: 697b ldr r3, [r7, #20]
|
|
80080d8: 68da ldr r2, [r3, #12]
|
|
80080da: 697b ldr r3, [r7, #20]
|
|
80080dc: 691b ldr r3, [r3, #16]
|
|
80080de: 1ad2 subs r2, r2, r3
|
|
80080e0: 697b ldr r3, [r7, #20]
|
|
80080e2: 60da str r2, [r3, #12]
|
|
|
|
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
|
|
80080e4: 697b ldr r3, [r7, #20]
|
|
80080e6: 68db ldr r3, [r3, #12]
|
|
80080e8: b29b uxth r3, r3
|
|
80080ea: 461a mov r2, r3
|
|
80080ec: 6879 ldr r1, [r7, #4]
|
|
80080ee: 68f8 ldr r0, [r7, #12]
|
|
80080f0: f000 febe bl 8008e70 <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
80080f4: 2300 movs r3, #0
|
|
80080f6: 2200 movs r2, #0
|
|
80080f8: 2100 movs r1, #0
|
|
80080fa: 68f8 ldr r0, [r7, #12]
|
|
80080fc: f001 fbb7 bl 800986e <USBD_LL_PrepareReceive>
|
|
8008100: e04e b.n 80081a0 <USBD_LL_DataInStage+0xfa>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->total_length % pep->maxpacket == 0U) &&
|
|
8008102: 697b ldr r3, [r7, #20]
|
|
8008104: 689b ldr r3, [r3, #8]
|
|
8008106: 697a ldr r2, [r7, #20]
|
|
8008108: 6912 ldr r2, [r2, #16]
|
|
800810a: fbb3 f1f2 udiv r1, r3, r2
|
|
800810e: fb01 f202 mul.w r2, r1, r2
|
|
8008112: 1a9b subs r3, r3, r2
|
|
8008114: 2b00 cmp r3, #0
|
|
8008116: d11c bne.n 8008152 <USBD_LL_DataInStage+0xac>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8008118: 697b ldr r3, [r7, #20]
|
|
800811a: 689a ldr r2, [r3, #8]
|
|
800811c: 697b ldr r3, [r7, #20]
|
|
800811e: 691b ldr r3, [r3, #16]
|
|
if ((pep->total_length % pep->maxpacket == 0U) &&
|
|
8008120: 429a cmp r2, r3
|
|
8008122: d316 bcc.n 8008152 <USBD_LL_DataInStage+0xac>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
8008124: 697b ldr r3, [r7, #20]
|
|
8008126: 689a ldr r2, [r3, #8]
|
|
8008128: 68fb ldr r3, [r7, #12]
|
|
800812a: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
800812e: 429a cmp r2, r3
|
|
8008130: d20f bcs.n 8008152 <USBD_LL_DataInStage+0xac>
|
|
{
|
|
USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
8008132: 2200 movs r2, #0
|
|
8008134: 2100 movs r1, #0
|
|
8008136: 68f8 ldr r0, [r7, #12]
|
|
8008138: f000 fe9a bl 8008e70 <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
800813c: 68fb ldr r3, [r7, #12]
|
|
800813e: 2200 movs r2, #0
|
|
8008140: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8008144: 2300 movs r3, #0
|
|
8008146: 2200 movs r2, #0
|
|
8008148: 2100 movs r1, #0
|
|
800814a: 68f8 ldr r0, [r7, #12]
|
|
800814c: f001 fb8f bl 800986e <USBD_LL_PrepareReceive>
|
|
8008150: e026 b.n 80081a0 <USBD_LL_DataInStage+0xfa>
|
|
}
|
|
else
|
|
{
|
|
if ((pdev->pClass->EP0_TxSent != NULL) &&
|
|
8008152: 68fb ldr r3, [r7, #12]
|
|
8008154: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008158: 68db ldr r3, [r3, #12]
|
|
800815a: 2b00 cmp r3, #0
|
|
800815c: d00a beq.n 8008174 <USBD_LL_DataInStage+0xce>
|
|
(pdev->dev_state == USBD_STATE_CONFIGURED))
|
|
800815e: 68fb ldr r3, [r7, #12]
|
|
8008160: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
if ((pdev->pClass->EP0_TxSent != NULL) &&
|
|
8008164: 2b03 cmp r3, #3
|
|
8008166: d105 bne.n 8008174 <USBD_LL_DataInStage+0xce>
|
|
{
|
|
pdev->pClass->EP0_TxSent(pdev);
|
|
8008168: 68fb ldr r3, [r7, #12]
|
|
800816a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800816e: 68db ldr r3, [r3, #12]
|
|
8008170: 68f8 ldr r0, [r7, #12]
|
|
8008172: 4798 blx r3
|
|
}
|
|
USBD_LL_StallEP(pdev, 0x80U);
|
|
8008174: 2180 movs r1, #128 @ 0x80
|
|
8008176: 68f8 ldr r0, [r7, #12]
|
|
8008178: f001 face bl 8009718 <USBD_LL_StallEP>
|
|
USBD_CtlReceiveStatus(pdev);
|
|
800817c: 68f8 ldr r0, [r7, #12]
|
|
800817e: f000 fecc bl 8008f1a <USBD_CtlReceiveStatus>
|
|
8008182: e00d b.n 80081a0 <USBD_LL_DataInStage+0xfa>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
|
|
8008184: 68fb ldr r3, [r7, #12]
|
|
8008186: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
800818a: 2b04 cmp r3, #4
|
|
800818c: d004 beq.n 8008198 <USBD_LL_DataInStage+0xf2>
|
|
(pdev->ep0_state == USBD_EP0_IDLE))
|
|
800818e: 68fb ldr r3, [r7, #12]
|
|
8008190: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
|
|
8008194: 2b00 cmp r3, #0
|
|
8008196: d103 bne.n 80081a0 <USBD_LL_DataInStage+0xfa>
|
|
{
|
|
USBD_LL_StallEP(pdev, 0x80U);
|
|
8008198: 2180 movs r1, #128 @ 0x80
|
|
800819a: 68f8 ldr r0, [r7, #12]
|
|
800819c: f001 fabc bl 8009718 <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode == 1U)
|
|
80081a0: 68fb ldr r3, [r7, #12]
|
|
80081a2: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
80081a6: 2b01 cmp r3, #1
|
|
80081a8: d11d bne.n 80081e6 <USBD_LL_DataInStage+0x140>
|
|
{
|
|
USBD_RunTestMode(pdev);
|
|
80081aa: 68f8 ldr r0, [r7, #12]
|
|
80081ac: f7ff fe81 bl 8007eb2 <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
80081b0: 68fb ldr r3, [r7, #12]
|
|
80081b2: 2200 movs r2, #0
|
|
80081b4: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
80081b8: e015 b.n 80081e6 <USBD_LL_DataInStage+0x140>
|
|
}
|
|
}
|
|
else if ((pdev->pClass->DataIn != NULL) &&
|
|
80081ba: 68fb ldr r3, [r7, #12]
|
|
80081bc: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80081c0: 695b ldr r3, [r3, #20]
|
|
80081c2: 2b00 cmp r3, #0
|
|
80081c4: d00d beq.n 80081e2 <USBD_LL_DataInStage+0x13c>
|
|
(pdev->dev_state == USBD_STATE_CONFIGURED))
|
|
80081c6: 68fb ldr r3, [r7, #12]
|
|
80081c8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
else if ((pdev->pClass->DataIn != NULL) &&
|
|
80081cc: 2b03 cmp r3, #3
|
|
80081ce: d108 bne.n 80081e2 <USBD_LL_DataInStage+0x13c>
|
|
{
|
|
pdev->pClass->DataIn(pdev, epnum);
|
|
80081d0: 68fb ldr r3, [r7, #12]
|
|
80081d2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80081d6: 695b ldr r3, [r3, #20]
|
|
80081d8: 7afa ldrb r2, [r7, #11]
|
|
80081da: 4611 mov r1, r2
|
|
80081dc: 68f8 ldr r0, [r7, #12]
|
|
80081de: 4798 blx r3
|
|
80081e0: e001 b.n 80081e6 <USBD_LL_DataInStage+0x140>
|
|
}
|
|
else
|
|
{
|
|
/* should never be in this condition */
|
|
return USBD_FAIL;
|
|
80081e2: 2302 movs r3, #2
|
|
80081e4: e000 b.n 80081e8 <USBD_LL_DataInStage+0x142>
|
|
}
|
|
|
|
return USBD_OK;
|
|
80081e6: 2300 movs r3, #0
|
|
}
|
|
80081e8: 4618 mov r0, r3
|
|
80081ea: 3718 adds r7, #24
|
|
80081ec: 46bd mov sp, r7
|
|
80081ee: bd80 pop {r7, pc}
|
|
|
|
080081f0 <USBD_LL_Reset>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80081f0: b580 push {r7, lr}
|
|
80081f2: b082 sub sp, #8
|
|
80081f4: af00 add r7, sp, #0
|
|
80081f6: 6078 str r0, [r7, #4]
|
|
/* Open EP0 OUT */
|
|
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
80081f8: 2340 movs r3, #64 @ 0x40
|
|
80081fa: 2200 movs r2, #0
|
|
80081fc: 2100 movs r1, #0
|
|
80081fe: 6878 ldr r0, [r7, #4]
|
|
8008200: f001 fa45 bl 800968e <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8008204: 687b ldr r3, [r7, #4]
|
|
8008206: 2201 movs r2, #1
|
|
8008208: f8c3 2158 str.w r2, [r3, #344] @ 0x158
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
800820c: 687b ldr r3, [r7, #4]
|
|
800820e: 2240 movs r2, #64 @ 0x40
|
|
8008210: f8c3 2164 str.w r2, [r3, #356] @ 0x164
|
|
|
|
/* Open EP0 IN */
|
|
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8008214: 2340 movs r3, #64 @ 0x40
|
|
8008216: 2200 movs r2, #0
|
|
8008218: 2180 movs r1, #128 @ 0x80
|
|
800821a: 6878 ldr r0, [r7, #4]
|
|
800821c: f001 fa37 bl 800968e <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8008220: 687b ldr r3, [r7, #4]
|
|
8008222: 2201 movs r2, #1
|
|
8008224: 619a str r2, [r3, #24]
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8008226: 687b ldr r3, [r7, #4]
|
|
8008228: 2240 movs r2, #64 @ 0x40
|
|
800822a: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
800822c: 687b ldr r3, [r7, #4]
|
|
800822e: 2201 movs r2, #1
|
|
8008230: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
8008234: 687b ldr r3, [r7, #4]
|
|
8008236: 2200 movs r2, #0
|
|
8008238: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
800823c: 687b ldr r3, [r7, #4]
|
|
800823e: 2200 movs r2, #0
|
|
8008240: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8008242: 687b ldr r3, [r7, #4]
|
|
8008244: 2200 movs r2, #0
|
|
8008246: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
|
|
if (pdev->pClassData)
|
|
800824a: 687b ldr r3, [r7, #4]
|
|
800824c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008250: 2b00 cmp r3, #0
|
|
8008252: d009 beq.n 8008268 <USBD_LL_Reset+0x78>
|
|
{
|
|
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
|
|
8008254: 687b ldr r3, [r7, #4]
|
|
8008256: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800825a: 685b ldr r3, [r3, #4]
|
|
800825c: 687a ldr r2, [r7, #4]
|
|
800825e: 6852 ldr r2, [r2, #4]
|
|
8008260: b2d2 uxtb r2, r2
|
|
8008262: 4611 mov r1, r2
|
|
8008264: 6878 ldr r0, [r7, #4]
|
|
8008266: 4798 blx r3
|
|
}
|
|
|
|
return USBD_OK;
|
|
8008268: 2300 movs r3, #0
|
|
}
|
|
800826a: 4618 mov r0, r3
|
|
800826c: 3708 adds r7, #8
|
|
800826e: 46bd mov sp, r7
|
|
8008270: bd80 pop {r7, pc}
|
|
|
|
08008272 <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8008272: b480 push {r7}
|
|
8008274: b083 sub sp, #12
|
|
8008276: af00 add r7, sp, #0
|
|
8008278: 6078 str r0, [r7, #4]
|
|
800827a: 460b mov r3, r1
|
|
800827c: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
800827e: 687b ldr r3, [r7, #4]
|
|
8008280: 78fa ldrb r2, [r7, #3]
|
|
8008282: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
8008284: 2300 movs r3, #0
|
|
}
|
|
8008286: 4618 mov r0, r3
|
|
8008288: 370c adds r7, #12
|
|
800828a: 46bd mov sp, r7
|
|
800828c: bc80 pop {r7}
|
|
800828e: 4770 bx lr
|
|
|
|
08008290 <USBD_LL_Suspend>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008290: b480 push {r7}
|
|
8008292: b083 sub sp, #12
|
|
8008294: af00 add r7, sp, #0
|
|
8008296: 6078 str r0, [r7, #4]
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
8008298: 687b ldr r3, [r7, #4]
|
|
800829a: f893 229c ldrb.w r2, [r3, #668] @ 0x29c
|
|
800829e: 687b ldr r3, [r7, #4]
|
|
80082a0: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
80082a4: 687b ldr r3, [r7, #4]
|
|
80082a6: 2204 movs r2, #4
|
|
80082a8: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
80082ac: 2300 movs r3, #0
|
|
}
|
|
80082ae: 4618 mov r0, r3
|
|
80082b0: 370c adds r7, #12
|
|
80082b2: 46bd mov sp, r7
|
|
80082b4: bc80 pop {r7}
|
|
80082b6: 4770 bx lr
|
|
|
|
080082b8 <USBD_LL_Resume>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80082b8: b480 push {r7}
|
|
80082ba: b083 sub sp, #12
|
|
80082bc: af00 add r7, sp, #0
|
|
80082be: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
80082c0: 687b ldr r3, [r7, #4]
|
|
80082c2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80082c6: 2b04 cmp r3, #4
|
|
80082c8: d105 bne.n 80082d6 <USBD_LL_Resume+0x1e>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
80082ca: 687b ldr r3, [r7, #4]
|
|
80082cc: f893 229d ldrb.w r2, [r3, #669] @ 0x29d
|
|
80082d0: 687b ldr r3, [r7, #4]
|
|
80082d2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
80082d6: 2300 movs r3, #0
|
|
}
|
|
80082d8: 4618 mov r0, r3
|
|
80082da: 370c adds r7, #12
|
|
80082dc: 46bd mov sp, r7
|
|
80082de: bc80 pop {r7}
|
|
80082e0: 4770 bx lr
|
|
|
|
080082e2 <USBD_LL_SOF>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80082e2: b580 push {r7, lr}
|
|
80082e4: b082 sub sp, #8
|
|
80082e6: af00 add r7, sp, #0
|
|
80082e8: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80082ea: 687b ldr r3, [r7, #4]
|
|
80082ec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80082f0: 2b03 cmp r3, #3
|
|
80082f2: d10b bne.n 800830c <USBD_LL_SOF+0x2a>
|
|
{
|
|
if (pdev->pClass->SOF != NULL)
|
|
80082f4: 687b ldr r3, [r7, #4]
|
|
80082f6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80082fa: 69db ldr r3, [r3, #28]
|
|
80082fc: 2b00 cmp r3, #0
|
|
80082fe: d005 beq.n 800830c <USBD_LL_SOF+0x2a>
|
|
{
|
|
pdev->pClass->SOF(pdev);
|
|
8008300: 687b ldr r3, [r7, #4]
|
|
8008302: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008306: 69db ldr r3, [r3, #28]
|
|
8008308: 6878 ldr r0, [r7, #4]
|
|
800830a: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
800830c: 2300 movs r3, #0
|
|
}
|
|
800830e: 4618 mov r0, r3
|
|
8008310: 3708 adds r7, #8
|
|
8008312: 46bd mov sp, r7
|
|
8008314: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008318 <USBD_StdDevReq>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
8008318: b580 push {r7, lr}
|
|
800831a: b084 sub sp, #16
|
|
800831c: af00 add r7, sp, #0
|
|
800831e: 6078 str r0, [r7, #4]
|
|
8008320: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008322: 2300 movs r3, #0
|
|
8008324: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8008326: 683b ldr r3, [r7, #0]
|
|
8008328: 781b ldrb r3, [r3, #0]
|
|
800832a: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
800832e: 2b40 cmp r3, #64 @ 0x40
|
|
8008330: d005 beq.n 800833e <USBD_StdDevReq+0x26>
|
|
8008332: 2b40 cmp r3, #64 @ 0x40
|
|
8008334: d84f bhi.n 80083d6 <USBD_StdDevReq+0xbe>
|
|
8008336: 2b00 cmp r3, #0
|
|
8008338: d009 beq.n 800834e <USBD_StdDevReq+0x36>
|
|
800833a: 2b20 cmp r3, #32
|
|
800833c: d14b bne.n 80083d6 <USBD_StdDevReq+0xbe>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
pdev->pClass->Setup(pdev, req);
|
|
800833e: 687b ldr r3, [r7, #4]
|
|
8008340: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008344: 689b ldr r3, [r3, #8]
|
|
8008346: 6839 ldr r1, [r7, #0]
|
|
8008348: 6878 ldr r0, [r7, #4]
|
|
800834a: 4798 blx r3
|
|
break;
|
|
800834c: e048 b.n 80083e0 <USBD_StdDevReq+0xc8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
800834e: 683b ldr r3, [r7, #0]
|
|
8008350: 785b ldrb r3, [r3, #1]
|
|
8008352: 2b09 cmp r3, #9
|
|
8008354: d839 bhi.n 80083ca <USBD_StdDevReq+0xb2>
|
|
8008356: a201 add r2, pc, #4 @ (adr r2, 800835c <USBD_StdDevReq+0x44>)
|
|
8008358: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800835c: 080083ad .word 0x080083ad
|
|
8008360: 080083c1 .word 0x080083c1
|
|
8008364: 080083cb .word 0x080083cb
|
|
8008368: 080083b7 .word 0x080083b7
|
|
800836c: 080083cb .word 0x080083cb
|
|
8008370: 0800838f .word 0x0800838f
|
|
8008374: 08008385 .word 0x08008385
|
|
8008378: 080083cb .word 0x080083cb
|
|
800837c: 080083a3 .word 0x080083a3
|
|
8008380: 08008399 .word 0x08008399
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
8008384: 6839 ldr r1, [r7, #0]
|
|
8008386: 6878 ldr r0, [r7, #4]
|
|
8008388: f000 f9dc bl 8008744 <USBD_GetDescriptor>
|
|
break;
|
|
800838c: e022 b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
800838e: 6839 ldr r1, [r7, #0]
|
|
8008390: 6878 ldr r0, [r7, #4]
|
|
8008392: f000 fb3f bl 8008a14 <USBD_SetAddress>
|
|
break;
|
|
8008396: e01d b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
USBD_SetConfig(pdev, req);
|
|
8008398: 6839 ldr r1, [r7, #0]
|
|
800839a: 6878 ldr r0, [r7, #4]
|
|
800839c: f000 fb7e bl 8008a9c <USBD_SetConfig>
|
|
break;
|
|
80083a0: e018 b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
80083a2: 6839 ldr r1, [r7, #0]
|
|
80083a4: 6878 ldr r0, [r7, #4]
|
|
80083a6: f000 fc07 bl 8008bb8 <USBD_GetConfig>
|
|
break;
|
|
80083aa: e013 b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
80083ac: 6839 ldr r1, [r7, #0]
|
|
80083ae: 6878 ldr r0, [r7, #4]
|
|
80083b0: f000 fc37 bl 8008c22 <USBD_GetStatus>
|
|
break;
|
|
80083b4: e00e b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
80083b6: 6839 ldr r1, [r7, #0]
|
|
80083b8: 6878 ldr r0, [r7, #4]
|
|
80083ba: f000 fc65 bl 8008c88 <USBD_SetFeature>
|
|
break;
|
|
80083be: e009 b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
80083c0: 6839 ldr r1, [r7, #0]
|
|
80083c2: 6878 ldr r0, [r7, #4]
|
|
80083c4: f000 fc74 bl 8008cb0 <USBD_ClrFeature>
|
|
break;
|
|
80083c8: e004 b.n 80083d4 <USBD_StdDevReq+0xbc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80083ca: 6839 ldr r1, [r7, #0]
|
|
80083cc: 6878 ldr r0, [r7, #4]
|
|
80083ce: f000 fcc9 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
80083d2: bf00 nop
|
|
}
|
|
break;
|
|
80083d4: e004 b.n 80083e0 <USBD_StdDevReq+0xc8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80083d6: 6839 ldr r1, [r7, #0]
|
|
80083d8: 6878 ldr r0, [r7, #4]
|
|
80083da: f000 fcc3 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
80083de: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80083e0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80083e2: 4618 mov r0, r3
|
|
80083e4: 3710 adds r7, #16
|
|
80083e6: 46bd mov sp, r7
|
|
80083e8: bd80 pop {r7, pc}
|
|
80083ea: bf00 nop
|
|
|
|
080083ec <USBD_StdItfReq>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
80083ec: b580 push {r7, lr}
|
|
80083ee: b084 sub sp, #16
|
|
80083f0: af00 add r7, sp, #0
|
|
80083f2: 6078 str r0, [r7, #4]
|
|
80083f4: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80083f6: 2300 movs r3, #0
|
|
80083f8: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
80083fa: 683b ldr r3, [r7, #0]
|
|
80083fc: 781b ldrb r3, [r3, #0]
|
|
80083fe: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8008402: 2b40 cmp r3, #64 @ 0x40
|
|
8008404: d005 beq.n 8008412 <USBD_StdItfReq+0x26>
|
|
8008406: 2b40 cmp r3, #64 @ 0x40
|
|
8008408: d82e bhi.n 8008468 <USBD_StdItfReq+0x7c>
|
|
800840a: 2b00 cmp r3, #0
|
|
800840c: d001 beq.n 8008412 <USBD_StdItfReq+0x26>
|
|
800840e: 2b20 cmp r3, #32
|
|
8008410: d12a bne.n 8008468 <USBD_StdItfReq+0x7c>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
8008412: 687b ldr r3, [r7, #4]
|
|
8008414: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008418: 3b01 subs r3, #1
|
|
800841a: 2b02 cmp r3, #2
|
|
800841c: d81d bhi.n 800845a <USBD_StdItfReq+0x6e>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
800841e: 683b ldr r3, [r7, #0]
|
|
8008420: 889b ldrh r3, [r3, #4]
|
|
8008422: b2db uxtb r3, r3
|
|
8008424: 2b01 cmp r3, #1
|
|
8008426: d813 bhi.n 8008450 <USBD_StdItfReq+0x64>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
|
|
8008428: 687b ldr r3, [r7, #4]
|
|
800842a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800842e: 689b ldr r3, [r3, #8]
|
|
8008430: 6839 ldr r1, [r7, #0]
|
|
8008432: 6878 ldr r0, [r7, #4]
|
|
8008434: 4798 blx r3
|
|
8008436: 4603 mov r3, r0
|
|
8008438: 73fb strb r3, [r7, #15]
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
800843a: 683b ldr r3, [r7, #0]
|
|
800843c: 88db ldrh r3, [r3, #6]
|
|
800843e: 2b00 cmp r3, #0
|
|
8008440: d110 bne.n 8008464 <USBD_StdItfReq+0x78>
|
|
8008442: 7bfb ldrb r3, [r7, #15]
|
|
8008444: 2b00 cmp r3, #0
|
|
8008446: d10d bne.n 8008464 <USBD_StdItfReq+0x78>
|
|
{
|
|
USBD_CtlSendStatus(pdev);
|
|
8008448: 6878 ldr r0, [r7, #4]
|
|
800844a: f000 fd53 bl 8008ef4 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
800844e: e009 b.n 8008464 <USBD_StdItfReq+0x78>
|
|
USBD_CtlError(pdev, req);
|
|
8008450: 6839 ldr r1, [r7, #0]
|
|
8008452: 6878 ldr r0, [r7, #4]
|
|
8008454: f000 fc86 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008458: e004 b.n 8008464 <USBD_StdItfReq+0x78>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800845a: 6839 ldr r1, [r7, #0]
|
|
800845c: 6878 ldr r0, [r7, #4]
|
|
800845e: f000 fc81 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008462: e000 b.n 8008466 <USBD_StdItfReq+0x7a>
|
|
break;
|
|
8008464: bf00 nop
|
|
}
|
|
break;
|
|
8008466: e004 b.n 8008472 <USBD_StdItfReq+0x86>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008468: 6839 ldr r1, [r7, #0]
|
|
800846a: 6878 ldr r0, [r7, #4]
|
|
800846c: f000 fc7a bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008470: bf00 nop
|
|
}
|
|
|
|
return USBD_OK;
|
|
8008472: 2300 movs r3, #0
|
|
}
|
|
8008474: 4618 mov r0, r3
|
|
8008476: 3710 adds r7, #16
|
|
8008478: 46bd mov sp, r7
|
|
800847a: bd80 pop {r7, pc}
|
|
|
|
0800847c <USBD_StdEPReq>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
800847c: b580 push {r7, lr}
|
|
800847e: b084 sub sp, #16
|
|
8008480: af00 add r7, sp, #0
|
|
8008482: 6078 str r0, [r7, #4]
|
|
8008484: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008486: 2300 movs r3, #0
|
|
8008488: 73fb strb r3, [r7, #15]
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
800848a: 683b ldr r3, [r7, #0]
|
|
800848c: 889b ldrh r3, [r3, #4]
|
|
800848e: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8008490: 683b ldr r3, [r7, #0]
|
|
8008492: 781b ldrb r3, [r3, #0]
|
|
8008494: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8008498: 2b40 cmp r3, #64 @ 0x40
|
|
800849a: d007 beq.n 80084ac <USBD_StdEPReq+0x30>
|
|
800849c: 2b40 cmp r3, #64 @ 0x40
|
|
800849e: f200 8146 bhi.w 800872e <USBD_StdEPReq+0x2b2>
|
|
80084a2: 2b00 cmp r3, #0
|
|
80084a4: d00a beq.n 80084bc <USBD_StdEPReq+0x40>
|
|
80084a6: 2b20 cmp r3, #32
|
|
80084a8: f040 8141 bne.w 800872e <USBD_StdEPReq+0x2b2>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
pdev->pClass->Setup(pdev, req);
|
|
80084ac: 687b ldr r3, [r7, #4]
|
|
80084ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084b2: 689b ldr r3, [r3, #8]
|
|
80084b4: 6839 ldr r1, [r7, #0]
|
|
80084b6: 6878 ldr r0, [r7, #4]
|
|
80084b8: 4798 blx r3
|
|
break;
|
|
80084ba: e13d b.n 8008738 <USBD_StdEPReq+0x2bc>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
/* Check if it is a class request */
|
|
if ((req->bmRequest & 0x60U) == 0x20U)
|
|
80084bc: 683b ldr r3, [r7, #0]
|
|
80084be: 781b ldrb r3, [r3, #0]
|
|
80084c0: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
80084c4: 2b20 cmp r3, #32
|
|
80084c6: d10a bne.n 80084de <USBD_StdEPReq+0x62>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
|
|
80084c8: 687b ldr r3, [r7, #4]
|
|
80084ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084ce: 689b ldr r3, [r3, #8]
|
|
80084d0: 6839 ldr r1, [r7, #0]
|
|
80084d2: 6878 ldr r0, [r7, #4]
|
|
80084d4: 4798 blx r3
|
|
80084d6: 4603 mov r3, r0
|
|
80084d8: 73fb strb r3, [r7, #15]
|
|
|
|
return ret;
|
|
80084da: 7bfb ldrb r3, [r7, #15]
|
|
80084dc: e12d b.n 800873a <USBD_StdEPReq+0x2be>
|
|
}
|
|
|
|
switch (req->bRequest)
|
|
80084de: 683b ldr r3, [r7, #0]
|
|
80084e0: 785b ldrb r3, [r3, #1]
|
|
80084e2: 2b03 cmp r3, #3
|
|
80084e4: d007 beq.n 80084f6 <USBD_StdEPReq+0x7a>
|
|
80084e6: 2b03 cmp r3, #3
|
|
80084e8: f300 811b bgt.w 8008722 <USBD_StdEPReq+0x2a6>
|
|
80084ec: 2b00 cmp r3, #0
|
|
80084ee: d072 beq.n 80085d6 <USBD_StdEPReq+0x15a>
|
|
80084f0: 2b01 cmp r3, #1
|
|
80084f2: d03a beq.n 800856a <USBD_StdEPReq+0xee>
|
|
80084f4: e115 b.n 8008722 <USBD_StdEPReq+0x2a6>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
80084f6: 687b ldr r3, [r7, #4]
|
|
80084f8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80084fc: 2b02 cmp r3, #2
|
|
80084fe: d002 beq.n 8008506 <USBD_StdEPReq+0x8a>
|
|
8008500: 2b03 cmp r3, #3
|
|
8008502: d015 beq.n 8008530 <USBD_StdEPReq+0xb4>
|
|
8008504: e02b b.n 800855e <USBD_StdEPReq+0xe2>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8008506: 7bbb ldrb r3, [r7, #14]
|
|
8008508: 2b00 cmp r3, #0
|
|
800850a: d00c beq.n 8008526 <USBD_StdEPReq+0xaa>
|
|
800850c: 7bbb ldrb r3, [r7, #14]
|
|
800850e: 2b80 cmp r3, #128 @ 0x80
|
|
8008510: d009 beq.n 8008526 <USBD_StdEPReq+0xaa>
|
|
{
|
|
USBD_LL_StallEP(pdev, ep_addr);
|
|
8008512: 7bbb ldrb r3, [r7, #14]
|
|
8008514: 4619 mov r1, r3
|
|
8008516: 6878 ldr r0, [r7, #4]
|
|
8008518: f001 f8fe bl 8009718 <USBD_LL_StallEP>
|
|
USBD_LL_StallEP(pdev, 0x80U);
|
|
800851c: 2180 movs r1, #128 @ 0x80
|
|
800851e: 6878 ldr r0, [r7, #4]
|
|
8008520: f001 f8fa bl 8009718 <USBD_LL_StallEP>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008524: e020 b.n 8008568 <USBD_StdEPReq+0xec>
|
|
USBD_CtlError(pdev, req);
|
|
8008526: 6839 ldr r1, [r7, #0]
|
|
8008528: 6878 ldr r0, [r7, #4]
|
|
800852a: f000 fc1b bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
800852e: e01b b.n 8008568 <USBD_StdEPReq+0xec>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
8008530: 683b ldr r3, [r7, #0]
|
|
8008532: 885b ldrh r3, [r3, #2]
|
|
8008534: 2b00 cmp r3, #0
|
|
8008536: d10e bne.n 8008556 <USBD_StdEPReq+0xda>
|
|
{
|
|
if ((ep_addr != 0x00U) &&
|
|
8008538: 7bbb ldrb r3, [r7, #14]
|
|
800853a: 2b00 cmp r3, #0
|
|
800853c: d00b beq.n 8008556 <USBD_StdEPReq+0xda>
|
|
800853e: 7bbb ldrb r3, [r7, #14]
|
|
8008540: 2b80 cmp r3, #128 @ 0x80
|
|
8008542: d008 beq.n 8008556 <USBD_StdEPReq+0xda>
|
|
(ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
8008544: 683b ldr r3, [r7, #0]
|
|
8008546: 88db ldrh r3, [r3, #6]
|
|
8008548: 2b00 cmp r3, #0
|
|
800854a: d104 bne.n 8008556 <USBD_StdEPReq+0xda>
|
|
{
|
|
USBD_LL_StallEP(pdev, ep_addr);
|
|
800854c: 7bbb ldrb r3, [r7, #14]
|
|
800854e: 4619 mov r1, r3
|
|
8008550: 6878 ldr r0, [r7, #4]
|
|
8008552: f001 f8e1 bl 8009718 <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
USBD_CtlSendStatus(pdev);
|
|
8008556: 6878 ldr r0, [r7, #4]
|
|
8008558: f000 fccc bl 8008ef4 <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
800855c: e004 b.n 8008568 <USBD_StdEPReq+0xec>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800855e: 6839 ldr r1, [r7, #0]
|
|
8008560: 6878 ldr r0, [r7, #4]
|
|
8008562: f000 fbff bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008566: bf00 nop
|
|
}
|
|
break;
|
|
8008568: e0e0 b.n 800872c <USBD_StdEPReq+0x2b0>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
800856a: 687b ldr r3, [r7, #4]
|
|
800856c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008570: 2b02 cmp r3, #2
|
|
8008572: d002 beq.n 800857a <USBD_StdEPReq+0xfe>
|
|
8008574: 2b03 cmp r3, #3
|
|
8008576: d015 beq.n 80085a4 <USBD_StdEPReq+0x128>
|
|
8008578: e026 b.n 80085c8 <USBD_StdEPReq+0x14c>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
800857a: 7bbb ldrb r3, [r7, #14]
|
|
800857c: 2b00 cmp r3, #0
|
|
800857e: d00c beq.n 800859a <USBD_StdEPReq+0x11e>
|
|
8008580: 7bbb ldrb r3, [r7, #14]
|
|
8008582: 2b80 cmp r3, #128 @ 0x80
|
|
8008584: d009 beq.n 800859a <USBD_StdEPReq+0x11e>
|
|
{
|
|
USBD_LL_StallEP(pdev, ep_addr);
|
|
8008586: 7bbb ldrb r3, [r7, #14]
|
|
8008588: 4619 mov r1, r3
|
|
800858a: 6878 ldr r0, [r7, #4]
|
|
800858c: f001 f8c4 bl 8009718 <USBD_LL_StallEP>
|
|
USBD_LL_StallEP(pdev, 0x80U);
|
|
8008590: 2180 movs r1, #128 @ 0x80
|
|
8008592: 6878 ldr r0, [r7, #4]
|
|
8008594: f001 f8c0 bl 8009718 <USBD_LL_StallEP>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008598: e01c b.n 80085d4 <USBD_StdEPReq+0x158>
|
|
USBD_CtlError(pdev, req);
|
|
800859a: 6839 ldr r1, [r7, #0]
|
|
800859c: 6878 ldr r0, [r7, #4]
|
|
800859e: f000 fbe1 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
80085a2: e017 b.n 80085d4 <USBD_StdEPReq+0x158>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80085a4: 683b ldr r3, [r7, #0]
|
|
80085a6: 885b ldrh r3, [r3, #2]
|
|
80085a8: 2b00 cmp r3, #0
|
|
80085aa: d112 bne.n 80085d2 <USBD_StdEPReq+0x156>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
80085ac: 7bbb ldrb r3, [r7, #14]
|
|
80085ae: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80085b2: 2b00 cmp r3, #0
|
|
80085b4: d004 beq.n 80085c0 <USBD_StdEPReq+0x144>
|
|
{
|
|
USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
80085b6: 7bbb ldrb r3, [r7, #14]
|
|
80085b8: 4619 mov r1, r3
|
|
80085ba: 6878 ldr r0, [r7, #4]
|
|
80085bc: f001 f8cb bl 8009756 <USBD_LL_ClearStallEP>
|
|
}
|
|
USBD_CtlSendStatus(pdev);
|
|
80085c0: 6878 ldr r0, [r7, #4]
|
|
80085c2: f000 fc97 bl 8008ef4 <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
80085c6: e004 b.n 80085d2 <USBD_StdEPReq+0x156>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80085c8: 6839 ldr r1, [r7, #0]
|
|
80085ca: 6878 ldr r0, [r7, #4]
|
|
80085cc: f000 fbca bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
80085d0: e000 b.n 80085d4 <USBD_StdEPReq+0x158>
|
|
break;
|
|
80085d2: bf00 nop
|
|
}
|
|
break;
|
|
80085d4: e0aa b.n 800872c <USBD_StdEPReq+0x2b0>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
80085d6: 687b ldr r3, [r7, #4]
|
|
80085d8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80085dc: 2b02 cmp r3, #2
|
|
80085de: d002 beq.n 80085e6 <USBD_StdEPReq+0x16a>
|
|
80085e0: 2b03 cmp r3, #3
|
|
80085e2: d032 beq.n 800864a <USBD_StdEPReq+0x1ce>
|
|
80085e4: e097 b.n 8008716 <USBD_StdEPReq+0x29a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
80085e6: 7bbb ldrb r3, [r7, #14]
|
|
80085e8: 2b00 cmp r3, #0
|
|
80085ea: d007 beq.n 80085fc <USBD_StdEPReq+0x180>
|
|
80085ec: 7bbb ldrb r3, [r7, #14]
|
|
80085ee: 2b80 cmp r3, #128 @ 0x80
|
|
80085f0: d004 beq.n 80085fc <USBD_StdEPReq+0x180>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80085f2: 6839 ldr r1, [r7, #0]
|
|
80085f4: 6878 ldr r0, [r7, #4]
|
|
80085f6: f000 fbb5 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
80085fa: e091 b.n 8008720 <USBD_StdEPReq+0x2a4>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80085fc: f997 300e ldrsb.w r3, [r7, #14]
|
|
8008600: 2b00 cmp r3, #0
|
|
8008602: da0b bge.n 800861c <USBD_StdEPReq+0x1a0>
|
|
8008604: 7bbb ldrb r3, [r7, #14]
|
|
8008606: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800860a: 4613 mov r3, r2
|
|
800860c: 009b lsls r3, r3, #2
|
|
800860e: 4413 add r3, r2
|
|
8008610: 009b lsls r3, r3, #2
|
|
8008612: 3310 adds r3, #16
|
|
8008614: 687a ldr r2, [r7, #4]
|
|
8008616: 4413 add r3, r2
|
|
8008618: 3304 adds r3, #4
|
|
800861a: e00b b.n 8008634 <USBD_StdEPReq+0x1b8>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
800861c: 7bbb ldrb r3, [r7, #14]
|
|
800861e: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8008622: 4613 mov r3, r2
|
|
8008624: 009b lsls r3, r3, #2
|
|
8008626: 4413 add r3, r2
|
|
8008628: 009b lsls r3, r3, #2
|
|
800862a: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
800862e: 687a ldr r2, [r7, #4]
|
|
8008630: 4413 add r3, r2
|
|
8008632: 3304 adds r3, #4
|
|
8008634: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
8008636: 68bb ldr r3, [r7, #8]
|
|
8008638: 2200 movs r2, #0
|
|
800863a: 601a str r2, [r3, #0]
|
|
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
|
|
800863c: 68bb ldr r3, [r7, #8]
|
|
800863e: 2202 movs r2, #2
|
|
8008640: 4619 mov r1, r3
|
|
8008642: 6878 ldr r0, [r7, #4]
|
|
8008644: f000 fbf8 bl 8008e38 <USBD_CtlSendData>
|
|
break;
|
|
8008648: e06a b.n 8008720 <USBD_StdEPReq+0x2a4>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
800864a: f997 300e ldrsb.w r3, [r7, #14]
|
|
800864e: 2b00 cmp r3, #0
|
|
8008650: da11 bge.n 8008676 <USBD_StdEPReq+0x1fa>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
8008652: 7bbb ldrb r3, [r7, #14]
|
|
8008654: f003 020f and.w r2, r3, #15
|
|
8008658: 6879 ldr r1, [r7, #4]
|
|
800865a: 4613 mov r3, r2
|
|
800865c: 009b lsls r3, r3, #2
|
|
800865e: 4413 add r3, r2
|
|
8008660: 009b lsls r3, r3, #2
|
|
8008662: 440b add r3, r1
|
|
8008664: 3318 adds r3, #24
|
|
8008666: 681b ldr r3, [r3, #0]
|
|
8008668: 2b00 cmp r3, #0
|
|
800866a: d117 bne.n 800869c <USBD_StdEPReq+0x220>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800866c: 6839 ldr r1, [r7, #0]
|
|
800866e: 6878 ldr r0, [r7, #4]
|
|
8008670: f000 fb78 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008674: e054 b.n 8008720 <USBD_StdEPReq+0x2a4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
8008676: 7bbb ldrb r3, [r7, #14]
|
|
8008678: f003 020f and.w r2, r3, #15
|
|
800867c: 6879 ldr r1, [r7, #4]
|
|
800867e: 4613 mov r3, r2
|
|
8008680: 009b lsls r3, r3, #2
|
|
8008682: 4413 add r3, r2
|
|
8008684: 009b lsls r3, r3, #2
|
|
8008686: 440b add r3, r1
|
|
8008688: f503 73ac add.w r3, r3, #344 @ 0x158
|
|
800868c: 681b ldr r3, [r3, #0]
|
|
800868e: 2b00 cmp r3, #0
|
|
8008690: d104 bne.n 800869c <USBD_StdEPReq+0x220>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008692: 6839 ldr r1, [r7, #0]
|
|
8008694: 6878 ldr r0, [r7, #4]
|
|
8008696: f000 fb65 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
800869a: e041 b.n 8008720 <USBD_StdEPReq+0x2a4>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
800869c: f997 300e ldrsb.w r3, [r7, #14]
|
|
80086a0: 2b00 cmp r3, #0
|
|
80086a2: da0b bge.n 80086bc <USBD_StdEPReq+0x240>
|
|
80086a4: 7bbb ldrb r3, [r7, #14]
|
|
80086a6: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80086aa: 4613 mov r3, r2
|
|
80086ac: 009b lsls r3, r3, #2
|
|
80086ae: 4413 add r3, r2
|
|
80086b0: 009b lsls r3, r3, #2
|
|
80086b2: 3310 adds r3, #16
|
|
80086b4: 687a ldr r2, [r7, #4]
|
|
80086b6: 4413 add r3, r2
|
|
80086b8: 3304 adds r3, #4
|
|
80086ba: e00b b.n 80086d4 <USBD_StdEPReq+0x258>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
80086bc: 7bbb ldrb r3, [r7, #14]
|
|
80086be: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80086c2: 4613 mov r3, r2
|
|
80086c4: 009b lsls r3, r3, #2
|
|
80086c6: 4413 add r3, r2
|
|
80086c8: 009b lsls r3, r3, #2
|
|
80086ca: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80086ce: 687a ldr r2, [r7, #4]
|
|
80086d0: 4413 add r3, r2
|
|
80086d2: 3304 adds r3, #4
|
|
80086d4: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
80086d6: 7bbb ldrb r3, [r7, #14]
|
|
80086d8: 2b00 cmp r3, #0
|
|
80086da: d002 beq.n 80086e2 <USBD_StdEPReq+0x266>
|
|
80086dc: 7bbb ldrb r3, [r7, #14]
|
|
80086de: 2b80 cmp r3, #128 @ 0x80
|
|
80086e0: d103 bne.n 80086ea <USBD_StdEPReq+0x26e>
|
|
{
|
|
pep->status = 0x0000U;
|
|
80086e2: 68bb ldr r3, [r7, #8]
|
|
80086e4: 2200 movs r2, #0
|
|
80086e6: 601a str r2, [r3, #0]
|
|
80086e8: e00e b.n 8008708 <USBD_StdEPReq+0x28c>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr))
|
|
80086ea: 7bbb ldrb r3, [r7, #14]
|
|
80086ec: 4619 mov r1, r3
|
|
80086ee: 6878 ldr r0, [r7, #4]
|
|
80086f0: f001 f850 bl 8009794 <USBD_LL_IsStallEP>
|
|
80086f4: 4603 mov r3, r0
|
|
80086f6: 2b00 cmp r3, #0
|
|
80086f8: d003 beq.n 8008702 <USBD_StdEPReq+0x286>
|
|
{
|
|
pep->status = 0x0001U;
|
|
80086fa: 68bb ldr r3, [r7, #8]
|
|
80086fc: 2201 movs r2, #1
|
|
80086fe: 601a str r2, [r3, #0]
|
|
8008700: e002 b.n 8008708 <USBD_StdEPReq+0x28c>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
8008702: 68bb ldr r3, [r7, #8]
|
|
8008704: 2200 movs r2, #0
|
|
8008706: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
|
|
8008708: 68bb ldr r3, [r7, #8]
|
|
800870a: 2202 movs r2, #2
|
|
800870c: 4619 mov r1, r3
|
|
800870e: 6878 ldr r0, [r7, #4]
|
|
8008710: f000 fb92 bl 8008e38 <USBD_CtlSendData>
|
|
break;
|
|
8008714: e004 b.n 8008720 <USBD_StdEPReq+0x2a4>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008716: 6839 ldr r1, [r7, #0]
|
|
8008718: 6878 ldr r0, [r7, #4]
|
|
800871a: f000 fb23 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
800871e: bf00 nop
|
|
}
|
|
break;
|
|
8008720: e004 b.n 800872c <USBD_StdEPReq+0x2b0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008722: 6839 ldr r1, [r7, #0]
|
|
8008724: 6878 ldr r0, [r7, #4]
|
|
8008726: f000 fb1d bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
800872a: bf00 nop
|
|
}
|
|
break;
|
|
800872c: e004 b.n 8008738 <USBD_StdEPReq+0x2bc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800872e: 6839 ldr r1, [r7, #0]
|
|
8008730: 6878 ldr r0, [r7, #4]
|
|
8008732: f000 fb17 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008736: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008738: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800873a: 4618 mov r0, r3
|
|
800873c: 3710 adds r7, #16
|
|
800873e: 46bd mov sp, r7
|
|
8008740: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008744 <USBD_GetDescriptor>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
8008744: b580 push {r7, lr}
|
|
8008746: b084 sub sp, #16
|
|
8008748: af00 add r7, sp, #0
|
|
800874a: 6078 str r0, [r7, #4]
|
|
800874c: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
800874e: 2300 movs r3, #0
|
|
8008750: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
8008752: 2300 movs r3, #0
|
|
8008754: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
8008756: 2300 movs r3, #0
|
|
8008758: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
800875a: 683b ldr r3, [r7, #0]
|
|
800875c: 885b ldrh r3, [r3, #2]
|
|
800875e: 0a1b lsrs r3, r3, #8
|
|
8008760: b29b uxth r3, r3
|
|
8008762: 3b01 subs r3, #1
|
|
8008764: 2b06 cmp r3, #6
|
|
8008766: f200 8128 bhi.w 80089ba <USBD_GetDescriptor+0x276>
|
|
800876a: a201 add r2, pc, #4 @ (adr r2, 8008770 <USBD_GetDescriptor+0x2c>)
|
|
800876c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008770: 0800878d .word 0x0800878d
|
|
8008774: 080087a5 .word 0x080087a5
|
|
8008778: 080087e5 .word 0x080087e5
|
|
800877c: 080089bb .word 0x080089bb
|
|
8008780: 080089bb .word 0x080089bb
|
|
8008784: 0800895b .word 0x0800895b
|
|
8008788: 08008987 .word 0x08008987
|
|
err++;
|
|
}
|
|
break;
|
|
#endif
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
800878c: 687b ldr r3, [r7, #4]
|
|
800878e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
8008792: 681b ldr r3, [r3, #0]
|
|
8008794: 687a ldr r2, [r7, #4]
|
|
8008796: 7c12 ldrb r2, [r2, #16]
|
|
8008798: f107 0108 add.w r1, r7, #8
|
|
800879c: 4610 mov r0, r2
|
|
800879e: 4798 blx r3
|
|
80087a0: 60f8 str r0, [r7, #12]
|
|
break;
|
|
80087a2: e112 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80087a4: 687b ldr r3, [r7, #4]
|
|
80087a6: 7c1b ldrb r3, [r3, #16]
|
|
80087a8: 2b00 cmp r3, #0
|
|
80087aa: d10d bne.n 80087c8 <USBD_GetDescriptor+0x84>
|
|
{
|
|
pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
|
|
80087ac: 687b ldr r3, [r7, #4]
|
|
80087ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80087b2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80087b4: f107 0208 add.w r2, r7, #8
|
|
80087b8: 4610 mov r0, r2
|
|
80087ba: 4798 blx r3
|
|
80087bc: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
80087be: 68fb ldr r3, [r7, #12]
|
|
80087c0: 3301 adds r3, #1
|
|
80087c2: 2202 movs r2, #2
|
|
80087c4: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
80087c6: e100 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
|
|
80087c8: 687b ldr r3, [r7, #4]
|
|
80087ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80087ce: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80087d0: f107 0208 add.w r2, r7, #8
|
|
80087d4: 4610 mov r0, r2
|
|
80087d6: 4798 blx r3
|
|
80087d8: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
80087da: 68fb ldr r3, [r7, #12]
|
|
80087dc: 3301 adds r3, #1
|
|
80087de: 2202 movs r2, #2
|
|
80087e0: 701a strb r2, [r3, #0]
|
|
break;
|
|
80087e2: e0f2 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
80087e4: 683b ldr r3, [r7, #0]
|
|
80087e6: 885b ldrh r3, [r3, #2]
|
|
80087e8: b2db uxtb r3, r3
|
|
80087ea: 2b05 cmp r3, #5
|
|
80087ec: f200 80ac bhi.w 8008948 <USBD_GetDescriptor+0x204>
|
|
80087f0: a201 add r2, pc, #4 @ (adr r2, 80087f8 <USBD_GetDescriptor+0xb4>)
|
|
80087f2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80087f6: bf00 nop
|
|
80087f8: 08008811 .word 0x08008811
|
|
80087fc: 08008845 .word 0x08008845
|
|
8008800: 08008879 .word 0x08008879
|
|
8008804: 080088ad .word 0x080088ad
|
|
8008808: 080088e1 .word 0x080088e1
|
|
800880c: 08008915 .word 0x08008915
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
8008810: 687b ldr r3, [r7, #4]
|
|
8008812: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
8008816: 685b ldr r3, [r3, #4]
|
|
8008818: 2b00 cmp r3, #0
|
|
800881a: d00b beq.n 8008834 <USBD_GetDescriptor+0xf0>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
800881c: 687b ldr r3, [r7, #4]
|
|
800881e: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
8008822: 685b ldr r3, [r3, #4]
|
|
8008824: 687a ldr r2, [r7, #4]
|
|
8008826: 7c12 ldrb r2, [r2, #16]
|
|
8008828: f107 0108 add.w r1, r7, #8
|
|
800882c: 4610 mov r0, r2
|
|
800882e: 4798 blx r3
|
|
8008830: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008832: e091 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
8008834: 6839 ldr r1, [r7, #0]
|
|
8008836: 6878 ldr r0, [r7, #4]
|
|
8008838: f000 fa94 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
800883c: 7afb ldrb r3, [r7, #11]
|
|
800883e: 3301 adds r3, #1
|
|
8008840: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008842: e089 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
8008844: 687b ldr r3, [r7, #4]
|
|
8008846: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
800884a: 689b ldr r3, [r3, #8]
|
|
800884c: 2b00 cmp r3, #0
|
|
800884e: d00b beq.n 8008868 <USBD_GetDescriptor+0x124>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
8008850: 687b ldr r3, [r7, #4]
|
|
8008852: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
8008856: 689b ldr r3, [r3, #8]
|
|
8008858: 687a ldr r2, [r7, #4]
|
|
800885a: 7c12 ldrb r2, [r2, #16]
|
|
800885c: f107 0108 add.w r1, r7, #8
|
|
8008860: 4610 mov r0, r2
|
|
8008862: 4798 blx r3
|
|
8008864: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008866: e077 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
8008868: 6839 ldr r1, [r7, #0]
|
|
800886a: 6878 ldr r0, [r7, #4]
|
|
800886c: f000 fa7a bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
8008870: 7afb ldrb r3, [r7, #11]
|
|
8008872: 3301 adds r3, #1
|
|
8008874: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008876: e06f b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
8008878: 687b ldr r3, [r7, #4]
|
|
800887a: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
800887e: 68db ldr r3, [r3, #12]
|
|
8008880: 2b00 cmp r3, #0
|
|
8008882: d00b beq.n 800889c <USBD_GetDescriptor+0x158>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
8008884: 687b ldr r3, [r7, #4]
|
|
8008886: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
800888a: 68db ldr r3, [r3, #12]
|
|
800888c: 687a ldr r2, [r7, #4]
|
|
800888e: 7c12 ldrb r2, [r2, #16]
|
|
8008890: f107 0108 add.w r1, r7, #8
|
|
8008894: 4610 mov r0, r2
|
|
8008896: 4798 blx r3
|
|
8008898: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800889a: e05d b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
800889c: 6839 ldr r1, [r7, #0]
|
|
800889e: 6878 ldr r0, [r7, #4]
|
|
80088a0: f000 fa60 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
80088a4: 7afb ldrb r3, [r7, #11]
|
|
80088a6: 3301 adds r3, #1
|
|
80088a8: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80088aa: e055 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
80088ac: 687b ldr r3, [r7, #4]
|
|
80088ae: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
80088b2: 691b ldr r3, [r3, #16]
|
|
80088b4: 2b00 cmp r3, #0
|
|
80088b6: d00b beq.n 80088d0 <USBD_GetDescriptor+0x18c>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
80088b8: 687b ldr r3, [r7, #4]
|
|
80088ba: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
80088be: 691b ldr r3, [r3, #16]
|
|
80088c0: 687a ldr r2, [r7, #4]
|
|
80088c2: 7c12 ldrb r2, [r2, #16]
|
|
80088c4: f107 0108 add.w r1, r7, #8
|
|
80088c8: 4610 mov r0, r2
|
|
80088ca: 4798 blx r3
|
|
80088cc: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80088ce: e043 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
80088d0: 6839 ldr r1, [r7, #0]
|
|
80088d2: 6878 ldr r0, [r7, #4]
|
|
80088d4: f000 fa46 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
80088d8: 7afb ldrb r3, [r7, #11]
|
|
80088da: 3301 adds r3, #1
|
|
80088dc: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80088de: e03b b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
80088e0: 687b ldr r3, [r7, #4]
|
|
80088e2: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
80088e6: 695b ldr r3, [r3, #20]
|
|
80088e8: 2b00 cmp r3, #0
|
|
80088ea: d00b beq.n 8008904 <USBD_GetDescriptor+0x1c0>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
80088ec: 687b ldr r3, [r7, #4]
|
|
80088ee: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
80088f2: 695b ldr r3, [r3, #20]
|
|
80088f4: 687a ldr r2, [r7, #4]
|
|
80088f6: 7c12 ldrb r2, [r2, #16]
|
|
80088f8: f107 0108 add.w r1, r7, #8
|
|
80088fc: 4610 mov r0, r2
|
|
80088fe: 4798 blx r3
|
|
8008900: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008902: e029 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
8008904: 6839 ldr r1, [r7, #0]
|
|
8008906: 6878 ldr r0, [r7, #4]
|
|
8008908: f000 fa2c bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
800890c: 7afb ldrb r3, [r7, #11]
|
|
800890e: 3301 adds r3, #1
|
|
8008910: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008912: e021 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
8008914: 687b ldr r3, [r7, #4]
|
|
8008916: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
800891a: 699b ldr r3, [r3, #24]
|
|
800891c: 2b00 cmp r3, #0
|
|
800891e: d00b beq.n 8008938 <USBD_GetDescriptor+0x1f4>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
8008920: 687b ldr r3, [r7, #4]
|
|
8008922: f8d3 32b0 ldr.w r3, [r3, #688] @ 0x2b0
|
|
8008926: 699b ldr r3, [r3, #24]
|
|
8008928: 687a ldr r2, [r7, #4]
|
|
800892a: 7c12 ldrb r2, [r2, #16]
|
|
800892c: f107 0108 add.w r1, r7, #8
|
|
8008930: 4610 mov r0, r2
|
|
8008932: 4798 blx r3
|
|
8008934: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008936: e00f b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
8008938: 6839 ldr r1, [r7, #0]
|
|
800893a: 6878 ldr r0, [r7, #4]
|
|
800893c: f000 fa12 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
8008940: 7afb ldrb r3, [r7, #11]
|
|
8008942: 3301 adds r3, #1
|
|
8008944: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008946: e007 b.n 8008958 <USBD_GetDescriptor+0x214>
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
#else
|
|
USBD_CtlError(pdev, req);
|
|
8008948: 6839 ldr r1, [r7, #0]
|
|
800894a: 6878 ldr r0, [r7, #4]
|
|
800894c: f000 fa0a bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
8008950: 7afb ldrb r3, [r7, #11]
|
|
8008952: 3301 adds r3, #1
|
|
8008954: 72fb strb r3, [r7, #11]
|
|
#endif
|
|
}
|
|
break;
|
|
8008956: e038 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
8008958: e037 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
800895a: 687b ldr r3, [r7, #4]
|
|
800895c: 7c1b ldrb r3, [r3, #16]
|
|
800895e: 2b00 cmp r3, #0
|
|
8008960: d109 bne.n 8008976 <USBD_GetDescriptor+0x232>
|
|
{
|
|
pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
|
|
8008962: 687b ldr r3, [r7, #4]
|
|
8008964: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008968: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800896a: f107 0208 add.w r2, r7, #8
|
|
800896e: 4610 mov r0, r2
|
|
8008970: 4798 blx r3
|
|
8008972: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008974: e029 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
USBD_CtlError(pdev, req);
|
|
8008976: 6839 ldr r1, [r7, #0]
|
|
8008978: 6878 ldr r0, [r7, #4]
|
|
800897a: f000 f9f3 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
800897e: 7afb ldrb r3, [r7, #11]
|
|
8008980: 3301 adds r3, #1
|
|
8008982: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008984: e021 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8008986: 687b ldr r3, [r7, #4]
|
|
8008988: 7c1b ldrb r3, [r3, #16]
|
|
800898a: 2b00 cmp r3, #0
|
|
800898c: d10d bne.n 80089aa <USBD_GetDescriptor+0x266>
|
|
{
|
|
pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
|
|
800898e: 687b ldr r3, [r7, #4]
|
|
8008990: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008994: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008996: f107 0208 add.w r2, r7, #8
|
|
800899a: 4610 mov r0, r2
|
|
800899c: 4798 blx r3
|
|
800899e: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
80089a0: 68fb ldr r3, [r7, #12]
|
|
80089a2: 3301 adds r3, #1
|
|
80089a4: 2207 movs r2, #7
|
|
80089a6: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80089a8: e00f b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
USBD_CtlError(pdev, req);
|
|
80089aa: 6839 ldr r1, [r7, #0]
|
|
80089ac: 6878 ldr r0, [r7, #4]
|
|
80089ae: f000 f9d9 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
80089b2: 7afb ldrb r3, [r7, #11]
|
|
80089b4: 3301 adds r3, #1
|
|
80089b6: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80089b8: e007 b.n 80089ca <USBD_GetDescriptor+0x286>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80089ba: 6839 ldr r1, [r7, #0]
|
|
80089bc: 6878 ldr r0, [r7, #4]
|
|
80089be: f000 f9d1 bl 8008d64 <USBD_CtlError>
|
|
err++;
|
|
80089c2: 7afb ldrb r3, [r7, #11]
|
|
80089c4: 3301 adds r3, #1
|
|
80089c6: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80089c8: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
80089ca: 7afb ldrb r3, [r7, #11]
|
|
80089cc: 2b00 cmp r3, #0
|
|
80089ce: d11c bne.n 8008a0a <USBD_GetDescriptor+0x2c6>
|
|
{
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
if ((len != 0U) && (req->wLength != 0U))
|
|
80089d0: 893b ldrh r3, [r7, #8]
|
|
80089d2: 2b00 cmp r3, #0
|
|
80089d4: d011 beq.n 80089fa <USBD_GetDescriptor+0x2b6>
|
|
80089d6: 683b ldr r3, [r7, #0]
|
|
80089d8: 88db ldrh r3, [r3, #6]
|
|
80089da: 2b00 cmp r3, #0
|
|
80089dc: d00d beq.n 80089fa <USBD_GetDescriptor+0x2b6>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
80089de: 683b ldr r3, [r7, #0]
|
|
80089e0: 88da ldrh r2, [r3, #6]
|
|
80089e2: 893b ldrh r3, [r7, #8]
|
|
80089e4: 4293 cmp r3, r2
|
|
80089e6: bf28 it cs
|
|
80089e8: 4613 movcs r3, r2
|
|
80089ea: b29b uxth r3, r3
|
|
80089ec: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
80089ee: 893b ldrh r3, [r7, #8]
|
|
80089f0: 461a mov r2, r3
|
|
80089f2: 68f9 ldr r1, [r7, #12]
|
|
80089f4: 6878 ldr r0, [r7, #4]
|
|
80089f6: f000 fa1f bl 8008e38 <USBD_CtlSendData>
|
|
}
|
|
|
|
if (req->wLength == 0U)
|
|
80089fa: 683b ldr r3, [r7, #0]
|
|
80089fc: 88db ldrh r3, [r3, #6]
|
|
80089fe: 2b00 cmp r3, #0
|
|
8008a00: d104 bne.n 8008a0c <USBD_GetDescriptor+0x2c8>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008a02: 6878 ldr r0, [r7, #4]
|
|
8008a04: f000 fa76 bl 8008ef4 <USBD_CtlSendStatus>
|
|
8008a08: e000 b.n 8008a0c <USBD_GetDescriptor+0x2c8>
|
|
return;
|
|
8008a0a: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
8008a0c: 3710 adds r7, #16
|
|
8008a0e: 46bd mov sp, r7
|
|
8008a10: bd80 pop {r7, pc}
|
|
8008a12: bf00 nop
|
|
|
|
08008a14 <USBD_SetAddress>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
8008a14: b580 push {r7, lr}
|
|
8008a16: b084 sub sp, #16
|
|
8008a18: af00 add r7, sp, #0
|
|
8008a1a: 6078 str r0, [r7, #4]
|
|
8008a1c: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
8008a1e: 683b ldr r3, [r7, #0]
|
|
8008a20: 889b ldrh r3, [r3, #4]
|
|
8008a22: 2b00 cmp r3, #0
|
|
8008a24: d130 bne.n 8008a88 <USBD_SetAddress+0x74>
|
|
8008a26: 683b ldr r3, [r7, #0]
|
|
8008a28: 88db ldrh r3, [r3, #6]
|
|
8008a2a: 2b00 cmp r3, #0
|
|
8008a2c: d12c bne.n 8008a88 <USBD_SetAddress+0x74>
|
|
8008a2e: 683b ldr r3, [r7, #0]
|
|
8008a30: 885b ldrh r3, [r3, #2]
|
|
8008a32: 2b7f cmp r3, #127 @ 0x7f
|
|
8008a34: d828 bhi.n 8008a88 <USBD_SetAddress+0x74>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
8008a36: 683b ldr r3, [r7, #0]
|
|
8008a38: 885b ldrh r3, [r3, #2]
|
|
8008a3a: b2db uxtb r3, r3
|
|
8008a3c: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8008a40: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008a42: 687b ldr r3, [r7, #4]
|
|
8008a44: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008a48: 2b03 cmp r3, #3
|
|
8008a4a: d104 bne.n 8008a56 <USBD_SetAddress+0x42>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008a4c: 6839 ldr r1, [r7, #0]
|
|
8008a4e: 6878 ldr r0, [r7, #4]
|
|
8008a50: f000 f988 bl 8008d64 <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008a54: e01d b.n 8008a92 <USBD_SetAddress+0x7e>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
8008a56: 687b ldr r3, [r7, #4]
|
|
8008a58: 7bfa ldrb r2, [r7, #15]
|
|
8008a5a: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8008a5e: 7bfb ldrb r3, [r7, #15]
|
|
8008a60: 4619 mov r1, r3
|
|
8008a62: 6878 ldr r0, [r7, #4]
|
|
8008a64: f000 fec1 bl 80097ea <USBD_LL_SetUSBAddress>
|
|
USBD_CtlSendStatus(pdev);
|
|
8008a68: 6878 ldr r0, [r7, #4]
|
|
8008a6a: f000 fa43 bl 8008ef4 <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
8008a6e: 7bfb ldrb r3, [r7, #15]
|
|
8008a70: 2b00 cmp r3, #0
|
|
8008a72: d004 beq.n 8008a7e <USBD_SetAddress+0x6a>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8008a74: 687b ldr r3, [r7, #4]
|
|
8008a76: 2202 movs r2, #2
|
|
8008a78: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008a7c: e009 b.n 8008a92 <USBD_SetAddress+0x7e>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8008a7e: 687b ldr r3, [r7, #4]
|
|
8008a80: 2201 movs r2, #1
|
|
8008a82: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008a86: e004 b.n 8008a92 <USBD_SetAddress+0x7e>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008a88: 6839 ldr r1, [r7, #0]
|
|
8008a8a: 6878 ldr r0, [r7, #4]
|
|
8008a8c: f000 f96a bl 8008d64 <USBD_CtlError>
|
|
}
|
|
}
|
|
8008a90: bf00 nop
|
|
8008a92: bf00 nop
|
|
8008a94: 3710 adds r7, #16
|
|
8008a96: 46bd mov sp, r7
|
|
8008a98: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008a9c <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008a9c: b580 push {r7, lr}
|
|
8008a9e: b082 sub sp, #8
|
|
8008aa0: af00 add r7, sp, #0
|
|
8008aa2: 6078 str r0, [r7, #4]
|
|
8008aa4: 6039 str r1, [r7, #0]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
8008aa6: 683b ldr r3, [r7, #0]
|
|
8008aa8: 885b ldrh r3, [r3, #2]
|
|
8008aaa: b2da uxtb r2, r3
|
|
8008aac: 4b41 ldr r3, [pc, #260] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008aae: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
8008ab0: 4b40 ldr r3, [pc, #256] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008ab2: 781b ldrb r3, [r3, #0]
|
|
8008ab4: 2b01 cmp r3, #1
|
|
8008ab6: d904 bls.n 8008ac2 <USBD_SetConfig+0x26>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008ab8: 6839 ldr r1, [r7, #0]
|
|
8008aba: 6878 ldr r0, [r7, #4]
|
|
8008abc: f000 f952 bl 8008d64 <USBD_CtlError>
|
|
8008ac0: e075 b.n 8008bae <USBD_SetConfig+0x112>
|
|
}
|
|
else
|
|
{
|
|
switch (pdev->dev_state)
|
|
8008ac2: 687b ldr r3, [r7, #4]
|
|
8008ac4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008ac8: 2b02 cmp r3, #2
|
|
8008aca: d002 beq.n 8008ad2 <USBD_SetConfig+0x36>
|
|
8008acc: 2b03 cmp r3, #3
|
|
8008ace: d023 beq.n 8008b18 <USBD_SetConfig+0x7c>
|
|
8008ad0: e062 b.n 8008b98 <USBD_SetConfig+0xfc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx)
|
|
8008ad2: 4b38 ldr r3, [pc, #224] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008ad4: 781b ldrb r3, [r3, #0]
|
|
8008ad6: 2b00 cmp r3, #0
|
|
8008ad8: d01a beq.n 8008b10 <USBD_SetConfig+0x74>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
8008ada: 4b36 ldr r3, [pc, #216] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008adc: 781b ldrb r3, [r3, #0]
|
|
8008ade: 461a mov r2, r3
|
|
8008ae0: 687b ldr r3, [r7, #4]
|
|
8008ae2: 605a str r2, [r3, #4]
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
8008ae4: 687b ldr r3, [r7, #4]
|
|
8008ae6: 2203 movs r2, #3
|
|
8008ae8: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
|
|
8008aec: 4b31 ldr r3, [pc, #196] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008aee: 781b ldrb r3, [r3, #0]
|
|
8008af0: 4619 mov r1, r3
|
|
8008af2: 6878 ldr r0, [r7, #4]
|
|
8008af4: f7ff f9e7 bl 8007ec6 <USBD_SetClassConfig>
|
|
8008af8: 4603 mov r3, r0
|
|
8008afa: 2b02 cmp r3, #2
|
|
8008afc: d104 bne.n 8008b08 <USBD_SetConfig+0x6c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008afe: 6839 ldr r1, [r7, #0]
|
|
8008b00: 6878 ldr r0, [r7, #4]
|
|
8008b02: f000 f92f bl 8008d64 <USBD_CtlError>
|
|
return;
|
|
8008b06: e052 b.n 8008bae <USBD_SetConfig+0x112>
|
|
}
|
|
USBD_CtlSendStatus(pdev);
|
|
8008b08: 6878 ldr r0, [r7, #4]
|
|
8008b0a: f000 f9f3 bl 8008ef4 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8008b0e: e04e b.n 8008bae <USBD_SetConfig+0x112>
|
|
USBD_CtlSendStatus(pdev);
|
|
8008b10: 6878 ldr r0, [r7, #4]
|
|
8008b12: f000 f9ef bl 8008ef4 <USBD_CtlSendStatus>
|
|
break;
|
|
8008b16: e04a b.n 8008bae <USBD_SetConfig+0x112>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
8008b18: 4b26 ldr r3, [pc, #152] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008b1a: 781b ldrb r3, [r3, #0]
|
|
8008b1c: 2b00 cmp r3, #0
|
|
8008b1e: d112 bne.n 8008b46 <USBD_SetConfig+0xaa>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8008b20: 687b ldr r3, [r7, #4]
|
|
8008b22: 2202 movs r2, #2
|
|
8008b24: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
8008b28: 4b22 ldr r3, [pc, #136] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008b2a: 781b ldrb r3, [r3, #0]
|
|
8008b2c: 461a mov r2, r3
|
|
8008b2e: 687b ldr r3, [r7, #4]
|
|
8008b30: 605a str r2, [r3, #4]
|
|
USBD_ClrClassConfig(pdev, cfgidx);
|
|
8008b32: 4b20 ldr r3, [pc, #128] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008b34: 781b ldrb r3, [r3, #0]
|
|
8008b36: 4619 mov r1, r3
|
|
8008b38: 6878 ldr r0, [r7, #4]
|
|
8008b3a: f7ff f9e3 bl 8007f04 <USBD_ClrClassConfig>
|
|
USBD_CtlSendStatus(pdev);
|
|
8008b3e: 6878 ldr r0, [r7, #4]
|
|
8008b40: f000 f9d8 bl 8008ef4 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8008b44: e033 b.n 8008bae <USBD_SetConfig+0x112>
|
|
else if (cfgidx != pdev->dev_config)
|
|
8008b46: 4b1b ldr r3, [pc, #108] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008b48: 781b ldrb r3, [r3, #0]
|
|
8008b4a: 461a mov r2, r3
|
|
8008b4c: 687b ldr r3, [r7, #4]
|
|
8008b4e: 685b ldr r3, [r3, #4]
|
|
8008b50: 429a cmp r2, r3
|
|
8008b52: d01d beq.n 8008b90 <USBD_SetConfig+0xf4>
|
|
USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8008b54: 687b ldr r3, [r7, #4]
|
|
8008b56: 685b ldr r3, [r3, #4]
|
|
8008b58: b2db uxtb r3, r3
|
|
8008b5a: 4619 mov r1, r3
|
|
8008b5c: 6878 ldr r0, [r7, #4]
|
|
8008b5e: f7ff f9d1 bl 8007f04 <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
8008b62: 4b14 ldr r3, [pc, #80] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008b64: 781b ldrb r3, [r3, #0]
|
|
8008b66: 461a mov r2, r3
|
|
8008b68: 687b ldr r3, [r7, #4]
|
|
8008b6a: 605a str r2, [r3, #4]
|
|
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
|
|
8008b6c: 4b11 ldr r3, [pc, #68] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008b6e: 781b ldrb r3, [r3, #0]
|
|
8008b70: 4619 mov r1, r3
|
|
8008b72: 6878 ldr r0, [r7, #4]
|
|
8008b74: f7ff f9a7 bl 8007ec6 <USBD_SetClassConfig>
|
|
8008b78: 4603 mov r3, r0
|
|
8008b7a: 2b02 cmp r3, #2
|
|
8008b7c: d104 bne.n 8008b88 <USBD_SetConfig+0xec>
|
|
USBD_CtlError(pdev, req);
|
|
8008b7e: 6839 ldr r1, [r7, #0]
|
|
8008b80: 6878 ldr r0, [r7, #4]
|
|
8008b82: f000 f8ef bl 8008d64 <USBD_CtlError>
|
|
return;
|
|
8008b86: e012 b.n 8008bae <USBD_SetConfig+0x112>
|
|
USBD_CtlSendStatus(pdev);
|
|
8008b88: 6878 ldr r0, [r7, #4]
|
|
8008b8a: f000 f9b3 bl 8008ef4 <USBD_CtlSendStatus>
|
|
break;
|
|
8008b8e: e00e b.n 8008bae <USBD_SetConfig+0x112>
|
|
USBD_CtlSendStatus(pdev);
|
|
8008b90: 6878 ldr r0, [r7, #4]
|
|
8008b92: f000 f9af bl 8008ef4 <USBD_CtlSendStatus>
|
|
break;
|
|
8008b96: e00a b.n 8008bae <USBD_SetConfig+0x112>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008b98: 6839 ldr r1, [r7, #0]
|
|
8008b9a: 6878 ldr r0, [r7, #4]
|
|
8008b9c: f000 f8e2 bl 8008d64 <USBD_CtlError>
|
|
USBD_ClrClassConfig(pdev, cfgidx);
|
|
8008ba0: 4b04 ldr r3, [pc, #16] @ (8008bb4 <USBD_SetConfig+0x118>)
|
|
8008ba2: 781b ldrb r3, [r3, #0]
|
|
8008ba4: 4619 mov r1, r3
|
|
8008ba6: 6878 ldr r0, [r7, #4]
|
|
8008ba8: f7ff f9ac bl 8007f04 <USBD_ClrClassConfig>
|
|
break;
|
|
8008bac: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
8008bae: 3708 adds r7, #8
|
|
8008bb0: 46bd mov sp, r7
|
|
8008bb2: bd80 pop {r7, pc}
|
|
8008bb4: 200003ac .word 0x200003ac
|
|
|
|
08008bb8 <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008bb8: b580 push {r7, lr}
|
|
8008bba: b082 sub sp, #8
|
|
8008bbc: af00 add r7, sp, #0
|
|
8008bbe: 6078 str r0, [r7, #4]
|
|
8008bc0: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
8008bc2: 683b ldr r3, [r7, #0]
|
|
8008bc4: 88db ldrh r3, [r3, #6]
|
|
8008bc6: 2b01 cmp r3, #1
|
|
8008bc8: d004 beq.n 8008bd4 <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008bca: 6839 ldr r1, [r7, #0]
|
|
8008bcc: 6878 ldr r0, [r7, #4]
|
|
8008bce: f000 f8c9 bl 8008d64 <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
8008bd2: e022 b.n 8008c1a <USBD_GetConfig+0x62>
|
|
switch (pdev->dev_state)
|
|
8008bd4: 687b ldr r3, [r7, #4]
|
|
8008bd6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008bda: 2b02 cmp r3, #2
|
|
8008bdc: dc02 bgt.n 8008be4 <USBD_GetConfig+0x2c>
|
|
8008bde: 2b00 cmp r3, #0
|
|
8008be0: dc03 bgt.n 8008bea <USBD_GetConfig+0x32>
|
|
8008be2: e015 b.n 8008c10 <USBD_GetConfig+0x58>
|
|
8008be4: 2b03 cmp r3, #3
|
|
8008be6: d00b beq.n 8008c00 <USBD_GetConfig+0x48>
|
|
8008be8: e012 b.n 8008c10 <USBD_GetConfig+0x58>
|
|
pdev->dev_default_config = 0U;
|
|
8008bea: 687b ldr r3, [r7, #4]
|
|
8008bec: 2200 movs r2, #0
|
|
8008bee: 609a str r2, [r3, #8]
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
|
|
8008bf0: 687b ldr r3, [r7, #4]
|
|
8008bf2: 3308 adds r3, #8
|
|
8008bf4: 2201 movs r2, #1
|
|
8008bf6: 4619 mov r1, r3
|
|
8008bf8: 6878 ldr r0, [r7, #4]
|
|
8008bfa: f000 f91d bl 8008e38 <USBD_CtlSendData>
|
|
break;
|
|
8008bfe: e00c b.n 8008c1a <USBD_GetConfig+0x62>
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
|
|
8008c00: 687b ldr r3, [r7, #4]
|
|
8008c02: 3304 adds r3, #4
|
|
8008c04: 2201 movs r2, #1
|
|
8008c06: 4619 mov r1, r3
|
|
8008c08: 6878 ldr r0, [r7, #4]
|
|
8008c0a: f000 f915 bl 8008e38 <USBD_CtlSendData>
|
|
break;
|
|
8008c0e: e004 b.n 8008c1a <USBD_GetConfig+0x62>
|
|
USBD_CtlError(pdev, req);
|
|
8008c10: 6839 ldr r1, [r7, #0]
|
|
8008c12: 6878 ldr r0, [r7, #4]
|
|
8008c14: f000 f8a6 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008c18: bf00 nop
|
|
}
|
|
8008c1a: bf00 nop
|
|
8008c1c: 3708 adds r7, #8
|
|
8008c1e: 46bd mov sp, r7
|
|
8008c20: bd80 pop {r7, pc}
|
|
|
|
08008c22 <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008c22: b580 push {r7, lr}
|
|
8008c24: b082 sub sp, #8
|
|
8008c26: af00 add r7, sp, #0
|
|
8008c28: 6078 str r0, [r7, #4]
|
|
8008c2a: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8008c2c: 687b ldr r3, [r7, #4]
|
|
8008c2e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008c32: 3b01 subs r3, #1
|
|
8008c34: 2b02 cmp r3, #2
|
|
8008c36: d81e bhi.n 8008c76 <USBD_GetStatus+0x54>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
8008c38: 683b ldr r3, [r7, #0]
|
|
8008c3a: 88db ldrh r3, [r3, #6]
|
|
8008c3c: 2b02 cmp r3, #2
|
|
8008c3e: d004 beq.n 8008c4a <USBD_GetStatus+0x28>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008c40: 6839 ldr r1, [r7, #0]
|
|
8008c42: 6878 ldr r0, [r7, #4]
|
|
8008c44: f000 f88e bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008c48: e01a b.n 8008c80 <USBD_GetStatus+0x5e>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
8008c4a: 687b ldr r3, [r7, #4]
|
|
8008c4c: 2201 movs r2, #1
|
|
8008c4e: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif
|
|
|
|
if (pdev->dev_remote_wakeup)
|
|
8008c50: 687b ldr r3, [r7, #4]
|
|
8008c52: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
8008c56: 2b00 cmp r3, #0
|
|
8008c58: d005 beq.n 8008c66 <USBD_GetStatus+0x44>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
8008c5a: 687b ldr r3, [r7, #4]
|
|
8008c5c: 68db ldr r3, [r3, #12]
|
|
8008c5e: f043 0202 orr.w r2, r3, #2
|
|
8008c62: 687b ldr r3, [r7, #4]
|
|
8008c64: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
|
|
8008c66: 687b ldr r3, [r7, #4]
|
|
8008c68: 330c adds r3, #12
|
|
8008c6a: 2202 movs r2, #2
|
|
8008c6c: 4619 mov r1, r3
|
|
8008c6e: 6878 ldr r0, [r7, #4]
|
|
8008c70: f000 f8e2 bl 8008e38 <USBD_CtlSendData>
|
|
break;
|
|
8008c74: e004 b.n 8008c80 <USBD_GetStatus+0x5e>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008c76: 6839 ldr r1, [r7, #0]
|
|
8008c78: 6878 ldr r0, [r7, #4]
|
|
8008c7a: f000 f873 bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008c7e: bf00 nop
|
|
}
|
|
}
|
|
8008c80: bf00 nop
|
|
8008c82: 3708 adds r7, #8
|
|
8008c84: 46bd mov sp, r7
|
|
8008c86: bd80 pop {r7, pc}
|
|
|
|
08008c88 <USBD_SetFeature>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
8008c88: b580 push {r7, lr}
|
|
8008c8a: b082 sub sp, #8
|
|
8008c8c: af00 add r7, sp, #0
|
|
8008c8e: 6078 str r0, [r7, #4]
|
|
8008c90: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8008c92: 683b ldr r3, [r7, #0]
|
|
8008c94: 885b ldrh r3, [r3, #2]
|
|
8008c96: 2b01 cmp r3, #1
|
|
8008c98: d106 bne.n 8008ca8 <USBD_SetFeature+0x20>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
8008c9a: 687b ldr r3, [r7, #4]
|
|
8008c9c: 2201 movs r2, #1
|
|
8008c9e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
USBD_CtlSendStatus(pdev);
|
|
8008ca2: 6878 ldr r0, [r7, #4]
|
|
8008ca4: f000 f926 bl 8008ef4 <USBD_CtlSendStatus>
|
|
}
|
|
}
|
|
8008ca8: bf00 nop
|
|
8008caa: 3708 adds r7, #8
|
|
8008cac: 46bd mov sp, r7
|
|
8008cae: bd80 pop {r7, pc}
|
|
|
|
08008cb0 <USBD_ClrFeature>:
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
8008cb0: b580 push {r7, lr}
|
|
8008cb2: b082 sub sp, #8
|
|
8008cb4: af00 add r7, sp, #0
|
|
8008cb6: 6078 str r0, [r7, #4]
|
|
8008cb8: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8008cba: 687b ldr r3, [r7, #4]
|
|
8008cbc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008cc0: 3b01 subs r3, #1
|
|
8008cc2: 2b02 cmp r3, #2
|
|
8008cc4: d80b bhi.n 8008cde <USBD_ClrFeature+0x2e>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8008cc6: 683b ldr r3, [r7, #0]
|
|
8008cc8: 885b ldrh r3, [r3, #2]
|
|
8008cca: 2b01 cmp r3, #1
|
|
8008ccc: d10c bne.n 8008ce8 <USBD_ClrFeature+0x38>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8008cce: 687b ldr r3, [r7, #4]
|
|
8008cd0: 2200 movs r2, #0
|
|
8008cd2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
USBD_CtlSendStatus(pdev);
|
|
8008cd6: 6878 ldr r0, [r7, #4]
|
|
8008cd8: f000 f90c bl 8008ef4 <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
8008cdc: e004 b.n 8008ce8 <USBD_ClrFeature+0x38>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008cde: 6839 ldr r1, [r7, #0]
|
|
8008ce0: 6878 ldr r0, [r7, #4]
|
|
8008ce2: f000 f83f bl 8008d64 <USBD_CtlError>
|
|
break;
|
|
8008ce6: e000 b.n 8008cea <USBD_ClrFeature+0x3a>
|
|
break;
|
|
8008ce8: bf00 nop
|
|
}
|
|
}
|
|
8008cea: bf00 nop
|
|
8008cec: 3708 adds r7, #8
|
|
8008cee: 46bd mov sp, r7
|
|
8008cf0: bd80 pop {r7, pc}
|
|
|
|
08008cf2 <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
8008cf2: b480 push {r7}
|
|
8008cf4: b083 sub sp, #12
|
|
8008cf6: af00 add r7, sp, #0
|
|
8008cf8: 6078 str r0, [r7, #4]
|
|
8008cfa: 6039 str r1, [r7, #0]
|
|
req->bmRequest = *(uint8_t *)(pdata);
|
|
8008cfc: 683b ldr r3, [r7, #0]
|
|
8008cfe: 781a ldrb r2, [r3, #0]
|
|
8008d00: 687b ldr r3, [r7, #4]
|
|
8008d02: 701a strb r2, [r3, #0]
|
|
req->bRequest = *(uint8_t *)(pdata + 1U);
|
|
8008d04: 683b ldr r3, [r7, #0]
|
|
8008d06: 785a ldrb r2, [r3, #1]
|
|
8008d08: 687b ldr r3, [r7, #4]
|
|
8008d0a: 705a strb r2, [r3, #1]
|
|
req->wValue = SWAPBYTE(pdata + 2U);
|
|
8008d0c: 683b ldr r3, [r7, #0]
|
|
8008d0e: 3302 adds r3, #2
|
|
8008d10: 781b ldrb r3, [r3, #0]
|
|
8008d12: 461a mov r2, r3
|
|
8008d14: 683b ldr r3, [r7, #0]
|
|
8008d16: 3303 adds r3, #3
|
|
8008d18: 781b ldrb r3, [r3, #0]
|
|
8008d1a: 021b lsls r3, r3, #8
|
|
8008d1c: b29b uxth r3, r3
|
|
8008d1e: 4413 add r3, r2
|
|
8008d20: b29a uxth r2, r3
|
|
8008d22: 687b ldr r3, [r7, #4]
|
|
8008d24: 805a strh r2, [r3, #2]
|
|
req->wIndex = SWAPBYTE(pdata + 4U);
|
|
8008d26: 683b ldr r3, [r7, #0]
|
|
8008d28: 3304 adds r3, #4
|
|
8008d2a: 781b ldrb r3, [r3, #0]
|
|
8008d2c: 461a mov r2, r3
|
|
8008d2e: 683b ldr r3, [r7, #0]
|
|
8008d30: 3305 adds r3, #5
|
|
8008d32: 781b ldrb r3, [r3, #0]
|
|
8008d34: 021b lsls r3, r3, #8
|
|
8008d36: b29b uxth r3, r3
|
|
8008d38: 4413 add r3, r2
|
|
8008d3a: b29a uxth r2, r3
|
|
8008d3c: 687b ldr r3, [r7, #4]
|
|
8008d3e: 809a strh r2, [r3, #4]
|
|
req->wLength = SWAPBYTE(pdata + 6U);
|
|
8008d40: 683b ldr r3, [r7, #0]
|
|
8008d42: 3306 adds r3, #6
|
|
8008d44: 781b ldrb r3, [r3, #0]
|
|
8008d46: 461a mov r2, r3
|
|
8008d48: 683b ldr r3, [r7, #0]
|
|
8008d4a: 3307 adds r3, #7
|
|
8008d4c: 781b ldrb r3, [r3, #0]
|
|
8008d4e: 021b lsls r3, r3, #8
|
|
8008d50: b29b uxth r3, r3
|
|
8008d52: 4413 add r3, r2
|
|
8008d54: b29a uxth r2, r3
|
|
8008d56: 687b ldr r3, [r7, #4]
|
|
8008d58: 80da strh r2, [r3, #6]
|
|
|
|
}
|
|
8008d5a: bf00 nop
|
|
8008d5c: 370c adds r7, #12
|
|
8008d5e: 46bd mov sp, r7
|
|
8008d60: bc80 pop {r7}
|
|
8008d62: 4770 bx lr
|
|
|
|
08008d64 <USBD_CtlError>:
|
|
* @retval None
|
|
*/
|
|
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
8008d64: b580 push {r7, lr}
|
|
8008d66: b082 sub sp, #8
|
|
8008d68: af00 add r7, sp, #0
|
|
8008d6a: 6078 str r0, [r7, #4]
|
|
8008d6c: 6039 str r1, [r7, #0]
|
|
USBD_LL_StallEP(pdev, 0x80U);
|
|
8008d6e: 2180 movs r1, #128 @ 0x80
|
|
8008d70: 6878 ldr r0, [r7, #4]
|
|
8008d72: f000 fcd1 bl 8009718 <USBD_LL_StallEP>
|
|
USBD_LL_StallEP(pdev, 0U);
|
|
8008d76: 2100 movs r1, #0
|
|
8008d78: 6878 ldr r0, [r7, #4]
|
|
8008d7a: f000 fccd bl 8009718 <USBD_LL_StallEP>
|
|
}
|
|
8008d7e: bf00 nop
|
|
8008d80: 3708 adds r7, #8
|
|
8008d82: 46bd mov sp, r7
|
|
8008d84: bd80 pop {r7, pc}
|
|
|
|
08008d86 <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
8008d86: b580 push {r7, lr}
|
|
8008d88: b086 sub sp, #24
|
|
8008d8a: af00 add r7, sp, #0
|
|
8008d8c: 60f8 str r0, [r7, #12]
|
|
8008d8e: 60b9 str r1, [r7, #8]
|
|
8008d90: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
8008d92: 2300 movs r3, #0
|
|
8008d94: 75fb strb r3, [r7, #23]
|
|
|
|
if (desc != NULL)
|
|
8008d96: 68fb ldr r3, [r7, #12]
|
|
8008d98: 2b00 cmp r3, #0
|
|
8008d9a: d032 beq.n 8008e02 <USBD_GetString+0x7c>
|
|
{
|
|
*len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
|
|
8008d9c: 68f8 ldr r0, [r7, #12]
|
|
8008d9e: f000 f834 bl 8008e0a <USBD_GetLen>
|
|
8008da2: 4603 mov r3, r0
|
|
8008da4: 3301 adds r3, #1
|
|
8008da6: b29b uxth r3, r3
|
|
8008da8: 005b lsls r3, r3, #1
|
|
8008daa: b29a uxth r2, r3
|
|
8008dac: 687b ldr r3, [r7, #4]
|
|
8008dae: 801a strh r2, [r3, #0]
|
|
unicode[idx++] = *(uint8_t *)(void *)len;
|
|
8008db0: 7dfb ldrb r3, [r7, #23]
|
|
8008db2: 1c5a adds r2, r3, #1
|
|
8008db4: 75fa strb r2, [r7, #23]
|
|
8008db6: 461a mov r2, r3
|
|
8008db8: 68bb ldr r3, [r7, #8]
|
|
8008dba: 4413 add r3, r2
|
|
8008dbc: 687a ldr r2, [r7, #4]
|
|
8008dbe: 7812 ldrb r2, [r2, #0]
|
|
8008dc0: 701a strb r2, [r3, #0]
|
|
unicode[idx++] = USB_DESC_TYPE_STRING;
|
|
8008dc2: 7dfb ldrb r3, [r7, #23]
|
|
8008dc4: 1c5a adds r2, r3, #1
|
|
8008dc6: 75fa strb r2, [r7, #23]
|
|
8008dc8: 461a mov r2, r3
|
|
8008dca: 68bb ldr r3, [r7, #8]
|
|
8008dcc: 4413 add r3, r2
|
|
8008dce: 2203 movs r2, #3
|
|
8008dd0: 701a strb r2, [r3, #0]
|
|
|
|
while (*desc != '\0')
|
|
8008dd2: e012 b.n 8008dfa <USBD_GetString+0x74>
|
|
{
|
|
unicode[idx++] = *desc++;
|
|
8008dd4: 68fb ldr r3, [r7, #12]
|
|
8008dd6: 1c5a adds r2, r3, #1
|
|
8008dd8: 60fa str r2, [r7, #12]
|
|
8008dda: 7dfa ldrb r2, [r7, #23]
|
|
8008ddc: 1c51 adds r1, r2, #1
|
|
8008dde: 75f9 strb r1, [r7, #23]
|
|
8008de0: 4611 mov r1, r2
|
|
8008de2: 68ba ldr r2, [r7, #8]
|
|
8008de4: 440a add r2, r1
|
|
8008de6: 781b ldrb r3, [r3, #0]
|
|
8008de8: 7013 strb r3, [r2, #0]
|
|
unicode[idx++] = 0U;
|
|
8008dea: 7dfb ldrb r3, [r7, #23]
|
|
8008dec: 1c5a adds r2, r3, #1
|
|
8008dee: 75fa strb r2, [r7, #23]
|
|
8008df0: 461a mov r2, r3
|
|
8008df2: 68bb ldr r3, [r7, #8]
|
|
8008df4: 4413 add r3, r2
|
|
8008df6: 2200 movs r2, #0
|
|
8008df8: 701a strb r2, [r3, #0]
|
|
while (*desc != '\0')
|
|
8008dfa: 68fb ldr r3, [r7, #12]
|
|
8008dfc: 781b ldrb r3, [r3, #0]
|
|
8008dfe: 2b00 cmp r3, #0
|
|
8008e00: d1e8 bne.n 8008dd4 <USBD_GetString+0x4e>
|
|
}
|
|
}
|
|
}
|
|
8008e02: bf00 nop
|
|
8008e04: 3718 adds r7, #24
|
|
8008e06: 46bd mov sp, r7
|
|
8008e08: bd80 pop {r7, pc}
|
|
|
|
08008e0a <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
8008e0a: b480 push {r7}
|
|
8008e0c: b085 sub sp, #20
|
|
8008e0e: af00 add r7, sp, #0
|
|
8008e10: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
8008e12: 2300 movs r3, #0
|
|
8008e14: 73fb strb r3, [r7, #15]
|
|
|
|
while (*buf != '\0')
|
|
8008e16: e005 b.n 8008e24 <USBD_GetLen+0x1a>
|
|
{
|
|
len++;
|
|
8008e18: 7bfb ldrb r3, [r7, #15]
|
|
8008e1a: 3301 adds r3, #1
|
|
8008e1c: 73fb strb r3, [r7, #15]
|
|
buf++;
|
|
8008e1e: 687b ldr r3, [r7, #4]
|
|
8008e20: 3301 adds r3, #1
|
|
8008e22: 607b str r3, [r7, #4]
|
|
while (*buf != '\0')
|
|
8008e24: 687b ldr r3, [r7, #4]
|
|
8008e26: 781b ldrb r3, [r3, #0]
|
|
8008e28: 2b00 cmp r3, #0
|
|
8008e2a: d1f5 bne.n 8008e18 <USBD_GetLen+0xe>
|
|
}
|
|
|
|
return len;
|
|
8008e2c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008e2e: 4618 mov r0, r3
|
|
8008e30: 3714 adds r7, #20
|
|
8008e32: 46bd mov sp, r7
|
|
8008e34: bc80 pop {r7}
|
|
8008e36: 4770 bx lr
|
|
|
|
08008e38 <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint16_t len)
|
|
{
|
|
8008e38: b580 push {r7, lr}
|
|
8008e3a: b084 sub sp, #16
|
|
8008e3c: af00 add r7, sp, #0
|
|
8008e3e: 60f8 str r0, [r7, #12]
|
|
8008e40: 60b9 str r1, [r7, #8]
|
|
8008e42: 4613 mov r3, r2
|
|
8008e44: 80fb strh r3, [r7, #6]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
8008e46: 68fb ldr r3, [r7, #12]
|
|
8008e48: 2202 movs r2, #2
|
|
8008e4a: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
8008e4e: 88fa ldrh r2, [r7, #6]
|
|
8008e50: 68fb ldr r3, [r7, #12]
|
|
8008e52: 61da str r2, [r3, #28]
|
|
pdev->ep_in[0].rem_length = len;
|
|
8008e54: 88fa ldrh r2, [r7, #6]
|
|
8008e56: 68fb ldr r3, [r7, #12]
|
|
8008e58: 621a str r2, [r3, #32]
|
|
|
|
/* Start the transfer */
|
|
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8008e5a: 88fb ldrh r3, [r7, #6]
|
|
8008e5c: 68ba ldr r2, [r7, #8]
|
|
8008e5e: 2100 movs r1, #0
|
|
8008e60: 68f8 ldr r0, [r7, #12]
|
|
8008e62: f000 fce1 bl 8009828 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008e66: 2300 movs r3, #0
|
|
}
|
|
8008e68: 4618 mov r0, r3
|
|
8008e6a: 3710 adds r7, #16
|
|
8008e6c: 46bd mov sp, r7
|
|
8008e6e: bd80 pop {r7, pc}
|
|
|
|
08008e70 <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint16_t len)
|
|
{
|
|
8008e70: b580 push {r7, lr}
|
|
8008e72: b084 sub sp, #16
|
|
8008e74: af00 add r7, sp, #0
|
|
8008e76: 60f8 str r0, [r7, #12]
|
|
8008e78: 60b9 str r1, [r7, #8]
|
|
8008e7a: 4613 mov r3, r2
|
|
8008e7c: 80fb strh r3, [r7, #6]
|
|
/* Start the next transfer */
|
|
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8008e7e: 88fb ldrh r3, [r7, #6]
|
|
8008e80: 68ba ldr r2, [r7, #8]
|
|
8008e82: 2100 movs r1, #0
|
|
8008e84: 68f8 ldr r0, [r7, #12]
|
|
8008e86: f000 fccf bl 8009828 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008e8a: 2300 movs r3, #0
|
|
}
|
|
8008e8c: 4618 mov r0, r3
|
|
8008e8e: 3710 adds r7, #16
|
|
8008e90: 46bd mov sp, r7
|
|
8008e92: bd80 pop {r7, pc}
|
|
|
|
08008e94 <USBD_CtlPrepareRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint16_t len)
|
|
{
|
|
8008e94: b580 push {r7, lr}
|
|
8008e96: b084 sub sp, #16
|
|
8008e98: af00 add r7, sp, #0
|
|
8008e9a: 60f8 str r0, [r7, #12]
|
|
8008e9c: 60b9 str r1, [r7, #8]
|
|
8008e9e: 4613 mov r3, r2
|
|
8008ea0: 80fb strh r3, [r7, #6]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_OUT;
|
|
8008ea2: 68fb ldr r3, [r7, #12]
|
|
8008ea4: 2203 movs r2, #3
|
|
8008ea6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_out[0].total_length = len;
|
|
8008eaa: 88fa ldrh r2, [r7, #6]
|
|
8008eac: 68fb ldr r3, [r7, #12]
|
|
8008eae: f8c3 215c str.w r2, [r3, #348] @ 0x15c
|
|
pdev->ep_out[0].rem_length = len;
|
|
8008eb2: 88fa ldrh r2, [r7, #6]
|
|
8008eb4: 68fb ldr r3, [r7, #12]
|
|
8008eb6: f8c3 2160 str.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Start the transfer */
|
|
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8008eba: 88fb ldrh r3, [r7, #6]
|
|
8008ebc: 68ba ldr r2, [r7, #8]
|
|
8008ebe: 2100 movs r1, #0
|
|
8008ec0: 68f8 ldr r0, [r7, #12]
|
|
8008ec2: f000 fcd4 bl 800986e <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008ec6: 2300 movs r3, #0
|
|
}
|
|
8008ec8: 4618 mov r0, r3
|
|
8008eca: 3710 adds r7, #16
|
|
8008ecc: 46bd mov sp, r7
|
|
8008ece: bd80 pop {r7, pc}
|
|
|
|
08008ed0 <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint16_t len)
|
|
{
|
|
8008ed0: b580 push {r7, lr}
|
|
8008ed2: b084 sub sp, #16
|
|
8008ed4: af00 add r7, sp, #0
|
|
8008ed6: 60f8 str r0, [r7, #12]
|
|
8008ed8: 60b9 str r1, [r7, #8]
|
|
8008eda: 4613 mov r3, r2
|
|
8008edc: 80fb strh r3, [r7, #6]
|
|
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8008ede: 88fb ldrh r3, [r7, #6]
|
|
8008ee0: 68ba ldr r2, [r7, #8]
|
|
8008ee2: 2100 movs r1, #0
|
|
8008ee4: 68f8 ldr r0, [r7, #12]
|
|
8008ee6: f000 fcc2 bl 800986e <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008eea: 2300 movs r3, #0
|
|
}
|
|
8008eec: 4618 mov r0, r3
|
|
8008eee: 3710 adds r7, #16
|
|
8008ef0: 46bd mov sp, r7
|
|
8008ef2: bd80 pop {r7, pc}
|
|
|
|
08008ef4 <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008ef4: b580 push {r7, lr}
|
|
8008ef6: b082 sub sp, #8
|
|
8008ef8: af00 add r7, sp, #0
|
|
8008efa: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
8008efc: 687b ldr r3, [r7, #4]
|
|
8008efe: 2204 movs r2, #4
|
|
8008f00: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
8008f04: 2300 movs r3, #0
|
|
8008f06: 2200 movs r2, #0
|
|
8008f08: 2100 movs r1, #0
|
|
8008f0a: 6878 ldr r0, [r7, #4]
|
|
8008f0c: f000 fc8c bl 8009828 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008f10: 2300 movs r3, #0
|
|
}
|
|
8008f12: 4618 mov r0, r3
|
|
8008f14: 3708 adds r7, #8
|
|
8008f16: 46bd mov sp, r7
|
|
8008f18: bd80 pop {r7, pc}
|
|
|
|
08008f1a <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008f1a: b580 push {r7, lr}
|
|
8008f1c: b082 sub sp, #8
|
|
8008f1e: af00 add r7, sp, #0
|
|
8008f20: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
8008f22: 687b ldr r3, [r7, #4]
|
|
8008f24: 2205 movs r2, #5
|
|
8008f26: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8008f2a: 2300 movs r3, #0
|
|
8008f2c: 2200 movs r2, #0
|
|
8008f2e: 2100 movs r1, #0
|
|
8008f30: 6878 ldr r0, [r7, #4]
|
|
8008f32: f000 fc9c bl 800986e <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008f36: 2300 movs r3, #0
|
|
}
|
|
8008f38: 4618 mov r0, r3
|
|
8008f3a: 3708 adds r7, #8
|
|
8008f3c: 46bd mov sp, r7
|
|
8008f3e: bd80 pop {r7, pc}
|
|
|
|
08008f40 <MX_USB_DEVICE_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_DEVICE_Init(void)
|
|
{
|
|
8008f40: b580 push {r7, lr}
|
|
8008f42: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
|
|
8008f44: 2200 movs r2, #0
|
|
8008f46: 4912 ldr r1, [pc, #72] @ (8008f90 <MX_USB_DEVICE_Init+0x50>)
|
|
8008f48: 4812 ldr r0, [pc, #72] @ (8008f94 <MX_USB_DEVICE_Init+0x54>)
|
|
8008f4a: f7fe ff62 bl 8007e12 <USBD_Init>
|
|
8008f4e: 4603 mov r3, r0
|
|
8008f50: 2b00 cmp r3, #0
|
|
8008f52: d001 beq.n 8008f58 <MX_USB_DEVICE_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
8008f54: f7f7 fe64 bl 8000c20 <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
|
|
8008f58: 490f ldr r1, [pc, #60] @ (8008f98 <MX_USB_DEVICE_Init+0x58>)
|
|
8008f5a: 480e ldr r0, [pc, #56] @ (8008f94 <MX_USB_DEVICE_Init+0x54>)
|
|
8008f5c: f7fe ff84 bl 8007e68 <USBD_RegisterClass>
|
|
8008f60: 4603 mov r3, r0
|
|
8008f62: 2b00 cmp r3, #0
|
|
8008f64: d001 beq.n 8008f6a <MX_USB_DEVICE_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
8008f66: f7f7 fe5b bl 8000c20 <Error_Handler>
|
|
}
|
|
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
|
|
8008f6a: 490c ldr r1, [pc, #48] @ (8008f9c <MX_USB_DEVICE_Init+0x5c>)
|
|
8008f6c: 4809 ldr r0, [pc, #36] @ (8008f94 <MX_USB_DEVICE_Init+0x54>)
|
|
8008f6e: f7fe feb5 bl 8007cdc <USBD_CDC_RegisterInterface>
|
|
8008f72: 4603 mov r3, r0
|
|
8008f74: 2b00 cmp r3, #0
|
|
8008f76: d001 beq.n 8008f7c <MX_USB_DEVICE_Init+0x3c>
|
|
{
|
|
Error_Handler();
|
|
8008f78: f7f7 fe52 bl 8000c20 <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
|
|
8008f7c: 4805 ldr r0, [pc, #20] @ (8008f94 <MX_USB_DEVICE_Init+0x54>)
|
|
8008f7e: f7fe ff8c bl 8007e9a <USBD_Start>
|
|
8008f82: 4603 mov r3, r0
|
|
8008f84: 2b00 cmp r3, #0
|
|
8008f86: d001 beq.n 8008f8c <MX_USB_DEVICE_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8008f88: f7f7 fe4a bl 8000c20 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PostTreatment */
|
|
}
|
|
8008f8c: bf00 nop
|
|
8008f8e: bd80 pop {r7, pc}
|
|
8008f90: 2000012c .word 0x2000012c
|
|
8008f94: 200003b0 .word 0x200003b0
|
|
8008f98: 20000018 .word 0x20000018
|
|
8008f9c: 2000011c .word 0x2000011c
|
|
|
|
08008fa0 <fifo_push>:
|
|
/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
|
|
#define RX_FIFO_SZ 256
|
|
static uint8_t rx_fifo[RX_FIFO_SZ];
|
|
static volatile uint16_t rx_head = 0, rx_tail = 0;
|
|
|
|
static void fifo_push(const uint8_t* data, uint32_t len) {
|
|
8008fa0: b480 push {r7}
|
|
8008fa2: b085 sub sp, #20
|
|
8008fa4: af00 add r7, sp, #0
|
|
8008fa6: 6078 str r0, [r7, #4]
|
|
8008fa8: 6039 str r1, [r7, #0]
|
|
while (len--) {
|
|
8008faa: e01e b.n 8008fea <fifo_push+0x4a>
|
|
uint16_t next = (rx_head + 1u) & (RX_FIFO_SZ - 1u);
|
|
8008fac: 4b14 ldr r3, [pc, #80] @ (8009000 <fifo_push+0x60>)
|
|
8008fae: 881b ldrh r3, [r3, #0]
|
|
8008fb0: b29b uxth r3, r3
|
|
8008fb2: 3301 adds r3, #1
|
|
8008fb4: b29b uxth r3, r3
|
|
8008fb6: b2db uxtb r3, r3
|
|
8008fb8: 81fb strh r3, [r7, #14]
|
|
if (next == (rx_tail & (RX_FIFO_SZ - 1u))) {
|
|
8008fba: 89fa ldrh r2, [r7, #14]
|
|
8008fbc: 4b11 ldr r3, [pc, #68] @ (8009004 <fifo_push+0x64>)
|
|
8008fbe: 881b ldrh r3, [r3, #0]
|
|
8008fc0: b29b uxth r3, r3
|
|
8008fc2: b2db uxtb r3, r3
|
|
8008fc4: 429a cmp r2, r3
|
|
8008fc6: d103 bne.n 8008fd0 <fifo_push+0x30>
|
|
/* overflow — drop byte (or set a flag) */
|
|
data++;
|
|
8008fc8: 687b ldr r3, [r7, #4]
|
|
8008fca: 3301 adds r3, #1
|
|
8008fcc: 607b str r3, [r7, #4]
|
|
continue;
|
|
8008fce: e00c b.n 8008fea <fifo_push+0x4a>
|
|
}
|
|
rx_fifo[rx_head & (RX_FIFO_SZ - 1u)] = *data++;
|
|
8008fd0: 687b ldr r3, [r7, #4]
|
|
8008fd2: 1c5a adds r2, r3, #1
|
|
8008fd4: 607a str r2, [r7, #4]
|
|
8008fd6: 4a0a ldr r2, [pc, #40] @ (8009000 <fifo_push+0x60>)
|
|
8008fd8: 8812 ldrh r2, [r2, #0]
|
|
8008fda: b292 uxth r2, r2
|
|
8008fdc: b2d2 uxtb r2, r2
|
|
8008fde: 7819 ldrb r1, [r3, #0]
|
|
8008fe0: 4b09 ldr r3, [pc, #36] @ (8009008 <fifo_push+0x68>)
|
|
8008fe2: 5499 strb r1, [r3, r2]
|
|
rx_head = next;
|
|
8008fe4: 4a06 ldr r2, [pc, #24] @ (8009000 <fifo_push+0x60>)
|
|
8008fe6: 89fb ldrh r3, [r7, #14]
|
|
8008fe8: 8013 strh r3, [r2, #0]
|
|
while (len--) {
|
|
8008fea: 683b ldr r3, [r7, #0]
|
|
8008fec: 1e5a subs r2, r3, #1
|
|
8008fee: 603a str r2, [r7, #0]
|
|
8008ff0: 2b00 cmp r3, #0
|
|
8008ff2: d1db bne.n 8008fac <fifo_push+0xc>
|
|
}
|
|
}
|
|
8008ff4: bf00 nop
|
|
8008ff6: bf00 nop
|
|
8008ff8: 3714 adds r7, #20
|
|
8008ffa: 46bd mov sp, r7
|
|
8008ffc: bc80 pop {r7}
|
|
8008ffe: 4770 bx lr
|
|
8009000: 20000f74 .word 0x20000f74
|
|
8009004: 20000f76 .word 0x20000f76
|
|
8009008: 20000e74 .word 0x20000e74
|
|
|
|
0800900c <CDC_Available>:
|
|
|
|
uint32_t CDC_Available(void) {
|
|
800900c: b480 push {r7}
|
|
800900e: af00 add r7, sp, #0
|
|
return (uint16_t)((rx_head - rx_tail) & (RX_FIFO_SZ - 1u));
|
|
8009010: 4b06 ldr r3, [pc, #24] @ (800902c <CDC_Available+0x20>)
|
|
8009012: 881b ldrh r3, [r3, #0]
|
|
8009014: b29a uxth r2, r3
|
|
8009016: 4b06 ldr r3, [pc, #24] @ (8009030 <CDC_Available+0x24>)
|
|
8009018: 881b ldrh r3, [r3, #0]
|
|
800901a: b29b uxth r3, r3
|
|
800901c: 1ad3 subs r3, r2, r3
|
|
800901e: b29b uxth r3, r3
|
|
8009020: b2db uxtb r3, r3
|
|
}
|
|
8009022: 4618 mov r0, r3
|
|
8009024: 46bd mov sp, r7
|
|
8009026: bc80 pop {r7}
|
|
8009028: 4770 bx lr
|
|
800902a: bf00 nop
|
|
800902c: 20000f74 .word 0x20000f74
|
|
8009030: 20000f76 .word 0x20000f76
|
|
|
|
08009034 <CDC_ReadByte>:
|
|
|
|
int CDC_ReadByte(void) {
|
|
8009034: b480 push {r7}
|
|
8009036: b083 sub sp, #12
|
|
8009038: af00 add r7, sp, #0
|
|
if (rx_tail == rx_head) return -1;
|
|
800903a: 4b10 ldr r3, [pc, #64] @ (800907c <CDC_ReadByte+0x48>)
|
|
800903c: 881b ldrh r3, [r3, #0]
|
|
800903e: b29a uxth r2, r3
|
|
8009040: 4b0f ldr r3, [pc, #60] @ (8009080 <CDC_ReadByte+0x4c>)
|
|
8009042: 881b ldrh r3, [r3, #0]
|
|
8009044: b29b uxth r3, r3
|
|
8009046: 429a cmp r2, r3
|
|
8009048: d102 bne.n 8009050 <CDC_ReadByte+0x1c>
|
|
800904a: f04f 33ff mov.w r3, #4294967295
|
|
800904e: e010 b.n 8009072 <CDC_ReadByte+0x3e>
|
|
int b = rx_fifo[rx_tail & (RX_FIFO_SZ - 1u)];
|
|
8009050: 4b0a ldr r3, [pc, #40] @ (800907c <CDC_ReadByte+0x48>)
|
|
8009052: 881b ldrh r3, [r3, #0]
|
|
8009054: b29b uxth r3, r3
|
|
8009056: b2db uxtb r3, r3
|
|
8009058: 4a0a ldr r2, [pc, #40] @ (8009084 <CDC_ReadByte+0x50>)
|
|
800905a: 5cd3 ldrb r3, [r2, r3]
|
|
800905c: 607b str r3, [r7, #4]
|
|
rx_tail = (rx_tail + 1u) & (RX_FIFO_SZ - 1u);
|
|
800905e: 4b07 ldr r3, [pc, #28] @ (800907c <CDC_ReadByte+0x48>)
|
|
8009060: 881b ldrh r3, [r3, #0]
|
|
8009062: b29b uxth r3, r3
|
|
8009064: 3301 adds r3, #1
|
|
8009066: b29b uxth r3, r3
|
|
8009068: b2db uxtb r3, r3
|
|
800906a: b29a uxth r2, r3
|
|
800906c: 4b03 ldr r3, [pc, #12] @ (800907c <CDC_ReadByte+0x48>)
|
|
800906e: 801a strh r2, [r3, #0]
|
|
return b;
|
|
8009070: 687b ldr r3, [r7, #4]
|
|
}
|
|
8009072: 4618 mov r0, r3
|
|
8009074: 370c adds r7, #12
|
|
8009076: 46bd mov sp, r7
|
|
8009078: bc80 pop {r7}
|
|
800907a: 4770 bx lr
|
|
800907c: 20000f76 .word 0x20000f76
|
|
8009080: 20000f74 .word 0x20000f74
|
|
8009084: 20000e74 .word 0x20000e74
|
|
|
|
08009088 <CDC_Init_FS>:
|
|
/**
|
|
* @brief Initializes the CDC media low layer over the FS USB IP
|
|
* @retval USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_Init_FS(void)
|
|
{
|
|
8009088: b580 push {r7, lr}
|
|
800908a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 3 */
|
|
/* Set Application Buffers */
|
|
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
|
|
800908c: 2200 movs r2, #0
|
|
800908e: 4905 ldr r1, [pc, #20] @ (80090a4 <CDC_Init_FS+0x1c>)
|
|
8009090: 4805 ldr r0, [pc, #20] @ (80090a8 <CDC_Init_FS+0x20>)
|
|
8009092: f7fe fe39 bl 8007d08 <USBD_CDC_SetTxBuffer>
|
|
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
|
|
8009096: 4905 ldr r1, [pc, #20] @ (80090ac <CDC_Init_FS+0x24>)
|
|
8009098: 4803 ldr r0, [pc, #12] @ (80090a8 <CDC_Init_FS+0x20>)
|
|
800909a: f7fe fe4e bl 8007d3a <USBD_CDC_SetRxBuffer>
|
|
return (USBD_OK);
|
|
800909e: 2300 movs r3, #0
|
|
/* USER CODE END 3 */
|
|
}
|
|
80090a0: 4618 mov r0, r3
|
|
80090a2: bd80 pop {r7, pc}
|
|
80090a4: 20000a74 .word 0x20000a74
|
|
80090a8: 200003b0 .word 0x200003b0
|
|
80090ac: 20000674 .word 0x20000674
|
|
|
|
080090b0 <CDC_DeInit_FS>:
|
|
/**
|
|
* @brief DeInitializes the CDC media low layer
|
|
* @retval USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_DeInit_FS(void)
|
|
{
|
|
80090b0: b480 push {r7}
|
|
80090b2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 4 */
|
|
return (USBD_OK);
|
|
80090b4: 2300 movs r3, #0
|
|
/* USER CODE END 4 */
|
|
}
|
|
80090b6: 4618 mov r0, r3
|
|
80090b8: 46bd mov sp, r7
|
|
80090ba: bc80 pop {r7}
|
|
80090bc: 4770 bx lr
|
|
...
|
|
|
|
080090c0 <CDC_Control_FS>:
|
|
* @param pbuf: Buffer containing command data (request parameters)
|
|
* @param length: Number of data to be sent (in bytes)
|
|
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
|
|
{
|
|
80090c0: b480 push {r7}
|
|
80090c2: b083 sub sp, #12
|
|
80090c4: af00 add r7, sp, #0
|
|
80090c6: 4603 mov r3, r0
|
|
80090c8: 6039 str r1, [r7, #0]
|
|
80090ca: 71fb strb r3, [r7, #7]
|
|
80090cc: 4613 mov r3, r2
|
|
80090ce: 80bb strh r3, [r7, #4]
|
|
/* USER CODE BEGIN 5 */
|
|
switch(cmd)
|
|
80090d0: 79fb ldrb r3, [r7, #7]
|
|
80090d2: 2b23 cmp r3, #35 @ 0x23
|
|
80090d4: d84a bhi.n 800916c <CDC_Control_FS+0xac>
|
|
80090d6: a201 add r2, pc, #4 @ (adr r2, 80090dc <CDC_Control_FS+0x1c>)
|
|
80090d8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80090dc: 0800916d .word 0x0800916d
|
|
80090e0: 0800916d .word 0x0800916d
|
|
80090e4: 0800916d .word 0x0800916d
|
|
80090e8: 0800916d .word 0x0800916d
|
|
80090ec: 0800916d .word 0x0800916d
|
|
80090f0: 0800916d .word 0x0800916d
|
|
80090f4: 0800916d .word 0x0800916d
|
|
80090f8: 0800916d .word 0x0800916d
|
|
80090fc: 0800916d .word 0x0800916d
|
|
8009100: 0800916d .word 0x0800916d
|
|
8009104: 0800916d .word 0x0800916d
|
|
8009108: 0800916d .word 0x0800916d
|
|
800910c: 0800916d .word 0x0800916d
|
|
8009110: 0800916d .word 0x0800916d
|
|
8009114: 0800916d .word 0x0800916d
|
|
8009118: 0800916d .word 0x0800916d
|
|
800911c: 0800916d .word 0x0800916d
|
|
8009120: 0800916d .word 0x0800916d
|
|
8009124: 0800916d .word 0x0800916d
|
|
8009128: 0800916d .word 0x0800916d
|
|
800912c: 0800916d .word 0x0800916d
|
|
8009130: 0800916d .word 0x0800916d
|
|
8009134: 0800916d .word 0x0800916d
|
|
8009138: 0800916d .word 0x0800916d
|
|
800913c: 0800916d .word 0x0800916d
|
|
8009140: 0800916d .word 0x0800916d
|
|
8009144: 0800916d .word 0x0800916d
|
|
8009148: 0800916d .word 0x0800916d
|
|
800914c: 0800916d .word 0x0800916d
|
|
8009150: 0800916d .word 0x0800916d
|
|
8009154: 0800916d .word 0x0800916d
|
|
8009158: 0800916d .word 0x0800916d
|
|
800915c: 0800916d .word 0x0800916d
|
|
8009160: 0800916d .word 0x0800916d
|
|
8009164: 0800916d .word 0x0800916d
|
|
8009168: 0800916d .word 0x0800916d
|
|
case CDC_SEND_BREAK:
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
800916c: bf00 nop
|
|
}
|
|
|
|
return (USBD_OK);
|
|
800916e: 2300 movs r3, #0
|
|
/* USER CODE END 5 */
|
|
}
|
|
8009170: 4618 mov r0, r3
|
|
8009172: 370c adds r7, #12
|
|
8009174: 46bd mov sp, r7
|
|
8009176: bc80 pop {r7}
|
|
8009178: 4770 bx lr
|
|
800917a: bf00 nop
|
|
|
|
0800917c <CDC_Receive_FS>:
|
|
* @param Buf: Buffer of data to be received
|
|
* @param Len: Number of data received (in bytes)
|
|
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
|
|
{
|
|
800917c: b580 push {r7, lr}
|
|
800917e: b082 sub sp, #8
|
|
8009180: af00 add r7, sp, #0
|
|
8009182: 6078 str r0, [r7, #4]
|
|
8009184: 6039 str r1, [r7, #0]
|
|
/* USER CODE BEGIN 6 */
|
|
if (*Len) fifo_push(Buf, *Len);
|
|
8009186: 683b ldr r3, [r7, #0]
|
|
8009188: 681b ldr r3, [r3, #0]
|
|
800918a: 2b00 cmp r3, #0
|
|
800918c: d005 beq.n 800919a <CDC_Receive_FS+0x1e>
|
|
800918e: 683b ldr r3, [r7, #0]
|
|
8009190: 681b ldr r3, [r3, #0]
|
|
8009192: 4619 mov r1, r3
|
|
8009194: 6878 ldr r0, [r7, #4]
|
|
8009196: f7ff ff03 bl 8008fa0 <fifo_push>
|
|
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
|
|
800919a: 6879 ldr r1, [r7, #4]
|
|
800919c: 4805 ldr r0, [pc, #20] @ (80091b4 <CDC_Receive_FS+0x38>)
|
|
800919e: f7fe fdcc bl 8007d3a <USBD_CDC_SetRxBuffer>
|
|
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
|
|
80091a2: 4804 ldr r0, [pc, #16] @ (80091b4 <CDC_Receive_FS+0x38>)
|
|
80091a4: f7fe fe0b bl 8007dbe <USBD_CDC_ReceivePacket>
|
|
return (USBD_OK);
|
|
80091a8: 2300 movs r3, #0
|
|
/* USER CODE END 6 */
|
|
}
|
|
80091aa: 4618 mov r0, r3
|
|
80091ac: 3708 adds r7, #8
|
|
80091ae: 46bd mov sp, r7
|
|
80091b0: bd80 pop {r7, pc}
|
|
80091b2: bf00 nop
|
|
80091b4: 200003b0 .word 0x200003b0
|
|
|
|
080091b8 <CDC_Transmit_FS>:
|
|
* @param Buf: Buffer of data to be sent
|
|
* @param Len: Number of data to be sent (in bytes)
|
|
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
|
|
*/
|
|
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
|
|
{
|
|
80091b8: b580 push {r7, lr}
|
|
80091ba: b084 sub sp, #16
|
|
80091bc: af00 add r7, sp, #0
|
|
80091be: 6078 str r0, [r7, #4]
|
|
80091c0: 460b mov r3, r1
|
|
80091c2: 807b strh r3, [r7, #2]
|
|
uint8_t result = USBD_OK;
|
|
80091c4: 2300 movs r3, #0
|
|
80091c6: 73fb strb r3, [r7, #15]
|
|
/* USER CODE BEGIN 7 */
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
|
|
80091c8: 4b0d ldr r3, [pc, #52] @ (8009200 <CDC_Transmit_FS+0x48>)
|
|
80091ca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80091ce: 60bb str r3, [r7, #8]
|
|
if (hcdc->TxState != 0){
|
|
80091d0: 68bb ldr r3, [r7, #8]
|
|
80091d2: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
|
|
80091d6: 2b00 cmp r3, #0
|
|
80091d8: d001 beq.n 80091de <CDC_Transmit_FS+0x26>
|
|
return USBD_BUSY;
|
|
80091da: 2301 movs r3, #1
|
|
80091dc: e00b b.n 80091f6 <CDC_Transmit_FS+0x3e>
|
|
}
|
|
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
|
|
80091de: 887b ldrh r3, [r7, #2]
|
|
80091e0: 461a mov r2, r3
|
|
80091e2: 6879 ldr r1, [r7, #4]
|
|
80091e4: 4806 ldr r0, [pc, #24] @ (8009200 <CDC_Transmit_FS+0x48>)
|
|
80091e6: f7fe fd8f bl 8007d08 <USBD_CDC_SetTxBuffer>
|
|
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
|
|
80091ea: 4805 ldr r0, [pc, #20] @ (8009200 <CDC_Transmit_FS+0x48>)
|
|
80091ec: f7fe fdb8 bl 8007d60 <USBD_CDC_TransmitPacket>
|
|
80091f0: 4603 mov r3, r0
|
|
80091f2: 73fb strb r3, [r7, #15]
|
|
/* USER CODE END 7 */
|
|
return result;
|
|
80091f4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80091f6: 4618 mov r0, r3
|
|
80091f8: 3710 adds r7, #16
|
|
80091fa: 46bd mov sp, r7
|
|
80091fc: bd80 pop {r7, pc}
|
|
80091fe: bf00 nop
|
|
8009200: 200003b0 .word 0x200003b0
|
|
|
|
08009204 <USBD_FS_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8009204: b480 push {r7}
|
|
8009206: b083 sub sp, #12
|
|
8009208: af00 add r7, sp, #0
|
|
800920a: 4603 mov r3, r0
|
|
800920c: 6039 str r1, [r7, #0]
|
|
800920e: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_DeviceDesc);
|
|
8009210: 683b ldr r3, [r7, #0]
|
|
8009212: 2212 movs r2, #18
|
|
8009214: 801a strh r2, [r3, #0]
|
|
return USBD_FS_DeviceDesc;
|
|
8009216: 4b03 ldr r3, [pc, #12] @ (8009224 <USBD_FS_DeviceDescriptor+0x20>)
|
|
}
|
|
8009218: 4618 mov r0, r3
|
|
800921a: 370c adds r7, #12
|
|
800921c: 46bd mov sp, r7
|
|
800921e: bc80 pop {r7}
|
|
8009220: 4770 bx lr
|
|
8009222: bf00 nop
|
|
8009224: 20000148 .word 0x20000148
|
|
|
|
08009228 <USBD_FS_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8009228: b480 push {r7}
|
|
800922a: b083 sub sp, #12
|
|
800922c: af00 add r7, sp, #0
|
|
800922e: 4603 mov r3, r0
|
|
8009230: 6039 str r1, [r7, #0]
|
|
8009232: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
8009234: 683b ldr r3, [r7, #0]
|
|
8009236: 2204 movs r2, #4
|
|
8009238: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
800923a: 4b03 ldr r3, [pc, #12] @ (8009248 <USBD_FS_LangIDStrDescriptor+0x20>)
|
|
}
|
|
800923c: 4618 mov r0, r3
|
|
800923e: 370c adds r7, #12
|
|
8009240: 46bd mov sp, r7
|
|
8009242: bc80 pop {r7}
|
|
8009244: 4770 bx lr
|
|
8009246: bf00 nop
|
|
8009248: 2000015c .word 0x2000015c
|
|
|
|
0800924c <USBD_FS_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800924c: b580 push {r7, lr}
|
|
800924e: b082 sub sp, #8
|
|
8009250: af00 add r7, sp, #0
|
|
8009252: 4603 mov r3, r0
|
|
8009254: 6039 str r1, [r7, #0]
|
|
8009256: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8009258: 79fb ldrb r3, [r7, #7]
|
|
800925a: 2b00 cmp r3, #0
|
|
800925c: d105 bne.n 800926a <USBD_FS_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
800925e: 683a ldr r2, [r7, #0]
|
|
8009260: 4907 ldr r1, [pc, #28] @ (8009280 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
8009262: 4808 ldr r0, [pc, #32] @ (8009284 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8009264: f7ff fd8f bl 8008d86 <USBD_GetString>
|
|
8009268: e004 b.n 8009274 <USBD_FS_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
800926a: 683a ldr r2, [r7, #0]
|
|
800926c: 4904 ldr r1, [pc, #16] @ (8009280 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
800926e: 4805 ldr r0, [pc, #20] @ (8009284 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8009270: f7ff fd89 bl 8008d86 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8009274: 4b02 ldr r3, [pc, #8] @ (8009280 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
}
|
|
8009276: 4618 mov r0, r3
|
|
8009278: 3708 adds r7, #8
|
|
800927a: 46bd mov sp, r7
|
|
800927c: bd80 pop {r7, pc}
|
|
800927e: bf00 nop
|
|
8009280: 20000f78 .word 0x20000f78
|
|
8009284: 0800a3a0 .word 0x0800a3a0
|
|
|
|
08009288 <USBD_FS_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8009288: b580 push {r7, lr}
|
|
800928a: b082 sub sp, #8
|
|
800928c: af00 add r7, sp, #0
|
|
800928e: 4603 mov r3, r0
|
|
8009290: 6039 str r1, [r7, #0]
|
|
8009292: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
8009294: 683a ldr r2, [r7, #0]
|
|
8009296: 4904 ldr r1, [pc, #16] @ (80092a8 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
8009298: 4804 ldr r0, [pc, #16] @ (80092ac <USBD_FS_ManufacturerStrDescriptor+0x24>)
|
|
800929a: f7ff fd74 bl 8008d86 <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
800929e: 4b02 ldr r3, [pc, #8] @ (80092a8 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
80092a0: 4618 mov r0, r3
|
|
80092a2: 3708 adds r7, #8
|
|
80092a4: 46bd mov sp, r7
|
|
80092a6: bd80 pop {r7, pc}
|
|
80092a8: 20000f78 .word 0x20000f78
|
|
80092ac: 0800a3b8 .word 0x0800a3b8
|
|
|
|
080092b0 <USBD_FS_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
80092b0: b580 push {r7, lr}
|
|
80092b2: b082 sub sp, #8
|
|
80092b4: af00 add r7, sp, #0
|
|
80092b6: 4603 mov r3, r0
|
|
80092b8: 6039 str r1, [r7, #0]
|
|
80092ba: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
80092bc: 683b ldr r3, [r7, #0]
|
|
80092be: 221a movs r2, #26
|
|
80092c0: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
80092c2: f000 f843 bl 800934c <Get_SerialNum>
|
|
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_FS_SerialStrDescriptor */
|
|
return (uint8_t *) USBD_StringSerial;
|
|
80092c6: 4b02 ldr r3, [pc, #8] @ (80092d0 <USBD_FS_SerialStrDescriptor+0x20>)
|
|
}
|
|
80092c8: 4618 mov r0, r3
|
|
80092ca: 3708 adds r7, #8
|
|
80092cc: 46bd mov sp, r7
|
|
80092ce: bd80 pop {r7, pc}
|
|
80092d0: 20000160 .word 0x20000160
|
|
|
|
080092d4 <USBD_FS_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
80092d4: b580 push {r7, lr}
|
|
80092d6: b082 sub sp, #8
|
|
80092d8: af00 add r7, sp, #0
|
|
80092da: 4603 mov r3, r0
|
|
80092dc: 6039 str r1, [r7, #0]
|
|
80092de: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
80092e0: 79fb ldrb r3, [r7, #7]
|
|
80092e2: 2b00 cmp r3, #0
|
|
80092e4: d105 bne.n 80092f2 <USBD_FS_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
80092e6: 683a ldr r2, [r7, #0]
|
|
80092e8: 4907 ldr r1, [pc, #28] @ (8009308 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
80092ea: 4808 ldr r0, [pc, #32] @ (800930c <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
80092ec: f7ff fd4b bl 8008d86 <USBD_GetString>
|
|
80092f0: e004 b.n 80092fc <USBD_FS_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
80092f2: 683a ldr r2, [r7, #0]
|
|
80092f4: 4904 ldr r1, [pc, #16] @ (8009308 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
80092f6: 4805 ldr r0, [pc, #20] @ (800930c <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
80092f8: f7ff fd45 bl 8008d86 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
80092fc: 4b02 ldr r3, [pc, #8] @ (8009308 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
}
|
|
80092fe: 4618 mov r0, r3
|
|
8009300: 3708 adds r7, #8
|
|
8009302: 46bd mov sp, r7
|
|
8009304: bd80 pop {r7, pc}
|
|
8009306: bf00 nop
|
|
8009308: 20000f78 .word 0x20000f78
|
|
800930c: 0800a3cc .word 0x0800a3cc
|
|
|
|
08009310 <USBD_FS_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8009310: b580 push {r7, lr}
|
|
8009312: b082 sub sp, #8
|
|
8009314: af00 add r7, sp, #0
|
|
8009316: 4603 mov r3, r0
|
|
8009318: 6039 str r1, [r7, #0]
|
|
800931a: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
800931c: 79fb ldrb r3, [r7, #7]
|
|
800931e: 2b00 cmp r3, #0
|
|
8009320: d105 bne.n 800932e <USBD_FS_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
8009322: 683a ldr r2, [r7, #0]
|
|
8009324: 4907 ldr r1, [pc, #28] @ (8009344 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
8009326: 4808 ldr r0, [pc, #32] @ (8009348 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8009328: f7ff fd2d bl 8008d86 <USBD_GetString>
|
|
800932c: e004 b.n 8009338 <USBD_FS_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
800932e: 683a ldr r2, [r7, #0]
|
|
8009330: 4904 ldr r1, [pc, #16] @ (8009344 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
8009332: 4805 ldr r0, [pc, #20] @ (8009348 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8009334: f7ff fd27 bl 8008d86 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8009338: 4b02 ldr r3, [pc, #8] @ (8009344 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
800933a: 4618 mov r0, r3
|
|
800933c: 3708 adds r7, #8
|
|
800933e: 46bd mov sp, r7
|
|
8009340: bd80 pop {r7, pc}
|
|
8009342: bf00 nop
|
|
8009344: 20000f78 .word 0x20000f78
|
|
8009348: 0800a3d8 .word 0x0800a3d8
|
|
|
|
0800934c <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
800934c: b580 push {r7, lr}
|
|
800934e: b084 sub sp, #16
|
|
8009350: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
8009352: 4b0f ldr r3, [pc, #60] @ (8009390 <Get_SerialNum+0x44>)
|
|
8009354: 681b ldr r3, [r3, #0]
|
|
8009356: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
8009358: 4b0e ldr r3, [pc, #56] @ (8009394 <Get_SerialNum+0x48>)
|
|
800935a: 681b ldr r3, [r3, #0]
|
|
800935c: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
800935e: 4b0e ldr r3, [pc, #56] @ (8009398 <Get_SerialNum+0x4c>)
|
|
8009360: 681b ldr r3, [r3, #0]
|
|
8009362: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
8009364: 68fa ldr r2, [r7, #12]
|
|
8009366: 687b ldr r3, [r7, #4]
|
|
8009368: 4413 add r3, r2
|
|
800936a: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
800936c: 68fb ldr r3, [r7, #12]
|
|
800936e: 2b00 cmp r3, #0
|
|
8009370: d009 beq.n 8009386 <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
8009372: 2208 movs r2, #8
|
|
8009374: 4909 ldr r1, [pc, #36] @ (800939c <Get_SerialNum+0x50>)
|
|
8009376: 68f8 ldr r0, [r7, #12]
|
|
8009378: f000 f814 bl 80093a4 <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
800937c: 2204 movs r2, #4
|
|
800937e: 4908 ldr r1, [pc, #32] @ (80093a0 <Get_SerialNum+0x54>)
|
|
8009380: 68b8 ldr r0, [r7, #8]
|
|
8009382: f000 f80f bl 80093a4 <IntToUnicode>
|
|
}
|
|
}
|
|
8009386: bf00 nop
|
|
8009388: 3710 adds r7, #16
|
|
800938a: 46bd mov sp, r7
|
|
800938c: bd80 pop {r7, pc}
|
|
800938e: bf00 nop
|
|
8009390: 1ffff7e8 .word 0x1ffff7e8
|
|
8009394: 1ffff7ec .word 0x1ffff7ec
|
|
8009398: 1ffff7f0 .word 0x1ffff7f0
|
|
800939c: 20000162 .word 0x20000162
|
|
80093a0: 20000172 .word 0x20000172
|
|
|
|
080093a4 <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
80093a4: b480 push {r7}
|
|
80093a6: b087 sub sp, #28
|
|
80093a8: af00 add r7, sp, #0
|
|
80093aa: 60f8 str r0, [r7, #12]
|
|
80093ac: 60b9 str r1, [r7, #8]
|
|
80093ae: 4613 mov r3, r2
|
|
80093b0: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
80093b2: 2300 movs r3, #0
|
|
80093b4: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
80093b6: 2300 movs r3, #0
|
|
80093b8: 75fb strb r3, [r7, #23]
|
|
80093ba: e027 b.n 800940c <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
80093bc: 68fb ldr r3, [r7, #12]
|
|
80093be: 0f1b lsrs r3, r3, #28
|
|
80093c0: 2b09 cmp r3, #9
|
|
80093c2: d80b bhi.n 80093dc <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
80093c4: 68fb ldr r3, [r7, #12]
|
|
80093c6: 0f1b lsrs r3, r3, #28
|
|
80093c8: b2da uxtb r2, r3
|
|
80093ca: 7dfb ldrb r3, [r7, #23]
|
|
80093cc: 005b lsls r3, r3, #1
|
|
80093ce: 4619 mov r1, r3
|
|
80093d0: 68bb ldr r3, [r7, #8]
|
|
80093d2: 440b add r3, r1
|
|
80093d4: 3230 adds r2, #48 @ 0x30
|
|
80093d6: b2d2 uxtb r2, r2
|
|
80093d8: 701a strb r2, [r3, #0]
|
|
80093da: e00a b.n 80093f2 <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
80093dc: 68fb ldr r3, [r7, #12]
|
|
80093de: 0f1b lsrs r3, r3, #28
|
|
80093e0: b2da uxtb r2, r3
|
|
80093e2: 7dfb ldrb r3, [r7, #23]
|
|
80093e4: 005b lsls r3, r3, #1
|
|
80093e6: 4619 mov r1, r3
|
|
80093e8: 68bb ldr r3, [r7, #8]
|
|
80093ea: 440b add r3, r1
|
|
80093ec: 3237 adds r2, #55 @ 0x37
|
|
80093ee: b2d2 uxtb r2, r2
|
|
80093f0: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
80093f2: 68fb ldr r3, [r7, #12]
|
|
80093f4: 011b lsls r3, r3, #4
|
|
80093f6: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
80093f8: 7dfb ldrb r3, [r7, #23]
|
|
80093fa: 005b lsls r3, r3, #1
|
|
80093fc: 3301 adds r3, #1
|
|
80093fe: 68ba ldr r2, [r7, #8]
|
|
8009400: 4413 add r3, r2
|
|
8009402: 2200 movs r2, #0
|
|
8009404: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
8009406: 7dfb ldrb r3, [r7, #23]
|
|
8009408: 3301 adds r3, #1
|
|
800940a: 75fb strb r3, [r7, #23]
|
|
800940c: 7dfa ldrb r2, [r7, #23]
|
|
800940e: 79fb ldrb r3, [r7, #7]
|
|
8009410: 429a cmp r2, r3
|
|
8009412: d3d3 bcc.n 80093bc <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
8009414: bf00 nop
|
|
8009416: bf00 nop
|
|
8009418: 371c adds r7, #28
|
|
800941a: 46bd mov sp, r7
|
|
800941c: bc80 pop {r7}
|
|
800941e: 4770 bx lr
|
|
|
|
08009420 <HAL_PCD_MspInit>:
|
|
LL Driver Callbacks (PCD -> USB Device Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
{
|
|
8009420: b580 push {r7, lr}
|
|
8009422: b084 sub sp, #16
|
|
8009424: af00 add r7, sp, #0
|
|
8009426: 6078 str r0, [r7, #4]
|
|
if(pcdHandle->Instance==USB)
|
|
8009428: 687b ldr r3, [r7, #4]
|
|
800942a: 681b ldr r3, [r3, #0]
|
|
800942c: 4a0d ldr r2, [pc, #52] @ (8009464 <HAL_PCD_MspInit+0x44>)
|
|
800942e: 4293 cmp r3, r2
|
|
8009430: d113 bne.n 800945a <HAL_PCD_MspInit+0x3a>
|
|
{
|
|
/* USER CODE BEGIN USB_MspInit 0 */
|
|
|
|
/* USER CODE END USB_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_CLK_ENABLE();
|
|
8009432: 4b0d ldr r3, [pc, #52] @ (8009468 <HAL_PCD_MspInit+0x48>)
|
|
8009434: 69db ldr r3, [r3, #28]
|
|
8009436: 4a0c ldr r2, [pc, #48] @ (8009468 <HAL_PCD_MspInit+0x48>)
|
|
8009438: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
|
|
800943c: 61d3 str r3, [r2, #28]
|
|
800943e: 4b0a ldr r3, [pc, #40] @ (8009468 <HAL_PCD_MspInit+0x48>)
|
|
8009440: 69db ldr r3, [r3, #28]
|
|
8009442: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8009446: 60fb str r3, [r7, #12]
|
|
8009448: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
|
|
800944a: 2200 movs r2, #0
|
|
800944c: 2100 movs r1, #0
|
|
800944e: 2014 movs r0, #20
|
|
8009450: f7f8 fb0f bl 8001a72 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
|
|
8009454: 2014 movs r0, #20
|
|
8009456: f7f8 fb28 bl 8001aaa <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_MspInit 1 */
|
|
|
|
/* USER CODE END USB_MspInit 1 */
|
|
}
|
|
}
|
|
800945a: bf00 nop
|
|
800945c: 3710 adds r7, #16
|
|
800945e: 46bd mov sp, r7
|
|
8009460: bd80 pop {r7, pc}
|
|
8009462: bf00 nop
|
|
8009464: 40005c00 .word 0x40005c00
|
|
8009468: 40021000 .word 0x40021000
|
|
|
|
0800946c <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800946c: b580 push {r7, lr}
|
|
800946e: b082 sub sp, #8
|
|
8009470: af00 add r7, sp, #0
|
|
8009472: 6078 str r0, [r7, #4]
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
8009474: 687b ldr r3, [r7, #4]
|
|
8009476: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800947a: 687b ldr r3, [r7, #4]
|
|
800947c: f503 7326 add.w r3, r3, #664 @ 0x298
|
|
8009480: 4619 mov r1, r3
|
|
8009482: 4610 mov r0, r2
|
|
8009484: f7fe fd51 bl 8007f2a <USBD_LL_SetupStage>
|
|
}
|
|
8009488: bf00 nop
|
|
800948a: 3708 adds r7, #8
|
|
800948c: 46bd mov sp, r7
|
|
800948e: bd80 pop {r7, pc}
|
|
|
|
08009490 <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009490: b580 push {r7, lr}
|
|
8009492: b082 sub sp, #8
|
|
8009494: af00 add r7, sp, #0
|
|
8009496: 6078 str r0, [r7, #4]
|
|
8009498: 460b mov r3, r1
|
|
800949a: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
800949c: 687b ldr r3, [r7, #4]
|
|
800949e: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
|
|
80094a2: 78fa ldrb r2, [r7, #3]
|
|
80094a4: 6879 ldr r1, [r7, #4]
|
|
80094a6: 4613 mov r3, r2
|
|
80094a8: 009b lsls r3, r3, #2
|
|
80094aa: 4413 add r3, r2
|
|
80094ac: 00db lsls r3, r3, #3
|
|
80094ae: 440b add r3, r1
|
|
80094b0: f503 73b2 add.w r3, r3, #356 @ 0x164
|
|
80094b4: 681a ldr r2, [r3, #0]
|
|
80094b6: 78fb ldrb r3, [r7, #3]
|
|
80094b8: 4619 mov r1, r3
|
|
80094ba: f7fe fd83 bl 8007fc4 <USBD_LL_DataOutStage>
|
|
}
|
|
80094be: bf00 nop
|
|
80094c0: 3708 adds r7, #8
|
|
80094c2: 46bd mov sp, r7
|
|
80094c4: bd80 pop {r7, pc}
|
|
|
|
080094c6 <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80094c6: b580 push {r7, lr}
|
|
80094c8: b082 sub sp, #8
|
|
80094ca: af00 add r7, sp, #0
|
|
80094cc: 6078 str r0, [r7, #4]
|
|
80094ce: 460b mov r3, r1
|
|
80094d0: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
80094d2: 687b ldr r3, [r7, #4]
|
|
80094d4: f8d3 02d4 ldr.w r0, [r3, #724] @ 0x2d4
|
|
80094d8: 78fa ldrb r2, [r7, #3]
|
|
80094da: 6879 ldr r1, [r7, #4]
|
|
80094dc: 4613 mov r3, r2
|
|
80094de: 009b lsls r3, r3, #2
|
|
80094e0: 4413 add r3, r2
|
|
80094e2: 00db lsls r3, r3, #3
|
|
80094e4: 440b add r3, r1
|
|
80094e6: 3324 adds r3, #36 @ 0x24
|
|
80094e8: 681a ldr r2, [r3, #0]
|
|
80094ea: 78fb ldrb r3, [r7, #3]
|
|
80094ec: 4619 mov r1, r3
|
|
80094ee: f7fe fdda bl 80080a6 <USBD_LL_DataInStage>
|
|
}
|
|
80094f2: bf00 nop
|
|
80094f4: 3708 adds r7, #8
|
|
80094f6: 46bd mov sp, r7
|
|
80094f8: bd80 pop {r7, pc}
|
|
|
|
080094fa <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80094fa: b580 push {r7, lr}
|
|
80094fc: b082 sub sp, #8
|
|
80094fe: af00 add r7, sp, #0
|
|
8009500: 6078 str r0, [r7, #4]
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009502: 687b ldr r3, [r7, #4]
|
|
8009504: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8009508: 4618 mov r0, r3
|
|
800950a: f7fe feea bl 80082e2 <USBD_LL_SOF>
|
|
}
|
|
800950e: bf00 nop
|
|
8009510: 3708 adds r7, #8
|
|
8009512: 46bd mov sp, r7
|
|
8009514: bd80 pop {r7, pc}
|
|
|
|
08009516 <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009516: b580 push {r7, lr}
|
|
8009518: b084 sub sp, #16
|
|
800951a: af00 add r7, sp, #0
|
|
800951c: 6078 str r0, [r7, #4]
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
800951e: 2301 movs r3, #1
|
|
8009520: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed != PCD_SPEED_FULL)
|
|
8009522: 687b ldr r3, [r7, #4]
|
|
8009524: 799b ldrb r3, [r3, #6]
|
|
8009526: 2b02 cmp r3, #2
|
|
8009528: d001 beq.n 800952e <HAL_PCD_ResetCallback+0x18>
|
|
{
|
|
Error_Handler();
|
|
800952a: f7f7 fb79 bl 8000c20 <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
800952e: 687b ldr r3, [r7, #4]
|
|
8009530: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8009534: 7bfa ldrb r2, [r7, #15]
|
|
8009536: 4611 mov r1, r2
|
|
8009538: 4618 mov r0, r3
|
|
800953a: f7fe fe9a bl 8008272 <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
800953e: 687b ldr r3, [r7, #4]
|
|
8009540: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8009544: 4618 mov r0, r3
|
|
8009546: f7fe fe53 bl 80081f0 <USBD_LL_Reset>
|
|
}
|
|
800954a: bf00 nop
|
|
800954c: 3710 adds r7, #16
|
|
800954e: 46bd mov sp, r7
|
|
8009550: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009554 <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009554: b580 push {r7, lr}
|
|
8009556: b082 sub sp, #8
|
|
8009558: af00 add r7, sp, #0
|
|
800955a: 6078 str r0, [r7, #4]
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
800955c: 687b ldr r3, [r7, #4]
|
|
800955e: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8009562: 4618 mov r0, r3
|
|
8009564: f7fe fe94 bl 8008290 <USBD_LL_Suspend>
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
8009568: 687b ldr r3, [r7, #4]
|
|
800956a: 7a9b ldrb r3, [r3, #10]
|
|
800956c: 2b00 cmp r3, #0
|
|
800956e: d005 beq.n 800957c <HAL_PCD_SuspendCallback+0x28>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
8009570: 4b04 ldr r3, [pc, #16] @ (8009584 <HAL_PCD_SuspendCallback+0x30>)
|
|
8009572: 691b ldr r3, [r3, #16]
|
|
8009574: 4a03 ldr r2, [pc, #12] @ (8009584 <HAL_PCD_SuspendCallback+0x30>)
|
|
8009576: f043 0306 orr.w r3, r3, #6
|
|
800957a: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
}
|
|
800957c: bf00 nop
|
|
800957e: 3708 adds r7, #8
|
|
8009580: 46bd mov sp, r7
|
|
8009582: bd80 pop {r7, pc}
|
|
8009584: e000ed00 .word 0xe000ed00
|
|
|
|
08009588 <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009588: b580 push {r7, lr}
|
|
800958a: b082 sub sp, #8
|
|
800958c: af00 add r7, sp, #0
|
|
800958e: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009590: 687b ldr r3, [r7, #4]
|
|
8009592: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8009596: 4618 mov r0, r3
|
|
8009598: f7fe fe8e bl 80082b8 <USBD_LL_Resume>
|
|
}
|
|
800959c: bf00 nop
|
|
800959e: 3708 adds r7, #8
|
|
80095a0: 46bd mov sp, r7
|
|
80095a2: bd80 pop {r7, pc}
|
|
|
|
080095a4 <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80095a4: b580 push {r7, lr}
|
|
80095a6: b082 sub sp, #8
|
|
80095a8: af00 add r7, sp, #0
|
|
80095aa: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
/* Link the driver to the stack. */
|
|
hpcd_USB_FS.pData = pdev;
|
|
80095ac: 4a28 ldr r2, [pc, #160] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095ae: 687b ldr r3, [r7, #4]
|
|
80095b0: f8c2 32d4 str.w r3, [r2, #724] @ 0x2d4
|
|
pdev->pData = &hpcd_USB_FS;
|
|
80095b4: 687b ldr r3, [r7, #4]
|
|
80095b6: 4a26 ldr r2, [pc, #152] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095b8: f8c3 22c0 str.w r2, [r3, #704] @ 0x2c0
|
|
|
|
hpcd_USB_FS.Instance = USB;
|
|
80095bc: 4b24 ldr r3, [pc, #144] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095be: 4a25 ldr r2, [pc, #148] @ (8009654 <USBD_LL_Init+0xb0>)
|
|
80095c0: 601a str r2, [r3, #0]
|
|
hpcd_USB_FS.Init.dev_endpoints = 8;
|
|
80095c2: 4b23 ldr r3, [pc, #140] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095c4: 2208 movs r2, #8
|
|
80095c6: 711a strb r2, [r3, #4]
|
|
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
|
|
80095c8: 4b21 ldr r3, [pc, #132] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095ca: 2202 movs r2, #2
|
|
80095cc: 719a strb r2, [r3, #6]
|
|
hpcd_USB_FS.Init.low_power_enable = DISABLE;
|
|
80095ce: 4b20 ldr r3, [pc, #128] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095d0: 2200 movs r2, #0
|
|
80095d2: 729a strb r2, [r3, #10]
|
|
hpcd_USB_FS.Init.lpm_enable = DISABLE;
|
|
80095d4: 4b1e ldr r3, [pc, #120] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095d6: 2200 movs r2, #0
|
|
80095d8: 72da strb r2, [r3, #11]
|
|
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
|
|
80095da: 4b1d ldr r3, [pc, #116] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095dc: 2200 movs r2, #0
|
|
80095de: 731a strb r2, [r3, #12]
|
|
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
|
|
80095e0: 481b ldr r0, [pc, #108] @ (8009650 <USBD_LL_Init+0xac>)
|
|
80095e2: f7f8 fc38 bl 8001e56 <HAL_PCD_Init>
|
|
80095e6: 4603 mov r3, r0
|
|
80095e8: 2b00 cmp r3, #0
|
|
80095ea: d001 beq.n 80095f0 <USBD_LL_Init+0x4c>
|
|
{
|
|
Error_Handler( );
|
|
80095ec: f7f7 fb18 bl 8000c20 <Error_Handler>
|
|
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
|
|
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
|
|
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
/* USER CODE BEGIN EndPoint_Configuration */
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
|
|
80095f0: 687b ldr r3, [r7, #4]
|
|
80095f2: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
80095f6: 2318 movs r3, #24
|
|
80095f8: 2200 movs r2, #0
|
|
80095fa: 2100 movs r1, #0
|
|
80095fc: f7fa f949 bl 8003892 <HAL_PCDEx_PMAConfig>
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
|
|
8009600: 687b ldr r3, [r7, #4]
|
|
8009602: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
8009606: 2358 movs r3, #88 @ 0x58
|
|
8009608: 2200 movs r2, #0
|
|
800960a: 2180 movs r1, #128 @ 0x80
|
|
800960c: f7fa f941 bl 8003892 <HAL_PCDEx_PMAConfig>
|
|
/* USER CODE END EndPoint_Configuration */
|
|
/* USER CODE BEGIN EndPoint_Configuration_CDC */
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
|
|
8009610: 687b ldr r3, [r7, #4]
|
|
8009612: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
8009616: 23c0 movs r3, #192 @ 0xc0
|
|
8009618: 2200 movs r2, #0
|
|
800961a: 2181 movs r1, #129 @ 0x81
|
|
800961c: f7fa f939 bl 8003892 <HAL_PCDEx_PMAConfig>
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
|
|
8009620: 687b ldr r3, [r7, #4]
|
|
8009622: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
8009626: f44f 7388 mov.w r3, #272 @ 0x110
|
|
800962a: 2200 movs r2, #0
|
|
800962c: 2101 movs r1, #1
|
|
800962e: f7fa f930 bl 8003892 <HAL_PCDEx_PMAConfig>
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
|
|
8009632: 687b ldr r3, [r7, #4]
|
|
8009634: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
8009638: f44f 7380 mov.w r3, #256 @ 0x100
|
|
800963c: 2200 movs r2, #0
|
|
800963e: 2182 movs r1, #130 @ 0x82
|
|
8009640: f7fa f927 bl 8003892 <HAL_PCDEx_PMAConfig>
|
|
/* USER CODE END EndPoint_Configuration_CDC */
|
|
return USBD_OK;
|
|
8009644: 2300 movs r3, #0
|
|
}
|
|
8009646: 4618 mov r0, r3
|
|
8009648: 3708 adds r7, #8
|
|
800964a: 46bd mov sp, r7
|
|
800964c: bd80 pop {r7, pc}
|
|
800964e: bf00 nop
|
|
8009650: 20001178 .word 0x20001178
|
|
8009654: 40005c00 .word 0x40005c00
|
|
|
|
08009658 <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009658: b580 push {r7, lr}
|
|
800965a: b084 sub sp, #16
|
|
800965c: af00 add r7, sp, #0
|
|
800965e: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009660: 2300 movs r3, #0
|
|
8009662: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009664: 2300 movs r3, #0
|
|
8009666: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
8009668: 687b ldr r3, [r7, #4]
|
|
800966a: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
800966e: 4618 mov r0, r3
|
|
8009670: f7f8 fce7 bl 8002042 <HAL_PCD_Start>
|
|
8009674: 4603 mov r3, r0
|
|
8009676: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009678: 7bfb ldrb r3, [r7, #15]
|
|
800967a: 4618 mov r0, r3
|
|
800967c: f000 f94e bl 800991c <USBD_Get_USB_Status>
|
|
8009680: 4603 mov r3, r0
|
|
8009682: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8009684: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009686: 4618 mov r0, r3
|
|
8009688: 3710 adds r7, #16
|
|
800968a: 46bd mov sp, r7
|
|
800968c: bd80 pop {r7, pc}
|
|
|
|
0800968e <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
800968e: b580 push {r7, lr}
|
|
8009690: b084 sub sp, #16
|
|
8009692: af00 add r7, sp, #0
|
|
8009694: 6078 str r0, [r7, #4]
|
|
8009696: 4608 mov r0, r1
|
|
8009698: 4611 mov r1, r2
|
|
800969a: 461a mov r2, r3
|
|
800969c: 4603 mov r3, r0
|
|
800969e: 70fb strb r3, [r7, #3]
|
|
80096a0: 460b mov r3, r1
|
|
80096a2: 70bb strb r3, [r7, #2]
|
|
80096a4: 4613 mov r3, r2
|
|
80096a6: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80096a8: 2300 movs r3, #0
|
|
80096aa: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80096ac: 2300 movs r3, #0
|
|
80096ae: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
80096b0: 687b ldr r3, [r7, #4]
|
|
80096b2: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
80096b6: 78bb ldrb r3, [r7, #2]
|
|
80096b8: 883a ldrh r2, [r7, #0]
|
|
80096ba: 78f9 ldrb r1, [r7, #3]
|
|
80096bc: f7f8 fe3b bl 8002336 <HAL_PCD_EP_Open>
|
|
80096c0: 4603 mov r3, r0
|
|
80096c2: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80096c4: 7bfb ldrb r3, [r7, #15]
|
|
80096c6: 4618 mov r0, r3
|
|
80096c8: f000 f928 bl 800991c <USBD_Get_USB_Status>
|
|
80096cc: 4603 mov r3, r0
|
|
80096ce: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80096d0: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80096d2: 4618 mov r0, r3
|
|
80096d4: 3710 adds r7, #16
|
|
80096d6: 46bd mov sp, r7
|
|
80096d8: bd80 pop {r7, pc}
|
|
|
|
080096da <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80096da: b580 push {r7, lr}
|
|
80096dc: b084 sub sp, #16
|
|
80096de: af00 add r7, sp, #0
|
|
80096e0: 6078 str r0, [r7, #4]
|
|
80096e2: 460b mov r3, r1
|
|
80096e4: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80096e6: 2300 movs r3, #0
|
|
80096e8: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80096ea: 2300 movs r3, #0
|
|
80096ec: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
80096ee: 687b ldr r3, [r7, #4]
|
|
80096f0: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
80096f4: 78fa ldrb r2, [r7, #3]
|
|
80096f6: 4611 mov r1, r2
|
|
80096f8: 4618 mov r0, r3
|
|
80096fa: f7f8 fe79 bl 80023f0 <HAL_PCD_EP_Close>
|
|
80096fe: 4603 mov r3, r0
|
|
8009700: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009702: 7bfb ldrb r3, [r7, #15]
|
|
8009704: 4618 mov r0, r3
|
|
8009706: f000 f909 bl 800991c <USBD_Get_USB_Status>
|
|
800970a: 4603 mov r3, r0
|
|
800970c: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800970e: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009710: 4618 mov r0, r3
|
|
8009712: 3710 adds r7, #16
|
|
8009714: 46bd mov sp, r7
|
|
8009716: bd80 pop {r7, pc}
|
|
|
|
08009718 <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8009718: b580 push {r7, lr}
|
|
800971a: b084 sub sp, #16
|
|
800971c: af00 add r7, sp, #0
|
|
800971e: 6078 str r0, [r7, #4]
|
|
8009720: 460b mov r3, r1
|
|
8009722: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009724: 2300 movs r3, #0
|
|
8009726: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009728: 2300 movs r3, #0
|
|
800972a: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
800972c: 687b ldr r3, [r7, #4]
|
|
800972e: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
8009732: 78fa ldrb r2, [r7, #3]
|
|
8009734: 4611 mov r1, r2
|
|
8009736: 4618 mov r0, r3
|
|
8009738: f7f8 ff21 bl 800257e <HAL_PCD_EP_SetStall>
|
|
800973c: 4603 mov r3, r0
|
|
800973e: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009740: 7bfb ldrb r3, [r7, #15]
|
|
8009742: 4618 mov r0, r3
|
|
8009744: f000 f8ea bl 800991c <USBD_Get_USB_Status>
|
|
8009748: 4603 mov r3, r0
|
|
800974a: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800974c: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800974e: 4618 mov r0, r3
|
|
8009750: 3710 adds r7, #16
|
|
8009752: 46bd mov sp, r7
|
|
8009754: bd80 pop {r7, pc}
|
|
|
|
08009756 <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8009756: b580 push {r7, lr}
|
|
8009758: b084 sub sp, #16
|
|
800975a: af00 add r7, sp, #0
|
|
800975c: 6078 str r0, [r7, #4]
|
|
800975e: 460b mov r3, r1
|
|
8009760: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009762: 2300 movs r3, #0
|
|
8009764: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009766: 2300 movs r3, #0
|
|
8009768: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
800976a: 687b ldr r3, [r7, #4]
|
|
800976c: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
8009770: 78fa ldrb r2, [r7, #3]
|
|
8009772: 4611 mov r1, r2
|
|
8009774: 4618 mov r0, r3
|
|
8009776: f7f8 ff62 bl 800263e <HAL_PCD_EP_ClrStall>
|
|
800977a: 4603 mov r3, r0
|
|
800977c: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800977e: 7bfb ldrb r3, [r7, #15]
|
|
8009780: 4618 mov r0, r3
|
|
8009782: f000 f8cb bl 800991c <USBD_Get_USB_Status>
|
|
8009786: 4603 mov r3, r0
|
|
8009788: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800978a: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800978c: 4618 mov r0, r3
|
|
800978e: 3710 adds r7, #16
|
|
8009790: 46bd mov sp, r7
|
|
8009792: bd80 pop {r7, pc}
|
|
|
|
08009794 <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8009794: b480 push {r7}
|
|
8009796: b085 sub sp, #20
|
|
8009798: af00 add r7, sp, #0
|
|
800979a: 6078 str r0, [r7, #4]
|
|
800979c: 460b mov r3, r1
|
|
800979e: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
80097a0: 687b ldr r3, [r7, #4]
|
|
80097a2: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
80097a6: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
80097a8: f997 3003 ldrsb.w r3, [r7, #3]
|
|
80097ac: 2b00 cmp r3, #0
|
|
80097ae: da0b bge.n 80097c8 <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
80097b0: 78fb ldrb r3, [r7, #3]
|
|
80097b2: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80097b6: 68f9 ldr r1, [r7, #12]
|
|
80097b8: 4613 mov r3, r2
|
|
80097ba: 009b lsls r3, r3, #2
|
|
80097bc: 4413 add r3, r2
|
|
80097be: 00db lsls r3, r3, #3
|
|
80097c0: 440b add r3, r1
|
|
80097c2: 3312 adds r3, #18
|
|
80097c4: 781b ldrb r3, [r3, #0]
|
|
80097c6: e00b b.n 80097e0 <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
80097c8: 78fb ldrb r3, [r7, #3]
|
|
80097ca: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80097ce: 68f9 ldr r1, [r7, #12]
|
|
80097d0: 4613 mov r3, r2
|
|
80097d2: 009b lsls r3, r3, #2
|
|
80097d4: 4413 add r3, r2
|
|
80097d6: 00db lsls r3, r3, #3
|
|
80097d8: 440b add r3, r1
|
|
80097da: f503 73a9 add.w r3, r3, #338 @ 0x152
|
|
80097de: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
80097e0: 4618 mov r0, r3
|
|
80097e2: 3714 adds r7, #20
|
|
80097e4: 46bd mov sp, r7
|
|
80097e6: bc80 pop {r7}
|
|
80097e8: 4770 bx lr
|
|
|
|
080097ea <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
80097ea: b580 push {r7, lr}
|
|
80097ec: b084 sub sp, #16
|
|
80097ee: af00 add r7, sp, #0
|
|
80097f0: 6078 str r0, [r7, #4]
|
|
80097f2: 460b mov r3, r1
|
|
80097f4: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80097f6: 2300 movs r3, #0
|
|
80097f8: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80097fa: 2300 movs r3, #0
|
|
80097fc: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
80097fe: 687b ldr r3, [r7, #4]
|
|
8009800: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
8009804: 78fa ldrb r2, [r7, #3]
|
|
8009806: 4611 mov r1, r2
|
|
8009808: 4618 mov r0, r3
|
|
800980a: f7f8 fd70 bl 80022ee <HAL_PCD_SetAddress>
|
|
800980e: 4603 mov r3, r0
|
|
8009810: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009812: 7bfb ldrb r3, [r7, #15]
|
|
8009814: 4618 mov r0, r3
|
|
8009816: f000 f881 bl 800991c <USBD_Get_USB_Status>
|
|
800981a: 4603 mov r3, r0
|
|
800981c: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800981e: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009820: 4618 mov r0, r3
|
|
8009822: 3710 adds r7, #16
|
|
8009824: 46bd mov sp, r7
|
|
8009826: bd80 pop {r7, pc}
|
|
|
|
08009828 <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
|
|
{
|
|
8009828: b580 push {r7, lr}
|
|
800982a: b086 sub sp, #24
|
|
800982c: af00 add r7, sp, #0
|
|
800982e: 60f8 str r0, [r7, #12]
|
|
8009830: 607a str r2, [r7, #4]
|
|
8009832: 461a mov r2, r3
|
|
8009834: 460b mov r3, r1
|
|
8009836: 72fb strb r3, [r7, #11]
|
|
8009838: 4613 mov r3, r2
|
|
800983a: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800983c: 2300 movs r3, #0
|
|
800983e: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009840: 2300 movs r3, #0
|
|
8009842: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
8009844: 68fb ldr r3, [r7, #12]
|
|
8009846: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
800984a: 893b ldrh r3, [r7, #8]
|
|
800984c: 7af9 ldrb r1, [r7, #11]
|
|
800984e: 687a ldr r2, [r7, #4]
|
|
8009850: f7f8 fe5e bl 8002510 <HAL_PCD_EP_Transmit>
|
|
8009854: 4603 mov r3, r0
|
|
8009856: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009858: 7dfb ldrb r3, [r7, #23]
|
|
800985a: 4618 mov r0, r3
|
|
800985c: f000 f85e bl 800991c <USBD_Get_USB_Status>
|
|
8009860: 4603 mov r3, r0
|
|
8009862: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
8009864: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
8009866: 4618 mov r0, r3
|
|
8009868: 3718 adds r7, #24
|
|
800986a: 46bd mov sp, r7
|
|
800986c: bd80 pop {r7, pc}
|
|
|
|
0800986e <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
|
|
{
|
|
800986e: b580 push {r7, lr}
|
|
8009870: b086 sub sp, #24
|
|
8009872: af00 add r7, sp, #0
|
|
8009874: 60f8 str r0, [r7, #12]
|
|
8009876: 607a str r2, [r7, #4]
|
|
8009878: 461a mov r2, r3
|
|
800987a: 460b mov r3, r1
|
|
800987c: 72fb strb r3, [r7, #11]
|
|
800987e: 4613 mov r3, r2
|
|
8009880: 813b strh r3, [r7, #8]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009882: 2300 movs r3, #0
|
|
8009884: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009886: 2300 movs r3, #0
|
|
8009888: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
800988a: 68fb ldr r3, [r7, #12]
|
|
800988c: f8d3 02c0 ldr.w r0, [r3, #704] @ 0x2c0
|
|
8009890: 893b ldrh r3, [r7, #8]
|
|
8009892: 7af9 ldrb r1, [r7, #11]
|
|
8009894: 687a ldr r2, [r7, #4]
|
|
8009896: f7f8 fdf3 bl 8002480 <HAL_PCD_EP_Receive>
|
|
800989a: 4603 mov r3, r0
|
|
800989c: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800989e: 7dfb ldrb r3, [r7, #23]
|
|
80098a0: 4618 mov r0, r3
|
|
80098a2: f000 f83b bl 800991c <USBD_Get_USB_Status>
|
|
80098a6: 4603 mov r3, r0
|
|
80098a8: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
80098aa: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
80098ac: 4618 mov r0, r3
|
|
80098ae: 3718 adds r7, #24
|
|
80098b0: 46bd mov sp, r7
|
|
80098b2: bd80 pop {r7, pc}
|
|
|
|
080098b4 <USBD_LL_GetRxDataSize>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Received Data Size
|
|
*/
|
|
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80098b4: b580 push {r7, lr}
|
|
80098b6: b082 sub sp, #8
|
|
80098b8: af00 add r7, sp, #0
|
|
80098ba: 6078 str r0, [r7, #4]
|
|
80098bc: 460b mov r3, r1
|
|
80098be: 70fb strb r3, [r7, #3]
|
|
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
|
|
80098c0: 687b ldr r3, [r7, #4]
|
|
80098c2: f8d3 32c0 ldr.w r3, [r3, #704] @ 0x2c0
|
|
80098c6: 78fa ldrb r2, [r7, #3]
|
|
80098c8: 4611 mov r1, r2
|
|
80098ca: 4618 mov r0, r3
|
|
80098cc: f7f8 fe09 bl 80024e2 <HAL_PCD_EP_GetRxCount>
|
|
80098d0: 4603 mov r3, r0
|
|
}
|
|
80098d2: 4618 mov r0, r3
|
|
80098d4: 3708 adds r7, #8
|
|
80098d6: 46bd mov sp, r7
|
|
80098d8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080098dc <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
80098dc: b480 push {r7}
|
|
80098de: b083 sub sp, #12
|
|
80098e0: af00 add r7, sp, #0
|
|
80098e2: 6078 str r0, [r7, #4]
|
|
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
80098e4: 4b02 ldr r3, [pc, #8] @ (80098f0 <USBD_static_malloc+0x14>)
|
|
}
|
|
80098e6: 4618 mov r0, r3
|
|
80098e8: 370c adds r7, #12
|
|
80098ea: 46bd mov sp, r7
|
|
80098ec: bc80 pop {r7}
|
|
80098ee: 4770 bx lr
|
|
80098f0: 20001450 .word 0x20001450
|
|
|
|
080098f4 <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
80098f4: b480 push {r7}
|
|
80098f6: b083 sub sp, #12
|
|
80098f8: af00 add r7, sp, #0
|
|
80098fa: 6078 str r0, [r7, #4]
|
|
|
|
}
|
|
80098fc: bf00 nop
|
|
80098fe: 370c adds r7, #12
|
|
8009900: 46bd mov sp, r7
|
|
8009902: bc80 pop {r7}
|
|
8009904: 4770 bx lr
|
|
|
|
08009906 <HAL_PCDEx_SetConnectionState>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
|
#else
|
|
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009906: b480 push {r7}
|
|
8009908: b083 sub sp, #12
|
|
800990a: af00 add r7, sp, #0
|
|
800990c: 6078 str r0, [r7, #4]
|
|
800990e: 460b mov r3, r1
|
|
8009910: 70fb strb r3, [r7, #3]
|
|
{
|
|
/* Configure High connection state. */
|
|
|
|
}
|
|
/* USER CODE END 6 */
|
|
}
|
|
8009912: bf00 nop
|
|
8009914: 370c adds r7, #12
|
|
8009916: 46bd mov sp, r7
|
|
8009918: bc80 pop {r7}
|
|
800991a: 4770 bx lr
|
|
|
|
0800991c <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
800991c: b480 push {r7}
|
|
800991e: b085 sub sp, #20
|
|
8009920: af00 add r7, sp, #0
|
|
8009922: 4603 mov r3, r0
|
|
8009924: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009926: 2300 movs r3, #0
|
|
8009928: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
800992a: 79fb ldrb r3, [r7, #7]
|
|
800992c: 2b03 cmp r3, #3
|
|
800992e: d817 bhi.n 8009960 <USBD_Get_USB_Status+0x44>
|
|
8009930: a201 add r2, pc, #4 @ (adr r2, 8009938 <USBD_Get_USB_Status+0x1c>)
|
|
8009932: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009936: bf00 nop
|
|
8009938: 08009949 .word 0x08009949
|
|
800993c: 0800994f .word 0x0800994f
|
|
8009940: 08009955 .word 0x08009955
|
|
8009944: 0800995b .word 0x0800995b
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
8009948: 2300 movs r3, #0
|
|
800994a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800994c: e00b b.n 8009966 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
800994e: 2302 movs r3, #2
|
|
8009950: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009952: e008 b.n 8009966 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
8009954: 2301 movs r3, #1
|
|
8009956: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009958: e005 b.n 8009966 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
800995a: 2302 movs r3, #2
|
|
800995c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800995e: e002 b.n 8009966 <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
8009960: 2302 movs r3, #2
|
|
8009962: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009964: bf00 nop
|
|
}
|
|
return usb_status;
|
|
8009966: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009968: 4618 mov r0, r3
|
|
800996a: 3714 adds r7, #20
|
|
800996c: 46bd mov sp, r7
|
|
800996e: bc80 pop {r7}
|
|
8009970: 4770 bx lr
|
|
8009972: bf00 nop
|
|
|
|
08009974 <siprintf>:
|
|
8009974: b40e push {r1, r2, r3}
|
|
8009976: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
|
|
800997a: b510 push {r4, lr}
|
|
800997c: 2400 movs r4, #0
|
|
800997e: b09d sub sp, #116 @ 0x74
|
|
8009980: ab1f add r3, sp, #124 @ 0x7c
|
|
8009982: 9002 str r0, [sp, #8]
|
|
8009984: 9006 str r0, [sp, #24]
|
|
8009986: 9107 str r1, [sp, #28]
|
|
8009988: 9104 str r1, [sp, #16]
|
|
800998a: 4809 ldr r0, [pc, #36] @ (80099b0 <siprintf+0x3c>)
|
|
800998c: 4909 ldr r1, [pc, #36] @ (80099b4 <siprintf+0x40>)
|
|
800998e: f853 2b04 ldr.w r2, [r3], #4
|
|
8009992: 9105 str r1, [sp, #20]
|
|
8009994: 6800 ldr r0, [r0, #0]
|
|
8009996: a902 add r1, sp, #8
|
|
8009998: 9301 str r3, [sp, #4]
|
|
800999a: 941b str r4, [sp, #108] @ 0x6c
|
|
800999c: f000 f992 bl 8009cc4 <_svfiprintf_r>
|
|
80099a0: 9b02 ldr r3, [sp, #8]
|
|
80099a2: 701c strb r4, [r3, #0]
|
|
80099a4: b01d add sp, #116 @ 0x74
|
|
80099a6: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
80099aa: b003 add sp, #12
|
|
80099ac: 4770 bx lr
|
|
80099ae: bf00 nop
|
|
80099b0: 2000017c .word 0x2000017c
|
|
80099b4: ffff0208 .word 0xffff0208
|
|
|
|
080099b8 <memset>:
|
|
80099b8: 4603 mov r3, r0
|
|
80099ba: 4402 add r2, r0
|
|
80099bc: 4293 cmp r3, r2
|
|
80099be: d100 bne.n 80099c2 <memset+0xa>
|
|
80099c0: 4770 bx lr
|
|
80099c2: f803 1b01 strb.w r1, [r3], #1
|
|
80099c6: e7f9 b.n 80099bc <memset+0x4>
|
|
|
|
080099c8 <__errno>:
|
|
80099c8: 4b01 ldr r3, [pc, #4] @ (80099d0 <__errno+0x8>)
|
|
80099ca: 6818 ldr r0, [r3, #0]
|
|
80099cc: 4770 bx lr
|
|
80099ce: bf00 nop
|
|
80099d0: 2000017c .word 0x2000017c
|
|
|
|
080099d4 <__libc_init_array>:
|
|
80099d4: b570 push {r4, r5, r6, lr}
|
|
80099d6: 2600 movs r6, #0
|
|
80099d8: 4d0c ldr r5, [pc, #48] @ (8009a0c <__libc_init_array+0x38>)
|
|
80099da: 4c0d ldr r4, [pc, #52] @ (8009a10 <__libc_init_array+0x3c>)
|
|
80099dc: 1b64 subs r4, r4, r5
|
|
80099de: 10a4 asrs r4, r4, #2
|
|
80099e0: 42a6 cmp r6, r4
|
|
80099e2: d109 bne.n 80099f8 <__libc_init_array+0x24>
|
|
80099e4: f000 fc76 bl 800a2d4 <_init>
|
|
80099e8: 2600 movs r6, #0
|
|
80099ea: 4d0a ldr r5, [pc, #40] @ (8009a14 <__libc_init_array+0x40>)
|
|
80099ec: 4c0a ldr r4, [pc, #40] @ (8009a18 <__libc_init_array+0x44>)
|
|
80099ee: 1b64 subs r4, r4, r5
|
|
80099f0: 10a4 asrs r4, r4, #2
|
|
80099f2: 42a6 cmp r6, r4
|
|
80099f4: d105 bne.n 8009a02 <__libc_init_array+0x2e>
|
|
80099f6: bd70 pop {r4, r5, r6, pc}
|
|
80099f8: f855 3b04 ldr.w r3, [r5], #4
|
|
80099fc: 4798 blx r3
|
|
80099fe: 3601 adds r6, #1
|
|
8009a00: e7ee b.n 80099e0 <__libc_init_array+0xc>
|
|
8009a02: f855 3b04 ldr.w r3, [r5], #4
|
|
8009a06: 4798 blx r3
|
|
8009a08: 3601 adds r6, #1
|
|
8009a0a: e7f2 b.n 80099f2 <__libc_init_array+0x1e>
|
|
8009a0c: 0800a450 .word 0x0800a450
|
|
8009a10: 0800a450 .word 0x0800a450
|
|
8009a14: 0800a450 .word 0x0800a450
|
|
8009a18: 0800a454 .word 0x0800a454
|
|
|
|
08009a1c <__retarget_lock_acquire_recursive>:
|
|
8009a1c: 4770 bx lr
|
|
|
|
08009a1e <__retarget_lock_release_recursive>:
|
|
8009a1e: 4770 bx lr
|
|
|
|
08009a20 <_free_r>:
|
|
8009a20: b538 push {r3, r4, r5, lr}
|
|
8009a22: 4605 mov r5, r0
|
|
8009a24: 2900 cmp r1, #0
|
|
8009a26: d040 beq.n 8009aaa <_free_r+0x8a>
|
|
8009a28: f851 3c04 ldr.w r3, [r1, #-4]
|
|
8009a2c: 1f0c subs r4, r1, #4
|
|
8009a2e: 2b00 cmp r3, #0
|
|
8009a30: bfb8 it lt
|
|
8009a32: 18e4 addlt r4, r4, r3
|
|
8009a34: f000 f8de bl 8009bf4 <__malloc_lock>
|
|
8009a38: 4a1c ldr r2, [pc, #112] @ (8009aac <_free_r+0x8c>)
|
|
8009a3a: 6813 ldr r3, [r2, #0]
|
|
8009a3c: b933 cbnz r3, 8009a4c <_free_r+0x2c>
|
|
8009a3e: 6063 str r3, [r4, #4]
|
|
8009a40: 6014 str r4, [r2, #0]
|
|
8009a42: 4628 mov r0, r5
|
|
8009a44: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8009a48: f000 b8da b.w 8009c00 <__malloc_unlock>
|
|
8009a4c: 42a3 cmp r3, r4
|
|
8009a4e: d908 bls.n 8009a62 <_free_r+0x42>
|
|
8009a50: 6820 ldr r0, [r4, #0]
|
|
8009a52: 1821 adds r1, r4, r0
|
|
8009a54: 428b cmp r3, r1
|
|
8009a56: bf01 itttt eq
|
|
8009a58: 6819 ldreq r1, [r3, #0]
|
|
8009a5a: 685b ldreq r3, [r3, #4]
|
|
8009a5c: 1809 addeq r1, r1, r0
|
|
8009a5e: 6021 streq r1, [r4, #0]
|
|
8009a60: e7ed b.n 8009a3e <_free_r+0x1e>
|
|
8009a62: 461a mov r2, r3
|
|
8009a64: 685b ldr r3, [r3, #4]
|
|
8009a66: b10b cbz r3, 8009a6c <_free_r+0x4c>
|
|
8009a68: 42a3 cmp r3, r4
|
|
8009a6a: d9fa bls.n 8009a62 <_free_r+0x42>
|
|
8009a6c: 6811 ldr r1, [r2, #0]
|
|
8009a6e: 1850 adds r0, r2, r1
|
|
8009a70: 42a0 cmp r0, r4
|
|
8009a72: d10b bne.n 8009a8c <_free_r+0x6c>
|
|
8009a74: 6820 ldr r0, [r4, #0]
|
|
8009a76: 4401 add r1, r0
|
|
8009a78: 1850 adds r0, r2, r1
|
|
8009a7a: 4283 cmp r3, r0
|
|
8009a7c: 6011 str r1, [r2, #0]
|
|
8009a7e: d1e0 bne.n 8009a42 <_free_r+0x22>
|
|
8009a80: 6818 ldr r0, [r3, #0]
|
|
8009a82: 685b ldr r3, [r3, #4]
|
|
8009a84: 4408 add r0, r1
|
|
8009a86: 6010 str r0, [r2, #0]
|
|
8009a88: 6053 str r3, [r2, #4]
|
|
8009a8a: e7da b.n 8009a42 <_free_r+0x22>
|
|
8009a8c: d902 bls.n 8009a94 <_free_r+0x74>
|
|
8009a8e: 230c movs r3, #12
|
|
8009a90: 602b str r3, [r5, #0]
|
|
8009a92: e7d6 b.n 8009a42 <_free_r+0x22>
|
|
8009a94: 6820 ldr r0, [r4, #0]
|
|
8009a96: 1821 adds r1, r4, r0
|
|
8009a98: 428b cmp r3, r1
|
|
8009a9a: bf01 itttt eq
|
|
8009a9c: 6819 ldreq r1, [r3, #0]
|
|
8009a9e: 685b ldreq r3, [r3, #4]
|
|
8009aa0: 1809 addeq r1, r1, r0
|
|
8009aa2: 6021 streq r1, [r4, #0]
|
|
8009aa4: 6063 str r3, [r4, #4]
|
|
8009aa6: 6054 str r4, [r2, #4]
|
|
8009aa8: e7cb b.n 8009a42 <_free_r+0x22>
|
|
8009aaa: bd38 pop {r3, r4, r5, pc}
|
|
8009aac: 200017b4 .word 0x200017b4
|
|
|
|
08009ab0 <sbrk_aligned>:
|
|
8009ab0: b570 push {r4, r5, r6, lr}
|
|
8009ab2: 4e0f ldr r6, [pc, #60] @ (8009af0 <sbrk_aligned+0x40>)
|
|
8009ab4: 460c mov r4, r1
|
|
8009ab6: 6831 ldr r1, [r6, #0]
|
|
8009ab8: 4605 mov r5, r0
|
|
8009aba: b911 cbnz r1, 8009ac2 <sbrk_aligned+0x12>
|
|
8009abc: f000 fba8 bl 800a210 <_sbrk_r>
|
|
8009ac0: 6030 str r0, [r6, #0]
|
|
8009ac2: 4621 mov r1, r4
|
|
8009ac4: 4628 mov r0, r5
|
|
8009ac6: f000 fba3 bl 800a210 <_sbrk_r>
|
|
8009aca: 1c43 adds r3, r0, #1
|
|
8009acc: d103 bne.n 8009ad6 <sbrk_aligned+0x26>
|
|
8009ace: f04f 34ff mov.w r4, #4294967295
|
|
8009ad2: 4620 mov r0, r4
|
|
8009ad4: bd70 pop {r4, r5, r6, pc}
|
|
8009ad6: 1cc4 adds r4, r0, #3
|
|
8009ad8: f024 0403 bic.w r4, r4, #3
|
|
8009adc: 42a0 cmp r0, r4
|
|
8009ade: d0f8 beq.n 8009ad2 <sbrk_aligned+0x22>
|
|
8009ae0: 1a21 subs r1, r4, r0
|
|
8009ae2: 4628 mov r0, r5
|
|
8009ae4: f000 fb94 bl 800a210 <_sbrk_r>
|
|
8009ae8: 3001 adds r0, #1
|
|
8009aea: d1f2 bne.n 8009ad2 <sbrk_aligned+0x22>
|
|
8009aec: e7ef b.n 8009ace <sbrk_aligned+0x1e>
|
|
8009aee: bf00 nop
|
|
8009af0: 200017b0 .word 0x200017b0
|
|
|
|
08009af4 <_malloc_r>:
|
|
8009af4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8009af8: 1ccd adds r5, r1, #3
|
|
8009afa: f025 0503 bic.w r5, r5, #3
|
|
8009afe: 3508 adds r5, #8
|
|
8009b00: 2d0c cmp r5, #12
|
|
8009b02: bf38 it cc
|
|
8009b04: 250c movcc r5, #12
|
|
8009b06: 2d00 cmp r5, #0
|
|
8009b08: 4606 mov r6, r0
|
|
8009b0a: db01 blt.n 8009b10 <_malloc_r+0x1c>
|
|
8009b0c: 42a9 cmp r1, r5
|
|
8009b0e: d904 bls.n 8009b1a <_malloc_r+0x26>
|
|
8009b10: 230c movs r3, #12
|
|
8009b12: 6033 str r3, [r6, #0]
|
|
8009b14: 2000 movs r0, #0
|
|
8009b16: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8009b1a: f8df 80d4 ldr.w r8, [pc, #212] @ 8009bf0 <_malloc_r+0xfc>
|
|
8009b1e: f000 f869 bl 8009bf4 <__malloc_lock>
|
|
8009b22: f8d8 3000 ldr.w r3, [r8]
|
|
8009b26: 461c mov r4, r3
|
|
8009b28: bb44 cbnz r4, 8009b7c <_malloc_r+0x88>
|
|
8009b2a: 4629 mov r1, r5
|
|
8009b2c: 4630 mov r0, r6
|
|
8009b2e: f7ff ffbf bl 8009ab0 <sbrk_aligned>
|
|
8009b32: 1c43 adds r3, r0, #1
|
|
8009b34: 4604 mov r4, r0
|
|
8009b36: d158 bne.n 8009bea <_malloc_r+0xf6>
|
|
8009b38: f8d8 4000 ldr.w r4, [r8]
|
|
8009b3c: 4627 mov r7, r4
|
|
8009b3e: 2f00 cmp r7, #0
|
|
8009b40: d143 bne.n 8009bca <_malloc_r+0xd6>
|
|
8009b42: 2c00 cmp r4, #0
|
|
8009b44: d04b beq.n 8009bde <_malloc_r+0xea>
|
|
8009b46: 6823 ldr r3, [r4, #0]
|
|
8009b48: 4639 mov r1, r7
|
|
8009b4a: 4630 mov r0, r6
|
|
8009b4c: eb04 0903 add.w r9, r4, r3
|
|
8009b50: f000 fb5e bl 800a210 <_sbrk_r>
|
|
8009b54: 4581 cmp r9, r0
|
|
8009b56: d142 bne.n 8009bde <_malloc_r+0xea>
|
|
8009b58: 6821 ldr r1, [r4, #0]
|
|
8009b5a: 4630 mov r0, r6
|
|
8009b5c: 1a6d subs r5, r5, r1
|
|
8009b5e: 4629 mov r1, r5
|
|
8009b60: f7ff ffa6 bl 8009ab0 <sbrk_aligned>
|
|
8009b64: 3001 adds r0, #1
|
|
8009b66: d03a beq.n 8009bde <_malloc_r+0xea>
|
|
8009b68: 6823 ldr r3, [r4, #0]
|
|
8009b6a: 442b add r3, r5
|
|
8009b6c: 6023 str r3, [r4, #0]
|
|
8009b6e: f8d8 3000 ldr.w r3, [r8]
|
|
8009b72: 685a ldr r2, [r3, #4]
|
|
8009b74: bb62 cbnz r2, 8009bd0 <_malloc_r+0xdc>
|
|
8009b76: f8c8 7000 str.w r7, [r8]
|
|
8009b7a: e00f b.n 8009b9c <_malloc_r+0xa8>
|
|
8009b7c: 6822 ldr r2, [r4, #0]
|
|
8009b7e: 1b52 subs r2, r2, r5
|
|
8009b80: d420 bmi.n 8009bc4 <_malloc_r+0xd0>
|
|
8009b82: 2a0b cmp r2, #11
|
|
8009b84: d917 bls.n 8009bb6 <_malloc_r+0xc2>
|
|
8009b86: 1961 adds r1, r4, r5
|
|
8009b88: 42a3 cmp r3, r4
|
|
8009b8a: 6025 str r5, [r4, #0]
|
|
8009b8c: bf18 it ne
|
|
8009b8e: 6059 strne r1, [r3, #4]
|
|
8009b90: 6863 ldr r3, [r4, #4]
|
|
8009b92: bf08 it eq
|
|
8009b94: f8c8 1000 streq.w r1, [r8]
|
|
8009b98: 5162 str r2, [r4, r5]
|
|
8009b9a: 604b str r3, [r1, #4]
|
|
8009b9c: 4630 mov r0, r6
|
|
8009b9e: f000 f82f bl 8009c00 <__malloc_unlock>
|
|
8009ba2: f104 000b add.w r0, r4, #11
|
|
8009ba6: 1d23 adds r3, r4, #4
|
|
8009ba8: f020 0007 bic.w r0, r0, #7
|
|
8009bac: 1ac2 subs r2, r0, r3
|
|
8009bae: bf1c itt ne
|
|
8009bb0: 1a1b subne r3, r3, r0
|
|
8009bb2: 50a3 strne r3, [r4, r2]
|
|
8009bb4: e7af b.n 8009b16 <_malloc_r+0x22>
|
|
8009bb6: 6862 ldr r2, [r4, #4]
|
|
8009bb8: 42a3 cmp r3, r4
|
|
8009bba: bf0c ite eq
|
|
8009bbc: f8c8 2000 streq.w r2, [r8]
|
|
8009bc0: 605a strne r2, [r3, #4]
|
|
8009bc2: e7eb b.n 8009b9c <_malloc_r+0xa8>
|
|
8009bc4: 4623 mov r3, r4
|
|
8009bc6: 6864 ldr r4, [r4, #4]
|
|
8009bc8: e7ae b.n 8009b28 <_malloc_r+0x34>
|
|
8009bca: 463c mov r4, r7
|
|
8009bcc: 687f ldr r7, [r7, #4]
|
|
8009bce: e7b6 b.n 8009b3e <_malloc_r+0x4a>
|
|
8009bd0: 461a mov r2, r3
|
|
8009bd2: 685b ldr r3, [r3, #4]
|
|
8009bd4: 42a3 cmp r3, r4
|
|
8009bd6: d1fb bne.n 8009bd0 <_malloc_r+0xdc>
|
|
8009bd8: 2300 movs r3, #0
|
|
8009bda: 6053 str r3, [r2, #4]
|
|
8009bdc: e7de b.n 8009b9c <_malloc_r+0xa8>
|
|
8009bde: 230c movs r3, #12
|
|
8009be0: 4630 mov r0, r6
|
|
8009be2: 6033 str r3, [r6, #0]
|
|
8009be4: f000 f80c bl 8009c00 <__malloc_unlock>
|
|
8009be8: e794 b.n 8009b14 <_malloc_r+0x20>
|
|
8009bea: 6005 str r5, [r0, #0]
|
|
8009bec: e7d6 b.n 8009b9c <_malloc_r+0xa8>
|
|
8009bee: bf00 nop
|
|
8009bf0: 200017b4 .word 0x200017b4
|
|
|
|
08009bf4 <__malloc_lock>:
|
|
8009bf4: 4801 ldr r0, [pc, #4] @ (8009bfc <__malloc_lock+0x8>)
|
|
8009bf6: f7ff bf11 b.w 8009a1c <__retarget_lock_acquire_recursive>
|
|
8009bfa: bf00 nop
|
|
8009bfc: 200017ac .word 0x200017ac
|
|
|
|
08009c00 <__malloc_unlock>:
|
|
8009c00: 4801 ldr r0, [pc, #4] @ (8009c08 <__malloc_unlock+0x8>)
|
|
8009c02: f7ff bf0c b.w 8009a1e <__retarget_lock_release_recursive>
|
|
8009c06: bf00 nop
|
|
8009c08: 200017ac .word 0x200017ac
|
|
|
|
08009c0c <__ssputs_r>:
|
|
8009c0c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8009c10: 461f mov r7, r3
|
|
8009c12: 688e ldr r6, [r1, #8]
|
|
8009c14: 4682 mov sl, r0
|
|
8009c16: 42be cmp r6, r7
|
|
8009c18: 460c mov r4, r1
|
|
8009c1a: 4690 mov r8, r2
|
|
8009c1c: 680b ldr r3, [r1, #0]
|
|
8009c1e: d82d bhi.n 8009c7c <__ssputs_r+0x70>
|
|
8009c20: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
8009c24: f412 6f90 tst.w r2, #1152 @ 0x480
|
|
8009c28: d026 beq.n 8009c78 <__ssputs_r+0x6c>
|
|
8009c2a: 6965 ldr r5, [r4, #20]
|
|
8009c2c: 6909 ldr r1, [r1, #16]
|
|
8009c2e: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
8009c32: eba3 0901 sub.w r9, r3, r1
|
|
8009c36: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
8009c3a: 1c7b adds r3, r7, #1
|
|
8009c3c: 444b add r3, r9
|
|
8009c3e: 106d asrs r5, r5, #1
|
|
8009c40: 429d cmp r5, r3
|
|
8009c42: bf38 it cc
|
|
8009c44: 461d movcc r5, r3
|
|
8009c46: 0553 lsls r3, r2, #21
|
|
8009c48: d527 bpl.n 8009c9a <__ssputs_r+0x8e>
|
|
8009c4a: 4629 mov r1, r5
|
|
8009c4c: f7ff ff52 bl 8009af4 <_malloc_r>
|
|
8009c50: 4606 mov r6, r0
|
|
8009c52: b360 cbz r0, 8009cae <__ssputs_r+0xa2>
|
|
8009c54: 464a mov r2, r9
|
|
8009c56: 6921 ldr r1, [r4, #16]
|
|
8009c58: f000 faf8 bl 800a24c <memcpy>
|
|
8009c5c: 89a3 ldrh r3, [r4, #12]
|
|
8009c5e: f423 6390 bic.w r3, r3, #1152 @ 0x480
|
|
8009c62: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8009c66: 81a3 strh r3, [r4, #12]
|
|
8009c68: 6126 str r6, [r4, #16]
|
|
8009c6a: 444e add r6, r9
|
|
8009c6c: 6026 str r6, [r4, #0]
|
|
8009c6e: 463e mov r6, r7
|
|
8009c70: 6165 str r5, [r4, #20]
|
|
8009c72: eba5 0509 sub.w r5, r5, r9
|
|
8009c76: 60a5 str r5, [r4, #8]
|
|
8009c78: 42be cmp r6, r7
|
|
8009c7a: d900 bls.n 8009c7e <__ssputs_r+0x72>
|
|
8009c7c: 463e mov r6, r7
|
|
8009c7e: 4632 mov r2, r6
|
|
8009c80: 4641 mov r1, r8
|
|
8009c82: 6820 ldr r0, [r4, #0]
|
|
8009c84: f000 faaa bl 800a1dc <memmove>
|
|
8009c88: 2000 movs r0, #0
|
|
8009c8a: 68a3 ldr r3, [r4, #8]
|
|
8009c8c: 1b9b subs r3, r3, r6
|
|
8009c8e: 60a3 str r3, [r4, #8]
|
|
8009c90: 6823 ldr r3, [r4, #0]
|
|
8009c92: 4433 add r3, r6
|
|
8009c94: 6023 str r3, [r4, #0]
|
|
8009c96: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8009c9a: 462a mov r2, r5
|
|
8009c9c: f000 fae4 bl 800a268 <_realloc_r>
|
|
8009ca0: 4606 mov r6, r0
|
|
8009ca2: 2800 cmp r0, #0
|
|
8009ca4: d1e0 bne.n 8009c68 <__ssputs_r+0x5c>
|
|
8009ca6: 4650 mov r0, sl
|
|
8009ca8: 6921 ldr r1, [r4, #16]
|
|
8009caa: f7ff feb9 bl 8009a20 <_free_r>
|
|
8009cae: 230c movs r3, #12
|
|
8009cb0: f8ca 3000 str.w r3, [sl]
|
|
8009cb4: 89a3 ldrh r3, [r4, #12]
|
|
8009cb6: f04f 30ff mov.w r0, #4294967295
|
|
8009cba: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009cbe: 81a3 strh r3, [r4, #12]
|
|
8009cc0: e7e9 b.n 8009c96 <__ssputs_r+0x8a>
|
|
...
|
|
|
|
08009cc4 <_svfiprintf_r>:
|
|
8009cc4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8009cc8: 4698 mov r8, r3
|
|
8009cca: 898b ldrh r3, [r1, #12]
|
|
8009ccc: 4607 mov r7, r0
|
|
8009cce: 061b lsls r3, r3, #24
|
|
8009cd0: 460d mov r5, r1
|
|
8009cd2: 4614 mov r4, r2
|
|
8009cd4: b09d sub sp, #116 @ 0x74
|
|
8009cd6: d510 bpl.n 8009cfa <_svfiprintf_r+0x36>
|
|
8009cd8: 690b ldr r3, [r1, #16]
|
|
8009cda: b973 cbnz r3, 8009cfa <_svfiprintf_r+0x36>
|
|
8009cdc: 2140 movs r1, #64 @ 0x40
|
|
8009cde: f7ff ff09 bl 8009af4 <_malloc_r>
|
|
8009ce2: 6028 str r0, [r5, #0]
|
|
8009ce4: 6128 str r0, [r5, #16]
|
|
8009ce6: b930 cbnz r0, 8009cf6 <_svfiprintf_r+0x32>
|
|
8009ce8: 230c movs r3, #12
|
|
8009cea: 603b str r3, [r7, #0]
|
|
8009cec: f04f 30ff mov.w r0, #4294967295
|
|
8009cf0: b01d add sp, #116 @ 0x74
|
|
8009cf2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8009cf6: 2340 movs r3, #64 @ 0x40
|
|
8009cf8: 616b str r3, [r5, #20]
|
|
8009cfa: 2300 movs r3, #0
|
|
8009cfc: 9309 str r3, [sp, #36] @ 0x24
|
|
8009cfe: 2320 movs r3, #32
|
|
8009d00: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
8009d04: 2330 movs r3, #48 @ 0x30
|
|
8009d06: f04f 0901 mov.w r9, #1
|
|
8009d0a: f8cd 800c str.w r8, [sp, #12]
|
|
8009d0e: f8df 8198 ldr.w r8, [pc, #408] @ 8009ea8 <_svfiprintf_r+0x1e4>
|
|
8009d12: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
8009d16: 4623 mov r3, r4
|
|
8009d18: 469a mov sl, r3
|
|
8009d1a: f813 2b01 ldrb.w r2, [r3], #1
|
|
8009d1e: b10a cbz r2, 8009d24 <_svfiprintf_r+0x60>
|
|
8009d20: 2a25 cmp r2, #37 @ 0x25
|
|
8009d22: d1f9 bne.n 8009d18 <_svfiprintf_r+0x54>
|
|
8009d24: ebba 0b04 subs.w fp, sl, r4
|
|
8009d28: d00b beq.n 8009d42 <_svfiprintf_r+0x7e>
|
|
8009d2a: 465b mov r3, fp
|
|
8009d2c: 4622 mov r2, r4
|
|
8009d2e: 4629 mov r1, r5
|
|
8009d30: 4638 mov r0, r7
|
|
8009d32: f7ff ff6b bl 8009c0c <__ssputs_r>
|
|
8009d36: 3001 adds r0, #1
|
|
8009d38: f000 80a7 beq.w 8009e8a <_svfiprintf_r+0x1c6>
|
|
8009d3c: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8009d3e: 445a add r2, fp
|
|
8009d40: 9209 str r2, [sp, #36] @ 0x24
|
|
8009d42: f89a 3000 ldrb.w r3, [sl]
|
|
8009d46: 2b00 cmp r3, #0
|
|
8009d48: f000 809f beq.w 8009e8a <_svfiprintf_r+0x1c6>
|
|
8009d4c: 2300 movs r3, #0
|
|
8009d4e: f04f 32ff mov.w r2, #4294967295
|
|
8009d52: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8009d56: f10a 0a01 add.w sl, sl, #1
|
|
8009d5a: 9304 str r3, [sp, #16]
|
|
8009d5c: 9307 str r3, [sp, #28]
|
|
8009d5e: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
8009d62: 931a str r3, [sp, #104] @ 0x68
|
|
8009d64: 4654 mov r4, sl
|
|
8009d66: 2205 movs r2, #5
|
|
8009d68: f814 1b01 ldrb.w r1, [r4], #1
|
|
8009d6c: 484e ldr r0, [pc, #312] @ (8009ea8 <_svfiprintf_r+0x1e4>)
|
|
8009d6e: f000 fa5f bl 800a230 <memchr>
|
|
8009d72: 9a04 ldr r2, [sp, #16]
|
|
8009d74: b9d8 cbnz r0, 8009dae <_svfiprintf_r+0xea>
|
|
8009d76: 06d0 lsls r0, r2, #27
|
|
8009d78: bf44 itt mi
|
|
8009d7a: 2320 movmi r3, #32
|
|
8009d7c: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8009d80: 0711 lsls r1, r2, #28
|
|
8009d82: bf44 itt mi
|
|
8009d84: 232b movmi r3, #43 @ 0x2b
|
|
8009d86: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8009d8a: f89a 3000 ldrb.w r3, [sl]
|
|
8009d8e: 2b2a cmp r3, #42 @ 0x2a
|
|
8009d90: d015 beq.n 8009dbe <_svfiprintf_r+0xfa>
|
|
8009d92: 4654 mov r4, sl
|
|
8009d94: 2000 movs r0, #0
|
|
8009d96: f04f 0c0a mov.w ip, #10
|
|
8009d9a: 9a07 ldr r2, [sp, #28]
|
|
8009d9c: 4621 mov r1, r4
|
|
8009d9e: f811 3b01 ldrb.w r3, [r1], #1
|
|
8009da2: 3b30 subs r3, #48 @ 0x30
|
|
8009da4: 2b09 cmp r3, #9
|
|
8009da6: d94b bls.n 8009e40 <_svfiprintf_r+0x17c>
|
|
8009da8: b1b0 cbz r0, 8009dd8 <_svfiprintf_r+0x114>
|
|
8009daa: 9207 str r2, [sp, #28]
|
|
8009dac: e014 b.n 8009dd8 <_svfiprintf_r+0x114>
|
|
8009dae: eba0 0308 sub.w r3, r0, r8
|
|
8009db2: fa09 f303 lsl.w r3, r9, r3
|
|
8009db6: 4313 orrs r3, r2
|
|
8009db8: 46a2 mov sl, r4
|
|
8009dba: 9304 str r3, [sp, #16]
|
|
8009dbc: e7d2 b.n 8009d64 <_svfiprintf_r+0xa0>
|
|
8009dbe: 9b03 ldr r3, [sp, #12]
|
|
8009dc0: 1d19 adds r1, r3, #4
|
|
8009dc2: 681b ldr r3, [r3, #0]
|
|
8009dc4: 9103 str r1, [sp, #12]
|
|
8009dc6: 2b00 cmp r3, #0
|
|
8009dc8: bfbb ittet lt
|
|
8009dca: 425b neglt r3, r3
|
|
8009dcc: f042 0202 orrlt.w r2, r2, #2
|
|
8009dd0: 9307 strge r3, [sp, #28]
|
|
8009dd2: 9307 strlt r3, [sp, #28]
|
|
8009dd4: bfb8 it lt
|
|
8009dd6: 9204 strlt r2, [sp, #16]
|
|
8009dd8: 7823 ldrb r3, [r4, #0]
|
|
8009dda: 2b2e cmp r3, #46 @ 0x2e
|
|
8009ddc: d10a bne.n 8009df4 <_svfiprintf_r+0x130>
|
|
8009dde: 7863 ldrb r3, [r4, #1]
|
|
8009de0: 2b2a cmp r3, #42 @ 0x2a
|
|
8009de2: d132 bne.n 8009e4a <_svfiprintf_r+0x186>
|
|
8009de4: 9b03 ldr r3, [sp, #12]
|
|
8009de6: 3402 adds r4, #2
|
|
8009de8: 1d1a adds r2, r3, #4
|
|
8009dea: 681b ldr r3, [r3, #0]
|
|
8009dec: 9203 str r2, [sp, #12]
|
|
8009dee: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
8009df2: 9305 str r3, [sp, #20]
|
|
8009df4: f8df a0b4 ldr.w sl, [pc, #180] @ 8009eac <_svfiprintf_r+0x1e8>
|
|
8009df8: 2203 movs r2, #3
|
|
8009dfa: 4650 mov r0, sl
|
|
8009dfc: 7821 ldrb r1, [r4, #0]
|
|
8009dfe: f000 fa17 bl 800a230 <memchr>
|
|
8009e02: b138 cbz r0, 8009e14 <_svfiprintf_r+0x150>
|
|
8009e04: 2240 movs r2, #64 @ 0x40
|
|
8009e06: 9b04 ldr r3, [sp, #16]
|
|
8009e08: eba0 000a sub.w r0, r0, sl
|
|
8009e0c: 4082 lsls r2, r0
|
|
8009e0e: 4313 orrs r3, r2
|
|
8009e10: 3401 adds r4, #1
|
|
8009e12: 9304 str r3, [sp, #16]
|
|
8009e14: f814 1b01 ldrb.w r1, [r4], #1
|
|
8009e18: 2206 movs r2, #6
|
|
8009e1a: 4825 ldr r0, [pc, #148] @ (8009eb0 <_svfiprintf_r+0x1ec>)
|
|
8009e1c: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8009e20: f000 fa06 bl 800a230 <memchr>
|
|
8009e24: 2800 cmp r0, #0
|
|
8009e26: d036 beq.n 8009e96 <_svfiprintf_r+0x1d2>
|
|
8009e28: 4b22 ldr r3, [pc, #136] @ (8009eb4 <_svfiprintf_r+0x1f0>)
|
|
8009e2a: bb1b cbnz r3, 8009e74 <_svfiprintf_r+0x1b0>
|
|
8009e2c: 9b03 ldr r3, [sp, #12]
|
|
8009e2e: 3307 adds r3, #7
|
|
8009e30: f023 0307 bic.w r3, r3, #7
|
|
8009e34: 3308 adds r3, #8
|
|
8009e36: 9303 str r3, [sp, #12]
|
|
8009e38: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8009e3a: 4433 add r3, r6
|
|
8009e3c: 9309 str r3, [sp, #36] @ 0x24
|
|
8009e3e: e76a b.n 8009d16 <_svfiprintf_r+0x52>
|
|
8009e40: 460c mov r4, r1
|
|
8009e42: 2001 movs r0, #1
|
|
8009e44: fb0c 3202 mla r2, ip, r2, r3
|
|
8009e48: e7a8 b.n 8009d9c <_svfiprintf_r+0xd8>
|
|
8009e4a: 2300 movs r3, #0
|
|
8009e4c: f04f 0c0a mov.w ip, #10
|
|
8009e50: 4619 mov r1, r3
|
|
8009e52: 3401 adds r4, #1
|
|
8009e54: 9305 str r3, [sp, #20]
|
|
8009e56: 4620 mov r0, r4
|
|
8009e58: f810 2b01 ldrb.w r2, [r0], #1
|
|
8009e5c: 3a30 subs r2, #48 @ 0x30
|
|
8009e5e: 2a09 cmp r2, #9
|
|
8009e60: d903 bls.n 8009e6a <_svfiprintf_r+0x1a6>
|
|
8009e62: 2b00 cmp r3, #0
|
|
8009e64: d0c6 beq.n 8009df4 <_svfiprintf_r+0x130>
|
|
8009e66: 9105 str r1, [sp, #20]
|
|
8009e68: e7c4 b.n 8009df4 <_svfiprintf_r+0x130>
|
|
8009e6a: 4604 mov r4, r0
|
|
8009e6c: 2301 movs r3, #1
|
|
8009e6e: fb0c 2101 mla r1, ip, r1, r2
|
|
8009e72: e7f0 b.n 8009e56 <_svfiprintf_r+0x192>
|
|
8009e74: ab03 add r3, sp, #12
|
|
8009e76: 9300 str r3, [sp, #0]
|
|
8009e78: 462a mov r2, r5
|
|
8009e7a: 4638 mov r0, r7
|
|
8009e7c: 4b0e ldr r3, [pc, #56] @ (8009eb8 <_svfiprintf_r+0x1f4>)
|
|
8009e7e: a904 add r1, sp, #16
|
|
8009e80: f3af 8000 nop.w
|
|
8009e84: 1c42 adds r2, r0, #1
|
|
8009e86: 4606 mov r6, r0
|
|
8009e88: d1d6 bne.n 8009e38 <_svfiprintf_r+0x174>
|
|
8009e8a: 89ab ldrh r3, [r5, #12]
|
|
8009e8c: 065b lsls r3, r3, #25
|
|
8009e8e: f53f af2d bmi.w 8009cec <_svfiprintf_r+0x28>
|
|
8009e92: 9809 ldr r0, [sp, #36] @ 0x24
|
|
8009e94: e72c b.n 8009cf0 <_svfiprintf_r+0x2c>
|
|
8009e96: ab03 add r3, sp, #12
|
|
8009e98: 9300 str r3, [sp, #0]
|
|
8009e9a: 462a mov r2, r5
|
|
8009e9c: 4638 mov r0, r7
|
|
8009e9e: 4b06 ldr r3, [pc, #24] @ (8009eb8 <_svfiprintf_r+0x1f4>)
|
|
8009ea0: a904 add r1, sp, #16
|
|
8009ea2: f000 f87d bl 8009fa0 <_printf_i>
|
|
8009ea6: e7ed b.n 8009e84 <_svfiprintf_r+0x1c0>
|
|
8009ea8: 0800a412 .word 0x0800a412
|
|
8009eac: 0800a418 .word 0x0800a418
|
|
8009eb0: 0800a41c .word 0x0800a41c
|
|
8009eb4: 00000000 .word 0x00000000
|
|
8009eb8: 08009c0d .word 0x08009c0d
|
|
|
|
08009ebc <_printf_common>:
|
|
8009ebc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8009ec0: 4616 mov r6, r2
|
|
8009ec2: 4698 mov r8, r3
|
|
8009ec4: 688a ldr r2, [r1, #8]
|
|
8009ec6: 690b ldr r3, [r1, #16]
|
|
8009ec8: 4607 mov r7, r0
|
|
8009eca: 4293 cmp r3, r2
|
|
8009ecc: bfb8 it lt
|
|
8009ece: 4613 movlt r3, r2
|
|
8009ed0: 6033 str r3, [r6, #0]
|
|
8009ed2: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
|
|
8009ed6: 460c mov r4, r1
|
|
8009ed8: f8dd 9020 ldr.w r9, [sp, #32]
|
|
8009edc: b10a cbz r2, 8009ee2 <_printf_common+0x26>
|
|
8009ede: 3301 adds r3, #1
|
|
8009ee0: 6033 str r3, [r6, #0]
|
|
8009ee2: 6823 ldr r3, [r4, #0]
|
|
8009ee4: 0699 lsls r1, r3, #26
|
|
8009ee6: bf42 ittt mi
|
|
8009ee8: 6833 ldrmi r3, [r6, #0]
|
|
8009eea: 3302 addmi r3, #2
|
|
8009eec: 6033 strmi r3, [r6, #0]
|
|
8009eee: 6825 ldr r5, [r4, #0]
|
|
8009ef0: f015 0506 ands.w r5, r5, #6
|
|
8009ef4: d106 bne.n 8009f04 <_printf_common+0x48>
|
|
8009ef6: f104 0a19 add.w sl, r4, #25
|
|
8009efa: 68e3 ldr r3, [r4, #12]
|
|
8009efc: 6832 ldr r2, [r6, #0]
|
|
8009efe: 1a9b subs r3, r3, r2
|
|
8009f00: 42ab cmp r3, r5
|
|
8009f02: dc2b bgt.n 8009f5c <_printf_common+0xa0>
|
|
8009f04: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
|
|
8009f08: 6822 ldr r2, [r4, #0]
|
|
8009f0a: 3b00 subs r3, #0
|
|
8009f0c: bf18 it ne
|
|
8009f0e: 2301 movne r3, #1
|
|
8009f10: 0692 lsls r2, r2, #26
|
|
8009f12: d430 bmi.n 8009f76 <_printf_common+0xba>
|
|
8009f14: 4641 mov r1, r8
|
|
8009f16: 4638 mov r0, r7
|
|
8009f18: f104 0243 add.w r2, r4, #67 @ 0x43
|
|
8009f1c: 47c8 blx r9
|
|
8009f1e: 3001 adds r0, #1
|
|
8009f20: d023 beq.n 8009f6a <_printf_common+0xae>
|
|
8009f22: 6823 ldr r3, [r4, #0]
|
|
8009f24: 6922 ldr r2, [r4, #16]
|
|
8009f26: f003 0306 and.w r3, r3, #6
|
|
8009f2a: 2b04 cmp r3, #4
|
|
8009f2c: bf14 ite ne
|
|
8009f2e: 2500 movne r5, #0
|
|
8009f30: 6833 ldreq r3, [r6, #0]
|
|
8009f32: f04f 0600 mov.w r6, #0
|
|
8009f36: bf08 it eq
|
|
8009f38: 68e5 ldreq r5, [r4, #12]
|
|
8009f3a: f104 041a add.w r4, r4, #26
|
|
8009f3e: bf08 it eq
|
|
8009f40: 1aed subeq r5, r5, r3
|
|
8009f42: f854 3c12 ldr.w r3, [r4, #-18]
|
|
8009f46: bf08 it eq
|
|
8009f48: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
8009f4c: 4293 cmp r3, r2
|
|
8009f4e: bfc4 itt gt
|
|
8009f50: 1a9b subgt r3, r3, r2
|
|
8009f52: 18ed addgt r5, r5, r3
|
|
8009f54: 42b5 cmp r5, r6
|
|
8009f56: d11a bne.n 8009f8e <_printf_common+0xd2>
|
|
8009f58: 2000 movs r0, #0
|
|
8009f5a: e008 b.n 8009f6e <_printf_common+0xb2>
|
|
8009f5c: 2301 movs r3, #1
|
|
8009f5e: 4652 mov r2, sl
|
|
8009f60: 4641 mov r1, r8
|
|
8009f62: 4638 mov r0, r7
|
|
8009f64: 47c8 blx r9
|
|
8009f66: 3001 adds r0, #1
|
|
8009f68: d103 bne.n 8009f72 <_printf_common+0xb6>
|
|
8009f6a: f04f 30ff mov.w r0, #4294967295
|
|
8009f6e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8009f72: 3501 adds r5, #1
|
|
8009f74: e7c1 b.n 8009efa <_printf_common+0x3e>
|
|
8009f76: 2030 movs r0, #48 @ 0x30
|
|
8009f78: 18e1 adds r1, r4, r3
|
|
8009f7a: f881 0043 strb.w r0, [r1, #67] @ 0x43
|
|
8009f7e: 1c5a adds r2, r3, #1
|
|
8009f80: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
|
|
8009f84: 4422 add r2, r4
|
|
8009f86: 3302 adds r3, #2
|
|
8009f88: f882 1043 strb.w r1, [r2, #67] @ 0x43
|
|
8009f8c: e7c2 b.n 8009f14 <_printf_common+0x58>
|
|
8009f8e: 2301 movs r3, #1
|
|
8009f90: 4622 mov r2, r4
|
|
8009f92: 4641 mov r1, r8
|
|
8009f94: 4638 mov r0, r7
|
|
8009f96: 47c8 blx r9
|
|
8009f98: 3001 adds r0, #1
|
|
8009f9a: d0e6 beq.n 8009f6a <_printf_common+0xae>
|
|
8009f9c: 3601 adds r6, #1
|
|
8009f9e: e7d9 b.n 8009f54 <_printf_common+0x98>
|
|
|
|
08009fa0 <_printf_i>:
|
|
8009fa0: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8009fa4: 7e0f ldrb r7, [r1, #24]
|
|
8009fa6: 4691 mov r9, r2
|
|
8009fa8: 2f78 cmp r7, #120 @ 0x78
|
|
8009faa: 4680 mov r8, r0
|
|
8009fac: 460c mov r4, r1
|
|
8009fae: 469a mov sl, r3
|
|
8009fb0: 9e0c ldr r6, [sp, #48] @ 0x30
|
|
8009fb2: f101 0243 add.w r2, r1, #67 @ 0x43
|
|
8009fb6: d807 bhi.n 8009fc8 <_printf_i+0x28>
|
|
8009fb8: 2f62 cmp r7, #98 @ 0x62
|
|
8009fba: d80a bhi.n 8009fd2 <_printf_i+0x32>
|
|
8009fbc: 2f00 cmp r7, #0
|
|
8009fbe: f000 80d1 beq.w 800a164 <_printf_i+0x1c4>
|
|
8009fc2: 2f58 cmp r7, #88 @ 0x58
|
|
8009fc4: f000 80b8 beq.w 800a138 <_printf_i+0x198>
|
|
8009fc8: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8009fcc: f884 7042 strb.w r7, [r4, #66] @ 0x42
|
|
8009fd0: e03a b.n 800a048 <_printf_i+0xa8>
|
|
8009fd2: f1a7 0363 sub.w r3, r7, #99 @ 0x63
|
|
8009fd6: 2b15 cmp r3, #21
|
|
8009fd8: d8f6 bhi.n 8009fc8 <_printf_i+0x28>
|
|
8009fda: a101 add r1, pc, #4 @ (adr r1, 8009fe0 <_printf_i+0x40>)
|
|
8009fdc: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
8009fe0: 0800a039 .word 0x0800a039
|
|
8009fe4: 0800a04d .word 0x0800a04d
|
|
8009fe8: 08009fc9 .word 0x08009fc9
|
|
8009fec: 08009fc9 .word 0x08009fc9
|
|
8009ff0: 08009fc9 .word 0x08009fc9
|
|
8009ff4: 08009fc9 .word 0x08009fc9
|
|
8009ff8: 0800a04d .word 0x0800a04d
|
|
8009ffc: 08009fc9 .word 0x08009fc9
|
|
800a000: 08009fc9 .word 0x08009fc9
|
|
800a004: 08009fc9 .word 0x08009fc9
|
|
800a008: 08009fc9 .word 0x08009fc9
|
|
800a00c: 0800a14b .word 0x0800a14b
|
|
800a010: 0800a077 .word 0x0800a077
|
|
800a014: 0800a105 .word 0x0800a105
|
|
800a018: 08009fc9 .word 0x08009fc9
|
|
800a01c: 08009fc9 .word 0x08009fc9
|
|
800a020: 0800a16d .word 0x0800a16d
|
|
800a024: 08009fc9 .word 0x08009fc9
|
|
800a028: 0800a077 .word 0x0800a077
|
|
800a02c: 08009fc9 .word 0x08009fc9
|
|
800a030: 08009fc9 .word 0x08009fc9
|
|
800a034: 0800a10d .word 0x0800a10d
|
|
800a038: 6833 ldr r3, [r6, #0]
|
|
800a03a: 1d1a adds r2, r3, #4
|
|
800a03c: 681b ldr r3, [r3, #0]
|
|
800a03e: 6032 str r2, [r6, #0]
|
|
800a040: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
800a044: f884 3042 strb.w r3, [r4, #66] @ 0x42
|
|
800a048: 2301 movs r3, #1
|
|
800a04a: e09c b.n 800a186 <_printf_i+0x1e6>
|
|
800a04c: 6833 ldr r3, [r6, #0]
|
|
800a04e: 6820 ldr r0, [r4, #0]
|
|
800a050: 1d19 adds r1, r3, #4
|
|
800a052: 6031 str r1, [r6, #0]
|
|
800a054: 0606 lsls r6, r0, #24
|
|
800a056: d501 bpl.n 800a05c <_printf_i+0xbc>
|
|
800a058: 681d ldr r5, [r3, #0]
|
|
800a05a: e003 b.n 800a064 <_printf_i+0xc4>
|
|
800a05c: 0645 lsls r5, r0, #25
|
|
800a05e: d5fb bpl.n 800a058 <_printf_i+0xb8>
|
|
800a060: f9b3 5000 ldrsh.w r5, [r3]
|
|
800a064: 2d00 cmp r5, #0
|
|
800a066: da03 bge.n 800a070 <_printf_i+0xd0>
|
|
800a068: 232d movs r3, #45 @ 0x2d
|
|
800a06a: 426d negs r5, r5
|
|
800a06c: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800a070: 230a movs r3, #10
|
|
800a072: 4858 ldr r0, [pc, #352] @ (800a1d4 <_printf_i+0x234>)
|
|
800a074: e011 b.n 800a09a <_printf_i+0xfa>
|
|
800a076: 6821 ldr r1, [r4, #0]
|
|
800a078: 6833 ldr r3, [r6, #0]
|
|
800a07a: 0608 lsls r0, r1, #24
|
|
800a07c: f853 5b04 ldr.w r5, [r3], #4
|
|
800a080: d402 bmi.n 800a088 <_printf_i+0xe8>
|
|
800a082: 0649 lsls r1, r1, #25
|
|
800a084: bf48 it mi
|
|
800a086: b2ad uxthmi r5, r5
|
|
800a088: 2f6f cmp r7, #111 @ 0x6f
|
|
800a08a: 6033 str r3, [r6, #0]
|
|
800a08c: bf14 ite ne
|
|
800a08e: 230a movne r3, #10
|
|
800a090: 2308 moveq r3, #8
|
|
800a092: 4850 ldr r0, [pc, #320] @ (800a1d4 <_printf_i+0x234>)
|
|
800a094: 2100 movs r1, #0
|
|
800a096: f884 1043 strb.w r1, [r4, #67] @ 0x43
|
|
800a09a: 6866 ldr r6, [r4, #4]
|
|
800a09c: 2e00 cmp r6, #0
|
|
800a09e: 60a6 str r6, [r4, #8]
|
|
800a0a0: db05 blt.n 800a0ae <_printf_i+0x10e>
|
|
800a0a2: 6821 ldr r1, [r4, #0]
|
|
800a0a4: 432e orrs r6, r5
|
|
800a0a6: f021 0104 bic.w r1, r1, #4
|
|
800a0aa: 6021 str r1, [r4, #0]
|
|
800a0ac: d04b beq.n 800a146 <_printf_i+0x1a6>
|
|
800a0ae: 4616 mov r6, r2
|
|
800a0b0: fbb5 f1f3 udiv r1, r5, r3
|
|
800a0b4: fb03 5711 mls r7, r3, r1, r5
|
|
800a0b8: 5dc7 ldrb r7, [r0, r7]
|
|
800a0ba: f806 7d01 strb.w r7, [r6, #-1]!
|
|
800a0be: 462f mov r7, r5
|
|
800a0c0: 42bb cmp r3, r7
|
|
800a0c2: 460d mov r5, r1
|
|
800a0c4: d9f4 bls.n 800a0b0 <_printf_i+0x110>
|
|
800a0c6: 2b08 cmp r3, #8
|
|
800a0c8: d10b bne.n 800a0e2 <_printf_i+0x142>
|
|
800a0ca: 6823 ldr r3, [r4, #0]
|
|
800a0cc: 07df lsls r7, r3, #31
|
|
800a0ce: d508 bpl.n 800a0e2 <_printf_i+0x142>
|
|
800a0d0: 6923 ldr r3, [r4, #16]
|
|
800a0d2: 6861 ldr r1, [r4, #4]
|
|
800a0d4: 4299 cmp r1, r3
|
|
800a0d6: bfde ittt le
|
|
800a0d8: 2330 movle r3, #48 @ 0x30
|
|
800a0da: f806 3c01 strble.w r3, [r6, #-1]
|
|
800a0de: f106 36ff addle.w r6, r6, #4294967295
|
|
800a0e2: 1b92 subs r2, r2, r6
|
|
800a0e4: 6122 str r2, [r4, #16]
|
|
800a0e6: 464b mov r3, r9
|
|
800a0e8: 4621 mov r1, r4
|
|
800a0ea: 4640 mov r0, r8
|
|
800a0ec: f8cd a000 str.w sl, [sp]
|
|
800a0f0: aa03 add r2, sp, #12
|
|
800a0f2: f7ff fee3 bl 8009ebc <_printf_common>
|
|
800a0f6: 3001 adds r0, #1
|
|
800a0f8: d14a bne.n 800a190 <_printf_i+0x1f0>
|
|
800a0fa: f04f 30ff mov.w r0, #4294967295
|
|
800a0fe: b004 add sp, #16
|
|
800a100: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800a104: 6823 ldr r3, [r4, #0]
|
|
800a106: f043 0320 orr.w r3, r3, #32
|
|
800a10a: 6023 str r3, [r4, #0]
|
|
800a10c: 2778 movs r7, #120 @ 0x78
|
|
800a10e: 4832 ldr r0, [pc, #200] @ (800a1d8 <_printf_i+0x238>)
|
|
800a110: f884 7045 strb.w r7, [r4, #69] @ 0x45
|
|
800a114: 6823 ldr r3, [r4, #0]
|
|
800a116: 6831 ldr r1, [r6, #0]
|
|
800a118: 061f lsls r7, r3, #24
|
|
800a11a: f851 5b04 ldr.w r5, [r1], #4
|
|
800a11e: d402 bmi.n 800a126 <_printf_i+0x186>
|
|
800a120: 065f lsls r7, r3, #25
|
|
800a122: bf48 it mi
|
|
800a124: b2ad uxthmi r5, r5
|
|
800a126: 6031 str r1, [r6, #0]
|
|
800a128: 07d9 lsls r1, r3, #31
|
|
800a12a: bf44 itt mi
|
|
800a12c: f043 0320 orrmi.w r3, r3, #32
|
|
800a130: 6023 strmi r3, [r4, #0]
|
|
800a132: b11d cbz r5, 800a13c <_printf_i+0x19c>
|
|
800a134: 2310 movs r3, #16
|
|
800a136: e7ad b.n 800a094 <_printf_i+0xf4>
|
|
800a138: 4826 ldr r0, [pc, #152] @ (800a1d4 <_printf_i+0x234>)
|
|
800a13a: e7e9 b.n 800a110 <_printf_i+0x170>
|
|
800a13c: 6823 ldr r3, [r4, #0]
|
|
800a13e: f023 0320 bic.w r3, r3, #32
|
|
800a142: 6023 str r3, [r4, #0]
|
|
800a144: e7f6 b.n 800a134 <_printf_i+0x194>
|
|
800a146: 4616 mov r6, r2
|
|
800a148: e7bd b.n 800a0c6 <_printf_i+0x126>
|
|
800a14a: 6833 ldr r3, [r6, #0]
|
|
800a14c: 6825 ldr r5, [r4, #0]
|
|
800a14e: 1d18 adds r0, r3, #4
|
|
800a150: 6961 ldr r1, [r4, #20]
|
|
800a152: 6030 str r0, [r6, #0]
|
|
800a154: 062e lsls r6, r5, #24
|
|
800a156: 681b ldr r3, [r3, #0]
|
|
800a158: d501 bpl.n 800a15e <_printf_i+0x1be>
|
|
800a15a: 6019 str r1, [r3, #0]
|
|
800a15c: e002 b.n 800a164 <_printf_i+0x1c4>
|
|
800a15e: 0668 lsls r0, r5, #25
|
|
800a160: d5fb bpl.n 800a15a <_printf_i+0x1ba>
|
|
800a162: 8019 strh r1, [r3, #0]
|
|
800a164: 2300 movs r3, #0
|
|
800a166: 4616 mov r6, r2
|
|
800a168: 6123 str r3, [r4, #16]
|
|
800a16a: e7bc b.n 800a0e6 <_printf_i+0x146>
|
|
800a16c: 6833 ldr r3, [r6, #0]
|
|
800a16e: 2100 movs r1, #0
|
|
800a170: 1d1a adds r2, r3, #4
|
|
800a172: 6032 str r2, [r6, #0]
|
|
800a174: 681e ldr r6, [r3, #0]
|
|
800a176: 6862 ldr r2, [r4, #4]
|
|
800a178: 4630 mov r0, r6
|
|
800a17a: f000 f859 bl 800a230 <memchr>
|
|
800a17e: b108 cbz r0, 800a184 <_printf_i+0x1e4>
|
|
800a180: 1b80 subs r0, r0, r6
|
|
800a182: 6060 str r0, [r4, #4]
|
|
800a184: 6863 ldr r3, [r4, #4]
|
|
800a186: 6123 str r3, [r4, #16]
|
|
800a188: 2300 movs r3, #0
|
|
800a18a: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800a18e: e7aa b.n 800a0e6 <_printf_i+0x146>
|
|
800a190: 4632 mov r2, r6
|
|
800a192: 4649 mov r1, r9
|
|
800a194: 4640 mov r0, r8
|
|
800a196: 6923 ldr r3, [r4, #16]
|
|
800a198: 47d0 blx sl
|
|
800a19a: 3001 adds r0, #1
|
|
800a19c: d0ad beq.n 800a0fa <_printf_i+0x15a>
|
|
800a19e: 6823 ldr r3, [r4, #0]
|
|
800a1a0: 079b lsls r3, r3, #30
|
|
800a1a2: d413 bmi.n 800a1cc <_printf_i+0x22c>
|
|
800a1a4: 68e0 ldr r0, [r4, #12]
|
|
800a1a6: 9b03 ldr r3, [sp, #12]
|
|
800a1a8: 4298 cmp r0, r3
|
|
800a1aa: bfb8 it lt
|
|
800a1ac: 4618 movlt r0, r3
|
|
800a1ae: e7a6 b.n 800a0fe <_printf_i+0x15e>
|
|
800a1b0: 2301 movs r3, #1
|
|
800a1b2: 4632 mov r2, r6
|
|
800a1b4: 4649 mov r1, r9
|
|
800a1b6: 4640 mov r0, r8
|
|
800a1b8: 47d0 blx sl
|
|
800a1ba: 3001 adds r0, #1
|
|
800a1bc: d09d beq.n 800a0fa <_printf_i+0x15a>
|
|
800a1be: 3501 adds r5, #1
|
|
800a1c0: 68e3 ldr r3, [r4, #12]
|
|
800a1c2: 9903 ldr r1, [sp, #12]
|
|
800a1c4: 1a5b subs r3, r3, r1
|
|
800a1c6: 42ab cmp r3, r5
|
|
800a1c8: dcf2 bgt.n 800a1b0 <_printf_i+0x210>
|
|
800a1ca: e7eb b.n 800a1a4 <_printf_i+0x204>
|
|
800a1cc: 2500 movs r5, #0
|
|
800a1ce: f104 0619 add.w r6, r4, #25
|
|
800a1d2: e7f5 b.n 800a1c0 <_printf_i+0x220>
|
|
800a1d4: 0800a423 .word 0x0800a423
|
|
800a1d8: 0800a434 .word 0x0800a434
|
|
|
|
0800a1dc <memmove>:
|
|
800a1dc: 4288 cmp r0, r1
|
|
800a1de: b510 push {r4, lr}
|
|
800a1e0: eb01 0402 add.w r4, r1, r2
|
|
800a1e4: d902 bls.n 800a1ec <memmove+0x10>
|
|
800a1e6: 4284 cmp r4, r0
|
|
800a1e8: 4623 mov r3, r4
|
|
800a1ea: d807 bhi.n 800a1fc <memmove+0x20>
|
|
800a1ec: 1e43 subs r3, r0, #1
|
|
800a1ee: 42a1 cmp r1, r4
|
|
800a1f0: d008 beq.n 800a204 <memmove+0x28>
|
|
800a1f2: f811 2b01 ldrb.w r2, [r1], #1
|
|
800a1f6: f803 2f01 strb.w r2, [r3, #1]!
|
|
800a1fa: e7f8 b.n 800a1ee <memmove+0x12>
|
|
800a1fc: 4601 mov r1, r0
|
|
800a1fe: 4402 add r2, r0
|
|
800a200: 428a cmp r2, r1
|
|
800a202: d100 bne.n 800a206 <memmove+0x2a>
|
|
800a204: bd10 pop {r4, pc}
|
|
800a206: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
800a20a: f802 4d01 strb.w r4, [r2, #-1]!
|
|
800a20e: e7f7 b.n 800a200 <memmove+0x24>
|
|
|
|
0800a210 <_sbrk_r>:
|
|
800a210: b538 push {r3, r4, r5, lr}
|
|
800a212: 2300 movs r3, #0
|
|
800a214: 4d05 ldr r5, [pc, #20] @ (800a22c <_sbrk_r+0x1c>)
|
|
800a216: 4604 mov r4, r0
|
|
800a218: 4608 mov r0, r1
|
|
800a21a: 602b str r3, [r5, #0]
|
|
800a21c: f7f7 f87c bl 8001318 <_sbrk>
|
|
800a220: 1c43 adds r3, r0, #1
|
|
800a222: d102 bne.n 800a22a <_sbrk_r+0x1a>
|
|
800a224: 682b ldr r3, [r5, #0]
|
|
800a226: b103 cbz r3, 800a22a <_sbrk_r+0x1a>
|
|
800a228: 6023 str r3, [r4, #0]
|
|
800a22a: bd38 pop {r3, r4, r5, pc}
|
|
800a22c: 200017a8 .word 0x200017a8
|
|
|
|
0800a230 <memchr>:
|
|
800a230: 4603 mov r3, r0
|
|
800a232: b510 push {r4, lr}
|
|
800a234: b2c9 uxtb r1, r1
|
|
800a236: 4402 add r2, r0
|
|
800a238: 4293 cmp r3, r2
|
|
800a23a: 4618 mov r0, r3
|
|
800a23c: d101 bne.n 800a242 <memchr+0x12>
|
|
800a23e: 2000 movs r0, #0
|
|
800a240: e003 b.n 800a24a <memchr+0x1a>
|
|
800a242: 7804 ldrb r4, [r0, #0]
|
|
800a244: 3301 adds r3, #1
|
|
800a246: 428c cmp r4, r1
|
|
800a248: d1f6 bne.n 800a238 <memchr+0x8>
|
|
800a24a: bd10 pop {r4, pc}
|
|
|
|
0800a24c <memcpy>:
|
|
800a24c: 440a add r2, r1
|
|
800a24e: 4291 cmp r1, r2
|
|
800a250: f100 33ff add.w r3, r0, #4294967295
|
|
800a254: d100 bne.n 800a258 <memcpy+0xc>
|
|
800a256: 4770 bx lr
|
|
800a258: b510 push {r4, lr}
|
|
800a25a: f811 4b01 ldrb.w r4, [r1], #1
|
|
800a25e: 4291 cmp r1, r2
|
|
800a260: f803 4f01 strb.w r4, [r3, #1]!
|
|
800a264: d1f9 bne.n 800a25a <memcpy+0xe>
|
|
800a266: bd10 pop {r4, pc}
|
|
|
|
0800a268 <_realloc_r>:
|
|
800a268: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800a26c: 4607 mov r7, r0
|
|
800a26e: 4614 mov r4, r2
|
|
800a270: 460d mov r5, r1
|
|
800a272: b921 cbnz r1, 800a27e <_realloc_r+0x16>
|
|
800a274: 4611 mov r1, r2
|
|
800a276: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
800a27a: f7ff bc3b b.w 8009af4 <_malloc_r>
|
|
800a27e: b92a cbnz r2, 800a28c <_realloc_r+0x24>
|
|
800a280: f7ff fbce bl 8009a20 <_free_r>
|
|
800a284: 4625 mov r5, r4
|
|
800a286: 4628 mov r0, r5
|
|
800a288: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
800a28c: f000 f81a bl 800a2c4 <_malloc_usable_size_r>
|
|
800a290: 4284 cmp r4, r0
|
|
800a292: 4606 mov r6, r0
|
|
800a294: d802 bhi.n 800a29c <_realloc_r+0x34>
|
|
800a296: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
800a29a: d8f4 bhi.n 800a286 <_realloc_r+0x1e>
|
|
800a29c: 4621 mov r1, r4
|
|
800a29e: 4638 mov r0, r7
|
|
800a2a0: f7ff fc28 bl 8009af4 <_malloc_r>
|
|
800a2a4: 4680 mov r8, r0
|
|
800a2a6: b908 cbnz r0, 800a2ac <_realloc_r+0x44>
|
|
800a2a8: 4645 mov r5, r8
|
|
800a2aa: e7ec b.n 800a286 <_realloc_r+0x1e>
|
|
800a2ac: 42b4 cmp r4, r6
|
|
800a2ae: 4622 mov r2, r4
|
|
800a2b0: 4629 mov r1, r5
|
|
800a2b2: bf28 it cs
|
|
800a2b4: 4632 movcs r2, r6
|
|
800a2b6: f7ff ffc9 bl 800a24c <memcpy>
|
|
800a2ba: 4629 mov r1, r5
|
|
800a2bc: 4638 mov r0, r7
|
|
800a2be: f7ff fbaf bl 8009a20 <_free_r>
|
|
800a2c2: e7f1 b.n 800a2a8 <_realloc_r+0x40>
|
|
|
|
0800a2c4 <_malloc_usable_size_r>:
|
|
800a2c4: f851 3c04 ldr.w r3, [r1, #-4]
|
|
800a2c8: 1f18 subs r0, r3, #4
|
|
800a2ca: 2b00 cmp r3, #0
|
|
800a2cc: bfbc itt lt
|
|
800a2ce: 580b ldrlt r3, [r1, r0]
|
|
800a2d0: 18c0 addlt r0, r0, r3
|
|
800a2d2: 4770 bx lr
|
|
|
|
0800a2d4 <_init>:
|
|
800a2d4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800a2d6: bf00 nop
|
|
800a2d8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800a2da: bc08 pop {r3}
|
|
800a2dc: 469e mov lr, r3
|
|
800a2de: 4770 bx lr
|
|
|
|
0800a2e0 <_fini>:
|
|
800a2e0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800a2e2: bf00 nop
|
|
800a2e4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800a2e6: bc08 pop {r3}
|
|
800a2e8: 469e mov lr, r3
|
|
800a2ea: 4770 bx lr
|