5715 lines
211 KiB
Plaintext
5715 lines
211 KiB
Plaintext
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AUTOM2.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000000b8 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00001e18 080000b8 080000b8 000010b8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000094 08001ed0 08001ed0 00002ed0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08001f64 08001f64 0000300c 2**0
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CONTENTS, READONLY
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4 .ARM 00000000 08001f64 08001f64 0000300c 2**0
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CONTENTS, READONLY
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5 .preinit_array 00000000 08001f64 08001f64 0000300c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08001f64 08001f64 00002f64 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08001f68 08001f68 00002f68 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 0000000c 20000000 08001f6c 00003000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000006c 2000000c 08001f78 0000300c 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000078 08001f78 00003078 2**0
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ALLOC
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11 .ARM.attributes 00000028 00000000 00000000 0000300c 2**0
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CONTENTS, READONLY
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12 .debug_info 00008745 00000000 00000000 00003034 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 000016fe 00000000 00000000 0000b779 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000a00 00000000 00000000 0000ce78 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000007bf 00000000 00000000 0000d878 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00013d8b 00000000 00000000 0000e037 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0000b21a 00000000 00000000 00021dc2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 00080769 00000000 00000000 0002cfdc 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 000ad745 2**0
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CONTENTS, READONLY
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20 .debug_frame 000023c0 00000000 00000000 000ad788 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000052 00000000 00000000 000afb48 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080000b8 <__do_global_dtors_aux>:
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80000b8: b510 push {r4, lr}
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80000ba: 4c06 ldr r4, [pc, #24] @ (80000d4 <__do_global_dtors_aux+0x1c>)
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80000bc: 7823 ldrb r3, [r4, #0]
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80000be: 2b00 cmp r3, #0
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80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a>
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80000c2: 4b05 ldr r3, [pc, #20] @ (80000d8 <__do_global_dtors_aux+0x20>)
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80000c4: 2b00 cmp r3, #0
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80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16>
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80000c8: 4804 ldr r0, [pc, #16] @ (80000dc <__do_global_dtors_aux+0x24>)
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80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16>
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80000cc: bf00 nop
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80000ce: 2301 movs r3, #1
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80000d0: 7023 strb r3, [r4, #0]
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80000d2: bd10 pop {r4, pc}
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80000d4: 2000000c .word 0x2000000c
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80000d8: 00000000 .word 0x00000000
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80000dc: 08001eb8 .word 0x08001eb8
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080000e0 <frame_dummy>:
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80000e0: 4b04 ldr r3, [pc, #16] @ (80000f4 <frame_dummy+0x14>)
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80000e2: b510 push {r4, lr}
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80000e4: 2b00 cmp r3, #0
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80000e6: d003 beq.n 80000f0 <frame_dummy+0x10>
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80000e8: 4903 ldr r1, [pc, #12] @ (80000f8 <frame_dummy+0x18>)
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80000ea: 4804 ldr r0, [pc, #16] @ (80000fc <frame_dummy+0x1c>)
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80000ec: e000 b.n 80000f0 <frame_dummy+0x10>
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80000ee: bf00 nop
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80000f0: bd10 pop {r4, pc}
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80000f2: 46c0 nop @ (mov r8, r8)
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80000f4: 00000000 .word 0x00000000
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80000f8: 20000010 .word 0x20000010
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80000fc: 08001eb8 .word 0x08001eb8
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08000100 <__udivsi3>:
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8000100: 2200 movs r2, #0
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8000102: 0843 lsrs r3, r0, #1
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8000104: 428b cmp r3, r1
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8000106: d374 bcc.n 80001f2 <__udivsi3+0xf2>
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8000108: 0903 lsrs r3, r0, #4
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800010a: 428b cmp r3, r1
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800010c: d35f bcc.n 80001ce <__udivsi3+0xce>
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800010e: 0a03 lsrs r3, r0, #8
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8000110: 428b cmp r3, r1
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8000112: d344 bcc.n 800019e <__udivsi3+0x9e>
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8000114: 0b03 lsrs r3, r0, #12
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8000116: 428b cmp r3, r1
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8000118: d328 bcc.n 800016c <__udivsi3+0x6c>
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800011a: 0c03 lsrs r3, r0, #16
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800011c: 428b cmp r3, r1
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800011e: d30d bcc.n 800013c <__udivsi3+0x3c>
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8000120: 22ff movs r2, #255 @ 0xff
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8000122: 0209 lsls r1, r1, #8
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8000124: ba12 rev r2, r2
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8000126: 0c03 lsrs r3, r0, #16
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8000128: 428b cmp r3, r1
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800012a: d302 bcc.n 8000132 <__udivsi3+0x32>
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800012c: 1212 asrs r2, r2, #8
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800012e: 0209 lsls r1, r1, #8
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8000130: d065 beq.n 80001fe <__udivsi3+0xfe>
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8000132: 0b03 lsrs r3, r0, #12
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8000134: 428b cmp r3, r1
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8000136: d319 bcc.n 800016c <__udivsi3+0x6c>
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8000138: e000 b.n 800013c <__udivsi3+0x3c>
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800013a: 0a09 lsrs r1, r1, #8
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800013c: 0bc3 lsrs r3, r0, #15
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800013e: 428b cmp r3, r1
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8000140: d301 bcc.n 8000146 <__udivsi3+0x46>
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8000142: 03cb lsls r3, r1, #15
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8000144: 1ac0 subs r0, r0, r3
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8000146: 4152 adcs r2, r2
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8000148: 0b83 lsrs r3, r0, #14
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800014a: 428b cmp r3, r1
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800014c: d301 bcc.n 8000152 <__udivsi3+0x52>
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800014e: 038b lsls r3, r1, #14
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8000150: 1ac0 subs r0, r0, r3
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8000152: 4152 adcs r2, r2
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8000154: 0b43 lsrs r3, r0, #13
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8000156: 428b cmp r3, r1
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8000158: d301 bcc.n 800015e <__udivsi3+0x5e>
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800015a: 034b lsls r3, r1, #13
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800015c: 1ac0 subs r0, r0, r3
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800015e: 4152 adcs r2, r2
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8000160: 0b03 lsrs r3, r0, #12
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8000162: 428b cmp r3, r1
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8000164: d301 bcc.n 800016a <__udivsi3+0x6a>
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8000166: 030b lsls r3, r1, #12
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8000168: 1ac0 subs r0, r0, r3
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800016a: 4152 adcs r2, r2
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800016c: 0ac3 lsrs r3, r0, #11
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800016e: 428b cmp r3, r1
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8000170: d301 bcc.n 8000176 <__udivsi3+0x76>
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8000172: 02cb lsls r3, r1, #11
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8000174: 1ac0 subs r0, r0, r3
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8000176: 4152 adcs r2, r2
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8000178: 0a83 lsrs r3, r0, #10
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800017a: 428b cmp r3, r1
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800017c: d301 bcc.n 8000182 <__udivsi3+0x82>
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800017e: 028b lsls r3, r1, #10
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8000180: 1ac0 subs r0, r0, r3
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8000182: 4152 adcs r2, r2
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8000184: 0a43 lsrs r3, r0, #9
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8000186: 428b cmp r3, r1
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8000188: d301 bcc.n 800018e <__udivsi3+0x8e>
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800018a: 024b lsls r3, r1, #9
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800018c: 1ac0 subs r0, r0, r3
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800018e: 4152 adcs r2, r2
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8000190: 0a03 lsrs r3, r0, #8
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8000192: 428b cmp r3, r1
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8000194: d301 bcc.n 800019a <__udivsi3+0x9a>
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8000196: 020b lsls r3, r1, #8
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8000198: 1ac0 subs r0, r0, r3
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800019a: 4152 adcs r2, r2
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800019c: d2cd bcs.n 800013a <__udivsi3+0x3a>
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800019e: 09c3 lsrs r3, r0, #7
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80001a0: 428b cmp r3, r1
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80001a2: d301 bcc.n 80001a8 <__udivsi3+0xa8>
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80001a4: 01cb lsls r3, r1, #7
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80001a6: 1ac0 subs r0, r0, r3
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80001a8: 4152 adcs r2, r2
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80001aa: 0983 lsrs r3, r0, #6
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80001ac: 428b cmp r3, r1
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80001ae: d301 bcc.n 80001b4 <__udivsi3+0xb4>
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80001b0: 018b lsls r3, r1, #6
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80001b2: 1ac0 subs r0, r0, r3
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80001b4: 4152 adcs r2, r2
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80001b6: 0943 lsrs r3, r0, #5
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80001b8: 428b cmp r3, r1
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80001ba: d301 bcc.n 80001c0 <__udivsi3+0xc0>
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80001bc: 014b lsls r3, r1, #5
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80001be: 1ac0 subs r0, r0, r3
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80001c0: 4152 adcs r2, r2
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80001c2: 0903 lsrs r3, r0, #4
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80001c4: 428b cmp r3, r1
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80001c6: d301 bcc.n 80001cc <__udivsi3+0xcc>
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80001c8: 010b lsls r3, r1, #4
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80001ca: 1ac0 subs r0, r0, r3
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80001cc: 4152 adcs r2, r2
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80001ce: 08c3 lsrs r3, r0, #3
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80001d0: 428b cmp r3, r1
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80001d2: d301 bcc.n 80001d8 <__udivsi3+0xd8>
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80001d4: 00cb lsls r3, r1, #3
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80001d6: 1ac0 subs r0, r0, r3
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80001d8: 4152 adcs r2, r2
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80001da: 0883 lsrs r3, r0, #2
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80001dc: 428b cmp r3, r1
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80001de: d301 bcc.n 80001e4 <__udivsi3+0xe4>
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80001e0: 008b lsls r3, r1, #2
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80001e2: 1ac0 subs r0, r0, r3
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80001e4: 4152 adcs r2, r2
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80001e6: 0843 lsrs r3, r0, #1
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80001e8: 428b cmp r3, r1
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80001ea: d301 bcc.n 80001f0 <__udivsi3+0xf0>
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80001ec: 004b lsls r3, r1, #1
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80001ee: 1ac0 subs r0, r0, r3
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80001f0: 4152 adcs r2, r2
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80001f2: 1a41 subs r1, r0, r1
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80001f4: d200 bcs.n 80001f8 <__udivsi3+0xf8>
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80001f6: 4601 mov r1, r0
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80001f8: 4152 adcs r2, r2
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80001fa: 4610 mov r0, r2
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80001fc: 4770 bx lr
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80001fe: e7ff b.n 8000200 <__udivsi3+0x100>
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8000200: b501 push {r0, lr}
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8000202: 2000 movs r0, #0
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8000204: f000 f806 bl 8000214 <__aeabi_idiv0>
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8000208: bd02 pop {r1, pc}
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800020a: 46c0 nop @ (mov r8, r8)
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0800020c <__aeabi_uidivmod>:
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800020c: 2900 cmp r1, #0
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800020e: d0f7 beq.n 8000200 <__udivsi3+0x100>
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8000210: e776 b.n 8000100 <__udivsi3>
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8000212: 4770 bx lr
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08000214 <__aeabi_idiv0>:
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8000214: 4770 bx lr
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8000216: 46c0 nop @ (mov r8, r8)
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08000218 <main>:
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void)
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{
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8000218: b580 push {r7, lr}
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800021a: af00 add r7, sp, #0
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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800021c: f000 f9d8 bl 80005d0 <HAL_Init>
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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8000220: f000 f806 bl 8000230 <SystemClock_Config>
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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8000224: f000 f8c2 bl 80003ac <MX_GPIO_Init>
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MX_TIM3_Init();
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8000228: f000 f84a bl 80002c0 <MX_TIM3_Init>
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/* USER CODE END 2 */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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800022c: 46c0 nop @ (mov r8, r8)
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800022e: e7fd b.n 800022c <main+0x14>
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08000230 <SystemClock_Config>:
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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8000230: b590 push {r4, r7, lr}
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8000232: b093 sub sp, #76 @ 0x4c
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8000234: af00 add r7, sp, #0
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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8000236: 2414 movs r4, #20
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8000238: 193b adds r3, r7, r4
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800023a: 0018 movs r0, r3
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800023c: 2334 movs r3, #52 @ 0x34
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800023e: 001a movs r2, r3
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8000240: 2100 movs r1, #0
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8000242: f001 fe0d bl 8001e60 <memset>
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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8000246: 1d3b adds r3, r7, #4
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8000248: 0018 movs r0, r3
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800024a: 2310 movs r3, #16
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800024c: 001a movs r2, r3
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800024e: 2100 movs r1, #0
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8000250: f001 fe06 bl 8001e60 <memset>
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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8000254: 2380 movs r3, #128 @ 0x80
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8000256: 009b lsls r3, r3, #2
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8000258: 0018 movs r0, r3
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800025a: f000 fc57 bl 8000b0c <HAL_PWREx_ControlVoltageScaling>
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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800025e: 193b adds r3, r7, r4
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8000260: 2202 movs r2, #2
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8000262: 601a str r2, [r3, #0]
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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8000264: 193b adds r3, r7, r4
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8000266: 2280 movs r2, #128 @ 0x80
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8000268: 0052 lsls r2, r2, #1
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800026a: 60da str r2, [r3, #12]
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RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
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800026c: 193b adds r3, r7, r4
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800026e: 2200 movs r2, #0
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8000270: 611a str r2, [r3, #16]
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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8000272: 193b adds r3, r7, r4
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8000274: 2240 movs r2, #64 @ 0x40
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8000276: 615a str r2, [r3, #20]
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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8000278: 193b adds r3, r7, r4
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800027a: 2200 movs r2, #0
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800027c: 61da str r2, [r3, #28]
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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800027e: 193b adds r3, r7, r4
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8000280: 0018 movs r0, r3
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8000282: f000 fc83 bl 8000b8c <HAL_RCC_OscConfig>
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8000286: 1e03 subs r3, r0, #0
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8000288: d001 beq.n 800028e <SystemClock_Config+0x5e>
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{
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Error_Handler();
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800028a: f000 f8b1 bl 80003f0 <Error_Handler>
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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800028e: 1d3b adds r3, r7, #4
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8000290: 2207 movs r2, #7
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8000292: 601a str r2, [r3, #0]
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|RCC_CLOCKTYPE_PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
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8000294: 1d3b adds r3, r7, #4
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8000296: 2200 movs r2, #0
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8000298: 605a str r2, [r3, #4]
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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800029a: 1d3b adds r3, r7, #4
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800029c: 2200 movs r2, #0
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800029e: 609a str r2, [r3, #8]
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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80002a0: 1d3b adds r3, r7, #4
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80002a2: 2200 movs r2, #0
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80002a4: 60da str r2, [r3, #12]
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|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|
80002a6: 1d3b adds r3, r7, #4
|
|
80002a8: 2100 movs r1, #0
|
|
80002aa: 0018 movs r0, r3
|
|
80002ac: f000 ff7e bl 80011ac <HAL_RCC_ClockConfig>
|
|
80002b0: 1e03 subs r3, r0, #0
|
|
80002b2: d001 beq.n 80002b8 <SystemClock_Config+0x88>
|
|
{
|
|
Error_Handler();
|
|
80002b4: f000 f89c bl 80003f0 <Error_Handler>
|
|
}
|
|
}
|
|
80002b8: 46c0 nop @ (mov r8, r8)
|
|
80002ba: 46bd mov sp, r7
|
|
80002bc: b013 add sp, #76 @ 0x4c
|
|
80002be: bd90 pop {r4, r7, pc}
|
|
|
|
080002c0 <MX_TIM3_Init>:
|
|
* @brief TIM3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM3_Init(void)
|
|
{
|
|
80002c0: b580 push {r7, lr}
|
|
80002c2: b08a sub sp, #40 @ 0x28
|
|
80002c4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80002c6: 231c movs r3, #28
|
|
80002c8: 18fb adds r3, r7, r3
|
|
80002ca: 0018 movs r0, r3
|
|
80002cc: 230c movs r3, #12
|
|
80002ce: 001a movs r2, r3
|
|
80002d0: 2100 movs r1, #0
|
|
80002d2: f001 fdc5 bl 8001e60 <memset>
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
80002d6: 003b movs r3, r7
|
|
80002d8: 0018 movs r0, r3
|
|
80002da: 231c movs r3, #28
|
|
80002dc: 001a movs r2, r3
|
|
80002de: 2100 movs r1, #0
|
|
80002e0: f001 fdbe bl 8001e60 <memset>
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
80002e4: 4b2e ldr r3, [pc, #184] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
80002e6: 4a2f ldr r2, [pc, #188] @ (80003a4 <MX_TIM3_Init+0xe4>)
|
|
80002e8: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
80002ea: 4b2d ldr r3, [pc, #180] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
80002ec: 2200 movs r2, #0
|
|
80002ee: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
80002f0: 4b2b ldr r3, [pc, #172] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
80002f2: 2200 movs r2, #0
|
|
80002f4: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
80002f6: 4b2a ldr r3, [pc, #168] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
80002f8: 4a2b ldr r2, [pc, #172] @ (80003a8 <MX_TIM3_Init+0xe8>)
|
|
80002fa: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
80002fc: 4b28 ldr r3, [pc, #160] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
80002fe: 2200 movs r2, #0
|
|
8000300: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000302: 4b27 ldr r3, [pc, #156] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
8000304: 2200 movs r2, #0
|
|
8000306: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
|
|
8000308: 4b25 ldr r3, [pc, #148] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
800030a: 0018 movs r0, r3
|
|
800030c: f001 f8d8 bl 80014c0 <HAL_TIM_PWM_Init>
|
|
8000310: 1e03 subs r3, r0, #0
|
|
8000312: d001 beq.n 8000318 <MX_TIM3_Init+0x58>
|
|
{
|
|
Error_Handler();
|
|
8000314: f000 f86c bl 80003f0 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000318: 211c movs r1, #28
|
|
800031a: 187b adds r3, r7, r1
|
|
800031c: 2200 movs r2, #0
|
|
800031e: 601a str r2, [r3, #0]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8000320: 187b adds r3, r7, r1
|
|
8000322: 2200 movs r2, #0
|
|
8000324: 609a str r2, [r3, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8000326: 187a adds r2, r7, r1
|
|
8000328: 4b1d ldr r3, [pc, #116] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
800032a: 0011 movs r1, r2
|
|
800032c: 0018 movs r0, r3
|
|
800032e: f001 fd35 bl 8001d9c <HAL_TIMEx_MasterConfigSynchronization>
|
|
8000332: 1e03 subs r3, r0, #0
|
|
8000334: d001 beq.n 800033a <MX_TIM3_Init+0x7a>
|
|
{
|
|
Error_Handler();
|
|
8000336: f000 f85b bl 80003f0 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
800033a: 003b movs r3, r7
|
|
800033c: 2260 movs r2, #96 @ 0x60
|
|
800033e: 601a str r2, [r3, #0]
|
|
sConfigOC.Pulse = 0;
|
|
8000340: 003b movs r3, r7
|
|
8000342: 2200 movs r2, #0
|
|
8000344: 605a str r2, [r3, #4]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
8000346: 003b movs r3, r7
|
|
8000348: 2200 movs r2, #0
|
|
800034a: 609a str r2, [r3, #8]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
800034c: 003b movs r3, r7
|
|
800034e: 2200 movs r2, #0
|
|
8000350: 611a str r2, [r3, #16]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8000352: 0039 movs r1, r7
|
|
8000354: 4b12 ldr r3, [pc, #72] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
8000356: 2200 movs r2, #0
|
|
8000358: 0018 movs r0, r3
|
|
800035a: f001 f909 bl 8001570 <HAL_TIM_PWM_ConfigChannel>
|
|
800035e: 1e03 subs r3, r0, #0
|
|
8000360: d001 beq.n 8000366 <MX_TIM3_Init+0xa6>
|
|
{
|
|
Error_Handler();
|
|
8000362: f000 f845 bl 80003f0 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
|
8000366: 0039 movs r1, r7
|
|
8000368: 4b0d ldr r3, [pc, #52] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
800036a: 2204 movs r2, #4
|
|
800036c: 0018 movs r0, r3
|
|
800036e: f001 f8ff bl 8001570 <HAL_TIM_PWM_ConfigChannel>
|
|
8000372: 1e03 subs r3, r0, #0
|
|
8000374: d001 beq.n 800037a <MX_TIM3_Init+0xba>
|
|
{
|
|
Error_Handler();
|
|
8000376: f000 f83b bl 80003f0 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
|
800037a: 0039 movs r1, r7
|
|
800037c: 4b08 ldr r3, [pc, #32] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
800037e: 2208 movs r2, #8
|
|
8000380: 0018 movs r0, r3
|
|
8000382: f001 f8f5 bl 8001570 <HAL_TIM_PWM_ConfigChannel>
|
|
8000386: 1e03 subs r3, r0, #0
|
|
8000388: d001 beq.n 800038e <MX_TIM3_Init+0xce>
|
|
{
|
|
Error_Handler();
|
|
800038a: f000 f831 bl 80003f0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim3);
|
|
800038e: 4b04 ldr r3, [pc, #16] @ (80003a0 <MX_TIM3_Init+0xe0>)
|
|
8000390: 0018 movs r0, r3
|
|
8000392: f000 f875 bl 8000480 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000396: 46c0 nop @ (mov r8, r8)
|
|
8000398: 46bd mov sp, r7
|
|
800039a: b00a add sp, #40 @ 0x28
|
|
800039c: bd80 pop {r7, pc}
|
|
800039e: 46c0 nop @ (mov r8, r8)
|
|
80003a0: 20000028 .word 0x20000028
|
|
80003a4: 40000400 .word 0x40000400
|
|
80003a8: 0000ffff .word 0x0000ffff
|
|
|
|
080003ac <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
80003ac: b580 push {r7, lr}
|
|
80003ae: b082 sub sp, #8
|
|
80003b0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80003b2: 4b0e ldr r3, [pc, #56] @ (80003ec <MX_GPIO_Init+0x40>)
|
|
80003b4: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80003b6: 4b0d ldr r3, [pc, #52] @ (80003ec <MX_GPIO_Init+0x40>)
|
|
80003b8: 2101 movs r1, #1
|
|
80003ba: 430a orrs r2, r1
|
|
80003bc: 635a str r2, [r3, #52] @ 0x34
|
|
80003be: 4b0b ldr r3, [pc, #44] @ (80003ec <MX_GPIO_Init+0x40>)
|
|
80003c0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80003c2: 2201 movs r2, #1
|
|
80003c4: 4013 ands r3, r2
|
|
80003c6: 607b str r3, [r7, #4]
|
|
80003c8: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80003ca: 4b08 ldr r3, [pc, #32] @ (80003ec <MX_GPIO_Init+0x40>)
|
|
80003cc: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80003ce: 4b07 ldr r3, [pc, #28] @ (80003ec <MX_GPIO_Init+0x40>)
|
|
80003d0: 2102 movs r1, #2
|
|
80003d2: 430a orrs r2, r1
|
|
80003d4: 635a str r2, [r3, #52] @ 0x34
|
|
80003d6: 4b05 ldr r3, [pc, #20] @ (80003ec <MX_GPIO_Init+0x40>)
|
|
80003d8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80003da: 2202 movs r2, #2
|
|
80003dc: 4013 ands r3, r2
|
|
80003de: 603b str r3, [r7, #0]
|
|
80003e0: 683b ldr r3, [r7, #0]
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
80003e2: 46c0 nop @ (mov r8, r8)
|
|
80003e4: 46bd mov sp, r7
|
|
80003e6: b002 add sp, #8
|
|
80003e8: bd80 pop {r7, pc}
|
|
80003ea: 46c0 nop @ (mov r8, r8)
|
|
80003ec: 40021000 .word 0x40021000
|
|
|
|
080003f0 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
80003f0: b580 push {r7, lr}
|
|
80003f2: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80003f4: b672 cpsid i
|
|
}
|
|
80003f6: 46c0 nop @ (mov r8, r8)
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80003f8: 46c0 nop @ (mov r8, r8)
|
|
80003fa: e7fd b.n 80003f8 <Error_Handler+0x8>
|
|
|
|
080003fc <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80003fc: b580 push {r7, lr}
|
|
80003fe: b082 sub sp, #8
|
|
8000400: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000402: 4b0f ldr r3, [pc, #60] @ (8000440 <HAL_MspInit+0x44>)
|
|
8000404: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8000406: 4b0e ldr r3, [pc, #56] @ (8000440 <HAL_MspInit+0x44>)
|
|
8000408: 2101 movs r1, #1
|
|
800040a: 430a orrs r2, r1
|
|
800040c: 641a str r2, [r3, #64] @ 0x40
|
|
800040e: 4b0c ldr r3, [pc, #48] @ (8000440 <HAL_MspInit+0x44>)
|
|
8000410: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000412: 2201 movs r2, #1
|
|
8000414: 4013 ands r3, r2
|
|
8000416: 607b str r3, [r7, #4]
|
|
8000418: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800041a: 4b09 ldr r3, [pc, #36] @ (8000440 <HAL_MspInit+0x44>)
|
|
800041c: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
800041e: 4b08 ldr r3, [pc, #32] @ (8000440 <HAL_MspInit+0x44>)
|
|
8000420: 2180 movs r1, #128 @ 0x80
|
|
8000422: 0549 lsls r1, r1, #21
|
|
8000424: 430a orrs r2, r1
|
|
8000426: 63da str r2, [r3, #60] @ 0x3c
|
|
8000428: 4b05 ldr r3, [pc, #20] @ (8000440 <HAL_MspInit+0x44>)
|
|
800042a: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
800042c: 2380 movs r3, #128 @ 0x80
|
|
800042e: 055b lsls r3, r3, #21
|
|
8000430: 4013 ands r3, r2
|
|
8000432: 603b str r3, [r7, #0]
|
|
8000434: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000436: 46c0 nop @ (mov r8, r8)
|
|
8000438: 46bd mov sp, r7
|
|
800043a: b002 add sp, #8
|
|
800043c: bd80 pop {r7, pc}
|
|
800043e: 46c0 nop @ (mov r8, r8)
|
|
8000440: 40021000 .word 0x40021000
|
|
|
|
08000444 <HAL_TIM_PWM_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_pwm: TIM_PWM handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
|
|
{
|
|
8000444: b580 push {r7, lr}
|
|
8000446: b084 sub sp, #16
|
|
8000448: af00 add r7, sp, #0
|
|
800044a: 6078 str r0, [r7, #4]
|
|
if(htim_pwm->Instance==TIM3)
|
|
800044c: 687b ldr r3, [r7, #4]
|
|
800044e: 681b ldr r3, [r3, #0]
|
|
8000450: 4a09 ldr r2, [pc, #36] @ (8000478 <HAL_TIM_PWM_MspInit+0x34>)
|
|
8000452: 4293 cmp r3, r2
|
|
8000454: d10b bne.n 800046e <HAL_TIM_PWM_MspInit+0x2a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
8000456: 4b09 ldr r3, [pc, #36] @ (800047c <HAL_TIM_PWM_MspInit+0x38>)
|
|
8000458: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
800045a: 4b08 ldr r3, [pc, #32] @ (800047c <HAL_TIM_PWM_MspInit+0x38>)
|
|
800045c: 2102 movs r1, #2
|
|
800045e: 430a orrs r2, r1
|
|
8000460: 63da str r2, [r3, #60] @ 0x3c
|
|
8000462: 4b06 ldr r3, [pc, #24] @ (800047c <HAL_TIM_PWM_MspInit+0x38>)
|
|
8000464: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8000466: 2202 movs r2, #2
|
|
8000468: 4013 ands r3, r2
|
|
800046a: 60fb str r3, [r7, #12]
|
|
800046c: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800046e: 46c0 nop @ (mov r8, r8)
|
|
8000470: 46bd mov sp, r7
|
|
8000472: b004 add sp, #16
|
|
8000474: bd80 pop {r7, pc}
|
|
8000476: 46c0 nop @ (mov r8, r8)
|
|
8000478: 40000400 .word 0x40000400
|
|
800047c: 40021000 .word 0x40021000
|
|
|
|
08000480 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8000480: b590 push {r4, r7, lr}
|
|
8000482: b08b sub sp, #44 @ 0x2c
|
|
8000484: af00 add r7, sp, #0
|
|
8000486: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000488: 2414 movs r4, #20
|
|
800048a: 193b adds r3, r7, r4
|
|
800048c: 0018 movs r0, r3
|
|
800048e: 2314 movs r3, #20
|
|
8000490: 001a movs r2, r3
|
|
8000492: 2100 movs r1, #0
|
|
8000494: f001 fce4 bl 8001e60 <memset>
|
|
if(htim->Instance==TIM3)
|
|
8000498: 687b ldr r3, [r7, #4]
|
|
800049a: 681b ldr r3, [r3, #0]
|
|
800049c: 4a25 ldr r2, [pc, #148] @ (8000534 <HAL_TIM_MspPostInit+0xb4>)
|
|
800049e: 4293 cmp r3, r2
|
|
80004a0: d143 bne.n 800052a <HAL_TIM_MspPostInit+0xaa>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80004a2: 4b25 ldr r3, [pc, #148] @ (8000538 <HAL_TIM_MspPostInit+0xb8>)
|
|
80004a4: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80004a6: 4b24 ldr r3, [pc, #144] @ (8000538 <HAL_TIM_MspPostInit+0xb8>)
|
|
80004a8: 2101 movs r1, #1
|
|
80004aa: 430a orrs r2, r1
|
|
80004ac: 635a str r2, [r3, #52] @ 0x34
|
|
80004ae: 4b22 ldr r3, [pc, #136] @ (8000538 <HAL_TIM_MspPostInit+0xb8>)
|
|
80004b0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80004b2: 2201 movs r2, #1
|
|
80004b4: 4013 ands r3, r2
|
|
80004b6: 613b str r3, [r7, #16]
|
|
80004b8: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80004ba: 4b1f ldr r3, [pc, #124] @ (8000538 <HAL_TIM_MspPostInit+0xb8>)
|
|
80004bc: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80004be: 4b1e ldr r3, [pc, #120] @ (8000538 <HAL_TIM_MspPostInit+0xb8>)
|
|
80004c0: 2102 movs r1, #2
|
|
80004c2: 430a orrs r2, r1
|
|
80004c4: 635a str r2, [r3, #52] @ 0x34
|
|
80004c6: 4b1c ldr r3, [pc, #112] @ (8000538 <HAL_TIM_MspPostInit+0xb8>)
|
|
80004c8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80004ca: 2202 movs r2, #2
|
|
80004cc: 4013 ands r3, r2
|
|
80004ce: 60fb str r3, [r7, #12]
|
|
80004d0: 68fb ldr r3, [r7, #12]
|
|
/**TIM3 GPIO Configuration
|
|
PA7 ------> TIM3_CH2
|
|
PB0 ------> TIM3_CH3
|
|
PB4 ------> TIM3_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_7;
|
|
80004d2: 193b adds r3, r7, r4
|
|
80004d4: 2280 movs r2, #128 @ 0x80
|
|
80004d6: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80004d8: 193b adds r3, r7, r4
|
|
80004da: 2202 movs r2, #2
|
|
80004dc: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80004de: 193b adds r3, r7, r4
|
|
80004e0: 2200 movs r2, #0
|
|
80004e2: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80004e4: 193b adds r3, r7, r4
|
|
80004e6: 2200 movs r2, #0
|
|
80004e8: 60da str r2, [r3, #12]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
|
80004ea: 193b adds r3, r7, r4
|
|
80004ec: 2201 movs r2, #1
|
|
80004ee: 611a str r2, [r3, #16]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80004f0: 193a adds r2, r7, r4
|
|
80004f2: 23a0 movs r3, #160 @ 0xa0
|
|
80004f4: 05db lsls r3, r3, #23
|
|
80004f6: 0011 movs r1, r2
|
|
80004f8: 0018 movs r0, r3
|
|
80004fa: f000 f9a3 bl 8000844 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4;
|
|
80004fe: 0021 movs r1, r4
|
|
8000500: 187b adds r3, r7, r1
|
|
8000502: 2211 movs r2, #17
|
|
8000504: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000506: 187b adds r3, r7, r1
|
|
8000508: 2202 movs r2, #2
|
|
800050a: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800050c: 187b adds r3, r7, r1
|
|
800050e: 2200 movs r2, #0
|
|
8000510: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000512: 187b adds r3, r7, r1
|
|
8000514: 2200 movs r2, #0
|
|
8000516: 60da str r2, [r3, #12]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
|
8000518: 187b adds r3, r7, r1
|
|
800051a: 2201 movs r2, #1
|
|
800051c: 611a str r2, [r3, #16]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
800051e: 187b adds r3, r7, r1
|
|
8000520: 4a06 ldr r2, [pc, #24] @ (800053c <HAL_TIM_MspPostInit+0xbc>)
|
|
8000522: 0019 movs r1, r3
|
|
8000524: 0010 movs r0, r2
|
|
8000526: f000 f98d bl 8000844 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM3_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM3_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
800052a: 46c0 nop @ (mov r8, r8)
|
|
800052c: 46bd mov sp, r7
|
|
800052e: b00b add sp, #44 @ 0x2c
|
|
8000530: bd90 pop {r4, r7, pc}
|
|
8000532: 46c0 nop @ (mov r8, r8)
|
|
8000534: 40000400 .word 0x40000400
|
|
8000538: 40021000 .word 0x40021000
|
|
800053c: 50000400 .word 0x50000400
|
|
|
|
08000540 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000540: b580 push {r7, lr}
|
|
8000542: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8000544: 46c0 nop @ (mov r8, r8)
|
|
8000546: e7fd b.n 8000544 <NMI_Handler+0x4>
|
|
|
|
08000548 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000548: b580 push {r7, lr}
|
|
800054a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
800054c: 46c0 nop @ (mov r8, r8)
|
|
800054e: e7fd b.n 800054c <HardFault_Handler+0x4>
|
|
|
|
08000550 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000550: b580 push {r7, lr}
|
|
8000552: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVC_IRQn 0 */
|
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
|
|
|
/* USER CODE END SVC_IRQn 1 */
|
|
}
|
|
8000554: 46c0 nop @ (mov r8, r8)
|
|
8000556: 46bd mov sp, r7
|
|
8000558: bd80 pop {r7, pc}
|
|
|
|
0800055a <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
800055a: b580 push {r7, lr}
|
|
800055c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
800055e: 46c0 nop @ (mov r8, r8)
|
|
8000560: 46bd mov sp, r7
|
|
8000562: bd80 pop {r7, pc}
|
|
|
|
08000564 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8000564: b580 push {r7, lr}
|
|
8000566: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8000568: f000 f89c bl 80006a4 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
800056c: 46c0 nop @ (mov r8, r8)
|
|
800056e: 46bd mov sp, r7
|
|
8000570: bd80 pop {r7, pc}
|
|
|
|
08000572 <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8000572: b580 push {r7, lr}
|
|
8000574: af00 add r7, sp, #0
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8000576: 46c0 nop @ (mov r8, r8)
|
|
8000578: 46bd mov sp, r7
|
|
800057a: bd80 pop {r7, pc}
|
|
|
|
0800057c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
800057c: 480d ldr r0, [pc, #52] @ (80005b4 <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
800057e: 4685 mov sp, r0
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8000580: f7ff fff7 bl 8000572 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8000584: 480c ldr r0, [pc, #48] @ (80005b8 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8000586: 490d ldr r1, [pc, #52] @ (80005bc <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8000588: 4a0d ldr r2, [pc, #52] @ (80005c0 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
800058a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800058c: e002 b.n 8000594 <LoopCopyDataInit>
|
|
|
|
0800058e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800058e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8000590: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8000592: 3304 adds r3, #4
|
|
|
|
08000594 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8000594: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8000596: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8000598: d3f9 bcc.n 800058e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800059a: 4a0a ldr r2, [pc, #40] @ (80005c4 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
800059c: 4c0a ldr r4, [pc, #40] @ (80005c8 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
800059e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
80005a0: e001 b.n 80005a6 <LoopFillZerobss>
|
|
|
|
080005a2 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
80005a2: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
80005a4: 3204 adds r2, #4
|
|
|
|
080005a6 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
80005a6: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
80005a8: d3fb bcc.n 80005a2 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80005aa: f001 fc61 bl 8001e70 <__libc_init_array>
|
|
/* Call the application s entry point.*/
|
|
bl main
|
|
80005ae: f7ff fe33 bl 8000218 <main>
|
|
|
|
080005b2 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
80005b2: e7fe b.n 80005b2 <LoopForever>
|
|
ldr r0, =_estack
|
|
80005b4: 20002000 .word 0x20002000
|
|
ldr r0, =_sdata
|
|
80005b8: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80005bc: 2000000c .word 0x2000000c
|
|
ldr r2, =_sidata
|
|
80005c0: 08001f6c .word 0x08001f6c
|
|
ldr r2, =_sbss
|
|
80005c4: 2000000c .word 0x2000000c
|
|
ldr r4, =_ebss
|
|
80005c8: 20000078 .word 0x20000078
|
|
|
|
080005cc <ADC1_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80005cc: e7fe b.n 80005cc <ADC1_IRQHandler>
|
|
...
|
|
|
|
080005d0 <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80005d0: b580 push {r7, lr}
|
|
80005d2: b082 sub sp, #8
|
|
80005d4: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80005d6: 1dfb adds r3, r7, #7
|
|
80005d8: 2200 movs r2, #0
|
|
80005da: 701a strb r2, [r3, #0]
|
|
#if (INSTRUCTION_CACHE_ENABLE == 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
80005dc: 4b0b ldr r3, [pc, #44] @ (800060c <HAL_Init+0x3c>)
|
|
80005de: 681a ldr r2, [r3, #0]
|
|
80005e0: 4b0a ldr r3, [pc, #40] @ (800060c <HAL_Init+0x3c>)
|
|
80005e2: 2180 movs r1, #128 @ 0x80
|
|
80005e4: 0049 lsls r1, r1, #1
|
|
80005e6: 430a orrs r2, r1
|
|
80005e8: 601a str r2, [r3, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
80005ea: 2003 movs r0, #3
|
|
80005ec: f000 f810 bl 8000610 <HAL_InitTick>
|
|
80005f0: 1e03 subs r3, r0, #0
|
|
80005f2: d003 beq.n 80005fc <HAL_Init+0x2c>
|
|
{
|
|
status = HAL_ERROR;
|
|
80005f4: 1dfb adds r3, r7, #7
|
|
80005f6: 2201 movs r2, #1
|
|
80005f8: 701a strb r2, [r3, #0]
|
|
80005fa: e001 b.n 8000600 <HAL_Init+0x30>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80005fc: f7ff fefe bl 80003fc <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8000600: 1dfb adds r3, r7, #7
|
|
8000602: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8000604: 0018 movs r0, r3
|
|
8000606: 46bd mov sp, r7
|
|
8000608: b002 add sp, #8
|
|
800060a: bd80 pop {r7, pc}
|
|
800060c: 40022000 .word 0x40022000
|
|
|
|
08000610 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8000610: b590 push {r4, r7, lr}
|
|
8000612: b085 sub sp, #20
|
|
8000614: af00 add r7, sp, #0
|
|
8000616: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8000618: 230f movs r3, #15
|
|
800061a: 18fb adds r3, r7, r3
|
|
800061c: 2200 movs r2, #0
|
|
800061e: 701a strb r2, [r3, #0]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
8000620: 4b1d ldr r3, [pc, #116] @ (8000698 <HAL_InitTick+0x88>)
|
|
8000622: 781b ldrb r3, [r3, #0]
|
|
8000624: 2b00 cmp r3, #0
|
|
8000626: d02b beq.n 8000680 <HAL_InitTick+0x70>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
|
|
8000628: 4b1c ldr r3, [pc, #112] @ (800069c <HAL_InitTick+0x8c>)
|
|
800062a: 681c ldr r4, [r3, #0]
|
|
800062c: 4b1a ldr r3, [pc, #104] @ (8000698 <HAL_InitTick+0x88>)
|
|
800062e: 781b ldrb r3, [r3, #0]
|
|
8000630: 0019 movs r1, r3
|
|
8000632: 23fa movs r3, #250 @ 0xfa
|
|
8000634: 0098 lsls r0, r3, #2
|
|
8000636: f7ff fd63 bl 8000100 <__udivsi3>
|
|
800063a: 0003 movs r3, r0
|
|
800063c: 0019 movs r1, r3
|
|
800063e: 0020 movs r0, r4
|
|
8000640: f7ff fd5e bl 8000100 <__udivsi3>
|
|
8000644: 0003 movs r3, r0
|
|
8000646: 0018 movs r0, r3
|
|
8000648: f000 f8ef bl 800082a <HAL_SYSTICK_Config>
|
|
800064c: 1e03 subs r3, r0, #0
|
|
800064e: d112 bne.n 8000676 <HAL_InitTick+0x66>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8000650: 687b ldr r3, [r7, #4]
|
|
8000652: 2b03 cmp r3, #3
|
|
8000654: d80a bhi.n 800066c <HAL_InitTick+0x5c>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000656: 6879 ldr r1, [r7, #4]
|
|
8000658: 2301 movs r3, #1
|
|
800065a: 425b negs r3, r3
|
|
800065c: 2200 movs r2, #0
|
|
800065e: 0018 movs r0, r3
|
|
8000660: f000 f8ce bl 8000800 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8000664: 4b0e ldr r3, [pc, #56] @ (80006a0 <HAL_InitTick+0x90>)
|
|
8000666: 687a ldr r2, [r7, #4]
|
|
8000668: 601a str r2, [r3, #0]
|
|
800066a: e00d b.n 8000688 <HAL_InitTick+0x78>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800066c: 230f movs r3, #15
|
|
800066e: 18fb adds r3, r7, r3
|
|
8000670: 2201 movs r2, #1
|
|
8000672: 701a strb r2, [r3, #0]
|
|
8000674: e008 b.n 8000688 <HAL_InitTick+0x78>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000676: 230f movs r3, #15
|
|
8000678: 18fb adds r3, r7, r3
|
|
800067a: 2201 movs r2, #1
|
|
800067c: 701a strb r2, [r3, #0]
|
|
800067e: e003 b.n 8000688 <HAL_InitTick+0x78>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000680: 230f movs r3, #15
|
|
8000682: 18fb adds r3, r7, r3
|
|
8000684: 2201 movs r2, #1
|
|
8000686: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8000688: 230f movs r3, #15
|
|
800068a: 18fb adds r3, r7, r3
|
|
800068c: 781b ldrb r3, [r3, #0]
|
|
}
|
|
800068e: 0018 movs r0, r3
|
|
8000690: 46bd mov sp, r7
|
|
8000692: b005 add sp, #20
|
|
8000694: bd90 pop {r4, r7, pc}
|
|
8000696: 46c0 nop @ (mov r8, r8)
|
|
8000698: 20000008 .word 0x20000008
|
|
800069c: 20000000 .word 0x20000000
|
|
80006a0: 20000004 .word 0x20000004
|
|
|
|
080006a4 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80006a4: b580 push {r7, lr}
|
|
80006a6: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
80006a8: 4b05 ldr r3, [pc, #20] @ (80006c0 <HAL_IncTick+0x1c>)
|
|
80006aa: 781b ldrb r3, [r3, #0]
|
|
80006ac: 001a movs r2, r3
|
|
80006ae: 4b05 ldr r3, [pc, #20] @ (80006c4 <HAL_IncTick+0x20>)
|
|
80006b0: 681b ldr r3, [r3, #0]
|
|
80006b2: 18d2 adds r2, r2, r3
|
|
80006b4: 4b03 ldr r3, [pc, #12] @ (80006c4 <HAL_IncTick+0x20>)
|
|
80006b6: 601a str r2, [r3, #0]
|
|
}
|
|
80006b8: 46c0 nop @ (mov r8, r8)
|
|
80006ba: 46bd mov sp, r7
|
|
80006bc: bd80 pop {r7, pc}
|
|
80006be: 46c0 nop @ (mov r8, r8)
|
|
80006c0: 20000008 .word 0x20000008
|
|
80006c4: 20000074 .word 0x20000074
|
|
|
|
080006c8 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80006c8: b580 push {r7, lr}
|
|
80006ca: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80006cc: 4b02 ldr r3, [pc, #8] @ (80006d8 <HAL_GetTick+0x10>)
|
|
80006ce: 681b ldr r3, [r3, #0]
|
|
}
|
|
80006d0: 0018 movs r0, r3
|
|
80006d2: 46bd mov sp, r7
|
|
80006d4: bd80 pop {r7, pc}
|
|
80006d6: 46c0 nop @ (mov r8, r8)
|
|
80006d8: 20000074 .word 0x20000074
|
|
|
|
080006dc <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
80006dc: b590 push {r4, r7, lr}
|
|
80006de: b083 sub sp, #12
|
|
80006e0: af00 add r7, sp, #0
|
|
80006e2: 0002 movs r2, r0
|
|
80006e4: 6039 str r1, [r7, #0]
|
|
80006e6: 1dfb adds r3, r7, #7
|
|
80006e8: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80006ea: 1dfb adds r3, r7, #7
|
|
80006ec: 781b ldrb r3, [r3, #0]
|
|
80006ee: 2b7f cmp r3, #127 @ 0x7f
|
|
80006f0: d828 bhi.n 8000744 <__NVIC_SetPriority+0x68>
|
|
{
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
80006f2: 4a2f ldr r2, [pc, #188] @ (80007b0 <__NVIC_SetPriority+0xd4>)
|
|
80006f4: 1dfb adds r3, r7, #7
|
|
80006f6: 781b ldrb r3, [r3, #0]
|
|
80006f8: b25b sxtb r3, r3
|
|
80006fa: 089b lsrs r3, r3, #2
|
|
80006fc: 33c0 adds r3, #192 @ 0xc0
|
|
80006fe: 009b lsls r3, r3, #2
|
|
8000700: 589b ldr r3, [r3, r2]
|
|
8000702: 1dfa adds r2, r7, #7
|
|
8000704: 7812 ldrb r2, [r2, #0]
|
|
8000706: 0011 movs r1, r2
|
|
8000708: 2203 movs r2, #3
|
|
800070a: 400a ands r2, r1
|
|
800070c: 00d2 lsls r2, r2, #3
|
|
800070e: 21ff movs r1, #255 @ 0xff
|
|
8000710: 4091 lsls r1, r2
|
|
8000712: 000a movs r2, r1
|
|
8000714: 43d2 mvns r2, r2
|
|
8000716: 401a ands r2, r3
|
|
8000718: 0011 movs r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
800071a: 683b ldr r3, [r7, #0]
|
|
800071c: 019b lsls r3, r3, #6
|
|
800071e: 22ff movs r2, #255 @ 0xff
|
|
8000720: 401a ands r2, r3
|
|
8000722: 1dfb adds r3, r7, #7
|
|
8000724: 781b ldrb r3, [r3, #0]
|
|
8000726: 0018 movs r0, r3
|
|
8000728: 2303 movs r3, #3
|
|
800072a: 4003 ands r3, r0
|
|
800072c: 00db lsls r3, r3, #3
|
|
800072e: 409a lsls r2, r3
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8000730: 481f ldr r0, [pc, #124] @ (80007b0 <__NVIC_SetPriority+0xd4>)
|
|
8000732: 1dfb adds r3, r7, #7
|
|
8000734: 781b ldrb r3, [r3, #0]
|
|
8000736: b25b sxtb r3, r3
|
|
8000738: 089b lsrs r3, r3, #2
|
|
800073a: 430a orrs r2, r1
|
|
800073c: 33c0 adds r3, #192 @ 0xc0
|
|
800073e: 009b lsls r3, r3, #2
|
|
8000740: 501a str r2, [r3, r0]
|
|
else
|
|
{
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
}
|
|
}
|
|
8000742: e031 b.n 80007a8 <__NVIC_SetPriority+0xcc>
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8000744: 4a1b ldr r2, [pc, #108] @ (80007b4 <__NVIC_SetPriority+0xd8>)
|
|
8000746: 1dfb adds r3, r7, #7
|
|
8000748: 781b ldrb r3, [r3, #0]
|
|
800074a: 0019 movs r1, r3
|
|
800074c: 230f movs r3, #15
|
|
800074e: 400b ands r3, r1
|
|
8000750: 3b08 subs r3, #8
|
|
8000752: 089b lsrs r3, r3, #2
|
|
8000754: 3306 adds r3, #6
|
|
8000756: 009b lsls r3, r3, #2
|
|
8000758: 18d3 adds r3, r2, r3
|
|
800075a: 3304 adds r3, #4
|
|
800075c: 681b ldr r3, [r3, #0]
|
|
800075e: 1dfa adds r2, r7, #7
|
|
8000760: 7812 ldrb r2, [r2, #0]
|
|
8000762: 0011 movs r1, r2
|
|
8000764: 2203 movs r2, #3
|
|
8000766: 400a ands r2, r1
|
|
8000768: 00d2 lsls r2, r2, #3
|
|
800076a: 21ff movs r1, #255 @ 0xff
|
|
800076c: 4091 lsls r1, r2
|
|
800076e: 000a movs r2, r1
|
|
8000770: 43d2 mvns r2, r2
|
|
8000772: 401a ands r2, r3
|
|
8000774: 0011 movs r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8000776: 683b ldr r3, [r7, #0]
|
|
8000778: 019b lsls r3, r3, #6
|
|
800077a: 22ff movs r2, #255 @ 0xff
|
|
800077c: 401a ands r2, r3
|
|
800077e: 1dfb adds r3, r7, #7
|
|
8000780: 781b ldrb r3, [r3, #0]
|
|
8000782: 0018 movs r0, r3
|
|
8000784: 2303 movs r3, #3
|
|
8000786: 4003 ands r3, r0
|
|
8000788: 00db lsls r3, r3, #3
|
|
800078a: 409a lsls r2, r3
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
800078c: 4809 ldr r0, [pc, #36] @ (80007b4 <__NVIC_SetPriority+0xd8>)
|
|
800078e: 1dfb adds r3, r7, #7
|
|
8000790: 781b ldrb r3, [r3, #0]
|
|
8000792: 001c movs r4, r3
|
|
8000794: 230f movs r3, #15
|
|
8000796: 4023 ands r3, r4
|
|
8000798: 3b08 subs r3, #8
|
|
800079a: 089b lsrs r3, r3, #2
|
|
800079c: 430a orrs r2, r1
|
|
800079e: 3306 adds r3, #6
|
|
80007a0: 009b lsls r3, r3, #2
|
|
80007a2: 18c3 adds r3, r0, r3
|
|
80007a4: 3304 adds r3, #4
|
|
80007a6: 601a str r2, [r3, #0]
|
|
}
|
|
80007a8: 46c0 nop @ (mov r8, r8)
|
|
80007aa: 46bd mov sp, r7
|
|
80007ac: b003 add sp, #12
|
|
80007ae: bd90 pop {r4, r7, pc}
|
|
80007b0: e000e100 .word 0xe000e100
|
|
80007b4: e000ed00 .word 0xe000ed00
|
|
|
|
080007b8 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80007b8: b580 push {r7, lr}
|
|
80007ba: b082 sub sp, #8
|
|
80007bc: af00 add r7, sp, #0
|
|
80007be: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80007c0: 687b ldr r3, [r7, #4]
|
|
80007c2: 1e5a subs r2, r3, #1
|
|
80007c4: 2380 movs r3, #128 @ 0x80
|
|
80007c6: 045b lsls r3, r3, #17
|
|
80007c8: 429a cmp r2, r3
|
|
80007ca: d301 bcc.n 80007d0 <SysTick_Config+0x18>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80007cc: 2301 movs r3, #1
|
|
80007ce: e010 b.n 80007f2 <SysTick_Config+0x3a>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
80007d0: 4b0a ldr r3, [pc, #40] @ (80007fc <SysTick_Config+0x44>)
|
|
80007d2: 687a ldr r2, [r7, #4]
|
|
80007d4: 3a01 subs r2, #1
|
|
80007d6: 605a str r2, [r3, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
80007d8: 2301 movs r3, #1
|
|
80007da: 425b negs r3, r3
|
|
80007dc: 2103 movs r1, #3
|
|
80007de: 0018 movs r0, r3
|
|
80007e0: f7ff ff7c bl 80006dc <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
80007e4: 4b05 ldr r3, [pc, #20] @ (80007fc <SysTick_Config+0x44>)
|
|
80007e6: 2200 movs r2, #0
|
|
80007e8: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
80007ea: 4b04 ldr r3, [pc, #16] @ (80007fc <SysTick_Config+0x44>)
|
|
80007ec: 2207 movs r2, #7
|
|
80007ee: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
80007f0: 2300 movs r3, #0
|
|
}
|
|
80007f2: 0018 movs r0, r3
|
|
80007f4: 46bd mov sp, r7
|
|
80007f6: b002 add sp, #8
|
|
80007f8: bd80 pop {r7, pc}
|
|
80007fa: 46c0 nop @ (mov r8, r8)
|
|
80007fc: e000e010 .word 0xe000e010
|
|
|
|
08000800 <HAL_NVIC_SetPriority>:
|
|
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
|
|
* no subpriority supported in Cortex M0+ based products.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000800: b580 push {r7, lr}
|
|
8000802: b084 sub sp, #16
|
|
8000804: af00 add r7, sp, #0
|
|
8000806: 60b9 str r1, [r7, #8]
|
|
8000808: 607a str r2, [r7, #4]
|
|
800080a: 210f movs r1, #15
|
|
800080c: 187b adds r3, r7, r1
|
|
800080e: 1c02 adds r2, r0, #0
|
|
8000810: 701a strb r2, [r3, #0]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(SubPriority);
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
NVIC_SetPriority(IRQn, PreemptPriority);
|
|
8000812: 68ba ldr r2, [r7, #8]
|
|
8000814: 187b adds r3, r7, r1
|
|
8000816: 781b ldrb r3, [r3, #0]
|
|
8000818: b25b sxtb r3, r3
|
|
800081a: 0011 movs r1, r2
|
|
800081c: 0018 movs r0, r3
|
|
800081e: f7ff ff5d bl 80006dc <__NVIC_SetPriority>
|
|
}
|
|
8000822: 46c0 nop @ (mov r8, r8)
|
|
8000824: 46bd mov sp, r7
|
|
8000826: b004 add sp, #16
|
|
8000828: bd80 pop {r7, pc}
|
|
|
|
0800082a <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
800082a: b580 push {r7, lr}
|
|
800082c: b082 sub sp, #8
|
|
800082e: af00 add r7, sp, #0
|
|
8000830: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000832: 687b ldr r3, [r7, #4]
|
|
8000834: 0018 movs r0, r3
|
|
8000836: f7ff ffbf bl 80007b8 <SysTick_Config>
|
|
800083a: 0003 movs r3, r0
|
|
}
|
|
800083c: 0018 movs r0, r3
|
|
800083e: 46bd mov sp, r7
|
|
8000840: b002 add sp, #8
|
|
8000842: bd80 pop {r7, pc}
|
|
|
|
08000844 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8000844: b580 push {r7, lr}
|
|
8000846: b086 sub sp, #24
|
|
8000848: af00 add r7, sp, #0
|
|
800084a: 6078 str r0, [r7, #4]
|
|
800084c: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
800084e: 2300 movs r3, #0
|
|
8000850: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000852: e147 b.n 8000ae4 <HAL_GPIO_Init+0x2a0>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
8000854: 683b ldr r3, [r7, #0]
|
|
8000856: 681b ldr r3, [r3, #0]
|
|
8000858: 2101 movs r1, #1
|
|
800085a: 697a ldr r2, [r7, #20]
|
|
800085c: 4091 lsls r1, r2
|
|
800085e: 000a movs r2, r1
|
|
8000860: 4013 ands r3, r2
|
|
8000862: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8000864: 68fb ldr r3, [r7, #12]
|
|
8000866: 2b00 cmp r3, #0
|
|
8000868: d100 bne.n 800086c <HAL_GPIO_Init+0x28>
|
|
800086a: e138 b.n 8000ade <HAL_GPIO_Init+0x29a>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
800086c: 683b ldr r3, [r7, #0]
|
|
800086e: 685b ldr r3, [r3, #4]
|
|
8000870: 2203 movs r2, #3
|
|
8000872: 4013 ands r3, r2
|
|
8000874: 2b01 cmp r3, #1
|
|
8000876: d005 beq.n 8000884 <HAL_GPIO_Init+0x40>
|
|
8000878: 683b ldr r3, [r7, #0]
|
|
800087a: 685b ldr r3, [r3, #4]
|
|
800087c: 2203 movs r2, #3
|
|
800087e: 4013 ands r3, r2
|
|
8000880: 2b02 cmp r3, #2
|
|
8000882: d130 bne.n 80008e6 <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8000884: 687b ldr r3, [r7, #4]
|
|
8000886: 689b ldr r3, [r3, #8]
|
|
8000888: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
800088a: 697b ldr r3, [r7, #20]
|
|
800088c: 005b lsls r3, r3, #1
|
|
800088e: 2203 movs r2, #3
|
|
8000890: 409a lsls r2, r3
|
|
8000892: 0013 movs r3, r2
|
|
8000894: 43da mvns r2, r3
|
|
8000896: 693b ldr r3, [r7, #16]
|
|
8000898: 4013 ands r3, r2
|
|
800089a: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
800089c: 683b ldr r3, [r7, #0]
|
|
800089e: 68da ldr r2, [r3, #12]
|
|
80008a0: 697b ldr r3, [r7, #20]
|
|
80008a2: 005b lsls r3, r3, #1
|
|
80008a4: 409a lsls r2, r3
|
|
80008a6: 0013 movs r3, r2
|
|
80008a8: 693a ldr r2, [r7, #16]
|
|
80008aa: 4313 orrs r3, r2
|
|
80008ac: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
80008ae: 687b ldr r3, [r7, #4]
|
|
80008b0: 693a ldr r2, [r7, #16]
|
|
80008b2: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
80008b4: 687b ldr r3, [r7, #4]
|
|
80008b6: 685b ldr r3, [r3, #4]
|
|
80008b8: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
80008ba: 2201 movs r2, #1
|
|
80008bc: 697b ldr r3, [r7, #20]
|
|
80008be: 409a lsls r2, r3
|
|
80008c0: 0013 movs r3, r2
|
|
80008c2: 43da mvns r2, r3
|
|
80008c4: 693b ldr r3, [r7, #16]
|
|
80008c6: 4013 ands r3, r2
|
|
80008c8: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
80008ca: 683b ldr r3, [r7, #0]
|
|
80008cc: 685b ldr r3, [r3, #4]
|
|
80008ce: 091b lsrs r3, r3, #4
|
|
80008d0: 2201 movs r2, #1
|
|
80008d2: 401a ands r2, r3
|
|
80008d4: 697b ldr r3, [r7, #20]
|
|
80008d6: 409a lsls r2, r3
|
|
80008d8: 0013 movs r3, r2
|
|
80008da: 693a ldr r2, [r7, #16]
|
|
80008dc: 4313 orrs r3, r2
|
|
80008de: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
80008e0: 687b ldr r3, [r7, #4]
|
|
80008e2: 693a ldr r2, [r7, #16]
|
|
80008e4: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
80008e6: 683b ldr r3, [r7, #0]
|
|
80008e8: 685b ldr r3, [r3, #4]
|
|
80008ea: 2203 movs r2, #3
|
|
80008ec: 4013 ands r3, r2
|
|
80008ee: 2b03 cmp r3, #3
|
|
80008f0: d017 beq.n 8000922 <HAL_GPIO_Init+0xde>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
80008f2: 687b ldr r3, [r7, #4]
|
|
80008f4: 68db ldr r3, [r3, #12]
|
|
80008f6: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
|
80008f8: 697b ldr r3, [r7, #20]
|
|
80008fa: 005b lsls r3, r3, #1
|
|
80008fc: 2203 movs r2, #3
|
|
80008fe: 409a lsls r2, r3
|
|
8000900: 0013 movs r3, r2
|
|
8000902: 43da mvns r2, r3
|
|
8000904: 693b ldr r3, [r7, #16]
|
|
8000906: 4013 ands r3, r2
|
|
8000908: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
|
800090a: 683b ldr r3, [r7, #0]
|
|
800090c: 689a ldr r2, [r3, #8]
|
|
800090e: 697b ldr r3, [r7, #20]
|
|
8000910: 005b lsls r3, r3, #1
|
|
8000912: 409a lsls r2, r3
|
|
8000914: 0013 movs r3, r2
|
|
8000916: 693a ldr r2, [r7, #16]
|
|
8000918: 4313 orrs r3, r2
|
|
800091a: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
800091c: 687b ldr r3, [r7, #4]
|
|
800091e: 693a ldr r2, [r7, #16]
|
|
8000920: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8000922: 683b ldr r3, [r7, #0]
|
|
8000924: 685b ldr r3, [r3, #4]
|
|
8000926: 2203 movs r2, #3
|
|
8000928: 4013 ands r3, r2
|
|
800092a: 2b02 cmp r3, #2
|
|
800092c: d123 bne.n 8000976 <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
800092e: 697b ldr r3, [r7, #20]
|
|
8000930: 08da lsrs r2, r3, #3
|
|
8000932: 687b ldr r3, [r7, #4]
|
|
8000934: 3208 adds r2, #8
|
|
8000936: 0092 lsls r2, r2, #2
|
|
8000938: 58d3 ldr r3, [r2, r3]
|
|
800093a: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
800093c: 697b ldr r3, [r7, #20]
|
|
800093e: 2207 movs r2, #7
|
|
8000940: 4013 ands r3, r2
|
|
8000942: 009b lsls r3, r3, #2
|
|
8000944: 220f movs r2, #15
|
|
8000946: 409a lsls r2, r3
|
|
8000948: 0013 movs r3, r2
|
|
800094a: 43da mvns r2, r3
|
|
800094c: 693b ldr r3, [r7, #16]
|
|
800094e: 4013 ands r3, r2
|
|
8000950: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8000952: 683b ldr r3, [r7, #0]
|
|
8000954: 691a ldr r2, [r3, #16]
|
|
8000956: 697b ldr r3, [r7, #20]
|
|
8000958: 2107 movs r1, #7
|
|
800095a: 400b ands r3, r1
|
|
800095c: 009b lsls r3, r3, #2
|
|
800095e: 409a lsls r2, r3
|
|
8000960: 0013 movs r3, r2
|
|
8000962: 693a ldr r2, [r7, #16]
|
|
8000964: 4313 orrs r3, r2
|
|
8000966: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
8000968: 697b ldr r3, [r7, #20]
|
|
800096a: 08da lsrs r2, r3, #3
|
|
800096c: 687b ldr r3, [r7, #4]
|
|
800096e: 3208 adds r2, #8
|
|
8000970: 0092 lsls r2, r2, #2
|
|
8000972: 6939 ldr r1, [r7, #16]
|
|
8000974: 50d1 str r1, [r2, r3]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8000976: 687b ldr r3, [r7, #4]
|
|
8000978: 681b ldr r3, [r3, #0]
|
|
800097a: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
800097c: 697b ldr r3, [r7, #20]
|
|
800097e: 005b lsls r3, r3, #1
|
|
8000980: 2203 movs r2, #3
|
|
8000982: 409a lsls r2, r3
|
|
8000984: 0013 movs r3, r2
|
|
8000986: 43da mvns r2, r3
|
|
8000988: 693b ldr r3, [r7, #16]
|
|
800098a: 4013 ands r3, r2
|
|
800098c: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
800098e: 683b ldr r3, [r7, #0]
|
|
8000990: 685b ldr r3, [r3, #4]
|
|
8000992: 2203 movs r2, #3
|
|
8000994: 401a ands r2, r3
|
|
8000996: 697b ldr r3, [r7, #20]
|
|
8000998: 005b lsls r3, r3, #1
|
|
800099a: 409a lsls r2, r3
|
|
800099c: 0013 movs r3, r2
|
|
800099e: 693a ldr r2, [r7, #16]
|
|
80009a0: 4313 orrs r3, r2
|
|
80009a2: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
80009a4: 687b ldr r3, [r7, #4]
|
|
80009a6: 693a ldr r2, [r7, #16]
|
|
80009a8: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
80009aa: 683b ldr r3, [r7, #0]
|
|
80009ac: 685a ldr r2, [r3, #4]
|
|
80009ae: 23c0 movs r3, #192 @ 0xc0
|
|
80009b0: 029b lsls r3, r3, #10
|
|
80009b2: 4013 ands r3, r2
|
|
80009b4: d100 bne.n 80009b8 <HAL_GPIO_Init+0x174>
|
|
80009b6: e092 b.n 8000ade <HAL_GPIO_Init+0x29a>
|
|
{
|
|
temp = EXTI->EXTICR[position >> 2u];
|
|
80009b8: 4a50 ldr r2, [pc, #320] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
80009ba: 697b ldr r3, [r7, #20]
|
|
80009bc: 089b lsrs r3, r3, #2
|
|
80009be: 3318 adds r3, #24
|
|
80009c0: 009b lsls r3, r3, #2
|
|
80009c2: 589b ldr r3, [r3, r2]
|
|
80009c4: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
|
|
80009c6: 697b ldr r3, [r7, #20]
|
|
80009c8: 2203 movs r2, #3
|
|
80009ca: 4013 ands r3, r2
|
|
80009cc: 00db lsls r3, r3, #3
|
|
80009ce: 220f movs r2, #15
|
|
80009d0: 409a lsls r2, r3
|
|
80009d2: 0013 movs r3, r2
|
|
80009d4: 43da mvns r2, r3
|
|
80009d6: 693b ldr r3, [r7, #16]
|
|
80009d8: 4013 ands r3, r2
|
|
80009da: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
|
|
80009dc: 687a ldr r2, [r7, #4]
|
|
80009de: 23a0 movs r3, #160 @ 0xa0
|
|
80009e0: 05db lsls r3, r3, #23
|
|
80009e2: 429a cmp r2, r3
|
|
80009e4: d013 beq.n 8000a0e <HAL_GPIO_Init+0x1ca>
|
|
80009e6: 687b ldr r3, [r7, #4]
|
|
80009e8: 4a45 ldr r2, [pc, #276] @ (8000b00 <HAL_GPIO_Init+0x2bc>)
|
|
80009ea: 4293 cmp r3, r2
|
|
80009ec: d00d beq.n 8000a0a <HAL_GPIO_Init+0x1c6>
|
|
80009ee: 687b ldr r3, [r7, #4]
|
|
80009f0: 4a44 ldr r2, [pc, #272] @ (8000b04 <HAL_GPIO_Init+0x2c0>)
|
|
80009f2: 4293 cmp r3, r2
|
|
80009f4: d007 beq.n 8000a06 <HAL_GPIO_Init+0x1c2>
|
|
80009f6: 687b ldr r3, [r7, #4]
|
|
80009f8: 4a43 ldr r2, [pc, #268] @ (8000b08 <HAL_GPIO_Init+0x2c4>)
|
|
80009fa: 4293 cmp r3, r2
|
|
80009fc: d101 bne.n 8000a02 <HAL_GPIO_Init+0x1be>
|
|
80009fe: 2303 movs r3, #3
|
|
8000a00: e006 b.n 8000a10 <HAL_GPIO_Init+0x1cc>
|
|
8000a02: 2305 movs r3, #5
|
|
8000a04: e004 b.n 8000a10 <HAL_GPIO_Init+0x1cc>
|
|
8000a06: 2302 movs r3, #2
|
|
8000a08: e002 b.n 8000a10 <HAL_GPIO_Init+0x1cc>
|
|
8000a0a: 2301 movs r3, #1
|
|
8000a0c: e000 b.n 8000a10 <HAL_GPIO_Init+0x1cc>
|
|
8000a0e: 2300 movs r3, #0
|
|
8000a10: 697a ldr r2, [r7, #20]
|
|
8000a12: 2103 movs r1, #3
|
|
8000a14: 400a ands r2, r1
|
|
8000a16: 00d2 lsls r2, r2, #3
|
|
8000a18: 4093 lsls r3, r2
|
|
8000a1a: 693a ldr r2, [r7, #16]
|
|
8000a1c: 4313 orrs r3, r2
|
|
8000a1e: 613b str r3, [r7, #16]
|
|
EXTI->EXTICR[position >> 2u] = temp;
|
|
8000a20: 4936 ldr r1, [pc, #216] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000a22: 697b ldr r3, [r7, #20]
|
|
8000a24: 089b lsrs r3, r3, #2
|
|
8000a26: 3318 adds r3, #24
|
|
8000a28: 009b lsls r3, r3, #2
|
|
8000a2a: 693a ldr r2, [r7, #16]
|
|
8000a2c: 505a str r2, [r3, r1]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
8000a2e: 4b33 ldr r3, [pc, #204] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000a30: 681b ldr r3, [r3, #0]
|
|
8000a32: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000a34: 68fb ldr r3, [r7, #12]
|
|
8000a36: 43da mvns r2, r3
|
|
8000a38: 693b ldr r3, [r7, #16]
|
|
8000a3a: 4013 ands r3, r2
|
|
8000a3c: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
8000a3e: 683b ldr r3, [r7, #0]
|
|
8000a40: 685a ldr r2, [r3, #4]
|
|
8000a42: 2380 movs r3, #128 @ 0x80
|
|
8000a44: 035b lsls r3, r3, #13
|
|
8000a46: 4013 ands r3, r2
|
|
8000a48: d003 beq.n 8000a52 <HAL_GPIO_Init+0x20e>
|
|
{
|
|
temp |= iocurrent;
|
|
8000a4a: 693a ldr r2, [r7, #16]
|
|
8000a4c: 68fb ldr r3, [r7, #12]
|
|
8000a4e: 4313 orrs r3, r2
|
|
8000a50: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
8000a52: 4b2a ldr r3, [pc, #168] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000a54: 693a ldr r2, [r7, #16]
|
|
8000a56: 601a str r2, [r3, #0]
|
|
|
|
temp = EXTI->FTSR1;
|
|
8000a58: 4b28 ldr r3, [pc, #160] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000a5a: 685b ldr r3, [r3, #4]
|
|
8000a5c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000a5e: 68fb ldr r3, [r7, #12]
|
|
8000a60: 43da mvns r2, r3
|
|
8000a62: 693b ldr r3, [r7, #16]
|
|
8000a64: 4013 ands r3, r2
|
|
8000a66: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
8000a68: 683b ldr r3, [r7, #0]
|
|
8000a6a: 685a ldr r2, [r3, #4]
|
|
8000a6c: 2380 movs r3, #128 @ 0x80
|
|
8000a6e: 039b lsls r3, r3, #14
|
|
8000a70: 4013 ands r3, r2
|
|
8000a72: d003 beq.n 8000a7c <HAL_GPIO_Init+0x238>
|
|
{
|
|
temp |= iocurrent;
|
|
8000a74: 693a ldr r2, [r7, #16]
|
|
8000a76: 68fb ldr r3, [r7, #12]
|
|
8000a78: 4313 orrs r3, r2
|
|
8000a7a: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8000a7c: 4b1f ldr r3, [pc, #124] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000a7e: 693a ldr r2, [r7, #16]
|
|
8000a80: 605a str r2, [r3, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->EMR1;
|
|
8000a82: 4a1e ldr r2, [pc, #120] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000a84: 2384 movs r3, #132 @ 0x84
|
|
8000a86: 58d3 ldr r3, [r2, r3]
|
|
8000a88: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000a8a: 68fb ldr r3, [r7, #12]
|
|
8000a8c: 43da mvns r2, r3
|
|
8000a8e: 693b ldr r3, [r7, #16]
|
|
8000a90: 4013 ands r3, r2
|
|
8000a92: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8000a94: 683b ldr r3, [r7, #0]
|
|
8000a96: 685a ldr r2, [r3, #4]
|
|
8000a98: 2380 movs r3, #128 @ 0x80
|
|
8000a9a: 029b lsls r3, r3, #10
|
|
8000a9c: 4013 ands r3, r2
|
|
8000a9e: d003 beq.n 8000aa8 <HAL_GPIO_Init+0x264>
|
|
{
|
|
temp |= iocurrent;
|
|
8000aa0: 693a ldr r2, [r7, #16]
|
|
8000aa2: 68fb ldr r3, [r7, #12]
|
|
8000aa4: 4313 orrs r3, r2
|
|
8000aa6: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
8000aa8: 4914 ldr r1, [pc, #80] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000aaa: 2284 movs r2, #132 @ 0x84
|
|
8000aac: 693b ldr r3, [r7, #16]
|
|
8000aae: 508b str r3, [r1, r2]
|
|
|
|
temp = EXTI->IMR1;
|
|
8000ab0: 4a12 ldr r2, [pc, #72] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000ab2: 2380 movs r3, #128 @ 0x80
|
|
8000ab4: 58d3 ldr r3, [r2, r3]
|
|
8000ab6: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000ab8: 68fb ldr r3, [r7, #12]
|
|
8000aba: 43da mvns r2, r3
|
|
8000abc: 693b ldr r3, [r7, #16]
|
|
8000abe: 4013 ands r3, r2
|
|
8000ac0: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
8000ac2: 683b ldr r3, [r7, #0]
|
|
8000ac4: 685a ldr r2, [r3, #4]
|
|
8000ac6: 2380 movs r3, #128 @ 0x80
|
|
8000ac8: 025b lsls r3, r3, #9
|
|
8000aca: 4013 ands r3, r2
|
|
8000acc: d003 beq.n 8000ad6 <HAL_GPIO_Init+0x292>
|
|
{
|
|
temp |= iocurrent;
|
|
8000ace: 693a ldr r2, [r7, #16]
|
|
8000ad0: 68fb ldr r3, [r7, #12]
|
|
8000ad2: 4313 orrs r3, r2
|
|
8000ad4: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8000ad6: 4909 ldr r1, [pc, #36] @ (8000afc <HAL_GPIO_Init+0x2b8>)
|
|
8000ad8: 2280 movs r2, #128 @ 0x80
|
|
8000ada: 693b ldr r3, [r7, #16]
|
|
8000adc: 508b str r3, [r1, r2]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8000ade: 697b ldr r3, [r7, #20]
|
|
8000ae0: 3301 adds r3, #1
|
|
8000ae2: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000ae4: 683b ldr r3, [r7, #0]
|
|
8000ae6: 681a ldr r2, [r3, #0]
|
|
8000ae8: 697b ldr r3, [r7, #20]
|
|
8000aea: 40da lsrs r2, r3
|
|
8000aec: 1e13 subs r3, r2, #0
|
|
8000aee: d000 beq.n 8000af2 <HAL_GPIO_Init+0x2ae>
|
|
8000af0: e6b0 b.n 8000854 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8000af2: 46c0 nop @ (mov r8, r8)
|
|
8000af4: 46c0 nop @ (mov r8, r8)
|
|
8000af6: 46bd mov sp, r7
|
|
8000af8: b006 add sp, #24
|
|
8000afa: bd80 pop {r7, pc}
|
|
8000afc: 40021800 .word 0x40021800
|
|
8000b00: 50000400 .word 0x50000400
|
|
8000b04: 50000800 .word 0x50000800
|
|
8000b08: 50000c00 .word 0x50000c00
|
|
|
|
08000b0c <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 6 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
8000b0c: b580 push {r7, lr}
|
|
8000b0e: b084 sub sp, #16
|
|
8000b10: af00 add r7, sp, #0
|
|
8000b12: 6078 str r0, [r7, #4]
|
|
uint32_t wait_loop_index;
|
|
|
|
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
|
|
|
|
/* Modify voltage scaling range */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
|
|
8000b14: 4b19 ldr r3, [pc, #100] @ (8000b7c <HAL_PWREx_ControlVoltageScaling+0x70>)
|
|
8000b16: 681b ldr r3, [r3, #0]
|
|
8000b18: 4a19 ldr r2, [pc, #100] @ (8000b80 <HAL_PWREx_ControlVoltageScaling+0x74>)
|
|
8000b1a: 4013 ands r3, r2
|
|
8000b1c: 0019 movs r1, r3
|
|
8000b1e: 4b17 ldr r3, [pc, #92] @ (8000b7c <HAL_PWREx_ControlVoltageScaling+0x70>)
|
|
8000b20: 687a ldr r2, [r7, #4]
|
|
8000b22: 430a orrs r2, r1
|
|
8000b24: 601a str r2, [r3, #0]
|
|
|
|
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8000b26: 687a ldr r2, [r7, #4]
|
|
8000b28: 2380 movs r3, #128 @ 0x80
|
|
8000b2a: 009b lsls r3, r3, #2
|
|
8000b2c: 429a cmp r2, r3
|
|
8000b2e: d11f bne.n 8000b70 <HAL_PWREx_ControlVoltageScaling+0x64>
|
|
{
|
|
/* Set timeout value */
|
|
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
|
|
8000b30: 4b14 ldr r3, [pc, #80] @ (8000b84 <HAL_PWREx_ControlVoltageScaling+0x78>)
|
|
8000b32: 681a ldr r2, [r3, #0]
|
|
8000b34: 0013 movs r3, r2
|
|
8000b36: 005b lsls r3, r3, #1
|
|
8000b38: 189b adds r3, r3, r2
|
|
8000b3a: 005b lsls r3, r3, #1
|
|
8000b3c: 4912 ldr r1, [pc, #72] @ (8000b88 <HAL_PWREx_ControlVoltageScaling+0x7c>)
|
|
8000b3e: 0018 movs r0, r3
|
|
8000b40: f7ff fade bl 8000100 <__udivsi3>
|
|
8000b44: 0003 movs r3, r0
|
|
8000b46: 3301 adds r3, #1
|
|
8000b48: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until VOSF is reset */
|
|
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8000b4a: e008 b.n 8000b5e <HAL_PWREx_ControlVoltageScaling+0x52>
|
|
{
|
|
if (wait_loop_index != 0U)
|
|
8000b4c: 68fb ldr r3, [r7, #12]
|
|
8000b4e: 2b00 cmp r3, #0
|
|
8000b50: d003 beq.n 8000b5a <HAL_PWREx_ControlVoltageScaling+0x4e>
|
|
{
|
|
wait_loop_index--;
|
|
8000b52: 68fb ldr r3, [r7, #12]
|
|
8000b54: 3b01 subs r3, #1
|
|
8000b56: 60fb str r3, [r7, #12]
|
|
8000b58: e001 b.n 8000b5e <HAL_PWREx_ControlVoltageScaling+0x52>
|
|
}
|
|
else
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000b5a: 2303 movs r3, #3
|
|
8000b5c: e009 b.n 8000b72 <HAL_PWREx_ControlVoltageScaling+0x66>
|
|
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8000b5e: 4b07 ldr r3, [pc, #28] @ (8000b7c <HAL_PWREx_ControlVoltageScaling+0x70>)
|
|
8000b60: 695a ldr r2, [r3, #20]
|
|
8000b62: 2380 movs r3, #128 @ 0x80
|
|
8000b64: 00db lsls r3, r3, #3
|
|
8000b66: 401a ands r2, r3
|
|
8000b68: 2380 movs r3, #128 @ 0x80
|
|
8000b6a: 00db lsls r3, r3, #3
|
|
8000b6c: 429a cmp r2, r3
|
|
8000b6e: d0ed beq.n 8000b4c <HAL_PWREx_ControlVoltageScaling+0x40>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8000b70: 2300 movs r3, #0
|
|
}
|
|
8000b72: 0018 movs r0, r3
|
|
8000b74: 46bd mov sp, r7
|
|
8000b76: b004 add sp, #16
|
|
8000b78: bd80 pop {r7, pc}
|
|
8000b7a: 46c0 nop @ (mov r8, r8)
|
|
8000b7c: 40007000 .word 0x40007000
|
|
8000b80: fffff9ff .word 0xfffff9ff
|
|
8000b84: 20000000 .word 0x20000000
|
|
8000b88: 000f4240 .word 0x000f4240
|
|
|
|
08000b8c <HAL_RCC_OscConfig>:
|
|
* supported by this function. User should request a transition to LSE Off
|
|
* first and then to LSE On or LSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8000b8c: b580 push {r7, lr}
|
|
8000b8e: b088 sub sp, #32
|
|
8000b90: af00 add r7, sp, #0
|
|
8000b92: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t temp_sysclksrc;
|
|
uint32_t temp_pllckcfg;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8000b94: 687b ldr r3, [r7, #4]
|
|
8000b96: 2b00 cmp r3, #0
|
|
8000b98: d101 bne.n 8000b9e <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8000b9a: 2301 movs r3, #1
|
|
8000b9c: e2f3 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8000b9e: 687b ldr r3, [r7, #4]
|
|
8000ba0: 681b ldr r3, [r3, #0]
|
|
8000ba2: 2201 movs r2, #1
|
|
8000ba4: 4013 ands r3, r2
|
|
8000ba6: d100 bne.n 8000baa <HAL_RCC_OscConfig+0x1e>
|
|
8000ba8: e07c b.n 8000ca4 <HAL_RCC_OscConfig+0x118>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8000baa: 4bc3 ldr r3, [pc, #780] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000bac: 689b ldr r3, [r3, #8]
|
|
8000bae: 2238 movs r2, #56 @ 0x38
|
|
8000bb0: 4013 ands r3, r2
|
|
8000bb2: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8000bb4: 4bc0 ldr r3, [pc, #768] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000bb6: 68db ldr r3, [r3, #12]
|
|
8000bb8: 2203 movs r2, #3
|
|
8000bba: 4013 ands r3, r2
|
|
8000bbc: 617b str r3, [r7, #20]
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
|
|
8000bbe: 69bb ldr r3, [r7, #24]
|
|
8000bc0: 2b10 cmp r3, #16
|
|
8000bc2: d102 bne.n 8000bca <HAL_RCC_OscConfig+0x3e>
|
|
8000bc4: 697b ldr r3, [r7, #20]
|
|
8000bc6: 2b03 cmp r3, #3
|
|
8000bc8: d002 beq.n 8000bd0 <HAL_RCC_OscConfig+0x44>
|
|
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
|
|
8000bca: 69bb ldr r3, [r7, #24]
|
|
8000bcc: 2b08 cmp r3, #8
|
|
8000bce: d10b bne.n 8000be8 <HAL_RCC_OscConfig+0x5c>
|
|
{
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000bd0: 4bb9 ldr r3, [pc, #740] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000bd2: 681a ldr r2, [r3, #0]
|
|
8000bd4: 2380 movs r3, #128 @ 0x80
|
|
8000bd6: 029b lsls r3, r3, #10
|
|
8000bd8: 4013 ands r3, r2
|
|
8000bda: d062 beq.n 8000ca2 <HAL_RCC_OscConfig+0x116>
|
|
8000bdc: 687b ldr r3, [r7, #4]
|
|
8000bde: 685b ldr r3, [r3, #4]
|
|
8000be0: 2b00 cmp r3, #0
|
|
8000be2: d15e bne.n 8000ca2 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_ERROR;
|
|
8000be4: 2301 movs r3, #1
|
|
8000be6: e2ce b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8000be8: 687b ldr r3, [r7, #4]
|
|
8000bea: 685a ldr r2, [r3, #4]
|
|
8000bec: 2380 movs r3, #128 @ 0x80
|
|
8000bee: 025b lsls r3, r3, #9
|
|
8000bf0: 429a cmp r2, r3
|
|
8000bf2: d107 bne.n 8000c04 <HAL_RCC_OscConfig+0x78>
|
|
8000bf4: 4bb0 ldr r3, [pc, #704] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000bf6: 681a ldr r2, [r3, #0]
|
|
8000bf8: 4baf ldr r3, [pc, #700] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000bfa: 2180 movs r1, #128 @ 0x80
|
|
8000bfc: 0249 lsls r1, r1, #9
|
|
8000bfe: 430a orrs r2, r1
|
|
8000c00: 601a str r2, [r3, #0]
|
|
8000c02: e020 b.n 8000c46 <HAL_RCC_OscConfig+0xba>
|
|
8000c04: 687b ldr r3, [r7, #4]
|
|
8000c06: 685a ldr r2, [r3, #4]
|
|
8000c08: 23a0 movs r3, #160 @ 0xa0
|
|
8000c0a: 02db lsls r3, r3, #11
|
|
8000c0c: 429a cmp r2, r3
|
|
8000c0e: d10e bne.n 8000c2e <HAL_RCC_OscConfig+0xa2>
|
|
8000c10: 4ba9 ldr r3, [pc, #676] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c12: 681a ldr r2, [r3, #0]
|
|
8000c14: 4ba8 ldr r3, [pc, #672] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c16: 2180 movs r1, #128 @ 0x80
|
|
8000c18: 02c9 lsls r1, r1, #11
|
|
8000c1a: 430a orrs r2, r1
|
|
8000c1c: 601a str r2, [r3, #0]
|
|
8000c1e: 4ba6 ldr r3, [pc, #664] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c20: 681a ldr r2, [r3, #0]
|
|
8000c22: 4ba5 ldr r3, [pc, #660] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c24: 2180 movs r1, #128 @ 0x80
|
|
8000c26: 0249 lsls r1, r1, #9
|
|
8000c28: 430a orrs r2, r1
|
|
8000c2a: 601a str r2, [r3, #0]
|
|
8000c2c: e00b b.n 8000c46 <HAL_RCC_OscConfig+0xba>
|
|
8000c2e: 4ba2 ldr r3, [pc, #648] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c30: 681a ldr r2, [r3, #0]
|
|
8000c32: 4ba1 ldr r3, [pc, #644] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c34: 49a1 ldr r1, [pc, #644] @ (8000ebc <HAL_RCC_OscConfig+0x330>)
|
|
8000c36: 400a ands r2, r1
|
|
8000c38: 601a str r2, [r3, #0]
|
|
8000c3a: 4b9f ldr r3, [pc, #636] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c3c: 681a ldr r2, [r3, #0]
|
|
8000c3e: 4b9e ldr r3, [pc, #632] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c40: 499f ldr r1, [pc, #636] @ (8000ec0 <HAL_RCC_OscConfig+0x334>)
|
|
8000c42: 400a ands r2, r1
|
|
8000c44: 601a str r2, [r3, #0]
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8000c46: 687b ldr r3, [r7, #4]
|
|
8000c48: 685b ldr r3, [r3, #4]
|
|
8000c4a: 2b00 cmp r3, #0
|
|
8000c4c: d014 beq.n 8000c78 <HAL_RCC_OscConfig+0xec>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000c4e: f7ff fd3b bl 80006c8 <HAL_GetTick>
|
|
8000c52: 0003 movs r3, r0
|
|
8000c54: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8000c56: e008 b.n 8000c6a <HAL_RCC_OscConfig+0xde>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000c58: f7ff fd36 bl 80006c8 <HAL_GetTick>
|
|
8000c5c: 0002 movs r2, r0
|
|
8000c5e: 693b ldr r3, [r7, #16]
|
|
8000c60: 1ad3 subs r3, r2, r3
|
|
8000c62: 2b64 cmp r3, #100 @ 0x64
|
|
8000c64: d901 bls.n 8000c6a <HAL_RCC_OscConfig+0xde>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000c66: 2303 movs r3, #3
|
|
8000c68: e28d b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8000c6a: 4b93 ldr r3, [pc, #588] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c6c: 681a ldr r2, [r3, #0]
|
|
8000c6e: 2380 movs r3, #128 @ 0x80
|
|
8000c70: 029b lsls r3, r3, #10
|
|
8000c72: 4013 ands r3, r2
|
|
8000c74: d0f0 beq.n 8000c58 <HAL_RCC_OscConfig+0xcc>
|
|
8000c76: e015 b.n 8000ca4 <HAL_RCC_OscConfig+0x118>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000c78: f7ff fd26 bl 80006c8 <HAL_GetTick>
|
|
8000c7c: 0003 movs r3, r0
|
|
8000c7e: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8000c80: e008 b.n 8000c94 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000c82: f7ff fd21 bl 80006c8 <HAL_GetTick>
|
|
8000c86: 0002 movs r2, r0
|
|
8000c88: 693b ldr r3, [r7, #16]
|
|
8000c8a: 1ad3 subs r3, r2, r3
|
|
8000c8c: 2b64 cmp r3, #100 @ 0x64
|
|
8000c8e: d901 bls.n 8000c94 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000c90: 2303 movs r3, #3
|
|
8000c92: e278 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8000c94: 4b88 ldr r3, [pc, #544] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000c96: 681a ldr r2, [r3, #0]
|
|
8000c98: 2380 movs r3, #128 @ 0x80
|
|
8000c9a: 029b lsls r3, r3, #10
|
|
8000c9c: 4013 ands r3, r2
|
|
8000c9e: d1f0 bne.n 8000c82 <HAL_RCC_OscConfig+0xf6>
|
|
8000ca0: e000 b.n 8000ca4 <HAL_RCC_OscConfig+0x118>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000ca2: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8000ca4: 687b ldr r3, [r7, #4]
|
|
8000ca6: 681b ldr r3, [r3, #0]
|
|
8000ca8: 2202 movs r2, #2
|
|
8000caa: 4013 ands r3, r2
|
|
8000cac: d100 bne.n 8000cb0 <HAL_RCC_OscConfig+0x124>
|
|
8000cae: e099 b.n 8000de4 <HAL_RCC_OscConfig+0x258>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
|
|
|
|
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8000cb0: 4b81 ldr r3, [pc, #516] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000cb2: 689b ldr r3, [r3, #8]
|
|
8000cb4: 2238 movs r2, #56 @ 0x38
|
|
8000cb6: 4013 ands r3, r2
|
|
8000cb8: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8000cba: 4b7f ldr r3, [pc, #508] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000cbc: 68db ldr r3, [r3, #12]
|
|
8000cbe: 2203 movs r2, #3
|
|
8000cc0: 4013 ands r3, r2
|
|
8000cc2: 617b str r3, [r7, #20]
|
|
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
|
|
8000cc4: 69bb ldr r3, [r7, #24]
|
|
8000cc6: 2b10 cmp r3, #16
|
|
8000cc8: d102 bne.n 8000cd0 <HAL_RCC_OscConfig+0x144>
|
|
8000cca: 697b ldr r3, [r7, #20]
|
|
8000ccc: 2b02 cmp r3, #2
|
|
8000cce: d002 beq.n 8000cd6 <HAL_RCC_OscConfig+0x14a>
|
|
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
|
|
8000cd0: 69bb ldr r3, [r7, #24]
|
|
8000cd2: 2b00 cmp r3, #0
|
|
8000cd4: d135 bne.n 8000d42 <HAL_RCC_OscConfig+0x1b6>
|
|
{
|
|
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8000cd6: 4b78 ldr r3, [pc, #480] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000cd8: 681a ldr r2, [r3, #0]
|
|
8000cda: 2380 movs r3, #128 @ 0x80
|
|
8000cdc: 00db lsls r3, r3, #3
|
|
8000cde: 4013 ands r3, r2
|
|
8000ce0: d005 beq.n 8000cee <HAL_RCC_OscConfig+0x162>
|
|
8000ce2: 687b ldr r3, [r7, #4]
|
|
8000ce4: 68db ldr r3, [r3, #12]
|
|
8000ce6: 2b00 cmp r3, #0
|
|
8000ce8: d101 bne.n 8000cee <HAL_RCC_OscConfig+0x162>
|
|
{
|
|
return HAL_ERROR;
|
|
8000cea: 2301 movs r3, #1
|
|
8000cec: e24b b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000cee: 4b72 ldr r3, [pc, #456] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000cf0: 685b ldr r3, [r3, #4]
|
|
8000cf2: 4a74 ldr r2, [pc, #464] @ (8000ec4 <HAL_RCC_OscConfig+0x338>)
|
|
8000cf4: 4013 ands r3, r2
|
|
8000cf6: 0019 movs r1, r3
|
|
8000cf8: 687b ldr r3, [r7, #4]
|
|
8000cfa: 695b ldr r3, [r3, #20]
|
|
8000cfc: 021a lsls r2, r3, #8
|
|
8000cfe: 4b6e ldr r3, [pc, #440] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d00: 430a orrs r2, r1
|
|
8000d02: 605a str r2, [r3, #4]
|
|
|
|
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8000d04: 69bb ldr r3, [r7, #24]
|
|
8000d06: 2b00 cmp r3, #0
|
|
8000d08: d112 bne.n 8000d30 <HAL_RCC_OscConfig+0x1a4>
|
|
{
|
|
/* Adjust the HSI16 division factor */
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
8000d0a: 4b6b ldr r3, [pc, #428] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d0c: 681b ldr r3, [r3, #0]
|
|
8000d0e: 4a6e ldr r2, [pc, #440] @ (8000ec8 <HAL_RCC_OscConfig+0x33c>)
|
|
8000d10: 4013 ands r3, r2
|
|
8000d12: 0019 movs r1, r3
|
|
8000d14: 687b ldr r3, [r7, #4]
|
|
8000d16: 691a ldr r2, [r3, #16]
|
|
8000d18: 4b67 ldr r3, [pc, #412] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d1a: 430a orrs r2, r1
|
|
8000d1c: 601a str r2, [r3, #0]
|
|
|
|
/* Update the SystemCoreClock global variable with HSISYS value */
|
|
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
|
|
8000d1e: 4b66 ldr r3, [pc, #408] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d20: 681b ldr r3, [r3, #0]
|
|
8000d22: 0adb lsrs r3, r3, #11
|
|
8000d24: 2207 movs r2, #7
|
|
8000d26: 4013 ands r3, r2
|
|
8000d28: 4a68 ldr r2, [pc, #416] @ (8000ecc <HAL_RCC_OscConfig+0x340>)
|
|
8000d2a: 40da lsrs r2, r3
|
|
8000d2c: 4b68 ldr r3, [pc, #416] @ (8000ed0 <HAL_RCC_OscConfig+0x344>)
|
|
8000d2e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Adapt Systick interrupt period */
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
8000d30: 4b68 ldr r3, [pc, #416] @ (8000ed4 <HAL_RCC_OscConfig+0x348>)
|
|
8000d32: 681b ldr r3, [r3, #0]
|
|
8000d34: 0018 movs r0, r3
|
|
8000d36: f7ff fc6b bl 8000610 <HAL_InitTick>
|
|
8000d3a: 1e03 subs r3, r0, #0
|
|
8000d3c: d051 beq.n 8000de2 <HAL_RCC_OscConfig+0x256>
|
|
{
|
|
return HAL_ERROR;
|
|
8000d3e: 2301 movs r3, #1
|
|
8000d40: e221 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8000d42: 687b ldr r3, [r7, #4]
|
|
8000d44: 68db ldr r3, [r3, #12]
|
|
8000d46: 2b00 cmp r3, #0
|
|
8000d48: d030 beq.n 8000dac <HAL_RCC_OscConfig+0x220>
|
|
{
|
|
/* Configure the HSI16 division factor */
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
8000d4a: 4b5b ldr r3, [pc, #364] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d4c: 681b ldr r3, [r3, #0]
|
|
8000d4e: 4a5e ldr r2, [pc, #376] @ (8000ec8 <HAL_RCC_OscConfig+0x33c>)
|
|
8000d50: 4013 ands r3, r2
|
|
8000d52: 0019 movs r1, r3
|
|
8000d54: 687b ldr r3, [r7, #4]
|
|
8000d56: 691a ldr r2, [r3, #16]
|
|
8000d58: 4b57 ldr r3, [pc, #348] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d5a: 430a orrs r2, r1
|
|
8000d5c: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the Internal High Speed oscillator (HSI16). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8000d5e: 4b56 ldr r3, [pc, #344] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d60: 681a ldr r2, [r3, #0]
|
|
8000d62: 4b55 ldr r3, [pc, #340] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d64: 2180 movs r1, #128 @ 0x80
|
|
8000d66: 0049 lsls r1, r1, #1
|
|
8000d68: 430a orrs r2, r1
|
|
8000d6a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000d6c: f7ff fcac bl 80006c8 <HAL_GetTick>
|
|
8000d70: 0003 movs r3, r0
|
|
8000d72: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8000d74: e008 b.n 8000d88 <HAL_RCC_OscConfig+0x1fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000d76: f7ff fca7 bl 80006c8 <HAL_GetTick>
|
|
8000d7a: 0002 movs r2, r0
|
|
8000d7c: 693b ldr r3, [r7, #16]
|
|
8000d7e: 1ad3 subs r3, r2, r3
|
|
8000d80: 2b02 cmp r3, #2
|
|
8000d82: d901 bls.n 8000d88 <HAL_RCC_OscConfig+0x1fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000d84: 2303 movs r3, #3
|
|
8000d86: e1fe b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8000d88: 4b4b ldr r3, [pc, #300] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d8a: 681a ldr r2, [r3, #0]
|
|
8000d8c: 2380 movs r3, #128 @ 0x80
|
|
8000d8e: 00db lsls r3, r3, #3
|
|
8000d90: 4013 ands r3, r2
|
|
8000d92: d0f0 beq.n 8000d76 <HAL_RCC_OscConfig+0x1ea>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000d94: 4b48 ldr r3, [pc, #288] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000d96: 685b ldr r3, [r3, #4]
|
|
8000d98: 4a4a ldr r2, [pc, #296] @ (8000ec4 <HAL_RCC_OscConfig+0x338>)
|
|
8000d9a: 4013 ands r3, r2
|
|
8000d9c: 0019 movs r1, r3
|
|
8000d9e: 687b ldr r3, [r7, #4]
|
|
8000da0: 695b ldr r3, [r3, #20]
|
|
8000da2: 021a lsls r2, r3, #8
|
|
8000da4: 4b44 ldr r3, [pc, #272] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000da6: 430a orrs r2, r1
|
|
8000da8: 605a str r2, [r3, #4]
|
|
8000daa: e01b b.n 8000de4 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI16). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8000dac: 4b42 ldr r3, [pc, #264] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000dae: 681a ldr r2, [r3, #0]
|
|
8000db0: 4b41 ldr r3, [pc, #260] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000db2: 4949 ldr r1, [pc, #292] @ (8000ed8 <HAL_RCC_OscConfig+0x34c>)
|
|
8000db4: 400a ands r2, r1
|
|
8000db6: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000db8: f7ff fc86 bl 80006c8 <HAL_GetTick>
|
|
8000dbc: 0003 movs r3, r0
|
|
8000dbe: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8000dc0: e008 b.n 8000dd4 <HAL_RCC_OscConfig+0x248>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000dc2: f7ff fc81 bl 80006c8 <HAL_GetTick>
|
|
8000dc6: 0002 movs r2, r0
|
|
8000dc8: 693b ldr r3, [r7, #16]
|
|
8000dca: 1ad3 subs r3, r2, r3
|
|
8000dcc: 2b02 cmp r3, #2
|
|
8000dce: d901 bls.n 8000dd4 <HAL_RCC_OscConfig+0x248>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000dd0: 2303 movs r3, #3
|
|
8000dd2: e1d8 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8000dd4: 4b38 ldr r3, [pc, #224] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000dd6: 681a ldr r2, [r3, #0]
|
|
8000dd8: 2380 movs r3, #128 @ 0x80
|
|
8000dda: 00db lsls r3, r3, #3
|
|
8000ddc: 4013 ands r3, r2
|
|
8000dde: d1f0 bne.n 8000dc2 <HAL_RCC_OscConfig+0x236>
|
|
8000de0: e000 b.n 8000de4 <HAL_RCC_OscConfig+0x258>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8000de2: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8000de4: 687b ldr r3, [r7, #4]
|
|
8000de6: 681b ldr r3, [r3, #0]
|
|
8000de8: 2208 movs r2, #8
|
|
8000dea: 4013 ands r3, r2
|
|
8000dec: d047 beq.n 8000e7e <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check if LSI is used as system clock */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
|
|
8000dee: 4b32 ldr r3, [pc, #200] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000df0: 689b ldr r3, [r3, #8]
|
|
8000df2: 2238 movs r2, #56 @ 0x38
|
|
8000df4: 4013 ands r3, r2
|
|
8000df6: 2b18 cmp r3, #24
|
|
8000df8: d10a bne.n 8000e10 <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* When LSI is used as system clock it will not be disabled */
|
|
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
|
|
8000dfa: 4b2f ldr r3, [pc, #188] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000dfc: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8000dfe: 2202 movs r2, #2
|
|
8000e00: 4013 ands r3, r2
|
|
8000e02: d03c beq.n 8000e7e <HAL_RCC_OscConfig+0x2f2>
|
|
8000e04: 687b ldr r3, [r7, #4]
|
|
8000e06: 699b ldr r3, [r3, #24]
|
|
8000e08: 2b00 cmp r3, #0
|
|
8000e0a: d138 bne.n 8000e7e <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
return HAL_ERROR;
|
|
8000e0c: 2301 movs r3, #1
|
|
8000e0e: e1ba b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8000e10: 687b ldr r3, [r7, #4]
|
|
8000e12: 699b ldr r3, [r3, #24]
|
|
8000e14: 2b00 cmp r3, #0
|
|
8000e16: d019 beq.n 8000e4c <HAL_RCC_OscConfig+0x2c0>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8000e18: 4b27 ldr r3, [pc, #156] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e1a: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8000e1c: 4b26 ldr r3, [pc, #152] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e1e: 2101 movs r1, #1
|
|
8000e20: 430a orrs r2, r1
|
|
8000e22: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000e24: f7ff fc50 bl 80006c8 <HAL_GetTick>
|
|
8000e28: 0003 movs r3, r0
|
|
8000e2a: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8000e2c: e008 b.n 8000e40 <HAL_RCC_OscConfig+0x2b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000e2e: f7ff fc4b bl 80006c8 <HAL_GetTick>
|
|
8000e32: 0002 movs r2, r0
|
|
8000e34: 693b ldr r3, [r7, #16]
|
|
8000e36: 1ad3 subs r3, r2, r3
|
|
8000e38: 2b02 cmp r3, #2
|
|
8000e3a: d901 bls.n 8000e40 <HAL_RCC_OscConfig+0x2b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e3c: 2303 movs r3, #3
|
|
8000e3e: e1a2 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8000e40: 4b1d ldr r3, [pc, #116] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e42: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8000e44: 2202 movs r2, #2
|
|
8000e46: 4013 ands r3, r2
|
|
8000e48: d0f1 beq.n 8000e2e <HAL_RCC_OscConfig+0x2a2>
|
|
8000e4a: e018 b.n 8000e7e <HAL_RCC_OscConfig+0x2f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8000e4c: 4b1a ldr r3, [pc, #104] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e4e: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8000e50: 4b19 ldr r3, [pc, #100] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e52: 2101 movs r1, #1
|
|
8000e54: 438a bics r2, r1
|
|
8000e56: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000e58: f7ff fc36 bl 80006c8 <HAL_GetTick>
|
|
8000e5c: 0003 movs r3, r0
|
|
8000e5e: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8000e60: e008 b.n 8000e74 <HAL_RCC_OscConfig+0x2e8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000e62: f7ff fc31 bl 80006c8 <HAL_GetTick>
|
|
8000e66: 0002 movs r2, r0
|
|
8000e68: 693b ldr r3, [r7, #16]
|
|
8000e6a: 1ad3 subs r3, r2, r3
|
|
8000e6c: 2b02 cmp r3, #2
|
|
8000e6e: d901 bls.n 8000e74 <HAL_RCC_OscConfig+0x2e8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e70: 2303 movs r3, #3
|
|
8000e72: e188 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8000e74: 4b10 ldr r3, [pc, #64] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e76: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8000e78: 2202 movs r2, #2
|
|
8000e7a: 4013 ands r3, r2
|
|
8000e7c: d1f1 bne.n 8000e62 <HAL_RCC_OscConfig+0x2d6>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8000e7e: 687b ldr r3, [r7, #4]
|
|
8000e80: 681b ldr r3, [r3, #0]
|
|
8000e82: 2204 movs r2, #4
|
|
8000e84: 4013 ands r3, r2
|
|
8000e86: d100 bne.n 8000e8a <HAL_RCC_OscConfig+0x2fe>
|
|
8000e88: e0c6 b.n 8001018 <HAL_RCC_OscConfig+0x48c>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8000e8a: 231f movs r3, #31
|
|
8000e8c: 18fb adds r3, r7, r3
|
|
8000e8e: 2200 movs r2, #0
|
|
8000e90: 701a strb r2, [r3, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* When the LSE is used as system clock, it is not allowed disable it */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
|
|
8000e92: 4b09 ldr r3, [pc, #36] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000e94: 689b ldr r3, [r3, #8]
|
|
8000e96: 2238 movs r2, #56 @ 0x38
|
|
8000e98: 4013 ands r3, r2
|
|
8000e9a: 2b20 cmp r3, #32
|
|
8000e9c: d11e bne.n 8000edc <HAL_RCC_OscConfig+0x350>
|
|
{
|
|
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
|
|
8000e9e: 4b06 ldr r3, [pc, #24] @ (8000eb8 <HAL_RCC_OscConfig+0x32c>)
|
|
8000ea0: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8000ea2: 2202 movs r2, #2
|
|
8000ea4: 4013 ands r3, r2
|
|
8000ea6: d100 bne.n 8000eaa <HAL_RCC_OscConfig+0x31e>
|
|
8000ea8: e0b6 b.n 8001018 <HAL_RCC_OscConfig+0x48c>
|
|
8000eaa: 687b ldr r3, [r7, #4]
|
|
8000eac: 689b ldr r3, [r3, #8]
|
|
8000eae: 2b00 cmp r3, #0
|
|
8000eb0: d000 beq.n 8000eb4 <HAL_RCC_OscConfig+0x328>
|
|
8000eb2: e0b1 b.n 8001018 <HAL_RCC_OscConfig+0x48c>
|
|
{
|
|
return HAL_ERROR;
|
|
8000eb4: 2301 movs r3, #1
|
|
8000eb6: e166 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
8000eb8: 40021000 .word 0x40021000
|
|
8000ebc: fffeffff .word 0xfffeffff
|
|
8000ec0: fffbffff .word 0xfffbffff
|
|
8000ec4: ffff80ff .word 0xffff80ff
|
|
8000ec8: ffffc7ff .word 0xffffc7ff
|
|
8000ecc: 00f42400 .word 0x00f42400
|
|
8000ed0: 20000000 .word 0x20000000
|
|
8000ed4: 20000004 .word 0x20000004
|
|
8000ed8: fffffeff .word 0xfffffeff
|
|
}
|
|
else
|
|
{
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
8000edc: 4bac ldr r3, [pc, #688] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000ede: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8000ee0: 2380 movs r3, #128 @ 0x80
|
|
8000ee2: 055b lsls r3, r3, #21
|
|
8000ee4: 4013 ands r3, r2
|
|
8000ee6: d101 bne.n 8000eec <HAL_RCC_OscConfig+0x360>
|
|
8000ee8: 2301 movs r3, #1
|
|
8000eea: e000 b.n 8000eee <HAL_RCC_OscConfig+0x362>
|
|
8000eec: 2300 movs r3, #0
|
|
8000eee: 2b00 cmp r3, #0
|
|
8000ef0: d011 beq.n 8000f16 <HAL_RCC_OscConfig+0x38a>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000ef2: 4ba7 ldr r3, [pc, #668] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000ef4: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8000ef6: 4ba6 ldr r3, [pc, #664] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000ef8: 2180 movs r1, #128 @ 0x80
|
|
8000efa: 0549 lsls r1, r1, #21
|
|
8000efc: 430a orrs r2, r1
|
|
8000efe: 63da str r2, [r3, #60] @ 0x3c
|
|
8000f00: 4ba3 ldr r3, [pc, #652] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f02: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8000f04: 2380 movs r3, #128 @ 0x80
|
|
8000f06: 055b lsls r3, r3, #21
|
|
8000f08: 4013 ands r3, r2
|
|
8000f0a: 60fb str r3, [r7, #12]
|
|
8000f0c: 68fb ldr r3, [r7, #12]
|
|
pwrclkchanged = SET;
|
|
8000f0e: 231f movs r3, #31
|
|
8000f10: 18fb adds r3, r7, r3
|
|
8000f12: 2201 movs r2, #1
|
|
8000f14: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8000f16: 4b9f ldr r3, [pc, #636] @ (8001194 <HAL_RCC_OscConfig+0x608>)
|
|
8000f18: 681a ldr r2, [r3, #0]
|
|
8000f1a: 2380 movs r3, #128 @ 0x80
|
|
8000f1c: 005b lsls r3, r3, #1
|
|
8000f1e: 4013 ands r3, r2
|
|
8000f20: d11a bne.n 8000f58 <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8000f22: 4b9c ldr r3, [pc, #624] @ (8001194 <HAL_RCC_OscConfig+0x608>)
|
|
8000f24: 681a ldr r2, [r3, #0]
|
|
8000f26: 4b9b ldr r3, [pc, #620] @ (8001194 <HAL_RCC_OscConfig+0x608>)
|
|
8000f28: 2180 movs r1, #128 @ 0x80
|
|
8000f2a: 0049 lsls r1, r1, #1
|
|
8000f2c: 430a orrs r2, r1
|
|
8000f2e: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8000f30: f7ff fbca bl 80006c8 <HAL_GetTick>
|
|
8000f34: 0003 movs r3, r0
|
|
8000f36: 613b str r3, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8000f38: e008 b.n 8000f4c <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8000f3a: f7ff fbc5 bl 80006c8 <HAL_GetTick>
|
|
8000f3e: 0002 movs r2, r0
|
|
8000f40: 693b ldr r3, [r7, #16]
|
|
8000f42: 1ad3 subs r3, r2, r3
|
|
8000f44: 2b02 cmp r3, #2
|
|
8000f46: d901 bls.n 8000f4c <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000f48: 2303 movs r3, #3
|
|
8000f4a: e11c b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8000f4c: 4b91 ldr r3, [pc, #580] @ (8001194 <HAL_RCC_OscConfig+0x608>)
|
|
8000f4e: 681a ldr r2, [r3, #0]
|
|
8000f50: 2380 movs r3, #128 @ 0x80
|
|
8000f52: 005b lsls r3, r3, #1
|
|
8000f54: 4013 ands r3, r2
|
|
8000f56: d0f0 beq.n 8000f3a <HAL_RCC_OscConfig+0x3ae>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8000f58: 687b ldr r3, [r7, #4]
|
|
8000f5a: 689b ldr r3, [r3, #8]
|
|
8000f5c: 2b01 cmp r3, #1
|
|
8000f5e: d106 bne.n 8000f6e <HAL_RCC_OscConfig+0x3e2>
|
|
8000f60: 4b8b ldr r3, [pc, #556] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f62: 6dda ldr r2, [r3, #92] @ 0x5c
|
|
8000f64: 4b8a ldr r3, [pc, #552] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f66: 2101 movs r1, #1
|
|
8000f68: 430a orrs r2, r1
|
|
8000f6a: 65da str r2, [r3, #92] @ 0x5c
|
|
8000f6c: e01c b.n 8000fa8 <HAL_RCC_OscConfig+0x41c>
|
|
8000f6e: 687b ldr r3, [r7, #4]
|
|
8000f70: 689b ldr r3, [r3, #8]
|
|
8000f72: 2b05 cmp r3, #5
|
|
8000f74: d10c bne.n 8000f90 <HAL_RCC_OscConfig+0x404>
|
|
8000f76: 4b86 ldr r3, [pc, #536] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f78: 6dda ldr r2, [r3, #92] @ 0x5c
|
|
8000f7a: 4b85 ldr r3, [pc, #532] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f7c: 2104 movs r1, #4
|
|
8000f7e: 430a orrs r2, r1
|
|
8000f80: 65da str r2, [r3, #92] @ 0x5c
|
|
8000f82: 4b83 ldr r3, [pc, #524] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f84: 6dda ldr r2, [r3, #92] @ 0x5c
|
|
8000f86: 4b82 ldr r3, [pc, #520] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f88: 2101 movs r1, #1
|
|
8000f8a: 430a orrs r2, r1
|
|
8000f8c: 65da str r2, [r3, #92] @ 0x5c
|
|
8000f8e: e00b b.n 8000fa8 <HAL_RCC_OscConfig+0x41c>
|
|
8000f90: 4b7f ldr r3, [pc, #508] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f92: 6dda ldr r2, [r3, #92] @ 0x5c
|
|
8000f94: 4b7e ldr r3, [pc, #504] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f96: 2101 movs r1, #1
|
|
8000f98: 438a bics r2, r1
|
|
8000f9a: 65da str r2, [r3, #92] @ 0x5c
|
|
8000f9c: 4b7c ldr r3, [pc, #496] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000f9e: 6dda ldr r2, [r3, #92] @ 0x5c
|
|
8000fa0: 4b7b ldr r3, [pc, #492] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000fa2: 2104 movs r1, #4
|
|
8000fa4: 438a bics r2, r1
|
|
8000fa6: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8000fa8: 687b ldr r3, [r7, #4]
|
|
8000faa: 689b ldr r3, [r3, #8]
|
|
8000fac: 2b00 cmp r3, #0
|
|
8000fae: d014 beq.n 8000fda <HAL_RCC_OscConfig+0x44e>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000fb0: f7ff fb8a bl 80006c8 <HAL_GetTick>
|
|
8000fb4: 0003 movs r3, r0
|
|
8000fb6: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8000fb8: e009 b.n 8000fce <HAL_RCC_OscConfig+0x442>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000fba: f7ff fb85 bl 80006c8 <HAL_GetTick>
|
|
8000fbe: 0002 movs r2, r0
|
|
8000fc0: 693b ldr r3, [r7, #16]
|
|
8000fc2: 1ad3 subs r3, r2, r3
|
|
8000fc4: 4a74 ldr r2, [pc, #464] @ (8001198 <HAL_RCC_OscConfig+0x60c>)
|
|
8000fc6: 4293 cmp r3, r2
|
|
8000fc8: d901 bls.n 8000fce <HAL_RCC_OscConfig+0x442>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000fca: 2303 movs r3, #3
|
|
8000fcc: e0db b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8000fce: 4b70 ldr r3, [pc, #448] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000fd0: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8000fd2: 2202 movs r2, #2
|
|
8000fd4: 4013 ands r3, r2
|
|
8000fd6: d0f0 beq.n 8000fba <HAL_RCC_OscConfig+0x42e>
|
|
8000fd8: e013 b.n 8001002 <HAL_RCC_OscConfig+0x476>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8000fda: f7ff fb75 bl 80006c8 <HAL_GetTick>
|
|
8000fde: 0003 movs r3, r0
|
|
8000fe0: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8000fe2: e009 b.n 8000ff8 <HAL_RCC_OscConfig+0x46c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000fe4: f7ff fb70 bl 80006c8 <HAL_GetTick>
|
|
8000fe8: 0002 movs r2, r0
|
|
8000fea: 693b ldr r3, [r7, #16]
|
|
8000fec: 1ad3 subs r3, r2, r3
|
|
8000fee: 4a6a ldr r2, [pc, #424] @ (8001198 <HAL_RCC_OscConfig+0x60c>)
|
|
8000ff0: 4293 cmp r3, r2
|
|
8000ff2: d901 bls.n 8000ff8 <HAL_RCC_OscConfig+0x46c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000ff4: 2303 movs r3, #3
|
|
8000ff6: e0c6 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8000ff8: 4b65 ldr r3, [pc, #404] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8000ffa: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8000ffc: 2202 movs r2, #2
|
|
8000ffe: 4013 ands r3, r2
|
|
8001000: d1f0 bne.n 8000fe4 <HAL_RCC_OscConfig+0x458>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8001002: 231f movs r3, #31
|
|
8001004: 18fb adds r3, r7, r3
|
|
8001006: 781b ldrb r3, [r3, #0]
|
|
8001008: 2b01 cmp r3, #1
|
|
800100a: d105 bne.n 8001018 <HAL_RCC_OscConfig+0x48c>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
800100c: 4b60 ldr r3, [pc, #384] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800100e: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8001010: 4b5f ldr r3, [pc, #380] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8001012: 4962 ldr r1, [pc, #392] @ (800119c <HAL_RCC_OscConfig+0x610>)
|
|
8001014: 400a ands r2, r1
|
|
8001016: 63da str r2, [r3, #60] @ 0x3c
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8001018: 687b ldr r3, [r7, #4]
|
|
800101a: 69db ldr r3, [r3, #28]
|
|
800101c: 2b00 cmp r3, #0
|
|
800101e: d100 bne.n 8001022 <HAL_RCC_OscConfig+0x496>
|
|
8001020: e0b0 b.n 8001184 <HAL_RCC_OscConfig+0x5f8>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8001022: 4b5b ldr r3, [pc, #364] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8001024: 689b ldr r3, [r3, #8]
|
|
8001026: 2238 movs r2, #56 @ 0x38
|
|
8001028: 4013 ands r3, r2
|
|
800102a: 2b10 cmp r3, #16
|
|
800102c: d100 bne.n 8001030 <HAL_RCC_OscConfig+0x4a4>
|
|
800102e: e078 b.n 8001122 <HAL_RCC_OscConfig+0x596>
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8001030: 687b ldr r3, [r7, #4]
|
|
8001032: 69db ldr r3, [r3, #28]
|
|
8001034: 2b02 cmp r3, #2
|
|
8001036: d153 bne.n 80010e0 <HAL_RCC_OscConfig+0x554>
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
#endif /* RCC_PLLQ_SUPPORT */
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8001038: 4b55 ldr r3, [pc, #340] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800103a: 681a ldr r2, [r3, #0]
|
|
800103c: 4b54 ldr r3, [pc, #336] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800103e: 4958 ldr r1, [pc, #352] @ (80011a0 <HAL_RCC_OscConfig+0x614>)
|
|
8001040: 400a ands r2, r1
|
|
8001042: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8001044: f7ff fb40 bl 80006c8 <HAL_GetTick>
|
|
8001048: 0003 movs r3, r0
|
|
800104a: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800104c: e008 b.n 8001060 <HAL_RCC_OscConfig+0x4d4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800104e: f7ff fb3b bl 80006c8 <HAL_GetTick>
|
|
8001052: 0002 movs r2, r0
|
|
8001054: 693b ldr r3, [r7, #16]
|
|
8001056: 1ad3 subs r3, r2, r3
|
|
8001058: 2b02 cmp r3, #2
|
|
800105a: d901 bls.n 8001060 <HAL_RCC_OscConfig+0x4d4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800105c: 2303 movs r3, #3
|
|
800105e: e092 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8001060: 4b4b ldr r3, [pc, #300] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8001062: 681a ldr r2, [r3, #0]
|
|
8001064: 2380 movs r3, #128 @ 0x80
|
|
8001066: 049b lsls r3, r3, #18
|
|
8001068: 4013 ands r3, r2
|
|
800106a: d1f0 bne.n 800104e <HAL_RCC_OscConfig+0x4c2>
|
|
RCC_OscInitStruct->PLL.PLLN,
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#else /* !RCC_PLLQ_SUPPORT */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
800106c: 4b48 ldr r3, [pc, #288] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800106e: 68db ldr r3, [r3, #12]
|
|
8001070: 4a4c ldr r2, [pc, #304] @ (80011a4 <HAL_RCC_OscConfig+0x618>)
|
|
8001072: 4013 ands r3, r2
|
|
8001074: 0019 movs r1, r3
|
|
8001076: 687b ldr r3, [r7, #4]
|
|
8001078: 6a1a ldr r2, [r3, #32]
|
|
800107a: 687b ldr r3, [r7, #4]
|
|
800107c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800107e: 431a orrs r2, r3
|
|
8001080: 687b ldr r3, [r7, #4]
|
|
8001082: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001084: 021b lsls r3, r3, #8
|
|
8001086: 431a orrs r2, r3
|
|
8001088: 687b ldr r3, [r7, #4]
|
|
800108a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800108c: 431a orrs r2, r3
|
|
800108e: 687b ldr r3, [r7, #4]
|
|
8001090: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001092: 431a orrs r2, r3
|
|
8001094: 4b3e ldr r3, [pc, #248] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8001096: 430a orrs r2, r1
|
|
8001098: 60da str r2, [r3, #12]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#endif /* RCC_PLLQ_SUPPORT */
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800109a: 4b3d ldr r3, [pc, #244] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800109c: 681a ldr r2, [r3, #0]
|
|
800109e: 4b3c ldr r3, [pc, #240] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
80010a0: 2180 movs r1, #128 @ 0x80
|
|
80010a2: 0449 lsls r1, r1, #17
|
|
80010a4: 430a orrs r2, r1
|
|
80010a6: 601a str r2, [r3, #0]
|
|
|
|
/* Enable PLLR Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
|
|
80010a8: 4b39 ldr r3, [pc, #228] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
80010aa: 68da ldr r2, [r3, #12]
|
|
80010ac: 4b38 ldr r3, [pc, #224] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
80010ae: 2180 movs r1, #128 @ 0x80
|
|
80010b0: 0549 lsls r1, r1, #21
|
|
80010b2: 430a orrs r2, r1
|
|
80010b4: 60da str r2, [r3, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80010b6: f7ff fb07 bl 80006c8 <HAL_GetTick>
|
|
80010ba: 0003 movs r3, r0
|
|
80010bc: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80010be: e008 b.n 80010d2 <HAL_RCC_OscConfig+0x546>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80010c0: f7ff fb02 bl 80006c8 <HAL_GetTick>
|
|
80010c4: 0002 movs r2, r0
|
|
80010c6: 693b ldr r3, [r7, #16]
|
|
80010c8: 1ad3 subs r3, r2, r3
|
|
80010ca: 2b02 cmp r3, #2
|
|
80010cc: d901 bls.n 80010d2 <HAL_RCC_OscConfig+0x546>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80010ce: 2303 movs r3, #3
|
|
80010d0: e059 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80010d2: 4b2f ldr r3, [pc, #188] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
80010d4: 681a ldr r2, [r3, #0]
|
|
80010d6: 2380 movs r3, #128 @ 0x80
|
|
80010d8: 049b lsls r3, r3, #18
|
|
80010da: 4013 ands r3, r2
|
|
80010dc: d0f0 beq.n 80010c0 <HAL_RCC_OscConfig+0x534>
|
|
80010de: e051 b.n 8001184 <HAL_RCC_OscConfig+0x5f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80010e0: 4b2b ldr r3, [pc, #172] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
80010e2: 681a ldr r2, [r3, #0]
|
|
80010e4: 4b2a ldr r3, [pc, #168] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
80010e6: 492e ldr r1, [pc, #184] @ (80011a0 <HAL_RCC_OscConfig+0x614>)
|
|
80010e8: 400a ands r2, r1
|
|
80010ea: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80010ec: f7ff faec bl 80006c8 <HAL_GetTick>
|
|
80010f0: 0003 movs r3, r0
|
|
80010f2: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80010f4: e008 b.n 8001108 <HAL_RCC_OscConfig+0x57c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80010f6: f7ff fae7 bl 80006c8 <HAL_GetTick>
|
|
80010fa: 0002 movs r2, r0
|
|
80010fc: 693b ldr r3, [r7, #16]
|
|
80010fe: 1ad3 subs r3, r2, r3
|
|
8001100: 2b02 cmp r3, #2
|
|
8001102: d901 bls.n 8001108 <HAL_RCC_OscConfig+0x57c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001104: 2303 movs r3, #3
|
|
8001106: e03e b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8001108: 4b21 ldr r3, [pc, #132] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800110a: 681a ldr r2, [r3, #0]
|
|
800110c: 2380 movs r3, #128 @ 0x80
|
|
800110e: 049b lsls r3, r3, #18
|
|
8001110: 4013 ands r3, r2
|
|
8001112: d1f0 bne.n 80010f6 <HAL_RCC_OscConfig+0x56a>
|
|
}
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
#if defined(RCC_PLLQ_SUPPORT)
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
|
|
#else
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN);
|
|
8001114: 4b1e ldr r3, [pc, #120] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8001116: 68da ldr r2, [r3, #12]
|
|
8001118: 4b1d ldr r3, [pc, #116] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
800111a: 4923 ldr r1, [pc, #140] @ (80011a8 <HAL_RCC_OscConfig+0x61c>)
|
|
800111c: 400a ands r2, r1
|
|
800111e: 60da str r2, [r3, #12]
|
|
8001120: e030 b.n 8001184 <HAL_RCC_OscConfig+0x5f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8001122: 687b ldr r3, [r7, #4]
|
|
8001124: 69db ldr r3, [r3, #28]
|
|
8001126: 2b01 cmp r3, #1
|
|
8001128: d101 bne.n 800112e <HAL_RCC_OscConfig+0x5a2>
|
|
{
|
|
return HAL_ERROR;
|
|
800112a: 2301 movs r3, #1
|
|
800112c: e02b b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
temp_pllckcfg = RCC->PLLCFGR;
|
|
800112e: 4b18 ldr r3, [pc, #96] @ (8001190 <HAL_RCC_OscConfig+0x604>)
|
|
8001130: 68db ldr r3, [r3, #12]
|
|
8001132: 617b str r3, [r7, #20]
|
|
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8001134: 697b ldr r3, [r7, #20]
|
|
8001136: 2203 movs r2, #3
|
|
8001138: 401a ands r2, r3
|
|
800113a: 687b ldr r3, [r7, #4]
|
|
800113c: 6a1b ldr r3, [r3, #32]
|
|
800113e: 429a cmp r2, r3
|
|
8001140: d11e bne.n 8001180 <HAL_RCC_OscConfig+0x5f4>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
8001142: 697b ldr r3, [r7, #20]
|
|
8001144: 2270 movs r2, #112 @ 0x70
|
|
8001146: 401a ands r2, r3
|
|
8001148: 687b ldr r3, [r7, #4]
|
|
800114a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800114c: 429a cmp r2, r3
|
|
800114e: d117 bne.n 8001180 <HAL_RCC_OscConfig+0x5f4>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8001150: 697a ldr r2, [r7, #20]
|
|
8001152: 23fe movs r3, #254 @ 0xfe
|
|
8001154: 01db lsls r3, r3, #7
|
|
8001156: 401a ands r2, r3
|
|
8001158: 687b ldr r3, [r7, #4]
|
|
800115a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800115c: 021b lsls r3, r3, #8
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
800115e: 429a cmp r2, r3
|
|
8001160: d10e bne.n 8001180 <HAL_RCC_OscConfig+0x5f4>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
|
8001162: 697a ldr r2, [r7, #20]
|
|
8001164: 23f8 movs r3, #248 @ 0xf8
|
|
8001166: 039b lsls r3, r3, #14
|
|
8001168: 401a ands r2, r3
|
|
800116a: 687b ldr r3, [r7, #4]
|
|
800116c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
800116e: 429a cmp r2, r3
|
|
8001170: d106 bne.n 8001180 <HAL_RCC_OscConfig+0x5f4>
|
|
#if defined (RCC_PLLQ_SUPPORT)
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
|
|
#endif /* RCC_PLLQ_SUPPORT */
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
|
|
8001172: 697b ldr r3, [r7, #20]
|
|
8001174: 0f5b lsrs r3, r3, #29
|
|
8001176: 075a lsls r2, r3, #29
|
|
8001178: 687b ldr r3, [r7, #4]
|
|
800117a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
|
800117c: 429a cmp r2, r3
|
|
800117e: d001 beq.n 8001184 <HAL_RCC_OscConfig+0x5f8>
|
|
{
|
|
return HAL_ERROR;
|
|
8001180: 2301 movs r3, #1
|
|
8001182: e000 b.n 8001186 <HAL_RCC_OscConfig+0x5fa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8001184: 2300 movs r3, #0
|
|
}
|
|
8001186: 0018 movs r0, r3
|
|
8001188: 46bd mov sp, r7
|
|
800118a: b008 add sp, #32
|
|
800118c: bd80 pop {r7, pc}
|
|
800118e: 46c0 nop @ (mov r8, r8)
|
|
8001190: 40021000 .word 0x40021000
|
|
8001194: 40007000 .word 0x40007000
|
|
8001198: 00001388 .word 0x00001388
|
|
800119c: efffffff .word 0xefffffff
|
|
80011a0: feffffff .word 0xfeffffff
|
|
80011a4: 1fc1808c .word 0x1fc1808c
|
|
80011a8: effefffc .word 0xeffefffc
|
|
|
|
080011ac <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80011ac: b580 push {r7, lr}
|
|
80011ae: b084 sub sp, #16
|
|
80011b0: af00 add r7, sp, #0
|
|
80011b2: 6078 str r0, [r7, #4]
|
|
80011b4: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
80011b6: 687b ldr r3, [r7, #4]
|
|
80011b8: 2b00 cmp r3, #0
|
|
80011ba: d101 bne.n 80011c0 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80011bc: 2301 movs r3, #1
|
|
80011be: e0e9 b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the FLASH clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80011c0: 4b76 ldr r3, [pc, #472] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
80011c2: 681b ldr r3, [r3, #0]
|
|
80011c4: 2207 movs r2, #7
|
|
80011c6: 4013 ands r3, r2
|
|
80011c8: 683a ldr r2, [r7, #0]
|
|
80011ca: 429a cmp r2, r3
|
|
80011cc: d91e bls.n 800120c <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80011ce: 4b73 ldr r3, [pc, #460] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
80011d0: 681b ldr r3, [r3, #0]
|
|
80011d2: 2207 movs r2, #7
|
|
80011d4: 4393 bics r3, r2
|
|
80011d6: 0019 movs r1, r3
|
|
80011d8: 4b70 ldr r3, [pc, #448] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
80011da: 683a ldr r2, [r7, #0]
|
|
80011dc: 430a orrs r2, r1
|
|
80011de: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by polling the FLASH_ACR register */
|
|
tickstart = HAL_GetTick();
|
|
80011e0: f7ff fa72 bl 80006c8 <HAL_GetTick>
|
|
80011e4: 0003 movs r3, r0
|
|
80011e6: 60fb str r3, [r7, #12]
|
|
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
80011e8: e009 b.n 80011fe <HAL_RCC_ClockConfig+0x52>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80011ea: f7ff fa6d bl 80006c8 <HAL_GetTick>
|
|
80011ee: 0002 movs r2, r0
|
|
80011f0: 68fb ldr r3, [r7, #12]
|
|
80011f2: 1ad3 subs r3, r2, r3
|
|
80011f4: 4a6a ldr r2, [pc, #424] @ (80013a0 <HAL_RCC_ClockConfig+0x1f4>)
|
|
80011f6: 4293 cmp r3, r2
|
|
80011f8: d901 bls.n 80011fe <HAL_RCC_ClockConfig+0x52>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80011fa: 2303 movs r3, #3
|
|
80011fc: e0ca b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
80011fe: 4b67 ldr r3, [pc, #412] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8001200: 681b ldr r3, [r3, #0]
|
|
8001202: 2207 movs r2, #7
|
|
8001204: 4013 ands r3, r2
|
|
8001206: 683a ldr r2, [r7, #0]
|
|
8001208: 429a cmp r2, r3
|
|
800120a: d1ee bne.n 80011ea <HAL_RCC_ClockConfig+0x3e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
800120c: 687b ldr r3, [r7, #4]
|
|
800120e: 681b ldr r3, [r3, #0]
|
|
8001210: 2202 movs r2, #2
|
|
8001212: 4013 ands r3, r2
|
|
8001214: d015 beq.n 8001242 <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Set the highest APB divider in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001216: 687b ldr r3, [r7, #4]
|
|
8001218: 681b ldr r3, [r3, #0]
|
|
800121a: 2204 movs r2, #4
|
|
800121c: 4013 ands r3, r2
|
|
800121e: d006 beq.n 800122e <HAL_RCC_ClockConfig+0x82>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
|
|
8001220: 4b60 ldr r3, [pc, #384] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001222: 689a ldr r2, [r3, #8]
|
|
8001224: 4b5f ldr r3, [pc, #380] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001226: 21e0 movs r1, #224 @ 0xe0
|
|
8001228: 01c9 lsls r1, r1, #7
|
|
800122a: 430a orrs r2, r1
|
|
800122c: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
800122e: 4b5d ldr r3, [pc, #372] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001230: 689b ldr r3, [r3, #8]
|
|
8001232: 4a5d ldr r2, [pc, #372] @ (80013a8 <HAL_RCC_ClockConfig+0x1fc>)
|
|
8001234: 4013 ands r3, r2
|
|
8001236: 0019 movs r1, r3
|
|
8001238: 687b ldr r3, [r7, #4]
|
|
800123a: 689a ldr r2, [r3, #8]
|
|
800123c: 4b59 ldr r3, [pc, #356] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
800123e: 430a orrs r2, r1
|
|
8001240: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8001242: 687b ldr r3, [r7, #4]
|
|
8001244: 681b ldr r3, [r3, #0]
|
|
8001246: 2201 movs r2, #1
|
|
8001248: 4013 ands r3, r2
|
|
800124a: d057 beq.n 80012fc <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800124c: 687b ldr r3, [r7, #4]
|
|
800124e: 685b ldr r3, [r3, #4]
|
|
8001250: 2b01 cmp r3, #1
|
|
8001252: d107 bne.n 8001264 <HAL_RCC_ClockConfig+0xb8>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8001254: 4b53 ldr r3, [pc, #332] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001256: 681a ldr r2, [r3, #0]
|
|
8001258: 2380 movs r3, #128 @ 0x80
|
|
800125a: 029b lsls r3, r3, #10
|
|
800125c: 4013 ands r3, r2
|
|
800125e: d12b bne.n 80012b8 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8001260: 2301 movs r3, #1
|
|
8001262: e097 b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8001264: 687b ldr r3, [r7, #4]
|
|
8001266: 685b ldr r3, [r3, #4]
|
|
8001268: 2b02 cmp r3, #2
|
|
800126a: d107 bne.n 800127c <HAL_RCC_ClockConfig+0xd0>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800126c: 4b4d ldr r3, [pc, #308] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
800126e: 681a ldr r2, [r3, #0]
|
|
8001270: 2380 movs r3, #128 @ 0x80
|
|
8001272: 049b lsls r3, r3, #18
|
|
8001274: 4013 ands r3, r2
|
|
8001276: d11f bne.n 80012b8 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8001278: 2301 movs r3, #1
|
|
800127a: e08b b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|
800127c: 687b ldr r3, [r7, #4]
|
|
800127e: 685b ldr r3, [r3, #4]
|
|
8001280: 2b00 cmp r3, #0
|
|
8001282: d107 bne.n 8001294 <HAL_RCC_ClockConfig+0xe8>
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8001284: 4b47 ldr r3, [pc, #284] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001286: 681a ldr r2, [r3, #0]
|
|
8001288: 2380 movs r3, #128 @ 0x80
|
|
800128a: 00db lsls r3, r3, #3
|
|
800128c: 4013 ands r3, r2
|
|
800128e: d113 bne.n 80012b8 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
8001290: 2301 movs r3, #1
|
|
8001292: e07f b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
/* LSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
|
|
8001294: 687b ldr r3, [r7, #4]
|
|
8001296: 685b ldr r3, [r3, #4]
|
|
8001298: 2b03 cmp r3, #3
|
|
800129a: d106 bne.n 80012aa <HAL_RCC_ClockConfig+0xfe>
|
|
{
|
|
/* Check the LSI ready flag */
|
|
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
800129c: 4b41 ldr r3, [pc, #260] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
800129e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80012a0: 2202 movs r2, #2
|
|
80012a2: 4013 ands r3, r2
|
|
80012a4: d108 bne.n 80012b8 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
80012a6: 2301 movs r3, #1
|
|
80012a8: e074 b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
/* LSE is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the LSE ready flag */
|
|
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
80012aa: 4b3e ldr r3, [pc, #248] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80012ac: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80012ae: 2202 movs r2, #2
|
|
80012b0: 4013 ands r3, r2
|
|
80012b2: d101 bne.n 80012b8 <HAL_RCC_ClockConfig+0x10c>
|
|
{
|
|
return HAL_ERROR;
|
|
80012b4: 2301 movs r3, #1
|
|
80012b6: e06d b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
}
|
|
}
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
80012b8: 4b3a ldr r3, [pc, #232] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80012ba: 689b ldr r3, [r3, #8]
|
|
80012bc: 2207 movs r2, #7
|
|
80012be: 4393 bics r3, r2
|
|
80012c0: 0019 movs r1, r3
|
|
80012c2: 687b ldr r3, [r7, #4]
|
|
80012c4: 685a ldr r2, [r3, #4]
|
|
80012c6: 4b37 ldr r3, [pc, #220] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80012c8: 430a orrs r2, r1
|
|
80012ca: 609a str r2, [r3, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80012cc: f7ff f9fc bl 80006c8 <HAL_GetTick>
|
|
80012d0: 0003 movs r3, r0
|
|
80012d2: 60fb str r3, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80012d4: e009 b.n 80012ea <HAL_RCC_ClockConfig+0x13e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80012d6: f7ff f9f7 bl 80006c8 <HAL_GetTick>
|
|
80012da: 0002 movs r2, r0
|
|
80012dc: 68fb ldr r3, [r7, #12]
|
|
80012de: 1ad3 subs r3, r2, r3
|
|
80012e0: 4a2f ldr r2, [pc, #188] @ (80013a0 <HAL_RCC_ClockConfig+0x1f4>)
|
|
80012e2: 4293 cmp r3, r2
|
|
80012e4: d901 bls.n 80012ea <HAL_RCC_ClockConfig+0x13e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80012e6: 2303 movs r3, #3
|
|
80012e8: e054 b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80012ea: 4b2e ldr r3, [pc, #184] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80012ec: 689b ldr r3, [r3, #8]
|
|
80012ee: 2238 movs r2, #56 @ 0x38
|
|
80012f0: 401a ands r2, r3
|
|
80012f2: 687b ldr r3, [r7, #4]
|
|
80012f4: 685b ldr r3, [r3, #4]
|
|
80012f6: 00db lsls r3, r3, #3
|
|
80012f8: 429a cmp r2, r3
|
|
80012fa: d1ec bne.n 80012d6 <HAL_RCC_ClockConfig+0x12a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80012fc: 4b27 ldr r3, [pc, #156] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
80012fe: 681b ldr r3, [r3, #0]
|
|
8001300: 2207 movs r2, #7
|
|
8001302: 4013 ands r3, r2
|
|
8001304: 683a ldr r2, [r7, #0]
|
|
8001306: 429a cmp r2, r3
|
|
8001308: d21e bcs.n 8001348 <HAL_RCC_ClockConfig+0x19c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800130a: 4b24 ldr r3, [pc, #144] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
800130c: 681b ldr r3, [r3, #0]
|
|
800130e: 2207 movs r2, #7
|
|
8001310: 4393 bics r3, r2
|
|
8001312: 0019 movs r1, r3
|
|
8001314: 4b21 ldr r3, [pc, #132] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
8001316: 683a ldr r2, [r7, #0]
|
|
8001318: 430a orrs r2, r1
|
|
800131a: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by polling the FLASH_ACR register */
|
|
tickstart = HAL_GetTick();
|
|
800131c: f7ff f9d4 bl 80006c8 <HAL_GetTick>
|
|
8001320: 0003 movs r3, r0
|
|
8001322: 60fb str r3, [r7, #12]
|
|
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
8001324: e009 b.n 800133a <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8001326: f7ff f9cf bl 80006c8 <HAL_GetTick>
|
|
800132a: 0002 movs r2, r0
|
|
800132c: 68fb ldr r3, [r7, #12]
|
|
800132e: 1ad3 subs r3, r2, r3
|
|
8001330: 4a1b ldr r2, [pc, #108] @ (80013a0 <HAL_RCC_ClockConfig+0x1f4>)
|
|
8001332: 4293 cmp r3, r2
|
|
8001334: d901 bls.n 800133a <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001336: 2303 movs r3, #3
|
|
8001338: e02c b.n 8001394 <HAL_RCC_ClockConfig+0x1e8>
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
800133a: 4b18 ldr r3, [pc, #96] @ (800139c <HAL_RCC_ClockConfig+0x1f0>)
|
|
800133c: 681b ldr r3, [r3, #0]
|
|
800133e: 2207 movs r2, #7
|
|
8001340: 4013 ands r3, r2
|
|
8001342: 683a ldr r2, [r7, #0]
|
|
8001344: 429a cmp r2, r3
|
|
8001346: d1ee bne.n 8001326 <HAL_RCC_ClockConfig+0x17a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001348: 687b ldr r3, [r7, #4]
|
|
800134a: 681b ldr r3, [r3, #0]
|
|
800134c: 2204 movs r2, #4
|
|
800134e: 4013 ands r3, r2
|
|
8001350: d009 beq.n 8001366 <HAL_RCC_ClockConfig+0x1ba>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8001352: 4b14 ldr r3, [pc, #80] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001354: 689b ldr r3, [r3, #8]
|
|
8001356: 4a15 ldr r2, [pc, #84] @ (80013ac <HAL_RCC_ClockConfig+0x200>)
|
|
8001358: 4013 ands r3, r2
|
|
800135a: 0019 movs r1, r3
|
|
800135c: 687b ldr r3, [r7, #4]
|
|
800135e: 68da ldr r2, [r3, #12]
|
|
8001360: 4b10 ldr r3, [pc, #64] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
8001362: 430a orrs r2, r1
|
|
8001364: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
|
|
8001366: f000 f829 bl 80013bc <HAL_RCC_GetSysClockFreq>
|
|
800136a: 0001 movs r1, r0
|
|
800136c: 4b0d ldr r3, [pc, #52] @ (80013a4 <HAL_RCC_ClockConfig+0x1f8>)
|
|
800136e: 689b ldr r3, [r3, #8]
|
|
8001370: 0a1b lsrs r3, r3, #8
|
|
8001372: 220f movs r2, #15
|
|
8001374: 401a ands r2, r3
|
|
8001376: 4b0e ldr r3, [pc, #56] @ (80013b0 <HAL_RCC_ClockConfig+0x204>)
|
|
8001378: 0092 lsls r2, r2, #2
|
|
800137a: 58d3 ldr r3, [r2, r3]
|
|
800137c: 221f movs r2, #31
|
|
800137e: 4013 ands r3, r2
|
|
8001380: 000a movs r2, r1
|
|
8001382: 40da lsrs r2, r3
|
|
8001384: 4b0b ldr r3, [pc, #44] @ (80013b4 <HAL_RCC_ClockConfig+0x208>)
|
|
8001386: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
return HAL_InitTick(uwTickPrio);
|
|
8001388: 4b0b ldr r3, [pc, #44] @ (80013b8 <HAL_RCC_ClockConfig+0x20c>)
|
|
800138a: 681b ldr r3, [r3, #0]
|
|
800138c: 0018 movs r0, r3
|
|
800138e: f7ff f93f bl 8000610 <HAL_InitTick>
|
|
8001392: 0003 movs r3, r0
|
|
}
|
|
8001394: 0018 movs r0, r3
|
|
8001396: 46bd mov sp, r7
|
|
8001398: b004 add sp, #16
|
|
800139a: bd80 pop {r7, pc}
|
|
800139c: 40022000 .word 0x40022000
|
|
80013a0: 00001388 .word 0x00001388
|
|
80013a4: 40021000 .word 0x40021000
|
|
80013a8: fffff0ff .word 0xfffff0ff
|
|
80013ac: ffff8fff .word 0xffff8fff
|
|
80013b0: 08001ed0 .word 0x08001ed0
|
|
80013b4: 20000000 .word 0x20000000
|
|
80013b8: 20000004 .word 0x20000004
|
|
|
|
080013bc <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80013bc: b580 push {r7, lr}
|
|
80013be: b086 sub sp, #24
|
|
80013c0: af00 add r7, sp, #0
|
|
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
|
|
uint32_t sysclockfreq;
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80013c2: 4b3c ldr r3, [pc, #240] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
80013c4: 689b ldr r3, [r3, #8]
|
|
80013c6: 2238 movs r2, #56 @ 0x38
|
|
80013c8: 4013 ands r3, r2
|
|
80013ca: d10f bne.n 80013ec <HAL_RCC_GetSysClockFreq+0x30>
|
|
{
|
|
/* HSISYS can be derived for HSI16 */
|
|
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
|
|
80013cc: 4b39 ldr r3, [pc, #228] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
80013ce: 681b ldr r3, [r3, #0]
|
|
80013d0: 0adb lsrs r3, r3, #11
|
|
80013d2: 2207 movs r2, #7
|
|
80013d4: 4013 ands r3, r2
|
|
80013d6: 2201 movs r2, #1
|
|
80013d8: 409a lsls r2, r3
|
|
80013da: 0013 movs r3, r2
|
|
80013dc: 603b str r3, [r7, #0]
|
|
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = (HSI_VALUE / hsidiv);
|
|
80013de: 6839 ldr r1, [r7, #0]
|
|
80013e0: 4835 ldr r0, [pc, #212] @ (80014b8 <HAL_RCC_GetSysClockFreq+0xfc>)
|
|
80013e2: f7fe fe8d bl 8000100 <__udivsi3>
|
|
80013e6: 0003 movs r3, r0
|
|
80013e8: 613b str r3, [r7, #16]
|
|
80013ea: e05d b.n 80014a8 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
80013ec: 4b31 ldr r3, [pc, #196] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
80013ee: 689b ldr r3, [r3, #8]
|
|
80013f0: 2238 movs r2, #56 @ 0x38
|
|
80013f2: 4013 ands r3, r2
|
|
80013f4: 2b08 cmp r3, #8
|
|
80013f6: d102 bne.n 80013fe <HAL_RCC_GetSysClockFreq+0x42>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
80013f8: 4b30 ldr r3, [pc, #192] @ (80014bc <HAL_RCC_GetSysClockFreq+0x100>)
|
|
80013fa: 613b str r3, [r7, #16]
|
|
80013fc: e054 b.n 80014a8 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
80013fe: 4b2d ldr r3, [pc, #180] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8001400: 689b ldr r3, [r3, #8]
|
|
8001402: 2238 movs r2, #56 @ 0x38
|
|
8001404: 4013 ands r3, r2
|
|
8001406: 2b10 cmp r3, #16
|
|
8001408: d138 bne.n 800147c <HAL_RCC_GetSysClockFreq+0xc0>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
800140a: 4b2a ldr r3, [pc, #168] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
800140c: 68db ldr r3, [r3, #12]
|
|
800140e: 2203 movs r2, #3
|
|
8001410: 4013 ands r3, r2
|
|
8001412: 60fb str r3, [r7, #12]
|
|
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8001414: 4b27 ldr r3, [pc, #156] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8001416: 68db ldr r3, [r3, #12]
|
|
8001418: 091b lsrs r3, r3, #4
|
|
800141a: 2207 movs r2, #7
|
|
800141c: 4013 ands r3, r2
|
|
800141e: 3301 adds r3, #1
|
|
8001420: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
8001422: 68fb ldr r3, [r7, #12]
|
|
8001424: 2b03 cmp r3, #3
|
|
8001426: d10d bne.n 8001444 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8001428: 68b9 ldr r1, [r7, #8]
|
|
800142a: 4824 ldr r0, [pc, #144] @ (80014bc <HAL_RCC_GetSysClockFreq+0x100>)
|
|
800142c: f7fe fe68 bl 8000100 <__udivsi3>
|
|
8001430: 0003 movs r3, r0
|
|
8001432: 0019 movs r1, r3
|
|
8001434: 4b1f ldr r3, [pc, #124] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8001436: 68db ldr r3, [r3, #12]
|
|
8001438: 0a1b lsrs r3, r3, #8
|
|
800143a: 227f movs r2, #127 @ 0x7f
|
|
800143c: 4013 ands r3, r2
|
|
800143e: 434b muls r3, r1
|
|
8001440: 617b str r3, [r7, #20]
|
|
break;
|
|
8001442: e00d b.n 8001460 <HAL_RCC_GetSysClockFreq+0xa4>
|
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
|
|
default: /* HSI16 used as PLL clock source */
|
|
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
|
|
8001444: 68b9 ldr r1, [r7, #8]
|
|
8001446: 481c ldr r0, [pc, #112] @ (80014b8 <HAL_RCC_GetSysClockFreq+0xfc>)
|
|
8001448: f7fe fe5a bl 8000100 <__udivsi3>
|
|
800144c: 0003 movs r3, r0
|
|
800144e: 0019 movs r1, r3
|
|
8001450: 4b18 ldr r3, [pc, #96] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8001452: 68db ldr r3, [r3, #12]
|
|
8001454: 0a1b lsrs r3, r3, #8
|
|
8001456: 227f movs r2, #127 @ 0x7f
|
|
8001458: 4013 ands r3, r2
|
|
800145a: 434b muls r3, r1
|
|
800145c: 617b str r3, [r7, #20]
|
|
break;
|
|
800145e: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
|
|
8001460: 4b14 ldr r3, [pc, #80] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8001462: 68db ldr r3, [r3, #12]
|
|
8001464: 0f5b lsrs r3, r3, #29
|
|
8001466: 2207 movs r2, #7
|
|
8001468: 4013 ands r3, r2
|
|
800146a: 3301 adds r3, #1
|
|
800146c: 607b str r3, [r7, #4]
|
|
sysclockfreq = pllvco / pllr;
|
|
800146e: 6879 ldr r1, [r7, #4]
|
|
8001470: 6978 ldr r0, [r7, #20]
|
|
8001472: f7fe fe45 bl 8000100 <__udivsi3>
|
|
8001476: 0003 movs r3, r0
|
|
8001478: 613b str r3, [r7, #16]
|
|
800147a: e015 b.n 80014a8 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
|
|
800147c: 4b0d ldr r3, [pc, #52] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
800147e: 689b ldr r3, [r3, #8]
|
|
8001480: 2238 movs r2, #56 @ 0x38
|
|
8001482: 4013 ands r3, r2
|
|
8001484: 2b20 cmp r3, #32
|
|
8001486: d103 bne.n 8001490 <HAL_RCC_GetSysClockFreq+0xd4>
|
|
{
|
|
/* LSE used as system clock source */
|
|
sysclockfreq = LSE_VALUE;
|
|
8001488: 2380 movs r3, #128 @ 0x80
|
|
800148a: 021b lsls r3, r3, #8
|
|
800148c: 613b str r3, [r7, #16]
|
|
800148e: e00b b.n 80014a8 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
|
|
8001490: 4b08 ldr r3, [pc, #32] @ (80014b4 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8001492: 689b ldr r3, [r3, #8]
|
|
8001494: 2238 movs r2, #56 @ 0x38
|
|
8001496: 4013 ands r3, r2
|
|
8001498: 2b18 cmp r3, #24
|
|
800149a: d103 bne.n 80014a4 <HAL_RCC_GetSysClockFreq+0xe8>
|
|
{
|
|
/* LSI used as system clock source */
|
|
sysclockfreq = LSI_VALUE;
|
|
800149c: 23fa movs r3, #250 @ 0xfa
|
|
800149e: 01db lsls r3, r3, #7
|
|
80014a0: 613b str r3, [r7, #16]
|
|
80014a2: e001 b.n 80014a8 <HAL_RCC_GetSysClockFreq+0xec>
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = 0U;
|
|
80014a4: 2300 movs r3, #0
|
|
80014a6: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
80014a8: 693b ldr r3, [r7, #16]
|
|
}
|
|
80014aa: 0018 movs r0, r3
|
|
80014ac: 46bd mov sp, r7
|
|
80014ae: b006 add sp, #24
|
|
80014b0: bd80 pop {r7, pc}
|
|
80014b2: 46c0 nop @ (mov r8, r8)
|
|
80014b4: 40021000 .word 0x40021000
|
|
80014b8: 00f42400 .word 0x00f42400
|
|
80014bc: 007a1200 .word 0x007a1200
|
|
|
|
080014c0 <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80014c0: b580 push {r7, lr}
|
|
80014c2: b082 sub sp, #8
|
|
80014c4: af00 add r7, sp, #0
|
|
80014c6: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80014c8: 687b ldr r3, [r7, #4]
|
|
80014ca: 2b00 cmp r3, #0
|
|
80014cc: d101 bne.n 80014d2 <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80014ce: 2301 movs r3, #1
|
|
80014d0: e04a b.n 8001568 <HAL_TIM_PWM_Init+0xa8>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80014d2: 687b ldr r3, [r7, #4]
|
|
80014d4: 223d movs r2, #61 @ 0x3d
|
|
80014d6: 5c9b ldrb r3, [r3, r2]
|
|
80014d8: b2db uxtb r3, r3
|
|
80014da: 2b00 cmp r3, #0
|
|
80014dc: d107 bne.n 80014ee <HAL_TIM_PWM_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80014de: 687b ldr r3, [r7, #4]
|
|
80014e0: 223c movs r2, #60 @ 0x3c
|
|
80014e2: 2100 movs r1, #0
|
|
80014e4: 5499 strb r1, [r3, r2]
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
80014e6: 687b ldr r3, [r7, #4]
|
|
80014e8: 0018 movs r0, r3
|
|
80014ea: f7fe ffab bl 8000444 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80014ee: 687b ldr r3, [r7, #4]
|
|
80014f0: 223d movs r2, #61 @ 0x3d
|
|
80014f2: 2102 movs r1, #2
|
|
80014f4: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80014f6: 687b ldr r3, [r7, #4]
|
|
80014f8: 681a ldr r2, [r3, #0]
|
|
80014fa: 687b ldr r3, [r7, #4]
|
|
80014fc: 3304 adds r3, #4
|
|
80014fe: 0019 movs r1, r3
|
|
8001500: 0010 movs r0, r2
|
|
8001502: f000 f935 bl 8001770 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8001506: 687b ldr r3, [r7, #4]
|
|
8001508: 2248 movs r2, #72 @ 0x48
|
|
800150a: 2101 movs r1, #1
|
|
800150c: 5499 strb r1, [r3, r2]
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800150e: 687b ldr r3, [r7, #4]
|
|
8001510: 223e movs r2, #62 @ 0x3e
|
|
8001512: 2101 movs r1, #1
|
|
8001514: 5499 strb r1, [r3, r2]
|
|
8001516: 687b ldr r3, [r7, #4]
|
|
8001518: 223f movs r2, #63 @ 0x3f
|
|
800151a: 2101 movs r1, #1
|
|
800151c: 5499 strb r1, [r3, r2]
|
|
800151e: 687b ldr r3, [r7, #4]
|
|
8001520: 2240 movs r2, #64 @ 0x40
|
|
8001522: 2101 movs r1, #1
|
|
8001524: 5499 strb r1, [r3, r2]
|
|
8001526: 687b ldr r3, [r7, #4]
|
|
8001528: 2241 movs r2, #65 @ 0x41
|
|
800152a: 2101 movs r1, #1
|
|
800152c: 5499 strb r1, [r3, r2]
|
|
800152e: 687b ldr r3, [r7, #4]
|
|
8001530: 2242 movs r2, #66 @ 0x42
|
|
8001532: 2101 movs r1, #1
|
|
8001534: 5499 strb r1, [r3, r2]
|
|
8001536: 687b ldr r3, [r7, #4]
|
|
8001538: 2243 movs r2, #67 @ 0x43
|
|
800153a: 2101 movs r1, #1
|
|
800153c: 5499 strb r1, [r3, r2]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800153e: 687b ldr r3, [r7, #4]
|
|
8001540: 2244 movs r2, #68 @ 0x44
|
|
8001542: 2101 movs r1, #1
|
|
8001544: 5499 strb r1, [r3, r2]
|
|
8001546: 687b ldr r3, [r7, #4]
|
|
8001548: 2245 movs r2, #69 @ 0x45
|
|
800154a: 2101 movs r1, #1
|
|
800154c: 5499 strb r1, [r3, r2]
|
|
800154e: 687b ldr r3, [r7, #4]
|
|
8001550: 2246 movs r2, #70 @ 0x46
|
|
8001552: 2101 movs r1, #1
|
|
8001554: 5499 strb r1, [r3, r2]
|
|
8001556: 687b ldr r3, [r7, #4]
|
|
8001558: 2247 movs r2, #71 @ 0x47
|
|
800155a: 2101 movs r1, #1
|
|
800155c: 5499 strb r1, [r3, r2]
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800155e: 687b ldr r3, [r7, #4]
|
|
8001560: 223d movs r2, #61 @ 0x3d
|
|
8001562: 2101 movs r1, #1
|
|
8001564: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8001566: 2300 movs r3, #0
|
|
}
|
|
8001568: 0018 movs r0, r3
|
|
800156a: 46bd mov sp, r7
|
|
800156c: b002 add sp, #8
|
|
800156e: bd80 pop {r7, pc}
|
|
|
|
08001570 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
8001570: b580 push {r7, lr}
|
|
8001572: b086 sub sp, #24
|
|
8001574: af00 add r7, sp, #0
|
|
8001576: 60f8 str r0, [r7, #12]
|
|
8001578: 60b9 str r1, [r7, #8]
|
|
800157a: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800157c: 2317 movs r3, #23
|
|
800157e: 18fb adds r3, r7, r3
|
|
8001580: 2200 movs r2, #0
|
|
8001582: 701a strb r2, [r3, #0]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8001584: 68fb ldr r3, [r7, #12]
|
|
8001586: 223c movs r2, #60 @ 0x3c
|
|
8001588: 5c9b ldrb r3, [r3, r2]
|
|
800158a: 2b01 cmp r3, #1
|
|
800158c: d101 bne.n 8001592 <HAL_TIM_PWM_ConfigChannel+0x22>
|
|
800158e: 2302 movs r3, #2
|
|
8001590: e0e5 b.n 800175e <HAL_TIM_PWM_ConfigChannel+0x1ee>
|
|
8001592: 68fb ldr r3, [r7, #12]
|
|
8001594: 223c movs r2, #60 @ 0x3c
|
|
8001596: 2101 movs r1, #1
|
|
8001598: 5499 strb r1, [r3, r2]
|
|
|
|
switch (Channel)
|
|
800159a: 687b ldr r3, [r7, #4]
|
|
800159c: 2b14 cmp r3, #20
|
|
800159e: d900 bls.n 80015a2 <HAL_TIM_PWM_ConfigChannel+0x32>
|
|
80015a0: e0d1 b.n 8001746 <HAL_TIM_PWM_ConfigChannel+0x1d6>
|
|
80015a2: 687b ldr r3, [r7, #4]
|
|
80015a4: 009a lsls r2, r3, #2
|
|
80015a6: 4b70 ldr r3, [pc, #448] @ (8001768 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
|
|
80015a8: 18d3 adds r3, r2, r3
|
|
80015aa: 681b ldr r3, [r3, #0]
|
|
80015ac: 469f mov pc, r3
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
80015ae: 68fb ldr r3, [r7, #12]
|
|
80015b0: 681b ldr r3, [r3, #0]
|
|
80015b2: 68ba ldr r2, [r7, #8]
|
|
80015b4: 0011 movs r1, r2
|
|
80015b6: 0018 movs r0, r3
|
|
80015b8: f000 f954 bl 8001864 <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
80015bc: 68fb ldr r3, [r7, #12]
|
|
80015be: 681b ldr r3, [r3, #0]
|
|
80015c0: 699a ldr r2, [r3, #24]
|
|
80015c2: 68fb ldr r3, [r7, #12]
|
|
80015c4: 681b ldr r3, [r3, #0]
|
|
80015c6: 2108 movs r1, #8
|
|
80015c8: 430a orrs r2, r1
|
|
80015ca: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
80015cc: 68fb ldr r3, [r7, #12]
|
|
80015ce: 681b ldr r3, [r3, #0]
|
|
80015d0: 699a ldr r2, [r3, #24]
|
|
80015d2: 68fb ldr r3, [r7, #12]
|
|
80015d4: 681b ldr r3, [r3, #0]
|
|
80015d6: 2104 movs r1, #4
|
|
80015d8: 438a bics r2, r1
|
|
80015da: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
80015dc: 68fb ldr r3, [r7, #12]
|
|
80015de: 681b ldr r3, [r3, #0]
|
|
80015e0: 6999 ldr r1, [r3, #24]
|
|
80015e2: 68bb ldr r3, [r7, #8]
|
|
80015e4: 691a ldr r2, [r3, #16]
|
|
80015e6: 68fb ldr r3, [r7, #12]
|
|
80015e8: 681b ldr r3, [r3, #0]
|
|
80015ea: 430a orrs r2, r1
|
|
80015ec: 619a str r2, [r3, #24]
|
|
break;
|
|
80015ee: e0af b.n 8001750 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
80015f0: 68fb ldr r3, [r7, #12]
|
|
80015f2: 681b ldr r3, [r3, #0]
|
|
80015f4: 68ba ldr r2, [r7, #8]
|
|
80015f6: 0011 movs r1, r2
|
|
80015f8: 0018 movs r0, r3
|
|
80015fa: f000 f9b3 bl 8001964 <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
80015fe: 68fb ldr r3, [r7, #12]
|
|
8001600: 681b ldr r3, [r3, #0]
|
|
8001602: 699a ldr r2, [r3, #24]
|
|
8001604: 68fb ldr r3, [r7, #12]
|
|
8001606: 681b ldr r3, [r3, #0]
|
|
8001608: 2180 movs r1, #128 @ 0x80
|
|
800160a: 0109 lsls r1, r1, #4
|
|
800160c: 430a orrs r2, r1
|
|
800160e: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
8001610: 68fb ldr r3, [r7, #12]
|
|
8001612: 681b ldr r3, [r3, #0]
|
|
8001614: 699a ldr r2, [r3, #24]
|
|
8001616: 68fb ldr r3, [r7, #12]
|
|
8001618: 681b ldr r3, [r3, #0]
|
|
800161a: 4954 ldr r1, [pc, #336] @ (800176c <HAL_TIM_PWM_ConfigChannel+0x1fc>)
|
|
800161c: 400a ands r2, r1
|
|
800161e: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
8001620: 68fb ldr r3, [r7, #12]
|
|
8001622: 681b ldr r3, [r3, #0]
|
|
8001624: 6999 ldr r1, [r3, #24]
|
|
8001626: 68bb ldr r3, [r7, #8]
|
|
8001628: 691b ldr r3, [r3, #16]
|
|
800162a: 021a lsls r2, r3, #8
|
|
800162c: 68fb ldr r3, [r7, #12]
|
|
800162e: 681b ldr r3, [r3, #0]
|
|
8001630: 430a orrs r2, r1
|
|
8001632: 619a str r2, [r3, #24]
|
|
break;
|
|
8001634: e08c b.n 8001750 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8001636: 68fb ldr r3, [r7, #12]
|
|
8001638: 681b ldr r3, [r3, #0]
|
|
800163a: 68ba ldr r2, [r7, #8]
|
|
800163c: 0011 movs r1, r2
|
|
800163e: 0018 movs r0, r3
|
|
8001640: f000 fa0e bl 8001a60 <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
8001644: 68fb ldr r3, [r7, #12]
|
|
8001646: 681b ldr r3, [r3, #0]
|
|
8001648: 69da ldr r2, [r3, #28]
|
|
800164a: 68fb ldr r3, [r7, #12]
|
|
800164c: 681b ldr r3, [r3, #0]
|
|
800164e: 2108 movs r1, #8
|
|
8001650: 430a orrs r2, r1
|
|
8001652: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
8001654: 68fb ldr r3, [r7, #12]
|
|
8001656: 681b ldr r3, [r3, #0]
|
|
8001658: 69da ldr r2, [r3, #28]
|
|
800165a: 68fb ldr r3, [r7, #12]
|
|
800165c: 681b ldr r3, [r3, #0]
|
|
800165e: 2104 movs r1, #4
|
|
8001660: 438a bics r2, r1
|
|
8001662: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
8001664: 68fb ldr r3, [r7, #12]
|
|
8001666: 681b ldr r3, [r3, #0]
|
|
8001668: 69d9 ldr r1, [r3, #28]
|
|
800166a: 68bb ldr r3, [r7, #8]
|
|
800166c: 691a ldr r2, [r3, #16]
|
|
800166e: 68fb ldr r3, [r7, #12]
|
|
8001670: 681b ldr r3, [r3, #0]
|
|
8001672: 430a orrs r2, r1
|
|
8001674: 61da str r2, [r3, #28]
|
|
break;
|
|
8001676: e06b b.n 8001750 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
8001678: 68fb ldr r3, [r7, #12]
|
|
800167a: 681b ldr r3, [r3, #0]
|
|
800167c: 68ba ldr r2, [r7, #8]
|
|
800167e: 0011 movs r1, r2
|
|
8001680: 0018 movs r0, r3
|
|
8001682: f000 fa6f bl 8001b64 <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
8001686: 68fb ldr r3, [r7, #12]
|
|
8001688: 681b ldr r3, [r3, #0]
|
|
800168a: 69da ldr r2, [r3, #28]
|
|
800168c: 68fb ldr r3, [r7, #12]
|
|
800168e: 681b ldr r3, [r3, #0]
|
|
8001690: 2180 movs r1, #128 @ 0x80
|
|
8001692: 0109 lsls r1, r1, #4
|
|
8001694: 430a orrs r2, r1
|
|
8001696: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
8001698: 68fb ldr r3, [r7, #12]
|
|
800169a: 681b ldr r3, [r3, #0]
|
|
800169c: 69da ldr r2, [r3, #28]
|
|
800169e: 68fb ldr r3, [r7, #12]
|
|
80016a0: 681b ldr r3, [r3, #0]
|
|
80016a2: 4932 ldr r1, [pc, #200] @ (800176c <HAL_TIM_PWM_ConfigChannel+0x1fc>)
|
|
80016a4: 400a ands r2, r1
|
|
80016a6: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
80016a8: 68fb ldr r3, [r7, #12]
|
|
80016aa: 681b ldr r3, [r3, #0]
|
|
80016ac: 69d9 ldr r1, [r3, #28]
|
|
80016ae: 68bb ldr r3, [r7, #8]
|
|
80016b0: 691b ldr r3, [r3, #16]
|
|
80016b2: 021a lsls r2, r3, #8
|
|
80016b4: 68fb ldr r3, [r7, #12]
|
|
80016b6: 681b ldr r3, [r3, #0]
|
|
80016b8: 430a orrs r2, r1
|
|
80016ba: 61da str r2, [r3, #28]
|
|
break;
|
|
80016bc: e048 b.n 8001750 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
80016be: 68fb ldr r3, [r7, #12]
|
|
80016c0: 681b ldr r3, [r3, #0]
|
|
80016c2: 68ba ldr r2, [r7, #8]
|
|
80016c4: 0011 movs r1, r2
|
|
80016c6: 0018 movs r0, r3
|
|
80016c8: f000 fab0 bl 8001c2c <TIM_OC5_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
80016cc: 68fb ldr r3, [r7, #12]
|
|
80016ce: 681b ldr r3, [r3, #0]
|
|
80016d0: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
80016d2: 68fb ldr r3, [r7, #12]
|
|
80016d4: 681b ldr r3, [r3, #0]
|
|
80016d6: 2108 movs r1, #8
|
|
80016d8: 430a orrs r2, r1
|
|
80016da: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
80016dc: 68fb ldr r3, [r7, #12]
|
|
80016de: 681b ldr r3, [r3, #0]
|
|
80016e0: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
80016e2: 68fb ldr r3, [r7, #12]
|
|
80016e4: 681b ldr r3, [r3, #0]
|
|
80016e6: 2104 movs r1, #4
|
|
80016e8: 438a bics r2, r1
|
|
80016ea: 655a str r2, [r3, #84] @ 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
80016ec: 68fb ldr r3, [r7, #12]
|
|
80016ee: 681b ldr r3, [r3, #0]
|
|
80016f0: 6d59 ldr r1, [r3, #84] @ 0x54
|
|
80016f2: 68bb ldr r3, [r7, #8]
|
|
80016f4: 691a ldr r2, [r3, #16]
|
|
80016f6: 68fb ldr r3, [r7, #12]
|
|
80016f8: 681b ldr r3, [r3, #0]
|
|
80016fa: 430a orrs r2, r1
|
|
80016fc: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
80016fe: e027 b.n 8001750 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
8001700: 68fb ldr r3, [r7, #12]
|
|
8001702: 681b ldr r3, [r3, #0]
|
|
8001704: 68ba ldr r2, [r7, #8]
|
|
8001706: 0011 movs r1, r2
|
|
8001708: 0018 movs r0, r3
|
|
800170a: f000 fae9 bl 8001ce0 <TIM_OC6_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
800170e: 68fb ldr r3, [r7, #12]
|
|
8001710: 681b ldr r3, [r3, #0]
|
|
8001712: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
8001714: 68fb ldr r3, [r7, #12]
|
|
8001716: 681b ldr r3, [r3, #0]
|
|
8001718: 2180 movs r1, #128 @ 0x80
|
|
800171a: 0109 lsls r1, r1, #4
|
|
800171c: 430a orrs r2, r1
|
|
800171e: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
8001720: 68fb ldr r3, [r7, #12]
|
|
8001722: 681b ldr r3, [r3, #0]
|
|
8001724: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
8001726: 68fb ldr r3, [r7, #12]
|
|
8001728: 681b ldr r3, [r3, #0]
|
|
800172a: 4910 ldr r1, [pc, #64] @ (800176c <HAL_TIM_PWM_ConfigChannel+0x1fc>)
|
|
800172c: 400a ands r2, r1
|
|
800172e: 655a str r2, [r3, #84] @ 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
8001730: 68fb ldr r3, [r7, #12]
|
|
8001732: 681b ldr r3, [r3, #0]
|
|
8001734: 6d59 ldr r1, [r3, #84] @ 0x54
|
|
8001736: 68bb ldr r3, [r7, #8]
|
|
8001738: 691b ldr r3, [r3, #16]
|
|
800173a: 021a lsls r2, r3, #8
|
|
800173c: 68fb ldr r3, [r7, #12]
|
|
800173e: 681b ldr r3, [r3, #0]
|
|
8001740: 430a orrs r2, r1
|
|
8001742: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
8001744: e004 b.n 8001750 <HAL_TIM_PWM_ConfigChannel+0x1e0>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8001746: 2317 movs r3, #23
|
|
8001748: 18fb adds r3, r7, r3
|
|
800174a: 2201 movs r2, #1
|
|
800174c: 701a strb r2, [r3, #0]
|
|
break;
|
|
800174e: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8001750: 68fb ldr r3, [r7, #12]
|
|
8001752: 223c movs r2, #60 @ 0x3c
|
|
8001754: 2100 movs r1, #0
|
|
8001756: 5499 strb r1, [r3, r2]
|
|
|
|
return status;
|
|
8001758: 2317 movs r3, #23
|
|
800175a: 18fb adds r3, r7, r3
|
|
800175c: 781b ldrb r3, [r3, #0]
|
|
}
|
|
800175e: 0018 movs r0, r3
|
|
8001760: 46bd mov sp, r7
|
|
8001762: b006 add sp, #24
|
|
8001764: bd80 pop {r7, pc}
|
|
8001766: 46c0 nop @ (mov r8, r8)
|
|
8001768: 08001f10 .word 0x08001f10
|
|
800176c: fffffbff .word 0xfffffbff
|
|
|
|
08001770 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8001770: b580 push {r7, lr}
|
|
8001772: b084 sub sp, #16
|
|
8001774: af00 add r7, sp, #0
|
|
8001776: 6078 str r0, [r7, #4]
|
|
8001778: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800177a: 687b ldr r3, [r7, #4]
|
|
800177c: 681b ldr r3, [r3, #0]
|
|
800177e: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8001780: 687b ldr r3, [r7, #4]
|
|
8001782: 4a32 ldr r2, [pc, #200] @ (800184c <TIM_Base_SetConfig+0xdc>)
|
|
8001784: 4293 cmp r3, r2
|
|
8001786: d003 beq.n 8001790 <TIM_Base_SetConfig+0x20>
|
|
8001788: 687b ldr r3, [r7, #4]
|
|
800178a: 4a31 ldr r2, [pc, #196] @ (8001850 <TIM_Base_SetConfig+0xe0>)
|
|
800178c: 4293 cmp r3, r2
|
|
800178e: d108 bne.n 80017a2 <TIM_Base_SetConfig+0x32>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8001790: 68fb ldr r3, [r7, #12]
|
|
8001792: 2270 movs r2, #112 @ 0x70
|
|
8001794: 4393 bics r3, r2
|
|
8001796: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
8001798: 683b ldr r3, [r7, #0]
|
|
800179a: 685b ldr r3, [r3, #4]
|
|
800179c: 68fa ldr r2, [r7, #12]
|
|
800179e: 4313 orrs r3, r2
|
|
80017a0: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80017a2: 687b ldr r3, [r7, #4]
|
|
80017a4: 4a29 ldr r2, [pc, #164] @ (800184c <TIM_Base_SetConfig+0xdc>)
|
|
80017a6: 4293 cmp r3, r2
|
|
80017a8: d00f beq.n 80017ca <TIM_Base_SetConfig+0x5a>
|
|
80017aa: 687b ldr r3, [r7, #4]
|
|
80017ac: 4a28 ldr r2, [pc, #160] @ (8001850 <TIM_Base_SetConfig+0xe0>)
|
|
80017ae: 4293 cmp r3, r2
|
|
80017b0: d00b beq.n 80017ca <TIM_Base_SetConfig+0x5a>
|
|
80017b2: 687b ldr r3, [r7, #4]
|
|
80017b4: 4a27 ldr r2, [pc, #156] @ (8001854 <TIM_Base_SetConfig+0xe4>)
|
|
80017b6: 4293 cmp r3, r2
|
|
80017b8: d007 beq.n 80017ca <TIM_Base_SetConfig+0x5a>
|
|
80017ba: 687b ldr r3, [r7, #4]
|
|
80017bc: 4a26 ldr r2, [pc, #152] @ (8001858 <TIM_Base_SetConfig+0xe8>)
|
|
80017be: 4293 cmp r3, r2
|
|
80017c0: d003 beq.n 80017ca <TIM_Base_SetConfig+0x5a>
|
|
80017c2: 687b ldr r3, [r7, #4]
|
|
80017c4: 4a25 ldr r2, [pc, #148] @ (800185c <TIM_Base_SetConfig+0xec>)
|
|
80017c6: 4293 cmp r3, r2
|
|
80017c8: d108 bne.n 80017dc <TIM_Base_SetConfig+0x6c>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
80017ca: 68fb ldr r3, [r7, #12]
|
|
80017cc: 4a24 ldr r2, [pc, #144] @ (8001860 <TIM_Base_SetConfig+0xf0>)
|
|
80017ce: 4013 ands r3, r2
|
|
80017d0: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
80017d2: 683b ldr r3, [r7, #0]
|
|
80017d4: 68db ldr r3, [r3, #12]
|
|
80017d6: 68fa ldr r2, [r7, #12]
|
|
80017d8: 4313 orrs r3, r2
|
|
80017da: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
80017dc: 68fb ldr r3, [r7, #12]
|
|
80017de: 2280 movs r2, #128 @ 0x80
|
|
80017e0: 4393 bics r3, r2
|
|
80017e2: 001a movs r2, r3
|
|
80017e4: 683b ldr r3, [r7, #0]
|
|
80017e6: 695b ldr r3, [r3, #20]
|
|
80017e8: 4313 orrs r3, r2
|
|
80017ea: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
80017ec: 687b ldr r3, [r7, #4]
|
|
80017ee: 68fa ldr r2, [r7, #12]
|
|
80017f0: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
80017f2: 683b ldr r3, [r7, #0]
|
|
80017f4: 689a ldr r2, [r3, #8]
|
|
80017f6: 687b ldr r3, [r7, #4]
|
|
80017f8: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
80017fa: 683b ldr r3, [r7, #0]
|
|
80017fc: 681a ldr r2, [r3, #0]
|
|
80017fe: 687b ldr r3, [r7, #4]
|
|
8001800: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8001802: 687b ldr r3, [r7, #4]
|
|
8001804: 4a11 ldr r2, [pc, #68] @ (800184c <TIM_Base_SetConfig+0xdc>)
|
|
8001806: 4293 cmp r3, r2
|
|
8001808: d007 beq.n 800181a <TIM_Base_SetConfig+0xaa>
|
|
800180a: 687b ldr r3, [r7, #4]
|
|
800180c: 4a12 ldr r2, [pc, #72] @ (8001858 <TIM_Base_SetConfig+0xe8>)
|
|
800180e: 4293 cmp r3, r2
|
|
8001810: d003 beq.n 800181a <TIM_Base_SetConfig+0xaa>
|
|
8001812: 687b ldr r3, [r7, #4]
|
|
8001814: 4a11 ldr r2, [pc, #68] @ (800185c <TIM_Base_SetConfig+0xec>)
|
|
8001816: 4293 cmp r3, r2
|
|
8001818: d103 bne.n 8001822 <TIM_Base_SetConfig+0xb2>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800181a: 683b ldr r3, [r7, #0]
|
|
800181c: 691a ldr r2, [r3, #16]
|
|
800181e: 687b ldr r3, [r7, #4]
|
|
8001820: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8001822: 687b ldr r3, [r7, #4]
|
|
8001824: 2201 movs r2, #1
|
|
8001826: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
8001828: 687b ldr r3, [r7, #4]
|
|
800182a: 691b ldr r3, [r3, #16]
|
|
800182c: 2201 movs r2, #1
|
|
800182e: 4013 ands r3, r2
|
|
8001830: 2b01 cmp r3, #1
|
|
8001832: d106 bne.n 8001842 <TIM_Base_SetConfig+0xd2>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
8001834: 687b ldr r3, [r7, #4]
|
|
8001836: 691b ldr r3, [r3, #16]
|
|
8001838: 2201 movs r2, #1
|
|
800183a: 4393 bics r3, r2
|
|
800183c: 001a movs r2, r3
|
|
800183e: 687b ldr r3, [r7, #4]
|
|
8001840: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
8001842: 46c0 nop @ (mov r8, r8)
|
|
8001844: 46bd mov sp, r7
|
|
8001846: b004 add sp, #16
|
|
8001848: bd80 pop {r7, pc}
|
|
800184a: 46c0 nop @ (mov r8, r8)
|
|
800184c: 40012c00 .word 0x40012c00
|
|
8001850: 40000400 .word 0x40000400
|
|
8001854: 40002000 .word 0x40002000
|
|
8001858: 40014400 .word 0x40014400
|
|
800185c: 40014800 .word 0x40014800
|
|
8001860: fffffcff .word 0xfffffcff
|
|
|
|
08001864 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001864: b580 push {r7, lr}
|
|
8001866: b086 sub sp, #24
|
|
8001868: af00 add r7, sp, #0
|
|
800186a: 6078 str r0, [r7, #4]
|
|
800186c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800186e: 687b ldr r3, [r7, #4]
|
|
8001870: 6a1b ldr r3, [r3, #32]
|
|
8001872: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8001874: 687b ldr r3, [r7, #4]
|
|
8001876: 6a1b ldr r3, [r3, #32]
|
|
8001878: 2201 movs r2, #1
|
|
800187a: 4393 bics r3, r2
|
|
800187c: 001a movs r2, r3
|
|
800187e: 687b ldr r3, [r7, #4]
|
|
8001880: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001882: 687b ldr r3, [r7, #4]
|
|
8001884: 685b ldr r3, [r3, #4]
|
|
8001886: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8001888: 687b ldr r3, [r7, #4]
|
|
800188a: 699b ldr r3, [r3, #24]
|
|
800188c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
800188e: 68fb ldr r3, [r7, #12]
|
|
8001890: 4a2e ldr r2, [pc, #184] @ (800194c <TIM_OC1_SetConfig+0xe8>)
|
|
8001892: 4013 ands r3, r2
|
|
8001894: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8001896: 68fb ldr r3, [r7, #12]
|
|
8001898: 2203 movs r2, #3
|
|
800189a: 4393 bics r3, r2
|
|
800189c: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800189e: 683b ldr r3, [r7, #0]
|
|
80018a0: 681b ldr r3, [r3, #0]
|
|
80018a2: 68fa ldr r2, [r7, #12]
|
|
80018a4: 4313 orrs r3, r2
|
|
80018a6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
80018a8: 697b ldr r3, [r7, #20]
|
|
80018aa: 2202 movs r2, #2
|
|
80018ac: 4393 bics r3, r2
|
|
80018ae: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
80018b0: 683b ldr r3, [r7, #0]
|
|
80018b2: 689b ldr r3, [r3, #8]
|
|
80018b4: 697a ldr r2, [r7, #20]
|
|
80018b6: 4313 orrs r3, r2
|
|
80018b8: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
80018ba: 687b ldr r3, [r7, #4]
|
|
80018bc: 4a24 ldr r2, [pc, #144] @ (8001950 <TIM_OC1_SetConfig+0xec>)
|
|
80018be: 4293 cmp r3, r2
|
|
80018c0: d007 beq.n 80018d2 <TIM_OC1_SetConfig+0x6e>
|
|
80018c2: 687b ldr r3, [r7, #4]
|
|
80018c4: 4a23 ldr r2, [pc, #140] @ (8001954 <TIM_OC1_SetConfig+0xf0>)
|
|
80018c6: 4293 cmp r3, r2
|
|
80018c8: d003 beq.n 80018d2 <TIM_OC1_SetConfig+0x6e>
|
|
80018ca: 687b ldr r3, [r7, #4]
|
|
80018cc: 4a22 ldr r2, [pc, #136] @ (8001958 <TIM_OC1_SetConfig+0xf4>)
|
|
80018ce: 4293 cmp r3, r2
|
|
80018d0: d10c bne.n 80018ec <TIM_OC1_SetConfig+0x88>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
80018d2: 697b ldr r3, [r7, #20]
|
|
80018d4: 2208 movs r2, #8
|
|
80018d6: 4393 bics r3, r2
|
|
80018d8: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
80018da: 683b ldr r3, [r7, #0]
|
|
80018dc: 68db ldr r3, [r3, #12]
|
|
80018de: 697a ldr r2, [r7, #20]
|
|
80018e0: 4313 orrs r3, r2
|
|
80018e2: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
80018e4: 697b ldr r3, [r7, #20]
|
|
80018e6: 2204 movs r2, #4
|
|
80018e8: 4393 bics r3, r2
|
|
80018ea: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80018ec: 687b ldr r3, [r7, #4]
|
|
80018ee: 4a18 ldr r2, [pc, #96] @ (8001950 <TIM_OC1_SetConfig+0xec>)
|
|
80018f0: 4293 cmp r3, r2
|
|
80018f2: d007 beq.n 8001904 <TIM_OC1_SetConfig+0xa0>
|
|
80018f4: 687b ldr r3, [r7, #4]
|
|
80018f6: 4a17 ldr r2, [pc, #92] @ (8001954 <TIM_OC1_SetConfig+0xf0>)
|
|
80018f8: 4293 cmp r3, r2
|
|
80018fa: d003 beq.n 8001904 <TIM_OC1_SetConfig+0xa0>
|
|
80018fc: 687b ldr r3, [r7, #4]
|
|
80018fe: 4a16 ldr r2, [pc, #88] @ (8001958 <TIM_OC1_SetConfig+0xf4>)
|
|
8001900: 4293 cmp r3, r2
|
|
8001902: d111 bne.n 8001928 <TIM_OC1_SetConfig+0xc4>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8001904: 693b ldr r3, [r7, #16]
|
|
8001906: 4a15 ldr r2, [pc, #84] @ (800195c <TIM_OC1_SetConfig+0xf8>)
|
|
8001908: 4013 ands r3, r2
|
|
800190a: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
800190c: 693b ldr r3, [r7, #16]
|
|
800190e: 4a14 ldr r2, [pc, #80] @ (8001960 <TIM_OC1_SetConfig+0xfc>)
|
|
8001910: 4013 ands r3, r2
|
|
8001912: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8001914: 683b ldr r3, [r7, #0]
|
|
8001916: 695b ldr r3, [r3, #20]
|
|
8001918: 693a ldr r2, [r7, #16]
|
|
800191a: 4313 orrs r3, r2
|
|
800191c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
800191e: 683b ldr r3, [r7, #0]
|
|
8001920: 699b ldr r3, [r3, #24]
|
|
8001922: 693a ldr r2, [r7, #16]
|
|
8001924: 4313 orrs r3, r2
|
|
8001926: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001928: 687b ldr r3, [r7, #4]
|
|
800192a: 693a ldr r2, [r7, #16]
|
|
800192c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800192e: 687b ldr r3, [r7, #4]
|
|
8001930: 68fa ldr r2, [r7, #12]
|
|
8001932: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8001934: 683b ldr r3, [r7, #0]
|
|
8001936: 685a ldr r2, [r3, #4]
|
|
8001938: 687b ldr r3, [r7, #4]
|
|
800193a: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800193c: 687b ldr r3, [r7, #4]
|
|
800193e: 697a ldr r2, [r7, #20]
|
|
8001940: 621a str r2, [r3, #32]
|
|
}
|
|
8001942: 46c0 nop @ (mov r8, r8)
|
|
8001944: 46bd mov sp, r7
|
|
8001946: b006 add sp, #24
|
|
8001948: bd80 pop {r7, pc}
|
|
800194a: 46c0 nop @ (mov r8, r8)
|
|
800194c: fffeff8f .word 0xfffeff8f
|
|
8001950: 40012c00 .word 0x40012c00
|
|
8001954: 40014400 .word 0x40014400
|
|
8001958: 40014800 .word 0x40014800
|
|
800195c: fffffeff .word 0xfffffeff
|
|
8001960: fffffdff .word 0xfffffdff
|
|
|
|
08001964 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001964: b580 push {r7, lr}
|
|
8001966: b086 sub sp, #24
|
|
8001968: af00 add r7, sp, #0
|
|
800196a: 6078 str r0, [r7, #4]
|
|
800196c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800196e: 687b ldr r3, [r7, #4]
|
|
8001970: 6a1b ldr r3, [r3, #32]
|
|
8001972: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8001974: 687b ldr r3, [r7, #4]
|
|
8001976: 6a1b ldr r3, [r3, #32]
|
|
8001978: 2210 movs r2, #16
|
|
800197a: 4393 bics r3, r2
|
|
800197c: 001a movs r2, r3
|
|
800197e: 687b ldr r3, [r7, #4]
|
|
8001980: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001982: 687b ldr r3, [r7, #4]
|
|
8001984: 685b ldr r3, [r3, #4]
|
|
8001986: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8001988: 687b ldr r3, [r7, #4]
|
|
800198a: 699b ldr r3, [r3, #24]
|
|
800198c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
800198e: 68fb ldr r3, [r7, #12]
|
|
8001990: 4a2c ldr r2, [pc, #176] @ (8001a44 <TIM_OC2_SetConfig+0xe0>)
|
|
8001992: 4013 ands r3, r2
|
|
8001994: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8001996: 68fb ldr r3, [r7, #12]
|
|
8001998: 4a2b ldr r2, [pc, #172] @ (8001a48 <TIM_OC2_SetConfig+0xe4>)
|
|
800199a: 4013 ands r3, r2
|
|
800199c: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800199e: 683b ldr r3, [r7, #0]
|
|
80019a0: 681b ldr r3, [r3, #0]
|
|
80019a2: 021b lsls r3, r3, #8
|
|
80019a4: 68fa ldr r2, [r7, #12]
|
|
80019a6: 4313 orrs r3, r2
|
|
80019a8: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
80019aa: 697b ldr r3, [r7, #20]
|
|
80019ac: 2220 movs r2, #32
|
|
80019ae: 4393 bics r3, r2
|
|
80019b0: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
80019b2: 683b ldr r3, [r7, #0]
|
|
80019b4: 689b ldr r3, [r3, #8]
|
|
80019b6: 011b lsls r3, r3, #4
|
|
80019b8: 697a ldr r2, [r7, #20]
|
|
80019ba: 4313 orrs r3, r2
|
|
80019bc: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
80019be: 687b ldr r3, [r7, #4]
|
|
80019c0: 4a22 ldr r2, [pc, #136] @ (8001a4c <TIM_OC2_SetConfig+0xe8>)
|
|
80019c2: 4293 cmp r3, r2
|
|
80019c4: d10d bne.n 80019e2 <TIM_OC2_SetConfig+0x7e>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
80019c6: 697b ldr r3, [r7, #20]
|
|
80019c8: 2280 movs r2, #128 @ 0x80
|
|
80019ca: 4393 bics r3, r2
|
|
80019cc: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
80019ce: 683b ldr r3, [r7, #0]
|
|
80019d0: 68db ldr r3, [r3, #12]
|
|
80019d2: 011b lsls r3, r3, #4
|
|
80019d4: 697a ldr r2, [r7, #20]
|
|
80019d6: 4313 orrs r3, r2
|
|
80019d8: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
80019da: 697b ldr r3, [r7, #20]
|
|
80019dc: 2240 movs r2, #64 @ 0x40
|
|
80019de: 4393 bics r3, r2
|
|
80019e0: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80019e2: 687b ldr r3, [r7, #4]
|
|
80019e4: 4a19 ldr r2, [pc, #100] @ (8001a4c <TIM_OC2_SetConfig+0xe8>)
|
|
80019e6: 4293 cmp r3, r2
|
|
80019e8: d007 beq.n 80019fa <TIM_OC2_SetConfig+0x96>
|
|
80019ea: 687b ldr r3, [r7, #4]
|
|
80019ec: 4a18 ldr r2, [pc, #96] @ (8001a50 <TIM_OC2_SetConfig+0xec>)
|
|
80019ee: 4293 cmp r3, r2
|
|
80019f0: d003 beq.n 80019fa <TIM_OC2_SetConfig+0x96>
|
|
80019f2: 687b ldr r3, [r7, #4]
|
|
80019f4: 4a17 ldr r2, [pc, #92] @ (8001a54 <TIM_OC2_SetConfig+0xf0>)
|
|
80019f6: 4293 cmp r3, r2
|
|
80019f8: d113 bne.n 8001a22 <TIM_OC2_SetConfig+0xbe>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
80019fa: 693b ldr r3, [r7, #16]
|
|
80019fc: 4a16 ldr r2, [pc, #88] @ (8001a58 <TIM_OC2_SetConfig+0xf4>)
|
|
80019fe: 4013 ands r3, r2
|
|
8001a00: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8001a02: 693b ldr r3, [r7, #16]
|
|
8001a04: 4a15 ldr r2, [pc, #84] @ (8001a5c <TIM_OC2_SetConfig+0xf8>)
|
|
8001a06: 4013 ands r3, r2
|
|
8001a08: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8001a0a: 683b ldr r3, [r7, #0]
|
|
8001a0c: 695b ldr r3, [r3, #20]
|
|
8001a0e: 009b lsls r3, r3, #2
|
|
8001a10: 693a ldr r2, [r7, #16]
|
|
8001a12: 4313 orrs r3, r2
|
|
8001a14: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8001a16: 683b ldr r3, [r7, #0]
|
|
8001a18: 699b ldr r3, [r3, #24]
|
|
8001a1a: 009b lsls r3, r3, #2
|
|
8001a1c: 693a ldr r2, [r7, #16]
|
|
8001a1e: 4313 orrs r3, r2
|
|
8001a20: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001a22: 687b ldr r3, [r7, #4]
|
|
8001a24: 693a ldr r2, [r7, #16]
|
|
8001a26: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8001a28: 687b ldr r3, [r7, #4]
|
|
8001a2a: 68fa ldr r2, [r7, #12]
|
|
8001a2c: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8001a2e: 683b ldr r3, [r7, #0]
|
|
8001a30: 685a ldr r2, [r3, #4]
|
|
8001a32: 687b ldr r3, [r7, #4]
|
|
8001a34: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001a36: 687b ldr r3, [r7, #4]
|
|
8001a38: 697a ldr r2, [r7, #20]
|
|
8001a3a: 621a str r2, [r3, #32]
|
|
}
|
|
8001a3c: 46c0 nop @ (mov r8, r8)
|
|
8001a3e: 46bd mov sp, r7
|
|
8001a40: b006 add sp, #24
|
|
8001a42: bd80 pop {r7, pc}
|
|
8001a44: feff8fff .word 0xfeff8fff
|
|
8001a48: fffffcff .word 0xfffffcff
|
|
8001a4c: 40012c00 .word 0x40012c00
|
|
8001a50: 40014400 .word 0x40014400
|
|
8001a54: 40014800 .word 0x40014800
|
|
8001a58: fffffbff .word 0xfffffbff
|
|
8001a5c: fffff7ff .word 0xfffff7ff
|
|
|
|
08001a60 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001a60: b580 push {r7, lr}
|
|
8001a62: b086 sub sp, #24
|
|
8001a64: af00 add r7, sp, #0
|
|
8001a66: 6078 str r0, [r7, #4]
|
|
8001a68: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001a6a: 687b ldr r3, [r7, #4]
|
|
8001a6c: 6a1b ldr r3, [r3, #32]
|
|
8001a6e: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8001a70: 687b ldr r3, [r7, #4]
|
|
8001a72: 6a1b ldr r3, [r3, #32]
|
|
8001a74: 4a31 ldr r2, [pc, #196] @ (8001b3c <TIM_OC3_SetConfig+0xdc>)
|
|
8001a76: 401a ands r2, r3
|
|
8001a78: 687b ldr r3, [r7, #4]
|
|
8001a7a: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001a7c: 687b ldr r3, [r7, #4]
|
|
8001a7e: 685b ldr r3, [r3, #4]
|
|
8001a80: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8001a82: 687b ldr r3, [r7, #4]
|
|
8001a84: 69db ldr r3, [r3, #28]
|
|
8001a86: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8001a88: 68fb ldr r3, [r7, #12]
|
|
8001a8a: 4a2d ldr r2, [pc, #180] @ (8001b40 <TIM_OC3_SetConfig+0xe0>)
|
|
8001a8c: 4013 ands r3, r2
|
|
8001a8e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
8001a90: 68fb ldr r3, [r7, #12]
|
|
8001a92: 2203 movs r2, #3
|
|
8001a94: 4393 bics r3, r2
|
|
8001a96: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8001a98: 683b ldr r3, [r7, #0]
|
|
8001a9a: 681b ldr r3, [r3, #0]
|
|
8001a9c: 68fa ldr r2, [r7, #12]
|
|
8001a9e: 4313 orrs r3, r2
|
|
8001aa0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8001aa2: 697b ldr r3, [r7, #20]
|
|
8001aa4: 4a27 ldr r2, [pc, #156] @ (8001b44 <TIM_OC3_SetConfig+0xe4>)
|
|
8001aa6: 4013 ands r3, r2
|
|
8001aa8: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8001aaa: 683b ldr r3, [r7, #0]
|
|
8001aac: 689b ldr r3, [r3, #8]
|
|
8001aae: 021b lsls r3, r3, #8
|
|
8001ab0: 697a ldr r2, [r7, #20]
|
|
8001ab2: 4313 orrs r3, r2
|
|
8001ab4: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8001ab6: 687b ldr r3, [r7, #4]
|
|
8001ab8: 4a23 ldr r2, [pc, #140] @ (8001b48 <TIM_OC3_SetConfig+0xe8>)
|
|
8001aba: 4293 cmp r3, r2
|
|
8001abc: d10d bne.n 8001ada <TIM_OC3_SetConfig+0x7a>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8001abe: 697b ldr r3, [r7, #20]
|
|
8001ac0: 4a22 ldr r2, [pc, #136] @ (8001b4c <TIM_OC3_SetConfig+0xec>)
|
|
8001ac2: 4013 ands r3, r2
|
|
8001ac4: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8001ac6: 683b ldr r3, [r7, #0]
|
|
8001ac8: 68db ldr r3, [r3, #12]
|
|
8001aca: 021b lsls r3, r3, #8
|
|
8001acc: 697a ldr r2, [r7, #20]
|
|
8001ace: 4313 orrs r3, r2
|
|
8001ad0: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8001ad2: 697b ldr r3, [r7, #20]
|
|
8001ad4: 4a1e ldr r2, [pc, #120] @ (8001b50 <TIM_OC3_SetConfig+0xf0>)
|
|
8001ad6: 4013 ands r3, r2
|
|
8001ad8: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001ada: 687b ldr r3, [r7, #4]
|
|
8001adc: 4a1a ldr r2, [pc, #104] @ (8001b48 <TIM_OC3_SetConfig+0xe8>)
|
|
8001ade: 4293 cmp r3, r2
|
|
8001ae0: d007 beq.n 8001af2 <TIM_OC3_SetConfig+0x92>
|
|
8001ae2: 687b ldr r3, [r7, #4]
|
|
8001ae4: 4a1b ldr r2, [pc, #108] @ (8001b54 <TIM_OC3_SetConfig+0xf4>)
|
|
8001ae6: 4293 cmp r3, r2
|
|
8001ae8: d003 beq.n 8001af2 <TIM_OC3_SetConfig+0x92>
|
|
8001aea: 687b ldr r3, [r7, #4]
|
|
8001aec: 4a1a ldr r2, [pc, #104] @ (8001b58 <TIM_OC3_SetConfig+0xf8>)
|
|
8001aee: 4293 cmp r3, r2
|
|
8001af0: d113 bne.n 8001b1a <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8001af2: 693b ldr r3, [r7, #16]
|
|
8001af4: 4a19 ldr r2, [pc, #100] @ (8001b5c <TIM_OC3_SetConfig+0xfc>)
|
|
8001af6: 4013 ands r3, r2
|
|
8001af8: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8001afa: 693b ldr r3, [r7, #16]
|
|
8001afc: 4a18 ldr r2, [pc, #96] @ (8001b60 <TIM_OC3_SetConfig+0x100>)
|
|
8001afe: 4013 ands r3, r2
|
|
8001b00: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8001b02: 683b ldr r3, [r7, #0]
|
|
8001b04: 695b ldr r3, [r3, #20]
|
|
8001b06: 011b lsls r3, r3, #4
|
|
8001b08: 693a ldr r2, [r7, #16]
|
|
8001b0a: 4313 orrs r3, r2
|
|
8001b0c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8001b0e: 683b ldr r3, [r7, #0]
|
|
8001b10: 699b ldr r3, [r3, #24]
|
|
8001b12: 011b lsls r3, r3, #4
|
|
8001b14: 693a ldr r2, [r7, #16]
|
|
8001b16: 4313 orrs r3, r2
|
|
8001b18: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001b1a: 687b ldr r3, [r7, #4]
|
|
8001b1c: 693a ldr r2, [r7, #16]
|
|
8001b1e: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8001b20: 687b ldr r3, [r7, #4]
|
|
8001b22: 68fa ldr r2, [r7, #12]
|
|
8001b24: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8001b26: 683b ldr r3, [r7, #0]
|
|
8001b28: 685a ldr r2, [r3, #4]
|
|
8001b2a: 687b ldr r3, [r7, #4]
|
|
8001b2c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001b2e: 687b ldr r3, [r7, #4]
|
|
8001b30: 697a ldr r2, [r7, #20]
|
|
8001b32: 621a str r2, [r3, #32]
|
|
}
|
|
8001b34: 46c0 nop @ (mov r8, r8)
|
|
8001b36: 46bd mov sp, r7
|
|
8001b38: b006 add sp, #24
|
|
8001b3a: bd80 pop {r7, pc}
|
|
8001b3c: fffffeff .word 0xfffffeff
|
|
8001b40: fffeff8f .word 0xfffeff8f
|
|
8001b44: fffffdff .word 0xfffffdff
|
|
8001b48: 40012c00 .word 0x40012c00
|
|
8001b4c: fffff7ff .word 0xfffff7ff
|
|
8001b50: fffffbff .word 0xfffffbff
|
|
8001b54: 40014400 .word 0x40014400
|
|
8001b58: 40014800 .word 0x40014800
|
|
8001b5c: ffffefff .word 0xffffefff
|
|
8001b60: ffffdfff .word 0xffffdfff
|
|
|
|
08001b64 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001b64: b580 push {r7, lr}
|
|
8001b66: b086 sub sp, #24
|
|
8001b68: af00 add r7, sp, #0
|
|
8001b6a: 6078 str r0, [r7, #4]
|
|
8001b6c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001b6e: 687b ldr r3, [r7, #4]
|
|
8001b70: 6a1b ldr r3, [r3, #32]
|
|
8001b72: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8001b74: 687b ldr r3, [r7, #4]
|
|
8001b76: 6a1b ldr r3, [r3, #32]
|
|
8001b78: 4a24 ldr r2, [pc, #144] @ (8001c0c <TIM_OC4_SetConfig+0xa8>)
|
|
8001b7a: 401a ands r2, r3
|
|
8001b7c: 687b ldr r3, [r7, #4]
|
|
8001b7e: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001b80: 687b ldr r3, [r7, #4]
|
|
8001b82: 685b ldr r3, [r3, #4]
|
|
8001b84: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8001b86: 687b ldr r3, [r7, #4]
|
|
8001b88: 69db ldr r3, [r3, #28]
|
|
8001b8a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8001b8c: 68fb ldr r3, [r7, #12]
|
|
8001b8e: 4a20 ldr r2, [pc, #128] @ (8001c10 <TIM_OC4_SetConfig+0xac>)
|
|
8001b90: 4013 ands r3, r2
|
|
8001b92: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8001b94: 68fb ldr r3, [r7, #12]
|
|
8001b96: 4a1f ldr r2, [pc, #124] @ (8001c14 <TIM_OC4_SetConfig+0xb0>)
|
|
8001b98: 4013 ands r3, r2
|
|
8001b9a: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8001b9c: 683b ldr r3, [r7, #0]
|
|
8001b9e: 681b ldr r3, [r3, #0]
|
|
8001ba0: 021b lsls r3, r3, #8
|
|
8001ba2: 68fa ldr r2, [r7, #12]
|
|
8001ba4: 4313 orrs r3, r2
|
|
8001ba6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8001ba8: 693b ldr r3, [r7, #16]
|
|
8001baa: 4a1b ldr r2, [pc, #108] @ (8001c18 <TIM_OC4_SetConfig+0xb4>)
|
|
8001bac: 4013 ands r3, r2
|
|
8001bae: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8001bb0: 683b ldr r3, [r7, #0]
|
|
8001bb2: 689b ldr r3, [r3, #8]
|
|
8001bb4: 031b lsls r3, r3, #12
|
|
8001bb6: 693a ldr r2, [r7, #16]
|
|
8001bb8: 4313 orrs r3, r2
|
|
8001bba: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001bbc: 687b ldr r3, [r7, #4]
|
|
8001bbe: 4a17 ldr r2, [pc, #92] @ (8001c1c <TIM_OC4_SetConfig+0xb8>)
|
|
8001bc0: 4293 cmp r3, r2
|
|
8001bc2: d007 beq.n 8001bd4 <TIM_OC4_SetConfig+0x70>
|
|
8001bc4: 687b ldr r3, [r7, #4]
|
|
8001bc6: 4a16 ldr r2, [pc, #88] @ (8001c20 <TIM_OC4_SetConfig+0xbc>)
|
|
8001bc8: 4293 cmp r3, r2
|
|
8001bca: d003 beq.n 8001bd4 <TIM_OC4_SetConfig+0x70>
|
|
8001bcc: 687b ldr r3, [r7, #4]
|
|
8001bce: 4a15 ldr r2, [pc, #84] @ (8001c24 <TIM_OC4_SetConfig+0xc0>)
|
|
8001bd0: 4293 cmp r3, r2
|
|
8001bd2: d109 bne.n 8001be8 <TIM_OC4_SetConfig+0x84>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8001bd4: 697b ldr r3, [r7, #20]
|
|
8001bd6: 4a14 ldr r2, [pc, #80] @ (8001c28 <TIM_OC4_SetConfig+0xc4>)
|
|
8001bd8: 4013 ands r3, r2
|
|
8001bda: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8001bdc: 683b ldr r3, [r7, #0]
|
|
8001bde: 695b ldr r3, [r3, #20]
|
|
8001be0: 019b lsls r3, r3, #6
|
|
8001be2: 697a ldr r2, [r7, #20]
|
|
8001be4: 4313 orrs r3, r2
|
|
8001be6: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001be8: 687b ldr r3, [r7, #4]
|
|
8001bea: 697a ldr r2, [r7, #20]
|
|
8001bec: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8001bee: 687b ldr r3, [r7, #4]
|
|
8001bf0: 68fa ldr r2, [r7, #12]
|
|
8001bf2: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8001bf4: 683b ldr r3, [r7, #0]
|
|
8001bf6: 685a ldr r2, [r3, #4]
|
|
8001bf8: 687b ldr r3, [r7, #4]
|
|
8001bfa: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001bfc: 687b ldr r3, [r7, #4]
|
|
8001bfe: 693a ldr r2, [r7, #16]
|
|
8001c00: 621a str r2, [r3, #32]
|
|
}
|
|
8001c02: 46c0 nop @ (mov r8, r8)
|
|
8001c04: 46bd mov sp, r7
|
|
8001c06: b006 add sp, #24
|
|
8001c08: bd80 pop {r7, pc}
|
|
8001c0a: 46c0 nop @ (mov r8, r8)
|
|
8001c0c: ffffefff .word 0xffffefff
|
|
8001c10: feff8fff .word 0xfeff8fff
|
|
8001c14: fffffcff .word 0xfffffcff
|
|
8001c18: ffffdfff .word 0xffffdfff
|
|
8001c1c: 40012c00 .word 0x40012c00
|
|
8001c20: 40014400 .word 0x40014400
|
|
8001c24: 40014800 .word 0x40014800
|
|
8001c28: ffffbfff .word 0xffffbfff
|
|
|
|
08001c2c <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001c2c: b580 push {r7, lr}
|
|
8001c2e: b086 sub sp, #24
|
|
8001c30: af00 add r7, sp, #0
|
|
8001c32: 6078 str r0, [r7, #4]
|
|
8001c34: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001c36: 687b ldr r3, [r7, #4]
|
|
8001c38: 6a1b ldr r3, [r3, #32]
|
|
8001c3a: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
8001c3c: 687b ldr r3, [r7, #4]
|
|
8001c3e: 6a1b ldr r3, [r3, #32]
|
|
8001c40: 4a21 ldr r2, [pc, #132] @ (8001cc8 <TIM_OC5_SetConfig+0x9c>)
|
|
8001c42: 401a ands r2, r3
|
|
8001c44: 687b ldr r3, [r7, #4]
|
|
8001c46: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001c48: 687b ldr r3, [r7, #4]
|
|
8001c4a: 685b ldr r3, [r3, #4]
|
|
8001c4c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
8001c4e: 687b ldr r3, [r7, #4]
|
|
8001c50: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001c52: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
8001c54: 68fb ldr r3, [r7, #12]
|
|
8001c56: 4a1d ldr r2, [pc, #116] @ (8001ccc <TIM_OC5_SetConfig+0xa0>)
|
|
8001c58: 4013 ands r3, r2
|
|
8001c5a: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8001c5c: 683b ldr r3, [r7, #0]
|
|
8001c5e: 681b ldr r3, [r3, #0]
|
|
8001c60: 68fa ldr r2, [r7, #12]
|
|
8001c62: 4313 orrs r3, r2
|
|
8001c64: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
8001c66: 693b ldr r3, [r7, #16]
|
|
8001c68: 4a19 ldr r2, [pc, #100] @ (8001cd0 <TIM_OC5_SetConfig+0xa4>)
|
|
8001c6a: 4013 ands r3, r2
|
|
8001c6c: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
8001c6e: 683b ldr r3, [r7, #0]
|
|
8001c70: 689b ldr r3, [r3, #8]
|
|
8001c72: 041b lsls r3, r3, #16
|
|
8001c74: 693a ldr r2, [r7, #16]
|
|
8001c76: 4313 orrs r3, r2
|
|
8001c78: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001c7a: 687b ldr r3, [r7, #4]
|
|
8001c7c: 4a15 ldr r2, [pc, #84] @ (8001cd4 <TIM_OC5_SetConfig+0xa8>)
|
|
8001c7e: 4293 cmp r3, r2
|
|
8001c80: d007 beq.n 8001c92 <TIM_OC5_SetConfig+0x66>
|
|
8001c82: 687b ldr r3, [r7, #4]
|
|
8001c84: 4a14 ldr r2, [pc, #80] @ (8001cd8 <TIM_OC5_SetConfig+0xac>)
|
|
8001c86: 4293 cmp r3, r2
|
|
8001c88: d003 beq.n 8001c92 <TIM_OC5_SetConfig+0x66>
|
|
8001c8a: 687b ldr r3, [r7, #4]
|
|
8001c8c: 4a13 ldr r2, [pc, #76] @ (8001cdc <TIM_OC5_SetConfig+0xb0>)
|
|
8001c8e: 4293 cmp r3, r2
|
|
8001c90: d109 bne.n 8001ca6 <TIM_OC5_SetConfig+0x7a>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
8001c92: 697b ldr r3, [r7, #20]
|
|
8001c94: 4a0c ldr r2, [pc, #48] @ (8001cc8 <TIM_OC5_SetConfig+0x9c>)
|
|
8001c96: 4013 ands r3, r2
|
|
8001c98: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
8001c9a: 683b ldr r3, [r7, #0]
|
|
8001c9c: 695b ldr r3, [r3, #20]
|
|
8001c9e: 021b lsls r3, r3, #8
|
|
8001ca0: 697a ldr r2, [r7, #20]
|
|
8001ca2: 4313 orrs r3, r2
|
|
8001ca4: 617b str r3, [r7, #20]
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001ca6: 687b ldr r3, [r7, #4]
|
|
8001ca8: 697a ldr r2, [r7, #20]
|
|
8001caa: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8001cac: 687b ldr r3, [r7, #4]
|
|
8001cae: 68fa ldr r2, [r7, #12]
|
|
8001cb0: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
8001cb2: 683b ldr r3, [r7, #0]
|
|
8001cb4: 685a ldr r2, [r3, #4]
|
|
8001cb6: 687b ldr r3, [r7, #4]
|
|
8001cb8: 659a str r2, [r3, #88] @ 0x58
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001cba: 687b ldr r3, [r7, #4]
|
|
8001cbc: 693a ldr r2, [r7, #16]
|
|
8001cbe: 621a str r2, [r3, #32]
|
|
}
|
|
8001cc0: 46c0 nop @ (mov r8, r8)
|
|
8001cc2: 46bd mov sp, r7
|
|
8001cc4: b006 add sp, #24
|
|
8001cc6: bd80 pop {r7, pc}
|
|
8001cc8: fffeffff .word 0xfffeffff
|
|
8001ccc: fffeff8f .word 0xfffeff8f
|
|
8001cd0: fffdffff .word 0xfffdffff
|
|
8001cd4: 40012c00 .word 0x40012c00
|
|
8001cd8: 40014400 .word 0x40014400
|
|
8001cdc: 40014800 .word 0x40014800
|
|
|
|
08001ce0 <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001ce0: b580 push {r7, lr}
|
|
8001ce2: b086 sub sp, #24
|
|
8001ce4: af00 add r7, sp, #0
|
|
8001ce6: 6078 str r0, [r7, #4]
|
|
8001ce8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001cea: 687b ldr r3, [r7, #4]
|
|
8001cec: 6a1b ldr r3, [r3, #32]
|
|
8001cee: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
8001cf0: 687b ldr r3, [r7, #4]
|
|
8001cf2: 6a1b ldr r3, [r3, #32]
|
|
8001cf4: 4a22 ldr r2, [pc, #136] @ (8001d80 <TIM_OC6_SetConfig+0xa0>)
|
|
8001cf6: 401a ands r2, r3
|
|
8001cf8: 687b ldr r3, [r7, #4]
|
|
8001cfa: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001cfc: 687b ldr r3, [r7, #4]
|
|
8001cfe: 685b ldr r3, [r3, #4]
|
|
8001d00: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
8001d02: 687b ldr r3, [r7, #4]
|
|
8001d04: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001d06: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
8001d08: 68fb ldr r3, [r7, #12]
|
|
8001d0a: 4a1e ldr r2, [pc, #120] @ (8001d84 <TIM_OC6_SetConfig+0xa4>)
|
|
8001d0c: 4013 ands r3, r2
|
|
8001d0e: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8001d10: 683b ldr r3, [r7, #0]
|
|
8001d12: 681b ldr r3, [r3, #0]
|
|
8001d14: 021b lsls r3, r3, #8
|
|
8001d16: 68fa ldr r2, [r7, #12]
|
|
8001d18: 4313 orrs r3, r2
|
|
8001d1a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
8001d1c: 693b ldr r3, [r7, #16]
|
|
8001d1e: 4a1a ldr r2, [pc, #104] @ (8001d88 <TIM_OC6_SetConfig+0xa8>)
|
|
8001d20: 4013 ands r3, r2
|
|
8001d22: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
8001d24: 683b ldr r3, [r7, #0]
|
|
8001d26: 689b ldr r3, [r3, #8]
|
|
8001d28: 051b lsls r3, r3, #20
|
|
8001d2a: 693a ldr r2, [r7, #16]
|
|
8001d2c: 4313 orrs r3, r2
|
|
8001d2e: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001d30: 687b ldr r3, [r7, #4]
|
|
8001d32: 4a16 ldr r2, [pc, #88] @ (8001d8c <TIM_OC6_SetConfig+0xac>)
|
|
8001d34: 4293 cmp r3, r2
|
|
8001d36: d007 beq.n 8001d48 <TIM_OC6_SetConfig+0x68>
|
|
8001d38: 687b ldr r3, [r7, #4]
|
|
8001d3a: 4a15 ldr r2, [pc, #84] @ (8001d90 <TIM_OC6_SetConfig+0xb0>)
|
|
8001d3c: 4293 cmp r3, r2
|
|
8001d3e: d003 beq.n 8001d48 <TIM_OC6_SetConfig+0x68>
|
|
8001d40: 687b ldr r3, [r7, #4]
|
|
8001d42: 4a14 ldr r2, [pc, #80] @ (8001d94 <TIM_OC6_SetConfig+0xb4>)
|
|
8001d44: 4293 cmp r3, r2
|
|
8001d46: d109 bne.n 8001d5c <TIM_OC6_SetConfig+0x7c>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
8001d48: 697b ldr r3, [r7, #20]
|
|
8001d4a: 4a13 ldr r2, [pc, #76] @ (8001d98 <TIM_OC6_SetConfig+0xb8>)
|
|
8001d4c: 4013 ands r3, r2
|
|
8001d4e: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
8001d50: 683b ldr r3, [r7, #0]
|
|
8001d52: 695b ldr r3, [r3, #20]
|
|
8001d54: 029b lsls r3, r3, #10
|
|
8001d56: 697a ldr r2, [r7, #20]
|
|
8001d58: 4313 orrs r3, r2
|
|
8001d5a: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001d5c: 687b ldr r3, [r7, #4]
|
|
8001d5e: 697a ldr r2, [r7, #20]
|
|
8001d60: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8001d62: 687b ldr r3, [r7, #4]
|
|
8001d64: 68fa ldr r2, [r7, #12]
|
|
8001d66: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
8001d68: 683b ldr r3, [r7, #0]
|
|
8001d6a: 685a ldr r2, [r3, #4]
|
|
8001d6c: 687b ldr r3, [r7, #4]
|
|
8001d6e: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001d70: 687b ldr r3, [r7, #4]
|
|
8001d72: 693a ldr r2, [r7, #16]
|
|
8001d74: 621a str r2, [r3, #32]
|
|
}
|
|
8001d76: 46c0 nop @ (mov r8, r8)
|
|
8001d78: 46bd mov sp, r7
|
|
8001d7a: b006 add sp, #24
|
|
8001d7c: bd80 pop {r7, pc}
|
|
8001d7e: 46c0 nop @ (mov r8, r8)
|
|
8001d80: ffefffff .word 0xffefffff
|
|
8001d84: feff8fff .word 0xfeff8fff
|
|
8001d88: ffdfffff .word 0xffdfffff
|
|
8001d8c: 40012c00 .word 0x40012c00
|
|
8001d90: 40014400 .word 0x40014400
|
|
8001d94: 40014800 .word 0x40014800
|
|
8001d98: fffbffff .word 0xfffbffff
|
|
|
|
08001d9c <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8001d9c: b580 push {r7, lr}
|
|
8001d9e: b084 sub sp, #16
|
|
8001da0: af00 add r7, sp, #0
|
|
8001da2: 6078 str r0, [r7, #4]
|
|
8001da4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8001da6: 687b ldr r3, [r7, #4]
|
|
8001da8: 223c movs r2, #60 @ 0x3c
|
|
8001daa: 5c9b ldrb r3, [r3, r2]
|
|
8001dac: 2b01 cmp r3, #1
|
|
8001dae: d101 bne.n 8001db4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8001db0: 2302 movs r3, #2
|
|
8001db2: e04a b.n 8001e4a <HAL_TIMEx_MasterConfigSynchronization+0xae>
|
|
8001db4: 687b ldr r3, [r7, #4]
|
|
8001db6: 223c movs r2, #60 @ 0x3c
|
|
8001db8: 2101 movs r1, #1
|
|
8001dba: 5499 strb r1, [r3, r2]
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8001dbc: 687b ldr r3, [r7, #4]
|
|
8001dbe: 223d movs r2, #61 @ 0x3d
|
|
8001dc0: 2102 movs r1, #2
|
|
8001dc2: 5499 strb r1, [r3, r2]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8001dc4: 687b ldr r3, [r7, #4]
|
|
8001dc6: 681b ldr r3, [r3, #0]
|
|
8001dc8: 685b ldr r3, [r3, #4]
|
|
8001dca: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8001dcc: 687b ldr r3, [r7, #4]
|
|
8001dce: 681b ldr r3, [r3, #0]
|
|
8001dd0: 689b ldr r3, [r3, #8]
|
|
8001dd2: 60bb str r3, [r7, #8]
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
8001dd4: 687b ldr r3, [r7, #4]
|
|
8001dd6: 681b ldr r3, [r3, #0]
|
|
8001dd8: 4a1e ldr r2, [pc, #120] @ (8001e54 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
8001dda: 4293 cmp r3, r2
|
|
8001ddc: d108 bne.n 8001df0 <HAL_TIMEx_MasterConfigSynchronization+0x54>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
8001dde: 68fb ldr r3, [r7, #12]
|
|
8001de0: 4a1d ldr r2, [pc, #116] @ (8001e58 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
|
|
8001de2: 4013 ands r3, r2
|
|
8001de4: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
8001de6: 683b ldr r3, [r7, #0]
|
|
8001de8: 685b ldr r3, [r3, #4]
|
|
8001dea: 68fa ldr r2, [r7, #12]
|
|
8001dec: 4313 orrs r3, r2
|
|
8001dee: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8001df0: 68fb ldr r3, [r7, #12]
|
|
8001df2: 2270 movs r2, #112 @ 0x70
|
|
8001df4: 4393 bics r3, r2
|
|
8001df6: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8001df8: 683b ldr r3, [r7, #0]
|
|
8001dfa: 681b ldr r3, [r3, #0]
|
|
8001dfc: 68fa ldr r2, [r7, #12]
|
|
8001dfe: 4313 orrs r3, r2
|
|
8001e00: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8001e02: 687b ldr r3, [r7, #4]
|
|
8001e04: 681b ldr r3, [r3, #0]
|
|
8001e06: 68fa ldr r2, [r7, #12]
|
|
8001e08: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8001e0a: 687b ldr r3, [r7, #4]
|
|
8001e0c: 681b ldr r3, [r3, #0]
|
|
8001e0e: 4a11 ldr r2, [pc, #68] @ (8001e54 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
8001e10: 4293 cmp r3, r2
|
|
8001e12: d004 beq.n 8001e1e <HAL_TIMEx_MasterConfigSynchronization+0x82>
|
|
8001e14: 687b ldr r3, [r7, #4]
|
|
8001e16: 681b ldr r3, [r3, #0]
|
|
8001e18: 4a10 ldr r2, [pc, #64] @ (8001e5c <HAL_TIMEx_MasterConfigSynchronization+0xc0>)
|
|
8001e1a: 4293 cmp r3, r2
|
|
8001e1c: d10c bne.n 8001e38 <HAL_TIMEx_MasterConfigSynchronization+0x9c>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8001e1e: 68bb ldr r3, [r7, #8]
|
|
8001e20: 2280 movs r2, #128 @ 0x80
|
|
8001e22: 4393 bics r3, r2
|
|
8001e24: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8001e26: 683b ldr r3, [r7, #0]
|
|
8001e28: 689b ldr r3, [r3, #8]
|
|
8001e2a: 68ba ldr r2, [r7, #8]
|
|
8001e2c: 4313 orrs r3, r2
|
|
8001e2e: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8001e30: 687b ldr r3, [r7, #4]
|
|
8001e32: 681b ldr r3, [r3, #0]
|
|
8001e34: 68ba ldr r2, [r7, #8]
|
|
8001e36: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8001e38: 687b ldr r3, [r7, #4]
|
|
8001e3a: 223d movs r2, #61 @ 0x3d
|
|
8001e3c: 2101 movs r1, #1
|
|
8001e3e: 5499 strb r1, [r3, r2]
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8001e40: 687b ldr r3, [r7, #4]
|
|
8001e42: 223c movs r2, #60 @ 0x3c
|
|
8001e44: 2100 movs r1, #0
|
|
8001e46: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8001e48: 2300 movs r3, #0
|
|
}
|
|
8001e4a: 0018 movs r0, r3
|
|
8001e4c: 46bd mov sp, r7
|
|
8001e4e: b004 add sp, #16
|
|
8001e50: bd80 pop {r7, pc}
|
|
8001e52: 46c0 nop @ (mov r8, r8)
|
|
8001e54: 40012c00 .word 0x40012c00
|
|
8001e58: ff0fffff .word 0xff0fffff
|
|
8001e5c: 40000400 .word 0x40000400
|
|
|
|
08001e60 <memset>:
|
|
8001e60: 0003 movs r3, r0
|
|
8001e62: 1882 adds r2, r0, r2
|
|
8001e64: 4293 cmp r3, r2
|
|
8001e66: d100 bne.n 8001e6a <memset+0xa>
|
|
8001e68: 4770 bx lr
|
|
8001e6a: 7019 strb r1, [r3, #0]
|
|
8001e6c: 3301 adds r3, #1
|
|
8001e6e: e7f9 b.n 8001e64 <memset+0x4>
|
|
|
|
08001e70 <__libc_init_array>:
|
|
8001e70: b570 push {r4, r5, r6, lr}
|
|
8001e72: 2600 movs r6, #0
|
|
8001e74: 4c0c ldr r4, [pc, #48] @ (8001ea8 <__libc_init_array+0x38>)
|
|
8001e76: 4d0d ldr r5, [pc, #52] @ (8001eac <__libc_init_array+0x3c>)
|
|
8001e78: 1b64 subs r4, r4, r5
|
|
8001e7a: 10a4 asrs r4, r4, #2
|
|
8001e7c: 42a6 cmp r6, r4
|
|
8001e7e: d109 bne.n 8001e94 <__libc_init_array+0x24>
|
|
8001e80: 2600 movs r6, #0
|
|
8001e82: f000 f819 bl 8001eb8 <_init>
|
|
8001e86: 4c0a ldr r4, [pc, #40] @ (8001eb0 <__libc_init_array+0x40>)
|
|
8001e88: 4d0a ldr r5, [pc, #40] @ (8001eb4 <__libc_init_array+0x44>)
|
|
8001e8a: 1b64 subs r4, r4, r5
|
|
8001e8c: 10a4 asrs r4, r4, #2
|
|
8001e8e: 42a6 cmp r6, r4
|
|
8001e90: d105 bne.n 8001e9e <__libc_init_array+0x2e>
|
|
8001e92: bd70 pop {r4, r5, r6, pc}
|
|
8001e94: 00b3 lsls r3, r6, #2
|
|
8001e96: 58eb ldr r3, [r5, r3]
|
|
8001e98: 4798 blx r3
|
|
8001e9a: 3601 adds r6, #1
|
|
8001e9c: e7ee b.n 8001e7c <__libc_init_array+0xc>
|
|
8001e9e: 00b3 lsls r3, r6, #2
|
|
8001ea0: 58eb ldr r3, [r5, r3]
|
|
8001ea2: 4798 blx r3
|
|
8001ea4: 3601 adds r6, #1
|
|
8001ea6: e7f2 b.n 8001e8e <__libc_init_array+0x1e>
|
|
8001ea8: 08001f64 .word 0x08001f64
|
|
8001eac: 08001f64 .word 0x08001f64
|
|
8001eb0: 08001f68 .word 0x08001f68
|
|
8001eb4: 08001f64 .word 0x08001f64
|
|
|
|
08001eb8 <_init>:
|
|
8001eb8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8001eba: 46c0 nop @ (mov r8, r8)
|
|
8001ebc: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8001ebe: bc08 pop {r3}
|
|
8001ec0: 469e mov lr, r3
|
|
8001ec2: 4770 bx lr
|
|
|
|
08001ec4 <_fini>:
|
|
8001ec4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8001ec6: 46c0 nop @ (mov r8, r8)
|
|
8001ec8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8001eca: bc08 pop {r3}
|
|
8001ecc: 469e mov lr, r3
|
|
8001ece: 4770 bx lr
|