3250 lines
121 KiB
Plaintext
3250 lines
121 KiB
Plaintext
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blink.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000010c 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00001104 0800010c 0800010c 0000110c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000024 08001210 08001210 00002210 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08001234 08001234 0000300c 2**0
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CONTENTS, READONLY
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4 .ARM 00000000 08001234 08001234 0000300c 2**0
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CONTENTS, READONLY
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5 .preinit_array 00000000 08001234 08001234 0000300c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08001234 08001234 00002234 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08001238 08001238 00002238 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 0000000c 20000000 0800123c 00003000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000020 2000000c 08001248 0000300c 2**2
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ALLOC
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10 ._user_heap_stack 00000604 2000002c 08001248 0000302c 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 0000300c 2**0
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CONTENTS, READONLY
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12 .debug_info 0000291a 00000000 00000000 00003035 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00000e1e 00000000 00000000 0000594f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 000003d0 00000000 00000000 00006770 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000002b9 00000000 00000000 00006b40 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00015958 00000000 00000000 00006df9 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00004980 00000000 00000000 0001c751 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 0007bc95 00000000 00000000 000210d1 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 0009cd66 2**0
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CONTENTS, READONLY
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20 .debug_frame 00000d2c 00000000 00000000 0009cdac 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000051 00000000 00000000 0009dad8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800010c <__do_global_dtors_aux>:
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800010c: b510 push {r4, lr}
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800010e: 4c05 ldr r4, [pc, #20] @ (8000124 <__do_global_dtors_aux+0x18>)
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8000110: 7823 ldrb r3, [r4, #0]
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8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
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8000114: 4b04 ldr r3, [pc, #16] @ (8000128 <__do_global_dtors_aux+0x1c>)
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8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
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8000118: 4804 ldr r0, [pc, #16] @ (800012c <__do_global_dtors_aux+0x20>)
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800011a: f3af 8000 nop.w
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800011e: 2301 movs r3, #1
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8000120: 7023 strb r3, [r4, #0]
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8000122: bd10 pop {r4, pc}
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8000124: 2000000c .word 0x2000000c
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8000128: 00000000 .word 0x00000000
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800012c: 080011f8 .word 0x080011f8
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08000130 <frame_dummy>:
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8000130: b508 push {r3, lr}
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8000132: 4b03 ldr r3, [pc, #12] @ (8000140 <frame_dummy+0x10>)
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8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
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8000136: 4903 ldr r1, [pc, #12] @ (8000144 <frame_dummy+0x14>)
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8000138: 4803 ldr r0, [pc, #12] @ (8000148 <frame_dummy+0x18>)
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800013a: f3af 8000 nop.w
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800013e: bd08 pop {r3, pc}
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8000140: 00000000 .word 0x00000000
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8000144: 20000010 .word 0x20000010
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8000148: 080011f8 .word 0x080011f8
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0800014c <main>:
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void)
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{
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800014c: b580 push {r7, lr}
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800014e: af00 add r7, sp, #0
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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8000150: f000 f928 bl 80003a4 <HAL_Init>
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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8000154: f000 f810 bl 8000178 <SystemClock_Config>
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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8000158: f000 f854 bl 8000204 <MX_GPIO_Init>
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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{
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HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
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800015c: f44f 5100 mov.w r1, #8192 @ 0x2000
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8000160: 4804 ldr r0, [pc, #16] @ (8000174 <main+0x28>)
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8000162: f000 fc25 bl 80009b0 <HAL_GPIO_TogglePin>
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HAL_Delay(1000);
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8000166: f44f 707a mov.w r0, #1000 @ 0x3e8
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800016a: f000 f97d bl 8000468 <HAL_Delay>
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HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
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800016e: bf00 nop
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8000170: e7f4 b.n 800015c <main+0x10>
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8000172: bf00 nop
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8000174: 40011000 .word 0x40011000
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08000178 <SystemClock_Config>:
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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8000178: b580 push {r7, lr}
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800017a: b090 sub sp, #64 @ 0x40
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800017c: af00 add r7, sp, #0
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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800017e: f107 0318 add.w r3, r7, #24
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8000182: 2228 movs r2, #40 @ 0x28
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8000184: 2100 movs r1, #0
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8000186: 4618 mov r0, r3
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8000188: f001 f80a bl 80011a0 <memset>
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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800018c: 1d3b adds r3, r7, #4
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800018e: 2200 movs r2, #0
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8000190: 601a str r2, [r3, #0]
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8000192: 605a str r2, [r3, #4]
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8000194: 609a str r2, [r3, #8]
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8000196: 60da str r2, [r3, #12]
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8000198: 611a str r2, [r3, #16]
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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800019a: 2301 movs r3, #1
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800019c: 61bb str r3, [r7, #24]
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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800019e: f44f 3380 mov.w r3, #65536 @ 0x10000
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80001a2: 61fb str r3, [r7, #28]
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RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
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80001a4: 2300 movs r3, #0
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80001a6: 623b str r3, [r7, #32]
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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80001a8: 2301 movs r3, #1
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80001aa: 62bb str r3, [r7, #40] @ 0x28
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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80001ac: 2302 movs r3, #2
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80001ae: 637b str r3, [r7, #52] @ 0x34
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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80001b0: f44f 3380 mov.w r3, #65536 @ 0x10000
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80001b4: 63bb str r3, [r7, #56] @ 0x38
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
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80001b6: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000
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80001ba: 63fb str r3, [r7, #60] @ 0x3c
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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80001bc: f107 0318 add.w r3, r7, #24
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80001c0: 4618 mov r0, r3
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80001c2: f000 fc0f bl 80009e4 <HAL_RCC_OscConfig>
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80001c6: 4603 mov r3, r0
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80001c8: 2b00 cmp r3, #0
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80001ca: d001 beq.n 80001d0 <SystemClock_Config+0x58>
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{
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Error_Handler();
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80001cc: f000 f85a bl 8000284 <Error_Handler>
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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80001d0: 230f movs r3, #15
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80001d2: 607b str r3, [r7, #4]
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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80001d4: 2302 movs r3, #2
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80001d6: 60bb str r3, [r7, #8]
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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80001d8: 2300 movs r3, #0
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80001da: 60fb str r3, [r7, #12]
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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80001dc: f44f 6380 mov.w r3, #1024 @ 0x400
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80001e0: 613b str r3, [r7, #16]
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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80001e2: 2300 movs r3, #0
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80001e4: 617b str r3, [r7, #20]
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
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80001e6: 1d3b adds r3, r7, #4
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80001e8: 2102 movs r1, #2
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80001ea: 4618 mov r0, r3
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80001ec: f000 fe7c bl 8000ee8 <HAL_RCC_ClockConfig>
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80001f0: 4603 mov r3, r0
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80001f2: 2b00 cmp r3, #0
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80001f4: d001 beq.n 80001fa <SystemClock_Config+0x82>
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{
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Error_Handler();
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80001f6: f000 f845 bl 8000284 <Error_Handler>
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}
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}
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80001fa: bf00 nop
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80001fc: 3740 adds r7, #64 @ 0x40
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80001fe: 46bd mov sp, r7
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8000200: bd80 pop {r7, pc}
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...
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08000204 <MX_GPIO_Init>:
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* @brief GPIO Initialization Function
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* @param None
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* @retval None
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*/
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static void MX_GPIO_Init(void)
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{
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8000204: b580 push {r7, lr}
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8000206: b086 sub sp, #24
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8000208: af00 add r7, sp, #0
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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800020a: f107 0308 add.w r3, r7, #8
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800020e: 2200 movs r2, #0
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8000210: 601a str r2, [r3, #0]
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8000212: 605a str r2, [r3, #4]
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8000214: 609a str r2, [r3, #8]
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8000216: 60da str r2, [r3, #12]
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/* USER CODE BEGIN MX_GPIO_Init_1 */
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/* USER CODE END MX_GPIO_Init_1 */
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOC_CLK_ENABLE();
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8000218: 4b18 ldr r3, [pc, #96] @ (800027c <MX_GPIO_Init+0x78>)
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800021a: 699b ldr r3, [r3, #24]
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800021c: 4a17 ldr r2, [pc, #92] @ (800027c <MX_GPIO_Init+0x78>)
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800021e: f043 0310 orr.w r3, r3, #16
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8000222: 6193 str r3, [r2, #24]
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8000224: 4b15 ldr r3, [pc, #84] @ (800027c <MX_GPIO_Init+0x78>)
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8000226: 699b ldr r3, [r3, #24]
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8000228: f003 0310 and.w r3, r3, #16
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800022c: 607b str r3, [r7, #4]
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800022e: 687b ldr r3, [r7, #4]
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__HAL_RCC_GPIOD_CLK_ENABLE();
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8000230: 4b12 ldr r3, [pc, #72] @ (800027c <MX_GPIO_Init+0x78>)
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8000232: 699b ldr r3, [r3, #24]
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8000234: 4a11 ldr r2, [pc, #68] @ (800027c <MX_GPIO_Init+0x78>)
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8000236: f043 0320 orr.w r3, r3, #32
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800023a: 6193 str r3, [r2, #24]
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800023c: 4b0f ldr r3, [pc, #60] @ (800027c <MX_GPIO_Init+0x78>)
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800023e: 699b ldr r3, [r3, #24]
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8000240: f003 0320 and.w r3, r3, #32
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8000244: 603b str r3, [r7, #0]
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8000246: 683b ldr r3, [r7, #0]
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/*Configure GPIO pin Output Level */
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HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
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8000248: 2200 movs r2, #0
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800024a: f44f 5100 mov.w r1, #8192 @ 0x2000
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800024e: 480c ldr r0, [pc, #48] @ (8000280 <MX_GPIO_Init+0x7c>)
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8000250: f000 fb96 bl 8000980 <HAL_GPIO_WritePin>
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/*Configure GPIO pin : PC13 */
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GPIO_InitStruct.Pin = GPIO_PIN_13;
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8000254: f44f 5300 mov.w r3, #8192 @ 0x2000
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8000258: 60bb str r3, [r7, #8]
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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800025a: 2301 movs r3, #1
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800025c: 60fb str r3, [r7, #12]
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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800025e: 2300 movs r3, #0
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8000260: 613b str r3, [r7, #16]
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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8000262: 2302 movs r3, #2
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8000264: 617b str r3, [r7, #20]
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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8000266: f107 0308 add.w r3, r7, #8
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800026a: 4619 mov r1, r3
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800026c: 4804 ldr r0, [pc, #16] @ (8000280 <MX_GPIO_Init+0x7c>)
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800026e: f000 fa03 bl 8000678 <HAL_GPIO_Init>
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/* USER CODE BEGIN MX_GPIO_Init_2 */
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/* USER CODE END MX_GPIO_Init_2 */
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}
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8000272: bf00 nop
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8000274: 3718 adds r7, #24
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8000276: 46bd mov sp, r7
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8000278: bd80 pop {r7, pc}
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800027a: bf00 nop
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800027c: 40021000 .word 0x40021000
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8000280: 40011000 .word 0x40011000
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08000284 <Error_Handler>:
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/**
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* @brief This function is executed in case of error occurrence.
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* @retval None
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*/
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void Error_Handler(void)
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{
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8000284: b480 push {r7}
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8000286: af00 add r7, sp, #0
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\details Disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__STATIC_FORCEINLINE void __disable_irq(void)
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{
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__ASM volatile ("cpsid i" : : : "memory");
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8000288: b672 cpsid i
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}
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800028a: bf00 nop
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/* USER CODE BEGIN Error_Handler_Debug */
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/* User can add his own implementation to report the HAL error return state */
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__disable_irq();
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while (1)
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800028c: bf00 nop
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800028e: e7fd b.n 800028c <Error_Handler+0x8>
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08000290 <HAL_MspInit>:
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/* USER CODE END 0 */
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/**
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* Initializes the Global MSP.
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*/
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void HAL_MspInit(void)
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{
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8000290: b480 push {r7}
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8000292: b085 sub sp, #20
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8000294: af00 add r7, sp, #0
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/* USER CODE BEGIN MspInit 0 */
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/* USER CODE END MspInit 0 */
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__HAL_RCC_AFIO_CLK_ENABLE();
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8000296: 4b15 ldr r3, [pc, #84] @ (80002ec <HAL_MspInit+0x5c>)
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8000298: 699b ldr r3, [r3, #24]
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800029a: 4a14 ldr r2, [pc, #80] @ (80002ec <HAL_MspInit+0x5c>)
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800029c: f043 0301 orr.w r3, r3, #1
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80002a0: 6193 str r3, [r2, #24]
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80002a2: 4b12 ldr r3, [pc, #72] @ (80002ec <HAL_MspInit+0x5c>)
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80002a4: 699b ldr r3, [r3, #24]
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80002a6: f003 0301 and.w r3, r3, #1
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80002aa: 60bb str r3, [r7, #8]
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80002ac: 68bb ldr r3, [r7, #8]
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__HAL_RCC_PWR_CLK_ENABLE();
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80002ae: 4b0f ldr r3, [pc, #60] @ (80002ec <HAL_MspInit+0x5c>)
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80002b0: 69db ldr r3, [r3, #28]
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80002b2: 4a0e ldr r2, [pc, #56] @ (80002ec <HAL_MspInit+0x5c>)
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80002b4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
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80002b8: 61d3 str r3, [r2, #28]
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80002ba: 4b0c ldr r3, [pc, #48] @ (80002ec <HAL_MspInit+0x5c>)
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80002bc: 69db ldr r3, [r3, #28]
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80002be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
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80002c2: 607b str r3, [r7, #4]
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80002c4: 687b ldr r3, [r7, #4]
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/* System interrupt init*/
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/** DISABLE: JTAG-DP Disabled and SW-DP Disabled
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*/
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__HAL_AFIO_REMAP_SWJ_DISABLE();
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80002c6: 4b0a ldr r3, [pc, #40] @ (80002f0 <HAL_MspInit+0x60>)
|
|
80002c8: 685b ldr r3, [r3, #4]
|
|
80002ca: 60fb str r3, [r7, #12]
|
|
80002cc: 68fb ldr r3, [r7, #12]
|
|
80002ce: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000
|
|
80002d2: 60fb str r3, [r7, #12]
|
|
80002d4: 68fb ldr r3, [r7, #12]
|
|
80002d6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
80002da: 60fb str r3, [r7, #12]
|
|
80002dc: 4a04 ldr r2, [pc, #16] @ (80002f0 <HAL_MspInit+0x60>)
|
|
80002de: 68fb ldr r3, [r7, #12]
|
|
80002e0: 6053 str r3, [r2, #4]
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80002e2: bf00 nop
|
|
80002e4: 3714 adds r7, #20
|
|
80002e6: 46bd mov sp, r7
|
|
80002e8: bc80 pop {r7}
|
|
80002ea: 4770 bx lr
|
|
80002ec: 40021000 .word 0x40021000
|
|
80002f0: 40010000 .word 0x40010000
|
|
|
|
080002f4 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80002f4: b480 push {r7}
|
|
80002f6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80002f8: bf00 nop
|
|
80002fa: e7fd b.n 80002f8 <NMI_Handler+0x4>
|
|
|
|
080002fc <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80002fc: b480 push {r7}
|
|
80002fe: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000300: bf00 nop
|
|
8000302: e7fd b.n 8000300 <HardFault_Handler+0x4>
|
|
|
|
08000304 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000304: b480 push {r7}
|
|
8000306: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000308: bf00 nop
|
|
800030a: e7fd b.n 8000308 <MemManage_Handler+0x4>
|
|
|
|
0800030c <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
800030c: b480 push {r7}
|
|
800030e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000310: bf00 nop
|
|
8000312: e7fd b.n 8000310 <BusFault_Handler+0x4>
|
|
|
|
08000314 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000314: b480 push {r7}
|
|
8000316: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000318: bf00 nop
|
|
800031a: e7fd b.n 8000318 <UsageFault_Handler+0x4>
|
|
|
|
0800031c <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
800031c: b480 push {r7}
|
|
800031e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000320: bf00 nop
|
|
8000322: 46bd mov sp, r7
|
|
8000324: bc80 pop {r7}
|
|
8000326: 4770 bx lr
|
|
|
|
08000328 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000328: b480 push {r7}
|
|
800032a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800032c: bf00 nop
|
|
800032e: 46bd mov sp, r7
|
|
8000330: bc80 pop {r7}
|
|
8000332: 4770 bx lr
|
|
|
|
08000334 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000334: b480 push {r7}
|
|
8000336: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000338: bf00 nop
|
|
800033a: 46bd mov sp, r7
|
|
800033c: bc80 pop {r7}
|
|
800033e: 4770 bx lr
|
|
|
|
08000340 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8000340: b580 push {r7, lr}
|
|
8000342: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8000344: f000 f874 bl 8000430 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8000348: bf00 nop
|
|
800034a: bd80 pop {r7, pc}
|
|
|
|
0800034c <SystemInit>:
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit (void)
|
|
{
|
|
800034c: b480 push {r7}
|
|
800034e: af00 add r7, sp, #0
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8000350: bf00 nop
|
|
8000352: 46bd mov sp, r7
|
|
8000354: bc80 pop {r7}
|
|
8000356: 4770 bx lr
|
|
|
|
08000358 <Reset_Handler>:
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8000358: f7ff fff8 bl 800034c <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
800035c: 480b ldr r0, [pc, #44] @ (800038c <LoopFillZerobss+0xe>)
|
|
ldr r1, =_edata
|
|
800035e: 490c ldr r1, [pc, #48] @ (8000390 <LoopFillZerobss+0x12>)
|
|
ldr r2, =_sidata
|
|
8000360: 4a0c ldr r2, [pc, #48] @ (8000394 <LoopFillZerobss+0x16>)
|
|
movs r3, #0
|
|
8000362: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8000364: e002 b.n 800036c <LoopCopyDataInit>
|
|
|
|
08000366 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8000366: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8000368: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
800036a: 3304 adds r3, #4
|
|
|
|
0800036c <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
800036c: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
800036e: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8000370: d3f9 bcc.n 8000366 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8000372: 4a09 ldr r2, [pc, #36] @ (8000398 <LoopFillZerobss+0x1a>)
|
|
ldr r4, =_ebss
|
|
8000374: 4c09 ldr r4, [pc, #36] @ (800039c <LoopFillZerobss+0x1e>)
|
|
movs r3, #0
|
|
8000376: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8000378: e001 b.n 800037e <LoopFillZerobss>
|
|
|
|
0800037a <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
800037a: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
800037c: 3204 adds r2, #4
|
|
|
|
0800037e <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
800037e: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8000380: d3fb bcc.n 800037a <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8000382: f000 ff15 bl 80011b0 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8000386: f7ff fee1 bl 800014c <main>
|
|
bx lr
|
|
800038a: 4770 bx lr
|
|
ldr r0, =_sdata
|
|
800038c: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8000390: 2000000c .word 0x2000000c
|
|
ldr r2, =_sidata
|
|
8000394: 0800123c .word 0x0800123c
|
|
ldr r2, =_sbss
|
|
8000398: 2000000c .word 0x2000000c
|
|
ldr r4, =_ebss
|
|
800039c: 2000002c .word 0x2000002c
|
|
|
|
080003a0 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80003a0: e7fe b.n 80003a0 <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
080003a4 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80003a4: b580 push {r7, lr}
|
|
80003a6: af00 add r7, sp, #0
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
80003a8: 4b08 ldr r3, [pc, #32] @ (80003cc <HAL_Init+0x28>)
|
|
80003aa: 681b ldr r3, [r3, #0]
|
|
80003ac: 4a07 ldr r2, [pc, #28] @ (80003cc <HAL_Init+0x28>)
|
|
80003ae: f043 0310 orr.w r3, r3, #16
|
|
80003b2: 6013 str r3, [r2, #0]
|
|
#endif
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80003b4: 2003 movs r0, #3
|
|
80003b6: f000 f92b bl 8000610 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
80003ba: 200f movs r0, #15
|
|
80003bc: f000 f808 bl 80003d0 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80003c0: f7ff ff66 bl 8000290 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80003c4: 2300 movs r3, #0
|
|
}
|
|
80003c6: 4618 mov r0, r3
|
|
80003c8: bd80 pop {r7, pc}
|
|
80003ca: bf00 nop
|
|
80003cc: 40022000 .word 0x40022000
|
|
|
|
080003d0 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80003d0: b580 push {r7, lr}
|
|
80003d2: b082 sub sp, #8
|
|
80003d4: af00 add r7, sp, #0
|
|
80003d6: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
80003d8: 4b12 ldr r3, [pc, #72] @ (8000424 <HAL_InitTick+0x54>)
|
|
80003da: 681a ldr r2, [r3, #0]
|
|
80003dc: 4b12 ldr r3, [pc, #72] @ (8000428 <HAL_InitTick+0x58>)
|
|
80003de: 781b ldrb r3, [r3, #0]
|
|
80003e0: 4619 mov r1, r3
|
|
80003e2: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80003e6: fbb3 f3f1 udiv r3, r3, r1
|
|
80003ea: fbb2 f3f3 udiv r3, r2, r3
|
|
80003ee: 4618 mov r0, r3
|
|
80003f0: f000 f935 bl 800065e <HAL_SYSTICK_Config>
|
|
80003f4: 4603 mov r3, r0
|
|
80003f6: 2b00 cmp r3, #0
|
|
80003f8: d001 beq.n 80003fe <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
80003fa: 2301 movs r3, #1
|
|
80003fc: e00e b.n 800041c <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80003fe: 687b ldr r3, [r7, #4]
|
|
8000400: 2b0f cmp r3, #15
|
|
8000402: d80a bhi.n 800041a <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000404: 2200 movs r2, #0
|
|
8000406: 6879 ldr r1, [r7, #4]
|
|
8000408: f04f 30ff mov.w r0, #4294967295
|
|
800040c: f000 f90b bl 8000626 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8000410: 4a06 ldr r2, [pc, #24] @ (800042c <HAL_InitTick+0x5c>)
|
|
8000412: 687b ldr r3, [r7, #4]
|
|
8000414: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8000416: 2300 movs r3, #0
|
|
8000418: e000 b.n 800041c <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
800041a: 2301 movs r3, #1
|
|
}
|
|
800041c: 4618 mov r0, r3
|
|
800041e: 3708 adds r7, #8
|
|
8000420: 46bd mov sp, r7
|
|
8000422: bd80 pop {r7, pc}
|
|
8000424: 20000000 .word 0x20000000
|
|
8000428: 20000008 .word 0x20000008
|
|
800042c: 20000004 .word 0x20000004
|
|
|
|
08000430 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8000430: b480 push {r7}
|
|
8000432: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8000434: 4b05 ldr r3, [pc, #20] @ (800044c <HAL_IncTick+0x1c>)
|
|
8000436: 781b ldrb r3, [r3, #0]
|
|
8000438: 461a mov r2, r3
|
|
800043a: 4b05 ldr r3, [pc, #20] @ (8000450 <HAL_IncTick+0x20>)
|
|
800043c: 681b ldr r3, [r3, #0]
|
|
800043e: 4413 add r3, r2
|
|
8000440: 4a03 ldr r2, [pc, #12] @ (8000450 <HAL_IncTick+0x20>)
|
|
8000442: 6013 str r3, [r2, #0]
|
|
}
|
|
8000444: bf00 nop
|
|
8000446: 46bd mov sp, r7
|
|
8000448: bc80 pop {r7}
|
|
800044a: 4770 bx lr
|
|
800044c: 20000008 .word 0x20000008
|
|
8000450: 20000028 .word 0x20000028
|
|
|
|
08000454 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8000454: b480 push {r7}
|
|
8000456: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8000458: 4b02 ldr r3, [pc, #8] @ (8000464 <HAL_GetTick+0x10>)
|
|
800045a: 681b ldr r3, [r3, #0]
|
|
}
|
|
800045c: 4618 mov r0, r3
|
|
800045e: 46bd mov sp, r7
|
|
8000460: bc80 pop {r7}
|
|
8000462: 4770 bx lr
|
|
8000464: 20000028 .word 0x20000028
|
|
|
|
08000468 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8000468: b580 push {r7, lr}
|
|
800046a: b084 sub sp, #16
|
|
800046c: af00 add r7, sp, #0
|
|
800046e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8000470: f7ff fff0 bl 8000454 <HAL_GetTick>
|
|
8000474: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8000476: 687b ldr r3, [r7, #4]
|
|
8000478: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
800047a: 68fb ldr r3, [r7, #12]
|
|
800047c: f1b3 3fff cmp.w r3, #4294967295
|
|
8000480: d005 beq.n 800048e <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8000482: 4b0a ldr r3, [pc, #40] @ (80004ac <HAL_Delay+0x44>)
|
|
8000484: 781b ldrb r3, [r3, #0]
|
|
8000486: 461a mov r2, r3
|
|
8000488: 68fb ldr r3, [r7, #12]
|
|
800048a: 4413 add r3, r2
|
|
800048c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
800048e: bf00 nop
|
|
8000490: f7ff ffe0 bl 8000454 <HAL_GetTick>
|
|
8000494: 4602 mov r2, r0
|
|
8000496: 68bb ldr r3, [r7, #8]
|
|
8000498: 1ad3 subs r3, r2, r3
|
|
800049a: 68fa ldr r2, [r7, #12]
|
|
800049c: 429a cmp r2, r3
|
|
800049e: d8f7 bhi.n 8000490 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
80004a0: bf00 nop
|
|
80004a2: bf00 nop
|
|
80004a4: 3710 adds r7, #16
|
|
80004a6: 46bd mov sp, r7
|
|
80004a8: bd80 pop {r7, pc}
|
|
80004aa: bf00 nop
|
|
80004ac: 20000008 .word 0x20000008
|
|
|
|
080004b0 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80004b0: b480 push {r7}
|
|
80004b2: b085 sub sp, #20
|
|
80004b4: af00 add r7, sp, #0
|
|
80004b6: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80004b8: 687b ldr r3, [r7, #4]
|
|
80004ba: f003 0307 and.w r3, r3, #7
|
|
80004be: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80004c0: 4b0c ldr r3, [pc, #48] @ (80004f4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80004c2: 68db ldr r3, [r3, #12]
|
|
80004c4: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80004c6: 68ba ldr r2, [r7, #8]
|
|
80004c8: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80004cc: 4013 ands r3, r2
|
|
80004ce: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80004d0: 68fb ldr r3, [r7, #12]
|
|
80004d2: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80004d4: 68bb ldr r3, [r7, #8]
|
|
80004d6: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80004d8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80004dc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80004e0: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80004e2: 4a04 ldr r2, [pc, #16] @ (80004f4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80004e4: 68bb ldr r3, [r7, #8]
|
|
80004e6: 60d3 str r3, [r2, #12]
|
|
}
|
|
80004e8: bf00 nop
|
|
80004ea: 3714 adds r7, #20
|
|
80004ec: 46bd mov sp, r7
|
|
80004ee: bc80 pop {r7}
|
|
80004f0: 4770 bx lr
|
|
80004f2: bf00 nop
|
|
80004f4: e000ed00 .word 0xe000ed00
|
|
|
|
080004f8 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80004f8: b480 push {r7}
|
|
80004fa: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80004fc: 4b04 ldr r3, [pc, #16] @ (8000510 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80004fe: 68db ldr r3, [r3, #12]
|
|
8000500: 0a1b lsrs r3, r3, #8
|
|
8000502: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000506: 4618 mov r0, r3
|
|
8000508: 46bd mov sp, r7
|
|
800050a: bc80 pop {r7}
|
|
800050c: 4770 bx lr
|
|
800050e: bf00 nop
|
|
8000510: e000ed00 .word 0xe000ed00
|
|
|
|
08000514 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8000514: b480 push {r7}
|
|
8000516: b083 sub sp, #12
|
|
8000518: af00 add r7, sp, #0
|
|
800051a: 4603 mov r3, r0
|
|
800051c: 6039 str r1, [r7, #0]
|
|
800051e: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8000520: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000524: 2b00 cmp r3, #0
|
|
8000526: db0a blt.n 800053e <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000528: 683b ldr r3, [r7, #0]
|
|
800052a: b2da uxtb r2, r3
|
|
800052c: 490c ldr r1, [pc, #48] @ (8000560 <__NVIC_SetPriority+0x4c>)
|
|
800052e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000532: 0112 lsls r2, r2, #4
|
|
8000534: b2d2 uxtb r2, r2
|
|
8000536: 440b add r3, r1
|
|
8000538: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
800053c: e00a b.n 8000554 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800053e: 683b ldr r3, [r7, #0]
|
|
8000540: b2da uxtb r2, r3
|
|
8000542: 4908 ldr r1, [pc, #32] @ (8000564 <__NVIC_SetPriority+0x50>)
|
|
8000544: 79fb ldrb r3, [r7, #7]
|
|
8000546: f003 030f and.w r3, r3, #15
|
|
800054a: 3b04 subs r3, #4
|
|
800054c: 0112 lsls r2, r2, #4
|
|
800054e: b2d2 uxtb r2, r2
|
|
8000550: 440b add r3, r1
|
|
8000552: 761a strb r2, [r3, #24]
|
|
}
|
|
8000554: bf00 nop
|
|
8000556: 370c adds r7, #12
|
|
8000558: 46bd mov sp, r7
|
|
800055a: bc80 pop {r7}
|
|
800055c: 4770 bx lr
|
|
800055e: bf00 nop
|
|
8000560: e000e100 .word 0xe000e100
|
|
8000564: e000ed00 .word 0xe000ed00
|
|
|
|
08000568 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000568: b480 push {r7}
|
|
800056a: b089 sub sp, #36 @ 0x24
|
|
800056c: af00 add r7, sp, #0
|
|
800056e: 60f8 str r0, [r7, #12]
|
|
8000570: 60b9 str r1, [r7, #8]
|
|
8000572: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000574: 68fb ldr r3, [r7, #12]
|
|
8000576: f003 0307 and.w r3, r3, #7
|
|
800057a: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
800057c: 69fb ldr r3, [r7, #28]
|
|
800057e: f1c3 0307 rsb r3, r3, #7
|
|
8000582: 2b04 cmp r3, #4
|
|
8000584: bf28 it cs
|
|
8000586: 2304 movcs r3, #4
|
|
8000588: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
800058a: 69fb ldr r3, [r7, #28]
|
|
800058c: 3304 adds r3, #4
|
|
800058e: 2b06 cmp r3, #6
|
|
8000590: d902 bls.n 8000598 <NVIC_EncodePriority+0x30>
|
|
8000592: 69fb ldr r3, [r7, #28]
|
|
8000594: 3b03 subs r3, #3
|
|
8000596: e000 b.n 800059a <NVIC_EncodePriority+0x32>
|
|
8000598: 2300 movs r3, #0
|
|
800059a: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
800059c: f04f 32ff mov.w r2, #4294967295
|
|
80005a0: 69bb ldr r3, [r7, #24]
|
|
80005a2: fa02 f303 lsl.w r3, r2, r3
|
|
80005a6: 43da mvns r2, r3
|
|
80005a8: 68bb ldr r3, [r7, #8]
|
|
80005aa: 401a ands r2, r3
|
|
80005ac: 697b ldr r3, [r7, #20]
|
|
80005ae: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80005b0: f04f 31ff mov.w r1, #4294967295
|
|
80005b4: 697b ldr r3, [r7, #20]
|
|
80005b6: fa01 f303 lsl.w r3, r1, r3
|
|
80005ba: 43d9 mvns r1, r3
|
|
80005bc: 687b ldr r3, [r7, #4]
|
|
80005be: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80005c0: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80005c2: 4618 mov r0, r3
|
|
80005c4: 3724 adds r7, #36 @ 0x24
|
|
80005c6: 46bd mov sp, r7
|
|
80005c8: bc80 pop {r7}
|
|
80005ca: 4770 bx lr
|
|
|
|
080005cc <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80005cc: b580 push {r7, lr}
|
|
80005ce: b082 sub sp, #8
|
|
80005d0: af00 add r7, sp, #0
|
|
80005d2: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80005d4: 687b ldr r3, [r7, #4]
|
|
80005d6: 3b01 subs r3, #1
|
|
80005d8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80005dc: d301 bcc.n 80005e2 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80005de: 2301 movs r3, #1
|
|
80005e0: e00f b.n 8000602 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
80005e2: 4a0a ldr r2, [pc, #40] @ (800060c <SysTick_Config+0x40>)
|
|
80005e4: 687b ldr r3, [r7, #4]
|
|
80005e6: 3b01 subs r3, #1
|
|
80005e8: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
80005ea: 210f movs r1, #15
|
|
80005ec: f04f 30ff mov.w r0, #4294967295
|
|
80005f0: f7ff ff90 bl 8000514 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
80005f4: 4b05 ldr r3, [pc, #20] @ (800060c <SysTick_Config+0x40>)
|
|
80005f6: 2200 movs r2, #0
|
|
80005f8: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
80005fa: 4b04 ldr r3, [pc, #16] @ (800060c <SysTick_Config+0x40>)
|
|
80005fc: 2207 movs r2, #7
|
|
80005fe: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8000600: 2300 movs r3, #0
|
|
}
|
|
8000602: 4618 mov r0, r3
|
|
8000604: 3708 adds r7, #8
|
|
8000606: 46bd mov sp, r7
|
|
8000608: bd80 pop {r7, pc}
|
|
800060a: bf00 nop
|
|
800060c: e000e010 .word 0xe000e010
|
|
|
|
08000610 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8000610: b580 push {r7, lr}
|
|
8000612: b082 sub sp, #8
|
|
8000614: af00 add r7, sp, #0
|
|
8000616: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8000618: 6878 ldr r0, [r7, #4]
|
|
800061a: f7ff ff49 bl 80004b0 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800061e: bf00 nop
|
|
8000620: 3708 adds r7, #8
|
|
8000622: 46bd mov sp, r7
|
|
8000624: bd80 pop {r7, pc}
|
|
|
|
08000626 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000626: b580 push {r7, lr}
|
|
8000628: b086 sub sp, #24
|
|
800062a: af00 add r7, sp, #0
|
|
800062c: 4603 mov r3, r0
|
|
800062e: 60b9 str r1, [r7, #8]
|
|
8000630: 607a str r2, [r7, #4]
|
|
8000632: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8000634: 2300 movs r3, #0
|
|
8000636: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8000638: f7ff ff5e bl 80004f8 <__NVIC_GetPriorityGrouping>
|
|
800063c: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800063e: 687a ldr r2, [r7, #4]
|
|
8000640: 68b9 ldr r1, [r7, #8]
|
|
8000642: 6978 ldr r0, [r7, #20]
|
|
8000644: f7ff ff90 bl 8000568 <NVIC_EncodePriority>
|
|
8000648: 4602 mov r2, r0
|
|
800064a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800064e: 4611 mov r1, r2
|
|
8000650: 4618 mov r0, r3
|
|
8000652: f7ff ff5f bl 8000514 <__NVIC_SetPriority>
|
|
}
|
|
8000656: bf00 nop
|
|
8000658: 3718 adds r7, #24
|
|
800065a: 46bd mov sp, r7
|
|
800065c: bd80 pop {r7, pc}
|
|
|
|
0800065e <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
800065e: b580 push {r7, lr}
|
|
8000660: b082 sub sp, #8
|
|
8000662: af00 add r7, sp, #0
|
|
8000664: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000666: 6878 ldr r0, [r7, #4]
|
|
8000668: f7ff ffb0 bl 80005cc <SysTick_Config>
|
|
800066c: 4603 mov r3, r0
|
|
}
|
|
800066e: 4618 mov r0, r3
|
|
8000670: 3708 adds r7, #8
|
|
8000672: 46bd mov sp, r7
|
|
8000674: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000678 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8000678: b480 push {r7}
|
|
800067a: b08b sub sp, #44 @ 0x2c
|
|
800067c: af00 add r7, sp, #0
|
|
800067e: 6078 str r0, [r7, #4]
|
|
8000680: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8000682: 2300 movs r3, #0
|
|
8000684: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t ioposition;
|
|
uint32_t iocurrent;
|
|
uint32_t temp;
|
|
uint32_t config = 0x00u;
|
|
8000686: 2300 movs r3, #0
|
|
8000688: 623b str r3, [r7, #32]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800068a: e169 b.n 8000960 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = (0x01uL << position);
|
|
800068c: 2201 movs r2, #1
|
|
800068e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000690: fa02 f303 lsl.w r3, r2, r3
|
|
8000694: 61fb str r3, [r7, #28]
|
|
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8000696: 683b ldr r3, [r7, #0]
|
|
8000698: 681b ldr r3, [r3, #0]
|
|
800069a: 69fa ldr r2, [r7, #28]
|
|
800069c: 4013 ands r3, r2
|
|
800069e: 61bb str r3, [r7, #24]
|
|
|
|
if (iocurrent == ioposition)
|
|
80006a0: 69ba ldr r2, [r7, #24]
|
|
80006a2: 69fb ldr r3, [r7, #28]
|
|
80006a4: 429a cmp r2, r3
|
|
80006a6: f040 8158 bne.w 800095a <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
switch (GPIO_Init->Mode)
|
|
80006aa: 683b ldr r3, [r7, #0]
|
|
80006ac: 685b ldr r3, [r3, #4]
|
|
80006ae: 4a9a ldr r2, [pc, #616] @ (8000918 <HAL_GPIO_Init+0x2a0>)
|
|
80006b0: 4293 cmp r3, r2
|
|
80006b2: d05e beq.n 8000772 <HAL_GPIO_Init+0xfa>
|
|
80006b4: 4a98 ldr r2, [pc, #608] @ (8000918 <HAL_GPIO_Init+0x2a0>)
|
|
80006b6: 4293 cmp r3, r2
|
|
80006b8: d875 bhi.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
80006ba: 4a98 ldr r2, [pc, #608] @ (800091c <HAL_GPIO_Init+0x2a4>)
|
|
80006bc: 4293 cmp r3, r2
|
|
80006be: d058 beq.n 8000772 <HAL_GPIO_Init+0xfa>
|
|
80006c0: 4a96 ldr r2, [pc, #600] @ (800091c <HAL_GPIO_Init+0x2a4>)
|
|
80006c2: 4293 cmp r3, r2
|
|
80006c4: d86f bhi.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
80006c6: 4a96 ldr r2, [pc, #600] @ (8000920 <HAL_GPIO_Init+0x2a8>)
|
|
80006c8: 4293 cmp r3, r2
|
|
80006ca: d052 beq.n 8000772 <HAL_GPIO_Init+0xfa>
|
|
80006cc: 4a94 ldr r2, [pc, #592] @ (8000920 <HAL_GPIO_Init+0x2a8>)
|
|
80006ce: 4293 cmp r3, r2
|
|
80006d0: d869 bhi.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
80006d2: 4a94 ldr r2, [pc, #592] @ (8000924 <HAL_GPIO_Init+0x2ac>)
|
|
80006d4: 4293 cmp r3, r2
|
|
80006d6: d04c beq.n 8000772 <HAL_GPIO_Init+0xfa>
|
|
80006d8: 4a92 ldr r2, [pc, #584] @ (8000924 <HAL_GPIO_Init+0x2ac>)
|
|
80006da: 4293 cmp r3, r2
|
|
80006dc: d863 bhi.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
80006de: 4a92 ldr r2, [pc, #584] @ (8000928 <HAL_GPIO_Init+0x2b0>)
|
|
80006e0: 4293 cmp r3, r2
|
|
80006e2: d046 beq.n 8000772 <HAL_GPIO_Init+0xfa>
|
|
80006e4: 4a90 ldr r2, [pc, #576] @ (8000928 <HAL_GPIO_Init+0x2b0>)
|
|
80006e6: 4293 cmp r3, r2
|
|
80006e8: d85d bhi.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
80006ea: 2b12 cmp r3, #18
|
|
80006ec: d82a bhi.n 8000744 <HAL_GPIO_Init+0xcc>
|
|
80006ee: 2b12 cmp r3, #18
|
|
80006f0: d859 bhi.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
80006f2: a201 add r2, pc, #4 @ (adr r2, 80006f8 <HAL_GPIO_Init+0x80>)
|
|
80006f4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80006f8: 08000773 .word 0x08000773
|
|
80006fc: 0800074d .word 0x0800074d
|
|
8000700: 0800075f .word 0x0800075f
|
|
8000704: 080007a1 .word 0x080007a1
|
|
8000708: 080007a7 .word 0x080007a7
|
|
800070c: 080007a7 .word 0x080007a7
|
|
8000710: 080007a7 .word 0x080007a7
|
|
8000714: 080007a7 .word 0x080007a7
|
|
8000718: 080007a7 .word 0x080007a7
|
|
800071c: 080007a7 .word 0x080007a7
|
|
8000720: 080007a7 .word 0x080007a7
|
|
8000724: 080007a7 .word 0x080007a7
|
|
8000728: 080007a7 .word 0x080007a7
|
|
800072c: 080007a7 .word 0x080007a7
|
|
8000730: 080007a7 .word 0x080007a7
|
|
8000734: 080007a7 .word 0x080007a7
|
|
8000738: 080007a7 .word 0x080007a7
|
|
800073c: 08000755 .word 0x08000755
|
|
8000740: 08000769 .word 0x08000769
|
|
8000744: 4a79 ldr r2, [pc, #484] @ (800092c <HAL_GPIO_Init+0x2b4>)
|
|
8000746: 4293 cmp r3, r2
|
|
8000748: d013 beq.n 8000772 <HAL_GPIO_Init+0xfa>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
break;
|
|
|
|
/* Parameters are checked with assert_param */
|
|
default:
|
|
break;
|
|
800074a: e02c b.n 80007a6 <HAL_GPIO_Init+0x12e>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
800074c: 683b ldr r3, [r7, #0]
|
|
800074e: 68db ldr r3, [r3, #12]
|
|
8000750: 623b str r3, [r7, #32]
|
|
break;
|
|
8000752: e029 b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
8000754: 683b ldr r3, [r7, #0]
|
|
8000756: 68db ldr r3, [r3, #12]
|
|
8000758: 3304 adds r3, #4
|
|
800075a: 623b str r3, [r7, #32]
|
|
break;
|
|
800075c: e024 b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
800075e: 683b ldr r3, [r7, #0]
|
|
8000760: 68db ldr r3, [r3, #12]
|
|
8000762: 3308 adds r3, #8
|
|
8000764: 623b str r3, [r7, #32]
|
|
break;
|
|
8000766: e01f b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
8000768: 683b ldr r3, [r7, #0]
|
|
800076a: 68db ldr r3, [r3, #12]
|
|
800076c: 330c adds r3, #12
|
|
800076e: 623b str r3, [r7, #32]
|
|
break;
|
|
8000770: e01a b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
8000772: 683b ldr r3, [r7, #0]
|
|
8000774: 689b ldr r3, [r3, #8]
|
|
8000776: 2b00 cmp r3, #0
|
|
8000778: d102 bne.n 8000780 <HAL_GPIO_Init+0x108>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
800077a: 2304 movs r3, #4
|
|
800077c: 623b str r3, [r7, #32]
|
|
break;
|
|
800077e: e013 b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
8000780: 683b ldr r3, [r7, #0]
|
|
8000782: 689b ldr r3, [r3, #8]
|
|
8000784: 2b01 cmp r3, #1
|
|
8000786: d105 bne.n 8000794 <HAL_GPIO_Init+0x11c>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8000788: 2308 movs r3, #8
|
|
800078a: 623b str r3, [r7, #32]
|
|
GPIOx->BSRR = ioposition;
|
|
800078c: 687b ldr r3, [r7, #4]
|
|
800078e: 69fa ldr r2, [r7, #28]
|
|
8000790: 611a str r2, [r3, #16]
|
|
break;
|
|
8000792: e009 b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8000794: 2308 movs r3, #8
|
|
8000796: 623b str r3, [r7, #32]
|
|
GPIOx->BRR = ioposition;
|
|
8000798: 687b ldr r3, [r7, #4]
|
|
800079a: 69fa ldr r2, [r7, #28]
|
|
800079c: 615a str r2, [r3, #20]
|
|
break;
|
|
800079e: e003 b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
80007a0: 2300 movs r3, #0
|
|
80007a2: 623b str r3, [r7, #32]
|
|
break;
|
|
80007a4: e000 b.n 80007a8 <HAL_GPIO_Init+0x130>
|
|
break;
|
|
80007a6: bf00 nop
|
|
}
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
in order to address CRH or CRL register*/
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
80007a8: 69bb ldr r3, [r7, #24]
|
|
80007aa: 2bff cmp r3, #255 @ 0xff
|
|
80007ac: d801 bhi.n 80007b2 <HAL_GPIO_Init+0x13a>
|
|
80007ae: 687b ldr r3, [r7, #4]
|
|
80007b0: e001 b.n 80007b6 <HAL_GPIO_Init+0x13e>
|
|
80007b2: 687b ldr r3, [r7, #4]
|
|
80007b4: 3304 adds r3, #4
|
|
80007b6: 617b str r3, [r7, #20]
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
80007b8: 69bb ldr r3, [r7, #24]
|
|
80007ba: 2bff cmp r3, #255 @ 0xff
|
|
80007bc: d802 bhi.n 80007c4 <HAL_GPIO_Init+0x14c>
|
|
80007be: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80007c0: 009b lsls r3, r3, #2
|
|
80007c2: e002 b.n 80007ca <HAL_GPIO_Init+0x152>
|
|
80007c4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80007c6: 3b08 subs r3, #8
|
|
80007c8: 009b lsls r3, r3, #2
|
|
80007ca: 613b str r3, [r7, #16]
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
80007cc: 697b ldr r3, [r7, #20]
|
|
80007ce: 681a ldr r2, [r3, #0]
|
|
80007d0: 210f movs r1, #15
|
|
80007d2: 693b ldr r3, [r7, #16]
|
|
80007d4: fa01 f303 lsl.w r3, r1, r3
|
|
80007d8: 43db mvns r3, r3
|
|
80007da: 401a ands r2, r3
|
|
80007dc: 6a39 ldr r1, [r7, #32]
|
|
80007de: 693b ldr r3, [r7, #16]
|
|
80007e0: fa01 f303 lsl.w r3, r1, r3
|
|
80007e4: 431a orrs r2, r3
|
|
80007e6: 697b ldr r3, [r7, #20]
|
|
80007e8: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
80007ea: 683b ldr r3, [r7, #0]
|
|
80007ec: 685b ldr r3, [r3, #4]
|
|
80007ee: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80007f2: 2b00 cmp r3, #0
|
|
80007f4: f000 80b1 beq.w 800095a <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable AFIO Clock */
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
80007f8: 4b4d ldr r3, [pc, #308] @ (8000930 <HAL_GPIO_Init+0x2b8>)
|
|
80007fa: 699b ldr r3, [r3, #24]
|
|
80007fc: 4a4c ldr r2, [pc, #304] @ (8000930 <HAL_GPIO_Init+0x2b8>)
|
|
80007fe: f043 0301 orr.w r3, r3, #1
|
|
8000802: 6193 str r3, [r2, #24]
|
|
8000804: 4b4a ldr r3, [pc, #296] @ (8000930 <HAL_GPIO_Init+0x2b8>)
|
|
8000806: 699b ldr r3, [r3, #24]
|
|
8000808: f003 0301 and.w r3, r3, #1
|
|
800080c: 60bb str r3, [r7, #8]
|
|
800080e: 68bb ldr r3, [r7, #8]
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
8000810: 4a48 ldr r2, [pc, #288] @ (8000934 <HAL_GPIO_Init+0x2bc>)
|
|
8000812: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000814: 089b lsrs r3, r3, #2
|
|
8000816: 3302 adds r3, #2
|
|
8000818: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800081c: 60fb str r3, [r7, #12]
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
800081e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000820: f003 0303 and.w r3, r3, #3
|
|
8000824: 009b lsls r3, r3, #2
|
|
8000826: 220f movs r2, #15
|
|
8000828: fa02 f303 lsl.w r3, r2, r3
|
|
800082c: 43db mvns r3, r3
|
|
800082e: 68fa ldr r2, [r7, #12]
|
|
8000830: 4013 ands r3, r2
|
|
8000832: 60fb str r3, [r7, #12]
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
8000834: 687b ldr r3, [r7, #4]
|
|
8000836: 4a40 ldr r2, [pc, #256] @ (8000938 <HAL_GPIO_Init+0x2c0>)
|
|
8000838: 4293 cmp r3, r2
|
|
800083a: d013 beq.n 8000864 <HAL_GPIO_Init+0x1ec>
|
|
800083c: 687b ldr r3, [r7, #4]
|
|
800083e: 4a3f ldr r2, [pc, #252] @ (800093c <HAL_GPIO_Init+0x2c4>)
|
|
8000840: 4293 cmp r3, r2
|
|
8000842: d00d beq.n 8000860 <HAL_GPIO_Init+0x1e8>
|
|
8000844: 687b ldr r3, [r7, #4]
|
|
8000846: 4a3e ldr r2, [pc, #248] @ (8000940 <HAL_GPIO_Init+0x2c8>)
|
|
8000848: 4293 cmp r3, r2
|
|
800084a: d007 beq.n 800085c <HAL_GPIO_Init+0x1e4>
|
|
800084c: 687b ldr r3, [r7, #4]
|
|
800084e: 4a3d ldr r2, [pc, #244] @ (8000944 <HAL_GPIO_Init+0x2cc>)
|
|
8000850: 4293 cmp r3, r2
|
|
8000852: d101 bne.n 8000858 <HAL_GPIO_Init+0x1e0>
|
|
8000854: 2303 movs r3, #3
|
|
8000856: e006 b.n 8000866 <HAL_GPIO_Init+0x1ee>
|
|
8000858: 2304 movs r3, #4
|
|
800085a: e004 b.n 8000866 <HAL_GPIO_Init+0x1ee>
|
|
800085c: 2302 movs r3, #2
|
|
800085e: e002 b.n 8000866 <HAL_GPIO_Init+0x1ee>
|
|
8000860: 2301 movs r3, #1
|
|
8000862: e000 b.n 8000866 <HAL_GPIO_Init+0x1ee>
|
|
8000864: 2300 movs r3, #0
|
|
8000866: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8000868: f002 0203 and.w r2, r2, #3
|
|
800086c: 0092 lsls r2, r2, #2
|
|
800086e: 4093 lsls r3, r2
|
|
8000870: 68fa ldr r2, [r7, #12]
|
|
8000872: 4313 orrs r3, r2
|
|
8000874: 60fb str r3, [r7, #12]
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
8000876: 492f ldr r1, [pc, #188] @ (8000934 <HAL_GPIO_Init+0x2bc>)
|
|
8000878: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800087a: 089b lsrs r3, r3, #2
|
|
800087c: 3302 adds r3, #2
|
|
800087e: 68fa ldr r2, [r7, #12]
|
|
8000880: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
/* Enable or disable the rising trigger */
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
8000884: 683b ldr r3, [r7, #0]
|
|
8000886: 685b ldr r3, [r3, #4]
|
|
8000888: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800088c: 2b00 cmp r3, #0
|
|
800088e: d006 beq.n 800089e <HAL_GPIO_Init+0x226>
|
|
{
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
8000890: 4b2d ldr r3, [pc, #180] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
8000892: 689a ldr r2, [r3, #8]
|
|
8000894: 492c ldr r1, [pc, #176] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
8000896: 69bb ldr r3, [r7, #24]
|
|
8000898: 4313 orrs r3, r2
|
|
800089a: 608b str r3, [r1, #8]
|
|
800089c: e006 b.n 80008ac <HAL_GPIO_Init+0x234>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
800089e: 4b2a ldr r3, [pc, #168] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008a0: 689a ldr r2, [r3, #8]
|
|
80008a2: 69bb ldr r3, [r7, #24]
|
|
80008a4: 43db mvns r3, r3
|
|
80008a6: 4928 ldr r1, [pc, #160] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008a8: 4013 ands r3, r2
|
|
80008aa: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Enable or disable the falling trigger */
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
80008ac: 683b ldr r3, [r7, #0]
|
|
80008ae: 685b ldr r3, [r3, #4]
|
|
80008b0: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80008b4: 2b00 cmp r3, #0
|
|
80008b6: d006 beq.n 80008c6 <HAL_GPIO_Init+0x24e>
|
|
{
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
80008b8: 4b23 ldr r3, [pc, #140] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008ba: 68da ldr r2, [r3, #12]
|
|
80008bc: 4922 ldr r1, [pc, #136] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008be: 69bb ldr r3, [r7, #24]
|
|
80008c0: 4313 orrs r3, r2
|
|
80008c2: 60cb str r3, [r1, #12]
|
|
80008c4: e006 b.n 80008d4 <HAL_GPIO_Init+0x25c>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
80008c6: 4b20 ldr r3, [pc, #128] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008c8: 68da ldr r2, [r3, #12]
|
|
80008ca: 69bb ldr r3, [r7, #24]
|
|
80008cc: 43db mvns r3, r3
|
|
80008ce: 491e ldr r1, [pc, #120] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008d0: 4013 ands r3, r2
|
|
80008d2: 60cb str r3, [r1, #12]
|
|
}
|
|
|
|
/* Configure the event mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
80008d4: 683b ldr r3, [r7, #0]
|
|
80008d6: 685b ldr r3, [r3, #4]
|
|
80008d8: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80008dc: 2b00 cmp r3, #0
|
|
80008de: d006 beq.n 80008ee <HAL_GPIO_Init+0x276>
|
|
{
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
80008e0: 4b19 ldr r3, [pc, #100] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008e2: 685a ldr r2, [r3, #4]
|
|
80008e4: 4918 ldr r1, [pc, #96] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008e6: 69bb ldr r3, [r7, #24]
|
|
80008e8: 4313 orrs r3, r2
|
|
80008ea: 604b str r3, [r1, #4]
|
|
80008ec: e006 b.n 80008fc <HAL_GPIO_Init+0x284>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
80008ee: 4b16 ldr r3, [pc, #88] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008f0: 685a ldr r2, [r3, #4]
|
|
80008f2: 69bb ldr r3, [r7, #24]
|
|
80008f4: 43db mvns r3, r3
|
|
80008f6: 4914 ldr r1, [pc, #80] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
80008f8: 4013 ands r3, r2
|
|
80008fa: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the interrupt mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
80008fc: 683b ldr r3, [r7, #0]
|
|
80008fe: 685b ldr r3, [r3, #4]
|
|
8000900: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8000904: 2b00 cmp r3, #0
|
|
8000906: d021 beq.n 800094c <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
8000908: 4b0f ldr r3, [pc, #60] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
800090a: 681a ldr r2, [r3, #0]
|
|
800090c: 490e ldr r1, [pc, #56] @ (8000948 <HAL_GPIO_Init+0x2d0>)
|
|
800090e: 69bb ldr r3, [r7, #24]
|
|
8000910: 4313 orrs r3, r2
|
|
8000912: 600b str r3, [r1, #0]
|
|
8000914: e021 b.n 800095a <HAL_GPIO_Init+0x2e2>
|
|
8000916: bf00 nop
|
|
8000918: 10320000 .word 0x10320000
|
|
800091c: 10310000 .word 0x10310000
|
|
8000920: 10220000 .word 0x10220000
|
|
8000924: 10210000 .word 0x10210000
|
|
8000928: 10120000 .word 0x10120000
|
|
800092c: 10110000 .word 0x10110000
|
|
8000930: 40021000 .word 0x40021000
|
|
8000934: 40010000 .word 0x40010000
|
|
8000938: 40010800 .word 0x40010800
|
|
800093c: 40010c00 .word 0x40010c00
|
|
8000940: 40011000 .word 0x40011000
|
|
8000944: 40011400 .word 0x40011400
|
|
8000948: 40010400 .word 0x40010400
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
800094c: 4b0b ldr r3, [pc, #44] @ (800097c <HAL_GPIO_Init+0x304>)
|
|
800094e: 681a ldr r2, [r3, #0]
|
|
8000950: 69bb ldr r3, [r7, #24]
|
|
8000952: 43db mvns r3, r3
|
|
8000954: 4909 ldr r1, [pc, #36] @ (800097c <HAL_GPIO_Init+0x304>)
|
|
8000956: 4013 ands r3, r2
|
|
8000958: 600b str r3, [r1, #0]
|
|
}
|
|
}
|
|
}
|
|
|
|
position++;
|
|
800095a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800095c: 3301 adds r3, #1
|
|
800095e: 627b str r3, [r7, #36] @ 0x24
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000960: 683b ldr r3, [r7, #0]
|
|
8000962: 681a ldr r2, [r3, #0]
|
|
8000964: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000966: fa22 f303 lsr.w r3, r2, r3
|
|
800096a: 2b00 cmp r3, #0
|
|
800096c: f47f ae8e bne.w 800068c <HAL_GPIO_Init+0x14>
|
|
}
|
|
}
|
|
8000970: bf00 nop
|
|
8000972: bf00 nop
|
|
8000974: 372c adds r7, #44 @ 0x2c
|
|
8000976: 46bd mov sp, r7
|
|
8000978: bc80 pop {r7}
|
|
800097a: 4770 bx lr
|
|
800097c: 40010400 .word 0x40010400
|
|
|
|
08000980 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8000980: b480 push {r7}
|
|
8000982: b083 sub sp, #12
|
|
8000984: af00 add r7, sp, #0
|
|
8000986: 6078 str r0, [r7, #4]
|
|
8000988: 460b mov r3, r1
|
|
800098a: 807b strh r3, [r7, #2]
|
|
800098c: 4613 mov r3, r2
|
|
800098e: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8000990: 787b ldrb r3, [r7, #1]
|
|
8000992: 2b00 cmp r3, #0
|
|
8000994: d003 beq.n 800099e <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8000996: 887a ldrh r2, [r7, #2]
|
|
8000998: 687b ldr r3, [r7, #4]
|
|
800099a: 611a str r2, [r3, #16]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
}
|
|
}
|
|
800099c: e003 b.n 80009a6 <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
800099e: 887b ldrh r3, [r7, #2]
|
|
80009a0: 041a lsls r2, r3, #16
|
|
80009a2: 687b ldr r3, [r7, #4]
|
|
80009a4: 611a str r2, [r3, #16]
|
|
}
|
|
80009a6: bf00 nop
|
|
80009a8: 370c adds r7, #12
|
|
80009aa: 46bd mov sp, r7
|
|
80009ac: bc80 pop {r7}
|
|
80009ae: 4770 bx lr
|
|
|
|
080009b0 <HAL_GPIO_TogglePin>:
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
|
* @param GPIO_Pin: Specifies the pins to be toggled.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
80009b0: b480 push {r7}
|
|
80009b2: b085 sub sp, #20
|
|
80009b4: af00 add r7, sp, #0
|
|
80009b6: 6078 str r0, [r7, #4]
|
|
80009b8: 460b mov r3, r1
|
|
80009ba: 807b strh r3, [r7, #2]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* get current Output Data Register value */
|
|
odr = GPIOx->ODR;
|
|
80009bc: 687b ldr r3, [r7, #4]
|
|
80009be: 68db ldr r3, [r3, #12]
|
|
80009c0: 60fb str r3, [r7, #12]
|
|
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
|
80009c2: 887a ldrh r2, [r7, #2]
|
|
80009c4: 68fb ldr r3, [r7, #12]
|
|
80009c6: 4013 ands r3, r2
|
|
80009c8: 041a lsls r2, r3, #16
|
|
80009ca: 68fb ldr r3, [r7, #12]
|
|
80009cc: 43d9 mvns r1, r3
|
|
80009ce: 887b ldrh r3, [r7, #2]
|
|
80009d0: 400b ands r3, r1
|
|
80009d2: 431a orrs r2, r3
|
|
80009d4: 687b ldr r3, [r7, #4]
|
|
80009d6: 611a str r2, [r3, #16]
|
|
}
|
|
80009d8: bf00 nop
|
|
80009da: 3714 adds r7, #20
|
|
80009dc: 46bd mov sp, r7
|
|
80009de: bc80 pop {r7}
|
|
80009e0: 4770 bx lr
|
|
...
|
|
|
|
080009e4 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
80009e4: b580 push {r7, lr}
|
|
80009e6: b086 sub sp, #24
|
|
80009e8: af00 add r7, sp, #0
|
|
80009ea: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
80009ec: 687b ldr r3, [r7, #4]
|
|
80009ee: 2b00 cmp r3, #0
|
|
80009f0: d101 bne.n 80009f6 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80009f2: 2301 movs r3, #1
|
|
80009f4: e272 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
80009f6: 687b ldr r3, [r7, #4]
|
|
80009f8: 681b ldr r3, [r3, #0]
|
|
80009fa: f003 0301 and.w r3, r3, #1
|
|
80009fe: 2b00 cmp r3, #0
|
|
8000a00: f000 8087 beq.w 8000b12 <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8000a04: 4b92 ldr r3, [pc, #584] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a06: 685b ldr r3, [r3, #4]
|
|
8000a08: f003 030c and.w r3, r3, #12
|
|
8000a0c: 2b04 cmp r3, #4
|
|
8000a0e: d00c beq.n 8000a2a <HAL_RCC_OscConfig+0x46>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8000a10: 4b8f ldr r3, [pc, #572] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a12: 685b ldr r3, [r3, #4]
|
|
8000a14: f003 030c and.w r3, r3, #12
|
|
8000a18: 2b08 cmp r3, #8
|
|
8000a1a: d112 bne.n 8000a42 <HAL_RCC_OscConfig+0x5e>
|
|
8000a1c: 4b8c ldr r3, [pc, #560] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a1e: 685b ldr r3, [r3, #4]
|
|
8000a20: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8000a24: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8000a28: d10b bne.n 8000a42 <HAL_RCC_OscConfig+0x5e>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000a2a: 4b89 ldr r3, [pc, #548] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a2c: 681b ldr r3, [r3, #0]
|
|
8000a2e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8000a32: 2b00 cmp r3, #0
|
|
8000a34: d06c beq.n 8000b10 <HAL_RCC_OscConfig+0x12c>
|
|
8000a36: 687b ldr r3, [r7, #4]
|
|
8000a38: 685b ldr r3, [r3, #4]
|
|
8000a3a: 2b00 cmp r3, #0
|
|
8000a3c: d168 bne.n 8000b10 <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
return HAL_ERROR;
|
|
8000a3e: 2301 movs r3, #1
|
|
8000a40: e24c b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8000a42: 687b ldr r3, [r7, #4]
|
|
8000a44: 685b ldr r3, [r3, #4]
|
|
8000a46: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8000a4a: d106 bne.n 8000a5a <HAL_RCC_OscConfig+0x76>
|
|
8000a4c: 4b80 ldr r3, [pc, #512] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a4e: 681b ldr r3, [r3, #0]
|
|
8000a50: 4a7f ldr r2, [pc, #508] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a52: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8000a56: 6013 str r3, [r2, #0]
|
|
8000a58: e02e b.n 8000ab8 <HAL_RCC_OscConfig+0xd4>
|
|
8000a5a: 687b ldr r3, [r7, #4]
|
|
8000a5c: 685b ldr r3, [r3, #4]
|
|
8000a5e: 2b00 cmp r3, #0
|
|
8000a60: d10c bne.n 8000a7c <HAL_RCC_OscConfig+0x98>
|
|
8000a62: 4b7b ldr r3, [pc, #492] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a64: 681b ldr r3, [r3, #0]
|
|
8000a66: 4a7a ldr r2, [pc, #488] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a68: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8000a6c: 6013 str r3, [r2, #0]
|
|
8000a6e: 4b78 ldr r3, [pc, #480] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a70: 681b ldr r3, [r3, #0]
|
|
8000a72: 4a77 ldr r2, [pc, #476] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a74: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8000a78: 6013 str r3, [r2, #0]
|
|
8000a7a: e01d b.n 8000ab8 <HAL_RCC_OscConfig+0xd4>
|
|
8000a7c: 687b ldr r3, [r7, #4]
|
|
8000a7e: 685b ldr r3, [r3, #4]
|
|
8000a80: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8000a84: d10c bne.n 8000aa0 <HAL_RCC_OscConfig+0xbc>
|
|
8000a86: 4b72 ldr r3, [pc, #456] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a88: 681b ldr r3, [r3, #0]
|
|
8000a8a: 4a71 ldr r2, [pc, #452] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a8c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8000a90: 6013 str r3, [r2, #0]
|
|
8000a92: 4b6f ldr r3, [pc, #444] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a94: 681b ldr r3, [r3, #0]
|
|
8000a96: 4a6e ldr r2, [pc, #440] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000a98: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8000a9c: 6013 str r3, [r2, #0]
|
|
8000a9e: e00b b.n 8000ab8 <HAL_RCC_OscConfig+0xd4>
|
|
8000aa0: 4b6b ldr r3, [pc, #428] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000aa2: 681b ldr r3, [r3, #0]
|
|
8000aa4: 4a6a ldr r2, [pc, #424] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000aa6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8000aaa: 6013 str r3, [r2, #0]
|
|
8000aac: 4b68 ldr r3, [pc, #416] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000aae: 681b ldr r3, [r3, #0]
|
|
8000ab0: 4a67 ldr r2, [pc, #412] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000ab2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8000ab6: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8000ab8: 687b ldr r3, [r7, #4]
|
|
8000aba: 685b ldr r3, [r3, #4]
|
|
8000abc: 2b00 cmp r3, #0
|
|
8000abe: d013 beq.n 8000ae8 <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000ac0: f7ff fcc8 bl 8000454 <HAL_GetTick>
|
|
8000ac4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000ac6: e008 b.n 8000ada <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000ac8: f7ff fcc4 bl 8000454 <HAL_GetTick>
|
|
8000acc: 4602 mov r2, r0
|
|
8000ace: 693b ldr r3, [r7, #16]
|
|
8000ad0: 1ad3 subs r3, r2, r3
|
|
8000ad2: 2b64 cmp r3, #100 @ 0x64
|
|
8000ad4: d901 bls.n 8000ada <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000ad6: 2303 movs r3, #3
|
|
8000ad8: e200 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000ada: 4b5d ldr r3, [pc, #372] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000adc: 681b ldr r3, [r3, #0]
|
|
8000ade: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8000ae2: 2b00 cmp r3, #0
|
|
8000ae4: d0f0 beq.n 8000ac8 <HAL_RCC_OscConfig+0xe4>
|
|
8000ae6: e014 b.n 8000b12 <HAL_RCC_OscConfig+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000ae8: f7ff fcb4 bl 8000454 <HAL_GetTick>
|
|
8000aec: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000aee: e008 b.n 8000b02 <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000af0: f7ff fcb0 bl 8000454 <HAL_GetTick>
|
|
8000af4: 4602 mov r2, r0
|
|
8000af6: 693b ldr r3, [r7, #16]
|
|
8000af8: 1ad3 subs r3, r2, r3
|
|
8000afa: 2b64 cmp r3, #100 @ 0x64
|
|
8000afc: d901 bls.n 8000b02 <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000afe: 2303 movs r3, #3
|
|
8000b00: e1ec b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000b02: 4b53 ldr r3, [pc, #332] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b04: 681b ldr r3, [r3, #0]
|
|
8000b06: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8000b0a: 2b00 cmp r3, #0
|
|
8000b0c: d1f0 bne.n 8000af0 <HAL_RCC_OscConfig+0x10c>
|
|
8000b0e: e000 b.n 8000b12 <HAL_RCC_OscConfig+0x12e>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000b10: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8000b12: 687b ldr r3, [r7, #4]
|
|
8000b14: 681b ldr r3, [r3, #0]
|
|
8000b16: f003 0302 and.w r3, r3, #2
|
|
8000b1a: 2b00 cmp r3, #0
|
|
8000b1c: d063 beq.n 8000be6 <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8000b1e: 4b4c ldr r3, [pc, #304] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b20: 685b ldr r3, [r3, #4]
|
|
8000b22: f003 030c and.w r3, r3, #12
|
|
8000b26: 2b00 cmp r3, #0
|
|
8000b28: d00b beq.n 8000b42 <HAL_RCC_OscConfig+0x15e>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
8000b2a: 4b49 ldr r3, [pc, #292] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b2c: 685b ldr r3, [r3, #4]
|
|
8000b2e: f003 030c and.w r3, r3, #12
|
|
8000b32: 2b08 cmp r3, #8
|
|
8000b34: d11c bne.n 8000b70 <HAL_RCC_OscConfig+0x18c>
|
|
8000b36: 4b46 ldr r3, [pc, #280] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b38: 685b ldr r3, [r3, #4]
|
|
8000b3a: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8000b3e: 2b00 cmp r3, #0
|
|
8000b40: d116 bne.n 8000b70 <HAL_RCC_OscConfig+0x18c>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000b42: 4b43 ldr r3, [pc, #268] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b44: 681b ldr r3, [r3, #0]
|
|
8000b46: f003 0302 and.w r3, r3, #2
|
|
8000b4a: 2b00 cmp r3, #0
|
|
8000b4c: d005 beq.n 8000b5a <HAL_RCC_OscConfig+0x176>
|
|
8000b4e: 687b ldr r3, [r7, #4]
|
|
8000b50: 691b ldr r3, [r3, #16]
|
|
8000b52: 2b01 cmp r3, #1
|
|
8000b54: d001 beq.n 8000b5a <HAL_RCC_OscConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8000b56: 2301 movs r3, #1
|
|
8000b58: e1c0 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000b5a: 4b3d ldr r3, [pc, #244] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b5c: 681b ldr r3, [r3, #0]
|
|
8000b5e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8000b62: 687b ldr r3, [r7, #4]
|
|
8000b64: 695b ldr r3, [r3, #20]
|
|
8000b66: 00db lsls r3, r3, #3
|
|
8000b68: 4939 ldr r1, [pc, #228] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b6a: 4313 orrs r3, r2
|
|
8000b6c: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000b6e: e03a b.n 8000be6 <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8000b70: 687b ldr r3, [r7, #4]
|
|
8000b72: 691b ldr r3, [r3, #16]
|
|
8000b74: 2b00 cmp r3, #0
|
|
8000b76: d020 beq.n 8000bba <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8000b78: 4b36 ldr r3, [pc, #216] @ (8000c54 <HAL_RCC_OscConfig+0x270>)
|
|
8000b7a: 2201 movs r2, #1
|
|
8000b7c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000b7e: f7ff fc69 bl 8000454 <HAL_GetTick>
|
|
8000b82: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000b84: e008 b.n 8000b98 <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000b86: f7ff fc65 bl 8000454 <HAL_GetTick>
|
|
8000b8a: 4602 mov r2, r0
|
|
8000b8c: 693b ldr r3, [r7, #16]
|
|
8000b8e: 1ad3 subs r3, r2, r3
|
|
8000b90: 2b02 cmp r3, #2
|
|
8000b92: d901 bls.n 8000b98 <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000b94: 2303 movs r3, #3
|
|
8000b96: e1a1 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000b98: 4b2d ldr r3, [pc, #180] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b9a: 681b ldr r3, [r3, #0]
|
|
8000b9c: f003 0302 and.w r3, r3, #2
|
|
8000ba0: 2b00 cmp r3, #0
|
|
8000ba2: d0f0 beq.n 8000b86 <HAL_RCC_OscConfig+0x1a2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000ba4: 4b2a ldr r3, [pc, #168] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000ba6: 681b ldr r3, [r3, #0]
|
|
8000ba8: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8000bac: 687b ldr r3, [r7, #4]
|
|
8000bae: 695b ldr r3, [r3, #20]
|
|
8000bb0: 00db lsls r3, r3, #3
|
|
8000bb2: 4927 ldr r1, [pc, #156] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bb4: 4313 orrs r3, r2
|
|
8000bb6: 600b str r3, [r1, #0]
|
|
8000bb8: e015 b.n 8000be6 <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8000bba: 4b26 ldr r3, [pc, #152] @ (8000c54 <HAL_RCC_OscConfig+0x270>)
|
|
8000bbc: 2200 movs r2, #0
|
|
8000bbe: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000bc0: f7ff fc48 bl 8000454 <HAL_GetTick>
|
|
8000bc4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8000bc6: e008 b.n 8000bda <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000bc8: f7ff fc44 bl 8000454 <HAL_GetTick>
|
|
8000bcc: 4602 mov r2, r0
|
|
8000bce: 693b ldr r3, [r7, #16]
|
|
8000bd0: 1ad3 subs r3, r2, r3
|
|
8000bd2: 2b02 cmp r3, #2
|
|
8000bd4: d901 bls.n 8000bda <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000bd6: 2303 movs r3, #3
|
|
8000bd8: e180 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8000bda: 4b1d ldr r3, [pc, #116] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bdc: 681b ldr r3, [r3, #0]
|
|
8000bde: f003 0302 and.w r3, r3, #2
|
|
8000be2: 2b00 cmp r3, #0
|
|
8000be4: d1f0 bne.n 8000bc8 <HAL_RCC_OscConfig+0x1e4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8000be6: 687b ldr r3, [r7, #4]
|
|
8000be8: 681b ldr r3, [r3, #0]
|
|
8000bea: f003 0308 and.w r3, r3, #8
|
|
8000bee: 2b00 cmp r3, #0
|
|
8000bf0: d03a beq.n 8000c68 <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8000bf2: 687b ldr r3, [r7, #4]
|
|
8000bf4: 699b ldr r3, [r3, #24]
|
|
8000bf6: 2b00 cmp r3, #0
|
|
8000bf8: d019 beq.n 8000c2e <HAL_RCC_OscConfig+0x24a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8000bfa: 4b17 ldr r3, [pc, #92] @ (8000c58 <HAL_RCC_OscConfig+0x274>)
|
|
8000bfc: 2201 movs r2, #1
|
|
8000bfe: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000c00: f7ff fc28 bl 8000454 <HAL_GetTick>
|
|
8000c04: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8000c06: e008 b.n 8000c1a <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000c08: f7ff fc24 bl 8000454 <HAL_GetTick>
|
|
8000c0c: 4602 mov r2, r0
|
|
8000c0e: 693b ldr r3, [r7, #16]
|
|
8000c10: 1ad3 subs r3, r2, r3
|
|
8000c12: 2b02 cmp r3, #2
|
|
8000c14: d901 bls.n 8000c1a <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000c16: 2303 movs r3, #3
|
|
8000c18: e160 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8000c1a: 4b0d ldr r3, [pc, #52] @ (8000c50 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c1c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000c1e: f003 0302 and.w r3, r3, #2
|
|
8000c22: 2b00 cmp r3, #0
|
|
8000c24: d0f0 beq.n 8000c08 <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
}
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
should be added.*/
|
|
RCC_Delay(1);
|
|
8000c26: 2001 movs r0, #1
|
|
8000c28: f000 fa9c bl 8001164 <RCC_Delay>
|
|
8000c2c: e01c b.n 8000c68 <HAL_RCC_OscConfig+0x284>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8000c2e: 4b0a ldr r3, [pc, #40] @ (8000c58 <HAL_RCC_OscConfig+0x274>)
|
|
8000c30: 2200 movs r2, #0
|
|
8000c32: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000c34: f7ff fc0e bl 8000454 <HAL_GetTick>
|
|
8000c38: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8000c3a: e00f b.n 8000c5c <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000c3c: f7ff fc0a bl 8000454 <HAL_GetTick>
|
|
8000c40: 4602 mov r2, r0
|
|
8000c42: 693b ldr r3, [r7, #16]
|
|
8000c44: 1ad3 subs r3, r2, r3
|
|
8000c46: 2b02 cmp r3, #2
|
|
8000c48: d908 bls.n 8000c5c <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000c4a: 2303 movs r3, #3
|
|
8000c4c: e146 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
8000c4e: bf00 nop
|
|
8000c50: 40021000 .word 0x40021000
|
|
8000c54: 42420000 .word 0x42420000
|
|
8000c58: 42420480 .word 0x42420480
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8000c5c: 4b92 ldr r3, [pc, #584] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000c5e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000c60: f003 0302 and.w r3, r3, #2
|
|
8000c64: 2b00 cmp r3, #0
|
|
8000c66: d1e9 bne.n 8000c3c <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8000c68: 687b ldr r3, [r7, #4]
|
|
8000c6a: 681b ldr r3, [r3, #0]
|
|
8000c6c: f003 0304 and.w r3, r3, #4
|
|
8000c70: 2b00 cmp r3, #0
|
|
8000c72: f000 80a6 beq.w 8000dc2 <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8000c76: 2300 movs r3, #0
|
|
8000c78: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8000c7a: 4b8b ldr r3, [pc, #556] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000c7c: 69db ldr r3, [r3, #28]
|
|
8000c7e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000c82: 2b00 cmp r3, #0
|
|
8000c84: d10d bne.n 8000ca2 <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000c86: 4b88 ldr r3, [pc, #544] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000c88: 69db ldr r3, [r3, #28]
|
|
8000c8a: 4a87 ldr r2, [pc, #540] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000c8c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000c90: 61d3 str r3, [r2, #28]
|
|
8000c92: 4b85 ldr r3, [pc, #532] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000c94: 69db ldr r3, [r3, #28]
|
|
8000c96: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000c9a: 60bb str r3, [r7, #8]
|
|
8000c9c: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8000c9e: 2301 movs r3, #1
|
|
8000ca0: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000ca2: 4b82 ldr r3, [pc, #520] @ (8000eac <HAL_RCC_OscConfig+0x4c8>)
|
|
8000ca4: 681b ldr r3, [r3, #0]
|
|
8000ca6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8000caa: 2b00 cmp r3, #0
|
|
8000cac: d118 bne.n 8000ce0 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8000cae: 4b7f ldr r3, [pc, #508] @ (8000eac <HAL_RCC_OscConfig+0x4c8>)
|
|
8000cb0: 681b ldr r3, [r3, #0]
|
|
8000cb2: 4a7e ldr r2, [pc, #504] @ (8000eac <HAL_RCC_OscConfig+0x4c8>)
|
|
8000cb4: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8000cb8: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8000cba: f7ff fbcb bl 8000454 <HAL_GetTick>
|
|
8000cbe: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000cc0: e008 b.n 8000cd4 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8000cc2: f7ff fbc7 bl 8000454 <HAL_GetTick>
|
|
8000cc6: 4602 mov r2, r0
|
|
8000cc8: 693b ldr r3, [r7, #16]
|
|
8000cca: 1ad3 subs r3, r2, r3
|
|
8000ccc: 2b64 cmp r3, #100 @ 0x64
|
|
8000cce: d901 bls.n 8000cd4 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000cd0: 2303 movs r3, #3
|
|
8000cd2: e103 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000cd4: 4b75 ldr r3, [pc, #468] @ (8000eac <HAL_RCC_OscConfig+0x4c8>)
|
|
8000cd6: 681b ldr r3, [r3, #0]
|
|
8000cd8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8000cdc: 2b00 cmp r3, #0
|
|
8000cde: d0f0 beq.n 8000cc2 <HAL_RCC_OscConfig+0x2de>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8000ce0: 687b ldr r3, [r7, #4]
|
|
8000ce2: 68db ldr r3, [r3, #12]
|
|
8000ce4: 2b01 cmp r3, #1
|
|
8000ce6: d106 bne.n 8000cf6 <HAL_RCC_OscConfig+0x312>
|
|
8000ce8: 4b6f ldr r3, [pc, #444] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000cea: 6a1b ldr r3, [r3, #32]
|
|
8000cec: 4a6e ldr r2, [pc, #440] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000cee: f043 0301 orr.w r3, r3, #1
|
|
8000cf2: 6213 str r3, [r2, #32]
|
|
8000cf4: e02d b.n 8000d52 <HAL_RCC_OscConfig+0x36e>
|
|
8000cf6: 687b ldr r3, [r7, #4]
|
|
8000cf8: 68db ldr r3, [r3, #12]
|
|
8000cfa: 2b00 cmp r3, #0
|
|
8000cfc: d10c bne.n 8000d18 <HAL_RCC_OscConfig+0x334>
|
|
8000cfe: 4b6a ldr r3, [pc, #424] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d00: 6a1b ldr r3, [r3, #32]
|
|
8000d02: 4a69 ldr r2, [pc, #420] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d04: f023 0301 bic.w r3, r3, #1
|
|
8000d08: 6213 str r3, [r2, #32]
|
|
8000d0a: 4b67 ldr r3, [pc, #412] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d0c: 6a1b ldr r3, [r3, #32]
|
|
8000d0e: 4a66 ldr r2, [pc, #408] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d10: f023 0304 bic.w r3, r3, #4
|
|
8000d14: 6213 str r3, [r2, #32]
|
|
8000d16: e01c b.n 8000d52 <HAL_RCC_OscConfig+0x36e>
|
|
8000d18: 687b ldr r3, [r7, #4]
|
|
8000d1a: 68db ldr r3, [r3, #12]
|
|
8000d1c: 2b05 cmp r3, #5
|
|
8000d1e: d10c bne.n 8000d3a <HAL_RCC_OscConfig+0x356>
|
|
8000d20: 4b61 ldr r3, [pc, #388] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d22: 6a1b ldr r3, [r3, #32]
|
|
8000d24: 4a60 ldr r2, [pc, #384] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d26: f043 0304 orr.w r3, r3, #4
|
|
8000d2a: 6213 str r3, [r2, #32]
|
|
8000d2c: 4b5e ldr r3, [pc, #376] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d2e: 6a1b ldr r3, [r3, #32]
|
|
8000d30: 4a5d ldr r2, [pc, #372] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d32: f043 0301 orr.w r3, r3, #1
|
|
8000d36: 6213 str r3, [r2, #32]
|
|
8000d38: e00b b.n 8000d52 <HAL_RCC_OscConfig+0x36e>
|
|
8000d3a: 4b5b ldr r3, [pc, #364] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d3c: 6a1b ldr r3, [r3, #32]
|
|
8000d3e: 4a5a ldr r2, [pc, #360] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d40: f023 0301 bic.w r3, r3, #1
|
|
8000d44: 6213 str r3, [r2, #32]
|
|
8000d46: 4b58 ldr r3, [pc, #352] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d48: 6a1b ldr r3, [r3, #32]
|
|
8000d4a: 4a57 ldr r2, [pc, #348] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d4c: f023 0304 bic.w r3, r3, #4
|
|
8000d50: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8000d52: 687b ldr r3, [r7, #4]
|
|
8000d54: 68db ldr r3, [r3, #12]
|
|
8000d56: 2b00 cmp r3, #0
|
|
8000d58: d015 beq.n 8000d86 <HAL_RCC_OscConfig+0x3a2>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000d5a: f7ff fb7b bl 8000454 <HAL_GetTick>
|
|
8000d5e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8000d60: e00a b.n 8000d78 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000d62: f7ff fb77 bl 8000454 <HAL_GetTick>
|
|
8000d66: 4602 mov r2, r0
|
|
8000d68: 693b ldr r3, [r7, #16]
|
|
8000d6a: 1ad3 subs r3, r2, r3
|
|
8000d6c: f241 3288 movw r2, #5000 @ 0x1388
|
|
8000d70: 4293 cmp r3, r2
|
|
8000d72: d901 bls.n 8000d78 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000d74: 2303 movs r3, #3
|
|
8000d76: e0b1 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8000d78: 4b4b ldr r3, [pc, #300] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d7a: 6a1b ldr r3, [r3, #32]
|
|
8000d7c: f003 0302 and.w r3, r3, #2
|
|
8000d80: 2b00 cmp r3, #0
|
|
8000d82: d0ee beq.n 8000d62 <HAL_RCC_OscConfig+0x37e>
|
|
8000d84: e014 b.n 8000db0 <HAL_RCC_OscConfig+0x3cc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000d86: f7ff fb65 bl 8000454 <HAL_GetTick>
|
|
8000d8a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8000d8c: e00a b.n 8000da4 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000d8e: f7ff fb61 bl 8000454 <HAL_GetTick>
|
|
8000d92: 4602 mov r2, r0
|
|
8000d94: 693b ldr r3, [r7, #16]
|
|
8000d96: 1ad3 subs r3, r2, r3
|
|
8000d98: f241 3288 movw r2, #5000 @ 0x1388
|
|
8000d9c: 4293 cmp r3, r2
|
|
8000d9e: d901 bls.n 8000da4 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000da0: 2303 movs r3, #3
|
|
8000da2: e09b b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8000da4: 4b40 ldr r3, [pc, #256] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000da6: 6a1b ldr r3, [r3, #32]
|
|
8000da8: f003 0302 and.w r3, r3, #2
|
|
8000dac: 2b00 cmp r3, #0
|
|
8000dae: d1ee bne.n 8000d8e <HAL_RCC_OscConfig+0x3aa>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
8000db0: 7dfb ldrb r3, [r7, #23]
|
|
8000db2: 2b01 cmp r3, #1
|
|
8000db4: d105 bne.n 8000dc2 <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8000db6: 4b3c ldr r3, [pc, #240] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000db8: 69db ldr r3, [r3, #28]
|
|
8000dba: 4a3b ldr r2, [pc, #236] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000dbc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8000dc0: 61d3 str r3, [r2, #28]
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8000dc2: 687b ldr r3, [r7, #4]
|
|
8000dc4: 69db ldr r3, [r3, #28]
|
|
8000dc6: 2b00 cmp r3, #0
|
|
8000dc8: f000 8087 beq.w 8000eda <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8000dcc: 4b36 ldr r3, [pc, #216] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000dce: 685b ldr r3, [r3, #4]
|
|
8000dd0: f003 030c and.w r3, r3, #12
|
|
8000dd4: 2b08 cmp r3, #8
|
|
8000dd6: d061 beq.n 8000e9c <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8000dd8: 687b ldr r3, [r7, #4]
|
|
8000dda: 69db ldr r3, [r3, #28]
|
|
8000ddc: 2b02 cmp r3, #2
|
|
8000dde: d146 bne.n 8000e6e <HAL_RCC_OscConfig+0x48a>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8000de0: 4b33 ldr r3, [pc, #204] @ (8000eb0 <HAL_RCC_OscConfig+0x4cc>)
|
|
8000de2: 2200 movs r2, #0
|
|
8000de4: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000de6: f7ff fb35 bl 8000454 <HAL_GetTick>
|
|
8000dea: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000dec: e008 b.n 8000e00 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8000dee: f7ff fb31 bl 8000454 <HAL_GetTick>
|
|
8000df2: 4602 mov r2, r0
|
|
8000df4: 693b ldr r3, [r7, #16]
|
|
8000df6: 1ad3 subs r3, r2, r3
|
|
8000df8: 2b02 cmp r3, #2
|
|
8000dfa: d901 bls.n 8000e00 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000dfc: 2303 movs r3, #3
|
|
8000dfe: e06d b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000e00: 4b29 ldr r3, [pc, #164] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e02: 681b ldr r3, [r3, #0]
|
|
8000e04: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8000e08: 2b00 cmp r3, #0
|
|
8000e0a: d1f0 bne.n 8000dee <HAL_RCC_OscConfig+0x40a>
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
8000e0c: 687b ldr r3, [r7, #4]
|
|
8000e0e: 6a1b ldr r3, [r3, #32]
|
|
8000e10: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8000e14: d108 bne.n 8000e28 <HAL_RCC_OscConfig+0x444>
|
|
/* Set PREDIV1 source */
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Set PREDIV1 Value */
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8000e16: 4b24 ldr r3, [pc, #144] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e18: 685b ldr r3, [r3, #4]
|
|
8000e1a: f423 3200 bic.w r2, r3, #131072 @ 0x20000
|
|
8000e1e: 687b ldr r3, [r7, #4]
|
|
8000e20: 689b ldr r3, [r3, #8]
|
|
8000e22: 4921 ldr r1, [pc, #132] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e24: 4313 orrs r3, r2
|
|
8000e26: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8000e28: 4b1f ldr r3, [pc, #124] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e2a: 685b ldr r3, [r3, #4]
|
|
8000e2c: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
|
|
8000e30: 687b ldr r3, [r7, #4]
|
|
8000e32: 6a19 ldr r1, [r3, #32]
|
|
8000e34: 687b ldr r3, [r7, #4]
|
|
8000e36: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000e38: 430b orrs r3, r1
|
|
8000e3a: 491b ldr r1, [pc, #108] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e3c: 4313 orrs r3, r2
|
|
8000e3e: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8000e40: 4b1b ldr r3, [pc, #108] @ (8000eb0 <HAL_RCC_OscConfig+0x4cc>)
|
|
8000e42: 2201 movs r2, #1
|
|
8000e44: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e46: f7ff fb05 bl 8000454 <HAL_GetTick>
|
|
8000e4a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8000e4c: e008 b.n 8000e60 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8000e4e: f7ff fb01 bl 8000454 <HAL_GetTick>
|
|
8000e52: 4602 mov r2, r0
|
|
8000e54: 693b ldr r3, [r7, #16]
|
|
8000e56: 1ad3 subs r3, r2, r3
|
|
8000e58: 2b02 cmp r3, #2
|
|
8000e5a: d901 bls.n 8000e60 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e5c: 2303 movs r3, #3
|
|
8000e5e: e03d b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8000e60: 4b11 ldr r3, [pc, #68] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e62: 681b ldr r3, [r3, #0]
|
|
8000e64: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8000e68: 2b00 cmp r3, #0
|
|
8000e6a: d0f0 beq.n 8000e4e <HAL_RCC_OscConfig+0x46a>
|
|
8000e6c: e035 b.n 8000eda <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8000e6e: 4b10 ldr r3, [pc, #64] @ (8000eb0 <HAL_RCC_OscConfig+0x4cc>)
|
|
8000e70: 2200 movs r2, #0
|
|
8000e72: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e74: f7ff faee bl 8000454 <HAL_GetTick>
|
|
8000e78: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000e7a: e008 b.n 8000e8e <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8000e7c: f7ff faea bl 8000454 <HAL_GetTick>
|
|
8000e80: 4602 mov r2, r0
|
|
8000e82: 693b ldr r3, [r7, #16]
|
|
8000e84: 1ad3 subs r3, r2, r3
|
|
8000e86: 2b02 cmp r3, #2
|
|
8000e88: d901 bls.n 8000e8e <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e8a: 2303 movs r3, #3
|
|
8000e8c: e026 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000e8e: 4b06 ldr r3, [pc, #24] @ (8000ea8 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e90: 681b ldr r3, [r3, #0]
|
|
8000e92: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8000e96: 2b00 cmp r3, #0
|
|
8000e98: d1f0 bne.n 8000e7c <HAL_RCC_OscConfig+0x498>
|
|
8000e9a: e01e b.n 8000eda <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8000e9c: 687b ldr r3, [r7, #4]
|
|
8000e9e: 69db ldr r3, [r3, #28]
|
|
8000ea0: 2b01 cmp r3, #1
|
|
8000ea2: d107 bne.n 8000eb4 <HAL_RCC_OscConfig+0x4d0>
|
|
{
|
|
return HAL_ERROR;
|
|
8000ea4: 2301 movs r3, #1
|
|
8000ea6: e019 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
8000ea8: 40021000 .word 0x40021000
|
|
8000eac: 40007000 .word 0x40007000
|
|
8000eb0: 42420060 .word 0x42420060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8000eb4: 4b0b ldr r3, [pc, #44] @ (8000ee4 <HAL_RCC_OscConfig+0x500>)
|
|
8000eb6: 685b ldr r3, [r3, #4]
|
|
8000eb8: 60fb str r3, [r7, #12]
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8000eba: 68fb ldr r3, [r7, #12]
|
|
8000ebc: f403 3280 and.w r2, r3, #65536 @ 0x10000
|
|
8000ec0: 687b ldr r3, [r7, #4]
|
|
8000ec2: 6a1b ldr r3, [r3, #32]
|
|
8000ec4: 429a cmp r2, r3
|
|
8000ec6: d106 bne.n 8000ed6 <HAL_RCC_OscConfig+0x4f2>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8000ec8: 68fb ldr r3, [r7, #12]
|
|
8000eca: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
|
|
8000ece: 687b ldr r3, [r7, #4]
|
|
8000ed0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8000ed2: 429a cmp r2, r3
|
|
8000ed4: d001 beq.n 8000eda <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
return HAL_ERROR;
|
|
8000ed6: 2301 movs r3, #1
|
|
8000ed8: e000 b.n 8000edc <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8000eda: 2300 movs r3, #0
|
|
}
|
|
8000edc: 4618 mov r0, r3
|
|
8000ede: 3718 adds r7, #24
|
|
8000ee0: 46bd mov sp, r7
|
|
8000ee2: bd80 pop {r7, pc}
|
|
8000ee4: 40021000 .word 0x40021000
|
|
|
|
08000ee8 <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8000ee8: b580 push {r7, lr}
|
|
8000eea: b084 sub sp, #16
|
|
8000eec: af00 add r7, sp, #0
|
|
8000eee: 6078 str r0, [r7, #4]
|
|
8000ef0: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8000ef2: 687b ldr r3, [r7, #4]
|
|
8000ef4: 2b00 cmp r3, #0
|
|
8000ef6: d101 bne.n 8000efc <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8000ef8: 2301 movs r3, #1
|
|
8000efa: e0d0 b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8000efc: 4b6a ldr r3, [pc, #424] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8000efe: 681b ldr r3, [r3, #0]
|
|
8000f00: f003 0307 and.w r3, r3, #7
|
|
8000f04: 683a ldr r2, [r7, #0]
|
|
8000f06: 429a cmp r2, r3
|
|
8000f08: d910 bls.n 8000f2c <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8000f0a: 4b67 ldr r3, [pc, #412] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8000f0c: 681b ldr r3, [r3, #0]
|
|
8000f0e: f023 0207 bic.w r2, r3, #7
|
|
8000f12: 4965 ldr r1, [pc, #404] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8000f14: 683b ldr r3, [r7, #0]
|
|
8000f16: 4313 orrs r3, r2
|
|
8000f18: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8000f1a: 4b63 ldr r3, [pc, #396] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8000f1c: 681b ldr r3, [r3, #0]
|
|
8000f1e: f003 0307 and.w r3, r3, #7
|
|
8000f22: 683a ldr r2, [r7, #0]
|
|
8000f24: 429a cmp r2, r3
|
|
8000f26: d001 beq.n 8000f2c <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8000f28: 2301 movs r3, #1
|
|
8000f2a: e0b8 b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8000f2c: 687b ldr r3, [r7, #4]
|
|
8000f2e: 681b ldr r3, [r3, #0]
|
|
8000f30: f003 0302 and.w r3, r3, #2
|
|
8000f34: 2b00 cmp r3, #0
|
|
8000f36: d020 beq.n 8000f7a <HAL_RCC_ClockConfig+0x92>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8000f38: 687b ldr r3, [r7, #4]
|
|
8000f3a: 681b ldr r3, [r3, #0]
|
|
8000f3c: f003 0304 and.w r3, r3, #4
|
|
8000f40: 2b00 cmp r3, #0
|
|
8000f42: d005 beq.n 8000f50 <HAL_RCC_ClockConfig+0x68>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8000f44: 4b59 ldr r3, [pc, #356] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f46: 685b ldr r3, [r3, #4]
|
|
8000f48: 4a58 ldr r2, [pc, #352] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f4a: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
8000f4e: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8000f50: 687b ldr r3, [r7, #4]
|
|
8000f52: 681b ldr r3, [r3, #0]
|
|
8000f54: f003 0308 and.w r3, r3, #8
|
|
8000f58: 2b00 cmp r3, #0
|
|
8000f5a: d005 beq.n 8000f68 <HAL_RCC_ClockConfig+0x80>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8000f5c: 4b53 ldr r3, [pc, #332] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f5e: 685b ldr r3, [r3, #4]
|
|
8000f60: 4a52 ldr r2, [pc, #328] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f62: f443 5360 orr.w r3, r3, #14336 @ 0x3800
|
|
8000f66: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8000f68: 4b50 ldr r3, [pc, #320] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f6a: 685b ldr r3, [r3, #4]
|
|
8000f6c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8000f70: 687b ldr r3, [r7, #4]
|
|
8000f72: 689b ldr r3, [r3, #8]
|
|
8000f74: 494d ldr r1, [pc, #308] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f76: 4313 orrs r3, r2
|
|
8000f78: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8000f7a: 687b ldr r3, [r7, #4]
|
|
8000f7c: 681b ldr r3, [r3, #0]
|
|
8000f7e: f003 0301 and.w r3, r3, #1
|
|
8000f82: 2b00 cmp r3, #0
|
|
8000f84: d040 beq.n 8001008 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8000f86: 687b ldr r3, [r7, #4]
|
|
8000f88: 685b ldr r3, [r3, #4]
|
|
8000f8a: 2b01 cmp r3, #1
|
|
8000f8c: d107 bne.n 8000f9e <HAL_RCC_ClockConfig+0xb6>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000f8e: 4b47 ldr r3, [pc, #284] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000f90: 681b ldr r3, [r3, #0]
|
|
8000f92: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8000f96: 2b00 cmp r3, #0
|
|
8000f98: d115 bne.n 8000fc6 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8000f9a: 2301 movs r3, #1
|
|
8000f9c: e07f b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8000f9e: 687b ldr r3, [r7, #4]
|
|
8000fa0: 685b ldr r3, [r3, #4]
|
|
8000fa2: 2b02 cmp r3, #2
|
|
8000fa4: d107 bne.n 8000fb6 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8000fa6: 4b41 ldr r3, [pc, #260] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000fa8: 681b ldr r3, [r3, #0]
|
|
8000faa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8000fae: 2b00 cmp r3, #0
|
|
8000fb0: d109 bne.n 8000fc6 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8000fb2: 2301 movs r3, #1
|
|
8000fb4: e073 b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000fb6: 4b3d ldr r3, [pc, #244] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000fb8: 681b ldr r3, [r3, #0]
|
|
8000fba: f003 0302 and.w r3, r3, #2
|
|
8000fbe: 2b00 cmp r3, #0
|
|
8000fc0: d101 bne.n 8000fc6 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8000fc2: 2301 movs r3, #1
|
|
8000fc4: e06b b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8000fc6: 4b39 ldr r3, [pc, #228] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000fc8: 685b ldr r3, [r3, #4]
|
|
8000fca: f023 0203 bic.w r2, r3, #3
|
|
8000fce: 687b ldr r3, [r7, #4]
|
|
8000fd0: 685b ldr r3, [r3, #4]
|
|
8000fd2: 4936 ldr r1, [pc, #216] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000fd4: 4313 orrs r3, r2
|
|
8000fd6: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000fd8: f7ff fa3c bl 8000454 <HAL_GetTick>
|
|
8000fdc: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8000fde: e00a b.n 8000ff6 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8000fe0: f7ff fa38 bl 8000454 <HAL_GetTick>
|
|
8000fe4: 4602 mov r2, r0
|
|
8000fe6: 68fb ldr r3, [r7, #12]
|
|
8000fe8: 1ad3 subs r3, r2, r3
|
|
8000fea: f241 3288 movw r2, #5000 @ 0x1388
|
|
8000fee: 4293 cmp r3, r2
|
|
8000ff0: d901 bls.n 8000ff6 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000ff2: 2303 movs r3, #3
|
|
8000ff4: e053 b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8000ff6: 4b2d ldr r3, [pc, #180] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8000ff8: 685b ldr r3, [r3, #4]
|
|
8000ffa: f003 020c and.w r2, r3, #12
|
|
8000ffe: 687b ldr r3, [r7, #4]
|
|
8001000: 685b ldr r3, [r3, #4]
|
|
8001002: 009b lsls r3, r3, #2
|
|
8001004: 429a cmp r2, r3
|
|
8001006: d1eb bne.n 8000fe0 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8001008: 4b27 ldr r3, [pc, #156] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
800100a: 681b ldr r3, [r3, #0]
|
|
800100c: f003 0307 and.w r3, r3, #7
|
|
8001010: 683a ldr r2, [r7, #0]
|
|
8001012: 429a cmp r2, r3
|
|
8001014: d210 bcs.n 8001038 <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8001016: 4b24 ldr r3, [pc, #144] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001018: 681b ldr r3, [r3, #0]
|
|
800101a: f023 0207 bic.w r2, r3, #7
|
|
800101e: 4922 ldr r1, [pc, #136] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001020: 683b ldr r3, [r7, #0]
|
|
8001022: 4313 orrs r3, r2
|
|
8001024: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8001026: 4b20 ldr r3, [pc, #128] @ (80010a8 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001028: 681b ldr r3, [r3, #0]
|
|
800102a: f003 0307 and.w r3, r3, #7
|
|
800102e: 683a ldr r2, [r7, #0]
|
|
8001030: 429a cmp r2, r3
|
|
8001032: d001 beq.n 8001038 <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
return HAL_ERROR;
|
|
8001034: 2301 movs r3, #1
|
|
8001036: e032 b.n 800109e <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001038: 687b ldr r3, [r7, #4]
|
|
800103a: 681b ldr r3, [r3, #0]
|
|
800103c: f003 0304 and.w r3, r3, #4
|
|
8001040: 2b00 cmp r3, #0
|
|
8001042: d008 beq.n 8001056 <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8001044: 4b19 ldr r3, [pc, #100] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001046: 685b ldr r3, [r3, #4]
|
|
8001048: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
800104c: 687b ldr r3, [r7, #4]
|
|
800104e: 68db ldr r3, [r3, #12]
|
|
8001050: 4916 ldr r1, [pc, #88] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001052: 4313 orrs r3, r2
|
|
8001054: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8001056: 687b ldr r3, [r7, #4]
|
|
8001058: 681b ldr r3, [r3, #0]
|
|
800105a: f003 0308 and.w r3, r3, #8
|
|
800105e: 2b00 cmp r3, #0
|
|
8001060: d009 beq.n 8001076 <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
8001062: 4b12 ldr r3, [pc, #72] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001064: 685b ldr r3, [r3, #4]
|
|
8001066: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
800106a: 687b ldr r3, [r7, #4]
|
|
800106c: 691b ldr r3, [r3, #16]
|
|
800106e: 00db lsls r3, r3, #3
|
|
8001070: 490e ldr r1, [pc, #56] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001072: 4313 orrs r3, r2
|
|
8001074: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8001076: f000 f821 bl 80010bc <HAL_RCC_GetSysClockFreq>
|
|
800107a: 4602 mov r2, r0
|
|
800107c: 4b0b ldr r3, [pc, #44] @ (80010ac <HAL_RCC_ClockConfig+0x1c4>)
|
|
800107e: 685b ldr r3, [r3, #4]
|
|
8001080: 091b lsrs r3, r3, #4
|
|
8001082: f003 030f and.w r3, r3, #15
|
|
8001086: 490a ldr r1, [pc, #40] @ (80010b0 <HAL_RCC_ClockConfig+0x1c8>)
|
|
8001088: 5ccb ldrb r3, [r1, r3]
|
|
800108a: fa22 f303 lsr.w r3, r2, r3
|
|
800108e: 4a09 ldr r2, [pc, #36] @ (80010b4 <HAL_RCC_ClockConfig+0x1cc>)
|
|
8001090: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick(uwTickPrio);
|
|
8001092: 4b09 ldr r3, [pc, #36] @ (80010b8 <HAL_RCC_ClockConfig+0x1d0>)
|
|
8001094: 681b ldr r3, [r3, #0]
|
|
8001096: 4618 mov r0, r3
|
|
8001098: f7ff f99a bl 80003d0 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
800109c: 2300 movs r3, #0
|
|
}
|
|
800109e: 4618 mov r0, r3
|
|
80010a0: 3710 adds r7, #16
|
|
80010a2: 46bd mov sp, r7
|
|
80010a4: bd80 pop {r7, pc}
|
|
80010a6: bf00 nop
|
|
80010a8: 40022000 .word 0x40022000
|
|
80010ac: 40021000 .word 0x40021000
|
|
80010b0: 08001210 .word 0x08001210
|
|
80010b4: 20000000 .word 0x20000000
|
|
80010b8: 20000004 .word 0x20000004
|
|
|
|
080010bc <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80010bc: b480 push {r7}
|
|
80010be: b087 sub sp, #28
|
|
80010c0: af00 add r7, sp, #0
|
|
#else
|
|
static const uint8_t aPredivFactorTable[2U] = {1, 2};
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
#endif
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
80010c2: 2300 movs r3, #0
|
|
80010c4: 60fb str r3, [r7, #12]
|
|
80010c6: 2300 movs r3, #0
|
|
80010c8: 60bb str r3, [r7, #8]
|
|
80010ca: 2300 movs r3, #0
|
|
80010cc: 617b str r3, [r7, #20]
|
|
80010ce: 2300 movs r3, #0
|
|
80010d0: 607b str r3, [r7, #4]
|
|
uint32_t sysclockfreq = 0U;
|
|
80010d2: 2300 movs r3, #0
|
|
80010d4: 613b str r3, [r7, #16]
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
tmpreg = RCC->CFGR;
|
|
80010d6: 4b1e ldr r3, [pc, #120] @ (8001150 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
80010d8: 685b ldr r3, [r3, #4]
|
|
80010da: 60fb str r3, [r7, #12]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
80010dc: 68fb ldr r3, [r7, #12]
|
|
80010de: f003 030c and.w r3, r3, #12
|
|
80010e2: 2b04 cmp r3, #4
|
|
80010e4: d002 beq.n 80010ec <HAL_RCC_GetSysClockFreq+0x30>
|
|
80010e6: 2b08 cmp r3, #8
|
|
80010e8: d003 beq.n 80010f2 <HAL_RCC_GetSysClockFreq+0x36>
|
|
80010ea: e027 b.n 800113c <HAL_RCC_GetSysClockFreq+0x80>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
80010ec: 4b19 ldr r3, [pc, #100] @ (8001154 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
80010ee: 613b str r3, [r7, #16]
|
|
break;
|
|
80010f0: e027 b.n 8001142 <HAL_RCC_GetSysClockFreq+0x86>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
80010f2: 68fb ldr r3, [r7, #12]
|
|
80010f4: 0c9b lsrs r3, r3, #18
|
|
80010f6: f003 030f and.w r3, r3, #15
|
|
80010fa: 4a17 ldr r2, [pc, #92] @ (8001158 <HAL_RCC_GetSysClockFreq+0x9c>)
|
|
80010fc: 5cd3 ldrb r3, [r2, r3]
|
|
80010fe: 607b str r3, [r7, #4]
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
8001100: 68fb ldr r3, [r7, #12]
|
|
8001102: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001106: 2b00 cmp r3, #0
|
|
8001108: d010 beq.n 800112c <HAL_RCC_GetSysClockFreq+0x70>
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
800110a: 4b11 ldr r3, [pc, #68] @ (8001150 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
800110c: 685b ldr r3, [r3, #4]
|
|
800110e: 0c5b lsrs r3, r3, #17
|
|
8001110: f003 0301 and.w r3, r3, #1
|
|
8001114: 4a11 ldr r2, [pc, #68] @ (800115c <HAL_RCC_GetSysClockFreq+0xa0>)
|
|
8001116: 5cd3 ldrb r3, [r2, r3]
|
|
8001118: 60bb str r3, [r7, #8]
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
800111a: 687b ldr r3, [r7, #4]
|
|
800111c: 4a0d ldr r2, [pc, #52] @ (8001154 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
800111e: fb03 f202 mul.w r2, r3, r2
|
|
8001122: 68bb ldr r3, [r7, #8]
|
|
8001124: fbb2 f3f3 udiv r3, r2, r3
|
|
8001128: 617b str r3, [r7, #20]
|
|
800112a: e004 b.n 8001136 <HAL_RCC_GetSysClockFreq+0x7a>
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
800112c: 687b ldr r3, [r7, #4]
|
|
800112e: 4a0c ldr r2, [pc, #48] @ (8001160 <HAL_RCC_GetSysClockFreq+0xa4>)
|
|
8001130: fb02 f303 mul.w r3, r2, r3
|
|
8001134: 617b str r3, [r7, #20]
|
|
}
|
|
sysclockfreq = pllclk;
|
|
8001136: 697b ldr r3, [r7, #20]
|
|
8001138: 613b str r3, [r7, #16]
|
|
break;
|
|
800113a: e002 b.n 8001142 <HAL_RCC_GetSysClockFreq+0x86>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
800113c: 4b05 ldr r3, [pc, #20] @ (8001154 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
800113e: 613b str r3, [r7, #16]
|
|
break;
|
|
8001140: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8001142: 693b ldr r3, [r7, #16]
|
|
}
|
|
8001144: 4618 mov r0, r3
|
|
8001146: 371c adds r7, #28
|
|
8001148: 46bd mov sp, r7
|
|
800114a: bc80 pop {r7}
|
|
800114c: 4770 bx lr
|
|
800114e: bf00 nop
|
|
8001150: 40021000 .word 0x40021000
|
|
8001154: 007a1200 .word 0x007a1200
|
|
8001158: 08001220 .word 0x08001220
|
|
800115c: 08001230 .word 0x08001230
|
|
8001160: 003d0900 .word 0x003d0900
|
|
|
|
08001164 <RCC_Delay>:
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
{
|
|
8001164: b480 push {r7}
|
|
8001166: b085 sub sp, #20
|
|
8001168: af00 add r7, sp, #0
|
|
800116a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
800116c: 4b0a ldr r3, [pc, #40] @ (8001198 <RCC_Delay+0x34>)
|
|
800116e: 681b ldr r3, [r3, #0]
|
|
8001170: 4a0a ldr r2, [pc, #40] @ (800119c <RCC_Delay+0x38>)
|
|
8001172: fba2 2303 umull r2, r3, r2, r3
|
|
8001176: 0a5b lsrs r3, r3, #9
|
|
8001178: 687a ldr r2, [r7, #4]
|
|
800117a: fb02 f303 mul.w r3, r2, r3
|
|
800117e: 60fb str r3, [r7, #12]
|
|
do
|
|
{
|
|
__NOP();
|
|
8001180: bf00 nop
|
|
}
|
|
while (Delay --);
|
|
8001182: 68fb ldr r3, [r7, #12]
|
|
8001184: 1e5a subs r2, r3, #1
|
|
8001186: 60fa str r2, [r7, #12]
|
|
8001188: 2b00 cmp r3, #0
|
|
800118a: d1f9 bne.n 8001180 <RCC_Delay+0x1c>
|
|
}
|
|
800118c: bf00 nop
|
|
800118e: bf00 nop
|
|
8001190: 3714 adds r7, #20
|
|
8001192: 46bd mov sp, r7
|
|
8001194: bc80 pop {r7}
|
|
8001196: 4770 bx lr
|
|
8001198: 20000000 .word 0x20000000
|
|
800119c: 10624dd3 .word 0x10624dd3
|
|
|
|
080011a0 <memset>:
|
|
80011a0: 4603 mov r3, r0
|
|
80011a2: 4402 add r2, r0
|
|
80011a4: 4293 cmp r3, r2
|
|
80011a6: d100 bne.n 80011aa <memset+0xa>
|
|
80011a8: 4770 bx lr
|
|
80011aa: f803 1b01 strb.w r1, [r3], #1
|
|
80011ae: e7f9 b.n 80011a4 <memset+0x4>
|
|
|
|
080011b0 <__libc_init_array>:
|
|
80011b0: b570 push {r4, r5, r6, lr}
|
|
80011b2: 2600 movs r6, #0
|
|
80011b4: 4d0c ldr r5, [pc, #48] @ (80011e8 <__libc_init_array+0x38>)
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80011b6: 4c0d ldr r4, [pc, #52] @ (80011ec <__libc_init_array+0x3c>)
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|
80011b8: 1b64 subs r4, r4, r5
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|
80011ba: 10a4 asrs r4, r4, #2
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|
80011bc: 42a6 cmp r6, r4
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|
80011be: d109 bne.n 80011d4 <__libc_init_array+0x24>
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|
80011c0: f000 f81a bl 80011f8 <_init>
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|
80011c4: 2600 movs r6, #0
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|
80011c6: 4d0a ldr r5, [pc, #40] @ (80011f0 <__libc_init_array+0x40>)
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|
80011c8: 4c0a ldr r4, [pc, #40] @ (80011f4 <__libc_init_array+0x44>)
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|
80011ca: 1b64 subs r4, r4, r5
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|
80011cc: 10a4 asrs r4, r4, #2
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|
80011ce: 42a6 cmp r6, r4
|
|
80011d0: d105 bne.n 80011de <__libc_init_array+0x2e>
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|
80011d2: bd70 pop {r4, r5, r6, pc}
|
|
80011d4: f855 3b04 ldr.w r3, [r5], #4
|
|
80011d8: 4798 blx r3
|
|
80011da: 3601 adds r6, #1
|
|
80011dc: e7ee b.n 80011bc <__libc_init_array+0xc>
|
|
80011de: f855 3b04 ldr.w r3, [r5], #4
|
|
80011e2: 4798 blx r3
|
|
80011e4: 3601 adds r6, #1
|
|
80011e6: e7f2 b.n 80011ce <__libc_init_array+0x1e>
|
|
80011e8: 08001234 .word 0x08001234
|
|
80011ec: 08001234 .word 0x08001234
|
|
80011f0: 08001234 .word 0x08001234
|
|
80011f4: 08001238 .word 0x08001238
|
|
|
|
080011f8 <_init>:
|
|
80011f8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80011fa: bf00 nop
|
|
80011fc: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80011fe: bc08 pop {r3}
|
|
8001200: 469e mov lr, r3
|
|
8001202: 4770 bx lr
|
|
|
|
08001204 <_fini>:
|
|
8001204: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8001206: bf00 nop
|
|
8001208: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800120a: bc08 pop {r3}
|
|
800120c: 469e mov lr, r3
|
|
800120e: 4770 bx lr
|